1 /*
    2  * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
    3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    4  *
    5  * This code is free software; you can redistribute it and/or modify it
    6  * under the terms of the GNU General Public License version 2 only, as
    7  * published by the Free Software Foundation.
    8  *
    9  * This code is distributed in the hope that it will be useful, but WITHOUT
   10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   12  * version 2 for more details (a copy is included in the LICENSE file that
   13  * accompanied this code).
   14  *
   15  * You should have received a copy of the GNU General Public License version
   16  * 2 along with this work; if not, write to the Free Software Foundation,
   17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   18  *
   19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   20  * or visit www.oracle.com if you need additional information or have any
   21  * questions.
   22  *
   23  */
   24 
   25 #include "precompiled.hpp"
   26 #include "jvm.h"
   27 #include "asm/assembler.hpp"
   28 #include "asm/assembler.inline.hpp"
   29 #include "compiler/compiler_globals.hpp"
   30 #include "compiler/disassembler.hpp"
   31 #include "ci/ciInlineKlass.hpp"
   32 #include "gc/shared/barrierSet.hpp"
   33 #include "gc/shared/barrierSetAssembler.hpp"
   34 #include "gc/shared/collectedHeap.inline.hpp"
   35 #include "gc/shared/tlab_globals.hpp"
   36 #include "interpreter/bytecodeHistogram.hpp"
   37 #include "interpreter/interpreter.hpp"
   38 #include "memory/resourceArea.hpp"
   39 #include "memory/universe.hpp"
   40 #include "oops/accessDecorators.hpp"
   41 #include "oops/compressedOops.inline.hpp"
   42 #include "oops/klass.inline.hpp"
   43 #include "prims/methodHandles.hpp"
   44 #include "runtime/continuation.hpp"
   45 #include "runtime/flags/flagSetting.hpp"
   46 #include "runtime/interfaceSupport.inline.hpp"
   47 #include "runtime/javaThread.hpp"
   48 #include "runtime/jniHandles.hpp"
   49 #include "runtime/objectMonitor.hpp"
   50 #include "runtime/os.hpp"
   51 #include "runtime/safepoint.hpp"
   52 #include "runtime/safepointMechanism.hpp"
   53 #include "runtime/sharedRuntime.hpp"
   54 #include "runtime/signature_cc.hpp"
   55 #include "runtime/stubRoutines.hpp"
   56 #include "utilities/macros.hpp"
   57 #include "vmreg_x86.inline.hpp"
   58 #include "crc32c.h"
   59 #ifdef COMPILER2
   60 #include "opto/output.hpp"
   61 #endif
   62 
   63 #ifdef PRODUCT
   64 #define BLOCK_COMMENT(str) /* nothing */
   65 #define STOP(error) stop(error)
   66 #else
   67 #define BLOCK_COMMENT(str) block_comment(str)
   68 #define STOP(error) block_comment(error); stop(error)
   69 #endif
   70 
   71 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
   72 
   73 #ifdef ASSERT
   74 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
   75 #endif
   76 
   77 static Assembler::Condition reverse[] = {
   78     Assembler::noOverflow     /* overflow      = 0x0 */ ,
   79     Assembler::overflow       /* noOverflow    = 0x1 */ ,
   80     Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
   81     Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
   82     Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
   83     Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
   84     Assembler::above          /* belowEqual    = 0x6 */ ,
   85     Assembler::belowEqual     /* above         = 0x7 */ ,
   86     Assembler::positive       /* negative      = 0x8 */ ,
   87     Assembler::negative       /* positive      = 0x9 */ ,
   88     Assembler::noParity       /* parity        = 0xa */ ,
   89     Assembler::parity         /* noParity      = 0xb */ ,
   90     Assembler::greaterEqual   /* less          = 0xc */ ,
   91     Assembler::less           /* greaterEqual  = 0xd */ ,
   92     Assembler::greater        /* lessEqual     = 0xe */ ,
   93     Assembler::lessEqual      /* greater       = 0xf, */
   94 
   95 };
   96 
   97 
   98 // Implementation of MacroAssembler
   99 
  100 // First all the versions that have distinct versions depending on 32/64 bit
  101 // Unless the difference is trivial (1 line or so).
  102 
  103 #ifndef _LP64
  104 
  105 // 32bit versions
  106 
  107 Address MacroAssembler::as_Address(AddressLiteral adr) {
  108   return Address(adr.target(), adr.rspec());
  109 }
  110 
  111 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
  112   assert(rscratch == noreg, "");
  113   return Address::make_array(adr);
  114 }
  115 
  116 void MacroAssembler::call_VM_leaf_base(address entry_point,
  117                                        int number_of_arguments) {
  118   call(RuntimeAddress(entry_point));
  119   increment(rsp, number_of_arguments * wordSize);
  120 }
  121 
  122 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
  123   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
  124 }
  125 
  126 
  127 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
  128   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
  129 }
  130 
  131 void MacroAssembler::cmpoop(Address src1, jobject obj) {
  132   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
  133 }
  134 
  135 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) {
  136   assert(rscratch == noreg, "redundant");
  137   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
  138 }
  139 
  140 void MacroAssembler::extend_sign(Register hi, Register lo) {
  141   // According to Intel Doc. AP-526, "Integer Divide", p.18.
  142   if (VM_Version::is_P6() && hi == rdx && lo == rax) {
  143     cdql();
  144   } else {
  145     movl(hi, lo);
  146     sarl(hi, 31);
  147   }
  148 }
  149 
  150 void MacroAssembler::jC2(Register tmp, Label& L) {
  151   // set parity bit if FPU flag C2 is set (via rax)
  152   save_rax(tmp);
  153   fwait(); fnstsw_ax();
  154   sahf();
  155   restore_rax(tmp);
  156   // branch
  157   jcc(Assembler::parity, L);
  158 }
  159 
  160 void MacroAssembler::jnC2(Register tmp, Label& L) {
  161   // set parity bit if FPU flag C2 is set (via rax)
  162   save_rax(tmp);
  163   fwait(); fnstsw_ax();
  164   sahf();
  165   restore_rax(tmp);
  166   // branch
  167   jcc(Assembler::noParity, L);
  168 }
  169 
  170 // 32bit can do a case table jump in one instruction but we no longer allow the base
  171 // to be installed in the Address class
  172 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
  173   assert(rscratch == noreg, "not needed");
  174   jmp(as_Address(entry, noreg));
  175 }
  176 
  177 // Note: y_lo will be destroyed
  178 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
  179   // Long compare for Java (semantics as described in JVM spec.)
  180   Label high, low, done;
  181 
  182   cmpl(x_hi, y_hi);
  183   jcc(Assembler::less, low);
  184   jcc(Assembler::greater, high);
  185   // x_hi is the return register
  186   xorl(x_hi, x_hi);
  187   cmpl(x_lo, y_lo);
  188   jcc(Assembler::below, low);
  189   jcc(Assembler::equal, done);
  190 
  191   bind(high);
  192   xorl(x_hi, x_hi);
  193   increment(x_hi);
  194   jmp(done);
  195 
  196   bind(low);
  197   xorl(x_hi, x_hi);
  198   decrementl(x_hi);
  199 
  200   bind(done);
  201 }
  202 
  203 void MacroAssembler::lea(Register dst, AddressLiteral src) {
  204   mov_literal32(dst, (int32_t)src.target(), src.rspec());
  205 }
  206 
  207 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
  208   assert(rscratch == noreg, "not needed");
  209 
  210   // leal(dst, as_Address(adr));
  211   // see note in movl as to why we must use a move
  212   mov_literal32(dst, (int32_t)adr.target(), adr.rspec());
  213 }
  214 
  215 void MacroAssembler::leave() {
  216   mov(rsp, rbp);
  217   pop(rbp);
  218 }
  219 
  220 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
  221   // Multiplication of two Java long values stored on the stack
  222   // as illustrated below. Result is in rdx:rax.
  223   //
  224   // rsp ---> [  ??  ] \               \
  225   //            ....    | y_rsp_offset  |
  226   //          [ y_lo ] /  (in bytes)    | x_rsp_offset
  227   //          [ y_hi ]                  | (in bytes)
  228   //            ....                    |
  229   //          [ x_lo ]                 /
  230   //          [ x_hi ]
  231   //            ....
  232   //
  233   // Basic idea: lo(result) = lo(x_lo * y_lo)
  234   //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
  235   Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
  236   Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
  237   Label quick;
  238   // load x_hi, y_hi and check if quick
  239   // multiplication is possible
  240   movl(rbx, x_hi);
  241   movl(rcx, y_hi);
  242   movl(rax, rbx);
  243   orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
  244   jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
  245   // do full multiplication
  246   // 1st step
  247   mull(y_lo);                                    // x_hi * y_lo
  248   movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
  249   // 2nd step
  250   movl(rax, x_lo);
  251   mull(rcx);                                     // x_lo * y_hi
  252   addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
  253   // 3rd step
  254   bind(quick);                                   // note: rbx, = 0 if quick multiply!
  255   movl(rax, x_lo);
  256   mull(y_lo);                                    // x_lo * y_lo
  257   addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
  258 }
  259 
  260 void MacroAssembler::lneg(Register hi, Register lo) {
  261   negl(lo);
  262   adcl(hi, 0);
  263   negl(hi);
  264 }
  265 
  266 void MacroAssembler::lshl(Register hi, Register lo) {
  267   // Java shift left long support (semantics as described in JVM spec., p.305)
  268   // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
  269   // shift value is in rcx !
  270   assert(hi != rcx, "must not use rcx");
  271   assert(lo != rcx, "must not use rcx");
  272   const Register s = rcx;                        // shift count
  273   const int      n = BitsPerWord;
  274   Label L;
  275   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
  276   cmpl(s, n);                                    // if (s < n)
  277   jcc(Assembler::less, L);                       // else (s >= n)
  278   movl(hi, lo);                                  // x := x << n
  279   xorl(lo, lo);
  280   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
  281   bind(L);                                       // s (mod n) < n
  282   shldl(hi, lo);                                 // x := x << s
  283   shll(lo);
  284 }
  285 
  286 
  287 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
  288   // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
  289   // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
  290   assert(hi != rcx, "must not use rcx");
  291   assert(lo != rcx, "must not use rcx");
  292   const Register s = rcx;                        // shift count
  293   const int      n = BitsPerWord;
  294   Label L;
  295   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
  296   cmpl(s, n);                                    // if (s < n)
  297   jcc(Assembler::less, L);                       // else (s >= n)
  298   movl(lo, hi);                                  // x := x >> n
  299   if (sign_extension) sarl(hi, 31);
  300   else                xorl(hi, hi);
  301   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
  302   bind(L);                                       // s (mod n) < n
  303   shrdl(lo, hi);                                 // x := x >> s
  304   if (sign_extension) sarl(hi);
  305   else                shrl(hi);
  306 }
  307 
  308 void MacroAssembler::movoop(Register dst, jobject obj) {
  309   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
  310 }
  311 
  312 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
  313   assert(rscratch == noreg, "redundant");
  314   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
  315 }
  316 
  317 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
  318   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
  319 }
  320 
  321 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
  322   assert(rscratch == noreg, "redundant");
  323   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
  324 }
  325 
  326 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
  327   if (src.is_lval()) {
  328     mov_literal32(dst, (intptr_t)src.target(), src.rspec());
  329   } else {
  330     movl(dst, as_Address(src));
  331   }
  332 }
  333 
  334 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
  335   assert(rscratch == noreg, "redundant");
  336   movl(as_Address(dst, noreg), src);
  337 }
  338 
  339 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
  340   movl(dst, as_Address(src, noreg));
  341 }
  342 
  343 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
  344   assert(rscratch == noreg, "redundant");
  345   movl(dst, src);
  346 }
  347 
  348 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
  349   assert(rscratch == noreg, "redundant");
  350   push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
  351 }
  352 
  353 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
  354   assert(rscratch == noreg, "redundant");
  355   push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
  356 }
  357 
  358 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
  359   assert(rscratch == noreg, "redundant");
  360   if (src.is_lval()) {
  361     push_literal32((int32_t)src.target(), src.rspec());
  362   } else {
  363     pushl(as_Address(src));
  364   }
  365 }
  366 
  367 static void pass_arg0(MacroAssembler* masm, Register arg) {
  368   masm->push(arg);
  369 }
  370 
  371 static void pass_arg1(MacroAssembler* masm, Register arg) {
  372   masm->push(arg);
  373 }
  374 
  375 static void pass_arg2(MacroAssembler* masm, Register arg) {
  376   masm->push(arg);
  377 }
  378 
  379 static void pass_arg3(MacroAssembler* masm, Register arg) {
  380   masm->push(arg);
  381 }
  382 
  383 #ifndef PRODUCT
  384 extern "C" void findpc(intptr_t x);
  385 #endif
  386 
  387 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
  388   // In order to get locks to work, we need to fake a in_VM state
  389   JavaThread* thread = JavaThread::current();
  390   JavaThreadState saved_state = thread->thread_state();
  391   thread->set_thread_state(_thread_in_vm);
  392   if (ShowMessageBoxOnError) {
  393     JavaThread* thread = JavaThread::current();
  394     JavaThreadState saved_state = thread->thread_state();
  395     thread->set_thread_state(_thread_in_vm);
  396     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
  397       ttyLocker ttyl;
  398       BytecodeCounter::print();
  399     }
  400     // To see where a verify_oop failed, get $ebx+40/X for this frame.
  401     // This is the value of eip which points to where verify_oop will return.
  402     if (os::message_box(msg, "Execution stopped, print registers?")) {
  403       print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
  404       BREAKPOINT;
  405     }
  406   }
  407   fatal("DEBUG MESSAGE: %s", msg);
  408 }
  409 
  410 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
  411   ttyLocker ttyl;
  412   FlagSetting fs(Debugging, true);
  413   tty->print_cr("eip = 0x%08x", eip);
  414 #ifndef PRODUCT
  415   if ((WizardMode || Verbose) && PrintMiscellaneous) {
  416     tty->cr();
  417     findpc(eip);
  418     tty->cr();
  419   }
  420 #endif
  421 #define PRINT_REG(rax) \
  422   { tty->print("%s = ", #rax); os::print_location(tty, rax); }
  423   PRINT_REG(rax);
  424   PRINT_REG(rbx);
  425   PRINT_REG(rcx);
  426   PRINT_REG(rdx);
  427   PRINT_REG(rdi);
  428   PRINT_REG(rsi);
  429   PRINT_REG(rbp);
  430   PRINT_REG(rsp);
  431 #undef PRINT_REG
  432   // Print some words near top of staack.
  433   int* dump_sp = (int*) rsp;
  434   for (int col1 = 0; col1 < 8; col1++) {
  435     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
  436     os::print_location(tty, *dump_sp++);
  437   }
  438   for (int row = 0; row < 16; row++) {
  439     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
  440     for (int col = 0; col < 8; col++) {
  441       tty->print(" 0x%08x", *dump_sp++);
  442     }
  443     tty->cr();
  444   }
  445   // Print some instructions around pc:
  446   Disassembler::decode((address)eip-64, (address)eip);
  447   tty->print_cr("--------");
  448   Disassembler::decode((address)eip, (address)eip+32);
  449 }
  450 
  451 void MacroAssembler::stop(const char* msg) {
  452   // push address of message
  453   ExternalAddress message((address)msg);
  454   pushptr(message.addr(), noreg);
  455   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
  456   pusha();                                            // push registers
  457   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
  458   hlt();
  459 }
  460 
  461 void MacroAssembler::warn(const char* msg) {
  462   push_CPU_state();
  463 
  464   // push address of message
  465   ExternalAddress message((address)msg);
  466   pushptr(message.addr(), noreg);
  467 
  468   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
  469   addl(rsp, wordSize);       // discard argument
  470   pop_CPU_state();
  471 }
  472 
  473 void MacroAssembler::print_state() {
  474   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
  475   pusha();                                            // push registers
  476 
  477   push_CPU_state();
  478   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
  479   pop_CPU_state();
  480 
  481   popa();
  482   addl(rsp, wordSize);
  483 }
  484 
  485 #else // _LP64
  486 
  487 // 64 bit versions
  488 
  489 Address MacroAssembler::as_Address(AddressLiteral adr) {
  490   // amd64 always does this as a pc-rel
  491   // we can be absolute or disp based on the instruction type
  492   // jmp/call are displacements others are absolute
  493   assert(!adr.is_lval(), "must be rval");
  494   assert(reachable(adr), "must be");
  495   return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
  496 
  497 }
  498 
  499 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
  500   AddressLiteral base = adr.base();
  501   lea(rscratch, base);
  502   Address index = adr.index();
  503   assert(index._disp == 0, "must not have disp"); // maybe it can?
  504   Address array(rscratch, index._index, index._scale, index._disp);
  505   return array;
  506 }
  507 
  508 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
  509   Label L, E;
  510 
  511 #ifdef _WIN64
  512   // Windows always allocates space for it's register args
  513   assert(num_args <= 4, "only register arguments supported");
  514   subq(rsp,  frame::arg_reg_save_area_bytes);
  515 #endif
  516 
  517   // Align stack if necessary
  518   testl(rsp, 15);
  519   jcc(Assembler::zero, L);
  520 
  521   subq(rsp, 8);
  522   call(RuntimeAddress(entry_point));
  523   addq(rsp, 8);
  524   jmp(E);
  525 
  526   bind(L);
  527   call(RuntimeAddress(entry_point));
  528 
  529   bind(E);
  530 
  531 #ifdef _WIN64
  532   // restore stack pointer
  533   addq(rsp, frame::arg_reg_save_area_bytes);
  534 #endif
  535 
  536 }
  537 
  538 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
  539   assert(!src2.is_lval(), "should use cmpptr");
  540   assert(rscratch != noreg || always_reachable(src2), "missing");
  541 
  542   if (reachable(src2)) {
  543     cmpq(src1, as_Address(src2));
  544   } else {
  545     lea(rscratch, src2);
  546     Assembler::cmpq(src1, Address(rscratch, 0));
  547   }
  548 }
  549 
  550 int MacroAssembler::corrected_idivq(Register reg) {
  551   // Full implementation of Java ldiv and lrem; checks for special
  552   // case as described in JVM spec., p.243 & p.271.  The function
  553   // returns the (pc) offset of the idivl instruction - may be needed
  554   // for implicit exceptions.
  555   //
  556   //         normal case                           special case
  557   //
  558   // input : rax: dividend                         min_long
  559   //         reg: divisor   (may not be eax/edx)   -1
  560   //
  561   // output: rax: quotient  (= rax idiv reg)       min_long
  562   //         rdx: remainder (= rax irem reg)       0
  563   assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
  564   static const int64_t min_long = 0x8000000000000000;
  565   Label normal_case, special_case;
  566 
  567   // check for special case
  568   cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
  569   jcc(Assembler::notEqual, normal_case);
  570   xorl(rdx, rdx); // prepare rdx for possible special case (where
  571                   // remainder = 0)
  572   cmpq(reg, -1);
  573   jcc(Assembler::equal, special_case);
  574 
  575   // handle normal case
  576   bind(normal_case);
  577   cdqq();
  578   int idivq_offset = offset();
  579   idivq(reg);
  580 
  581   // normal and special case exit
  582   bind(special_case);
  583 
  584   return idivq_offset;
  585 }
  586 
  587 void MacroAssembler::decrementq(Register reg, int value) {
  588   if (value == min_jint) { subq(reg, value); return; }
  589   if (value <  0) { incrementq(reg, -value); return; }
  590   if (value == 0) {                        ; return; }
  591   if (value == 1 && UseIncDec) { decq(reg) ; return; }
  592   /* else */      { subq(reg, value)       ; return; }
  593 }
  594 
  595 void MacroAssembler::decrementq(Address dst, int value) {
  596   if (value == min_jint) { subq(dst, value); return; }
  597   if (value <  0) { incrementq(dst, -value); return; }
  598   if (value == 0) {                        ; return; }
  599   if (value == 1 && UseIncDec) { decq(dst) ; return; }
  600   /* else */      { subq(dst, value)       ; return; }
  601 }
  602 
  603 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
  604   assert(rscratch != noreg || always_reachable(dst), "missing");
  605 
  606   if (reachable(dst)) {
  607     incrementq(as_Address(dst));
  608   } else {
  609     lea(rscratch, dst);
  610     incrementq(Address(rscratch, 0));
  611   }
  612 }
  613 
  614 void MacroAssembler::incrementq(Register reg, int value) {
  615   if (value == min_jint) { addq(reg, value); return; }
  616   if (value <  0) { decrementq(reg, -value); return; }
  617   if (value == 0) {                        ; return; }
  618   if (value == 1 && UseIncDec) { incq(reg) ; return; }
  619   /* else */      { addq(reg, value)       ; return; }
  620 }
  621 
  622 void MacroAssembler::incrementq(Address dst, int value) {
  623   if (value == min_jint) { addq(dst, value); return; }
  624   if (value <  0) { decrementq(dst, -value); return; }
  625   if (value == 0) {                        ; return; }
  626   if (value == 1 && UseIncDec) { incq(dst) ; return; }
  627   /* else */      { addq(dst, value)       ; return; }
  628 }
  629 
  630 // 32bit can do a case table jump in one instruction but we no longer allow the base
  631 // to be installed in the Address class
  632 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
  633   lea(rscratch, entry.base());
  634   Address dispatch = entry.index();
  635   assert(dispatch._base == noreg, "must be");
  636   dispatch._base = rscratch;
  637   jmp(dispatch);
  638 }
  639 
  640 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
  641   ShouldNotReachHere(); // 64bit doesn't use two regs
  642   cmpq(x_lo, y_lo);
  643 }
  644 
  645 void MacroAssembler::lea(Register dst, AddressLiteral src) {
  646   mov_literal64(dst, (intptr_t)src.target(), src.rspec());
  647 }
  648 
  649 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
  650   lea(rscratch, adr);
  651   movptr(dst, rscratch);
  652 }
  653 
  654 void MacroAssembler::leave() {
  655   // %%% is this really better? Why not on 32bit too?
  656   emit_int8((unsigned char)0xC9); // LEAVE
  657 }
  658 
  659 void MacroAssembler::lneg(Register hi, Register lo) {
  660   ShouldNotReachHere(); // 64bit doesn't use two regs
  661   negq(lo);
  662 }
  663 
  664 void MacroAssembler::movoop(Register dst, jobject obj) {
  665   mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
  666 }
  667 
  668 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
  669   mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
  670   movq(dst, rscratch);
  671 }
  672 
  673 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
  674   mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
  675 }
  676 
  677 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
  678   mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
  679   movq(dst, rscratch);
  680 }
  681 
  682 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
  683   if (src.is_lval()) {
  684     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
  685   } else {
  686     if (reachable(src)) {
  687       movq(dst, as_Address(src));
  688     } else {
  689       lea(dst, src);
  690       movq(dst, Address(dst, 0));
  691     }
  692   }
  693 }
  694 
  695 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
  696   movq(as_Address(dst, rscratch), src);
  697 }
  698 
  699 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
  700   movq(dst, as_Address(src, dst /*rscratch*/));
  701 }
  702 
  703 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
  704 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
  705   if (is_simm32(src)) {
  706     movptr(dst, checked_cast<int32_t>(src));
  707   } else {
  708     mov64(rscratch, src);
  709     movq(dst, rscratch);
  710   }
  711 }
  712 
  713 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
  714   movoop(rscratch, obj);
  715   push(rscratch);
  716 }
  717 
  718 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
  719   mov_metadata(rscratch, obj);
  720   push(rscratch);
  721 }
  722 
  723 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
  724   lea(rscratch, src);
  725   if (src.is_lval()) {
  726     push(rscratch);
  727   } else {
  728     pushq(Address(rscratch, 0));
  729   }
  730 }
  731 
  732 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
  733   reset_last_Java_frame(r15_thread, clear_fp);
  734 }
  735 
  736 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
  737                                          Register last_java_fp,
  738                                          address  last_java_pc,
  739                                          Register rscratch) {
  740   set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch);
  741 }
  742 
  743 static void pass_arg0(MacroAssembler* masm, Register arg) {
  744   if (c_rarg0 != arg ) {
  745     masm->mov(c_rarg0, arg);
  746   }
  747 }
  748 
  749 static void pass_arg1(MacroAssembler* masm, Register arg) {
  750   if (c_rarg1 != arg ) {
  751     masm->mov(c_rarg1, arg);
  752   }
  753 }
  754 
  755 static void pass_arg2(MacroAssembler* masm, Register arg) {
  756   if (c_rarg2 != arg ) {
  757     masm->mov(c_rarg2, arg);
  758   }
  759 }
  760 
  761 static void pass_arg3(MacroAssembler* masm, Register arg) {
  762   if (c_rarg3 != arg ) {
  763     masm->mov(c_rarg3, arg);
  764   }
  765 }
  766 
  767 void MacroAssembler::stop(const char* msg) {
  768   if (ShowMessageBoxOnError) {
  769     address rip = pc();
  770     pusha(); // get regs on stack
  771     lea(c_rarg1, InternalAddress(rip));
  772     movq(c_rarg2, rsp); // pass pointer to regs array
  773   }
  774   lea(c_rarg0, ExternalAddress((address) msg));
  775   andq(rsp, -16); // align stack as required by ABI
  776   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
  777   hlt();
  778 }
  779 
  780 void MacroAssembler::warn(const char* msg) {
  781   push(rbp);
  782   movq(rbp, rsp);
  783   andq(rsp, -16);     // align stack as required by push_CPU_state and call
  784   push_CPU_state();   // keeps alignment at 16 bytes
  785 
  786   lea(c_rarg0, ExternalAddress((address) msg));
  787   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
  788 
  789   pop_CPU_state();
  790   mov(rsp, rbp);
  791   pop(rbp);
  792 }
  793 
  794 void MacroAssembler::print_state() {
  795   address rip = pc();
  796   pusha();            // get regs on stack
  797   push(rbp);
  798   movq(rbp, rsp);
  799   andq(rsp, -16);     // align stack as required by push_CPU_state and call
  800   push_CPU_state();   // keeps alignment at 16 bytes
  801 
  802   lea(c_rarg0, InternalAddress(rip));
  803   lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
  804   call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
  805 
  806   pop_CPU_state();
  807   mov(rsp, rbp);
  808   pop(rbp);
  809   popa();
  810 }
  811 
  812 #ifndef PRODUCT
  813 extern "C" void findpc(intptr_t x);
  814 #endif
  815 
  816 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
  817   // In order to get locks to work, we need to fake a in_VM state
  818   if (ShowMessageBoxOnError) {
  819     JavaThread* thread = JavaThread::current();
  820     JavaThreadState saved_state = thread->thread_state();
  821     thread->set_thread_state(_thread_in_vm);
  822 #ifndef PRODUCT
  823     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
  824       ttyLocker ttyl;
  825       BytecodeCounter::print();
  826     }
  827 #endif
  828     // To see where a verify_oop failed, get $ebx+40/X for this frame.
  829     // XXX correct this offset for amd64
  830     // This is the value of eip which points to where verify_oop will return.
  831     if (os::message_box(msg, "Execution stopped, print registers?")) {
  832       print_state64(pc, regs);
  833       BREAKPOINT;
  834     }
  835   }
  836   fatal("DEBUG MESSAGE: %s", msg);
  837 }
  838 
  839 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
  840   ttyLocker ttyl;
  841   FlagSetting fs(Debugging, true);
  842   tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
  843 #ifndef PRODUCT
  844   tty->cr();
  845   findpc(pc);
  846   tty->cr();
  847 #endif
  848 #define PRINT_REG(rax, value) \
  849   { tty->print("%s = ", #rax); os::print_location(tty, value); }
  850   PRINT_REG(rax, regs[15]);
  851   PRINT_REG(rbx, regs[12]);
  852   PRINT_REG(rcx, regs[14]);
  853   PRINT_REG(rdx, regs[13]);
  854   PRINT_REG(rdi, regs[8]);
  855   PRINT_REG(rsi, regs[9]);
  856   PRINT_REG(rbp, regs[10]);
  857   // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
  858   PRINT_REG(rsp, (intptr_t)(&regs[16]));
  859   PRINT_REG(r8 , regs[7]);
  860   PRINT_REG(r9 , regs[6]);
  861   PRINT_REG(r10, regs[5]);
  862   PRINT_REG(r11, regs[4]);
  863   PRINT_REG(r12, regs[3]);
  864   PRINT_REG(r13, regs[2]);
  865   PRINT_REG(r14, regs[1]);
  866   PRINT_REG(r15, regs[0]);
  867 #undef PRINT_REG
  868   // Print some words near the top of the stack.
  869   int64_t* rsp = &regs[16];
  870   int64_t* dump_sp = rsp;
  871   for (int col1 = 0; col1 < 8; col1++) {
  872     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
  873     os::print_location(tty, *dump_sp++);
  874   }
  875   for (int row = 0; row < 25; row++) {
  876     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
  877     for (int col = 0; col < 4; col++) {
  878       tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
  879     }
  880     tty->cr();
  881   }
  882   // Print some instructions around pc:
  883   Disassembler::decode((address)pc-64, (address)pc);
  884   tty->print_cr("--------");
  885   Disassembler::decode((address)pc, (address)pc+32);
  886 }
  887 
  888 // The java_calling_convention describes stack locations as ideal slots on
  889 // a frame with no abi restrictions. Since we must observe abi restrictions
  890 // (like the placement of the register window) the slots must be biased by
  891 // the following value.
  892 static int reg2offset_in(VMReg r) {
  893   // Account for saved rbp and return address
  894   // This should really be in_preserve_stack_slots
  895   return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
  896 }
  897 
  898 static int reg2offset_out(VMReg r) {
  899   return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
  900 }
  901 
  902 // A long move
  903 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
  904 
  905   // The calling conventions assures us that each VMregpair is either
  906   // all really one physical register or adjacent stack slots.
  907 
  908   if (src.is_single_phys_reg() ) {
  909     if (dst.is_single_phys_reg()) {
  910       if (dst.first() != src.first()) {
  911         mov(dst.first()->as_Register(), src.first()->as_Register());
  912       }
  913     } else {
  914       assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
  915              src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
  916       movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
  917     }
  918   } else if (dst.is_single_phys_reg()) {
  919     assert(src.is_single_reg(),  "not a stack pair");
  920     movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
  921   } else {
  922     assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
  923     movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
  924     movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
  925   }
  926 }
  927 
  928 // A double move
  929 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
  930 
  931   // The calling conventions assures us that each VMregpair is either
  932   // all really one physical register or adjacent stack slots.
  933 
  934   if (src.is_single_phys_reg() ) {
  935     if (dst.is_single_phys_reg()) {
  936       // In theory these overlap but the ordering is such that this is likely a nop
  937       if ( src.first() != dst.first()) {
  938         movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
  939       }
  940     } else {
  941       assert(dst.is_single_reg(), "not a stack pair");
  942       movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
  943     }
  944   } else if (dst.is_single_phys_reg()) {
  945     assert(src.is_single_reg(),  "not a stack pair");
  946     movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
  947   } else {
  948     assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
  949     movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
  950     movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
  951   }
  952 }
  953 
  954 
  955 // A float arg may have to do float reg int reg conversion
  956 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
  957   assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
  958 
  959   // The calling conventions assures us that each VMregpair is either
  960   // all really one physical register or adjacent stack slots.
  961 
  962   if (src.first()->is_stack()) {
  963     if (dst.first()->is_stack()) {
  964       movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
  965       movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
  966     } else {
  967       // stack to reg
  968       assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
  969       movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
  970     }
  971   } else if (dst.first()->is_stack()) {
  972     // reg to stack
  973     assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
  974     movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
  975   } else {
  976     // reg to reg
  977     // In theory these overlap but the ordering is such that this is likely a nop
  978     if ( src.first() != dst.first()) {
  979       movdbl(dst.first()->as_XMMRegister(),  src.first()->as_XMMRegister());
  980     }
  981   }
  982 }
  983 
  984 // On 64 bit we will store integer like items to the stack as
  985 // 64 bits items (x86_32/64 abi) even though java would only store
  986 // 32bits for a parameter. On 32bit it will simply be 32 bits
  987 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
  988 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
  989   if (src.first()->is_stack()) {
  990     if (dst.first()->is_stack()) {
  991       // stack to stack
  992       movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
  993       movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
  994     } else {
  995       // stack to reg
  996       movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
  997     }
  998   } else if (dst.first()->is_stack()) {
  999     // reg to stack
 1000     // Do we really have to sign extend???
 1001     // __ movslq(src.first()->as_Register(), src.first()->as_Register());
 1002     movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
 1003   } else {
 1004     // Do we really have to sign extend???
 1005     // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
 1006     if (dst.first() != src.first()) {
 1007       movq(dst.first()->as_Register(), src.first()->as_Register());
 1008     }
 1009   }
 1010 }
 1011 
 1012 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
 1013   if (src.first()->is_stack()) {
 1014     if (dst.first()->is_stack()) {
 1015       // stack to stack
 1016       movq(rax, Address(rbp, reg2offset_in(src.first())));
 1017       movq(Address(rsp, reg2offset_out(dst.first())), rax);
 1018     } else {
 1019       // stack to reg
 1020       movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
 1021     }
 1022   } else if (dst.first()->is_stack()) {
 1023     // reg to stack
 1024     movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
 1025   } else {
 1026     if (dst.first() != src.first()) {
 1027       movq(dst.first()->as_Register(), src.first()->as_Register());
 1028     }
 1029   }
 1030 }
 1031 
 1032 // An oop arg. Must pass a handle not the oop itself
 1033 void MacroAssembler::object_move(OopMap* map,
 1034                         int oop_handle_offset,
 1035                         int framesize_in_slots,
 1036                         VMRegPair src,
 1037                         VMRegPair dst,
 1038                         bool is_receiver,
 1039                         int* receiver_offset) {
 1040 
 1041   // must pass a handle. First figure out the location we use as a handle
 1042 
 1043   Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
 1044 
 1045   // See if oop is NULL if it is we need no handle
 1046 
 1047   if (src.first()->is_stack()) {
 1048 
 1049     // Oop is already on the stack as an argument
 1050     int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
 1051     map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
 1052     if (is_receiver) {
 1053       *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
 1054     }
 1055 
 1056     cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
 1057     lea(rHandle, Address(rbp, reg2offset_in(src.first())));
 1058     // conditionally move a NULL
 1059     cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
 1060   } else {
 1061 
 1062     // Oop is in a register we must store it to the space we reserve
 1063     // on the stack for oop_handles and pass a handle if oop is non-NULL
 1064 
 1065     const Register rOop = src.first()->as_Register();
 1066     int oop_slot;
 1067     if (rOop == j_rarg0)
 1068       oop_slot = 0;
 1069     else if (rOop == j_rarg1)
 1070       oop_slot = 1;
 1071     else if (rOop == j_rarg2)
 1072       oop_slot = 2;
 1073     else if (rOop == j_rarg3)
 1074       oop_slot = 3;
 1075     else if (rOop == j_rarg4)
 1076       oop_slot = 4;
 1077     else {
 1078       assert(rOop == j_rarg5, "wrong register");
 1079       oop_slot = 5;
 1080     }
 1081 
 1082     oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
 1083     int offset = oop_slot*VMRegImpl::stack_slot_size;
 1084 
 1085     map->set_oop(VMRegImpl::stack2reg(oop_slot));
 1086     // Store oop in handle area, may be NULL
 1087     movptr(Address(rsp, offset), rOop);
 1088     if (is_receiver) {
 1089       *receiver_offset = offset;
 1090     }
 1091 
 1092     cmpptr(rOop, NULL_WORD);
 1093     lea(rHandle, Address(rsp, offset));
 1094     // conditionally move a NULL from the handle area where it was just stored
 1095     cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
 1096   }
 1097 
 1098   // If arg is on the stack then place it otherwise it is already in correct reg.
 1099   if (dst.first()->is_stack()) {
 1100     movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
 1101   }
 1102 }
 1103 
 1104 #endif // _LP64
 1105 
 1106 // Now versions that are common to 32/64 bit
 1107 
 1108 void MacroAssembler::addptr(Register dst, int32_t imm32) {
 1109   LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
 1110 }
 1111 
 1112 void MacroAssembler::addptr(Register dst, Register src) {
 1113   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
 1114 }
 1115 
 1116 void MacroAssembler::addptr(Address dst, Register src) {
 1117   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
 1118 }
 1119 
 1120 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
 1121   assert(rscratch != noreg || always_reachable(src), "missing");
 1122 
 1123   if (reachable(src)) {
 1124     Assembler::addsd(dst, as_Address(src));
 1125   } else {
 1126     lea(rscratch, src);
 1127     Assembler::addsd(dst, Address(rscratch, 0));
 1128   }
 1129 }
 1130 
 1131 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
 1132   assert(rscratch != noreg || always_reachable(src), "missing");
 1133 
 1134   if (reachable(src)) {
 1135     addss(dst, as_Address(src));
 1136   } else {
 1137     lea(rscratch, src);
 1138     addss(dst, Address(rscratch, 0));
 1139   }
 1140 }
 1141 
 1142 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
 1143   assert(rscratch != noreg || always_reachable(src), "missing");
 1144 
 1145   if (reachable(src)) {
 1146     Assembler::addpd(dst, as_Address(src));
 1147   } else {
 1148     lea(rscratch, src);
 1149     Assembler::addpd(dst, Address(rscratch, 0));
 1150   }
 1151 }
 1152 
 1153 // See 8273459.  Function for ensuring 64-byte alignment, intended for stubs only.
 1154 // Stub code is generated once and never copied.
 1155 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
 1156 void MacroAssembler::align64() {
 1157   align(64, (unsigned long long) pc());
 1158 }
 1159 
 1160 void MacroAssembler::align32() {
 1161   align(32, (unsigned long long) pc());
 1162 }
 1163 
 1164 void MacroAssembler::align(int modulus) {
 1165   // 8273459: Ensure alignment is possible with current segment alignment
 1166   assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
 1167   align(modulus, offset());
 1168 }
 1169 
 1170 void MacroAssembler::align(int modulus, int target) {
 1171   if (target % modulus != 0) {
 1172     nop(modulus - (target % modulus));
 1173   }
 1174 }
 1175 
 1176 void MacroAssembler::push_f(XMMRegister r) {
 1177   subptr(rsp, wordSize);
 1178   movflt(Address(rsp, 0), r);
 1179 }
 1180 
 1181 void MacroAssembler::pop_f(XMMRegister r) {
 1182   movflt(r, Address(rsp, 0));
 1183   addptr(rsp, wordSize);
 1184 }
 1185 
 1186 void MacroAssembler::push_d(XMMRegister r) {
 1187   subptr(rsp, 2 * wordSize);
 1188   movdbl(Address(rsp, 0), r);
 1189 }
 1190 
 1191 void MacroAssembler::pop_d(XMMRegister r) {
 1192   movdbl(r, Address(rsp, 0));
 1193   addptr(rsp, 2 * Interpreter::stackElementSize);
 1194 }
 1195 
 1196 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
 1197   // Used in sign-masking with aligned address.
 1198   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
 1199   assert(rscratch != noreg || always_reachable(src), "missing");
 1200 
 1201   if (reachable(src)) {
 1202     Assembler::andpd(dst, as_Address(src));
 1203   } else {
 1204     lea(rscratch, src);
 1205     Assembler::andpd(dst, Address(rscratch, 0));
 1206   }
 1207 }
 1208 
 1209 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
 1210   // Used in sign-masking with aligned address.
 1211   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
 1212   assert(rscratch != noreg || always_reachable(src), "missing");
 1213 
 1214   if (reachable(src)) {
 1215     Assembler::andps(dst, as_Address(src));
 1216   } else {
 1217     lea(rscratch, src);
 1218     Assembler::andps(dst, Address(rscratch, 0));
 1219   }
 1220 }
 1221 
 1222 void MacroAssembler::andptr(Register dst, int32_t imm32) {
 1223   LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
 1224 }
 1225 
 1226 void MacroAssembler::atomic_incl(Address counter_addr) {
 1227   lock();
 1228   incrementl(counter_addr);
 1229 }
 1230 
 1231 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
 1232   assert(rscratch != noreg || always_reachable(counter_addr), "missing");
 1233 
 1234   if (reachable(counter_addr)) {
 1235     atomic_incl(as_Address(counter_addr));
 1236   } else {
 1237     lea(rscratch, counter_addr);
 1238     atomic_incl(Address(rscratch, 0));
 1239   }
 1240 }
 1241 
 1242 #ifdef _LP64
 1243 void MacroAssembler::atomic_incq(Address counter_addr) {
 1244   lock();
 1245   incrementq(counter_addr);
 1246 }
 1247 
 1248 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
 1249   assert(rscratch != noreg || always_reachable(counter_addr), "missing");
 1250 
 1251   if (reachable(counter_addr)) {
 1252     atomic_incq(as_Address(counter_addr));
 1253   } else {
 1254     lea(rscratch, counter_addr);
 1255     atomic_incq(Address(rscratch, 0));
 1256   }
 1257 }
 1258 #endif
 1259 
 1260 // Writes to stack successive pages until offset reached to check for
 1261 // stack overflow + shadow pages.  This clobbers tmp.
 1262 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
 1263   movptr(tmp, rsp);
 1264   // Bang stack for total size given plus shadow page size.
 1265   // Bang one page at a time because large size can bang beyond yellow and
 1266   // red zones.
 1267   Label loop;
 1268   bind(loop);
 1269   movl(Address(tmp, (-os::vm_page_size())), size );
 1270   subptr(tmp, os::vm_page_size());
 1271   subl(size, os::vm_page_size());
 1272   jcc(Assembler::greater, loop);
 1273 
 1274   // Bang down shadow pages too.
 1275   // At this point, (tmp-0) is the last address touched, so don't
 1276   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
 1277   // was post-decremented.)  Skip this address by starting at i=1, and
 1278   // touch a few more pages below.  N.B.  It is important to touch all
 1279   // the way down including all pages in the shadow zone.
 1280   for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / os::vm_page_size()); i++) {
 1281     // this could be any sized move but this is can be a debugging crumb
 1282     // so the bigger the better.
 1283     movptr(Address(tmp, (-i*os::vm_page_size())), size );
 1284   }
 1285 }
 1286 
 1287 void MacroAssembler::reserved_stack_check() {
 1288   // testing if reserved zone needs to be enabled
 1289   Label no_reserved_zone_enabling;
 1290   Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
 1291   NOT_LP64(get_thread(rsi);)
 1292 
 1293   cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
 1294   jcc(Assembler::below, no_reserved_zone_enabling);
 1295 
 1296   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
 1297   jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
 1298   should_not_reach_here();
 1299 
 1300   bind(no_reserved_zone_enabling);
 1301 }
 1302 
 1303 void MacroAssembler::c2bool(Register x) {
 1304   // implements x == 0 ? 0 : 1
 1305   // note: must only look at least-significant byte of x
 1306   //       since C-style booleans are stored in one byte
 1307   //       only! (was bug)
 1308   andl(x, 0xFF);
 1309   setb(Assembler::notZero, x);
 1310 }
 1311 
 1312 // Wouldn't need if AddressLiteral version had new name
 1313 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
 1314   Assembler::call(L, rtype);
 1315 }
 1316 
 1317 void MacroAssembler::call(Register entry) {
 1318   Assembler::call(entry);
 1319 }
 1320 
 1321 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
 1322   assert(rscratch != noreg || always_reachable(entry), "missing");
 1323 
 1324   if (reachable(entry)) {
 1325     Assembler::call_literal(entry.target(), entry.rspec());
 1326   } else {
 1327     lea(rscratch, entry);
 1328     Assembler::call(rscratch);
 1329   }
 1330 }
 1331 
 1332 void MacroAssembler::ic_call(address entry, jint method_index) {
 1333   RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
 1334   movptr(rax, (intptr_t)Universe::non_oop_word());
 1335   call(AddressLiteral(entry, rh));
 1336 }
 1337 
 1338 void MacroAssembler::emit_static_call_stub() {
 1339   // Static stub relocation also tags the Method* in the code-stream.
 1340   mov_metadata(rbx, (Metadata*) NULL);  // Method is zapped till fixup time.
 1341   // This is recognized as unresolved by relocs/nativeinst/ic code.
 1342   jump(RuntimeAddress(pc()));
 1343 }
 1344 
 1345 // Implementation of call_VM versions
 1346 
 1347 void MacroAssembler::call_VM(Register oop_result,
 1348                              address entry_point,
 1349                              bool check_exceptions) {
 1350   Label C, E;
 1351   call(C, relocInfo::none);
 1352   jmp(E);
 1353 
 1354   bind(C);
 1355   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
 1356   ret(0);
 1357 
 1358   bind(E);
 1359 }
 1360 
 1361 void MacroAssembler::call_VM(Register oop_result,
 1362                              address entry_point,
 1363                              Register arg_1,
 1364                              bool check_exceptions) {
 1365   Label C, E;
 1366   call(C, relocInfo::none);
 1367   jmp(E);
 1368 
 1369   bind(C);
 1370   pass_arg1(this, arg_1);
 1371   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
 1372   ret(0);
 1373 
 1374   bind(E);
 1375 }
 1376 
 1377 void MacroAssembler::call_VM(Register oop_result,
 1378                              address entry_point,
 1379                              Register arg_1,
 1380                              Register arg_2,
 1381                              bool check_exceptions) {
 1382   Label C, E;
 1383   call(C, relocInfo::none);
 1384   jmp(E);
 1385 
 1386   bind(C);
 1387 
 1388   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
 1389 
 1390   pass_arg2(this, arg_2);
 1391   pass_arg1(this, arg_1);
 1392   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
 1393   ret(0);
 1394 
 1395   bind(E);
 1396 }
 1397 
 1398 void MacroAssembler::call_VM(Register oop_result,
 1399                              address entry_point,
 1400                              Register arg_1,
 1401                              Register arg_2,
 1402                              Register arg_3,
 1403                              bool check_exceptions) {
 1404   Label C, E;
 1405   call(C, relocInfo::none);
 1406   jmp(E);
 1407 
 1408   bind(C);
 1409 
 1410   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
 1411   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
 1412   pass_arg3(this, arg_3);
 1413 
 1414   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
 1415   pass_arg2(this, arg_2);
 1416 
 1417   pass_arg1(this, arg_1);
 1418   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
 1419   ret(0);
 1420 
 1421   bind(E);
 1422 }
 1423 
 1424 void MacroAssembler::call_VM(Register oop_result,
 1425                              Register last_java_sp,
 1426                              address entry_point,
 1427                              int number_of_arguments,
 1428                              bool check_exceptions) {
 1429   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
 1430   call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
 1431 }
 1432 
 1433 void MacroAssembler::call_VM(Register oop_result,
 1434                              Register last_java_sp,
 1435                              address entry_point,
 1436                              Register arg_1,
 1437                              bool check_exceptions) {
 1438   pass_arg1(this, arg_1);
 1439   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
 1440 }
 1441 
 1442 void MacroAssembler::call_VM(Register oop_result,
 1443                              Register last_java_sp,
 1444                              address entry_point,
 1445                              Register arg_1,
 1446                              Register arg_2,
 1447                              bool check_exceptions) {
 1448 
 1449   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
 1450   pass_arg2(this, arg_2);
 1451   pass_arg1(this, arg_1);
 1452   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
 1453 }
 1454 
 1455 void MacroAssembler::call_VM(Register oop_result,
 1456                              Register last_java_sp,
 1457                              address entry_point,
 1458                              Register arg_1,
 1459                              Register arg_2,
 1460                              Register arg_3,
 1461                              bool check_exceptions) {
 1462   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
 1463   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
 1464   pass_arg3(this, arg_3);
 1465   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
 1466   pass_arg2(this, arg_2);
 1467   pass_arg1(this, arg_1);
 1468   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
 1469 }
 1470 
 1471 void MacroAssembler::super_call_VM(Register oop_result,
 1472                                    Register last_java_sp,
 1473                                    address entry_point,
 1474                                    int number_of_arguments,
 1475                                    bool check_exceptions) {
 1476   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
 1477   MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
 1478 }
 1479 
 1480 void MacroAssembler::super_call_VM(Register oop_result,
 1481                                    Register last_java_sp,
 1482                                    address entry_point,
 1483                                    Register arg_1,
 1484                                    bool check_exceptions) {
 1485   pass_arg1(this, arg_1);
 1486   super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
 1487 }
 1488 
 1489 void MacroAssembler::super_call_VM(Register oop_result,
 1490                                    Register last_java_sp,
 1491                                    address entry_point,
 1492                                    Register arg_1,
 1493                                    Register arg_2,
 1494                                    bool check_exceptions) {
 1495 
 1496   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
 1497   pass_arg2(this, arg_2);
 1498   pass_arg1(this, arg_1);
 1499   super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
 1500 }
 1501 
 1502 void MacroAssembler::super_call_VM(Register oop_result,
 1503                                    Register last_java_sp,
 1504                                    address entry_point,
 1505                                    Register arg_1,
 1506                                    Register arg_2,
 1507                                    Register arg_3,
 1508                                    bool check_exceptions) {
 1509   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
 1510   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
 1511   pass_arg3(this, arg_3);
 1512   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
 1513   pass_arg2(this, arg_2);
 1514   pass_arg1(this, arg_1);
 1515   super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
 1516 }
 1517 
 1518 void MacroAssembler::call_VM_base(Register oop_result,
 1519                                   Register java_thread,
 1520                                   Register last_java_sp,
 1521                                   address  entry_point,
 1522                                   int      number_of_arguments,
 1523                                   bool     check_exceptions) {
 1524   // determine java_thread register
 1525   if (!java_thread->is_valid()) {
 1526 #ifdef _LP64
 1527     java_thread = r15_thread;
 1528 #else
 1529     java_thread = rdi;
 1530     get_thread(java_thread);
 1531 #endif // LP64
 1532   }
 1533   // determine last_java_sp register
 1534   if (!last_java_sp->is_valid()) {
 1535     last_java_sp = rsp;
 1536   }
 1537   // debugging support
 1538   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
 1539   LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
 1540 #ifdef ASSERT
 1541   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
 1542   // r12 is the heapbase.
 1543   LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
 1544 #endif // ASSERT
 1545 
 1546   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
 1547   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
 1548 
 1549   // push java thread (becomes first argument of C function)
 1550 
 1551   NOT_LP64(push(java_thread); number_of_arguments++);
 1552   LP64_ONLY(mov(c_rarg0, r15_thread));
 1553 
 1554   // set last Java frame before call
 1555   assert(last_java_sp != rbp, "can't use ebp/rbp");
 1556 
 1557   // Only interpreter should have to set fp
 1558   set_last_Java_frame(java_thread, last_java_sp, rbp, NULL, rscratch1);
 1559 
 1560   // do the call, remove parameters
 1561   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
 1562 
 1563   // restore the thread (cannot use the pushed argument since arguments
 1564   // may be overwritten by C code generated by an optimizing compiler);
 1565   // however can use the register value directly if it is callee saved.
 1566   if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
 1567     // rdi & rsi (also r15) are callee saved -> nothing to do
 1568 #ifdef ASSERT
 1569     guarantee(java_thread != rax, "change this code");
 1570     push(rax);
 1571     { Label L;
 1572       get_thread(rax);
 1573       cmpptr(java_thread, rax);
 1574       jcc(Assembler::equal, L);
 1575       STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
 1576       bind(L);
 1577     }
 1578     pop(rax);
 1579 #endif
 1580   } else {
 1581     get_thread(java_thread);
 1582   }
 1583   // reset last Java frame
 1584   // Only interpreter should have to clear fp
 1585   reset_last_Java_frame(java_thread, true);
 1586 
 1587    // C++ interp handles this in the interpreter
 1588   check_and_handle_popframe(java_thread);
 1589   check_and_handle_earlyret(java_thread);
 1590 
 1591   if (check_exceptions) {
 1592     // check for pending exceptions (java_thread is set upon return)
 1593     cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
 1594 #ifndef _LP64
 1595     jump_cc(Assembler::notEqual,
 1596             RuntimeAddress(StubRoutines::forward_exception_entry()));
 1597 #else
 1598     // This used to conditionally jump to forward_exception however it is
 1599     // possible if we relocate that the branch will not reach. So we must jump
 1600     // around so we can always reach
 1601 
 1602     Label ok;
 1603     jcc(Assembler::equal, ok);
 1604     jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
 1605     bind(ok);
 1606 #endif // LP64
 1607   }
 1608 
 1609   // get oop result if there is one and reset the value in the thread
 1610   if (oop_result->is_valid()) {
 1611     get_vm_result(oop_result, java_thread);
 1612   }
 1613 }
 1614 
 1615 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
 1616 
 1617   // Calculate the value for last_Java_sp
 1618   // somewhat subtle. call_VM does an intermediate call
 1619   // which places a return address on the stack just under the
 1620   // stack pointer as the user finished with it. This allows
 1621   // use to retrieve last_Java_pc from last_Java_sp[-1].
 1622   // On 32bit we then have to push additional args on the stack to accomplish
 1623   // the actual requested call. On 64bit call_VM only can use register args
 1624   // so the only extra space is the return address that call_VM created.
 1625   // This hopefully explains the calculations here.
 1626 
 1627 #ifdef _LP64
 1628   // We've pushed one address, correct last_Java_sp
 1629   lea(rax, Address(rsp, wordSize));
 1630 #else
 1631   lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
 1632 #endif // LP64
 1633 
 1634   call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
 1635 
 1636 }
 1637 
 1638 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
 1639 void MacroAssembler::call_VM_leaf0(address entry_point) {
 1640   MacroAssembler::call_VM_leaf_base(entry_point, 0);
 1641 }
 1642 
 1643 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
 1644   call_VM_leaf_base(entry_point, number_of_arguments);
 1645 }
 1646 
 1647 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
 1648   pass_arg0(this, arg_0);
 1649   call_VM_leaf(entry_point, 1);
 1650 }
 1651 
 1652 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
 1653 
 1654   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
 1655   pass_arg1(this, arg_1);
 1656   pass_arg0(this, arg_0);
 1657   call_VM_leaf(entry_point, 2);
 1658 }
 1659 
 1660 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
 1661   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
 1662   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
 1663   pass_arg2(this, arg_2);
 1664   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
 1665   pass_arg1(this, arg_1);
 1666   pass_arg0(this, arg_0);
 1667   call_VM_leaf(entry_point, 3);
 1668 }
 1669 
 1670 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
 1671   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
 1672   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
 1673   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
 1674   pass_arg3(this, arg_3);
 1675   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
 1676   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
 1677   pass_arg2(this, arg_2);
 1678   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
 1679   pass_arg1(this, arg_1);
 1680   pass_arg0(this, arg_0);
 1681   call_VM_leaf(entry_point, 3);
 1682 }
 1683 
 1684 void MacroAssembler::super_call_VM_leaf(address entry_point) {
 1685   MacroAssembler::call_VM_leaf_base(entry_point, 1);
 1686 }
 1687 
 1688 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
 1689   pass_arg0(this, arg_0);
 1690   MacroAssembler::call_VM_leaf_base(entry_point, 1);
 1691 }
 1692 
 1693 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
 1694 
 1695   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
 1696   pass_arg1(this, arg_1);
 1697   pass_arg0(this, arg_0);
 1698   MacroAssembler::call_VM_leaf_base(entry_point, 2);
 1699 }
 1700 
 1701 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
 1702   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
 1703   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
 1704   pass_arg2(this, arg_2);
 1705   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
 1706   pass_arg1(this, arg_1);
 1707   pass_arg0(this, arg_0);
 1708   MacroAssembler::call_VM_leaf_base(entry_point, 3);
 1709 }
 1710 
 1711 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
 1712   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
 1713   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
 1714   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
 1715   pass_arg3(this, arg_3);
 1716   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
 1717   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
 1718   pass_arg2(this, arg_2);
 1719   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
 1720   pass_arg1(this, arg_1);
 1721   pass_arg0(this, arg_0);
 1722   MacroAssembler::call_VM_leaf_base(entry_point, 4);
 1723 }
 1724 
 1725 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
 1726   movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
 1727   movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
 1728   verify_oop_msg(oop_result, "broken oop in call_VM_base");
 1729 }
 1730 
 1731 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
 1732   movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
 1733   movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
 1734 }
 1735 
 1736 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
 1737 }
 1738 
 1739 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
 1740 }
 1741 
 1742 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
 1743   assert(rscratch != noreg || always_reachable(src1), "missing");
 1744 
 1745   if (reachable(src1)) {
 1746     cmpl(as_Address(src1), imm);
 1747   } else {
 1748     lea(rscratch, src1);
 1749     cmpl(Address(rscratch, 0), imm);
 1750   }
 1751 }
 1752 
 1753 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
 1754   assert(!src2.is_lval(), "use cmpptr");
 1755   assert(rscratch != noreg || always_reachable(src2), "missing");
 1756 
 1757   if (reachable(src2)) {
 1758     cmpl(src1, as_Address(src2));
 1759   } else {
 1760     lea(rscratch, src2);
 1761     cmpl(src1, Address(rscratch, 0));
 1762   }
 1763 }
 1764 
 1765 void MacroAssembler::cmp32(Register src1, int32_t imm) {
 1766   Assembler::cmpl(src1, imm);
 1767 }
 1768 
 1769 void MacroAssembler::cmp32(Register src1, Address src2) {
 1770   Assembler::cmpl(src1, src2);
 1771 }
 1772 
 1773 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
 1774   ucomisd(opr1, opr2);
 1775 
 1776   Label L;
 1777   if (unordered_is_less) {
 1778     movl(dst, -1);
 1779     jcc(Assembler::parity, L);
 1780     jcc(Assembler::below , L);
 1781     movl(dst, 0);
 1782     jcc(Assembler::equal , L);
 1783     increment(dst);
 1784   } else { // unordered is greater
 1785     movl(dst, 1);
 1786     jcc(Assembler::parity, L);
 1787     jcc(Assembler::above , L);
 1788     movl(dst, 0);
 1789     jcc(Assembler::equal , L);
 1790     decrementl(dst);
 1791   }
 1792   bind(L);
 1793 }
 1794 
 1795 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
 1796   ucomiss(opr1, opr2);
 1797 
 1798   Label L;
 1799   if (unordered_is_less) {
 1800     movl(dst, -1);
 1801     jcc(Assembler::parity, L);
 1802     jcc(Assembler::below , L);
 1803     movl(dst, 0);
 1804     jcc(Assembler::equal , L);
 1805     increment(dst);
 1806   } else { // unordered is greater
 1807     movl(dst, 1);
 1808     jcc(Assembler::parity, L);
 1809     jcc(Assembler::above , L);
 1810     movl(dst, 0);
 1811     jcc(Assembler::equal , L);
 1812     decrementl(dst);
 1813   }
 1814   bind(L);
 1815 }
 1816 
 1817 
 1818 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
 1819   assert(rscratch != noreg || always_reachable(src1), "missing");
 1820 
 1821   if (reachable(src1)) {
 1822     cmpb(as_Address(src1), imm);
 1823   } else {
 1824     lea(rscratch, src1);
 1825     cmpb(Address(rscratch, 0), imm);
 1826   }
 1827 }
 1828 
 1829 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
 1830 #ifdef _LP64
 1831   assert(rscratch != noreg || always_reachable(src2), "missing");
 1832 
 1833   if (src2.is_lval()) {
 1834     movptr(rscratch, src2);
 1835     Assembler::cmpq(src1, rscratch);
 1836   } else if (reachable(src2)) {
 1837     cmpq(src1, as_Address(src2));
 1838   } else {
 1839     lea(rscratch, src2);
 1840     Assembler::cmpq(src1, Address(rscratch, 0));
 1841   }
 1842 #else
 1843   assert(rscratch == noreg, "not needed");
 1844   if (src2.is_lval()) {
 1845     cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
 1846   } else {
 1847     cmpl(src1, as_Address(src2));
 1848   }
 1849 #endif // _LP64
 1850 }
 1851 
 1852 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
 1853   assert(src2.is_lval(), "not a mem-mem compare");
 1854 #ifdef _LP64
 1855   // moves src2's literal address
 1856   movptr(rscratch, src2);
 1857   Assembler::cmpq(src1, rscratch);
 1858 #else
 1859   assert(rscratch == noreg, "not needed");
 1860   cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
 1861 #endif // _LP64
 1862 }
 1863 
 1864 void MacroAssembler::cmpoop(Register src1, Register src2) {
 1865   cmpptr(src1, src2);
 1866 }
 1867 
 1868 void MacroAssembler::cmpoop(Register src1, Address src2) {
 1869   cmpptr(src1, src2);
 1870 }
 1871 
 1872 #ifdef _LP64
 1873 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
 1874   movoop(rscratch, src2);
 1875   cmpptr(src1, rscratch);
 1876 }
 1877 #endif
 1878 
 1879 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
 1880   assert(rscratch != noreg || always_reachable(adr), "missing");
 1881 
 1882   if (reachable(adr)) {
 1883     lock();
 1884     cmpxchgptr(reg, as_Address(adr));
 1885   } else {
 1886     lea(rscratch, adr);
 1887     lock();
 1888     cmpxchgptr(reg, Address(rscratch, 0));
 1889   }
 1890 }
 1891 
 1892 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
 1893   LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
 1894 }
 1895 
 1896 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
 1897   assert(rscratch != noreg || always_reachable(src), "missing");
 1898 
 1899   if (reachable(src)) {
 1900     Assembler::comisd(dst, as_Address(src));
 1901   } else {
 1902     lea(rscratch, src);
 1903     Assembler::comisd(dst, Address(rscratch, 0));
 1904   }
 1905 }
 1906 
 1907 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
 1908   assert(rscratch != noreg || always_reachable(src), "missing");
 1909 
 1910   if (reachable(src)) {
 1911     Assembler::comiss(dst, as_Address(src));
 1912   } else {
 1913     lea(rscratch, src);
 1914     Assembler::comiss(dst, Address(rscratch, 0));
 1915   }
 1916 }
 1917 
 1918 
 1919 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
 1920   assert(rscratch != noreg || always_reachable(counter_addr), "missing");
 1921 
 1922   Condition negated_cond = negate_condition(cond);
 1923   Label L;
 1924   jcc(negated_cond, L);
 1925   pushf(); // Preserve flags
 1926   atomic_incl(counter_addr, rscratch);
 1927   popf();
 1928   bind(L);
 1929 }
 1930 
 1931 int MacroAssembler::corrected_idivl(Register reg) {
 1932   // Full implementation of Java idiv and irem; checks for
 1933   // special case as described in JVM spec., p.243 & p.271.
 1934   // The function returns the (pc) offset of the idivl
 1935   // instruction - may be needed for implicit exceptions.
 1936   //
 1937   //         normal case                           special case
 1938   //
 1939   // input : rax,: dividend                         min_int
 1940   //         reg: divisor   (may not be rax,/rdx)   -1
 1941   //
 1942   // output: rax,: quotient  (= rax, idiv reg)       min_int
 1943   //         rdx: remainder (= rax, irem reg)       0
 1944   assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
 1945   const int min_int = 0x80000000;
 1946   Label normal_case, special_case;
 1947 
 1948   // check for special case
 1949   cmpl(rax, min_int);
 1950   jcc(Assembler::notEqual, normal_case);
 1951   xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
 1952   cmpl(reg, -1);
 1953   jcc(Assembler::equal, special_case);
 1954 
 1955   // handle normal case
 1956   bind(normal_case);
 1957   cdql();
 1958   int idivl_offset = offset();
 1959   idivl(reg);
 1960 
 1961   // normal and special case exit
 1962   bind(special_case);
 1963 
 1964   return idivl_offset;
 1965 }
 1966 
 1967 
 1968 
 1969 void MacroAssembler::decrementl(Register reg, int value) {
 1970   if (value == min_jint) {subl(reg, value) ; return; }
 1971   if (value <  0) { incrementl(reg, -value); return; }
 1972   if (value == 0) {                        ; return; }
 1973   if (value == 1 && UseIncDec) { decl(reg) ; return; }
 1974   /* else */      { subl(reg, value)       ; return; }
 1975 }
 1976 
 1977 void MacroAssembler::decrementl(Address dst, int value) {
 1978   if (value == min_jint) {subl(dst, value) ; return; }
 1979   if (value <  0) { incrementl(dst, -value); return; }
 1980   if (value == 0) {                        ; return; }
 1981   if (value == 1 && UseIncDec) { decl(dst) ; return; }
 1982   /* else */      { subl(dst, value)       ; return; }
 1983 }
 1984 
 1985 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
 1986   assert(shift_value > 0, "illegal shift value");
 1987   Label _is_positive;
 1988   testl (reg, reg);
 1989   jcc (Assembler::positive, _is_positive);
 1990   int offset = (1 << shift_value) - 1 ;
 1991 
 1992   if (offset == 1) {
 1993     incrementl(reg);
 1994   } else {
 1995     addl(reg, offset);
 1996   }
 1997 
 1998   bind (_is_positive);
 1999   sarl(reg, shift_value);
 2000 }
 2001 
 2002 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2003   assert(rscratch != noreg || always_reachable(src), "missing");
 2004 
 2005   if (reachable(src)) {
 2006     Assembler::divsd(dst, as_Address(src));
 2007   } else {
 2008     lea(rscratch, src);
 2009     Assembler::divsd(dst, Address(rscratch, 0));
 2010   }
 2011 }
 2012 
 2013 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2014   assert(rscratch != noreg || always_reachable(src), "missing");
 2015 
 2016   if (reachable(src)) {
 2017     Assembler::divss(dst, as_Address(src));
 2018   } else {
 2019     lea(rscratch, src);
 2020     Assembler::divss(dst, Address(rscratch, 0));
 2021   }
 2022 }
 2023 
 2024 void MacroAssembler::enter() {
 2025   push(rbp);
 2026   mov(rbp, rsp);
 2027 }
 2028 
 2029 void MacroAssembler::post_call_nop() {
 2030   if (!Continuations::enabled()) {
 2031     return;
 2032   }
 2033   InstructionMark im(this);
 2034   relocate(post_call_nop_Relocation::spec());
 2035   emit_int8((int8_t)0x0f);
 2036   emit_int8((int8_t)0x1f);
 2037   emit_int8((int8_t)0x84);
 2038   emit_int8((int8_t)0x00);
 2039   emit_int32(0x00);
 2040 }
 2041 
 2042 // A 5 byte nop that is safe for patching (see patch_verified_entry)
 2043 void MacroAssembler::fat_nop() {
 2044   if (UseAddressNop) {
 2045     addr_nop_5();
 2046   } else {
 2047     emit_int8((int8_t)0x26); // es:
 2048     emit_int8((int8_t)0x2e); // cs:
 2049     emit_int8((int8_t)0x64); // fs:
 2050     emit_int8((int8_t)0x65); // gs:
 2051     emit_int8((int8_t)0x90);
 2052   }
 2053 }
 2054 
 2055 #ifndef _LP64
 2056 void MacroAssembler::fcmp(Register tmp) {
 2057   fcmp(tmp, 1, true, true);
 2058 }
 2059 
 2060 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
 2061   assert(!pop_right || pop_left, "usage error");
 2062   if (VM_Version::supports_cmov()) {
 2063     assert(tmp == noreg, "unneeded temp");
 2064     if (pop_left) {
 2065       fucomip(index);
 2066     } else {
 2067       fucomi(index);
 2068     }
 2069     if (pop_right) {
 2070       fpop();
 2071     }
 2072   } else {
 2073     assert(tmp != noreg, "need temp");
 2074     if (pop_left) {
 2075       if (pop_right) {
 2076         fcompp();
 2077       } else {
 2078         fcomp(index);
 2079       }
 2080     } else {
 2081       fcom(index);
 2082     }
 2083     // convert FPU condition into eflags condition via rax,
 2084     save_rax(tmp);
 2085     fwait(); fnstsw_ax();
 2086     sahf();
 2087     restore_rax(tmp);
 2088   }
 2089   // condition codes set as follows:
 2090   //
 2091   // CF (corresponds to C0) if x < y
 2092   // PF (corresponds to C2) if unordered
 2093   // ZF (corresponds to C3) if x = y
 2094 }
 2095 
 2096 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
 2097   fcmp2int(dst, unordered_is_less, 1, true, true);
 2098 }
 2099 
 2100 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
 2101   fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
 2102   Label L;
 2103   if (unordered_is_less) {
 2104     movl(dst, -1);
 2105     jcc(Assembler::parity, L);
 2106     jcc(Assembler::below , L);
 2107     movl(dst, 0);
 2108     jcc(Assembler::equal , L);
 2109     increment(dst);
 2110   } else { // unordered is greater
 2111     movl(dst, 1);
 2112     jcc(Assembler::parity, L);
 2113     jcc(Assembler::above , L);
 2114     movl(dst, 0);
 2115     jcc(Assembler::equal , L);
 2116     decrementl(dst);
 2117   }
 2118   bind(L);
 2119 }
 2120 
 2121 void MacroAssembler::fld_d(AddressLiteral src) {
 2122   fld_d(as_Address(src));
 2123 }
 2124 
 2125 void MacroAssembler::fld_s(AddressLiteral src) {
 2126   fld_s(as_Address(src));
 2127 }
 2128 
 2129 void MacroAssembler::fldcw(AddressLiteral src) {
 2130   fldcw(as_Address(src));
 2131 }
 2132 
 2133 void MacroAssembler::fpop() {
 2134   ffree();
 2135   fincstp();
 2136 }
 2137 
 2138 void MacroAssembler::fremr(Register tmp) {
 2139   save_rax(tmp);
 2140   { Label L;
 2141     bind(L);
 2142     fprem();
 2143     fwait(); fnstsw_ax();
 2144     sahf();
 2145     jcc(Assembler::parity, L);
 2146   }
 2147   restore_rax(tmp);
 2148   // Result is in ST0.
 2149   // Note: fxch & fpop to get rid of ST1
 2150   // (otherwise FPU stack could overflow eventually)
 2151   fxch(1);
 2152   fpop();
 2153 }
 2154 
 2155 void MacroAssembler::empty_FPU_stack() {
 2156   if (VM_Version::supports_mmx()) {
 2157     emms();
 2158   } else {
 2159     for (int i = 8; i-- > 0; ) ffree(i);
 2160   }
 2161 }
 2162 #endif // !LP64
 2163 
 2164 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2165   assert(rscratch != noreg || always_reachable(src), "missing");
 2166   if (reachable(src)) {
 2167     Assembler::mulpd(dst, as_Address(src));
 2168   } else {
 2169     lea(rscratch, src);
 2170     Assembler::mulpd(dst, Address(rscratch, 0));
 2171   }
 2172 }
 2173 
 2174 void MacroAssembler::load_float(Address src) {
 2175 #ifdef _LP64
 2176   movflt(xmm0, src);
 2177 #else
 2178   if (UseSSE >= 1) {
 2179     movflt(xmm0, src);
 2180   } else {
 2181     fld_s(src);
 2182   }
 2183 #endif // LP64
 2184 }
 2185 
 2186 void MacroAssembler::store_float(Address dst) {
 2187 #ifdef _LP64
 2188   movflt(dst, xmm0);
 2189 #else
 2190   if (UseSSE >= 1) {
 2191     movflt(dst, xmm0);
 2192   } else {
 2193     fstp_s(dst);
 2194   }
 2195 #endif // LP64
 2196 }
 2197 
 2198 void MacroAssembler::load_double(Address src) {
 2199 #ifdef _LP64
 2200   movdbl(xmm0, src);
 2201 #else
 2202   if (UseSSE >= 2) {
 2203     movdbl(xmm0, src);
 2204   } else {
 2205     fld_d(src);
 2206   }
 2207 #endif // LP64
 2208 }
 2209 
 2210 void MacroAssembler::store_double(Address dst) {
 2211 #ifdef _LP64
 2212   movdbl(dst, xmm0);
 2213 #else
 2214   if (UseSSE >= 2) {
 2215     movdbl(dst, xmm0);
 2216   } else {
 2217     fstp_d(dst);
 2218   }
 2219 #endif // LP64
 2220 }
 2221 
 2222 // dst = c = a * b + c
 2223 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
 2224   Assembler::vfmadd231sd(c, a, b);
 2225   if (dst != c) {
 2226     movdbl(dst, c);
 2227   }
 2228 }
 2229 
 2230 // dst = c = a * b + c
 2231 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
 2232   Assembler::vfmadd231ss(c, a, b);
 2233   if (dst != c) {
 2234     movflt(dst, c);
 2235   }
 2236 }
 2237 
 2238 // dst = c = a * b + c
 2239 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
 2240   Assembler::vfmadd231pd(c, a, b, vector_len);
 2241   if (dst != c) {
 2242     vmovdqu(dst, c);
 2243   }
 2244 }
 2245 
 2246 // dst = c = a * b + c
 2247 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
 2248   Assembler::vfmadd231ps(c, a, b, vector_len);
 2249   if (dst != c) {
 2250     vmovdqu(dst, c);
 2251   }
 2252 }
 2253 
 2254 // dst = c = a * b + c
 2255 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
 2256   Assembler::vfmadd231pd(c, a, b, vector_len);
 2257   if (dst != c) {
 2258     vmovdqu(dst, c);
 2259   }
 2260 }
 2261 
 2262 // dst = c = a * b + c
 2263 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
 2264   Assembler::vfmadd231ps(c, a, b, vector_len);
 2265   if (dst != c) {
 2266     vmovdqu(dst, c);
 2267   }
 2268 }
 2269 
 2270 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
 2271   assert(rscratch != noreg || always_reachable(dst), "missing");
 2272 
 2273   if (reachable(dst)) {
 2274     incrementl(as_Address(dst));
 2275   } else {
 2276     lea(rscratch, dst);
 2277     incrementl(Address(rscratch, 0));
 2278   }
 2279 }
 2280 
 2281 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
 2282   incrementl(as_Address(dst, rscratch));
 2283 }
 2284 
 2285 void MacroAssembler::incrementl(Register reg, int value) {
 2286   if (value == min_jint) {addl(reg, value) ; return; }
 2287   if (value <  0) { decrementl(reg, -value); return; }
 2288   if (value == 0) {                        ; return; }
 2289   if (value == 1 && UseIncDec) { incl(reg) ; return; }
 2290   /* else */      { addl(reg, value)       ; return; }
 2291 }
 2292 
 2293 void MacroAssembler::incrementl(Address dst, int value) {
 2294   if (value == min_jint) {addl(dst, value) ; return; }
 2295   if (value <  0) { decrementl(dst, -value); return; }
 2296   if (value == 0) {                        ; return; }
 2297   if (value == 1 && UseIncDec) { incl(dst) ; return; }
 2298   /* else */      { addl(dst, value)       ; return; }
 2299 }
 2300 
 2301 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
 2302   assert(rscratch != noreg || always_reachable(dst), "missing");
 2303 
 2304   if (reachable(dst)) {
 2305     jmp_literal(dst.target(), dst.rspec());
 2306   } else {
 2307     lea(rscratch, dst);
 2308     jmp(rscratch);
 2309   }
 2310 }
 2311 
 2312 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
 2313   assert(rscratch != noreg || always_reachable(dst), "missing");
 2314 
 2315   if (reachable(dst)) {
 2316     InstructionMark im(this);
 2317     relocate(dst.reloc());
 2318     const int short_size = 2;
 2319     const int long_size = 6;
 2320     int offs = (intptr_t)dst.target() - ((intptr_t)pc());
 2321     if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
 2322       // 0111 tttn #8-bit disp
 2323       emit_int8(0x70 | cc);
 2324       emit_int8((offs - short_size) & 0xFF);
 2325     } else {
 2326       // 0000 1111 1000 tttn #32-bit disp
 2327       emit_int8(0x0F);
 2328       emit_int8((unsigned char)(0x80 | cc));
 2329       emit_int32(offs - long_size);
 2330     }
 2331   } else {
 2332 #ifdef ASSERT
 2333     warning("reversing conditional branch");
 2334 #endif /* ASSERT */
 2335     Label skip;
 2336     jccb(reverse[cc], skip);
 2337     lea(rscratch, dst);
 2338     Assembler::jmp(rscratch);
 2339     bind(skip);
 2340   }
 2341 }
 2342 
 2343 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
 2344   assert(rscratch != noreg || always_reachable(src), "missing");
 2345 
 2346   if (reachable(src)) {
 2347     Assembler::ldmxcsr(as_Address(src));
 2348   } else {
 2349     lea(rscratch, src);
 2350     Assembler::ldmxcsr(Address(rscratch, 0));
 2351   }
 2352 }
 2353 
 2354 int MacroAssembler::load_signed_byte(Register dst, Address src) {
 2355   int off;
 2356   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
 2357     off = offset();
 2358     movsbl(dst, src); // movsxb
 2359   } else {
 2360     off = load_unsigned_byte(dst, src);
 2361     shll(dst, 24);
 2362     sarl(dst, 24);
 2363   }
 2364   return off;
 2365 }
 2366 
 2367 // Note: load_signed_short used to be called load_signed_word.
 2368 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
 2369 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
 2370 // The term "word" in HotSpot means a 32- or 64-bit machine word.
 2371 int MacroAssembler::load_signed_short(Register dst, Address src) {
 2372   int off;
 2373   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
 2374     // This is dubious to me since it seems safe to do a signed 16 => 64 bit
 2375     // version but this is what 64bit has always done. This seems to imply
 2376     // that users are only using 32bits worth.
 2377     off = offset();
 2378     movswl(dst, src); // movsxw
 2379   } else {
 2380     off = load_unsigned_short(dst, src);
 2381     shll(dst, 16);
 2382     sarl(dst, 16);
 2383   }
 2384   return off;
 2385 }
 2386 
 2387 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
 2388   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
 2389   // and "3.9 Partial Register Penalties", p. 22).
 2390   int off;
 2391   if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
 2392     off = offset();
 2393     movzbl(dst, src); // movzxb
 2394   } else {
 2395     xorl(dst, dst);
 2396     off = offset();
 2397     movb(dst, src);
 2398   }
 2399   return off;
 2400 }
 2401 
 2402 // Note: load_unsigned_short used to be called load_unsigned_word.
 2403 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
 2404   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
 2405   // and "3.9 Partial Register Penalties", p. 22).
 2406   int off;
 2407   if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
 2408     off = offset();
 2409     movzwl(dst, src); // movzxw
 2410   } else {
 2411     xorl(dst, dst);
 2412     off = offset();
 2413     movw(dst, src);
 2414   }
 2415   return off;
 2416 }
 2417 
 2418 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
 2419   switch (size_in_bytes) {
 2420 #ifndef _LP64
 2421   case  8:
 2422     assert(dst2 != noreg, "second dest register required");
 2423     movl(dst,  src);
 2424     movl(dst2, src.plus_disp(BytesPerInt));
 2425     break;
 2426 #else
 2427   case  8:  movq(dst, src); break;
 2428 #endif
 2429   case  4:  movl(dst, src); break;
 2430   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
 2431   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
 2432   default:  ShouldNotReachHere();
 2433   }
 2434 }
 2435 
 2436 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
 2437   switch (size_in_bytes) {
 2438 #ifndef _LP64
 2439   case  8:
 2440     assert(src2 != noreg, "second source register required");
 2441     movl(dst,                        src);
 2442     movl(dst.plus_disp(BytesPerInt), src2);
 2443     break;
 2444 #else
 2445   case  8:  movq(dst, src); break;
 2446 #endif
 2447   case  4:  movl(dst, src); break;
 2448   case  2:  movw(dst, src); break;
 2449   case  1:  movb(dst, src); break;
 2450   default:  ShouldNotReachHere();
 2451   }
 2452 }
 2453 
 2454 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
 2455   assert(rscratch != noreg || always_reachable(dst), "missing");
 2456 
 2457   if (reachable(dst)) {
 2458     movl(as_Address(dst), src);
 2459   } else {
 2460     lea(rscratch, dst);
 2461     movl(Address(rscratch, 0), src);
 2462   }
 2463 }
 2464 
 2465 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
 2466   if (reachable(src)) {
 2467     movl(dst, as_Address(src));
 2468   } else {
 2469     lea(dst, src);
 2470     movl(dst, Address(dst, 0));
 2471   }
 2472 }
 2473 
 2474 // C++ bool manipulation
 2475 
 2476 void MacroAssembler::movbool(Register dst, Address src) {
 2477   if(sizeof(bool) == 1)
 2478     movb(dst, src);
 2479   else if(sizeof(bool) == 2)
 2480     movw(dst, src);
 2481   else if(sizeof(bool) == 4)
 2482     movl(dst, src);
 2483   else
 2484     // unsupported
 2485     ShouldNotReachHere();
 2486 }
 2487 
 2488 void MacroAssembler::movbool(Address dst, bool boolconst) {
 2489   if(sizeof(bool) == 1)
 2490     movb(dst, (int) boolconst);
 2491   else if(sizeof(bool) == 2)
 2492     movw(dst, (int) boolconst);
 2493   else if(sizeof(bool) == 4)
 2494     movl(dst, (int) boolconst);
 2495   else
 2496     // unsupported
 2497     ShouldNotReachHere();
 2498 }
 2499 
 2500 void MacroAssembler::movbool(Address dst, Register src) {
 2501   if(sizeof(bool) == 1)
 2502     movb(dst, src);
 2503   else if(sizeof(bool) == 2)
 2504     movw(dst, src);
 2505   else if(sizeof(bool) == 4)
 2506     movl(dst, src);
 2507   else
 2508     // unsupported
 2509     ShouldNotReachHere();
 2510 }
 2511 
 2512 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2513   assert(rscratch != noreg || always_reachable(src), "missing");
 2514 
 2515   if (reachable(src)) {
 2516     movdl(dst, as_Address(src));
 2517   } else {
 2518     lea(rscratch, src);
 2519     movdl(dst, Address(rscratch, 0));
 2520   }
 2521 }
 2522 
 2523 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2524   assert(rscratch != noreg || always_reachable(src), "missing");
 2525 
 2526   if (reachable(src)) {
 2527     movq(dst, as_Address(src));
 2528   } else {
 2529     lea(rscratch, src);
 2530     movq(dst, Address(rscratch, 0));
 2531   }
 2532 }
 2533 
 2534 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2535   assert(rscratch != noreg || always_reachable(src), "missing");
 2536 
 2537   if (reachable(src)) {
 2538     if (UseXmmLoadAndClearUpper) {
 2539       movsd (dst, as_Address(src));
 2540     } else {
 2541       movlpd(dst, as_Address(src));
 2542     }
 2543   } else {
 2544     lea(rscratch, src);
 2545     if (UseXmmLoadAndClearUpper) {
 2546       movsd (dst, Address(rscratch, 0));
 2547     } else {
 2548       movlpd(dst, Address(rscratch, 0));
 2549     }
 2550   }
 2551 }
 2552 
 2553 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2554   assert(rscratch != noreg || always_reachable(src), "missing");
 2555 
 2556   if (reachable(src)) {
 2557     movss(dst, as_Address(src));
 2558   } else {
 2559     lea(rscratch, src);
 2560     movss(dst, Address(rscratch, 0));
 2561   }
 2562 }
 2563 
 2564 void MacroAssembler::movptr(Register dst, Register src) {
 2565   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
 2566 }
 2567 
 2568 void MacroAssembler::movptr(Register dst, Address src) {
 2569   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
 2570 }
 2571 
 2572 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 2573 void MacroAssembler::movptr(Register dst, intptr_t src) {
 2574   LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
 2575 }
 2576 
 2577 void MacroAssembler::movptr(Address dst, Register src) {
 2578   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
 2579 }
 2580 
 2581 void MacroAssembler::movptr(Address dst, int32_t src) {
 2582   LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src));
 2583 }
 2584 
 2585 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
 2586   assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
 2587   Assembler::movdqu(dst, src);
 2588 }
 2589 
 2590 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
 2591   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
 2592   Assembler::movdqu(dst, src);
 2593 }
 2594 
 2595 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
 2596   assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
 2597   Assembler::movdqu(dst, src);
 2598 }
 2599 
 2600 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2601   assert(rscratch != noreg || always_reachable(src), "missing");
 2602 
 2603   if (reachable(src)) {
 2604     movdqu(dst, as_Address(src));
 2605   } else {
 2606     lea(rscratch, src);
 2607     movdqu(dst, Address(rscratch, 0));
 2608   }
 2609 }
 2610 
 2611 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
 2612   assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
 2613   Assembler::vmovdqu(dst, src);
 2614 }
 2615 
 2616 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
 2617   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
 2618   Assembler::vmovdqu(dst, src);
 2619 }
 2620 
 2621 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
 2622   assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
 2623   Assembler::vmovdqu(dst, src);
 2624 }
 2625 
 2626 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2627   assert(rscratch != noreg || always_reachable(src), "missing");
 2628 
 2629   if (reachable(src)) {
 2630     vmovdqu(dst, as_Address(src));
 2631   }
 2632   else {
 2633     lea(rscratch, src);
 2634     vmovdqu(dst, Address(rscratch, 0));
 2635   }
 2636 }
 2637 
 2638 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
 2639   assert(rscratch != noreg || always_reachable(src), "missing");
 2640 
 2641   if (vector_len == AVX_512bit) {
 2642     evmovdquq(dst, src, AVX_512bit, rscratch);
 2643   } else if (vector_len == AVX_256bit) {
 2644     vmovdqu(dst, src, rscratch);
 2645   } else {
 2646     movdqu(dst, src, rscratch);
 2647   }
 2648 }
 2649 
 2650 void MacroAssembler::kmov(KRegister dst, Address src) {
 2651   if (VM_Version::supports_avx512bw()) {
 2652     kmovql(dst, src);
 2653   } else {
 2654     assert(VM_Version::supports_evex(), "");
 2655     kmovwl(dst, src);
 2656   }
 2657 }
 2658 
 2659 void MacroAssembler::kmov(Address dst, KRegister src) {
 2660   if (VM_Version::supports_avx512bw()) {
 2661     kmovql(dst, src);
 2662   } else {
 2663     assert(VM_Version::supports_evex(), "");
 2664     kmovwl(dst, src);
 2665   }
 2666 }
 2667 
 2668 void MacroAssembler::kmov(KRegister dst, KRegister src) {
 2669   if (VM_Version::supports_avx512bw()) {
 2670     kmovql(dst, src);
 2671   } else {
 2672     assert(VM_Version::supports_evex(), "");
 2673     kmovwl(dst, src);
 2674   }
 2675 }
 2676 
 2677 void MacroAssembler::kmov(Register dst, KRegister src) {
 2678   if (VM_Version::supports_avx512bw()) {
 2679     kmovql(dst, src);
 2680   } else {
 2681     assert(VM_Version::supports_evex(), "");
 2682     kmovwl(dst, src);
 2683   }
 2684 }
 2685 
 2686 void MacroAssembler::kmov(KRegister dst, Register src) {
 2687   if (VM_Version::supports_avx512bw()) {
 2688     kmovql(dst, src);
 2689   } else {
 2690     assert(VM_Version::supports_evex(), "");
 2691     kmovwl(dst, src);
 2692   }
 2693 }
 2694 
 2695 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
 2696   assert(rscratch != noreg || always_reachable(src), "missing");
 2697 
 2698   if (reachable(src)) {
 2699     kmovql(dst, as_Address(src));
 2700   } else {
 2701     lea(rscratch, src);
 2702     kmovql(dst, Address(rscratch, 0));
 2703   }
 2704 }
 2705 
 2706 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
 2707   assert(rscratch != noreg || always_reachable(src), "missing");
 2708 
 2709   if (reachable(src)) {
 2710     kmovwl(dst, as_Address(src));
 2711   } else {
 2712     lea(rscratch, src);
 2713     kmovwl(dst, Address(rscratch, 0));
 2714   }
 2715 }
 2716 
 2717 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
 2718                                int vector_len, Register rscratch) {
 2719   assert(rscratch != noreg || always_reachable(src), "missing");
 2720 
 2721   if (reachable(src)) {
 2722     Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
 2723   } else {
 2724     lea(rscratch, src);
 2725     Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
 2726   }
 2727 }
 2728 
 2729 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
 2730                                int vector_len, Register rscratch) {
 2731   assert(rscratch != noreg || always_reachable(src), "missing");
 2732 
 2733   if (reachable(src)) {
 2734     Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
 2735   } else {
 2736     lea(rscratch, src);
 2737     Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
 2738   }
 2739 }
 2740 
 2741 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
 2742   assert(rscratch != noreg || always_reachable(src), "missing");
 2743 
 2744   if (reachable(src)) {
 2745     Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
 2746   } else {
 2747     lea(rscratch, src);
 2748     Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
 2749   }
 2750 }
 2751 
 2752 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
 2753   assert(rscratch != noreg || always_reachable(src), "missing");
 2754 
 2755   if (reachable(src)) {
 2756     Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
 2757   } else {
 2758     lea(rscratch, src);
 2759     Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
 2760   }
 2761 }
 2762 
 2763 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
 2764   assert(rscratch != noreg || always_reachable(src), "missing");
 2765 
 2766   if (reachable(src)) {
 2767     Assembler::evmovdquq(dst, as_Address(src), vector_len);
 2768   } else {
 2769     lea(rscratch, src);
 2770     Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
 2771   }
 2772 }
 2773 
 2774 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2775   assert(rscratch != noreg || always_reachable(src), "missing");
 2776 
 2777   if (reachable(src)) {
 2778     Assembler::movdqa(dst, as_Address(src));
 2779   } else {
 2780     lea(rscratch, src);
 2781     Assembler::movdqa(dst, Address(rscratch, 0));
 2782   }
 2783 }
 2784 
 2785 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2786   assert(rscratch != noreg || always_reachable(src), "missing");
 2787 
 2788   if (reachable(src)) {
 2789     Assembler::movsd(dst, as_Address(src));
 2790   } else {
 2791     lea(rscratch, src);
 2792     Assembler::movsd(dst, Address(rscratch, 0));
 2793   }
 2794 }
 2795 
 2796 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2797   assert(rscratch != noreg || always_reachable(src), "missing");
 2798 
 2799   if (reachable(src)) {
 2800     Assembler::movss(dst, as_Address(src));
 2801   } else {
 2802     lea(rscratch, src);
 2803     Assembler::movss(dst, Address(rscratch, 0));
 2804   }
 2805 }
 2806 
 2807 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2808   assert(rscratch != noreg || always_reachable(src), "missing");
 2809 
 2810   if (reachable(src)) {
 2811     Assembler::movddup(dst, as_Address(src));
 2812   } else {
 2813     lea(rscratch, src);
 2814     Assembler::movddup(dst, Address(rscratch, 0));
 2815   }
 2816 }
 2817 
 2818 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
 2819   assert(rscratch != noreg || always_reachable(src), "missing");
 2820 
 2821   if (reachable(src)) {
 2822     Assembler::vmovddup(dst, as_Address(src), vector_len);
 2823   } else {
 2824     lea(rscratch, src);
 2825     Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
 2826   }
 2827 }
 2828 
 2829 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2830   assert(rscratch != noreg || always_reachable(src), "missing");
 2831 
 2832   if (reachable(src)) {
 2833     Assembler::mulsd(dst, as_Address(src));
 2834   } else {
 2835     lea(rscratch, src);
 2836     Assembler::mulsd(dst, Address(rscratch, 0));
 2837   }
 2838 }
 2839 
 2840 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
 2841   assert(rscratch != noreg || always_reachable(src), "missing");
 2842 
 2843   if (reachable(src)) {
 2844     Assembler::mulss(dst, as_Address(src));
 2845   } else {
 2846     lea(rscratch, src);
 2847     Assembler::mulss(dst, Address(rscratch, 0));
 2848   }
 2849 }
 2850 
 2851 void MacroAssembler::null_check(Register reg, int offset) {
 2852   if (needs_explicit_null_check(offset)) {
 2853     // provoke OS NULL exception if reg = NULL by
 2854     // accessing M[reg] w/o changing any (non-CC) registers
 2855     // NOTE: cmpl is plenty here to provoke a segv
 2856     cmpptr(rax, Address(reg, 0));
 2857     // Note: should probably use testl(rax, Address(reg, 0));
 2858     //       may be shorter code (however, this version of
 2859     //       testl needs to be implemented first)
 2860   } else {
 2861     // nothing to do, (later) access of M[reg + offset]
 2862     // will provoke OS NULL exception if reg = NULL
 2863   }
 2864 }
 2865 
 2866 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
 2867   andptr(markword, markWord::inline_type_mask_in_place);
 2868   cmpptr(markword, markWord::inline_type_pattern);
 2869   jcc(Assembler::equal, is_inline_type);
 2870 }
 2871 
 2872 void MacroAssembler::test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type) {
 2873   movl(temp_reg, Address(klass, Klass::access_flags_offset()));
 2874   testl(temp_reg, JVM_ACC_VALUE);
 2875   jcc(Assembler::notZero, is_inline_type);
 2876 }
 2877 
 2878 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type) {
 2879   testptr(object, object);
 2880   jcc(Assembler::zero, not_inline_type);
 2881   const int is_inline_type_mask = markWord::inline_type_pattern;
 2882   movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
 2883   andptr(tmp, is_inline_type_mask);
 2884   cmpptr(tmp, is_inline_type_mask);
 2885   jcc(Assembler::notEqual, not_inline_type);
 2886 }
 2887 
 2888 void MacroAssembler::test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type) {
 2889 #ifdef ASSERT
 2890   {
 2891     Label done_check;
 2892     test_klass_is_inline_type(klass, temp_reg, done_check);
 2893     stop("test_klass_is_empty_inline_type with non inline type klass");
 2894     bind(done_check);
 2895   }
 2896 #endif
 2897   movl(temp_reg, Address(klass, InstanceKlass::misc_flags_offset()));
 2898   testl(temp_reg, InstanceKlass::misc_flag_is_empty_inline_type());
 2899   jcc(Assembler::notZero, is_empty_inline_type);
 2900 }
 2901 
 2902 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
 2903   movl(temp_reg, flags);
 2904   shrl(temp_reg, ConstantPoolCacheEntry::is_null_free_inline_type_shift);
 2905   andl(temp_reg, 0x1);
 2906   testl(temp_reg, temp_reg);
 2907   jcc(Assembler::notZero, is_null_free_inline_type);
 2908 }
 2909 
 2910 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
 2911   movl(temp_reg, flags);
 2912   shrl(temp_reg, ConstantPoolCacheEntry::is_null_free_inline_type_shift);
 2913   andl(temp_reg, 0x1);
 2914   testl(temp_reg, temp_reg);
 2915   jcc(Assembler::zero, not_null_free_inline_type);
 2916 }
 2917 
 2918 void MacroAssembler::test_field_is_inlined(Register flags, Register temp_reg, Label& is_inlined) {
 2919   movl(temp_reg, flags);
 2920   shrl(temp_reg, ConstantPoolCacheEntry::is_inlined_shift);
 2921   andl(temp_reg, 0x1);
 2922   testl(temp_reg, temp_reg);
 2923   jcc(Assembler::notZero, is_inlined);
 2924 }
 2925 
 2926 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
 2927   Label test_mark_word;
 2928   // load mark word
 2929   movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
 2930   // check displaced
 2931   testl(temp_reg, markWord::unlocked_value);
 2932   jccb(Assembler::notZero, test_mark_word);
 2933   // slow path use klass prototype
 2934   push(rscratch1);
 2935   load_prototype_header(temp_reg, oop, rscratch1);
 2936   pop(rscratch1);
 2937 
 2938   bind(test_mark_word);
 2939   testl(temp_reg, test_bit);
 2940   jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
 2941 }
 2942 
 2943 void MacroAssembler::test_flattened_array_oop(Register oop, Register temp_reg,
 2944                                               Label&is_flattened_array) {
 2945 #ifdef _LP64
 2946   test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flattened_array);
 2947 #else
 2948   load_klass(temp_reg, oop, noreg);
 2949   movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
 2950   test_flattened_array_layout(temp_reg, is_flattened_array);
 2951 #endif
 2952 }
 2953 
 2954 void MacroAssembler::test_non_flattened_array_oop(Register oop, Register temp_reg,
 2955                                                   Label&is_non_flattened_array) {
 2956 #ifdef _LP64
 2957   test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flattened_array);
 2958 #else
 2959   load_klass(temp_reg, oop, noreg);
 2960   movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
 2961   test_non_flattened_array_layout(temp_reg, is_non_flattened_array);
 2962 #endif
 2963 }
 2964 
 2965 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
 2966 #ifdef _LP64
 2967   test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
 2968 #else
 2969   load_klass(temp_reg, oop, noreg);
 2970   movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
 2971   test_null_free_array_layout(temp_reg, is_null_free_array);
 2972 #endif
 2973 }
 2974 
 2975 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
 2976 #ifdef _LP64
 2977   test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
 2978 #else
 2979   load_klass(temp_reg, oop, noreg);
 2980   movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
 2981   test_non_null_free_array_layout(temp_reg, is_non_null_free_array);
 2982 #endif
 2983 }
 2984 
 2985 void MacroAssembler::test_flattened_array_layout(Register lh, Label& is_flattened_array) {
 2986   testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
 2987   jcc(Assembler::notZero, is_flattened_array);
 2988 }
 2989 
 2990 void MacroAssembler::test_non_flattened_array_layout(Register lh, Label& is_non_flattened_array) {
 2991   testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
 2992   jcc(Assembler::zero, is_non_flattened_array);
 2993 }
 2994 
 2995 void MacroAssembler::test_null_free_array_layout(Register lh, Label& is_null_free_array) {
 2996   testl(lh, Klass::_lh_null_free_array_bit_inplace);
 2997   jcc(Assembler::notZero, is_null_free_array);
 2998 }
 2999 
 3000 void MacroAssembler::test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array) {
 3001   testl(lh, Klass::_lh_null_free_array_bit_inplace);
 3002   jcc(Assembler::zero, is_non_null_free_array);
 3003 }
 3004 
 3005 
 3006 void MacroAssembler::os_breakpoint() {
 3007   // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
 3008   // (e.g., MSVC can't call ps() otherwise)
 3009   call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
 3010 }
 3011 
 3012 void MacroAssembler::unimplemented(const char* what) {
 3013   const char* buf = NULL;
 3014   {
 3015     ResourceMark rm;
 3016     stringStream ss;
 3017     ss.print("unimplemented: %s", what);
 3018     buf = code_string(ss.as_string());
 3019   }
 3020   stop(buf);
 3021 }
 3022 
 3023 #ifdef _LP64
 3024 #define XSTATE_BV 0x200
 3025 #endif
 3026 
 3027 void MacroAssembler::pop_CPU_state() {
 3028   pop_FPU_state();
 3029   pop_IU_state();
 3030 }
 3031 
 3032 void MacroAssembler::pop_FPU_state() {
 3033 #ifndef _LP64
 3034   frstor(Address(rsp, 0));
 3035 #else
 3036   fxrstor(Address(rsp, 0));
 3037 #endif
 3038   addptr(rsp, FPUStateSizeInWords * wordSize);
 3039 }
 3040 
 3041 void MacroAssembler::pop_IU_state() {
 3042   popa();
 3043   LP64_ONLY(addq(rsp, 8));
 3044   popf();
 3045 }
 3046 
 3047 // Save Integer and Float state
 3048 // Warning: Stack must be 16 byte aligned (64bit)
 3049 void MacroAssembler::push_CPU_state() {
 3050   push_IU_state();
 3051   push_FPU_state();
 3052 }
 3053 
 3054 void MacroAssembler::push_FPU_state() {
 3055   subptr(rsp, FPUStateSizeInWords * wordSize);
 3056 #ifndef _LP64
 3057   fnsave(Address(rsp, 0));
 3058   fwait();
 3059 #else
 3060   fxsave(Address(rsp, 0));
 3061 #endif // LP64
 3062 }
 3063 
 3064 void MacroAssembler::push_IU_state() {
 3065   // Push flags first because pusha kills them
 3066   pushf();
 3067   // Make sure rsp stays 16-byte aligned
 3068   LP64_ONLY(subq(rsp, 8));
 3069   pusha();
 3070 }
 3071 
 3072 void MacroAssembler::push_cont_fastpath() {
 3073   if (!Continuations::enabled()) return;
 3074 
 3075 #ifndef _LP64
 3076   Register rthread = rax;
 3077   Register rrealsp = rbx;
 3078   push(rthread);
 3079   push(rrealsp);
 3080 
 3081   get_thread(rthread);
 3082 
 3083   // The code below wants the original RSP.
 3084   // Move it back after the pushes above.
 3085   movptr(rrealsp, rsp);
 3086   addptr(rrealsp, 2*wordSize);
 3087 #else
 3088   Register rthread = r15_thread;
 3089   Register rrealsp = rsp;
 3090 #endif
 3091 
 3092   Label done;
 3093   cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
 3094   jccb(Assembler::belowEqual, done);
 3095   movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp);
 3096   bind(done);
 3097 
 3098 #ifndef _LP64
 3099   pop(rrealsp);
 3100   pop(rthread);
 3101 #endif
 3102 }
 3103 
 3104 void MacroAssembler::pop_cont_fastpath() {
 3105   if (!Continuations::enabled()) return;
 3106 
 3107 #ifndef _LP64
 3108   Register rthread = rax;
 3109   Register rrealsp = rbx;
 3110   push(rthread);
 3111   push(rrealsp);
 3112 
 3113   get_thread(rthread);
 3114 
 3115   // The code below wants the original RSP.
 3116   // Move it back after the pushes above.
 3117   movptr(rrealsp, rsp);
 3118   addptr(rrealsp, 2*wordSize);
 3119 #else
 3120   Register rthread = r15_thread;
 3121   Register rrealsp = rsp;
 3122 #endif
 3123 
 3124   Label done;
 3125   cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
 3126   jccb(Assembler::below, done);
 3127   movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0);
 3128   bind(done);
 3129 
 3130 #ifndef _LP64
 3131   pop(rrealsp);
 3132   pop(rthread);
 3133 #endif
 3134 }
 3135 
 3136 void MacroAssembler::inc_held_monitor_count() {
 3137 #ifndef _LP64
 3138   Register thread = rax;
 3139   push(thread);
 3140   get_thread(thread);
 3141   incrementl(Address(thread, JavaThread::held_monitor_count_offset()));
 3142   pop(thread);
 3143 #else // LP64
 3144   incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
 3145 #endif
 3146 }
 3147 
 3148 void MacroAssembler::dec_held_monitor_count() {
 3149 #ifndef _LP64
 3150   Register thread = rax;
 3151   push(thread);
 3152   get_thread(thread);
 3153   decrementl(Address(thread, JavaThread::held_monitor_count_offset()));
 3154   pop(thread);
 3155 #else // LP64
 3156   decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
 3157 #endif
 3158 }
 3159 
 3160 #ifdef ASSERT
 3161 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
 3162 #ifdef _LP64
 3163   Label no_cont;
 3164   movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
 3165   testl(cont, cont);
 3166   jcc(Assembler::zero, no_cont);
 3167   stop(name);
 3168   bind(no_cont);
 3169 #else
 3170   Unimplemented();
 3171 #endif
 3172 }
 3173 #endif
 3174 
 3175 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
 3176   if (!java_thread->is_valid()) {
 3177     java_thread = rdi;
 3178     get_thread(java_thread);
 3179   }
 3180   // we must set sp to zero to clear frame
 3181   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
 3182   // must clear fp, so that compiled frames are not confused; it is
 3183   // possible that we need it only for debugging
 3184   if (clear_fp) {
 3185     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
 3186   }
 3187   // Always clear the pc because it could have been set by make_walkable()
 3188   movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
 3189   vzeroupper();
 3190 }
 3191 
 3192 void MacroAssembler::restore_rax(Register tmp) {
 3193   if (tmp == noreg) pop(rax);
 3194   else if (tmp != rax) mov(rax, tmp);
 3195 }
 3196 
 3197 void MacroAssembler::round_to(Register reg, int modulus) {
 3198   addptr(reg, modulus - 1);
 3199   andptr(reg, -modulus);
 3200 }
 3201 
 3202 void MacroAssembler::save_rax(Register tmp) {
 3203   if (tmp == noreg) push(rax);
 3204   else if (tmp != rax) mov(tmp, rax);
 3205 }
 3206 
 3207 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
 3208   if (at_return) {
 3209     // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
 3210     // we may safely use rsp instead to perform the stack watermark check.
 3211     cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
 3212     jcc(Assembler::above, slow_path);
 3213     return;
 3214   }
 3215   testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
 3216   jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
 3217 }
 3218 
 3219 // Calls to C land
 3220 //
 3221 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
 3222 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
 3223 // has to be reset to 0. This is required to allow proper stack traversal.
 3224 void MacroAssembler::set_last_Java_frame(Register java_thread,
 3225                                          Register last_java_sp,
 3226                                          Register last_java_fp,
 3227                                          address  last_java_pc,
 3228                                          Register rscratch) {
 3229   vzeroupper();
 3230   // determine java_thread register
 3231   if (!java_thread->is_valid()) {
 3232     java_thread = rdi;
 3233     get_thread(java_thread);
 3234   }
 3235   // determine last_java_sp register
 3236   if (!last_java_sp->is_valid()) {
 3237     last_java_sp = rsp;
 3238   }
 3239   // last_java_fp is optional
 3240   if (last_java_fp->is_valid()) {
 3241     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
 3242   }
 3243   // last_java_pc is optional
 3244   if (last_java_pc != NULL) {
 3245     Address java_pc(java_thread,
 3246                     JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
 3247     lea(java_pc, InternalAddress(last_java_pc), rscratch);
 3248   }
 3249   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
 3250 }
 3251 
 3252 void MacroAssembler::shlptr(Register dst, int imm8) {
 3253   LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
 3254 }
 3255 
 3256 void MacroAssembler::shrptr(Register dst, int imm8) {
 3257   LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
 3258 }
 3259 
 3260 void MacroAssembler::sign_extend_byte(Register reg) {
 3261   if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
 3262     movsbl(reg, reg); // movsxb
 3263   } else {
 3264     shll(reg, 24);
 3265     sarl(reg, 24);
 3266   }
 3267 }
 3268 
 3269 void MacroAssembler::sign_extend_short(Register reg) {
 3270   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
 3271     movswl(reg, reg); // movsxw
 3272   } else {
 3273     shll(reg, 16);
 3274     sarl(reg, 16);
 3275   }
 3276 }
 3277 
 3278 void MacroAssembler::testl(Address dst, int32_t imm32) {
 3279   if (imm32 >= 0 && is8bit(imm32)) {
 3280     testb(dst, imm32);
 3281   } else {
 3282     Assembler::testl(dst, imm32);
 3283   }
 3284 }
 3285 
 3286 void MacroAssembler::testl(Register dst, int32_t imm32) {
 3287   if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
 3288     testb(dst, imm32);
 3289   } else {
 3290     Assembler::testl(dst, imm32);
 3291   }
 3292 }
 3293 
 3294 void MacroAssembler::testl(Register dst, AddressLiteral src) {
 3295   assert(always_reachable(src), "Address should be reachable");
 3296   testl(dst, as_Address(src));
 3297 }
 3298 
 3299 #ifdef _LP64
 3300 
 3301 void MacroAssembler::testq(Address dst, int32_t imm32) {
 3302   if (imm32 >= 0) {
 3303     testl(dst, imm32);
 3304   } else {
 3305     Assembler::testq(dst, imm32);
 3306   }
 3307 }
 3308 
 3309 void MacroAssembler::testq(Register dst, int32_t imm32) {
 3310   if (imm32 >= 0) {
 3311     testl(dst, imm32);
 3312   } else {
 3313     Assembler::testq(dst, imm32);
 3314   }
 3315 }
 3316 
 3317 #endif
 3318 
 3319 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
 3320   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3321   Assembler::pcmpeqb(dst, src);
 3322 }
 3323 
 3324 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
 3325   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3326   Assembler::pcmpeqw(dst, src);
 3327 }
 3328 
 3329 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
 3330   assert((dst->encoding() < 16),"XMM register should be 0-15");
 3331   Assembler::pcmpestri(dst, src, imm8);
 3332 }
 3333 
 3334 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
 3335   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
 3336   Assembler::pcmpestri(dst, src, imm8);
 3337 }
 3338 
 3339 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
 3340   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3341   Assembler::pmovzxbw(dst, src);
 3342 }
 3343 
 3344 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
 3345   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3346   Assembler::pmovzxbw(dst, src);
 3347 }
 3348 
 3349 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
 3350   assert((src->encoding() < 16),"XMM register should be 0-15");
 3351   Assembler::pmovmskb(dst, src);
 3352 }
 3353 
 3354 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
 3355   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
 3356   Assembler::ptest(dst, src);
 3357 }
 3358 
 3359 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
 3360   assert(rscratch != noreg || always_reachable(src), "missing");
 3361 
 3362   if (reachable(src)) {
 3363     Assembler::sqrtss(dst, as_Address(src));
 3364   } else {
 3365     lea(rscratch, src);
 3366     Assembler::sqrtss(dst, Address(rscratch, 0));
 3367   }
 3368 }
 3369 
 3370 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
 3371   assert(rscratch != noreg || always_reachable(src), "missing");
 3372 
 3373   if (reachable(src)) {
 3374     Assembler::subsd(dst, as_Address(src));
 3375   } else {
 3376     lea(rscratch, src);
 3377     Assembler::subsd(dst, Address(rscratch, 0));
 3378   }
 3379 }
 3380 
 3381 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
 3382   assert(rscratch != noreg || always_reachable(src), "missing");
 3383 
 3384   if (reachable(src)) {
 3385     Assembler::roundsd(dst, as_Address(src), rmode);
 3386   } else {
 3387     lea(rscratch, src);
 3388     Assembler::roundsd(dst, Address(rscratch, 0), rmode);
 3389   }
 3390 }
 3391 
 3392 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
 3393   assert(rscratch != noreg || always_reachable(src), "missing");
 3394 
 3395   if (reachable(src)) {
 3396     Assembler::subss(dst, as_Address(src));
 3397   } else {
 3398     lea(rscratch, src);
 3399     Assembler::subss(dst, Address(rscratch, 0));
 3400   }
 3401 }
 3402 
 3403 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
 3404   assert(rscratch != noreg || always_reachable(src), "missing");
 3405 
 3406   if (reachable(src)) {
 3407     Assembler::ucomisd(dst, as_Address(src));
 3408   } else {
 3409     lea(rscratch, src);
 3410     Assembler::ucomisd(dst, Address(rscratch, 0));
 3411   }
 3412 }
 3413 
 3414 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
 3415   assert(rscratch != noreg || always_reachable(src), "missing");
 3416 
 3417   if (reachable(src)) {
 3418     Assembler::ucomiss(dst, as_Address(src));
 3419   } else {
 3420     lea(rscratch, src);
 3421     Assembler::ucomiss(dst, Address(rscratch, 0));
 3422   }
 3423 }
 3424 
 3425 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
 3426   assert(rscratch != noreg || always_reachable(src), "missing");
 3427 
 3428   // Used in sign-bit flipping with aligned address.
 3429   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
 3430   if (reachable(src)) {
 3431     Assembler::xorpd(dst, as_Address(src));
 3432   } else {
 3433     lea(rscratch, src);
 3434     Assembler::xorpd(dst, Address(rscratch, 0));
 3435   }
 3436 }
 3437 
 3438 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
 3439   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
 3440     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
 3441   }
 3442   else {
 3443     Assembler::xorpd(dst, src);
 3444   }
 3445 }
 3446 
 3447 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
 3448   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
 3449     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
 3450   } else {
 3451     Assembler::xorps(dst, src);
 3452   }
 3453 }
 3454 
 3455 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
 3456   assert(rscratch != noreg || always_reachable(src), "missing");
 3457 
 3458   // Used in sign-bit flipping with aligned address.
 3459   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
 3460   if (reachable(src)) {
 3461     Assembler::xorps(dst, as_Address(src));
 3462   } else {
 3463     lea(rscratch, src);
 3464     Assembler::xorps(dst, Address(rscratch, 0));
 3465   }
 3466 }
 3467 
 3468 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
 3469   assert(rscratch != noreg || always_reachable(src), "missing");
 3470 
 3471   // Used in sign-bit flipping with aligned address.
 3472   bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
 3473   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
 3474   if (reachable(src)) {
 3475     Assembler::pshufb(dst, as_Address(src));
 3476   } else {
 3477     lea(rscratch, src);
 3478     Assembler::pshufb(dst, Address(rscratch, 0));
 3479   }
 3480 }
 3481 
 3482 // AVX 3-operands instructions
 3483 
 3484 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
 3485   assert(rscratch != noreg || always_reachable(src), "missing");
 3486 
 3487   if (reachable(src)) {
 3488     vaddsd(dst, nds, as_Address(src));
 3489   } else {
 3490     lea(rscratch, src);
 3491     vaddsd(dst, nds, Address(rscratch, 0));
 3492   }
 3493 }
 3494 
 3495 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
 3496   assert(rscratch != noreg || always_reachable(src), "missing");
 3497 
 3498   if (reachable(src)) {
 3499     vaddss(dst, nds, as_Address(src));
 3500   } else {
 3501     lea(rscratch, src);
 3502     vaddss(dst, nds, Address(rscratch, 0));
 3503   }
 3504 }
 3505 
 3506 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
 3507   assert(UseAVX > 0, "requires some form of AVX");
 3508   assert(rscratch != noreg || always_reachable(src), "missing");
 3509 
 3510   if (reachable(src)) {
 3511     Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
 3512   } else {
 3513     lea(rscratch, src);
 3514     Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
 3515   }
 3516 }
 3517 
 3518 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
 3519   assert(UseAVX > 0, "requires some form of AVX");
 3520   assert(rscratch != noreg || always_reachable(src), "missing");
 3521 
 3522   if (reachable(src)) {
 3523     Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
 3524   } else {
 3525     lea(rscratch, src);
 3526     Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
 3527   }
 3528 }
 3529 
 3530 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
 3531   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
 3532   assert(rscratch != noreg || always_reachable(negate_field), "missing");
 3533 
 3534   vandps(dst, nds, negate_field, vector_len, rscratch);
 3535 }
 3536 
 3537 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
 3538   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
 3539   assert(rscratch != noreg || always_reachable(negate_field), "missing");
 3540 
 3541   vandpd(dst, nds, negate_field, vector_len, rscratch);
 3542 }
 3543 
 3544 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 3545   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3546   Assembler::vpaddb(dst, nds, src, vector_len);
 3547 }
 3548 
 3549 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 3550   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3551   Assembler::vpaddb(dst, nds, src, vector_len);
 3552 }
 3553 
 3554 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 3555   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3556   Assembler::vpaddw(dst, nds, src, vector_len);
 3557 }
 3558 
 3559 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 3560   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3561   Assembler::vpaddw(dst, nds, src, vector_len);
 3562 }
 3563 
 3564 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
 3565   assert(rscratch != noreg || always_reachable(src), "missing");
 3566 
 3567   if (reachable(src)) {
 3568     Assembler::vpand(dst, nds, as_Address(src), vector_len);
 3569   } else {
 3570     lea(rscratch, src);
 3571     Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
 3572   }
 3573 }
 3574 
 3575 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
 3576   assert(rscratch != noreg || always_reachable(src), "missing");
 3577 
 3578   if (reachable(src)) {
 3579     Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
 3580   } else {
 3581     lea(rscratch, src);
 3582     Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
 3583   }
 3584 }
 3585 
 3586 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
 3587   assert(rscratch != noreg || always_reachable(src), "missing");
 3588 
 3589   if (reachable(src)) {
 3590     Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
 3591   } else {
 3592     lea(rscratch, src);
 3593     Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
 3594   }
 3595 }
 3596 
 3597 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
 3598   assert(rscratch != noreg || always_reachable(src), "missing");
 3599 
 3600   if (reachable(src)) {
 3601     Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
 3602   } else {
 3603     lea(rscratch, src);
 3604     Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
 3605   }
 3606 }
 3607 
 3608 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
 3609   assert(rscratch != noreg || always_reachable(src), "missing");
 3610 
 3611   if (reachable(src)) {
 3612     Assembler::vbroadcastss(dst, as_Address(src), vector_len);
 3613   } else {
 3614     lea(rscratch, src);
 3615     Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
 3616   }
 3617 }
 3618 
 3619 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 3620   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3621   Assembler::vpcmpeqb(dst, nds, src, vector_len);
 3622 }
 3623 
 3624 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 3625   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3626   Assembler::vpcmpeqw(dst, nds, src, vector_len);
 3627 }
 3628 
 3629 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
 3630   assert(rscratch != noreg || always_reachable(src), "missing");
 3631 
 3632   if (reachable(src)) {
 3633     Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
 3634   } else {
 3635     lea(rscratch, src);
 3636     Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
 3637   }
 3638 }
 3639 
 3640 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
 3641                              int comparison, bool is_signed, int vector_len, Register rscratch) {
 3642   assert(rscratch != noreg || always_reachable(src), "missing");
 3643 
 3644   if (reachable(src)) {
 3645     Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
 3646   } else {
 3647     lea(rscratch, src);
 3648     Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
 3649   }
 3650 }
 3651 
 3652 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
 3653                              int comparison, bool is_signed, int vector_len, Register rscratch) {
 3654   assert(rscratch != noreg || always_reachable(src), "missing");
 3655 
 3656   if (reachable(src)) {
 3657     Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
 3658   } else {
 3659     lea(rscratch, src);
 3660     Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
 3661   }
 3662 }
 3663 
 3664 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
 3665                              int comparison, bool is_signed, int vector_len, Register rscratch) {
 3666   assert(rscratch != noreg || always_reachable(src), "missing");
 3667 
 3668   if (reachable(src)) {
 3669     Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
 3670   } else {
 3671     lea(rscratch, src);
 3672     Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
 3673   }
 3674 }
 3675 
 3676 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
 3677                              int comparison, bool is_signed, int vector_len, Register rscratch) {
 3678   assert(rscratch != noreg || always_reachable(src), "missing");
 3679 
 3680   if (reachable(src)) {
 3681     Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
 3682   } else {
 3683     lea(rscratch, src);
 3684     Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
 3685   }
 3686 }
 3687 
 3688 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
 3689   if (width == Assembler::Q) {
 3690     Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
 3691   } else {
 3692     Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
 3693   }
 3694 }
 3695 
 3696 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
 3697   int eq_cond_enc = 0x29;
 3698   int gt_cond_enc = 0x37;
 3699   if (width != Assembler::Q) {
 3700     eq_cond_enc = 0x74 + width;
 3701     gt_cond_enc = 0x64 + width;
 3702   }
 3703   switch (cond) {
 3704   case eq:
 3705     vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
 3706     break;
 3707   case neq:
 3708     vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
 3709     vallones(xtmp, vector_len);
 3710     vpxor(dst, xtmp, dst, vector_len);
 3711     break;
 3712   case le:
 3713     vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
 3714     vallones(xtmp, vector_len);
 3715     vpxor(dst, xtmp, dst, vector_len);
 3716     break;
 3717   case nlt:
 3718     vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
 3719     vallones(xtmp, vector_len);
 3720     vpxor(dst, xtmp, dst, vector_len);
 3721     break;
 3722   case lt:
 3723     vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
 3724     break;
 3725   case nle:
 3726     vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
 3727     break;
 3728   default:
 3729     assert(false, "Should not reach here");
 3730   }
 3731 }
 3732 
 3733 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
 3734   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3735   Assembler::vpmovzxbw(dst, src, vector_len);
 3736 }
 3737 
 3738 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
 3739   assert((src->encoding() < 16),"XMM register should be 0-15");
 3740   Assembler::vpmovmskb(dst, src, vector_len);
 3741 }
 3742 
 3743 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 3744   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3745   Assembler::vpmullw(dst, nds, src, vector_len);
 3746 }
 3747 
 3748 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 3749   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3750   Assembler::vpmullw(dst, nds, src, vector_len);
 3751 }
 3752 
 3753 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
 3754   assert((UseAVX > 0), "AVX support is needed");
 3755   assert(rscratch != noreg || always_reachable(src), "missing");
 3756 
 3757   if (reachable(src)) {
 3758     Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
 3759   } else {
 3760     lea(rscratch, src);
 3761     Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
 3762   }
 3763 }
 3764 
 3765 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 3766   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3767   Assembler::vpsubb(dst, nds, src, vector_len);
 3768 }
 3769 
 3770 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 3771   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3772   Assembler::vpsubb(dst, nds, src, vector_len);
 3773 }
 3774 
 3775 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 3776   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3777   Assembler::vpsubw(dst, nds, src, vector_len);
 3778 }
 3779 
 3780 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 3781   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3782   Assembler::vpsubw(dst, nds, src, vector_len);
 3783 }
 3784 
 3785 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
 3786   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3787   Assembler::vpsraw(dst, nds, shift, vector_len);
 3788 }
 3789 
 3790 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
 3791   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3792   Assembler::vpsraw(dst, nds, shift, vector_len);
 3793 }
 3794 
 3795 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
 3796   assert(UseAVX > 2,"");
 3797   if (!VM_Version::supports_avx512vl() && vector_len < 2) {
 3798      vector_len = 2;
 3799   }
 3800   Assembler::evpsraq(dst, nds, shift, vector_len);
 3801 }
 3802 
 3803 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
 3804   assert(UseAVX > 2,"");
 3805   if (!VM_Version::supports_avx512vl() && vector_len < 2) {
 3806      vector_len = 2;
 3807   }
 3808   Assembler::evpsraq(dst, nds, shift, vector_len);
 3809 }
 3810 
 3811 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
 3812   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3813   Assembler::vpsrlw(dst, nds, shift, vector_len);
 3814 }
 3815 
 3816 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
 3817   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3818   Assembler::vpsrlw(dst, nds, shift, vector_len);
 3819 }
 3820 
 3821 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
 3822   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3823   Assembler::vpsllw(dst, nds, shift, vector_len);
 3824 }
 3825 
 3826 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
 3827   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3828   Assembler::vpsllw(dst, nds, shift, vector_len);
 3829 }
 3830 
 3831 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
 3832   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
 3833   Assembler::vptest(dst, src);
 3834 }
 3835 
 3836 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
 3837   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3838   Assembler::punpcklbw(dst, src);
 3839 }
 3840 
 3841 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
 3842   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
 3843   Assembler::pshufd(dst, src, mode);
 3844 }
 3845 
 3846 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
 3847   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
 3848   Assembler::pshuflw(dst, src, mode);
 3849 }
 3850 
 3851 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
 3852   assert(rscratch != noreg || always_reachable(src), "missing");
 3853 
 3854   if (reachable(src)) {
 3855     vandpd(dst, nds, as_Address(src), vector_len);
 3856   } else {
 3857     lea(rscratch, src);
 3858     vandpd(dst, nds, Address(rscratch, 0), vector_len);
 3859   }
 3860 }
 3861 
 3862 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
 3863   assert(rscratch != noreg || always_reachable(src), "missing");
 3864 
 3865   if (reachable(src)) {
 3866     vandps(dst, nds, as_Address(src), vector_len);
 3867   } else {
 3868     lea(rscratch, src);
 3869     vandps(dst, nds, Address(rscratch, 0), vector_len);
 3870   }
 3871 }
 3872 
 3873 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
 3874                             bool merge, int vector_len, Register rscratch) {
 3875   assert(rscratch != noreg || always_reachable(src), "missing");
 3876 
 3877   if (reachable(src)) {
 3878     Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
 3879   } else {
 3880     lea(rscratch, src);
 3881     Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
 3882   }
 3883 }
 3884 
 3885 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
 3886   assert(rscratch != noreg || always_reachable(src), "missing");
 3887 
 3888   if (reachable(src)) {
 3889     vdivsd(dst, nds, as_Address(src));
 3890   } else {
 3891     lea(rscratch, src);
 3892     vdivsd(dst, nds, Address(rscratch, 0));
 3893   }
 3894 }
 3895 
 3896 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
 3897   assert(rscratch != noreg || always_reachable(src), "missing");
 3898 
 3899   if (reachable(src)) {
 3900     vdivss(dst, nds, as_Address(src));
 3901   } else {
 3902     lea(rscratch, src);
 3903     vdivss(dst, nds, Address(rscratch, 0));
 3904   }
 3905 }
 3906 
 3907 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
 3908   assert(rscratch != noreg || always_reachable(src), "missing");
 3909 
 3910   if (reachable(src)) {
 3911     vmulsd(dst, nds, as_Address(src));
 3912   } else {
 3913     lea(rscratch, src);
 3914     vmulsd(dst, nds, Address(rscratch, 0));
 3915   }
 3916 }
 3917 
 3918 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
 3919   assert(rscratch != noreg || always_reachable(src), "missing");
 3920 
 3921   if (reachable(src)) {
 3922     vmulss(dst, nds, as_Address(src));
 3923   } else {
 3924     lea(rscratch, src);
 3925     vmulss(dst, nds, Address(rscratch, 0));
 3926   }
 3927 }
 3928 
 3929 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
 3930   assert(rscratch != noreg || always_reachable(src), "missing");
 3931 
 3932   if (reachable(src)) {
 3933     vsubsd(dst, nds, as_Address(src));
 3934   } else {
 3935     lea(rscratch, src);
 3936     vsubsd(dst, nds, Address(rscratch, 0));
 3937   }
 3938 }
 3939 
 3940 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
 3941   assert(rscratch != noreg || always_reachable(src), "missing");
 3942 
 3943   if (reachable(src)) {
 3944     vsubss(dst, nds, as_Address(src));
 3945   } else {
 3946     lea(rscratch, src);
 3947     vsubss(dst, nds, Address(rscratch, 0));
 3948   }
 3949 }
 3950 
 3951 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
 3952   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
 3953   assert(rscratch != noreg || always_reachable(src), "missing");
 3954 
 3955   vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
 3956 }
 3957 
 3958 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
 3959   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
 3960   assert(rscratch != noreg || always_reachable(src), "missing");
 3961 
 3962   vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
 3963 }
 3964 
 3965 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
 3966   assert(rscratch != noreg || always_reachable(src), "missing");
 3967 
 3968   if (reachable(src)) {
 3969     vxorpd(dst, nds, as_Address(src), vector_len);
 3970   } else {
 3971     lea(rscratch, src);
 3972     vxorpd(dst, nds, Address(rscratch, 0), vector_len);
 3973   }
 3974 }
 3975 
 3976 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
 3977   assert(rscratch != noreg || always_reachable(src), "missing");
 3978 
 3979   if (reachable(src)) {
 3980     vxorps(dst, nds, as_Address(src), vector_len);
 3981   } else {
 3982     lea(rscratch, src);
 3983     vxorps(dst, nds, Address(rscratch, 0), vector_len);
 3984   }
 3985 }
 3986 
 3987 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
 3988   assert(rscratch != noreg || always_reachable(src), "missing");
 3989 
 3990   if (UseAVX > 1 || (vector_len < 1)) {
 3991     if (reachable(src)) {
 3992       Assembler::vpxor(dst, nds, as_Address(src), vector_len);
 3993     } else {
 3994       lea(rscratch, src);
 3995       Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
 3996     }
 3997   } else {
 3998     MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
 3999   }
 4000 }
 4001 
 4002 void MacroAssembler::vpermd(XMMRegister dst,  XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
 4003   assert(rscratch != noreg || always_reachable(src), "missing");
 4004 
 4005   if (reachable(src)) {
 4006     Assembler::vpermd(dst, nds, as_Address(src), vector_len);
 4007   } else {
 4008     lea(rscratch, src);
 4009     Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
 4010   }
 4011 }
 4012 
 4013 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
 4014   const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
 4015   STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
 4016   // The inverted mask is sign-extended
 4017   andptr(possibly_jweak, inverted_jweak_mask);
 4018 }
 4019 
 4020 void MacroAssembler::resolve_jobject(Register value,
 4021                                      Register thread,
 4022                                      Register tmp) {
 4023   assert_different_registers(value, thread, tmp);
 4024   Label done, not_weak;
 4025   testptr(value, value);
 4026   jcc(Assembler::zero, done);                // Use NULL as-is.
 4027   testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
 4028   jcc(Assembler::zero, not_weak);
 4029   // Resolve jweak.
 4030   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
 4031                  value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
 4032   verify_oop(value);
 4033   jmp(done);
 4034   bind(not_weak);
 4035   // Resolve (untagged) jobject.
 4036   access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
 4037   verify_oop(value);
 4038   bind(done);
 4039 }
 4040 
 4041 void MacroAssembler::subptr(Register dst, int32_t imm32) {
 4042   LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
 4043 }
 4044 
 4045 // Force generation of a 4 byte immediate value even if it fits into 8bit
 4046 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
 4047   LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
 4048 }
 4049 
 4050 void MacroAssembler::subptr(Register dst, Register src) {
 4051   LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
 4052 }
 4053 
 4054 // C++ bool manipulation
 4055 void MacroAssembler::testbool(Register dst) {
 4056   if(sizeof(bool) == 1)
 4057     testb(dst, 0xff);
 4058   else if(sizeof(bool) == 2) {
 4059     // testw implementation needed for two byte bools
 4060     ShouldNotReachHere();
 4061   } else if(sizeof(bool) == 4)
 4062     testl(dst, dst);
 4063   else
 4064     // unsupported
 4065     ShouldNotReachHere();
 4066 }
 4067 
 4068 void MacroAssembler::testptr(Register dst, Register src) {
 4069   LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
 4070 }
 4071 
 4072 // Object / value buffer allocation...
 4073 //
 4074 // Kills klass and rsi on LP64
 4075 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
 4076                                        Register t1, Register t2,
 4077                                        bool clear_fields, Label& alloc_failed)
 4078 {
 4079   Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
 4080   Register layout_size = t1;
 4081   assert(new_obj == rax, "needs to be rax");
 4082   assert_different_registers(klass, new_obj, t1, t2);
 4083 
 4084   // get instance_size in InstanceKlass (scaled to a count of bytes)
 4085   movl(layout_size, Address(klass, Klass::layout_helper_offset()));
 4086   // test to see if it has a finalizer or is malformed in some way
 4087   testl(layout_size, Klass::_lh_instance_slow_path_bit);
 4088   jcc(Assembler::notZero, slow_case_no_pop);
 4089 
 4090   // Allocate the instance:
 4091   //  If TLAB is enabled:
 4092   //    Try to allocate in the TLAB.
 4093   //    If fails, go to the slow path.
 4094   //  Else If inline contiguous allocations are enabled:
 4095   //    Try to allocate in eden.
 4096   //    If fails due to heap end, go to slow path.
 4097   //
 4098   //  If TLAB is enabled OR inline contiguous is enabled:
 4099   //    Initialize the allocation.
 4100   //    Exit.
 4101   //
 4102   //  Go to slow path.
 4103 
 4104   push(klass);
 4105   const Register thread = LP64_ONLY(r15_thread) NOT_LP64(klass);
 4106 #ifndef _LP64
 4107   if (UseTLAB) {
 4108     get_thread(thread);
 4109   }
 4110 #endif // _LP64
 4111 
 4112   if (UseTLAB) {
 4113     tlab_allocate(thread, new_obj, layout_size, 0, klass, t2, slow_case);
 4114     if (ZeroTLAB || (!clear_fields)) {
 4115       // the fields have been already cleared
 4116       jmp(initialize_header);
 4117     } else {
 4118       // initialize both the header and fields
 4119       jmp(initialize_object);
 4120     }
 4121   } else {
 4122     jmp(slow_case);
 4123   }
 4124 
 4125   // If UseTLAB is true, the object is created above and there is an initialize need.
 4126   // Otherwise, skip and go to the slow path.
 4127   if (UseTLAB) {
 4128     if (clear_fields) {
 4129       // The object is initialized before the header.  If the object size is
 4130       // zero, go directly to the header initialization.
 4131       bind(initialize_object);
 4132       decrement(layout_size, sizeof(oopDesc));
 4133       jcc(Assembler::zero, initialize_header);
 4134 
 4135       // Initialize topmost object field, divide size by 8, check if odd and
 4136       // test if zero.
 4137       Register zero = klass;
 4138       xorl(zero, zero);    // use zero reg to clear memory (shorter code)
 4139       shrl(layout_size, LogBytesPerLong); // divide by 2*oopSize and set carry flag if odd
 4140 
 4141   #ifdef ASSERT
 4142       // make sure instance_size was multiple of 8
 4143       Label L;
 4144       // Ignore partial flag stall after shrl() since it is debug VM
 4145       jcc(Assembler::carryClear, L);
 4146       stop("object size is not multiple of 2 - adjust this code");
 4147       bind(L);
 4148       // must be > 0, no extra check needed here
 4149   #endif
 4150 
 4151       // initialize remaining object fields: instance_size was a multiple of 8
 4152       {
 4153         Label loop;
 4154         bind(loop);
 4155         movptr(Address(new_obj, layout_size, Address::times_8, sizeof(oopDesc) - 1*oopSize), zero);
 4156         NOT_LP64(movptr(Address(new_obj, layout_size, Address::times_8, sizeof(oopDesc) - 2*oopSize), zero));
 4157         decrement(layout_size);
 4158         jcc(Assembler::notZero, loop);
 4159       }
 4160     } // clear_fields
 4161 
 4162     // initialize object header only.
 4163     bind(initialize_header);
 4164     pop(klass);
 4165     Register mark_word = t2;
 4166     movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
 4167     movptr(Address(new_obj, oopDesc::mark_offset_in_bytes ()), mark_word);
 4168 #ifdef _LP64
 4169     xorl(rsi, rsi);                 // use zero reg to clear memory (shorter code)
 4170     store_klass_gap(new_obj, rsi);  // zero klass gap for compressed oops
 4171 #endif
 4172     movptr(t2, klass);         // preserve klass
 4173     store_klass(new_obj, t2, rscratch1);  // src klass reg is potentially compressed
 4174 
 4175     jmp(done);
 4176   }
 4177 
 4178   bind(slow_case);
 4179   pop(klass);
 4180   bind(slow_case_no_pop);
 4181   jmp(alloc_failed);
 4182 
 4183   bind(done);
 4184 }
 4185 
 4186 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
 4187 void MacroAssembler::tlab_allocate(Register thread, Register obj,
 4188                                    Register var_size_in_bytes,
 4189                                    int con_size_in_bytes,
 4190                                    Register t1,
 4191                                    Register t2,
 4192                                    Label& slow_case) {
 4193   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 4194   bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
 4195 }
 4196 
 4197 RegSet MacroAssembler::call_clobbered_gp_registers() {
 4198   RegSet regs;
 4199 #ifdef _LP64
 4200   regs += RegSet::of(rax, rcx, rdx);
 4201 #ifndef WINDOWS
 4202   regs += RegSet::of(rsi, rdi);
 4203 #endif
 4204   regs += RegSet::range(r8, r11);
 4205 #else
 4206   regs += RegSet::of(rax, rcx, rdx);
 4207 #endif
 4208   return regs;
 4209 }
 4210 
 4211 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
 4212   int num_xmm_registers = XMMRegister::available_xmm_registers();
 4213 #if defined(WINDOWS) && defined(_LP64)
 4214   XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
 4215   if (num_xmm_registers > 16) {
 4216      result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
 4217   }
 4218   return result;
 4219 #else
 4220   return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
 4221 #endif
 4222 }
 4223 
 4224 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
 4225 
 4226 #ifndef _LP64
 4227 static bool use_x87_registers() { return UseSSE < 2; }
 4228 #endif
 4229 static bool use_xmm_registers() { return UseSSE >= 1; }
 4230 
 4231 // C1 only ever uses the first double/float of the XMM register.
 4232 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
 4233 
 4234 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
 4235   if (UseSSE == 1) {
 4236     masm->movflt(Address(rsp, offset), reg);
 4237   } else {
 4238     masm->movdbl(Address(rsp, offset), reg);
 4239   }
 4240 }
 4241 
 4242 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
 4243   if (UseSSE == 1) {
 4244     masm->movflt(reg, Address(rsp, offset));
 4245   } else {
 4246     masm->movdbl(reg, Address(rsp, offset));
 4247   }
 4248 }
 4249 
 4250 int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers, bool save_fpu,
 4251                            int& gp_area_size, int& fp_area_size, int& xmm_area_size) {
 4252 
 4253   gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
 4254                          StackAlignmentInBytes);
 4255 #ifdef _LP64
 4256   fp_area_size = 0;
 4257 #else
 4258   fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
 4259 #endif
 4260   xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
 4261 
 4262   return gp_area_size + fp_area_size + xmm_area_size;
 4263 }
 4264 
 4265 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
 4266   block_comment("push_call_clobbered_registers start");
 4267   // Regular registers
 4268   RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
 4269 
 4270   int gp_area_size;
 4271   int fp_area_size;
 4272   int xmm_area_size;
 4273   int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
 4274                                                gp_area_size, fp_area_size, xmm_area_size);
 4275   subptr(rsp, total_save_size);
 4276 
 4277   push_set(gp_registers_to_push, 0);
 4278 
 4279 #ifndef _LP64
 4280   if (save_fpu && use_x87_registers()) {
 4281     fnsave(Address(rsp, gp_area_size));
 4282     fwait();
 4283   }
 4284 #endif
 4285   if (save_fpu && use_xmm_registers()) {
 4286     push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
 4287   }
 4288 
 4289   block_comment("push_call_clobbered_registers end");
 4290 }
 4291 
 4292 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
 4293   block_comment("pop_call_clobbered_registers start");
 4294 
 4295   RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
 4296 
 4297   int gp_area_size;
 4298   int fp_area_size;
 4299   int xmm_area_size;
 4300   int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
 4301                                                gp_area_size, fp_area_size, xmm_area_size);
 4302 
 4303   if (restore_fpu && use_xmm_registers()) {
 4304     pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
 4305   }
 4306 #ifndef _LP64
 4307   if (restore_fpu && use_x87_registers()) {
 4308     frstor(Address(rsp, gp_area_size));
 4309   }
 4310 #endif
 4311 
 4312   pop_set(gp_registers_to_pop, 0);
 4313 
 4314   addptr(rsp, total_save_size);
 4315 
 4316   vzeroupper();
 4317 
 4318   block_comment("pop_call_clobbered_registers end");
 4319 }
 4320 
 4321 void MacroAssembler::push_set(XMMRegSet set, int offset) {
 4322   assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
 4323   int spill_offset = offset;
 4324 
 4325   for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
 4326     save_xmm_register(this, spill_offset, *it);
 4327     spill_offset += xmm_save_size();
 4328   }
 4329 }
 4330 
 4331 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
 4332   int restore_size = set.size() * xmm_save_size();
 4333   assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
 4334 
 4335   int restore_offset = offset + restore_size - xmm_save_size();
 4336 
 4337   for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
 4338     restore_xmm_register(this, restore_offset, *it);
 4339     restore_offset -= xmm_save_size();
 4340   }
 4341 }
 4342 
 4343 void MacroAssembler::push_set(RegSet set, int offset) {
 4344   int spill_offset;
 4345   if (offset == -1) {
 4346     int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
 4347     int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
 4348     subptr(rsp, aligned_size);
 4349     spill_offset = 0;
 4350   } else {
 4351     spill_offset = offset;
 4352   }
 4353 
 4354   for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
 4355     movptr(Address(rsp, spill_offset), *it);
 4356     spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
 4357   }
 4358 }
 4359 
 4360 void MacroAssembler::pop_set(RegSet set, int offset) {
 4361 
 4362   int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
 4363   int restore_size = set.size() * gp_reg_size;
 4364   int aligned_size = align_up(restore_size, StackAlignmentInBytes);
 4365 
 4366   int restore_offset;
 4367   if (offset == -1) {
 4368     restore_offset = restore_size - gp_reg_size;
 4369   } else {
 4370     restore_offset = offset + restore_size - gp_reg_size;
 4371   }
 4372   for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
 4373     movptr(*it, Address(rsp, restore_offset));
 4374     restore_offset -= gp_reg_size;
 4375   }
 4376 
 4377   if (offset == -1) {
 4378     addptr(rsp, aligned_size);
 4379   }
 4380 }
 4381 
 4382 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
 4383 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
 4384   assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
 4385   assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
 4386   Label done;
 4387 
 4388   testptr(length_in_bytes, length_in_bytes);
 4389   jcc(Assembler::zero, done);
 4390 
 4391   // initialize topmost word, divide index by 2, check if odd and test if zero
 4392   // note: for the remaining code to work, index must be a multiple of BytesPerWord
 4393 #ifdef ASSERT
 4394   {
 4395     Label L;
 4396     testptr(length_in_bytes, BytesPerWord - 1);
 4397     jcc(Assembler::zero, L);
 4398     stop("length must be a multiple of BytesPerWord");
 4399     bind(L);
 4400   }
 4401 #endif
 4402   Register index = length_in_bytes;
 4403   xorptr(temp, temp);    // use _zero reg to clear memory (shorter code)
 4404   if (UseIncDec) {
 4405     shrptr(index, 3);  // divide by 8/16 and set carry flag if bit 2 was set
 4406   } else {
 4407     shrptr(index, 2);  // use 2 instructions to avoid partial flag stall
 4408     shrptr(index, 1);
 4409   }
 4410 #ifndef _LP64
 4411   // index could have not been a multiple of 8 (i.e., bit 2 was set)
 4412   {
 4413     Label even;
 4414     // note: if index was a multiple of 8, then it cannot
 4415     //       be 0 now otherwise it must have been 0 before
 4416     //       => if it is even, we don't need to check for 0 again
 4417     jcc(Assembler::carryClear, even);
 4418     // clear topmost word (no jump would be needed if conditional assignment worked here)
 4419     movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
 4420     // index could be 0 now, must check again
 4421     jcc(Assembler::zero, done);
 4422     bind(even);
 4423   }
 4424 #endif // !_LP64
 4425   // initialize remaining object fields: index is a multiple of 2 now
 4426   {
 4427     Label loop;
 4428     bind(loop);
 4429     movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
 4430     NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
 4431     decrement(index);
 4432     jcc(Assembler::notZero, loop);
 4433   }
 4434 
 4435   bind(done);
 4436 }
 4437 
 4438 void MacroAssembler::get_inline_type_field_klass(Register klass, Register index, Register inline_klass) {
 4439   movptr(inline_klass, Address(klass, InstanceKlass::inline_type_field_klasses_offset()));
 4440 #ifdef ASSERT
 4441   {
 4442     Label done;
 4443     cmpptr(inline_klass, 0);
 4444     jcc(Assembler::notEqual, done);
 4445     stop("get_inline_type_field_klass contains no inline klass");
 4446     bind(done);
 4447   }
 4448 #endif
 4449   movptr(inline_klass, Address(inline_klass, index, Address::times_ptr));
 4450 }
 4451 
 4452 void MacroAssembler::get_default_value_oop(Register inline_klass, Register temp_reg, Register obj) {
 4453 #ifdef ASSERT
 4454   {
 4455     Label done_check;
 4456     test_klass_is_inline_type(inline_klass, temp_reg, done_check);
 4457     stop("get_default_value_oop from non inline type klass");
 4458     bind(done_check);
 4459   }
 4460 #endif
 4461   Register offset = temp_reg;
 4462   // Getting the offset of the pre-allocated default value
 4463   movptr(offset, Address(inline_klass, in_bytes(InstanceKlass::adr_inlineklass_fixed_block_offset())));
 4464   movl(offset, Address(offset, in_bytes(InlineKlass::default_value_offset_offset())));
 4465 
 4466   // Getting the mirror
 4467   movptr(obj, Address(inline_klass, in_bytes(Klass::java_mirror_offset())));
 4468   resolve_oop_handle(obj, inline_klass);
 4469 
 4470   // Getting the pre-allocated default value from the mirror
 4471   Address field(obj, offset, Address::times_1);
 4472   load_heap_oop(obj, field);
 4473 }
 4474 
 4475 void MacroAssembler::get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj) {
 4476 #ifdef ASSERT
 4477   {
 4478     Label done_check;
 4479     test_klass_is_empty_inline_type(inline_klass, temp_reg, done_check);
 4480     stop("get_empty_value from non-empty inline klass");
 4481     bind(done_check);
 4482   }
 4483 #endif
 4484   get_default_value_oop(inline_klass, temp_reg, obj);
 4485 }
 4486 
 4487 
 4488 // Look up the method for a megamorphic invokeinterface call.
 4489 // The target method is determined by <intf_klass, itable_index>.
 4490 // The receiver klass is in recv_klass.
 4491 // On success, the result will be in method_result, and execution falls through.
 4492 // On failure, execution transfers to the given label.
 4493 void MacroAssembler::lookup_interface_method(Register recv_klass,
 4494                                              Register intf_klass,
 4495                                              RegisterOrConstant itable_index,
 4496                                              Register method_result,
 4497                                              Register scan_temp,
 4498                                              Label& L_no_such_interface,
 4499                                              bool return_method) {
 4500   assert_different_registers(recv_klass, intf_klass, scan_temp);
 4501   assert_different_registers(method_result, intf_klass, scan_temp);
 4502   assert(recv_klass != method_result || !return_method,
 4503          "recv_klass can be destroyed when method isn't needed");
 4504 
 4505   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
 4506          "caller must use same register for non-constant itable index as for method");
 4507 
 4508   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
 4509   int vtable_base = in_bytes(Klass::vtable_start_offset());
 4510   int itentry_off = itableMethodEntry::method_offset_in_bytes();
 4511   int scan_step   = itableOffsetEntry::size() * wordSize;
 4512   int vte_size    = vtableEntry::size_in_bytes();
 4513   Address::ScaleFactor times_vte_scale = Address::times_ptr;
 4514   assert(vte_size == wordSize, "else adjust times_vte_scale");
 4515 
 4516   movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
 4517 
 4518   // %%% Could store the aligned, prescaled offset in the klassoop.
 4519   lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
 4520 
 4521   if (return_method) {
 4522     // Adjust recv_klass by scaled itable_index, so we can free itable_index.
 4523     assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
 4524     lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
 4525   }
 4526 
 4527   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
 4528   //   if (scan->interface() == intf) {
 4529   //     result = (klass + scan->offset() + itable_index);
 4530   //   }
 4531   // }
 4532   Label search, found_method;
 4533 
 4534   for (int peel = 1; peel >= 0; peel--) {
 4535     movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
 4536     cmpptr(intf_klass, method_result);
 4537 
 4538     if (peel) {
 4539       jccb(Assembler::equal, found_method);
 4540     } else {
 4541       jccb(Assembler::notEqual, search);
 4542       // (invert the test to fall through to found_method...)
 4543     }
 4544 
 4545     if (!peel)  break;
 4546 
 4547     bind(search);
 4548 
 4549     // Check that the previous entry is non-null.  A null entry means that
 4550     // the receiver class doesn't implement the interface, and wasn't the
 4551     // same as when the caller was compiled.
 4552     testptr(method_result, method_result);
 4553     jcc(Assembler::zero, L_no_such_interface);
 4554     addptr(scan_temp, scan_step);
 4555   }
 4556 
 4557   bind(found_method);
 4558 
 4559   if (return_method) {
 4560     // Got a hit.
 4561     movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
 4562     movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
 4563   }
 4564 }
 4565 
 4566 
 4567 // virtual method calling
 4568 void MacroAssembler::lookup_virtual_method(Register recv_klass,
 4569                                            RegisterOrConstant vtable_index,
 4570                                            Register method_result) {
 4571   const int base = in_bytes(Klass::vtable_start_offset());
 4572   assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
 4573   Address vtable_entry_addr(recv_klass,
 4574                             vtable_index, Address::times_ptr,
 4575                             base + vtableEntry::method_offset_in_bytes());
 4576   movptr(method_result, vtable_entry_addr);
 4577 }
 4578 
 4579 
 4580 void MacroAssembler::check_klass_subtype(Register sub_klass,
 4581                            Register super_klass,
 4582                            Register temp_reg,
 4583                            Label& L_success) {
 4584   Label L_failure;
 4585   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
 4586   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
 4587   bind(L_failure);
 4588 }
 4589 
 4590 
 4591 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
 4592                                                    Register super_klass,
 4593                                                    Register temp_reg,
 4594                                                    Label* L_success,
 4595                                                    Label* L_failure,
 4596                                                    Label* L_slow_path,
 4597                                         RegisterOrConstant super_check_offset) {
 4598   assert_different_registers(sub_klass, super_klass, temp_reg);
 4599   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
 4600   if (super_check_offset.is_register()) {
 4601     assert_different_registers(sub_klass, super_klass,
 4602                                super_check_offset.as_register());
 4603   } else if (must_load_sco) {
 4604     assert(temp_reg != noreg, "supply either a temp or a register offset");
 4605   }
 4606 
 4607   Label L_fallthrough;
 4608   int label_nulls = 0;
 4609   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
 4610   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
 4611   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
 4612   assert(label_nulls <= 1, "at most one NULL in the batch");
 4613 
 4614   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
 4615   int sco_offset = in_bytes(Klass::super_check_offset_offset());
 4616   Address super_check_offset_addr(super_klass, sco_offset);
 4617 
 4618   // Hacked jcc, which "knows" that L_fallthrough, at least, is in
 4619   // range of a jccb.  If this routine grows larger, reconsider at
 4620   // least some of these.
 4621 #define local_jcc(assembler_cond, label)                                \
 4622   if (&(label) == &L_fallthrough)  jccb(assembler_cond, label);         \
 4623   else                             jcc( assembler_cond, label) /*omit semi*/
 4624 
 4625   // Hacked jmp, which may only be used just before L_fallthrough.
 4626 #define final_jmp(label)                                                \
 4627   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
 4628   else                            jmp(label)                /*omit semi*/
 4629 
 4630   // If the pointers are equal, we are done (e.g., String[] elements).
 4631   // This self-check enables sharing of secondary supertype arrays among
 4632   // non-primary types such as array-of-interface.  Otherwise, each such
 4633   // type would need its own customized SSA.
 4634   // We move this check to the front of the fast path because many
 4635   // type checks are in fact trivially successful in this manner,
 4636   // so we get a nicely predicted branch right at the start of the check.
 4637   cmpptr(sub_klass, super_klass);
 4638   local_jcc(Assembler::equal, *L_success);
 4639 
 4640   // Check the supertype display:
 4641   if (must_load_sco) {
 4642     // Positive movl does right thing on LP64.
 4643     movl(temp_reg, super_check_offset_addr);
 4644     super_check_offset = RegisterOrConstant(temp_reg);
 4645   }
 4646   Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
 4647   cmpptr(super_klass, super_check_addr); // load displayed supertype
 4648 
 4649   // This check has worked decisively for primary supers.
 4650   // Secondary supers are sought in the super_cache ('super_cache_addr').
 4651   // (Secondary supers are interfaces and very deeply nested subtypes.)
 4652   // This works in the same check above because of a tricky aliasing
 4653   // between the super_cache and the primary super display elements.
 4654   // (The 'super_check_addr' can address either, as the case requires.)
 4655   // Note that the cache is updated below if it does not help us find
 4656   // what we need immediately.
 4657   // So if it was a primary super, we can just fail immediately.
 4658   // Otherwise, it's the slow path for us (no success at this point).
 4659 
 4660   if (super_check_offset.is_register()) {
 4661     local_jcc(Assembler::equal, *L_success);
 4662     cmpl(super_check_offset.as_register(), sc_offset);
 4663     if (L_failure == &L_fallthrough) {
 4664       local_jcc(Assembler::equal, *L_slow_path);
 4665     } else {
 4666       local_jcc(Assembler::notEqual, *L_failure);
 4667       final_jmp(*L_slow_path);
 4668     }
 4669   } else if (super_check_offset.as_constant() == sc_offset) {
 4670     // Need a slow path; fast failure is impossible.
 4671     if (L_slow_path == &L_fallthrough) {
 4672       local_jcc(Assembler::equal, *L_success);
 4673     } else {
 4674       local_jcc(Assembler::notEqual, *L_slow_path);
 4675       final_jmp(*L_success);
 4676     }
 4677   } else {
 4678     // No slow path; it's a fast decision.
 4679     if (L_failure == &L_fallthrough) {
 4680       local_jcc(Assembler::equal, *L_success);
 4681     } else {
 4682       local_jcc(Assembler::notEqual, *L_failure);
 4683       final_jmp(*L_success);
 4684     }
 4685   }
 4686 
 4687   bind(L_fallthrough);
 4688 
 4689 #undef local_jcc
 4690 #undef final_jmp
 4691 }
 4692 
 4693 
 4694 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
 4695                                                    Register super_klass,
 4696                                                    Register temp_reg,
 4697                                                    Register temp2_reg,
 4698                                                    Label* L_success,
 4699                                                    Label* L_failure,
 4700                                                    bool set_cond_codes) {
 4701   assert_different_registers(sub_klass, super_klass, temp_reg);
 4702   if (temp2_reg != noreg)
 4703     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
 4704 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
 4705 
 4706   Label L_fallthrough;
 4707   int label_nulls = 0;
 4708   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
 4709   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
 4710   assert(label_nulls <= 1, "at most one NULL in the batch");
 4711 
 4712   // a couple of useful fields in sub_klass:
 4713   int ss_offset = in_bytes(Klass::secondary_supers_offset());
 4714   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
 4715   Address secondary_supers_addr(sub_klass, ss_offset);
 4716   Address super_cache_addr(     sub_klass, sc_offset);
 4717 
 4718   // Do a linear scan of the secondary super-klass chain.
 4719   // This code is rarely used, so simplicity is a virtue here.
 4720   // The repne_scan instruction uses fixed registers, which we must spill.
 4721   // Don't worry too much about pre-existing connections with the input regs.
 4722 
 4723   assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
 4724   assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
 4725 
 4726   // Get super_klass value into rax (even if it was in rdi or rcx).
 4727   bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
 4728   if (super_klass != rax) {
 4729     if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
 4730     mov(rax, super_klass);
 4731   }
 4732   if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
 4733   if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
 4734 
 4735 #ifndef PRODUCT
 4736   int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
 4737   ExternalAddress pst_counter_addr((address) pst_counter);
 4738   NOT_LP64(  incrementl(pst_counter_addr) );
 4739   LP64_ONLY( lea(rcx, pst_counter_addr) );
 4740   LP64_ONLY( incrementl(Address(rcx, 0)) );
 4741 #endif //PRODUCT
 4742 
 4743   // We will consult the secondary-super array.
 4744   movptr(rdi, secondary_supers_addr);
 4745   // Load the array length.  (Positive movl does right thing on LP64.)
 4746   movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
 4747   // Skip to start of data.
 4748   addptr(rdi, Array<Klass*>::base_offset_in_bytes());
 4749 
 4750   // Scan RCX words at [RDI] for an occurrence of RAX.
 4751   // Set NZ/Z based on last compare.
 4752   // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
 4753   // not change flags (only scas instruction which is repeated sets flags).
 4754   // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
 4755 
 4756     testptr(rax,rax); // Set Z = 0
 4757     repne_scan();
 4758 
 4759   // Unspill the temp. registers:
 4760   if (pushed_rdi)  pop(rdi);
 4761   if (pushed_rcx)  pop(rcx);
 4762   if (pushed_rax)  pop(rax);
 4763 
 4764   if (set_cond_codes) {
 4765     // Special hack for the AD files:  rdi is guaranteed non-zero.
 4766     assert(!pushed_rdi, "rdi must be left non-NULL");
 4767     // Also, the condition codes are properly set Z/NZ on succeed/failure.
 4768   }
 4769 
 4770   if (L_failure == &L_fallthrough)
 4771         jccb(Assembler::notEqual, *L_failure);
 4772   else  jcc(Assembler::notEqual, *L_failure);
 4773 
 4774   // Success.  Cache the super we found and proceed in triumph.
 4775   movptr(super_cache_addr, super_klass);
 4776 
 4777   if (L_success != &L_fallthrough) {
 4778     jmp(*L_success);
 4779   }
 4780 
 4781 #undef IS_A_TEMP
 4782 
 4783   bind(L_fallthrough);
 4784 }
 4785 
 4786 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
 4787   assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
 4788 
 4789   Label L_fallthrough;
 4790   if (L_fast_path == NULL) {
 4791     L_fast_path = &L_fallthrough;
 4792   } else if (L_slow_path == NULL) {
 4793     L_slow_path = &L_fallthrough;
 4794   }
 4795 
 4796   // Fast path check: class is fully initialized
 4797   cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
 4798   jcc(Assembler::equal, *L_fast_path);
 4799 
 4800   // Fast path check: current thread is initializer thread
 4801   cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
 4802   if (L_slow_path == &L_fallthrough) {
 4803     jcc(Assembler::equal, *L_fast_path);
 4804     bind(*L_slow_path);
 4805   } else if (L_fast_path == &L_fallthrough) {
 4806     jcc(Assembler::notEqual, *L_slow_path);
 4807     bind(*L_fast_path);
 4808   } else {
 4809     Unimplemented();
 4810   }
 4811 }
 4812 
 4813 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
 4814   if (VM_Version::supports_cmov()) {
 4815     cmovl(cc, dst, src);
 4816   } else {
 4817     Label L;
 4818     jccb(negate_condition(cc), L);
 4819     movl(dst, src);
 4820     bind(L);
 4821   }
 4822 }
 4823 
 4824 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
 4825   if (VM_Version::supports_cmov()) {
 4826     cmovl(cc, dst, src);
 4827   } else {
 4828     Label L;
 4829     jccb(negate_condition(cc), L);
 4830     movl(dst, src);
 4831     bind(L);
 4832   }
 4833 }
 4834 
 4835 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
 4836   if (!VerifyOops || VerifyAdapterSharing) {
 4837     // Below address of the code string confuses VerifyAdapterSharing
 4838     // because it may differ between otherwise equivalent adapters.
 4839     return;
 4840   }
 4841 
 4842   BLOCK_COMMENT("verify_oop {");
 4843 #ifdef _LP64
 4844   push(rscratch1);
 4845 #endif
 4846   push(rax);                          // save rax
 4847   push(reg);                          // pass register argument
 4848 
 4849   // Pass register number to verify_oop_subroutine
 4850   const char* b = NULL;
 4851   {
 4852     ResourceMark rm;
 4853     stringStream ss;
 4854     ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
 4855     b = code_string(ss.as_string());
 4856   }
 4857   ExternalAddress buffer((address) b);
 4858   pushptr(buffer.addr(), rscratch1);
 4859 
 4860   // call indirectly to solve generation ordering problem
 4861   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
 4862   call(rax);
 4863   // Caller pops the arguments (oop, message) and restores rax, r10
 4864   BLOCK_COMMENT("} verify_oop");
 4865 }
 4866 
 4867 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
 4868   if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
 4869     // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
 4870     // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
 4871     vpternlogd(dst, 0xFF, dst, dst, vector_len);
 4872   } else if (VM_Version::supports_avx()) {
 4873     vpcmpeqd(dst, dst, dst, vector_len);
 4874   } else {
 4875     assert(VM_Version::supports_sse2(), "");
 4876     pcmpeqd(dst, dst);
 4877   }
 4878 }
 4879 
 4880 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
 4881                                          int extra_slot_offset) {
 4882   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
 4883   int stackElementSize = Interpreter::stackElementSize;
 4884   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
 4885 #ifdef ASSERT
 4886   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
 4887   assert(offset1 - offset == stackElementSize, "correct arithmetic");
 4888 #endif
 4889   Register             scale_reg    = noreg;
 4890   Address::ScaleFactor scale_factor = Address::no_scale;
 4891   if (arg_slot.is_constant()) {
 4892     offset += arg_slot.as_constant() * stackElementSize;
 4893   } else {
 4894     scale_reg    = arg_slot.as_register();
 4895     scale_factor = Address::times(stackElementSize);
 4896   }
 4897   offset += wordSize;           // return PC is on stack
 4898   return Address(rsp, scale_reg, scale_factor, offset);
 4899 }
 4900 
 4901 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
 4902   if (!VerifyOops || VerifyAdapterSharing) {
 4903     // Below address of the code string confuses VerifyAdapterSharing
 4904     // because it may differ between otherwise equivalent adapters.
 4905     return;
 4906   }
 4907 
 4908 #ifdef _LP64
 4909   push(rscratch1);
 4910 #endif
 4911   push(rax); // save rax,
 4912   // addr may contain rsp so we will have to adjust it based on the push
 4913   // we just did (and on 64 bit we do two pushes)
 4914   // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
 4915   // stores rax into addr which is backwards of what was intended.
 4916   if (addr.uses(rsp)) {
 4917     lea(rax, addr);
 4918     pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
 4919   } else {
 4920     pushptr(addr);
 4921   }
 4922 
 4923   // Pass register number to verify_oop_subroutine
 4924   const char* b = NULL;
 4925   {
 4926     ResourceMark rm;
 4927     stringStream ss;
 4928     ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
 4929     b = code_string(ss.as_string());
 4930   }
 4931   ExternalAddress buffer((address) b);
 4932   pushptr(buffer.addr(), rscratch1);
 4933 
 4934   // call indirectly to solve generation ordering problem
 4935   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
 4936   call(rax);
 4937   // Caller pops the arguments (addr, message) and restores rax, r10.
 4938 }
 4939 
 4940 void MacroAssembler::verify_tlab() {
 4941 #ifdef ASSERT
 4942   if (UseTLAB && VerifyOops) {
 4943     Label next, ok;
 4944     Register t1 = rsi;
 4945     Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
 4946 
 4947     push(t1);
 4948     NOT_LP64(push(thread_reg));
 4949     NOT_LP64(get_thread(thread_reg));
 4950 
 4951     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
 4952     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
 4953     jcc(Assembler::aboveEqual, next);
 4954     STOP("assert(top >= start)");
 4955     should_not_reach_here();
 4956 
 4957     bind(next);
 4958     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
 4959     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
 4960     jcc(Assembler::aboveEqual, ok);
 4961     STOP("assert(top <= end)");
 4962     should_not_reach_here();
 4963 
 4964     bind(ok);
 4965     NOT_LP64(pop(thread_reg));
 4966     pop(t1);
 4967   }
 4968 #endif
 4969 }
 4970 
 4971 class ControlWord {
 4972  public:
 4973   int32_t _value;
 4974 
 4975   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
 4976   int  precision_control() const       { return  (_value >>  8) & 3      ; }
 4977   bool precision() const               { return ((_value >>  5) & 1) != 0; }
 4978   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
 4979   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
 4980   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
 4981   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
 4982   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
 4983 
 4984   void print() const {
 4985     // rounding control
 4986     const char* rc;
 4987     switch (rounding_control()) {
 4988       case 0: rc = "round near"; break;
 4989       case 1: rc = "round down"; break;
 4990       case 2: rc = "round up  "; break;
 4991       case 3: rc = "chop      "; break;
 4992       default:
 4993         rc = NULL; // silence compiler warnings
 4994         fatal("Unknown rounding control: %d", rounding_control());
 4995     };
 4996     // precision control
 4997     const char* pc;
 4998     switch (precision_control()) {
 4999       case 0: pc = "24 bits "; break;
 5000       case 1: pc = "reserved"; break;
 5001       case 2: pc = "53 bits "; break;
 5002       case 3: pc = "64 bits "; break;
 5003       default:
 5004         pc = NULL; // silence compiler warnings
 5005         fatal("Unknown precision control: %d", precision_control());
 5006     };
 5007     // flags
 5008     char f[9];
 5009     f[0] = ' ';
 5010     f[1] = ' ';
 5011     f[2] = (precision   ()) ? 'P' : 'p';
 5012     f[3] = (underflow   ()) ? 'U' : 'u';
 5013     f[4] = (overflow    ()) ? 'O' : 'o';
 5014     f[5] = (zero_divide ()) ? 'Z' : 'z';
 5015     f[6] = (denormalized()) ? 'D' : 'd';
 5016     f[7] = (invalid     ()) ? 'I' : 'i';
 5017     f[8] = '\x0';
 5018     // output
 5019     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
 5020   }
 5021 
 5022 };
 5023 
 5024 class StatusWord {
 5025  public:
 5026   int32_t _value;
 5027 
 5028   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
 5029   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
 5030   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
 5031   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
 5032   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
 5033   int  top() const                     { return  (_value >> 11) & 7      ; }
 5034   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
 5035   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
 5036   bool precision() const               { return ((_value >>  5) & 1) != 0; }
 5037   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
 5038   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
 5039   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
 5040   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
 5041   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
 5042 
 5043   void print() const {
 5044     // condition codes
 5045     char c[5];
 5046     c[0] = (C3()) ? '3' : '-';
 5047     c[1] = (C2()) ? '2' : '-';
 5048     c[2] = (C1()) ? '1' : '-';
 5049     c[3] = (C0()) ? '0' : '-';
 5050     c[4] = '\x0';
 5051     // flags
 5052     char f[9];
 5053     f[0] = (error_status()) ? 'E' : '-';
 5054     f[1] = (stack_fault ()) ? 'S' : '-';
 5055     f[2] = (precision   ()) ? 'P' : '-';
 5056     f[3] = (underflow   ()) ? 'U' : '-';
 5057     f[4] = (overflow    ()) ? 'O' : '-';
 5058     f[5] = (zero_divide ()) ? 'Z' : '-';
 5059     f[6] = (denormalized()) ? 'D' : '-';
 5060     f[7] = (invalid     ()) ? 'I' : '-';
 5061     f[8] = '\x0';
 5062     // output
 5063     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
 5064   }
 5065 
 5066 };
 5067 
 5068 class TagWord {
 5069  public:
 5070   int32_t _value;
 5071 
 5072   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
 5073 
 5074   void print() const {
 5075     printf("%04x", _value & 0xFFFF);
 5076   }
 5077 
 5078 };
 5079 
 5080 class FPU_Register {
 5081  public:
 5082   int32_t _m0;
 5083   int32_t _m1;
 5084   int16_t _ex;
 5085 
 5086   bool is_indefinite() const           {
 5087     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
 5088   }
 5089 
 5090   void print() const {
 5091     char  sign = (_ex < 0) ? '-' : '+';
 5092     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
 5093     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
 5094   };
 5095 
 5096 };
 5097 
 5098 class FPU_State {
 5099  public:
 5100   enum {
 5101     register_size       = 10,
 5102     number_of_registers =  8,
 5103     register_mask       =  7
 5104   };
 5105 
 5106   ControlWord  _control_word;
 5107   StatusWord   _status_word;
 5108   TagWord      _tag_word;
 5109   int32_t      _error_offset;
 5110   int32_t      _error_selector;
 5111   int32_t      _data_offset;
 5112   int32_t      _data_selector;
 5113   int8_t       _register[register_size * number_of_registers];
 5114 
 5115   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
 5116   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
 5117 
 5118   const char* tag_as_string(int tag) const {
 5119     switch (tag) {
 5120       case 0: return "valid";
 5121       case 1: return "zero";
 5122       case 2: return "special";
 5123       case 3: return "empty";
 5124     }
 5125     ShouldNotReachHere();
 5126     return NULL;
 5127   }
 5128 
 5129   void print() const {
 5130     // print computation registers
 5131     { int t = _status_word.top();
 5132       for (int i = 0; i < number_of_registers; i++) {
 5133         int j = (i - t) & register_mask;
 5134         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
 5135         st(j)->print();
 5136         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
 5137       }
 5138     }
 5139     printf("\n");
 5140     // print control registers
 5141     printf("ctrl = "); _control_word.print(); printf("\n");
 5142     printf("stat = "); _status_word .print(); printf("\n");
 5143     printf("tags = "); _tag_word    .print(); printf("\n");
 5144   }
 5145 
 5146 };
 5147 
 5148 class Flag_Register {
 5149  public:
 5150   int32_t _value;
 5151 
 5152   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
 5153   bool direction() const               { return ((_value >> 10) & 1) != 0; }
 5154   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
 5155   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
 5156   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
 5157   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
 5158   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
 5159 
 5160   void print() const {
 5161     // flags
 5162     char f[8];
 5163     f[0] = (overflow       ()) ? 'O' : '-';
 5164     f[1] = (direction      ()) ? 'D' : '-';
 5165     f[2] = (sign           ()) ? 'S' : '-';
 5166     f[3] = (zero           ()) ? 'Z' : '-';
 5167     f[4] = (auxiliary_carry()) ? 'A' : '-';
 5168     f[5] = (parity         ()) ? 'P' : '-';
 5169     f[6] = (carry          ()) ? 'C' : '-';
 5170     f[7] = '\x0';
 5171     // output
 5172     printf("%08x  flags = %s", _value, f);
 5173   }
 5174 
 5175 };
 5176 
 5177 class IU_Register {
 5178  public:
 5179   int32_t _value;
 5180 
 5181   void print() const {
 5182     printf("%08x  %11d", _value, _value);
 5183   }
 5184 
 5185 };
 5186 
 5187 class IU_State {
 5188  public:
 5189   Flag_Register _eflags;
 5190   IU_Register   _rdi;
 5191   IU_Register   _rsi;
 5192   IU_Register   _rbp;
 5193   IU_Register   _rsp;
 5194   IU_Register   _rbx;
 5195   IU_Register   _rdx;
 5196   IU_Register   _rcx;
 5197   IU_Register   _rax;
 5198 
 5199   void print() const {
 5200     // computation registers
 5201     printf("rax,  = "); _rax.print(); printf("\n");
 5202     printf("rbx,  = "); _rbx.print(); printf("\n");
 5203     printf("rcx  = "); _rcx.print(); printf("\n");
 5204     printf("rdx  = "); _rdx.print(); printf("\n");
 5205     printf("rdi  = "); _rdi.print(); printf("\n");
 5206     printf("rsi  = "); _rsi.print(); printf("\n");
 5207     printf("rbp,  = "); _rbp.print(); printf("\n");
 5208     printf("rsp  = "); _rsp.print(); printf("\n");
 5209     printf("\n");
 5210     // control registers
 5211     printf("flgs = "); _eflags.print(); printf("\n");
 5212   }
 5213 };
 5214 
 5215 
 5216 class CPU_State {
 5217  public:
 5218   FPU_State _fpu_state;
 5219   IU_State  _iu_state;
 5220 
 5221   void print() const {
 5222     printf("--------------------------------------------------\n");
 5223     _iu_state .print();
 5224     printf("\n");
 5225     _fpu_state.print();
 5226     printf("--------------------------------------------------\n");
 5227   }
 5228 
 5229 };
 5230 
 5231 
 5232 static void _print_CPU_state(CPU_State* state) {
 5233   state->print();
 5234 };
 5235 
 5236 
 5237 void MacroAssembler::print_CPU_state() {
 5238   push_CPU_state();
 5239   push(rsp);                // pass CPU state
 5240   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
 5241   addptr(rsp, wordSize);       // discard argument
 5242   pop_CPU_state();
 5243 }
 5244 
 5245 
 5246 #ifndef _LP64
 5247 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
 5248   static int counter = 0;
 5249   FPU_State* fs = &state->_fpu_state;
 5250   counter++;
 5251   // For leaf calls, only verify that the top few elements remain empty.
 5252   // We only need 1 empty at the top for C2 code.
 5253   if( stack_depth < 0 ) {
 5254     if( fs->tag_for_st(7) != 3 ) {
 5255       printf("FPR7 not empty\n");
 5256       state->print();
 5257       assert(false, "error");
 5258       return false;
 5259     }
 5260     return true;                // All other stack states do not matter
 5261   }
 5262 
 5263   assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
 5264          "bad FPU control word");
 5265 
 5266   // compute stack depth
 5267   int i = 0;
 5268   while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
 5269   int d = i;
 5270   while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
 5271   // verify findings
 5272   if (i != FPU_State::number_of_registers) {
 5273     // stack not contiguous
 5274     printf("%s: stack not contiguous at ST%d\n", s, i);
 5275     state->print();
 5276     assert(false, "error");
 5277     return false;
 5278   }
 5279   // check if computed stack depth corresponds to expected stack depth
 5280   if (stack_depth < 0) {
 5281     // expected stack depth is -stack_depth or less
 5282     if (d > -stack_depth) {
 5283       // too many elements on the stack
 5284       printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
 5285       state->print();
 5286       assert(false, "error");
 5287       return false;
 5288     }
 5289   } else {
 5290     // expected stack depth is stack_depth
 5291     if (d != stack_depth) {
 5292       // wrong stack depth
 5293       printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
 5294       state->print();
 5295       assert(false, "error");
 5296       return false;
 5297     }
 5298   }
 5299   // everything is cool
 5300   return true;
 5301 }
 5302 
 5303 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
 5304   if (!VerifyFPU) return;
 5305   push_CPU_state();
 5306   push(rsp);                // pass CPU state
 5307   ExternalAddress msg((address) s);
 5308   // pass message string s
 5309   pushptr(msg.addr(), noreg);
 5310   push(stack_depth);        // pass stack depth
 5311   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
 5312   addptr(rsp, 3 * wordSize);   // discard arguments
 5313   // check for error
 5314   { Label L;
 5315     testl(rax, rax);
 5316     jcc(Assembler::notZero, L);
 5317     int3();                  // break if error condition
 5318     bind(L);
 5319   }
 5320   pop_CPU_state();
 5321 }
 5322 #endif // _LP64
 5323 
 5324 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
 5325   // Either restore the MXCSR register after returning from the JNI Call
 5326   // or verify that it wasn't changed (with -Xcheck:jni flag).
 5327   if (VM_Version::supports_sse()) {
 5328     if (RestoreMXCSROnJNICalls) {
 5329       ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
 5330     } else if (CheckJNICalls) {
 5331       call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
 5332     }
 5333   }
 5334   // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
 5335   vzeroupper();
 5336 
 5337 #ifndef _LP64
 5338   // Either restore the x87 floating pointer control word after returning
 5339   // from the JNI call or verify that it wasn't changed.
 5340   if (CheckJNICalls) {
 5341     call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
 5342   }
 5343 #endif // _LP64
 5344 }
 5345 
 5346 // ((OopHandle)result).resolve();
 5347 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
 5348   assert_different_registers(result, tmp);
 5349 
 5350   // Only 64 bit platforms support GCs that require a tmp register
 5351   // Only IN_HEAP loads require a thread_tmp register
 5352   // OopHandle::resolve is an indirection like jobject.
 5353   access_load_at(T_OBJECT, IN_NATIVE,
 5354                  result, Address(result, 0), tmp, /*tmp_thread*/noreg);
 5355 }
 5356 
 5357 // ((WeakHandle)result).resolve();
 5358 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
 5359   assert_different_registers(rresult, rtmp);
 5360   Label resolved;
 5361 
 5362   // A null weak handle resolves to null.
 5363   cmpptr(rresult, 0);
 5364   jcc(Assembler::equal, resolved);
 5365 
 5366   // Only 64 bit platforms support GCs that require a tmp register
 5367   // Only IN_HEAP loads require a thread_tmp register
 5368   // WeakHandle::resolve is an indirection like jweak.
 5369   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
 5370                  rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
 5371   bind(resolved);
 5372 }
 5373 
 5374 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
 5375   // get mirror
 5376   const int mirror_offset = in_bytes(Klass::java_mirror_offset());
 5377   load_method_holder(mirror, method);
 5378   movptr(mirror, Address(mirror, mirror_offset));
 5379   resolve_oop_handle(mirror, tmp);
 5380 }
 5381 
 5382 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
 5383   load_method_holder(rresult, rmethod);
 5384   movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
 5385 }
 5386 
 5387 void MacroAssembler::load_method_holder(Register holder, Register method) {
 5388   movptr(holder, Address(method, Method::const_offset()));                      // ConstMethod*
 5389   movptr(holder, Address(holder, ConstMethod::constants_offset()));             // ConstantPool*
 5390   movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
 5391 }
 5392 
 5393 void MacroAssembler::load_metadata(Register dst, Register src) {
 5394   if (UseCompressedClassPointers) {
 5395     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
 5396   } else {
 5397     movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
 5398   }
 5399 }
 5400 
 5401 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
 5402   assert_different_registers(src, tmp);
 5403   assert_different_registers(dst, tmp);
 5404 #ifdef _LP64
 5405   if (UseCompressedClassPointers) {
 5406     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
 5407     decode_klass_not_null(dst, tmp);
 5408   } else
 5409 #endif
 5410   movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
 5411 }
 5412 
 5413 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
 5414   load_klass(dst, src, tmp);
 5415   movptr(dst, Address(dst, Klass::prototype_header_offset()));
 5416 }
 5417 
 5418 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
 5419   assert_different_registers(src, tmp);
 5420   assert_different_registers(dst, tmp);
 5421 #ifdef _LP64
 5422   if (UseCompressedClassPointers) {
 5423     encode_klass_not_null(src, tmp);
 5424     movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
 5425   } else
 5426 #endif
 5427     movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
 5428 }
 5429 
 5430 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 5431                                     Register tmp1, Register thread_tmp) {
 5432   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 5433   decorators = AccessInternal::decorator_fixup(decorators);
 5434   bool as_raw = (decorators & AS_RAW) != 0;
 5435   if (as_raw) {
 5436     bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
 5437   } else {
 5438     bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
 5439   }
 5440 }
 5441 
 5442 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 5443                                      Register tmp1, Register tmp2, Register tmp3) {
 5444   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 5445   decorators = AccessInternal::decorator_fixup(decorators);
 5446   bool as_raw = (decorators & AS_RAW) != 0;
 5447   if (as_raw) {
 5448     bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2, tmp3);
 5449   } else {
 5450     bs->store_at(this, decorators, type, dst, src, tmp1, tmp2, tmp3);
 5451   }
 5452 }
 5453 
 5454 void MacroAssembler::access_value_copy(DecoratorSet decorators, Register src, Register dst,
 5455                                        Register inline_klass) {
 5456   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 5457   bs->value_copy(this, decorators, src, dst, inline_klass);
 5458 }
 5459 
 5460 void MacroAssembler::first_field_offset(Register inline_klass, Register offset) {
 5461   movptr(offset, Address(inline_klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
 5462   movl(offset, Address(offset, InlineKlass::first_field_offset_offset()));
 5463 }
 5464 
 5465 void MacroAssembler::data_for_oop(Register oop, Register data, Register inline_klass) {
 5466   // ((address) (void*) o) + vk->first_field_offset();
 5467   Register offset = (data == oop) ? rscratch1 : data;
 5468   first_field_offset(inline_klass, offset);
 5469   if (data == oop) {
 5470     addptr(data, offset);
 5471   } else {
 5472     lea(data, Address(oop, offset));
 5473   }
 5474 }
 5475 
 5476 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
 5477                                                 Register index, Register data) {
 5478   assert(index != rcx, "index needs to shift by rcx");
 5479   assert_different_registers(array, array_klass, index);
 5480   assert_different_registers(rcx, array, index);
 5481 
 5482   // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
 5483   movl(rcx, Address(array_klass, Klass::layout_helper_offset()));
 5484 
 5485   // Klass::layout_helper_log2_element_size(lh)
 5486   // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
 5487   shrl(rcx, Klass::_lh_log2_element_size_shift);
 5488   andl(rcx, Klass::_lh_log2_element_size_mask);
 5489   shlptr(index); // index << rcx
 5490 
 5491   lea(data, Address(array, index, Address::times_1, arrayOopDesc::base_offset_in_bytes(T_PRIMITIVE_OBJECT)));
 5492 }
 5493 
 5494 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
 5495                                    Register thread_tmp, DecoratorSet decorators) {
 5496   access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
 5497 }
 5498 
 5499 // Doesn't do verification, generates fixed size code
 5500 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
 5501                                             Register thread_tmp, DecoratorSet decorators) {
 5502   access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
 5503 }
 5504 
 5505 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
 5506                                     Register tmp2, Register tmp3, DecoratorSet decorators) {
 5507   access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2, tmp3);
 5508 }
 5509 
 5510 // Used for storing NULLs.
 5511 void MacroAssembler::store_heap_oop_null(Address dst) {
 5512   access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
 5513 }
 5514 
 5515 #ifdef _LP64
 5516 void MacroAssembler::store_klass_gap(Register dst, Register src) {
 5517   if (UseCompressedClassPointers) {
 5518     // Store to klass gap in destination
 5519     movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
 5520   }
 5521 }
 5522 
 5523 #ifdef ASSERT
 5524 void MacroAssembler::verify_heapbase(const char* msg) {
 5525   assert (UseCompressedOops, "should be compressed");
 5526   assert (Universe::heap() != NULL, "java heap should be initialized");
 5527   if (CheckCompressedOops) {
 5528     Label ok;
 5529     ExternalAddress src2(CompressedOops::ptrs_base_addr());
 5530     const bool is_src2_reachable = reachable(src2);
 5531     if (!is_src2_reachable) {
 5532       push(rscratch1);  // cmpptr trashes rscratch1
 5533     }
 5534     cmpptr(r12_heapbase, src2, rscratch1);
 5535     jcc(Assembler::equal, ok);
 5536     STOP(msg);
 5537     bind(ok);
 5538     if (!is_src2_reachable) {
 5539       pop(rscratch1);
 5540     }
 5541   }
 5542 }
 5543 #endif
 5544 
 5545 // Algorithm must match oop.inline.hpp encode_heap_oop.
 5546 void MacroAssembler::encode_heap_oop(Register r) {
 5547 #ifdef ASSERT
 5548   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
 5549 #endif
 5550   verify_oop_msg(r, "broken oop in encode_heap_oop");
 5551   if (CompressedOops::base() == NULL) {
 5552     if (CompressedOops::shift() != 0) {
 5553       assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
 5554       shrq(r, LogMinObjAlignmentInBytes);
 5555     }
 5556     return;
 5557   }
 5558   testq(r, r);
 5559   cmovq(Assembler::equal, r, r12_heapbase);
 5560   subq(r, r12_heapbase);
 5561   shrq(r, LogMinObjAlignmentInBytes);
 5562 }
 5563 
 5564 void MacroAssembler::encode_heap_oop_not_null(Register r) {
 5565 #ifdef ASSERT
 5566   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
 5567   if (CheckCompressedOops) {
 5568     Label ok;
 5569     testq(r, r);
 5570     jcc(Assembler::notEqual, ok);
 5571     STOP("null oop passed to encode_heap_oop_not_null");
 5572     bind(ok);
 5573   }
 5574 #endif
 5575   verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
 5576   if (CompressedOops::base() != NULL) {
 5577     subq(r, r12_heapbase);
 5578   }
 5579   if (CompressedOops::shift() != 0) {
 5580     assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
 5581     shrq(r, LogMinObjAlignmentInBytes);
 5582   }
 5583 }
 5584 
 5585 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
 5586 #ifdef ASSERT
 5587   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
 5588   if (CheckCompressedOops) {
 5589     Label ok;
 5590     testq(src, src);
 5591     jcc(Assembler::notEqual, ok);
 5592     STOP("null oop passed to encode_heap_oop_not_null2");
 5593     bind(ok);
 5594   }
 5595 #endif
 5596   verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
 5597   if (dst != src) {
 5598     movq(dst, src);
 5599   }
 5600   if (CompressedOops::base() != NULL) {
 5601     subq(dst, r12_heapbase);
 5602   }
 5603   if (CompressedOops::shift() != 0) {
 5604     assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
 5605     shrq(dst, LogMinObjAlignmentInBytes);
 5606   }
 5607 }
 5608 
 5609 void  MacroAssembler::decode_heap_oop(Register r) {
 5610 #ifdef ASSERT
 5611   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
 5612 #endif
 5613   if (CompressedOops::base() == NULL) {
 5614     if (CompressedOops::shift() != 0) {
 5615       assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
 5616       shlq(r, LogMinObjAlignmentInBytes);
 5617     }
 5618   } else {
 5619     Label done;
 5620     shlq(r, LogMinObjAlignmentInBytes);
 5621     jccb(Assembler::equal, done);
 5622     addq(r, r12_heapbase);
 5623     bind(done);
 5624   }
 5625   verify_oop_msg(r, "broken oop in decode_heap_oop");
 5626 }
 5627 
 5628 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
 5629   // Note: it will change flags
 5630   assert (UseCompressedOops, "should only be used for compressed headers");
 5631   assert (Universe::heap() != NULL, "java heap should be initialized");
 5632   // Cannot assert, unverified entry point counts instructions (see .ad file)
 5633   // vtableStubs also counts instructions in pd_code_size_limit.
 5634   // Also do not verify_oop as this is called by verify_oop.
 5635   if (CompressedOops::shift() != 0) {
 5636     assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
 5637     shlq(r, LogMinObjAlignmentInBytes);
 5638     if (CompressedOops::base() != NULL) {
 5639       addq(r, r12_heapbase);
 5640     }
 5641   } else {
 5642     assert (CompressedOops::base() == NULL, "sanity");
 5643   }
 5644 }
 5645 
 5646 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
 5647   // Note: it will change flags
 5648   assert (UseCompressedOops, "should only be used for compressed headers");
 5649   assert (Universe::heap() != NULL, "java heap should be initialized");
 5650   // Cannot assert, unverified entry point counts instructions (see .ad file)
 5651   // vtableStubs also counts instructions in pd_code_size_limit.
 5652   // Also do not verify_oop as this is called by verify_oop.
 5653   if (CompressedOops::shift() != 0) {
 5654     assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
 5655     if (LogMinObjAlignmentInBytes == Address::times_8) {
 5656       leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
 5657     } else {
 5658       if (dst != src) {
 5659         movq(dst, src);
 5660       }
 5661       shlq(dst, LogMinObjAlignmentInBytes);
 5662       if (CompressedOops::base() != NULL) {
 5663         addq(dst, r12_heapbase);
 5664       }
 5665     }
 5666   } else {
 5667     assert (CompressedOops::base() == NULL, "sanity");
 5668     if (dst != src) {
 5669       movq(dst, src);
 5670     }
 5671   }
 5672 }
 5673 
 5674 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
 5675   assert_different_registers(r, tmp);
 5676   if (CompressedKlassPointers::base() != NULL) {
 5677     mov64(tmp, (int64_t)CompressedKlassPointers::base());
 5678     subq(r, tmp);
 5679   }
 5680   if (CompressedKlassPointers::shift() != 0) {
 5681     assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
 5682     shrq(r, LogKlassAlignmentInBytes);
 5683   }
 5684 }
 5685 
 5686 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
 5687   assert_different_registers(src, dst);
 5688   if (CompressedKlassPointers::base() != NULL) {
 5689     mov64(dst, -(int64_t)CompressedKlassPointers::base());
 5690     addq(dst, src);
 5691   } else {
 5692     movptr(dst, src);
 5693   }
 5694   if (CompressedKlassPointers::shift() != 0) {
 5695     assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
 5696     shrq(dst, LogKlassAlignmentInBytes);
 5697   }
 5698 }
 5699 
 5700 void  MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
 5701   assert_different_registers(r, tmp);
 5702   // Note: it will change flags
 5703   assert(UseCompressedClassPointers, "should only be used for compressed headers");
 5704   // Cannot assert, unverified entry point counts instructions (see .ad file)
 5705   // vtableStubs also counts instructions in pd_code_size_limit.
 5706   // Also do not verify_oop as this is called by verify_oop.
 5707   if (CompressedKlassPointers::shift() != 0) {
 5708     assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
 5709     shlq(r, LogKlassAlignmentInBytes);
 5710   }
 5711   if (CompressedKlassPointers::base() != NULL) {
 5712     mov64(tmp, (int64_t)CompressedKlassPointers::base());
 5713     addq(r, tmp);
 5714   }
 5715 }
 5716 
 5717 void  MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
 5718   assert_different_registers(src, dst);
 5719   // Note: it will change flags
 5720   assert (UseCompressedClassPointers, "should only be used for compressed headers");
 5721   // Cannot assert, unverified entry point counts instructions (see .ad file)
 5722   // vtableStubs also counts instructions in pd_code_size_limit.
 5723   // Also do not verify_oop as this is called by verify_oop.
 5724 
 5725   if (CompressedKlassPointers::base() == NULL &&
 5726       CompressedKlassPointers::shift() == 0) {
 5727     // The best case scenario is that there is no base or shift. Then it is already
 5728     // a pointer that needs nothing but a register rename.
 5729     movl(dst, src);
 5730   } else {
 5731     if (CompressedKlassPointers::base() != NULL) {
 5732       mov64(dst, (int64_t)CompressedKlassPointers::base());
 5733     } else {
 5734       xorq(dst, dst);
 5735     }
 5736     if (CompressedKlassPointers::shift() != 0) {
 5737       assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
 5738       assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
 5739       leaq(dst, Address(dst, src, Address::times_8, 0));
 5740     } else {
 5741       addq(dst, src);
 5742     }
 5743   }
 5744 }
 5745 
 5746 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
 5747   assert (UseCompressedOops, "should only be used for compressed headers");
 5748   assert (Universe::heap() != NULL, "java heap should be initialized");
 5749   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
 5750   int oop_index = oop_recorder()->find_index(obj);
 5751   RelocationHolder rspec = oop_Relocation::spec(oop_index);
 5752   mov_narrow_oop(dst, oop_index, rspec);
 5753 }
 5754 
 5755 void  MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
 5756   assert (UseCompressedOops, "should only be used for compressed headers");
 5757   assert (Universe::heap() != NULL, "java heap should be initialized");
 5758   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
 5759   int oop_index = oop_recorder()->find_index(obj);
 5760   RelocationHolder rspec = oop_Relocation::spec(oop_index);
 5761   mov_narrow_oop(dst, oop_index, rspec);
 5762 }
 5763 
 5764 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
 5765   assert (UseCompressedClassPointers, "should only be used for compressed headers");
 5766   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
 5767   int klass_index = oop_recorder()->find_index(k);
 5768   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
 5769   mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
 5770 }
 5771 
 5772 void  MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
 5773   assert (UseCompressedClassPointers, "should only be used for compressed headers");
 5774   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
 5775   int klass_index = oop_recorder()->find_index(k);
 5776   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
 5777   mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
 5778 }
 5779 
 5780 void  MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
 5781   assert (UseCompressedOops, "should only be used for compressed headers");
 5782   assert (Universe::heap() != NULL, "java heap should be initialized");
 5783   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
 5784   int oop_index = oop_recorder()->find_index(obj);
 5785   RelocationHolder rspec = oop_Relocation::spec(oop_index);
 5786   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
 5787 }
 5788 
 5789 void  MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
 5790   assert (UseCompressedOops, "should only be used for compressed headers");
 5791   assert (Universe::heap() != NULL, "java heap should be initialized");
 5792   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
 5793   int oop_index = oop_recorder()->find_index(obj);
 5794   RelocationHolder rspec = oop_Relocation::spec(oop_index);
 5795   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
 5796 }
 5797 
 5798 void  MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
 5799   assert (UseCompressedClassPointers, "should only be used for compressed headers");
 5800   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
 5801   int klass_index = oop_recorder()->find_index(k);
 5802   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
 5803   Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
 5804 }
 5805 
 5806 void  MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
 5807   assert (UseCompressedClassPointers, "should only be used for compressed headers");
 5808   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
 5809   int klass_index = oop_recorder()->find_index(k);
 5810   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
 5811   Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
 5812 }
 5813 
 5814 void MacroAssembler::reinit_heapbase() {
 5815   if (UseCompressedOops) {
 5816     if (Universe::heap() != NULL) {
 5817       if (CompressedOops::base() == NULL) {
 5818         MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
 5819       } else {
 5820         mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
 5821       }
 5822     } else {
 5823       movptr(r12_heapbase, ExternalAddress(CompressedOops::ptrs_base_addr()));
 5824     }
 5825   }
 5826 }
 5827 
 5828 #endif // _LP64
 5829 
 5830 #if COMPILER2_OR_JVMCI
 5831 
 5832 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
 5833 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
 5834   // cnt - number of qwords (8-byte words).
 5835   // base - start address, qword aligned.
 5836   Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
 5837   bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
 5838   if (use64byteVector) {
 5839     evpbroadcastq(xtmp, val, AVX_512bit);
 5840   } else if (MaxVectorSize >= 32) {
 5841     movdq(xtmp, val);
 5842     punpcklqdq(xtmp, xtmp);
 5843     vinserti128_high(xtmp, xtmp);
 5844   } else {
 5845     movdq(xtmp, val);
 5846     punpcklqdq(xtmp, xtmp);
 5847   }
 5848   jmp(L_zero_64_bytes);
 5849 
 5850   BIND(L_loop);
 5851   if (MaxVectorSize >= 32) {
 5852     fill64(base, 0, xtmp, use64byteVector);
 5853   } else {
 5854     movdqu(Address(base,  0), xtmp);
 5855     movdqu(Address(base, 16), xtmp);
 5856     movdqu(Address(base, 32), xtmp);
 5857     movdqu(Address(base, 48), xtmp);
 5858   }
 5859   addptr(base, 64);
 5860 
 5861   BIND(L_zero_64_bytes);
 5862   subptr(cnt, 8);
 5863   jccb(Assembler::greaterEqual, L_loop);
 5864 
 5865   // Copy trailing 64 bytes
 5866   if (use64byteVector) {
 5867     addptr(cnt, 8);
 5868     jccb(Assembler::equal, L_end);
 5869     fill64_masked(3, base, 0, xtmp, mask, cnt, val, true);
 5870     jmp(L_end);
 5871   } else {
 5872     addptr(cnt, 4);
 5873     jccb(Assembler::less, L_tail);
 5874     if (MaxVectorSize >= 32) {
 5875       vmovdqu(Address(base, 0), xtmp);
 5876     } else {
 5877       movdqu(Address(base,  0), xtmp);
 5878       movdqu(Address(base, 16), xtmp);
 5879     }
 5880   }
 5881   addptr(base, 32);
 5882   subptr(cnt, 4);
 5883 
 5884   BIND(L_tail);
 5885   addptr(cnt, 4);
 5886   jccb(Assembler::lessEqual, L_end);
 5887   if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
 5888     fill32_masked(3, base, 0, xtmp, mask, cnt, val);
 5889   } else {
 5890     decrement(cnt);
 5891 
 5892     BIND(L_sloop);
 5893     movq(Address(base, 0), xtmp);
 5894     addptr(base, 8);
 5895     decrement(cnt);
 5896     jccb(Assembler::greaterEqual, L_sloop);
 5897   }
 5898   BIND(L_end);
 5899 }
 5900 
 5901 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
 5902   assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
 5903   // An inline type might be returned. If fields are in registers we
 5904   // need to allocate an inline type instance and initialize it with
 5905   // the value of the fields.
 5906   Label skip;
 5907   // We only need a new buffered inline type if a new one is not returned
 5908   testptr(rax, 1);
 5909   jcc(Assembler::zero, skip);
 5910   int call_offset = -1;
 5911 
 5912 #ifdef _LP64
 5913   // The following code is similar to allocate_instance but has some slight differences,
 5914   // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
 5915   // allocating is not necessary if vk != NULL, etc. allocate_instance is not aware of these.
 5916   Label slow_case;
 5917   // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
 5918   mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
 5919   if (vk != NULL) {
 5920     // Called from C1, where the return type is statically known.
 5921     movptr(rbx, (intptr_t)vk->get_InlineKlass());
 5922     jint obj_size = vk->layout_helper();
 5923     assert(obj_size != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
 5924     if (UseTLAB) {
 5925       tlab_allocate(r15_thread, rax, noreg, obj_size, r13, r14, slow_case);
 5926     } else {
 5927       jmp(slow_case);
 5928     }
 5929   } else {
 5930     // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
 5931     mov(rbx, rax);
 5932     andptr(rbx, -2);
 5933     movl(r14, Address(rbx, Klass::layout_helper_offset()));
 5934     if (UseTLAB) {
 5935       tlab_allocate(r15_thread, rax, r14, 0, r13, r14, slow_case);
 5936     } else {
 5937       jmp(slow_case);
 5938     }
 5939   }
 5940   if (UseTLAB) {
 5941     // 2. Initialize buffered inline instance header
 5942     Register buffer_obj = rax;
 5943     movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
 5944     xorl(r13, r13);
 5945     store_klass_gap(buffer_obj, r13);
 5946     if (vk == NULL) {
 5947       // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
 5948       mov(r13, rbx);
 5949     }
 5950     store_klass(buffer_obj, rbx, rscratch1);
 5951     // 3. Initialize its fields with an inline class specific handler
 5952     if (vk != NULL) {
 5953       call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
 5954     } else {
 5955       movptr(rbx, Address(r13, InstanceKlass::adr_inlineklass_fixed_block_offset()));
 5956       movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
 5957       call(rbx);
 5958     }
 5959     jmp(skip);
 5960   }
 5961   bind(slow_case);
 5962   // We failed to allocate a new inline type, fall back to a runtime
 5963   // call. Some oop field may be live in some registers but we can't
 5964   // tell. That runtime call will take care of preserving them
 5965   // across a GC if there's one.
 5966   mov(rax, rscratch1);
 5967 #endif
 5968 
 5969   if (from_interpreter) {
 5970     super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
 5971   } else {
 5972     call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
 5973     call_offset = offset();
 5974   }
 5975 
 5976   bind(skip);
 5977   return call_offset;
 5978 }
 5979 
 5980 // Move a value between registers/stack slots and update the reg_state
 5981 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
 5982   assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
 5983   if (reg_state[to->value()] == reg_written) {
 5984     return true; // Already written
 5985   }
 5986   if (from != to && bt != T_VOID) {
 5987     if (reg_state[to->value()] == reg_readonly) {
 5988       return false; // Not yet writable
 5989     }
 5990     if (from->is_reg()) {
 5991       if (to->is_reg()) {
 5992         if (from->is_XMMRegister()) {
 5993           if (bt == T_DOUBLE) {
 5994             movdbl(to->as_XMMRegister(), from->as_XMMRegister());
 5995           } else {
 5996             assert(bt == T_FLOAT, "must be float");
 5997             movflt(to->as_XMMRegister(), from->as_XMMRegister());
 5998           }
 5999         } else {
 6000           movq(to->as_Register(), from->as_Register());
 6001         }
 6002       } else {
 6003         int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
 6004         Address to_addr = Address(rsp, st_off);
 6005         if (from->is_XMMRegister()) {
 6006           if (bt == T_DOUBLE) {
 6007             movdbl(to_addr, from->as_XMMRegister());
 6008           } else {
 6009             assert(bt == T_FLOAT, "must be float");
 6010             movflt(to_addr, from->as_XMMRegister());
 6011           }
 6012         } else {
 6013           movq(to_addr, from->as_Register());
 6014         }
 6015       }
 6016     } else {
 6017       Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
 6018       if (to->is_reg()) {
 6019         if (to->is_XMMRegister()) {
 6020           if (bt == T_DOUBLE) {
 6021             movdbl(to->as_XMMRegister(), from_addr);
 6022           } else {
 6023             assert(bt == T_FLOAT, "must be float");
 6024             movflt(to->as_XMMRegister(), from_addr);
 6025           }
 6026         } else {
 6027           movq(to->as_Register(), from_addr);
 6028         }
 6029       } else {
 6030         int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
 6031         movq(r13, from_addr);
 6032         movq(Address(rsp, st_off), r13);
 6033       }
 6034     }
 6035   }
 6036   // Update register states
 6037   reg_state[from->value()] = reg_writable;
 6038   reg_state[to->value()] = reg_written;
 6039   return true;
 6040 }
 6041 
 6042 // Calculate the extra stack space required for packing or unpacking inline
 6043 // args and adjust the stack pointer
 6044 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
 6045   // Two additional slots to account for return address
 6046   int sp_inc = (args_on_stack + 2) * VMRegImpl::stack_slot_size;
 6047   sp_inc = align_up(sp_inc, StackAlignmentInBytes);
 6048   // Save the return address, adjust the stack (make sure it is properly
 6049   // 16-byte aligned) and copy the return address to the new top of the stack.
 6050   // The stack will be repaired on return (see MacroAssembler::remove_frame).
 6051   assert(sp_inc > 0, "sanity");
 6052   pop(r13);
 6053   subptr(rsp, sp_inc);
 6054   push(r13);
 6055   return sp_inc;
 6056 }
 6057 
 6058 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
 6059 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
 6060                                           VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
 6061                                           RegState reg_state[]) {
 6062   assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
 6063   assert(from->is_valid(), "source must be valid");
 6064   bool progress = false;
 6065 #ifdef ASSERT
 6066   const int start_offset = offset();
 6067 #endif
 6068 
 6069   Label L_null, L_notNull;
 6070   // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
 6071   Register tmp1 = r10;
 6072   Register tmp2 = r13;
 6073   Register fromReg = noreg;
 6074   ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
 6075   bool done = true;
 6076   bool mark_done = true;
 6077   VMReg toReg;
 6078   BasicType bt;
 6079   // Check if argument requires a null check
 6080   bool null_check = false;
 6081   VMReg nullCheckReg;
 6082   while (stream.next(nullCheckReg, bt)) {
 6083     if (sig->at(stream.sig_index())._offset == -1) {
 6084       null_check = true;
 6085       break;
 6086     }
 6087   }
 6088   stream.reset(sig_index, to_index);
 6089   while (stream.next(toReg, bt)) {
 6090     assert(toReg->is_valid(), "destination must be valid");
 6091     int idx = (int)toReg->value();
 6092     if (reg_state[idx] == reg_readonly) {
 6093       if (idx != from->value()) {
 6094         mark_done = false;
 6095       }
 6096       done = false;
 6097       continue;
 6098     } else if (reg_state[idx] == reg_written) {
 6099       continue;
 6100     }
 6101     assert(reg_state[idx] == reg_writable, "must be writable");
 6102     reg_state[idx] = reg_written;
 6103     progress = true;
 6104 
 6105     if (fromReg == noreg) {
 6106       if (from->is_reg()) {
 6107         fromReg = from->as_Register();
 6108       } else {
 6109         int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
 6110         movq(tmp1, Address(rsp, st_off));
 6111         fromReg = tmp1;
 6112       }
 6113       if (null_check) {
 6114         // Nullable inline type argument, emit null check
 6115         testptr(fromReg, fromReg);
 6116         jcc(Assembler::zero, L_null);
 6117       }
 6118     }
 6119     int off = sig->at(stream.sig_index())._offset;
 6120     if (off == -1) {
 6121       assert(null_check, "Missing null check at");
 6122       if (toReg->is_stack()) {
 6123         int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
 6124         movq(Address(rsp, st_off), 1);
 6125       } else {
 6126         movq(toReg->as_Register(), 1);
 6127       }
 6128       continue;
 6129     }
 6130     assert(off > 0, "offset in object should be positive");
 6131     Address fromAddr = Address(fromReg, off);
 6132     if (!toReg->is_XMMRegister()) {
 6133       Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
 6134       if (is_reference_type(bt)) {
 6135         load_heap_oop(dst, fromAddr);
 6136       } else {
 6137         bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
 6138         load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
 6139       }
 6140       if (toReg->is_stack()) {
 6141         int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
 6142         movq(Address(rsp, st_off), dst);
 6143       }
 6144     } else if (bt == T_DOUBLE) {
 6145       movdbl(toReg->as_XMMRegister(), fromAddr);
 6146     } else {
 6147       assert(bt == T_FLOAT, "must be float");
 6148       movflt(toReg->as_XMMRegister(), fromAddr);
 6149     }
 6150   }
 6151   if (progress && null_check) {
 6152     if (done) {
 6153       jmp(L_notNull);
 6154       bind(L_null);
 6155       // Set IsInit field to zero to signal that the argument is null.
 6156       // Also set all oop fields to zero to make the GC happy.
 6157       stream.reset(sig_index, to_index);
 6158       while (stream.next(toReg, bt)) {
 6159         if (sig->at(stream.sig_index())._offset == -1 ||
 6160             bt == T_OBJECT || bt == T_ARRAY) {
 6161           if (toReg->is_stack()) {
 6162             int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
 6163             movq(Address(rsp, st_off), 0);
 6164           } else {
 6165             xorq(toReg->as_Register(), toReg->as_Register());
 6166           }
 6167         }
 6168       }
 6169       bind(L_notNull);
 6170     } else {
 6171       bind(L_null);
 6172     }
 6173   }
 6174 
 6175   sig_index = stream.sig_index();
 6176   to_index = stream.regs_index();
 6177 
 6178   if (mark_done && reg_state[from->value()] != reg_written) {
 6179     // This is okay because no one else will write to that slot
 6180     reg_state[from->value()] = reg_writable;
 6181   }
 6182   from_index--;
 6183   assert(progress || (start_offset == offset()), "should not emit code");
 6184   return done;
 6185 }
 6186 
 6187 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
 6188                                         VMRegPair* from, int from_count, int& from_index, VMReg to,
 6189                                         RegState reg_state[], Register val_array) {
 6190   assert(sig->at(sig_index)._bt == T_PRIMITIVE_OBJECT, "should be at end delimiter");
 6191   assert(to->is_valid(), "destination must be valid");
 6192 
 6193   if (reg_state[to->value()] == reg_written) {
 6194     skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
 6195     return true; // Already written
 6196   }
 6197 
 6198   // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
 6199   // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
 6200   Register val_obj_tmp = r11;
 6201   Register from_reg_tmp = r14;
 6202   Register tmp1 = r10;
 6203   Register tmp2 = r13;
 6204   Register tmp3 = rbx;
 6205   Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
 6206 
 6207   assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
 6208 
 6209   if (reg_state[to->value()] == reg_readonly) {
 6210     if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
 6211       skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
 6212       return false; // Not yet writable
 6213     }
 6214     val_obj = val_obj_tmp;
 6215   }
 6216 
 6217   int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_PRIMITIVE_OBJECT);
 6218   load_heap_oop(val_obj, Address(val_array, index));
 6219 
 6220   ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
 6221   VMReg fromReg;
 6222   BasicType bt;
 6223   Label L_null;
 6224   while (stream.next(fromReg, bt)) {
 6225     assert(fromReg->is_valid(), "source must be valid");
 6226     reg_state[fromReg->value()] = reg_writable;
 6227 
 6228     int off = sig->at(stream.sig_index())._offset;
 6229     if (off == -1) {
 6230       // Nullable inline type argument, emit null check
 6231       Label L_notNull;
 6232       if (fromReg->is_stack()) {
 6233         int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
 6234         testb(Address(rsp, ld_off), 1);
 6235       } else {
 6236         testb(fromReg->as_Register(), 1);
 6237       }
 6238       jcc(Assembler::notZero, L_notNull);
 6239       movptr(val_obj, 0);
 6240       jmp(L_null);
 6241       bind(L_notNull);
 6242       continue;
 6243     }
 6244 
 6245     assert(off > 0, "offset in object should be positive");
 6246     size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
 6247 
 6248     Address dst(val_obj, off);
 6249     if (!fromReg->is_XMMRegister()) {
 6250       Register src;
 6251       if (fromReg->is_stack()) {
 6252         src = from_reg_tmp;
 6253         int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
 6254         load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
 6255       } else {
 6256         src = fromReg->as_Register();
 6257       }
 6258       assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
 6259       if (is_reference_type(bt)) {
 6260         store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
 6261       } else {
 6262         store_sized_value(dst, src, size_in_bytes);
 6263       }
 6264     } else if (bt == T_DOUBLE) {
 6265       movdbl(dst, fromReg->as_XMMRegister());
 6266     } else {
 6267       assert(bt == T_FLOAT, "must be float");
 6268       movflt(dst, fromReg->as_XMMRegister());
 6269     }
 6270   }
 6271   bind(L_null);
 6272   sig_index = stream.sig_index();
 6273   from_index = stream.regs_index();
 6274 
 6275   assert(reg_state[to->value()] == reg_writable, "must have already been read");
 6276   bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
 6277   assert(success, "to register must be writeable");
 6278   return true;
 6279 }
 6280 
 6281 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
 6282   return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
 6283 }
 6284 
 6285 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
 6286   assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
 6287   if (needs_stack_repair) {
 6288     movq(rbp, Address(rsp, initial_framesize));
 6289     // The stack increment resides just below the saved rbp
 6290     addq(rsp, Address(rsp, initial_framesize - wordSize));
 6291   } else {
 6292     if (initial_framesize > 0) {
 6293       addq(rsp, initial_framesize);
 6294     }
 6295     pop(rbp);
 6296   }
 6297 }
 6298 
 6299 // Clearing constant sized memory using YMM/ZMM registers.
 6300 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
 6301   assert(UseAVX > 2 && VM_Version::supports_avx512vlbw(), "");
 6302   bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
 6303 
 6304   int vector64_count = (cnt & (~0x7)) >> 3;
 6305   cnt = cnt & 0x7;
 6306   const int fill64_per_loop = 4;
 6307   const int max_unrolled_fill64 = 8;
 6308 
 6309   // 64 byte initialization loop.
 6310   vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
 6311   int start64 = 0;
 6312   if (vector64_count > max_unrolled_fill64) {
 6313     Label LOOP;
 6314     Register index = rtmp;
 6315 
 6316     start64 = vector64_count - (vector64_count % fill64_per_loop);
 6317 
 6318     movl(index, 0);
 6319     BIND(LOOP);
 6320     for (int i = 0; i < fill64_per_loop; i++) {
 6321       fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
 6322     }
 6323     addl(index, fill64_per_loop * 64);
 6324     cmpl(index, start64 * 64);
 6325     jccb(Assembler::less, LOOP);
 6326   }
 6327   for (int i = start64; i < vector64_count; i++) {
 6328     fill64(base, i * 64, xtmp, use64byteVector);
 6329   }
 6330 
 6331   // Clear remaining 64 byte tail.
 6332   int disp = vector64_count * 64;
 6333   if (cnt) {
 6334     switch (cnt) {
 6335       case 1:
 6336         movq(Address(base, disp), xtmp);
 6337         break;
 6338       case 2:
 6339         evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
 6340         break;
 6341       case 3:
 6342         movl(rtmp, 0x7);
 6343         kmovwl(mask, rtmp);
 6344         evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
 6345         break;
 6346       case 4:
 6347         evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
 6348         break;
 6349       case 5:
 6350         if (use64byteVector) {
 6351           movl(rtmp, 0x1F);
 6352           kmovwl(mask, rtmp);
 6353           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
 6354         } else {
 6355           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
 6356           movq(Address(base, disp + 32), xtmp);
 6357         }
 6358         break;
 6359       case 6:
 6360         if (use64byteVector) {
 6361           movl(rtmp, 0x3F);
 6362           kmovwl(mask, rtmp);
 6363           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
 6364         } else {
 6365           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
 6366           evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
 6367         }
 6368         break;
 6369       case 7:
 6370         if (use64byteVector) {
 6371           movl(rtmp, 0x7F);
 6372           kmovwl(mask, rtmp);
 6373           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
 6374         } else {
 6375           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
 6376           movl(rtmp, 0x7);
 6377           kmovwl(mask, rtmp);
 6378           evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
 6379         }
 6380         break;
 6381       default:
 6382         fatal("Unexpected length : %d\n",cnt);
 6383         break;
 6384     }
 6385   }
 6386 }
 6387 
 6388 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
 6389                                bool is_large, bool word_copy_only, KRegister mask) {
 6390   // cnt      - number of qwords (8-byte words).
 6391   // base     - start address, qword aligned.
 6392   // is_large - if optimizers know cnt is larger than InitArrayShortSize
 6393   assert(base==rdi, "base register must be edi for rep stos");
 6394   assert(val==rax,   "val register must be eax for rep stos");
 6395   assert(cnt==rcx,   "cnt register must be ecx for rep stos");
 6396   assert(InitArrayShortSize % BytesPerLong == 0,
 6397     "InitArrayShortSize should be the multiple of BytesPerLong");
 6398 
 6399   Label DONE;
 6400 
 6401   if (!is_large) {
 6402     Label LOOP, LONG;
 6403     cmpptr(cnt, InitArrayShortSize/BytesPerLong);
 6404     jccb(Assembler::greater, LONG);
 6405 
 6406     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
 6407 
 6408     decrement(cnt);
 6409     jccb(Assembler::negative, DONE); // Zero length
 6410 
 6411     // Use individual pointer-sized stores for small counts:
 6412     BIND(LOOP);
 6413     movptr(Address(base, cnt, Address::times_ptr), val);
 6414     decrement(cnt);
 6415     jccb(Assembler::greaterEqual, LOOP);
 6416     jmpb(DONE);
 6417 
 6418     BIND(LONG);
 6419   }
 6420 
 6421   // Use longer rep-prefixed ops for non-small counts:
 6422   if (UseFastStosb && !word_copy_only) {
 6423     shlptr(cnt, 3); // convert to number of bytes
 6424     rep_stosb();
 6425   } else if (UseXMMForObjInit) {
 6426     xmm_clear_mem(base, cnt, val, xtmp, mask);
 6427   } else {
 6428     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
 6429     rep_stos();
 6430   }
 6431 
 6432   BIND(DONE);
 6433 }
 6434 
 6435 #endif //COMPILER2_OR_JVMCI
 6436 
 6437 
 6438 void MacroAssembler::generate_fill(BasicType t, bool aligned,
 6439                                    Register to, Register value, Register count,
 6440                                    Register rtmp, XMMRegister xtmp) {
 6441   ShortBranchVerifier sbv(this);
 6442   assert_different_registers(to, value, count, rtmp);
 6443   Label L_exit;
 6444   Label L_fill_2_bytes, L_fill_4_bytes;
 6445 
 6446 #if defined(COMPILER2) && defined(_LP64)
 6447   if(MaxVectorSize >=32 &&
 6448      VM_Version::supports_avx512vlbw() &&
 6449      VM_Version::supports_bmi2()) {
 6450     generate_fill_avx3(t, to, value, count, rtmp, xtmp);
 6451     return;
 6452   }
 6453 #endif
 6454 
 6455   int shift = -1;
 6456   switch (t) {
 6457     case T_BYTE:
 6458       shift = 2;
 6459       break;
 6460     case T_SHORT:
 6461       shift = 1;
 6462       break;
 6463     case T_INT:
 6464       shift = 0;
 6465       break;
 6466     default: ShouldNotReachHere();
 6467   }
 6468 
 6469   if (t == T_BYTE) {
 6470     andl(value, 0xff);
 6471     movl(rtmp, value);
 6472     shll(rtmp, 8);
 6473     orl(value, rtmp);
 6474   }
 6475   if (t == T_SHORT) {
 6476     andl(value, 0xffff);
 6477   }
 6478   if (t == T_BYTE || t == T_SHORT) {
 6479     movl(rtmp, value);
 6480     shll(rtmp, 16);
 6481     orl(value, rtmp);
 6482   }
 6483 
 6484   cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
 6485   jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
 6486   if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
 6487     Label L_skip_align2;
 6488     // align source address at 4 bytes address boundary
 6489     if (t == T_BYTE) {
 6490       Label L_skip_align1;
 6491       // One byte misalignment happens only for byte arrays
 6492       testptr(to, 1);
 6493       jccb(Assembler::zero, L_skip_align1);
 6494       movb(Address(to, 0), value);
 6495       increment(to);
 6496       decrement(count);
 6497       BIND(L_skip_align1);
 6498     }
 6499     // Two bytes misalignment happens only for byte and short (char) arrays
 6500     testptr(to, 2);
 6501     jccb(Assembler::zero, L_skip_align2);
 6502     movw(Address(to, 0), value);
 6503     addptr(to, 2);
 6504     subl(count, 1<<(shift-1));
 6505     BIND(L_skip_align2);
 6506   }
 6507   if (UseSSE < 2) {
 6508     Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
 6509     // Fill 32-byte chunks
 6510     subl(count, 8 << shift);
 6511     jcc(Assembler::less, L_check_fill_8_bytes);
 6512     align(16);
 6513 
 6514     BIND(L_fill_32_bytes_loop);
 6515 
 6516     for (int i = 0; i < 32; i += 4) {
 6517       movl(Address(to, i), value);
 6518     }
 6519 
 6520     addptr(to, 32);
 6521     subl(count, 8 << shift);
 6522     jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
 6523     BIND(L_check_fill_8_bytes);
 6524     addl(count, 8 << shift);
 6525     jccb(Assembler::zero, L_exit);
 6526     jmpb(L_fill_8_bytes);
 6527 
 6528     //
 6529     // length is too short, just fill qwords
 6530     //
 6531     BIND(L_fill_8_bytes_loop);
 6532     movl(Address(to, 0), value);
 6533     movl(Address(to, 4), value);
 6534     addptr(to, 8);
 6535     BIND(L_fill_8_bytes);
 6536     subl(count, 1 << (shift + 1));
 6537     jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
 6538     // fall through to fill 4 bytes
 6539   } else {
 6540     Label L_fill_32_bytes;
 6541     if (!UseUnalignedLoadStores) {
 6542       // align to 8 bytes, we know we are 4 byte aligned to start
 6543       testptr(to, 4);
 6544       jccb(Assembler::zero, L_fill_32_bytes);
 6545       movl(Address(to, 0), value);
 6546       addptr(to, 4);
 6547       subl(count, 1<<shift);
 6548     }
 6549     BIND(L_fill_32_bytes);
 6550     {
 6551       assert( UseSSE >= 2, "supported cpu only" );
 6552       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
 6553       movdl(xtmp, value);
 6554       if (UseAVX >= 2 && UseUnalignedLoadStores) {
 6555         Label L_check_fill_32_bytes;
 6556         if (UseAVX > 2) {
 6557           // Fill 64-byte chunks
 6558           Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
 6559 
 6560           // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
 6561           cmpl(count, VM_Version::avx3_threshold());
 6562           jccb(Assembler::below, L_check_fill_64_bytes_avx2);
 6563 
 6564           vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
 6565 
 6566           subl(count, 16 << shift);
 6567           jccb(Assembler::less, L_check_fill_32_bytes);
 6568           align(16);
 6569 
 6570           BIND(L_fill_64_bytes_loop_avx3);
 6571           evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
 6572           addptr(to, 64);
 6573           subl(count, 16 << shift);
 6574           jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
 6575           jmpb(L_check_fill_32_bytes);
 6576 
 6577           BIND(L_check_fill_64_bytes_avx2);
 6578         }
 6579         // Fill 64-byte chunks
 6580         Label L_fill_64_bytes_loop;
 6581         vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
 6582 
 6583         subl(count, 16 << shift);
 6584         jcc(Assembler::less, L_check_fill_32_bytes);
 6585         align(16);
 6586 
 6587         BIND(L_fill_64_bytes_loop);
 6588         vmovdqu(Address(to, 0), xtmp);
 6589         vmovdqu(Address(to, 32), xtmp);
 6590         addptr(to, 64);
 6591         subl(count, 16 << shift);
 6592         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
 6593 
 6594         BIND(L_check_fill_32_bytes);
 6595         addl(count, 8 << shift);
 6596         jccb(Assembler::less, L_check_fill_8_bytes);
 6597         vmovdqu(Address(to, 0), xtmp);
 6598         addptr(to, 32);
 6599         subl(count, 8 << shift);
 6600 
 6601         BIND(L_check_fill_8_bytes);
 6602         // clean upper bits of YMM registers
 6603         movdl(xtmp, value);
 6604         pshufd(xtmp, xtmp, 0);
 6605       } else {
 6606         // Fill 32-byte chunks
 6607         pshufd(xtmp, xtmp, 0);
 6608 
 6609         subl(count, 8 << shift);
 6610         jcc(Assembler::less, L_check_fill_8_bytes);
 6611         align(16);
 6612 
 6613         BIND(L_fill_32_bytes_loop);
 6614 
 6615         if (UseUnalignedLoadStores) {
 6616           movdqu(Address(to, 0), xtmp);
 6617           movdqu(Address(to, 16), xtmp);
 6618         } else {
 6619           movq(Address(to, 0), xtmp);
 6620           movq(Address(to, 8), xtmp);
 6621           movq(Address(to, 16), xtmp);
 6622           movq(Address(to, 24), xtmp);
 6623         }
 6624 
 6625         addptr(to, 32);
 6626         subl(count, 8 << shift);
 6627         jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
 6628 
 6629         BIND(L_check_fill_8_bytes);
 6630       }
 6631       addl(count, 8 << shift);
 6632       jccb(Assembler::zero, L_exit);
 6633       jmpb(L_fill_8_bytes);
 6634 
 6635       //
 6636       // length is too short, just fill qwords
 6637       //
 6638       BIND(L_fill_8_bytes_loop);
 6639       movq(Address(to, 0), xtmp);
 6640       addptr(to, 8);
 6641       BIND(L_fill_8_bytes);
 6642       subl(count, 1 << (shift + 1));
 6643       jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
 6644     }
 6645   }
 6646   // fill trailing 4 bytes
 6647   BIND(L_fill_4_bytes);
 6648   testl(count, 1<<shift);
 6649   jccb(Assembler::zero, L_fill_2_bytes);
 6650   movl(Address(to, 0), value);
 6651   if (t == T_BYTE || t == T_SHORT) {
 6652     Label L_fill_byte;
 6653     addptr(to, 4);
 6654     BIND(L_fill_2_bytes);
 6655     // fill trailing 2 bytes
 6656     testl(count, 1<<(shift-1));
 6657     jccb(Assembler::zero, L_fill_byte);
 6658     movw(Address(to, 0), value);
 6659     if (t == T_BYTE) {
 6660       addptr(to, 2);
 6661       BIND(L_fill_byte);
 6662       // fill trailing byte
 6663       testl(count, 1);
 6664       jccb(Assembler::zero, L_exit);
 6665       movb(Address(to, 0), value);
 6666     } else {
 6667       BIND(L_fill_byte);
 6668     }
 6669   } else {
 6670     BIND(L_fill_2_bytes);
 6671   }
 6672   BIND(L_exit);
 6673 }
 6674 
 6675 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
 6676   switch(type) {
 6677     case T_BYTE:
 6678     case T_BOOLEAN:
 6679       evpbroadcastb(dst, src, vector_len);
 6680       break;
 6681     case T_SHORT:
 6682     case T_CHAR:
 6683       evpbroadcastw(dst, src, vector_len);
 6684       break;
 6685     case T_INT:
 6686     case T_FLOAT:
 6687       evpbroadcastd(dst, src, vector_len);
 6688       break;
 6689     case T_LONG:
 6690     case T_DOUBLE:
 6691       evpbroadcastq(dst, src, vector_len);
 6692       break;
 6693     default:
 6694       fatal("Unhandled type : %s", type2name(type));
 6695       break;
 6696   }
 6697 }
 6698 
 6699 // encode char[] to byte[] in ISO_8859_1 or ASCII
 6700    //@IntrinsicCandidate
 6701    //private static int implEncodeISOArray(byte[] sa, int sp,
 6702    //byte[] da, int dp, int len) {
 6703    //  int i = 0;
 6704    //  for (; i < len; i++) {
 6705    //    char c = StringUTF16.getChar(sa, sp++);
 6706    //    if (c > '\u00FF')
 6707    //      break;
 6708    //    da[dp++] = (byte)c;
 6709    //  }
 6710    //  return i;
 6711    //}
 6712    //
 6713    //@IntrinsicCandidate
 6714    //private static int implEncodeAsciiArray(char[] sa, int sp,
 6715    //    byte[] da, int dp, int len) {
 6716    //  int i = 0;
 6717    //  for (; i < len; i++) {
 6718    //    char c = sa[sp++];
 6719    //    if (c >= '\u0080')
 6720    //      break;
 6721    //    da[dp++] = (byte)c;
 6722    //  }
 6723    //  return i;
 6724    //}
 6725 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
 6726   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
 6727   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
 6728   Register tmp5, Register result, bool ascii) {
 6729 
 6730   // rsi: src
 6731   // rdi: dst
 6732   // rdx: len
 6733   // rcx: tmp5
 6734   // rax: result
 6735   ShortBranchVerifier sbv(this);
 6736   assert_different_registers(src, dst, len, tmp5, result);
 6737   Label L_done, L_copy_1_char, L_copy_1_char_exit;
 6738 
 6739   int mask = ascii ? 0xff80ff80 : 0xff00ff00;
 6740   int short_mask = ascii ? 0xff80 : 0xff00;
 6741 
 6742   // set result
 6743   xorl(result, result);
 6744   // check for zero length
 6745   testl(len, len);
 6746   jcc(Assembler::zero, L_done);
 6747 
 6748   movl(result, len);
 6749 
 6750   // Setup pointers
 6751   lea(src, Address(src, len, Address::times_2)); // char[]
 6752   lea(dst, Address(dst, len, Address::times_1)); // byte[]
 6753   negptr(len);
 6754 
 6755   if (UseSSE42Intrinsics || UseAVX >= 2) {
 6756     Label L_copy_8_chars, L_copy_8_chars_exit;
 6757     Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
 6758 
 6759     if (UseAVX >= 2) {
 6760       Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
 6761       movl(tmp5, mask);   // create mask to test for Unicode or non-ASCII chars in vector
 6762       movdl(tmp1Reg, tmp5);
 6763       vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
 6764       jmp(L_chars_32_check);
 6765 
 6766       bind(L_copy_32_chars);
 6767       vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
 6768       vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
 6769       vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
 6770       vptest(tmp2Reg, tmp1Reg);       // check for Unicode or non-ASCII chars in vector
 6771       jccb(Assembler::notZero, L_copy_32_chars_exit);
 6772       vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
 6773       vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
 6774       vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
 6775 
 6776       bind(L_chars_32_check);
 6777       addptr(len, 32);
 6778       jcc(Assembler::lessEqual, L_copy_32_chars);
 6779 
 6780       bind(L_copy_32_chars_exit);
 6781       subptr(len, 16);
 6782       jccb(Assembler::greater, L_copy_16_chars_exit);
 6783 
 6784     } else if (UseSSE42Intrinsics) {
 6785       movl(tmp5, mask);   // create mask to test for Unicode or non-ASCII chars in vector
 6786       movdl(tmp1Reg, tmp5);
 6787       pshufd(tmp1Reg, tmp1Reg, 0);
 6788       jmpb(L_chars_16_check);
 6789     }
 6790 
 6791     bind(L_copy_16_chars);
 6792     if (UseAVX >= 2) {
 6793       vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
 6794       vptest(tmp2Reg, tmp1Reg);
 6795       jcc(Assembler::notZero, L_copy_16_chars_exit);
 6796       vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
 6797       vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
 6798     } else {
 6799       if (UseAVX > 0) {
 6800         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
 6801         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
 6802         vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
 6803       } else {
 6804         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
 6805         por(tmp2Reg, tmp3Reg);
 6806         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
 6807         por(tmp2Reg, tmp4Reg);
 6808       }
 6809       ptest(tmp2Reg, tmp1Reg);       // check for Unicode or non-ASCII chars in vector
 6810       jccb(Assembler::notZero, L_copy_16_chars_exit);
 6811       packuswb(tmp3Reg, tmp4Reg);
 6812     }
 6813     movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
 6814 
 6815     bind(L_chars_16_check);
 6816     addptr(len, 16);
 6817     jcc(Assembler::lessEqual, L_copy_16_chars);
 6818 
 6819     bind(L_copy_16_chars_exit);
 6820     if (UseAVX >= 2) {
 6821       // clean upper bits of YMM registers
 6822       vpxor(tmp2Reg, tmp2Reg);
 6823       vpxor(tmp3Reg, tmp3Reg);
 6824       vpxor(tmp4Reg, tmp4Reg);
 6825       movdl(tmp1Reg, tmp5);
 6826       pshufd(tmp1Reg, tmp1Reg, 0);
 6827     }
 6828     subptr(len, 8);
 6829     jccb(Assembler::greater, L_copy_8_chars_exit);
 6830 
 6831     bind(L_copy_8_chars);
 6832     movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
 6833     ptest(tmp3Reg, tmp1Reg);
 6834     jccb(Assembler::notZero, L_copy_8_chars_exit);
 6835     packuswb(tmp3Reg, tmp1Reg);
 6836     movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
 6837     addptr(len, 8);
 6838     jccb(Assembler::lessEqual, L_copy_8_chars);
 6839 
 6840     bind(L_copy_8_chars_exit);
 6841     subptr(len, 8);
 6842     jccb(Assembler::zero, L_done);
 6843   }
 6844 
 6845   bind(L_copy_1_char);
 6846   load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
 6847   testl(tmp5, short_mask);      // check if Unicode or non-ASCII char
 6848   jccb(Assembler::notZero, L_copy_1_char_exit);
 6849   movb(Address(dst, len, Address::times_1, 0), tmp5);
 6850   addptr(len, 1);
 6851   jccb(Assembler::less, L_copy_1_char);
 6852 
 6853   bind(L_copy_1_char_exit);
 6854   addptr(result, len); // len is negative count of not processed elements
 6855 
 6856   bind(L_done);
 6857 }
 6858 
 6859 #ifdef _LP64
 6860 /**
 6861  * Helper for multiply_to_len().
 6862  */
 6863 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
 6864   addq(dest_lo, src1);
 6865   adcq(dest_hi, 0);
 6866   addq(dest_lo, src2);
 6867   adcq(dest_hi, 0);
 6868 }
 6869 
 6870 /**
 6871  * Multiply 64 bit by 64 bit first loop.
 6872  */
 6873 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
 6874                                            Register y, Register y_idx, Register z,
 6875                                            Register carry, Register product,
 6876                                            Register idx, Register kdx) {
 6877   //
 6878   //  jlong carry, x[], y[], z[];
 6879   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
 6880   //    huge_128 product = y[idx] * x[xstart] + carry;
 6881   //    z[kdx] = (jlong)product;
 6882   //    carry  = (jlong)(product >>> 64);
 6883   //  }
 6884   //  z[xstart] = carry;
 6885   //
 6886 
 6887   Label L_first_loop, L_first_loop_exit;
 6888   Label L_one_x, L_one_y, L_multiply;
 6889 
 6890   decrementl(xstart);
 6891   jcc(Assembler::negative, L_one_x);
 6892 
 6893   movq(x_xstart, Address(x, xstart, Address::times_4,  0));
 6894   rorq(x_xstart, 32); // convert big-endian to little-endian
 6895 
 6896   bind(L_first_loop);
 6897   decrementl(idx);
 6898   jcc(Assembler::negative, L_first_loop_exit);
 6899   decrementl(idx);
 6900   jcc(Assembler::negative, L_one_y);
 6901   movq(y_idx, Address(y, idx, Address::times_4,  0));
 6902   rorq(y_idx, 32); // convert big-endian to little-endian
 6903   bind(L_multiply);
 6904   movq(product, x_xstart);
 6905   mulq(y_idx); // product(rax) * y_idx -> rdx:rax
 6906   addq(product, carry);
 6907   adcq(rdx, 0);
 6908   subl(kdx, 2);
 6909   movl(Address(z, kdx, Address::times_4,  4), product);
 6910   shrq(product, 32);
 6911   movl(Address(z, kdx, Address::times_4,  0), product);
 6912   movq(carry, rdx);
 6913   jmp(L_first_loop);
 6914 
 6915   bind(L_one_y);
 6916   movl(y_idx, Address(y,  0));
 6917   jmp(L_multiply);
 6918 
 6919   bind(L_one_x);
 6920   movl(x_xstart, Address(x,  0));
 6921   jmp(L_first_loop);
 6922 
 6923   bind(L_first_loop_exit);
 6924 }
 6925 
 6926 /**
 6927  * Multiply 64 bit by 64 bit and add 128 bit.
 6928  */
 6929 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
 6930                                             Register yz_idx, Register idx,
 6931                                             Register carry, Register product, int offset) {
 6932   //     huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
 6933   //     z[kdx] = (jlong)product;
 6934 
 6935   movq(yz_idx, Address(y, idx, Address::times_4,  offset));
 6936   rorq(yz_idx, 32); // convert big-endian to little-endian
 6937   movq(product, x_xstart);
 6938   mulq(yz_idx);     // product(rax) * yz_idx -> rdx:product(rax)
 6939   movq(yz_idx, Address(z, idx, Address::times_4,  offset));
 6940   rorq(yz_idx, 32); // convert big-endian to little-endian
 6941 
 6942   add2_with_carry(rdx, product, carry, yz_idx);
 6943 
 6944   movl(Address(z, idx, Address::times_4,  offset+4), product);
 6945   shrq(product, 32);
 6946   movl(Address(z, idx, Address::times_4,  offset), product);
 6947 
 6948 }
 6949 
 6950 /**
 6951  * Multiply 128 bit by 128 bit. Unrolled inner loop.
 6952  */
 6953 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
 6954                                              Register yz_idx, Register idx, Register jdx,
 6955                                              Register carry, Register product,
 6956                                              Register carry2) {
 6957   //   jlong carry, x[], y[], z[];
 6958   //   int kdx = ystart+1;
 6959   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
 6960   //     huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
 6961   //     z[kdx+idx+1] = (jlong)product;
 6962   //     jlong carry2  = (jlong)(product >>> 64);
 6963   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
 6964   //     z[kdx+idx] = (jlong)product;
 6965   //     carry  = (jlong)(product >>> 64);
 6966   //   }
 6967   //   idx += 2;
 6968   //   if (idx > 0) {
 6969   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
 6970   //     z[kdx+idx] = (jlong)product;
 6971   //     carry  = (jlong)(product >>> 64);
 6972   //   }
 6973   //
 6974 
 6975   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
 6976 
 6977   movl(jdx, idx);
 6978   andl(jdx, 0xFFFFFFFC);
 6979   shrl(jdx, 2);
 6980 
 6981   bind(L_third_loop);
 6982   subl(jdx, 1);
 6983   jcc(Assembler::negative, L_third_loop_exit);
 6984   subl(idx, 4);
 6985 
 6986   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
 6987   movq(carry2, rdx);
 6988 
 6989   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
 6990   movq(carry, rdx);
 6991   jmp(L_third_loop);
 6992 
 6993   bind (L_third_loop_exit);
 6994 
 6995   andl (idx, 0x3);
 6996   jcc(Assembler::zero, L_post_third_loop_done);
 6997 
 6998   Label L_check_1;
 6999   subl(idx, 2);
 7000   jcc(Assembler::negative, L_check_1);
 7001 
 7002   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
 7003   movq(carry, rdx);
 7004 
 7005   bind (L_check_1);
 7006   addl (idx, 0x2);
 7007   andl (idx, 0x1);
 7008   subl(idx, 1);
 7009   jcc(Assembler::negative, L_post_third_loop_done);
 7010 
 7011   movl(yz_idx, Address(y, idx, Address::times_4,  0));
 7012   movq(product, x_xstart);
 7013   mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
 7014   movl(yz_idx, Address(z, idx, Address::times_4,  0));
 7015 
 7016   add2_with_carry(rdx, product, yz_idx, carry);
 7017 
 7018   movl(Address(z, idx, Address::times_4,  0), product);
 7019   shrq(product, 32);
 7020 
 7021   shlq(rdx, 32);
 7022   orq(product, rdx);
 7023   movq(carry, product);
 7024 
 7025   bind(L_post_third_loop_done);
 7026 }
 7027 
 7028 /**
 7029  * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
 7030  *
 7031  */
 7032 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
 7033                                                   Register carry, Register carry2,
 7034                                                   Register idx, Register jdx,
 7035                                                   Register yz_idx1, Register yz_idx2,
 7036                                                   Register tmp, Register tmp3, Register tmp4) {
 7037   assert(UseBMI2Instructions, "should be used only when BMI2 is available");
 7038 
 7039   //   jlong carry, x[], y[], z[];
 7040   //   int kdx = ystart+1;
 7041   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
 7042   //     huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
 7043   //     jlong carry2  = (jlong)(tmp3 >>> 64);
 7044   //     huge_128 tmp4 = (y[idx]   * rdx) + z[kdx+idx] + carry2;
 7045   //     carry  = (jlong)(tmp4 >>> 64);
 7046   //     z[kdx+idx+1] = (jlong)tmp3;
 7047   //     z[kdx+idx] = (jlong)tmp4;
 7048   //   }
 7049   //   idx += 2;
 7050   //   if (idx > 0) {
 7051   //     yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
 7052   //     z[kdx+idx] = (jlong)yz_idx1;
 7053   //     carry  = (jlong)(yz_idx1 >>> 64);
 7054   //   }
 7055   //
 7056 
 7057   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
 7058 
 7059   movl(jdx, idx);
 7060   andl(jdx, 0xFFFFFFFC);
 7061   shrl(jdx, 2);
 7062 
 7063   bind(L_third_loop);
 7064   subl(jdx, 1);
 7065   jcc(Assembler::negative, L_third_loop_exit);
 7066   subl(idx, 4);
 7067 
 7068   movq(yz_idx1,  Address(y, idx, Address::times_4,  8));
 7069   rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
 7070   movq(yz_idx2, Address(y, idx, Address::times_4,  0));
 7071   rorxq(yz_idx2, yz_idx2, 32);
 7072 
 7073   mulxq(tmp4, tmp3, yz_idx1);  //  yz_idx1 * rdx -> tmp4:tmp3
 7074   mulxq(carry2, tmp, yz_idx2); //  yz_idx2 * rdx -> carry2:tmp
 7075 
 7076   movq(yz_idx1,  Address(z, idx, Address::times_4,  8));
 7077   rorxq(yz_idx1, yz_idx1, 32);
 7078   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
 7079   rorxq(yz_idx2, yz_idx2, 32);
 7080 
 7081   if (VM_Version::supports_adx()) {
 7082     adcxq(tmp3, carry);
 7083     adoxq(tmp3, yz_idx1);
 7084 
 7085     adcxq(tmp4, tmp);
 7086     adoxq(tmp4, yz_idx2);
 7087 
 7088     movl(carry, 0); // does not affect flags
 7089     adcxq(carry2, carry);
 7090     adoxq(carry2, carry);
 7091   } else {
 7092     add2_with_carry(tmp4, tmp3, carry, yz_idx1);
 7093     add2_with_carry(carry2, tmp4, tmp, yz_idx2);
 7094   }
 7095   movq(carry, carry2);
 7096 
 7097   movl(Address(z, idx, Address::times_4, 12), tmp3);
 7098   shrq(tmp3, 32);
 7099   movl(Address(z, idx, Address::times_4,  8), tmp3);
 7100 
 7101   movl(Address(z, idx, Address::times_4,  4), tmp4);
 7102   shrq(tmp4, 32);
 7103   movl(Address(z, idx, Address::times_4,  0), tmp4);
 7104 
 7105   jmp(L_third_loop);
 7106 
 7107   bind (L_third_loop_exit);
 7108 
 7109   andl (idx, 0x3);
 7110   jcc(Assembler::zero, L_post_third_loop_done);
 7111 
 7112   Label L_check_1;
 7113   subl(idx, 2);
 7114   jcc(Assembler::negative, L_check_1);
 7115 
 7116   movq(yz_idx1, Address(y, idx, Address::times_4,  0));
 7117   rorxq(yz_idx1, yz_idx1, 32);
 7118   mulxq(tmp4, tmp3, yz_idx1); //  yz_idx1 * rdx -> tmp4:tmp3
 7119   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
 7120   rorxq(yz_idx2, yz_idx2, 32);
 7121 
 7122   add2_with_carry(tmp4, tmp3, carry, yz_idx2);
 7123 
 7124   movl(Address(z, idx, Address::times_4,  4), tmp3);
 7125   shrq(tmp3, 32);
 7126   movl(Address(z, idx, Address::times_4,  0), tmp3);
 7127   movq(carry, tmp4);
 7128 
 7129   bind (L_check_1);
 7130   addl (idx, 0x2);
 7131   andl (idx, 0x1);
 7132   subl(idx, 1);
 7133   jcc(Assembler::negative, L_post_third_loop_done);
 7134   movl(tmp4, Address(y, idx, Address::times_4,  0));
 7135   mulxq(carry2, tmp3, tmp4);  //  tmp4 * rdx -> carry2:tmp3
 7136   movl(tmp4, Address(z, idx, Address::times_4,  0));
 7137 
 7138   add2_with_carry(carry2, tmp3, tmp4, carry);
 7139 
 7140   movl(Address(z, idx, Address::times_4,  0), tmp3);
 7141   shrq(tmp3, 32);
 7142 
 7143   shlq(carry2, 32);
 7144   orq(tmp3, carry2);
 7145   movq(carry, tmp3);
 7146 
 7147   bind(L_post_third_loop_done);
 7148 }
 7149 
 7150 /**
 7151  * Code for BigInteger::multiplyToLen() intrinsic.
 7152  *
 7153  * rdi: x
 7154  * rax: xlen
 7155  * rsi: y
 7156  * rcx: ylen
 7157  * r8:  z
 7158  * r11: zlen
 7159  * r12: tmp1
 7160  * r13: tmp2
 7161  * r14: tmp3
 7162  * r15: tmp4
 7163  * rbx: tmp5
 7164  *
 7165  */
 7166 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
 7167                                      Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
 7168   ShortBranchVerifier sbv(this);
 7169   assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
 7170 
 7171   push(tmp1);
 7172   push(tmp2);
 7173   push(tmp3);
 7174   push(tmp4);
 7175   push(tmp5);
 7176 
 7177   push(xlen);
 7178   push(zlen);
 7179 
 7180   const Register idx = tmp1;
 7181   const Register kdx = tmp2;
 7182   const Register xstart = tmp3;
 7183 
 7184   const Register y_idx = tmp4;
 7185   const Register carry = tmp5;
 7186   const Register product  = xlen;
 7187   const Register x_xstart = zlen;  // reuse register
 7188 
 7189   // First Loop.
 7190   //
 7191   //  final static long LONG_MASK = 0xffffffffL;
 7192   //  int xstart = xlen - 1;
 7193   //  int ystart = ylen - 1;
 7194   //  long carry = 0;
 7195   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
 7196   //    long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
 7197   //    z[kdx] = (int)product;
 7198   //    carry = product >>> 32;
 7199   //  }
 7200   //  z[xstart] = (int)carry;
 7201   //
 7202 
 7203   movl(idx, ylen);      // idx = ylen;
 7204   movl(kdx, zlen);      // kdx = xlen+ylen;
 7205   xorq(carry, carry);   // carry = 0;
 7206 
 7207   Label L_done;
 7208 
 7209   movl(xstart, xlen);
 7210   decrementl(xstart);
 7211   jcc(Assembler::negative, L_done);
 7212 
 7213   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
 7214 
 7215   Label L_second_loop;
 7216   testl(kdx, kdx);
 7217   jcc(Assembler::zero, L_second_loop);
 7218 
 7219   Label L_carry;
 7220   subl(kdx, 1);
 7221   jcc(Assembler::zero, L_carry);
 7222 
 7223   movl(Address(z, kdx, Address::times_4,  0), carry);
 7224   shrq(carry, 32);
 7225   subl(kdx, 1);
 7226 
 7227   bind(L_carry);
 7228   movl(Address(z, kdx, Address::times_4,  0), carry);
 7229 
 7230   // Second and third (nested) loops.
 7231   //
 7232   // for (int i = xstart-1; i >= 0; i--) { // Second loop
 7233   //   carry = 0;
 7234   //   for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
 7235   //     long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
 7236   //                    (z[k] & LONG_MASK) + carry;
 7237   //     z[k] = (int)product;
 7238   //     carry = product >>> 32;
 7239   //   }
 7240   //   z[i] = (int)carry;
 7241   // }
 7242   //
 7243   // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
 7244 
 7245   const Register jdx = tmp1;
 7246 
 7247   bind(L_second_loop);
 7248   xorl(carry, carry);    // carry = 0;
 7249   movl(jdx, ylen);       // j = ystart+1
 7250 
 7251   subl(xstart, 1);       // i = xstart-1;
 7252   jcc(Assembler::negative, L_done);
 7253 
 7254   push (z);
 7255 
 7256   Label L_last_x;
 7257   lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
 7258   subl(xstart, 1);       // i = xstart-1;
 7259   jcc(Assembler::negative, L_last_x);
 7260 
 7261   if (UseBMI2Instructions) {
 7262     movq(rdx,  Address(x, xstart, Address::times_4,  0));
 7263     rorxq(rdx, rdx, 32); // convert big-endian to little-endian
 7264   } else {
 7265     movq(x_xstart, Address(x, xstart, Address::times_4,  0));
 7266     rorq(x_xstart, 32);  // convert big-endian to little-endian
 7267   }
 7268 
 7269   Label L_third_loop_prologue;
 7270   bind(L_third_loop_prologue);
 7271 
 7272   push (x);
 7273   push (xstart);
 7274   push (ylen);
 7275 
 7276 
 7277   if (UseBMI2Instructions) {
 7278     multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
 7279   } else { // !UseBMI2Instructions
 7280     multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
 7281   }
 7282 
 7283   pop(ylen);
 7284   pop(xlen);
 7285   pop(x);
 7286   pop(z);
 7287 
 7288   movl(tmp3, xlen);
 7289   addl(tmp3, 1);
 7290   movl(Address(z, tmp3, Address::times_4,  0), carry);
 7291   subl(tmp3, 1);
 7292   jccb(Assembler::negative, L_done);
 7293 
 7294   shrq(carry, 32);
 7295   movl(Address(z, tmp3, Address::times_4,  0), carry);
 7296   jmp(L_second_loop);
 7297 
 7298   // Next infrequent code is moved outside loops.
 7299   bind(L_last_x);
 7300   if (UseBMI2Instructions) {
 7301     movl(rdx, Address(x,  0));
 7302   } else {
 7303     movl(x_xstart, Address(x,  0));
 7304   }
 7305   jmp(L_third_loop_prologue);
 7306 
 7307   bind(L_done);
 7308 
 7309   pop(zlen);
 7310   pop(xlen);
 7311 
 7312   pop(tmp5);
 7313   pop(tmp4);
 7314   pop(tmp3);
 7315   pop(tmp2);
 7316   pop(tmp1);
 7317 }
 7318 
 7319 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
 7320   Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
 7321   assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
 7322   Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
 7323   Label VECTOR8_TAIL, VECTOR4_TAIL;
 7324   Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
 7325   Label SAME_TILL_END, DONE;
 7326   Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
 7327 
 7328   //scale is in rcx in both Win64 and Unix
 7329   ShortBranchVerifier sbv(this);
 7330 
 7331   shlq(length);
 7332   xorq(result, result);
 7333 
 7334   if ((AVX3Threshold == 0) && (UseAVX > 2) &&
 7335       VM_Version::supports_avx512vlbw()) {
 7336     Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
 7337 
 7338     cmpq(length, 64);
 7339     jcc(Assembler::less, VECTOR32_TAIL);
 7340 
 7341     movq(tmp1, length);
 7342     andq(tmp1, 0x3F);      // tail count
 7343     andq(length, ~(0x3F)); //vector count
 7344 
 7345     bind(VECTOR64_LOOP);
 7346     // AVX512 code to compare 64 byte vectors.
 7347     evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
 7348     evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
 7349     kortestql(k7, k7);
 7350     jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL);     // mismatch
 7351     addq(result, 64);
 7352     subq(length, 64);
 7353     jccb(Assembler::notZero, VECTOR64_LOOP);
 7354 
 7355     //bind(VECTOR64_TAIL);
 7356     testq(tmp1, tmp1);
 7357     jcc(Assembler::zero, SAME_TILL_END);
 7358 
 7359     //bind(VECTOR64_TAIL);
 7360     // AVX512 code to compare up to 63 byte vectors.
 7361     mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
 7362     shlxq(tmp2, tmp2, tmp1);
 7363     notq(tmp2);
 7364     kmovql(k3, tmp2);
 7365 
 7366     evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
 7367     evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
 7368 
 7369     ktestql(k7, k3);
 7370     jcc(Assembler::below, SAME_TILL_END);     // not mismatch
 7371 
 7372     bind(VECTOR64_NOT_EQUAL);
 7373     kmovql(tmp1, k7);
 7374     notq(tmp1);
 7375     tzcntq(tmp1, tmp1);
 7376     addq(result, tmp1);
 7377     shrq(result);
 7378     jmp(DONE);
 7379     bind(VECTOR32_TAIL);
 7380   }
 7381 
 7382   cmpq(length, 8);
 7383   jcc(Assembler::equal, VECTOR8_LOOP);
 7384   jcc(Assembler::less, VECTOR4_TAIL);
 7385 
 7386   if (UseAVX >= 2) {
 7387     Label VECTOR16_TAIL, VECTOR32_LOOP;
 7388 
 7389     cmpq(length, 16);
 7390     jcc(Assembler::equal, VECTOR16_LOOP);
 7391     jcc(Assembler::less, VECTOR8_LOOP);
 7392 
 7393     cmpq(length, 32);
 7394     jccb(Assembler::less, VECTOR16_TAIL);
 7395 
 7396     subq(length, 32);
 7397     bind(VECTOR32_LOOP);
 7398     vmovdqu(rymm0, Address(obja, result));
 7399     vmovdqu(rymm1, Address(objb, result));
 7400     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
 7401     vptest(rymm2, rymm2);
 7402     jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
 7403     addq(result, 32);
 7404     subq(length, 32);
 7405     jcc(Assembler::greaterEqual, VECTOR32_LOOP);
 7406     addq(length, 32);
 7407     jcc(Assembler::equal, SAME_TILL_END);
 7408     //falling through if less than 32 bytes left //close the branch here.
 7409 
 7410     bind(VECTOR16_TAIL);
 7411     cmpq(length, 16);
 7412     jccb(Assembler::less, VECTOR8_TAIL);
 7413     bind(VECTOR16_LOOP);
 7414     movdqu(rymm0, Address(obja, result));
 7415     movdqu(rymm1, Address(objb, result));
 7416     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
 7417     ptest(rymm2, rymm2);
 7418     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
 7419     addq(result, 16);
 7420     subq(length, 16);
 7421     jcc(Assembler::equal, SAME_TILL_END);
 7422     //falling through if less than 16 bytes left
 7423   } else {//regular intrinsics
 7424 
 7425     cmpq(length, 16);
 7426     jccb(Assembler::less, VECTOR8_TAIL);
 7427 
 7428     subq(length, 16);
 7429     bind(VECTOR16_LOOP);
 7430     movdqu(rymm0, Address(obja, result));
 7431     movdqu(rymm1, Address(objb, result));
 7432     pxor(rymm0, rymm1);
 7433     ptest(rymm0, rymm0);
 7434     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
 7435     addq(result, 16);
 7436     subq(length, 16);
 7437     jccb(Assembler::greaterEqual, VECTOR16_LOOP);
 7438     addq(length, 16);
 7439     jcc(Assembler::equal, SAME_TILL_END);
 7440     //falling through if less than 16 bytes left
 7441   }
 7442 
 7443   bind(VECTOR8_TAIL);
 7444   cmpq(length, 8);
 7445   jccb(Assembler::less, VECTOR4_TAIL);
 7446   bind(VECTOR8_LOOP);
 7447   movq(tmp1, Address(obja, result));
 7448   movq(tmp2, Address(objb, result));
 7449   xorq(tmp1, tmp2);
 7450   testq(tmp1, tmp1);
 7451   jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
 7452   addq(result, 8);
 7453   subq(length, 8);
 7454   jcc(Assembler::equal, SAME_TILL_END);
 7455   //falling through if less than 8 bytes left
 7456 
 7457   bind(VECTOR4_TAIL);
 7458   cmpq(length, 4);
 7459   jccb(Assembler::less, BYTES_TAIL);
 7460   bind(VECTOR4_LOOP);
 7461   movl(tmp1, Address(obja, result));
 7462   xorl(tmp1, Address(objb, result));
 7463   testl(tmp1, tmp1);
 7464   jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
 7465   addq(result, 4);
 7466   subq(length, 4);
 7467   jcc(Assembler::equal, SAME_TILL_END);
 7468   //falling through if less than 4 bytes left
 7469 
 7470   bind(BYTES_TAIL);
 7471   bind(BYTES_LOOP);
 7472   load_unsigned_byte(tmp1, Address(obja, result));
 7473   load_unsigned_byte(tmp2, Address(objb, result));
 7474   xorl(tmp1, tmp2);
 7475   testl(tmp1, tmp1);
 7476   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
 7477   decq(length);
 7478   jcc(Assembler::zero, SAME_TILL_END);
 7479   incq(result);
 7480   load_unsigned_byte(tmp1, Address(obja, result));
 7481   load_unsigned_byte(tmp2, Address(objb, result));
 7482   xorl(tmp1, tmp2);
 7483   testl(tmp1, tmp1);
 7484   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
 7485   decq(length);
 7486   jcc(Assembler::zero, SAME_TILL_END);
 7487   incq(result);
 7488   load_unsigned_byte(tmp1, Address(obja, result));
 7489   load_unsigned_byte(tmp2, Address(objb, result));
 7490   xorl(tmp1, tmp2);
 7491   testl(tmp1, tmp1);
 7492   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
 7493   jmp(SAME_TILL_END);
 7494 
 7495   if (UseAVX >= 2) {
 7496     bind(VECTOR32_NOT_EQUAL);
 7497     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
 7498     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
 7499     vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
 7500     vpmovmskb(tmp1, rymm0);
 7501     bsfq(tmp1, tmp1);
 7502     addq(result, tmp1);
 7503     shrq(result);
 7504     jmp(DONE);
 7505   }
 7506 
 7507   bind(VECTOR16_NOT_EQUAL);
 7508   if (UseAVX >= 2) {
 7509     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
 7510     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
 7511     pxor(rymm0, rymm2);
 7512   } else {
 7513     pcmpeqb(rymm2, rymm2);
 7514     pxor(rymm0, rymm1);
 7515     pcmpeqb(rymm0, rymm1);
 7516     pxor(rymm0, rymm2);
 7517   }
 7518   pmovmskb(tmp1, rymm0);
 7519   bsfq(tmp1, tmp1);
 7520   addq(result, tmp1);
 7521   shrq(result);
 7522   jmpb(DONE);
 7523 
 7524   bind(VECTOR8_NOT_EQUAL);
 7525   bind(VECTOR4_NOT_EQUAL);
 7526   bsfq(tmp1, tmp1);
 7527   shrq(tmp1, 3);
 7528   addq(result, tmp1);
 7529   bind(BYTES_NOT_EQUAL);
 7530   shrq(result);
 7531   jmpb(DONE);
 7532 
 7533   bind(SAME_TILL_END);
 7534   mov64(result, -1);
 7535 
 7536   bind(DONE);
 7537 }
 7538 
 7539 //Helper functions for square_to_len()
 7540 
 7541 /**
 7542  * Store the squares of x[], right shifted one bit (divided by 2) into z[]
 7543  * Preserves x and z and modifies rest of the registers.
 7544  */
 7545 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
 7546   // Perform square and right shift by 1
 7547   // Handle odd xlen case first, then for even xlen do the following
 7548   // jlong carry = 0;
 7549   // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
 7550   //     huge_128 product = x[j:j+1] * x[j:j+1];
 7551   //     z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
 7552   //     z[i+2:i+3] = (jlong)(product >>> 1);
 7553   //     carry = (jlong)product;
 7554   // }
 7555 
 7556   xorq(tmp5, tmp5);     // carry
 7557   xorq(rdxReg, rdxReg);
 7558   xorl(tmp1, tmp1);     // index for x
 7559   xorl(tmp4, tmp4);     // index for z
 7560 
 7561   Label L_first_loop, L_first_loop_exit;
 7562 
 7563   testl(xlen, 1);
 7564   jccb(Assembler::zero, L_first_loop); //jump if xlen is even
 7565 
 7566   // Square and right shift by 1 the odd element using 32 bit multiply
 7567   movl(raxReg, Address(x, tmp1, Address::times_4, 0));
 7568   imulq(raxReg, raxReg);
 7569   shrq(raxReg, 1);
 7570   adcq(tmp5, 0);
 7571   movq(Address(z, tmp4, Address::times_4, 0), raxReg);
 7572   incrementl(tmp1);
 7573   addl(tmp4, 2);
 7574 
 7575   // Square and  right shift by 1 the rest using 64 bit multiply
 7576   bind(L_first_loop);
 7577   cmpptr(tmp1, xlen);
 7578   jccb(Assembler::equal, L_first_loop_exit);
 7579 
 7580   // Square
 7581   movq(raxReg, Address(x, tmp1, Address::times_4,  0));
 7582   rorq(raxReg, 32);    // convert big-endian to little-endian
 7583   mulq(raxReg);        // 64-bit multiply rax * rax -> rdx:rax
 7584 
 7585   // Right shift by 1 and save carry
 7586   shrq(tmp5, 1);       // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
 7587   rcrq(rdxReg, 1);
 7588   rcrq(raxReg, 1);
 7589   adcq(tmp5, 0);
 7590 
 7591   // Store result in z
 7592   movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
 7593   movq(Address(z, tmp4, Address::times_4, 8), raxReg);
 7594 
 7595   // Update indices for x and z
 7596   addl(tmp1, 2);
 7597   addl(tmp4, 4);
 7598   jmp(L_first_loop);
 7599 
 7600   bind(L_first_loop_exit);
 7601 }
 7602 
 7603 
 7604 /**
 7605  * Perform the following multiply add operation using BMI2 instructions
 7606  * carry:sum = sum + op1*op2 + carry
 7607  * op2 should be in rdx
 7608  * op2 is preserved, all other registers are modified
 7609  */
 7610 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
 7611   // assert op2 is rdx
 7612   mulxq(tmp2, op1, op1);  //  op1 * op2 -> tmp2:op1
 7613   addq(sum, carry);
 7614   adcq(tmp2, 0);
 7615   addq(sum, op1);
 7616   adcq(tmp2, 0);
 7617   movq(carry, tmp2);
 7618 }
 7619 
 7620 /**
 7621  * Perform the following multiply add operation:
 7622  * carry:sum = sum + op1*op2 + carry
 7623  * Preserves op1, op2 and modifies rest of registers
 7624  */
 7625 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
 7626   // rdx:rax = op1 * op2
 7627   movq(raxReg, op2);
 7628   mulq(op1);
 7629 
 7630   //  rdx:rax = sum + carry + rdx:rax
 7631   addq(sum, carry);
 7632   adcq(rdxReg, 0);
 7633   addq(sum, raxReg);
 7634   adcq(rdxReg, 0);
 7635 
 7636   // carry:sum = rdx:sum
 7637   movq(carry, rdxReg);
 7638 }
 7639 
 7640 /**
 7641  * Add 64 bit long carry into z[] with carry propagation.
 7642  * Preserves z and carry register values and modifies rest of registers.
 7643  *
 7644  */
 7645 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
 7646   Label L_fourth_loop, L_fourth_loop_exit;
 7647 
 7648   movl(tmp1, 1);
 7649   subl(zlen, 2);
 7650   addq(Address(z, zlen, Address::times_4, 0), carry);
 7651 
 7652   bind(L_fourth_loop);
 7653   jccb(Assembler::carryClear, L_fourth_loop_exit);
 7654   subl(zlen, 2);
 7655   jccb(Assembler::negative, L_fourth_loop_exit);
 7656   addq(Address(z, zlen, Address::times_4, 0), tmp1);
 7657   jmp(L_fourth_loop);
 7658   bind(L_fourth_loop_exit);
 7659 }
 7660 
 7661 /**
 7662  * Shift z[] left by 1 bit.
 7663  * Preserves x, len, z and zlen registers and modifies rest of the registers.
 7664  *
 7665  */
 7666 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
 7667 
 7668   Label L_fifth_loop, L_fifth_loop_exit;
 7669 
 7670   // Fifth loop
 7671   // Perform primitiveLeftShift(z, zlen, 1)
 7672 
 7673   const Register prev_carry = tmp1;
 7674   const Register new_carry = tmp4;
 7675   const Register value = tmp2;
 7676   const Register zidx = tmp3;
 7677 
 7678   // int zidx, carry;
 7679   // long value;
 7680   // carry = 0;
 7681   // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
 7682   //    (carry:value)  = (z[i] << 1) | carry ;
 7683   //    z[i] = value;
 7684   // }
 7685 
 7686   movl(zidx, zlen);
 7687   xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
 7688 
 7689   bind(L_fifth_loop);
 7690   decl(zidx);  // Use decl to preserve carry flag
 7691   decl(zidx);
 7692   jccb(Assembler::negative, L_fifth_loop_exit);
 7693 
 7694   if (UseBMI2Instructions) {
 7695      movq(value, Address(z, zidx, Address::times_4, 0));
 7696      rclq(value, 1);
 7697      rorxq(value, value, 32);
 7698      movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
 7699   }
 7700   else {
 7701     // clear new_carry
 7702     xorl(new_carry, new_carry);
 7703 
 7704     // Shift z[i] by 1, or in previous carry and save new carry
 7705     movq(value, Address(z, zidx, Address::times_4, 0));
 7706     shlq(value, 1);
 7707     adcl(new_carry, 0);
 7708 
 7709     orq(value, prev_carry);
 7710     rorq(value, 0x20);
 7711     movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
 7712 
 7713     // Set previous carry = new carry
 7714     movl(prev_carry, new_carry);
 7715   }
 7716   jmp(L_fifth_loop);
 7717 
 7718   bind(L_fifth_loop_exit);
 7719 }
 7720 
 7721 
 7722 /**
 7723  * Code for BigInteger::squareToLen() intrinsic
 7724  *
 7725  * rdi: x
 7726  * rsi: len
 7727  * r8:  z
 7728  * rcx: zlen
 7729  * r12: tmp1
 7730  * r13: tmp2
 7731  * r14: tmp3
 7732  * r15: tmp4
 7733  * rbx: tmp5
 7734  *
 7735  */
 7736 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
 7737 
 7738   Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
 7739   push(tmp1);
 7740   push(tmp2);
 7741   push(tmp3);
 7742   push(tmp4);
 7743   push(tmp5);
 7744 
 7745   // First loop
 7746   // Store the squares, right shifted one bit (i.e., divided by 2).
 7747   square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
 7748 
 7749   // Add in off-diagonal sums.
 7750   //
 7751   // Second, third (nested) and fourth loops.
 7752   // zlen +=2;
 7753   // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
 7754   //    carry = 0;
 7755   //    long op2 = x[xidx:xidx+1];
 7756   //    for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
 7757   //       k -= 2;
 7758   //       long op1 = x[j:j+1];
 7759   //       long sum = z[k:k+1];
 7760   //       carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
 7761   //       z[k:k+1] = sum;
 7762   //    }
 7763   //    add_one_64(z, k, carry, tmp_regs);
 7764   // }
 7765 
 7766   const Register carry = tmp5;
 7767   const Register sum = tmp3;
 7768   const Register op1 = tmp4;
 7769   Register op2 = tmp2;
 7770 
 7771   push(zlen);
 7772   push(len);
 7773   addl(zlen,2);
 7774   bind(L_second_loop);
 7775   xorq(carry, carry);
 7776   subl(zlen, 4);
 7777   subl(len, 2);
 7778   push(zlen);
 7779   push(len);
 7780   cmpl(len, 0);
 7781   jccb(Assembler::lessEqual, L_second_loop_exit);
 7782 
 7783   // Multiply an array by one 64 bit long.
 7784   if (UseBMI2Instructions) {
 7785     op2 = rdxReg;
 7786     movq(op2, Address(x, len, Address::times_4,  0));
 7787     rorxq(op2, op2, 32);
 7788   }
 7789   else {
 7790     movq(op2, Address(x, len, Address::times_4,  0));
 7791     rorq(op2, 32);
 7792   }
 7793 
 7794   bind(L_third_loop);
 7795   decrementl(len);
 7796   jccb(Assembler::negative, L_third_loop_exit);
 7797   decrementl(len);
 7798   jccb(Assembler::negative, L_last_x);
 7799 
 7800   movq(op1, Address(x, len, Address::times_4,  0));
 7801   rorq(op1, 32);
 7802 
 7803   bind(L_multiply);
 7804   subl(zlen, 2);
 7805   movq(sum, Address(z, zlen, Address::times_4,  0));
 7806 
 7807   // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
 7808   if (UseBMI2Instructions) {
 7809     multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
 7810   }
 7811   else {
 7812     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
 7813   }
 7814 
 7815   movq(Address(z, zlen, Address::times_4, 0), sum);
 7816 
 7817   jmp(L_third_loop);
 7818   bind(L_third_loop_exit);
 7819 
 7820   // Fourth loop
 7821   // Add 64 bit long carry into z with carry propagation.
 7822   // Uses offsetted zlen.
 7823   add_one_64(z, zlen, carry, tmp1);
 7824 
 7825   pop(len);
 7826   pop(zlen);
 7827   jmp(L_second_loop);
 7828 
 7829   // Next infrequent code is moved outside loops.
 7830   bind(L_last_x);
 7831   movl(op1, Address(x, 0));
 7832   jmp(L_multiply);
 7833 
 7834   bind(L_second_loop_exit);
 7835   pop(len);
 7836   pop(zlen);
 7837   pop(len);
 7838   pop(zlen);
 7839 
 7840   // Fifth loop
 7841   // Shift z left 1 bit.
 7842   lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
 7843 
 7844   // z[zlen-1] |= x[len-1] & 1;
 7845   movl(tmp3, Address(x, len, Address::times_4, -4));
 7846   andl(tmp3, 1);
 7847   orl(Address(z, zlen, Address::times_4,  -4), tmp3);
 7848 
 7849   pop(tmp5);
 7850   pop(tmp4);
 7851   pop(tmp3);
 7852   pop(tmp2);
 7853   pop(tmp1);
 7854 }
 7855 
 7856 /**
 7857  * Helper function for mul_add()
 7858  * Multiply the in[] by int k and add to out[] starting at offset offs using
 7859  * 128 bit by 32 bit multiply and return the carry in tmp5.
 7860  * Only quad int aligned length of in[] is operated on in this function.
 7861  * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
 7862  * This function preserves out, in and k registers.
 7863  * len and offset point to the appropriate index in "in" & "out" correspondingly
 7864  * tmp5 has the carry.
 7865  * other registers are temporary and are modified.
 7866  *
 7867  */
 7868 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
 7869   Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
 7870   Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
 7871 
 7872   Label L_first_loop, L_first_loop_exit;
 7873 
 7874   movl(tmp1, len);
 7875   shrl(tmp1, 2);
 7876 
 7877   bind(L_first_loop);
 7878   subl(tmp1, 1);
 7879   jccb(Assembler::negative, L_first_loop_exit);
 7880 
 7881   subl(len, 4);
 7882   subl(offset, 4);
 7883 
 7884   Register op2 = tmp2;
 7885   const Register sum = tmp3;
 7886   const Register op1 = tmp4;
 7887   const Register carry = tmp5;
 7888 
 7889   if (UseBMI2Instructions) {
 7890     op2 = rdxReg;
 7891   }
 7892 
 7893   movq(op1, Address(in, len, Address::times_4,  8));
 7894   rorq(op1, 32);
 7895   movq(sum, Address(out, offset, Address::times_4,  8));
 7896   rorq(sum, 32);
 7897   if (UseBMI2Instructions) {
 7898     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
 7899   }
 7900   else {
 7901     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
 7902   }
 7903   // Store back in big endian from little endian
 7904   rorq(sum, 0x20);
 7905   movq(Address(out, offset, Address::times_4,  8), sum);
 7906 
 7907   movq(op1, Address(in, len, Address::times_4,  0));
 7908   rorq(op1, 32);
 7909   movq(sum, Address(out, offset, Address::times_4,  0));
 7910   rorq(sum, 32);
 7911   if (UseBMI2Instructions) {
 7912     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
 7913   }
 7914   else {
 7915     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
 7916   }
 7917   // Store back in big endian from little endian
 7918   rorq(sum, 0x20);
 7919   movq(Address(out, offset, Address::times_4,  0), sum);
 7920 
 7921   jmp(L_first_loop);
 7922   bind(L_first_loop_exit);
 7923 }
 7924 
 7925 /**
 7926  * Code for BigInteger::mulAdd() intrinsic
 7927  *
 7928  * rdi: out
 7929  * rsi: in
 7930  * r11: offs (out.length - offset)
 7931  * rcx: len
 7932  * r8:  k
 7933  * r12: tmp1
 7934  * r13: tmp2
 7935  * r14: tmp3
 7936  * r15: tmp4
 7937  * rbx: tmp5
 7938  * Multiply the in[] by word k and add to out[], return the carry in rax
 7939  */
 7940 void MacroAssembler::mul_add(Register out, Register in, Register offs,
 7941    Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
 7942    Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
 7943 
 7944   Label L_carry, L_last_in, L_done;
 7945 
 7946 // carry = 0;
 7947 // for (int j=len-1; j >= 0; j--) {
 7948 //    long product = (in[j] & LONG_MASK) * kLong +
 7949 //                   (out[offs] & LONG_MASK) + carry;
 7950 //    out[offs--] = (int)product;
 7951 //    carry = product >>> 32;
 7952 // }
 7953 //
 7954   push(tmp1);
 7955   push(tmp2);
 7956   push(tmp3);
 7957   push(tmp4);
 7958   push(tmp5);
 7959 
 7960   Register op2 = tmp2;
 7961   const Register sum = tmp3;
 7962   const Register op1 = tmp4;
 7963   const Register carry =  tmp5;
 7964 
 7965   if (UseBMI2Instructions) {
 7966     op2 = rdxReg;
 7967     movl(op2, k);
 7968   }
 7969   else {
 7970     movl(op2, k);
 7971   }
 7972 
 7973   xorq(carry, carry);
 7974 
 7975   //First loop
 7976 
 7977   //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
 7978   //The carry is in tmp5
 7979   mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
 7980 
 7981   //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
 7982   decrementl(len);
 7983   jccb(Assembler::negative, L_carry);
 7984   decrementl(len);
 7985   jccb(Assembler::negative, L_last_in);
 7986 
 7987   movq(op1, Address(in, len, Address::times_4,  0));
 7988   rorq(op1, 32);
 7989 
 7990   subl(offs, 2);
 7991   movq(sum, Address(out, offs, Address::times_4,  0));
 7992   rorq(sum, 32);
 7993 
 7994   if (UseBMI2Instructions) {
 7995     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
 7996   }
 7997   else {
 7998     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
 7999   }
 8000 
 8001   // Store back in big endian from little endian
 8002   rorq(sum, 0x20);
 8003   movq(Address(out, offs, Address::times_4,  0), sum);
 8004 
 8005   testl(len, len);
 8006   jccb(Assembler::zero, L_carry);
 8007 
 8008   //Multiply the last in[] entry, if any
 8009   bind(L_last_in);
 8010   movl(op1, Address(in, 0));
 8011   movl(sum, Address(out, offs, Address::times_4,  -4));
 8012 
 8013   movl(raxReg, k);
 8014   mull(op1); //tmp4 * eax -> edx:eax
 8015   addl(sum, carry);
 8016   adcl(rdxReg, 0);
 8017   addl(sum, raxReg);
 8018   adcl(rdxReg, 0);
 8019   movl(carry, rdxReg);
 8020 
 8021   movl(Address(out, offs, Address::times_4,  -4), sum);
 8022 
 8023   bind(L_carry);
 8024   //return tmp5/carry as carry in rax
 8025   movl(rax, carry);
 8026 
 8027   bind(L_done);
 8028   pop(tmp5);
 8029   pop(tmp4);
 8030   pop(tmp3);
 8031   pop(tmp2);
 8032   pop(tmp1);
 8033 }
 8034 #endif
 8035 
 8036 /**
 8037  * Emits code to update CRC-32 with a byte value according to constants in table
 8038  *
 8039  * @param [in,out]crc   Register containing the crc.
 8040  * @param [in]val       Register containing the byte to fold into the CRC.
 8041  * @param [in]table     Register containing the table of crc constants.
 8042  *
 8043  * uint32_t crc;
 8044  * val = crc_table[(val ^ crc) & 0xFF];
 8045  * crc = val ^ (crc >> 8);
 8046  *
 8047  */
 8048 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
 8049   xorl(val, crc);
 8050   andl(val, 0xFF);
 8051   shrl(crc, 8); // unsigned shift
 8052   xorl(crc, Address(table, val, Address::times_4, 0));
 8053 }
 8054 
 8055 /**
 8056  * Fold 128-bit data chunk
 8057  */
 8058 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
 8059   if (UseAVX > 0) {
 8060     vpclmulhdq(xtmp, xK, xcrc); // [123:64]
 8061     vpclmulldq(xcrc, xK, xcrc); // [63:0]
 8062     vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
 8063     pxor(xcrc, xtmp);
 8064   } else {
 8065     movdqa(xtmp, xcrc);
 8066     pclmulhdq(xtmp, xK);   // [123:64]
 8067     pclmulldq(xcrc, xK);   // [63:0]
 8068     pxor(xcrc, xtmp);
 8069     movdqu(xtmp, Address(buf, offset));
 8070     pxor(xcrc, xtmp);
 8071   }
 8072 }
 8073 
 8074 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
 8075   if (UseAVX > 0) {
 8076     vpclmulhdq(xtmp, xK, xcrc);
 8077     vpclmulldq(xcrc, xK, xcrc);
 8078     pxor(xcrc, xbuf);
 8079     pxor(xcrc, xtmp);
 8080   } else {
 8081     movdqa(xtmp, xcrc);
 8082     pclmulhdq(xtmp, xK);
 8083     pclmulldq(xcrc, xK);
 8084     pxor(xcrc, xbuf);
 8085     pxor(xcrc, xtmp);
 8086   }
 8087 }
 8088 
 8089 /**
 8090  * 8-bit folds to compute 32-bit CRC
 8091  *
 8092  * uint64_t xcrc;
 8093  * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
 8094  */
 8095 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
 8096   movdl(tmp, xcrc);
 8097   andl(tmp, 0xFF);
 8098   movdl(xtmp, Address(table, tmp, Address::times_4, 0));
 8099   psrldq(xcrc, 1); // unsigned shift one byte
 8100   pxor(xcrc, xtmp);
 8101 }
 8102 
 8103 /**
 8104  * uint32_t crc;
 8105  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
 8106  */
 8107 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
 8108   movl(tmp, crc);
 8109   andl(tmp, 0xFF);
 8110   shrl(crc, 8);
 8111   xorl(crc, Address(table, tmp, Address::times_4, 0));
 8112 }
 8113 
 8114 /**
 8115  * @param crc   register containing existing CRC (32-bit)
 8116  * @param buf   register pointing to input byte buffer (byte*)
 8117  * @param len   register containing number of bytes
 8118  * @param table register that will contain address of CRC table
 8119  * @param tmp   scratch register
 8120  */
 8121 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
 8122   assert_different_registers(crc, buf, len, table, tmp, rax);
 8123 
 8124   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
 8125   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
 8126 
 8127   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
 8128   // context for the registers used, where all instructions below are using 128-bit mode
 8129   // On EVEX without VL and BW, these instructions will all be AVX.
 8130   lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
 8131   notl(crc); // ~crc
 8132   cmpl(len, 16);
 8133   jcc(Assembler::less, L_tail);
 8134 
 8135   // Align buffer to 16 bytes
 8136   movl(tmp, buf);
 8137   andl(tmp, 0xF);
 8138   jccb(Assembler::zero, L_aligned);
 8139   subl(tmp,  16);
 8140   addl(len, tmp);
 8141 
 8142   align(4);
 8143   BIND(L_align_loop);
 8144   movsbl(rax, Address(buf, 0)); // load byte with sign extension
 8145   update_byte_crc32(crc, rax, table);
 8146   increment(buf);
 8147   incrementl(tmp);
 8148   jccb(Assembler::less, L_align_loop);
 8149 
 8150   BIND(L_aligned);
 8151   movl(tmp, len); // save
 8152   shrl(len, 4);
 8153   jcc(Assembler::zero, L_tail_restore);
 8154 
 8155   // Fold crc into first bytes of vector
 8156   movdqa(xmm1, Address(buf, 0));
 8157   movdl(rax, xmm1);
 8158   xorl(crc, rax);
 8159   if (VM_Version::supports_sse4_1()) {
 8160     pinsrd(xmm1, crc, 0);
 8161   } else {
 8162     pinsrw(xmm1, crc, 0);
 8163     shrl(crc, 16);
 8164     pinsrw(xmm1, crc, 1);
 8165   }
 8166   addptr(buf, 16);
 8167   subl(len, 4); // len > 0
 8168   jcc(Assembler::less, L_fold_tail);
 8169 
 8170   movdqa(xmm2, Address(buf,  0));
 8171   movdqa(xmm3, Address(buf, 16));
 8172   movdqa(xmm4, Address(buf, 32));
 8173   addptr(buf, 48);
 8174   subl(len, 3);
 8175   jcc(Assembler::lessEqual, L_fold_512b);
 8176 
 8177   // Fold total 512 bits of polynomial on each iteration,
 8178   // 128 bits per each of 4 parallel streams.
 8179   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
 8180 
 8181   align32();
 8182   BIND(L_fold_512b_loop);
 8183   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
 8184   fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
 8185   fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
 8186   fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
 8187   addptr(buf, 64);
 8188   subl(len, 4);
 8189   jcc(Assembler::greater, L_fold_512b_loop);
 8190 
 8191   // Fold 512 bits to 128 bits.
 8192   BIND(L_fold_512b);
 8193   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
 8194   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
 8195   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
 8196   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
 8197 
 8198   // Fold the rest of 128 bits data chunks
 8199   BIND(L_fold_tail);
 8200   addl(len, 3);
 8201   jccb(Assembler::lessEqual, L_fold_128b);
 8202   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
 8203 
 8204   BIND(L_fold_tail_loop);
 8205   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
 8206   addptr(buf, 16);
 8207   decrementl(len);
 8208   jccb(Assembler::greater, L_fold_tail_loop);
 8209 
 8210   // Fold 128 bits in xmm1 down into 32 bits in crc register.
 8211   BIND(L_fold_128b);
 8212   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
 8213   if (UseAVX > 0) {
 8214     vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
 8215     vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
 8216     vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
 8217   } else {
 8218     movdqa(xmm2, xmm0);
 8219     pclmulqdq(xmm2, xmm1, 0x1);
 8220     movdqa(xmm3, xmm0);
 8221     pand(xmm3, xmm2);
 8222     pclmulqdq(xmm0, xmm3, 0x1);
 8223   }
 8224   psrldq(xmm1, 8);
 8225   psrldq(xmm2, 4);
 8226   pxor(xmm0, xmm1);
 8227   pxor(xmm0, xmm2);
 8228 
 8229   // 8 8-bit folds to compute 32-bit CRC.
 8230   for (int j = 0; j < 4; j++) {
 8231     fold_8bit_crc32(xmm0, table, xmm1, rax);
 8232   }
 8233   movdl(crc, xmm0); // mov 32 bits to general register
 8234   for (int j = 0; j < 4; j++) {
 8235     fold_8bit_crc32(crc, table, rax);
 8236   }
 8237 
 8238   BIND(L_tail_restore);
 8239   movl(len, tmp); // restore
 8240   BIND(L_tail);
 8241   andl(len, 0xf);
 8242   jccb(Assembler::zero, L_exit);
 8243 
 8244   // Fold the rest of bytes
 8245   align(4);
 8246   BIND(L_tail_loop);
 8247   movsbl(rax, Address(buf, 0)); // load byte with sign extension
 8248   update_byte_crc32(crc, rax, table);
 8249   increment(buf);
 8250   decrementl(len);
 8251   jccb(Assembler::greater, L_tail_loop);
 8252 
 8253   BIND(L_exit);
 8254   notl(crc); // ~c
 8255 }
 8256 
 8257 #ifdef _LP64
 8258 // Helper function for AVX 512 CRC32
 8259 // Fold 512-bit data chunks
 8260 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
 8261                                              Register pos, int offset) {
 8262   evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
 8263   evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
 8264   evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
 8265   evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
 8266   evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
 8267 }
 8268 
 8269 // Helper function for AVX 512 CRC32
 8270 // Compute CRC32 for < 256B buffers
 8271 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
 8272                                               Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
 8273                                               Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
 8274 
 8275   Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
 8276   Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
 8277   Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
 8278 
 8279   // check if there is enough buffer to be able to fold 16B at a time
 8280   cmpl(len, 32);
 8281   jcc(Assembler::less, L_less_than_32);
 8282 
 8283   // if there is, load the constants
 8284   movdqu(xmm10, Address(table, 1 * 16));    //rk1 and rk2 in xmm10
 8285   movdl(xmm0, crc);                        // get the initial crc value
 8286   movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
 8287   pxor(xmm7, xmm0);
 8288 
 8289   // update the buffer pointer
 8290   addl(pos, 16);
 8291   //update the counter.subtract 32 instead of 16 to save one instruction from the loop
 8292   subl(len, 32);
 8293   jmp(L_16B_reduction_loop);
 8294 
 8295   bind(L_less_than_32);
 8296   //mov initial crc to the return value. this is necessary for zero - length buffers.
 8297   movl(rax, crc);
 8298   testl(len, len);
 8299   jcc(Assembler::equal, L_cleanup);
 8300 
 8301   movdl(xmm0, crc);                        //get the initial crc value
 8302 
 8303   cmpl(len, 16);
 8304   jcc(Assembler::equal, L_exact_16_left);
 8305   jcc(Assembler::less, L_less_than_16_left);
 8306 
 8307   movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
 8308   pxor(xmm7, xmm0);                       //xor the initial crc value
 8309   addl(pos, 16);
 8310   subl(len, 16);
 8311   movdqu(xmm10, Address(table, 1 * 16));    // rk1 and rk2 in xmm10
 8312   jmp(L_get_last_two_xmms);
 8313 
 8314   bind(L_less_than_16_left);
 8315   //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
 8316   pxor(xmm1, xmm1);
 8317   movptr(tmp1, rsp);
 8318   movdqu(Address(tmp1, 0 * 16), xmm1);
 8319 
 8320   cmpl(len, 4);
 8321   jcc(Assembler::less, L_only_less_than_4);
 8322 
 8323   //backup the counter value
 8324   movl(tmp2, len);
 8325   cmpl(len, 8);
 8326   jcc(Assembler::less, L_less_than_8_left);
 8327 
 8328   //load 8 Bytes
 8329   movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
 8330   movq(Address(tmp1, 0 * 16), rax);
 8331   addptr(tmp1, 8);
 8332   subl(len, 8);
 8333   addl(pos, 8);
 8334 
 8335   bind(L_less_than_8_left);
 8336   cmpl(len, 4);
 8337   jcc(Assembler::less, L_less_than_4_left);
 8338 
 8339   //load 4 Bytes
 8340   movl(rax, Address(buf, pos, Address::times_1, 0));
 8341   movl(Address(tmp1, 0 * 16), rax);
 8342   addptr(tmp1, 4);
 8343   subl(len, 4);
 8344   addl(pos, 4);
 8345 
 8346   bind(L_less_than_4_left);
 8347   cmpl(len, 2);
 8348   jcc(Assembler::less, L_less_than_2_left);
 8349 
 8350   // load 2 Bytes
 8351   movw(rax, Address(buf, pos, Address::times_1, 0));
 8352   movl(Address(tmp1, 0 * 16), rax);
 8353   addptr(tmp1, 2);
 8354   subl(len, 2);
 8355   addl(pos, 2);
 8356 
 8357   bind(L_less_than_2_left);
 8358   cmpl(len, 1);
 8359   jcc(Assembler::less, L_zero_left);
 8360 
 8361   // load 1 Byte
 8362   movb(rax, Address(buf, pos, Address::times_1, 0));
 8363   movb(Address(tmp1, 0 * 16), rax);
 8364 
 8365   bind(L_zero_left);
 8366   movdqu(xmm7, Address(rsp, 0));
 8367   pxor(xmm7, xmm0);                       //xor the initial crc value
 8368 
 8369   lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
 8370   movdqu(xmm0, Address(rax, tmp2));
 8371   pshufb(xmm7, xmm0);
 8372   jmp(L_128_done);
 8373 
 8374   bind(L_exact_16_left);
 8375   movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
 8376   pxor(xmm7, xmm0);                       //xor the initial crc value
 8377   jmp(L_128_done);
 8378 
 8379   bind(L_only_less_than_4);
 8380   cmpl(len, 3);
 8381   jcc(Assembler::less, L_only_less_than_3);
 8382 
 8383   // load 3 Bytes
 8384   movb(rax, Address(buf, pos, Address::times_1, 0));
 8385   movb(Address(tmp1, 0), rax);
 8386 
 8387   movb(rax, Address(buf, pos, Address::times_1, 1));
 8388   movb(Address(tmp1, 1), rax);
 8389 
 8390   movb(rax, Address(buf, pos, Address::times_1, 2));
 8391   movb(Address(tmp1, 2), rax);
 8392 
 8393   movdqu(xmm7, Address(rsp, 0));
 8394   pxor(xmm7, xmm0);                     //xor the initial crc value
 8395 
 8396   pslldq(xmm7, 0x5);
 8397   jmp(L_barrett);
 8398   bind(L_only_less_than_3);
 8399   cmpl(len, 2);
 8400   jcc(Assembler::less, L_only_less_than_2);
 8401 
 8402   // load 2 Bytes
 8403   movb(rax, Address(buf, pos, Address::times_1, 0));
 8404   movb(Address(tmp1, 0), rax);
 8405 
 8406   movb(rax, Address(buf, pos, Address::times_1, 1));
 8407   movb(Address(tmp1, 1), rax);
 8408 
 8409   movdqu(xmm7, Address(rsp, 0));
 8410   pxor(xmm7, xmm0);                     //xor the initial crc value
 8411 
 8412   pslldq(xmm7, 0x6);
 8413   jmp(L_barrett);
 8414 
 8415   bind(L_only_less_than_2);
 8416   //load 1 Byte
 8417   movb(rax, Address(buf, pos, Address::times_1, 0));
 8418   movb(Address(tmp1, 0), rax);
 8419 
 8420   movdqu(xmm7, Address(rsp, 0));
 8421   pxor(xmm7, xmm0);                     //xor the initial crc value
 8422 
 8423   pslldq(xmm7, 0x7);
 8424 }
 8425 
 8426 /**
 8427 * Compute CRC32 using AVX512 instructions
 8428 * param crc   register containing existing CRC (32-bit)
 8429 * param buf   register pointing to input byte buffer (byte*)
 8430 * param len   register containing number of bytes
 8431 * param table address of crc or crc32c table
 8432 * param tmp1  scratch register
 8433 * param tmp2  scratch register
 8434 * return rax  result register
 8435 *
 8436 * This routine is identical for crc32c with the exception of the precomputed constant
 8437 * table which will be passed as the table argument.  The calculation steps are
 8438 * the same for both variants.
 8439 */
 8440 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
 8441   assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
 8442 
 8443   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
 8444   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
 8445   Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
 8446   Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
 8447   Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
 8448 
 8449   const Register pos = r12;
 8450   push(r12);
 8451   subptr(rsp, 16 * 2 + 8);
 8452 
 8453   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
 8454   // context for the registers used, where all instructions below are using 128-bit mode
 8455   // On EVEX without VL and BW, these instructions will all be AVX.
 8456   movl(pos, 0);
 8457 
 8458   // check if smaller than 256B
 8459   cmpl(len, 256);
 8460   jcc(Assembler::less, L_less_than_256);
 8461 
 8462   // load the initial crc value
 8463   movdl(xmm10, crc);
 8464 
 8465   // receive the initial 64B data, xor the initial crc value
 8466   evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
 8467   evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
 8468   evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
 8469   evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
 8470 
 8471   subl(len, 256);
 8472   cmpl(len, 256);
 8473   jcc(Assembler::less, L_fold_128_B_loop);
 8474 
 8475   evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
 8476   evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
 8477   evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
 8478   subl(len, 256);
 8479 
 8480   bind(L_fold_256_B_loop);
 8481   addl(pos, 256);
 8482   fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
 8483   fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
 8484   fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
 8485   fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
 8486 
 8487   subl(len, 256);
 8488   jcc(Assembler::greaterEqual, L_fold_256_B_loop);
 8489 
 8490   // Fold 256 into 128
 8491   addl(pos, 256);
 8492   evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
 8493   evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
 8494   vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
 8495 
 8496   evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
 8497   evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
 8498   vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
 8499 
 8500   evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
 8501   evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
 8502 
 8503   addl(len, 128);
 8504   jmp(L_fold_128_B_register);
 8505 
 8506   // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
 8507   // loop will fold 128B at a time until we have 128 + y Bytes of buffer
 8508 
 8509   // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
 8510   bind(L_fold_128_B_loop);
 8511   addl(pos, 128);
 8512   fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
 8513   fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
 8514 
 8515   subl(len, 128);
 8516   jcc(Assembler::greaterEqual, L_fold_128_B_loop);
 8517 
 8518   addl(pos, 128);
 8519 
 8520   // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
 8521   // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
 8522   bind(L_fold_128_B_register);
 8523   evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
 8524   evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
 8525   evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
 8526   evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
 8527   // save last that has no multiplicand
 8528   vextracti64x2(xmm7, xmm4, 3);
 8529 
 8530   evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
 8531   evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
 8532   // Needed later in reduction loop
 8533   movdqu(xmm10, Address(table, 1 * 16));
 8534   vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
 8535   vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
 8536 
 8537   // Swap 1,0,3,2 - 01 00 11 10
 8538   evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
 8539   evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
 8540   vextracti128(xmm5, xmm8, 1);
 8541   evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
 8542 
 8543   // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
 8544   // instead of a cmp instruction, we use the negative flag with the jl instruction
 8545   addl(len, 128 - 16);
 8546   jcc(Assembler::less, L_final_reduction_for_128);
 8547 
 8548   bind(L_16B_reduction_loop);
 8549   vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
 8550   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
 8551   vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
 8552   movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
 8553   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
 8554   addl(pos, 16);
 8555   subl(len, 16);
 8556   jcc(Assembler::greaterEqual, L_16B_reduction_loop);
 8557 
 8558   bind(L_final_reduction_for_128);
 8559   addl(len, 16);
 8560   jcc(Assembler::equal, L_128_done);
 8561 
 8562   bind(L_get_last_two_xmms);
 8563   movdqu(xmm2, xmm7);
 8564   addl(pos, len);
 8565   movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
 8566   subl(pos, len);
 8567 
 8568   // get rid of the extra data that was loaded before
 8569   // load the shift constant
 8570   lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
 8571   movdqu(xmm0, Address(rax, len));
 8572   addl(rax, len);
 8573 
 8574   vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
 8575   //Change mask to 512
 8576   vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
 8577   vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
 8578 
 8579   blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
 8580   vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
 8581   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
 8582   vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
 8583   vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
 8584 
 8585   bind(L_128_done);
 8586   // compute crc of a 128-bit value
 8587   movdqu(xmm10, Address(table, 3 * 16));
 8588   movdqu(xmm0, xmm7);
 8589 
 8590   // 64b fold
 8591   vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
 8592   vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
 8593   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
 8594 
 8595   // 32b fold
 8596   movdqu(xmm0, xmm7);
 8597   vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
 8598   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
 8599   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
 8600   jmp(L_barrett);
 8601 
 8602   bind(L_less_than_256);
 8603   kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
 8604 
 8605   //barrett reduction
 8606   bind(L_barrett);
 8607   vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
 8608   movdqu(xmm1, xmm7);
 8609   movdqu(xmm2, xmm7);
 8610   movdqu(xmm10, Address(table, 4 * 16));
 8611 
 8612   pclmulqdq(xmm7, xmm10, 0x0);
 8613   pxor(xmm7, xmm2);
 8614   vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
 8615   movdqu(xmm2, xmm7);
 8616   pclmulqdq(xmm7, xmm10, 0x10);
 8617   pxor(xmm7, xmm2);
 8618   pxor(xmm7, xmm1);
 8619   pextrd(crc, xmm7, 2);
 8620 
 8621   bind(L_cleanup);
 8622   addptr(rsp, 16 * 2 + 8);
 8623   pop(r12);
 8624 }
 8625 
 8626 // S. Gueron / Information Processing Letters 112 (2012) 184
 8627 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
 8628 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
 8629 // Output: the 64-bit carry-less product of B * CONST
 8630 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
 8631                                      Register tmp1, Register tmp2, Register tmp3) {
 8632   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
 8633   if (n > 0) {
 8634     addq(tmp3, n * 256 * 8);
 8635   }
 8636   //    Q1 = TABLEExt[n][B & 0xFF];
 8637   movl(tmp1, in);
 8638   andl(tmp1, 0x000000FF);
 8639   shll(tmp1, 3);
 8640   addq(tmp1, tmp3);
 8641   movq(tmp1, Address(tmp1, 0));
 8642 
 8643   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
 8644   movl(tmp2, in);
 8645   shrl(tmp2, 8);
 8646   andl(tmp2, 0x000000FF);
 8647   shll(tmp2, 3);
 8648   addq(tmp2, tmp3);
 8649   movq(tmp2, Address(tmp2, 0));
 8650 
 8651   shlq(tmp2, 8);
 8652   xorq(tmp1, tmp2);
 8653 
 8654   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
 8655   movl(tmp2, in);
 8656   shrl(tmp2, 16);
 8657   andl(tmp2, 0x000000FF);
 8658   shll(tmp2, 3);
 8659   addq(tmp2, tmp3);
 8660   movq(tmp2, Address(tmp2, 0));
 8661 
 8662   shlq(tmp2, 16);
 8663   xorq(tmp1, tmp2);
 8664 
 8665   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
 8666   shrl(in, 24);
 8667   andl(in, 0x000000FF);
 8668   shll(in, 3);
 8669   addq(in, tmp3);
 8670   movq(in, Address(in, 0));
 8671 
 8672   shlq(in, 24);
 8673   xorq(in, tmp1);
 8674   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
 8675 }
 8676 
 8677 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
 8678                                       Register in_out,
 8679                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
 8680                                       XMMRegister w_xtmp2,
 8681                                       Register tmp1,
 8682                                       Register n_tmp2, Register n_tmp3) {
 8683   if (is_pclmulqdq_supported) {
 8684     movdl(w_xtmp1, in_out); // modified blindly
 8685 
 8686     movl(tmp1, const_or_pre_comp_const_index);
 8687     movdl(w_xtmp2, tmp1);
 8688     pclmulqdq(w_xtmp1, w_xtmp2, 0);
 8689 
 8690     movdq(in_out, w_xtmp1);
 8691   } else {
 8692     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
 8693   }
 8694 }
 8695 
 8696 // Recombination Alternative 2: No bit-reflections
 8697 // T1 = (CRC_A * U1) << 1
 8698 // T2 = (CRC_B * U2) << 1
 8699 // C1 = T1 >> 32
 8700 // C2 = T2 >> 32
 8701 // T1 = T1 & 0xFFFFFFFF
 8702 // T2 = T2 & 0xFFFFFFFF
 8703 // T1 = CRC32(0, T1)
 8704 // T2 = CRC32(0, T2)
 8705 // C1 = C1 ^ T1
 8706 // C2 = C2 ^ T2
 8707 // CRC = C1 ^ C2 ^ CRC_C
 8708 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
 8709                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
 8710                                      Register tmp1, Register tmp2,
 8711                                      Register n_tmp3) {
 8712   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
 8713   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
 8714   shlq(in_out, 1);
 8715   movl(tmp1, in_out);
 8716   shrq(in_out, 32);
 8717   xorl(tmp2, tmp2);
 8718   crc32(tmp2, tmp1, 4);
 8719   xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
 8720   shlq(in1, 1);
 8721   movl(tmp1, in1);
 8722   shrq(in1, 32);
 8723   xorl(tmp2, tmp2);
 8724   crc32(tmp2, tmp1, 4);
 8725   xorl(in1, tmp2);
 8726   xorl(in_out, in1);
 8727   xorl(in_out, in2);
 8728 }
 8729 
 8730 // Set N to predefined value
 8731 // Subtract from a length of a buffer
 8732 // execute in a loop:
 8733 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
 8734 // for i = 1 to N do
 8735 //  CRC_A = CRC32(CRC_A, A[i])
 8736 //  CRC_B = CRC32(CRC_B, B[i])
 8737 //  CRC_C = CRC32(CRC_C, C[i])
 8738 // end for
 8739 // Recombine
 8740 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
 8741                                        Register in_out1, Register in_out2, Register in_out3,
 8742                                        Register tmp1, Register tmp2, Register tmp3,
 8743                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
 8744                                        Register tmp4, Register tmp5,
 8745                                        Register n_tmp6) {
 8746   Label L_processPartitions;
 8747   Label L_processPartition;
 8748   Label L_exit;
 8749 
 8750   bind(L_processPartitions);
 8751   cmpl(in_out1, 3 * size);
 8752   jcc(Assembler::less, L_exit);
 8753     xorl(tmp1, tmp1);
 8754     xorl(tmp2, tmp2);
 8755     movq(tmp3, in_out2);
 8756     addq(tmp3, size);
 8757 
 8758     bind(L_processPartition);
 8759       crc32(in_out3, Address(in_out2, 0), 8);
 8760       crc32(tmp1, Address(in_out2, size), 8);
 8761       crc32(tmp2, Address(in_out2, size * 2), 8);
 8762       addq(in_out2, 8);
 8763       cmpq(in_out2, tmp3);
 8764       jcc(Assembler::less, L_processPartition);
 8765     crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
 8766             w_xtmp1, w_xtmp2, w_xtmp3,
 8767             tmp4, tmp5,
 8768             n_tmp6);
 8769     addq(in_out2, 2 * size);
 8770     subl(in_out1, 3 * size);
 8771     jmp(L_processPartitions);
 8772 
 8773   bind(L_exit);
 8774 }
 8775 #else
 8776 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
 8777                                      Register tmp1, Register tmp2, Register tmp3,
 8778                                      XMMRegister xtmp1, XMMRegister xtmp2) {
 8779   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
 8780   if (n > 0) {
 8781     addl(tmp3, n * 256 * 8);
 8782   }
 8783   //    Q1 = TABLEExt[n][B & 0xFF];
 8784   movl(tmp1, in_out);
 8785   andl(tmp1, 0x000000FF);
 8786   shll(tmp1, 3);
 8787   addl(tmp1, tmp3);
 8788   movq(xtmp1, Address(tmp1, 0));
 8789 
 8790   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
 8791   movl(tmp2, in_out);
 8792   shrl(tmp2, 8);
 8793   andl(tmp2, 0x000000FF);
 8794   shll(tmp2, 3);
 8795   addl(tmp2, tmp3);
 8796   movq(xtmp2, Address(tmp2, 0));
 8797 
 8798   psllq(xtmp2, 8);
 8799   pxor(xtmp1, xtmp2);
 8800 
 8801   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
 8802   movl(tmp2, in_out);
 8803   shrl(tmp2, 16);
 8804   andl(tmp2, 0x000000FF);
 8805   shll(tmp2, 3);
 8806   addl(tmp2, tmp3);
 8807   movq(xtmp2, Address(tmp2, 0));
 8808 
 8809   psllq(xtmp2, 16);
 8810   pxor(xtmp1, xtmp2);
 8811 
 8812   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
 8813   shrl(in_out, 24);
 8814   andl(in_out, 0x000000FF);
 8815   shll(in_out, 3);
 8816   addl(in_out, tmp3);
 8817   movq(xtmp2, Address(in_out, 0));
 8818 
 8819   psllq(xtmp2, 24);
 8820   pxor(xtmp1, xtmp2); // Result in CXMM
 8821   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
 8822 }
 8823 
 8824 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
 8825                                       Register in_out,
 8826                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
 8827                                       XMMRegister w_xtmp2,
 8828                                       Register tmp1,
 8829                                       Register n_tmp2, Register n_tmp3) {
 8830   if (is_pclmulqdq_supported) {
 8831     movdl(w_xtmp1, in_out);
 8832 
 8833     movl(tmp1, const_or_pre_comp_const_index);
 8834     movdl(w_xtmp2, tmp1);
 8835     pclmulqdq(w_xtmp1, w_xtmp2, 0);
 8836     // Keep result in XMM since GPR is 32 bit in length
 8837   } else {
 8838     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
 8839   }
 8840 }
 8841 
 8842 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
 8843                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
 8844                                      Register tmp1, Register tmp2,
 8845                                      Register n_tmp3) {
 8846   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
 8847   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
 8848 
 8849   psllq(w_xtmp1, 1);
 8850   movdl(tmp1, w_xtmp1);
 8851   psrlq(w_xtmp1, 32);
 8852   movdl(in_out, w_xtmp1);
 8853 
 8854   xorl(tmp2, tmp2);
 8855   crc32(tmp2, tmp1, 4);
 8856   xorl(in_out, tmp2);
 8857 
 8858   psllq(w_xtmp2, 1);
 8859   movdl(tmp1, w_xtmp2);
 8860   psrlq(w_xtmp2, 32);
 8861   movdl(in1, w_xtmp2);
 8862 
 8863   xorl(tmp2, tmp2);
 8864   crc32(tmp2, tmp1, 4);
 8865   xorl(in1, tmp2);
 8866   xorl(in_out, in1);
 8867   xorl(in_out, in2);
 8868 }
 8869 
 8870 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
 8871                                        Register in_out1, Register in_out2, Register in_out3,
 8872                                        Register tmp1, Register tmp2, Register tmp3,
 8873                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
 8874                                        Register tmp4, Register tmp5,
 8875                                        Register n_tmp6) {
 8876   Label L_processPartitions;
 8877   Label L_processPartition;
 8878   Label L_exit;
 8879 
 8880   bind(L_processPartitions);
 8881   cmpl(in_out1, 3 * size);
 8882   jcc(Assembler::less, L_exit);
 8883     xorl(tmp1, tmp1);
 8884     xorl(tmp2, tmp2);
 8885     movl(tmp3, in_out2);
 8886     addl(tmp3, size);
 8887 
 8888     bind(L_processPartition);
 8889       crc32(in_out3, Address(in_out2, 0), 4);
 8890       crc32(tmp1, Address(in_out2, size), 4);
 8891       crc32(tmp2, Address(in_out2, size*2), 4);
 8892       crc32(in_out3, Address(in_out2, 0+4), 4);
 8893       crc32(tmp1, Address(in_out2, size+4), 4);
 8894       crc32(tmp2, Address(in_out2, size*2+4), 4);
 8895       addl(in_out2, 8);
 8896       cmpl(in_out2, tmp3);
 8897       jcc(Assembler::less, L_processPartition);
 8898 
 8899         push(tmp3);
 8900         push(in_out1);
 8901         push(in_out2);
 8902         tmp4 = tmp3;
 8903         tmp5 = in_out1;
 8904         n_tmp6 = in_out2;
 8905 
 8906       crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
 8907             w_xtmp1, w_xtmp2, w_xtmp3,
 8908             tmp4, tmp5,
 8909             n_tmp6);
 8910 
 8911         pop(in_out2);
 8912         pop(in_out1);
 8913         pop(tmp3);
 8914 
 8915     addl(in_out2, 2 * size);
 8916     subl(in_out1, 3 * size);
 8917     jmp(L_processPartitions);
 8918 
 8919   bind(L_exit);
 8920 }
 8921 #endif //LP64
 8922 
 8923 #ifdef _LP64
 8924 // Algorithm 2: Pipelined usage of the CRC32 instruction.
 8925 // Input: A buffer I of L bytes.
 8926 // Output: the CRC32C value of the buffer.
 8927 // Notations:
 8928 // Write L = 24N + r, with N = floor (L/24).
 8929 // r = L mod 24 (0 <= r < 24).
 8930 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
 8931 // N quadwords, and R consists of r bytes.
 8932 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
 8933 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
 8934 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
 8935 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
 8936 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
 8937                                           Register tmp1, Register tmp2, Register tmp3,
 8938                                           Register tmp4, Register tmp5, Register tmp6,
 8939                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
 8940                                           bool is_pclmulqdq_supported) {
 8941   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
 8942   Label L_wordByWord;
 8943   Label L_byteByByteProlog;
 8944   Label L_byteByByte;
 8945   Label L_exit;
 8946 
 8947   if (is_pclmulqdq_supported ) {
 8948     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
 8949     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
 8950 
 8951     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
 8952     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
 8953 
 8954     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
 8955     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
 8956     assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
 8957   } else {
 8958     const_or_pre_comp_const_index[0] = 1;
 8959     const_or_pre_comp_const_index[1] = 0;
 8960 
 8961     const_or_pre_comp_const_index[2] = 3;
 8962     const_or_pre_comp_const_index[3] = 2;
 8963 
 8964     const_or_pre_comp_const_index[4] = 5;
 8965     const_or_pre_comp_const_index[5] = 4;
 8966    }
 8967   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
 8968                     in2, in1, in_out,
 8969                     tmp1, tmp2, tmp3,
 8970                     w_xtmp1, w_xtmp2, w_xtmp3,
 8971                     tmp4, tmp5,
 8972                     tmp6);
 8973   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
 8974                     in2, in1, in_out,
 8975                     tmp1, tmp2, tmp3,
 8976                     w_xtmp1, w_xtmp2, w_xtmp3,
 8977                     tmp4, tmp5,
 8978                     tmp6);
 8979   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
 8980                     in2, in1, in_out,
 8981                     tmp1, tmp2, tmp3,
 8982                     w_xtmp1, w_xtmp2, w_xtmp3,
 8983                     tmp4, tmp5,
 8984                     tmp6);
 8985   movl(tmp1, in2);
 8986   andl(tmp1, 0x00000007);
 8987   negl(tmp1);
 8988   addl(tmp1, in2);
 8989   addq(tmp1, in1);
 8990 
 8991   BIND(L_wordByWord);
 8992   cmpq(in1, tmp1);
 8993   jcc(Assembler::greaterEqual, L_byteByByteProlog);
 8994     crc32(in_out, Address(in1, 0), 4);
 8995     addq(in1, 4);
 8996     jmp(L_wordByWord);
 8997 
 8998   BIND(L_byteByByteProlog);
 8999   andl(in2, 0x00000007);
 9000   movl(tmp2, 1);
 9001 
 9002   BIND(L_byteByByte);
 9003   cmpl(tmp2, in2);
 9004   jccb(Assembler::greater, L_exit);
 9005     crc32(in_out, Address(in1, 0), 1);
 9006     incq(in1);
 9007     incl(tmp2);
 9008     jmp(L_byteByByte);
 9009 
 9010   BIND(L_exit);
 9011 }
 9012 #else
 9013 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
 9014                                           Register tmp1, Register  tmp2, Register tmp3,
 9015                                           Register tmp4, Register  tmp5, Register tmp6,
 9016                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
 9017                                           bool is_pclmulqdq_supported) {
 9018   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
 9019   Label L_wordByWord;
 9020   Label L_byteByByteProlog;
 9021   Label L_byteByByte;
 9022   Label L_exit;
 9023 
 9024   if (is_pclmulqdq_supported) {
 9025     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
 9026     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
 9027 
 9028     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
 9029     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
 9030 
 9031     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
 9032     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
 9033   } else {
 9034     const_or_pre_comp_const_index[0] = 1;
 9035     const_or_pre_comp_const_index[1] = 0;
 9036 
 9037     const_or_pre_comp_const_index[2] = 3;
 9038     const_or_pre_comp_const_index[3] = 2;
 9039 
 9040     const_or_pre_comp_const_index[4] = 5;
 9041     const_or_pre_comp_const_index[5] = 4;
 9042   }
 9043   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
 9044                     in2, in1, in_out,
 9045                     tmp1, tmp2, tmp3,
 9046                     w_xtmp1, w_xtmp2, w_xtmp3,
 9047                     tmp4, tmp5,
 9048                     tmp6);
 9049   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
 9050                     in2, in1, in_out,
 9051                     tmp1, tmp2, tmp3,
 9052                     w_xtmp1, w_xtmp2, w_xtmp3,
 9053                     tmp4, tmp5,
 9054                     tmp6);
 9055   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
 9056                     in2, in1, in_out,
 9057                     tmp1, tmp2, tmp3,
 9058                     w_xtmp1, w_xtmp2, w_xtmp3,
 9059                     tmp4, tmp5,
 9060                     tmp6);
 9061   movl(tmp1, in2);
 9062   andl(tmp1, 0x00000007);
 9063   negl(tmp1);
 9064   addl(tmp1, in2);
 9065   addl(tmp1, in1);
 9066 
 9067   BIND(L_wordByWord);
 9068   cmpl(in1, tmp1);
 9069   jcc(Assembler::greaterEqual, L_byteByByteProlog);
 9070     crc32(in_out, Address(in1,0), 4);
 9071     addl(in1, 4);
 9072     jmp(L_wordByWord);
 9073 
 9074   BIND(L_byteByByteProlog);
 9075   andl(in2, 0x00000007);
 9076   movl(tmp2, 1);
 9077 
 9078   BIND(L_byteByByte);
 9079   cmpl(tmp2, in2);
 9080   jccb(Assembler::greater, L_exit);
 9081     movb(tmp1, Address(in1, 0));
 9082     crc32(in_out, tmp1, 1);
 9083     incl(in1);
 9084     incl(tmp2);
 9085     jmp(L_byteByByte);
 9086 
 9087   BIND(L_exit);
 9088 }
 9089 #endif // LP64
 9090 #undef BIND
 9091 #undef BLOCK_COMMENT
 9092 
 9093 // Compress char[] array to byte[].
 9094 //   ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
 9095 //   @IntrinsicCandidate
 9096 //   private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
 9097 //     for (int i = 0; i < len; i++) {
 9098 //       int c = src[srcOff++];
 9099 //       if (c >>> 8 != 0) {
 9100 //         return 0;
 9101 //       }
 9102 //       dst[dstOff++] = (byte)c;
 9103 //     }
 9104 //     return len;
 9105 //   }
 9106 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
 9107   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
 9108   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
 9109   Register tmp5, Register result, KRegister mask1, KRegister mask2) {
 9110   Label copy_chars_loop, return_length, return_zero, done;
 9111 
 9112   // rsi: src
 9113   // rdi: dst
 9114   // rdx: len
 9115   // rcx: tmp5
 9116   // rax: result
 9117 
 9118   // rsi holds start addr of source char[] to be compressed
 9119   // rdi holds start addr of destination byte[]
 9120   // rdx holds length
 9121 
 9122   assert(len != result, "");
 9123 
 9124   // save length for return
 9125   push(len);
 9126 
 9127   if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
 9128     VM_Version::supports_avx512vlbw() &&
 9129     VM_Version::supports_bmi2()) {
 9130 
 9131     Label copy_32_loop, copy_loop_tail, below_threshold;
 9132 
 9133     // alignment
 9134     Label post_alignment;
 9135 
 9136     // if length of the string is less than 16, handle it in an old fashioned way
 9137     testl(len, -32);
 9138     jcc(Assembler::zero, below_threshold);
 9139 
 9140     // First check whether a character is compressible ( <= 0xFF).
 9141     // Create mask to test for Unicode chars inside zmm vector
 9142     movl(result, 0x00FF);
 9143     evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
 9144 
 9145     testl(len, -64);
 9146     jcc(Assembler::zero, post_alignment);
 9147 
 9148     movl(tmp5, dst);
 9149     andl(tmp5, (32 - 1));
 9150     negl(tmp5);
 9151     andl(tmp5, (32 - 1));
 9152 
 9153     // bail out when there is nothing to be done
 9154     testl(tmp5, 0xFFFFFFFF);
 9155     jcc(Assembler::zero, post_alignment);
 9156 
 9157     // ~(~0 << len), where len is the # of remaining elements to process
 9158     movl(result, 0xFFFFFFFF);
 9159     shlxl(result, result, tmp5);
 9160     notl(result);
 9161     kmovdl(mask2, result);
 9162 
 9163     evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
 9164     evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
 9165     ktestd(mask1, mask2);
 9166     jcc(Assembler::carryClear, return_zero);
 9167 
 9168     evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
 9169 
 9170     addptr(src, tmp5);
 9171     addptr(src, tmp5);
 9172     addptr(dst, tmp5);
 9173     subl(len, tmp5);
 9174 
 9175     bind(post_alignment);
 9176     // end of alignment
 9177 
 9178     movl(tmp5, len);
 9179     andl(tmp5, (32 - 1));    // tail count (in chars)
 9180     andl(len, ~(32 - 1));    // vector count (in chars)
 9181     jcc(Assembler::zero, copy_loop_tail);
 9182 
 9183     lea(src, Address(src, len, Address::times_2));
 9184     lea(dst, Address(dst, len, Address::times_1));
 9185     negptr(len);
 9186 
 9187     bind(copy_32_loop);
 9188     evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
 9189     evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
 9190     kortestdl(mask1, mask1);
 9191     jcc(Assembler::carryClear, return_zero);
 9192 
 9193     // All elements in current processed chunk are valid candidates for
 9194     // compression. Write a truncated byte elements to the memory.
 9195     evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
 9196     addptr(len, 32);
 9197     jcc(Assembler::notZero, copy_32_loop);
 9198 
 9199     bind(copy_loop_tail);
 9200     // bail out when there is nothing to be done
 9201     testl(tmp5, 0xFFFFFFFF);
 9202     jcc(Assembler::zero, return_length);
 9203 
 9204     movl(len, tmp5);
 9205 
 9206     // ~(~0 << len), where len is the # of remaining elements to process
 9207     movl(result, 0xFFFFFFFF);
 9208     shlxl(result, result, len);
 9209     notl(result);
 9210 
 9211     kmovdl(mask2, result);
 9212 
 9213     evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
 9214     evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
 9215     ktestd(mask1, mask2);
 9216     jcc(Assembler::carryClear, return_zero);
 9217 
 9218     evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
 9219     jmp(return_length);
 9220 
 9221     bind(below_threshold);
 9222   }
 9223 
 9224   if (UseSSE42Intrinsics) {
 9225     Label copy_32_loop, copy_16, copy_tail;
 9226 
 9227     movl(result, len);
 9228 
 9229     movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vectors
 9230 
 9231     // vectored compression
 9232     andl(len, 0xfffffff0);    // vector count (in chars)
 9233     andl(result, 0x0000000f);    // tail count (in chars)
 9234     testl(len, len);
 9235     jcc(Assembler::zero, copy_16);
 9236 
 9237     // compress 16 chars per iter
 9238     movdl(tmp1Reg, tmp5);
 9239     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
 9240     pxor(tmp4Reg, tmp4Reg);
 9241 
 9242     lea(src, Address(src, len, Address::times_2));
 9243     lea(dst, Address(dst, len, Address::times_1));
 9244     negptr(len);
 9245 
 9246     bind(copy_32_loop);
 9247     movdqu(tmp2Reg, Address(src, len, Address::times_2));     // load 1st 8 characters
 9248     por(tmp4Reg, tmp2Reg);
 9249     movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
 9250     por(tmp4Reg, tmp3Reg);
 9251     ptest(tmp4Reg, tmp1Reg);       // check for Unicode chars in next vector
 9252     jcc(Assembler::notZero, return_zero);
 9253     packuswb(tmp2Reg, tmp3Reg);    // only ASCII chars; compress each to 1 byte
 9254     movdqu(Address(dst, len, Address::times_1), tmp2Reg);
 9255     addptr(len, 16);
 9256     jcc(Assembler::notZero, copy_32_loop);
 9257 
 9258     // compress next vector of 8 chars (if any)
 9259     bind(copy_16);
 9260     movl(len, result);
 9261     andl(len, 0xfffffff8);    // vector count (in chars)
 9262     andl(result, 0x00000007);    // tail count (in chars)
 9263     testl(len, len);
 9264     jccb(Assembler::zero, copy_tail);
 9265 
 9266     movdl(tmp1Reg, tmp5);
 9267     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
 9268     pxor(tmp3Reg, tmp3Reg);
 9269 
 9270     movdqu(tmp2Reg, Address(src, 0));
 9271     ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in vector
 9272     jccb(Assembler::notZero, return_zero);
 9273     packuswb(tmp2Reg, tmp3Reg);    // only LATIN1 chars; compress each to 1 byte
 9274     movq(Address(dst, 0), tmp2Reg);
 9275     addptr(src, 16);
 9276     addptr(dst, 8);
 9277 
 9278     bind(copy_tail);
 9279     movl(len, result);
 9280   }
 9281   // compress 1 char per iter
 9282   testl(len, len);
 9283   jccb(Assembler::zero, return_length);
 9284   lea(src, Address(src, len, Address::times_2));
 9285   lea(dst, Address(dst, len, Address::times_1));
 9286   negptr(len);
 9287 
 9288   bind(copy_chars_loop);
 9289   load_unsigned_short(result, Address(src, len, Address::times_2));
 9290   testl(result, 0xff00);      // check if Unicode char
 9291   jccb(Assembler::notZero, return_zero);
 9292   movb(Address(dst, len, Address::times_1), result);  // ASCII char; compress to 1 byte
 9293   increment(len);
 9294   jcc(Assembler::notZero, copy_chars_loop);
 9295 
 9296   // if compression succeeded, return length
 9297   bind(return_length);
 9298   pop(result);
 9299   jmpb(done);
 9300 
 9301   // if compression failed, return 0
 9302   bind(return_zero);
 9303   xorl(result, result);
 9304   addptr(rsp, wordSize);
 9305 
 9306   bind(done);
 9307 }
 9308 
 9309 // Inflate byte[] array to char[].
 9310 //   ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
 9311 //   @IntrinsicCandidate
 9312 //   private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
 9313 //     for (int i = 0; i < len; i++) {
 9314 //       dst[dstOff++] = (char)(src[srcOff++] & 0xff);
 9315 //     }
 9316 //   }
 9317 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
 9318   XMMRegister tmp1, Register tmp2, KRegister mask) {
 9319   Label copy_chars_loop, done, below_threshold, avx3_threshold;
 9320   // rsi: src
 9321   // rdi: dst
 9322   // rdx: len
 9323   // rcx: tmp2
 9324 
 9325   // rsi holds start addr of source byte[] to be inflated
 9326   // rdi holds start addr of destination char[]
 9327   // rdx holds length
 9328   assert_different_registers(src, dst, len, tmp2);
 9329   movl(tmp2, len);
 9330   if ((UseAVX > 2) && // AVX512
 9331     VM_Version::supports_avx512vlbw() &&
 9332     VM_Version::supports_bmi2()) {
 9333 
 9334     Label copy_32_loop, copy_tail;
 9335     Register tmp3_aliased = len;
 9336 
 9337     // if length of the string is less than 16, handle it in an old fashioned way
 9338     testl(len, -16);
 9339     jcc(Assembler::zero, below_threshold);
 9340 
 9341     testl(len, -1 * AVX3Threshold);
 9342     jcc(Assembler::zero, avx3_threshold);
 9343 
 9344     // In order to use only one arithmetic operation for the main loop we use
 9345     // this pre-calculation
 9346     andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
 9347     andl(len, -32);     // vector count
 9348     jccb(Assembler::zero, copy_tail);
 9349 
 9350     lea(src, Address(src, len, Address::times_1));
 9351     lea(dst, Address(dst, len, Address::times_2));
 9352     negptr(len);
 9353 
 9354 
 9355     // inflate 32 chars per iter
 9356     bind(copy_32_loop);
 9357     vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
 9358     evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
 9359     addptr(len, 32);
 9360     jcc(Assembler::notZero, copy_32_loop);
 9361 
 9362     bind(copy_tail);
 9363     // bail out when there is nothing to be done
 9364     testl(tmp2, -1); // we don't destroy the contents of tmp2 here
 9365     jcc(Assembler::zero, done);
 9366 
 9367     // ~(~0 << length), where length is the # of remaining elements to process
 9368     movl(tmp3_aliased, -1);
 9369     shlxl(tmp3_aliased, tmp3_aliased, tmp2);
 9370     notl(tmp3_aliased);
 9371     kmovdl(mask, tmp3_aliased);
 9372     evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
 9373     evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
 9374 
 9375     jmp(done);
 9376     bind(avx3_threshold);
 9377   }
 9378   if (UseSSE42Intrinsics) {
 9379     Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
 9380 
 9381     if (UseAVX > 1) {
 9382       andl(tmp2, (16 - 1));
 9383       andl(len, -16);
 9384       jccb(Assembler::zero, copy_new_tail);
 9385     } else {
 9386       andl(tmp2, 0x00000007);   // tail count (in chars)
 9387       andl(len, 0xfffffff8);    // vector count (in chars)
 9388       jccb(Assembler::zero, copy_tail);
 9389     }
 9390 
 9391     // vectored inflation
 9392     lea(src, Address(src, len, Address::times_1));
 9393     lea(dst, Address(dst, len, Address::times_2));
 9394     negptr(len);
 9395 
 9396     if (UseAVX > 1) {
 9397       bind(copy_16_loop);
 9398       vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
 9399       vmovdqu(Address(dst, len, Address::times_2), tmp1);
 9400       addptr(len, 16);
 9401       jcc(Assembler::notZero, copy_16_loop);
 9402 
 9403       bind(below_threshold);
 9404       bind(copy_new_tail);
 9405       movl(len, tmp2);
 9406       andl(tmp2, 0x00000007);
 9407       andl(len, 0xFFFFFFF8);
 9408       jccb(Assembler::zero, copy_tail);
 9409 
 9410       pmovzxbw(tmp1, Address(src, 0));
 9411       movdqu(Address(dst, 0), tmp1);
 9412       addptr(src, 8);
 9413       addptr(dst, 2 * 8);
 9414 
 9415       jmp(copy_tail, true);
 9416     }
 9417 
 9418     // inflate 8 chars per iter
 9419     bind(copy_8_loop);
 9420     pmovzxbw(tmp1, Address(src, len, Address::times_1));  // unpack to 8 words
 9421     movdqu(Address(dst, len, Address::times_2), tmp1);
 9422     addptr(len, 8);
 9423     jcc(Assembler::notZero, copy_8_loop);
 9424 
 9425     bind(copy_tail);
 9426     movl(len, tmp2);
 9427 
 9428     cmpl(len, 4);
 9429     jccb(Assembler::less, copy_bytes);
 9430 
 9431     movdl(tmp1, Address(src, 0));  // load 4 byte chars
 9432     pmovzxbw(tmp1, tmp1);
 9433     movq(Address(dst, 0), tmp1);
 9434     subptr(len, 4);
 9435     addptr(src, 4);
 9436     addptr(dst, 8);
 9437 
 9438     bind(copy_bytes);
 9439   } else {
 9440     bind(below_threshold);
 9441   }
 9442 
 9443   testl(len, len);
 9444   jccb(Assembler::zero, done);
 9445   lea(src, Address(src, len, Address::times_1));
 9446   lea(dst, Address(dst, len, Address::times_2));
 9447   negptr(len);
 9448 
 9449   // inflate 1 char per iter
 9450   bind(copy_chars_loop);
 9451   load_unsigned_byte(tmp2, Address(src, len, Address::times_1));  // load byte char
 9452   movw(Address(dst, len, Address::times_2), tmp2);  // inflate byte char to word
 9453   increment(len);
 9454   jcc(Assembler::notZero, copy_chars_loop);
 9455 
 9456   bind(done);
 9457 }
 9458 
 9459 
 9460 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
 9461   switch(type) {
 9462     case T_BYTE:
 9463     case T_BOOLEAN:
 9464       evmovdqub(dst, kmask, src, merge, vector_len);
 9465       break;
 9466     case T_CHAR:
 9467     case T_SHORT:
 9468       evmovdquw(dst, kmask, src, merge, vector_len);
 9469       break;
 9470     case T_INT:
 9471     case T_FLOAT:
 9472       evmovdqul(dst, kmask, src, merge, vector_len);
 9473       break;
 9474     case T_LONG:
 9475     case T_DOUBLE:
 9476       evmovdquq(dst, kmask, src, merge, vector_len);
 9477       break;
 9478     default:
 9479       fatal("Unexpected type argument %s", type2name(type));
 9480       break;
 9481   }
 9482 }
 9483 
 9484 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
 9485   switch(type) {
 9486     case T_BYTE:
 9487     case T_BOOLEAN:
 9488       evmovdqub(dst, kmask, src, merge, vector_len);
 9489       break;
 9490     case T_CHAR:
 9491     case T_SHORT:
 9492       evmovdquw(dst, kmask, src, merge, vector_len);
 9493       break;
 9494     case T_INT:
 9495     case T_FLOAT:
 9496       evmovdqul(dst, kmask, src, merge, vector_len);
 9497       break;
 9498     case T_LONG:
 9499     case T_DOUBLE:
 9500       evmovdquq(dst, kmask, src, merge, vector_len);
 9501       break;
 9502     default:
 9503       fatal("Unexpected type argument %s", type2name(type));
 9504       break;
 9505   }
 9506 }
 9507 
 9508 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
 9509   switch(masklen) {
 9510     case 2:
 9511        knotbl(dst, src);
 9512        movl(rtmp, 3);
 9513        kmovbl(ktmp, rtmp);
 9514        kandbl(dst, ktmp, dst);
 9515        break;
 9516     case 4:
 9517        knotbl(dst, src);
 9518        movl(rtmp, 15);
 9519        kmovbl(ktmp, rtmp);
 9520        kandbl(dst, ktmp, dst);
 9521        break;
 9522     case 8:
 9523        knotbl(dst, src);
 9524        break;
 9525     case 16:
 9526        knotwl(dst, src);
 9527        break;
 9528     case 32:
 9529        knotdl(dst, src);
 9530        break;
 9531     case 64:
 9532        knotql(dst, src);
 9533        break;
 9534     default:
 9535       fatal("Unexpected vector length %d", masklen);
 9536       break;
 9537   }
 9538 }
 9539 
 9540 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
 9541   switch(type) {
 9542     case T_BOOLEAN:
 9543     case T_BYTE:
 9544        kandbl(dst, src1, src2);
 9545        break;
 9546     case T_CHAR:
 9547     case T_SHORT:
 9548        kandwl(dst, src1, src2);
 9549        break;
 9550     case T_INT:
 9551     case T_FLOAT:
 9552        kanddl(dst, src1, src2);
 9553        break;
 9554     case T_LONG:
 9555     case T_DOUBLE:
 9556        kandql(dst, src1, src2);
 9557        break;
 9558     default:
 9559       fatal("Unexpected type argument %s", type2name(type));
 9560       break;
 9561   }
 9562 }
 9563 
 9564 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
 9565   switch(type) {
 9566     case T_BOOLEAN:
 9567     case T_BYTE:
 9568        korbl(dst, src1, src2);
 9569        break;
 9570     case T_CHAR:
 9571     case T_SHORT:
 9572        korwl(dst, src1, src2);
 9573        break;
 9574     case T_INT:
 9575     case T_FLOAT:
 9576        kordl(dst, src1, src2);
 9577        break;
 9578     case T_LONG:
 9579     case T_DOUBLE:
 9580        korql(dst, src1, src2);
 9581        break;
 9582     default:
 9583       fatal("Unexpected type argument %s", type2name(type));
 9584       break;
 9585   }
 9586 }
 9587 
 9588 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
 9589   switch(type) {
 9590     case T_BOOLEAN:
 9591     case T_BYTE:
 9592        kxorbl(dst, src1, src2);
 9593        break;
 9594     case T_CHAR:
 9595     case T_SHORT:
 9596        kxorwl(dst, src1, src2);
 9597        break;
 9598     case T_INT:
 9599     case T_FLOAT:
 9600        kxordl(dst, src1, src2);
 9601        break;
 9602     case T_LONG:
 9603     case T_DOUBLE:
 9604        kxorql(dst, src1, src2);
 9605        break;
 9606     default:
 9607       fatal("Unexpected type argument %s", type2name(type));
 9608       break;
 9609   }
 9610 }
 9611 
 9612 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9613   switch(type) {
 9614     case T_BOOLEAN:
 9615     case T_BYTE:
 9616       evpermb(dst, mask, nds, src, merge, vector_len); break;
 9617     case T_CHAR:
 9618     case T_SHORT:
 9619       evpermw(dst, mask, nds, src, merge, vector_len); break;
 9620     case T_INT:
 9621     case T_FLOAT:
 9622       evpermd(dst, mask, nds, src, merge, vector_len); break;
 9623     case T_LONG:
 9624     case T_DOUBLE:
 9625       evpermq(dst, mask, nds, src, merge, vector_len); break;
 9626     default:
 9627       fatal("Unexpected type argument %s", type2name(type)); break;
 9628   }
 9629 }
 9630 
 9631 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9632   switch(type) {
 9633     case T_BOOLEAN:
 9634     case T_BYTE:
 9635       evpermb(dst, mask, nds, src, merge, vector_len); break;
 9636     case T_CHAR:
 9637     case T_SHORT:
 9638       evpermw(dst, mask, nds, src, merge, vector_len); break;
 9639     case T_INT:
 9640     case T_FLOAT:
 9641       evpermd(dst, mask, nds, src, merge, vector_len); break;
 9642     case T_LONG:
 9643     case T_DOUBLE:
 9644       evpermq(dst, mask, nds, src, merge, vector_len); break;
 9645     default:
 9646       fatal("Unexpected type argument %s", type2name(type)); break;
 9647   }
 9648 }
 9649 
 9650 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9651   switch(type) {
 9652     case T_BYTE:
 9653       evpminsb(dst, mask, nds, src, merge, vector_len); break;
 9654     case T_SHORT:
 9655       evpminsw(dst, mask, nds, src, merge, vector_len); break;
 9656     case T_INT:
 9657       evpminsd(dst, mask, nds, src, merge, vector_len); break;
 9658     case T_LONG:
 9659       evpminsq(dst, mask, nds, src, merge, vector_len); break;
 9660     default:
 9661       fatal("Unexpected type argument %s", type2name(type)); break;
 9662   }
 9663 }
 9664 
 9665 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9666   switch(type) {
 9667     case T_BYTE:
 9668       evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
 9669     case T_SHORT:
 9670       evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
 9671     case T_INT:
 9672       evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
 9673     case T_LONG:
 9674       evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
 9675     default:
 9676       fatal("Unexpected type argument %s", type2name(type)); break;
 9677   }
 9678 }
 9679 
 9680 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9681   switch(type) {
 9682     case T_BYTE:
 9683       evpminsb(dst, mask, nds, src, merge, vector_len); break;
 9684     case T_SHORT:
 9685       evpminsw(dst, mask, nds, src, merge, vector_len); break;
 9686     case T_INT:
 9687       evpminsd(dst, mask, nds, src, merge, vector_len); break;
 9688     case T_LONG:
 9689       evpminsq(dst, mask, nds, src, merge, vector_len); break;
 9690     default:
 9691       fatal("Unexpected type argument %s", type2name(type)); break;
 9692   }
 9693 }
 9694 
 9695 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9696   switch(type) {
 9697     case T_BYTE:
 9698       evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
 9699     case T_SHORT:
 9700       evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
 9701     case T_INT:
 9702       evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
 9703     case T_LONG:
 9704       evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
 9705     default:
 9706       fatal("Unexpected type argument %s", type2name(type)); break;
 9707   }
 9708 }
 9709 
 9710 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9711   switch(type) {
 9712     case T_INT:
 9713       evpxord(dst, mask, nds, src, merge, vector_len); break;
 9714     case T_LONG:
 9715       evpxorq(dst, mask, nds, src, merge, vector_len); break;
 9716     default:
 9717       fatal("Unexpected type argument %s", type2name(type)); break;
 9718   }
 9719 }
 9720 
 9721 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9722   switch(type) {
 9723     case T_INT:
 9724       evpxord(dst, mask, nds, src, merge, vector_len); break;
 9725     case T_LONG:
 9726       evpxorq(dst, mask, nds, src, merge, vector_len); break;
 9727     default:
 9728       fatal("Unexpected type argument %s", type2name(type)); break;
 9729   }
 9730 }
 9731 
 9732 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9733   switch(type) {
 9734     case T_INT:
 9735       Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
 9736     case T_LONG:
 9737       evporq(dst, mask, nds, src, merge, vector_len); break;
 9738     default:
 9739       fatal("Unexpected type argument %s", type2name(type)); break;
 9740   }
 9741 }
 9742 
 9743 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9744   switch(type) {
 9745     case T_INT:
 9746       Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
 9747     case T_LONG:
 9748       evporq(dst, mask, nds, src, merge, vector_len); break;
 9749     default:
 9750       fatal("Unexpected type argument %s", type2name(type)); break;
 9751   }
 9752 }
 9753 
 9754 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9755   switch(type) {
 9756     case T_INT:
 9757       evpandd(dst, mask, nds, src, merge, vector_len); break;
 9758     case T_LONG:
 9759       evpandq(dst, mask, nds, src, merge, vector_len); break;
 9760     default:
 9761       fatal("Unexpected type argument %s", type2name(type)); break;
 9762   }
 9763 }
 9764 
 9765 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9766   switch(type) {
 9767     case T_INT:
 9768       evpandd(dst, mask, nds, src, merge, vector_len); break;
 9769     case T_LONG:
 9770       evpandq(dst, mask, nds, src, merge, vector_len); break;
 9771     default:
 9772       fatal("Unexpected type argument %s", type2name(type)); break;
 9773   }
 9774 }
 9775 
 9776 void MacroAssembler::anytrue(Register dst, uint masklen, KRegister src1, KRegister src2) {
 9777    masklen = masklen < 8 ? 8 : masklen;
 9778    ktest(masklen, src1, src2);
 9779    setb(Assembler::notZero, dst);
 9780    movzbl(dst, dst);
 9781 }
 9782 
 9783 void MacroAssembler::alltrue(Register dst, uint masklen, KRegister src1, KRegister src2, KRegister kscratch) {
 9784   if (masklen < 8) {
 9785     knotbl(kscratch, src2);
 9786     kortestbl(src1, kscratch);
 9787     setb(Assembler::carrySet, dst);
 9788     movzbl(dst, dst);
 9789   } else {
 9790     ktest(masklen, src1, src2);
 9791     setb(Assembler::carrySet, dst);
 9792     movzbl(dst, dst);
 9793   }
 9794 }
 9795 
 9796 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
 9797   switch(masklen) {
 9798     case 8:
 9799        kortestbl(src1, src2);
 9800        break;
 9801     case 16:
 9802        kortestwl(src1, src2);
 9803        break;
 9804     case 32:
 9805        kortestdl(src1, src2);
 9806        break;
 9807     case 64:
 9808        kortestql(src1, src2);
 9809        break;
 9810     default:
 9811       fatal("Unexpected mask length %d", masklen);
 9812       break;
 9813   }
 9814 }
 9815 
 9816 
 9817 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
 9818   switch(masklen)  {
 9819     case 8:
 9820        ktestbl(src1, src2);
 9821        break;
 9822     case 16:
 9823        ktestwl(src1, src2);
 9824        break;
 9825     case 32:
 9826        ktestdl(src1, src2);
 9827        break;
 9828     case 64:
 9829        ktestql(src1, src2);
 9830        break;
 9831     default:
 9832       fatal("Unexpected mask length %d", masklen);
 9833       break;
 9834   }
 9835 }
 9836 
 9837 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
 9838   switch(type) {
 9839     case T_INT:
 9840       evprold(dst, mask, src, shift, merge, vlen_enc); break;
 9841     case T_LONG:
 9842       evprolq(dst, mask, src, shift, merge, vlen_enc); break;
 9843     default:
 9844       fatal("Unexpected type argument %s", type2name(type)); break;
 9845       break;
 9846   }
 9847 }
 9848 
 9849 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
 9850   switch(type) {
 9851     case T_INT:
 9852       evprord(dst, mask, src, shift, merge, vlen_enc); break;
 9853     case T_LONG:
 9854       evprorq(dst, mask, src, shift, merge, vlen_enc); break;
 9855     default:
 9856       fatal("Unexpected type argument %s", type2name(type)); break;
 9857   }
 9858 }
 9859 
 9860 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
 9861   switch(type) {
 9862     case T_INT:
 9863       evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
 9864     case T_LONG:
 9865       evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
 9866     default:
 9867       fatal("Unexpected type argument %s", type2name(type)); break;
 9868   }
 9869 }
 9870 
 9871 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
 9872   switch(type) {
 9873     case T_INT:
 9874       evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
 9875     case T_LONG:
 9876       evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
 9877     default:
 9878       fatal("Unexpected type argument %s", type2name(type)); break;
 9879   }
 9880 }
 9881 #if COMPILER2_OR_JVMCI
 9882 
 9883 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
 9884                                  Register length, Register temp, int vec_enc) {
 9885   // Computing mask for predicated vector store.
 9886   movptr(temp, -1);
 9887   bzhiq(temp, temp, length);
 9888   kmov(mask, temp);
 9889   evmovdqu(bt, mask, dst, xmm, true, vec_enc);
 9890 }
 9891 
 9892 // Set memory operation for length "less than" 64 bytes.
 9893 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
 9894                                        XMMRegister xmm, KRegister mask, Register length,
 9895                                        Register temp, bool use64byteVector) {
 9896   assert(MaxVectorSize >= 32, "vector length should be >= 32");
 9897   BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
 9898   if (!use64byteVector) {
 9899     fill32(dst, disp, xmm);
 9900     subptr(length, 32 >> shift);
 9901     fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
 9902   } else {
 9903     assert(MaxVectorSize == 64, "vector length != 64");
 9904     fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
 9905   }
 9906 }
 9907 
 9908 
 9909 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
 9910                                        XMMRegister xmm, KRegister mask, Register length,
 9911                                        Register temp) {
 9912   assert(MaxVectorSize >= 32, "vector length should be >= 32");
 9913   BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
 9914   fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
 9915 }
 9916 
 9917 
 9918 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
 9919   assert(MaxVectorSize >= 32, "vector length should be >= 32");
 9920   vmovdqu(dst, xmm);
 9921 }
 9922 
 9923 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
 9924   fill32(Address(dst, disp), xmm);
 9925 }
 9926 
 9927 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
 9928   assert(MaxVectorSize >= 32, "vector length should be >= 32");
 9929   if (!use64byteVector) {
 9930     fill32(dst, xmm);
 9931     fill32(dst.plus_disp(32), xmm);
 9932   } else {
 9933     evmovdquq(dst, xmm, Assembler::AVX_512bit);
 9934   }
 9935 }
 9936 
 9937 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
 9938   fill64(Address(dst, disp), xmm, use64byteVector);
 9939 }
 9940 
 9941 #ifdef _LP64
 9942 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
 9943                                         Register count, Register rtmp, XMMRegister xtmp) {
 9944   Label L_exit;
 9945   Label L_fill_start;
 9946   Label L_fill_64_bytes;
 9947   Label L_fill_96_bytes;
 9948   Label L_fill_128_bytes;
 9949   Label L_fill_128_bytes_loop;
 9950   Label L_fill_128_loop_header;
 9951   Label L_fill_128_bytes_loop_header;
 9952   Label L_fill_128_bytes_loop_pre_header;
 9953   Label L_fill_zmm_sequence;
 9954 
 9955   int shift = -1;
 9956   int avx3threshold = VM_Version::avx3_threshold();
 9957   switch(type) {
 9958     case T_BYTE:  shift = 0;
 9959       break;
 9960     case T_SHORT: shift = 1;
 9961       break;
 9962     case T_INT:   shift = 2;
 9963       break;
 9964     /* Uncomment when LONG fill stubs are supported.
 9965     case T_LONG:  shift = 3;
 9966       break;
 9967     */
 9968     default:
 9969       fatal("Unhandled type: %s\n", type2name(type));
 9970   }
 9971 
 9972   if ((avx3threshold != 0)  || (MaxVectorSize == 32)) {
 9973 
 9974     if (MaxVectorSize == 64) {
 9975       cmpq(count, avx3threshold >> shift);
 9976       jcc(Assembler::greater, L_fill_zmm_sequence);
 9977     }
 9978 
 9979     evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
 9980 
 9981     bind(L_fill_start);
 9982 
 9983     cmpq(count, 32 >> shift);
 9984     jccb(Assembler::greater, L_fill_64_bytes);
 9985     fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
 9986     jmp(L_exit);
 9987 
 9988     bind(L_fill_64_bytes);
 9989     cmpq(count, 64 >> shift);
 9990     jccb(Assembler::greater, L_fill_96_bytes);
 9991     fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
 9992     jmp(L_exit);
 9993 
 9994     bind(L_fill_96_bytes);
 9995     cmpq(count, 96 >> shift);
 9996     jccb(Assembler::greater, L_fill_128_bytes);
 9997     fill64(to, 0, xtmp);
 9998     subq(count, 64 >> shift);
 9999     fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10000     jmp(L_exit);
10001 
10002     bind(L_fill_128_bytes);
10003     cmpq(count, 128 >> shift);
10004     jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10005     fill64(to, 0, xtmp);
10006     fill32(to, 64, xtmp);
10007     subq(count, 96 >> shift);
10008     fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10009     jmp(L_exit);
10010 
10011     bind(L_fill_128_bytes_loop_pre_header);
10012     {
10013       mov(rtmp, to);
10014       andq(rtmp, 31);
10015       jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10016       negq(rtmp);
10017       addq(rtmp, 32);
10018       mov64(r8, -1L);
10019       bzhiq(r8, r8, rtmp);
10020       kmovql(k2, r8);
10021       evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10022       addq(to, rtmp);
10023       shrq(rtmp, shift);
10024       subq(count, rtmp);
10025     }
10026 
10027     cmpq(count, 128 >> shift);
10028     jcc(Assembler::less, L_fill_start);
10029 
10030     bind(L_fill_128_bytes_loop_header);
10031     subq(count, 128 >> shift);
10032 
10033     align32();
10034     bind(L_fill_128_bytes_loop);
10035       fill64(to, 0, xtmp);
10036       fill64(to, 64, xtmp);
10037       addq(to, 128);
10038       subq(count, 128 >> shift);
10039       jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10040 
10041     addq(count, 128 >> shift);
10042     jcc(Assembler::zero, L_exit);
10043     jmp(L_fill_start);
10044   }
10045 
10046   if (MaxVectorSize == 64) {
10047     // Sequence using 64 byte ZMM register.
10048     Label L_fill_128_bytes_zmm;
10049     Label L_fill_192_bytes_zmm;
10050     Label L_fill_192_bytes_loop_zmm;
10051     Label L_fill_192_bytes_loop_header_zmm;
10052     Label L_fill_192_bytes_loop_pre_header_zmm;
10053     Label L_fill_start_zmm_sequence;
10054 
10055     bind(L_fill_zmm_sequence);
10056     evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10057 
10058     bind(L_fill_start_zmm_sequence);
10059     cmpq(count, 64 >> shift);
10060     jccb(Assembler::greater, L_fill_128_bytes_zmm);
10061     fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10062     jmp(L_exit);
10063 
10064     bind(L_fill_128_bytes_zmm);
10065     cmpq(count, 128 >> shift);
10066     jccb(Assembler::greater, L_fill_192_bytes_zmm);
10067     fill64(to, 0, xtmp, true);
10068     subq(count, 64 >> shift);
10069     fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10070     jmp(L_exit);
10071 
10072     bind(L_fill_192_bytes_zmm);
10073     cmpq(count, 192 >> shift);
10074     jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10075     fill64(to, 0, xtmp, true);
10076     fill64(to, 64, xtmp, true);
10077     subq(count, 128 >> shift);
10078     fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10079     jmp(L_exit);
10080 
10081     bind(L_fill_192_bytes_loop_pre_header_zmm);
10082     {
10083       movq(rtmp, to);
10084       andq(rtmp, 63);
10085       jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10086       negq(rtmp);
10087       addq(rtmp, 64);
10088       mov64(r8, -1L);
10089       bzhiq(r8, r8, rtmp);
10090       kmovql(k2, r8);
10091       evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10092       addq(to, rtmp);
10093       shrq(rtmp, shift);
10094       subq(count, rtmp);
10095     }
10096 
10097     cmpq(count, 192 >> shift);
10098     jcc(Assembler::less, L_fill_start_zmm_sequence);
10099 
10100     bind(L_fill_192_bytes_loop_header_zmm);
10101     subq(count, 192 >> shift);
10102 
10103     align32();
10104     bind(L_fill_192_bytes_loop_zmm);
10105       fill64(to, 0, xtmp, true);
10106       fill64(to, 64, xtmp, true);
10107       fill64(to, 128, xtmp, true);
10108       addq(to, 192);
10109       subq(count, 192 >> shift);
10110       jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10111 
10112     addq(count, 192 >> shift);
10113     jcc(Assembler::zero, L_exit);
10114     jmp(L_fill_start_zmm_sequence);
10115   }
10116   bind(L_exit);
10117 }
10118 #endif
10119 #endif //COMPILER2_OR_JVMCI
10120 
10121 
10122 #ifdef _LP64
10123 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10124   Label done;
10125   cvttss2sil(dst, src);
10126   // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10127   cmpl(dst, 0x80000000); // float_sign_flip
10128   jccb(Assembler::notEqual, done);
10129   subptr(rsp, 8);
10130   movflt(Address(rsp, 0), src);
10131   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10132   pop(dst);
10133   bind(done);
10134 }
10135 
10136 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10137   Label done;
10138   cvttsd2sil(dst, src);
10139   // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10140   cmpl(dst, 0x80000000); // float_sign_flip
10141   jccb(Assembler::notEqual, done);
10142   subptr(rsp, 8);
10143   movdbl(Address(rsp, 0), src);
10144   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10145   pop(dst);
10146   bind(done);
10147 }
10148 
10149 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10150   Label done;
10151   cvttss2siq(dst, src);
10152   cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10153   jccb(Assembler::notEqual, done);
10154   subptr(rsp, 8);
10155   movflt(Address(rsp, 0), src);
10156   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10157   pop(dst);
10158   bind(done);
10159 }
10160 
10161 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10162   // Following code is line by line assembly translation rounding algorithm.
10163   // Please refer to java.lang.Math.round(float) algorithm for details.
10164   const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10165   const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10166   const int32_t FloatConsts_EXP_BIAS = 127;
10167   const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10168   const int32_t MINUS_32 = 0xFFFFFFE0;
10169   Label L_special_case, L_block1, L_exit;
10170   movl(rtmp, FloatConsts_EXP_BIT_MASK);
10171   movdl(dst, src);
10172   andl(dst, rtmp);
10173   sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10174   movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10175   subl(rtmp, dst);
10176   movl(rcx, rtmp);
10177   movl(dst, MINUS_32);
10178   testl(rtmp, dst);
10179   jccb(Assembler::notEqual, L_special_case);
10180   movdl(dst, src);
10181   andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10182   orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10183   movdl(rtmp, src);
10184   testl(rtmp, rtmp);
10185   jccb(Assembler::greaterEqual, L_block1);
10186   negl(dst);
10187   bind(L_block1);
10188   sarl(dst);
10189   addl(dst, 0x1);
10190   sarl(dst, 0x1);
10191   jmp(L_exit);
10192   bind(L_special_case);
10193   convert_f2i(dst, src);
10194   bind(L_exit);
10195 }
10196 
10197 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10198   // Following code is line by line assembly translation rounding algorithm.
10199   // Please refer to java.lang.Math.round(double) algorithm for details.
10200   const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10201   const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10202   const int64_t DoubleConsts_EXP_BIAS = 1023;
10203   const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10204   const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10205   Label L_special_case, L_block1, L_exit;
10206   mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10207   movq(dst, src);
10208   andq(dst, rtmp);
10209   sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10210   mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10211   subq(rtmp, dst);
10212   movq(rcx, rtmp);
10213   mov64(dst, MINUS_64);
10214   testq(rtmp, dst);
10215   jccb(Assembler::notEqual, L_special_case);
10216   movq(dst, src);
10217   mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10218   andq(dst, rtmp);
10219   mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10220   orq(dst, rtmp);
10221   movq(rtmp, src);
10222   testq(rtmp, rtmp);
10223   jccb(Assembler::greaterEqual, L_block1);
10224   negq(dst);
10225   bind(L_block1);
10226   sarq(dst);
10227   addq(dst, 0x1);
10228   sarq(dst, 0x1);
10229   jmp(L_exit);
10230   bind(L_special_case);
10231   convert_d2l(dst, src);
10232   bind(L_exit);
10233 }
10234 
10235 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10236   Label done;
10237   cvttsd2siq(dst, src);
10238   cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10239   jccb(Assembler::notEqual, done);
10240   subptr(rsp, 8);
10241   movdbl(Address(rsp, 0), src);
10242   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10243   pop(dst);
10244   bind(done);
10245 }
10246 
10247 void MacroAssembler::cache_wb(Address line)
10248 {
10249   // 64 bit cpus always support clflush
10250   assert(VM_Version::supports_clflush(), "clflush should be available");
10251   bool optimized = VM_Version::supports_clflushopt();
10252   bool no_evict = VM_Version::supports_clwb();
10253 
10254   // prefer clwb (writeback without evict) otherwise
10255   // prefer clflushopt (potentially parallel writeback with evict)
10256   // otherwise fallback on clflush (serial writeback with evict)
10257 
10258   if (optimized) {
10259     if (no_evict) {
10260       clwb(line);
10261     } else {
10262       clflushopt(line);
10263     }
10264   } else {
10265     // no need for fence when using CLFLUSH
10266     clflush(line);
10267   }
10268 }
10269 
10270 void MacroAssembler::cache_wbsync(bool is_pre)
10271 {
10272   assert(VM_Version::supports_clflush(), "clflush should be available");
10273   bool optimized = VM_Version::supports_clflushopt();
10274   bool no_evict = VM_Version::supports_clwb();
10275 
10276   // pick the correct implementation
10277 
10278   if (!is_pre && (optimized || no_evict)) {
10279     // need an sfence for post flush when using clflushopt or clwb
10280     // otherwise no no need for any synchroniaztion
10281 
10282     sfence();
10283   }
10284 }
10285 
10286 #endif // _LP64
10287 
10288 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10289   switch (cond) {
10290     // Note some conditions are synonyms for others
10291     case Assembler::zero:         return Assembler::notZero;
10292     case Assembler::notZero:      return Assembler::zero;
10293     case Assembler::less:         return Assembler::greaterEqual;
10294     case Assembler::lessEqual:    return Assembler::greater;
10295     case Assembler::greater:      return Assembler::lessEqual;
10296     case Assembler::greaterEqual: return Assembler::less;
10297     case Assembler::below:        return Assembler::aboveEqual;
10298     case Assembler::belowEqual:   return Assembler::above;
10299     case Assembler::above:        return Assembler::belowEqual;
10300     case Assembler::aboveEqual:   return Assembler::below;
10301     case Assembler::overflow:     return Assembler::noOverflow;
10302     case Assembler::noOverflow:   return Assembler::overflow;
10303     case Assembler::negative:     return Assembler::positive;
10304     case Assembler::positive:     return Assembler::negative;
10305     case Assembler::parity:       return Assembler::noParity;
10306     case Assembler::noParity:     return Assembler::parity;
10307   }
10308   ShouldNotReachHere(); return Assembler::overflow;
10309 }
10310 
10311 SkipIfEqual::SkipIfEqual(
10312     MacroAssembler* masm, const bool* flag_addr, bool value, Register rscratch) {
10313   _masm = masm;
10314   _masm->cmp8(ExternalAddress((address)flag_addr), value, rscratch);
10315   _masm->jcc(Assembler::equal, _label);
10316 }
10317 
10318 SkipIfEqual::~SkipIfEqual() {
10319   _masm->bind(_label);
10320 }
10321 
10322 // 32-bit Windows has its own fast-path implementation
10323 // of get_thread
10324 #if !defined(WIN32) || defined(_LP64)
10325 
10326 // This is simply a call to Thread::current()
10327 void MacroAssembler::get_thread(Register thread) {
10328   if (thread != rax) {
10329     push(rax);
10330   }
10331   LP64_ONLY(push(rdi);)
10332   LP64_ONLY(push(rsi);)
10333   push(rdx);
10334   push(rcx);
10335 #ifdef _LP64
10336   push(r8);
10337   push(r9);
10338   push(r10);
10339   push(r11);
10340 #endif
10341 
10342   MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10343 
10344 #ifdef _LP64
10345   pop(r11);
10346   pop(r10);
10347   pop(r9);
10348   pop(r8);
10349 #endif
10350   pop(rcx);
10351   pop(rdx);
10352   LP64_ONLY(pop(rsi);)
10353   LP64_ONLY(pop(rdi);)
10354   if (thread != rax) {
10355     mov(thread, rax);
10356     pop(rax);
10357   }
10358 }
10359 
10360 
10361 #endif // !WIN32 || _LP64
10362 
10363 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10364   Label L_stack_ok;
10365   if (bias == 0) {
10366     testptr(sp, 2 * wordSize - 1);
10367   } else {
10368     // lea(tmp, Address(rsp, bias);
10369     mov(tmp, sp);
10370     addptr(tmp, bias);
10371     testptr(tmp, 2 * wordSize - 1);
10372   }
10373   jcc(Assembler::equal, L_stack_ok);
10374   block_comment(msg);
10375   stop(msg);
10376   bind(L_stack_ok);
10377 }