1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/aotCodeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "ci/ciInlineKlass.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "interpreter/interpreterRuntime.hpp"
40 #include "jvm.h"
41 #include "memory/resourceArea.hpp"
42 #include "memory/universe.hpp"
43 #include "oops/accessDecorators.hpp"
44 #include "oops/compressedKlass.inline.hpp"
45 #include "oops/compressedOops.inline.hpp"
46 #include "oops/klass.inline.hpp"
47 #include "oops/resolvedFieldEntry.hpp"
48 #include "prims/methodHandles.hpp"
49 #include "runtime/arguments.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/interfaceSupport.inline.hpp"
52 #include "runtime/javaThread.hpp"
53 #include "runtime/jniHandles.hpp"
54 #include "runtime/objectMonitor.hpp"
55 #include "runtime/os.hpp"
56 #include "runtime/safepoint.hpp"
57 #include "runtime/safepointMechanism.hpp"
58 #include "runtime/sharedRuntime.hpp"
59 #include "runtime/signature_cc.hpp"
60 #include "runtime/stubRoutines.hpp"
61 #include "utilities/checkedCast.hpp"
62 #include "utilities/globalDefinitions.hpp"
63 #include "utilities/macros.hpp"
64 #include "vmreg_x86.inline.hpp"
65 #ifdef COMPILER2
66 #include "opto/output.hpp"
67 #endif
68
69 #ifdef PRODUCT
70 #define BLOCK_COMMENT(str) /* nothing */
71 #define STOP(error) stop(error)
72 #else
73 #define BLOCK_COMMENT(str) block_comment(str)
74 #define STOP(error) block_comment(error); stop(error)
75 #endif
76
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
79 #ifdef ASSERT
80 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
81 #endif
82
83 static const Assembler::Condition reverse[] = {
84 Assembler::noOverflow /* overflow = 0x0 */ ,
85 Assembler::overflow /* noOverflow = 0x1 */ ,
86 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
87 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
88 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
89 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
90 Assembler::above /* belowEqual = 0x6 */ ,
91 Assembler::belowEqual /* above = 0x7 */ ,
92 Assembler::positive /* negative = 0x8 */ ,
93 Assembler::negative /* positive = 0x9 */ ,
94 Assembler::noParity /* parity = 0xa */ ,
95 Assembler::parity /* noParity = 0xb */ ,
96 Assembler::greaterEqual /* less = 0xc */ ,
97 Assembler::less /* greaterEqual = 0xd */ ,
98 Assembler::greater /* lessEqual = 0xe */ ,
99 Assembler::lessEqual /* greater = 0xf, */
100
101 };
102
103
104 // Implementation of MacroAssembler
105
106 Address MacroAssembler::as_Address(AddressLiteral adr) {
107 // amd64 always does this as a pc-rel
108 // we can be absolute or disp based on the instruction type
109 // jmp/call are displacements others are absolute
110 assert(!adr.is_lval(), "must be rval");
111 assert(reachable(adr), "must be");
112 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
113
114 }
115
116 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
117 AddressLiteral base = adr.base();
118 lea(rscratch, base);
119 Address index = adr.index();
120 assert(index._disp == 0, "must not have disp"); // maybe it can?
121 Address array(rscratch, index._index, index._scale, index._disp);
122 return array;
123 }
124
125 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
126 Label L, E;
127
128 #ifdef _WIN64
129 // Windows always allocates space for it's register args
130 assert(num_args <= 4, "only register arguments supported");
131 subq(rsp, frame::arg_reg_save_area_bytes);
132 #endif
133
134 // Align stack if necessary
135 testl(rsp, 15);
136 jcc(Assembler::zero, L);
137
138 subq(rsp, 8);
139 call(RuntimeAddress(entry_point));
140 addq(rsp, 8);
141 jmp(E);
142
143 bind(L);
144 call(RuntimeAddress(entry_point));
145
146 bind(E);
147
148 #ifdef _WIN64
149 // restore stack pointer
150 addq(rsp, frame::arg_reg_save_area_bytes);
151 #endif
152 }
153
154 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
155 assert(!src2.is_lval(), "should use cmpptr");
156 assert(rscratch != noreg || always_reachable(src2), "missing");
157
158 if (reachable(src2)) {
159 cmpq(src1, as_Address(src2));
160 } else {
161 lea(rscratch, src2);
162 Assembler::cmpq(src1, Address(rscratch, 0));
163 }
164 }
165
166 int MacroAssembler::corrected_idivq(Register reg) {
167 // Full implementation of Java ldiv and lrem; checks for special
168 // case as described in JVM spec., p.243 & p.271. The function
169 // returns the (pc) offset of the idivl instruction - may be needed
170 // for implicit exceptions.
171 //
172 // normal case special case
173 //
174 // input : rax: dividend min_long
175 // reg: divisor (may not be eax/edx) -1
176 //
177 // output: rax: quotient (= rax idiv reg) min_long
178 // rdx: remainder (= rax irem reg) 0
179 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
180 static const int64_t min_long = 0x8000000000000000;
181 Label normal_case, special_case;
182
183 // check for special case
184 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
185 jcc(Assembler::notEqual, normal_case);
186 xorl(rdx, rdx); // prepare rdx for possible special case (where
187 // remainder = 0)
188 cmpq(reg, -1);
189 jcc(Assembler::equal, special_case);
190
191 // handle normal case
192 bind(normal_case);
193 cdqq();
194 int idivq_offset = offset();
195 idivq(reg);
196
197 // normal and special case exit
198 bind(special_case);
199
200 return idivq_offset;
201 }
202
203 void MacroAssembler::decrementq(Register reg, int value) {
204 if (value == min_jint) { subq(reg, value); return; }
205 if (value < 0) { incrementq(reg, -value); return; }
206 if (value == 0) { ; return; }
207 if (value == 1 && UseIncDec) { decq(reg) ; return; }
208 /* else */ { subq(reg, value) ; return; }
209 }
210
211 void MacroAssembler::decrementq(Address dst, int value) {
212 if (value == min_jint) { subq(dst, value); return; }
213 if (value < 0) { incrementq(dst, -value); return; }
214 if (value == 0) { ; return; }
215 if (value == 1 && UseIncDec) { decq(dst) ; return; }
216 /* else */ { subq(dst, value) ; return; }
217 }
218
219 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
220 assert(rscratch != noreg || always_reachable(dst), "missing");
221
222 if (reachable(dst)) {
223 incrementq(as_Address(dst));
224 } else {
225 lea(rscratch, dst);
226 incrementq(Address(rscratch, 0));
227 }
228 }
229
230 void MacroAssembler::incrementq(Register reg, int value) {
231 if (value == min_jint) { addq(reg, value); return; }
232 if (value < 0) { decrementq(reg, -value); return; }
233 if (value == 0) { ; return; }
234 if (value == 1 && UseIncDec) { incq(reg) ; return; }
235 /* else */ { addq(reg, value) ; return; }
236 }
237
238 void MacroAssembler::incrementq(Address dst, int value) {
239 if (value == min_jint) { addq(dst, value); return; }
240 if (value < 0) { decrementq(dst, -value); return; }
241 if (value == 0) { ; return; }
242 if (value == 1 && UseIncDec) { incq(dst) ; return; }
243 /* else */ { addq(dst, value) ; return; }
244 }
245
246 // 32bit can do a case table jump in one instruction but we no longer allow the base
247 // to be installed in the Address class
248 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
249 lea(rscratch, entry.base());
250 Address dispatch = entry.index();
251 assert(dispatch._base == noreg, "must be");
252 dispatch._base = rscratch;
253 jmp(dispatch);
254 }
255
256 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
257 ShouldNotReachHere(); // 64bit doesn't use two regs
258 cmpq(x_lo, y_lo);
259 }
260
261 void MacroAssembler::lea(Register dst, AddressLiteral src) {
262 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
263 }
264
265 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
266 lea(rscratch, adr);
267 movptr(dst, rscratch);
268 }
269
270 void MacroAssembler::leave() {
271 // %%% is this really better? Why not on 32bit too?
272 emit_int8((unsigned char)0xC9); // LEAVE
273 }
274
275 void MacroAssembler::lneg(Register hi, Register lo) {
276 ShouldNotReachHere(); // 64bit doesn't use two regs
277 negq(lo);
278 }
279
280 void MacroAssembler::movoop(Register dst, jobject obj) {
281 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
282 }
283
284 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
285 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
286 movq(dst, rscratch);
287 }
288
289 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
290 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
291 }
292
293 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
294 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
295 movq(dst, rscratch);
296 }
297
298 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
299 if (src.is_lval()) {
300 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
301 } else {
302 if (reachable(src)) {
303 movq(dst, as_Address(src));
304 } else {
305 lea(dst, src);
306 movq(dst, Address(dst, 0));
307 }
308 }
309 }
310
311 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
312 movq(as_Address(dst, rscratch), src);
313 }
314
315 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
316 movq(dst, as_Address(src, dst /*rscratch*/));
317 }
318
319 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
320 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
321 if (is_simm32(src)) {
322 movptr(dst, checked_cast<int32_t>(src));
323 } else {
324 mov64(rscratch, src);
325 movq(dst, rscratch);
326 }
327 }
328
329 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
330 movoop(rscratch, obj);
331 push(rscratch);
332 }
333
334 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
335 mov_metadata(rscratch, obj);
336 push(rscratch);
337 }
338
339 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
340 lea(rscratch, src);
341 if (src.is_lval()) {
342 push(rscratch);
343 } else {
344 pushq(Address(rscratch, 0));
345 }
346 }
347
348 static void pass_arg0(MacroAssembler* masm, Register arg) {
349 if (c_rarg0 != arg ) {
350 masm->mov(c_rarg0, arg);
351 }
352 }
353
354 static void pass_arg1(MacroAssembler* masm, Register arg) {
355 if (c_rarg1 != arg ) {
356 masm->mov(c_rarg1, arg);
357 }
358 }
359
360 static void pass_arg2(MacroAssembler* masm, Register arg) {
361 if (c_rarg2 != arg ) {
362 masm->mov(c_rarg2, arg);
363 }
364 }
365
366 static void pass_arg3(MacroAssembler* masm, Register arg) {
367 if (c_rarg3 != arg ) {
368 masm->mov(c_rarg3, arg);
369 }
370 }
371
372 void MacroAssembler::stop(const char* msg) {
373 if (ShowMessageBoxOnError) {
374 address rip = pc();
375 pusha(); // get regs on stack
376 lea(c_rarg1, InternalAddress(rip));
377 movq(c_rarg2, rsp); // pass pointer to regs array
378 }
379 // Skip AOT caching C strings in scratch buffer.
380 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
381 lea(c_rarg0, ExternalAddress((address) str));
382 andq(rsp, -16); // align stack as required by ABI
383 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
384 hlt();
385 }
386
387 void MacroAssembler::warn(const char* msg) {
388 push(rbp);
389 movq(rbp, rsp);
390 andq(rsp, -16); // align stack as required by push_CPU_state and call
391 push_CPU_state(); // keeps alignment at 16 bytes
392
393 #ifdef _WIN64
394 // Windows always allocates space for its register args
395 subq(rsp, frame::arg_reg_save_area_bytes);
396 #endif
397 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
398 lea(c_rarg0, ExternalAddress((address) str));
399 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
400
401 #ifdef _WIN64
402 // restore stack pointer
403 addq(rsp, frame::arg_reg_save_area_bytes);
404 #endif
405 pop_CPU_state();
406 mov(rsp, rbp);
407 pop(rbp);
408 }
409
410 void MacroAssembler::print_state() {
411 address rip = pc();
412 pusha(); // get regs on stack
413 push(rbp);
414 movq(rbp, rsp);
415 andq(rsp, -16); // align stack as required by push_CPU_state and call
416 push_CPU_state(); // keeps alignment at 16 bytes
417
418 lea(c_rarg0, InternalAddress(rip));
419 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
420 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
421
422 pop_CPU_state();
423 mov(rsp, rbp);
424 pop(rbp);
425 popa();
426 }
427
428 #ifndef PRODUCT
429 extern "C" void findpc(intptr_t x);
430 #endif
431
432 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
433 // In order to get locks to work, we need to fake a in_VM state
434 if (ShowMessageBoxOnError) {
435 JavaThread* thread = JavaThread::current();
436 JavaThreadState saved_state = thread->thread_state();
437 thread->set_thread_state(_thread_in_vm);
438 #ifndef PRODUCT
439 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
440 ttyLocker ttyl;
441 BytecodeCounter::print();
442 }
443 #endif
444 // To see where a verify_oop failed, get $ebx+40/X for this frame.
445 // XXX correct this offset for amd64
446 // This is the value of eip which points to where verify_oop will return.
447 if (os::message_box(msg, "Execution stopped, print registers?")) {
448 print_state64(pc, regs);
449 BREAKPOINT;
450 }
451 }
452 fatal("DEBUG MESSAGE: %s", msg);
453 }
454
455 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
456 ttyLocker ttyl;
457 DebuggingContext debugging{};
458 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
459 #ifndef PRODUCT
460 tty->cr();
461 findpc(pc);
462 tty->cr();
463 #endif
464 #define PRINT_REG(rax, value) \
465 { tty->print("%s = ", #rax); os::print_location(tty, value); }
466 PRINT_REG(rax, regs[15]);
467 PRINT_REG(rbx, regs[12]);
468 PRINT_REG(rcx, regs[14]);
469 PRINT_REG(rdx, regs[13]);
470 PRINT_REG(rdi, regs[8]);
471 PRINT_REG(rsi, regs[9]);
472 PRINT_REG(rbp, regs[10]);
473 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
474 PRINT_REG(rsp, (intptr_t)(®s[16]));
475 PRINT_REG(r8 , regs[7]);
476 PRINT_REG(r9 , regs[6]);
477 PRINT_REG(r10, regs[5]);
478 PRINT_REG(r11, regs[4]);
479 PRINT_REG(r12, regs[3]);
480 PRINT_REG(r13, regs[2]);
481 PRINT_REG(r14, regs[1]);
482 PRINT_REG(r15, regs[0]);
483 #undef PRINT_REG
484 // Print some words near the top of the stack.
485 int64_t* rsp = ®s[16];
486 int64_t* dump_sp = rsp;
487 for (int col1 = 0; col1 < 8; col1++) {
488 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
489 os::print_location(tty, *dump_sp++);
490 }
491 for (int row = 0; row < 25; row++) {
492 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
493 for (int col = 0; col < 4; col++) {
494 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
495 }
496 tty->cr();
497 }
498 // Print some instructions around pc:
499 Disassembler::decode((address)pc-64, (address)pc);
500 tty->print_cr("--------");
501 Disassembler::decode((address)pc, (address)pc+32);
502 }
503
504 // The java_calling_convention describes stack locations as ideal slots on
505 // a frame with no abi restrictions. Since we must observe abi restrictions
506 // (like the placement of the register window) the slots must be biased by
507 // the following value.
508 static int reg2offset_in(VMReg r) {
509 // Account for saved rbp and return address
510 // This should really be in_preserve_stack_slots
511 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
512 }
513
514 static int reg2offset_out(VMReg r) {
515 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
516 }
517
518 // A long move
519 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
520
521 // The calling conventions assures us that each VMregpair is either
522 // all really one physical register or adjacent stack slots.
523
524 if (src.is_single_phys_reg() ) {
525 if (dst.is_single_phys_reg()) {
526 if (dst.first() != src.first()) {
527 mov(dst.first()->as_Register(), src.first()->as_Register());
528 }
529 } else {
530 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
531 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
532 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
533 }
534 } else if (dst.is_single_phys_reg()) {
535 assert(src.is_single_reg(), "not a stack pair");
536 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
537 } else {
538 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
539 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
540 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
541 }
542 }
543
544 // A double move
545 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
546
547 // The calling conventions assures us that each VMregpair is either
548 // all really one physical register or adjacent stack slots.
549
550 if (src.is_single_phys_reg() ) {
551 if (dst.is_single_phys_reg()) {
552 // In theory these overlap but the ordering is such that this is likely a nop
553 if ( src.first() != dst.first()) {
554 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
555 }
556 } else {
557 assert(dst.is_single_reg(), "not a stack pair");
558 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
559 }
560 } else if (dst.is_single_phys_reg()) {
561 assert(src.is_single_reg(), "not a stack pair");
562 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
563 } else {
564 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
565 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
566 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
567 }
568 }
569
570
571 // A float arg may have to do float reg int reg conversion
572 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
573 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
574
575 // The calling conventions assures us that each VMregpair is either
576 // all really one physical register or adjacent stack slots.
577
578 if (src.first()->is_stack()) {
579 if (dst.first()->is_stack()) {
580 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
581 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
582 } else {
583 // stack to reg
584 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
585 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
586 }
587 } else if (dst.first()->is_stack()) {
588 // reg to stack
589 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
590 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
591 } else {
592 // reg to reg
593 // In theory these overlap but the ordering is such that this is likely a nop
594 if ( src.first() != dst.first()) {
595 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
596 }
597 }
598 }
599
600 // On 64 bit we will store integer like items to the stack as
601 // 64 bits items (x86_32/64 abi) even though java would only store
602 // 32bits for a parameter. On 32bit it will simply be 32 bits
603 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
604 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
605 if (src.first()->is_stack()) {
606 if (dst.first()->is_stack()) {
607 // stack to stack
608 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
609 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
610 } else {
611 // stack to reg
612 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
613 }
614 } else if (dst.first()->is_stack()) {
615 // reg to stack
616 // Do we really have to sign extend???
617 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
618 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
619 } else {
620 // Do we really have to sign extend???
621 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
622 if (dst.first() != src.first()) {
623 movq(dst.first()->as_Register(), src.first()->as_Register());
624 }
625 }
626 }
627
628 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
629 if (src.first()->is_stack()) {
630 if (dst.first()->is_stack()) {
631 // stack to stack
632 movq(rax, Address(rbp, reg2offset_in(src.first())));
633 movq(Address(rsp, reg2offset_out(dst.first())), rax);
634 } else {
635 // stack to reg
636 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
637 }
638 } else if (dst.first()->is_stack()) {
639 // reg to stack
640 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
641 } else {
642 if (dst.first() != src.first()) {
643 movq(dst.first()->as_Register(), src.first()->as_Register());
644 }
645 }
646 }
647
648 // An oop arg. Must pass a handle not the oop itself
649 void MacroAssembler::object_move(OopMap* map,
650 int oop_handle_offset,
651 int framesize_in_slots,
652 VMRegPair src,
653 VMRegPair dst,
654 bool is_receiver,
655 int* receiver_offset) {
656
657 // must pass a handle. First figure out the location we use as a handle
658
659 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
660
661 // See if oop is null if it is we need no handle
662
663 if (src.first()->is_stack()) {
664
665 // Oop is already on the stack as an argument
666 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
667 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
668 if (is_receiver) {
669 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
670 }
671
672 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
673 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
674 // conditionally move a null
675 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
676 } else {
677
678 // Oop is in a register we must store it to the space we reserve
679 // on the stack for oop_handles and pass a handle if oop is non-null
680
681 const Register rOop = src.first()->as_Register();
682 int oop_slot;
683 if (rOop == j_rarg0)
684 oop_slot = 0;
685 else if (rOop == j_rarg1)
686 oop_slot = 1;
687 else if (rOop == j_rarg2)
688 oop_slot = 2;
689 else if (rOop == j_rarg3)
690 oop_slot = 3;
691 else if (rOop == j_rarg4)
692 oop_slot = 4;
693 else {
694 assert(rOop == j_rarg5, "wrong register");
695 oop_slot = 5;
696 }
697
698 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
699 int offset = oop_slot*VMRegImpl::stack_slot_size;
700
701 map->set_oop(VMRegImpl::stack2reg(oop_slot));
702 // Store oop in handle area, may be null
703 movptr(Address(rsp, offset), rOop);
704 if (is_receiver) {
705 *receiver_offset = offset;
706 }
707
708 cmpptr(rOop, NULL_WORD);
709 lea(rHandle, Address(rsp, offset));
710 // conditionally move a null from the handle area where it was just stored
711 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
712 }
713
714 // If arg is on the stack then place it otherwise it is already in correct reg.
715 if (dst.first()->is_stack()) {
716 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
717 }
718 }
719
720 void MacroAssembler::addptr(Register dst, int32_t imm32) {
721 addq(dst, imm32);
722 }
723
724 void MacroAssembler::addptr(Register dst, Register src) {
725 addq(dst, src);
726 }
727
728 void MacroAssembler::addptr(Address dst, Register src) {
729 addq(dst, src);
730 }
731
732 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
733 assert(rscratch != noreg || always_reachable(src), "missing");
734
735 if (reachable(src)) {
736 Assembler::addsd(dst, as_Address(src));
737 } else {
738 lea(rscratch, src);
739 Assembler::addsd(dst, Address(rscratch, 0));
740 }
741 }
742
743 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
744 assert(rscratch != noreg || always_reachable(src), "missing");
745
746 if (reachable(src)) {
747 addss(dst, as_Address(src));
748 } else {
749 lea(rscratch, src);
750 addss(dst, Address(rscratch, 0));
751 }
752 }
753
754 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
755 assert(rscratch != noreg || always_reachable(src), "missing");
756
757 if (reachable(src)) {
758 Assembler::addpd(dst, as_Address(src));
759 } else {
760 lea(rscratch, src);
761 Assembler::addpd(dst, Address(rscratch, 0));
762 }
763 }
764
765 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
766 // Stub code is generated once and never copied.
767 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
768 void MacroAssembler::align64() {
769 align(64, (uint)(uintptr_t)pc());
770 }
771
772 void MacroAssembler::align32() {
773 align(32, (uint)(uintptr_t)pc());
774 }
775
776 void MacroAssembler::align(uint modulus) {
777 // 8273459: Ensure alignment is possible with current segment alignment
778 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
779 align(modulus, offset());
780 }
781
782 void MacroAssembler::align(uint modulus, uint target) {
783 if (target % modulus != 0) {
784 nop(modulus - (target % modulus));
785 }
786 }
787
788 void MacroAssembler::push_f(XMMRegister r) {
789 subptr(rsp, wordSize);
790 movflt(Address(rsp, 0), r);
791 }
792
793 void MacroAssembler::pop_f(XMMRegister r) {
794 movflt(r, Address(rsp, 0));
795 addptr(rsp, wordSize);
796 }
797
798 void MacroAssembler::push_d(XMMRegister r) {
799 subptr(rsp, 2 * wordSize);
800 movdbl(Address(rsp, 0), r);
801 }
802
803 void MacroAssembler::pop_d(XMMRegister r) {
804 movdbl(r, Address(rsp, 0));
805 addptr(rsp, 2 * Interpreter::stackElementSize);
806 }
807
808 void MacroAssembler::push_ppx(Register src) {
809 if (VM_Version::supports_apx_f()) {
810 pushp(src);
811 } else {
812 Assembler::push(src);
813 }
814 }
815
816 void MacroAssembler::pop_ppx(Register dst) {
817 if (VM_Version::supports_apx_f()) {
818 popp(dst);
819 } else {
820 Assembler::pop(dst);
821 }
822 }
823
824 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
825 // Used in sign-masking with aligned address.
826 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
827 assert(rscratch != noreg || always_reachable(src), "missing");
828
829 if (UseAVX > 2 &&
830 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
831 (dst->encoding() >= 16)) {
832 vpand(dst, dst, src, AVX_512bit, rscratch);
833 } else if (reachable(src)) {
834 Assembler::andpd(dst, as_Address(src));
835 } else {
836 lea(rscratch, src);
837 Assembler::andpd(dst, Address(rscratch, 0));
838 }
839 }
840
841 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
842 // Used in sign-masking with aligned address.
843 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
844 assert(rscratch != noreg || always_reachable(src), "missing");
845
846 if (reachable(src)) {
847 Assembler::andps(dst, as_Address(src));
848 } else {
849 lea(rscratch, src);
850 Assembler::andps(dst, Address(rscratch, 0));
851 }
852 }
853
854 void MacroAssembler::andptr(Register dst, int32_t imm32) {
855 andq(dst, imm32);
856 }
857
858 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
859 assert(rscratch != noreg || always_reachable(src), "missing");
860
861 if (reachable(src)) {
862 andq(dst, as_Address(src));
863 } else {
864 lea(rscratch, src);
865 andq(dst, Address(rscratch, 0));
866 }
867 }
868
869 void MacroAssembler::atomic_incl(Address counter_addr) {
870 lock();
871 incrementl(counter_addr);
872 }
873
874 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
875 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
876
877 if (reachable(counter_addr)) {
878 atomic_incl(as_Address(counter_addr));
879 } else {
880 lea(rscratch, counter_addr);
881 atomic_incl(Address(rscratch, 0));
882 }
883 }
884
885 void MacroAssembler::atomic_incq(Address counter_addr) {
886 lock();
887 incrementq(counter_addr);
888 }
889
890 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
891 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
892
893 if (reachable(counter_addr)) {
894 atomic_incq(as_Address(counter_addr));
895 } else {
896 lea(rscratch, counter_addr);
897 atomic_incq(Address(rscratch, 0));
898 }
899 }
900
901 // Writes to stack successive pages until offset reached to check for
902 // stack overflow + shadow pages. This clobbers tmp.
903 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
904 movptr(tmp, rsp);
905 // Bang stack for total size given plus shadow page size.
906 // Bang one page at a time because large size can bang beyond yellow and
907 // red zones.
908 Label loop;
909 bind(loop);
910 movl(Address(tmp, (-(int)os::vm_page_size())), size );
911 subptr(tmp, (int)os::vm_page_size());
912 subl(size, (int)os::vm_page_size());
913 jcc(Assembler::greater, loop);
914
915 // Bang down shadow pages too.
916 // At this point, (tmp-0) is the last address touched, so don't
917 // touch it again. (It was touched as (tmp-pagesize) but then tmp
918 // was post-decremented.) Skip this address by starting at i=1, and
919 // touch a few more pages below. N.B. It is important to touch all
920 // the way down including all pages in the shadow zone.
921 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
922 // this could be any sized move but this is can be a debugging crumb
923 // so the bigger the better.
924 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
925 }
926 }
927
928 void MacroAssembler::reserved_stack_check() {
929 // testing if reserved zone needs to be enabled
930 Label no_reserved_zone_enabling;
931
932 cmpptr(rsp, Address(r15_thread, JavaThread::reserved_stack_activation_offset()));
933 jcc(Assembler::below, no_reserved_zone_enabling);
934
935 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), r15_thread);
936 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
937 should_not_reach_here();
938
939 bind(no_reserved_zone_enabling);
940 }
941
942 void MacroAssembler::c2bool(Register x) {
943 // implements x == 0 ? 0 : 1
944 // note: must only look at least-significant byte of x
945 // since C-style booleans are stored in one byte
946 // only! (was bug)
947 andl(x, 0xFF);
948 setb(Assembler::notZero, x);
949 }
950
951 // Wouldn't need if AddressLiteral version had new name
952 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
953 Assembler::call(L, rtype);
954 }
955
956 void MacroAssembler::call(Register entry) {
957 Assembler::call(entry);
958 }
959
960 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
961 assert(rscratch != noreg || always_reachable(entry), "missing");
962
963 if (reachable(entry)) {
964 Assembler::call_literal(entry.target(), entry.rspec());
965 } else {
966 lea(rscratch, entry);
967 Assembler::call(rscratch);
968 }
969 }
970
971 void MacroAssembler::ic_call(address entry, jint method_index) {
972 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
973 // Needs full 64-bit immediate for later patching.
974 Assembler::mov64(rax, (int64_t)Universe::non_oop_word());
975 call(AddressLiteral(entry, rh));
976 }
977
978 int MacroAssembler::ic_check_size() {
979 return UseCompactObjectHeaders ? 17 : 14;
980 }
981
982 int MacroAssembler::ic_check(int end_alignment) {
983 Register receiver = j_rarg0;
984 Register data = rax;
985 Register temp = rscratch1;
986
987 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
988 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
989 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
990 // before the inline cache check here, and not after
991 align(end_alignment, offset() + ic_check_size());
992
993 int uep_offset = offset();
994
995 if (UseCompactObjectHeaders) {
996 load_narrow_klass_compact(temp, receiver);
997 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
998 } else {
999 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1000 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1001 }
1002
1003 // if inline cache check fails, then jump to runtime routine
1004 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1005 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1006
1007 return uep_offset;
1008 }
1009
1010 void MacroAssembler::emit_static_call_stub() {
1011 // Static stub relocation also tags the Method* in the code-stream.
1012 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1013 // This is recognized as unresolved by relocs/nativeinst/ic code.
1014 jump(RuntimeAddress(pc()));
1015 }
1016
1017 // Implementation of call_VM versions
1018
1019 void MacroAssembler::call_VM(Register oop_result,
1020 address entry_point,
1021 bool check_exceptions) {
1022 Label C, E;
1023 call(C, relocInfo::none);
1024 jmp(E);
1025
1026 bind(C);
1027 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1028 ret(0);
1029
1030 bind(E);
1031 }
1032
1033 void MacroAssembler::call_VM(Register oop_result,
1034 address entry_point,
1035 Register arg_1,
1036 bool check_exceptions) {
1037 Label C, E;
1038 call(C, relocInfo::none);
1039 jmp(E);
1040
1041 bind(C);
1042 pass_arg1(this, arg_1);
1043 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1044 ret(0);
1045
1046 bind(E);
1047 }
1048
1049 void MacroAssembler::call_VM(Register oop_result,
1050 address entry_point,
1051 Register arg_1,
1052 Register arg_2,
1053 bool check_exceptions) {
1054 Label C, E;
1055 call(C, relocInfo::none);
1056 jmp(E);
1057
1058 bind(C);
1059
1060 assert_different_registers(arg_1, c_rarg2);
1061
1062 pass_arg2(this, arg_2);
1063 pass_arg1(this, arg_1);
1064 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1065 ret(0);
1066
1067 bind(E);
1068 }
1069
1070 void MacroAssembler::call_VM(Register oop_result,
1071 address entry_point,
1072 Register arg_1,
1073 Register arg_2,
1074 Register arg_3,
1075 bool check_exceptions) {
1076 Label C, E;
1077 call(C, relocInfo::none);
1078 jmp(E);
1079
1080 bind(C);
1081
1082 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1083 assert_different_registers(arg_2, c_rarg3);
1084 pass_arg3(this, arg_3);
1085 pass_arg2(this, arg_2);
1086 pass_arg1(this, arg_1);
1087 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1088 ret(0);
1089
1090 bind(E);
1091 }
1092
1093 void MacroAssembler::call_VM(Register oop_result,
1094 Register last_java_sp,
1095 address entry_point,
1096 int number_of_arguments,
1097 bool check_exceptions) {
1098 call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1099 }
1100
1101 void MacroAssembler::call_VM(Register oop_result,
1102 Register last_java_sp,
1103 address entry_point,
1104 Register arg_1,
1105 bool check_exceptions) {
1106 pass_arg1(this, arg_1);
1107 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1108 }
1109
1110 void MacroAssembler::call_VM(Register oop_result,
1111 Register last_java_sp,
1112 address entry_point,
1113 Register arg_1,
1114 Register arg_2,
1115 bool check_exceptions) {
1116
1117 assert_different_registers(arg_1, c_rarg2);
1118 pass_arg2(this, arg_2);
1119 pass_arg1(this, arg_1);
1120 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1121 }
1122
1123 void MacroAssembler::call_VM(Register oop_result,
1124 Register last_java_sp,
1125 address entry_point,
1126 Register arg_1,
1127 Register arg_2,
1128 Register arg_3,
1129 bool check_exceptions) {
1130 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1131 assert_different_registers(arg_2, c_rarg3);
1132 pass_arg3(this, arg_3);
1133 pass_arg2(this, arg_2);
1134 pass_arg1(this, arg_1);
1135 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1136 }
1137
1138 void MacroAssembler::super_call_VM(Register oop_result,
1139 Register last_java_sp,
1140 address entry_point,
1141 int number_of_arguments,
1142 bool check_exceptions) {
1143 MacroAssembler::call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1144 }
1145
1146 void MacroAssembler::super_call_VM(Register oop_result,
1147 Register last_java_sp,
1148 address entry_point,
1149 Register arg_1,
1150 bool check_exceptions) {
1151 pass_arg1(this, arg_1);
1152 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1153 }
1154
1155 void MacroAssembler::super_call_VM(Register oop_result,
1156 Register last_java_sp,
1157 address entry_point,
1158 Register arg_1,
1159 Register arg_2,
1160 bool check_exceptions) {
1161
1162 assert_different_registers(arg_1, c_rarg2);
1163 pass_arg2(this, arg_2);
1164 pass_arg1(this, arg_1);
1165 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1166 }
1167
1168 void MacroAssembler::super_call_VM(Register oop_result,
1169 Register last_java_sp,
1170 address entry_point,
1171 Register arg_1,
1172 Register arg_2,
1173 Register arg_3,
1174 bool check_exceptions) {
1175 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1176 assert_different_registers(arg_2, c_rarg3);
1177 pass_arg3(this, arg_3);
1178 pass_arg2(this, arg_2);
1179 pass_arg1(this, arg_1);
1180 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1181 }
1182
1183 void MacroAssembler::call_VM_base(Register oop_result,
1184 Register last_java_sp,
1185 address entry_point,
1186 int number_of_arguments,
1187 bool check_exceptions) {
1188 Register java_thread = r15_thread;
1189
1190 // determine last_java_sp register
1191 if (!last_java_sp->is_valid()) {
1192 last_java_sp = rsp;
1193 }
1194 // debugging support
1195 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1196 #ifdef ASSERT
1197 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1198 // r12 is the heapbase.
1199 if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
1200 #endif // ASSERT
1201
1202 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1203 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1204
1205 // push java thread (becomes first argument of C function)
1206
1207 mov(c_rarg0, r15_thread);
1208
1209 // set last Java frame before call
1210 assert(last_java_sp != rbp, "can't use ebp/rbp");
1211
1212 // Only interpreter should have to set fp
1213 set_last_Java_frame(last_java_sp, rbp, nullptr, rscratch1);
1214
1215 // do the call, remove parameters
1216 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1217
1218 #ifdef ASSERT
1219 // Check that thread register is not clobbered.
1220 guarantee(java_thread != rax, "change this code");
1221 push(rax);
1222 { Label L;
1223 get_thread_slow(rax);
1224 cmpptr(java_thread, rax);
1225 jcc(Assembler::equal, L);
1226 STOP("MacroAssembler::call_VM_base: java_thread not callee saved?");
1227 bind(L);
1228 }
1229 pop(rax);
1230 #endif
1231
1232 // reset last Java frame
1233 // Only interpreter should have to clear fp
1234 reset_last_Java_frame(true);
1235
1236 // C++ interp handles this in the interpreter
1237 check_and_handle_popframe();
1238 check_and_handle_earlyret();
1239
1240 if (check_exceptions) {
1241 // check for pending exceptions (java_thread is set upon return)
1242 cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
1243 // This used to conditionally jump to forward_exception however it is
1244 // possible if we relocate that the branch will not reach. So we must jump
1245 // around so we can always reach
1246
1247 Label ok;
1248 jcc(Assembler::equal, ok);
1249 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1250 bind(ok);
1251 }
1252
1253 // get oop result if there is one and reset the value in the thread
1254 if (oop_result->is_valid()) {
1255 get_vm_result_oop(oop_result);
1256 }
1257 }
1258
1259 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1260 // Calculate the value for last_Java_sp somewhat subtle.
1261 // call_VM does an intermediate call which places a return address on
1262 // the stack just under the stack pointer as the user finished with it.
1263 // This allows use to retrieve last_Java_pc from last_Java_sp[-1].
1264
1265 // We've pushed one address, correct last_Java_sp
1266 lea(rax, Address(rsp, wordSize));
1267
1268 call_VM_base(oop_result, rax, entry_point, number_of_arguments, check_exceptions);
1269 }
1270
1271 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1272 void MacroAssembler::call_VM_leaf0(address entry_point) {
1273 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1274 }
1275
1276 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1277 call_VM_leaf_base(entry_point, number_of_arguments);
1278 }
1279
1280 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1281 pass_arg0(this, arg_0);
1282 call_VM_leaf(entry_point, 1);
1283 }
1284
1285 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1286
1287 assert_different_registers(arg_0, c_rarg1);
1288 pass_arg1(this, arg_1);
1289 pass_arg0(this, arg_0);
1290 call_VM_leaf(entry_point, 2);
1291 }
1292
1293 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1294 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1295 assert_different_registers(arg_1, c_rarg2);
1296 pass_arg2(this, arg_2);
1297 pass_arg1(this, arg_1);
1298 pass_arg0(this, arg_0);
1299 call_VM_leaf(entry_point, 3);
1300 }
1301
1302 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1303 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1304 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1305 assert_different_registers(arg_2, c_rarg3);
1306 pass_arg3(this, arg_3);
1307 pass_arg2(this, arg_2);
1308 pass_arg1(this, arg_1);
1309 pass_arg0(this, arg_0);
1310 call_VM_leaf(entry_point, 3);
1311 }
1312
1313 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1314 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1315 }
1316
1317 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1318 pass_arg0(this, arg_0);
1319 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1320 }
1321
1322 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1323 assert_different_registers(arg_0, c_rarg1);
1324 pass_arg1(this, arg_1);
1325 pass_arg0(this, arg_0);
1326 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1327 }
1328
1329 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1330 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1331 assert_different_registers(arg_1, c_rarg2);
1332 pass_arg2(this, arg_2);
1333 pass_arg1(this, arg_1);
1334 pass_arg0(this, arg_0);
1335 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1336 }
1337
1338 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1339 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1340 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1341 assert_different_registers(arg_2, c_rarg3);
1342 pass_arg3(this, arg_3);
1343 pass_arg2(this, arg_2);
1344 pass_arg1(this, arg_1);
1345 pass_arg0(this, arg_0);
1346 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1347 }
1348
1349 void MacroAssembler::get_vm_result_oop(Register oop_result) {
1350 movptr(oop_result, Address(r15_thread, JavaThread::vm_result_oop_offset()));
1351 movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
1352 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1353 }
1354
1355 void MacroAssembler::get_vm_result_metadata(Register metadata_result) {
1356 movptr(metadata_result, Address(r15_thread, JavaThread::vm_result_metadata_offset()));
1357 movptr(Address(r15_thread, JavaThread::vm_result_metadata_offset()), NULL_WORD);
1358 }
1359
1360 void MacroAssembler::check_and_handle_earlyret() {
1361 }
1362
1363 void MacroAssembler::check_and_handle_popframe() {
1364 }
1365
1366 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1367 assert(rscratch != noreg || always_reachable(src1), "missing");
1368
1369 if (reachable(src1)) {
1370 cmpl(as_Address(src1), imm);
1371 } else {
1372 lea(rscratch, src1);
1373 cmpl(Address(rscratch, 0), imm);
1374 }
1375 }
1376
1377 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1378 assert(!src2.is_lval(), "use cmpptr");
1379 assert(rscratch != noreg || always_reachable(src2), "missing");
1380
1381 if (reachable(src2)) {
1382 cmpl(src1, as_Address(src2));
1383 } else {
1384 lea(rscratch, src2);
1385 cmpl(src1, Address(rscratch, 0));
1386 }
1387 }
1388
1389 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1390 Assembler::cmpl(src1, imm);
1391 }
1392
1393 void MacroAssembler::cmp32(Register src1, Address src2) {
1394 Assembler::cmpl(src1, src2);
1395 }
1396
1397 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1398 ucomisd(opr1, opr2);
1399
1400 Label L;
1401 if (unordered_is_less) {
1402 movl(dst, -1);
1403 jcc(Assembler::parity, L);
1404 jcc(Assembler::below , L);
1405 movl(dst, 0);
1406 jcc(Assembler::equal , L);
1407 increment(dst);
1408 } else { // unordered is greater
1409 movl(dst, 1);
1410 jcc(Assembler::parity, L);
1411 jcc(Assembler::above , L);
1412 movl(dst, 0);
1413 jcc(Assembler::equal , L);
1414 decrementl(dst);
1415 }
1416 bind(L);
1417 }
1418
1419 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1420 ucomiss(opr1, opr2);
1421
1422 Label L;
1423 if (unordered_is_less) {
1424 movl(dst, -1);
1425 jcc(Assembler::parity, L);
1426 jcc(Assembler::below , L);
1427 movl(dst, 0);
1428 jcc(Assembler::equal , L);
1429 increment(dst);
1430 } else { // unordered is greater
1431 movl(dst, 1);
1432 jcc(Assembler::parity, L);
1433 jcc(Assembler::above , L);
1434 movl(dst, 0);
1435 jcc(Assembler::equal , L);
1436 decrementl(dst);
1437 }
1438 bind(L);
1439 }
1440
1441
1442 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1443 assert(rscratch != noreg || always_reachable(src1), "missing");
1444
1445 if (reachable(src1)) {
1446 cmpb(as_Address(src1), imm);
1447 } else {
1448 lea(rscratch, src1);
1449 cmpb(Address(rscratch, 0), imm);
1450 }
1451 }
1452
1453 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1454 assert(rscratch != noreg || always_reachable(src2), "missing");
1455
1456 if (src2.is_lval()) {
1457 movptr(rscratch, src2);
1458 Assembler::cmpq(src1, rscratch);
1459 } else if (reachable(src2)) {
1460 cmpq(src1, as_Address(src2));
1461 } else {
1462 lea(rscratch, src2);
1463 Assembler::cmpq(src1, Address(rscratch, 0));
1464 }
1465 }
1466
1467 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1468 assert(src2.is_lval(), "not a mem-mem compare");
1469 // moves src2's literal address
1470 movptr(rscratch, src2);
1471 Assembler::cmpq(src1, rscratch);
1472 }
1473
1474 void MacroAssembler::cmpoop(Register src1, Register src2) {
1475 cmpptr(src1, src2);
1476 }
1477
1478 void MacroAssembler::cmpoop(Register src1, Address src2) {
1479 cmpptr(src1, src2);
1480 }
1481
1482 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1483 movoop(rscratch, src2);
1484 cmpptr(src1, rscratch);
1485 }
1486
1487 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1488 assert(rscratch != noreg || always_reachable(adr), "missing");
1489
1490 if (reachable(adr)) {
1491 lock();
1492 cmpxchgptr(reg, as_Address(adr));
1493 } else {
1494 lea(rscratch, adr);
1495 lock();
1496 cmpxchgptr(reg, Address(rscratch, 0));
1497 }
1498 }
1499
1500 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1501 cmpxchgq(reg, adr);
1502 }
1503
1504 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1505 assert(rscratch != noreg || always_reachable(src), "missing");
1506
1507 if (reachable(src)) {
1508 Assembler::comisd(dst, as_Address(src));
1509 } else {
1510 lea(rscratch, src);
1511 Assembler::comisd(dst, Address(rscratch, 0));
1512 }
1513 }
1514
1515 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1516 assert(rscratch != noreg || always_reachable(src), "missing");
1517
1518 if (reachable(src)) {
1519 Assembler::comiss(dst, as_Address(src));
1520 } else {
1521 lea(rscratch, src);
1522 Assembler::comiss(dst, Address(rscratch, 0));
1523 }
1524 }
1525
1526
1527 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1528 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1529
1530 Condition negated_cond = negate_condition(cond);
1531 Label L;
1532 jcc(negated_cond, L);
1533 pushf(); // Preserve flags
1534 atomic_incl(counter_addr, rscratch);
1535 popf();
1536 bind(L);
1537 }
1538
1539 int MacroAssembler::corrected_idivl(Register reg) {
1540 // Full implementation of Java idiv and irem; checks for
1541 // special case as described in JVM spec., p.243 & p.271.
1542 // The function returns the (pc) offset of the idivl
1543 // instruction - may be needed for implicit exceptions.
1544 //
1545 // normal case special case
1546 //
1547 // input : rax,: dividend min_int
1548 // reg: divisor (may not be rax,/rdx) -1
1549 //
1550 // output: rax,: quotient (= rax, idiv reg) min_int
1551 // rdx: remainder (= rax, irem reg) 0
1552 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1553 const int min_int = 0x80000000;
1554 Label normal_case, special_case;
1555
1556 // check for special case
1557 cmpl(rax, min_int);
1558 jcc(Assembler::notEqual, normal_case);
1559 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1560 cmpl(reg, -1);
1561 jcc(Assembler::equal, special_case);
1562
1563 // handle normal case
1564 bind(normal_case);
1565 cdql();
1566 int idivl_offset = offset();
1567 idivl(reg);
1568
1569 // normal and special case exit
1570 bind(special_case);
1571
1572 return idivl_offset;
1573 }
1574
1575
1576
1577 void MacroAssembler::decrementl(Register reg, int value) {
1578 if (value == min_jint) {subl(reg, value) ; return; }
1579 if (value < 0) { incrementl(reg, -value); return; }
1580 if (value == 0) { ; return; }
1581 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1582 /* else */ { subl(reg, value) ; return; }
1583 }
1584
1585 void MacroAssembler::decrementl(Address dst, int value) {
1586 if (value == min_jint) {subl(dst, value) ; return; }
1587 if (value < 0) { incrementl(dst, -value); return; }
1588 if (value == 0) { ; return; }
1589 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1590 /* else */ { subl(dst, value) ; return; }
1591 }
1592
1593 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1594 assert(shift_value > 0, "illegal shift value");
1595 Label _is_positive;
1596 testl (reg, reg);
1597 jcc (Assembler::positive, _is_positive);
1598 int offset = (1 << shift_value) - 1 ;
1599
1600 if (offset == 1) {
1601 incrementl(reg);
1602 } else {
1603 addl(reg, offset);
1604 }
1605
1606 bind (_is_positive);
1607 sarl(reg, shift_value);
1608 }
1609
1610 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1611 assert(rscratch != noreg || always_reachable(src), "missing");
1612
1613 if (reachable(src)) {
1614 Assembler::divsd(dst, as_Address(src));
1615 } else {
1616 lea(rscratch, src);
1617 Assembler::divsd(dst, Address(rscratch, 0));
1618 }
1619 }
1620
1621 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1622 assert(rscratch != noreg || always_reachable(src), "missing");
1623
1624 if (reachable(src)) {
1625 Assembler::divss(dst, as_Address(src));
1626 } else {
1627 lea(rscratch, src);
1628 Assembler::divss(dst, Address(rscratch, 0));
1629 }
1630 }
1631
1632 void MacroAssembler::enter() {
1633 push(rbp);
1634 mov(rbp, rsp);
1635 }
1636
1637 void MacroAssembler::post_call_nop() {
1638 if (!Continuations::enabled()) {
1639 return;
1640 }
1641 InstructionMark im(this);
1642 relocate(post_call_nop_Relocation::spec());
1643 InlineSkippedInstructionsCounter skipCounter(this);
1644 emit_int8((uint8_t)0x0f);
1645 emit_int8((uint8_t)0x1f);
1646 emit_int8((uint8_t)0x84);
1647 emit_int8((uint8_t)0x00);
1648 emit_int32(0x00);
1649 }
1650
1651 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1652 assert(rscratch != noreg || always_reachable(src), "missing");
1653 if (reachable(src)) {
1654 Assembler::mulpd(dst, as_Address(src));
1655 } else {
1656 lea(rscratch, src);
1657 Assembler::mulpd(dst, Address(rscratch, 0));
1658 }
1659 }
1660
1661 // dst = c = a * b + c
1662 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1663 Assembler::vfmadd231sd(c, a, b);
1664 if (dst != c) {
1665 movdbl(dst, c);
1666 }
1667 }
1668
1669 // dst = c = a * b + c
1670 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1671 Assembler::vfmadd231ss(c, a, b);
1672 if (dst != c) {
1673 movflt(dst, c);
1674 }
1675 }
1676
1677 // dst = c = a * b + c
1678 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1679 Assembler::vfmadd231pd(c, a, b, vector_len);
1680 if (dst != c) {
1681 vmovdqu(dst, c);
1682 }
1683 }
1684
1685 // dst = c = a * b + c
1686 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1687 Assembler::vfmadd231ps(c, a, b, vector_len);
1688 if (dst != c) {
1689 vmovdqu(dst, c);
1690 }
1691 }
1692
1693 // dst = c = a * b + c
1694 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1695 Assembler::vfmadd231pd(c, a, b, vector_len);
1696 if (dst != c) {
1697 vmovdqu(dst, c);
1698 }
1699 }
1700
1701 // dst = c = a * b + c
1702 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1703 Assembler::vfmadd231ps(c, a, b, vector_len);
1704 if (dst != c) {
1705 vmovdqu(dst, c);
1706 }
1707 }
1708
1709 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
1710 assert(rscratch != noreg || always_reachable(dst), "missing");
1711
1712 if (reachable(dst)) {
1713 incrementl(as_Address(dst));
1714 } else {
1715 lea(rscratch, dst);
1716 incrementl(Address(rscratch, 0));
1717 }
1718 }
1719
1720 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
1721 incrementl(as_Address(dst, rscratch));
1722 }
1723
1724 void MacroAssembler::incrementl(Register reg, int value) {
1725 if (value == min_jint) {addl(reg, value) ; return; }
1726 if (value < 0) { decrementl(reg, -value); return; }
1727 if (value == 0) { ; return; }
1728 if (value == 1 && UseIncDec) { incl(reg) ; return; }
1729 /* else */ { addl(reg, value) ; return; }
1730 }
1731
1732 void MacroAssembler::incrementl(Address dst, int value) {
1733 if (value == min_jint) {addl(dst, value) ; return; }
1734 if (value < 0) { decrementl(dst, -value); return; }
1735 if (value == 0) { ; return; }
1736 if (value == 1 && UseIncDec) { incl(dst) ; return; }
1737 /* else */ { addl(dst, value) ; return; }
1738 }
1739
1740 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
1741 assert(rscratch != noreg || always_reachable(dst), "missing");
1742 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
1743 if (reachable(dst)) {
1744 jmp_literal(dst.target(), dst.rspec());
1745 } else {
1746 lea(rscratch, dst);
1747 jmp(rscratch);
1748 }
1749 }
1750
1751 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
1752 assert(rscratch != noreg || always_reachable(dst), "missing");
1753 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
1754 if (reachable(dst)) {
1755 InstructionMark im(this);
1756 relocate(dst.reloc());
1757 const int short_size = 2;
1758 const int long_size = 6;
1759 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
1760 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
1761 // 0111 tttn #8-bit disp
1762 emit_int8(0x70 | cc);
1763 emit_int8((offs - short_size) & 0xFF);
1764 } else {
1765 // 0000 1111 1000 tttn #32-bit disp
1766 emit_int8(0x0F);
1767 emit_int8((unsigned char)(0x80 | cc));
1768 emit_int32(offs - long_size);
1769 }
1770 } else {
1771 #ifdef ASSERT
1772 warning("reversing conditional branch");
1773 #endif /* ASSERT */
1774 Label skip;
1775 jccb(reverse[cc], skip);
1776 lea(rscratch, dst);
1777 Assembler::jmp(rscratch);
1778 bind(skip);
1779 }
1780 }
1781
1782 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
1783 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
1784 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
1785
1786 stmxcsr(mxcsr_save);
1787 movl(tmp, mxcsr_save);
1788 if (EnableX86ECoreOpts) {
1789 // The mxcsr_std has status bits set for performance on ECore
1790 orl(tmp, 0x003f);
1791 } else {
1792 // Mask out status bits (only check control and mask bits)
1793 andl(tmp, 0xFFC0);
1794 }
1795 cmp32(tmp, mxcsr_std, rscratch);
1796 }
1797
1798 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
1799 assert(rscratch != noreg || always_reachable(src), "missing");
1800
1801 if (reachable(src)) {
1802 Assembler::ldmxcsr(as_Address(src));
1803 } else {
1804 lea(rscratch, src);
1805 Assembler::ldmxcsr(Address(rscratch, 0));
1806 }
1807 }
1808
1809 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1810 int off = offset();
1811 movsbl(dst, src); // movsxb
1812 return off;
1813 }
1814
1815 // Note: load_signed_short used to be called load_signed_word.
1816 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
1817 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
1818 // The term "word" in HotSpot means a 32- or 64-bit machine word.
1819 int MacroAssembler::load_signed_short(Register dst, Address src) {
1820 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
1821 // version but this is what 64bit has always done. This seems to imply
1822 // that users are only using 32bits worth.
1823 int off = offset();
1824 movswl(dst, src); // movsxw
1825 return off;
1826 }
1827
1828 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1829 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1830 // and "3.9 Partial Register Penalties", p. 22).
1831 int off = offset();
1832 movzbl(dst, src); // movzxb
1833 return off;
1834 }
1835
1836 // Note: load_unsigned_short used to be called load_unsigned_word.
1837 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1838 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1839 // and "3.9 Partial Register Penalties", p. 22).
1840 int off = offset();
1841 movzwl(dst, src); // movzxw
1842 return off;
1843 }
1844
1845 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1846 switch (size_in_bytes) {
1847 case 8: movq(dst, src); break;
1848 case 4: movl(dst, src); break;
1849 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1850 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1851 default: ShouldNotReachHere();
1852 }
1853 }
1854
1855 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1856 switch (size_in_bytes) {
1857 case 8: movq(dst, src); break;
1858 case 4: movl(dst, src); break;
1859 case 2: movw(dst, src); break;
1860 case 1: movb(dst, src); break;
1861 default: ShouldNotReachHere();
1862 }
1863 }
1864
1865 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
1866 assert(rscratch != noreg || always_reachable(dst), "missing");
1867
1868 if (reachable(dst)) {
1869 movl(as_Address(dst), src);
1870 } else {
1871 lea(rscratch, dst);
1872 movl(Address(rscratch, 0), src);
1873 }
1874 }
1875
1876 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
1877 if (reachable(src)) {
1878 movl(dst, as_Address(src));
1879 } else {
1880 lea(dst, src);
1881 movl(dst, Address(dst, 0));
1882 }
1883 }
1884
1885 // C++ bool manipulation
1886
1887 void MacroAssembler::movbool(Register dst, Address src) {
1888 if(sizeof(bool) == 1)
1889 movb(dst, src);
1890 else if(sizeof(bool) == 2)
1891 movw(dst, src);
1892 else if(sizeof(bool) == 4)
1893 movl(dst, src);
1894 else
1895 // unsupported
1896 ShouldNotReachHere();
1897 }
1898
1899 void MacroAssembler::movbool(Address dst, bool boolconst) {
1900 if(sizeof(bool) == 1)
1901 movb(dst, (int) boolconst);
1902 else if(sizeof(bool) == 2)
1903 movw(dst, (int) boolconst);
1904 else if(sizeof(bool) == 4)
1905 movl(dst, (int) boolconst);
1906 else
1907 // unsupported
1908 ShouldNotReachHere();
1909 }
1910
1911 void MacroAssembler::movbool(Address dst, Register src) {
1912 if(sizeof(bool) == 1)
1913 movb(dst, src);
1914 else if(sizeof(bool) == 2)
1915 movw(dst, src);
1916 else if(sizeof(bool) == 4)
1917 movl(dst, src);
1918 else
1919 // unsupported
1920 ShouldNotReachHere();
1921 }
1922
1923 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1924 assert(rscratch != noreg || always_reachable(src), "missing");
1925
1926 if (reachable(src)) {
1927 movdl(dst, as_Address(src));
1928 } else {
1929 lea(rscratch, src);
1930 movdl(dst, Address(rscratch, 0));
1931 }
1932 }
1933
1934 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
1935 assert(rscratch != noreg || always_reachable(src), "missing");
1936
1937 if (reachable(src)) {
1938 movq(dst, as_Address(src));
1939 } else {
1940 lea(rscratch, src);
1941 movq(dst, Address(rscratch, 0));
1942 }
1943 }
1944
1945 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1946 assert(rscratch != noreg || always_reachable(src), "missing");
1947
1948 if (reachable(src)) {
1949 if (UseXmmLoadAndClearUpper) {
1950 movsd (dst, as_Address(src));
1951 } else {
1952 movlpd(dst, as_Address(src));
1953 }
1954 } else {
1955 lea(rscratch, src);
1956 if (UseXmmLoadAndClearUpper) {
1957 movsd (dst, Address(rscratch, 0));
1958 } else {
1959 movlpd(dst, Address(rscratch, 0));
1960 }
1961 }
1962 }
1963
1964 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
1965 assert(rscratch != noreg || always_reachable(src), "missing");
1966
1967 if (reachable(src)) {
1968 movss(dst, as_Address(src));
1969 } else {
1970 lea(rscratch, src);
1971 movss(dst, Address(rscratch, 0));
1972 }
1973 }
1974
1975 void MacroAssembler::movhlf(XMMRegister dst, XMMRegister src, Register rscratch) {
1976 if (VM_Version::supports_avx10_2()) {
1977 evmovw(dst, src);
1978 } else {
1979 assert(rscratch != noreg, "missing");
1980 evmovw(rscratch, src);
1981 evmovw(dst, rscratch);
1982 }
1983 }
1984
1985 void MacroAssembler::mov64(Register dst, int64_t imm64) {
1986 if (is_uimm32(imm64)) {
1987 movl(dst, checked_cast<uint32_t>(imm64));
1988 } else if (is_simm32(imm64)) {
1989 movq(dst, checked_cast<int32_t>(imm64));
1990 } else {
1991 Assembler::mov64(dst, imm64);
1992 }
1993 }
1994
1995 void MacroAssembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) {
1996 Assembler::mov64(dst, imm64, rtype, format);
1997 }
1998
1999 void MacroAssembler::movptr(Register dst, Register src) {
2000 movq(dst, src);
2001 }
2002
2003 void MacroAssembler::movptr(Register dst, Address src) {
2004 movq(dst, src);
2005 }
2006
2007 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2008 void MacroAssembler::movptr(Register dst, intptr_t src) {
2009 mov64(dst, src);
2010 }
2011
2012 void MacroAssembler::movptr(Address dst, Register src) {
2013 movq(dst, src);
2014 }
2015
2016 void MacroAssembler::movptr(Address dst, int32_t src) {
2017 movslq(dst, src);
2018 }
2019
2020 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2021 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2022 Assembler::movdqu(dst, src);
2023 }
2024
2025 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2026 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2027 Assembler::movdqu(dst, src);
2028 }
2029
2030 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2031 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2032 Assembler::movdqu(dst, src);
2033 }
2034
2035 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2036 assert(rscratch != noreg || always_reachable(src), "missing");
2037
2038 if (reachable(src)) {
2039 movdqu(dst, as_Address(src));
2040 } else {
2041 lea(rscratch, src);
2042 movdqu(dst, Address(rscratch, 0));
2043 }
2044 }
2045
2046 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2047 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2048 Assembler::vmovdqu(dst, src);
2049 }
2050
2051 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2052 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2053 Assembler::vmovdqu(dst, src);
2054 }
2055
2056 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2057 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2058 Assembler::vmovdqu(dst, src);
2059 }
2060
2061 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2062 assert(rscratch != noreg || always_reachable(src), "missing");
2063
2064 if (reachable(src)) {
2065 vmovdqu(dst, as_Address(src));
2066 }
2067 else {
2068 lea(rscratch, src);
2069 vmovdqu(dst, Address(rscratch, 0));
2070 }
2071 }
2072
2073 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2074 assert(rscratch != noreg || always_reachable(src), "missing");
2075
2076 if (vector_len == AVX_512bit) {
2077 evmovdquq(dst, src, AVX_512bit, rscratch);
2078 } else if (vector_len == AVX_256bit) {
2079 vmovdqu(dst, src, rscratch);
2080 } else {
2081 movdqu(dst, src, rscratch);
2082 }
2083 }
2084
2085 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2086 if (vector_len == AVX_512bit) {
2087 evmovdquq(dst, src, AVX_512bit);
2088 } else if (vector_len == AVX_256bit) {
2089 vmovdqu(dst, src);
2090 } else {
2091 movdqu(dst, src);
2092 }
2093 }
2094
2095 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2096 if (vector_len == AVX_512bit) {
2097 evmovdquq(dst, src, AVX_512bit);
2098 } else if (vector_len == AVX_256bit) {
2099 vmovdqu(dst, src);
2100 } else {
2101 movdqu(dst, src);
2102 }
2103 }
2104
2105 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2106 if (vector_len == AVX_512bit) {
2107 evmovdquq(dst, src, AVX_512bit);
2108 } else if (vector_len == AVX_256bit) {
2109 vmovdqu(dst, src);
2110 } else {
2111 movdqu(dst, src);
2112 }
2113 }
2114
2115 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2116 assert(rscratch != noreg || always_reachable(src), "missing");
2117
2118 if (reachable(src)) {
2119 vmovdqa(dst, as_Address(src));
2120 }
2121 else {
2122 lea(rscratch, src);
2123 vmovdqa(dst, Address(rscratch, 0));
2124 }
2125 }
2126
2127 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2128 assert(rscratch != noreg || always_reachable(src), "missing");
2129
2130 if (vector_len == AVX_512bit) {
2131 evmovdqaq(dst, src, AVX_512bit, rscratch);
2132 } else if (vector_len == AVX_256bit) {
2133 vmovdqa(dst, src, rscratch);
2134 } else {
2135 movdqa(dst, src, rscratch);
2136 }
2137 }
2138
2139 void MacroAssembler::vmovdqa(XMMRegister dst, Address src, int vector_len) {
2140 if (vector_len == AVX_512bit) {
2141 Assembler::evmovdqaq(dst, src, AVX_512bit);
2142 } else if (vector_len == AVX_256bit) {
2143 Assembler::vmovdqa(dst, src);
2144 } else {
2145 Assembler::movdqa(dst, src);
2146 }
2147 }
2148
2149 void MacroAssembler::vmovdqa(Address dst, XMMRegister src, int vector_len) {
2150 if (vector_len == AVX_512bit) {
2151 Assembler::evmovdqaq(dst, src, AVX_512bit);
2152 } else if (vector_len == AVX_256bit) {
2153 Assembler::vmovdqa(dst, src);
2154 } else {
2155 Assembler::movdqa(dst, src);
2156 }
2157 }
2158
2159 void MacroAssembler::kmov(KRegister dst, Address src) {
2160 if (VM_Version::supports_avx512bw()) {
2161 kmovql(dst, src);
2162 } else {
2163 assert(VM_Version::supports_evex(), "");
2164 kmovwl(dst, src);
2165 }
2166 }
2167
2168 void MacroAssembler::kmov(Address dst, KRegister src) {
2169 if (VM_Version::supports_avx512bw()) {
2170 kmovql(dst, src);
2171 } else {
2172 assert(VM_Version::supports_evex(), "");
2173 kmovwl(dst, src);
2174 }
2175 }
2176
2177 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2178 if (VM_Version::supports_avx512bw()) {
2179 kmovql(dst, src);
2180 } else {
2181 assert(VM_Version::supports_evex(), "");
2182 kmovwl(dst, src);
2183 }
2184 }
2185
2186 void MacroAssembler::kmov(Register dst, KRegister src) {
2187 if (VM_Version::supports_avx512bw()) {
2188 kmovql(dst, src);
2189 } else {
2190 assert(VM_Version::supports_evex(), "");
2191 kmovwl(dst, src);
2192 }
2193 }
2194
2195 void MacroAssembler::kmov(KRegister dst, Register src) {
2196 if (VM_Version::supports_avx512bw()) {
2197 kmovql(dst, src);
2198 } else {
2199 assert(VM_Version::supports_evex(), "");
2200 kmovwl(dst, src);
2201 }
2202 }
2203
2204 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2205 assert(rscratch != noreg || always_reachable(src), "missing");
2206
2207 if (reachable(src)) {
2208 kmovql(dst, as_Address(src));
2209 } else {
2210 lea(rscratch, src);
2211 kmovql(dst, Address(rscratch, 0));
2212 }
2213 }
2214
2215 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2216 assert(rscratch != noreg || always_reachable(src), "missing");
2217
2218 if (reachable(src)) {
2219 kmovwl(dst, as_Address(src));
2220 } else {
2221 lea(rscratch, src);
2222 kmovwl(dst, Address(rscratch, 0));
2223 }
2224 }
2225
2226 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2227 int vector_len, Register rscratch) {
2228 assert(rscratch != noreg || always_reachable(src), "missing");
2229
2230 if (reachable(src)) {
2231 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2232 } else {
2233 lea(rscratch, src);
2234 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2235 }
2236 }
2237
2238 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2239 int vector_len, Register rscratch) {
2240 assert(rscratch != noreg || always_reachable(src), "missing");
2241
2242 if (reachable(src)) {
2243 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2244 } else {
2245 lea(rscratch, src);
2246 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2247 }
2248 }
2249
2250 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2251 assert(rscratch != noreg || always_reachable(src), "missing");
2252
2253 if (reachable(src)) {
2254 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2255 } else {
2256 lea(rscratch, src);
2257 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2258 }
2259 }
2260
2261 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2262 assert(rscratch != noreg || always_reachable(src), "missing");
2263
2264 if (reachable(src)) {
2265 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2266 } else {
2267 lea(rscratch, src);
2268 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2269 }
2270 }
2271
2272 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2273 assert(rscratch != noreg || always_reachable(src), "missing");
2274
2275 if (reachable(src)) {
2276 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2277 } else {
2278 lea(rscratch, src);
2279 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2280 }
2281 }
2282
2283 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2284 assert(rscratch != noreg || always_reachable(src), "missing");
2285
2286 if (reachable(src)) {
2287 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2288 } else {
2289 lea(rscratch, src);
2290 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2291 }
2292 }
2293
2294 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2295 assert(rscratch != noreg || always_reachable(src), "missing");
2296
2297 if (reachable(src)) {
2298 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2299 } else {
2300 lea(rscratch, src);
2301 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2302 }
2303 }
2304
2305 void MacroAssembler::movapd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2306 assert(rscratch != noreg || always_reachable(src), "missing");
2307
2308 if (reachable(src)) {
2309 Assembler::movapd(dst, as_Address(src));
2310 } else {
2311 lea(rscratch, src);
2312 Assembler::movapd(dst, Address(rscratch, 0));
2313 }
2314 }
2315
2316 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2317 assert(rscratch != noreg || always_reachable(src), "missing");
2318
2319 if (reachable(src)) {
2320 Assembler::movdqa(dst, as_Address(src));
2321 } else {
2322 lea(rscratch, src);
2323 Assembler::movdqa(dst, Address(rscratch, 0));
2324 }
2325 }
2326
2327 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2328 assert(rscratch != noreg || always_reachable(src), "missing");
2329
2330 if (reachable(src)) {
2331 Assembler::movsd(dst, as_Address(src));
2332 } else {
2333 lea(rscratch, src);
2334 Assembler::movsd(dst, Address(rscratch, 0));
2335 }
2336 }
2337
2338 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2339 assert(rscratch != noreg || always_reachable(src), "missing");
2340
2341 if (reachable(src)) {
2342 Assembler::movss(dst, as_Address(src));
2343 } else {
2344 lea(rscratch, src);
2345 Assembler::movss(dst, Address(rscratch, 0));
2346 }
2347 }
2348
2349 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2350 assert(rscratch != noreg || always_reachable(src), "missing");
2351
2352 if (reachable(src)) {
2353 Assembler::movddup(dst, as_Address(src));
2354 } else {
2355 lea(rscratch, src);
2356 Assembler::movddup(dst, Address(rscratch, 0));
2357 }
2358 }
2359
2360 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2361 assert(rscratch != noreg || always_reachable(src), "missing");
2362
2363 if (reachable(src)) {
2364 Assembler::vmovddup(dst, as_Address(src), vector_len);
2365 } else {
2366 lea(rscratch, src);
2367 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2368 }
2369 }
2370
2371 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2372 assert(rscratch != noreg || always_reachable(src), "missing");
2373
2374 if (reachable(src)) {
2375 Assembler::mulsd(dst, as_Address(src));
2376 } else {
2377 lea(rscratch, src);
2378 Assembler::mulsd(dst, Address(rscratch, 0));
2379 }
2380 }
2381
2382 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2383 assert(rscratch != noreg || always_reachable(src), "missing");
2384
2385 if (reachable(src)) {
2386 Assembler::mulss(dst, as_Address(src));
2387 } else {
2388 lea(rscratch, src);
2389 Assembler::mulss(dst, Address(rscratch, 0));
2390 }
2391 }
2392
2393 void MacroAssembler::null_check(Register reg, int offset) {
2394 if (needs_explicit_null_check(offset)) {
2395 // provoke OS null exception if reg is null by
2396 // accessing M[reg] w/o changing any (non-CC) registers
2397 // NOTE: cmpl is plenty here to provoke a segv
2398 cmpptr(rax, Address(reg, 0));
2399 // Note: should probably use testl(rax, Address(reg, 0));
2400 // may be shorter code (however, this version of
2401 // testl needs to be implemented first)
2402 } else {
2403 // nothing to do, (later) access of M[reg + offset]
2404 // will provoke OS null exception if reg is null
2405 }
2406 }
2407
2408 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2409 andptr(markword, markWord::inline_type_pattern_mask);
2410 cmpptr(markword, markWord::inline_type_pattern);
2411 jcc(Assembler::equal, is_inline_type);
2412 }
2413
2414 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null) {
2415 if (can_be_null) {
2416 testptr(object, object);
2417 jcc(Assembler::zero, not_inline_type);
2418 }
2419 const int is_inline_type_mask = markWord::inline_type_pattern;
2420 movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2421 andptr(tmp, is_inline_type_mask);
2422 cmpptr(tmp, is_inline_type_mask);
2423 jcc(Assembler::notEqual, not_inline_type);
2424 }
2425
2426 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2427 movl(temp_reg, flags);
2428 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2429 jcc(Assembler::notEqual, is_null_free_inline_type);
2430 }
2431
2432 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2433 movl(temp_reg, flags);
2434 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2435 jcc(Assembler::equal, not_null_free_inline_type);
2436 }
2437
2438 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2439 movl(temp_reg, flags);
2440 testl(temp_reg, 1 << ResolvedFieldEntry::is_flat_shift);
2441 jcc(Assembler::notEqual, is_flat);
2442 }
2443
2444 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2445 // load mark word
2446 movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2447 if (!UseObjectMonitorTable) {
2448 Label test_mark_word;
2449 // check displaced
2450 testl(temp_reg, markWord::unlocked_value);
2451 jccb(Assembler::notZero, test_mark_word);
2452 // slow path use klass prototype
2453 push(rscratch1);
2454 load_prototype_header(temp_reg, oop, rscratch1);
2455 pop(rscratch1);
2456
2457 bind(test_mark_word);
2458 }
2459 testl(temp_reg, test_bit);
2460 jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
2461 }
2462
2463 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg,
2464 Label& is_flat_array) {
2465 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2466 }
2467
2468 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2469 Label& is_non_flat_array) {
2470 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2471 }
2472
2473 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
2474 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2475 }
2476
2477 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2478 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2479 }
2480
2481 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2482 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2483 jcc(Assembler::notZero, is_flat_array);
2484 }
2485
2486 void MacroAssembler::os_breakpoint() {
2487 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2488 // (e.g., MSVC can't call ps() otherwise)
2489 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2490 }
2491
2492 void MacroAssembler::unimplemented(const char* what) {
2493 const char* buf = nullptr;
2494 {
2495 ResourceMark rm;
2496 stringStream ss;
2497 ss.print("unimplemented: %s", what);
2498 buf = code_string(ss.as_string());
2499 }
2500 stop(buf);
2501 }
2502
2503 #define XSTATE_BV 0x200
2504
2505 void MacroAssembler::pop_CPU_state() {
2506 pop_FPU_state();
2507 pop_IU_state();
2508 }
2509
2510 void MacroAssembler::pop_FPU_state() {
2511 fxrstor(Address(rsp, 0));
2512 addptr(rsp, FPUStateSizeInWords * wordSize);
2513 }
2514
2515 void MacroAssembler::pop_IU_state() {
2516 popa();
2517 addq(rsp, 8);
2518 popf();
2519 }
2520
2521 // Save Integer and Float state
2522 // Warning: Stack must be 16 byte aligned (64bit)
2523 void MacroAssembler::push_CPU_state() {
2524 push_IU_state();
2525 push_FPU_state();
2526 }
2527
2528 void MacroAssembler::push_FPU_state() {
2529 subptr(rsp, FPUStateSizeInWords * wordSize);
2530 fxsave(Address(rsp, 0));
2531 }
2532
2533 void MacroAssembler::push_IU_state() {
2534 // Push flags first because pusha kills them
2535 pushf();
2536 // Make sure rsp stays 16-byte aligned
2537 subq(rsp, 8);
2538 pusha();
2539 }
2540
2541 void MacroAssembler::push_cont_fastpath() {
2542 if (!Continuations::enabled()) return;
2543
2544 Label L_done;
2545 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2546 jccb(Assembler::belowEqual, L_done);
2547 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), rsp);
2548 bind(L_done);
2549 }
2550
2551 void MacroAssembler::pop_cont_fastpath() {
2552 if (!Continuations::enabled()) return;
2553
2554 Label L_done;
2555 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2556 jccb(Assembler::below, L_done);
2557 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), 0);
2558 bind(L_done);
2559 }
2560
2561 #ifdef ASSERT
2562 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2563 Label no_cont;
2564 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2565 testl(cont, cont);
2566 jcc(Assembler::zero, no_cont);
2567 stop(name);
2568 bind(no_cont);
2569 }
2570 #endif
2571
2572 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { // determine java_thread register
2573 // we must set sp to zero to clear frame
2574 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2575 // must clear fp, so that compiled frames are not confused; it is
2576 // possible that we need it only for debugging
2577 if (clear_fp) {
2578 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2579 }
2580 // Always clear the pc because it could have been set by make_walkable()
2581 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2582 vzeroupper();
2583 }
2584
2585 void MacroAssembler::round_to(Register reg, int modulus) {
2586 addptr(reg, modulus - 1);
2587 andptr(reg, -modulus);
2588 }
2589
2590 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod) {
2591 if (at_return) {
2592 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2593 // we may safely use rsp instead to perform the stack watermark check.
2594 cmpptr(in_nmethod ? rsp : rbp, Address(r15_thread, JavaThread::polling_word_offset()));
2595 jcc(Assembler::above, slow_path);
2596 return;
2597 }
2598 testb(Address(r15_thread, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2599 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2600 }
2601
2602 // Calls to C land
2603 //
2604 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2605 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2606 // has to be reset to 0. This is required to allow proper stack traversal.
2607 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2608 Register last_java_fp,
2609 address last_java_pc,
2610 Register rscratch) {
2611 vzeroupper();
2612 // determine last_java_sp register
2613 if (!last_java_sp->is_valid()) {
2614 last_java_sp = rsp;
2615 }
2616 // last_java_fp is optional
2617 if (last_java_fp->is_valid()) {
2618 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2619 }
2620 // last_java_pc is optional
2621 if (last_java_pc != nullptr) {
2622 Address java_pc(r15_thread,
2623 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
2624 lea(java_pc, InternalAddress(last_java_pc), rscratch);
2625 }
2626 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2627 }
2628
2629 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2630 Register last_java_fp,
2631 Label &L,
2632 Register scratch) {
2633 lea(scratch, L);
2634 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
2635 set_last_Java_frame(last_java_sp, last_java_fp, nullptr, scratch);
2636 }
2637
2638 void MacroAssembler::shlptr(Register dst, int imm8) {
2639 shlq(dst, imm8);
2640 }
2641
2642 void MacroAssembler::shrptr(Register dst, int imm8) {
2643 shrq(dst, imm8);
2644 }
2645
2646 void MacroAssembler::sign_extend_byte(Register reg) {
2647 movsbl(reg, reg); // movsxb
2648 }
2649
2650 void MacroAssembler::sign_extend_short(Register reg) {
2651 movswl(reg, reg); // movsxw
2652 }
2653
2654 void MacroAssembler::narrow_subword_type(Register reg, BasicType bt) {
2655 assert(is_subword_type(bt), "required");
2656 switch (bt) {
2657 case T_BOOLEAN: andl(reg, 1); break;
2658 case T_BYTE: movsbl(reg, reg); break;
2659 case T_CHAR: movzwl(reg, reg); break;
2660 case T_SHORT: movswl(reg, reg); break;
2661 default: ShouldNotReachHere();
2662 }
2663 }
2664
2665 void MacroAssembler::testl(Address dst, int32_t imm32) {
2666 if (imm32 >= 0 && is8bit(imm32)) {
2667 testb(dst, imm32);
2668 } else {
2669 Assembler::testl(dst, imm32);
2670 }
2671 }
2672
2673 void MacroAssembler::testl(Register dst, int32_t imm32) {
2674 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
2675 testb(dst, imm32);
2676 } else {
2677 Assembler::testl(dst, imm32);
2678 }
2679 }
2680
2681 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2682 assert(always_reachable(src), "Address should be reachable");
2683 testl(dst, as_Address(src));
2684 }
2685
2686 void MacroAssembler::testq(Address dst, int32_t imm32) {
2687 if (imm32 >= 0) {
2688 testl(dst, imm32);
2689 } else {
2690 Assembler::testq(dst, imm32);
2691 }
2692 }
2693
2694 void MacroAssembler::testq(Register dst, int32_t imm32) {
2695 if (imm32 >= 0) {
2696 testl(dst, imm32);
2697 } else {
2698 Assembler::testq(dst, imm32);
2699 }
2700 }
2701
2702 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2703 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2704 Assembler::pcmpeqb(dst, src);
2705 }
2706
2707 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2708 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2709 Assembler::pcmpeqw(dst, src);
2710 }
2711
2712 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2713 assert((dst->encoding() < 16),"XMM register should be 0-15");
2714 Assembler::pcmpestri(dst, src, imm8);
2715 }
2716
2717 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2718 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2719 Assembler::pcmpestri(dst, src, imm8);
2720 }
2721
2722 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2723 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2724 Assembler::pmovzxbw(dst, src);
2725 }
2726
2727 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2728 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2729 Assembler::pmovzxbw(dst, src);
2730 }
2731
2732 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2733 assert((src->encoding() < 16),"XMM register should be 0-15");
2734 Assembler::pmovmskb(dst, src);
2735 }
2736
2737 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2738 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2739 Assembler::ptest(dst, src);
2740 }
2741
2742 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2743 assert(rscratch != noreg || always_reachable(src), "missing");
2744
2745 if (reachable(src)) {
2746 Assembler::sqrtss(dst, as_Address(src));
2747 } else {
2748 lea(rscratch, src);
2749 Assembler::sqrtss(dst, Address(rscratch, 0));
2750 }
2751 }
2752
2753 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2754 assert(rscratch != noreg || always_reachable(src), "missing");
2755
2756 if (reachable(src)) {
2757 Assembler::subsd(dst, as_Address(src));
2758 } else {
2759 lea(rscratch, src);
2760 Assembler::subsd(dst, Address(rscratch, 0));
2761 }
2762 }
2763
2764 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
2765 assert(rscratch != noreg || always_reachable(src), "missing");
2766
2767 if (reachable(src)) {
2768 Assembler::roundsd(dst, as_Address(src), rmode);
2769 } else {
2770 lea(rscratch, src);
2771 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
2772 }
2773 }
2774
2775 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2776 assert(rscratch != noreg || always_reachable(src), "missing");
2777
2778 if (reachable(src)) {
2779 Assembler::subss(dst, as_Address(src));
2780 } else {
2781 lea(rscratch, src);
2782 Assembler::subss(dst, Address(rscratch, 0));
2783 }
2784 }
2785
2786 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2787 assert(rscratch != noreg || always_reachable(src), "missing");
2788
2789 if (reachable(src)) {
2790 Assembler::ucomisd(dst, as_Address(src));
2791 } else {
2792 lea(rscratch, src);
2793 Assembler::ucomisd(dst, Address(rscratch, 0));
2794 }
2795 }
2796
2797 void MacroAssembler::evucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2798 assert(rscratch != noreg || always_reachable(src), "missing");
2799
2800 if (reachable(src)) {
2801 Assembler::evucomxsd(dst, as_Address(src));
2802 } else {
2803 lea(rscratch, src);
2804 Assembler::evucomxsd(dst, Address(rscratch, 0));
2805 }
2806 }
2807
2808 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2809 assert(rscratch != noreg || always_reachable(src), "missing");
2810
2811 if (reachable(src)) {
2812 Assembler::ucomiss(dst, as_Address(src));
2813 } else {
2814 lea(rscratch, src);
2815 Assembler::ucomiss(dst, Address(rscratch, 0));
2816 }
2817 }
2818
2819 void MacroAssembler::evucomxss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2820 assert(rscratch != noreg || always_reachable(src), "missing");
2821
2822 if (reachable(src)) {
2823 Assembler::evucomxss(dst, as_Address(src));
2824 } else {
2825 lea(rscratch, src);
2826 Assembler::evucomxss(dst, Address(rscratch, 0));
2827 }
2828 }
2829
2830 void MacroAssembler::evucomish(XMMRegister dst, AddressLiteral src, Register rscratch) {
2831 assert(rscratch != noreg || always_reachable(src), "missing");
2832
2833 if (reachable(src)) {
2834 Assembler::evucomish(dst, as_Address(src));
2835 } else {
2836 lea(rscratch, src);
2837 Assembler::evucomish(dst, Address(rscratch, 0));
2838 }
2839 }
2840
2841 void MacroAssembler::evucomxsh(XMMRegister dst, AddressLiteral src, Register rscratch) {
2842 assert(rscratch != noreg || always_reachable(src), "missing");
2843
2844 if (reachable(src)) {
2845 Assembler::evucomxsh(dst, as_Address(src));
2846 } else {
2847 lea(rscratch, src);
2848 Assembler::evucomxsh(dst, Address(rscratch, 0));
2849 }
2850 }
2851
2852 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2853 assert(rscratch != noreg || always_reachable(src), "missing");
2854
2855 // Used in sign-bit flipping with aligned address.
2856 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2857
2858 if (UseAVX > 2 &&
2859 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2860 (dst->encoding() >= 16)) {
2861 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2862 } else if (reachable(src)) {
2863 Assembler::xorpd(dst, as_Address(src));
2864 } else {
2865 lea(rscratch, src);
2866 Assembler::xorpd(dst, Address(rscratch, 0));
2867 }
2868 }
2869
2870 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
2871 if (UseAVX > 2 &&
2872 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2873 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2874 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2875 } else {
2876 Assembler::xorpd(dst, src);
2877 }
2878 }
2879
2880 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
2881 if (UseAVX > 2 &&
2882 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2883 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2884 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2885 } else {
2886 Assembler::xorps(dst, src);
2887 }
2888 }
2889
2890 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
2891 assert(rscratch != noreg || always_reachable(src), "missing");
2892
2893 // Used in sign-bit flipping with aligned address.
2894 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2895
2896 if (UseAVX > 2 &&
2897 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2898 (dst->encoding() >= 16)) {
2899 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2900 } else if (reachable(src)) {
2901 Assembler::xorps(dst, as_Address(src));
2902 } else {
2903 lea(rscratch, src);
2904 Assembler::xorps(dst, Address(rscratch, 0));
2905 }
2906 }
2907
2908 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
2909 assert(rscratch != noreg || always_reachable(src), "missing");
2910
2911 // Used in sign-bit flipping with aligned address.
2912 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
2913 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2914 if (reachable(src)) {
2915 Assembler::pshufb(dst, as_Address(src));
2916 } else {
2917 lea(rscratch, src);
2918 Assembler::pshufb(dst, Address(rscratch, 0));
2919 }
2920 }
2921
2922 // AVX 3-operands instructions
2923
2924 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2925 assert(rscratch != noreg || always_reachable(src), "missing");
2926
2927 if (reachable(src)) {
2928 vaddsd(dst, nds, as_Address(src));
2929 } else {
2930 lea(rscratch, src);
2931 vaddsd(dst, nds, Address(rscratch, 0));
2932 }
2933 }
2934
2935 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2936 assert(rscratch != noreg || always_reachable(src), "missing");
2937
2938 if (reachable(src)) {
2939 vaddss(dst, nds, as_Address(src));
2940 } else {
2941 lea(rscratch, src);
2942 vaddss(dst, nds, Address(rscratch, 0));
2943 }
2944 }
2945
2946 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2947 assert(UseAVX > 0, "requires some form of AVX");
2948 assert(rscratch != noreg || always_reachable(src), "missing");
2949
2950 if (reachable(src)) {
2951 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
2952 } else {
2953 lea(rscratch, src);
2954 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
2955 }
2956 }
2957
2958 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2959 assert(UseAVX > 0, "requires some form of AVX");
2960 assert(rscratch != noreg || always_reachable(src), "missing");
2961
2962 if (reachable(src)) {
2963 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
2964 } else {
2965 lea(rscratch, src);
2966 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
2967 }
2968 }
2969
2970 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2971 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2972 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2973
2974 vandps(dst, nds, negate_field, vector_len, rscratch);
2975 }
2976
2977 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2978 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2979 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2980
2981 vandpd(dst, nds, negate_field, vector_len, rscratch);
2982 }
2983
2984 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2985 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2986 Assembler::vpaddb(dst, nds, src, vector_len);
2987 }
2988
2989 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2990 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2991 Assembler::vpaddb(dst, nds, src, vector_len);
2992 }
2993
2994 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2995 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2996 Assembler::vpaddw(dst, nds, src, vector_len);
2997 }
2998
2999 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3000 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3001 Assembler::vpaddw(dst, nds, src, vector_len);
3002 }
3003
3004 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3005 assert(rscratch != noreg || always_reachable(src), "missing");
3006
3007 if (reachable(src)) {
3008 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3009 } else {
3010 lea(rscratch, src);
3011 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3012 }
3013 }
3014
3015 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3016 assert(rscratch != noreg || always_reachable(src), "missing");
3017
3018 if (reachable(src)) {
3019 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3020 } else {
3021 lea(rscratch, src);
3022 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3023 }
3024 }
3025
3026 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3027 assert(rscratch != noreg || always_reachable(src), "missing");
3028
3029 if (reachable(src)) {
3030 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3031 } else {
3032 lea(rscratch, src);
3033 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3034 }
3035 }
3036
3037 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3038 assert(rscratch != noreg || always_reachable(src), "missing");
3039
3040 if (reachable(src)) {
3041 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3042 } else {
3043 lea(rscratch, src);
3044 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3045 }
3046 }
3047
3048 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3049 assert(rscratch != noreg || always_reachable(src), "missing");
3050
3051 if (reachable(src)) {
3052 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3053 } else {
3054 lea(rscratch, src);
3055 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3056 }
3057 }
3058
3059 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3060 assert(rscratch != noreg || always_reachable(src), "missing");
3061
3062 if (reachable(src)) {
3063 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3064 } else {
3065 lea(rscratch, src);
3066 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3067 }
3068 }
3069
3070 // Vector float blend
3071 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3072 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3073 // WARN: Allow dst == (src1|src2), mask == scratch
3074 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3075 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3076 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3077 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3078 if (blend_emulation && scratch_available && dst_available) {
3079 if (compute_mask) {
3080 vpsrad(scratch, mask, 32, vector_len);
3081 mask = scratch;
3082 }
3083 if (dst == src1) {
3084 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3085 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3086 } else {
3087 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3088 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3089 }
3090 vpor(dst, dst, scratch, vector_len);
3091 } else {
3092 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3093 }
3094 }
3095
3096 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3097 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3098 // WARN: Allow dst == (src1|src2), mask == scratch
3099 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3100 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3101 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3102 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3103 if (blend_emulation && scratch_available && dst_available) {
3104 if (compute_mask) {
3105 vpxor(scratch, scratch, scratch, vector_len);
3106 vpcmpgtq(scratch, scratch, mask, vector_len);
3107 mask = scratch;
3108 }
3109 if (dst == src1) {
3110 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3111 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3112 } else {
3113 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3114 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3115 }
3116 vpor(dst, dst, scratch, vector_len);
3117 } else {
3118 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3119 }
3120 }
3121
3122 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3123 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3124 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3125 }
3126
3127 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3128 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3129 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3130 }
3131
3132 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3133 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3134 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3135 }
3136
3137 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3138 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3139 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3140 }
3141
3142 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3143 assert(rscratch != noreg || always_reachable(src), "missing");
3144
3145 if (reachable(src)) {
3146 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3147 } else {
3148 lea(rscratch, src);
3149 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3150 }
3151 }
3152
3153 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3154 int comparison, bool is_signed, int vector_len, Register rscratch) {
3155 assert(rscratch != noreg || always_reachable(src), "missing");
3156
3157 if (reachable(src)) {
3158 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3159 } else {
3160 lea(rscratch, src);
3161 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3162 }
3163 }
3164
3165 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3166 int comparison, bool is_signed, int vector_len, Register rscratch) {
3167 assert(rscratch != noreg || always_reachable(src), "missing");
3168
3169 if (reachable(src)) {
3170 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3171 } else {
3172 lea(rscratch, src);
3173 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3174 }
3175 }
3176
3177 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3178 int comparison, bool is_signed, int vector_len, Register rscratch) {
3179 assert(rscratch != noreg || always_reachable(src), "missing");
3180
3181 if (reachable(src)) {
3182 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3183 } else {
3184 lea(rscratch, src);
3185 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3186 }
3187 }
3188
3189 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3190 int comparison, bool is_signed, int vector_len, Register rscratch) {
3191 assert(rscratch != noreg || always_reachable(src), "missing");
3192
3193 if (reachable(src)) {
3194 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3195 } else {
3196 lea(rscratch, src);
3197 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3198 }
3199 }
3200
3201 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3202 if (width == Assembler::Q) {
3203 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3204 } else {
3205 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3206 }
3207 }
3208
3209 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3210 int eq_cond_enc = 0x29;
3211 int gt_cond_enc = 0x37;
3212 if (width != Assembler::Q) {
3213 eq_cond_enc = 0x74 + width;
3214 gt_cond_enc = 0x64 + width;
3215 }
3216 switch (cond) {
3217 case eq:
3218 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3219 break;
3220 case neq:
3221 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3222 vallones(xtmp, vector_len);
3223 vpxor(dst, xtmp, dst, vector_len);
3224 break;
3225 case le:
3226 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3227 vallones(xtmp, vector_len);
3228 vpxor(dst, xtmp, dst, vector_len);
3229 break;
3230 case nlt:
3231 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3232 vallones(xtmp, vector_len);
3233 vpxor(dst, xtmp, dst, vector_len);
3234 break;
3235 case lt:
3236 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3237 break;
3238 case nle:
3239 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3240 break;
3241 default:
3242 assert(false, "Should not reach here");
3243 }
3244 }
3245
3246 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3247 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3248 Assembler::vpmovzxbw(dst, src, vector_len);
3249 }
3250
3251 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3252 assert((src->encoding() < 16),"XMM register should be 0-15");
3253 Assembler::vpmovmskb(dst, src, vector_len);
3254 }
3255
3256 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3257 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3258 Assembler::vpmullw(dst, nds, src, vector_len);
3259 }
3260
3261 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3262 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3263 Assembler::vpmullw(dst, nds, src, vector_len);
3264 }
3265
3266 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3267 assert((UseAVX > 0), "AVX support is needed");
3268 assert(rscratch != noreg || always_reachable(src), "missing");
3269
3270 if (reachable(src)) {
3271 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3272 } else {
3273 lea(rscratch, src);
3274 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3275 }
3276 }
3277
3278 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3279 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3280 Assembler::vpsubb(dst, nds, src, vector_len);
3281 }
3282
3283 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3284 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3285 Assembler::vpsubb(dst, nds, src, vector_len);
3286 }
3287
3288 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3289 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3290 Assembler::vpsubw(dst, nds, src, vector_len);
3291 }
3292
3293 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3294 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3295 Assembler::vpsubw(dst, nds, src, vector_len);
3296 }
3297
3298 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3299 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3300 Assembler::vpsraw(dst, nds, shift, vector_len);
3301 }
3302
3303 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3304 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3305 Assembler::vpsraw(dst, nds, shift, vector_len);
3306 }
3307
3308 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3309 assert(UseAVX > 2,"");
3310 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3311 vector_len = 2;
3312 }
3313 Assembler::evpsraq(dst, nds, shift, vector_len);
3314 }
3315
3316 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3317 assert(UseAVX > 2,"");
3318 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3319 vector_len = 2;
3320 }
3321 Assembler::evpsraq(dst, nds, shift, vector_len);
3322 }
3323
3324 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3325 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3326 Assembler::vpsrlw(dst, nds, shift, vector_len);
3327 }
3328
3329 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3330 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3331 Assembler::vpsrlw(dst, nds, shift, vector_len);
3332 }
3333
3334 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3335 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3336 Assembler::vpsllw(dst, nds, shift, vector_len);
3337 }
3338
3339 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3340 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3341 Assembler::vpsllw(dst, nds, shift, vector_len);
3342 }
3343
3344 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3345 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3346 Assembler::vptest(dst, src);
3347 }
3348
3349 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3350 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3351 Assembler::punpcklbw(dst, src);
3352 }
3353
3354 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3355 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3356 Assembler::pshufd(dst, src, mode);
3357 }
3358
3359 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3360 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3361 Assembler::pshuflw(dst, src, mode);
3362 }
3363
3364 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3365 assert(rscratch != noreg || always_reachable(src), "missing");
3366
3367 if (reachable(src)) {
3368 vandpd(dst, nds, as_Address(src), vector_len);
3369 } else {
3370 lea(rscratch, src);
3371 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3372 }
3373 }
3374
3375 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3376 assert(rscratch != noreg || always_reachable(src), "missing");
3377
3378 if (reachable(src)) {
3379 vandps(dst, nds, as_Address(src), vector_len);
3380 } else {
3381 lea(rscratch, src);
3382 vandps(dst, nds, Address(rscratch, 0), vector_len);
3383 }
3384 }
3385
3386 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3387 bool merge, int vector_len, Register rscratch) {
3388 assert(rscratch != noreg || always_reachable(src), "missing");
3389
3390 if (reachable(src)) {
3391 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3392 } else {
3393 lea(rscratch, src);
3394 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3395 }
3396 }
3397
3398 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3399 assert(rscratch != noreg || always_reachable(src), "missing");
3400
3401 if (reachable(src)) {
3402 vdivsd(dst, nds, as_Address(src));
3403 } else {
3404 lea(rscratch, src);
3405 vdivsd(dst, nds, Address(rscratch, 0));
3406 }
3407 }
3408
3409 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3410 assert(rscratch != noreg || always_reachable(src), "missing");
3411
3412 if (reachable(src)) {
3413 vdivss(dst, nds, as_Address(src));
3414 } else {
3415 lea(rscratch, src);
3416 vdivss(dst, nds, Address(rscratch, 0));
3417 }
3418 }
3419
3420 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3421 assert(rscratch != noreg || always_reachable(src), "missing");
3422
3423 if (reachable(src)) {
3424 vmulsd(dst, nds, as_Address(src));
3425 } else {
3426 lea(rscratch, src);
3427 vmulsd(dst, nds, Address(rscratch, 0));
3428 }
3429 }
3430
3431 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3432 assert(rscratch != noreg || always_reachable(src), "missing");
3433
3434 if (reachable(src)) {
3435 vmulss(dst, nds, as_Address(src));
3436 } else {
3437 lea(rscratch, src);
3438 vmulss(dst, nds, Address(rscratch, 0));
3439 }
3440 }
3441
3442 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3443 assert(rscratch != noreg || always_reachable(src), "missing");
3444
3445 if (reachable(src)) {
3446 vsubsd(dst, nds, as_Address(src));
3447 } else {
3448 lea(rscratch, src);
3449 vsubsd(dst, nds, Address(rscratch, 0));
3450 }
3451 }
3452
3453 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3454 assert(rscratch != noreg || always_reachable(src), "missing");
3455
3456 if (reachable(src)) {
3457 vsubss(dst, nds, as_Address(src));
3458 } else {
3459 lea(rscratch, src);
3460 vsubss(dst, nds, Address(rscratch, 0));
3461 }
3462 }
3463
3464 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3465 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3466 assert(rscratch != noreg || always_reachable(src), "missing");
3467
3468 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3469 }
3470
3471 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3472 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3473 assert(rscratch != noreg || always_reachable(src), "missing");
3474
3475 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3476 }
3477
3478 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3479 assert(rscratch != noreg || always_reachable(src), "missing");
3480
3481 if (reachable(src)) {
3482 vxorpd(dst, nds, as_Address(src), vector_len);
3483 } else {
3484 lea(rscratch, src);
3485 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3486 }
3487 }
3488
3489 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3490 assert(rscratch != noreg || always_reachable(src), "missing");
3491
3492 if (reachable(src)) {
3493 vxorps(dst, nds, as_Address(src), vector_len);
3494 } else {
3495 lea(rscratch, src);
3496 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3497 }
3498 }
3499
3500 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3501 assert(rscratch != noreg || always_reachable(src), "missing");
3502
3503 if (UseAVX > 1 || (vector_len < 1)) {
3504 if (reachable(src)) {
3505 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3506 } else {
3507 lea(rscratch, src);
3508 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3509 }
3510 } else {
3511 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3512 }
3513 }
3514
3515 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3516 assert(rscratch != noreg || always_reachable(src), "missing");
3517
3518 if (reachable(src)) {
3519 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3520 } else {
3521 lea(rscratch, src);
3522 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3523 }
3524 }
3525
3526 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3527 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3528 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3529 // The inverted mask is sign-extended
3530 andptr(possibly_non_local, inverted_mask);
3531 }
3532
3533 void MacroAssembler::resolve_jobject(Register value,
3534 Register tmp) {
3535 Register thread = r15_thread;
3536 assert_different_registers(value, thread, tmp);
3537 Label done, tagged, weak_tagged;
3538 testptr(value, value);
3539 jcc(Assembler::zero, done); // Use null as-is.
3540 testptr(value, JNIHandles::tag_mask); // Test for tag.
3541 jcc(Assembler::notZero, tagged);
3542
3543 // Resolve local handle
3544 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp);
3545 verify_oop(value);
3546 jmp(done);
3547
3548 bind(tagged);
3549 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3550 jcc(Assembler::notZero, weak_tagged);
3551
3552 // Resolve global handle
3553 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3554 verify_oop(value);
3555 jmp(done);
3556
3557 bind(weak_tagged);
3558 // Resolve jweak.
3559 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3560 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp);
3561 verify_oop(value);
3562
3563 bind(done);
3564 }
3565
3566 void MacroAssembler::resolve_global_jobject(Register value,
3567 Register tmp) {
3568 Register thread = r15_thread;
3569 assert_different_registers(value, thread, tmp);
3570 Label done;
3571
3572 testptr(value, value);
3573 jcc(Assembler::zero, done); // Use null as-is.
3574
3575 #ifdef ASSERT
3576 {
3577 Label valid_global_tag;
3578 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
3579 jcc(Assembler::notZero, valid_global_tag);
3580 stop("non global jobject using resolve_global_jobject");
3581 bind(valid_global_tag);
3582 }
3583 #endif
3584
3585 // Resolve global handle
3586 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3587 verify_oop(value);
3588
3589 bind(done);
3590 }
3591
3592 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3593 subq(dst, imm32);
3594 }
3595
3596 // Force generation of a 4 byte immediate value even if it fits into 8bit
3597 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3598 subq_imm32(dst, imm32);
3599 }
3600
3601 void MacroAssembler::subptr(Register dst, Register src) {
3602 subq(dst, src);
3603 }
3604
3605 // C++ bool manipulation
3606 void MacroAssembler::testbool(Register dst) {
3607 if(sizeof(bool) == 1)
3608 testb(dst, 0xff);
3609 else if(sizeof(bool) == 2) {
3610 // testw implementation needed for two byte bools
3611 ShouldNotReachHere();
3612 } else if(sizeof(bool) == 4)
3613 testl(dst, dst);
3614 else
3615 // unsupported
3616 ShouldNotReachHere();
3617 }
3618
3619 void MacroAssembler::testptr(Register dst, Register src) {
3620 testq(dst, src);
3621 }
3622
3623 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3624 void MacroAssembler::tlab_allocate(Register obj,
3625 Register var_size_in_bytes,
3626 int con_size_in_bytes,
3627 Register t1,
3628 Register t2,
3629 Label& slow_case) {
3630 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3631 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3632 }
3633
3634 RegSet MacroAssembler::call_clobbered_gp_registers() {
3635 RegSet regs;
3636 regs += RegSet::of(rax, rcx, rdx);
3637 #ifndef _WINDOWS
3638 regs += RegSet::of(rsi, rdi);
3639 #endif
3640 regs += RegSet::range(r8, r11);
3641 if (UseAPX) {
3642 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
3643 }
3644 return regs;
3645 }
3646
3647 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3648 int num_xmm_registers = XMMRegister::available_xmm_registers();
3649 #if defined(_WINDOWS)
3650 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3651 if (num_xmm_registers > 16) {
3652 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3653 }
3654 return result;
3655 #else
3656 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3657 #endif
3658 }
3659
3660 // C1 only ever uses the first double/float of the XMM register.
3661 static int xmm_save_size() { return sizeof(double); }
3662
3663 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3664 masm->movdbl(Address(rsp, offset), reg);
3665 }
3666
3667 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3668 masm->movdbl(reg, Address(rsp, offset));
3669 }
3670
3671 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
3672 bool save_fpu, int& gp_area_size, int& xmm_area_size) {
3673
3674 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
3675 StackAlignmentInBytes);
3676 xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
3677
3678 return gp_area_size + xmm_area_size;
3679 }
3680
3681 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3682 block_comment("push_call_clobbered_registers start");
3683 // Regular registers
3684 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3685
3686 int gp_area_size;
3687 int xmm_area_size;
3688 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3689 gp_area_size, xmm_area_size);
3690 subptr(rsp, total_save_size);
3691
3692 push_set(gp_registers_to_push, 0);
3693
3694 if (save_fpu) {
3695 push_set(call_clobbered_xmm_registers(), gp_area_size);
3696 }
3697
3698 block_comment("push_call_clobbered_registers end");
3699 }
3700
3701 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3702 block_comment("pop_call_clobbered_registers start");
3703
3704 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3705
3706 int gp_area_size;
3707 int xmm_area_size;
3708 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3709 gp_area_size, xmm_area_size);
3710
3711 if (restore_fpu) {
3712 pop_set(call_clobbered_xmm_registers(), gp_area_size);
3713 }
3714
3715 pop_set(gp_registers_to_pop, 0);
3716
3717 addptr(rsp, total_save_size);
3718
3719 vzeroupper();
3720
3721 block_comment("pop_call_clobbered_registers end");
3722 }
3723
3724 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3725 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3726 int spill_offset = offset;
3727
3728 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3729 save_xmm_register(this, spill_offset, *it);
3730 spill_offset += xmm_save_size();
3731 }
3732 }
3733
3734 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3735 int restore_size = set.size() * xmm_save_size();
3736 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3737
3738 int restore_offset = offset + restore_size - xmm_save_size();
3739
3740 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3741 restore_xmm_register(this, restore_offset, *it);
3742 restore_offset -= xmm_save_size();
3743 }
3744 }
3745
3746 void MacroAssembler::push_set(RegSet set, int offset) {
3747 int spill_offset;
3748 if (offset == -1) {
3749 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3750 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3751 subptr(rsp, aligned_size);
3752 spill_offset = 0;
3753 } else {
3754 spill_offset = offset;
3755 }
3756
3757 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3758 movptr(Address(rsp, spill_offset), *it);
3759 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3760 }
3761 }
3762
3763 void MacroAssembler::pop_set(RegSet set, int offset) {
3764
3765 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3766 int restore_size = set.size() * gp_reg_size;
3767 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3768
3769 int restore_offset;
3770 if (offset == -1) {
3771 restore_offset = restore_size - gp_reg_size;
3772 } else {
3773 restore_offset = offset + restore_size - gp_reg_size;
3774 }
3775 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3776 movptr(*it, Address(rsp, restore_offset));
3777 restore_offset -= gp_reg_size;
3778 }
3779
3780 if (offset == -1) {
3781 addptr(rsp, aligned_size);
3782 }
3783 }
3784
3785 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3786 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3787 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3788 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3789 Label done;
3790
3791 testptr(length_in_bytes, length_in_bytes);
3792 jcc(Assembler::zero, done);
3793
3794 // initialize topmost word, divide index by 2, check if odd and test if zero
3795 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3796 #ifdef ASSERT
3797 {
3798 Label L;
3799 testptr(length_in_bytes, BytesPerWord - 1);
3800 jcc(Assembler::zero, L);
3801 stop("length must be a multiple of BytesPerWord");
3802 bind(L);
3803 }
3804 #endif
3805 Register index = length_in_bytes;
3806 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3807 if (UseIncDec) {
3808 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3809 } else {
3810 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3811 shrptr(index, 1);
3812 }
3813
3814 // initialize remaining object fields: index is a multiple of 2 now
3815 {
3816 Label loop;
3817 bind(loop);
3818 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3819 decrement(index);
3820 jcc(Assembler::notZero, loop);
3821 }
3822
3823 bind(done);
3824 }
3825
3826 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
3827 movptr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
3828 #ifdef ASSERT
3829 {
3830 Label done;
3831 cmpptr(layout_info, 0);
3832 jcc(Assembler::notEqual, done);
3833 stop("inline_layout_info_array is null");
3834 bind(done);
3835 }
3836 #endif
3837
3838 InlineLayoutInfo array[2];
3839 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
3840 if (is_power_of_2(size)) {
3841 shll(index, log2i_exact(size)); // Scale index by power of 2
3842 } else {
3843 imull(index, index, size); // Scale the index to be the entry index * array_element_size
3844 }
3845 lea(layout_info, Address(layout_info, index, Address::times_1, Array<InlineLayoutInfo>::base_offset_in_bytes()));
3846 }
3847
3848 // Look up the method for a megamorphic invokeinterface call.
3849 // The target method is determined by <intf_klass, itable_index>.
3850 // The receiver klass is in recv_klass.
3851 // On success, the result will be in method_result, and execution falls through.
3852 // On failure, execution transfers to the given label.
3853 void MacroAssembler::lookup_interface_method(Register recv_klass,
3854 Register intf_klass,
3855 RegisterOrConstant itable_index,
3856 Register method_result,
3857 Register scan_temp,
3858 Label& L_no_such_interface,
3859 bool return_method) {
3860 assert_different_registers(recv_klass, intf_klass, scan_temp);
3861 assert_different_registers(method_result, intf_klass, scan_temp);
3862 assert(recv_klass != method_result || !return_method,
3863 "recv_klass can be destroyed when method isn't needed");
3864
3865 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3866 "caller must use same register for non-constant itable index as for method");
3867
3868 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3869 int vtable_base = in_bytes(Klass::vtable_start_offset());
3870 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3871 int scan_step = itableOffsetEntry::size() * wordSize;
3872 int vte_size = vtableEntry::size_in_bytes();
3873 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3874 assert(vte_size == wordSize, "else adjust times_vte_scale");
3875
3876 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3877
3878 // Could store the aligned, prescaled offset in the klass.
3879 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3880
3881 if (return_method) {
3882 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3883 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3884 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3885 }
3886
3887 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
3888 // if (scan->interface() == intf) {
3889 // result = (klass + scan->offset() + itable_index);
3890 // }
3891 // }
3892 Label search, found_method;
3893
3894 for (int peel = 1; peel >= 0; peel--) {
3895 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
3896 cmpptr(intf_klass, method_result);
3897
3898 if (peel) {
3899 jccb(Assembler::equal, found_method);
3900 } else {
3901 jccb(Assembler::notEqual, search);
3902 // (invert the test to fall through to found_method...)
3903 }
3904
3905 if (!peel) break;
3906
3907 bind(search);
3908
3909 // Check that the previous entry is non-null. A null entry means that
3910 // the receiver class doesn't implement the interface, and wasn't the
3911 // same as when the caller was compiled.
3912 testptr(method_result, method_result);
3913 jcc(Assembler::zero, L_no_such_interface);
3914 addptr(scan_temp, scan_step);
3915 }
3916
3917 bind(found_method);
3918
3919 if (return_method) {
3920 // Got a hit.
3921 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
3922 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3923 }
3924 }
3925
3926 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
3927 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
3928 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
3929 // The target method is determined by <holder_klass, itable_index>.
3930 // The receiver klass is in recv_klass.
3931 // On success, the result will be in method_result, and execution falls through.
3932 // On failure, execution transfers to the given label.
3933 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
3934 Register holder_klass,
3935 Register resolved_klass,
3936 Register method_result,
3937 Register scan_temp,
3938 Register temp_reg2,
3939 Register receiver,
3940 int itable_index,
3941 Label& L_no_such_interface) {
3942 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
3943 Register temp_itbl_klass = method_result;
3944 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
3945
3946 int vtable_base = in_bytes(Klass::vtable_start_offset());
3947 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3948 int scan_step = itableOffsetEntry::size() * wordSize;
3949 int vte_size = vtableEntry::size_in_bytes();
3950 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
3951 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
3952 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3953 assert(vte_size == wordSize, "adjust times_vte_scale");
3954
3955 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
3956
3957 // temp_itbl_klass = recv_klass.itable[0]
3958 // scan_temp = &recv_klass.itable[0] + step
3959 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3960 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
3961 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
3962 xorptr(temp_reg, temp_reg);
3963
3964 // Initial checks:
3965 // - if (holder_klass != resolved_klass), go to "scan for resolved"
3966 // - if (itable[0] == 0), no such interface
3967 // - if (itable[0] == holder_klass), shortcut to "holder found"
3968 cmpptr(holder_klass, resolved_klass);
3969 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
3970 testptr(temp_itbl_klass, temp_itbl_klass);
3971 jccb(Assembler::zero, L_no_such_interface);
3972 cmpptr(holder_klass, temp_itbl_klass);
3973 jccb(Assembler::equal, L_holder_found);
3974
3975 // Loop: Look for holder_klass record in itable
3976 // do {
3977 // tmp = itable[index];
3978 // index += step;
3979 // if (tmp == holder_klass) {
3980 // goto L_holder_found; // Found!
3981 // }
3982 // } while (tmp != 0);
3983 // goto L_no_such_interface // Not found.
3984 Label L_scan_holder;
3985 bind(L_scan_holder);
3986 movptr(temp_itbl_klass, Address(scan_temp, 0));
3987 addptr(scan_temp, scan_step);
3988 cmpptr(holder_klass, temp_itbl_klass);
3989 jccb(Assembler::equal, L_holder_found);
3990 testptr(temp_itbl_klass, temp_itbl_klass);
3991 jccb(Assembler::notZero, L_scan_holder);
3992
3993 jmpb(L_no_such_interface);
3994
3995 // Loop: Look for resolved_class record in itable
3996 // do {
3997 // tmp = itable[index];
3998 // index += step;
3999 // if (tmp == holder_klass) {
4000 // // Also check if we have met a holder klass
4001 // holder_tmp = itable[index-step-ioffset];
4002 // }
4003 // if (tmp == resolved_klass) {
4004 // goto L_resolved_found; // Found!
4005 // }
4006 // } while (tmp != 0);
4007 // goto L_no_such_interface // Not found.
4008 //
4009 Label L_loop_scan_resolved;
4010 bind(L_loop_scan_resolved);
4011 movptr(temp_itbl_klass, Address(scan_temp, 0));
4012 addptr(scan_temp, scan_step);
4013 bind(L_loop_scan_resolved_entry);
4014 cmpptr(holder_klass, temp_itbl_klass);
4015 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4016 cmpptr(resolved_klass, temp_itbl_klass);
4017 jccb(Assembler::equal, L_resolved_found);
4018 testptr(temp_itbl_klass, temp_itbl_klass);
4019 jccb(Assembler::notZero, L_loop_scan_resolved);
4020
4021 jmpb(L_no_such_interface);
4022
4023 Label L_ready;
4024
4025 // See if we already have a holder klass. If not, go and scan for it.
4026 bind(L_resolved_found);
4027 testptr(temp_reg, temp_reg);
4028 jccb(Assembler::zero, L_scan_holder);
4029 jmpb(L_ready);
4030
4031 bind(L_holder_found);
4032 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4033
4034 // Finally, temp_reg contains holder_klass vtable offset
4035 bind(L_ready);
4036 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4037 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4038 load_klass(scan_temp, receiver, noreg);
4039 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4040 } else {
4041 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4042 }
4043 }
4044
4045
4046 // virtual method calling
4047 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4048 RegisterOrConstant vtable_index,
4049 Register method_result) {
4050 const ByteSize base = Klass::vtable_start_offset();
4051 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4052 Address vtable_entry_addr(recv_klass,
4053 vtable_index, Address::times_ptr,
4054 base + vtableEntry::method_offset());
4055 movptr(method_result, vtable_entry_addr);
4056 }
4057
4058
4059 void MacroAssembler::check_klass_subtype(Register sub_klass,
4060 Register super_klass,
4061 Register temp_reg,
4062 Label& L_success) {
4063 Label L_failure;
4064 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4065 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4066 bind(L_failure);
4067 }
4068
4069
4070 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4071 Register super_klass,
4072 Register temp_reg,
4073 Label* L_success,
4074 Label* L_failure,
4075 Label* L_slow_path,
4076 RegisterOrConstant super_check_offset) {
4077 assert_different_registers(sub_klass, super_klass, temp_reg);
4078 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4079 if (super_check_offset.is_register()) {
4080 assert_different_registers(sub_klass, super_klass,
4081 super_check_offset.as_register());
4082 } else if (must_load_sco) {
4083 assert(temp_reg != noreg, "supply either a temp or a register offset");
4084 }
4085
4086 Label L_fallthrough;
4087 int label_nulls = 0;
4088 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4089 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4090 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4091 assert(label_nulls <= 1, "at most one null in the batch");
4092
4093 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4094 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4095 Address super_check_offset_addr(super_klass, sco_offset);
4096
4097 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4098 // range of a jccb. If this routine grows larger, reconsider at
4099 // least some of these.
4100 #define local_jcc(assembler_cond, label) \
4101 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4102 else jcc( assembler_cond, label) /*omit semi*/
4103
4104 // Hacked jmp, which may only be used just before L_fallthrough.
4105 #define final_jmp(label) \
4106 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4107 else jmp(label) /*omit semi*/
4108
4109 // If the pointers are equal, we are done (e.g., String[] elements).
4110 // This self-check enables sharing of secondary supertype arrays among
4111 // non-primary types such as array-of-interface. Otherwise, each such
4112 // type would need its own customized SSA.
4113 // We move this check to the front of the fast path because many
4114 // type checks are in fact trivially successful in this manner,
4115 // so we get a nicely predicted branch right at the start of the check.
4116 cmpptr(sub_klass, super_klass);
4117 local_jcc(Assembler::equal, *L_success);
4118
4119 // Check the supertype display:
4120 if (must_load_sco) {
4121 // Positive movl does right thing on LP64.
4122 movl(temp_reg, super_check_offset_addr);
4123 super_check_offset = RegisterOrConstant(temp_reg);
4124 }
4125 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4126 cmpptr(super_klass, super_check_addr); // load displayed supertype
4127
4128 // This check has worked decisively for primary supers.
4129 // Secondary supers are sought in the super_cache ('super_cache_addr').
4130 // (Secondary supers are interfaces and very deeply nested subtypes.)
4131 // This works in the same check above because of a tricky aliasing
4132 // between the super_cache and the primary super display elements.
4133 // (The 'super_check_addr' can address either, as the case requires.)
4134 // Note that the cache is updated below if it does not help us find
4135 // what we need immediately.
4136 // So if it was a primary super, we can just fail immediately.
4137 // Otherwise, it's the slow path for us (no success at this point).
4138
4139 if (super_check_offset.is_register()) {
4140 local_jcc(Assembler::equal, *L_success);
4141 cmpl(super_check_offset.as_register(), sc_offset);
4142 if (L_failure == &L_fallthrough) {
4143 local_jcc(Assembler::equal, *L_slow_path);
4144 } else {
4145 local_jcc(Assembler::notEqual, *L_failure);
4146 final_jmp(*L_slow_path);
4147 }
4148 } else if (super_check_offset.as_constant() == sc_offset) {
4149 // Need a slow path; fast failure is impossible.
4150 if (L_slow_path == &L_fallthrough) {
4151 local_jcc(Assembler::equal, *L_success);
4152 } else {
4153 local_jcc(Assembler::notEqual, *L_slow_path);
4154 final_jmp(*L_success);
4155 }
4156 } else {
4157 // No slow path; it's a fast decision.
4158 if (L_failure == &L_fallthrough) {
4159 local_jcc(Assembler::equal, *L_success);
4160 } else {
4161 local_jcc(Assembler::notEqual, *L_failure);
4162 final_jmp(*L_success);
4163 }
4164 }
4165
4166 bind(L_fallthrough);
4167
4168 #undef local_jcc
4169 #undef final_jmp
4170 }
4171
4172
4173 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4174 Register super_klass,
4175 Register temp_reg,
4176 Register temp2_reg,
4177 Label* L_success,
4178 Label* L_failure,
4179 bool set_cond_codes) {
4180 assert_different_registers(sub_klass, super_klass, temp_reg);
4181 if (temp2_reg != noreg)
4182 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4183 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4184
4185 Label L_fallthrough;
4186 int label_nulls = 0;
4187 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4188 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4189 assert(label_nulls <= 1, "at most one null in the batch");
4190
4191 // a couple of useful fields in sub_klass:
4192 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4193 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4194 Address secondary_supers_addr(sub_klass, ss_offset);
4195 Address super_cache_addr( sub_klass, sc_offset);
4196
4197 // Do a linear scan of the secondary super-klass chain.
4198 // This code is rarely used, so simplicity is a virtue here.
4199 // The repne_scan instruction uses fixed registers, which we must spill.
4200 // Don't worry too much about pre-existing connections with the input regs.
4201
4202 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4203 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4204
4205 // Get super_klass value into rax (even if it was in rdi or rcx).
4206 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4207 if (super_klass != rax) {
4208 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4209 mov(rax, super_klass);
4210 }
4211 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4212 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4213
4214 #ifndef PRODUCT
4215 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4216 ExternalAddress pst_counter_addr((address) pst_counter);
4217 lea(rcx, pst_counter_addr);
4218 incrementl(Address(rcx, 0));
4219 #endif //PRODUCT
4220
4221 // We will consult the secondary-super array.
4222 movptr(rdi, secondary_supers_addr);
4223 // Load the array length. (Positive movl does right thing on LP64.)
4224 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4225 // Skip to start of data.
4226 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4227
4228 // Scan RCX words at [RDI] for an occurrence of RAX.
4229 // Set NZ/Z based on last compare.
4230 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4231 // not change flags (only scas instruction which is repeated sets flags).
4232 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4233
4234 testptr(rax,rax); // Set Z = 0
4235 repne_scan();
4236
4237 // Unspill the temp. registers:
4238 if (pushed_rdi) pop(rdi);
4239 if (pushed_rcx) pop(rcx);
4240 if (pushed_rax) pop(rax);
4241
4242 if (set_cond_codes) {
4243 // Special hack for the AD files: rdi is guaranteed non-zero.
4244 assert(!pushed_rdi, "rdi must be left non-null");
4245 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4246 }
4247
4248 if (L_failure == &L_fallthrough)
4249 jccb(Assembler::notEqual, *L_failure);
4250 else jcc(Assembler::notEqual, *L_failure);
4251
4252 // Success. Cache the super we found and proceed in triumph.
4253 movptr(super_cache_addr, super_klass);
4254
4255 if (L_success != &L_fallthrough) {
4256 jmp(*L_success);
4257 }
4258
4259 #undef IS_A_TEMP
4260
4261 bind(L_fallthrough);
4262 }
4263
4264 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4265 Register super_klass,
4266 Register temp_reg,
4267 Register temp2_reg,
4268 Label* L_success,
4269 Label* L_failure,
4270 bool set_cond_codes) {
4271 assert(set_cond_codes == false, "must be false on 64-bit x86");
4272 check_klass_subtype_slow_path
4273 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4274 L_success, L_failure);
4275 }
4276
4277 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4278 Register super_klass,
4279 Register temp_reg,
4280 Register temp2_reg,
4281 Register temp3_reg,
4282 Register temp4_reg,
4283 Label* L_success,
4284 Label* L_failure) {
4285 if (UseSecondarySupersTable) {
4286 check_klass_subtype_slow_path_table
4287 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4288 L_success, L_failure);
4289 } else {
4290 check_klass_subtype_slow_path_linear
4291 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4292 }
4293 }
4294
4295 Register MacroAssembler::allocate_if_noreg(Register r,
4296 RegSetIterator<Register> &available_regs,
4297 RegSet ®s_to_push) {
4298 if (!r->is_valid()) {
4299 r = *available_regs++;
4300 regs_to_push += r;
4301 }
4302 return r;
4303 }
4304
4305 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4306 Register super_klass,
4307 Register temp_reg,
4308 Register temp2_reg,
4309 Register temp3_reg,
4310 Register result_reg,
4311 Label* L_success,
4312 Label* L_failure) {
4313 // NB! Callers may assume that, when temp2_reg is a valid register,
4314 // this code sets it to a nonzero value.
4315 bool temp2_reg_was_valid = temp2_reg->is_valid();
4316
4317 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4318
4319 Label L_fallthrough;
4320 int label_nulls = 0;
4321 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4322 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4323 assert(label_nulls <= 1, "at most one null in the batch");
4324
4325 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4326
4327 RegSetIterator<Register> available_regs
4328 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4329
4330 RegSet pushed_regs;
4331
4332 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4333 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4334 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4335 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4336 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4337
4338 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4339
4340 {
4341
4342 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4343 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4344 subptr(rsp, aligned_size);
4345 push_set(pushed_regs, 0);
4346
4347 lookup_secondary_supers_table_var(sub_klass,
4348 super_klass,
4349 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4350 cmpq(result_reg, 0);
4351
4352 // Unspill the temp. registers:
4353 pop_set(pushed_regs, 0);
4354 // Increment SP but do not clobber flags.
4355 lea(rsp, Address(rsp, aligned_size));
4356 }
4357
4358 if (temp2_reg_was_valid) {
4359 movq(temp2_reg, 1);
4360 }
4361
4362 jcc(Assembler::notEqual, *L_failure);
4363
4364 if (L_success != &L_fallthrough) {
4365 jmp(*L_success);
4366 }
4367
4368 bind(L_fallthrough);
4369 }
4370
4371 // population_count variant for running without the POPCNT
4372 // instruction, which was introduced with SSE4.2 in 2008.
4373 void MacroAssembler::population_count(Register dst, Register src,
4374 Register scratch1, Register scratch2) {
4375 assert_different_registers(src, scratch1, scratch2);
4376 if (UsePopCountInstruction) {
4377 Assembler::popcntq(dst, src);
4378 } else {
4379 assert_different_registers(src, scratch1, scratch2);
4380 assert_different_registers(dst, scratch1, scratch2);
4381 Label loop, done;
4382
4383 mov(scratch1, src);
4384 // dst = 0;
4385 // while(scratch1 != 0) {
4386 // dst++;
4387 // scratch1 &= (scratch1 - 1);
4388 // }
4389 xorl(dst, dst);
4390 testq(scratch1, scratch1);
4391 jccb(Assembler::equal, done);
4392 {
4393 bind(loop);
4394 incq(dst);
4395 movq(scratch2, scratch1);
4396 decq(scratch2);
4397 andq(scratch1, scratch2);
4398 jccb(Assembler::notEqual, loop);
4399 }
4400 bind(done);
4401 }
4402 #ifdef ASSERT
4403 mov64(scratch1, 0xCafeBabeDeadBeef);
4404 movq(scratch2, scratch1);
4405 #endif
4406 }
4407
4408 // Ensure that the inline code and the stub are using the same registers.
4409 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4410 do { \
4411 assert(r_super_klass == rax, "mismatch"); \
4412 assert(r_array_base == rbx, "mismatch"); \
4413 assert(r_array_length == rcx, "mismatch"); \
4414 assert(r_array_index == rdx, "mismatch"); \
4415 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4416 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4417 assert(result == rdi || result == noreg, "mismatch"); \
4418 } while(0)
4419
4420 // Versions of salq and rorq that don't need count to be in rcx
4421
4422 void MacroAssembler::salq(Register dest, Register count) {
4423 if (count == rcx) {
4424 Assembler::salq(dest);
4425 } else {
4426 assert_different_registers(rcx, dest);
4427 xchgq(rcx, count);
4428 Assembler::salq(dest);
4429 xchgq(rcx, count);
4430 }
4431 }
4432
4433 void MacroAssembler::rorq(Register dest, Register count) {
4434 if (count == rcx) {
4435 Assembler::rorq(dest);
4436 } else {
4437 assert_different_registers(rcx, dest);
4438 xchgq(rcx, count);
4439 Assembler::rorq(dest);
4440 xchgq(rcx, count);
4441 }
4442 }
4443
4444 // Return true: we succeeded in generating this code
4445 //
4446 // At runtime, return 0 in result if r_super_klass is a superclass of
4447 // r_sub_klass, otherwise return nonzero. Use this if you know the
4448 // super_klass_slot of the class you're looking for. This is always
4449 // the case for instanceof and checkcast.
4450 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4451 Register r_super_klass,
4452 Register temp1,
4453 Register temp2,
4454 Register temp3,
4455 Register temp4,
4456 Register result,
4457 u1 super_klass_slot) {
4458 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4459
4460 Label L_fallthrough, L_success, L_failure;
4461
4462 BLOCK_COMMENT("lookup_secondary_supers_table {");
4463
4464 const Register
4465 r_array_index = temp1,
4466 r_array_length = temp2,
4467 r_array_base = temp3,
4468 r_bitmap = temp4;
4469
4470 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4471
4472 xorq(result, result); // = 0
4473
4474 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4475 movq(r_array_index, r_bitmap);
4476
4477 // First check the bitmap to see if super_klass might be present. If
4478 // the bit is zero, we are certain that super_klass is not one of
4479 // the secondary supers.
4480 u1 bit = super_klass_slot;
4481 {
4482 // NB: If the count in a x86 shift instruction is 0, the flags are
4483 // not affected, so we do a testq instead.
4484 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4485 if (shift_count != 0) {
4486 salq(r_array_index, shift_count);
4487 } else {
4488 testq(r_array_index, r_array_index);
4489 }
4490 }
4491 // We test the MSB of r_array_index, i.e. its sign bit
4492 jcc(Assembler::positive, L_failure);
4493
4494 // Get the first array index that can contain super_klass into r_array_index.
4495 if (bit != 0) {
4496 population_count(r_array_index, r_array_index, temp2, temp3);
4497 } else {
4498 movl(r_array_index, 1);
4499 }
4500 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4501
4502 // We will consult the secondary-super array.
4503 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4504
4505 // We're asserting that the first word in an Array<Klass*> is the
4506 // length, and the second word is the first word of the data. If
4507 // that ever changes, r_array_base will have to be adjusted here.
4508 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4509 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4510
4511 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4512 jccb(Assembler::equal, L_success);
4513
4514 // Is there another entry to check? Consult the bitmap.
4515 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4516 jccb(Assembler::carryClear, L_failure);
4517
4518 // Linear probe. Rotate the bitmap so that the next bit to test is
4519 // in Bit 1.
4520 if (bit != 0) {
4521 rorq(r_bitmap, bit);
4522 }
4523
4524 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4525 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4526 // Kills: r_array_length.
4527 // Returns: result.
4528 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4529 // Result (0/1) is in rdi
4530 jmpb(L_fallthrough);
4531
4532 bind(L_failure);
4533 incq(result); // 0 => 1
4534
4535 bind(L_success);
4536 // result = 0;
4537
4538 bind(L_fallthrough);
4539 BLOCK_COMMENT("} lookup_secondary_supers_table");
4540
4541 if (VerifySecondarySupers) {
4542 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4543 temp1, temp2, temp3);
4544 }
4545 }
4546
4547 // At runtime, return 0 in result if r_super_klass is a superclass of
4548 // r_sub_klass, otherwise return nonzero. Use this version of
4549 // lookup_secondary_supers_table() if you don't know ahead of time
4550 // which superclass will be searched for. Used by interpreter and
4551 // runtime stubs. It is larger and has somewhat greater latency than
4552 // the version above, which takes a constant super_klass_slot.
4553 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
4554 Register r_super_klass,
4555 Register temp1,
4556 Register temp2,
4557 Register temp3,
4558 Register temp4,
4559 Register result) {
4560 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4561 assert_different_registers(r_sub_klass, r_super_klass, rcx);
4562 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
4563
4564 Label L_fallthrough, L_success, L_failure;
4565
4566 BLOCK_COMMENT("lookup_secondary_supers_table {");
4567
4568 RegSetIterator<Register> available_regs = (temps - rcx).begin();
4569
4570 // FIXME. Once we are sure that all paths reaching this point really
4571 // do pass rcx as one of our temps we can get rid of the following
4572 // workaround.
4573 assert(temps.contains(rcx), "fix this code");
4574
4575 // We prefer to have our shift count in rcx. If rcx is one of our
4576 // temps, use it for slot. If not, pick any of our temps.
4577 Register slot;
4578 if (!temps.contains(rcx)) {
4579 slot = *available_regs++;
4580 } else {
4581 slot = rcx;
4582 }
4583
4584 const Register r_array_index = *available_regs++;
4585 const Register r_bitmap = *available_regs++;
4586
4587 // The logic above guarantees this property, but we state it here.
4588 assert_different_registers(r_array_index, r_bitmap, rcx);
4589
4590 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4591 movq(r_array_index, r_bitmap);
4592
4593 // First check the bitmap to see if super_klass might be present. If
4594 // the bit is zero, we are certain that super_klass is not one of
4595 // the secondary supers.
4596 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4597 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
4598 salq(r_array_index, slot);
4599
4600 testq(r_array_index, r_array_index);
4601 // We test the MSB of r_array_index, i.e. its sign bit
4602 jcc(Assembler::positive, L_failure);
4603
4604 const Register r_array_base = *available_regs++;
4605
4606 // Get the first array index that can contain super_klass into r_array_index.
4607 // Note: Clobbers r_array_base and slot.
4608 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
4609
4610 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4611
4612 // We will consult the secondary-super array.
4613 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4614
4615 // We're asserting that the first word in an Array<Klass*> is the
4616 // length, and the second word is the first word of the data. If
4617 // that ever changes, r_array_base will have to be adjusted here.
4618 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4619 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4620
4621 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4622 jccb(Assembler::equal, L_success);
4623
4624 // Restore slot to its true value
4625 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4626
4627 // Linear probe. Rotate the bitmap so that the next bit to test is
4628 // in Bit 1.
4629 rorq(r_bitmap, slot);
4630
4631 // Is there another entry to check? Consult the bitmap.
4632 btq(r_bitmap, 1);
4633 jccb(Assembler::carryClear, L_failure);
4634
4635 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4636 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4637 // Kills: r_array_length.
4638 // Returns: result.
4639 lookup_secondary_supers_table_slow_path(r_super_klass,
4640 r_array_base,
4641 r_array_index,
4642 r_bitmap,
4643 /*temp1*/result,
4644 /*temp2*/slot,
4645 &L_success,
4646 nullptr);
4647
4648 bind(L_failure);
4649 movq(result, 1);
4650 jmpb(L_fallthrough);
4651
4652 bind(L_success);
4653 xorq(result, result); // = 0
4654
4655 bind(L_fallthrough);
4656 BLOCK_COMMENT("} lookup_secondary_supers_table");
4657
4658 if (VerifySecondarySupers) {
4659 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4660 temp1, temp2, temp3);
4661 }
4662 }
4663
4664 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4665 Label* L_success, Label* L_failure) {
4666 Label L_loop, L_fallthrough;
4667 {
4668 int label_nulls = 0;
4669 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4670 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4671 assert(label_nulls <= 1, "at most one null in the batch");
4672 }
4673 bind(L_loop);
4674 cmpq(value, Address(addr, count, Address::times_8));
4675 jcc(Assembler::equal, *L_success);
4676 addl(count, 1);
4677 cmpl(count, limit);
4678 jcc(Assembler::less, L_loop);
4679
4680 if (&L_fallthrough != L_failure) {
4681 jmp(*L_failure);
4682 }
4683 bind(L_fallthrough);
4684 }
4685
4686 // Called by code generated by check_klass_subtype_slow_path
4687 // above. This is called when there is a collision in the hashed
4688 // lookup in the secondary supers array.
4689 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4690 Register r_array_base,
4691 Register r_array_index,
4692 Register r_bitmap,
4693 Register temp1,
4694 Register temp2,
4695 Label* L_success,
4696 Label* L_failure) {
4697 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4698
4699 const Register
4700 r_array_length = temp1,
4701 r_sub_klass = noreg,
4702 result = noreg;
4703
4704 Label L_fallthrough;
4705 int label_nulls = 0;
4706 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4707 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4708 assert(label_nulls <= 1, "at most one null in the batch");
4709
4710 // Load the array length.
4711 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4712 // And adjust the array base to point to the data.
4713 // NB! Effectively increments current slot index by 1.
4714 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4715 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4716
4717 // Linear probe
4718 Label L_huge;
4719
4720 // The bitmap is full to bursting.
4721 // Implicit invariant: BITMAP_FULL implies (length > 0)
4722 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
4723 jcc(Assembler::greater, L_huge);
4724
4725 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4726 // current slot (at secondary_supers[r_array_index]) has not yet
4727 // been inspected, and r_array_index may be out of bounds if we
4728 // wrapped around the end of the array.
4729
4730 { // This is conventional linear probing, but instead of terminating
4731 // when a null entry is found in the table, we maintain a bitmap
4732 // in which a 0 indicates missing entries.
4733 // The check above guarantees there are 0s in the bitmap, so the loop
4734 // eventually terminates.
4735
4736 xorl(temp2, temp2); // = 0;
4737
4738 Label L_again;
4739 bind(L_again);
4740
4741 // Check for array wraparound.
4742 cmpl(r_array_index, r_array_length);
4743 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4744
4745 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4746 jcc(Assembler::equal, *L_success);
4747
4748 // If the next bit in bitmap is zero, we're done.
4749 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4750 jcc(Assembler::carryClear, *L_failure);
4751
4752 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4753 addl(r_array_index, 1);
4754
4755 jmp(L_again);
4756 }
4757
4758 { // Degenerate case: more than 64 secondary supers.
4759 // FIXME: We could do something smarter here, maybe a vectorized
4760 // comparison or a binary search, but is that worth any added
4761 // complexity?
4762 bind(L_huge);
4763 xorl(r_array_index, r_array_index); // = 0
4764 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4765 L_success,
4766 (&L_fallthrough != L_failure ? L_failure : nullptr));
4767
4768 bind(L_fallthrough);
4769 }
4770 }
4771
4772 struct VerifyHelperArguments {
4773 Klass* _super;
4774 Klass* _sub;
4775 intptr_t _linear_result;
4776 intptr_t _table_result;
4777 };
4778
4779 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
4780 Klass::on_secondary_supers_verification_failure(args->_super,
4781 args->_sub,
4782 args->_linear_result,
4783 args->_table_result,
4784 msg);
4785 }
4786
4787 // Make sure that the hashed lookup and a linear scan agree.
4788 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
4789 Register r_super_klass,
4790 Register result,
4791 Register temp1,
4792 Register temp2,
4793 Register temp3) {
4794 const Register
4795 r_array_index = temp1,
4796 r_array_length = temp2,
4797 r_array_base = temp3,
4798 r_bitmap = noreg;
4799
4800 BLOCK_COMMENT("verify_secondary_supers_table {");
4801
4802 Label L_success, L_failure, L_check, L_done;
4803
4804 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4805 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4806 // And adjust the array base to point to the data.
4807 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4808
4809 testl(r_array_length, r_array_length); // array_length == 0?
4810 jcc(Assembler::zero, L_failure);
4811
4812 movl(r_array_index, 0);
4813 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
4814 // fall through to L_failure
4815
4816 const Register linear_result = r_array_index; // reuse temp1
4817
4818 bind(L_failure); // not present
4819 movl(linear_result, 1);
4820 jmp(L_check);
4821
4822 bind(L_success); // present
4823 movl(linear_result, 0);
4824
4825 bind(L_check);
4826 cmpl(linear_result, result);
4827 jcc(Assembler::equal, L_done);
4828
4829 { // To avoid calling convention issues, build a record on the stack
4830 // and pass the pointer to that instead.
4831 push(result);
4832 push(linear_result);
4833 push(r_sub_klass);
4834 push(r_super_klass);
4835 movptr(c_rarg1, rsp);
4836 movptr(c_rarg0, (uintptr_t) "mismatch");
4837 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
4838 should_not_reach_here();
4839 }
4840 bind(L_done);
4841
4842 BLOCK_COMMENT("} verify_secondary_supers_table");
4843 }
4844
4845 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
4846
4847 void MacroAssembler::clinit_barrier(Register klass, Label* L_fast_path, Label* L_slow_path) {
4848 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
4849
4850 Label L_fallthrough;
4851 if (L_fast_path == nullptr) {
4852 L_fast_path = &L_fallthrough;
4853 } else if (L_slow_path == nullptr) {
4854 L_slow_path = &L_fallthrough;
4855 }
4856
4857 // Fast path check: class is fully initialized.
4858 // init_state needs acquire, but x86 is TSO, and so we are already good.
4859 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4860 jcc(Assembler::equal, *L_fast_path);
4861
4862 // Fast path check: current thread is initializer thread
4863 cmpptr(r15_thread, Address(klass, InstanceKlass::init_thread_offset()));
4864 if (L_slow_path == &L_fallthrough) {
4865 jcc(Assembler::equal, *L_fast_path);
4866 bind(*L_slow_path);
4867 } else if (L_fast_path == &L_fallthrough) {
4868 jcc(Assembler::notEqual, *L_slow_path);
4869 bind(*L_fast_path);
4870 } else {
4871 Unimplemented();
4872 }
4873 }
4874
4875 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4876 if (VM_Version::supports_cmov()) {
4877 cmovl(cc, dst, src);
4878 } else {
4879 Label L;
4880 jccb(negate_condition(cc), L);
4881 movl(dst, src);
4882 bind(L);
4883 }
4884 }
4885
4886 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4887 if (VM_Version::supports_cmov()) {
4888 cmovl(cc, dst, src);
4889 } else {
4890 Label L;
4891 jccb(negate_condition(cc), L);
4892 movl(dst, src);
4893 bind(L);
4894 }
4895 }
4896
4897 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4898 if (!VerifyOops || VerifyAdapterSharing) {
4899 // Below address of the code string confuses VerifyAdapterSharing
4900 // because it may differ between otherwise equivalent adapters.
4901 return;
4902 }
4903
4904 BLOCK_COMMENT("verify_oop {");
4905 push(rscratch1);
4906 push(rax); // save rax
4907 push(reg); // pass register argument
4908
4909 // Pass register number to verify_oop_subroutine
4910 const char* b = nullptr;
4911 {
4912 ResourceMark rm;
4913 stringStream ss;
4914 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4915 b = code_string(ss.as_string());
4916 }
4917 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
4918 pushptr(buffer.addr(), rscratch1);
4919
4920 // call indirectly to solve generation ordering problem
4921 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4922 call(rax);
4923 // Caller pops the arguments (oop, message) and restores rax, r10
4924 BLOCK_COMMENT("} verify_oop");
4925 }
4926
4927 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4928 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4929 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
4930 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
4931 vpternlogd(dst, 0xFF, dst, dst, vector_len);
4932 } else if (VM_Version::supports_avx()) {
4933 vpcmpeqd(dst, dst, dst, vector_len);
4934 } else {
4935 pcmpeqd(dst, dst);
4936 }
4937 }
4938
4939 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4940 int extra_slot_offset) {
4941 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4942 int stackElementSize = Interpreter::stackElementSize;
4943 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4944 #ifdef ASSERT
4945 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4946 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4947 #endif
4948 Register scale_reg = noreg;
4949 Address::ScaleFactor scale_factor = Address::no_scale;
4950 if (arg_slot.is_constant()) {
4951 offset += arg_slot.as_constant() * stackElementSize;
4952 } else {
4953 scale_reg = arg_slot.as_register();
4954 scale_factor = Address::times(stackElementSize);
4955 }
4956 offset += wordSize; // return PC is on stack
4957 return Address(rsp, scale_reg, scale_factor, offset);
4958 }
4959
4960 // Handle the receiver type profile update given the "recv" klass.
4961 //
4962 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
4963 // If there are no matching or claimable receiver entries in RD, updates
4964 // the polymorphic counter.
4965 //
4966 // This code expected to run by either the interpreter or JIT-ed code, without
4967 // extra synchronization. For safety, receiver cells are claimed atomically, which
4968 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
4969 // counter updates are not atomic.
4970 //
4971 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
4972 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
4973 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
4974 int poly_count_offset = in_bytes(CounterData::count_offset());
4975 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
4976 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
4977
4978 // Adjust for MDP offsets. Slots are pointer-sized, so is the global offset.
4979 assert(is_aligned(mdp_offset, BytesPerWord), "sanity");
4980 base_receiver_offset += mdp_offset;
4981 end_receiver_offset += mdp_offset;
4982 poly_count_offset += mdp_offset;
4983
4984 // Scale down to optimize encoding. Slots are pointer-sized.
4985 assert(is_aligned(base_receiver_offset, BytesPerWord), "sanity");
4986 assert(is_aligned(end_receiver_offset, BytesPerWord), "sanity");
4987 assert(is_aligned(poly_count_offset, BytesPerWord), "sanity");
4988 assert(is_aligned(receiver_step, BytesPerWord), "sanity");
4989 assert(is_aligned(receiver_to_count_step, BytesPerWord), "sanity");
4990 base_receiver_offset >>= LogBytesPerWord;
4991 end_receiver_offset >>= LogBytesPerWord;
4992 poly_count_offset >>= LogBytesPerWord;
4993 receiver_step >>= LogBytesPerWord;
4994 receiver_to_count_step >>= LogBytesPerWord;
4995
4996 #ifdef ASSERT
4997 // We are about to walk the MDO slots without asking for offsets.
4998 // Check that our math hits all the right spots.
4999 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
5000 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
5001 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
5002 int offset = base_receiver_offset + receiver_step*c;
5003 int count_offset = offset + receiver_to_count_step;
5004 assert((offset << LogBytesPerWord) == real_recv_offset, "receiver slot math");
5005 assert((count_offset << LogBytesPerWord) == real_count_offset, "receiver count math");
5006 }
5007 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
5008 assert(poly_count_offset << LogBytesPerWord == real_poly_count_offset, "poly counter math");
5009 #endif
5010
5011 // Corner case: no profile table. Increment poly counter and exit.
5012 if (ReceiverTypeData::row_limit() == 0) {
5013 addptr(Address(mdp, poly_count_offset, Address::times_ptr), DataLayout::counter_increment);
5014 return;
5015 }
5016
5017 Register offset = rscratch1;
5018
5019 Label L_loop_search_receiver, L_loop_search_empty;
5020 Label L_restart, L_found_recv, L_found_empty, L_count_update;
5021
5022 // The code here recognizes three major cases:
5023 // A. Fastest: receiver found in the table
5024 // B. Fast: no receiver in the table, and the table is full
5025 // C. Slow: no receiver in the table, free slots in the table
5026 //
5027 // The case A performance is most important, as perfectly-behaved code would end up
5028 // there, especially with larger TypeProfileWidth. The case B performance is
5029 // important as well, this is where bulk of code would land for normally megamorphic
5030 // cases. The case C performance is not essential, its job is to deal with installation
5031 // races, we optimize for code density instead. Case C needs to make sure that receiver
5032 // rows are only claimed once. This makes sure we never overwrite a row for another
5033 // receiver and never duplicate the receivers in the list, making profile type-accurate.
5034 //
5035 // It is very tempting to handle these cases in a single loop, and claim the first slot
5036 // without checking the rest of the table. But, profiling code should tolerate free slots
5037 // in the table, as class unloading can clear them. After such cleanup, the receiver
5038 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
5039 // to complete, before trying to install new slots. Splitting the code in several tight
5040 // loops also helpfully optimizes for cases A and B.
5041 //
5042 // This code is effectively:
5043 //
5044 // restart:
5045 // // Fastest: receiver is already installed
5046 // for (i = 0; i < receiver_count(); i++) {
5047 // if (receiver(i) == recv) goto found_recv(i);
5048 // }
5049 //
5050 // // Fast: no receiver, but profile is not full
5051 // for (i = 0; i < receiver_count(); i++) {
5052 // if (receiver(i) == null) goto found_null(i);
5053 // }
5054 //
5055 // // Slow: profile is full, polymorphic case
5056 // count++;
5057 // return
5058 //
5059 // // Slow: try to install receiver
5060 // found_null(i):
5061 // CAS(&receiver(i), null, recv);
5062 // goto restart
5063 //
5064 // found_recv(i):
5065 // *receiver_count(i)++
5066 //
5067
5068 bind(L_restart);
5069
5070 // Fastest: receiver is already installed
5071 movptr(offset, base_receiver_offset);
5072 bind(L_loop_search_receiver);
5073 cmpptr(recv, Address(mdp, offset, Address::times_ptr));
5074 jccb(Assembler::equal, L_found_recv);
5075 addptr(offset, receiver_step);
5076 cmpptr(offset, end_receiver_offset);
5077 jccb(Assembler::notEqual, L_loop_search_receiver);
5078
5079 // Fast: no receiver, but profile is not full
5080 movptr(offset, base_receiver_offset);
5081 bind(L_loop_search_empty);
5082 cmpptr(Address(mdp, offset, Address::times_ptr), NULL_WORD);
5083 jccb(Assembler::equal, L_found_empty);
5084 addptr(offset, receiver_step);
5085 cmpptr(offset, end_receiver_offset);
5086 jccb(Assembler::notEqual, L_loop_search_empty);
5087
5088 // Slow: Receiver is not found and table is full.
5089 // Increment polymorphic counter instead of receiver slot.
5090 movptr(offset, poly_count_offset);
5091 jmpb(L_count_update);
5092
5093 // Slowest: try to install receiver
5094 bind(L_found_empty);
5095
5096 // Atomically swing receiver slot: null -> recv.
5097 //
5098 // The update code uses CAS, which wants RAX register specifically, *and* it needs
5099 // other important registers untouched, as they form the address. Therefore, we need
5100 // to shift any important registers from RAX into some other spare register. If we
5101 // have a spare register, we are forced to save it on stack here.
5102
5103 Register spare_reg = noreg;
5104 Register shifted_mdp = mdp;
5105 Register shifted_recv = recv;
5106 if (recv == rax || mdp == rax) {
5107 spare_reg = (recv != rbx && mdp != rbx) ? rbx :
5108 (recv != rcx && mdp != rcx) ? rcx :
5109 rdx;
5110 assert_different_registers(mdp, recv, offset, spare_reg);
5111
5112 push(spare_reg);
5113 if (recv == rax) {
5114 movptr(spare_reg, recv);
5115 shifted_recv = spare_reg;
5116 } else {
5117 assert(mdp == rax, "Remaining case");
5118 movptr(spare_reg, mdp);
5119 shifted_mdp = spare_reg;
5120 }
5121 } else {
5122 push(rax);
5123 }
5124
5125 // None of the important registers are in RAX after this shuffle.
5126 assert_different_registers(rax, shifted_mdp, shifted_recv, offset);
5127
5128 xorptr(rax, rax);
5129 cmpxchgptr(shifted_recv, Address(shifted_mdp, offset, Address::times_ptr));
5130
5131 // Unshift registers.
5132 if (recv == rax || mdp == rax) {
5133 movptr(rax, spare_reg);
5134 pop(spare_reg);
5135 } else {
5136 pop(rax);
5137 }
5138
5139 // CAS success means the slot now has the receiver we want. CAS failure means
5140 // something had claimed the slot concurrently: it can be the same receiver we want,
5141 // or something else. Since this is a slow path, we can optimize for code density,
5142 // and just restart the search from the beginning.
5143 jmpb(L_restart);
5144
5145 // Found a receiver, convert its slot offset to corresponding count offset.
5146 bind(L_found_recv);
5147 addptr(offset, receiver_to_count_step);
5148
5149 // Finally, update the counter
5150 bind(L_count_update);
5151 addptr(Address(mdp, offset, Address::times_ptr), DataLayout::counter_increment);
5152 }
5153
5154 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5155 if (!VerifyOops || VerifyAdapterSharing) {
5156 // Below address of the code string confuses VerifyAdapterSharing
5157 // because it may differ between otherwise equivalent adapters.
5158 return;
5159 }
5160
5161 push(rscratch1);
5162 push(rax); // save rax,
5163 // addr may contain rsp so we will have to adjust it based on the push
5164 // we just did (and on 64 bit we do two pushes)
5165 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5166 // stores rax into addr which is backwards of what was intended.
5167 if (addr.uses(rsp)) {
5168 lea(rax, addr);
5169 pushptr(Address(rax, 2 * BytesPerWord));
5170 } else {
5171 pushptr(addr);
5172 }
5173
5174 // Pass register number to verify_oop_subroutine
5175 const char* b = nullptr;
5176 {
5177 ResourceMark rm;
5178 stringStream ss;
5179 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5180 b = code_string(ss.as_string());
5181 }
5182 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5183 pushptr(buffer.addr(), rscratch1);
5184
5185 // call indirectly to solve generation ordering problem
5186 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5187 call(rax);
5188 // Caller pops the arguments (addr, message) and restores rax, r10.
5189 }
5190
5191 void MacroAssembler::verify_tlab() {
5192 #ifdef ASSERT
5193 if (UseTLAB && VerifyOops) {
5194 Label next, ok;
5195 Register t1 = rsi;
5196
5197 push(t1);
5198
5199 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5200 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
5201 jcc(Assembler::aboveEqual, next);
5202 STOP("assert(top >= start)");
5203 should_not_reach_here();
5204
5205 bind(next);
5206 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
5207 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5208 jcc(Assembler::aboveEqual, ok);
5209 STOP("assert(top <= end)");
5210 should_not_reach_here();
5211
5212 bind(ok);
5213 pop(t1);
5214 }
5215 #endif
5216 }
5217
5218 class ControlWord {
5219 public:
5220 int32_t _value;
5221
5222 int rounding_control() const { return (_value >> 10) & 3 ; }
5223 int precision_control() const { return (_value >> 8) & 3 ; }
5224 bool precision() const { return ((_value >> 5) & 1) != 0; }
5225 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5226 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5227 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5228 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5229 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5230
5231 void print() const {
5232 // rounding control
5233 const char* rc;
5234 switch (rounding_control()) {
5235 case 0: rc = "round near"; break;
5236 case 1: rc = "round down"; break;
5237 case 2: rc = "round up "; break;
5238 case 3: rc = "chop "; break;
5239 default:
5240 rc = nullptr; // silence compiler warnings
5241 fatal("Unknown rounding control: %d", rounding_control());
5242 };
5243 // precision control
5244 const char* pc;
5245 switch (precision_control()) {
5246 case 0: pc = "24 bits "; break;
5247 case 1: pc = "reserved"; break;
5248 case 2: pc = "53 bits "; break;
5249 case 3: pc = "64 bits "; break;
5250 default:
5251 pc = nullptr; // silence compiler warnings
5252 fatal("Unknown precision control: %d", precision_control());
5253 };
5254 // flags
5255 char f[9];
5256 f[0] = ' ';
5257 f[1] = ' ';
5258 f[2] = (precision ()) ? 'P' : 'p';
5259 f[3] = (underflow ()) ? 'U' : 'u';
5260 f[4] = (overflow ()) ? 'O' : 'o';
5261 f[5] = (zero_divide ()) ? 'Z' : 'z';
5262 f[6] = (denormalized()) ? 'D' : 'd';
5263 f[7] = (invalid ()) ? 'I' : 'i';
5264 f[8] = '\x0';
5265 // output
5266 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5267 }
5268
5269 };
5270
5271 class StatusWord {
5272 public:
5273 int32_t _value;
5274
5275 bool busy() const { return ((_value >> 15) & 1) != 0; }
5276 bool C3() const { return ((_value >> 14) & 1) != 0; }
5277 bool C2() const { return ((_value >> 10) & 1) != 0; }
5278 bool C1() const { return ((_value >> 9) & 1) != 0; }
5279 bool C0() const { return ((_value >> 8) & 1) != 0; }
5280 int top() const { return (_value >> 11) & 7 ; }
5281 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5282 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5283 bool precision() const { return ((_value >> 5) & 1) != 0; }
5284 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5285 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5286 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5287 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5288 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5289
5290 void print() const {
5291 // condition codes
5292 char c[5];
5293 c[0] = (C3()) ? '3' : '-';
5294 c[1] = (C2()) ? '2' : '-';
5295 c[2] = (C1()) ? '1' : '-';
5296 c[3] = (C0()) ? '0' : '-';
5297 c[4] = '\x0';
5298 // flags
5299 char f[9];
5300 f[0] = (error_status()) ? 'E' : '-';
5301 f[1] = (stack_fault ()) ? 'S' : '-';
5302 f[2] = (precision ()) ? 'P' : '-';
5303 f[3] = (underflow ()) ? 'U' : '-';
5304 f[4] = (overflow ()) ? 'O' : '-';
5305 f[5] = (zero_divide ()) ? 'Z' : '-';
5306 f[6] = (denormalized()) ? 'D' : '-';
5307 f[7] = (invalid ()) ? 'I' : '-';
5308 f[8] = '\x0';
5309 // output
5310 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5311 }
5312
5313 };
5314
5315 class TagWord {
5316 public:
5317 int32_t _value;
5318
5319 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5320
5321 void print() const {
5322 printf("%04x", _value & 0xFFFF);
5323 }
5324
5325 };
5326
5327 class FPU_Register {
5328 public:
5329 int32_t _m0;
5330 int32_t _m1;
5331 int16_t _ex;
5332
5333 bool is_indefinite() const {
5334 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5335 }
5336
5337 void print() const {
5338 char sign = (_ex < 0) ? '-' : '+';
5339 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5340 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5341 };
5342
5343 };
5344
5345 class FPU_State {
5346 public:
5347 enum {
5348 register_size = 10,
5349 number_of_registers = 8,
5350 register_mask = 7
5351 };
5352
5353 ControlWord _control_word;
5354 StatusWord _status_word;
5355 TagWord _tag_word;
5356 int32_t _error_offset;
5357 int32_t _error_selector;
5358 int32_t _data_offset;
5359 int32_t _data_selector;
5360 int8_t _register[register_size * number_of_registers];
5361
5362 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5363 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5364
5365 const char* tag_as_string(int tag) const {
5366 switch (tag) {
5367 case 0: return "valid";
5368 case 1: return "zero";
5369 case 2: return "special";
5370 case 3: return "empty";
5371 }
5372 ShouldNotReachHere();
5373 return nullptr;
5374 }
5375
5376 void print() const {
5377 // print computation registers
5378 { int t = _status_word.top();
5379 for (int i = 0; i < number_of_registers; i++) {
5380 int j = (i - t) & register_mask;
5381 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5382 st(j)->print();
5383 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5384 }
5385 }
5386 printf("\n");
5387 // print control registers
5388 printf("ctrl = "); _control_word.print(); printf("\n");
5389 printf("stat = "); _status_word .print(); printf("\n");
5390 printf("tags = "); _tag_word .print(); printf("\n");
5391 }
5392
5393 };
5394
5395 class Flag_Register {
5396 public:
5397 int32_t _value;
5398
5399 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5400 bool direction() const { return ((_value >> 10) & 1) != 0; }
5401 bool sign() const { return ((_value >> 7) & 1) != 0; }
5402 bool zero() const { return ((_value >> 6) & 1) != 0; }
5403 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5404 bool parity() const { return ((_value >> 2) & 1) != 0; }
5405 bool carry() const { return ((_value >> 0) & 1) != 0; }
5406
5407 void print() const {
5408 // flags
5409 char f[8];
5410 f[0] = (overflow ()) ? 'O' : '-';
5411 f[1] = (direction ()) ? 'D' : '-';
5412 f[2] = (sign ()) ? 'S' : '-';
5413 f[3] = (zero ()) ? 'Z' : '-';
5414 f[4] = (auxiliary_carry()) ? 'A' : '-';
5415 f[5] = (parity ()) ? 'P' : '-';
5416 f[6] = (carry ()) ? 'C' : '-';
5417 f[7] = '\x0';
5418 // output
5419 printf("%08x flags = %s", _value, f);
5420 }
5421
5422 };
5423
5424 class IU_Register {
5425 public:
5426 int32_t _value;
5427
5428 void print() const {
5429 printf("%08x %11d", _value, _value);
5430 }
5431
5432 };
5433
5434 class IU_State {
5435 public:
5436 Flag_Register _eflags;
5437 IU_Register _rdi;
5438 IU_Register _rsi;
5439 IU_Register _rbp;
5440 IU_Register _rsp;
5441 IU_Register _rbx;
5442 IU_Register _rdx;
5443 IU_Register _rcx;
5444 IU_Register _rax;
5445
5446 void print() const {
5447 // computation registers
5448 printf("rax, = "); _rax.print(); printf("\n");
5449 printf("rbx, = "); _rbx.print(); printf("\n");
5450 printf("rcx = "); _rcx.print(); printf("\n");
5451 printf("rdx = "); _rdx.print(); printf("\n");
5452 printf("rdi = "); _rdi.print(); printf("\n");
5453 printf("rsi = "); _rsi.print(); printf("\n");
5454 printf("rbp, = "); _rbp.print(); printf("\n");
5455 printf("rsp = "); _rsp.print(); printf("\n");
5456 printf("\n");
5457 // control registers
5458 printf("flgs = "); _eflags.print(); printf("\n");
5459 }
5460 };
5461
5462
5463 class CPU_State {
5464 public:
5465 FPU_State _fpu_state;
5466 IU_State _iu_state;
5467
5468 void print() const {
5469 printf("--------------------------------------------------\n");
5470 _iu_state .print();
5471 printf("\n");
5472 _fpu_state.print();
5473 printf("--------------------------------------------------\n");
5474 }
5475
5476 };
5477
5478
5479 static void _print_CPU_state(CPU_State* state) {
5480 state->print();
5481 };
5482
5483
5484 void MacroAssembler::print_CPU_state() {
5485 push_CPU_state();
5486 push(rsp); // pass CPU state
5487 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5488 addptr(rsp, wordSize); // discard argument
5489 pop_CPU_state();
5490 }
5491
5492 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5493 // Either restore the MXCSR register after returning from the JNI Call
5494 // or verify that it wasn't changed (with -Xcheck:jni flag).
5495 if (RestoreMXCSROnJNICalls) {
5496 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5497 } else if (CheckJNICalls) {
5498 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5499 }
5500 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5501 vzeroupper();
5502 }
5503
5504 // ((OopHandle)result).resolve();
5505 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5506 assert_different_registers(result, tmp);
5507
5508 // Only 64 bit platforms support GCs that require a tmp register
5509 // Only IN_HEAP loads require a thread_tmp register
5510 // OopHandle::resolve is an indirection like jobject.
5511 access_load_at(T_OBJECT, IN_NATIVE,
5512 result, Address(result, 0), tmp);
5513 }
5514
5515 // ((WeakHandle)result).resolve();
5516 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5517 assert_different_registers(rresult, rtmp);
5518 Label resolved;
5519
5520 // A null weak handle resolves to null.
5521 cmpptr(rresult, 0);
5522 jcc(Assembler::equal, resolved);
5523
5524 // Only 64 bit platforms support GCs that require a tmp register
5525 // Only IN_HEAP loads require a thread_tmp register
5526 // WeakHandle::resolve is an indirection like jweak.
5527 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5528 rresult, Address(rresult, 0), rtmp);
5529 bind(resolved);
5530 }
5531
5532 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5533 // get mirror
5534 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5535 load_method_holder(mirror, method);
5536 movptr(mirror, Address(mirror, mirror_offset));
5537 resolve_oop_handle(mirror, tmp);
5538 }
5539
5540 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5541 load_method_holder(rresult, rmethod);
5542 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5543 }
5544
5545 void MacroAssembler::load_method_holder(Register holder, Register method) {
5546 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5547 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5548 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5549 }
5550
5551 void MacroAssembler::load_metadata(Register dst, Register src) {
5552 if (UseCompactObjectHeaders) {
5553 load_narrow_klass_compact(dst, src);
5554 } else {
5555 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5556 }
5557 }
5558
5559 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5560 assert(UseCompactObjectHeaders, "expect compact object headers");
5561 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5562 shrq(dst, markWord::klass_shift);
5563 }
5564
5565 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5566 assert_different_registers(src, tmp);
5567 assert_different_registers(dst, tmp);
5568
5569 if (UseCompactObjectHeaders) {
5570 load_narrow_klass_compact(dst, src);
5571 decode_klass_not_null(dst, tmp);
5572 } else {
5573 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5574 decode_klass_not_null(dst, tmp);
5575 }
5576 }
5577
5578 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
5579 load_klass(dst, src, tmp);
5580 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5581 }
5582
5583 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5584 assert(!UseCompactObjectHeaders, "not with compact headers");
5585 assert_different_registers(src, tmp);
5586 assert_different_registers(dst, tmp);
5587 encode_klass_not_null(src, tmp);
5588 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5589 }
5590
5591 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5592 if (UseCompactObjectHeaders) {
5593 assert(tmp != noreg, "need tmp");
5594 assert_different_registers(klass, obj, tmp);
5595 load_narrow_klass_compact(tmp, obj);
5596 cmpl(klass, tmp);
5597 } else {
5598 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5599 }
5600 }
5601
5602 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5603 if (UseCompactObjectHeaders) {
5604 assert(tmp2 != noreg, "need tmp2");
5605 assert_different_registers(obj1, obj2, tmp1, tmp2);
5606 load_narrow_klass_compact(tmp1, obj1);
5607 load_narrow_klass_compact(tmp2, obj2);
5608 cmpl(tmp1, tmp2);
5609 } else {
5610 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5611 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5612 }
5613 }
5614
5615 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5616 Register tmp1) {
5617 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5618 decorators = AccessInternal::decorator_fixup(decorators, type);
5619 bool as_raw = (decorators & AS_RAW) != 0;
5620 if (as_raw) {
5621 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1);
5622 } else {
5623 bs->load_at(this, decorators, type, dst, src, tmp1);
5624 }
5625 }
5626
5627 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5628 Register tmp1, Register tmp2, Register tmp3) {
5629 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5630 decorators = AccessInternal::decorator_fixup(decorators, type);
5631 bool as_raw = (decorators & AS_RAW) != 0;
5632 if (as_raw) {
5633 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5634 } else {
5635 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5636 }
5637 }
5638
5639 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5640 Register inline_layout_info) {
5641 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5642 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5643 }
5644
5645 void MacroAssembler::payload_offset(Register inline_klass, Register offset) {
5646 movptr(offset, Address(inline_klass, InlineKlass::adr_members_offset()));
5647 movl(offset, Address(offset, InlineKlass::payload_offset_offset()));
5648 }
5649
5650 void MacroAssembler::payload_addr(Register oop, Register data, Register inline_klass) {
5651 // ((address) (void*) o) + vk->payload_offset();
5652 Register offset = (data == oop) ? rscratch1 : data;
5653 payload_offset(inline_klass, offset);
5654 if (data == oop) {
5655 addptr(data, offset);
5656 } else {
5657 lea(data, Address(oop, offset));
5658 }
5659 }
5660
5661 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5662 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1);
5663 }
5664
5665 // Doesn't do verification, generates fixed size code
5666 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5667 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1);
5668 }
5669
5670 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5671 Register tmp2, Register tmp3, DecoratorSet decorators) {
5672 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5673 }
5674
5675 // Used for storing nulls.
5676 void MacroAssembler::store_heap_oop_null(Address dst) {
5677 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5678 }
5679
5680 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5681 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5682 // Store to klass gap in destination
5683 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5684 }
5685
5686 #ifdef ASSERT
5687 void MacroAssembler::verify_heapbase(const char* msg) {
5688 assert (UseCompressedOops, "should be compressed");
5689 assert (Universe::heap() != nullptr, "java heap should be initialized");
5690 if (CheckCompressedOops) {
5691 Label ok;
5692 ExternalAddress src2(CompressedOops::base_addr());
5693 const bool is_src2_reachable = reachable(src2);
5694 if (!is_src2_reachable) {
5695 push(rscratch1); // cmpptr trashes rscratch1
5696 }
5697 cmpptr(r12_heapbase, src2, rscratch1);
5698 jcc(Assembler::equal, ok);
5699 STOP(msg);
5700 bind(ok);
5701 if (!is_src2_reachable) {
5702 pop(rscratch1);
5703 }
5704 }
5705 }
5706 #endif
5707
5708 // Algorithm must match oop.inline.hpp encode_heap_oop.
5709 void MacroAssembler::encode_heap_oop(Register r) {
5710 #ifdef ASSERT
5711 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5712 #endif
5713 verify_oop_msg(r, "broken oop in encode_heap_oop");
5714 if (CompressedOops::base() == nullptr) {
5715 if (CompressedOops::shift() != 0) {
5716 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5717 shrq(r, LogMinObjAlignmentInBytes);
5718 }
5719 return;
5720 }
5721 testq(r, r);
5722 cmovq(Assembler::equal, r, r12_heapbase);
5723 subq(r, r12_heapbase);
5724 shrq(r, LogMinObjAlignmentInBytes);
5725 }
5726
5727 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5728 #ifdef ASSERT
5729 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5730 if (CheckCompressedOops) {
5731 Label ok;
5732 testq(r, r);
5733 jcc(Assembler::notEqual, ok);
5734 STOP("null oop passed to encode_heap_oop_not_null");
5735 bind(ok);
5736 }
5737 #endif
5738 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5739 if (CompressedOops::base() != nullptr) {
5740 subq(r, r12_heapbase);
5741 }
5742 if (CompressedOops::shift() != 0) {
5743 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5744 shrq(r, LogMinObjAlignmentInBytes);
5745 }
5746 }
5747
5748 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5749 #ifdef ASSERT
5750 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5751 if (CheckCompressedOops) {
5752 Label ok;
5753 testq(src, src);
5754 jcc(Assembler::notEqual, ok);
5755 STOP("null oop passed to encode_heap_oop_not_null2");
5756 bind(ok);
5757 }
5758 #endif
5759 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5760 if (dst != src) {
5761 movq(dst, src);
5762 }
5763 if (CompressedOops::base() != nullptr) {
5764 subq(dst, r12_heapbase);
5765 }
5766 if (CompressedOops::shift() != 0) {
5767 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5768 shrq(dst, LogMinObjAlignmentInBytes);
5769 }
5770 }
5771
5772 void MacroAssembler::decode_heap_oop(Register r) {
5773 #ifdef ASSERT
5774 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5775 #endif
5776 if (CompressedOops::base() == nullptr) {
5777 if (CompressedOops::shift() != 0) {
5778 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5779 shlq(r, LogMinObjAlignmentInBytes);
5780 }
5781 } else {
5782 Label done;
5783 shlq(r, LogMinObjAlignmentInBytes);
5784 jccb(Assembler::equal, done);
5785 addq(r, r12_heapbase);
5786 bind(done);
5787 }
5788 verify_oop_msg(r, "broken oop in decode_heap_oop");
5789 }
5790
5791 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5792 // Note: it will change flags
5793 assert (UseCompressedOops, "should only be used for compressed headers");
5794 assert (Universe::heap() != nullptr, "java heap should be initialized");
5795 // Cannot assert, unverified entry point counts instructions (see .ad file)
5796 // vtableStubs also counts instructions in pd_code_size_limit.
5797 // Also do not verify_oop as this is called by verify_oop.
5798 if (CompressedOops::shift() != 0) {
5799 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5800 shlq(r, LogMinObjAlignmentInBytes);
5801 if (CompressedOops::base() != nullptr) {
5802 addq(r, r12_heapbase);
5803 }
5804 } else {
5805 assert (CompressedOops::base() == nullptr, "sanity");
5806 }
5807 }
5808
5809 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5810 // Note: it will change flags
5811 assert (UseCompressedOops, "should only be used for compressed headers");
5812 assert (Universe::heap() != nullptr, "java heap should be initialized");
5813 // Cannot assert, unverified entry point counts instructions (see .ad file)
5814 // vtableStubs also counts instructions in pd_code_size_limit.
5815 // Also do not verify_oop as this is called by verify_oop.
5816 if (CompressedOops::shift() != 0) {
5817 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5818 if (LogMinObjAlignmentInBytes == Address::times_8) {
5819 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5820 } else {
5821 if (dst != src) {
5822 movq(dst, src);
5823 }
5824 shlq(dst, LogMinObjAlignmentInBytes);
5825 if (CompressedOops::base() != nullptr) {
5826 addq(dst, r12_heapbase);
5827 }
5828 }
5829 } else {
5830 assert (CompressedOops::base() == nullptr, "sanity");
5831 if (dst != src) {
5832 movq(dst, src);
5833 }
5834 }
5835 }
5836
5837 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5838 BLOCK_COMMENT("encode_klass_not_null {");
5839 assert_different_registers(r, tmp);
5840 if (CompressedKlassPointers::base() != nullptr) {
5841 if (AOTCodeCache::is_on_for_dump()) {
5842 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5843 } else {
5844 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5845 }
5846 subq(r, tmp);
5847 }
5848 if (CompressedKlassPointers::shift() != 0) {
5849 shrq(r, CompressedKlassPointers::shift());
5850 }
5851 BLOCK_COMMENT("} encode_klass_not_null");
5852 }
5853
5854 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5855 BLOCK_COMMENT("encode_and_move_klass_not_null {");
5856 assert_different_registers(src, dst);
5857 if (CompressedKlassPointers::base() != nullptr) {
5858 if (AOTCodeCache::is_on_for_dump()) {
5859 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5860 negq(dst);
5861 } else {
5862 movptr(dst, -(intptr_t)CompressedKlassPointers::base());
5863 }
5864 addq(dst, src);
5865 } else {
5866 movptr(dst, src);
5867 }
5868 if (CompressedKlassPointers::shift() != 0) {
5869 shrq(dst, CompressedKlassPointers::shift());
5870 }
5871 BLOCK_COMMENT("} encode_and_move_klass_not_null");
5872 }
5873
5874 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5875 BLOCK_COMMENT("decode_klass_not_null {");
5876 assert_different_registers(r, tmp);
5877 // Note: it will change flags
5878 // Cannot assert, unverified entry point counts instructions (see .ad file)
5879 // vtableStubs also counts instructions in pd_code_size_limit.
5880 // Also do not verify_oop as this is called by verify_oop.
5881 if (CompressedKlassPointers::shift() != 0) {
5882 shlq(r, CompressedKlassPointers::shift());
5883 }
5884 if (CompressedKlassPointers::base() != nullptr) {
5885 if (AOTCodeCache::is_on_for_dump()) {
5886 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5887 } else {
5888 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5889 }
5890 addq(r, tmp);
5891 }
5892 BLOCK_COMMENT("} decode_klass_not_null");
5893 }
5894
5895 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5896 BLOCK_COMMENT("decode_and_move_klass_not_null {");
5897 assert_different_registers(src, dst);
5898 // Note: it will change flags
5899 // Cannot assert, unverified entry point counts instructions (see .ad file)
5900 // vtableStubs also counts instructions in pd_code_size_limit.
5901 // Also do not verify_oop as this is called by verify_oop.
5902
5903 if (CompressedKlassPointers::base() == nullptr &&
5904 CompressedKlassPointers::shift() == 0) {
5905 // The best case scenario is that there is no base or shift. Then it is already
5906 // a pointer that needs nothing but a register rename.
5907 movl(dst, src);
5908 } else {
5909 if (CompressedKlassPointers::shift() <= Address::times_8) {
5910 if (CompressedKlassPointers::base() != nullptr) {
5911 if (AOTCodeCache::is_on_for_dump()) {
5912 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5913 } else {
5914 movptr(dst, (intptr_t)CompressedKlassPointers::base());
5915 }
5916 } else {
5917 xorq(dst, dst);
5918 }
5919 if (CompressedKlassPointers::shift() != 0) {
5920 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
5921 leaq(dst, Address(dst, src, Address::times_8, 0));
5922 } else {
5923 addq(dst, src);
5924 }
5925 } else {
5926 if (CompressedKlassPointers::base() != nullptr) {
5927 if (AOTCodeCache::is_on_for_dump()) {
5928 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5929 shrq(dst, CompressedKlassPointers::shift());
5930 } else {
5931 const intptr_t base_right_shifted =
5932 (intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5933 movptr(dst, base_right_shifted);
5934 }
5935 } else {
5936 xorq(dst, dst);
5937 }
5938 addq(dst, src);
5939 shlq(dst, CompressedKlassPointers::shift());
5940 }
5941 }
5942 BLOCK_COMMENT("} decode_and_move_klass_not_null");
5943 }
5944
5945 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5946 assert (UseCompressedOops, "should only be used for compressed headers");
5947 assert (Universe::heap() != nullptr, "java heap should be initialized");
5948 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5949 int oop_index = oop_recorder()->find_index(obj);
5950 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5951 mov_narrow_oop(dst, oop_index, rspec);
5952 }
5953
5954 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5955 assert (UseCompressedOops, "should only be used for compressed headers");
5956 assert (Universe::heap() != nullptr, "java heap should be initialized");
5957 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5958 int oop_index = oop_recorder()->find_index(obj);
5959 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5960 mov_narrow_oop(dst, oop_index, rspec);
5961 }
5962
5963 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5964 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5965 int klass_index = oop_recorder()->find_index(k);
5966 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5967 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5968 }
5969
5970 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5971 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5972 int klass_index = oop_recorder()->find_index(k);
5973 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5974 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5975 }
5976
5977 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5978 assert (UseCompressedOops, "should only be used for compressed headers");
5979 assert (Universe::heap() != nullptr, "java heap should be initialized");
5980 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5981 int oop_index = oop_recorder()->find_index(obj);
5982 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5983 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5984 }
5985
5986 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5987 assert (UseCompressedOops, "should only be used for compressed headers");
5988 assert (Universe::heap() != nullptr, "java heap should be initialized");
5989 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5990 int oop_index = oop_recorder()->find_index(obj);
5991 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5992 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5993 }
5994
5995 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5996 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5997 int klass_index = oop_recorder()->find_index(k);
5998 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5999 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6000 }
6001
6002 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6003 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6004 int klass_index = oop_recorder()->find_index(k);
6005 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6006 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6007 }
6008
6009 void MacroAssembler::reinit_heapbase() {
6010 if (UseCompressedOops) {
6011 if (Universe::heap() != nullptr && !AOTCodeCache::is_on_for_dump()) {
6012 if (CompressedOops::base() == nullptr) {
6013 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6014 } else {
6015 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6016 }
6017 } else {
6018 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6019 }
6020 }
6021 }
6022
6023 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6024 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6025 // An inline type might be returned. If fields are in registers we
6026 // need to allocate an inline type instance and initialize it with
6027 // the value of the fields.
6028 Label skip;
6029 // We only need a new buffered inline type if a new one is not returned
6030 testptr(rax, 1);
6031 jcc(Assembler::zero, skip);
6032 int call_offset = -1;
6033
6034 // The following code is similar to allocation code in TemplateTable::_new but has some slight differences,
6035 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6036 // allocating is not necessary if vk != nullptr, etc.
6037 Label slow_case;
6038 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6039 mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
6040 if (vk != nullptr) {
6041 // Called from C1, where the return type is statically known.
6042 movptr(rbx, (intptr_t)vk->get_InlineKlass());
6043 jint lh = vk->layout_helper();
6044 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6045 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6046 tlab_allocate(rax, noreg, lh, r13, r14, slow_case);
6047 } else {
6048 jmp(slow_case);
6049 }
6050 } else {
6051 // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
6052 mov(rbx, rax);
6053 andptr(rbx, -2);
6054 if (UseTLAB) {
6055 movl(r14, Address(rbx, Klass::layout_helper_offset()));
6056 testl(r14, Klass::_lh_instance_slow_path_bit);
6057 jcc(Assembler::notZero, slow_case);
6058 tlab_allocate(rax, r14, 0, r13, r14, slow_case);
6059 } else {
6060 jmp(slow_case);
6061 }
6062 }
6063 if (UseTLAB) {
6064 // 2. Initialize buffered inline instance header
6065 Register buffer_obj = rax;
6066 Register klass = rbx;
6067 if (UseCompactObjectHeaders) {
6068 Register mark_word = r13;
6069 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
6070 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), mark_word);
6071 } else {
6072 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
6073 xorl(r13, r13);
6074 store_klass_gap(buffer_obj, r13);
6075 if (vk == nullptr) {
6076 // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
6077 mov(r13, klass);
6078 }
6079 store_klass(buffer_obj, klass, rscratch1);
6080 klass = r13;
6081 }
6082 // 3. Initialize its fields with an inline class specific handler
6083 if (vk != nullptr) {
6084 call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6085 } else {
6086 movptr(rbx, Address(klass, InlineKlass::adr_members_offset()));
6087 movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
6088 call(rbx);
6089 }
6090 jmp(skip);
6091 }
6092 bind(slow_case);
6093 // We failed to allocate a new inline type, fall back to a runtime
6094 // call. Some oop field may be live in some registers but we can't
6095 // tell. That runtime call will take care of preserving them
6096 // across a GC if there's one.
6097 mov(rax, rscratch1);
6098
6099 if (from_interpreter) {
6100 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6101 } else {
6102 call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6103 call_offset = offset();
6104 }
6105
6106 bind(skip);
6107 return call_offset;
6108 }
6109
6110 // Move a value between registers/stack slots and update the reg_state
6111 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6112 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6113 if (reg_state[to->value()] == reg_written) {
6114 return true; // Already written
6115 }
6116 if (from != to && bt != T_VOID) {
6117 if (reg_state[to->value()] == reg_readonly) {
6118 return false; // Not yet writable
6119 }
6120 if (from->is_reg()) {
6121 if (to->is_reg()) {
6122 if (from->is_XMMRegister()) {
6123 if (bt == T_DOUBLE) {
6124 movdbl(to->as_XMMRegister(), from->as_XMMRegister());
6125 } else {
6126 assert(bt == T_FLOAT, "must be float");
6127 movflt(to->as_XMMRegister(), from->as_XMMRegister());
6128 }
6129 } else {
6130 movq(to->as_Register(), from->as_Register());
6131 }
6132 } else {
6133 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6134 Address to_addr = Address(rsp, st_off);
6135 if (from->is_XMMRegister()) {
6136 if (bt == T_DOUBLE) {
6137 movdbl(to_addr, from->as_XMMRegister());
6138 } else {
6139 assert(bt == T_FLOAT, "must be float");
6140 movflt(to_addr, from->as_XMMRegister());
6141 }
6142 } else {
6143 movq(to_addr, from->as_Register());
6144 }
6145 }
6146 } else {
6147 Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
6148 if (to->is_reg()) {
6149 if (to->is_XMMRegister()) {
6150 if (bt == T_DOUBLE) {
6151 movdbl(to->as_XMMRegister(), from_addr);
6152 } else {
6153 assert(bt == T_FLOAT, "must be float");
6154 movflt(to->as_XMMRegister(), from_addr);
6155 }
6156 } else {
6157 movq(to->as_Register(), from_addr);
6158 }
6159 } else {
6160 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6161 movq(r13, from_addr);
6162 movq(Address(rsp, st_off), r13);
6163 }
6164 }
6165 }
6166 // Update register states
6167 reg_state[from->value()] = reg_writable;
6168 reg_state[to->value()] = reg_written;
6169 return true;
6170 }
6171
6172 // Calculate the extra stack space required for packing or unpacking inline
6173 // args and adjust the stack pointer (see MacroAssembler::remove_frame).
6174 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6175 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
6176 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6177 assert(sp_inc > 0, "sanity");
6178 // Two additional slots to account for return address
6179 sp_inc += 2 * VMRegImpl::stack_slot_size;
6180
6181 push(rbp);
6182 subptr(rsp, sp_inc);
6183 #ifdef ASSERT
6184 movl(Address(rsp, 0), badRegWordVal);
6185 movl(Address(rsp, VMRegImpl::stack_slot_size), badRegWordVal);
6186 #endif
6187 return sp_inc + wordSize; // account for rbp space
6188 }
6189
6190 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
6191 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6192 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6193 RegState reg_state[]) {
6194 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6195 assert(from->is_valid(), "source must be valid");
6196 bool progress = false;
6197 #ifdef ASSERT
6198 const int start_offset = offset();
6199 #endif
6200
6201 Label L_null, L_notNull;
6202 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6203 Register tmp1 = r10;
6204 Register tmp2 = r13;
6205 Register fromReg = noreg;
6206 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, true);
6207 bool done = true;
6208 bool mark_done = true;
6209 VMReg toReg;
6210 BasicType bt;
6211 // Check if argument requires a null check
6212 bool null_check = false;
6213 VMReg nullCheckReg;
6214 while (stream.next(nullCheckReg, bt)) {
6215 if (sig->at(stream.sig_index())._offset == -1) {
6216 null_check = true;
6217 break;
6218 }
6219 }
6220 stream.reset(sig_index, to_index);
6221 while (stream.next(toReg, bt)) {
6222 assert(toReg->is_valid(), "destination must be valid");
6223 int idx = (int)toReg->value();
6224 if (reg_state[idx] == reg_readonly) {
6225 if (idx != from->value()) {
6226 mark_done = false;
6227 }
6228 done = false;
6229 continue;
6230 } else if (reg_state[idx] == reg_written) {
6231 continue;
6232 }
6233 assert(reg_state[idx] == reg_writable, "must be writable");
6234 reg_state[idx] = reg_written;
6235 progress = true;
6236
6237 if (fromReg == noreg) {
6238 if (from->is_reg()) {
6239 fromReg = from->as_Register();
6240 } else {
6241 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6242 movq(tmp1, Address(rsp, st_off));
6243 fromReg = tmp1;
6244 }
6245 if (null_check) {
6246 // Nullable inline type argument, emit null check
6247 testptr(fromReg, fromReg);
6248 jcc(Assembler::zero, L_null);
6249 }
6250 }
6251 int off = sig->at(stream.sig_index())._offset;
6252 if (off == -1) {
6253 assert(null_check, "Missing null check at");
6254 if (toReg->is_stack()) {
6255 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6256 movq(Address(rsp, st_off), 1);
6257 } else {
6258 movq(toReg->as_Register(), 1);
6259 }
6260 continue;
6261 }
6262 if (sig->at(stream.sig_index())._vt_oop) {
6263 if (toReg->is_stack()) {
6264 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6265 movq(Address(rsp, st_off), fromReg);
6266 } else {
6267 movq(toReg->as_Register(), fromReg);
6268 }
6269 continue;
6270 }
6271 assert(off > 0, "offset in object should be positive");
6272 Address fromAddr = Address(fromReg, off);
6273 if (!toReg->is_XMMRegister()) {
6274 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
6275 if (is_reference_type(bt)) {
6276 load_heap_oop(dst, fromAddr);
6277 } else {
6278 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
6279 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
6280 }
6281 if (toReg->is_stack()) {
6282 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6283 movq(Address(rsp, st_off), dst);
6284 }
6285 } else if (bt == T_DOUBLE) {
6286 movdbl(toReg->as_XMMRegister(), fromAddr);
6287 } else {
6288 assert(bt == T_FLOAT, "must be float");
6289 movflt(toReg->as_XMMRegister(), fromAddr);
6290 }
6291 }
6292 if (progress && null_check) {
6293 if (done) {
6294 jmp(L_notNull);
6295 bind(L_null);
6296 // Set null marker to zero to signal that the argument is null.
6297 // Also set all fields to zero since the runtime requires a canonical
6298 // representation of a flat null.
6299 stream.reset(sig_index, to_index);
6300 while (stream.next(toReg, bt)) {
6301 if (toReg->is_stack()) {
6302 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6303 movq(Address(rsp, st_off), 0);
6304 } else if (toReg->is_XMMRegister()) {
6305 xorps(toReg->as_XMMRegister(), toReg->as_XMMRegister());
6306 } else {
6307 xorl(toReg->as_Register(), toReg->as_Register());
6308 }
6309 }
6310 bind(L_notNull);
6311 } else {
6312 bind(L_null);
6313 }
6314 }
6315
6316 sig_index = stream.sig_index();
6317 to_index = stream.regs_index();
6318
6319 if (mark_done && reg_state[from->value()] != reg_written) {
6320 // This is okay because no one else will write to that slot
6321 reg_state[from->value()] = reg_writable;
6322 }
6323 from_index--;
6324 assert(progress || (start_offset == offset()), "should not emit code");
6325 return done;
6326 }
6327
6328 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
6329 VMRegPair* from, int from_count, int& from_index, VMReg to,
6330 RegState reg_state[], Register val_array) {
6331 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
6332 assert(to->is_valid(), "destination must be valid");
6333
6334 if (reg_state[to->value()] == reg_written) {
6335 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6336 return true; // Already written
6337 }
6338
6339 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
6340 Register val_obj_tmp = r11;
6341 Register from_reg_tmp = r14;
6342 Register tmp1 = r10;
6343 Register tmp2 = r13;
6344 Register tmp3 = rbx;
6345 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
6346
6347 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
6348
6349 if (reg_state[to->value()] == reg_readonly) {
6350 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
6351 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6352 return false; // Not yet writable
6353 }
6354 val_obj = val_obj_tmp;
6355 }
6356
6357 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
6358 VMReg fromReg;
6359 BasicType bt;
6360 Label L_null;
6361 while (stream.next(fromReg, bt)) {
6362 assert(fromReg->is_valid(), "source must be valid");
6363 reg_state[fromReg->value()] = reg_writable;
6364
6365 int off = sig->at(stream.sig_index())._offset;
6366 if (off == -1) {
6367 // Nullable inline type argument, emit null check
6368 Label L_notNull;
6369 if (fromReg->is_stack()) {
6370 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6371 testb(Address(rsp, ld_off), 1);
6372 } else {
6373 testb(fromReg->as_Register(), 1);
6374 }
6375 jcc(Assembler::notZero, L_notNull);
6376 movptr(val_obj, 0);
6377 jmp(L_null);
6378 bind(L_notNull);
6379 continue;
6380 }
6381 if (sig->at(stream.sig_index())._vt_oop) {
6382 // buffer argument: use if non null
6383 if (fromReg->is_stack()) {
6384 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6385 movptr(val_obj, Address(rsp, ld_off));
6386 } else {
6387 movptr(val_obj, fromReg->as_Register());
6388 }
6389 testptr(val_obj, val_obj);
6390 jcc(Assembler::notEqual, L_null);
6391 // otherwise get the buffer from the just allocated pool of buffers
6392 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
6393 load_heap_oop(val_obj, Address(val_array, index));
6394 continue;
6395 }
6396
6397 assert(off > 0, "offset in object should be positive");
6398 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
6399
6400 // Pack the scalarized field into the value object.
6401 Address dst(val_obj, off);
6402 if (!fromReg->is_XMMRegister()) {
6403 Register src;
6404 if (fromReg->is_stack()) {
6405 src = from_reg_tmp;
6406 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6407 load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
6408 } else {
6409 src = fromReg->as_Register();
6410 }
6411 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
6412 if (is_reference_type(bt)) {
6413 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep val_obj valid.
6414 mov(tmp3, val_obj);
6415 Address dst_with_tmp3(tmp3, off);
6416 store_heap_oop(dst_with_tmp3, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
6417 } else {
6418 store_sized_value(dst, src, size_in_bytes);
6419 }
6420 } else if (bt == T_DOUBLE) {
6421 movdbl(dst, fromReg->as_XMMRegister());
6422 } else {
6423 assert(bt == T_FLOAT, "must be float");
6424 movflt(dst, fromReg->as_XMMRegister());
6425 }
6426 }
6427 bind(L_null);
6428 sig_index = stream.sig_index();
6429 from_index = stream.regs_index();
6430
6431 assert(reg_state[to->value()] == reg_writable, "must have already been read");
6432 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6433 assert(success, "to register must be writable");
6434 return true;
6435 }
6436
6437 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6438 return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
6439 }
6440
6441 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
6442 assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6443 if (needs_stack_repair) {
6444 // The method has a scalarized entry point (where fields of value object arguments
6445 // are passed through registers and stack), and a non-scalarized entry point (where
6446 // value object arguments are given as oops). The non-scalarized entry point will
6447 // first load each field of value object arguments and store them in registers and on
6448 // the stack in a way compatible with the scalarized entry point. To do so, some extra
6449 // stack space might be reserved (if argument registers are not enough). On leaving the
6450 // method, this space must be freed.
6451 //
6452 // In case we used the non-scalarized entry point the stack looks like this:
6453 //
6454 // | Arguments from caller |
6455 // |---------------------------| <-- caller's SP
6456 // | Return address #1 |
6457 // | Saved RBP #1 |
6458 // |---------------------------|
6459 // | Extension space for |
6460 // | inline arg (un)packing |
6461 // |---------------------------| <-- start of this method's frame
6462 // | Return address #2 |
6463 // | Saved RBP #2 |
6464 // |---------------------------| <-- RBP (with -XX:+PreserveFramePointer)
6465 // | sp_inc |
6466 // | method locals |
6467 // |---------------------------| <-- SP
6468 //
6469 // Space for the return pc and saved rbp is reserved twice. But only the #1 copies
6470 // contain the real values of return pc and saved rbp. The #2 copies are not reliable
6471 // and should not be used. They are mostly needed to add space between the extension
6472 // space and the locals, as there would be between the real arguments and the locals
6473 // if we don't need to do unpacking (from the scalarized entry point).
6474 //
6475 // When leaving, one must load RBP #1 into RBP, and use the copy #1 of the return address,
6476 // while keeping in mind that from the scalarized entry point, there will be only one
6477 // copy. Indeed, in the case we used the scalarized calling convention, the stack looks like this:
6478 //
6479 // | Arguments from caller |
6480 // |---------------------------| <-- caller's SP
6481 // | Return address |
6482 // | Saved RBP |
6483 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer)
6484 // | sp_inc |
6485 // | method locals |
6486 // |---------------------------| <-- SP
6487 //
6488 // The sp_inc stack slot holds the total size of the frame, including the extension
6489 // space and copies #2 of the return address and the saved RBP (but never the copies
6490 // #1 of the return address and saved RBP). That is how to find the copies #1 of the
6491 // return address and saved rbp. This size is expressed in bytes. Be careful when using
6492 // it from C++ in pointer arithmetic you might need to divide it by wordSize.
6493
6494 // The stack increment resides just below the saved rbp
6495 addq(rsp, Address(rsp, initial_framesize - wordSize));
6496 pop(rbp);
6497 } else {
6498 if (initial_framesize > 0) {
6499 addq(rsp, initial_framesize);
6500 }
6501 pop(rbp);
6502 }
6503 }
6504
6505 #ifdef COMPILER2
6506
6507 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6508 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
6509 // cnt - number of qwords (8-byte words).
6510 // base - start address, qword aligned.
6511 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6512 bool use64byteVector = (MaxVectorSize == 64) && (CopyAVX3Threshold == 0);
6513 if (use64byteVector) {
6514 evpbroadcastq(xtmp, val, AVX_512bit);
6515 } else if (MaxVectorSize >= 32) {
6516 movdq(xtmp, val);
6517 punpcklqdq(xtmp, xtmp);
6518 vinserti128_high(xtmp, xtmp);
6519 } else {
6520 movdq(xtmp, val);
6521 punpcklqdq(xtmp, xtmp);
6522 }
6523 jmp(L_zero_64_bytes);
6524
6525 BIND(L_loop);
6526 if (MaxVectorSize >= 32) {
6527 fill64(base, 0, xtmp, use64byteVector);
6528 } else {
6529 movdqu(Address(base, 0), xtmp);
6530 movdqu(Address(base, 16), xtmp);
6531 movdqu(Address(base, 32), xtmp);
6532 movdqu(Address(base, 48), xtmp);
6533 }
6534 addptr(base, 64);
6535
6536 BIND(L_zero_64_bytes);
6537 subptr(cnt, 8);
6538 jccb(Assembler::greaterEqual, L_loop);
6539
6540 // Copy trailing 64 bytes
6541 if (use64byteVector) {
6542 addptr(cnt, 8);
6543 jccb(Assembler::equal, L_end);
6544 fill64_masked(3, base, 0, xtmp, mask, cnt, val, true);
6545 jmp(L_end);
6546 } else {
6547 addptr(cnt, 4);
6548 jccb(Assembler::less, L_tail);
6549 if (MaxVectorSize >= 32) {
6550 vmovdqu(Address(base, 0), xtmp);
6551 } else {
6552 movdqu(Address(base, 0), xtmp);
6553 movdqu(Address(base, 16), xtmp);
6554 }
6555 }
6556 addptr(base, 32);
6557 subptr(cnt, 4);
6558
6559 BIND(L_tail);
6560 addptr(cnt, 4);
6561 jccb(Assembler::lessEqual, L_end);
6562 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6563 fill32_masked(3, base, 0, xtmp, mask, cnt, val);
6564 } else {
6565 decrement(cnt);
6566
6567 BIND(L_sloop);
6568 movq(Address(base, 0), xtmp);
6569 addptr(base, 8);
6570 decrement(cnt);
6571 jccb(Assembler::greaterEqual, L_sloop);
6572 }
6573 BIND(L_end);
6574 }
6575
6576 // Clearing constant sized memory using YMM/ZMM registers.
6577 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6578 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6579 bool use64byteVector = (MaxVectorSize > 32) && (CopyAVX3Threshold == 0);
6580
6581 int vector64_count = (cnt & (~0x7)) >> 3;
6582 cnt = cnt & 0x7;
6583 const int fill64_per_loop = 4;
6584 const int max_unrolled_fill64 = 8;
6585
6586 // 64 byte initialization loop.
6587 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6588 int start64 = 0;
6589 if (vector64_count > max_unrolled_fill64) {
6590 Label LOOP;
6591 Register index = rtmp;
6592
6593 start64 = vector64_count - (vector64_count % fill64_per_loop);
6594
6595 movl(index, 0);
6596 BIND(LOOP);
6597 for (int i = 0; i < fill64_per_loop; i++) {
6598 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6599 }
6600 addl(index, fill64_per_loop * 64);
6601 cmpl(index, start64 * 64);
6602 jccb(Assembler::less, LOOP);
6603 }
6604 for (int i = start64; i < vector64_count; i++) {
6605 fill64(base, i * 64, xtmp, use64byteVector);
6606 }
6607
6608 // Clear remaining 64 byte tail.
6609 int disp = vector64_count * 64;
6610 if (cnt) {
6611 switch (cnt) {
6612 case 1:
6613 movq(Address(base, disp), xtmp);
6614 break;
6615 case 2:
6616 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6617 break;
6618 case 3:
6619 movl(rtmp, 0x7);
6620 kmovwl(mask, rtmp);
6621 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6622 break;
6623 case 4:
6624 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6625 break;
6626 case 5:
6627 if (use64byteVector) {
6628 movl(rtmp, 0x1F);
6629 kmovwl(mask, rtmp);
6630 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6631 } else {
6632 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6633 movq(Address(base, disp + 32), xtmp);
6634 }
6635 break;
6636 case 6:
6637 if (use64byteVector) {
6638 movl(rtmp, 0x3F);
6639 kmovwl(mask, rtmp);
6640 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6641 } else {
6642 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6643 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6644 }
6645 break;
6646 case 7:
6647 if (use64byteVector) {
6648 movl(rtmp, 0x7F);
6649 kmovwl(mask, rtmp);
6650 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6651 } else {
6652 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6653 movl(rtmp, 0x7);
6654 kmovwl(mask, rtmp);
6655 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6656 }
6657 break;
6658 default:
6659 fatal("Unexpected length : %d\n",cnt);
6660 break;
6661 }
6662 }
6663 }
6664
6665 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
6666 bool is_large, bool word_copy_only, KRegister mask) {
6667 // cnt - number of qwords (8-byte words).
6668 // base - start address, qword aligned.
6669 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6670 assert(base==rdi, "base register must be edi for rep stos");
6671 assert(val==rax, "val register must be eax for rep stos");
6672 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6673 assert(InitArrayShortSize % BytesPerLong == 0,
6674 "InitArrayShortSize should be the multiple of BytesPerLong");
6675
6676 Label DONE;
6677
6678 if (!is_large) {
6679 Label LOOP, LONG;
6680 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6681 jccb(Assembler::greater, LONG);
6682
6683 decrement(cnt);
6684 jccb(Assembler::negative, DONE); // Zero length
6685
6686 // Use individual pointer-sized stores for small counts:
6687 BIND(LOOP);
6688 movptr(Address(base, cnt, Address::times_ptr), val);
6689 decrement(cnt);
6690 jccb(Assembler::greaterEqual, LOOP);
6691 jmpb(DONE);
6692
6693 BIND(LONG);
6694 }
6695
6696 // Use longer rep-prefixed ops for non-small counts:
6697 if (UseFastStosb && !word_copy_only) {
6698 shlptr(cnt, 3); // convert to number of bytes
6699 rep_stosb();
6700 } else if (UseXMMForObjInit) {
6701 xmm_clear_mem(base, cnt, val, xtmp, mask);
6702 } else {
6703 rep_stos();
6704 }
6705
6706 BIND(DONE);
6707 }
6708
6709 #endif //COMPILER2
6710
6711
6712 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6713 Register to, Register value, Register count,
6714 Register rtmp, XMMRegister xtmp) {
6715 ShortBranchVerifier sbv(this);
6716 assert_different_registers(to, value, count, rtmp);
6717 Label L_exit;
6718 Label L_fill_2_bytes, L_fill_4_bytes;
6719
6720 #if defined(COMPILER2)
6721 if(MaxVectorSize >=32 &&
6722 VM_Version::supports_avx512vlbw() &&
6723 VM_Version::supports_bmi2()) {
6724 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6725 return;
6726 }
6727 #endif
6728
6729 int shift = -1;
6730 switch (t) {
6731 case T_BYTE:
6732 shift = 2;
6733 break;
6734 case T_SHORT:
6735 shift = 1;
6736 break;
6737 case T_INT:
6738 shift = 0;
6739 break;
6740 default: ShouldNotReachHere();
6741 }
6742
6743 if (t == T_BYTE) {
6744 andl(value, 0xff);
6745 movl(rtmp, value);
6746 shll(rtmp, 8);
6747 orl(value, rtmp);
6748 }
6749 if (t == T_SHORT) {
6750 andl(value, 0xffff);
6751 }
6752 if (t == T_BYTE || t == T_SHORT) {
6753 movl(rtmp, value);
6754 shll(rtmp, 16);
6755 orl(value, rtmp);
6756 }
6757
6758 cmpptr(count, 8 << shift); // Short arrays (< 32 bytes) fill by element
6759 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6760 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6761 Label L_skip_align2;
6762 // align source address at 4 bytes address boundary
6763 if (t == T_BYTE) {
6764 Label L_skip_align1;
6765 // One byte misalignment happens only for byte arrays
6766 testptr(to, 1);
6767 jccb(Assembler::zero, L_skip_align1);
6768 movb(Address(to, 0), value);
6769 increment(to);
6770 decrement(count);
6771 BIND(L_skip_align1);
6772 }
6773 // Two bytes misalignment happens only for byte and short (char) arrays
6774 testptr(to, 2);
6775 jccb(Assembler::zero, L_skip_align2);
6776 movw(Address(to, 0), value);
6777 addptr(to, 2);
6778 subptr(count, 1<<(shift-1));
6779 BIND(L_skip_align2);
6780 }
6781 {
6782 Label L_fill_32_bytes;
6783 if (!UseUnalignedLoadStores) {
6784 // align to 8 bytes, we know we are 4 byte aligned to start
6785 testptr(to, 4);
6786 jccb(Assembler::zero, L_fill_32_bytes);
6787 movl(Address(to, 0), value);
6788 addptr(to, 4);
6789 subptr(count, 1<<shift);
6790 }
6791 BIND(L_fill_32_bytes);
6792 {
6793 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6794 movdl(xtmp, value);
6795 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6796 Label L_check_fill_32_bytes;
6797 if (UseAVX > 2) {
6798 // Fill 64-byte chunks
6799 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6800
6801 // If number of bytes to fill < CopyAVX3Threshold, perform fill using AVX2
6802 cmpptr(count, CopyAVX3Threshold);
6803 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6804
6805 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6806
6807 subptr(count, 16 << shift);
6808 jcc(Assembler::less, L_check_fill_32_bytes);
6809 align(16);
6810
6811 BIND(L_fill_64_bytes_loop_avx3);
6812 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6813 addptr(to, 64);
6814 subptr(count, 16 << shift);
6815 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6816 jmpb(L_check_fill_32_bytes);
6817
6818 BIND(L_check_fill_64_bytes_avx2);
6819 }
6820 // Fill 64-byte chunks
6821 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6822
6823 subptr(count, 16 << shift);
6824 jcc(Assembler::less, L_check_fill_32_bytes);
6825
6826 // align data for 64-byte chunks
6827 Label L_fill_64_bytes_loop, L_align_64_bytes_loop;
6828 if (EnableX86ECoreOpts) {
6829 // align 'big' arrays to cache lines to minimize split_stores
6830 cmpptr(count, 96 << shift);
6831 jcc(Assembler::below, L_fill_64_bytes_loop);
6832
6833 // Find the bytes needed for alignment
6834 movptr(rtmp, to);
6835 andptr(rtmp, 0x1c);
6836 jcc(Assembler::zero, L_fill_64_bytes_loop);
6837 negptr(rtmp); // number of bytes to fill 32-rtmp. it filled by 2 mov by 32
6838 addptr(rtmp, 32);
6839 shrptr(rtmp, 2 - shift);// get number of elements from bytes
6840 subptr(count, rtmp); // adjust count by number of elements
6841
6842 align(16);
6843 BIND(L_align_64_bytes_loop);
6844 movdl(Address(to, 0), xtmp);
6845 addptr(to, 4);
6846 subptr(rtmp, 1 << shift);
6847 jcc(Assembler::greater, L_align_64_bytes_loop);
6848 }
6849
6850 align(16);
6851 BIND(L_fill_64_bytes_loop);
6852 vmovdqu(Address(to, 0), xtmp);
6853 vmovdqu(Address(to, 32), xtmp);
6854 addptr(to, 64);
6855 subptr(count, 16 << shift);
6856 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6857
6858 align(16);
6859 BIND(L_check_fill_32_bytes);
6860 addptr(count, 8 << shift);
6861 jccb(Assembler::less, L_check_fill_8_bytes);
6862 vmovdqu(Address(to, 0), xtmp);
6863 addptr(to, 32);
6864 subptr(count, 8 << shift);
6865
6866 BIND(L_check_fill_8_bytes);
6867 // clean upper bits of YMM registers
6868 movdl(xtmp, value);
6869 pshufd(xtmp, xtmp, 0);
6870 } else {
6871 // Fill 32-byte chunks
6872 pshufd(xtmp, xtmp, 0);
6873
6874 subptr(count, 8 << shift);
6875 jcc(Assembler::less, L_check_fill_8_bytes);
6876 align(16);
6877
6878 BIND(L_fill_32_bytes_loop);
6879
6880 if (UseUnalignedLoadStores) {
6881 movdqu(Address(to, 0), xtmp);
6882 movdqu(Address(to, 16), xtmp);
6883 } else {
6884 movq(Address(to, 0), xtmp);
6885 movq(Address(to, 8), xtmp);
6886 movq(Address(to, 16), xtmp);
6887 movq(Address(to, 24), xtmp);
6888 }
6889
6890 addptr(to, 32);
6891 subptr(count, 8 << shift);
6892 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6893
6894 BIND(L_check_fill_8_bytes);
6895 }
6896 addptr(count, 8 << shift);
6897 jccb(Assembler::zero, L_exit);
6898 jmpb(L_fill_8_bytes);
6899
6900 //
6901 // length is too short, just fill qwords
6902 //
6903 align(16);
6904 BIND(L_fill_8_bytes_loop);
6905 movq(Address(to, 0), xtmp);
6906 addptr(to, 8);
6907 BIND(L_fill_8_bytes);
6908 subptr(count, 1 << (shift + 1));
6909 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6910 }
6911 }
6912
6913 Label L_fill_4_bytes_loop;
6914 testl(count, 1 << shift);
6915 jccb(Assembler::zero, L_fill_2_bytes);
6916
6917 align(16);
6918 BIND(L_fill_4_bytes_loop);
6919 movl(Address(to, 0), value);
6920 addptr(to, 4);
6921
6922 BIND(L_fill_4_bytes);
6923 subptr(count, 1 << shift);
6924 jccb(Assembler::greaterEqual, L_fill_4_bytes_loop);
6925
6926 if (t == T_BYTE || t == T_SHORT) {
6927 Label L_fill_byte;
6928 BIND(L_fill_2_bytes);
6929 // fill trailing 2 bytes
6930 testl(count, 1<<(shift-1));
6931 jccb(Assembler::zero, L_fill_byte);
6932 movw(Address(to, 0), value);
6933 if (t == T_BYTE) {
6934 addptr(to, 2);
6935 BIND(L_fill_byte);
6936 // fill trailing byte
6937 testl(count, 1);
6938 jccb(Assembler::zero, L_exit);
6939 movb(Address(to, 0), value);
6940 } else {
6941 BIND(L_fill_byte);
6942 }
6943 } else {
6944 BIND(L_fill_2_bytes);
6945 }
6946 BIND(L_exit);
6947 }
6948
6949 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6950 switch(type) {
6951 case T_BYTE:
6952 case T_BOOLEAN:
6953 evpbroadcastb(dst, src, vector_len);
6954 break;
6955 case T_SHORT:
6956 case T_CHAR:
6957 evpbroadcastw(dst, src, vector_len);
6958 break;
6959 case T_INT:
6960 case T_FLOAT:
6961 evpbroadcastd(dst, src, vector_len);
6962 break;
6963 case T_LONG:
6964 case T_DOUBLE:
6965 evpbroadcastq(dst, src, vector_len);
6966 break;
6967 default:
6968 fatal("Unhandled type : %s", type2name(type));
6969 break;
6970 }
6971 }
6972
6973 // Encode given char[]/byte[] to byte[] in ISO_8859_1 or ASCII
6974 //
6975 // @IntrinsicCandidate
6976 // int sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(
6977 // char[] sa, int sp, byte[] da, int dp, int len) {
6978 // int i = 0;
6979 // for (; i < len; i++) {
6980 // char c = sa[sp++];
6981 // if (c > '\u00FF')
6982 // break;
6983 // da[dp++] = (byte) c;
6984 // }
6985 // return i;
6986 // }
6987 //
6988 // @IntrinsicCandidate
6989 // int java.lang.StringCoding.encodeISOArray0(
6990 // byte[] sa, int sp, byte[] da, int dp, int len) {
6991 // int i = 0;
6992 // for (; i < len; i++) {
6993 // char c = StringUTF16.getChar(sa, sp++);
6994 // if (c > '\u00FF')
6995 // break;
6996 // da[dp++] = (byte) c;
6997 // }
6998 // return i;
6999 // }
7000 //
7001 // @IntrinsicCandidate
7002 // int java.lang.StringCoding.encodeAsciiArray0(
7003 // char[] sa, int sp, byte[] da, int dp, int len) {
7004 // int i = 0;
7005 // for (; i < len; i++) {
7006 // char c = sa[sp++];
7007 // if (c >= '\u0080')
7008 // break;
7009 // da[dp++] = (byte) c;
7010 // }
7011 // return i;
7012 // }
7013 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7014 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7015 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7016 Register tmp5, Register result, bool ascii) {
7017
7018 // rsi: src
7019 // rdi: dst
7020 // rdx: len
7021 // rcx: tmp5
7022 // rax: result
7023 ShortBranchVerifier sbv(this);
7024 assert_different_registers(src, dst, len, tmp5, result);
7025 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7026
7027 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
7028 int short_mask = ascii ? 0xff80 : 0xff00;
7029
7030 // set result
7031 xorl(result, result);
7032 // check for zero length
7033 testl(len, len);
7034 jcc(Assembler::zero, L_done);
7035
7036 movl(result, len);
7037
7038 // Setup pointers
7039 lea(src, Address(src, len, Address::times_2)); // char[]
7040 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7041 negptr(len);
7042
7043 if (UseSSE42Intrinsics || UseAVX >= 2) {
7044 Label L_copy_8_chars, L_copy_8_chars_exit;
7045 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7046
7047 if (UseAVX >= 2) {
7048 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7049 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7050 movdl(tmp1Reg, tmp5);
7051 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7052 jmp(L_chars_32_check);
7053
7054 bind(L_copy_32_chars);
7055 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7056 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7057 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7058 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7059 jccb(Assembler::notZero, L_copy_32_chars_exit);
7060 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7061 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7062 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7063
7064 bind(L_chars_32_check);
7065 addptr(len, 32);
7066 jcc(Assembler::lessEqual, L_copy_32_chars);
7067
7068 bind(L_copy_32_chars_exit);
7069 subptr(len, 16);
7070 jccb(Assembler::greater, L_copy_16_chars_exit);
7071
7072 } else if (UseSSE42Intrinsics) {
7073 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7074 movdl(tmp1Reg, tmp5);
7075 pshufd(tmp1Reg, tmp1Reg, 0);
7076 jmpb(L_chars_16_check);
7077 }
7078
7079 bind(L_copy_16_chars);
7080 if (UseAVX >= 2) {
7081 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7082 vptest(tmp2Reg, tmp1Reg);
7083 jcc(Assembler::notZero, L_copy_16_chars_exit);
7084 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7085 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7086 } else {
7087 if (UseAVX > 0) {
7088 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7089 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7090 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7091 } else {
7092 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7093 por(tmp2Reg, tmp3Reg);
7094 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7095 por(tmp2Reg, tmp4Reg);
7096 }
7097 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7098 jccb(Assembler::notZero, L_copy_16_chars_exit);
7099 packuswb(tmp3Reg, tmp4Reg);
7100 }
7101 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7102
7103 bind(L_chars_16_check);
7104 addptr(len, 16);
7105 jcc(Assembler::lessEqual, L_copy_16_chars);
7106
7107 bind(L_copy_16_chars_exit);
7108 if (UseAVX >= 2) {
7109 // clean upper bits of YMM registers
7110 vpxor(tmp2Reg, tmp2Reg);
7111 vpxor(tmp3Reg, tmp3Reg);
7112 vpxor(tmp4Reg, tmp4Reg);
7113 movdl(tmp1Reg, tmp5);
7114 pshufd(tmp1Reg, tmp1Reg, 0);
7115 }
7116 subptr(len, 8);
7117 jccb(Assembler::greater, L_copy_8_chars_exit);
7118
7119 bind(L_copy_8_chars);
7120 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7121 ptest(tmp3Reg, tmp1Reg);
7122 jccb(Assembler::notZero, L_copy_8_chars_exit);
7123 packuswb(tmp3Reg, tmp1Reg);
7124 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7125 addptr(len, 8);
7126 jccb(Assembler::lessEqual, L_copy_8_chars);
7127
7128 bind(L_copy_8_chars_exit);
7129 subptr(len, 8);
7130 jccb(Assembler::zero, L_done);
7131 }
7132
7133 bind(L_copy_1_char);
7134 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7135 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7136 jccb(Assembler::notZero, L_copy_1_char_exit);
7137 movb(Address(dst, len, Address::times_1, 0), tmp5);
7138 addptr(len, 1);
7139 jccb(Assembler::less, L_copy_1_char);
7140
7141 bind(L_copy_1_char_exit);
7142 addptr(result, len); // len is negative count of not processed elements
7143
7144 bind(L_done);
7145 }
7146
7147 /**
7148 * Helper for multiply_to_len().
7149 */
7150 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7151 addq(dest_lo, src1);
7152 adcq(dest_hi, 0);
7153 addq(dest_lo, src2);
7154 adcq(dest_hi, 0);
7155 }
7156
7157 /**
7158 * Multiply 64 bit by 64 bit first loop.
7159 */
7160 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7161 Register y, Register y_idx, Register z,
7162 Register carry, Register product,
7163 Register idx, Register kdx) {
7164 //
7165 // jlong carry, x[], y[], z[];
7166 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7167 // huge_128 product = y[idx] * x[xstart] + carry;
7168 // z[kdx] = (jlong)product;
7169 // carry = (jlong)(product >>> 64);
7170 // }
7171 // z[xstart] = carry;
7172 //
7173
7174 Label L_first_loop, L_first_loop_exit;
7175 Label L_one_x, L_one_y, L_multiply;
7176
7177 decrementl(xstart);
7178 jcc(Assembler::negative, L_one_x);
7179
7180 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7181 rorq(x_xstart, 32); // convert big-endian to little-endian
7182
7183 bind(L_first_loop);
7184 decrementl(idx);
7185 jcc(Assembler::negative, L_first_loop_exit);
7186 decrementl(idx);
7187 jcc(Assembler::negative, L_one_y);
7188 movq(y_idx, Address(y, idx, Address::times_4, 0));
7189 rorq(y_idx, 32); // convert big-endian to little-endian
7190 bind(L_multiply);
7191 movq(product, x_xstart);
7192 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7193 addq(product, carry);
7194 adcq(rdx, 0);
7195 subl(kdx, 2);
7196 movl(Address(z, kdx, Address::times_4, 4), product);
7197 shrq(product, 32);
7198 movl(Address(z, kdx, Address::times_4, 0), product);
7199 movq(carry, rdx);
7200 jmp(L_first_loop);
7201
7202 bind(L_one_y);
7203 movl(y_idx, Address(y, 0));
7204 jmp(L_multiply);
7205
7206 bind(L_one_x);
7207 movl(x_xstart, Address(x, 0));
7208 jmp(L_first_loop);
7209
7210 bind(L_first_loop_exit);
7211 }
7212
7213 /**
7214 * Multiply 64 bit by 64 bit and add 128 bit.
7215 */
7216 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7217 Register yz_idx, Register idx,
7218 Register carry, Register product, int offset) {
7219 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7220 // z[kdx] = (jlong)product;
7221
7222 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7223 rorq(yz_idx, 32); // convert big-endian to little-endian
7224 movq(product, x_xstart);
7225 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7226 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7227 rorq(yz_idx, 32); // convert big-endian to little-endian
7228
7229 add2_with_carry(rdx, product, carry, yz_idx);
7230
7231 movl(Address(z, idx, Address::times_4, offset+4), product);
7232 shrq(product, 32);
7233 movl(Address(z, idx, Address::times_4, offset), product);
7234
7235 }
7236
7237 /**
7238 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7239 */
7240 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7241 Register yz_idx, Register idx, Register jdx,
7242 Register carry, Register product,
7243 Register carry2) {
7244 // jlong carry, x[], y[], z[];
7245 // int kdx = ystart+1;
7246 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7247 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7248 // z[kdx+idx+1] = (jlong)product;
7249 // jlong carry2 = (jlong)(product >>> 64);
7250 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7251 // z[kdx+idx] = (jlong)product;
7252 // carry = (jlong)(product >>> 64);
7253 // }
7254 // idx += 2;
7255 // if (idx > 0) {
7256 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7257 // z[kdx+idx] = (jlong)product;
7258 // carry = (jlong)(product >>> 64);
7259 // }
7260 //
7261
7262 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7263
7264 movl(jdx, idx);
7265 andl(jdx, 0xFFFFFFFC);
7266 shrl(jdx, 2);
7267
7268 bind(L_third_loop);
7269 subl(jdx, 1);
7270 jcc(Assembler::negative, L_third_loop_exit);
7271 subl(idx, 4);
7272
7273 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7274 movq(carry2, rdx);
7275
7276 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7277 movq(carry, rdx);
7278 jmp(L_third_loop);
7279
7280 bind (L_third_loop_exit);
7281
7282 andl (idx, 0x3);
7283 jcc(Assembler::zero, L_post_third_loop_done);
7284
7285 Label L_check_1;
7286 subl(idx, 2);
7287 jcc(Assembler::negative, L_check_1);
7288
7289 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7290 movq(carry, rdx);
7291
7292 bind (L_check_1);
7293 addl (idx, 0x2);
7294 andl (idx, 0x1);
7295 subl(idx, 1);
7296 jcc(Assembler::negative, L_post_third_loop_done);
7297
7298 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7299 movq(product, x_xstart);
7300 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7301 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7302
7303 add2_with_carry(rdx, product, yz_idx, carry);
7304
7305 movl(Address(z, idx, Address::times_4, 0), product);
7306 shrq(product, 32);
7307
7308 shlq(rdx, 32);
7309 orq(product, rdx);
7310 movq(carry, product);
7311
7312 bind(L_post_third_loop_done);
7313 }
7314
7315 /**
7316 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7317 *
7318 */
7319 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7320 Register carry, Register carry2,
7321 Register idx, Register jdx,
7322 Register yz_idx1, Register yz_idx2,
7323 Register tmp, Register tmp3, Register tmp4) {
7324 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7325
7326 // jlong carry, x[], y[], z[];
7327 // int kdx = ystart+1;
7328 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7329 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7330 // jlong carry2 = (jlong)(tmp3 >>> 64);
7331 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7332 // carry = (jlong)(tmp4 >>> 64);
7333 // z[kdx+idx+1] = (jlong)tmp3;
7334 // z[kdx+idx] = (jlong)tmp4;
7335 // }
7336 // idx += 2;
7337 // if (idx > 0) {
7338 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7339 // z[kdx+idx] = (jlong)yz_idx1;
7340 // carry = (jlong)(yz_idx1 >>> 64);
7341 // }
7342 //
7343
7344 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7345
7346 movl(jdx, idx);
7347 andl(jdx, 0xFFFFFFFC);
7348 shrl(jdx, 2);
7349
7350 bind(L_third_loop);
7351 subl(jdx, 1);
7352 jcc(Assembler::negative, L_third_loop_exit);
7353 subl(idx, 4);
7354
7355 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7356 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7357 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7358 rorxq(yz_idx2, yz_idx2, 32);
7359
7360 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7361 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7362
7363 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7364 rorxq(yz_idx1, yz_idx1, 32);
7365 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7366 rorxq(yz_idx2, yz_idx2, 32);
7367
7368 if (VM_Version::supports_adx()) {
7369 adcxq(tmp3, carry);
7370 adoxq(tmp3, yz_idx1);
7371
7372 adcxq(tmp4, tmp);
7373 adoxq(tmp4, yz_idx2);
7374
7375 movl(carry, 0); // does not affect flags
7376 adcxq(carry2, carry);
7377 adoxq(carry2, carry);
7378 } else {
7379 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7380 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7381 }
7382 movq(carry, carry2);
7383
7384 movl(Address(z, idx, Address::times_4, 12), tmp3);
7385 shrq(tmp3, 32);
7386 movl(Address(z, idx, Address::times_4, 8), tmp3);
7387
7388 movl(Address(z, idx, Address::times_4, 4), tmp4);
7389 shrq(tmp4, 32);
7390 movl(Address(z, idx, Address::times_4, 0), tmp4);
7391
7392 jmp(L_third_loop);
7393
7394 bind (L_third_loop_exit);
7395
7396 andl (idx, 0x3);
7397 jcc(Assembler::zero, L_post_third_loop_done);
7398
7399 Label L_check_1;
7400 subl(idx, 2);
7401 jcc(Assembler::negative, L_check_1);
7402
7403 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7404 rorxq(yz_idx1, yz_idx1, 32);
7405 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7406 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7407 rorxq(yz_idx2, yz_idx2, 32);
7408
7409 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7410
7411 movl(Address(z, idx, Address::times_4, 4), tmp3);
7412 shrq(tmp3, 32);
7413 movl(Address(z, idx, Address::times_4, 0), tmp3);
7414 movq(carry, tmp4);
7415
7416 bind (L_check_1);
7417 addl (idx, 0x2);
7418 andl (idx, 0x1);
7419 subl(idx, 1);
7420 jcc(Assembler::negative, L_post_third_loop_done);
7421 movl(tmp4, Address(y, idx, Address::times_4, 0));
7422 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7423 movl(tmp4, Address(z, idx, Address::times_4, 0));
7424
7425 add2_with_carry(carry2, tmp3, tmp4, carry);
7426
7427 movl(Address(z, idx, Address::times_4, 0), tmp3);
7428 shrq(tmp3, 32);
7429
7430 shlq(carry2, 32);
7431 orq(tmp3, carry2);
7432 movq(carry, tmp3);
7433
7434 bind(L_post_third_loop_done);
7435 }
7436
7437 /**
7438 * Code for BigInteger::multiplyToLen() intrinsic.
7439 *
7440 * rdi: x
7441 * rax: xlen
7442 * rsi: y
7443 * rcx: ylen
7444 * r8: z
7445 * r11: tmp0
7446 * r12: tmp1
7447 * r13: tmp2
7448 * r14: tmp3
7449 * r15: tmp4
7450 * rbx: tmp5
7451 *
7452 */
7453 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7454 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7455 ShortBranchVerifier sbv(this);
7456 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7457
7458 push(tmp0);
7459 push(tmp1);
7460 push(tmp2);
7461 push(tmp3);
7462 push(tmp4);
7463 push(tmp5);
7464
7465 push(xlen);
7466
7467 const Register idx = tmp1;
7468 const Register kdx = tmp2;
7469 const Register xstart = tmp3;
7470
7471 const Register y_idx = tmp4;
7472 const Register carry = tmp5;
7473 const Register product = xlen;
7474 const Register x_xstart = tmp0;
7475
7476 // First Loop.
7477 //
7478 // final static long LONG_MASK = 0xffffffffL;
7479 // int xstart = xlen - 1;
7480 // int ystart = ylen - 1;
7481 // long carry = 0;
7482 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7483 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7484 // z[kdx] = (int)product;
7485 // carry = product >>> 32;
7486 // }
7487 // z[xstart] = (int)carry;
7488 //
7489
7490 movl(idx, ylen); // idx = ylen;
7491 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7492 xorq(carry, carry); // carry = 0;
7493
7494 Label L_done;
7495
7496 movl(xstart, xlen);
7497 decrementl(xstart);
7498 jcc(Assembler::negative, L_done);
7499
7500 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7501
7502 Label L_second_loop;
7503 testl(kdx, kdx);
7504 jcc(Assembler::zero, L_second_loop);
7505
7506 Label L_carry;
7507 subl(kdx, 1);
7508 jcc(Assembler::zero, L_carry);
7509
7510 movl(Address(z, kdx, Address::times_4, 0), carry);
7511 shrq(carry, 32);
7512 subl(kdx, 1);
7513
7514 bind(L_carry);
7515 movl(Address(z, kdx, Address::times_4, 0), carry);
7516
7517 // Second and third (nested) loops.
7518 //
7519 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7520 // carry = 0;
7521 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7522 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7523 // (z[k] & LONG_MASK) + carry;
7524 // z[k] = (int)product;
7525 // carry = product >>> 32;
7526 // }
7527 // z[i] = (int)carry;
7528 // }
7529 //
7530 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7531
7532 const Register jdx = tmp1;
7533
7534 bind(L_second_loop);
7535 xorl(carry, carry); // carry = 0;
7536 movl(jdx, ylen); // j = ystart+1
7537
7538 subl(xstart, 1); // i = xstart-1;
7539 jcc(Assembler::negative, L_done);
7540
7541 push (z);
7542
7543 Label L_last_x;
7544 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7545 subl(xstart, 1); // i = xstart-1;
7546 jcc(Assembler::negative, L_last_x);
7547
7548 if (UseBMI2Instructions) {
7549 movq(rdx, Address(x, xstart, Address::times_4, 0));
7550 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7551 } else {
7552 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7553 rorq(x_xstart, 32); // convert big-endian to little-endian
7554 }
7555
7556 Label L_third_loop_prologue;
7557 bind(L_third_loop_prologue);
7558
7559 push (x);
7560 push (xstart);
7561 push (ylen);
7562
7563
7564 if (UseBMI2Instructions) {
7565 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7566 } else { // !UseBMI2Instructions
7567 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7568 }
7569
7570 pop(ylen);
7571 pop(xlen);
7572 pop(x);
7573 pop(z);
7574
7575 movl(tmp3, xlen);
7576 addl(tmp3, 1);
7577 movl(Address(z, tmp3, Address::times_4, 0), carry);
7578 subl(tmp3, 1);
7579 jccb(Assembler::negative, L_done);
7580
7581 shrq(carry, 32);
7582 movl(Address(z, tmp3, Address::times_4, 0), carry);
7583 jmp(L_second_loop);
7584
7585 // Next infrequent code is moved outside loops.
7586 bind(L_last_x);
7587 if (UseBMI2Instructions) {
7588 movl(rdx, Address(x, 0));
7589 } else {
7590 movl(x_xstart, Address(x, 0));
7591 }
7592 jmp(L_third_loop_prologue);
7593
7594 bind(L_done);
7595
7596 pop(xlen);
7597
7598 pop(tmp5);
7599 pop(tmp4);
7600 pop(tmp3);
7601 pop(tmp2);
7602 pop(tmp1);
7603 pop(tmp0);
7604 }
7605
7606 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7607 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7608 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7609 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7610 Label VECTOR8_TAIL, VECTOR4_TAIL;
7611 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7612 Label SAME_TILL_END, DONE;
7613 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7614
7615 //scale is in rcx in both Win64 and Unix
7616 ShortBranchVerifier sbv(this);
7617
7618 shlq(length);
7619 xorq(result, result);
7620
7621 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7622 VM_Version::supports_avx512vlbw() && UseCountTrailingZerosInstruction) {
7623 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7624
7625 cmpq(length, 64);
7626 jcc(Assembler::less, VECTOR32_TAIL);
7627
7628 movq(tmp1, length);
7629 andq(tmp1, 0x3F); // tail count
7630 andq(length, ~(0x3F)); //vector count
7631
7632 bind(VECTOR64_LOOP);
7633 // AVX512 code to compare 64 byte vectors.
7634 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7635 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7636 kortestql(k7, k7);
7637 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7638 addq(result, 64);
7639 subq(length, 64);
7640 jccb(Assembler::notZero, VECTOR64_LOOP);
7641
7642 //bind(VECTOR64_TAIL);
7643 testq(tmp1, tmp1);
7644 jcc(Assembler::zero, SAME_TILL_END);
7645
7646 //bind(VECTOR64_TAIL);
7647 // AVX512 code to compare up to 63 byte vectors.
7648 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7649 shlxq(tmp2, tmp2, tmp1);
7650 notq(tmp2);
7651 kmovql(k3, tmp2);
7652
7653 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7654 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7655
7656 ktestql(k7, k3);
7657 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7658
7659 bind(VECTOR64_NOT_EQUAL);
7660 kmovql(tmp1, k7);
7661 notq(tmp1);
7662 tzcntq(tmp1, tmp1);
7663 addq(result, tmp1);
7664 shrq(result);
7665 jmp(DONE);
7666 bind(VECTOR32_TAIL);
7667 }
7668
7669 cmpq(length, 8);
7670 jcc(Assembler::equal, VECTOR8_LOOP);
7671 jcc(Assembler::less, VECTOR4_TAIL);
7672
7673 if (UseAVX >= 2) {
7674 Label VECTOR16_TAIL, VECTOR32_LOOP;
7675
7676 cmpq(length, 16);
7677 jcc(Assembler::equal, VECTOR16_LOOP);
7678 jcc(Assembler::less, VECTOR8_LOOP);
7679
7680 cmpq(length, 32);
7681 jccb(Assembler::less, VECTOR16_TAIL);
7682
7683 subq(length, 32);
7684 bind(VECTOR32_LOOP);
7685 vmovdqu(rymm0, Address(obja, result));
7686 vmovdqu(rymm1, Address(objb, result));
7687 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7688 vptest(rymm2, rymm2);
7689 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7690 addq(result, 32);
7691 subq(length, 32);
7692 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7693 addq(length, 32);
7694 jcc(Assembler::equal, SAME_TILL_END);
7695 //falling through if less than 32 bytes left //close the branch here.
7696
7697 bind(VECTOR16_TAIL);
7698 cmpq(length, 16);
7699 jccb(Assembler::less, VECTOR8_TAIL);
7700 bind(VECTOR16_LOOP);
7701 movdqu(rymm0, Address(obja, result));
7702 movdqu(rymm1, Address(objb, result));
7703 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7704 ptest(rymm2, rymm2);
7705 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7706 addq(result, 16);
7707 subq(length, 16);
7708 jcc(Assembler::equal, SAME_TILL_END);
7709 //falling through if less than 16 bytes left
7710 } else {//regular intrinsics
7711
7712 cmpq(length, 16);
7713 jccb(Assembler::less, VECTOR8_TAIL);
7714
7715 subq(length, 16);
7716 bind(VECTOR16_LOOP);
7717 movdqu(rymm0, Address(obja, result));
7718 movdqu(rymm1, Address(objb, result));
7719 pxor(rymm0, rymm1);
7720 ptest(rymm0, rymm0);
7721 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7722 addq(result, 16);
7723 subq(length, 16);
7724 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7725 addq(length, 16);
7726 jcc(Assembler::equal, SAME_TILL_END);
7727 //falling through if less than 16 bytes left
7728 }
7729
7730 bind(VECTOR8_TAIL);
7731 cmpq(length, 8);
7732 jccb(Assembler::less, VECTOR4_TAIL);
7733 bind(VECTOR8_LOOP);
7734 movq(tmp1, Address(obja, result));
7735 movq(tmp2, Address(objb, result));
7736 xorq(tmp1, tmp2);
7737 testq(tmp1, tmp1);
7738 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7739 addq(result, 8);
7740 subq(length, 8);
7741 jcc(Assembler::equal, SAME_TILL_END);
7742 //falling through if less than 8 bytes left
7743
7744 bind(VECTOR4_TAIL);
7745 cmpq(length, 4);
7746 jccb(Assembler::less, BYTES_TAIL);
7747 bind(VECTOR4_LOOP);
7748 movl(tmp1, Address(obja, result));
7749 xorl(tmp1, Address(objb, result));
7750 testl(tmp1, tmp1);
7751 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7752 addq(result, 4);
7753 subq(length, 4);
7754 jcc(Assembler::equal, SAME_TILL_END);
7755 //falling through if less than 4 bytes left
7756
7757 bind(BYTES_TAIL);
7758 bind(BYTES_LOOP);
7759 load_unsigned_byte(tmp1, Address(obja, result));
7760 load_unsigned_byte(tmp2, Address(objb, result));
7761 xorl(tmp1, tmp2);
7762 testl(tmp1, tmp1);
7763 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7764 decq(length);
7765 jcc(Assembler::zero, SAME_TILL_END);
7766 incq(result);
7767 load_unsigned_byte(tmp1, Address(obja, result));
7768 load_unsigned_byte(tmp2, Address(objb, result));
7769 xorl(tmp1, tmp2);
7770 testl(tmp1, tmp1);
7771 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7772 decq(length);
7773 jcc(Assembler::zero, SAME_TILL_END);
7774 incq(result);
7775 load_unsigned_byte(tmp1, Address(obja, result));
7776 load_unsigned_byte(tmp2, Address(objb, result));
7777 xorl(tmp1, tmp2);
7778 testl(tmp1, tmp1);
7779 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7780 jmp(SAME_TILL_END);
7781
7782 if (UseAVX >= 2) {
7783 bind(VECTOR32_NOT_EQUAL);
7784 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7785 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7786 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7787 vpmovmskb(tmp1, rymm0);
7788 bsfq(tmp1, tmp1);
7789 addq(result, tmp1);
7790 shrq(result);
7791 jmp(DONE);
7792 }
7793
7794 bind(VECTOR16_NOT_EQUAL);
7795 if (UseAVX >= 2) {
7796 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7797 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7798 pxor(rymm0, rymm2);
7799 } else {
7800 pcmpeqb(rymm2, rymm2);
7801 pxor(rymm0, rymm1);
7802 pcmpeqb(rymm0, rymm1);
7803 pxor(rymm0, rymm2);
7804 }
7805 pmovmskb(tmp1, rymm0);
7806 bsfq(tmp1, tmp1);
7807 addq(result, tmp1);
7808 shrq(result);
7809 jmpb(DONE);
7810
7811 bind(VECTOR8_NOT_EQUAL);
7812 bind(VECTOR4_NOT_EQUAL);
7813 bsfq(tmp1, tmp1);
7814 shrq(tmp1, 3);
7815 addq(result, tmp1);
7816 bind(BYTES_NOT_EQUAL);
7817 shrq(result);
7818 jmpb(DONE);
7819
7820 bind(SAME_TILL_END);
7821 mov64(result, -1);
7822
7823 bind(DONE);
7824 }
7825
7826 //Helper functions for square_to_len()
7827
7828 /**
7829 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7830 * Preserves x and z and modifies rest of the registers.
7831 */
7832 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7833 // Perform square and right shift by 1
7834 // Handle odd xlen case first, then for even xlen do the following
7835 // jlong carry = 0;
7836 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7837 // huge_128 product = x[j:j+1] * x[j:j+1];
7838 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7839 // z[i+2:i+3] = (jlong)(product >>> 1);
7840 // carry = (jlong)product;
7841 // }
7842
7843 xorq(tmp5, tmp5); // carry
7844 xorq(rdxReg, rdxReg);
7845 xorl(tmp1, tmp1); // index for x
7846 xorl(tmp4, tmp4); // index for z
7847
7848 Label L_first_loop, L_first_loop_exit;
7849
7850 testl(xlen, 1);
7851 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7852
7853 // Square and right shift by 1 the odd element using 32 bit multiply
7854 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7855 imulq(raxReg, raxReg);
7856 shrq(raxReg, 1);
7857 adcq(tmp5, 0);
7858 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7859 incrementl(tmp1);
7860 addl(tmp4, 2);
7861
7862 // Square and right shift by 1 the rest using 64 bit multiply
7863 bind(L_first_loop);
7864 cmpptr(tmp1, xlen);
7865 jccb(Assembler::equal, L_first_loop_exit);
7866
7867 // Square
7868 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7869 rorq(raxReg, 32); // convert big-endian to little-endian
7870 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7871
7872 // Right shift by 1 and save carry
7873 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7874 rcrq(rdxReg, 1);
7875 rcrq(raxReg, 1);
7876 adcq(tmp5, 0);
7877
7878 // Store result in z
7879 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7880 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7881
7882 // Update indices for x and z
7883 addl(tmp1, 2);
7884 addl(tmp4, 4);
7885 jmp(L_first_loop);
7886
7887 bind(L_first_loop_exit);
7888 }
7889
7890
7891 /**
7892 * Perform the following multiply add operation using BMI2 instructions
7893 * carry:sum = sum + op1*op2 + carry
7894 * op2 should be in rdx
7895 * op2 is preserved, all other registers are modified
7896 */
7897 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7898 // assert op2 is rdx
7899 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7900 addq(sum, carry);
7901 adcq(tmp2, 0);
7902 addq(sum, op1);
7903 adcq(tmp2, 0);
7904 movq(carry, tmp2);
7905 }
7906
7907 /**
7908 * Perform the following multiply add operation:
7909 * carry:sum = sum + op1*op2 + carry
7910 * Preserves op1, op2 and modifies rest of registers
7911 */
7912 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7913 // rdx:rax = op1 * op2
7914 movq(raxReg, op2);
7915 mulq(op1);
7916
7917 // rdx:rax = sum + carry + rdx:rax
7918 addq(sum, carry);
7919 adcq(rdxReg, 0);
7920 addq(sum, raxReg);
7921 adcq(rdxReg, 0);
7922
7923 // carry:sum = rdx:sum
7924 movq(carry, rdxReg);
7925 }
7926
7927 /**
7928 * Add 64 bit long carry into z[] with carry propagation.
7929 * Preserves z and carry register values and modifies rest of registers.
7930 *
7931 */
7932 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7933 Label L_fourth_loop, L_fourth_loop_exit;
7934
7935 movl(tmp1, 1);
7936 subl(zlen, 2);
7937 addq(Address(z, zlen, Address::times_4, 0), carry);
7938
7939 bind(L_fourth_loop);
7940 jccb(Assembler::carryClear, L_fourth_loop_exit);
7941 subl(zlen, 2);
7942 jccb(Assembler::negative, L_fourth_loop_exit);
7943 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7944 jmp(L_fourth_loop);
7945 bind(L_fourth_loop_exit);
7946 }
7947
7948 /**
7949 * Shift z[] left by 1 bit.
7950 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7951 *
7952 */
7953 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7954
7955 Label L_fifth_loop, L_fifth_loop_exit;
7956
7957 // Fifth loop
7958 // Perform primitiveLeftShift(z, zlen, 1)
7959
7960 const Register prev_carry = tmp1;
7961 const Register new_carry = tmp4;
7962 const Register value = tmp2;
7963 const Register zidx = tmp3;
7964
7965 // int zidx, carry;
7966 // long value;
7967 // carry = 0;
7968 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7969 // (carry:value) = (z[i] << 1) | carry ;
7970 // z[i] = value;
7971 // }
7972
7973 movl(zidx, zlen);
7974 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7975
7976 bind(L_fifth_loop);
7977 decl(zidx); // Use decl to preserve carry flag
7978 decl(zidx);
7979 jccb(Assembler::negative, L_fifth_loop_exit);
7980
7981 if (UseBMI2Instructions) {
7982 movq(value, Address(z, zidx, Address::times_4, 0));
7983 rclq(value, 1);
7984 rorxq(value, value, 32);
7985 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7986 }
7987 else {
7988 // clear new_carry
7989 xorl(new_carry, new_carry);
7990
7991 // Shift z[i] by 1, or in previous carry and save new carry
7992 movq(value, Address(z, zidx, Address::times_4, 0));
7993 shlq(value, 1);
7994 adcl(new_carry, 0);
7995
7996 orq(value, prev_carry);
7997 rorq(value, 0x20);
7998 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7999
8000 // Set previous carry = new carry
8001 movl(prev_carry, new_carry);
8002 }
8003 jmp(L_fifth_loop);
8004
8005 bind(L_fifth_loop_exit);
8006 }
8007
8008
8009 /**
8010 * Code for BigInteger::squareToLen() intrinsic
8011 *
8012 * rdi: x
8013 * rsi: len
8014 * r8: z
8015 * rcx: zlen
8016 * r12: tmp1
8017 * r13: tmp2
8018 * r14: tmp3
8019 * r15: tmp4
8020 * rbx: tmp5
8021 *
8022 */
8023 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8024
8025 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8026 push(tmp1);
8027 push(tmp2);
8028 push(tmp3);
8029 push(tmp4);
8030 push(tmp5);
8031
8032 // First loop
8033 // Store the squares, right shifted one bit (i.e., divided by 2).
8034 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8035
8036 // Add in off-diagonal sums.
8037 //
8038 // Second, third (nested) and fourth loops.
8039 // zlen +=2;
8040 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8041 // carry = 0;
8042 // long op2 = x[xidx:xidx+1];
8043 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8044 // k -= 2;
8045 // long op1 = x[j:j+1];
8046 // long sum = z[k:k+1];
8047 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8048 // z[k:k+1] = sum;
8049 // }
8050 // add_one_64(z, k, carry, tmp_regs);
8051 // }
8052
8053 const Register carry = tmp5;
8054 const Register sum = tmp3;
8055 const Register op1 = tmp4;
8056 Register op2 = tmp2;
8057
8058 push(zlen);
8059 push(len);
8060 addl(zlen,2);
8061 bind(L_second_loop);
8062 xorq(carry, carry);
8063 subl(zlen, 4);
8064 subl(len, 2);
8065 push(zlen);
8066 push(len);
8067 cmpl(len, 0);
8068 jccb(Assembler::lessEqual, L_second_loop_exit);
8069
8070 // Multiply an array by one 64 bit long.
8071 if (UseBMI2Instructions) {
8072 op2 = rdxReg;
8073 movq(op2, Address(x, len, Address::times_4, 0));
8074 rorxq(op2, op2, 32);
8075 }
8076 else {
8077 movq(op2, Address(x, len, Address::times_4, 0));
8078 rorq(op2, 32);
8079 }
8080
8081 bind(L_third_loop);
8082 decrementl(len);
8083 jccb(Assembler::negative, L_third_loop_exit);
8084 decrementl(len);
8085 jccb(Assembler::negative, L_last_x);
8086
8087 movq(op1, Address(x, len, Address::times_4, 0));
8088 rorq(op1, 32);
8089
8090 bind(L_multiply);
8091 subl(zlen, 2);
8092 movq(sum, Address(z, zlen, Address::times_4, 0));
8093
8094 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8095 if (UseBMI2Instructions) {
8096 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8097 }
8098 else {
8099 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8100 }
8101
8102 movq(Address(z, zlen, Address::times_4, 0), sum);
8103
8104 jmp(L_third_loop);
8105 bind(L_third_loop_exit);
8106
8107 // Fourth loop
8108 // Add 64 bit long carry into z with carry propagation.
8109 // Uses offsetted zlen.
8110 add_one_64(z, zlen, carry, tmp1);
8111
8112 pop(len);
8113 pop(zlen);
8114 jmp(L_second_loop);
8115
8116 // Next infrequent code is moved outside loops.
8117 bind(L_last_x);
8118 movl(op1, Address(x, 0));
8119 jmp(L_multiply);
8120
8121 bind(L_second_loop_exit);
8122 pop(len);
8123 pop(zlen);
8124 pop(len);
8125 pop(zlen);
8126
8127 // Fifth loop
8128 // Shift z left 1 bit.
8129 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8130
8131 // z[zlen-1] |= x[len-1] & 1;
8132 movl(tmp3, Address(x, len, Address::times_4, -4));
8133 andl(tmp3, 1);
8134 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8135
8136 pop(tmp5);
8137 pop(tmp4);
8138 pop(tmp3);
8139 pop(tmp2);
8140 pop(tmp1);
8141 }
8142
8143 /**
8144 * Helper function for mul_add()
8145 * Multiply the in[] by int k and add to out[] starting at offset offs using
8146 * 128 bit by 32 bit multiply and return the carry in tmp5.
8147 * Only quad int aligned length of in[] is operated on in this function.
8148 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8149 * This function preserves out, in and k registers.
8150 * len and offset point to the appropriate index in "in" & "out" correspondingly
8151 * tmp5 has the carry.
8152 * other registers are temporary and are modified.
8153 *
8154 */
8155 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8156 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8157 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8158
8159 Label L_first_loop, L_first_loop_exit;
8160
8161 movl(tmp1, len);
8162 shrl(tmp1, 2);
8163
8164 bind(L_first_loop);
8165 subl(tmp1, 1);
8166 jccb(Assembler::negative, L_first_loop_exit);
8167
8168 subl(len, 4);
8169 subl(offset, 4);
8170
8171 Register op2 = tmp2;
8172 const Register sum = tmp3;
8173 const Register op1 = tmp4;
8174 const Register carry = tmp5;
8175
8176 if (UseBMI2Instructions) {
8177 op2 = rdxReg;
8178 }
8179
8180 movq(op1, Address(in, len, Address::times_4, 8));
8181 rorq(op1, 32);
8182 movq(sum, Address(out, offset, Address::times_4, 8));
8183 rorq(sum, 32);
8184 if (UseBMI2Instructions) {
8185 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8186 }
8187 else {
8188 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8189 }
8190 // Store back in big endian from little endian
8191 rorq(sum, 0x20);
8192 movq(Address(out, offset, Address::times_4, 8), sum);
8193
8194 movq(op1, Address(in, len, Address::times_4, 0));
8195 rorq(op1, 32);
8196 movq(sum, Address(out, offset, Address::times_4, 0));
8197 rorq(sum, 32);
8198 if (UseBMI2Instructions) {
8199 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8200 }
8201 else {
8202 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8203 }
8204 // Store back in big endian from little endian
8205 rorq(sum, 0x20);
8206 movq(Address(out, offset, Address::times_4, 0), sum);
8207
8208 jmp(L_first_loop);
8209 bind(L_first_loop_exit);
8210 }
8211
8212 /**
8213 * Code for BigInteger::mulAdd() intrinsic
8214 *
8215 * rdi: out
8216 * rsi: in
8217 * r11: offs (out.length - offset)
8218 * rcx: len
8219 * r8: k
8220 * r12: tmp1
8221 * r13: tmp2
8222 * r14: tmp3
8223 * r15: tmp4
8224 * rbx: tmp5
8225 * Multiply the in[] by word k and add to out[], return the carry in rax
8226 */
8227 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8228 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8229 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8230
8231 Label L_carry, L_last_in, L_done;
8232
8233 // carry = 0;
8234 // for (int j=len-1; j >= 0; j--) {
8235 // long product = (in[j] & LONG_MASK) * kLong +
8236 // (out[offs] & LONG_MASK) + carry;
8237 // out[offs--] = (int)product;
8238 // carry = product >>> 32;
8239 // }
8240 //
8241 push(tmp1);
8242 push(tmp2);
8243 push(tmp3);
8244 push(tmp4);
8245 push(tmp5);
8246
8247 Register op2 = tmp2;
8248 const Register sum = tmp3;
8249 const Register op1 = tmp4;
8250 const Register carry = tmp5;
8251
8252 if (UseBMI2Instructions) {
8253 op2 = rdxReg;
8254 movl(op2, k);
8255 }
8256 else {
8257 movl(op2, k);
8258 }
8259
8260 xorq(carry, carry);
8261
8262 //First loop
8263
8264 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8265 //The carry is in tmp5
8266 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8267
8268 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8269 decrementl(len);
8270 jccb(Assembler::negative, L_carry);
8271 decrementl(len);
8272 jccb(Assembler::negative, L_last_in);
8273
8274 movq(op1, Address(in, len, Address::times_4, 0));
8275 rorq(op1, 32);
8276
8277 subl(offs, 2);
8278 movq(sum, Address(out, offs, Address::times_4, 0));
8279 rorq(sum, 32);
8280
8281 if (UseBMI2Instructions) {
8282 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8283 }
8284 else {
8285 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8286 }
8287
8288 // Store back in big endian from little endian
8289 rorq(sum, 0x20);
8290 movq(Address(out, offs, Address::times_4, 0), sum);
8291
8292 testl(len, len);
8293 jccb(Assembler::zero, L_carry);
8294
8295 //Multiply the last in[] entry, if any
8296 bind(L_last_in);
8297 movl(op1, Address(in, 0));
8298 movl(sum, Address(out, offs, Address::times_4, -4));
8299
8300 movl(raxReg, k);
8301 mull(op1); //tmp4 * eax -> edx:eax
8302 addl(sum, carry);
8303 adcl(rdxReg, 0);
8304 addl(sum, raxReg);
8305 adcl(rdxReg, 0);
8306 movl(carry, rdxReg);
8307
8308 movl(Address(out, offs, Address::times_4, -4), sum);
8309
8310 bind(L_carry);
8311 //return tmp5/carry as carry in rax
8312 movl(rax, carry);
8313
8314 bind(L_done);
8315 pop(tmp5);
8316 pop(tmp4);
8317 pop(tmp3);
8318 pop(tmp2);
8319 pop(tmp1);
8320 }
8321
8322 /**
8323 * Emits code to update CRC-32 with a byte value according to constants in table
8324 *
8325 * @param [in,out]crc Register containing the crc.
8326 * @param [in]val Register containing the byte to fold into the CRC.
8327 * @param [in]table Register containing the table of crc constants.
8328 *
8329 * uint32_t crc;
8330 * val = crc_table[(val ^ crc) & 0xFF];
8331 * crc = val ^ (crc >> 8);
8332 *
8333 */
8334 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8335 xorl(val, crc);
8336 andl(val, 0xFF);
8337 shrl(crc, 8); // unsigned shift
8338 xorl(crc, Address(table, val, Address::times_4, 0));
8339 }
8340
8341 /**
8342 * Fold 128-bit data chunk
8343 */
8344 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8345 if (UseAVX > 0) {
8346 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8347 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8348 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8349 pxor(xcrc, xtmp);
8350 } else {
8351 movdqa(xtmp, xcrc);
8352 pclmulhdq(xtmp, xK); // [123:64]
8353 pclmulldq(xcrc, xK); // [63:0]
8354 pxor(xcrc, xtmp);
8355 movdqu(xtmp, Address(buf, offset));
8356 pxor(xcrc, xtmp);
8357 }
8358 }
8359
8360 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8361 if (UseAVX > 0) {
8362 vpclmulhdq(xtmp, xK, xcrc);
8363 vpclmulldq(xcrc, xK, xcrc);
8364 pxor(xcrc, xbuf);
8365 pxor(xcrc, xtmp);
8366 } else {
8367 movdqa(xtmp, xcrc);
8368 pclmulhdq(xtmp, xK);
8369 pclmulldq(xcrc, xK);
8370 pxor(xcrc, xbuf);
8371 pxor(xcrc, xtmp);
8372 }
8373 }
8374
8375 /**
8376 * 8-bit folds to compute 32-bit CRC
8377 *
8378 * uint64_t xcrc;
8379 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8380 */
8381 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8382 movdl(tmp, xcrc);
8383 andl(tmp, 0xFF);
8384 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8385 psrldq(xcrc, 1); // unsigned shift one byte
8386 pxor(xcrc, xtmp);
8387 }
8388
8389 /**
8390 * uint32_t crc;
8391 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8392 */
8393 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8394 movl(tmp, crc);
8395 andl(tmp, 0xFF);
8396 shrl(crc, 8);
8397 xorl(crc, Address(table, tmp, Address::times_4, 0));
8398 }
8399
8400 /**
8401 * @param crc register containing existing CRC (32-bit)
8402 * @param buf register pointing to input byte buffer (byte*)
8403 * @param len register containing number of bytes
8404 * @param table register that will contain address of CRC table
8405 * @param tmp scratch register
8406 */
8407 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8408 assert_different_registers(crc, buf, len, table, tmp, rax);
8409
8410 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8411 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8412
8413 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8414 // context for the registers used, where all instructions below are using 128-bit mode
8415 // On EVEX without VL and BW, these instructions will all be AVX.
8416 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8417 notl(crc); // ~crc
8418 cmpl(len, 16);
8419 jcc(Assembler::less, L_tail);
8420
8421 // Align buffer to 16 bytes
8422 movl(tmp, buf);
8423 andl(tmp, 0xF);
8424 jccb(Assembler::zero, L_aligned);
8425 subl(tmp, 16);
8426 addl(len, tmp);
8427
8428 align(4);
8429 BIND(L_align_loop);
8430 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8431 update_byte_crc32(crc, rax, table);
8432 increment(buf);
8433 incrementl(tmp);
8434 jccb(Assembler::less, L_align_loop);
8435
8436 BIND(L_aligned);
8437 movl(tmp, len); // save
8438 shrl(len, 4);
8439 jcc(Assembler::zero, L_tail_restore);
8440
8441 // Fold crc into first bytes of vector
8442 movdqa(xmm1, Address(buf, 0));
8443 movdl(rax, xmm1);
8444 xorl(crc, rax);
8445 if (VM_Version::supports_sse4_1()) {
8446 pinsrd(xmm1, crc, 0);
8447 } else {
8448 pinsrw(xmm1, crc, 0);
8449 shrl(crc, 16);
8450 pinsrw(xmm1, crc, 1);
8451 }
8452 addptr(buf, 16);
8453 subl(len, 4); // len > 0
8454 jcc(Assembler::less, L_fold_tail);
8455
8456 movdqa(xmm2, Address(buf, 0));
8457 movdqa(xmm3, Address(buf, 16));
8458 movdqa(xmm4, Address(buf, 32));
8459 addptr(buf, 48);
8460 subl(len, 3);
8461 jcc(Assembler::lessEqual, L_fold_512b);
8462
8463 // Fold total 512 bits of polynomial on each iteration,
8464 // 128 bits per each of 4 parallel streams.
8465 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8466
8467 align32();
8468 BIND(L_fold_512b_loop);
8469 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8470 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8471 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8472 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8473 addptr(buf, 64);
8474 subl(len, 4);
8475 jcc(Assembler::greater, L_fold_512b_loop);
8476
8477 // Fold 512 bits to 128 bits.
8478 BIND(L_fold_512b);
8479 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8480 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8481 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8482 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8483
8484 // Fold the rest of 128 bits data chunks
8485 BIND(L_fold_tail);
8486 addl(len, 3);
8487 jccb(Assembler::lessEqual, L_fold_128b);
8488 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8489
8490 BIND(L_fold_tail_loop);
8491 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8492 addptr(buf, 16);
8493 decrementl(len);
8494 jccb(Assembler::greater, L_fold_tail_loop);
8495
8496 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8497 BIND(L_fold_128b);
8498 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8499 if (UseAVX > 0) {
8500 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8501 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8502 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8503 } else {
8504 movdqa(xmm2, xmm0);
8505 pclmulqdq(xmm2, xmm1, 0x1);
8506 movdqa(xmm3, xmm0);
8507 pand(xmm3, xmm2);
8508 pclmulqdq(xmm0, xmm3, 0x1);
8509 }
8510 psrldq(xmm1, 8);
8511 psrldq(xmm2, 4);
8512 pxor(xmm0, xmm1);
8513 pxor(xmm0, xmm2);
8514
8515 // 8 8-bit folds to compute 32-bit CRC.
8516 for (int j = 0; j < 4; j++) {
8517 fold_8bit_crc32(xmm0, table, xmm1, rax);
8518 }
8519 movdl(crc, xmm0); // mov 32 bits to general register
8520 for (int j = 0; j < 4; j++) {
8521 fold_8bit_crc32(crc, table, rax);
8522 }
8523
8524 BIND(L_tail_restore);
8525 movl(len, tmp); // restore
8526 BIND(L_tail);
8527 andl(len, 0xf);
8528 jccb(Assembler::zero, L_exit);
8529
8530 // Fold the rest of bytes
8531 align(4);
8532 BIND(L_tail_loop);
8533 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8534 update_byte_crc32(crc, rax, table);
8535 increment(buf);
8536 decrementl(len);
8537 jccb(Assembler::greater, L_tail_loop);
8538
8539 BIND(L_exit);
8540 notl(crc); // ~c
8541 }
8542
8543 // Helper function for AVX 512 CRC32
8544 // Fold 512-bit data chunks
8545 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8546 Register pos, int offset) {
8547 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8548 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8549 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8550 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8551 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8552 }
8553
8554 // Helper function for AVX 512 CRC32
8555 // Compute CRC32 for < 256B buffers
8556 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8557 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8558 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8559
8560 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8561 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8562 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8563
8564 // check if there is enough buffer to be able to fold 16B at a time
8565 cmpl(len, 32);
8566 jcc(Assembler::less, L_less_than_32);
8567
8568 // if there is, load the constants
8569 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8570 movdl(xmm0, crc); // get the initial crc value
8571 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8572 pxor(xmm7, xmm0);
8573
8574 // update the buffer pointer
8575 addl(pos, 16);
8576 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8577 subl(len, 32);
8578 jmp(L_16B_reduction_loop);
8579
8580 bind(L_less_than_32);
8581 //mov initial crc to the return value. this is necessary for zero - length buffers.
8582 movl(rax, crc);
8583 testl(len, len);
8584 jcc(Assembler::equal, L_cleanup);
8585
8586 movdl(xmm0, crc); //get the initial crc value
8587
8588 cmpl(len, 16);
8589 jcc(Assembler::equal, L_exact_16_left);
8590 jcc(Assembler::less, L_less_than_16_left);
8591
8592 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8593 pxor(xmm7, xmm0); //xor the initial crc value
8594 addl(pos, 16);
8595 subl(len, 16);
8596 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8597 jmp(L_get_last_two_xmms);
8598
8599 bind(L_less_than_16_left);
8600 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8601 pxor(xmm1, xmm1);
8602 movptr(tmp1, rsp);
8603 movdqu(Address(tmp1, 0 * 16), xmm1);
8604
8605 cmpl(len, 4);
8606 jcc(Assembler::less, L_only_less_than_4);
8607
8608 //backup the counter value
8609 movl(tmp2, len);
8610 cmpl(len, 8);
8611 jcc(Assembler::less, L_less_than_8_left);
8612
8613 //load 8 Bytes
8614 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8615 movq(Address(tmp1, 0 * 16), rax);
8616 addptr(tmp1, 8);
8617 subl(len, 8);
8618 addl(pos, 8);
8619
8620 bind(L_less_than_8_left);
8621 cmpl(len, 4);
8622 jcc(Assembler::less, L_less_than_4_left);
8623
8624 //load 4 Bytes
8625 movl(rax, Address(buf, pos, Address::times_1, 0));
8626 movl(Address(tmp1, 0 * 16), rax);
8627 addptr(tmp1, 4);
8628 subl(len, 4);
8629 addl(pos, 4);
8630
8631 bind(L_less_than_4_left);
8632 cmpl(len, 2);
8633 jcc(Assembler::less, L_less_than_2_left);
8634
8635 // load 2 Bytes
8636 movw(rax, Address(buf, pos, Address::times_1, 0));
8637 movl(Address(tmp1, 0 * 16), rax);
8638 addptr(tmp1, 2);
8639 subl(len, 2);
8640 addl(pos, 2);
8641
8642 bind(L_less_than_2_left);
8643 cmpl(len, 1);
8644 jcc(Assembler::less, L_zero_left);
8645
8646 // load 1 Byte
8647 movb(rax, Address(buf, pos, Address::times_1, 0));
8648 movb(Address(tmp1, 0 * 16), rax);
8649
8650 bind(L_zero_left);
8651 movdqu(xmm7, Address(rsp, 0));
8652 pxor(xmm7, xmm0); //xor the initial crc value
8653
8654 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8655 movdqu(xmm0, Address(rax, tmp2));
8656 pshufb(xmm7, xmm0);
8657 jmp(L_128_done);
8658
8659 bind(L_exact_16_left);
8660 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8661 pxor(xmm7, xmm0); //xor the initial crc value
8662 jmp(L_128_done);
8663
8664 bind(L_only_less_than_4);
8665 cmpl(len, 3);
8666 jcc(Assembler::less, L_only_less_than_3);
8667
8668 // load 3 Bytes
8669 movb(rax, Address(buf, pos, Address::times_1, 0));
8670 movb(Address(tmp1, 0), rax);
8671
8672 movb(rax, Address(buf, pos, Address::times_1, 1));
8673 movb(Address(tmp1, 1), rax);
8674
8675 movb(rax, Address(buf, pos, Address::times_1, 2));
8676 movb(Address(tmp1, 2), rax);
8677
8678 movdqu(xmm7, Address(rsp, 0));
8679 pxor(xmm7, xmm0); //xor the initial crc value
8680
8681 pslldq(xmm7, 0x5);
8682 jmp(L_barrett);
8683 bind(L_only_less_than_3);
8684 cmpl(len, 2);
8685 jcc(Assembler::less, L_only_less_than_2);
8686
8687 // load 2 Bytes
8688 movb(rax, Address(buf, pos, Address::times_1, 0));
8689 movb(Address(tmp1, 0), rax);
8690
8691 movb(rax, Address(buf, pos, Address::times_1, 1));
8692 movb(Address(tmp1, 1), rax);
8693
8694 movdqu(xmm7, Address(rsp, 0));
8695 pxor(xmm7, xmm0); //xor the initial crc value
8696
8697 pslldq(xmm7, 0x6);
8698 jmp(L_barrett);
8699
8700 bind(L_only_less_than_2);
8701 //load 1 Byte
8702 movb(rax, Address(buf, pos, Address::times_1, 0));
8703 movb(Address(tmp1, 0), rax);
8704
8705 movdqu(xmm7, Address(rsp, 0));
8706 pxor(xmm7, xmm0); //xor the initial crc value
8707
8708 pslldq(xmm7, 0x7);
8709 }
8710
8711 /**
8712 * Compute CRC32 using AVX512 instructions
8713 * param crc register containing existing CRC (32-bit)
8714 * param buf register pointing to input byte buffer (byte*)
8715 * param len register containing number of bytes
8716 * param table address of crc or crc32c table
8717 * param tmp1 scratch register
8718 * param tmp2 scratch register
8719 * return rax result register
8720 *
8721 * This routine is identical for crc32c with the exception of the precomputed constant
8722 * table which will be passed as the table argument. The calculation steps are
8723 * the same for both variants.
8724 */
8725 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8726 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8727
8728 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8729 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8730 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8731 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8732 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8733
8734 const Register pos = r12;
8735 push(r12);
8736 subptr(rsp, 16 * 2 + 8);
8737
8738 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8739 // context for the registers used, where all instructions below are using 128-bit mode
8740 // On EVEX without VL and BW, these instructions will all be AVX.
8741 movl(pos, 0);
8742
8743 // check if smaller than 256B
8744 cmpl(len, 256);
8745 jcc(Assembler::less, L_less_than_256);
8746
8747 // load the initial crc value
8748 movdl(xmm10, crc);
8749
8750 // receive the initial 64B data, xor the initial crc value
8751 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8752 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8753 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8754 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8755
8756 subl(len, 256);
8757 cmpl(len, 256);
8758 jcc(Assembler::less, L_fold_128_B_loop);
8759
8760 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8761 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8762 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8763 subl(len, 256);
8764
8765 bind(L_fold_256_B_loop);
8766 addl(pos, 256);
8767 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8768 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8769 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8770 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8771
8772 subl(len, 256);
8773 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8774
8775 // Fold 256 into 128
8776 addl(pos, 256);
8777 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8778 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8779 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8780
8781 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8782 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8783 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8784
8785 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8786 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8787
8788 addl(len, 128);
8789 jmp(L_fold_128_B_register);
8790
8791 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8792 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8793
8794 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8795 bind(L_fold_128_B_loop);
8796 addl(pos, 128);
8797 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8798 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8799
8800 subl(len, 128);
8801 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8802
8803 addl(pos, 128);
8804
8805 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8806 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8807 bind(L_fold_128_B_register);
8808 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8809 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8810 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8811 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8812 // save last that has no multiplicand
8813 vextracti64x2(xmm7, xmm4, 3);
8814
8815 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8816 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8817 // Needed later in reduction loop
8818 movdqu(xmm10, Address(table, 1 * 16));
8819 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8820 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8821
8822 // Swap 1,0,3,2 - 01 00 11 10
8823 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8824 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8825 vextracti128(xmm5, xmm8, 1);
8826 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8827
8828 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8829 // instead of a cmp instruction, we use the negative flag with the jl instruction
8830 addl(len, 128 - 16);
8831 jcc(Assembler::less, L_final_reduction_for_128);
8832
8833 bind(L_16B_reduction_loop);
8834 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8835 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8836 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8837 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8838 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8839 addl(pos, 16);
8840 subl(len, 16);
8841 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8842
8843 bind(L_final_reduction_for_128);
8844 addl(len, 16);
8845 jcc(Assembler::equal, L_128_done);
8846
8847 bind(L_get_last_two_xmms);
8848 movdqu(xmm2, xmm7);
8849 addl(pos, len);
8850 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8851 subl(pos, len);
8852
8853 // get rid of the extra data that was loaded before
8854 // load the shift constant
8855 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8856 movdqu(xmm0, Address(rax, len));
8857 addl(rax, len);
8858
8859 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8860 //Change mask to 512
8861 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8862 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8863
8864 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8865 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8866 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8867 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8868 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8869
8870 bind(L_128_done);
8871 // compute crc of a 128-bit value
8872 movdqu(xmm10, Address(table, 3 * 16));
8873 movdqu(xmm0, xmm7);
8874
8875 // 64b fold
8876 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8877 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8878 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8879
8880 // 32b fold
8881 movdqu(xmm0, xmm7);
8882 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8883 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8884 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8885 jmp(L_barrett);
8886
8887 bind(L_less_than_256);
8888 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8889
8890 //barrett reduction
8891 bind(L_barrett);
8892 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8893 movdqu(xmm1, xmm7);
8894 movdqu(xmm2, xmm7);
8895 movdqu(xmm10, Address(table, 4 * 16));
8896
8897 pclmulqdq(xmm7, xmm10, 0x0);
8898 pxor(xmm7, xmm2);
8899 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8900 movdqu(xmm2, xmm7);
8901 pclmulqdq(xmm7, xmm10, 0x10);
8902 pxor(xmm7, xmm2);
8903 pxor(xmm7, xmm1);
8904 pextrd(crc, xmm7, 2);
8905
8906 bind(L_cleanup);
8907 addptr(rsp, 16 * 2 + 8);
8908 pop(r12);
8909 }
8910
8911 // S. Gueron / Information Processing Letters 112 (2012) 184
8912 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8913 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8914 // Output: the 64-bit carry-less product of B * CONST
8915 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8916 Register tmp1, Register tmp2, Register tmp3) {
8917 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8918 if (n > 0) {
8919 addq(tmp3, n * 256 * 8);
8920 }
8921 // Q1 = TABLEExt[n][B & 0xFF];
8922 movl(tmp1, in);
8923 andl(tmp1, 0x000000FF);
8924 shll(tmp1, 3);
8925 addq(tmp1, tmp3);
8926 movq(tmp1, Address(tmp1, 0));
8927
8928 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8929 movl(tmp2, in);
8930 shrl(tmp2, 8);
8931 andl(tmp2, 0x000000FF);
8932 shll(tmp2, 3);
8933 addq(tmp2, tmp3);
8934 movq(tmp2, Address(tmp2, 0));
8935
8936 shlq(tmp2, 8);
8937 xorq(tmp1, tmp2);
8938
8939 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8940 movl(tmp2, in);
8941 shrl(tmp2, 16);
8942 andl(tmp2, 0x000000FF);
8943 shll(tmp2, 3);
8944 addq(tmp2, tmp3);
8945 movq(tmp2, Address(tmp2, 0));
8946
8947 shlq(tmp2, 16);
8948 xorq(tmp1, tmp2);
8949
8950 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8951 shrl(in, 24);
8952 andl(in, 0x000000FF);
8953 shll(in, 3);
8954 addq(in, tmp3);
8955 movq(in, Address(in, 0));
8956
8957 shlq(in, 24);
8958 xorq(in, tmp1);
8959 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8960 }
8961
8962 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8963 Register in_out,
8964 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8965 XMMRegister w_xtmp2,
8966 Register tmp1,
8967 Register n_tmp2, Register n_tmp3) {
8968 if (is_pclmulqdq_supported) {
8969 movdl(w_xtmp1, in_out); // modified blindly
8970
8971 movl(tmp1, const_or_pre_comp_const_index);
8972 movdl(w_xtmp2, tmp1);
8973 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8974
8975 movdq(in_out, w_xtmp1);
8976 } else {
8977 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8978 }
8979 }
8980
8981 // Recombination Alternative 2: No bit-reflections
8982 // T1 = (CRC_A * U1) << 1
8983 // T2 = (CRC_B * U2) << 1
8984 // C1 = T1 >> 32
8985 // C2 = T2 >> 32
8986 // T1 = T1 & 0xFFFFFFFF
8987 // T2 = T2 & 0xFFFFFFFF
8988 // T1 = CRC32(0, T1)
8989 // T2 = CRC32(0, T2)
8990 // C1 = C1 ^ T1
8991 // C2 = C2 ^ T2
8992 // CRC = C1 ^ C2 ^ CRC_C
8993 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8994 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8995 Register tmp1, Register tmp2,
8996 Register n_tmp3) {
8997 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8998 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8999 shlq(in_out, 1);
9000 movl(tmp1, in_out);
9001 shrq(in_out, 32);
9002 xorl(tmp2, tmp2);
9003 crc32(tmp2, tmp1, 4);
9004 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9005 shlq(in1, 1);
9006 movl(tmp1, in1);
9007 shrq(in1, 32);
9008 xorl(tmp2, tmp2);
9009 crc32(tmp2, tmp1, 4);
9010 xorl(in1, tmp2);
9011 xorl(in_out, in1);
9012 xorl(in_out, in2);
9013 }
9014
9015 // Set N to predefined value
9016 // Subtract from a length of a buffer
9017 // execute in a loop:
9018 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9019 // for i = 1 to N do
9020 // CRC_A = CRC32(CRC_A, A[i])
9021 // CRC_B = CRC32(CRC_B, B[i])
9022 // CRC_C = CRC32(CRC_C, C[i])
9023 // end for
9024 // Recombine
9025 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9026 Register in_out1, Register in_out2, Register in_out3,
9027 Register tmp1, Register tmp2, Register tmp3,
9028 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9029 Register tmp4, Register tmp5,
9030 Register n_tmp6) {
9031 Label L_processPartitions;
9032 Label L_processPartition;
9033 Label L_exit;
9034
9035 bind(L_processPartitions);
9036 cmpl(in_out1, 3 * size);
9037 jcc(Assembler::less, L_exit);
9038 xorl(tmp1, tmp1);
9039 xorl(tmp2, tmp2);
9040 movq(tmp3, in_out2);
9041 addq(tmp3, size);
9042
9043 bind(L_processPartition);
9044 crc32(in_out3, Address(in_out2, 0), 8);
9045 crc32(tmp1, Address(in_out2, size), 8);
9046 crc32(tmp2, Address(in_out2, size * 2), 8);
9047 addq(in_out2, 8);
9048 cmpq(in_out2, tmp3);
9049 jcc(Assembler::less, L_processPartition);
9050 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9051 w_xtmp1, w_xtmp2, w_xtmp3,
9052 tmp4, tmp5,
9053 n_tmp6);
9054 addq(in_out2, 2 * size);
9055 subl(in_out1, 3 * size);
9056 jmp(L_processPartitions);
9057
9058 bind(L_exit);
9059 }
9060
9061 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9062 // Input: A buffer I of L bytes.
9063 // Output: the CRC32C value of the buffer.
9064 // Notations:
9065 // Write L = 24N + r, with N = floor (L/24).
9066 // r = L mod 24 (0 <= r < 24).
9067 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9068 // N quadwords, and R consists of r bytes.
9069 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9070 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9071 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9072 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9073 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9074 Register tmp1, Register tmp2, Register tmp3,
9075 Register tmp4, Register tmp5, Register tmp6,
9076 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9077 bool is_pclmulqdq_supported) {
9078 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9079 Label L_wordByWord;
9080 Label L_byteByByteProlog;
9081 Label L_byteByByte;
9082 Label L_exit;
9083
9084 if (is_pclmulqdq_supported ) {
9085 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9086 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9087
9088 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9089 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9090
9091 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9092 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9093 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9094 } else {
9095 const_or_pre_comp_const_index[0] = 1;
9096 const_or_pre_comp_const_index[1] = 0;
9097
9098 const_or_pre_comp_const_index[2] = 3;
9099 const_or_pre_comp_const_index[3] = 2;
9100
9101 const_or_pre_comp_const_index[4] = 5;
9102 const_or_pre_comp_const_index[5] = 4;
9103 }
9104 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9105 in2, in1, in_out,
9106 tmp1, tmp2, tmp3,
9107 w_xtmp1, w_xtmp2, w_xtmp3,
9108 tmp4, tmp5,
9109 tmp6);
9110 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9111 in2, in1, in_out,
9112 tmp1, tmp2, tmp3,
9113 w_xtmp1, w_xtmp2, w_xtmp3,
9114 tmp4, tmp5,
9115 tmp6);
9116 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9117 in2, in1, in_out,
9118 tmp1, tmp2, tmp3,
9119 w_xtmp1, w_xtmp2, w_xtmp3,
9120 tmp4, tmp5,
9121 tmp6);
9122 movl(tmp1, in2);
9123 andl(tmp1, 0x00000007);
9124 negl(tmp1);
9125 addl(tmp1, in2);
9126 addq(tmp1, in1);
9127
9128 cmpq(in1, tmp1);
9129 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9130 align(16);
9131 BIND(L_wordByWord);
9132 crc32(in_out, Address(in1, 0), 8);
9133 addq(in1, 8);
9134 cmpq(in1, tmp1);
9135 jcc(Assembler::less, L_wordByWord);
9136
9137 BIND(L_byteByByteProlog);
9138 andl(in2, 0x00000007);
9139 movl(tmp2, 1);
9140
9141 cmpl(tmp2, in2);
9142 jccb(Assembler::greater, L_exit);
9143 BIND(L_byteByByte);
9144 crc32(in_out, Address(in1, 0), 1);
9145 incq(in1);
9146 incl(tmp2);
9147 cmpl(tmp2, in2);
9148 jcc(Assembler::lessEqual, L_byteByByte);
9149
9150 BIND(L_exit);
9151 }
9152 #undef BIND
9153 #undef BLOCK_COMMENT
9154
9155 // Compress char[] array to byte[].
9156 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9157 // Return the array length if every element in array can be encoded,
9158 // otherwise, the index of first non-latin1 (> 0xff) character.
9159 // @IntrinsicCandidate
9160 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9161 // for (int i = 0; i < len; i++) {
9162 // char c = src[srcOff];
9163 // if (c > 0xff) {
9164 // return i; // return index of non-latin1 char
9165 // }
9166 // dst[dstOff] = (byte)c;
9167 // srcOff++;
9168 // dstOff++;
9169 // }
9170 // return len;
9171 // }
9172 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9173 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9174 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9175 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9176 Label copy_chars_loop, done, reset_sp, copy_tail;
9177
9178 // rsi: src
9179 // rdi: dst
9180 // rdx: len
9181 // rcx: tmp5
9182 // rax: result
9183
9184 // rsi holds start addr of source char[] to be compressed
9185 // rdi holds start addr of destination byte[]
9186 // rdx holds length
9187
9188 assert(len != result, "");
9189
9190 // save length for return
9191 movl(result, len);
9192
9193 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9194 VM_Version::supports_avx512vlbw() &&
9195 VM_Version::supports_bmi2()) {
9196
9197 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9198
9199 // alignment
9200 Label post_alignment;
9201
9202 // if length of the string is less than 32, handle it the old fashioned way
9203 testl(len, -32);
9204 jcc(Assembler::zero, below_threshold);
9205
9206 // First check whether a character is compressible ( <= 0xFF).
9207 // Create mask to test for Unicode chars inside zmm vector
9208 movl(tmp5, 0x00FF);
9209 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9210
9211 testl(len, -64);
9212 jccb(Assembler::zero, post_alignment);
9213
9214 movl(tmp5, dst);
9215 andl(tmp5, (32 - 1));
9216 negl(tmp5);
9217 andl(tmp5, (32 - 1));
9218
9219 // bail out when there is nothing to be done
9220 testl(tmp5, 0xFFFFFFFF);
9221 jccb(Assembler::zero, post_alignment);
9222
9223 // ~(~0 << len), where len is the # of remaining elements to process
9224 movl(len, 0xFFFFFFFF);
9225 shlxl(len, len, tmp5);
9226 notl(len);
9227 kmovdl(mask2, len);
9228 movl(len, result);
9229
9230 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9231 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9232 ktestd(mask1, mask2);
9233 jcc(Assembler::carryClear, copy_tail);
9234
9235 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9236
9237 addptr(src, tmp5);
9238 addptr(src, tmp5);
9239 addptr(dst, tmp5);
9240 subl(len, tmp5);
9241
9242 bind(post_alignment);
9243 // end of alignment
9244
9245 movl(tmp5, len);
9246 andl(tmp5, (32 - 1)); // tail count (in chars)
9247 andl(len, ~(32 - 1)); // vector count (in chars)
9248 jccb(Assembler::zero, copy_loop_tail);
9249
9250 lea(src, Address(src, len, Address::times_2));
9251 lea(dst, Address(dst, len, Address::times_1));
9252 negptr(len);
9253
9254 bind(copy_32_loop);
9255 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9256 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9257 kortestdl(mask1, mask1);
9258 jccb(Assembler::carryClear, reset_for_copy_tail);
9259
9260 // All elements in current processed chunk are valid candidates for
9261 // compression. Write a truncated byte elements to the memory.
9262 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9263 addptr(len, 32);
9264 jccb(Assembler::notZero, copy_32_loop);
9265
9266 bind(copy_loop_tail);
9267 // bail out when there is nothing to be done
9268 testl(tmp5, 0xFFFFFFFF);
9269 jcc(Assembler::zero, done);
9270
9271 movl(len, tmp5);
9272
9273 // ~(~0 << len), where len is the # of remaining elements to process
9274 movl(tmp5, 0xFFFFFFFF);
9275 shlxl(tmp5, tmp5, len);
9276 notl(tmp5);
9277
9278 kmovdl(mask2, tmp5);
9279
9280 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9281 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9282 ktestd(mask1, mask2);
9283 jcc(Assembler::carryClear, copy_tail);
9284
9285 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9286 jmp(done);
9287
9288 bind(reset_for_copy_tail);
9289 lea(src, Address(src, tmp5, Address::times_2));
9290 lea(dst, Address(dst, tmp5, Address::times_1));
9291 subptr(len, tmp5);
9292 jmp(copy_chars_loop);
9293
9294 bind(below_threshold);
9295 }
9296
9297 if (UseSSE42Intrinsics) {
9298 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9299
9300 // vectored compression
9301 testl(len, 0xfffffff8);
9302 jcc(Assembler::zero, copy_tail);
9303
9304 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9305 movdl(tmp1Reg, tmp5);
9306 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9307
9308 andl(len, 0xfffffff0);
9309 jccb(Assembler::zero, copy_16);
9310
9311 // compress 16 chars per iter
9312 pxor(tmp4Reg, tmp4Reg);
9313
9314 lea(src, Address(src, len, Address::times_2));
9315 lea(dst, Address(dst, len, Address::times_1));
9316 negptr(len);
9317
9318 bind(copy_32_loop);
9319 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9320 por(tmp4Reg, tmp2Reg);
9321 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9322 por(tmp4Reg, tmp3Reg);
9323 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9324 jccb(Assembler::notZero, reset_for_copy_tail);
9325 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9326 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9327 addptr(len, 16);
9328 jccb(Assembler::notZero, copy_32_loop);
9329
9330 // compress next vector of 8 chars (if any)
9331 bind(copy_16);
9332 // len = 0
9333 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9334 jccb(Assembler::zero, copy_tail_sse);
9335
9336 pxor(tmp3Reg, tmp3Reg);
9337
9338 movdqu(tmp2Reg, Address(src, 0));
9339 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9340 jccb(Assembler::notZero, reset_for_copy_tail);
9341 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9342 movq(Address(dst, 0), tmp2Reg);
9343 addptr(src, 16);
9344 addptr(dst, 8);
9345 jmpb(copy_tail_sse);
9346
9347 bind(reset_for_copy_tail);
9348 movl(tmp5, result);
9349 andl(tmp5, 0x0000000f);
9350 lea(src, Address(src, tmp5, Address::times_2));
9351 lea(dst, Address(dst, tmp5, Address::times_1));
9352 subptr(len, tmp5);
9353 jmpb(copy_chars_loop);
9354
9355 bind(copy_tail_sse);
9356 movl(len, result);
9357 andl(len, 0x00000007); // tail count (in chars)
9358 }
9359 // compress 1 char per iter
9360 bind(copy_tail);
9361 testl(len, len);
9362 jccb(Assembler::zero, done);
9363 lea(src, Address(src, len, Address::times_2));
9364 lea(dst, Address(dst, len, Address::times_1));
9365 negptr(len);
9366
9367 bind(copy_chars_loop);
9368 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9369 testl(tmp5, 0xff00); // check if Unicode char
9370 jccb(Assembler::notZero, reset_sp);
9371 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9372 increment(len);
9373 jccb(Assembler::notZero, copy_chars_loop);
9374
9375 // add len then return (len will be zero if compress succeeded, otherwise negative)
9376 bind(reset_sp);
9377 addl(result, len);
9378
9379 bind(done);
9380 }
9381
9382 // Inflate byte[] array to char[].
9383 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9384 // @IntrinsicCandidate
9385 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9386 // for (int i = 0; i < len; i++) {
9387 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9388 // }
9389 // }
9390 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9391 XMMRegister tmp1, Register tmp2, KRegister mask) {
9392 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9393 // rsi: src
9394 // rdi: dst
9395 // rdx: len
9396 // rcx: tmp2
9397
9398 // rsi holds start addr of source byte[] to be inflated
9399 // rdi holds start addr of destination char[]
9400 // rdx holds length
9401 assert_different_registers(src, dst, len, tmp2);
9402 movl(tmp2, len);
9403 if ((UseAVX > 2) && // AVX512
9404 VM_Version::supports_avx512vlbw() &&
9405 VM_Version::supports_bmi2()) {
9406
9407 Label copy_32_loop, copy_tail;
9408 Register tmp3_aliased = len;
9409
9410 // if length of the string is less than 16, handle it in an old fashioned way
9411 testl(len, -16);
9412 jcc(Assembler::zero, below_threshold);
9413
9414 testl(len, -1 * AVX3Threshold);
9415 jcc(Assembler::zero, avx3_threshold);
9416
9417 // In order to use only one arithmetic operation for the main loop we use
9418 // this pre-calculation
9419 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9420 andl(len, -32); // vector count
9421 jccb(Assembler::zero, copy_tail);
9422
9423 lea(src, Address(src, len, Address::times_1));
9424 lea(dst, Address(dst, len, Address::times_2));
9425 negptr(len);
9426
9427
9428 // inflate 32 chars per iter
9429 bind(copy_32_loop);
9430 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9431 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9432 addptr(len, 32);
9433 jcc(Assembler::notZero, copy_32_loop);
9434
9435 bind(copy_tail);
9436 // bail out when there is nothing to be done
9437 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9438 jcc(Assembler::zero, done);
9439
9440 // ~(~0 << length), where length is the # of remaining elements to process
9441 movl(tmp3_aliased, -1);
9442 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9443 notl(tmp3_aliased);
9444 kmovdl(mask, tmp3_aliased);
9445 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9446 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9447
9448 jmp(done);
9449 bind(avx3_threshold);
9450 }
9451 if (UseSSE42Intrinsics) {
9452 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9453
9454 if (UseAVX > 1) {
9455 andl(tmp2, (16 - 1));
9456 andl(len, -16);
9457 jccb(Assembler::zero, copy_new_tail);
9458 } else {
9459 andl(tmp2, 0x00000007); // tail count (in chars)
9460 andl(len, 0xfffffff8); // vector count (in chars)
9461 jccb(Assembler::zero, copy_tail);
9462 }
9463
9464 // vectored inflation
9465 lea(src, Address(src, len, Address::times_1));
9466 lea(dst, Address(dst, len, Address::times_2));
9467 negptr(len);
9468
9469 if (UseAVX > 1) {
9470 bind(copy_16_loop);
9471 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9472 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9473 addptr(len, 16);
9474 jcc(Assembler::notZero, copy_16_loop);
9475
9476 bind(below_threshold);
9477 bind(copy_new_tail);
9478 movl(len, tmp2);
9479 andl(tmp2, 0x00000007);
9480 andl(len, 0xFFFFFFF8);
9481 jccb(Assembler::zero, copy_tail);
9482
9483 pmovzxbw(tmp1, Address(src, 0));
9484 movdqu(Address(dst, 0), tmp1);
9485 addptr(src, 8);
9486 addptr(dst, 2 * 8);
9487
9488 jmp(copy_tail, true);
9489 }
9490
9491 // inflate 8 chars per iter
9492 bind(copy_8_loop);
9493 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9494 movdqu(Address(dst, len, Address::times_2), tmp1);
9495 addptr(len, 8);
9496 jcc(Assembler::notZero, copy_8_loop);
9497
9498 bind(copy_tail);
9499 movl(len, tmp2);
9500
9501 cmpl(len, 4);
9502 jccb(Assembler::less, copy_bytes);
9503
9504 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9505 pmovzxbw(tmp1, tmp1);
9506 movq(Address(dst, 0), tmp1);
9507 subptr(len, 4);
9508 addptr(src, 4);
9509 addptr(dst, 8);
9510
9511 bind(copy_bytes);
9512 } else {
9513 bind(below_threshold);
9514 }
9515
9516 testl(len, len);
9517 jccb(Assembler::zero, done);
9518 lea(src, Address(src, len, Address::times_1));
9519 lea(dst, Address(dst, len, Address::times_2));
9520 negptr(len);
9521
9522 // inflate 1 char per iter
9523 bind(copy_chars_loop);
9524 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9525 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9526 increment(len);
9527 jcc(Assembler::notZero, copy_chars_loop);
9528
9529 bind(done);
9530 }
9531
9532 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9533 switch(type) {
9534 case T_BYTE:
9535 case T_BOOLEAN:
9536 evmovdqub(dst, kmask, src, merge, vector_len);
9537 break;
9538 case T_CHAR:
9539 case T_SHORT:
9540 evmovdquw(dst, kmask, src, merge, vector_len);
9541 break;
9542 case T_INT:
9543 case T_FLOAT:
9544 evmovdqul(dst, kmask, src, merge, vector_len);
9545 break;
9546 case T_LONG:
9547 case T_DOUBLE:
9548 evmovdquq(dst, kmask, src, merge, vector_len);
9549 break;
9550 default:
9551 fatal("Unexpected type argument %s", type2name(type));
9552 break;
9553 }
9554 }
9555
9556
9557 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9558 switch(type) {
9559 case T_BYTE:
9560 case T_BOOLEAN:
9561 evmovdqub(dst, kmask, src, merge, vector_len);
9562 break;
9563 case T_CHAR:
9564 case T_SHORT:
9565 evmovdquw(dst, kmask, src, merge, vector_len);
9566 break;
9567 case T_INT:
9568 case T_FLOAT:
9569 evmovdqul(dst, kmask, src, merge, vector_len);
9570 break;
9571 case T_LONG:
9572 case T_DOUBLE:
9573 evmovdquq(dst, kmask, src, merge, vector_len);
9574 break;
9575 default:
9576 fatal("Unexpected type argument %s", type2name(type));
9577 break;
9578 }
9579 }
9580
9581 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9582 switch(type) {
9583 case T_BYTE:
9584 case T_BOOLEAN:
9585 evmovdqub(dst, kmask, src, merge, vector_len);
9586 break;
9587 case T_CHAR:
9588 case T_SHORT:
9589 evmovdquw(dst, kmask, src, merge, vector_len);
9590 break;
9591 case T_INT:
9592 case T_FLOAT:
9593 evmovdqul(dst, kmask, src, merge, vector_len);
9594 break;
9595 case T_LONG:
9596 case T_DOUBLE:
9597 evmovdquq(dst, kmask, src, merge, vector_len);
9598 break;
9599 default:
9600 fatal("Unexpected type argument %s", type2name(type));
9601 break;
9602 }
9603 }
9604
9605 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9606 switch(masklen) {
9607 case 2:
9608 knotbl(dst, src);
9609 movl(rtmp, 3);
9610 kmovbl(ktmp, rtmp);
9611 kandbl(dst, ktmp, dst);
9612 break;
9613 case 4:
9614 knotbl(dst, src);
9615 movl(rtmp, 15);
9616 kmovbl(ktmp, rtmp);
9617 kandbl(dst, ktmp, dst);
9618 break;
9619 case 8:
9620 knotbl(dst, src);
9621 break;
9622 case 16:
9623 knotwl(dst, src);
9624 break;
9625 case 32:
9626 knotdl(dst, src);
9627 break;
9628 case 64:
9629 knotql(dst, src);
9630 break;
9631 default:
9632 fatal("Unexpected vector length %d", masklen);
9633 break;
9634 }
9635 }
9636
9637 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9638 switch(type) {
9639 case T_BOOLEAN:
9640 case T_BYTE:
9641 kandbl(dst, src1, src2);
9642 break;
9643 case T_CHAR:
9644 case T_SHORT:
9645 kandwl(dst, src1, src2);
9646 break;
9647 case T_INT:
9648 case T_FLOAT:
9649 kanddl(dst, src1, src2);
9650 break;
9651 case T_LONG:
9652 case T_DOUBLE:
9653 kandql(dst, src1, src2);
9654 break;
9655 default:
9656 fatal("Unexpected type argument %s", type2name(type));
9657 break;
9658 }
9659 }
9660
9661 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9662 switch(type) {
9663 case T_BOOLEAN:
9664 case T_BYTE:
9665 korbl(dst, src1, src2);
9666 break;
9667 case T_CHAR:
9668 case T_SHORT:
9669 korwl(dst, src1, src2);
9670 break;
9671 case T_INT:
9672 case T_FLOAT:
9673 kordl(dst, src1, src2);
9674 break;
9675 case T_LONG:
9676 case T_DOUBLE:
9677 korql(dst, src1, src2);
9678 break;
9679 default:
9680 fatal("Unexpected type argument %s", type2name(type));
9681 break;
9682 }
9683 }
9684
9685 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9686 switch(type) {
9687 case T_BOOLEAN:
9688 case T_BYTE:
9689 kxorbl(dst, src1, src2);
9690 break;
9691 case T_CHAR:
9692 case T_SHORT:
9693 kxorwl(dst, src1, src2);
9694 break;
9695 case T_INT:
9696 case T_FLOAT:
9697 kxordl(dst, src1, src2);
9698 break;
9699 case T_LONG:
9700 case T_DOUBLE:
9701 kxorql(dst, src1, src2);
9702 break;
9703 default:
9704 fatal("Unexpected type argument %s", type2name(type));
9705 break;
9706 }
9707 }
9708
9709 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9710 switch(type) {
9711 case T_BOOLEAN:
9712 case T_BYTE:
9713 evpermb(dst, mask, nds, src, merge, vector_len); break;
9714 case T_CHAR:
9715 case T_SHORT:
9716 evpermw(dst, mask, nds, src, merge, vector_len); break;
9717 case T_INT:
9718 case T_FLOAT:
9719 evpermd(dst, mask, nds, src, merge, vector_len); break;
9720 case T_LONG:
9721 case T_DOUBLE:
9722 evpermq(dst, mask, nds, src, merge, vector_len); break;
9723 default:
9724 fatal("Unexpected type argument %s", type2name(type)); break;
9725 }
9726 }
9727
9728 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9729 switch(type) {
9730 case T_BOOLEAN:
9731 case T_BYTE:
9732 evpermb(dst, mask, nds, src, merge, vector_len); break;
9733 case T_CHAR:
9734 case T_SHORT:
9735 evpermw(dst, mask, nds, src, merge, vector_len); break;
9736 case T_INT:
9737 case T_FLOAT:
9738 evpermd(dst, mask, nds, src, merge, vector_len); break;
9739 case T_LONG:
9740 case T_DOUBLE:
9741 evpermq(dst, mask, nds, src, merge, vector_len); break;
9742 default:
9743 fatal("Unexpected type argument %s", type2name(type)); break;
9744 }
9745 }
9746
9747 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9748 switch(type) {
9749 case T_BYTE:
9750 evpminub(dst, mask, nds, src, merge, vector_len); break;
9751 case T_SHORT:
9752 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9753 case T_INT:
9754 evpminud(dst, mask, nds, src, merge, vector_len); break;
9755 case T_LONG:
9756 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9757 default:
9758 fatal("Unexpected type argument %s", type2name(type)); break;
9759 }
9760 }
9761
9762 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9763 switch(type) {
9764 case T_BYTE:
9765 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9766 case T_SHORT:
9767 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9768 case T_INT:
9769 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9770 case T_LONG:
9771 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9772 default:
9773 fatal("Unexpected type argument %s", type2name(type)); break;
9774 }
9775 }
9776
9777 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9778 switch(type) {
9779 case T_BYTE:
9780 evpminub(dst, mask, nds, src, merge, vector_len); break;
9781 case T_SHORT:
9782 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9783 case T_INT:
9784 evpminud(dst, mask, nds, src, merge, vector_len); break;
9785 case T_LONG:
9786 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9787 default:
9788 fatal("Unexpected type argument %s", type2name(type)); break;
9789 }
9790 }
9791
9792 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9793 switch(type) {
9794 case T_BYTE:
9795 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9796 case T_SHORT:
9797 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9798 case T_INT:
9799 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9800 case T_LONG:
9801 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9802 default:
9803 fatal("Unexpected type argument %s", type2name(type)); break;
9804 }
9805 }
9806
9807 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9808 switch(type) {
9809 case T_BYTE:
9810 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9811 case T_SHORT:
9812 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9813 case T_INT:
9814 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9815 case T_LONG:
9816 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9817 case T_FLOAT:
9818 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9819 case T_DOUBLE:
9820 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9821 default:
9822 fatal("Unexpected type argument %s", type2name(type)); break;
9823 }
9824 }
9825
9826 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9827 switch(type) {
9828 case T_BYTE:
9829 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9830 case T_SHORT:
9831 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9832 case T_INT:
9833 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9834 case T_LONG:
9835 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9836 case T_FLOAT:
9837 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9838 case T_DOUBLE:
9839 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9840 default:
9841 fatal("Unexpected type argument %s", type2name(type)); break;
9842 }
9843 }
9844
9845 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9846 switch(type) {
9847 case T_BYTE:
9848 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9849 case T_SHORT:
9850 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9851 case T_INT:
9852 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9853 case T_LONG:
9854 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9855 case T_FLOAT:
9856 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9857 case T_DOUBLE:
9858 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9859 default:
9860 fatal("Unexpected type argument %s", type2name(type)); break;
9861 }
9862 }
9863
9864 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9865 switch(type) {
9866 case T_BYTE:
9867 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9868 case T_SHORT:
9869 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9870 case T_INT:
9871 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9872 case T_LONG:
9873 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9874 case T_FLOAT:
9875 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9876 case T_DOUBLE:
9877 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9878 default:
9879 fatal("Unexpected type argument %s", type2name(type)); break;
9880 }
9881 }
9882
9883 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9884 switch(type) {
9885 case T_INT:
9886 evpxord(dst, mask, nds, src, merge, vector_len); break;
9887 case T_LONG:
9888 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9889 default:
9890 fatal("Unexpected type argument %s", type2name(type)); break;
9891 }
9892 }
9893
9894 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9895 switch(type) {
9896 case T_INT:
9897 evpxord(dst, mask, nds, src, merge, vector_len); break;
9898 case T_LONG:
9899 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9900 default:
9901 fatal("Unexpected type argument %s", type2name(type)); break;
9902 }
9903 }
9904
9905 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9906 switch(type) {
9907 case T_INT:
9908 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9909 case T_LONG:
9910 evporq(dst, mask, nds, src, merge, vector_len); break;
9911 default:
9912 fatal("Unexpected type argument %s", type2name(type)); break;
9913 }
9914 }
9915
9916 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9917 switch(type) {
9918 case T_INT:
9919 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9920 case T_LONG:
9921 evporq(dst, mask, nds, src, merge, vector_len); break;
9922 default:
9923 fatal("Unexpected type argument %s", type2name(type)); break;
9924 }
9925 }
9926
9927 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9928 switch(type) {
9929 case T_INT:
9930 evpandd(dst, mask, nds, src, merge, vector_len); break;
9931 case T_LONG:
9932 evpandq(dst, mask, nds, src, merge, vector_len); break;
9933 default:
9934 fatal("Unexpected type argument %s", type2name(type)); break;
9935 }
9936 }
9937
9938 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9939 switch(type) {
9940 case T_INT:
9941 evpandd(dst, mask, nds, src, merge, vector_len); break;
9942 case T_LONG:
9943 evpandq(dst, mask, nds, src, merge, vector_len); break;
9944 default:
9945 fatal("Unexpected type argument %s", type2name(type)); break;
9946 }
9947 }
9948
9949 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
9950 switch(masklen) {
9951 case 8:
9952 kortestbl(src1, src2);
9953 break;
9954 case 16:
9955 kortestwl(src1, src2);
9956 break;
9957 case 32:
9958 kortestdl(src1, src2);
9959 break;
9960 case 64:
9961 kortestql(src1, src2);
9962 break;
9963 default:
9964 fatal("Unexpected mask length %d", masklen);
9965 break;
9966 }
9967 }
9968
9969
9970 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
9971 switch(masklen) {
9972 case 8:
9973 ktestbl(src1, src2);
9974 break;
9975 case 16:
9976 ktestwl(src1, src2);
9977 break;
9978 case 32:
9979 ktestdl(src1, src2);
9980 break;
9981 case 64:
9982 ktestql(src1, src2);
9983 break;
9984 default:
9985 fatal("Unexpected mask length %d", masklen);
9986 break;
9987 }
9988 }
9989
9990 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9991 switch(type) {
9992 case T_INT:
9993 evprold(dst, mask, src, shift, merge, vlen_enc); break;
9994 case T_LONG:
9995 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
9996 default:
9997 fatal("Unexpected type argument %s", type2name(type)); break;
9998 break;
9999 }
10000 }
10001
10002 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10003 switch(type) {
10004 case T_INT:
10005 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10006 case T_LONG:
10007 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10008 default:
10009 fatal("Unexpected type argument %s", type2name(type)); break;
10010 }
10011 }
10012
10013 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10014 switch(type) {
10015 case T_INT:
10016 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10017 case T_LONG:
10018 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10019 default:
10020 fatal("Unexpected type argument %s", type2name(type)); break;
10021 }
10022 }
10023
10024 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10025 switch(type) {
10026 case T_INT:
10027 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10028 case T_LONG:
10029 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10030 default:
10031 fatal("Unexpected type argument %s", type2name(type)); break;
10032 }
10033 }
10034
10035 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10036 assert(rscratch != noreg || always_reachable(src), "missing");
10037
10038 if (reachable(src)) {
10039 evpandq(dst, nds, as_Address(src), vector_len);
10040 } else {
10041 lea(rscratch, src);
10042 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10043 }
10044 }
10045
10046 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10047 assert(rscratch != noreg || always_reachable(src), "missing");
10048
10049 if (reachable(src)) {
10050 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10051 } else {
10052 lea(rscratch, src);
10053 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10054 }
10055 }
10056
10057 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10058 assert(rscratch != noreg || always_reachable(src), "missing");
10059
10060 if (reachable(src)) {
10061 evporq(dst, nds, as_Address(src), vector_len);
10062 } else {
10063 lea(rscratch, src);
10064 evporq(dst, nds, Address(rscratch, 0), vector_len);
10065 }
10066 }
10067
10068 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10069 assert(rscratch != noreg || always_reachable(src), "missing");
10070
10071 if (reachable(src)) {
10072 vpshufb(dst, nds, as_Address(src), vector_len);
10073 } else {
10074 lea(rscratch, src);
10075 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10076 }
10077 }
10078
10079 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10080 assert(rscratch != noreg || always_reachable(src), "missing");
10081
10082 if (reachable(src)) {
10083 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10084 } else {
10085 lea(rscratch, src);
10086 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10087 }
10088 }
10089
10090 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10091 assert(rscratch != noreg || always_reachable(src3), "missing");
10092
10093 if (reachable(src3)) {
10094 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10095 } else {
10096 lea(rscratch, src3);
10097 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10098 }
10099 }
10100
10101 #ifdef COMPILER2
10102
10103 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10104 Register length, Register temp, int vec_enc) {
10105 // Computing mask for predicated vector store.
10106 movptr(temp, -1);
10107 bzhiq(temp, temp, length);
10108 kmov(mask, temp);
10109 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10110 }
10111
10112 // Set memory operation for length "less than" 64 bytes.
10113 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10114 XMMRegister xmm, KRegister mask, Register length,
10115 Register temp, bool use64byteVector) {
10116 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10117 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10118 if (!use64byteVector) {
10119 fill32(dst, disp, xmm);
10120 subptr(length, 32 >> shift);
10121 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10122 } else {
10123 assert(MaxVectorSize == 64, "vector length != 64");
10124 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10125 }
10126 }
10127
10128
10129 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10130 XMMRegister xmm, KRegister mask, Register length,
10131 Register temp) {
10132 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10133 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10134 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10135 }
10136
10137
10138 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10139 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10140 vmovdqu(dst, xmm);
10141 }
10142
10143 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10144 fill32(Address(dst, disp), xmm);
10145 }
10146
10147 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10148 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10149 if (!use64byteVector) {
10150 fill32(dst, xmm);
10151 fill32(dst.plus_disp(32), xmm);
10152 } else {
10153 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10154 }
10155 }
10156
10157 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10158 fill64(Address(dst, disp), xmm, use64byteVector);
10159 }
10160
10161 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10162 Register count, Register rtmp, XMMRegister xtmp) {
10163 Label L_exit;
10164 Label L_fill_start;
10165 Label L_fill_64_bytes;
10166 Label L_fill_96_bytes;
10167 Label L_fill_128_bytes;
10168 Label L_fill_128_bytes_loop;
10169 Label L_fill_128_loop_header;
10170 Label L_fill_128_bytes_loop_header;
10171 Label L_fill_128_bytes_loop_pre_header;
10172 Label L_fill_zmm_sequence;
10173
10174 int shift = -1;
10175 switch(type) {
10176 case T_BYTE: shift = 0;
10177 break;
10178 case T_SHORT: shift = 1;
10179 break;
10180 case T_INT: shift = 2;
10181 break;
10182 /* Uncomment when LONG fill stubs are supported.
10183 case T_LONG: shift = 3;
10184 break;
10185 */
10186 default:
10187 fatal("Unhandled type: %s\n", type2name(type));
10188 }
10189
10190 if ((CopyAVX3Threshold != 0) || (MaxVectorSize == 32)) {
10191
10192 if (MaxVectorSize == 64) {
10193 cmpq(count, CopyAVX3Threshold >> shift);
10194 jcc(Assembler::greater, L_fill_zmm_sequence);
10195 }
10196
10197 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10198
10199 bind(L_fill_start);
10200
10201 cmpq(count, 32 >> shift);
10202 jccb(Assembler::greater, L_fill_64_bytes);
10203 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10204 jmp(L_exit);
10205
10206 bind(L_fill_64_bytes);
10207 cmpq(count, 64 >> shift);
10208 jccb(Assembler::greater, L_fill_96_bytes);
10209 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10210 jmp(L_exit);
10211
10212 bind(L_fill_96_bytes);
10213 cmpq(count, 96 >> shift);
10214 jccb(Assembler::greater, L_fill_128_bytes);
10215 fill64(to, 0, xtmp);
10216 subq(count, 64 >> shift);
10217 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10218 jmp(L_exit);
10219
10220 bind(L_fill_128_bytes);
10221 cmpq(count, 128 >> shift);
10222 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10223 fill64(to, 0, xtmp);
10224 fill32(to, 64, xtmp);
10225 subq(count, 96 >> shift);
10226 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10227 jmp(L_exit);
10228
10229 bind(L_fill_128_bytes_loop_pre_header);
10230 {
10231 mov(rtmp, to);
10232 andq(rtmp, 31);
10233 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10234 negq(rtmp);
10235 addq(rtmp, 32);
10236 mov64(r8, -1L);
10237 bzhiq(r8, r8, rtmp);
10238 kmovql(k2, r8);
10239 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10240 addq(to, rtmp);
10241 shrq(rtmp, shift);
10242 subq(count, rtmp);
10243 }
10244
10245 cmpq(count, 128 >> shift);
10246 jcc(Assembler::less, L_fill_start);
10247
10248 bind(L_fill_128_bytes_loop_header);
10249 subq(count, 128 >> shift);
10250
10251 align32();
10252 bind(L_fill_128_bytes_loop);
10253 fill64(to, 0, xtmp);
10254 fill64(to, 64, xtmp);
10255 addq(to, 128);
10256 subq(count, 128 >> shift);
10257 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10258
10259 addq(count, 128 >> shift);
10260 jcc(Assembler::zero, L_exit);
10261 jmp(L_fill_start);
10262 }
10263
10264 if (MaxVectorSize == 64) {
10265 // Sequence using 64 byte ZMM register.
10266 Label L_fill_128_bytes_zmm;
10267 Label L_fill_192_bytes_zmm;
10268 Label L_fill_192_bytes_loop_zmm;
10269 Label L_fill_192_bytes_loop_header_zmm;
10270 Label L_fill_192_bytes_loop_pre_header_zmm;
10271 Label L_fill_start_zmm_sequence;
10272
10273 bind(L_fill_zmm_sequence);
10274 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10275
10276 bind(L_fill_start_zmm_sequence);
10277 cmpq(count, 64 >> shift);
10278 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10279 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10280 jmp(L_exit);
10281
10282 bind(L_fill_128_bytes_zmm);
10283 cmpq(count, 128 >> shift);
10284 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10285 fill64(to, 0, xtmp, true);
10286 subq(count, 64 >> shift);
10287 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10288 jmp(L_exit);
10289
10290 bind(L_fill_192_bytes_zmm);
10291 cmpq(count, 192 >> shift);
10292 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10293 fill64(to, 0, xtmp, true);
10294 fill64(to, 64, xtmp, true);
10295 subq(count, 128 >> shift);
10296 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10297 jmp(L_exit);
10298
10299 bind(L_fill_192_bytes_loop_pre_header_zmm);
10300 {
10301 movq(rtmp, to);
10302 andq(rtmp, 63);
10303 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10304 negq(rtmp);
10305 addq(rtmp, 64);
10306 mov64(r8, -1L);
10307 bzhiq(r8, r8, rtmp);
10308 kmovql(k2, r8);
10309 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10310 addq(to, rtmp);
10311 shrq(rtmp, shift);
10312 subq(count, rtmp);
10313 }
10314
10315 cmpq(count, 192 >> shift);
10316 jcc(Assembler::less, L_fill_start_zmm_sequence);
10317
10318 bind(L_fill_192_bytes_loop_header_zmm);
10319 subq(count, 192 >> shift);
10320
10321 align32();
10322 bind(L_fill_192_bytes_loop_zmm);
10323 fill64(to, 0, xtmp, true);
10324 fill64(to, 64, xtmp, true);
10325 fill64(to, 128, xtmp, true);
10326 addq(to, 192);
10327 subq(count, 192 >> shift);
10328 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10329
10330 addq(count, 192 >> shift);
10331 jcc(Assembler::zero, L_exit);
10332 jmp(L_fill_start_zmm_sequence);
10333 }
10334 bind(L_exit);
10335 }
10336 #endif //COMPILER2
10337
10338
10339 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10340 Label done;
10341 cvttss2sil(dst, src);
10342 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10343 cmpl(dst, 0x80000000); // float_sign_flip
10344 jccb(Assembler::notEqual, done);
10345 subptr(rsp, 8);
10346 movflt(Address(rsp, 0), src);
10347 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10348 pop(dst);
10349 bind(done);
10350 }
10351
10352 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10353 Label done;
10354 cvttsd2sil(dst, src);
10355 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10356 cmpl(dst, 0x80000000); // float_sign_flip
10357 jccb(Assembler::notEqual, done);
10358 subptr(rsp, 8);
10359 movdbl(Address(rsp, 0), src);
10360 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10361 pop(dst);
10362 bind(done);
10363 }
10364
10365 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10366 Label done;
10367 cvttss2siq(dst, src);
10368 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10369 jccb(Assembler::notEqual, done);
10370 subptr(rsp, 8);
10371 movflt(Address(rsp, 0), src);
10372 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10373 pop(dst);
10374 bind(done);
10375 }
10376
10377 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10378 // Following code is line by line assembly translation rounding algorithm.
10379 // Please refer to java.lang.Math.round(float) algorithm for details.
10380 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10381 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10382 const int32_t FloatConsts_EXP_BIAS = 127;
10383 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10384 const int32_t MINUS_32 = 0xFFFFFFE0;
10385 Label L_special_case, L_block1, L_exit;
10386 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10387 movdl(dst, src);
10388 andl(dst, rtmp);
10389 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10390 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10391 subl(rtmp, dst);
10392 movl(rcx, rtmp);
10393 movl(dst, MINUS_32);
10394 testl(rtmp, dst);
10395 jccb(Assembler::notEqual, L_special_case);
10396 movdl(dst, src);
10397 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10398 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10399 movdl(rtmp, src);
10400 testl(rtmp, rtmp);
10401 jccb(Assembler::greaterEqual, L_block1);
10402 negl(dst);
10403 bind(L_block1);
10404 sarl(dst);
10405 addl(dst, 0x1);
10406 sarl(dst, 0x1);
10407 jmp(L_exit);
10408 bind(L_special_case);
10409 convert_f2i(dst, src);
10410 bind(L_exit);
10411 }
10412
10413 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10414 // Following code is line by line assembly translation rounding algorithm.
10415 // Please refer to java.lang.Math.round(double) algorithm for details.
10416 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10417 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10418 const int64_t DoubleConsts_EXP_BIAS = 1023;
10419 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10420 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10421 Label L_special_case, L_block1, L_exit;
10422 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10423 movq(dst, src);
10424 andq(dst, rtmp);
10425 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10426 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10427 subq(rtmp, dst);
10428 movq(rcx, rtmp);
10429 mov64(dst, MINUS_64);
10430 testq(rtmp, dst);
10431 jccb(Assembler::notEqual, L_special_case);
10432 movq(dst, src);
10433 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10434 andq(dst, rtmp);
10435 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10436 orq(dst, rtmp);
10437 movq(rtmp, src);
10438 testq(rtmp, rtmp);
10439 jccb(Assembler::greaterEqual, L_block1);
10440 negq(dst);
10441 bind(L_block1);
10442 sarq(dst);
10443 addq(dst, 0x1);
10444 sarq(dst, 0x1);
10445 jmp(L_exit);
10446 bind(L_special_case);
10447 convert_d2l(dst, src);
10448 bind(L_exit);
10449 }
10450
10451 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10452 Label done;
10453 cvttsd2siq(dst, src);
10454 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10455 jccb(Assembler::notEqual, done);
10456 subptr(rsp, 8);
10457 movdbl(Address(rsp, 0), src);
10458 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10459 pop(dst);
10460 bind(done);
10461 }
10462
10463 void MacroAssembler::cache_wb(Address line)
10464 {
10465 // 64 bit cpus always support clflush
10466 bool optimized = VM_Version::supports_clflushopt();
10467 bool no_evict = VM_Version::supports_clwb();
10468
10469 // prefer clwb (writeback without evict) otherwise
10470 // prefer clflushopt (potentially parallel writeback with evict)
10471 // otherwise fallback on clflush (serial writeback with evict)
10472
10473 if (optimized) {
10474 if (no_evict) {
10475 clwb(line);
10476 } else {
10477 clflushopt(line);
10478 }
10479 } else {
10480 // no need for fence when using CLFLUSH
10481 clflush(line);
10482 }
10483 }
10484
10485 void MacroAssembler::cache_wbsync(bool is_pre)
10486 {
10487 bool optimized = VM_Version::supports_clflushopt();
10488 bool no_evict = VM_Version::supports_clwb();
10489
10490 // pick the correct implementation
10491
10492 if (!is_pre && (optimized || no_evict)) {
10493 // need an sfence for post flush when using clflushopt or clwb
10494 // otherwise no no need for any synchroniaztion
10495
10496 sfence();
10497 }
10498 }
10499
10500 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10501 switch (cond) {
10502 // Note some conditions are synonyms for others
10503 case Assembler::zero: return Assembler::notZero;
10504 case Assembler::notZero: return Assembler::zero;
10505 case Assembler::less: return Assembler::greaterEqual;
10506 case Assembler::lessEqual: return Assembler::greater;
10507 case Assembler::greater: return Assembler::lessEqual;
10508 case Assembler::greaterEqual: return Assembler::less;
10509 case Assembler::below: return Assembler::aboveEqual;
10510 case Assembler::belowEqual: return Assembler::above;
10511 case Assembler::above: return Assembler::belowEqual;
10512 case Assembler::aboveEqual: return Assembler::below;
10513 case Assembler::overflow: return Assembler::noOverflow;
10514 case Assembler::noOverflow: return Assembler::overflow;
10515 case Assembler::negative: return Assembler::positive;
10516 case Assembler::positive: return Assembler::negative;
10517 case Assembler::parity: return Assembler::noParity;
10518 case Assembler::noParity: return Assembler::parity;
10519 }
10520 ShouldNotReachHere(); return Assembler::overflow;
10521 }
10522
10523 // This is simply a call to Thread::current()
10524 void MacroAssembler::get_thread_slow(Register thread) {
10525 if (thread != rax) {
10526 push(rax);
10527 }
10528 push(rdi);
10529 push(rsi);
10530 push(rdx);
10531 push(rcx);
10532 push(r8);
10533 push(r9);
10534 push(r10);
10535 push(r11);
10536
10537 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10538
10539 pop(r11);
10540 pop(r10);
10541 pop(r9);
10542 pop(r8);
10543 pop(rcx);
10544 pop(rdx);
10545 pop(rsi);
10546 pop(rdi);
10547 if (thread != rax) {
10548 mov(thread, rax);
10549 pop(rax);
10550 }
10551 }
10552
10553 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10554 Label L_stack_ok;
10555 if (bias == 0) {
10556 testptr(sp, 2 * wordSize - 1);
10557 } else {
10558 // lea(tmp, Address(rsp, bias);
10559 mov(tmp, sp);
10560 addptr(tmp, bias);
10561 testptr(tmp, 2 * wordSize - 1);
10562 }
10563 jcc(Assembler::equal, L_stack_ok);
10564 block_comment(msg);
10565 stop(msg);
10566 bind(L_stack_ok);
10567 }
10568
10569 // Implements fast-locking.
10570 //
10571 // obj: the object to be locked
10572 // reg_rax: rax
10573 // thread: the thread which attempts to lock obj
10574 // tmp: a temporary register
10575 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow) {
10576 Register thread = r15_thread;
10577
10578 assert(reg_rax == rax, "");
10579 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10580
10581 Label push;
10582 const Register top = tmp;
10583
10584 // Preload the markWord. It is important that this is the first
10585 // instruction emitted as it is part of C1's null check semantics.
10586 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10587
10588 if (UseObjectMonitorTable) {
10589 // Clear cache in case fast locking succeeds or we need to take the slow-path.
10590 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10591 }
10592
10593 if (DiagnoseSyncOnValueBasedClasses != 0) {
10594 load_klass(tmp, obj, rscratch1);
10595 testb(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
10596 jcc(Assembler::notZero, slow);
10597 }
10598
10599 // Load top.
10600 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10601
10602 // Check if the lock-stack is full.
10603 cmpl(top, LockStack::end_offset());
10604 jcc(Assembler::greaterEqual, slow);
10605
10606 // Check for recursion.
10607 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10608 jcc(Assembler::equal, push);
10609
10610 // Check header for monitor (0b10).
10611 testptr(reg_rax, markWord::monitor_value);
10612 jcc(Assembler::notZero, slow);
10613
10614 // Try to lock. Transition lock bits 0b01 => 0b00
10615 movptr(tmp, reg_rax);
10616 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10617 orptr(reg_rax, markWord::unlocked_value);
10618 // Mask inline_type bit such that we go to the slow path if object is an inline type
10619 andptr(reg_rax, ~((int) markWord::inline_type_bit_in_place));
10620
10621 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10622 jcc(Assembler::notEqual, slow);
10623
10624 // Restore top, CAS clobbers register.
10625 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10626
10627 bind(push);
10628 // After successful lock, push object on lock-stack.
10629 movptr(Address(thread, top), obj);
10630 incrementl(top, oopSize);
10631 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10632 }
10633
10634 // Implements fast-unlocking.
10635 //
10636 // obj: the object to be unlocked
10637 // reg_rax: rax
10638 // thread: the thread
10639 // tmp: a temporary register
10640 void MacroAssembler::fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow) {
10641 Register thread = r15_thread;
10642
10643 assert(reg_rax == rax, "");
10644 assert_different_registers(obj, reg_rax, thread, tmp);
10645
10646 Label unlocked, push_and_slow;
10647 const Register top = tmp;
10648
10649 // Check if obj is top of lock-stack.
10650 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10651 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10652 jcc(Assembler::notEqual, slow);
10653
10654 // Pop lock-stack.
10655 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10656 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10657
10658 // Check if recursive.
10659 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10660 jcc(Assembler::equal, unlocked);
10661
10662 // Not recursive. Check header for monitor (0b10).
10663 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10664 testptr(reg_rax, markWord::monitor_value);
10665 jcc(Assembler::notZero, push_and_slow);
10666
10667 #ifdef ASSERT
10668 // Check header not unlocked (0b01).
10669 Label not_unlocked;
10670 testptr(reg_rax, markWord::unlocked_value);
10671 jcc(Assembler::zero, not_unlocked);
10672 stop("fast_unlock already unlocked");
10673 bind(not_unlocked);
10674 #endif
10675
10676 // Try to unlock. Transition lock bits 0b00 => 0b01
10677 movptr(tmp, reg_rax);
10678 orptr(tmp, markWord::unlocked_value);
10679 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10680 jcc(Assembler::equal, unlocked);
10681
10682 bind(push_and_slow);
10683 // Restore lock-stack and handle the unlock in runtime.
10684 #ifdef ASSERT
10685 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10686 movptr(Address(thread, top), obj);
10687 #endif
10688 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10689 jmp(slow);
10690
10691 bind(unlocked);
10692 }
10693
10694 // Saves legacy GPRs state on stack.
10695 void MacroAssembler::save_legacy_gprs() {
10696 subq(rsp, 16 * wordSize);
10697 movq(Address(rsp, 15 * wordSize), rax);
10698 movq(Address(rsp, 14 * wordSize), rcx);
10699 movq(Address(rsp, 13 * wordSize), rdx);
10700 movq(Address(rsp, 12 * wordSize), rbx);
10701 movq(Address(rsp, 10 * wordSize), rbp);
10702 movq(Address(rsp, 9 * wordSize), rsi);
10703 movq(Address(rsp, 8 * wordSize), rdi);
10704 movq(Address(rsp, 7 * wordSize), r8);
10705 movq(Address(rsp, 6 * wordSize), r9);
10706 movq(Address(rsp, 5 * wordSize), r10);
10707 movq(Address(rsp, 4 * wordSize), r11);
10708 movq(Address(rsp, 3 * wordSize), r12);
10709 movq(Address(rsp, 2 * wordSize), r13);
10710 movq(Address(rsp, wordSize), r14);
10711 movq(Address(rsp, 0), r15);
10712 }
10713
10714 // Resotres back legacy GPRs state from stack.
10715 void MacroAssembler::restore_legacy_gprs() {
10716 movq(r15, Address(rsp, 0));
10717 movq(r14, Address(rsp, wordSize));
10718 movq(r13, Address(rsp, 2 * wordSize));
10719 movq(r12, Address(rsp, 3 * wordSize));
10720 movq(r11, Address(rsp, 4 * wordSize));
10721 movq(r10, Address(rsp, 5 * wordSize));
10722 movq(r9, Address(rsp, 6 * wordSize));
10723 movq(r8, Address(rsp, 7 * wordSize));
10724 movq(rdi, Address(rsp, 8 * wordSize));
10725 movq(rsi, Address(rsp, 9 * wordSize));
10726 movq(rbp, Address(rsp, 10 * wordSize));
10727 movq(rbx, Address(rsp, 12 * wordSize));
10728 movq(rdx, Address(rsp, 13 * wordSize));
10729 movq(rcx, Address(rsp, 14 * wordSize));
10730 movq(rax, Address(rsp, 15 * wordSize));
10731 addq(rsp, 16 * wordSize);
10732 }
10733
10734 void MacroAssembler::load_aotrc_address(Register reg, address a) {
10735 #if INCLUDE_CDS
10736 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
10737 if (AOTCodeCache::is_on_for_dump()) {
10738 // all aotrc field addresses should be registered in the AOTCodeCache address table
10739 lea(reg, ExternalAddress(a));
10740 } else {
10741 mov64(reg, (uint64_t)a);
10742 }
10743 #else
10744 ShouldNotReachHere();
10745 #endif
10746 }
10747
10748 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10749 setb(comparison, dst);
10750 movzbl(dst, dst);
10751 }