1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "ci/ciInlineKlass.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "jvm.h"
40 #include "memory/resourceArea.hpp"
41 #include "memory/universe.hpp"
42 #include "oops/accessDecorators.hpp"
43 #include "oops/compressedKlass.inline.hpp"
44 #include "oops/compressedOops.inline.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "oops/resolvedFieldEntry.hpp"
47 #include "prims/methodHandles.hpp"
48 #include "runtime/continuation.hpp"
49 #include "runtime/interfaceSupport.inline.hpp"
50 #include "runtime/javaThread.hpp"
51 #include "runtime/jniHandles.hpp"
52 #include "runtime/objectMonitor.hpp"
53 #include "runtime/os.hpp"
54 #include "runtime/safepoint.hpp"
55 #include "runtime/safepointMechanism.hpp"
56 #include "runtime/sharedRuntime.hpp"
57 #include "runtime/signature_cc.hpp"
58 #include "runtime/stubRoutines.hpp"
59 #include "utilities/checkedCast.hpp"
60 #include "utilities/macros.hpp"
61 #include "vmreg_x86.inline.hpp"
62 #ifdef COMPILER2
63 #include "opto/output.hpp"
64 #endif
65
66 #ifdef PRODUCT
67 #define BLOCK_COMMENT(str) /* nothing */
68 #define STOP(error) stop(error)
69 #else
70 #define BLOCK_COMMENT(str) block_comment(str)
71 #define STOP(error) block_comment(error); stop(error)
72 #endif
73
74 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
75
76 #ifdef ASSERT
77 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
78 #endif
79
80 static const Assembler::Condition reverse[] = {
81 Assembler::noOverflow /* overflow = 0x0 */ ,
82 Assembler::overflow /* noOverflow = 0x1 */ ,
83 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
84 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
85 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
86 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
87 Assembler::above /* belowEqual = 0x6 */ ,
88 Assembler::belowEqual /* above = 0x7 */ ,
89 Assembler::positive /* negative = 0x8 */ ,
90 Assembler::negative /* positive = 0x9 */ ,
91 Assembler::noParity /* parity = 0xa */ ,
92 Assembler::parity /* noParity = 0xb */ ,
93 Assembler::greaterEqual /* less = 0xc */ ,
94 Assembler::less /* greaterEqual = 0xd */ ,
95 Assembler::greater /* lessEqual = 0xe */ ,
96 Assembler::lessEqual /* greater = 0xf, */
97
98 };
99
100
101 // Implementation of MacroAssembler
102
103 // First all the versions that have distinct versions depending on 32/64 bit
104 // Unless the difference is trivial (1 line or so).
105
106 #ifndef _LP64
107
108 // 32bit versions
109
110 Address MacroAssembler::as_Address(AddressLiteral adr) {
111 return Address(adr.target(), adr.rspec());
112 }
113
114 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
115 assert(rscratch == noreg, "");
116 return Address::make_array(adr);
117 }
118
119 void MacroAssembler::call_VM_leaf_base(address entry_point,
120 int number_of_arguments) {
121 call(RuntimeAddress(entry_point));
122 increment(rsp, number_of_arguments * wordSize);
123 }
124
125 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
126 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
127 }
128
129
130 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
131 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
132 }
133
134 void MacroAssembler::cmpoop(Address src1, jobject obj) {
135 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
136 }
137
138 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) {
139 assert(rscratch == noreg, "redundant");
140 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
141 }
142
143 void MacroAssembler::extend_sign(Register hi, Register lo) {
144 // According to Intel Doc. AP-526, "Integer Divide", p.18.
145 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
146 cdql();
147 } else {
148 movl(hi, lo);
149 sarl(hi, 31);
150 }
151 }
152
153 void MacroAssembler::jC2(Register tmp, Label& L) {
154 // set parity bit if FPU flag C2 is set (via rax)
155 save_rax(tmp);
156 fwait(); fnstsw_ax();
157 sahf();
158 restore_rax(tmp);
159 // branch
160 jcc(Assembler::parity, L);
161 }
162
163 void MacroAssembler::jnC2(Register tmp, Label& L) {
164 // set parity bit if FPU flag C2 is set (via rax)
165 save_rax(tmp);
166 fwait(); fnstsw_ax();
167 sahf();
168 restore_rax(tmp);
169 // branch
170 jcc(Assembler::noParity, L);
171 }
172
173 // 32bit can do a case table jump in one instruction but we no longer allow the base
174 // to be installed in the Address class
175 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
176 assert(rscratch == noreg, "not needed");
177 jmp(as_Address(entry, noreg));
178 }
179
180 // Note: y_lo will be destroyed
181 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
182 // Long compare for Java (semantics as described in JVM spec.)
183 Label high, low, done;
184
185 cmpl(x_hi, y_hi);
186 jcc(Assembler::less, low);
187 jcc(Assembler::greater, high);
188 // x_hi is the return register
189 xorl(x_hi, x_hi);
190 cmpl(x_lo, y_lo);
191 jcc(Assembler::below, low);
192 jcc(Assembler::equal, done);
193
194 bind(high);
195 xorl(x_hi, x_hi);
196 increment(x_hi);
197 jmp(done);
198
199 bind(low);
200 xorl(x_hi, x_hi);
201 decrementl(x_hi);
202
203 bind(done);
204 }
205
206 void MacroAssembler::lea(Register dst, AddressLiteral src) {
207 mov_literal32(dst, (int32_t)src.target(), src.rspec());
208 }
209
210 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
211 assert(rscratch == noreg, "not needed");
212
213 // leal(dst, as_Address(adr));
214 // see note in movl as to why we must use a move
215 mov_literal32(dst, (int32_t)adr.target(), adr.rspec());
216 }
217
218 void MacroAssembler::leave() {
219 mov(rsp, rbp);
220 pop(rbp);
221 }
222
223 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
224 // Multiplication of two Java long values stored on the stack
225 // as illustrated below. Result is in rdx:rax.
226 //
227 // rsp ---> [ ?? ] \ \
228 // .... | y_rsp_offset |
229 // [ y_lo ] / (in bytes) | x_rsp_offset
230 // [ y_hi ] | (in bytes)
231 // .... |
232 // [ x_lo ] /
233 // [ x_hi ]
234 // ....
235 //
236 // Basic idea: lo(result) = lo(x_lo * y_lo)
237 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
238 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
239 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
240 Label quick;
241 // load x_hi, y_hi and check if quick
242 // multiplication is possible
243 movl(rbx, x_hi);
244 movl(rcx, y_hi);
245 movl(rax, rbx);
246 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
247 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
248 // do full multiplication
249 // 1st step
250 mull(y_lo); // x_hi * y_lo
251 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
252 // 2nd step
253 movl(rax, x_lo);
254 mull(rcx); // x_lo * y_hi
255 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
256 // 3rd step
257 bind(quick); // note: rbx, = 0 if quick multiply!
258 movl(rax, x_lo);
259 mull(y_lo); // x_lo * y_lo
260 addl(rdx, rbx); // correct hi(x_lo * y_lo)
261 }
262
263 void MacroAssembler::lneg(Register hi, Register lo) {
264 negl(lo);
265 adcl(hi, 0);
266 negl(hi);
267 }
268
269 void MacroAssembler::lshl(Register hi, Register lo) {
270 // Java shift left long support (semantics as described in JVM spec., p.305)
271 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
272 // shift value is in rcx !
273 assert(hi != rcx, "must not use rcx");
274 assert(lo != rcx, "must not use rcx");
275 const Register s = rcx; // shift count
276 const int n = BitsPerWord;
277 Label L;
278 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
279 cmpl(s, n); // if (s < n)
280 jcc(Assembler::less, L); // else (s >= n)
281 movl(hi, lo); // x := x << n
282 xorl(lo, lo);
283 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
284 bind(L); // s (mod n) < n
285 shldl(hi, lo); // x := x << s
286 shll(lo);
287 }
288
289
290 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
291 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
292 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
293 assert(hi != rcx, "must not use rcx");
294 assert(lo != rcx, "must not use rcx");
295 const Register s = rcx; // shift count
296 const int n = BitsPerWord;
297 Label L;
298 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
299 cmpl(s, n); // if (s < n)
300 jcc(Assembler::less, L); // else (s >= n)
301 movl(lo, hi); // x := x >> n
302 if (sign_extension) sarl(hi, 31);
303 else xorl(hi, hi);
304 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
305 bind(L); // s (mod n) < n
306 shrdl(lo, hi); // x := x >> s
307 if (sign_extension) sarl(hi);
308 else shrl(hi);
309 }
310
311 void MacroAssembler::movoop(Register dst, jobject obj) {
312 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
313 }
314
315 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
316 assert(rscratch == noreg, "redundant");
317 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
318 }
319
320 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
321 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
322 }
323
324 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
325 assert(rscratch == noreg, "redundant");
326 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
327 }
328
329 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
330 if (src.is_lval()) {
331 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
332 } else {
333 movl(dst, as_Address(src));
334 }
335 }
336
337 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
338 assert(rscratch == noreg, "redundant");
339 movl(as_Address(dst, noreg), src);
340 }
341
342 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
343 movl(dst, as_Address(src, noreg));
344 }
345
346 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
347 assert(rscratch == noreg, "redundant");
348 movl(dst, src);
349 }
350
351 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
352 assert(rscratch == noreg, "redundant");
353 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
354 }
355
356 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
357 assert(rscratch == noreg, "redundant");
358 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
359 }
360
361 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
362 assert(rscratch == noreg, "redundant");
363 if (src.is_lval()) {
364 push_literal32((int32_t)src.target(), src.rspec());
365 } else {
366 pushl(as_Address(src));
367 }
368 }
369
370 static void pass_arg0(MacroAssembler* masm, Register arg) {
371 masm->push(arg);
372 }
373
374 static void pass_arg1(MacroAssembler* masm, Register arg) {
375 masm->push(arg);
376 }
377
378 static void pass_arg2(MacroAssembler* masm, Register arg) {
379 masm->push(arg);
380 }
381
382 static void pass_arg3(MacroAssembler* masm, Register arg) {
383 masm->push(arg);
384 }
385
386 #ifndef PRODUCT
387 extern "C" void findpc(intptr_t x);
388 #endif
389
390 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
391 // In order to get locks to work, we need to fake a in_VM state
392 JavaThread* thread = JavaThread::current();
393 JavaThreadState saved_state = thread->thread_state();
394 thread->set_thread_state(_thread_in_vm);
395 if (ShowMessageBoxOnError) {
396 JavaThread* thread = JavaThread::current();
397 JavaThreadState saved_state = thread->thread_state();
398 thread->set_thread_state(_thread_in_vm);
399 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
400 ttyLocker ttyl;
401 BytecodeCounter::print();
402 }
403 // To see where a verify_oop failed, get $ebx+40/X for this frame.
404 // This is the value of eip which points to where verify_oop will return.
405 if (os::message_box(msg, "Execution stopped, print registers?")) {
406 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
407 BREAKPOINT;
408 }
409 }
410 fatal("DEBUG MESSAGE: %s", msg);
411 }
412
413 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
414 ttyLocker ttyl;
415 DebuggingContext debugging{};
416 tty->print_cr("eip = 0x%08x", eip);
417 #ifndef PRODUCT
418 if ((WizardMode || Verbose) && PrintMiscellaneous) {
419 tty->cr();
420 findpc(eip);
421 tty->cr();
422 }
423 #endif
424 #define PRINT_REG(rax) \
425 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
426 PRINT_REG(rax);
427 PRINT_REG(rbx);
428 PRINT_REG(rcx);
429 PRINT_REG(rdx);
430 PRINT_REG(rdi);
431 PRINT_REG(rsi);
432 PRINT_REG(rbp);
433 PRINT_REG(rsp);
434 #undef PRINT_REG
435 // Print some words near top of staack.
436 int* dump_sp = (int*) rsp;
437 for (int col1 = 0; col1 < 8; col1++) {
438 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
439 os::print_location(tty, *dump_sp++);
440 }
441 for (int row = 0; row < 16; row++) {
442 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
443 for (int col = 0; col < 8; col++) {
444 tty->print(" 0x%08x", *dump_sp++);
445 }
446 tty->cr();
447 }
448 // Print some instructions around pc:
449 Disassembler::decode((address)eip-64, (address)eip);
450 tty->print_cr("--------");
451 Disassembler::decode((address)eip, (address)eip+32);
452 }
453
454 void MacroAssembler::stop(const char* msg) {
455 // push address of message
456 ExternalAddress message((address)msg);
457 pushptr(message.addr(), noreg);
458 { Label L; call(L, relocInfo::none); bind(L); } // push eip
459 pusha(); // push registers
460 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
461 hlt();
462 }
463
464 void MacroAssembler::warn(const char* msg) {
465 push_CPU_state();
466
467 // push address of message
468 ExternalAddress message((address)msg);
469 pushptr(message.addr(), noreg);
470
471 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
472 addl(rsp, wordSize); // discard argument
473 pop_CPU_state();
474 }
475
476 void MacroAssembler::print_state() {
477 { Label L; call(L, relocInfo::none); bind(L); } // push eip
478 pusha(); // push registers
479
480 push_CPU_state();
481 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
482 pop_CPU_state();
483
484 popa();
485 addl(rsp, wordSize);
486 }
487
488 #else // _LP64
489
490 // 64 bit versions
491
492 Address MacroAssembler::as_Address(AddressLiteral adr) {
493 // amd64 always does this as a pc-rel
494 // we can be absolute or disp based on the instruction type
495 // jmp/call are displacements others are absolute
496 assert(!adr.is_lval(), "must be rval");
497 assert(reachable(adr), "must be");
498 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
499
500 }
501
502 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
503 AddressLiteral base = adr.base();
504 lea(rscratch, base);
505 Address index = adr.index();
506 assert(index._disp == 0, "must not have disp"); // maybe it can?
507 Address array(rscratch, index._index, index._scale, index._disp);
508 return array;
509 }
510
511 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
512 Label L, E;
513
514 #ifdef _WIN64
515 // Windows always allocates space for it's register args
516 assert(num_args <= 4, "only register arguments supported");
517 subq(rsp, frame::arg_reg_save_area_bytes);
518 #endif
519
520 // Align stack if necessary
521 testl(rsp, 15);
522 jcc(Assembler::zero, L);
523
524 subq(rsp, 8);
525 call(RuntimeAddress(entry_point));
526 addq(rsp, 8);
527 jmp(E);
528
529 bind(L);
530 call(RuntimeAddress(entry_point));
531
532 bind(E);
533
534 #ifdef _WIN64
535 // restore stack pointer
536 addq(rsp, frame::arg_reg_save_area_bytes);
537 #endif
538
539 }
540
541 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
542 assert(!src2.is_lval(), "should use cmpptr");
543 assert(rscratch != noreg || always_reachable(src2), "missing");
544
545 if (reachable(src2)) {
546 cmpq(src1, as_Address(src2));
547 } else {
548 lea(rscratch, src2);
549 Assembler::cmpq(src1, Address(rscratch, 0));
550 }
551 }
552
553 int MacroAssembler::corrected_idivq(Register reg) {
554 // Full implementation of Java ldiv and lrem; checks for special
555 // case as described in JVM spec., p.243 & p.271. The function
556 // returns the (pc) offset of the idivl instruction - may be needed
557 // for implicit exceptions.
558 //
559 // normal case special case
560 //
561 // input : rax: dividend min_long
562 // reg: divisor (may not be eax/edx) -1
563 //
564 // output: rax: quotient (= rax idiv reg) min_long
565 // rdx: remainder (= rax irem reg) 0
566 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
567 static const int64_t min_long = 0x8000000000000000;
568 Label normal_case, special_case;
569
570 // check for special case
571 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
572 jcc(Assembler::notEqual, normal_case);
573 xorl(rdx, rdx); // prepare rdx for possible special case (where
574 // remainder = 0)
575 cmpq(reg, -1);
576 jcc(Assembler::equal, special_case);
577
578 // handle normal case
579 bind(normal_case);
580 cdqq();
581 int idivq_offset = offset();
582 idivq(reg);
583
584 // normal and special case exit
585 bind(special_case);
586
587 return idivq_offset;
588 }
589
590 void MacroAssembler::decrementq(Register reg, int value) {
591 if (value == min_jint) { subq(reg, value); return; }
592 if (value < 0) { incrementq(reg, -value); return; }
593 if (value == 0) { ; return; }
594 if (value == 1 && UseIncDec) { decq(reg) ; return; }
595 /* else */ { subq(reg, value) ; return; }
596 }
597
598 void MacroAssembler::decrementq(Address dst, int value) {
599 if (value == min_jint) { subq(dst, value); return; }
600 if (value < 0) { incrementq(dst, -value); return; }
601 if (value == 0) { ; return; }
602 if (value == 1 && UseIncDec) { decq(dst) ; return; }
603 /* else */ { subq(dst, value) ; return; }
604 }
605
606 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
607 assert(rscratch != noreg || always_reachable(dst), "missing");
608
609 if (reachable(dst)) {
610 incrementq(as_Address(dst));
611 } else {
612 lea(rscratch, dst);
613 incrementq(Address(rscratch, 0));
614 }
615 }
616
617 void MacroAssembler::incrementq(Register reg, int value) {
618 if (value == min_jint) { addq(reg, value); return; }
619 if (value < 0) { decrementq(reg, -value); return; }
620 if (value == 0) { ; return; }
621 if (value == 1 && UseIncDec) { incq(reg) ; return; }
622 /* else */ { addq(reg, value) ; return; }
623 }
624
625 void MacroAssembler::incrementq(Address dst, int value) {
626 if (value == min_jint) { addq(dst, value); return; }
627 if (value < 0) { decrementq(dst, -value); return; }
628 if (value == 0) { ; return; }
629 if (value == 1 && UseIncDec) { incq(dst) ; return; }
630 /* else */ { addq(dst, value) ; return; }
631 }
632
633 // 32bit can do a case table jump in one instruction but we no longer allow the base
634 // to be installed in the Address class
635 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
636 lea(rscratch, entry.base());
637 Address dispatch = entry.index();
638 assert(dispatch._base == noreg, "must be");
639 dispatch._base = rscratch;
640 jmp(dispatch);
641 }
642
643 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
644 ShouldNotReachHere(); // 64bit doesn't use two regs
645 cmpq(x_lo, y_lo);
646 }
647
648 void MacroAssembler::lea(Register dst, AddressLiteral src) {
649 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
650 }
651
652 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
653 lea(rscratch, adr);
654 movptr(dst, rscratch);
655 }
656
657 void MacroAssembler::leave() {
658 // %%% is this really better? Why not on 32bit too?
659 emit_int8((unsigned char)0xC9); // LEAVE
660 }
661
662 void MacroAssembler::lneg(Register hi, Register lo) {
663 ShouldNotReachHere(); // 64bit doesn't use two regs
664 negq(lo);
665 }
666
667 void MacroAssembler::movoop(Register dst, jobject obj) {
668 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
669 }
670
671 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
672 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
673 movq(dst, rscratch);
674 }
675
676 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
677 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
678 }
679
680 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
681 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
682 movq(dst, rscratch);
683 }
684
685 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
686 if (src.is_lval()) {
687 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
688 } else {
689 if (reachable(src)) {
690 movq(dst, as_Address(src));
691 } else {
692 lea(dst, src);
693 movq(dst, Address(dst, 0));
694 }
695 }
696 }
697
698 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
699 movq(as_Address(dst, rscratch), src);
700 }
701
702 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
703 movq(dst, as_Address(src, dst /*rscratch*/));
704 }
705
706 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
707 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
708 if (is_simm32(src)) {
709 movptr(dst, checked_cast<int32_t>(src));
710 } else {
711 mov64(rscratch, src);
712 movq(dst, rscratch);
713 }
714 }
715
716 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
717 movoop(rscratch, obj);
718 push(rscratch);
719 }
720
721 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
722 mov_metadata(rscratch, obj);
723 push(rscratch);
724 }
725
726 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
727 lea(rscratch, src);
728 if (src.is_lval()) {
729 push(rscratch);
730 } else {
731 pushq(Address(rscratch, 0));
732 }
733 }
734
735 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
736 reset_last_Java_frame(r15_thread, clear_fp);
737 }
738
739 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
740 Register last_java_fp,
741 address last_java_pc,
742 Register rscratch) {
743 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch);
744 }
745
746 static void pass_arg0(MacroAssembler* masm, Register arg) {
747 if (c_rarg0 != arg ) {
748 masm->mov(c_rarg0, arg);
749 }
750 }
751
752 static void pass_arg1(MacroAssembler* masm, Register arg) {
753 if (c_rarg1 != arg ) {
754 masm->mov(c_rarg1, arg);
755 }
756 }
757
758 static void pass_arg2(MacroAssembler* masm, Register arg) {
759 if (c_rarg2 != arg ) {
760 masm->mov(c_rarg2, arg);
761 }
762 }
763
764 static void pass_arg3(MacroAssembler* masm, Register arg) {
765 if (c_rarg3 != arg ) {
766 masm->mov(c_rarg3, arg);
767 }
768 }
769
770 void MacroAssembler::stop(const char* msg) {
771 if (ShowMessageBoxOnError) {
772 address rip = pc();
773 pusha(); // get regs on stack
774 lea(c_rarg1, InternalAddress(rip));
775 movq(c_rarg2, rsp); // pass pointer to regs array
776 }
777 lea(c_rarg0, ExternalAddress((address) msg));
778 andq(rsp, -16); // align stack as required by ABI
779 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
780 hlt();
781 }
782
783 void MacroAssembler::warn(const char* msg) {
784 push(rbp);
785 movq(rbp, rsp);
786 andq(rsp, -16); // align stack as required by push_CPU_state and call
787 push_CPU_state(); // keeps alignment at 16 bytes
788
789 lea(c_rarg0, ExternalAddress((address) msg));
790 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
791
792 pop_CPU_state();
793 mov(rsp, rbp);
794 pop(rbp);
795 }
796
797 void MacroAssembler::print_state() {
798 address rip = pc();
799 pusha(); // get regs on stack
800 push(rbp);
801 movq(rbp, rsp);
802 andq(rsp, -16); // align stack as required by push_CPU_state and call
803 push_CPU_state(); // keeps alignment at 16 bytes
804
805 lea(c_rarg0, InternalAddress(rip));
806 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
807 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
808
809 pop_CPU_state();
810 mov(rsp, rbp);
811 pop(rbp);
812 popa();
813 }
814
815 #ifndef PRODUCT
816 extern "C" void findpc(intptr_t x);
817 #endif
818
819 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
820 // In order to get locks to work, we need to fake a in_VM state
821 if (ShowMessageBoxOnError) {
822 JavaThread* thread = JavaThread::current();
823 JavaThreadState saved_state = thread->thread_state();
824 thread->set_thread_state(_thread_in_vm);
825 #ifndef PRODUCT
826 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
827 ttyLocker ttyl;
828 BytecodeCounter::print();
829 }
830 #endif
831 // To see where a verify_oop failed, get $ebx+40/X for this frame.
832 // XXX correct this offset for amd64
833 // This is the value of eip which points to where verify_oop will return.
834 if (os::message_box(msg, "Execution stopped, print registers?")) {
835 print_state64(pc, regs);
836 BREAKPOINT;
837 }
838 }
839 fatal("DEBUG MESSAGE: %s", msg);
840 }
841
842 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
843 ttyLocker ttyl;
844 DebuggingContext debugging{};
845 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
846 #ifndef PRODUCT
847 tty->cr();
848 findpc(pc);
849 tty->cr();
850 #endif
851 #define PRINT_REG(rax, value) \
852 { tty->print("%s = ", #rax); os::print_location(tty, value); }
853 PRINT_REG(rax, regs[15]);
854 PRINT_REG(rbx, regs[12]);
855 PRINT_REG(rcx, regs[14]);
856 PRINT_REG(rdx, regs[13]);
857 PRINT_REG(rdi, regs[8]);
858 PRINT_REG(rsi, regs[9]);
859 PRINT_REG(rbp, regs[10]);
860 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
861 PRINT_REG(rsp, (intptr_t)(®s[16]));
862 PRINT_REG(r8 , regs[7]);
863 PRINT_REG(r9 , regs[6]);
864 PRINT_REG(r10, regs[5]);
865 PRINT_REG(r11, regs[4]);
866 PRINT_REG(r12, regs[3]);
867 PRINT_REG(r13, regs[2]);
868 PRINT_REG(r14, regs[1]);
869 PRINT_REG(r15, regs[0]);
870 #undef PRINT_REG
871 // Print some words near the top of the stack.
872 int64_t* rsp = ®s[16];
873 int64_t* dump_sp = rsp;
874 for (int col1 = 0; col1 < 8; col1++) {
875 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
876 os::print_location(tty, *dump_sp++);
877 }
878 for (int row = 0; row < 25; row++) {
879 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
880 for (int col = 0; col < 4; col++) {
881 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
882 }
883 tty->cr();
884 }
885 // Print some instructions around pc:
886 Disassembler::decode((address)pc-64, (address)pc);
887 tty->print_cr("--------");
888 Disassembler::decode((address)pc, (address)pc+32);
889 }
890
891 // The java_calling_convention describes stack locations as ideal slots on
892 // a frame with no abi restrictions. Since we must observe abi restrictions
893 // (like the placement of the register window) the slots must be biased by
894 // the following value.
895 static int reg2offset_in(VMReg r) {
896 // Account for saved rbp and return address
897 // This should really be in_preserve_stack_slots
898 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
899 }
900
901 static int reg2offset_out(VMReg r) {
902 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
903 }
904
905 // A long move
906 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
907
908 // The calling conventions assures us that each VMregpair is either
909 // all really one physical register or adjacent stack slots.
910
911 if (src.is_single_phys_reg() ) {
912 if (dst.is_single_phys_reg()) {
913 if (dst.first() != src.first()) {
914 mov(dst.first()->as_Register(), src.first()->as_Register());
915 }
916 } else {
917 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
918 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
919 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
920 }
921 } else if (dst.is_single_phys_reg()) {
922 assert(src.is_single_reg(), "not a stack pair");
923 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
924 } else {
925 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
926 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
927 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
928 }
929 }
930
931 // A double move
932 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
933
934 // The calling conventions assures us that each VMregpair is either
935 // all really one physical register or adjacent stack slots.
936
937 if (src.is_single_phys_reg() ) {
938 if (dst.is_single_phys_reg()) {
939 // In theory these overlap but the ordering is such that this is likely a nop
940 if ( src.first() != dst.first()) {
941 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
942 }
943 } else {
944 assert(dst.is_single_reg(), "not a stack pair");
945 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
946 }
947 } else if (dst.is_single_phys_reg()) {
948 assert(src.is_single_reg(), "not a stack pair");
949 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
950 } else {
951 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
952 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
953 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
954 }
955 }
956
957
958 // A float arg may have to do float reg int reg conversion
959 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
960 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
961
962 // The calling conventions assures us that each VMregpair is either
963 // all really one physical register or adjacent stack slots.
964
965 if (src.first()->is_stack()) {
966 if (dst.first()->is_stack()) {
967 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
968 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
969 } else {
970 // stack to reg
971 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
972 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
973 }
974 } else if (dst.first()->is_stack()) {
975 // reg to stack
976 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
977 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
978 } else {
979 // reg to reg
980 // In theory these overlap but the ordering is such that this is likely a nop
981 if ( src.first() != dst.first()) {
982 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
983 }
984 }
985 }
986
987 // On 64 bit we will store integer like items to the stack as
988 // 64 bits items (x86_32/64 abi) even though java would only store
989 // 32bits for a parameter. On 32bit it will simply be 32 bits
990 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
991 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
992 if (src.first()->is_stack()) {
993 if (dst.first()->is_stack()) {
994 // stack to stack
995 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
996 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
997 } else {
998 // stack to reg
999 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
1000 }
1001 } else if (dst.first()->is_stack()) {
1002 // reg to stack
1003 // Do we really have to sign extend???
1004 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1005 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
1006 } else {
1007 // Do we really have to sign extend???
1008 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1009 if (dst.first() != src.first()) {
1010 movq(dst.first()->as_Register(), src.first()->as_Register());
1011 }
1012 }
1013 }
1014
1015 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1016 if (src.first()->is_stack()) {
1017 if (dst.first()->is_stack()) {
1018 // stack to stack
1019 movq(rax, Address(rbp, reg2offset_in(src.first())));
1020 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1021 } else {
1022 // stack to reg
1023 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1024 }
1025 } else if (dst.first()->is_stack()) {
1026 // reg to stack
1027 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1028 } else {
1029 if (dst.first() != src.first()) {
1030 movq(dst.first()->as_Register(), src.first()->as_Register());
1031 }
1032 }
1033 }
1034
1035 // An oop arg. Must pass a handle not the oop itself
1036 void MacroAssembler::object_move(OopMap* map,
1037 int oop_handle_offset,
1038 int framesize_in_slots,
1039 VMRegPair src,
1040 VMRegPair dst,
1041 bool is_receiver,
1042 int* receiver_offset) {
1043
1044 // must pass a handle. First figure out the location we use as a handle
1045
1046 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1047
1048 // See if oop is null if it is we need no handle
1049
1050 if (src.first()->is_stack()) {
1051
1052 // Oop is already on the stack as an argument
1053 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1054 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1055 if (is_receiver) {
1056 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1057 }
1058
1059 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
1060 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1061 // conditionally move a null
1062 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1063 } else {
1064
1065 // Oop is in a register we must store it to the space we reserve
1066 // on the stack for oop_handles and pass a handle if oop is non-null
1067
1068 const Register rOop = src.first()->as_Register();
1069 int oop_slot;
1070 if (rOop == j_rarg0)
1071 oop_slot = 0;
1072 else if (rOop == j_rarg1)
1073 oop_slot = 1;
1074 else if (rOop == j_rarg2)
1075 oop_slot = 2;
1076 else if (rOop == j_rarg3)
1077 oop_slot = 3;
1078 else if (rOop == j_rarg4)
1079 oop_slot = 4;
1080 else {
1081 assert(rOop == j_rarg5, "wrong register");
1082 oop_slot = 5;
1083 }
1084
1085 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1086 int offset = oop_slot*VMRegImpl::stack_slot_size;
1087
1088 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1089 // Store oop in handle area, may be null
1090 movptr(Address(rsp, offset), rOop);
1091 if (is_receiver) {
1092 *receiver_offset = offset;
1093 }
1094
1095 cmpptr(rOop, NULL_WORD);
1096 lea(rHandle, Address(rsp, offset));
1097 // conditionally move a null from the handle area where it was just stored
1098 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1099 }
1100
1101 // If arg is on the stack then place it otherwise it is already in correct reg.
1102 if (dst.first()->is_stack()) {
1103 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1104 }
1105 }
1106
1107 #endif // _LP64
1108
1109 // Now versions that are common to 32/64 bit
1110
1111 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1112 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1113 }
1114
1115 void MacroAssembler::addptr(Register dst, Register src) {
1116 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1117 }
1118
1119 void MacroAssembler::addptr(Address dst, Register src) {
1120 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1121 }
1122
1123 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1124 assert(rscratch != noreg || always_reachable(src), "missing");
1125
1126 if (reachable(src)) {
1127 Assembler::addsd(dst, as_Address(src));
1128 } else {
1129 lea(rscratch, src);
1130 Assembler::addsd(dst, Address(rscratch, 0));
1131 }
1132 }
1133
1134 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1135 assert(rscratch != noreg || always_reachable(src), "missing");
1136
1137 if (reachable(src)) {
1138 addss(dst, as_Address(src));
1139 } else {
1140 lea(rscratch, src);
1141 addss(dst, Address(rscratch, 0));
1142 }
1143 }
1144
1145 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1146 assert(rscratch != noreg || always_reachable(src), "missing");
1147
1148 if (reachable(src)) {
1149 Assembler::addpd(dst, as_Address(src));
1150 } else {
1151 lea(rscratch, src);
1152 Assembler::addpd(dst, Address(rscratch, 0));
1153 }
1154 }
1155
1156 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
1157 // Stub code is generated once and never copied.
1158 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1159 void MacroAssembler::align64() {
1160 align(64, (uint)(uintptr_t)pc());
1161 }
1162
1163 void MacroAssembler::align32() {
1164 align(32, (uint)(uintptr_t)pc());
1165 }
1166
1167 void MacroAssembler::align(uint modulus) {
1168 // 8273459: Ensure alignment is possible with current segment alignment
1169 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1170 align(modulus, offset());
1171 }
1172
1173 void MacroAssembler::align(uint modulus, uint target) {
1174 if (target % modulus != 0) {
1175 nop(modulus - (target % modulus));
1176 }
1177 }
1178
1179 void MacroAssembler::push_f(XMMRegister r) {
1180 subptr(rsp, wordSize);
1181 movflt(Address(rsp, 0), r);
1182 }
1183
1184 void MacroAssembler::pop_f(XMMRegister r) {
1185 movflt(r, Address(rsp, 0));
1186 addptr(rsp, wordSize);
1187 }
1188
1189 void MacroAssembler::push_d(XMMRegister r) {
1190 subptr(rsp, 2 * wordSize);
1191 movdbl(Address(rsp, 0), r);
1192 }
1193
1194 void MacroAssembler::pop_d(XMMRegister r) {
1195 movdbl(r, Address(rsp, 0));
1196 addptr(rsp, 2 * Interpreter::stackElementSize);
1197 }
1198
1199 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1200 // Used in sign-masking with aligned address.
1201 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1202 assert(rscratch != noreg || always_reachable(src), "missing");
1203
1204 if (reachable(src)) {
1205 Assembler::andpd(dst, as_Address(src));
1206 } else {
1207 lea(rscratch, src);
1208 Assembler::andpd(dst, Address(rscratch, 0));
1209 }
1210 }
1211
1212 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
1213 // Used in sign-masking with aligned address.
1214 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1215 assert(rscratch != noreg || always_reachable(src), "missing");
1216
1217 if (reachable(src)) {
1218 Assembler::andps(dst, as_Address(src));
1219 } else {
1220 lea(rscratch, src);
1221 Assembler::andps(dst, Address(rscratch, 0));
1222 }
1223 }
1224
1225 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1226 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1227 }
1228
1229 #ifdef _LP64
1230 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
1231 assert(rscratch != noreg || always_reachable(src), "missing");
1232
1233 if (reachable(src)) {
1234 andq(dst, as_Address(src));
1235 } else {
1236 lea(rscratch, src);
1237 andq(dst, Address(rscratch, 0));
1238 }
1239 }
1240 #endif
1241
1242 void MacroAssembler::atomic_incl(Address counter_addr) {
1243 lock();
1244 incrementl(counter_addr);
1245 }
1246
1247 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
1248 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1249
1250 if (reachable(counter_addr)) {
1251 atomic_incl(as_Address(counter_addr));
1252 } else {
1253 lea(rscratch, counter_addr);
1254 atomic_incl(Address(rscratch, 0));
1255 }
1256 }
1257
1258 #ifdef _LP64
1259 void MacroAssembler::atomic_incq(Address counter_addr) {
1260 lock();
1261 incrementq(counter_addr);
1262 }
1263
1264 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
1265 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1266
1267 if (reachable(counter_addr)) {
1268 atomic_incq(as_Address(counter_addr));
1269 } else {
1270 lea(rscratch, counter_addr);
1271 atomic_incq(Address(rscratch, 0));
1272 }
1273 }
1274 #endif
1275
1276 // Writes to stack successive pages until offset reached to check for
1277 // stack overflow + shadow pages. This clobbers tmp.
1278 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1279 movptr(tmp, rsp);
1280 // Bang stack for total size given plus shadow page size.
1281 // Bang one page at a time because large size can bang beyond yellow and
1282 // red zones.
1283 Label loop;
1284 bind(loop);
1285 movl(Address(tmp, (-(int)os::vm_page_size())), size );
1286 subptr(tmp, (int)os::vm_page_size());
1287 subl(size, (int)os::vm_page_size());
1288 jcc(Assembler::greater, loop);
1289
1290 // Bang down shadow pages too.
1291 // At this point, (tmp-0) is the last address touched, so don't
1292 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1293 // was post-decremented.) Skip this address by starting at i=1, and
1294 // touch a few more pages below. N.B. It is important to touch all
1295 // the way down including all pages in the shadow zone.
1296 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
1297 // this could be any sized move but this is can be a debugging crumb
1298 // so the bigger the better.
1299 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
1300 }
1301 }
1302
1303 void MacroAssembler::reserved_stack_check() {
1304 // testing if reserved zone needs to be enabled
1305 Label no_reserved_zone_enabling;
1306 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1307 NOT_LP64(get_thread(rsi);)
1308
1309 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1310 jcc(Assembler::below, no_reserved_zone_enabling);
1311
1312 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1313 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
1314 should_not_reach_here();
1315
1316 bind(no_reserved_zone_enabling);
1317 }
1318
1319 void MacroAssembler::c2bool(Register x) {
1320 // implements x == 0 ? 0 : 1
1321 // note: must only look at least-significant byte of x
1322 // since C-style booleans are stored in one byte
1323 // only! (was bug)
1324 andl(x, 0xFF);
1325 setb(Assembler::notZero, x);
1326 }
1327
1328 // Wouldn't need if AddressLiteral version had new name
1329 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1330 Assembler::call(L, rtype);
1331 }
1332
1333 void MacroAssembler::call(Register entry) {
1334 Assembler::call(entry);
1335 }
1336
1337 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
1338 assert(rscratch != noreg || always_reachable(entry), "missing");
1339
1340 if (reachable(entry)) {
1341 Assembler::call_literal(entry.target(), entry.rspec());
1342 } else {
1343 lea(rscratch, entry);
1344 Assembler::call(rscratch);
1345 }
1346 }
1347
1348 void MacroAssembler::ic_call(address entry, jint method_index) {
1349 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1350 #ifdef _LP64
1351 // Needs full 64-bit immediate for later patching.
1352 mov64(rax, (int64_t)Universe::non_oop_word());
1353 #else
1354 movptr(rax, (intptr_t)Universe::non_oop_word());
1355 #endif
1356 call(AddressLiteral(entry, rh));
1357 }
1358
1359 int MacroAssembler::ic_check_size() {
1360 return LP64_ONLY(14) NOT_LP64(12);
1361 }
1362
1363 int MacroAssembler::ic_check(int end_alignment) {
1364 Register receiver = LP64_ONLY(j_rarg0) NOT_LP64(rcx);
1365 Register data = rax;
1366 Register temp = LP64_ONLY(rscratch1) NOT_LP64(rbx);
1367
1368 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1369 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1370 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1371 // before the inline cache check here, and not after
1372 align(end_alignment, offset() + ic_check_size());
1373
1374 int uep_offset = offset();
1375
1376 if (UseCompressedClassPointers) {
1377 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1378 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1379 } else {
1380 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1381 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1382 }
1383
1384 // if inline cache check fails, then jump to runtime routine
1385 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1386 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1387
1388 return uep_offset;
1389 }
1390
1391 void MacroAssembler::emit_static_call_stub() {
1392 // Static stub relocation also tags the Method* in the code-stream.
1393 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1394 // This is recognized as unresolved by relocs/nativeinst/ic code.
1395 jump(RuntimeAddress(pc()));
1396 }
1397
1398 // Implementation of call_VM versions
1399
1400 void MacroAssembler::call_VM(Register oop_result,
1401 address entry_point,
1402 bool check_exceptions) {
1403 Label C, E;
1404 call(C, relocInfo::none);
1405 jmp(E);
1406
1407 bind(C);
1408 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1409 ret(0);
1410
1411 bind(E);
1412 }
1413
1414 void MacroAssembler::call_VM(Register oop_result,
1415 address entry_point,
1416 Register arg_1,
1417 bool check_exceptions) {
1418 Label C, E;
1419 call(C, relocInfo::none);
1420 jmp(E);
1421
1422 bind(C);
1423 pass_arg1(this, arg_1);
1424 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1425 ret(0);
1426
1427 bind(E);
1428 }
1429
1430 void MacroAssembler::call_VM(Register oop_result,
1431 address entry_point,
1432 Register arg_1,
1433 Register arg_2,
1434 bool check_exceptions) {
1435 Label C, E;
1436 call(C, relocInfo::none);
1437 jmp(E);
1438
1439 bind(C);
1440
1441 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1442
1443 pass_arg2(this, arg_2);
1444 pass_arg1(this, arg_1);
1445 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1446 ret(0);
1447
1448 bind(E);
1449 }
1450
1451 void MacroAssembler::call_VM(Register oop_result,
1452 address entry_point,
1453 Register arg_1,
1454 Register arg_2,
1455 Register arg_3,
1456 bool check_exceptions) {
1457 Label C, E;
1458 call(C, relocInfo::none);
1459 jmp(E);
1460
1461 bind(C);
1462
1463 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1464 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1465 pass_arg3(this, arg_3);
1466 pass_arg2(this, arg_2);
1467 pass_arg1(this, arg_1);
1468 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1469 ret(0);
1470
1471 bind(E);
1472 }
1473
1474 void MacroAssembler::call_VM(Register oop_result,
1475 Register last_java_sp,
1476 address entry_point,
1477 int number_of_arguments,
1478 bool check_exceptions) {
1479 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1480 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1481 }
1482
1483 void MacroAssembler::call_VM(Register oop_result,
1484 Register last_java_sp,
1485 address entry_point,
1486 Register arg_1,
1487 bool check_exceptions) {
1488 pass_arg1(this, arg_1);
1489 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1490 }
1491
1492 void MacroAssembler::call_VM(Register oop_result,
1493 Register last_java_sp,
1494 address entry_point,
1495 Register arg_1,
1496 Register arg_2,
1497 bool check_exceptions) {
1498
1499 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1500 pass_arg2(this, arg_2);
1501 pass_arg1(this, arg_1);
1502 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1503 }
1504
1505 void MacroAssembler::call_VM(Register oop_result,
1506 Register last_java_sp,
1507 address entry_point,
1508 Register arg_1,
1509 Register arg_2,
1510 Register arg_3,
1511 bool check_exceptions) {
1512 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1513 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1514 pass_arg3(this, arg_3);
1515 pass_arg2(this, arg_2);
1516 pass_arg1(this, arg_1);
1517 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1518 }
1519
1520 void MacroAssembler::super_call_VM(Register oop_result,
1521 Register last_java_sp,
1522 address entry_point,
1523 int number_of_arguments,
1524 bool check_exceptions) {
1525 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1526 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1527 }
1528
1529 void MacroAssembler::super_call_VM(Register oop_result,
1530 Register last_java_sp,
1531 address entry_point,
1532 Register arg_1,
1533 bool check_exceptions) {
1534 pass_arg1(this, arg_1);
1535 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1536 }
1537
1538 void MacroAssembler::super_call_VM(Register oop_result,
1539 Register last_java_sp,
1540 address entry_point,
1541 Register arg_1,
1542 Register arg_2,
1543 bool check_exceptions) {
1544
1545 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1546 pass_arg2(this, arg_2);
1547 pass_arg1(this, arg_1);
1548 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1549 }
1550
1551 void MacroAssembler::super_call_VM(Register oop_result,
1552 Register last_java_sp,
1553 address entry_point,
1554 Register arg_1,
1555 Register arg_2,
1556 Register arg_3,
1557 bool check_exceptions) {
1558 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1559 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1560 pass_arg3(this, arg_3);
1561 pass_arg2(this, arg_2);
1562 pass_arg1(this, arg_1);
1563 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1564 }
1565
1566 void MacroAssembler::call_VM_base(Register oop_result,
1567 Register java_thread,
1568 Register last_java_sp,
1569 address entry_point,
1570 int number_of_arguments,
1571 bool check_exceptions) {
1572 // determine java_thread register
1573 if (!java_thread->is_valid()) {
1574 #ifdef _LP64
1575 java_thread = r15_thread;
1576 #else
1577 java_thread = rdi;
1578 get_thread(java_thread);
1579 #endif // LP64
1580 }
1581 // determine last_java_sp register
1582 if (!last_java_sp->is_valid()) {
1583 last_java_sp = rsp;
1584 }
1585 // debugging support
1586 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1587 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1588 #ifdef ASSERT
1589 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1590 // r12 is the heapbase.
1591 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1592 #endif // ASSERT
1593
1594 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1595 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1596
1597 // push java thread (becomes first argument of C function)
1598
1599 NOT_LP64(push(java_thread); number_of_arguments++);
1600 LP64_ONLY(mov(c_rarg0, r15_thread));
1601
1602 // set last Java frame before call
1603 assert(last_java_sp != rbp, "can't use ebp/rbp");
1604
1605 // Only interpreter should have to set fp
1606 set_last_Java_frame(java_thread, last_java_sp, rbp, nullptr, rscratch1);
1607
1608 // do the call, remove parameters
1609 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1610
1611 // restore the thread (cannot use the pushed argument since arguments
1612 // may be overwritten by C code generated by an optimizing compiler);
1613 // however can use the register value directly if it is callee saved.
1614 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1615 // rdi & rsi (also r15) are callee saved -> nothing to do
1616 #ifdef ASSERT
1617 guarantee(java_thread != rax, "change this code");
1618 push(rax);
1619 { Label L;
1620 get_thread(rax);
1621 cmpptr(java_thread, rax);
1622 jcc(Assembler::equal, L);
1623 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1624 bind(L);
1625 }
1626 pop(rax);
1627 #endif
1628 } else {
1629 get_thread(java_thread);
1630 }
1631 // reset last Java frame
1632 // Only interpreter should have to clear fp
1633 reset_last_Java_frame(java_thread, true);
1634
1635 // C++ interp handles this in the interpreter
1636 check_and_handle_popframe(java_thread);
1637 check_and_handle_earlyret(java_thread);
1638
1639 if (check_exceptions) {
1640 // check for pending exceptions (java_thread is set upon return)
1641 cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
1642 #ifndef _LP64
1643 jump_cc(Assembler::notEqual,
1644 RuntimeAddress(StubRoutines::forward_exception_entry()));
1645 #else
1646 // This used to conditionally jump to forward_exception however it is
1647 // possible if we relocate that the branch will not reach. So we must jump
1648 // around so we can always reach
1649
1650 Label ok;
1651 jcc(Assembler::equal, ok);
1652 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1653 bind(ok);
1654 #endif // LP64
1655 }
1656
1657 // get oop result if there is one and reset the value in the thread
1658 if (oop_result->is_valid()) {
1659 get_vm_result(oop_result, java_thread);
1660 }
1661 }
1662
1663 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1664
1665 // Calculate the value for last_Java_sp
1666 // somewhat subtle. call_VM does an intermediate call
1667 // which places a return address on the stack just under the
1668 // stack pointer as the user finished with it. This allows
1669 // use to retrieve last_Java_pc from last_Java_sp[-1].
1670 // On 32bit we then have to push additional args on the stack to accomplish
1671 // the actual requested call. On 64bit call_VM only can use register args
1672 // so the only extra space is the return address that call_VM created.
1673 // This hopefully explains the calculations here.
1674
1675 #ifdef _LP64
1676 // We've pushed one address, correct last_Java_sp
1677 lea(rax, Address(rsp, wordSize));
1678 #else
1679 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1680 #endif // LP64
1681
1682 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1683
1684 }
1685
1686 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1687 void MacroAssembler::call_VM_leaf0(address entry_point) {
1688 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1689 }
1690
1691 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1692 call_VM_leaf_base(entry_point, number_of_arguments);
1693 }
1694
1695 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1696 pass_arg0(this, arg_0);
1697 call_VM_leaf(entry_point, 1);
1698 }
1699
1700 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1701
1702 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1703 pass_arg1(this, arg_1);
1704 pass_arg0(this, arg_0);
1705 call_VM_leaf(entry_point, 2);
1706 }
1707
1708 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1709 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1710 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1711 pass_arg2(this, arg_2);
1712 pass_arg1(this, arg_1);
1713 pass_arg0(this, arg_0);
1714 call_VM_leaf(entry_point, 3);
1715 }
1716
1717 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1718 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1719 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1720 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1721 pass_arg3(this, arg_3);
1722 pass_arg2(this, arg_2);
1723 pass_arg1(this, arg_1);
1724 pass_arg0(this, arg_0);
1725 call_VM_leaf(entry_point, 3);
1726 }
1727
1728 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1729 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1730 }
1731
1732 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1733 pass_arg0(this, arg_0);
1734 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1735 }
1736
1737 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1738 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1739 pass_arg1(this, arg_1);
1740 pass_arg0(this, arg_0);
1741 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1742 }
1743
1744 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1745 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1746 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1747 pass_arg2(this, arg_2);
1748 pass_arg1(this, arg_1);
1749 pass_arg0(this, arg_0);
1750 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1751 }
1752
1753 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1754 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1755 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1756 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1757 pass_arg3(this, arg_3);
1758 pass_arg2(this, arg_2);
1759 pass_arg1(this, arg_1);
1760 pass_arg0(this, arg_0);
1761 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1762 }
1763
1764 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1765 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1766 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1767 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1768 }
1769
1770 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1771 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1772 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1773 }
1774
1775 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1776 }
1777
1778 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1779 }
1780
1781 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1782 assert(rscratch != noreg || always_reachable(src1), "missing");
1783
1784 if (reachable(src1)) {
1785 cmpl(as_Address(src1), imm);
1786 } else {
1787 lea(rscratch, src1);
1788 cmpl(Address(rscratch, 0), imm);
1789 }
1790 }
1791
1792 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1793 assert(!src2.is_lval(), "use cmpptr");
1794 assert(rscratch != noreg || always_reachable(src2), "missing");
1795
1796 if (reachable(src2)) {
1797 cmpl(src1, as_Address(src2));
1798 } else {
1799 lea(rscratch, src2);
1800 cmpl(src1, Address(rscratch, 0));
1801 }
1802 }
1803
1804 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1805 Assembler::cmpl(src1, imm);
1806 }
1807
1808 void MacroAssembler::cmp32(Register src1, Address src2) {
1809 Assembler::cmpl(src1, src2);
1810 }
1811
1812 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1813 ucomisd(opr1, opr2);
1814
1815 Label L;
1816 if (unordered_is_less) {
1817 movl(dst, -1);
1818 jcc(Assembler::parity, L);
1819 jcc(Assembler::below , L);
1820 movl(dst, 0);
1821 jcc(Assembler::equal , L);
1822 increment(dst);
1823 } else { // unordered is greater
1824 movl(dst, 1);
1825 jcc(Assembler::parity, L);
1826 jcc(Assembler::above , L);
1827 movl(dst, 0);
1828 jcc(Assembler::equal , L);
1829 decrementl(dst);
1830 }
1831 bind(L);
1832 }
1833
1834 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1835 ucomiss(opr1, opr2);
1836
1837 Label L;
1838 if (unordered_is_less) {
1839 movl(dst, -1);
1840 jcc(Assembler::parity, L);
1841 jcc(Assembler::below , L);
1842 movl(dst, 0);
1843 jcc(Assembler::equal , L);
1844 increment(dst);
1845 } else { // unordered is greater
1846 movl(dst, 1);
1847 jcc(Assembler::parity, L);
1848 jcc(Assembler::above , L);
1849 movl(dst, 0);
1850 jcc(Assembler::equal , L);
1851 decrementl(dst);
1852 }
1853 bind(L);
1854 }
1855
1856
1857 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1858 assert(rscratch != noreg || always_reachable(src1), "missing");
1859
1860 if (reachable(src1)) {
1861 cmpb(as_Address(src1), imm);
1862 } else {
1863 lea(rscratch, src1);
1864 cmpb(Address(rscratch, 0), imm);
1865 }
1866 }
1867
1868 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1869 #ifdef _LP64
1870 assert(rscratch != noreg || always_reachable(src2), "missing");
1871
1872 if (src2.is_lval()) {
1873 movptr(rscratch, src2);
1874 Assembler::cmpq(src1, rscratch);
1875 } else if (reachable(src2)) {
1876 cmpq(src1, as_Address(src2));
1877 } else {
1878 lea(rscratch, src2);
1879 Assembler::cmpq(src1, Address(rscratch, 0));
1880 }
1881 #else
1882 assert(rscratch == noreg, "not needed");
1883 if (src2.is_lval()) {
1884 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1885 } else {
1886 cmpl(src1, as_Address(src2));
1887 }
1888 #endif // _LP64
1889 }
1890
1891 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1892 assert(src2.is_lval(), "not a mem-mem compare");
1893 #ifdef _LP64
1894 // moves src2's literal address
1895 movptr(rscratch, src2);
1896 Assembler::cmpq(src1, rscratch);
1897 #else
1898 assert(rscratch == noreg, "not needed");
1899 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1900 #endif // _LP64
1901 }
1902
1903 void MacroAssembler::cmpoop(Register src1, Register src2) {
1904 cmpptr(src1, src2);
1905 }
1906
1907 void MacroAssembler::cmpoop(Register src1, Address src2) {
1908 cmpptr(src1, src2);
1909 }
1910
1911 #ifdef _LP64
1912 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1913 movoop(rscratch, src2);
1914 cmpptr(src1, rscratch);
1915 }
1916 #endif
1917
1918 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1919 assert(rscratch != noreg || always_reachable(adr), "missing");
1920
1921 if (reachable(adr)) {
1922 lock();
1923 cmpxchgptr(reg, as_Address(adr));
1924 } else {
1925 lea(rscratch, adr);
1926 lock();
1927 cmpxchgptr(reg, Address(rscratch, 0));
1928 }
1929 }
1930
1931 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1932 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1933 }
1934
1935 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1936 assert(rscratch != noreg || always_reachable(src), "missing");
1937
1938 if (reachable(src)) {
1939 Assembler::comisd(dst, as_Address(src));
1940 } else {
1941 lea(rscratch, src);
1942 Assembler::comisd(dst, Address(rscratch, 0));
1943 }
1944 }
1945
1946 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1947 assert(rscratch != noreg || always_reachable(src), "missing");
1948
1949 if (reachable(src)) {
1950 Assembler::comiss(dst, as_Address(src));
1951 } else {
1952 lea(rscratch, src);
1953 Assembler::comiss(dst, Address(rscratch, 0));
1954 }
1955 }
1956
1957
1958 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1959 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1960
1961 Condition negated_cond = negate_condition(cond);
1962 Label L;
1963 jcc(negated_cond, L);
1964 pushf(); // Preserve flags
1965 atomic_incl(counter_addr, rscratch);
1966 popf();
1967 bind(L);
1968 }
1969
1970 int MacroAssembler::corrected_idivl(Register reg) {
1971 // Full implementation of Java idiv and irem; checks for
1972 // special case as described in JVM spec., p.243 & p.271.
1973 // The function returns the (pc) offset of the idivl
1974 // instruction - may be needed for implicit exceptions.
1975 //
1976 // normal case special case
1977 //
1978 // input : rax,: dividend min_int
1979 // reg: divisor (may not be rax,/rdx) -1
1980 //
1981 // output: rax,: quotient (= rax, idiv reg) min_int
1982 // rdx: remainder (= rax, irem reg) 0
1983 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1984 const int min_int = 0x80000000;
1985 Label normal_case, special_case;
1986
1987 // check for special case
1988 cmpl(rax, min_int);
1989 jcc(Assembler::notEqual, normal_case);
1990 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1991 cmpl(reg, -1);
1992 jcc(Assembler::equal, special_case);
1993
1994 // handle normal case
1995 bind(normal_case);
1996 cdql();
1997 int idivl_offset = offset();
1998 idivl(reg);
1999
2000 // normal and special case exit
2001 bind(special_case);
2002
2003 return idivl_offset;
2004 }
2005
2006
2007
2008 void MacroAssembler::decrementl(Register reg, int value) {
2009 if (value == min_jint) {subl(reg, value) ; return; }
2010 if (value < 0) { incrementl(reg, -value); return; }
2011 if (value == 0) { ; return; }
2012 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2013 /* else */ { subl(reg, value) ; return; }
2014 }
2015
2016 void MacroAssembler::decrementl(Address dst, int value) {
2017 if (value == min_jint) {subl(dst, value) ; return; }
2018 if (value < 0) { incrementl(dst, -value); return; }
2019 if (value == 0) { ; return; }
2020 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2021 /* else */ { subl(dst, value) ; return; }
2022 }
2023
2024 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2025 assert(shift_value > 0, "illegal shift value");
2026 Label _is_positive;
2027 testl (reg, reg);
2028 jcc (Assembler::positive, _is_positive);
2029 int offset = (1 << shift_value) - 1 ;
2030
2031 if (offset == 1) {
2032 incrementl(reg);
2033 } else {
2034 addl(reg, offset);
2035 }
2036
2037 bind (_is_positive);
2038 sarl(reg, shift_value);
2039 }
2040
2041 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2042 assert(rscratch != noreg || always_reachable(src), "missing");
2043
2044 if (reachable(src)) {
2045 Assembler::divsd(dst, as_Address(src));
2046 } else {
2047 lea(rscratch, src);
2048 Assembler::divsd(dst, Address(rscratch, 0));
2049 }
2050 }
2051
2052 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2053 assert(rscratch != noreg || always_reachable(src), "missing");
2054
2055 if (reachable(src)) {
2056 Assembler::divss(dst, as_Address(src));
2057 } else {
2058 lea(rscratch, src);
2059 Assembler::divss(dst, Address(rscratch, 0));
2060 }
2061 }
2062
2063 void MacroAssembler::enter() {
2064 push(rbp);
2065 mov(rbp, rsp);
2066 }
2067
2068 void MacroAssembler::post_call_nop() {
2069 if (!Continuations::enabled()) {
2070 return;
2071 }
2072 InstructionMark im(this);
2073 relocate(post_call_nop_Relocation::spec());
2074 InlineSkippedInstructionsCounter skipCounter(this);
2075 emit_int8((uint8_t)0x0f);
2076 emit_int8((uint8_t)0x1f);
2077 emit_int8((uint8_t)0x84);
2078 emit_int8((uint8_t)0x00);
2079 emit_int32(0x00);
2080 }
2081
2082 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2083 void MacroAssembler::fat_nop() {
2084 if (UseAddressNop) {
2085 addr_nop_5();
2086 } else {
2087 emit_int8((uint8_t)0x26); // es:
2088 emit_int8((uint8_t)0x2e); // cs:
2089 emit_int8((uint8_t)0x64); // fs:
2090 emit_int8((uint8_t)0x65); // gs:
2091 emit_int8((uint8_t)0x90);
2092 }
2093 }
2094
2095 #ifndef _LP64
2096 void MacroAssembler::fcmp(Register tmp) {
2097 fcmp(tmp, 1, true, true);
2098 }
2099
2100 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2101 assert(!pop_right || pop_left, "usage error");
2102 if (VM_Version::supports_cmov()) {
2103 assert(tmp == noreg, "unneeded temp");
2104 if (pop_left) {
2105 fucomip(index);
2106 } else {
2107 fucomi(index);
2108 }
2109 if (pop_right) {
2110 fpop();
2111 }
2112 } else {
2113 assert(tmp != noreg, "need temp");
2114 if (pop_left) {
2115 if (pop_right) {
2116 fcompp();
2117 } else {
2118 fcomp(index);
2119 }
2120 } else {
2121 fcom(index);
2122 }
2123 // convert FPU condition into eflags condition via rax,
2124 save_rax(tmp);
2125 fwait(); fnstsw_ax();
2126 sahf();
2127 restore_rax(tmp);
2128 }
2129 // condition codes set as follows:
2130 //
2131 // CF (corresponds to C0) if x < y
2132 // PF (corresponds to C2) if unordered
2133 // ZF (corresponds to C3) if x = y
2134 }
2135
2136 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2137 fcmp2int(dst, unordered_is_less, 1, true, true);
2138 }
2139
2140 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2141 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2142 Label L;
2143 if (unordered_is_less) {
2144 movl(dst, -1);
2145 jcc(Assembler::parity, L);
2146 jcc(Assembler::below , L);
2147 movl(dst, 0);
2148 jcc(Assembler::equal , L);
2149 increment(dst);
2150 } else { // unordered is greater
2151 movl(dst, 1);
2152 jcc(Assembler::parity, L);
2153 jcc(Assembler::above , L);
2154 movl(dst, 0);
2155 jcc(Assembler::equal , L);
2156 decrementl(dst);
2157 }
2158 bind(L);
2159 }
2160
2161 void MacroAssembler::fld_d(AddressLiteral src) {
2162 fld_d(as_Address(src));
2163 }
2164
2165 void MacroAssembler::fld_s(AddressLiteral src) {
2166 fld_s(as_Address(src));
2167 }
2168
2169 void MacroAssembler::fldcw(AddressLiteral src) {
2170 fldcw(as_Address(src));
2171 }
2172
2173 void MacroAssembler::fpop() {
2174 ffree();
2175 fincstp();
2176 }
2177
2178 void MacroAssembler::fremr(Register tmp) {
2179 save_rax(tmp);
2180 { Label L;
2181 bind(L);
2182 fprem();
2183 fwait(); fnstsw_ax();
2184 sahf();
2185 jcc(Assembler::parity, L);
2186 }
2187 restore_rax(tmp);
2188 // Result is in ST0.
2189 // Note: fxch & fpop to get rid of ST1
2190 // (otherwise FPU stack could overflow eventually)
2191 fxch(1);
2192 fpop();
2193 }
2194
2195 void MacroAssembler::empty_FPU_stack() {
2196 if (VM_Version::supports_mmx()) {
2197 emms();
2198 } else {
2199 for (int i = 8; i-- > 0; ) ffree(i);
2200 }
2201 }
2202 #endif // !LP64
2203
2204 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2205 assert(rscratch != noreg || always_reachable(src), "missing");
2206 if (reachable(src)) {
2207 Assembler::mulpd(dst, as_Address(src));
2208 } else {
2209 lea(rscratch, src);
2210 Assembler::mulpd(dst, Address(rscratch, 0));
2211 }
2212 }
2213
2214 void MacroAssembler::load_float(Address src) {
2215 #ifdef _LP64
2216 movflt(xmm0, src);
2217 #else
2218 if (UseSSE >= 1) {
2219 movflt(xmm0, src);
2220 } else {
2221 fld_s(src);
2222 }
2223 #endif // LP64
2224 }
2225
2226 void MacroAssembler::store_float(Address dst) {
2227 #ifdef _LP64
2228 movflt(dst, xmm0);
2229 #else
2230 if (UseSSE >= 1) {
2231 movflt(dst, xmm0);
2232 } else {
2233 fstp_s(dst);
2234 }
2235 #endif // LP64
2236 }
2237
2238 void MacroAssembler::load_double(Address src) {
2239 #ifdef _LP64
2240 movdbl(xmm0, src);
2241 #else
2242 if (UseSSE >= 2) {
2243 movdbl(xmm0, src);
2244 } else {
2245 fld_d(src);
2246 }
2247 #endif // LP64
2248 }
2249
2250 void MacroAssembler::store_double(Address dst) {
2251 #ifdef _LP64
2252 movdbl(dst, xmm0);
2253 #else
2254 if (UseSSE >= 2) {
2255 movdbl(dst, xmm0);
2256 } else {
2257 fstp_d(dst);
2258 }
2259 #endif // LP64
2260 }
2261
2262 // dst = c = a * b + c
2263 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2264 Assembler::vfmadd231sd(c, a, b);
2265 if (dst != c) {
2266 movdbl(dst, c);
2267 }
2268 }
2269
2270 // dst = c = a * b + c
2271 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2272 Assembler::vfmadd231ss(c, a, b);
2273 if (dst != c) {
2274 movflt(dst, c);
2275 }
2276 }
2277
2278 // dst = c = a * b + c
2279 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2280 Assembler::vfmadd231pd(c, a, b, vector_len);
2281 if (dst != c) {
2282 vmovdqu(dst, c);
2283 }
2284 }
2285
2286 // dst = c = a * b + c
2287 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2288 Assembler::vfmadd231ps(c, a, b, vector_len);
2289 if (dst != c) {
2290 vmovdqu(dst, c);
2291 }
2292 }
2293
2294 // dst = c = a * b + c
2295 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2296 Assembler::vfmadd231pd(c, a, b, vector_len);
2297 if (dst != c) {
2298 vmovdqu(dst, c);
2299 }
2300 }
2301
2302 // dst = c = a * b + c
2303 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2304 Assembler::vfmadd231ps(c, a, b, vector_len);
2305 if (dst != c) {
2306 vmovdqu(dst, c);
2307 }
2308 }
2309
2310 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
2311 assert(rscratch != noreg || always_reachable(dst), "missing");
2312
2313 if (reachable(dst)) {
2314 incrementl(as_Address(dst));
2315 } else {
2316 lea(rscratch, dst);
2317 incrementl(Address(rscratch, 0));
2318 }
2319 }
2320
2321 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
2322 incrementl(as_Address(dst, rscratch));
2323 }
2324
2325 void MacroAssembler::incrementl(Register reg, int value) {
2326 if (value == min_jint) {addl(reg, value) ; return; }
2327 if (value < 0) { decrementl(reg, -value); return; }
2328 if (value == 0) { ; return; }
2329 if (value == 1 && UseIncDec) { incl(reg) ; return; }
2330 /* else */ { addl(reg, value) ; return; }
2331 }
2332
2333 void MacroAssembler::incrementl(Address dst, int value) {
2334 if (value == min_jint) {addl(dst, value) ; return; }
2335 if (value < 0) { decrementl(dst, -value); return; }
2336 if (value == 0) { ; return; }
2337 if (value == 1 && UseIncDec) { incl(dst) ; return; }
2338 /* else */ { addl(dst, value) ; return; }
2339 }
2340
2341 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
2342 assert(rscratch != noreg || always_reachable(dst), "missing");
2343 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
2344 if (reachable(dst)) {
2345 jmp_literal(dst.target(), dst.rspec());
2346 } else {
2347 lea(rscratch, dst);
2348 jmp(rscratch);
2349 }
2350 }
2351
2352 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
2353 assert(rscratch != noreg || always_reachable(dst), "missing");
2354 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
2355 if (reachable(dst)) {
2356 InstructionMark im(this);
2357 relocate(dst.reloc());
2358 const int short_size = 2;
2359 const int long_size = 6;
2360 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2361 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2362 // 0111 tttn #8-bit disp
2363 emit_int8(0x70 | cc);
2364 emit_int8((offs - short_size) & 0xFF);
2365 } else {
2366 // 0000 1111 1000 tttn #32-bit disp
2367 emit_int8(0x0F);
2368 emit_int8((unsigned char)(0x80 | cc));
2369 emit_int32(offs - long_size);
2370 }
2371 } else {
2372 #ifdef ASSERT
2373 warning("reversing conditional branch");
2374 #endif /* ASSERT */
2375 Label skip;
2376 jccb(reverse[cc], skip);
2377 lea(rscratch, dst);
2378 Assembler::jmp(rscratch);
2379 bind(skip);
2380 }
2381 }
2382
2383 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
2384 assert(rscratch != noreg || always_reachable(src), "missing");
2385
2386 if (reachable(src)) {
2387 Assembler::ldmxcsr(as_Address(src));
2388 } else {
2389 lea(rscratch, src);
2390 Assembler::ldmxcsr(Address(rscratch, 0));
2391 }
2392 }
2393
2394 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2395 int off;
2396 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2397 off = offset();
2398 movsbl(dst, src); // movsxb
2399 } else {
2400 off = load_unsigned_byte(dst, src);
2401 shll(dst, 24);
2402 sarl(dst, 24);
2403 }
2404 return off;
2405 }
2406
2407 // Note: load_signed_short used to be called load_signed_word.
2408 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2409 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2410 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2411 int MacroAssembler::load_signed_short(Register dst, Address src) {
2412 int off;
2413 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2414 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2415 // version but this is what 64bit has always done. This seems to imply
2416 // that users are only using 32bits worth.
2417 off = offset();
2418 movswl(dst, src); // movsxw
2419 } else {
2420 off = load_unsigned_short(dst, src);
2421 shll(dst, 16);
2422 sarl(dst, 16);
2423 }
2424 return off;
2425 }
2426
2427 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2428 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2429 // and "3.9 Partial Register Penalties", p. 22).
2430 int off;
2431 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2432 off = offset();
2433 movzbl(dst, src); // movzxb
2434 } else {
2435 xorl(dst, dst);
2436 off = offset();
2437 movb(dst, src);
2438 }
2439 return off;
2440 }
2441
2442 // Note: load_unsigned_short used to be called load_unsigned_word.
2443 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2444 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2445 // and "3.9 Partial Register Penalties", p. 22).
2446 int off;
2447 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2448 off = offset();
2449 movzwl(dst, src); // movzxw
2450 } else {
2451 xorl(dst, dst);
2452 off = offset();
2453 movw(dst, src);
2454 }
2455 return off;
2456 }
2457
2458 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2459 switch (size_in_bytes) {
2460 #ifndef _LP64
2461 case 8:
2462 assert(dst2 != noreg, "second dest register required");
2463 movl(dst, src);
2464 movl(dst2, src.plus_disp(BytesPerInt));
2465 break;
2466 #else
2467 case 8: movq(dst, src); break;
2468 #endif
2469 case 4: movl(dst, src); break;
2470 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2471 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2472 default: ShouldNotReachHere();
2473 }
2474 }
2475
2476 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2477 switch (size_in_bytes) {
2478 #ifndef _LP64
2479 case 8:
2480 assert(src2 != noreg, "second source register required");
2481 movl(dst, src);
2482 movl(dst.plus_disp(BytesPerInt), src2);
2483 break;
2484 #else
2485 case 8: movq(dst, src); break;
2486 #endif
2487 case 4: movl(dst, src); break;
2488 case 2: movw(dst, src); break;
2489 case 1: movb(dst, src); break;
2490 default: ShouldNotReachHere();
2491 }
2492 }
2493
2494 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
2495 assert(rscratch != noreg || always_reachable(dst), "missing");
2496
2497 if (reachable(dst)) {
2498 movl(as_Address(dst), src);
2499 } else {
2500 lea(rscratch, dst);
2501 movl(Address(rscratch, 0), src);
2502 }
2503 }
2504
2505 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2506 if (reachable(src)) {
2507 movl(dst, as_Address(src));
2508 } else {
2509 lea(dst, src);
2510 movl(dst, Address(dst, 0));
2511 }
2512 }
2513
2514 // C++ bool manipulation
2515
2516 void MacroAssembler::movbool(Register dst, Address src) {
2517 if(sizeof(bool) == 1)
2518 movb(dst, src);
2519 else if(sizeof(bool) == 2)
2520 movw(dst, src);
2521 else if(sizeof(bool) == 4)
2522 movl(dst, src);
2523 else
2524 // unsupported
2525 ShouldNotReachHere();
2526 }
2527
2528 void MacroAssembler::movbool(Address dst, bool boolconst) {
2529 if(sizeof(bool) == 1)
2530 movb(dst, (int) boolconst);
2531 else if(sizeof(bool) == 2)
2532 movw(dst, (int) boolconst);
2533 else if(sizeof(bool) == 4)
2534 movl(dst, (int) boolconst);
2535 else
2536 // unsupported
2537 ShouldNotReachHere();
2538 }
2539
2540 void MacroAssembler::movbool(Address dst, Register src) {
2541 if(sizeof(bool) == 1)
2542 movb(dst, src);
2543 else if(sizeof(bool) == 2)
2544 movw(dst, src);
2545 else if(sizeof(bool) == 4)
2546 movl(dst, src);
2547 else
2548 // unsupported
2549 ShouldNotReachHere();
2550 }
2551
2552 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2553 assert(rscratch != noreg || always_reachable(src), "missing");
2554
2555 if (reachable(src)) {
2556 movdl(dst, as_Address(src));
2557 } else {
2558 lea(rscratch, src);
2559 movdl(dst, Address(rscratch, 0));
2560 }
2561 }
2562
2563 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
2564 assert(rscratch != noreg || always_reachable(src), "missing");
2565
2566 if (reachable(src)) {
2567 movq(dst, as_Address(src));
2568 } else {
2569 lea(rscratch, src);
2570 movq(dst, Address(rscratch, 0));
2571 }
2572 }
2573
2574 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2575 assert(rscratch != noreg || always_reachable(src), "missing");
2576
2577 if (reachable(src)) {
2578 if (UseXmmLoadAndClearUpper) {
2579 movsd (dst, as_Address(src));
2580 } else {
2581 movlpd(dst, as_Address(src));
2582 }
2583 } else {
2584 lea(rscratch, src);
2585 if (UseXmmLoadAndClearUpper) {
2586 movsd (dst, Address(rscratch, 0));
2587 } else {
2588 movlpd(dst, Address(rscratch, 0));
2589 }
2590 }
2591 }
2592
2593 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
2594 assert(rscratch != noreg || always_reachable(src), "missing");
2595
2596 if (reachable(src)) {
2597 movss(dst, as_Address(src));
2598 } else {
2599 lea(rscratch, src);
2600 movss(dst, Address(rscratch, 0));
2601 }
2602 }
2603
2604 void MacroAssembler::movptr(Register dst, Register src) {
2605 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2606 }
2607
2608 void MacroAssembler::movptr(Register dst, Address src) {
2609 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2610 }
2611
2612 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2613 void MacroAssembler::movptr(Register dst, intptr_t src) {
2614 #ifdef _LP64
2615 if (is_uimm32(src)) {
2616 movl(dst, checked_cast<uint32_t>(src));
2617 } else if (is_simm32(src)) {
2618 movq(dst, checked_cast<int32_t>(src));
2619 } else {
2620 mov64(dst, src);
2621 }
2622 #else
2623 movl(dst, src);
2624 #endif
2625 }
2626
2627 void MacroAssembler::movptr(Address dst, Register src) {
2628 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2629 }
2630
2631 void MacroAssembler::movptr(Address dst, int32_t src) {
2632 LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src));
2633 }
2634
2635 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2636 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2637 Assembler::movdqu(dst, src);
2638 }
2639
2640 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2641 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2642 Assembler::movdqu(dst, src);
2643 }
2644
2645 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2646 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2647 Assembler::movdqu(dst, src);
2648 }
2649
2650 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2651 assert(rscratch != noreg || always_reachable(src), "missing");
2652
2653 if (reachable(src)) {
2654 movdqu(dst, as_Address(src));
2655 } else {
2656 lea(rscratch, src);
2657 movdqu(dst, Address(rscratch, 0));
2658 }
2659 }
2660
2661 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2662 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2663 Assembler::vmovdqu(dst, src);
2664 }
2665
2666 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2667 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2668 Assembler::vmovdqu(dst, src);
2669 }
2670
2671 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2672 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2673 Assembler::vmovdqu(dst, src);
2674 }
2675
2676 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2677 assert(rscratch != noreg || always_reachable(src), "missing");
2678
2679 if (reachable(src)) {
2680 vmovdqu(dst, as_Address(src));
2681 }
2682 else {
2683 lea(rscratch, src);
2684 vmovdqu(dst, Address(rscratch, 0));
2685 }
2686 }
2687
2688 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2689 assert(rscratch != noreg || always_reachable(src), "missing");
2690
2691 if (vector_len == AVX_512bit) {
2692 evmovdquq(dst, src, AVX_512bit, rscratch);
2693 } else if (vector_len == AVX_256bit) {
2694 vmovdqu(dst, src, rscratch);
2695 } else {
2696 movdqu(dst, src, rscratch);
2697 }
2698 }
2699
2700 void MacroAssembler::kmov(KRegister dst, Address src) {
2701 if (VM_Version::supports_avx512bw()) {
2702 kmovql(dst, src);
2703 } else {
2704 assert(VM_Version::supports_evex(), "");
2705 kmovwl(dst, src);
2706 }
2707 }
2708
2709 void MacroAssembler::kmov(Address dst, KRegister src) {
2710 if (VM_Version::supports_avx512bw()) {
2711 kmovql(dst, src);
2712 } else {
2713 assert(VM_Version::supports_evex(), "");
2714 kmovwl(dst, src);
2715 }
2716 }
2717
2718 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2719 if (VM_Version::supports_avx512bw()) {
2720 kmovql(dst, src);
2721 } else {
2722 assert(VM_Version::supports_evex(), "");
2723 kmovwl(dst, src);
2724 }
2725 }
2726
2727 void MacroAssembler::kmov(Register dst, KRegister src) {
2728 if (VM_Version::supports_avx512bw()) {
2729 kmovql(dst, src);
2730 } else {
2731 assert(VM_Version::supports_evex(), "");
2732 kmovwl(dst, src);
2733 }
2734 }
2735
2736 void MacroAssembler::kmov(KRegister dst, Register src) {
2737 if (VM_Version::supports_avx512bw()) {
2738 kmovql(dst, src);
2739 } else {
2740 assert(VM_Version::supports_evex(), "");
2741 kmovwl(dst, src);
2742 }
2743 }
2744
2745 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2746 assert(rscratch != noreg || always_reachable(src), "missing");
2747
2748 if (reachable(src)) {
2749 kmovql(dst, as_Address(src));
2750 } else {
2751 lea(rscratch, src);
2752 kmovql(dst, Address(rscratch, 0));
2753 }
2754 }
2755
2756 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2757 assert(rscratch != noreg || always_reachable(src), "missing");
2758
2759 if (reachable(src)) {
2760 kmovwl(dst, as_Address(src));
2761 } else {
2762 lea(rscratch, src);
2763 kmovwl(dst, Address(rscratch, 0));
2764 }
2765 }
2766
2767 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2768 int vector_len, Register rscratch) {
2769 assert(rscratch != noreg || always_reachable(src), "missing");
2770
2771 if (reachable(src)) {
2772 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2773 } else {
2774 lea(rscratch, src);
2775 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2776 }
2777 }
2778
2779 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2780 int vector_len, Register rscratch) {
2781 assert(rscratch != noreg || always_reachable(src), "missing");
2782
2783 if (reachable(src)) {
2784 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2785 } else {
2786 lea(rscratch, src);
2787 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2788 }
2789 }
2790
2791 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2792 assert(rscratch != noreg || always_reachable(src), "missing");
2793
2794 if (reachable(src)) {
2795 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2796 } else {
2797 lea(rscratch, src);
2798 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2799 }
2800 }
2801
2802 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2803 assert(rscratch != noreg || always_reachable(src), "missing");
2804
2805 if (reachable(src)) {
2806 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2807 } else {
2808 lea(rscratch, src);
2809 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2810 }
2811 }
2812
2813 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2814 assert(rscratch != noreg || always_reachable(src), "missing");
2815
2816 if (reachable(src)) {
2817 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2818 } else {
2819 lea(rscratch, src);
2820 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2821 }
2822 }
2823
2824 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2825 assert(rscratch != noreg || always_reachable(src), "missing");
2826
2827 if (reachable(src)) {
2828 Assembler::movdqa(dst, as_Address(src));
2829 } else {
2830 lea(rscratch, src);
2831 Assembler::movdqa(dst, Address(rscratch, 0));
2832 }
2833 }
2834
2835 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2836 assert(rscratch != noreg || always_reachable(src), "missing");
2837
2838 if (reachable(src)) {
2839 Assembler::movsd(dst, as_Address(src));
2840 } else {
2841 lea(rscratch, src);
2842 Assembler::movsd(dst, Address(rscratch, 0));
2843 }
2844 }
2845
2846 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2847 assert(rscratch != noreg || always_reachable(src), "missing");
2848
2849 if (reachable(src)) {
2850 Assembler::movss(dst, as_Address(src));
2851 } else {
2852 lea(rscratch, src);
2853 Assembler::movss(dst, Address(rscratch, 0));
2854 }
2855 }
2856
2857 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2858 assert(rscratch != noreg || always_reachable(src), "missing");
2859
2860 if (reachable(src)) {
2861 Assembler::movddup(dst, as_Address(src));
2862 } else {
2863 lea(rscratch, src);
2864 Assembler::movddup(dst, Address(rscratch, 0));
2865 }
2866 }
2867
2868 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2869 assert(rscratch != noreg || always_reachable(src), "missing");
2870
2871 if (reachable(src)) {
2872 Assembler::vmovddup(dst, as_Address(src), vector_len);
2873 } else {
2874 lea(rscratch, src);
2875 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2876 }
2877 }
2878
2879 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2880 assert(rscratch != noreg || always_reachable(src), "missing");
2881
2882 if (reachable(src)) {
2883 Assembler::mulsd(dst, as_Address(src));
2884 } else {
2885 lea(rscratch, src);
2886 Assembler::mulsd(dst, Address(rscratch, 0));
2887 }
2888 }
2889
2890 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2891 assert(rscratch != noreg || always_reachable(src), "missing");
2892
2893 if (reachable(src)) {
2894 Assembler::mulss(dst, as_Address(src));
2895 } else {
2896 lea(rscratch, src);
2897 Assembler::mulss(dst, Address(rscratch, 0));
2898 }
2899 }
2900
2901 void MacroAssembler::null_check(Register reg, int offset) {
2902 if (needs_explicit_null_check(offset)) {
2903 // provoke OS null exception if reg is null by
2904 // accessing M[reg] w/o changing any (non-CC) registers
2905 // NOTE: cmpl is plenty here to provoke a segv
2906 cmpptr(rax, Address(reg, 0));
2907 // Note: should probably use testl(rax, Address(reg, 0));
2908 // may be shorter code (however, this version of
2909 // testl needs to be implemented first)
2910 } else {
2911 // nothing to do, (later) access of M[reg + offset]
2912 // will provoke OS null exception if reg is null
2913 }
2914 }
2915
2916 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2917 andptr(markword, markWord::inline_type_mask_in_place);
2918 cmpptr(markword, markWord::inline_type_pattern);
2919 jcc(Assembler::equal, is_inline_type);
2920 }
2921
2922 void MacroAssembler::test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type) {
2923 movl(temp_reg, Address(klass, Klass::access_flags_offset()));
2924 testl(temp_reg, JVM_ACC_IDENTITY);
2925 jcc(Assembler::zero, is_inline_type);
2926 }
2927
2928 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type) {
2929 testptr(object, object);
2930 jcc(Assembler::zero, not_inline_type);
2931 const int is_inline_type_mask = markWord::inline_type_pattern;
2932 movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2933 andptr(tmp, is_inline_type_mask);
2934 cmpptr(tmp, is_inline_type_mask);
2935 jcc(Assembler::notEqual, not_inline_type);
2936 }
2937
2938 void MacroAssembler::test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type) {
2939 #ifdef ASSERT
2940 {
2941 Label done_check;
2942 test_klass_is_inline_type(klass, temp_reg, done_check);
2943 stop("test_klass_is_empty_inline_type with non inline type klass");
2944 bind(done_check);
2945 }
2946 #endif
2947 movl(temp_reg, Address(klass, InstanceKlass::misc_flags_offset()));
2948 testl(temp_reg, InstanceKlassFlags::is_empty_inline_type_value());
2949 jcc(Assembler::notZero, is_empty_inline_type);
2950 }
2951
2952 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2953 movl(temp_reg, flags);
2954 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2955 jcc(Assembler::notEqual, is_null_free_inline_type);
2956 }
2957
2958 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2959 movl(temp_reg, flags);
2960 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2961 jcc(Assembler::equal, not_null_free_inline_type);
2962 }
2963
2964 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2965 movl(temp_reg, flags);
2966 testl(temp_reg, 1 << ResolvedFieldEntry::is_flat_shift);
2967 jcc(Assembler::notEqual, is_flat);
2968 }
2969
2970 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2971 movl(temp_reg, flags);
2972 testl(temp_reg, 1 << ResolvedFieldEntry::has_null_marker_shift);
2973 jcc(Assembler::notEqual, has_null_marker);
2974 }
2975
2976 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2977 Label test_mark_word;
2978 // load mark word
2979 movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2980 // check displaced
2981 testl(temp_reg, markWord::unlocked_value);
2982 jccb(Assembler::notZero, test_mark_word);
2983 // slow path use klass prototype
2984 push(rscratch1);
2985 load_prototype_header(temp_reg, oop, rscratch1);
2986 pop(rscratch1);
2987
2988 bind(test_mark_word);
2989 testl(temp_reg, test_bit);
2990 jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
2991 }
2992
2993 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg,
2994 Label& is_flat_array) {
2995 #ifdef _LP64
2996 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2997 #else
2998 load_klass(temp_reg, oop, noreg);
2999 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
3000 test_flat_array_layout(temp_reg, is_flat_array);
3001 #endif
3002 }
3003
3004 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
3005 Label& is_non_flat_array) {
3006 #ifdef _LP64
3007 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
3008 #else
3009 load_klass(temp_reg, oop, noreg);
3010 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
3011 test_non_flat_array_layout(temp_reg, is_non_flat_array);
3012 #endif
3013 }
3014
3015 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
3016 #ifdef _LP64
3017 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
3018 #else
3019 Unimplemented();
3020 #endif
3021 }
3022
3023 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
3024 #ifdef _LP64
3025 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
3026 #else
3027 Unimplemented();
3028 #endif
3029 }
3030
3031 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
3032 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
3033 jcc(Assembler::notZero, is_flat_array);
3034 }
3035
3036 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
3037 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
3038 jcc(Assembler::zero, is_non_flat_array);
3039 }
3040
3041 void MacroAssembler::os_breakpoint() {
3042 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3043 // (e.g., MSVC can't call ps() otherwise)
3044 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3045 }
3046
3047 void MacroAssembler::unimplemented(const char* what) {
3048 const char* buf = nullptr;
3049 {
3050 ResourceMark rm;
3051 stringStream ss;
3052 ss.print("unimplemented: %s", what);
3053 buf = code_string(ss.as_string());
3054 }
3055 stop(buf);
3056 }
3057
3058 #ifdef _LP64
3059 #define XSTATE_BV 0x200
3060 #endif
3061
3062 void MacroAssembler::pop_CPU_state() {
3063 pop_FPU_state();
3064 pop_IU_state();
3065 }
3066
3067 void MacroAssembler::pop_FPU_state() {
3068 #ifndef _LP64
3069 frstor(Address(rsp, 0));
3070 #else
3071 fxrstor(Address(rsp, 0));
3072 #endif
3073 addptr(rsp, FPUStateSizeInWords * wordSize);
3074 }
3075
3076 void MacroAssembler::pop_IU_state() {
3077 popa();
3078 LP64_ONLY(addq(rsp, 8));
3079 popf();
3080 }
3081
3082 // Save Integer and Float state
3083 // Warning: Stack must be 16 byte aligned (64bit)
3084 void MacroAssembler::push_CPU_state() {
3085 push_IU_state();
3086 push_FPU_state();
3087 }
3088
3089 void MacroAssembler::push_FPU_state() {
3090 subptr(rsp, FPUStateSizeInWords * wordSize);
3091 #ifndef _LP64
3092 fnsave(Address(rsp, 0));
3093 fwait();
3094 #else
3095 fxsave(Address(rsp, 0));
3096 #endif // LP64
3097 }
3098
3099 void MacroAssembler::push_IU_state() {
3100 // Push flags first because pusha kills them
3101 pushf();
3102 // Make sure rsp stays 16-byte aligned
3103 LP64_ONLY(subq(rsp, 8));
3104 pusha();
3105 }
3106
3107 void MacroAssembler::push_cont_fastpath() {
3108 if (!Continuations::enabled()) return;
3109
3110 #ifndef _LP64
3111 Register rthread = rax;
3112 Register rrealsp = rbx;
3113 push(rthread);
3114 push(rrealsp);
3115
3116 get_thread(rthread);
3117
3118 // The code below wants the original RSP.
3119 // Move it back after the pushes above.
3120 movptr(rrealsp, rsp);
3121 addptr(rrealsp, 2*wordSize);
3122 #else
3123 Register rthread = r15_thread;
3124 Register rrealsp = rsp;
3125 #endif
3126
3127 Label done;
3128 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3129 jccb(Assembler::belowEqual, done);
3130 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp);
3131 bind(done);
3132
3133 #ifndef _LP64
3134 pop(rrealsp);
3135 pop(rthread);
3136 #endif
3137 }
3138
3139 void MacroAssembler::pop_cont_fastpath() {
3140 if (!Continuations::enabled()) return;
3141
3142 #ifndef _LP64
3143 Register rthread = rax;
3144 Register rrealsp = rbx;
3145 push(rthread);
3146 push(rrealsp);
3147
3148 get_thread(rthread);
3149
3150 // The code below wants the original RSP.
3151 // Move it back after the pushes above.
3152 movptr(rrealsp, rsp);
3153 addptr(rrealsp, 2*wordSize);
3154 #else
3155 Register rthread = r15_thread;
3156 Register rrealsp = rsp;
3157 #endif
3158
3159 Label done;
3160 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3161 jccb(Assembler::below, done);
3162 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0);
3163 bind(done);
3164
3165 #ifndef _LP64
3166 pop(rrealsp);
3167 pop(rthread);
3168 #endif
3169 }
3170
3171 void MacroAssembler::inc_held_monitor_count() {
3172 #ifndef _LP64
3173 Register thread = rax;
3174 push(thread);
3175 get_thread(thread);
3176 incrementl(Address(thread, JavaThread::held_monitor_count_offset()));
3177 pop(thread);
3178 #else // LP64
3179 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3180 #endif
3181 }
3182
3183 void MacroAssembler::dec_held_monitor_count() {
3184 #ifndef _LP64
3185 Register thread = rax;
3186 push(thread);
3187 get_thread(thread);
3188 decrementl(Address(thread, JavaThread::held_monitor_count_offset()));
3189 pop(thread);
3190 #else // LP64
3191 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3192 #endif
3193 }
3194
3195 #ifdef ASSERT
3196 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
3197 #ifdef _LP64
3198 Label no_cont;
3199 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
3200 testl(cont, cont);
3201 jcc(Assembler::zero, no_cont);
3202 stop(name);
3203 bind(no_cont);
3204 #else
3205 Unimplemented();
3206 #endif
3207 }
3208 #endif
3209
3210 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3211 if (!java_thread->is_valid()) {
3212 java_thread = rdi;
3213 get_thread(java_thread);
3214 }
3215 // we must set sp to zero to clear frame
3216 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3217 // must clear fp, so that compiled frames are not confused; it is
3218 // possible that we need it only for debugging
3219 if (clear_fp) {
3220 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3221 }
3222 // Always clear the pc because it could have been set by make_walkable()
3223 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3224 vzeroupper();
3225 }
3226
3227 void MacroAssembler::restore_rax(Register tmp) {
3228 if (tmp == noreg) pop(rax);
3229 else if (tmp != rax) mov(rax, tmp);
3230 }
3231
3232 void MacroAssembler::round_to(Register reg, int modulus) {
3233 addptr(reg, modulus - 1);
3234 andptr(reg, -modulus);
3235 }
3236
3237 void MacroAssembler::save_rax(Register tmp) {
3238 if (tmp == noreg) push(rax);
3239 else if (tmp != rax) mov(tmp, rax);
3240 }
3241
3242 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
3243 if (at_return) {
3244 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
3245 // we may safely use rsp instead to perform the stack watermark check.
3246 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
3247 jcc(Assembler::above, slow_path);
3248 return;
3249 }
3250 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
3251 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3252 }
3253
3254 // Calls to C land
3255 //
3256 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3257 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3258 // has to be reset to 0. This is required to allow proper stack traversal.
3259 void MacroAssembler::set_last_Java_frame(Register java_thread,
3260 Register last_java_sp,
3261 Register last_java_fp,
3262 address last_java_pc,
3263 Register rscratch) {
3264 vzeroupper();
3265 // determine java_thread register
3266 if (!java_thread->is_valid()) {
3267 java_thread = rdi;
3268 get_thread(java_thread);
3269 }
3270 // determine last_java_sp register
3271 if (!last_java_sp->is_valid()) {
3272 last_java_sp = rsp;
3273 }
3274 // last_java_fp is optional
3275 if (last_java_fp->is_valid()) {
3276 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3277 }
3278 // last_java_pc is optional
3279 if (last_java_pc != nullptr) {
3280 Address java_pc(java_thread,
3281 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
3282 lea(java_pc, InternalAddress(last_java_pc), rscratch);
3283 }
3284 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3285 }
3286
3287 void MacroAssembler::shlptr(Register dst, int imm8) {
3288 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3289 }
3290
3291 void MacroAssembler::shrptr(Register dst, int imm8) {
3292 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3293 }
3294
3295 void MacroAssembler::sign_extend_byte(Register reg) {
3296 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3297 movsbl(reg, reg); // movsxb
3298 } else {
3299 shll(reg, 24);
3300 sarl(reg, 24);
3301 }
3302 }
3303
3304 void MacroAssembler::sign_extend_short(Register reg) {
3305 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3306 movswl(reg, reg); // movsxw
3307 } else {
3308 shll(reg, 16);
3309 sarl(reg, 16);
3310 }
3311 }
3312
3313 void MacroAssembler::testl(Address dst, int32_t imm32) {
3314 if (imm32 >= 0 && is8bit(imm32)) {
3315 testb(dst, imm32);
3316 } else {
3317 Assembler::testl(dst, imm32);
3318 }
3319 }
3320
3321 void MacroAssembler::testl(Register dst, int32_t imm32) {
3322 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
3323 testb(dst, imm32);
3324 } else {
3325 Assembler::testl(dst, imm32);
3326 }
3327 }
3328
3329 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3330 assert(always_reachable(src), "Address should be reachable");
3331 testl(dst, as_Address(src));
3332 }
3333
3334 #ifdef _LP64
3335
3336 void MacroAssembler::testq(Address dst, int32_t imm32) {
3337 if (imm32 >= 0) {
3338 testl(dst, imm32);
3339 } else {
3340 Assembler::testq(dst, imm32);
3341 }
3342 }
3343
3344 void MacroAssembler::testq(Register dst, int32_t imm32) {
3345 if (imm32 >= 0) {
3346 testl(dst, imm32);
3347 } else {
3348 Assembler::testq(dst, imm32);
3349 }
3350 }
3351
3352 #endif
3353
3354 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3355 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3356 Assembler::pcmpeqb(dst, src);
3357 }
3358
3359 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3360 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3361 Assembler::pcmpeqw(dst, src);
3362 }
3363
3364 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3365 assert((dst->encoding() < 16),"XMM register should be 0-15");
3366 Assembler::pcmpestri(dst, src, imm8);
3367 }
3368
3369 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3370 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3371 Assembler::pcmpestri(dst, src, imm8);
3372 }
3373
3374 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3375 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3376 Assembler::pmovzxbw(dst, src);
3377 }
3378
3379 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3380 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3381 Assembler::pmovzxbw(dst, src);
3382 }
3383
3384 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3385 assert((src->encoding() < 16),"XMM register should be 0-15");
3386 Assembler::pmovmskb(dst, src);
3387 }
3388
3389 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3390 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3391 Assembler::ptest(dst, src);
3392 }
3393
3394 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3395 assert(rscratch != noreg || always_reachable(src), "missing");
3396
3397 if (reachable(src)) {
3398 Assembler::sqrtss(dst, as_Address(src));
3399 } else {
3400 lea(rscratch, src);
3401 Assembler::sqrtss(dst, Address(rscratch, 0));
3402 }
3403 }
3404
3405 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3406 assert(rscratch != noreg || always_reachable(src), "missing");
3407
3408 if (reachable(src)) {
3409 Assembler::subsd(dst, as_Address(src));
3410 } else {
3411 lea(rscratch, src);
3412 Assembler::subsd(dst, Address(rscratch, 0));
3413 }
3414 }
3415
3416 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
3417 assert(rscratch != noreg || always_reachable(src), "missing");
3418
3419 if (reachable(src)) {
3420 Assembler::roundsd(dst, as_Address(src), rmode);
3421 } else {
3422 lea(rscratch, src);
3423 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
3424 }
3425 }
3426
3427 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3428 assert(rscratch != noreg || always_reachable(src), "missing");
3429
3430 if (reachable(src)) {
3431 Assembler::subss(dst, as_Address(src));
3432 } else {
3433 lea(rscratch, src);
3434 Assembler::subss(dst, Address(rscratch, 0));
3435 }
3436 }
3437
3438 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3439 assert(rscratch != noreg || always_reachable(src), "missing");
3440
3441 if (reachable(src)) {
3442 Assembler::ucomisd(dst, as_Address(src));
3443 } else {
3444 lea(rscratch, src);
3445 Assembler::ucomisd(dst, Address(rscratch, 0));
3446 }
3447 }
3448
3449 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3450 assert(rscratch != noreg || always_reachable(src), "missing");
3451
3452 if (reachable(src)) {
3453 Assembler::ucomiss(dst, as_Address(src));
3454 } else {
3455 lea(rscratch, src);
3456 Assembler::ucomiss(dst, Address(rscratch, 0));
3457 }
3458 }
3459
3460 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3461 assert(rscratch != noreg || always_reachable(src), "missing");
3462
3463 // Used in sign-bit flipping with aligned address.
3464 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3465 if (reachable(src)) {
3466 Assembler::xorpd(dst, as_Address(src));
3467 } else {
3468 lea(rscratch, src);
3469 Assembler::xorpd(dst, Address(rscratch, 0));
3470 }
3471 }
3472
3473 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3474 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3475 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3476 }
3477 else {
3478 Assembler::xorpd(dst, src);
3479 }
3480 }
3481
3482 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3483 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3484 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3485 } else {
3486 Assembler::xorps(dst, src);
3487 }
3488 }
3489
3490 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
3491 assert(rscratch != noreg || always_reachable(src), "missing");
3492
3493 // Used in sign-bit flipping with aligned address.
3494 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3495 if (reachable(src)) {
3496 Assembler::xorps(dst, as_Address(src));
3497 } else {
3498 lea(rscratch, src);
3499 Assembler::xorps(dst, Address(rscratch, 0));
3500 }
3501 }
3502
3503 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
3504 assert(rscratch != noreg || always_reachable(src), "missing");
3505
3506 // Used in sign-bit flipping with aligned address.
3507 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3508 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3509 if (reachable(src)) {
3510 Assembler::pshufb(dst, as_Address(src));
3511 } else {
3512 lea(rscratch, src);
3513 Assembler::pshufb(dst, Address(rscratch, 0));
3514 }
3515 }
3516
3517 // AVX 3-operands instructions
3518
3519 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3520 assert(rscratch != noreg || always_reachable(src), "missing");
3521
3522 if (reachable(src)) {
3523 vaddsd(dst, nds, as_Address(src));
3524 } else {
3525 lea(rscratch, src);
3526 vaddsd(dst, nds, Address(rscratch, 0));
3527 }
3528 }
3529
3530 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3531 assert(rscratch != noreg || always_reachable(src), "missing");
3532
3533 if (reachable(src)) {
3534 vaddss(dst, nds, as_Address(src));
3535 } else {
3536 lea(rscratch, src);
3537 vaddss(dst, nds, Address(rscratch, 0));
3538 }
3539 }
3540
3541 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3542 assert(UseAVX > 0, "requires some form of AVX");
3543 assert(rscratch != noreg || always_reachable(src), "missing");
3544
3545 if (reachable(src)) {
3546 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3547 } else {
3548 lea(rscratch, src);
3549 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3550 }
3551 }
3552
3553 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3554 assert(UseAVX > 0, "requires some form of AVX");
3555 assert(rscratch != noreg || always_reachable(src), "missing");
3556
3557 if (reachable(src)) {
3558 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3559 } else {
3560 lea(rscratch, src);
3561 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3562 }
3563 }
3564
3565 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3566 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3567 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3568
3569 vandps(dst, nds, negate_field, vector_len, rscratch);
3570 }
3571
3572 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3573 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3574 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3575
3576 vandpd(dst, nds, negate_field, vector_len, rscratch);
3577 }
3578
3579 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3580 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3581 Assembler::vpaddb(dst, nds, src, vector_len);
3582 }
3583
3584 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3585 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3586 Assembler::vpaddb(dst, nds, src, vector_len);
3587 }
3588
3589 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3590 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3591 Assembler::vpaddw(dst, nds, src, vector_len);
3592 }
3593
3594 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3595 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3596 Assembler::vpaddw(dst, nds, src, vector_len);
3597 }
3598
3599 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3600 assert(rscratch != noreg || always_reachable(src), "missing");
3601
3602 if (reachable(src)) {
3603 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3604 } else {
3605 lea(rscratch, src);
3606 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3607 }
3608 }
3609
3610 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3611 assert(rscratch != noreg || always_reachable(src), "missing");
3612
3613 if (reachable(src)) {
3614 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3615 } else {
3616 lea(rscratch, src);
3617 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3618 }
3619 }
3620
3621 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3622 assert(rscratch != noreg || always_reachable(src), "missing");
3623
3624 if (reachable(src)) {
3625 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3626 } else {
3627 lea(rscratch, src);
3628 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3629 }
3630 }
3631
3632 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3633 assert(rscratch != noreg || always_reachable(src), "missing");
3634
3635 if (reachable(src)) {
3636 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3637 } else {
3638 lea(rscratch, src);
3639 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3640 }
3641 }
3642
3643 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3644 assert(rscratch != noreg || always_reachable(src), "missing");
3645
3646 if (reachable(src)) {
3647 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3648 } else {
3649 lea(rscratch, src);
3650 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3651 }
3652 }
3653
3654 // Vector float blend
3655 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3656 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3657 // WARN: Allow dst == (src1|src2), mask == scratch
3658 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3659 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3660 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3661 if (blend_emulation && scratch_available && dst_available) {
3662 if (compute_mask) {
3663 vpsrad(scratch, mask, 32, vector_len);
3664 mask = scratch;
3665 }
3666 if (dst == src1) {
3667 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3668 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3669 } else {
3670 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3671 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3672 }
3673 vpor(dst, dst, scratch, vector_len);
3674 } else {
3675 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3676 }
3677 }
3678
3679 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3680 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3681 // WARN: Allow dst == (src1|src2), mask == scratch
3682 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3683 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3684 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3685 if (blend_emulation && scratch_available && dst_available) {
3686 if (compute_mask) {
3687 vpxor(scratch, scratch, scratch, vector_len);
3688 vpcmpgtq(scratch, scratch, mask, vector_len);
3689 mask = scratch;
3690 }
3691 if (dst == src1) {
3692 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3693 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3694 } else {
3695 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3696 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3697 }
3698 vpor(dst, dst, scratch, vector_len);
3699 } else {
3700 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3701 }
3702 }
3703
3704 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3705 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3706 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3707 }
3708
3709 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3710 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3711 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3712 }
3713
3714 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3715 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3716 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3717 }
3718
3719 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3720 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3721 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3722 }
3723
3724 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3725 assert(rscratch != noreg || always_reachable(src), "missing");
3726
3727 if (reachable(src)) {
3728 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3729 } else {
3730 lea(rscratch, src);
3731 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3732 }
3733 }
3734
3735 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3736 int comparison, bool is_signed, int vector_len, Register rscratch) {
3737 assert(rscratch != noreg || always_reachable(src), "missing");
3738
3739 if (reachable(src)) {
3740 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3741 } else {
3742 lea(rscratch, src);
3743 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3744 }
3745 }
3746
3747 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3748 int comparison, bool is_signed, int vector_len, Register rscratch) {
3749 assert(rscratch != noreg || always_reachable(src), "missing");
3750
3751 if (reachable(src)) {
3752 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3753 } else {
3754 lea(rscratch, src);
3755 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3756 }
3757 }
3758
3759 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3760 int comparison, bool is_signed, int vector_len, Register rscratch) {
3761 assert(rscratch != noreg || always_reachable(src), "missing");
3762
3763 if (reachable(src)) {
3764 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3765 } else {
3766 lea(rscratch, src);
3767 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3768 }
3769 }
3770
3771 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3772 int comparison, bool is_signed, int vector_len, Register rscratch) {
3773 assert(rscratch != noreg || always_reachable(src), "missing");
3774
3775 if (reachable(src)) {
3776 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3777 } else {
3778 lea(rscratch, src);
3779 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3780 }
3781 }
3782
3783 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3784 if (width == Assembler::Q) {
3785 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3786 } else {
3787 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3788 }
3789 }
3790
3791 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3792 int eq_cond_enc = 0x29;
3793 int gt_cond_enc = 0x37;
3794 if (width != Assembler::Q) {
3795 eq_cond_enc = 0x74 + width;
3796 gt_cond_enc = 0x64 + width;
3797 }
3798 switch (cond) {
3799 case eq:
3800 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3801 break;
3802 case neq:
3803 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3804 vallones(xtmp, vector_len);
3805 vpxor(dst, xtmp, dst, vector_len);
3806 break;
3807 case le:
3808 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3809 vallones(xtmp, vector_len);
3810 vpxor(dst, xtmp, dst, vector_len);
3811 break;
3812 case nlt:
3813 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3814 vallones(xtmp, vector_len);
3815 vpxor(dst, xtmp, dst, vector_len);
3816 break;
3817 case lt:
3818 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3819 break;
3820 case nle:
3821 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3822 break;
3823 default:
3824 assert(false, "Should not reach here");
3825 }
3826 }
3827
3828 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3829 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3830 Assembler::vpmovzxbw(dst, src, vector_len);
3831 }
3832
3833 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3834 assert((src->encoding() < 16),"XMM register should be 0-15");
3835 Assembler::vpmovmskb(dst, src, vector_len);
3836 }
3837
3838 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3839 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3840 Assembler::vpmullw(dst, nds, src, vector_len);
3841 }
3842
3843 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3844 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3845 Assembler::vpmullw(dst, nds, src, vector_len);
3846 }
3847
3848 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3849 assert((UseAVX > 0), "AVX support is needed");
3850 assert(rscratch != noreg || always_reachable(src), "missing");
3851
3852 if (reachable(src)) {
3853 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3854 } else {
3855 lea(rscratch, src);
3856 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3857 }
3858 }
3859
3860 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3861 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3862 Assembler::vpsubb(dst, nds, src, vector_len);
3863 }
3864
3865 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3866 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3867 Assembler::vpsubb(dst, nds, src, vector_len);
3868 }
3869
3870 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3871 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3872 Assembler::vpsubw(dst, nds, src, vector_len);
3873 }
3874
3875 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3876 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3877 Assembler::vpsubw(dst, nds, src, vector_len);
3878 }
3879
3880 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3881 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3882 Assembler::vpsraw(dst, nds, shift, vector_len);
3883 }
3884
3885 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3886 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3887 Assembler::vpsraw(dst, nds, shift, vector_len);
3888 }
3889
3890 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3891 assert(UseAVX > 2,"");
3892 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3893 vector_len = 2;
3894 }
3895 Assembler::evpsraq(dst, nds, shift, vector_len);
3896 }
3897
3898 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3899 assert(UseAVX > 2,"");
3900 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3901 vector_len = 2;
3902 }
3903 Assembler::evpsraq(dst, nds, shift, vector_len);
3904 }
3905
3906 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3907 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3908 Assembler::vpsrlw(dst, nds, shift, vector_len);
3909 }
3910
3911 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3912 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3913 Assembler::vpsrlw(dst, nds, shift, vector_len);
3914 }
3915
3916 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3917 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3918 Assembler::vpsllw(dst, nds, shift, vector_len);
3919 }
3920
3921 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3922 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3923 Assembler::vpsllw(dst, nds, shift, vector_len);
3924 }
3925
3926 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3927 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3928 Assembler::vptest(dst, src);
3929 }
3930
3931 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3932 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3933 Assembler::punpcklbw(dst, src);
3934 }
3935
3936 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3937 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3938 Assembler::pshufd(dst, src, mode);
3939 }
3940
3941 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3942 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3943 Assembler::pshuflw(dst, src, mode);
3944 }
3945
3946 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3947 assert(rscratch != noreg || always_reachable(src), "missing");
3948
3949 if (reachable(src)) {
3950 vandpd(dst, nds, as_Address(src), vector_len);
3951 } else {
3952 lea(rscratch, src);
3953 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3954 }
3955 }
3956
3957 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3958 assert(rscratch != noreg || always_reachable(src), "missing");
3959
3960 if (reachable(src)) {
3961 vandps(dst, nds, as_Address(src), vector_len);
3962 } else {
3963 lea(rscratch, src);
3964 vandps(dst, nds, Address(rscratch, 0), vector_len);
3965 }
3966 }
3967
3968 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3969 bool merge, int vector_len, Register rscratch) {
3970 assert(rscratch != noreg || always_reachable(src), "missing");
3971
3972 if (reachable(src)) {
3973 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3974 } else {
3975 lea(rscratch, src);
3976 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3977 }
3978 }
3979
3980 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3981 assert(rscratch != noreg || always_reachable(src), "missing");
3982
3983 if (reachable(src)) {
3984 vdivsd(dst, nds, as_Address(src));
3985 } else {
3986 lea(rscratch, src);
3987 vdivsd(dst, nds, Address(rscratch, 0));
3988 }
3989 }
3990
3991 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3992 assert(rscratch != noreg || always_reachable(src), "missing");
3993
3994 if (reachable(src)) {
3995 vdivss(dst, nds, as_Address(src));
3996 } else {
3997 lea(rscratch, src);
3998 vdivss(dst, nds, Address(rscratch, 0));
3999 }
4000 }
4001
4002 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
4003 assert(rscratch != noreg || always_reachable(src), "missing");
4004
4005 if (reachable(src)) {
4006 vmulsd(dst, nds, as_Address(src));
4007 } else {
4008 lea(rscratch, src);
4009 vmulsd(dst, nds, Address(rscratch, 0));
4010 }
4011 }
4012
4013 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
4014 assert(rscratch != noreg || always_reachable(src), "missing");
4015
4016 if (reachable(src)) {
4017 vmulss(dst, nds, as_Address(src));
4018 } else {
4019 lea(rscratch, src);
4020 vmulss(dst, nds, Address(rscratch, 0));
4021 }
4022 }
4023
4024 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
4025 assert(rscratch != noreg || always_reachable(src), "missing");
4026
4027 if (reachable(src)) {
4028 vsubsd(dst, nds, as_Address(src));
4029 } else {
4030 lea(rscratch, src);
4031 vsubsd(dst, nds, Address(rscratch, 0));
4032 }
4033 }
4034
4035 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
4036 assert(rscratch != noreg || always_reachable(src), "missing");
4037
4038 if (reachable(src)) {
4039 vsubss(dst, nds, as_Address(src));
4040 } else {
4041 lea(rscratch, src);
4042 vsubss(dst, nds, Address(rscratch, 0));
4043 }
4044 }
4045
4046 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
4047 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4048 assert(rscratch != noreg || always_reachable(src), "missing");
4049
4050 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
4051 }
4052
4053 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
4054 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4055 assert(rscratch != noreg || always_reachable(src), "missing");
4056
4057 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
4058 }
4059
4060 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
4061 assert(rscratch != noreg || always_reachable(src), "missing");
4062
4063 if (reachable(src)) {
4064 vxorpd(dst, nds, as_Address(src), vector_len);
4065 } else {
4066 lea(rscratch, src);
4067 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
4068 }
4069 }
4070
4071 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
4072 assert(rscratch != noreg || always_reachable(src), "missing");
4073
4074 if (reachable(src)) {
4075 vxorps(dst, nds, as_Address(src), vector_len);
4076 } else {
4077 lea(rscratch, src);
4078 vxorps(dst, nds, Address(rscratch, 0), vector_len);
4079 }
4080 }
4081
4082 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
4083 assert(rscratch != noreg || always_reachable(src), "missing");
4084
4085 if (UseAVX > 1 || (vector_len < 1)) {
4086 if (reachable(src)) {
4087 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
4088 } else {
4089 lea(rscratch, src);
4090 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
4091 }
4092 } else {
4093 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
4094 }
4095 }
4096
4097 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
4098 assert(rscratch != noreg || always_reachable(src), "missing");
4099
4100 if (reachable(src)) {
4101 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
4102 } else {
4103 lea(rscratch, src);
4104 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
4105 }
4106 }
4107
4108 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
4109 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
4110 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
4111 // The inverted mask is sign-extended
4112 andptr(possibly_non_local, inverted_mask);
4113 }
4114
4115 void MacroAssembler::resolve_jobject(Register value,
4116 Register thread,
4117 Register tmp) {
4118 assert_different_registers(value, thread, tmp);
4119 Label done, tagged, weak_tagged;
4120 testptr(value, value);
4121 jcc(Assembler::zero, done); // Use null as-is.
4122 testptr(value, JNIHandles::tag_mask); // Test for tag.
4123 jcc(Assembler::notZero, tagged);
4124
4125 // Resolve local handle
4126 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp, thread);
4127 verify_oop(value);
4128 jmp(done);
4129
4130 bind(tagged);
4131 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
4132 jcc(Assembler::notZero, weak_tagged);
4133
4134 // Resolve global handle
4135 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4136 verify_oop(value);
4137 jmp(done);
4138
4139 bind(weak_tagged);
4140 // Resolve jweak.
4141 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4142 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp, thread);
4143 verify_oop(value);
4144
4145 bind(done);
4146 }
4147
4148 void MacroAssembler::resolve_global_jobject(Register value,
4149 Register thread,
4150 Register tmp) {
4151 assert_different_registers(value, thread, tmp);
4152 Label done;
4153
4154 testptr(value, value);
4155 jcc(Assembler::zero, done); // Use null as-is.
4156
4157 #ifdef ASSERT
4158 {
4159 Label valid_global_tag;
4160 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
4161 jcc(Assembler::notZero, valid_global_tag);
4162 stop("non global jobject using resolve_global_jobject");
4163 bind(valid_global_tag);
4164 }
4165 #endif
4166
4167 // Resolve global handle
4168 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4169 verify_oop(value);
4170
4171 bind(done);
4172 }
4173
4174 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4175 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4176 }
4177
4178 // Force generation of a 4 byte immediate value even if it fits into 8bit
4179 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4180 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4181 }
4182
4183 void MacroAssembler::subptr(Register dst, Register src) {
4184 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4185 }
4186
4187 // C++ bool manipulation
4188 void MacroAssembler::testbool(Register dst) {
4189 if(sizeof(bool) == 1)
4190 testb(dst, 0xff);
4191 else if(sizeof(bool) == 2) {
4192 // testw implementation needed for two byte bools
4193 ShouldNotReachHere();
4194 } else if(sizeof(bool) == 4)
4195 testl(dst, dst);
4196 else
4197 // unsupported
4198 ShouldNotReachHere();
4199 }
4200
4201 void MacroAssembler::testptr(Register dst, Register src) {
4202 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4203 }
4204
4205 // Object / value buffer allocation...
4206 //
4207 // Kills klass and rsi on LP64
4208 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
4209 Register t1, Register t2,
4210 bool clear_fields, Label& alloc_failed)
4211 {
4212 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
4213 Register layout_size = t1;
4214 assert(new_obj == rax, "needs to be rax");
4215 assert_different_registers(klass, new_obj, t1, t2);
4216
4217 // get instance_size in InstanceKlass (scaled to a count of bytes)
4218 movl(layout_size, Address(klass, Klass::layout_helper_offset()));
4219 // test to see if it is malformed in some way
4220 testl(layout_size, Klass::_lh_instance_slow_path_bit);
4221 jcc(Assembler::notZero, slow_case_no_pop);
4222
4223 // Allocate the instance:
4224 // If TLAB is enabled:
4225 // Try to allocate in the TLAB.
4226 // If fails, go to the slow path.
4227 // Else If inline contiguous allocations are enabled:
4228 // Try to allocate in eden.
4229 // If fails due to heap end, go to slow path.
4230 //
4231 // If TLAB is enabled OR inline contiguous is enabled:
4232 // Initialize the allocation.
4233 // Exit.
4234 //
4235 // Go to slow path.
4236
4237 push(klass);
4238 const Register thread = LP64_ONLY(r15_thread) NOT_LP64(klass);
4239 #ifndef _LP64
4240 if (UseTLAB) {
4241 get_thread(thread);
4242 }
4243 #endif // _LP64
4244
4245 if (UseTLAB) {
4246 tlab_allocate(thread, new_obj, layout_size, 0, klass, t2, slow_case);
4247 if (ZeroTLAB || (!clear_fields)) {
4248 // the fields have been already cleared
4249 jmp(initialize_header);
4250 } else {
4251 // initialize both the header and fields
4252 jmp(initialize_object);
4253 }
4254 } else {
4255 jmp(slow_case);
4256 }
4257
4258 // If UseTLAB is true, the object is created above and there is an initialize need.
4259 // Otherwise, skip and go to the slow path.
4260 if (UseTLAB) {
4261 if (clear_fields) {
4262 // The object is initialized before the header. If the object size is
4263 // zero, go directly to the header initialization.
4264 bind(initialize_object);
4265 decrement(layout_size, sizeof(oopDesc));
4266 jcc(Assembler::zero, initialize_header);
4267
4268 // Initialize topmost object field, divide size by 8, check if odd and
4269 // test if zero.
4270 Register zero = klass;
4271 xorl(zero, zero); // use zero reg to clear memory (shorter code)
4272 shrl(layout_size, LogBytesPerLong); // divide by 2*oopSize and set carry flag if odd
4273
4274 #ifdef ASSERT
4275 // make sure instance_size was multiple of 8
4276 Label L;
4277 // Ignore partial flag stall after shrl() since it is debug VM
4278 jcc(Assembler::carryClear, L);
4279 stop("object size is not multiple of 2 - adjust this code");
4280 bind(L);
4281 // must be > 0, no extra check needed here
4282 #endif
4283
4284 // initialize remaining object fields: instance_size was a multiple of 8
4285 {
4286 Label loop;
4287 bind(loop);
4288 movptr(Address(new_obj, layout_size, Address::times_8, sizeof(oopDesc) - 1*oopSize), zero);
4289 NOT_LP64(movptr(Address(new_obj, layout_size, Address::times_8, sizeof(oopDesc) - 2*oopSize), zero));
4290 decrement(layout_size);
4291 jcc(Assembler::notZero, loop);
4292 }
4293 } // clear_fields
4294
4295 // initialize object header only.
4296 bind(initialize_header);
4297 pop(klass);
4298 Register mark_word = t2;
4299 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
4300 movptr(Address(new_obj, oopDesc::mark_offset_in_bytes ()), mark_word);
4301 #ifdef _LP64
4302 xorl(rsi, rsi); // use zero reg to clear memory (shorter code)
4303 store_klass_gap(new_obj, rsi); // zero klass gap for compressed oops
4304 #endif
4305 movptr(t2, klass); // preserve klass
4306 store_klass(new_obj, t2, rscratch1); // src klass reg is potentially compressed
4307
4308 jmp(done);
4309 }
4310
4311 bind(slow_case);
4312 pop(klass);
4313 bind(slow_case_no_pop);
4314 jmp(alloc_failed);
4315
4316 bind(done);
4317 }
4318
4319 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4320 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4321 Register var_size_in_bytes,
4322 int con_size_in_bytes,
4323 Register t1,
4324 Register t2,
4325 Label& slow_case) {
4326 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4327 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4328 }
4329
4330 RegSet MacroAssembler::call_clobbered_gp_registers() {
4331 RegSet regs;
4332 #ifdef _LP64
4333 regs += RegSet::of(rax, rcx, rdx);
4334 #ifndef WINDOWS
4335 regs += RegSet::of(rsi, rdi);
4336 #endif
4337 regs += RegSet::range(r8, r11);
4338 #else
4339 regs += RegSet::of(rax, rcx, rdx);
4340 #endif
4341 #ifdef _LP64
4342 if (UseAPX) {
4343 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
4344 }
4345 #endif
4346 return regs;
4347 }
4348
4349 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
4350 int num_xmm_registers = XMMRegister::available_xmm_registers();
4351 #if defined(WINDOWS) && defined(_LP64)
4352 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
4353 if (num_xmm_registers > 16) {
4354 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
4355 }
4356 return result;
4357 #else
4358 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
4359 #endif
4360 }
4361
4362 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
4363
4364 #ifndef _LP64
4365 static bool use_x87_registers() { return UseSSE < 2; }
4366 #endif
4367 static bool use_xmm_registers() { return UseSSE >= 1; }
4368
4369 // C1 only ever uses the first double/float of the XMM register.
4370 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
4371
4372 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4373 if (UseSSE == 1) {
4374 masm->movflt(Address(rsp, offset), reg);
4375 } else {
4376 masm->movdbl(Address(rsp, offset), reg);
4377 }
4378 }
4379
4380 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4381 if (UseSSE == 1) {
4382 masm->movflt(reg, Address(rsp, offset));
4383 } else {
4384 masm->movdbl(reg, Address(rsp, offset));
4385 }
4386 }
4387
4388 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
4389 bool save_fpu, int& gp_area_size,
4390 int& fp_area_size, int& xmm_area_size) {
4391
4392 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
4393 StackAlignmentInBytes);
4394 #ifdef _LP64
4395 fp_area_size = 0;
4396 #else
4397 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
4398 #endif
4399 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
4400
4401 return gp_area_size + fp_area_size + xmm_area_size;
4402 }
4403
4404 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
4405 block_comment("push_call_clobbered_registers start");
4406 // Regular registers
4407 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
4408
4409 int gp_area_size;
4410 int fp_area_size;
4411 int xmm_area_size;
4412 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
4413 gp_area_size, fp_area_size, xmm_area_size);
4414 subptr(rsp, total_save_size);
4415
4416 push_set(gp_registers_to_push, 0);
4417
4418 #ifndef _LP64
4419 if (save_fpu && use_x87_registers()) {
4420 fnsave(Address(rsp, gp_area_size));
4421 fwait();
4422 }
4423 #endif
4424 if (save_fpu && use_xmm_registers()) {
4425 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4426 }
4427
4428 block_comment("push_call_clobbered_registers end");
4429 }
4430
4431 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
4432 block_comment("pop_call_clobbered_registers start");
4433
4434 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
4435
4436 int gp_area_size;
4437 int fp_area_size;
4438 int xmm_area_size;
4439 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
4440 gp_area_size, fp_area_size, xmm_area_size);
4441
4442 if (restore_fpu && use_xmm_registers()) {
4443 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4444 }
4445 #ifndef _LP64
4446 if (restore_fpu && use_x87_registers()) {
4447 frstor(Address(rsp, gp_area_size));
4448 }
4449 #endif
4450
4451 pop_set(gp_registers_to_pop, 0);
4452
4453 addptr(rsp, total_save_size);
4454
4455 vzeroupper();
4456
4457 block_comment("pop_call_clobbered_registers end");
4458 }
4459
4460 void MacroAssembler::push_set(XMMRegSet set, int offset) {
4461 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
4462 int spill_offset = offset;
4463
4464 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
4465 save_xmm_register(this, spill_offset, *it);
4466 spill_offset += xmm_save_size();
4467 }
4468 }
4469
4470 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
4471 int restore_size = set.size() * xmm_save_size();
4472 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
4473
4474 int restore_offset = offset + restore_size - xmm_save_size();
4475
4476 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
4477 restore_xmm_register(this, restore_offset, *it);
4478 restore_offset -= xmm_save_size();
4479 }
4480 }
4481
4482 void MacroAssembler::push_set(RegSet set, int offset) {
4483 int spill_offset;
4484 if (offset == -1) {
4485 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4486 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4487 subptr(rsp, aligned_size);
4488 spill_offset = 0;
4489 } else {
4490 spill_offset = offset;
4491 }
4492
4493 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
4494 movptr(Address(rsp, spill_offset), *it);
4495 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4496 }
4497 }
4498
4499 void MacroAssembler::pop_set(RegSet set, int offset) {
4500
4501 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4502 int restore_size = set.size() * gp_reg_size;
4503 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
4504
4505 int restore_offset;
4506 if (offset == -1) {
4507 restore_offset = restore_size - gp_reg_size;
4508 } else {
4509 restore_offset = offset + restore_size - gp_reg_size;
4510 }
4511 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
4512 movptr(*it, Address(rsp, restore_offset));
4513 restore_offset -= gp_reg_size;
4514 }
4515
4516 if (offset == -1) {
4517 addptr(rsp, aligned_size);
4518 }
4519 }
4520
4521 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4522 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4523 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4524 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4525 Label done;
4526
4527 testptr(length_in_bytes, length_in_bytes);
4528 jcc(Assembler::zero, done);
4529
4530 // initialize topmost word, divide index by 2, check if odd and test if zero
4531 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4532 #ifdef ASSERT
4533 {
4534 Label L;
4535 testptr(length_in_bytes, BytesPerWord - 1);
4536 jcc(Assembler::zero, L);
4537 stop("length must be a multiple of BytesPerWord");
4538 bind(L);
4539 }
4540 #endif
4541 Register index = length_in_bytes;
4542 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4543 if (UseIncDec) {
4544 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4545 } else {
4546 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4547 shrptr(index, 1);
4548 }
4549 #ifndef _LP64
4550 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4551 {
4552 Label even;
4553 // note: if index was a multiple of 8, then it cannot
4554 // be 0 now otherwise it must have been 0 before
4555 // => if it is even, we don't need to check for 0 again
4556 jcc(Assembler::carryClear, even);
4557 // clear topmost word (no jump would be needed if conditional assignment worked here)
4558 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4559 // index could be 0 now, must check again
4560 jcc(Assembler::zero, done);
4561 bind(even);
4562 }
4563 #endif // !_LP64
4564 // initialize remaining object fields: index is a multiple of 2 now
4565 {
4566 Label loop;
4567 bind(loop);
4568 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4569 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4570 decrement(index);
4571 jcc(Assembler::notZero, loop);
4572 }
4573
4574 bind(done);
4575 }
4576
4577 void MacroAssembler::get_inline_type_field_klass(Register holder_klass, Register index, Register inline_klass) {
4578 inline_layout_info(holder_klass, index, inline_klass);
4579 movptr(inline_klass, Address(inline_klass, InlineLayoutInfo::klass_offset()));
4580 }
4581
4582 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
4583 movptr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
4584 #ifdef ASSERT
4585 {
4586 Label done;
4587 cmpptr(layout_info, 0);
4588 jcc(Assembler::notEqual, done);
4589 stop("inline_layout_info_array is null");
4590 bind(done);
4591 }
4592 #endif
4593
4594 InlineLayoutInfo array[2];
4595 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
4596 if (is_power_of_2(size)) {
4597 shll(index, log2i_exact(size)); // Scale index by power of 2
4598 } else {
4599 imull(index, index, size); // Scale the index to be the entry index * array_element_size
4600 }
4601 lea(layout_info, Address(layout_info, index, Address::times_1, Array<InlineLayoutInfo>::base_offset_in_bytes()));
4602 }
4603
4604 void MacroAssembler::get_default_value_oop(Register inline_klass, Register temp_reg, Register obj) {
4605 #ifdef ASSERT
4606 {
4607 Label done_check;
4608 test_klass_is_inline_type(inline_klass, temp_reg, done_check);
4609 stop("get_default_value_oop from non inline type klass");
4610 bind(done_check);
4611 }
4612 #endif
4613 Register offset = temp_reg;
4614 // Getting the offset of the pre-allocated default value
4615 movptr(offset, Address(inline_klass, in_bytes(InstanceKlass::adr_inlineklass_fixed_block_offset())));
4616 movl(offset, Address(offset, in_bytes(InlineKlass::default_value_offset_offset())));
4617
4618 // Getting the mirror
4619 movptr(obj, Address(inline_klass, in_bytes(Klass::java_mirror_offset())));
4620 resolve_oop_handle(obj, inline_klass);
4621
4622 // Getting the pre-allocated default value from the mirror
4623 Address field(obj, offset, Address::times_1);
4624 load_heap_oop(obj, field);
4625 }
4626
4627 void MacroAssembler::get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj) {
4628 #ifdef ASSERT
4629 {
4630 Label done_check;
4631 test_klass_is_empty_inline_type(inline_klass, temp_reg, done_check);
4632 stop("get_empty_value from non-empty inline klass");
4633 bind(done_check);
4634 }
4635 #endif
4636 get_default_value_oop(inline_klass, temp_reg, obj);
4637 }
4638
4639
4640 // Look up the method for a megamorphic invokeinterface call.
4641 // The target method is determined by <intf_klass, itable_index>.
4642 // The receiver klass is in recv_klass.
4643 // On success, the result will be in method_result, and execution falls through.
4644 // On failure, execution transfers to the given label.
4645 void MacroAssembler::lookup_interface_method(Register recv_klass,
4646 Register intf_klass,
4647 RegisterOrConstant itable_index,
4648 Register method_result,
4649 Register scan_temp,
4650 Label& L_no_such_interface,
4651 bool return_method) {
4652 assert_different_registers(recv_klass, intf_klass, scan_temp);
4653 assert_different_registers(method_result, intf_klass, scan_temp);
4654 assert(recv_klass != method_result || !return_method,
4655 "recv_klass can be destroyed when method isn't needed");
4656
4657 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4658 "caller must use same register for non-constant itable index as for method");
4659
4660 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4661 int vtable_base = in_bytes(Klass::vtable_start_offset());
4662 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4663 int scan_step = itableOffsetEntry::size() * wordSize;
4664 int vte_size = vtableEntry::size_in_bytes();
4665 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4666 assert(vte_size == wordSize, "else adjust times_vte_scale");
4667
4668 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4669
4670 // Could store the aligned, prescaled offset in the klass.
4671 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4672
4673 if (return_method) {
4674 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4675 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4676 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4677 }
4678
4679 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
4680 // if (scan->interface() == intf) {
4681 // result = (klass + scan->offset() + itable_index);
4682 // }
4683 // }
4684 Label search, found_method;
4685
4686 for (int peel = 1; peel >= 0; peel--) {
4687 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
4688 cmpptr(intf_klass, method_result);
4689
4690 if (peel) {
4691 jccb(Assembler::equal, found_method);
4692 } else {
4693 jccb(Assembler::notEqual, search);
4694 // (invert the test to fall through to found_method...)
4695 }
4696
4697 if (!peel) break;
4698
4699 bind(search);
4700
4701 // Check that the previous entry is non-null. A null entry means that
4702 // the receiver class doesn't implement the interface, and wasn't the
4703 // same as when the caller was compiled.
4704 testptr(method_result, method_result);
4705 jcc(Assembler::zero, L_no_such_interface);
4706 addptr(scan_temp, scan_step);
4707 }
4708
4709 bind(found_method);
4710
4711 if (return_method) {
4712 // Got a hit.
4713 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4714 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4715 }
4716 }
4717
4718 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4719 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4720 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4721 // The target method is determined by <holder_klass, itable_index>.
4722 // The receiver klass is in recv_klass.
4723 // On success, the result will be in method_result, and execution falls through.
4724 // On failure, execution transfers to the given label.
4725 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4726 Register holder_klass,
4727 Register resolved_klass,
4728 Register method_result,
4729 Register scan_temp,
4730 Register temp_reg2,
4731 Register receiver,
4732 int itable_index,
4733 Label& L_no_such_interface) {
4734 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4735 Register temp_itbl_klass = method_result;
4736 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4737
4738 int vtable_base = in_bytes(Klass::vtable_start_offset());
4739 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4740 int scan_step = itableOffsetEntry::size() * wordSize;
4741 int vte_size = vtableEntry::size_in_bytes();
4742 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4743 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4744 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4745 assert(vte_size == wordSize, "adjust times_vte_scale");
4746
4747 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4748
4749 // temp_itbl_klass = recv_klass.itable[0]
4750 // scan_temp = &recv_klass.itable[0] + step
4751 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4752 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4753 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4754 xorptr(temp_reg, temp_reg);
4755
4756 // Initial checks:
4757 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4758 // - if (itable[0] == 0), no such interface
4759 // - if (itable[0] == holder_klass), shortcut to "holder found"
4760 cmpptr(holder_klass, resolved_klass);
4761 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4762 testptr(temp_itbl_klass, temp_itbl_klass);
4763 jccb(Assembler::zero, L_no_such_interface);
4764 cmpptr(holder_klass, temp_itbl_klass);
4765 jccb(Assembler::equal, L_holder_found);
4766
4767 // Loop: Look for holder_klass record in itable
4768 // do {
4769 // tmp = itable[index];
4770 // index += step;
4771 // if (tmp == holder_klass) {
4772 // goto L_holder_found; // Found!
4773 // }
4774 // } while (tmp != 0);
4775 // goto L_no_such_interface // Not found.
4776 Label L_scan_holder;
4777 bind(L_scan_holder);
4778 movptr(temp_itbl_klass, Address(scan_temp, 0));
4779 addptr(scan_temp, scan_step);
4780 cmpptr(holder_klass, temp_itbl_klass);
4781 jccb(Assembler::equal, L_holder_found);
4782 testptr(temp_itbl_klass, temp_itbl_klass);
4783 jccb(Assembler::notZero, L_scan_holder);
4784
4785 jmpb(L_no_such_interface);
4786
4787 // Loop: Look for resolved_class record in itable
4788 // do {
4789 // tmp = itable[index];
4790 // index += step;
4791 // if (tmp == holder_klass) {
4792 // // Also check if we have met a holder klass
4793 // holder_tmp = itable[index-step-ioffset];
4794 // }
4795 // if (tmp == resolved_klass) {
4796 // goto L_resolved_found; // Found!
4797 // }
4798 // } while (tmp != 0);
4799 // goto L_no_such_interface // Not found.
4800 //
4801 Label L_loop_scan_resolved;
4802 bind(L_loop_scan_resolved);
4803 movptr(temp_itbl_klass, Address(scan_temp, 0));
4804 addptr(scan_temp, scan_step);
4805 bind(L_loop_scan_resolved_entry);
4806 cmpptr(holder_klass, temp_itbl_klass);
4807 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4808 cmpptr(resolved_klass, temp_itbl_klass);
4809 jccb(Assembler::equal, L_resolved_found);
4810 testptr(temp_itbl_klass, temp_itbl_klass);
4811 jccb(Assembler::notZero, L_loop_scan_resolved);
4812
4813 jmpb(L_no_such_interface);
4814
4815 Label L_ready;
4816
4817 // See if we already have a holder klass. If not, go and scan for it.
4818 bind(L_resolved_found);
4819 testptr(temp_reg, temp_reg);
4820 jccb(Assembler::zero, L_scan_holder);
4821 jmpb(L_ready);
4822
4823 bind(L_holder_found);
4824 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4825
4826 // Finally, temp_reg contains holder_klass vtable offset
4827 bind(L_ready);
4828 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4829 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4830 load_klass(scan_temp, receiver, noreg);
4831 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4832 } else {
4833 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4834 }
4835 }
4836
4837
4838 // virtual method calling
4839 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4840 RegisterOrConstant vtable_index,
4841 Register method_result) {
4842 const ByteSize base = Klass::vtable_start_offset();
4843 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4844 Address vtable_entry_addr(recv_klass,
4845 vtable_index, Address::times_ptr,
4846 base + vtableEntry::method_offset());
4847 movptr(method_result, vtable_entry_addr);
4848 }
4849
4850
4851 void MacroAssembler::check_klass_subtype(Register sub_klass,
4852 Register super_klass,
4853 Register temp_reg,
4854 Label& L_success) {
4855 Label L_failure;
4856 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4857 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4858 bind(L_failure);
4859 }
4860
4861
4862 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4863 Register super_klass,
4864 Register temp_reg,
4865 Label* L_success,
4866 Label* L_failure,
4867 Label* L_slow_path,
4868 RegisterOrConstant super_check_offset) {
4869 assert_different_registers(sub_klass, super_klass, temp_reg);
4870 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4871 if (super_check_offset.is_register()) {
4872 assert_different_registers(sub_klass, super_klass,
4873 super_check_offset.as_register());
4874 } else if (must_load_sco) {
4875 assert(temp_reg != noreg, "supply either a temp or a register offset");
4876 }
4877
4878 Label L_fallthrough;
4879 int label_nulls = 0;
4880 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4881 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4882 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4883 assert(label_nulls <= 1, "at most one null in the batch");
4884
4885 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4886 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4887 Address super_check_offset_addr(super_klass, sco_offset);
4888
4889 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4890 // range of a jccb. If this routine grows larger, reconsider at
4891 // least some of these.
4892 #define local_jcc(assembler_cond, label) \
4893 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4894 else jcc( assembler_cond, label) /*omit semi*/
4895
4896 // Hacked jmp, which may only be used just before L_fallthrough.
4897 #define final_jmp(label) \
4898 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4899 else jmp(label) /*omit semi*/
4900
4901 // If the pointers are equal, we are done (e.g., String[] elements).
4902 // This self-check enables sharing of secondary supertype arrays among
4903 // non-primary types such as array-of-interface. Otherwise, each such
4904 // type would need its own customized SSA.
4905 // We move this check to the front of the fast path because many
4906 // type checks are in fact trivially successful in this manner,
4907 // so we get a nicely predicted branch right at the start of the check.
4908 cmpptr(sub_klass, super_klass);
4909 local_jcc(Assembler::equal, *L_success);
4910
4911 // Check the supertype display:
4912 if (must_load_sco) {
4913 // Positive movl does right thing on LP64.
4914 movl(temp_reg, super_check_offset_addr);
4915 super_check_offset = RegisterOrConstant(temp_reg);
4916 }
4917 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4918 cmpptr(super_klass, super_check_addr); // load displayed supertype
4919
4920 // This check has worked decisively for primary supers.
4921 // Secondary supers are sought in the super_cache ('super_cache_addr').
4922 // (Secondary supers are interfaces and very deeply nested subtypes.)
4923 // This works in the same check above because of a tricky aliasing
4924 // between the super_cache and the primary super display elements.
4925 // (The 'super_check_addr' can address either, as the case requires.)
4926 // Note that the cache is updated below if it does not help us find
4927 // what we need immediately.
4928 // So if it was a primary super, we can just fail immediately.
4929 // Otherwise, it's the slow path for us (no success at this point).
4930
4931 if (super_check_offset.is_register()) {
4932 local_jcc(Assembler::equal, *L_success);
4933 cmpl(super_check_offset.as_register(), sc_offset);
4934 if (L_failure == &L_fallthrough) {
4935 local_jcc(Assembler::equal, *L_slow_path);
4936 } else {
4937 local_jcc(Assembler::notEqual, *L_failure);
4938 final_jmp(*L_slow_path);
4939 }
4940 } else if (super_check_offset.as_constant() == sc_offset) {
4941 // Need a slow path; fast failure is impossible.
4942 if (L_slow_path == &L_fallthrough) {
4943 local_jcc(Assembler::equal, *L_success);
4944 } else {
4945 local_jcc(Assembler::notEqual, *L_slow_path);
4946 final_jmp(*L_success);
4947 }
4948 } else {
4949 // No slow path; it's a fast decision.
4950 if (L_failure == &L_fallthrough) {
4951 local_jcc(Assembler::equal, *L_success);
4952 } else {
4953 local_jcc(Assembler::notEqual, *L_failure);
4954 final_jmp(*L_success);
4955 }
4956 }
4957
4958 bind(L_fallthrough);
4959
4960 #undef local_jcc
4961 #undef final_jmp
4962 }
4963
4964
4965 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4966 Register super_klass,
4967 Register temp_reg,
4968 Register temp2_reg,
4969 Label* L_success,
4970 Label* L_failure,
4971 bool set_cond_codes) {
4972 assert_different_registers(sub_klass, super_klass, temp_reg);
4973 if (temp2_reg != noreg)
4974 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4975 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4976
4977 Label L_fallthrough;
4978 int label_nulls = 0;
4979 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4980 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4981 assert(label_nulls <= 1, "at most one null in the batch");
4982
4983 // a couple of useful fields in sub_klass:
4984 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4985 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4986 Address secondary_supers_addr(sub_klass, ss_offset);
4987 Address super_cache_addr( sub_klass, sc_offset);
4988
4989 // Do a linear scan of the secondary super-klass chain.
4990 // This code is rarely used, so simplicity is a virtue here.
4991 // The repne_scan instruction uses fixed registers, which we must spill.
4992 // Don't worry too much about pre-existing connections with the input regs.
4993
4994 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4995 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4996
4997 // Get super_klass value into rax (even if it was in rdi or rcx).
4998 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4999 if (super_klass != rax) {
5000 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
5001 mov(rax, super_klass);
5002 }
5003 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
5004 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
5005
5006 #ifndef PRODUCT
5007 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
5008 ExternalAddress pst_counter_addr((address) pst_counter);
5009 NOT_LP64( incrementl(pst_counter_addr) );
5010 LP64_ONLY( lea(rcx, pst_counter_addr) );
5011 LP64_ONLY( incrementl(Address(rcx, 0)) );
5012 #endif //PRODUCT
5013
5014 // We will consult the secondary-super array.
5015 movptr(rdi, secondary_supers_addr);
5016 // Load the array length. (Positive movl does right thing on LP64.)
5017 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
5018 // Skip to start of data.
5019 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
5020
5021 // Scan RCX words at [RDI] for an occurrence of RAX.
5022 // Set NZ/Z based on last compare.
5023 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
5024 // not change flags (only scas instruction which is repeated sets flags).
5025 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
5026
5027 testptr(rax,rax); // Set Z = 0
5028 repne_scan();
5029
5030 // Unspill the temp. registers:
5031 if (pushed_rdi) pop(rdi);
5032 if (pushed_rcx) pop(rcx);
5033 if (pushed_rax) pop(rax);
5034
5035 if (set_cond_codes) {
5036 // Special hack for the AD files: rdi is guaranteed non-zero.
5037 assert(!pushed_rdi, "rdi must be left non-null");
5038 // Also, the condition codes are properly set Z/NZ on succeed/failure.
5039 }
5040
5041 if (L_failure == &L_fallthrough)
5042 jccb(Assembler::notEqual, *L_failure);
5043 else jcc(Assembler::notEqual, *L_failure);
5044
5045 // Success. Cache the super we found and proceed in triumph.
5046 movptr(super_cache_addr, super_klass);
5047
5048 if (L_success != &L_fallthrough) {
5049 jmp(*L_success);
5050 }
5051
5052 #undef IS_A_TEMP
5053
5054 bind(L_fallthrough);
5055 }
5056
5057 #ifdef _LP64
5058
5059 // population_count variant for running without the POPCNT
5060 // instruction, which was introduced with SSE4.2 in 2008.
5061 void MacroAssembler::population_count(Register dst, Register src,
5062 Register scratch1, Register scratch2) {
5063 assert_different_registers(src, scratch1, scratch2);
5064 if (UsePopCountInstruction) {
5065 Assembler::popcntq(dst, src);
5066 } else {
5067 assert_different_registers(src, scratch1, scratch2);
5068 assert_different_registers(dst, scratch1, scratch2);
5069 Label loop, done;
5070
5071 mov(scratch1, src);
5072 // dst = 0;
5073 // while(scratch1 != 0) {
5074 // dst++;
5075 // scratch1 &= (scratch1 - 1);
5076 // }
5077 xorl(dst, dst);
5078 testq(scratch1, scratch1);
5079 jccb(Assembler::equal, done);
5080 {
5081 bind(loop);
5082 incq(dst);
5083 movq(scratch2, scratch1);
5084 decq(scratch2);
5085 andq(scratch1, scratch2);
5086 jccb(Assembler::notEqual, loop);
5087 }
5088 bind(done);
5089 }
5090 }
5091
5092 // Ensure that the inline code and the stub are using the same registers.
5093 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
5094 do { \
5095 assert(r_super_klass == rax, "mismatch"); \
5096 assert(r_array_base == rbx, "mismatch"); \
5097 assert(r_array_length == rcx, "mismatch"); \
5098 assert(r_array_index == rdx, "mismatch"); \
5099 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
5100 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
5101 assert(result == rdi || result == noreg, "mismatch"); \
5102 } while(0)
5103
5104 void MacroAssembler::lookup_secondary_supers_table(Register r_sub_klass,
5105 Register r_super_klass,
5106 Register temp1,
5107 Register temp2,
5108 Register temp3,
5109 Register temp4,
5110 Register result,
5111 u1 super_klass_slot) {
5112 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
5113
5114 Label L_fallthrough, L_success, L_failure;
5115
5116 BLOCK_COMMENT("lookup_secondary_supers_table {");
5117
5118 const Register
5119 r_array_index = temp1,
5120 r_array_length = temp2,
5121 r_array_base = temp3,
5122 r_bitmap = temp4;
5123
5124 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
5125
5126 xorq(result, result); // = 0
5127
5128 movq(r_bitmap, Address(r_sub_klass, Klass::bitmap_offset()));
5129 movq(r_array_index, r_bitmap);
5130
5131 // First check the bitmap to see if super_klass might be present. If
5132 // the bit is zero, we are certain that super_klass is not one of
5133 // the secondary supers.
5134 u1 bit = super_klass_slot;
5135 {
5136 // NB: If the count in a x86 shift instruction is 0, the flags are
5137 // not affected, so we do a testq instead.
5138 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
5139 if (shift_count != 0) {
5140 salq(r_array_index, shift_count);
5141 } else {
5142 testq(r_array_index, r_array_index);
5143 }
5144 }
5145 // We test the MSB of r_array_index, i.e. its sign bit
5146 jcc(Assembler::positive, L_failure);
5147
5148 // Get the first array index that can contain super_klass into r_array_index.
5149 if (bit != 0) {
5150 population_count(r_array_index, r_array_index, temp2, temp3);
5151 } else {
5152 movl(r_array_index, 1);
5153 }
5154 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5155
5156 // We will consult the secondary-super array.
5157 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5158
5159 // We're asserting that the first word in an Array<Klass*> is the
5160 // length, and the second word is the first word of the data. If
5161 // that ever changes, r_array_base will have to be adjusted here.
5162 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5163 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5164
5165 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5166 jccb(Assembler::equal, L_success);
5167
5168 // Is there another entry to check? Consult the bitmap.
5169 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
5170 jccb(Assembler::carryClear, L_failure);
5171
5172 // Linear probe. Rotate the bitmap so that the next bit to test is
5173 // in Bit 1.
5174 if (bit != 0) {
5175 rorq(r_bitmap, bit);
5176 }
5177
5178 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5179 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5180 // Kills: r_array_length.
5181 // Returns: result.
5182 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
5183 // Result (0/1) is in rdi
5184 jmpb(L_fallthrough);
5185
5186 bind(L_failure);
5187 incq(result); // 0 => 1
5188
5189 bind(L_success);
5190 // result = 0;
5191
5192 bind(L_fallthrough);
5193 BLOCK_COMMENT("} lookup_secondary_supers_table");
5194
5195 if (VerifySecondarySupers) {
5196 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5197 temp1, temp2, temp3);
5198 }
5199 }
5200
5201 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
5202 Label* L_success, Label* L_failure) {
5203 Label L_loop, L_fallthrough;
5204 {
5205 int label_nulls = 0;
5206 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5207 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5208 assert(label_nulls <= 1, "at most one null in the batch");
5209 }
5210 bind(L_loop);
5211 cmpq(value, Address(addr, count, Address::times_8));
5212 jcc(Assembler::equal, *L_success);
5213 addl(count, 1);
5214 cmpl(count, limit);
5215 jcc(Assembler::less, L_loop);
5216
5217 if (&L_fallthrough != L_failure) {
5218 jmp(*L_failure);
5219 }
5220 bind(L_fallthrough);
5221 }
5222
5223 // Called by code generated by check_klass_subtype_slow_path
5224 // above. This is called when there is a collision in the hashed
5225 // lookup in the secondary supers array.
5226 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
5227 Register r_array_base,
5228 Register r_array_index,
5229 Register r_bitmap,
5230 Register temp1,
5231 Register temp2,
5232 Label* L_success,
5233 Label* L_failure) {
5234 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
5235
5236 const Register
5237 r_array_length = temp1,
5238 r_sub_klass = noreg,
5239 result = noreg;
5240
5241 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
5242
5243 Label L_fallthrough;
5244 int label_nulls = 0;
5245 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5246 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5247 assert(label_nulls <= 1, "at most one null in the batch");
5248
5249 // Load the array length.
5250 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5251 // And adjust the array base to point to the data.
5252 // NB! Effectively increments current slot index by 1.
5253 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
5254 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5255
5256 // Linear probe
5257 Label L_huge;
5258
5259 // The bitmap is full to bursting.
5260 // Implicit invariant: BITMAP_FULL implies (length > 0)
5261 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
5262 jcc(Assembler::greater, L_huge);
5263
5264 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
5265 // current slot (at secondary_supers[r_array_index]) has not yet
5266 // been inspected, and r_array_index may be out of bounds if we
5267 // wrapped around the end of the array.
5268
5269 { // This is conventional linear probing, but instead of terminating
5270 // when a null entry is found in the table, we maintain a bitmap
5271 // in which a 0 indicates missing entries.
5272 // The check above guarantees there are 0s in the bitmap, so the loop
5273 // eventually terminates.
5274
5275 xorl(temp2, temp2); // = 0;
5276
5277 Label L_again;
5278 bind(L_again);
5279
5280 // Check for array wraparound.
5281 cmpl(r_array_index, r_array_length);
5282 cmovl(Assembler::greaterEqual, r_array_index, temp2);
5283
5284 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5285 jcc(Assembler::equal, *L_success);
5286
5287 // If the next bit in bitmap is zero, we're done.
5288 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
5289 jcc(Assembler::carryClear, *L_failure);
5290
5291 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
5292 addl(r_array_index, 1);
5293
5294 jmp(L_again);
5295 }
5296
5297 { // Degenerate case: more than 64 secondary supers.
5298 // FIXME: We could do something smarter here, maybe a vectorized
5299 // comparison or a binary search, but is that worth any added
5300 // complexity?
5301 bind(L_huge);
5302 xorl(r_array_index, r_array_index); // = 0
5303 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
5304 L_success,
5305 (&L_fallthrough != L_failure ? L_failure : nullptr));
5306
5307 bind(L_fallthrough);
5308 }
5309 }
5310
5311 struct VerifyHelperArguments {
5312 Klass* _super;
5313 Klass* _sub;
5314 intptr_t _linear_result;
5315 intptr_t _table_result;
5316 };
5317
5318 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
5319 Klass::on_secondary_supers_verification_failure(args->_super,
5320 args->_sub,
5321 args->_linear_result,
5322 args->_table_result,
5323 msg);
5324 }
5325
5326 // Make sure that the hashed lookup and a linear scan agree.
5327 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
5328 Register r_super_klass,
5329 Register result,
5330 Register temp1,
5331 Register temp2,
5332 Register temp3) {
5333 const Register
5334 r_array_index = temp1,
5335 r_array_length = temp2,
5336 r_array_base = temp3,
5337 r_bitmap = noreg;
5338
5339 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
5340
5341 BLOCK_COMMENT("verify_secondary_supers_table {");
5342
5343 Label L_success, L_failure, L_check, L_done;
5344
5345 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5346 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5347 // And adjust the array base to point to the data.
5348 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5349
5350 testl(r_array_length, r_array_length); // array_length == 0?
5351 jcc(Assembler::zero, L_failure);
5352
5353 movl(r_array_index, 0);
5354 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
5355 // fall through to L_failure
5356
5357 const Register linear_result = r_array_index; // reuse temp1
5358
5359 bind(L_failure); // not present
5360 movl(linear_result, 1);
5361 jmp(L_check);
5362
5363 bind(L_success); // present
5364 movl(linear_result, 0);
5365
5366 bind(L_check);
5367 cmpl(linear_result, result);
5368 jcc(Assembler::equal, L_done);
5369
5370 { // To avoid calling convention issues, build a record on the stack
5371 // and pass the pointer to that instead.
5372 push(result);
5373 push(linear_result);
5374 push(r_sub_klass);
5375 push(r_super_klass);
5376 movptr(c_rarg1, rsp);
5377 movptr(c_rarg0, (uintptr_t) "mismatch");
5378 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
5379 should_not_reach_here();
5380 }
5381 bind(L_done);
5382
5383 BLOCK_COMMENT("} verify_secondary_supers_table");
5384 }
5385
5386 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
5387
5388 #endif // LP64
5389
5390 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
5391 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
5392
5393 Label L_fallthrough;
5394 if (L_fast_path == nullptr) {
5395 L_fast_path = &L_fallthrough;
5396 } else if (L_slow_path == nullptr) {
5397 L_slow_path = &L_fallthrough;
5398 }
5399
5400 // Fast path check: class is fully initialized.
5401 // init_state needs acquire, but x86 is TSO, and so we are already good.
5402 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
5403 jcc(Assembler::equal, *L_fast_path);
5404
5405 // Fast path check: current thread is initializer thread
5406 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
5407 if (L_slow_path == &L_fallthrough) {
5408 jcc(Assembler::equal, *L_fast_path);
5409 bind(*L_slow_path);
5410 } else if (L_fast_path == &L_fallthrough) {
5411 jcc(Assembler::notEqual, *L_slow_path);
5412 bind(*L_fast_path);
5413 } else {
5414 Unimplemented();
5415 }
5416 }
5417
5418 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5419 if (VM_Version::supports_cmov()) {
5420 cmovl(cc, dst, src);
5421 } else {
5422 Label L;
5423 jccb(negate_condition(cc), L);
5424 movl(dst, src);
5425 bind(L);
5426 }
5427 }
5428
5429 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5430 if (VM_Version::supports_cmov()) {
5431 cmovl(cc, dst, src);
5432 } else {
5433 Label L;
5434 jccb(negate_condition(cc), L);
5435 movl(dst, src);
5436 bind(L);
5437 }
5438 }
5439
5440 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5441 if (!VerifyOops || VerifyAdapterSharing) {
5442 // Below address of the code string confuses VerifyAdapterSharing
5443 // because it may differ between otherwise equivalent adapters.
5444 return;
5445 }
5446
5447 BLOCK_COMMENT("verify_oop {");
5448 #ifdef _LP64
5449 push(rscratch1);
5450 #endif
5451 push(rax); // save rax
5452 push(reg); // pass register argument
5453
5454 // Pass register number to verify_oop_subroutine
5455 const char* b = nullptr;
5456 {
5457 ResourceMark rm;
5458 stringStream ss;
5459 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5460 b = code_string(ss.as_string());
5461 }
5462 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5463 pushptr(buffer.addr(), rscratch1);
5464
5465 // call indirectly to solve generation ordering problem
5466 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5467 call(rax);
5468 // Caller pops the arguments (oop, message) and restores rax, r10
5469 BLOCK_COMMENT("} verify_oop");
5470 }
5471
5472 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5473 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5474 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5475 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5476 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5477 } else if (VM_Version::supports_avx()) {
5478 vpcmpeqd(dst, dst, dst, vector_len);
5479 } else {
5480 assert(VM_Version::supports_sse2(), "");
5481 pcmpeqd(dst, dst);
5482 }
5483 }
5484
5485 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5486 int extra_slot_offset) {
5487 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5488 int stackElementSize = Interpreter::stackElementSize;
5489 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5490 #ifdef ASSERT
5491 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5492 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5493 #endif
5494 Register scale_reg = noreg;
5495 Address::ScaleFactor scale_factor = Address::no_scale;
5496 if (arg_slot.is_constant()) {
5497 offset += arg_slot.as_constant() * stackElementSize;
5498 } else {
5499 scale_reg = arg_slot.as_register();
5500 scale_factor = Address::times(stackElementSize);
5501 }
5502 offset += wordSize; // return PC is on stack
5503 return Address(rsp, scale_reg, scale_factor, offset);
5504 }
5505
5506 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5507 if (!VerifyOops || VerifyAdapterSharing) {
5508 // Below address of the code string confuses VerifyAdapterSharing
5509 // because it may differ between otherwise equivalent adapters.
5510 return;
5511 }
5512
5513 #ifdef _LP64
5514 push(rscratch1);
5515 #endif
5516 push(rax); // save rax,
5517 // addr may contain rsp so we will have to adjust it based on the push
5518 // we just did (and on 64 bit we do two pushes)
5519 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5520 // stores rax into addr which is backwards of what was intended.
5521 if (addr.uses(rsp)) {
5522 lea(rax, addr);
5523 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5524 } else {
5525 pushptr(addr);
5526 }
5527
5528 // Pass register number to verify_oop_subroutine
5529 const char* b = nullptr;
5530 {
5531 ResourceMark rm;
5532 stringStream ss;
5533 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5534 b = code_string(ss.as_string());
5535 }
5536 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5537 pushptr(buffer.addr(), rscratch1);
5538
5539 // call indirectly to solve generation ordering problem
5540 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5541 call(rax);
5542 // Caller pops the arguments (addr, message) and restores rax, r10.
5543 }
5544
5545 void MacroAssembler::verify_tlab() {
5546 #ifdef ASSERT
5547 if (UseTLAB && VerifyOops) {
5548 Label next, ok;
5549 Register t1 = rsi;
5550 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5551
5552 push(t1);
5553 NOT_LP64(push(thread_reg));
5554 NOT_LP64(get_thread(thread_reg));
5555
5556 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5557 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5558 jcc(Assembler::aboveEqual, next);
5559 STOP("assert(top >= start)");
5560 should_not_reach_here();
5561
5562 bind(next);
5563 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5564 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5565 jcc(Assembler::aboveEqual, ok);
5566 STOP("assert(top <= end)");
5567 should_not_reach_here();
5568
5569 bind(ok);
5570 NOT_LP64(pop(thread_reg));
5571 pop(t1);
5572 }
5573 #endif
5574 }
5575
5576 class ControlWord {
5577 public:
5578 int32_t _value;
5579
5580 int rounding_control() const { return (_value >> 10) & 3 ; }
5581 int precision_control() const { return (_value >> 8) & 3 ; }
5582 bool precision() const { return ((_value >> 5) & 1) != 0; }
5583 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5584 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5585 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5586 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5587 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5588
5589 void print() const {
5590 // rounding control
5591 const char* rc;
5592 switch (rounding_control()) {
5593 case 0: rc = "round near"; break;
5594 case 1: rc = "round down"; break;
5595 case 2: rc = "round up "; break;
5596 case 3: rc = "chop "; break;
5597 default:
5598 rc = nullptr; // silence compiler warnings
5599 fatal("Unknown rounding control: %d", rounding_control());
5600 };
5601 // precision control
5602 const char* pc;
5603 switch (precision_control()) {
5604 case 0: pc = "24 bits "; break;
5605 case 1: pc = "reserved"; break;
5606 case 2: pc = "53 bits "; break;
5607 case 3: pc = "64 bits "; break;
5608 default:
5609 pc = nullptr; // silence compiler warnings
5610 fatal("Unknown precision control: %d", precision_control());
5611 };
5612 // flags
5613 char f[9];
5614 f[0] = ' ';
5615 f[1] = ' ';
5616 f[2] = (precision ()) ? 'P' : 'p';
5617 f[3] = (underflow ()) ? 'U' : 'u';
5618 f[4] = (overflow ()) ? 'O' : 'o';
5619 f[5] = (zero_divide ()) ? 'Z' : 'z';
5620 f[6] = (denormalized()) ? 'D' : 'd';
5621 f[7] = (invalid ()) ? 'I' : 'i';
5622 f[8] = '\x0';
5623 // output
5624 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5625 }
5626
5627 };
5628
5629 class StatusWord {
5630 public:
5631 int32_t _value;
5632
5633 bool busy() const { return ((_value >> 15) & 1) != 0; }
5634 bool C3() const { return ((_value >> 14) & 1) != 0; }
5635 bool C2() const { return ((_value >> 10) & 1) != 0; }
5636 bool C1() const { return ((_value >> 9) & 1) != 0; }
5637 bool C0() const { return ((_value >> 8) & 1) != 0; }
5638 int top() const { return (_value >> 11) & 7 ; }
5639 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5640 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5641 bool precision() const { return ((_value >> 5) & 1) != 0; }
5642 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5643 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5644 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5645 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5646 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5647
5648 void print() const {
5649 // condition codes
5650 char c[5];
5651 c[0] = (C3()) ? '3' : '-';
5652 c[1] = (C2()) ? '2' : '-';
5653 c[2] = (C1()) ? '1' : '-';
5654 c[3] = (C0()) ? '0' : '-';
5655 c[4] = '\x0';
5656 // flags
5657 char f[9];
5658 f[0] = (error_status()) ? 'E' : '-';
5659 f[1] = (stack_fault ()) ? 'S' : '-';
5660 f[2] = (precision ()) ? 'P' : '-';
5661 f[3] = (underflow ()) ? 'U' : '-';
5662 f[4] = (overflow ()) ? 'O' : '-';
5663 f[5] = (zero_divide ()) ? 'Z' : '-';
5664 f[6] = (denormalized()) ? 'D' : '-';
5665 f[7] = (invalid ()) ? 'I' : '-';
5666 f[8] = '\x0';
5667 // output
5668 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5669 }
5670
5671 };
5672
5673 class TagWord {
5674 public:
5675 int32_t _value;
5676
5677 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5678
5679 void print() const {
5680 printf("%04x", _value & 0xFFFF);
5681 }
5682
5683 };
5684
5685 class FPU_Register {
5686 public:
5687 int32_t _m0;
5688 int32_t _m1;
5689 int16_t _ex;
5690
5691 bool is_indefinite() const {
5692 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5693 }
5694
5695 void print() const {
5696 char sign = (_ex < 0) ? '-' : '+';
5697 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5698 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5699 };
5700
5701 };
5702
5703 class FPU_State {
5704 public:
5705 enum {
5706 register_size = 10,
5707 number_of_registers = 8,
5708 register_mask = 7
5709 };
5710
5711 ControlWord _control_word;
5712 StatusWord _status_word;
5713 TagWord _tag_word;
5714 int32_t _error_offset;
5715 int32_t _error_selector;
5716 int32_t _data_offset;
5717 int32_t _data_selector;
5718 int8_t _register[register_size * number_of_registers];
5719
5720 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5721 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5722
5723 const char* tag_as_string(int tag) const {
5724 switch (tag) {
5725 case 0: return "valid";
5726 case 1: return "zero";
5727 case 2: return "special";
5728 case 3: return "empty";
5729 }
5730 ShouldNotReachHere();
5731 return nullptr;
5732 }
5733
5734 void print() const {
5735 // print computation registers
5736 { int t = _status_word.top();
5737 for (int i = 0; i < number_of_registers; i++) {
5738 int j = (i - t) & register_mask;
5739 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5740 st(j)->print();
5741 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5742 }
5743 }
5744 printf("\n");
5745 // print control registers
5746 printf("ctrl = "); _control_word.print(); printf("\n");
5747 printf("stat = "); _status_word .print(); printf("\n");
5748 printf("tags = "); _tag_word .print(); printf("\n");
5749 }
5750
5751 };
5752
5753 class Flag_Register {
5754 public:
5755 int32_t _value;
5756
5757 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5758 bool direction() const { return ((_value >> 10) & 1) != 0; }
5759 bool sign() const { return ((_value >> 7) & 1) != 0; }
5760 bool zero() const { return ((_value >> 6) & 1) != 0; }
5761 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5762 bool parity() const { return ((_value >> 2) & 1) != 0; }
5763 bool carry() const { return ((_value >> 0) & 1) != 0; }
5764
5765 void print() const {
5766 // flags
5767 char f[8];
5768 f[0] = (overflow ()) ? 'O' : '-';
5769 f[1] = (direction ()) ? 'D' : '-';
5770 f[2] = (sign ()) ? 'S' : '-';
5771 f[3] = (zero ()) ? 'Z' : '-';
5772 f[4] = (auxiliary_carry()) ? 'A' : '-';
5773 f[5] = (parity ()) ? 'P' : '-';
5774 f[6] = (carry ()) ? 'C' : '-';
5775 f[7] = '\x0';
5776 // output
5777 printf("%08x flags = %s", _value, f);
5778 }
5779
5780 };
5781
5782 class IU_Register {
5783 public:
5784 int32_t _value;
5785
5786 void print() const {
5787 printf("%08x %11d", _value, _value);
5788 }
5789
5790 };
5791
5792 class IU_State {
5793 public:
5794 Flag_Register _eflags;
5795 IU_Register _rdi;
5796 IU_Register _rsi;
5797 IU_Register _rbp;
5798 IU_Register _rsp;
5799 IU_Register _rbx;
5800 IU_Register _rdx;
5801 IU_Register _rcx;
5802 IU_Register _rax;
5803
5804 void print() const {
5805 // computation registers
5806 printf("rax, = "); _rax.print(); printf("\n");
5807 printf("rbx, = "); _rbx.print(); printf("\n");
5808 printf("rcx = "); _rcx.print(); printf("\n");
5809 printf("rdx = "); _rdx.print(); printf("\n");
5810 printf("rdi = "); _rdi.print(); printf("\n");
5811 printf("rsi = "); _rsi.print(); printf("\n");
5812 printf("rbp, = "); _rbp.print(); printf("\n");
5813 printf("rsp = "); _rsp.print(); printf("\n");
5814 printf("\n");
5815 // control registers
5816 printf("flgs = "); _eflags.print(); printf("\n");
5817 }
5818 };
5819
5820
5821 class CPU_State {
5822 public:
5823 FPU_State _fpu_state;
5824 IU_State _iu_state;
5825
5826 void print() const {
5827 printf("--------------------------------------------------\n");
5828 _iu_state .print();
5829 printf("\n");
5830 _fpu_state.print();
5831 printf("--------------------------------------------------\n");
5832 }
5833
5834 };
5835
5836
5837 static void _print_CPU_state(CPU_State* state) {
5838 state->print();
5839 };
5840
5841
5842 void MacroAssembler::print_CPU_state() {
5843 push_CPU_state();
5844 push(rsp); // pass CPU state
5845 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5846 addptr(rsp, wordSize); // discard argument
5847 pop_CPU_state();
5848 }
5849
5850
5851 #ifndef _LP64
5852 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5853 static int counter = 0;
5854 FPU_State* fs = &state->_fpu_state;
5855 counter++;
5856 // For leaf calls, only verify that the top few elements remain empty.
5857 // We only need 1 empty at the top for C2 code.
5858 if( stack_depth < 0 ) {
5859 if( fs->tag_for_st(7) != 3 ) {
5860 printf("FPR7 not empty\n");
5861 state->print();
5862 assert(false, "error");
5863 return false;
5864 }
5865 return true; // All other stack states do not matter
5866 }
5867
5868 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
5869 "bad FPU control word");
5870
5871 // compute stack depth
5872 int i = 0;
5873 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5874 int d = i;
5875 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5876 // verify findings
5877 if (i != FPU_State::number_of_registers) {
5878 // stack not contiguous
5879 printf("%s: stack not contiguous at ST%d\n", s, i);
5880 state->print();
5881 assert(false, "error");
5882 return false;
5883 }
5884 // check if computed stack depth corresponds to expected stack depth
5885 if (stack_depth < 0) {
5886 // expected stack depth is -stack_depth or less
5887 if (d > -stack_depth) {
5888 // too many elements on the stack
5889 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5890 state->print();
5891 assert(false, "error");
5892 return false;
5893 }
5894 } else {
5895 // expected stack depth is stack_depth
5896 if (d != stack_depth) {
5897 // wrong stack depth
5898 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5899 state->print();
5900 assert(false, "error");
5901 return false;
5902 }
5903 }
5904 // everything is cool
5905 return true;
5906 }
5907
5908 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5909 if (!VerifyFPU) return;
5910 push_CPU_state();
5911 push(rsp); // pass CPU state
5912 ExternalAddress msg((address) s);
5913 // pass message string s
5914 pushptr(msg.addr(), noreg);
5915 push(stack_depth); // pass stack depth
5916 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5917 addptr(rsp, 3 * wordSize); // discard arguments
5918 // check for error
5919 { Label L;
5920 testl(rax, rax);
5921 jcc(Assembler::notZero, L);
5922 int3(); // break if error condition
5923 bind(L);
5924 }
5925 pop_CPU_state();
5926 }
5927 #endif // _LP64
5928
5929 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5930 // Either restore the MXCSR register after returning from the JNI Call
5931 // or verify that it wasn't changed (with -Xcheck:jni flag).
5932 if (VM_Version::supports_sse()) {
5933 if (RestoreMXCSROnJNICalls) {
5934 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5935 } else if (CheckJNICalls) {
5936 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5937 }
5938 }
5939 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5940 vzeroupper();
5941
5942 #ifndef _LP64
5943 // Either restore the x87 floating pointer control word after returning
5944 // from the JNI call or verify that it wasn't changed.
5945 if (CheckJNICalls) {
5946 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5947 }
5948 #endif // _LP64
5949 }
5950
5951 // ((OopHandle)result).resolve();
5952 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5953 assert_different_registers(result, tmp);
5954
5955 // Only 64 bit platforms support GCs that require a tmp register
5956 // Only IN_HEAP loads require a thread_tmp register
5957 // OopHandle::resolve is an indirection like jobject.
5958 access_load_at(T_OBJECT, IN_NATIVE,
5959 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5960 }
5961
5962 // ((WeakHandle)result).resolve();
5963 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5964 assert_different_registers(rresult, rtmp);
5965 Label resolved;
5966
5967 // A null weak handle resolves to null.
5968 cmpptr(rresult, 0);
5969 jcc(Assembler::equal, resolved);
5970
5971 // Only 64 bit platforms support GCs that require a tmp register
5972 // Only IN_HEAP loads require a thread_tmp register
5973 // WeakHandle::resolve is an indirection like jweak.
5974 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5975 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5976 bind(resolved);
5977 }
5978
5979 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5980 // get mirror
5981 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5982 load_method_holder(mirror, method);
5983 movptr(mirror, Address(mirror, mirror_offset));
5984 resolve_oop_handle(mirror, tmp);
5985 }
5986
5987 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5988 load_method_holder(rresult, rmethod);
5989 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5990 }
5991
5992 void MacroAssembler::load_method_holder(Register holder, Register method) {
5993 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5994 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5995 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5996 }
5997
5998 void MacroAssembler::load_metadata(Register dst, Register src) {
5999 if (UseCompressedClassPointers) {
6000 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6001 } else {
6002 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6003 }
6004 }
6005
6006 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
6007 assert_different_registers(src, tmp);
6008 assert_different_registers(dst, tmp);
6009 #ifdef _LP64
6010 if (UseCompressedClassPointers) {
6011 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6012 decode_klass_not_null(dst, tmp);
6013 } else
6014 #endif
6015 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6016 }
6017
6018 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
6019 load_klass(dst, src, tmp);
6020 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6021 }
6022
6023 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
6024 assert_different_registers(src, tmp);
6025 assert_different_registers(dst, tmp);
6026 #ifdef _LP64
6027 if (UseCompressedClassPointers) {
6028 encode_klass_not_null(src, tmp);
6029 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6030 } else
6031 #endif
6032 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6033 }
6034
6035 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6036 Register tmp1, Register thread_tmp) {
6037 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6038 decorators = AccessInternal::decorator_fixup(decorators, type);
6039 bool as_raw = (decorators & AS_RAW) != 0;
6040 if (as_raw) {
6041 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6042 } else {
6043 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6044 }
6045 }
6046
6047 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
6048 Register tmp1, Register tmp2, Register tmp3) {
6049 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6050 decorators = AccessInternal::decorator_fixup(decorators, type);
6051 bool as_raw = (decorators & AS_RAW) != 0;
6052 if (as_raw) {
6053 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6054 } else {
6055 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6056 }
6057 }
6058
6059 void MacroAssembler::access_value_copy(DecoratorSet decorators, Register src, Register dst,
6060 Register inline_klass) {
6061 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6062 bs->value_copy(this, decorators, src, dst, inline_klass);
6063 }
6064
6065 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
6066 Register inline_layout_info) {
6067 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6068 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
6069 }
6070
6071 void MacroAssembler::first_field_offset(Register inline_klass, Register offset) {
6072 movptr(offset, Address(inline_klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
6073 movl(offset, Address(offset, InlineKlass::first_field_offset_offset()));
6074 }
6075
6076 void MacroAssembler::data_for_oop(Register oop, Register data, Register inline_klass) {
6077 // ((address) (void*) o) + vk->first_field_offset();
6078 Register offset = (data == oop) ? rscratch1 : data;
6079 first_field_offset(inline_klass, offset);
6080 if (data == oop) {
6081 addptr(data, offset);
6082 } else {
6083 lea(data, Address(oop, offset));
6084 }
6085 }
6086
6087 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
6088 Register index, Register data) {
6089 assert(index != rcx, "index needs to shift by rcx");
6090 assert_different_registers(array, array_klass, index);
6091 assert_different_registers(rcx, array, index);
6092
6093 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
6094 movl(rcx, Address(array_klass, Klass::layout_helper_offset()));
6095
6096 // Klass::layout_helper_log2_element_size(lh)
6097 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
6098 shrl(rcx, Klass::_lh_log2_element_size_shift);
6099 andl(rcx, Klass::_lh_log2_element_size_mask);
6100 shlptr(index); // index << rcx
6101
6102 lea(data, Address(array, index, Address::times_1, arrayOopDesc::base_offset_in_bytes(T_PRIMITIVE_OBJECT)));
6103 }
6104
6105 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6106 Register thread_tmp, DecoratorSet decorators) {
6107 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6108 }
6109
6110 // Doesn't do verification, generates fixed size code
6111 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6112 Register thread_tmp, DecoratorSet decorators) {
6113 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6114 }
6115
6116 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
6117 Register tmp2, Register tmp3, DecoratorSet decorators) {
6118 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
6119 }
6120
6121 // Used for storing nulls.
6122 void MacroAssembler::store_heap_oop_null(Address dst) {
6123 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
6124 }
6125
6126 #ifdef _LP64
6127 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6128 if (UseCompressedClassPointers) {
6129 // Store to klass gap in destination
6130 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6131 }
6132 }
6133
6134 #ifdef ASSERT
6135 void MacroAssembler::verify_heapbase(const char* msg) {
6136 assert (UseCompressedOops, "should be compressed");
6137 assert (Universe::heap() != nullptr, "java heap should be initialized");
6138 if (CheckCompressedOops) {
6139 Label ok;
6140 ExternalAddress src2(CompressedOops::base_addr());
6141 const bool is_src2_reachable = reachable(src2);
6142 if (!is_src2_reachable) {
6143 push(rscratch1); // cmpptr trashes rscratch1
6144 }
6145 cmpptr(r12_heapbase, src2, rscratch1);
6146 jcc(Assembler::equal, ok);
6147 STOP(msg);
6148 bind(ok);
6149 if (!is_src2_reachable) {
6150 pop(rscratch1);
6151 }
6152 }
6153 }
6154 #endif
6155
6156 // Algorithm must match oop.inline.hpp encode_heap_oop.
6157 void MacroAssembler::encode_heap_oop(Register r) {
6158 #ifdef ASSERT
6159 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6160 #endif
6161 verify_oop_msg(r, "broken oop in encode_heap_oop");
6162 if (CompressedOops::base() == nullptr) {
6163 if (CompressedOops::shift() != 0) {
6164 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6165 shrq(r, LogMinObjAlignmentInBytes);
6166 }
6167 return;
6168 }
6169 testq(r, r);
6170 cmovq(Assembler::equal, r, r12_heapbase);
6171 subq(r, r12_heapbase);
6172 shrq(r, LogMinObjAlignmentInBytes);
6173 }
6174
6175 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6176 #ifdef ASSERT
6177 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6178 if (CheckCompressedOops) {
6179 Label ok;
6180 testq(r, r);
6181 jcc(Assembler::notEqual, ok);
6182 STOP("null oop passed to encode_heap_oop_not_null");
6183 bind(ok);
6184 }
6185 #endif
6186 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
6187 if (CompressedOops::base() != nullptr) {
6188 subq(r, r12_heapbase);
6189 }
6190 if (CompressedOops::shift() != 0) {
6191 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6192 shrq(r, LogMinObjAlignmentInBytes);
6193 }
6194 }
6195
6196 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6197 #ifdef ASSERT
6198 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6199 if (CheckCompressedOops) {
6200 Label ok;
6201 testq(src, src);
6202 jcc(Assembler::notEqual, ok);
6203 STOP("null oop passed to encode_heap_oop_not_null2");
6204 bind(ok);
6205 }
6206 #endif
6207 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
6208 if (dst != src) {
6209 movq(dst, src);
6210 }
6211 if (CompressedOops::base() != nullptr) {
6212 subq(dst, r12_heapbase);
6213 }
6214 if (CompressedOops::shift() != 0) {
6215 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6216 shrq(dst, LogMinObjAlignmentInBytes);
6217 }
6218 }
6219
6220 void MacroAssembler::decode_heap_oop(Register r) {
6221 #ifdef ASSERT
6222 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6223 #endif
6224 if (CompressedOops::base() == nullptr) {
6225 if (CompressedOops::shift() != 0) {
6226 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6227 shlq(r, LogMinObjAlignmentInBytes);
6228 }
6229 } else {
6230 Label done;
6231 shlq(r, LogMinObjAlignmentInBytes);
6232 jccb(Assembler::equal, done);
6233 addq(r, r12_heapbase);
6234 bind(done);
6235 }
6236 verify_oop_msg(r, "broken oop in decode_heap_oop");
6237 }
6238
6239 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6240 // Note: it will change flags
6241 assert (UseCompressedOops, "should only be used for compressed headers");
6242 assert (Universe::heap() != nullptr, "java heap should be initialized");
6243 // Cannot assert, unverified entry point counts instructions (see .ad file)
6244 // vtableStubs also counts instructions in pd_code_size_limit.
6245 // Also do not verify_oop as this is called by verify_oop.
6246 if (CompressedOops::shift() != 0) {
6247 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6248 shlq(r, LogMinObjAlignmentInBytes);
6249 if (CompressedOops::base() != nullptr) {
6250 addq(r, r12_heapbase);
6251 }
6252 } else {
6253 assert (CompressedOops::base() == nullptr, "sanity");
6254 }
6255 }
6256
6257 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6258 // Note: it will change flags
6259 assert (UseCompressedOops, "should only be used for compressed headers");
6260 assert (Universe::heap() != nullptr, "java heap should be initialized");
6261 // Cannot assert, unverified entry point counts instructions (see .ad file)
6262 // vtableStubs also counts instructions in pd_code_size_limit.
6263 // Also do not verify_oop as this is called by verify_oop.
6264 if (CompressedOops::shift() != 0) {
6265 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6266 if (LogMinObjAlignmentInBytes == Address::times_8) {
6267 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6268 } else {
6269 if (dst != src) {
6270 movq(dst, src);
6271 }
6272 shlq(dst, LogMinObjAlignmentInBytes);
6273 if (CompressedOops::base() != nullptr) {
6274 addq(dst, r12_heapbase);
6275 }
6276 }
6277 } else {
6278 assert (CompressedOops::base() == nullptr, "sanity");
6279 if (dst != src) {
6280 movq(dst, src);
6281 }
6282 }
6283 }
6284
6285 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
6286 assert_different_registers(r, tmp);
6287 if (CompressedKlassPointers::base() != nullptr) {
6288 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6289 subq(r, tmp);
6290 }
6291 if (CompressedKlassPointers::shift() != 0) {
6292 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
6293 shrq(r, LogKlassAlignmentInBytes);
6294 }
6295 }
6296
6297 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
6298 assert_different_registers(src, dst);
6299 if (CompressedKlassPointers::base() != nullptr) {
6300 mov64(dst, -(int64_t)CompressedKlassPointers::base());
6301 addq(dst, src);
6302 } else {
6303 movptr(dst, src);
6304 }
6305 if (CompressedKlassPointers::shift() != 0) {
6306 assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
6307 shrq(dst, LogKlassAlignmentInBytes);
6308 }
6309 }
6310
6311 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
6312 assert_different_registers(r, tmp);
6313 // Note: it will change flags
6314 assert(UseCompressedClassPointers, "should only be used for compressed headers");
6315 // Cannot assert, unverified entry point counts instructions (see .ad file)
6316 // vtableStubs also counts instructions in pd_code_size_limit.
6317 // Also do not verify_oop as this is called by verify_oop.
6318 if (CompressedKlassPointers::shift() != 0) {
6319 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
6320 shlq(r, LogKlassAlignmentInBytes);
6321 }
6322 if (CompressedKlassPointers::base() != nullptr) {
6323 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6324 addq(r, tmp);
6325 }
6326 }
6327
6328 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
6329 assert_different_registers(src, dst);
6330 // Note: it will change flags
6331 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6332 // Cannot assert, unverified entry point counts instructions (see .ad file)
6333 // vtableStubs also counts instructions in pd_code_size_limit.
6334 // Also do not verify_oop as this is called by verify_oop.
6335
6336 if (CompressedKlassPointers::base() == nullptr &&
6337 CompressedKlassPointers::shift() == 0) {
6338 // The best case scenario is that there is no base or shift. Then it is already
6339 // a pointer that needs nothing but a register rename.
6340 movl(dst, src);
6341 } else {
6342 if (CompressedKlassPointers::base() != nullptr) {
6343 mov64(dst, (int64_t)CompressedKlassPointers::base());
6344 } else {
6345 xorq(dst, dst);
6346 }
6347 if (CompressedKlassPointers::shift() != 0) {
6348 assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
6349 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
6350 leaq(dst, Address(dst, src, Address::times_8, 0));
6351 } else {
6352 addq(dst, src);
6353 }
6354 }
6355 }
6356
6357 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6358 assert (UseCompressedOops, "should only be used for compressed headers");
6359 assert (Universe::heap() != nullptr, "java heap should be initialized");
6360 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6361 int oop_index = oop_recorder()->find_index(obj);
6362 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6363 mov_narrow_oop(dst, oop_index, rspec);
6364 }
6365
6366 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6367 assert (UseCompressedOops, "should only be used for compressed headers");
6368 assert (Universe::heap() != nullptr, "java heap should be initialized");
6369 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6370 int oop_index = oop_recorder()->find_index(obj);
6371 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6372 mov_narrow_oop(dst, oop_index, rspec);
6373 }
6374
6375 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6376 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6377 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6378 int klass_index = oop_recorder()->find_index(k);
6379 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6380 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6381 }
6382
6383 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6384 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6385 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6386 int klass_index = oop_recorder()->find_index(k);
6387 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6388 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6389 }
6390
6391 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6392 assert (UseCompressedOops, "should only be used for compressed headers");
6393 assert (Universe::heap() != nullptr, "java heap should be initialized");
6394 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6395 int oop_index = oop_recorder()->find_index(obj);
6396 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6397 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6398 }
6399
6400 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6401 assert (UseCompressedOops, "should only be used for compressed headers");
6402 assert (Universe::heap() != nullptr, "java heap should be initialized");
6403 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6404 int oop_index = oop_recorder()->find_index(obj);
6405 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6406 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6407 }
6408
6409 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6410 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6411 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6412 int klass_index = oop_recorder()->find_index(k);
6413 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6414 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6415 }
6416
6417 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6418 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6419 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6420 int klass_index = oop_recorder()->find_index(k);
6421 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6422 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6423 }
6424
6425 void MacroAssembler::reinit_heapbase() {
6426 if (UseCompressedOops) {
6427 if (Universe::heap() != nullptr) {
6428 if (CompressedOops::base() == nullptr) {
6429 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6430 } else {
6431 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6432 }
6433 } else {
6434 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6435 }
6436 }
6437 }
6438
6439 #endif // _LP64
6440
6441 #if COMPILER2_OR_JVMCI
6442
6443 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6444 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
6445 // cnt - number of qwords (8-byte words).
6446 // base - start address, qword aligned.
6447 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6448 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6449 if (use64byteVector) {
6450 evpbroadcastq(xtmp, val, AVX_512bit);
6451 } else if (MaxVectorSize >= 32) {
6452 movdq(xtmp, val);
6453 punpcklqdq(xtmp, xtmp);
6454 vinserti128_high(xtmp, xtmp);
6455 } else {
6456 movdq(xtmp, val);
6457 punpcklqdq(xtmp, xtmp);
6458 }
6459 jmp(L_zero_64_bytes);
6460
6461 BIND(L_loop);
6462 if (MaxVectorSize >= 32) {
6463 fill64(base, 0, xtmp, use64byteVector);
6464 } else {
6465 movdqu(Address(base, 0), xtmp);
6466 movdqu(Address(base, 16), xtmp);
6467 movdqu(Address(base, 32), xtmp);
6468 movdqu(Address(base, 48), xtmp);
6469 }
6470 addptr(base, 64);
6471
6472 BIND(L_zero_64_bytes);
6473 subptr(cnt, 8);
6474 jccb(Assembler::greaterEqual, L_loop);
6475
6476 // Copy trailing 64 bytes
6477 if (use64byteVector) {
6478 addptr(cnt, 8);
6479 jccb(Assembler::equal, L_end);
6480 fill64_masked(3, base, 0, xtmp, mask, cnt, val, true);
6481 jmp(L_end);
6482 } else {
6483 addptr(cnt, 4);
6484 jccb(Assembler::less, L_tail);
6485 if (MaxVectorSize >= 32) {
6486 vmovdqu(Address(base, 0), xtmp);
6487 } else {
6488 movdqu(Address(base, 0), xtmp);
6489 movdqu(Address(base, 16), xtmp);
6490 }
6491 }
6492 addptr(base, 32);
6493 subptr(cnt, 4);
6494
6495 BIND(L_tail);
6496 addptr(cnt, 4);
6497 jccb(Assembler::lessEqual, L_end);
6498 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6499 fill32_masked(3, base, 0, xtmp, mask, cnt, val);
6500 } else {
6501 decrement(cnt);
6502
6503 BIND(L_sloop);
6504 movq(Address(base, 0), xtmp);
6505 addptr(base, 8);
6506 decrement(cnt);
6507 jccb(Assembler::greaterEqual, L_sloop);
6508 }
6509 BIND(L_end);
6510 }
6511
6512 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6513 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6514 // An inline type might be returned. If fields are in registers we
6515 // need to allocate an inline type instance and initialize it with
6516 // the value of the fields.
6517 Label skip;
6518 // We only need a new buffered inline type if a new one is not returned
6519 testptr(rax, 1);
6520 jcc(Assembler::zero, skip);
6521 int call_offset = -1;
6522
6523 #ifdef _LP64
6524 // The following code is similar to allocate_instance but has some slight differences,
6525 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6526 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
6527 Label slow_case;
6528 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6529 mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
6530 if (vk != nullptr) {
6531 // Called from C1, where the return type is statically known.
6532 movptr(rbx, (intptr_t)vk->get_InlineKlass());
6533 jint lh = vk->layout_helper();
6534 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6535 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6536 tlab_allocate(r15_thread, rax, noreg, lh, r13, r14, slow_case);
6537 } else {
6538 jmp(slow_case);
6539 }
6540 } else {
6541 // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
6542 mov(rbx, rax);
6543 andptr(rbx, -2);
6544 if (UseTLAB) {
6545 movl(r14, Address(rbx, Klass::layout_helper_offset()));
6546 testl(r14, Klass::_lh_instance_slow_path_bit);
6547 jcc(Assembler::notZero, slow_case);
6548 tlab_allocate(r15_thread, rax, r14, 0, r13, r14, slow_case);
6549 } else {
6550 jmp(slow_case);
6551 }
6552 }
6553 if (UseTLAB) {
6554 // 2. Initialize buffered inline instance header
6555 Register buffer_obj = rax;
6556 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
6557 xorl(r13, r13);
6558 store_klass_gap(buffer_obj, r13);
6559 if (vk == nullptr) {
6560 // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
6561 mov(r13, rbx);
6562 }
6563 store_klass(buffer_obj, rbx, rscratch1);
6564 // 3. Initialize its fields with an inline class specific handler
6565 if (vk != nullptr) {
6566 call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6567 } else {
6568 movptr(rbx, Address(r13, InstanceKlass::adr_inlineklass_fixed_block_offset()));
6569 movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
6570 call(rbx);
6571 }
6572 jmp(skip);
6573 }
6574 bind(slow_case);
6575 // We failed to allocate a new inline type, fall back to a runtime
6576 // call. Some oop field may be live in some registers but we can't
6577 // tell. That runtime call will take care of preserving them
6578 // across a GC if there's one.
6579 mov(rax, rscratch1);
6580 #endif
6581
6582 if (from_interpreter) {
6583 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6584 } else {
6585 call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6586 call_offset = offset();
6587 }
6588
6589 bind(skip);
6590 return call_offset;
6591 }
6592
6593 // Move a value between registers/stack slots and update the reg_state
6594 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6595 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6596 if (reg_state[to->value()] == reg_written) {
6597 return true; // Already written
6598 }
6599 if (from != to && bt != T_VOID) {
6600 if (reg_state[to->value()] == reg_readonly) {
6601 return false; // Not yet writable
6602 }
6603 if (from->is_reg()) {
6604 if (to->is_reg()) {
6605 if (from->is_XMMRegister()) {
6606 if (bt == T_DOUBLE) {
6607 movdbl(to->as_XMMRegister(), from->as_XMMRegister());
6608 } else {
6609 assert(bt == T_FLOAT, "must be float");
6610 movflt(to->as_XMMRegister(), from->as_XMMRegister());
6611 }
6612 } else {
6613 movq(to->as_Register(), from->as_Register());
6614 }
6615 } else {
6616 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6617 Address to_addr = Address(rsp, st_off);
6618 if (from->is_XMMRegister()) {
6619 if (bt == T_DOUBLE) {
6620 movdbl(to_addr, from->as_XMMRegister());
6621 } else {
6622 assert(bt == T_FLOAT, "must be float");
6623 movflt(to_addr, from->as_XMMRegister());
6624 }
6625 } else {
6626 movq(to_addr, from->as_Register());
6627 }
6628 }
6629 } else {
6630 Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
6631 if (to->is_reg()) {
6632 if (to->is_XMMRegister()) {
6633 if (bt == T_DOUBLE) {
6634 movdbl(to->as_XMMRegister(), from_addr);
6635 } else {
6636 assert(bt == T_FLOAT, "must be float");
6637 movflt(to->as_XMMRegister(), from_addr);
6638 }
6639 } else {
6640 movq(to->as_Register(), from_addr);
6641 }
6642 } else {
6643 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6644 movq(r13, from_addr);
6645 movq(Address(rsp, st_off), r13);
6646 }
6647 }
6648 }
6649 // Update register states
6650 reg_state[from->value()] = reg_writable;
6651 reg_state[to->value()] = reg_written;
6652 return true;
6653 }
6654
6655 // Calculate the extra stack space required for packing or unpacking inline
6656 // args and adjust the stack pointer
6657 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6658 // Two additional slots to account for return address
6659 int sp_inc = (args_on_stack + 2) * VMRegImpl::stack_slot_size;
6660 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6661 // Save the return address, adjust the stack (make sure it is properly
6662 // 16-byte aligned) and copy the return address to the new top of the stack.
6663 // The stack will be repaired on return (see MacroAssembler::remove_frame).
6664 assert(sp_inc > 0, "sanity");
6665 pop(r13);
6666 subptr(rsp, sp_inc);
6667 push(r13);
6668 return sp_inc;
6669 }
6670
6671 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
6672 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6673 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6674 RegState reg_state[]) {
6675 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6676 assert(from->is_valid(), "source must be valid");
6677 bool progress = false;
6678 #ifdef ASSERT
6679 const int start_offset = offset();
6680 #endif
6681
6682 Label L_null, L_notNull;
6683 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6684 Register tmp1 = r10;
6685 Register tmp2 = r13;
6686 Register fromReg = noreg;
6687 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
6688 bool done = true;
6689 bool mark_done = true;
6690 VMReg toReg;
6691 BasicType bt;
6692 // Check if argument requires a null check
6693 bool null_check = false;
6694 VMReg nullCheckReg;
6695 while (stream.next(nullCheckReg, bt)) {
6696 if (sig->at(stream.sig_index())._offset == -1) {
6697 null_check = true;
6698 break;
6699 }
6700 }
6701 stream.reset(sig_index, to_index);
6702 while (stream.next(toReg, bt)) {
6703 assert(toReg->is_valid(), "destination must be valid");
6704 int idx = (int)toReg->value();
6705 if (reg_state[idx] == reg_readonly) {
6706 if (idx != from->value()) {
6707 mark_done = false;
6708 }
6709 done = false;
6710 continue;
6711 } else if (reg_state[idx] == reg_written) {
6712 continue;
6713 }
6714 assert(reg_state[idx] == reg_writable, "must be writable");
6715 reg_state[idx] = reg_written;
6716 progress = true;
6717
6718 if (fromReg == noreg) {
6719 if (from->is_reg()) {
6720 fromReg = from->as_Register();
6721 } else {
6722 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6723 movq(tmp1, Address(rsp, st_off));
6724 fromReg = tmp1;
6725 }
6726 if (null_check) {
6727 // Nullable inline type argument, emit null check
6728 testptr(fromReg, fromReg);
6729 jcc(Assembler::zero, L_null);
6730 }
6731 }
6732 int off = sig->at(stream.sig_index())._offset;
6733 if (off == -1) {
6734 assert(null_check, "Missing null check at");
6735 if (toReg->is_stack()) {
6736 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6737 movq(Address(rsp, st_off), 1);
6738 } else {
6739 movq(toReg->as_Register(), 1);
6740 }
6741 continue;
6742 }
6743 assert(off > 0, "offset in object should be positive");
6744 Address fromAddr = Address(fromReg, off);
6745 if (!toReg->is_XMMRegister()) {
6746 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
6747 if (is_reference_type(bt)) {
6748 load_heap_oop(dst, fromAddr);
6749 } else {
6750 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
6751 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
6752 }
6753 if (toReg->is_stack()) {
6754 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6755 movq(Address(rsp, st_off), dst);
6756 }
6757 } else if (bt == T_DOUBLE) {
6758 movdbl(toReg->as_XMMRegister(), fromAddr);
6759 } else {
6760 assert(bt == T_FLOAT, "must be float");
6761 movflt(toReg->as_XMMRegister(), fromAddr);
6762 }
6763 }
6764 if (progress && null_check) {
6765 if (done) {
6766 jmp(L_notNull);
6767 bind(L_null);
6768 // Set IsInit field to zero to signal that the argument is null.
6769 // Also set all oop fields to zero to make the GC happy.
6770 stream.reset(sig_index, to_index);
6771 while (stream.next(toReg, bt)) {
6772 if (sig->at(stream.sig_index())._offset == -1 ||
6773 bt == T_OBJECT || bt == T_ARRAY) {
6774 if (toReg->is_stack()) {
6775 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6776 movq(Address(rsp, st_off), 0);
6777 } else {
6778 xorq(toReg->as_Register(), toReg->as_Register());
6779 }
6780 }
6781 }
6782 bind(L_notNull);
6783 } else {
6784 bind(L_null);
6785 }
6786 }
6787
6788 sig_index = stream.sig_index();
6789 to_index = stream.regs_index();
6790
6791 if (mark_done && reg_state[from->value()] != reg_written) {
6792 // This is okay because no one else will write to that slot
6793 reg_state[from->value()] = reg_writable;
6794 }
6795 from_index--;
6796 assert(progress || (start_offset == offset()), "should not emit code");
6797 return done;
6798 }
6799
6800 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
6801 VMRegPair* from, int from_count, int& from_index, VMReg to,
6802 RegState reg_state[], Register val_array) {
6803 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
6804 assert(to->is_valid(), "destination must be valid");
6805
6806 if (reg_state[to->value()] == reg_written) {
6807 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6808 return true; // Already written
6809 }
6810
6811 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
6812 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
6813 Register val_obj_tmp = r11;
6814 Register from_reg_tmp = r14;
6815 Register tmp1 = r10;
6816 Register tmp2 = r13;
6817 Register tmp3 = rbx;
6818 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
6819
6820 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
6821
6822 if (reg_state[to->value()] == reg_readonly) {
6823 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
6824 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6825 return false; // Not yet writable
6826 }
6827 val_obj = val_obj_tmp;
6828 }
6829
6830 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
6831 load_heap_oop(val_obj, Address(val_array, index));
6832
6833 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
6834 VMReg fromReg;
6835 BasicType bt;
6836 Label L_null;
6837 while (stream.next(fromReg, bt)) {
6838 assert(fromReg->is_valid(), "source must be valid");
6839 reg_state[fromReg->value()] = reg_writable;
6840
6841 int off = sig->at(stream.sig_index())._offset;
6842 if (off == -1) {
6843 // Nullable inline type argument, emit null check
6844 Label L_notNull;
6845 if (fromReg->is_stack()) {
6846 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6847 testb(Address(rsp, ld_off), 1);
6848 } else {
6849 testb(fromReg->as_Register(), 1);
6850 }
6851 jcc(Assembler::notZero, L_notNull);
6852 movptr(val_obj, 0);
6853 jmp(L_null);
6854 bind(L_notNull);
6855 continue;
6856 }
6857
6858 assert(off > 0, "offset in object should be positive");
6859 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
6860
6861 Address dst(val_obj, off);
6862 if (!fromReg->is_XMMRegister()) {
6863 Register src;
6864 if (fromReg->is_stack()) {
6865 src = from_reg_tmp;
6866 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6867 load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
6868 } else {
6869 src = fromReg->as_Register();
6870 }
6871 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
6872 if (is_reference_type(bt)) {
6873 store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
6874 } else {
6875 store_sized_value(dst, src, size_in_bytes);
6876 }
6877 } else if (bt == T_DOUBLE) {
6878 movdbl(dst, fromReg->as_XMMRegister());
6879 } else {
6880 assert(bt == T_FLOAT, "must be float");
6881 movflt(dst, fromReg->as_XMMRegister());
6882 }
6883 }
6884 bind(L_null);
6885 sig_index = stream.sig_index();
6886 from_index = stream.regs_index();
6887
6888 assert(reg_state[to->value()] == reg_writable, "must have already been read");
6889 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6890 assert(success, "to register must be writeable");
6891 return true;
6892 }
6893
6894 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6895 return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
6896 }
6897
6898 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
6899 assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6900 if (needs_stack_repair) {
6901 movq(rbp, Address(rsp, initial_framesize));
6902 // The stack increment resides just below the saved rbp
6903 addq(rsp, Address(rsp, initial_framesize - wordSize));
6904 } else {
6905 if (initial_framesize > 0) {
6906 addq(rsp, initial_framesize);
6907 }
6908 pop(rbp);
6909 }
6910 }
6911
6912 // Clearing constant sized memory using YMM/ZMM registers.
6913 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6914 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6915 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6916
6917 int vector64_count = (cnt & (~0x7)) >> 3;
6918 cnt = cnt & 0x7;
6919 const int fill64_per_loop = 4;
6920 const int max_unrolled_fill64 = 8;
6921
6922 // 64 byte initialization loop.
6923 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6924 int start64 = 0;
6925 if (vector64_count > max_unrolled_fill64) {
6926 Label LOOP;
6927 Register index = rtmp;
6928
6929 start64 = vector64_count - (vector64_count % fill64_per_loop);
6930
6931 movl(index, 0);
6932 BIND(LOOP);
6933 for (int i = 0; i < fill64_per_loop; i++) {
6934 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6935 }
6936 addl(index, fill64_per_loop * 64);
6937 cmpl(index, start64 * 64);
6938 jccb(Assembler::less, LOOP);
6939 }
6940 for (int i = start64; i < vector64_count; i++) {
6941 fill64(base, i * 64, xtmp, use64byteVector);
6942 }
6943
6944 // Clear remaining 64 byte tail.
6945 int disp = vector64_count * 64;
6946 if (cnt) {
6947 switch (cnt) {
6948 case 1:
6949 movq(Address(base, disp), xtmp);
6950 break;
6951 case 2:
6952 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6953 break;
6954 case 3:
6955 movl(rtmp, 0x7);
6956 kmovwl(mask, rtmp);
6957 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6958 break;
6959 case 4:
6960 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6961 break;
6962 case 5:
6963 if (use64byteVector) {
6964 movl(rtmp, 0x1F);
6965 kmovwl(mask, rtmp);
6966 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6967 } else {
6968 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6969 movq(Address(base, disp + 32), xtmp);
6970 }
6971 break;
6972 case 6:
6973 if (use64byteVector) {
6974 movl(rtmp, 0x3F);
6975 kmovwl(mask, rtmp);
6976 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6977 } else {
6978 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6979 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6980 }
6981 break;
6982 case 7:
6983 if (use64byteVector) {
6984 movl(rtmp, 0x7F);
6985 kmovwl(mask, rtmp);
6986 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6987 } else {
6988 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6989 movl(rtmp, 0x7);
6990 kmovwl(mask, rtmp);
6991 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6992 }
6993 break;
6994 default:
6995 fatal("Unexpected length : %d\n",cnt);
6996 break;
6997 }
6998 }
6999 }
7000
7001 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
7002 bool is_large, bool word_copy_only, KRegister mask) {
7003 // cnt - number of qwords (8-byte words).
7004 // base - start address, qword aligned.
7005 // is_large - if optimizers know cnt is larger than InitArrayShortSize
7006 assert(base==rdi, "base register must be edi for rep stos");
7007 assert(val==rax, "val register must be eax for rep stos");
7008 assert(cnt==rcx, "cnt register must be ecx for rep stos");
7009 assert(InitArrayShortSize % BytesPerLong == 0,
7010 "InitArrayShortSize should be the multiple of BytesPerLong");
7011
7012 Label DONE;
7013
7014 if (!is_large) {
7015 Label LOOP, LONG;
7016 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7017 jccb(Assembler::greater, LONG);
7018
7019 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7020
7021 decrement(cnt);
7022 jccb(Assembler::negative, DONE); // Zero length
7023
7024 // Use individual pointer-sized stores for small counts:
7025 BIND(LOOP);
7026 movptr(Address(base, cnt, Address::times_ptr), val);
7027 decrement(cnt);
7028 jccb(Assembler::greaterEqual, LOOP);
7029 jmpb(DONE);
7030
7031 BIND(LONG);
7032 }
7033
7034 // Use longer rep-prefixed ops for non-small counts:
7035 if (UseFastStosb && !word_copy_only) {
7036 shlptr(cnt, 3); // convert to number of bytes
7037 rep_stosb();
7038 } else if (UseXMMForObjInit) {
7039 xmm_clear_mem(base, cnt, val, xtmp, mask);
7040 } else {
7041 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7042 rep_stos();
7043 }
7044
7045 BIND(DONE);
7046 }
7047
7048 #endif //COMPILER2_OR_JVMCI
7049
7050
7051 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7052 Register to, Register value, Register count,
7053 Register rtmp, XMMRegister xtmp) {
7054 ShortBranchVerifier sbv(this);
7055 assert_different_registers(to, value, count, rtmp);
7056 Label L_exit;
7057 Label L_fill_2_bytes, L_fill_4_bytes;
7058
7059 #if defined(COMPILER2) && defined(_LP64)
7060 if(MaxVectorSize >=32 &&
7061 VM_Version::supports_avx512vlbw() &&
7062 VM_Version::supports_bmi2()) {
7063 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
7064 return;
7065 }
7066 #endif
7067
7068 int shift = -1;
7069 switch (t) {
7070 case T_BYTE:
7071 shift = 2;
7072 break;
7073 case T_SHORT:
7074 shift = 1;
7075 break;
7076 case T_INT:
7077 shift = 0;
7078 break;
7079 default: ShouldNotReachHere();
7080 }
7081
7082 if (t == T_BYTE) {
7083 andl(value, 0xff);
7084 movl(rtmp, value);
7085 shll(rtmp, 8);
7086 orl(value, rtmp);
7087 }
7088 if (t == T_SHORT) {
7089 andl(value, 0xffff);
7090 }
7091 if (t == T_BYTE || t == T_SHORT) {
7092 movl(rtmp, value);
7093 shll(rtmp, 16);
7094 orl(value, rtmp);
7095 }
7096
7097 cmpptr(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
7098 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
7099 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
7100 Label L_skip_align2;
7101 // align source address at 4 bytes address boundary
7102 if (t == T_BYTE) {
7103 Label L_skip_align1;
7104 // One byte misalignment happens only for byte arrays
7105 testptr(to, 1);
7106 jccb(Assembler::zero, L_skip_align1);
7107 movb(Address(to, 0), value);
7108 increment(to);
7109 decrement(count);
7110 BIND(L_skip_align1);
7111 }
7112 // Two bytes misalignment happens only for byte and short (char) arrays
7113 testptr(to, 2);
7114 jccb(Assembler::zero, L_skip_align2);
7115 movw(Address(to, 0), value);
7116 addptr(to, 2);
7117 subptr(count, 1<<(shift-1));
7118 BIND(L_skip_align2);
7119 }
7120 if (UseSSE < 2) {
7121 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7122 // Fill 32-byte chunks
7123 subptr(count, 8 << shift);
7124 jcc(Assembler::less, L_check_fill_8_bytes);
7125 align(16);
7126
7127 BIND(L_fill_32_bytes_loop);
7128
7129 for (int i = 0; i < 32; i += 4) {
7130 movl(Address(to, i), value);
7131 }
7132
7133 addptr(to, 32);
7134 subptr(count, 8 << shift);
7135 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7136 BIND(L_check_fill_8_bytes);
7137 addptr(count, 8 << shift);
7138 jccb(Assembler::zero, L_exit);
7139 jmpb(L_fill_8_bytes);
7140
7141 //
7142 // length is too short, just fill qwords
7143 //
7144 BIND(L_fill_8_bytes_loop);
7145 movl(Address(to, 0), value);
7146 movl(Address(to, 4), value);
7147 addptr(to, 8);
7148 BIND(L_fill_8_bytes);
7149 subptr(count, 1 << (shift + 1));
7150 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7151 // fall through to fill 4 bytes
7152 } else {
7153 Label L_fill_32_bytes;
7154 if (!UseUnalignedLoadStores) {
7155 // align to 8 bytes, we know we are 4 byte aligned to start
7156 testptr(to, 4);
7157 jccb(Assembler::zero, L_fill_32_bytes);
7158 movl(Address(to, 0), value);
7159 addptr(to, 4);
7160 subptr(count, 1<<shift);
7161 }
7162 BIND(L_fill_32_bytes);
7163 {
7164 assert( UseSSE >= 2, "supported cpu only" );
7165 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
7166 movdl(xtmp, value);
7167 if (UseAVX >= 2 && UseUnalignedLoadStores) {
7168 Label L_check_fill_32_bytes;
7169 if (UseAVX > 2) {
7170 // Fill 64-byte chunks
7171 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
7172
7173 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
7174 cmpptr(count, VM_Version::avx3_threshold());
7175 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
7176
7177 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
7178
7179 subptr(count, 16 << shift);
7180 jccb(Assembler::less, L_check_fill_32_bytes);
7181 align(16);
7182
7183 BIND(L_fill_64_bytes_loop_avx3);
7184 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
7185 addptr(to, 64);
7186 subptr(count, 16 << shift);
7187 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
7188 jmpb(L_check_fill_32_bytes);
7189
7190 BIND(L_check_fill_64_bytes_avx2);
7191 }
7192 // Fill 64-byte chunks
7193 Label L_fill_64_bytes_loop;
7194 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
7195
7196 subptr(count, 16 << shift);
7197 jcc(Assembler::less, L_check_fill_32_bytes);
7198 align(16);
7199
7200 BIND(L_fill_64_bytes_loop);
7201 vmovdqu(Address(to, 0), xtmp);
7202 vmovdqu(Address(to, 32), xtmp);
7203 addptr(to, 64);
7204 subptr(count, 16 << shift);
7205 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
7206
7207 BIND(L_check_fill_32_bytes);
7208 addptr(count, 8 << shift);
7209 jccb(Assembler::less, L_check_fill_8_bytes);
7210 vmovdqu(Address(to, 0), xtmp);
7211 addptr(to, 32);
7212 subptr(count, 8 << shift);
7213
7214 BIND(L_check_fill_8_bytes);
7215 // clean upper bits of YMM registers
7216 movdl(xtmp, value);
7217 pshufd(xtmp, xtmp, 0);
7218 } else {
7219 // Fill 32-byte chunks
7220 pshufd(xtmp, xtmp, 0);
7221
7222 subptr(count, 8 << shift);
7223 jcc(Assembler::less, L_check_fill_8_bytes);
7224 align(16);
7225
7226 BIND(L_fill_32_bytes_loop);
7227
7228 if (UseUnalignedLoadStores) {
7229 movdqu(Address(to, 0), xtmp);
7230 movdqu(Address(to, 16), xtmp);
7231 } else {
7232 movq(Address(to, 0), xtmp);
7233 movq(Address(to, 8), xtmp);
7234 movq(Address(to, 16), xtmp);
7235 movq(Address(to, 24), xtmp);
7236 }
7237
7238 addptr(to, 32);
7239 subptr(count, 8 << shift);
7240 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7241
7242 BIND(L_check_fill_8_bytes);
7243 }
7244 addptr(count, 8 << shift);
7245 jccb(Assembler::zero, L_exit);
7246 jmpb(L_fill_8_bytes);
7247
7248 //
7249 // length is too short, just fill qwords
7250 //
7251 BIND(L_fill_8_bytes_loop);
7252 movq(Address(to, 0), xtmp);
7253 addptr(to, 8);
7254 BIND(L_fill_8_bytes);
7255 subptr(count, 1 << (shift + 1));
7256 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7257 }
7258 }
7259 // fill trailing 4 bytes
7260 BIND(L_fill_4_bytes);
7261 testl(count, 1<<shift);
7262 jccb(Assembler::zero, L_fill_2_bytes);
7263 movl(Address(to, 0), value);
7264 if (t == T_BYTE || t == T_SHORT) {
7265 Label L_fill_byte;
7266 addptr(to, 4);
7267 BIND(L_fill_2_bytes);
7268 // fill trailing 2 bytes
7269 testl(count, 1<<(shift-1));
7270 jccb(Assembler::zero, L_fill_byte);
7271 movw(Address(to, 0), value);
7272 if (t == T_BYTE) {
7273 addptr(to, 2);
7274 BIND(L_fill_byte);
7275 // fill trailing byte
7276 testl(count, 1);
7277 jccb(Assembler::zero, L_exit);
7278 movb(Address(to, 0), value);
7279 } else {
7280 BIND(L_fill_byte);
7281 }
7282 } else {
7283 BIND(L_fill_2_bytes);
7284 }
7285 BIND(L_exit);
7286 }
7287
7288 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
7289 switch(type) {
7290 case T_BYTE:
7291 case T_BOOLEAN:
7292 evpbroadcastb(dst, src, vector_len);
7293 break;
7294 case T_SHORT:
7295 case T_CHAR:
7296 evpbroadcastw(dst, src, vector_len);
7297 break;
7298 case T_INT:
7299 case T_FLOAT:
7300 evpbroadcastd(dst, src, vector_len);
7301 break;
7302 case T_LONG:
7303 case T_DOUBLE:
7304 evpbroadcastq(dst, src, vector_len);
7305 break;
7306 default:
7307 fatal("Unhandled type : %s", type2name(type));
7308 break;
7309 }
7310 }
7311
7312 // encode char[] to byte[] in ISO_8859_1 or ASCII
7313 //@IntrinsicCandidate
7314 //private static int implEncodeISOArray(byte[] sa, int sp,
7315 //byte[] da, int dp, int len) {
7316 // int i = 0;
7317 // for (; i < len; i++) {
7318 // char c = StringUTF16.getChar(sa, sp++);
7319 // if (c > '\u00FF')
7320 // break;
7321 // da[dp++] = (byte)c;
7322 // }
7323 // return i;
7324 //}
7325 //
7326 //@IntrinsicCandidate
7327 //private static int implEncodeAsciiArray(char[] sa, int sp,
7328 // byte[] da, int dp, int len) {
7329 // int i = 0;
7330 // for (; i < len; i++) {
7331 // char c = sa[sp++];
7332 // if (c >= '\u0080')
7333 // break;
7334 // da[dp++] = (byte)c;
7335 // }
7336 // return i;
7337 //}
7338 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7339 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7340 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7341 Register tmp5, Register result, bool ascii) {
7342
7343 // rsi: src
7344 // rdi: dst
7345 // rdx: len
7346 // rcx: tmp5
7347 // rax: result
7348 ShortBranchVerifier sbv(this);
7349 assert_different_registers(src, dst, len, tmp5, result);
7350 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7351
7352 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
7353 int short_mask = ascii ? 0xff80 : 0xff00;
7354
7355 // set result
7356 xorl(result, result);
7357 // check for zero length
7358 testl(len, len);
7359 jcc(Assembler::zero, L_done);
7360
7361 movl(result, len);
7362
7363 // Setup pointers
7364 lea(src, Address(src, len, Address::times_2)); // char[]
7365 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7366 negptr(len);
7367
7368 if (UseSSE42Intrinsics || UseAVX >= 2) {
7369 Label L_copy_8_chars, L_copy_8_chars_exit;
7370 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7371
7372 if (UseAVX >= 2) {
7373 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7374 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7375 movdl(tmp1Reg, tmp5);
7376 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7377 jmp(L_chars_32_check);
7378
7379 bind(L_copy_32_chars);
7380 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7381 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7382 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7383 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7384 jccb(Assembler::notZero, L_copy_32_chars_exit);
7385 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7386 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7387 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7388
7389 bind(L_chars_32_check);
7390 addptr(len, 32);
7391 jcc(Assembler::lessEqual, L_copy_32_chars);
7392
7393 bind(L_copy_32_chars_exit);
7394 subptr(len, 16);
7395 jccb(Assembler::greater, L_copy_16_chars_exit);
7396
7397 } else if (UseSSE42Intrinsics) {
7398 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7399 movdl(tmp1Reg, tmp5);
7400 pshufd(tmp1Reg, tmp1Reg, 0);
7401 jmpb(L_chars_16_check);
7402 }
7403
7404 bind(L_copy_16_chars);
7405 if (UseAVX >= 2) {
7406 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7407 vptest(tmp2Reg, tmp1Reg);
7408 jcc(Assembler::notZero, L_copy_16_chars_exit);
7409 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7410 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7411 } else {
7412 if (UseAVX > 0) {
7413 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7414 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7415 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7416 } else {
7417 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7418 por(tmp2Reg, tmp3Reg);
7419 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7420 por(tmp2Reg, tmp4Reg);
7421 }
7422 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7423 jccb(Assembler::notZero, L_copy_16_chars_exit);
7424 packuswb(tmp3Reg, tmp4Reg);
7425 }
7426 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7427
7428 bind(L_chars_16_check);
7429 addptr(len, 16);
7430 jcc(Assembler::lessEqual, L_copy_16_chars);
7431
7432 bind(L_copy_16_chars_exit);
7433 if (UseAVX >= 2) {
7434 // clean upper bits of YMM registers
7435 vpxor(tmp2Reg, tmp2Reg);
7436 vpxor(tmp3Reg, tmp3Reg);
7437 vpxor(tmp4Reg, tmp4Reg);
7438 movdl(tmp1Reg, tmp5);
7439 pshufd(tmp1Reg, tmp1Reg, 0);
7440 }
7441 subptr(len, 8);
7442 jccb(Assembler::greater, L_copy_8_chars_exit);
7443
7444 bind(L_copy_8_chars);
7445 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7446 ptest(tmp3Reg, tmp1Reg);
7447 jccb(Assembler::notZero, L_copy_8_chars_exit);
7448 packuswb(tmp3Reg, tmp1Reg);
7449 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7450 addptr(len, 8);
7451 jccb(Assembler::lessEqual, L_copy_8_chars);
7452
7453 bind(L_copy_8_chars_exit);
7454 subptr(len, 8);
7455 jccb(Assembler::zero, L_done);
7456 }
7457
7458 bind(L_copy_1_char);
7459 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7460 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7461 jccb(Assembler::notZero, L_copy_1_char_exit);
7462 movb(Address(dst, len, Address::times_1, 0), tmp5);
7463 addptr(len, 1);
7464 jccb(Assembler::less, L_copy_1_char);
7465
7466 bind(L_copy_1_char_exit);
7467 addptr(result, len); // len is negative count of not processed elements
7468
7469 bind(L_done);
7470 }
7471
7472 #ifdef _LP64
7473 /**
7474 * Helper for multiply_to_len().
7475 */
7476 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7477 addq(dest_lo, src1);
7478 adcq(dest_hi, 0);
7479 addq(dest_lo, src2);
7480 adcq(dest_hi, 0);
7481 }
7482
7483 /**
7484 * Multiply 64 bit by 64 bit first loop.
7485 */
7486 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7487 Register y, Register y_idx, Register z,
7488 Register carry, Register product,
7489 Register idx, Register kdx) {
7490 //
7491 // jlong carry, x[], y[], z[];
7492 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7493 // huge_128 product = y[idx] * x[xstart] + carry;
7494 // z[kdx] = (jlong)product;
7495 // carry = (jlong)(product >>> 64);
7496 // }
7497 // z[xstart] = carry;
7498 //
7499
7500 Label L_first_loop, L_first_loop_exit;
7501 Label L_one_x, L_one_y, L_multiply;
7502
7503 decrementl(xstart);
7504 jcc(Assembler::negative, L_one_x);
7505
7506 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7507 rorq(x_xstart, 32); // convert big-endian to little-endian
7508
7509 bind(L_first_loop);
7510 decrementl(idx);
7511 jcc(Assembler::negative, L_first_loop_exit);
7512 decrementl(idx);
7513 jcc(Assembler::negative, L_one_y);
7514 movq(y_idx, Address(y, idx, Address::times_4, 0));
7515 rorq(y_idx, 32); // convert big-endian to little-endian
7516 bind(L_multiply);
7517 movq(product, x_xstart);
7518 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7519 addq(product, carry);
7520 adcq(rdx, 0);
7521 subl(kdx, 2);
7522 movl(Address(z, kdx, Address::times_4, 4), product);
7523 shrq(product, 32);
7524 movl(Address(z, kdx, Address::times_4, 0), product);
7525 movq(carry, rdx);
7526 jmp(L_first_loop);
7527
7528 bind(L_one_y);
7529 movl(y_idx, Address(y, 0));
7530 jmp(L_multiply);
7531
7532 bind(L_one_x);
7533 movl(x_xstart, Address(x, 0));
7534 jmp(L_first_loop);
7535
7536 bind(L_first_loop_exit);
7537 }
7538
7539 /**
7540 * Multiply 64 bit by 64 bit and add 128 bit.
7541 */
7542 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7543 Register yz_idx, Register idx,
7544 Register carry, Register product, int offset) {
7545 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7546 // z[kdx] = (jlong)product;
7547
7548 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7549 rorq(yz_idx, 32); // convert big-endian to little-endian
7550 movq(product, x_xstart);
7551 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7552 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7553 rorq(yz_idx, 32); // convert big-endian to little-endian
7554
7555 add2_with_carry(rdx, product, carry, yz_idx);
7556
7557 movl(Address(z, idx, Address::times_4, offset+4), product);
7558 shrq(product, 32);
7559 movl(Address(z, idx, Address::times_4, offset), product);
7560
7561 }
7562
7563 /**
7564 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7565 */
7566 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7567 Register yz_idx, Register idx, Register jdx,
7568 Register carry, Register product,
7569 Register carry2) {
7570 // jlong carry, x[], y[], z[];
7571 // int kdx = ystart+1;
7572 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7573 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7574 // z[kdx+idx+1] = (jlong)product;
7575 // jlong carry2 = (jlong)(product >>> 64);
7576 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7577 // z[kdx+idx] = (jlong)product;
7578 // carry = (jlong)(product >>> 64);
7579 // }
7580 // idx += 2;
7581 // if (idx > 0) {
7582 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7583 // z[kdx+idx] = (jlong)product;
7584 // carry = (jlong)(product >>> 64);
7585 // }
7586 //
7587
7588 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7589
7590 movl(jdx, idx);
7591 andl(jdx, 0xFFFFFFFC);
7592 shrl(jdx, 2);
7593
7594 bind(L_third_loop);
7595 subl(jdx, 1);
7596 jcc(Assembler::negative, L_third_loop_exit);
7597 subl(idx, 4);
7598
7599 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7600 movq(carry2, rdx);
7601
7602 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7603 movq(carry, rdx);
7604 jmp(L_third_loop);
7605
7606 bind (L_third_loop_exit);
7607
7608 andl (idx, 0x3);
7609 jcc(Assembler::zero, L_post_third_loop_done);
7610
7611 Label L_check_1;
7612 subl(idx, 2);
7613 jcc(Assembler::negative, L_check_1);
7614
7615 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7616 movq(carry, rdx);
7617
7618 bind (L_check_1);
7619 addl (idx, 0x2);
7620 andl (idx, 0x1);
7621 subl(idx, 1);
7622 jcc(Assembler::negative, L_post_third_loop_done);
7623
7624 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7625 movq(product, x_xstart);
7626 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7627 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7628
7629 add2_with_carry(rdx, product, yz_idx, carry);
7630
7631 movl(Address(z, idx, Address::times_4, 0), product);
7632 shrq(product, 32);
7633
7634 shlq(rdx, 32);
7635 orq(product, rdx);
7636 movq(carry, product);
7637
7638 bind(L_post_third_loop_done);
7639 }
7640
7641 /**
7642 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7643 *
7644 */
7645 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7646 Register carry, Register carry2,
7647 Register idx, Register jdx,
7648 Register yz_idx1, Register yz_idx2,
7649 Register tmp, Register tmp3, Register tmp4) {
7650 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7651
7652 // jlong carry, x[], y[], z[];
7653 // int kdx = ystart+1;
7654 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7655 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7656 // jlong carry2 = (jlong)(tmp3 >>> 64);
7657 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7658 // carry = (jlong)(tmp4 >>> 64);
7659 // z[kdx+idx+1] = (jlong)tmp3;
7660 // z[kdx+idx] = (jlong)tmp4;
7661 // }
7662 // idx += 2;
7663 // if (idx > 0) {
7664 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7665 // z[kdx+idx] = (jlong)yz_idx1;
7666 // carry = (jlong)(yz_idx1 >>> 64);
7667 // }
7668 //
7669
7670 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7671
7672 movl(jdx, idx);
7673 andl(jdx, 0xFFFFFFFC);
7674 shrl(jdx, 2);
7675
7676 bind(L_third_loop);
7677 subl(jdx, 1);
7678 jcc(Assembler::negative, L_third_loop_exit);
7679 subl(idx, 4);
7680
7681 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7682 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7683 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7684 rorxq(yz_idx2, yz_idx2, 32);
7685
7686 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7687 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7688
7689 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7690 rorxq(yz_idx1, yz_idx1, 32);
7691 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7692 rorxq(yz_idx2, yz_idx2, 32);
7693
7694 if (VM_Version::supports_adx()) {
7695 adcxq(tmp3, carry);
7696 adoxq(tmp3, yz_idx1);
7697
7698 adcxq(tmp4, tmp);
7699 adoxq(tmp4, yz_idx2);
7700
7701 movl(carry, 0); // does not affect flags
7702 adcxq(carry2, carry);
7703 adoxq(carry2, carry);
7704 } else {
7705 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7706 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7707 }
7708 movq(carry, carry2);
7709
7710 movl(Address(z, idx, Address::times_4, 12), tmp3);
7711 shrq(tmp3, 32);
7712 movl(Address(z, idx, Address::times_4, 8), tmp3);
7713
7714 movl(Address(z, idx, Address::times_4, 4), tmp4);
7715 shrq(tmp4, 32);
7716 movl(Address(z, idx, Address::times_4, 0), tmp4);
7717
7718 jmp(L_third_loop);
7719
7720 bind (L_third_loop_exit);
7721
7722 andl (idx, 0x3);
7723 jcc(Assembler::zero, L_post_third_loop_done);
7724
7725 Label L_check_1;
7726 subl(idx, 2);
7727 jcc(Assembler::negative, L_check_1);
7728
7729 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7730 rorxq(yz_idx1, yz_idx1, 32);
7731 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7732 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7733 rorxq(yz_idx2, yz_idx2, 32);
7734
7735 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7736
7737 movl(Address(z, idx, Address::times_4, 4), tmp3);
7738 shrq(tmp3, 32);
7739 movl(Address(z, idx, Address::times_4, 0), tmp3);
7740 movq(carry, tmp4);
7741
7742 bind (L_check_1);
7743 addl (idx, 0x2);
7744 andl (idx, 0x1);
7745 subl(idx, 1);
7746 jcc(Assembler::negative, L_post_third_loop_done);
7747 movl(tmp4, Address(y, idx, Address::times_4, 0));
7748 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7749 movl(tmp4, Address(z, idx, Address::times_4, 0));
7750
7751 add2_with_carry(carry2, tmp3, tmp4, carry);
7752
7753 movl(Address(z, idx, Address::times_4, 0), tmp3);
7754 shrq(tmp3, 32);
7755
7756 shlq(carry2, 32);
7757 orq(tmp3, carry2);
7758 movq(carry, tmp3);
7759
7760 bind(L_post_third_loop_done);
7761 }
7762
7763 /**
7764 * Code for BigInteger::multiplyToLen() intrinsic.
7765 *
7766 * rdi: x
7767 * rax: xlen
7768 * rsi: y
7769 * rcx: ylen
7770 * r8: z
7771 * r11: tmp0
7772 * r12: tmp1
7773 * r13: tmp2
7774 * r14: tmp3
7775 * r15: tmp4
7776 * rbx: tmp5
7777 *
7778 */
7779 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7780 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7781 ShortBranchVerifier sbv(this);
7782 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7783
7784 push(tmp0);
7785 push(tmp1);
7786 push(tmp2);
7787 push(tmp3);
7788 push(tmp4);
7789 push(tmp5);
7790
7791 push(xlen);
7792
7793 const Register idx = tmp1;
7794 const Register kdx = tmp2;
7795 const Register xstart = tmp3;
7796
7797 const Register y_idx = tmp4;
7798 const Register carry = tmp5;
7799 const Register product = xlen;
7800 const Register x_xstart = tmp0;
7801
7802 // First Loop.
7803 //
7804 // final static long LONG_MASK = 0xffffffffL;
7805 // int xstart = xlen - 1;
7806 // int ystart = ylen - 1;
7807 // long carry = 0;
7808 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7809 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7810 // z[kdx] = (int)product;
7811 // carry = product >>> 32;
7812 // }
7813 // z[xstart] = (int)carry;
7814 //
7815
7816 movl(idx, ylen); // idx = ylen;
7817 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7818 xorq(carry, carry); // carry = 0;
7819
7820 Label L_done;
7821
7822 movl(xstart, xlen);
7823 decrementl(xstart);
7824 jcc(Assembler::negative, L_done);
7825
7826 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7827
7828 Label L_second_loop;
7829 testl(kdx, kdx);
7830 jcc(Assembler::zero, L_second_loop);
7831
7832 Label L_carry;
7833 subl(kdx, 1);
7834 jcc(Assembler::zero, L_carry);
7835
7836 movl(Address(z, kdx, Address::times_4, 0), carry);
7837 shrq(carry, 32);
7838 subl(kdx, 1);
7839
7840 bind(L_carry);
7841 movl(Address(z, kdx, Address::times_4, 0), carry);
7842
7843 // Second and third (nested) loops.
7844 //
7845 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7846 // carry = 0;
7847 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7848 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7849 // (z[k] & LONG_MASK) + carry;
7850 // z[k] = (int)product;
7851 // carry = product >>> 32;
7852 // }
7853 // z[i] = (int)carry;
7854 // }
7855 //
7856 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7857
7858 const Register jdx = tmp1;
7859
7860 bind(L_second_loop);
7861 xorl(carry, carry); // carry = 0;
7862 movl(jdx, ylen); // j = ystart+1
7863
7864 subl(xstart, 1); // i = xstart-1;
7865 jcc(Assembler::negative, L_done);
7866
7867 push (z);
7868
7869 Label L_last_x;
7870 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7871 subl(xstart, 1); // i = xstart-1;
7872 jcc(Assembler::negative, L_last_x);
7873
7874 if (UseBMI2Instructions) {
7875 movq(rdx, Address(x, xstart, Address::times_4, 0));
7876 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7877 } else {
7878 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7879 rorq(x_xstart, 32); // convert big-endian to little-endian
7880 }
7881
7882 Label L_third_loop_prologue;
7883 bind(L_third_loop_prologue);
7884
7885 push (x);
7886 push (xstart);
7887 push (ylen);
7888
7889
7890 if (UseBMI2Instructions) {
7891 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7892 } else { // !UseBMI2Instructions
7893 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7894 }
7895
7896 pop(ylen);
7897 pop(xlen);
7898 pop(x);
7899 pop(z);
7900
7901 movl(tmp3, xlen);
7902 addl(tmp3, 1);
7903 movl(Address(z, tmp3, Address::times_4, 0), carry);
7904 subl(tmp3, 1);
7905 jccb(Assembler::negative, L_done);
7906
7907 shrq(carry, 32);
7908 movl(Address(z, tmp3, Address::times_4, 0), carry);
7909 jmp(L_second_loop);
7910
7911 // Next infrequent code is moved outside loops.
7912 bind(L_last_x);
7913 if (UseBMI2Instructions) {
7914 movl(rdx, Address(x, 0));
7915 } else {
7916 movl(x_xstart, Address(x, 0));
7917 }
7918 jmp(L_third_loop_prologue);
7919
7920 bind(L_done);
7921
7922 pop(xlen);
7923
7924 pop(tmp5);
7925 pop(tmp4);
7926 pop(tmp3);
7927 pop(tmp2);
7928 pop(tmp1);
7929 pop(tmp0);
7930 }
7931
7932 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7933 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7934 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7935 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7936 Label VECTOR8_TAIL, VECTOR4_TAIL;
7937 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7938 Label SAME_TILL_END, DONE;
7939 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7940
7941 //scale is in rcx in both Win64 and Unix
7942 ShortBranchVerifier sbv(this);
7943
7944 shlq(length);
7945 xorq(result, result);
7946
7947 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7948 VM_Version::supports_avx512vlbw()) {
7949 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7950
7951 cmpq(length, 64);
7952 jcc(Assembler::less, VECTOR32_TAIL);
7953
7954 movq(tmp1, length);
7955 andq(tmp1, 0x3F); // tail count
7956 andq(length, ~(0x3F)); //vector count
7957
7958 bind(VECTOR64_LOOP);
7959 // AVX512 code to compare 64 byte vectors.
7960 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7961 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7962 kortestql(k7, k7);
7963 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7964 addq(result, 64);
7965 subq(length, 64);
7966 jccb(Assembler::notZero, VECTOR64_LOOP);
7967
7968 //bind(VECTOR64_TAIL);
7969 testq(tmp1, tmp1);
7970 jcc(Assembler::zero, SAME_TILL_END);
7971
7972 //bind(VECTOR64_TAIL);
7973 // AVX512 code to compare up to 63 byte vectors.
7974 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7975 shlxq(tmp2, tmp2, tmp1);
7976 notq(tmp2);
7977 kmovql(k3, tmp2);
7978
7979 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7980 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7981
7982 ktestql(k7, k3);
7983 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7984
7985 bind(VECTOR64_NOT_EQUAL);
7986 kmovql(tmp1, k7);
7987 notq(tmp1);
7988 tzcntq(tmp1, tmp1);
7989 addq(result, tmp1);
7990 shrq(result);
7991 jmp(DONE);
7992 bind(VECTOR32_TAIL);
7993 }
7994
7995 cmpq(length, 8);
7996 jcc(Assembler::equal, VECTOR8_LOOP);
7997 jcc(Assembler::less, VECTOR4_TAIL);
7998
7999 if (UseAVX >= 2) {
8000 Label VECTOR16_TAIL, VECTOR32_LOOP;
8001
8002 cmpq(length, 16);
8003 jcc(Assembler::equal, VECTOR16_LOOP);
8004 jcc(Assembler::less, VECTOR8_LOOP);
8005
8006 cmpq(length, 32);
8007 jccb(Assembler::less, VECTOR16_TAIL);
8008
8009 subq(length, 32);
8010 bind(VECTOR32_LOOP);
8011 vmovdqu(rymm0, Address(obja, result));
8012 vmovdqu(rymm1, Address(objb, result));
8013 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
8014 vptest(rymm2, rymm2);
8015 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
8016 addq(result, 32);
8017 subq(length, 32);
8018 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
8019 addq(length, 32);
8020 jcc(Assembler::equal, SAME_TILL_END);
8021 //falling through if less than 32 bytes left //close the branch here.
8022
8023 bind(VECTOR16_TAIL);
8024 cmpq(length, 16);
8025 jccb(Assembler::less, VECTOR8_TAIL);
8026 bind(VECTOR16_LOOP);
8027 movdqu(rymm0, Address(obja, result));
8028 movdqu(rymm1, Address(objb, result));
8029 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
8030 ptest(rymm2, rymm2);
8031 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8032 addq(result, 16);
8033 subq(length, 16);
8034 jcc(Assembler::equal, SAME_TILL_END);
8035 //falling through if less than 16 bytes left
8036 } else {//regular intrinsics
8037
8038 cmpq(length, 16);
8039 jccb(Assembler::less, VECTOR8_TAIL);
8040
8041 subq(length, 16);
8042 bind(VECTOR16_LOOP);
8043 movdqu(rymm0, Address(obja, result));
8044 movdqu(rymm1, Address(objb, result));
8045 pxor(rymm0, rymm1);
8046 ptest(rymm0, rymm0);
8047 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
8048 addq(result, 16);
8049 subq(length, 16);
8050 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
8051 addq(length, 16);
8052 jcc(Assembler::equal, SAME_TILL_END);
8053 //falling through if less than 16 bytes left
8054 }
8055
8056 bind(VECTOR8_TAIL);
8057 cmpq(length, 8);
8058 jccb(Assembler::less, VECTOR4_TAIL);
8059 bind(VECTOR8_LOOP);
8060 movq(tmp1, Address(obja, result));
8061 movq(tmp2, Address(objb, result));
8062 xorq(tmp1, tmp2);
8063 testq(tmp1, tmp1);
8064 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
8065 addq(result, 8);
8066 subq(length, 8);
8067 jcc(Assembler::equal, SAME_TILL_END);
8068 //falling through if less than 8 bytes left
8069
8070 bind(VECTOR4_TAIL);
8071 cmpq(length, 4);
8072 jccb(Assembler::less, BYTES_TAIL);
8073 bind(VECTOR4_LOOP);
8074 movl(tmp1, Address(obja, result));
8075 xorl(tmp1, Address(objb, result));
8076 testl(tmp1, tmp1);
8077 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
8078 addq(result, 4);
8079 subq(length, 4);
8080 jcc(Assembler::equal, SAME_TILL_END);
8081 //falling through if less than 4 bytes left
8082
8083 bind(BYTES_TAIL);
8084 bind(BYTES_LOOP);
8085 load_unsigned_byte(tmp1, Address(obja, result));
8086 load_unsigned_byte(tmp2, Address(objb, result));
8087 xorl(tmp1, tmp2);
8088 testl(tmp1, tmp1);
8089 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8090 decq(length);
8091 jcc(Assembler::zero, SAME_TILL_END);
8092 incq(result);
8093 load_unsigned_byte(tmp1, Address(obja, result));
8094 load_unsigned_byte(tmp2, Address(objb, result));
8095 xorl(tmp1, tmp2);
8096 testl(tmp1, tmp1);
8097 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8098 decq(length);
8099 jcc(Assembler::zero, SAME_TILL_END);
8100 incq(result);
8101 load_unsigned_byte(tmp1, Address(obja, result));
8102 load_unsigned_byte(tmp2, Address(objb, result));
8103 xorl(tmp1, tmp2);
8104 testl(tmp1, tmp1);
8105 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
8106 jmp(SAME_TILL_END);
8107
8108 if (UseAVX >= 2) {
8109 bind(VECTOR32_NOT_EQUAL);
8110 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
8111 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
8112 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
8113 vpmovmskb(tmp1, rymm0);
8114 bsfq(tmp1, tmp1);
8115 addq(result, tmp1);
8116 shrq(result);
8117 jmp(DONE);
8118 }
8119
8120 bind(VECTOR16_NOT_EQUAL);
8121 if (UseAVX >= 2) {
8122 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
8123 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
8124 pxor(rymm0, rymm2);
8125 } else {
8126 pcmpeqb(rymm2, rymm2);
8127 pxor(rymm0, rymm1);
8128 pcmpeqb(rymm0, rymm1);
8129 pxor(rymm0, rymm2);
8130 }
8131 pmovmskb(tmp1, rymm0);
8132 bsfq(tmp1, tmp1);
8133 addq(result, tmp1);
8134 shrq(result);
8135 jmpb(DONE);
8136
8137 bind(VECTOR8_NOT_EQUAL);
8138 bind(VECTOR4_NOT_EQUAL);
8139 bsfq(tmp1, tmp1);
8140 shrq(tmp1, 3);
8141 addq(result, tmp1);
8142 bind(BYTES_NOT_EQUAL);
8143 shrq(result);
8144 jmpb(DONE);
8145
8146 bind(SAME_TILL_END);
8147 mov64(result, -1);
8148
8149 bind(DONE);
8150 }
8151
8152 //Helper functions for square_to_len()
8153
8154 /**
8155 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
8156 * Preserves x and z and modifies rest of the registers.
8157 */
8158 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8159 // Perform square and right shift by 1
8160 // Handle odd xlen case first, then for even xlen do the following
8161 // jlong carry = 0;
8162 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
8163 // huge_128 product = x[j:j+1] * x[j:j+1];
8164 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
8165 // z[i+2:i+3] = (jlong)(product >>> 1);
8166 // carry = (jlong)product;
8167 // }
8168
8169 xorq(tmp5, tmp5); // carry
8170 xorq(rdxReg, rdxReg);
8171 xorl(tmp1, tmp1); // index for x
8172 xorl(tmp4, tmp4); // index for z
8173
8174 Label L_first_loop, L_first_loop_exit;
8175
8176 testl(xlen, 1);
8177 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
8178
8179 // Square and right shift by 1 the odd element using 32 bit multiply
8180 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
8181 imulq(raxReg, raxReg);
8182 shrq(raxReg, 1);
8183 adcq(tmp5, 0);
8184 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
8185 incrementl(tmp1);
8186 addl(tmp4, 2);
8187
8188 // Square and right shift by 1 the rest using 64 bit multiply
8189 bind(L_first_loop);
8190 cmpptr(tmp1, xlen);
8191 jccb(Assembler::equal, L_first_loop_exit);
8192
8193 // Square
8194 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
8195 rorq(raxReg, 32); // convert big-endian to little-endian
8196 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
8197
8198 // Right shift by 1 and save carry
8199 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
8200 rcrq(rdxReg, 1);
8201 rcrq(raxReg, 1);
8202 adcq(tmp5, 0);
8203
8204 // Store result in z
8205 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
8206 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
8207
8208 // Update indices for x and z
8209 addl(tmp1, 2);
8210 addl(tmp4, 4);
8211 jmp(L_first_loop);
8212
8213 bind(L_first_loop_exit);
8214 }
8215
8216
8217 /**
8218 * Perform the following multiply add operation using BMI2 instructions
8219 * carry:sum = sum + op1*op2 + carry
8220 * op2 should be in rdx
8221 * op2 is preserved, all other registers are modified
8222 */
8223 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
8224 // assert op2 is rdx
8225 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
8226 addq(sum, carry);
8227 adcq(tmp2, 0);
8228 addq(sum, op1);
8229 adcq(tmp2, 0);
8230 movq(carry, tmp2);
8231 }
8232
8233 /**
8234 * Perform the following multiply add operation:
8235 * carry:sum = sum + op1*op2 + carry
8236 * Preserves op1, op2 and modifies rest of registers
8237 */
8238 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8239 // rdx:rax = op1 * op2
8240 movq(raxReg, op2);
8241 mulq(op1);
8242
8243 // rdx:rax = sum + carry + rdx:rax
8244 addq(sum, carry);
8245 adcq(rdxReg, 0);
8246 addq(sum, raxReg);
8247 adcq(rdxReg, 0);
8248
8249 // carry:sum = rdx:sum
8250 movq(carry, rdxReg);
8251 }
8252
8253 /**
8254 * Add 64 bit long carry into z[] with carry propagation.
8255 * Preserves z and carry register values and modifies rest of registers.
8256 *
8257 */
8258 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8259 Label L_fourth_loop, L_fourth_loop_exit;
8260
8261 movl(tmp1, 1);
8262 subl(zlen, 2);
8263 addq(Address(z, zlen, Address::times_4, 0), carry);
8264
8265 bind(L_fourth_loop);
8266 jccb(Assembler::carryClear, L_fourth_loop_exit);
8267 subl(zlen, 2);
8268 jccb(Assembler::negative, L_fourth_loop_exit);
8269 addq(Address(z, zlen, Address::times_4, 0), tmp1);
8270 jmp(L_fourth_loop);
8271 bind(L_fourth_loop_exit);
8272 }
8273
8274 /**
8275 * Shift z[] left by 1 bit.
8276 * Preserves x, len, z and zlen registers and modifies rest of the registers.
8277 *
8278 */
8279 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8280
8281 Label L_fifth_loop, L_fifth_loop_exit;
8282
8283 // Fifth loop
8284 // Perform primitiveLeftShift(z, zlen, 1)
8285
8286 const Register prev_carry = tmp1;
8287 const Register new_carry = tmp4;
8288 const Register value = tmp2;
8289 const Register zidx = tmp3;
8290
8291 // int zidx, carry;
8292 // long value;
8293 // carry = 0;
8294 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8295 // (carry:value) = (z[i] << 1) | carry ;
8296 // z[i] = value;
8297 // }
8298
8299 movl(zidx, zlen);
8300 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8301
8302 bind(L_fifth_loop);
8303 decl(zidx); // Use decl to preserve carry flag
8304 decl(zidx);
8305 jccb(Assembler::negative, L_fifth_loop_exit);
8306
8307 if (UseBMI2Instructions) {
8308 movq(value, Address(z, zidx, Address::times_4, 0));
8309 rclq(value, 1);
8310 rorxq(value, value, 32);
8311 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8312 }
8313 else {
8314 // clear new_carry
8315 xorl(new_carry, new_carry);
8316
8317 // Shift z[i] by 1, or in previous carry and save new carry
8318 movq(value, Address(z, zidx, Address::times_4, 0));
8319 shlq(value, 1);
8320 adcl(new_carry, 0);
8321
8322 orq(value, prev_carry);
8323 rorq(value, 0x20);
8324 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8325
8326 // Set previous carry = new carry
8327 movl(prev_carry, new_carry);
8328 }
8329 jmp(L_fifth_loop);
8330
8331 bind(L_fifth_loop_exit);
8332 }
8333
8334
8335 /**
8336 * Code for BigInteger::squareToLen() intrinsic
8337 *
8338 * rdi: x
8339 * rsi: len
8340 * r8: z
8341 * rcx: zlen
8342 * r12: tmp1
8343 * r13: tmp2
8344 * r14: tmp3
8345 * r15: tmp4
8346 * rbx: tmp5
8347 *
8348 */
8349 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8350
8351 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8352 push(tmp1);
8353 push(tmp2);
8354 push(tmp3);
8355 push(tmp4);
8356 push(tmp5);
8357
8358 // First loop
8359 // Store the squares, right shifted one bit (i.e., divided by 2).
8360 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8361
8362 // Add in off-diagonal sums.
8363 //
8364 // Second, third (nested) and fourth loops.
8365 // zlen +=2;
8366 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8367 // carry = 0;
8368 // long op2 = x[xidx:xidx+1];
8369 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8370 // k -= 2;
8371 // long op1 = x[j:j+1];
8372 // long sum = z[k:k+1];
8373 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8374 // z[k:k+1] = sum;
8375 // }
8376 // add_one_64(z, k, carry, tmp_regs);
8377 // }
8378
8379 const Register carry = tmp5;
8380 const Register sum = tmp3;
8381 const Register op1 = tmp4;
8382 Register op2 = tmp2;
8383
8384 push(zlen);
8385 push(len);
8386 addl(zlen,2);
8387 bind(L_second_loop);
8388 xorq(carry, carry);
8389 subl(zlen, 4);
8390 subl(len, 2);
8391 push(zlen);
8392 push(len);
8393 cmpl(len, 0);
8394 jccb(Assembler::lessEqual, L_second_loop_exit);
8395
8396 // Multiply an array by one 64 bit long.
8397 if (UseBMI2Instructions) {
8398 op2 = rdxReg;
8399 movq(op2, Address(x, len, Address::times_4, 0));
8400 rorxq(op2, op2, 32);
8401 }
8402 else {
8403 movq(op2, Address(x, len, Address::times_4, 0));
8404 rorq(op2, 32);
8405 }
8406
8407 bind(L_third_loop);
8408 decrementl(len);
8409 jccb(Assembler::negative, L_third_loop_exit);
8410 decrementl(len);
8411 jccb(Assembler::negative, L_last_x);
8412
8413 movq(op1, Address(x, len, Address::times_4, 0));
8414 rorq(op1, 32);
8415
8416 bind(L_multiply);
8417 subl(zlen, 2);
8418 movq(sum, Address(z, zlen, Address::times_4, 0));
8419
8420 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8421 if (UseBMI2Instructions) {
8422 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8423 }
8424 else {
8425 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8426 }
8427
8428 movq(Address(z, zlen, Address::times_4, 0), sum);
8429
8430 jmp(L_third_loop);
8431 bind(L_third_loop_exit);
8432
8433 // Fourth loop
8434 // Add 64 bit long carry into z with carry propagation.
8435 // Uses offsetted zlen.
8436 add_one_64(z, zlen, carry, tmp1);
8437
8438 pop(len);
8439 pop(zlen);
8440 jmp(L_second_loop);
8441
8442 // Next infrequent code is moved outside loops.
8443 bind(L_last_x);
8444 movl(op1, Address(x, 0));
8445 jmp(L_multiply);
8446
8447 bind(L_second_loop_exit);
8448 pop(len);
8449 pop(zlen);
8450 pop(len);
8451 pop(zlen);
8452
8453 // Fifth loop
8454 // Shift z left 1 bit.
8455 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8456
8457 // z[zlen-1] |= x[len-1] & 1;
8458 movl(tmp3, Address(x, len, Address::times_4, -4));
8459 andl(tmp3, 1);
8460 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8461
8462 pop(tmp5);
8463 pop(tmp4);
8464 pop(tmp3);
8465 pop(tmp2);
8466 pop(tmp1);
8467 }
8468
8469 /**
8470 * Helper function for mul_add()
8471 * Multiply the in[] by int k and add to out[] starting at offset offs using
8472 * 128 bit by 32 bit multiply and return the carry in tmp5.
8473 * Only quad int aligned length of in[] is operated on in this function.
8474 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8475 * This function preserves out, in and k registers.
8476 * len and offset point to the appropriate index in "in" & "out" correspondingly
8477 * tmp5 has the carry.
8478 * other registers are temporary and are modified.
8479 *
8480 */
8481 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8482 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8483 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8484
8485 Label L_first_loop, L_first_loop_exit;
8486
8487 movl(tmp1, len);
8488 shrl(tmp1, 2);
8489
8490 bind(L_first_loop);
8491 subl(tmp1, 1);
8492 jccb(Assembler::negative, L_first_loop_exit);
8493
8494 subl(len, 4);
8495 subl(offset, 4);
8496
8497 Register op2 = tmp2;
8498 const Register sum = tmp3;
8499 const Register op1 = tmp4;
8500 const Register carry = tmp5;
8501
8502 if (UseBMI2Instructions) {
8503 op2 = rdxReg;
8504 }
8505
8506 movq(op1, Address(in, len, Address::times_4, 8));
8507 rorq(op1, 32);
8508 movq(sum, Address(out, offset, Address::times_4, 8));
8509 rorq(sum, 32);
8510 if (UseBMI2Instructions) {
8511 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8512 }
8513 else {
8514 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8515 }
8516 // Store back in big endian from little endian
8517 rorq(sum, 0x20);
8518 movq(Address(out, offset, Address::times_4, 8), sum);
8519
8520 movq(op1, Address(in, len, Address::times_4, 0));
8521 rorq(op1, 32);
8522 movq(sum, Address(out, offset, Address::times_4, 0));
8523 rorq(sum, 32);
8524 if (UseBMI2Instructions) {
8525 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8526 }
8527 else {
8528 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8529 }
8530 // Store back in big endian from little endian
8531 rorq(sum, 0x20);
8532 movq(Address(out, offset, Address::times_4, 0), sum);
8533
8534 jmp(L_first_loop);
8535 bind(L_first_loop_exit);
8536 }
8537
8538 /**
8539 * Code for BigInteger::mulAdd() intrinsic
8540 *
8541 * rdi: out
8542 * rsi: in
8543 * r11: offs (out.length - offset)
8544 * rcx: len
8545 * r8: k
8546 * r12: tmp1
8547 * r13: tmp2
8548 * r14: tmp3
8549 * r15: tmp4
8550 * rbx: tmp5
8551 * Multiply the in[] by word k and add to out[], return the carry in rax
8552 */
8553 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8554 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8555 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8556
8557 Label L_carry, L_last_in, L_done;
8558
8559 // carry = 0;
8560 // for (int j=len-1; j >= 0; j--) {
8561 // long product = (in[j] & LONG_MASK) * kLong +
8562 // (out[offs] & LONG_MASK) + carry;
8563 // out[offs--] = (int)product;
8564 // carry = product >>> 32;
8565 // }
8566 //
8567 push(tmp1);
8568 push(tmp2);
8569 push(tmp3);
8570 push(tmp4);
8571 push(tmp5);
8572
8573 Register op2 = tmp2;
8574 const Register sum = tmp3;
8575 const Register op1 = tmp4;
8576 const Register carry = tmp5;
8577
8578 if (UseBMI2Instructions) {
8579 op2 = rdxReg;
8580 movl(op2, k);
8581 }
8582 else {
8583 movl(op2, k);
8584 }
8585
8586 xorq(carry, carry);
8587
8588 //First loop
8589
8590 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8591 //The carry is in tmp5
8592 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8593
8594 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8595 decrementl(len);
8596 jccb(Assembler::negative, L_carry);
8597 decrementl(len);
8598 jccb(Assembler::negative, L_last_in);
8599
8600 movq(op1, Address(in, len, Address::times_4, 0));
8601 rorq(op1, 32);
8602
8603 subl(offs, 2);
8604 movq(sum, Address(out, offs, Address::times_4, 0));
8605 rorq(sum, 32);
8606
8607 if (UseBMI2Instructions) {
8608 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8609 }
8610 else {
8611 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8612 }
8613
8614 // Store back in big endian from little endian
8615 rorq(sum, 0x20);
8616 movq(Address(out, offs, Address::times_4, 0), sum);
8617
8618 testl(len, len);
8619 jccb(Assembler::zero, L_carry);
8620
8621 //Multiply the last in[] entry, if any
8622 bind(L_last_in);
8623 movl(op1, Address(in, 0));
8624 movl(sum, Address(out, offs, Address::times_4, -4));
8625
8626 movl(raxReg, k);
8627 mull(op1); //tmp4 * eax -> edx:eax
8628 addl(sum, carry);
8629 adcl(rdxReg, 0);
8630 addl(sum, raxReg);
8631 adcl(rdxReg, 0);
8632 movl(carry, rdxReg);
8633
8634 movl(Address(out, offs, Address::times_4, -4), sum);
8635
8636 bind(L_carry);
8637 //return tmp5/carry as carry in rax
8638 movl(rax, carry);
8639
8640 bind(L_done);
8641 pop(tmp5);
8642 pop(tmp4);
8643 pop(tmp3);
8644 pop(tmp2);
8645 pop(tmp1);
8646 }
8647 #endif
8648
8649 /**
8650 * Emits code to update CRC-32 with a byte value according to constants in table
8651 *
8652 * @param [in,out]crc Register containing the crc.
8653 * @param [in]val Register containing the byte to fold into the CRC.
8654 * @param [in]table Register containing the table of crc constants.
8655 *
8656 * uint32_t crc;
8657 * val = crc_table[(val ^ crc) & 0xFF];
8658 * crc = val ^ (crc >> 8);
8659 *
8660 */
8661 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8662 xorl(val, crc);
8663 andl(val, 0xFF);
8664 shrl(crc, 8); // unsigned shift
8665 xorl(crc, Address(table, val, Address::times_4, 0));
8666 }
8667
8668 /**
8669 * Fold 128-bit data chunk
8670 */
8671 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8672 if (UseAVX > 0) {
8673 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8674 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8675 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8676 pxor(xcrc, xtmp);
8677 } else {
8678 movdqa(xtmp, xcrc);
8679 pclmulhdq(xtmp, xK); // [123:64]
8680 pclmulldq(xcrc, xK); // [63:0]
8681 pxor(xcrc, xtmp);
8682 movdqu(xtmp, Address(buf, offset));
8683 pxor(xcrc, xtmp);
8684 }
8685 }
8686
8687 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8688 if (UseAVX > 0) {
8689 vpclmulhdq(xtmp, xK, xcrc);
8690 vpclmulldq(xcrc, xK, xcrc);
8691 pxor(xcrc, xbuf);
8692 pxor(xcrc, xtmp);
8693 } else {
8694 movdqa(xtmp, xcrc);
8695 pclmulhdq(xtmp, xK);
8696 pclmulldq(xcrc, xK);
8697 pxor(xcrc, xbuf);
8698 pxor(xcrc, xtmp);
8699 }
8700 }
8701
8702 /**
8703 * 8-bit folds to compute 32-bit CRC
8704 *
8705 * uint64_t xcrc;
8706 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8707 */
8708 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8709 movdl(tmp, xcrc);
8710 andl(tmp, 0xFF);
8711 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8712 psrldq(xcrc, 1); // unsigned shift one byte
8713 pxor(xcrc, xtmp);
8714 }
8715
8716 /**
8717 * uint32_t crc;
8718 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8719 */
8720 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8721 movl(tmp, crc);
8722 andl(tmp, 0xFF);
8723 shrl(crc, 8);
8724 xorl(crc, Address(table, tmp, Address::times_4, 0));
8725 }
8726
8727 /**
8728 * @param crc register containing existing CRC (32-bit)
8729 * @param buf register pointing to input byte buffer (byte*)
8730 * @param len register containing number of bytes
8731 * @param table register that will contain address of CRC table
8732 * @param tmp scratch register
8733 */
8734 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8735 assert_different_registers(crc, buf, len, table, tmp, rax);
8736
8737 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8738 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8739
8740 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8741 // context for the registers used, where all instructions below are using 128-bit mode
8742 // On EVEX without VL and BW, these instructions will all be AVX.
8743 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8744 notl(crc); // ~crc
8745 cmpl(len, 16);
8746 jcc(Assembler::less, L_tail);
8747
8748 // Align buffer to 16 bytes
8749 movl(tmp, buf);
8750 andl(tmp, 0xF);
8751 jccb(Assembler::zero, L_aligned);
8752 subl(tmp, 16);
8753 addl(len, tmp);
8754
8755 align(4);
8756 BIND(L_align_loop);
8757 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8758 update_byte_crc32(crc, rax, table);
8759 increment(buf);
8760 incrementl(tmp);
8761 jccb(Assembler::less, L_align_loop);
8762
8763 BIND(L_aligned);
8764 movl(tmp, len); // save
8765 shrl(len, 4);
8766 jcc(Assembler::zero, L_tail_restore);
8767
8768 // Fold crc into first bytes of vector
8769 movdqa(xmm1, Address(buf, 0));
8770 movdl(rax, xmm1);
8771 xorl(crc, rax);
8772 if (VM_Version::supports_sse4_1()) {
8773 pinsrd(xmm1, crc, 0);
8774 } else {
8775 pinsrw(xmm1, crc, 0);
8776 shrl(crc, 16);
8777 pinsrw(xmm1, crc, 1);
8778 }
8779 addptr(buf, 16);
8780 subl(len, 4); // len > 0
8781 jcc(Assembler::less, L_fold_tail);
8782
8783 movdqa(xmm2, Address(buf, 0));
8784 movdqa(xmm3, Address(buf, 16));
8785 movdqa(xmm4, Address(buf, 32));
8786 addptr(buf, 48);
8787 subl(len, 3);
8788 jcc(Assembler::lessEqual, L_fold_512b);
8789
8790 // Fold total 512 bits of polynomial on each iteration,
8791 // 128 bits per each of 4 parallel streams.
8792 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8793
8794 align32();
8795 BIND(L_fold_512b_loop);
8796 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8797 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8798 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8799 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8800 addptr(buf, 64);
8801 subl(len, 4);
8802 jcc(Assembler::greater, L_fold_512b_loop);
8803
8804 // Fold 512 bits to 128 bits.
8805 BIND(L_fold_512b);
8806 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8807 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8808 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8809 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8810
8811 // Fold the rest of 128 bits data chunks
8812 BIND(L_fold_tail);
8813 addl(len, 3);
8814 jccb(Assembler::lessEqual, L_fold_128b);
8815 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8816
8817 BIND(L_fold_tail_loop);
8818 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8819 addptr(buf, 16);
8820 decrementl(len);
8821 jccb(Assembler::greater, L_fold_tail_loop);
8822
8823 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8824 BIND(L_fold_128b);
8825 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8826 if (UseAVX > 0) {
8827 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8828 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8829 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8830 } else {
8831 movdqa(xmm2, xmm0);
8832 pclmulqdq(xmm2, xmm1, 0x1);
8833 movdqa(xmm3, xmm0);
8834 pand(xmm3, xmm2);
8835 pclmulqdq(xmm0, xmm3, 0x1);
8836 }
8837 psrldq(xmm1, 8);
8838 psrldq(xmm2, 4);
8839 pxor(xmm0, xmm1);
8840 pxor(xmm0, xmm2);
8841
8842 // 8 8-bit folds to compute 32-bit CRC.
8843 for (int j = 0; j < 4; j++) {
8844 fold_8bit_crc32(xmm0, table, xmm1, rax);
8845 }
8846 movdl(crc, xmm0); // mov 32 bits to general register
8847 for (int j = 0; j < 4; j++) {
8848 fold_8bit_crc32(crc, table, rax);
8849 }
8850
8851 BIND(L_tail_restore);
8852 movl(len, tmp); // restore
8853 BIND(L_tail);
8854 andl(len, 0xf);
8855 jccb(Assembler::zero, L_exit);
8856
8857 // Fold the rest of bytes
8858 align(4);
8859 BIND(L_tail_loop);
8860 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8861 update_byte_crc32(crc, rax, table);
8862 increment(buf);
8863 decrementl(len);
8864 jccb(Assembler::greater, L_tail_loop);
8865
8866 BIND(L_exit);
8867 notl(crc); // ~c
8868 }
8869
8870 #ifdef _LP64
8871 // Helper function for AVX 512 CRC32
8872 // Fold 512-bit data chunks
8873 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8874 Register pos, int offset) {
8875 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8876 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8877 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8878 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8879 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8880 }
8881
8882 // Helper function for AVX 512 CRC32
8883 // Compute CRC32 for < 256B buffers
8884 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8885 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8886 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8887
8888 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8889 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8890 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8891
8892 // check if there is enough buffer to be able to fold 16B at a time
8893 cmpl(len, 32);
8894 jcc(Assembler::less, L_less_than_32);
8895
8896 // if there is, load the constants
8897 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8898 movdl(xmm0, crc); // get the initial crc value
8899 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8900 pxor(xmm7, xmm0);
8901
8902 // update the buffer pointer
8903 addl(pos, 16);
8904 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8905 subl(len, 32);
8906 jmp(L_16B_reduction_loop);
8907
8908 bind(L_less_than_32);
8909 //mov initial crc to the return value. this is necessary for zero - length buffers.
8910 movl(rax, crc);
8911 testl(len, len);
8912 jcc(Assembler::equal, L_cleanup);
8913
8914 movdl(xmm0, crc); //get the initial crc value
8915
8916 cmpl(len, 16);
8917 jcc(Assembler::equal, L_exact_16_left);
8918 jcc(Assembler::less, L_less_than_16_left);
8919
8920 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8921 pxor(xmm7, xmm0); //xor the initial crc value
8922 addl(pos, 16);
8923 subl(len, 16);
8924 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8925 jmp(L_get_last_two_xmms);
8926
8927 bind(L_less_than_16_left);
8928 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8929 pxor(xmm1, xmm1);
8930 movptr(tmp1, rsp);
8931 movdqu(Address(tmp1, 0 * 16), xmm1);
8932
8933 cmpl(len, 4);
8934 jcc(Assembler::less, L_only_less_than_4);
8935
8936 //backup the counter value
8937 movl(tmp2, len);
8938 cmpl(len, 8);
8939 jcc(Assembler::less, L_less_than_8_left);
8940
8941 //load 8 Bytes
8942 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8943 movq(Address(tmp1, 0 * 16), rax);
8944 addptr(tmp1, 8);
8945 subl(len, 8);
8946 addl(pos, 8);
8947
8948 bind(L_less_than_8_left);
8949 cmpl(len, 4);
8950 jcc(Assembler::less, L_less_than_4_left);
8951
8952 //load 4 Bytes
8953 movl(rax, Address(buf, pos, Address::times_1, 0));
8954 movl(Address(tmp1, 0 * 16), rax);
8955 addptr(tmp1, 4);
8956 subl(len, 4);
8957 addl(pos, 4);
8958
8959 bind(L_less_than_4_left);
8960 cmpl(len, 2);
8961 jcc(Assembler::less, L_less_than_2_left);
8962
8963 // load 2 Bytes
8964 movw(rax, Address(buf, pos, Address::times_1, 0));
8965 movl(Address(tmp1, 0 * 16), rax);
8966 addptr(tmp1, 2);
8967 subl(len, 2);
8968 addl(pos, 2);
8969
8970 bind(L_less_than_2_left);
8971 cmpl(len, 1);
8972 jcc(Assembler::less, L_zero_left);
8973
8974 // load 1 Byte
8975 movb(rax, Address(buf, pos, Address::times_1, 0));
8976 movb(Address(tmp1, 0 * 16), rax);
8977
8978 bind(L_zero_left);
8979 movdqu(xmm7, Address(rsp, 0));
8980 pxor(xmm7, xmm0); //xor the initial crc value
8981
8982 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8983 movdqu(xmm0, Address(rax, tmp2));
8984 pshufb(xmm7, xmm0);
8985 jmp(L_128_done);
8986
8987 bind(L_exact_16_left);
8988 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8989 pxor(xmm7, xmm0); //xor the initial crc value
8990 jmp(L_128_done);
8991
8992 bind(L_only_less_than_4);
8993 cmpl(len, 3);
8994 jcc(Assembler::less, L_only_less_than_3);
8995
8996 // load 3 Bytes
8997 movb(rax, Address(buf, pos, Address::times_1, 0));
8998 movb(Address(tmp1, 0), rax);
8999
9000 movb(rax, Address(buf, pos, Address::times_1, 1));
9001 movb(Address(tmp1, 1), rax);
9002
9003 movb(rax, Address(buf, pos, Address::times_1, 2));
9004 movb(Address(tmp1, 2), rax);
9005
9006 movdqu(xmm7, Address(rsp, 0));
9007 pxor(xmm7, xmm0); //xor the initial crc value
9008
9009 pslldq(xmm7, 0x5);
9010 jmp(L_barrett);
9011 bind(L_only_less_than_3);
9012 cmpl(len, 2);
9013 jcc(Assembler::less, L_only_less_than_2);
9014
9015 // load 2 Bytes
9016 movb(rax, Address(buf, pos, Address::times_1, 0));
9017 movb(Address(tmp1, 0), rax);
9018
9019 movb(rax, Address(buf, pos, Address::times_1, 1));
9020 movb(Address(tmp1, 1), rax);
9021
9022 movdqu(xmm7, Address(rsp, 0));
9023 pxor(xmm7, xmm0); //xor the initial crc value
9024
9025 pslldq(xmm7, 0x6);
9026 jmp(L_barrett);
9027
9028 bind(L_only_less_than_2);
9029 //load 1 Byte
9030 movb(rax, Address(buf, pos, Address::times_1, 0));
9031 movb(Address(tmp1, 0), rax);
9032
9033 movdqu(xmm7, Address(rsp, 0));
9034 pxor(xmm7, xmm0); //xor the initial crc value
9035
9036 pslldq(xmm7, 0x7);
9037 }
9038
9039 /**
9040 * Compute CRC32 using AVX512 instructions
9041 * param crc register containing existing CRC (32-bit)
9042 * param buf register pointing to input byte buffer (byte*)
9043 * param len register containing number of bytes
9044 * param table address of crc or crc32c table
9045 * param tmp1 scratch register
9046 * param tmp2 scratch register
9047 * return rax result register
9048 *
9049 * This routine is identical for crc32c with the exception of the precomputed constant
9050 * table which will be passed as the table argument. The calculation steps are
9051 * the same for both variants.
9052 */
9053 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
9054 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
9055
9056 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
9057 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
9058 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
9059 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
9060 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
9061
9062 const Register pos = r12;
9063 push(r12);
9064 subptr(rsp, 16 * 2 + 8);
9065
9066 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
9067 // context for the registers used, where all instructions below are using 128-bit mode
9068 // On EVEX without VL and BW, these instructions will all be AVX.
9069 movl(pos, 0);
9070
9071 // check if smaller than 256B
9072 cmpl(len, 256);
9073 jcc(Assembler::less, L_less_than_256);
9074
9075 // load the initial crc value
9076 movdl(xmm10, crc);
9077
9078 // receive the initial 64B data, xor the initial crc value
9079 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
9080 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
9081 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
9082 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
9083
9084 subl(len, 256);
9085 cmpl(len, 256);
9086 jcc(Assembler::less, L_fold_128_B_loop);
9087
9088 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
9089 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
9090 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
9091 subl(len, 256);
9092
9093 bind(L_fold_256_B_loop);
9094 addl(pos, 256);
9095 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
9096 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
9097 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
9098 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
9099
9100 subl(len, 256);
9101 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
9102
9103 // Fold 256 into 128
9104 addl(pos, 256);
9105 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
9106 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
9107 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
9108
9109 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
9110 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
9111 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
9112
9113 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
9114 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
9115
9116 addl(len, 128);
9117 jmp(L_fold_128_B_register);
9118
9119 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
9120 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
9121
9122 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
9123 bind(L_fold_128_B_loop);
9124 addl(pos, 128);
9125 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
9126 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
9127
9128 subl(len, 128);
9129 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
9130
9131 addl(pos, 128);
9132
9133 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
9134 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
9135 bind(L_fold_128_B_register);
9136 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
9137 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
9138 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
9139 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
9140 // save last that has no multiplicand
9141 vextracti64x2(xmm7, xmm4, 3);
9142
9143 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
9144 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
9145 // Needed later in reduction loop
9146 movdqu(xmm10, Address(table, 1 * 16));
9147 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
9148 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
9149
9150 // Swap 1,0,3,2 - 01 00 11 10
9151 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
9152 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
9153 vextracti128(xmm5, xmm8, 1);
9154 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
9155
9156 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
9157 // instead of a cmp instruction, we use the negative flag with the jl instruction
9158 addl(len, 128 - 16);
9159 jcc(Assembler::less, L_final_reduction_for_128);
9160
9161 bind(L_16B_reduction_loop);
9162 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
9163 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
9164 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
9165 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
9166 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
9167 addl(pos, 16);
9168 subl(len, 16);
9169 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
9170
9171 bind(L_final_reduction_for_128);
9172 addl(len, 16);
9173 jcc(Assembler::equal, L_128_done);
9174
9175 bind(L_get_last_two_xmms);
9176 movdqu(xmm2, xmm7);
9177 addl(pos, len);
9178 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
9179 subl(pos, len);
9180
9181 // get rid of the extra data that was loaded before
9182 // load the shift constant
9183 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
9184 movdqu(xmm0, Address(rax, len));
9185 addl(rax, len);
9186
9187 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
9188 //Change mask to 512
9189 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
9190 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
9191
9192 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
9193 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
9194 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
9195 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
9196 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
9197
9198 bind(L_128_done);
9199 // compute crc of a 128-bit value
9200 movdqu(xmm10, Address(table, 3 * 16));
9201 movdqu(xmm0, xmm7);
9202
9203 // 64b fold
9204 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
9205 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
9206 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
9207
9208 // 32b fold
9209 movdqu(xmm0, xmm7);
9210 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
9211 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
9212 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
9213 jmp(L_barrett);
9214
9215 bind(L_less_than_256);
9216 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
9217
9218 //barrett reduction
9219 bind(L_barrett);
9220 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
9221 movdqu(xmm1, xmm7);
9222 movdqu(xmm2, xmm7);
9223 movdqu(xmm10, Address(table, 4 * 16));
9224
9225 pclmulqdq(xmm7, xmm10, 0x0);
9226 pxor(xmm7, xmm2);
9227 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
9228 movdqu(xmm2, xmm7);
9229 pclmulqdq(xmm7, xmm10, 0x10);
9230 pxor(xmm7, xmm2);
9231 pxor(xmm7, xmm1);
9232 pextrd(crc, xmm7, 2);
9233
9234 bind(L_cleanup);
9235 addptr(rsp, 16 * 2 + 8);
9236 pop(r12);
9237 }
9238
9239 // S. Gueron / Information Processing Letters 112 (2012) 184
9240 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
9241 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
9242 // Output: the 64-bit carry-less product of B * CONST
9243 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
9244 Register tmp1, Register tmp2, Register tmp3) {
9245 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9246 if (n > 0) {
9247 addq(tmp3, n * 256 * 8);
9248 }
9249 // Q1 = TABLEExt[n][B & 0xFF];
9250 movl(tmp1, in);
9251 andl(tmp1, 0x000000FF);
9252 shll(tmp1, 3);
9253 addq(tmp1, tmp3);
9254 movq(tmp1, Address(tmp1, 0));
9255
9256 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9257 movl(tmp2, in);
9258 shrl(tmp2, 8);
9259 andl(tmp2, 0x000000FF);
9260 shll(tmp2, 3);
9261 addq(tmp2, tmp3);
9262 movq(tmp2, Address(tmp2, 0));
9263
9264 shlq(tmp2, 8);
9265 xorq(tmp1, tmp2);
9266
9267 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9268 movl(tmp2, in);
9269 shrl(tmp2, 16);
9270 andl(tmp2, 0x000000FF);
9271 shll(tmp2, 3);
9272 addq(tmp2, tmp3);
9273 movq(tmp2, Address(tmp2, 0));
9274
9275 shlq(tmp2, 16);
9276 xorq(tmp1, tmp2);
9277
9278 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9279 shrl(in, 24);
9280 andl(in, 0x000000FF);
9281 shll(in, 3);
9282 addq(in, tmp3);
9283 movq(in, Address(in, 0));
9284
9285 shlq(in, 24);
9286 xorq(in, tmp1);
9287 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9288 }
9289
9290 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9291 Register in_out,
9292 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9293 XMMRegister w_xtmp2,
9294 Register tmp1,
9295 Register n_tmp2, Register n_tmp3) {
9296 if (is_pclmulqdq_supported) {
9297 movdl(w_xtmp1, in_out); // modified blindly
9298
9299 movl(tmp1, const_or_pre_comp_const_index);
9300 movdl(w_xtmp2, tmp1);
9301 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9302
9303 movdq(in_out, w_xtmp1);
9304 } else {
9305 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
9306 }
9307 }
9308
9309 // Recombination Alternative 2: No bit-reflections
9310 // T1 = (CRC_A * U1) << 1
9311 // T2 = (CRC_B * U2) << 1
9312 // C1 = T1 >> 32
9313 // C2 = T2 >> 32
9314 // T1 = T1 & 0xFFFFFFFF
9315 // T2 = T2 & 0xFFFFFFFF
9316 // T1 = CRC32(0, T1)
9317 // T2 = CRC32(0, T2)
9318 // C1 = C1 ^ T1
9319 // C2 = C2 ^ T2
9320 // CRC = C1 ^ C2 ^ CRC_C
9321 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9322 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9323 Register tmp1, Register tmp2,
9324 Register n_tmp3) {
9325 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9326 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9327 shlq(in_out, 1);
9328 movl(tmp1, in_out);
9329 shrq(in_out, 32);
9330 xorl(tmp2, tmp2);
9331 crc32(tmp2, tmp1, 4);
9332 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9333 shlq(in1, 1);
9334 movl(tmp1, in1);
9335 shrq(in1, 32);
9336 xorl(tmp2, tmp2);
9337 crc32(tmp2, tmp1, 4);
9338 xorl(in1, tmp2);
9339 xorl(in_out, in1);
9340 xorl(in_out, in2);
9341 }
9342
9343 // Set N to predefined value
9344 // Subtract from a length of a buffer
9345 // execute in a loop:
9346 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9347 // for i = 1 to N do
9348 // CRC_A = CRC32(CRC_A, A[i])
9349 // CRC_B = CRC32(CRC_B, B[i])
9350 // CRC_C = CRC32(CRC_C, C[i])
9351 // end for
9352 // Recombine
9353 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9354 Register in_out1, Register in_out2, Register in_out3,
9355 Register tmp1, Register tmp2, Register tmp3,
9356 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9357 Register tmp4, Register tmp5,
9358 Register n_tmp6) {
9359 Label L_processPartitions;
9360 Label L_processPartition;
9361 Label L_exit;
9362
9363 bind(L_processPartitions);
9364 cmpl(in_out1, 3 * size);
9365 jcc(Assembler::less, L_exit);
9366 xorl(tmp1, tmp1);
9367 xorl(tmp2, tmp2);
9368 movq(tmp3, in_out2);
9369 addq(tmp3, size);
9370
9371 bind(L_processPartition);
9372 crc32(in_out3, Address(in_out2, 0), 8);
9373 crc32(tmp1, Address(in_out2, size), 8);
9374 crc32(tmp2, Address(in_out2, size * 2), 8);
9375 addq(in_out2, 8);
9376 cmpq(in_out2, tmp3);
9377 jcc(Assembler::less, L_processPartition);
9378 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9379 w_xtmp1, w_xtmp2, w_xtmp3,
9380 tmp4, tmp5,
9381 n_tmp6);
9382 addq(in_out2, 2 * size);
9383 subl(in_out1, 3 * size);
9384 jmp(L_processPartitions);
9385
9386 bind(L_exit);
9387 }
9388 #else
9389 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
9390 Register tmp1, Register tmp2, Register tmp3,
9391 XMMRegister xtmp1, XMMRegister xtmp2) {
9392 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9393 if (n > 0) {
9394 addl(tmp3, n * 256 * 8);
9395 }
9396 // Q1 = TABLEExt[n][B & 0xFF];
9397 movl(tmp1, in_out);
9398 andl(tmp1, 0x000000FF);
9399 shll(tmp1, 3);
9400 addl(tmp1, tmp3);
9401 movq(xtmp1, Address(tmp1, 0));
9402
9403 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9404 movl(tmp2, in_out);
9405 shrl(tmp2, 8);
9406 andl(tmp2, 0x000000FF);
9407 shll(tmp2, 3);
9408 addl(tmp2, tmp3);
9409 movq(xtmp2, Address(tmp2, 0));
9410
9411 psllq(xtmp2, 8);
9412 pxor(xtmp1, xtmp2);
9413
9414 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9415 movl(tmp2, in_out);
9416 shrl(tmp2, 16);
9417 andl(tmp2, 0x000000FF);
9418 shll(tmp2, 3);
9419 addl(tmp2, tmp3);
9420 movq(xtmp2, Address(tmp2, 0));
9421
9422 psllq(xtmp2, 16);
9423 pxor(xtmp1, xtmp2);
9424
9425 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9426 shrl(in_out, 24);
9427 andl(in_out, 0x000000FF);
9428 shll(in_out, 3);
9429 addl(in_out, tmp3);
9430 movq(xtmp2, Address(in_out, 0));
9431
9432 psllq(xtmp2, 24);
9433 pxor(xtmp1, xtmp2); // Result in CXMM
9434 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9435 }
9436
9437 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9438 Register in_out,
9439 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9440 XMMRegister w_xtmp2,
9441 Register tmp1,
9442 Register n_tmp2, Register n_tmp3) {
9443 if (is_pclmulqdq_supported) {
9444 movdl(w_xtmp1, in_out);
9445
9446 movl(tmp1, const_or_pre_comp_const_index);
9447 movdl(w_xtmp2, tmp1);
9448 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9449 // Keep result in XMM since GPR is 32 bit in length
9450 } else {
9451 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9452 }
9453 }
9454
9455 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9456 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9457 Register tmp1, Register tmp2,
9458 Register n_tmp3) {
9459 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9460 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9461
9462 psllq(w_xtmp1, 1);
9463 movdl(tmp1, w_xtmp1);
9464 psrlq(w_xtmp1, 32);
9465 movdl(in_out, w_xtmp1);
9466
9467 xorl(tmp2, tmp2);
9468 crc32(tmp2, tmp1, 4);
9469 xorl(in_out, tmp2);
9470
9471 psllq(w_xtmp2, 1);
9472 movdl(tmp1, w_xtmp2);
9473 psrlq(w_xtmp2, 32);
9474 movdl(in1, w_xtmp2);
9475
9476 xorl(tmp2, tmp2);
9477 crc32(tmp2, tmp1, 4);
9478 xorl(in1, tmp2);
9479 xorl(in_out, in1);
9480 xorl(in_out, in2);
9481 }
9482
9483 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9484 Register in_out1, Register in_out2, Register in_out3,
9485 Register tmp1, Register tmp2, Register tmp3,
9486 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9487 Register tmp4, Register tmp5,
9488 Register n_tmp6) {
9489 Label L_processPartitions;
9490 Label L_processPartition;
9491 Label L_exit;
9492
9493 bind(L_processPartitions);
9494 cmpl(in_out1, 3 * size);
9495 jcc(Assembler::less, L_exit);
9496 xorl(tmp1, tmp1);
9497 xorl(tmp2, tmp2);
9498 movl(tmp3, in_out2);
9499 addl(tmp3, size);
9500
9501 bind(L_processPartition);
9502 crc32(in_out3, Address(in_out2, 0), 4);
9503 crc32(tmp1, Address(in_out2, size), 4);
9504 crc32(tmp2, Address(in_out2, size*2), 4);
9505 crc32(in_out3, Address(in_out2, 0+4), 4);
9506 crc32(tmp1, Address(in_out2, size+4), 4);
9507 crc32(tmp2, Address(in_out2, size*2+4), 4);
9508 addl(in_out2, 8);
9509 cmpl(in_out2, tmp3);
9510 jcc(Assembler::less, L_processPartition);
9511
9512 push(tmp3);
9513 push(in_out1);
9514 push(in_out2);
9515 tmp4 = tmp3;
9516 tmp5 = in_out1;
9517 n_tmp6 = in_out2;
9518
9519 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9520 w_xtmp1, w_xtmp2, w_xtmp3,
9521 tmp4, tmp5,
9522 n_tmp6);
9523
9524 pop(in_out2);
9525 pop(in_out1);
9526 pop(tmp3);
9527
9528 addl(in_out2, 2 * size);
9529 subl(in_out1, 3 * size);
9530 jmp(L_processPartitions);
9531
9532 bind(L_exit);
9533 }
9534 #endif //LP64
9535
9536 #ifdef _LP64
9537 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9538 // Input: A buffer I of L bytes.
9539 // Output: the CRC32C value of the buffer.
9540 // Notations:
9541 // Write L = 24N + r, with N = floor (L/24).
9542 // r = L mod 24 (0 <= r < 24).
9543 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9544 // N quadwords, and R consists of r bytes.
9545 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9546 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9547 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9548 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9549 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9550 Register tmp1, Register tmp2, Register tmp3,
9551 Register tmp4, Register tmp5, Register tmp6,
9552 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9553 bool is_pclmulqdq_supported) {
9554 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9555 Label L_wordByWord;
9556 Label L_byteByByteProlog;
9557 Label L_byteByByte;
9558 Label L_exit;
9559
9560 if (is_pclmulqdq_supported ) {
9561 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9562 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
9563
9564 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9565 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9566
9567 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9568 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9569 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9570 } else {
9571 const_or_pre_comp_const_index[0] = 1;
9572 const_or_pre_comp_const_index[1] = 0;
9573
9574 const_or_pre_comp_const_index[2] = 3;
9575 const_or_pre_comp_const_index[3] = 2;
9576
9577 const_or_pre_comp_const_index[4] = 5;
9578 const_or_pre_comp_const_index[5] = 4;
9579 }
9580 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9581 in2, in1, in_out,
9582 tmp1, tmp2, tmp3,
9583 w_xtmp1, w_xtmp2, w_xtmp3,
9584 tmp4, tmp5,
9585 tmp6);
9586 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9587 in2, in1, in_out,
9588 tmp1, tmp2, tmp3,
9589 w_xtmp1, w_xtmp2, w_xtmp3,
9590 tmp4, tmp5,
9591 tmp6);
9592 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9593 in2, in1, in_out,
9594 tmp1, tmp2, tmp3,
9595 w_xtmp1, w_xtmp2, w_xtmp3,
9596 tmp4, tmp5,
9597 tmp6);
9598 movl(tmp1, in2);
9599 andl(tmp1, 0x00000007);
9600 negl(tmp1);
9601 addl(tmp1, in2);
9602 addq(tmp1, in1);
9603
9604 cmpq(in1, tmp1);
9605 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9606 align(16);
9607 BIND(L_wordByWord);
9608 crc32(in_out, Address(in1, 0), 8);
9609 addq(in1, 8);
9610 cmpq(in1, tmp1);
9611 jcc(Assembler::less, L_wordByWord);
9612
9613 BIND(L_byteByByteProlog);
9614 andl(in2, 0x00000007);
9615 movl(tmp2, 1);
9616
9617 cmpl(tmp2, in2);
9618 jccb(Assembler::greater, L_exit);
9619 BIND(L_byteByByte);
9620 crc32(in_out, Address(in1, 0), 1);
9621 incq(in1);
9622 incl(tmp2);
9623 cmpl(tmp2, in2);
9624 jcc(Assembler::lessEqual, L_byteByByte);
9625
9626 BIND(L_exit);
9627 }
9628 #else
9629 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9630 Register tmp1, Register tmp2, Register tmp3,
9631 Register tmp4, Register tmp5, Register tmp6,
9632 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9633 bool is_pclmulqdq_supported) {
9634 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9635 Label L_wordByWord;
9636 Label L_byteByByteProlog;
9637 Label L_byteByByte;
9638 Label L_exit;
9639
9640 if (is_pclmulqdq_supported) {
9641 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
9642 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
9643
9644 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
9645 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
9646
9647 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
9648 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
9649 } else {
9650 const_or_pre_comp_const_index[0] = 1;
9651 const_or_pre_comp_const_index[1] = 0;
9652
9653 const_or_pre_comp_const_index[2] = 3;
9654 const_or_pre_comp_const_index[3] = 2;
9655
9656 const_or_pre_comp_const_index[4] = 5;
9657 const_or_pre_comp_const_index[5] = 4;
9658 }
9659 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9660 in2, in1, in_out,
9661 tmp1, tmp2, tmp3,
9662 w_xtmp1, w_xtmp2, w_xtmp3,
9663 tmp4, tmp5,
9664 tmp6);
9665 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9666 in2, in1, in_out,
9667 tmp1, tmp2, tmp3,
9668 w_xtmp1, w_xtmp2, w_xtmp3,
9669 tmp4, tmp5,
9670 tmp6);
9671 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9672 in2, in1, in_out,
9673 tmp1, tmp2, tmp3,
9674 w_xtmp1, w_xtmp2, w_xtmp3,
9675 tmp4, tmp5,
9676 tmp6);
9677 movl(tmp1, in2);
9678 andl(tmp1, 0x00000007);
9679 negl(tmp1);
9680 addl(tmp1, in2);
9681 addl(tmp1, in1);
9682
9683 BIND(L_wordByWord);
9684 cmpl(in1, tmp1);
9685 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9686 crc32(in_out, Address(in1,0), 4);
9687 addl(in1, 4);
9688 jmp(L_wordByWord);
9689
9690 BIND(L_byteByByteProlog);
9691 andl(in2, 0x00000007);
9692 movl(tmp2, 1);
9693
9694 BIND(L_byteByByte);
9695 cmpl(tmp2, in2);
9696 jccb(Assembler::greater, L_exit);
9697 movb(tmp1, Address(in1, 0));
9698 crc32(in_out, tmp1, 1);
9699 incl(in1);
9700 incl(tmp2);
9701 jmp(L_byteByByte);
9702
9703 BIND(L_exit);
9704 }
9705 #endif // LP64
9706 #undef BIND
9707 #undef BLOCK_COMMENT
9708
9709 // Compress char[] array to byte[].
9710 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9711 // Return the array length if every element in array can be encoded,
9712 // otherwise, the index of first non-latin1 (> 0xff) character.
9713 // @IntrinsicCandidate
9714 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9715 // for (int i = 0; i < len; i++) {
9716 // char c = src[srcOff];
9717 // if (c > 0xff) {
9718 // return i; // return index of non-latin1 char
9719 // }
9720 // dst[dstOff] = (byte)c;
9721 // srcOff++;
9722 // dstOff++;
9723 // }
9724 // return len;
9725 // }
9726 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9727 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9728 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9729 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9730 Label copy_chars_loop, done, reset_sp, copy_tail;
9731
9732 // rsi: src
9733 // rdi: dst
9734 // rdx: len
9735 // rcx: tmp5
9736 // rax: result
9737
9738 // rsi holds start addr of source char[] to be compressed
9739 // rdi holds start addr of destination byte[]
9740 // rdx holds length
9741
9742 assert(len != result, "");
9743
9744 // save length for return
9745 movl(result, len);
9746
9747 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9748 VM_Version::supports_avx512vlbw() &&
9749 VM_Version::supports_bmi2()) {
9750
9751 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9752
9753 // alignment
9754 Label post_alignment;
9755
9756 // if length of the string is less than 32, handle it the old fashioned way
9757 testl(len, -32);
9758 jcc(Assembler::zero, below_threshold);
9759
9760 // First check whether a character is compressible ( <= 0xFF).
9761 // Create mask to test for Unicode chars inside zmm vector
9762 movl(tmp5, 0x00FF);
9763 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9764
9765 testl(len, -64);
9766 jccb(Assembler::zero, post_alignment);
9767
9768 movl(tmp5, dst);
9769 andl(tmp5, (32 - 1));
9770 negl(tmp5);
9771 andl(tmp5, (32 - 1));
9772
9773 // bail out when there is nothing to be done
9774 testl(tmp5, 0xFFFFFFFF);
9775 jccb(Assembler::zero, post_alignment);
9776
9777 // ~(~0 << len), where len is the # of remaining elements to process
9778 movl(len, 0xFFFFFFFF);
9779 shlxl(len, len, tmp5);
9780 notl(len);
9781 kmovdl(mask2, len);
9782 movl(len, result);
9783
9784 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9785 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9786 ktestd(mask1, mask2);
9787 jcc(Assembler::carryClear, copy_tail);
9788
9789 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9790
9791 addptr(src, tmp5);
9792 addptr(src, tmp5);
9793 addptr(dst, tmp5);
9794 subl(len, tmp5);
9795
9796 bind(post_alignment);
9797 // end of alignment
9798
9799 movl(tmp5, len);
9800 andl(tmp5, (32 - 1)); // tail count (in chars)
9801 andl(len, ~(32 - 1)); // vector count (in chars)
9802 jccb(Assembler::zero, copy_loop_tail);
9803
9804 lea(src, Address(src, len, Address::times_2));
9805 lea(dst, Address(dst, len, Address::times_1));
9806 negptr(len);
9807
9808 bind(copy_32_loop);
9809 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9810 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9811 kortestdl(mask1, mask1);
9812 jccb(Assembler::carryClear, reset_for_copy_tail);
9813
9814 // All elements in current processed chunk are valid candidates for
9815 // compression. Write a truncated byte elements to the memory.
9816 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9817 addptr(len, 32);
9818 jccb(Assembler::notZero, copy_32_loop);
9819
9820 bind(copy_loop_tail);
9821 // bail out when there is nothing to be done
9822 testl(tmp5, 0xFFFFFFFF);
9823 jcc(Assembler::zero, done);
9824
9825 movl(len, tmp5);
9826
9827 // ~(~0 << len), where len is the # of remaining elements to process
9828 movl(tmp5, 0xFFFFFFFF);
9829 shlxl(tmp5, tmp5, len);
9830 notl(tmp5);
9831
9832 kmovdl(mask2, tmp5);
9833
9834 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9835 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9836 ktestd(mask1, mask2);
9837 jcc(Assembler::carryClear, copy_tail);
9838
9839 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9840 jmp(done);
9841
9842 bind(reset_for_copy_tail);
9843 lea(src, Address(src, tmp5, Address::times_2));
9844 lea(dst, Address(dst, tmp5, Address::times_1));
9845 subptr(len, tmp5);
9846 jmp(copy_chars_loop);
9847
9848 bind(below_threshold);
9849 }
9850
9851 if (UseSSE42Intrinsics) {
9852 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9853
9854 // vectored compression
9855 testl(len, 0xfffffff8);
9856 jcc(Assembler::zero, copy_tail);
9857
9858 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9859 movdl(tmp1Reg, tmp5);
9860 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9861
9862 andl(len, 0xfffffff0);
9863 jccb(Assembler::zero, copy_16);
9864
9865 // compress 16 chars per iter
9866 pxor(tmp4Reg, tmp4Reg);
9867
9868 lea(src, Address(src, len, Address::times_2));
9869 lea(dst, Address(dst, len, Address::times_1));
9870 negptr(len);
9871
9872 bind(copy_32_loop);
9873 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9874 por(tmp4Reg, tmp2Reg);
9875 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9876 por(tmp4Reg, tmp3Reg);
9877 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9878 jccb(Assembler::notZero, reset_for_copy_tail);
9879 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9880 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9881 addptr(len, 16);
9882 jccb(Assembler::notZero, copy_32_loop);
9883
9884 // compress next vector of 8 chars (if any)
9885 bind(copy_16);
9886 // len = 0
9887 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9888 jccb(Assembler::zero, copy_tail_sse);
9889
9890 pxor(tmp3Reg, tmp3Reg);
9891
9892 movdqu(tmp2Reg, Address(src, 0));
9893 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9894 jccb(Assembler::notZero, reset_for_copy_tail);
9895 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9896 movq(Address(dst, 0), tmp2Reg);
9897 addptr(src, 16);
9898 addptr(dst, 8);
9899 jmpb(copy_tail_sse);
9900
9901 bind(reset_for_copy_tail);
9902 movl(tmp5, result);
9903 andl(tmp5, 0x0000000f);
9904 lea(src, Address(src, tmp5, Address::times_2));
9905 lea(dst, Address(dst, tmp5, Address::times_1));
9906 subptr(len, tmp5);
9907 jmpb(copy_chars_loop);
9908
9909 bind(copy_tail_sse);
9910 movl(len, result);
9911 andl(len, 0x00000007); // tail count (in chars)
9912 }
9913 // compress 1 char per iter
9914 bind(copy_tail);
9915 testl(len, len);
9916 jccb(Assembler::zero, done);
9917 lea(src, Address(src, len, Address::times_2));
9918 lea(dst, Address(dst, len, Address::times_1));
9919 negptr(len);
9920
9921 bind(copy_chars_loop);
9922 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9923 testl(tmp5, 0xff00); // check if Unicode char
9924 jccb(Assembler::notZero, reset_sp);
9925 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9926 increment(len);
9927 jccb(Assembler::notZero, copy_chars_loop);
9928
9929 // add len then return (len will be zero if compress succeeded, otherwise negative)
9930 bind(reset_sp);
9931 addl(result, len);
9932
9933 bind(done);
9934 }
9935
9936 // Inflate byte[] array to char[].
9937 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9938 // @IntrinsicCandidate
9939 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9940 // for (int i = 0; i < len; i++) {
9941 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9942 // }
9943 // }
9944 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9945 XMMRegister tmp1, Register tmp2, KRegister mask) {
9946 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9947 // rsi: src
9948 // rdi: dst
9949 // rdx: len
9950 // rcx: tmp2
9951
9952 // rsi holds start addr of source byte[] to be inflated
9953 // rdi holds start addr of destination char[]
9954 // rdx holds length
9955 assert_different_registers(src, dst, len, tmp2);
9956 movl(tmp2, len);
9957 if ((UseAVX > 2) && // AVX512
9958 VM_Version::supports_avx512vlbw() &&
9959 VM_Version::supports_bmi2()) {
9960
9961 Label copy_32_loop, copy_tail;
9962 Register tmp3_aliased = len;
9963
9964 // if length of the string is less than 16, handle it in an old fashioned way
9965 testl(len, -16);
9966 jcc(Assembler::zero, below_threshold);
9967
9968 testl(len, -1 * AVX3Threshold);
9969 jcc(Assembler::zero, avx3_threshold);
9970
9971 // In order to use only one arithmetic operation for the main loop we use
9972 // this pre-calculation
9973 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9974 andl(len, -32); // vector count
9975 jccb(Assembler::zero, copy_tail);
9976
9977 lea(src, Address(src, len, Address::times_1));
9978 lea(dst, Address(dst, len, Address::times_2));
9979 negptr(len);
9980
9981
9982 // inflate 32 chars per iter
9983 bind(copy_32_loop);
9984 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9985 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9986 addptr(len, 32);
9987 jcc(Assembler::notZero, copy_32_loop);
9988
9989 bind(copy_tail);
9990 // bail out when there is nothing to be done
9991 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9992 jcc(Assembler::zero, done);
9993
9994 // ~(~0 << length), where length is the # of remaining elements to process
9995 movl(tmp3_aliased, -1);
9996 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9997 notl(tmp3_aliased);
9998 kmovdl(mask, tmp3_aliased);
9999 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
10000 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
10001
10002 jmp(done);
10003 bind(avx3_threshold);
10004 }
10005 if (UseSSE42Intrinsics) {
10006 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
10007
10008 if (UseAVX > 1) {
10009 andl(tmp2, (16 - 1));
10010 andl(len, -16);
10011 jccb(Assembler::zero, copy_new_tail);
10012 } else {
10013 andl(tmp2, 0x00000007); // tail count (in chars)
10014 andl(len, 0xfffffff8); // vector count (in chars)
10015 jccb(Assembler::zero, copy_tail);
10016 }
10017
10018 // vectored inflation
10019 lea(src, Address(src, len, Address::times_1));
10020 lea(dst, Address(dst, len, Address::times_2));
10021 negptr(len);
10022
10023 if (UseAVX > 1) {
10024 bind(copy_16_loop);
10025 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
10026 vmovdqu(Address(dst, len, Address::times_2), tmp1);
10027 addptr(len, 16);
10028 jcc(Assembler::notZero, copy_16_loop);
10029
10030 bind(below_threshold);
10031 bind(copy_new_tail);
10032 movl(len, tmp2);
10033 andl(tmp2, 0x00000007);
10034 andl(len, 0xFFFFFFF8);
10035 jccb(Assembler::zero, copy_tail);
10036
10037 pmovzxbw(tmp1, Address(src, 0));
10038 movdqu(Address(dst, 0), tmp1);
10039 addptr(src, 8);
10040 addptr(dst, 2 * 8);
10041
10042 jmp(copy_tail, true);
10043 }
10044
10045 // inflate 8 chars per iter
10046 bind(copy_8_loop);
10047 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
10048 movdqu(Address(dst, len, Address::times_2), tmp1);
10049 addptr(len, 8);
10050 jcc(Assembler::notZero, copy_8_loop);
10051
10052 bind(copy_tail);
10053 movl(len, tmp2);
10054
10055 cmpl(len, 4);
10056 jccb(Assembler::less, copy_bytes);
10057
10058 movdl(tmp1, Address(src, 0)); // load 4 byte chars
10059 pmovzxbw(tmp1, tmp1);
10060 movq(Address(dst, 0), tmp1);
10061 subptr(len, 4);
10062 addptr(src, 4);
10063 addptr(dst, 8);
10064
10065 bind(copy_bytes);
10066 } else {
10067 bind(below_threshold);
10068 }
10069
10070 testl(len, len);
10071 jccb(Assembler::zero, done);
10072 lea(src, Address(src, len, Address::times_1));
10073 lea(dst, Address(dst, len, Address::times_2));
10074 negptr(len);
10075
10076 // inflate 1 char per iter
10077 bind(copy_chars_loop);
10078 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
10079 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
10080 increment(len);
10081 jcc(Assembler::notZero, copy_chars_loop);
10082
10083 bind(done);
10084 }
10085
10086
10087 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
10088 switch(type) {
10089 case T_BYTE:
10090 case T_BOOLEAN:
10091 evmovdqub(dst, kmask, src, merge, vector_len);
10092 break;
10093 case T_CHAR:
10094 case T_SHORT:
10095 evmovdquw(dst, kmask, src, merge, vector_len);
10096 break;
10097 case T_INT:
10098 case T_FLOAT:
10099 evmovdqul(dst, kmask, src, merge, vector_len);
10100 break;
10101 case T_LONG:
10102 case T_DOUBLE:
10103 evmovdquq(dst, kmask, src, merge, vector_len);
10104 break;
10105 default:
10106 fatal("Unexpected type argument %s", type2name(type));
10107 break;
10108 }
10109 }
10110
10111 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
10112 switch(type) {
10113 case T_BYTE:
10114 case T_BOOLEAN:
10115 evmovdqub(dst, kmask, src, merge, vector_len);
10116 break;
10117 case T_CHAR:
10118 case T_SHORT:
10119 evmovdquw(dst, kmask, src, merge, vector_len);
10120 break;
10121 case T_INT:
10122 case T_FLOAT:
10123 evmovdqul(dst, kmask, src, merge, vector_len);
10124 break;
10125 case T_LONG:
10126 case T_DOUBLE:
10127 evmovdquq(dst, kmask, src, merge, vector_len);
10128 break;
10129 default:
10130 fatal("Unexpected type argument %s", type2name(type));
10131 break;
10132 }
10133 }
10134
10135 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
10136 switch(masklen) {
10137 case 2:
10138 knotbl(dst, src);
10139 movl(rtmp, 3);
10140 kmovbl(ktmp, rtmp);
10141 kandbl(dst, ktmp, dst);
10142 break;
10143 case 4:
10144 knotbl(dst, src);
10145 movl(rtmp, 15);
10146 kmovbl(ktmp, rtmp);
10147 kandbl(dst, ktmp, dst);
10148 break;
10149 case 8:
10150 knotbl(dst, src);
10151 break;
10152 case 16:
10153 knotwl(dst, src);
10154 break;
10155 case 32:
10156 knotdl(dst, src);
10157 break;
10158 case 64:
10159 knotql(dst, src);
10160 break;
10161 default:
10162 fatal("Unexpected vector length %d", masklen);
10163 break;
10164 }
10165 }
10166
10167 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
10168 switch(type) {
10169 case T_BOOLEAN:
10170 case T_BYTE:
10171 kandbl(dst, src1, src2);
10172 break;
10173 case T_CHAR:
10174 case T_SHORT:
10175 kandwl(dst, src1, src2);
10176 break;
10177 case T_INT:
10178 case T_FLOAT:
10179 kanddl(dst, src1, src2);
10180 break;
10181 case T_LONG:
10182 case T_DOUBLE:
10183 kandql(dst, src1, src2);
10184 break;
10185 default:
10186 fatal("Unexpected type argument %s", type2name(type));
10187 break;
10188 }
10189 }
10190
10191 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
10192 switch(type) {
10193 case T_BOOLEAN:
10194 case T_BYTE:
10195 korbl(dst, src1, src2);
10196 break;
10197 case T_CHAR:
10198 case T_SHORT:
10199 korwl(dst, src1, src2);
10200 break;
10201 case T_INT:
10202 case T_FLOAT:
10203 kordl(dst, src1, src2);
10204 break;
10205 case T_LONG:
10206 case T_DOUBLE:
10207 korql(dst, src1, src2);
10208 break;
10209 default:
10210 fatal("Unexpected type argument %s", type2name(type));
10211 break;
10212 }
10213 }
10214
10215 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
10216 switch(type) {
10217 case T_BOOLEAN:
10218 case T_BYTE:
10219 kxorbl(dst, src1, src2);
10220 break;
10221 case T_CHAR:
10222 case T_SHORT:
10223 kxorwl(dst, src1, src2);
10224 break;
10225 case T_INT:
10226 case T_FLOAT:
10227 kxordl(dst, src1, src2);
10228 break;
10229 case T_LONG:
10230 case T_DOUBLE:
10231 kxorql(dst, src1, src2);
10232 break;
10233 default:
10234 fatal("Unexpected type argument %s", type2name(type));
10235 break;
10236 }
10237 }
10238
10239 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10240 switch(type) {
10241 case T_BOOLEAN:
10242 case T_BYTE:
10243 evpermb(dst, mask, nds, src, merge, vector_len); break;
10244 case T_CHAR:
10245 case T_SHORT:
10246 evpermw(dst, mask, nds, src, merge, vector_len); break;
10247 case T_INT:
10248 case T_FLOAT:
10249 evpermd(dst, mask, nds, src, merge, vector_len); break;
10250 case T_LONG:
10251 case T_DOUBLE:
10252 evpermq(dst, mask, nds, src, merge, vector_len); break;
10253 default:
10254 fatal("Unexpected type argument %s", type2name(type)); break;
10255 }
10256 }
10257
10258 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10259 switch(type) {
10260 case T_BOOLEAN:
10261 case T_BYTE:
10262 evpermb(dst, mask, nds, src, merge, vector_len); break;
10263 case T_CHAR:
10264 case T_SHORT:
10265 evpermw(dst, mask, nds, src, merge, vector_len); break;
10266 case T_INT:
10267 case T_FLOAT:
10268 evpermd(dst, mask, nds, src, merge, vector_len); break;
10269 case T_LONG:
10270 case T_DOUBLE:
10271 evpermq(dst, mask, nds, src, merge, vector_len); break;
10272 default:
10273 fatal("Unexpected type argument %s", type2name(type)); break;
10274 }
10275 }
10276
10277 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10278 switch(type) {
10279 case T_BYTE:
10280 evpminsb(dst, mask, nds, src, merge, vector_len); break;
10281 case T_SHORT:
10282 evpminsw(dst, mask, nds, src, merge, vector_len); break;
10283 case T_INT:
10284 evpminsd(dst, mask, nds, src, merge, vector_len); break;
10285 case T_LONG:
10286 evpminsq(dst, mask, nds, src, merge, vector_len); break;
10287 default:
10288 fatal("Unexpected type argument %s", type2name(type)); break;
10289 }
10290 }
10291
10292 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10293 switch(type) {
10294 case T_BYTE:
10295 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
10296 case T_SHORT:
10297 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
10298 case T_INT:
10299 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
10300 case T_LONG:
10301 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
10302 default:
10303 fatal("Unexpected type argument %s", type2name(type)); break;
10304 }
10305 }
10306
10307 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10308 switch(type) {
10309 case T_BYTE:
10310 evpminsb(dst, mask, nds, src, merge, vector_len); break;
10311 case T_SHORT:
10312 evpminsw(dst, mask, nds, src, merge, vector_len); break;
10313 case T_INT:
10314 evpminsd(dst, mask, nds, src, merge, vector_len); break;
10315 case T_LONG:
10316 evpminsq(dst, mask, nds, src, merge, vector_len); break;
10317 default:
10318 fatal("Unexpected type argument %s", type2name(type)); break;
10319 }
10320 }
10321
10322 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10323 switch(type) {
10324 case T_BYTE:
10325 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
10326 case T_SHORT:
10327 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
10328 case T_INT:
10329 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
10330 case T_LONG:
10331 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
10332 default:
10333 fatal("Unexpected type argument %s", type2name(type)); break;
10334 }
10335 }
10336
10337 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10338 switch(type) {
10339 case T_INT:
10340 evpxord(dst, mask, nds, src, merge, vector_len); break;
10341 case T_LONG:
10342 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10343 default:
10344 fatal("Unexpected type argument %s", type2name(type)); break;
10345 }
10346 }
10347
10348 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10349 switch(type) {
10350 case T_INT:
10351 evpxord(dst, mask, nds, src, merge, vector_len); break;
10352 case T_LONG:
10353 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10354 default:
10355 fatal("Unexpected type argument %s", type2name(type)); break;
10356 }
10357 }
10358
10359 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10360 switch(type) {
10361 case T_INT:
10362 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10363 case T_LONG:
10364 evporq(dst, mask, nds, src, merge, vector_len); break;
10365 default:
10366 fatal("Unexpected type argument %s", type2name(type)); break;
10367 }
10368 }
10369
10370 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10371 switch(type) {
10372 case T_INT:
10373 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10374 case T_LONG:
10375 evporq(dst, mask, nds, src, merge, vector_len); break;
10376 default:
10377 fatal("Unexpected type argument %s", type2name(type)); break;
10378 }
10379 }
10380
10381 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10382 switch(type) {
10383 case T_INT:
10384 evpandd(dst, mask, nds, src, merge, vector_len); break;
10385 case T_LONG:
10386 evpandq(dst, mask, nds, src, merge, vector_len); break;
10387 default:
10388 fatal("Unexpected type argument %s", type2name(type)); break;
10389 }
10390 }
10391
10392 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10393 switch(type) {
10394 case T_INT:
10395 evpandd(dst, mask, nds, src, merge, vector_len); break;
10396 case T_LONG:
10397 evpandq(dst, mask, nds, src, merge, vector_len); break;
10398 default:
10399 fatal("Unexpected type argument %s", type2name(type)); break;
10400 }
10401 }
10402
10403 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
10404 switch(masklen) {
10405 case 8:
10406 kortestbl(src1, src2);
10407 break;
10408 case 16:
10409 kortestwl(src1, src2);
10410 break;
10411 case 32:
10412 kortestdl(src1, src2);
10413 break;
10414 case 64:
10415 kortestql(src1, src2);
10416 break;
10417 default:
10418 fatal("Unexpected mask length %d", masklen);
10419 break;
10420 }
10421 }
10422
10423
10424 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
10425 switch(masklen) {
10426 case 8:
10427 ktestbl(src1, src2);
10428 break;
10429 case 16:
10430 ktestwl(src1, src2);
10431 break;
10432 case 32:
10433 ktestdl(src1, src2);
10434 break;
10435 case 64:
10436 ktestql(src1, src2);
10437 break;
10438 default:
10439 fatal("Unexpected mask length %d", masklen);
10440 break;
10441 }
10442 }
10443
10444 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10445 switch(type) {
10446 case T_INT:
10447 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10448 case T_LONG:
10449 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10450 default:
10451 fatal("Unexpected type argument %s", type2name(type)); break;
10452 break;
10453 }
10454 }
10455
10456 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10457 switch(type) {
10458 case T_INT:
10459 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10460 case T_LONG:
10461 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10462 default:
10463 fatal("Unexpected type argument %s", type2name(type)); break;
10464 }
10465 }
10466
10467 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10468 switch(type) {
10469 case T_INT:
10470 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10471 case T_LONG:
10472 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10473 default:
10474 fatal("Unexpected type argument %s", type2name(type)); break;
10475 }
10476 }
10477
10478 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10479 switch(type) {
10480 case T_INT:
10481 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10482 case T_LONG:
10483 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10484 default:
10485 fatal("Unexpected type argument %s", type2name(type)); break;
10486 }
10487 }
10488
10489 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10490 assert(rscratch != noreg || always_reachable(src), "missing");
10491
10492 if (reachable(src)) {
10493 evpandq(dst, nds, as_Address(src), vector_len);
10494 } else {
10495 lea(rscratch, src);
10496 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10497 }
10498 }
10499
10500 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10501 assert(rscratch != noreg || always_reachable(src), "missing");
10502
10503 if (reachable(src)) {
10504 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10505 } else {
10506 lea(rscratch, src);
10507 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10508 }
10509 }
10510
10511 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10512 assert(rscratch != noreg || always_reachable(src), "missing");
10513
10514 if (reachable(src)) {
10515 evporq(dst, nds, as_Address(src), vector_len);
10516 } else {
10517 lea(rscratch, src);
10518 evporq(dst, nds, Address(rscratch, 0), vector_len);
10519 }
10520 }
10521
10522 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10523 assert(rscratch != noreg || always_reachable(src), "missing");
10524
10525 if (reachable(src)) {
10526 vpshufb(dst, nds, as_Address(src), vector_len);
10527 } else {
10528 lea(rscratch, src);
10529 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10530 }
10531 }
10532
10533 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10534 assert(rscratch != noreg || always_reachable(src), "missing");
10535
10536 if (reachable(src)) {
10537 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10538 } else {
10539 lea(rscratch, src);
10540 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10541 }
10542 }
10543
10544 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10545 assert(rscratch != noreg || always_reachable(src3), "missing");
10546
10547 if (reachable(src3)) {
10548 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10549 } else {
10550 lea(rscratch, src3);
10551 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10552 }
10553 }
10554
10555 #if COMPILER2_OR_JVMCI
10556
10557 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10558 Register length, Register temp, int vec_enc) {
10559 // Computing mask for predicated vector store.
10560 movptr(temp, -1);
10561 bzhiq(temp, temp, length);
10562 kmov(mask, temp);
10563 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10564 }
10565
10566 // Set memory operation for length "less than" 64 bytes.
10567 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10568 XMMRegister xmm, KRegister mask, Register length,
10569 Register temp, bool use64byteVector) {
10570 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10571 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10572 if (!use64byteVector) {
10573 fill32(dst, disp, xmm);
10574 subptr(length, 32 >> shift);
10575 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10576 } else {
10577 assert(MaxVectorSize == 64, "vector length != 64");
10578 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10579 }
10580 }
10581
10582
10583 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10584 XMMRegister xmm, KRegister mask, Register length,
10585 Register temp) {
10586 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10587 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10588 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10589 }
10590
10591
10592 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10593 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10594 vmovdqu(dst, xmm);
10595 }
10596
10597 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10598 fill32(Address(dst, disp), xmm);
10599 }
10600
10601 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10602 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10603 if (!use64byteVector) {
10604 fill32(dst, xmm);
10605 fill32(dst.plus_disp(32), xmm);
10606 } else {
10607 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10608 }
10609 }
10610
10611 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10612 fill64(Address(dst, disp), xmm, use64byteVector);
10613 }
10614
10615 #ifdef _LP64
10616 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10617 Register count, Register rtmp, XMMRegister xtmp) {
10618 Label L_exit;
10619 Label L_fill_start;
10620 Label L_fill_64_bytes;
10621 Label L_fill_96_bytes;
10622 Label L_fill_128_bytes;
10623 Label L_fill_128_bytes_loop;
10624 Label L_fill_128_loop_header;
10625 Label L_fill_128_bytes_loop_header;
10626 Label L_fill_128_bytes_loop_pre_header;
10627 Label L_fill_zmm_sequence;
10628
10629 int shift = -1;
10630 int avx3threshold = VM_Version::avx3_threshold();
10631 switch(type) {
10632 case T_BYTE: shift = 0;
10633 break;
10634 case T_SHORT: shift = 1;
10635 break;
10636 case T_INT: shift = 2;
10637 break;
10638 /* Uncomment when LONG fill stubs are supported.
10639 case T_LONG: shift = 3;
10640 break;
10641 */
10642 default:
10643 fatal("Unhandled type: %s\n", type2name(type));
10644 }
10645
10646 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
10647
10648 if (MaxVectorSize == 64) {
10649 cmpq(count, avx3threshold >> shift);
10650 jcc(Assembler::greater, L_fill_zmm_sequence);
10651 }
10652
10653 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10654
10655 bind(L_fill_start);
10656
10657 cmpq(count, 32 >> shift);
10658 jccb(Assembler::greater, L_fill_64_bytes);
10659 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10660 jmp(L_exit);
10661
10662 bind(L_fill_64_bytes);
10663 cmpq(count, 64 >> shift);
10664 jccb(Assembler::greater, L_fill_96_bytes);
10665 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10666 jmp(L_exit);
10667
10668 bind(L_fill_96_bytes);
10669 cmpq(count, 96 >> shift);
10670 jccb(Assembler::greater, L_fill_128_bytes);
10671 fill64(to, 0, xtmp);
10672 subq(count, 64 >> shift);
10673 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10674 jmp(L_exit);
10675
10676 bind(L_fill_128_bytes);
10677 cmpq(count, 128 >> shift);
10678 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10679 fill64(to, 0, xtmp);
10680 fill32(to, 64, xtmp);
10681 subq(count, 96 >> shift);
10682 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10683 jmp(L_exit);
10684
10685 bind(L_fill_128_bytes_loop_pre_header);
10686 {
10687 mov(rtmp, to);
10688 andq(rtmp, 31);
10689 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10690 negq(rtmp);
10691 addq(rtmp, 32);
10692 mov64(r8, -1L);
10693 bzhiq(r8, r8, rtmp);
10694 kmovql(k2, r8);
10695 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10696 addq(to, rtmp);
10697 shrq(rtmp, shift);
10698 subq(count, rtmp);
10699 }
10700
10701 cmpq(count, 128 >> shift);
10702 jcc(Assembler::less, L_fill_start);
10703
10704 bind(L_fill_128_bytes_loop_header);
10705 subq(count, 128 >> shift);
10706
10707 align32();
10708 bind(L_fill_128_bytes_loop);
10709 fill64(to, 0, xtmp);
10710 fill64(to, 64, xtmp);
10711 addq(to, 128);
10712 subq(count, 128 >> shift);
10713 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10714
10715 addq(count, 128 >> shift);
10716 jcc(Assembler::zero, L_exit);
10717 jmp(L_fill_start);
10718 }
10719
10720 if (MaxVectorSize == 64) {
10721 // Sequence using 64 byte ZMM register.
10722 Label L_fill_128_bytes_zmm;
10723 Label L_fill_192_bytes_zmm;
10724 Label L_fill_192_bytes_loop_zmm;
10725 Label L_fill_192_bytes_loop_header_zmm;
10726 Label L_fill_192_bytes_loop_pre_header_zmm;
10727 Label L_fill_start_zmm_sequence;
10728
10729 bind(L_fill_zmm_sequence);
10730 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10731
10732 bind(L_fill_start_zmm_sequence);
10733 cmpq(count, 64 >> shift);
10734 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10735 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10736 jmp(L_exit);
10737
10738 bind(L_fill_128_bytes_zmm);
10739 cmpq(count, 128 >> shift);
10740 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10741 fill64(to, 0, xtmp, true);
10742 subq(count, 64 >> shift);
10743 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10744 jmp(L_exit);
10745
10746 bind(L_fill_192_bytes_zmm);
10747 cmpq(count, 192 >> shift);
10748 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10749 fill64(to, 0, xtmp, true);
10750 fill64(to, 64, xtmp, true);
10751 subq(count, 128 >> shift);
10752 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10753 jmp(L_exit);
10754
10755 bind(L_fill_192_bytes_loop_pre_header_zmm);
10756 {
10757 movq(rtmp, to);
10758 andq(rtmp, 63);
10759 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10760 negq(rtmp);
10761 addq(rtmp, 64);
10762 mov64(r8, -1L);
10763 bzhiq(r8, r8, rtmp);
10764 kmovql(k2, r8);
10765 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10766 addq(to, rtmp);
10767 shrq(rtmp, shift);
10768 subq(count, rtmp);
10769 }
10770
10771 cmpq(count, 192 >> shift);
10772 jcc(Assembler::less, L_fill_start_zmm_sequence);
10773
10774 bind(L_fill_192_bytes_loop_header_zmm);
10775 subq(count, 192 >> shift);
10776
10777 align32();
10778 bind(L_fill_192_bytes_loop_zmm);
10779 fill64(to, 0, xtmp, true);
10780 fill64(to, 64, xtmp, true);
10781 fill64(to, 128, xtmp, true);
10782 addq(to, 192);
10783 subq(count, 192 >> shift);
10784 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10785
10786 addq(count, 192 >> shift);
10787 jcc(Assembler::zero, L_exit);
10788 jmp(L_fill_start_zmm_sequence);
10789 }
10790 bind(L_exit);
10791 }
10792 #endif
10793 #endif //COMPILER2_OR_JVMCI
10794
10795
10796 #ifdef _LP64
10797 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10798 Label done;
10799 cvttss2sil(dst, src);
10800 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10801 cmpl(dst, 0x80000000); // float_sign_flip
10802 jccb(Assembler::notEqual, done);
10803 subptr(rsp, 8);
10804 movflt(Address(rsp, 0), src);
10805 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10806 pop(dst);
10807 bind(done);
10808 }
10809
10810 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10811 Label done;
10812 cvttsd2sil(dst, src);
10813 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10814 cmpl(dst, 0x80000000); // float_sign_flip
10815 jccb(Assembler::notEqual, done);
10816 subptr(rsp, 8);
10817 movdbl(Address(rsp, 0), src);
10818 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10819 pop(dst);
10820 bind(done);
10821 }
10822
10823 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10824 Label done;
10825 cvttss2siq(dst, src);
10826 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10827 jccb(Assembler::notEqual, done);
10828 subptr(rsp, 8);
10829 movflt(Address(rsp, 0), src);
10830 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10831 pop(dst);
10832 bind(done);
10833 }
10834
10835 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10836 // Following code is line by line assembly translation rounding algorithm.
10837 // Please refer to java.lang.Math.round(float) algorithm for details.
10838 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10839 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10840 const int32_t FloatConsts_EXP_BIAS = 127;
10841 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10842 const int32_t MINUS_32 = 0xFFFFFFE0;
10843 Label L_special_case, L_block1, L_exit;
10844 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10845 movdl(dst, src);
10846 andl(dst, rtmp);
10847 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10848 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10849 subl(rtmp, dst);
10850 movl(rcx, rtmp);
10851 movl(dst, MINUS_32);
10852 testl(rtmp, dst);
10853 jccb(Assembler::notEqual, L_special_case);
10854 movdl(dst, src);
10855 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10856 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10857 movdl(rtmp, src);
10858 testl(rtmp, rtmp);
10859 jccb(Assembler::greaterEqual, L_block1);
10860 negl(dst);
10861 bind(L_block1);
10862 sarl(dst);
10863 addl(dst, 0x1);
10864 sarl(dst, 0x1);
10865 jmp(L_exit);
10866 bind(L_special_case);
10867 convert_f2i(dst, src);
10868 bind(L_exit);
10869 }
10870
10871 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10872 // Following code is line by line assembly translation rounding algorithm.
10873 // Please refer to java.lang.Math.round(double) algorithm for details.
10874 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10875 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10876 const int64_t DoubleConsts_EXP_BIAS = 1023;
10877 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10878 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10879 Label L_special_case, L_block1, L_exit;
10880 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10881 movq(dst, src);
10882 andq(dst, rtmp);
10883 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10884 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10885 subq(rtmp, dst);
10886 movq(rcx, rtmp);
10887 mov64(dst, MINUS_64);
10888 testq(rtmp, dst);
10889 jccb(Assembler::notEqual, L_special_case);
10890 movq(dst, src);
10891 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10892 andq(dst, rtmp);
10893 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10894 orq(dst, rtmp);
10895 movq(rtmp, src);
10896 testq(rtmp, rtmp);
10897 jccb(Assembler::greaterEqual, L_block1);
10898 negq(dst);
10899 bind(L_block1);
10900 sarq(dst);
10901 addq(dst, 0x1);
10902 sarq(dst, 0x1);
10903 jmp(L_exit);
10904 bind(L_special_case);
10905 convert_d2l(dst, src);
10906 bind(L_exit);
10907 }
10908
10909 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10910 Label done;
10911 cvttsd2siq(dst, src);
10912 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10913 jccb(Assembler::notEqual, done);
10914 subptr(rsp, 8);
10915 movdbl(Address(rsp, 0), src);
10916 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10917 pop(dst);
10918 bind(done);
10919 }
10920
10921 void MacroAssembler::cache_wb(Address line)
10922 {
10923 // 64 bit cpus always support clflush
10924 assert(VM_Version::supports_clflush(), "clflush should be available");
10925 bool optimized = VM_Version::supports_clflushopt();
10926 bool no_evict = VM_Version::supports_clwb();
10927
10928 // prefer clwb (writeback without evict) otherwise
10929 // prefer clflushopt (potentially parallel writeback with evict)
10930 // otherwise fallback on clflush (serial writeback with evict)
10931
10932 if (optimized) {
10933 if (no_evict) {
10934 clwb(line);
10935 } else {
10936 clflushopt(line);
10937 }
10938 } else {
10939 // no need for fence when using CLFLUSH
10940 clflush(line);
10941 }
10942 }
10943
10944 void MacroAssembler::cache_wbsync(bool is_pre)
10945 {
10946 assert(VM_Version::supports_clflush(), "clflush should be available");
10947 bool optimized = VM_Version::supports_clflushopt();
10948 bool no_evict = VM_Version::supports_clwb();
10949
10950 // pick the correct implementation
10951
10952 if (!is_pre && (optimized || no_evict)) {
10953 // need an sfence for post flush when using clflushopt or clwb
10954 // otherwise no no need for any synchroniaztion
10955
10956 sfence();
10957 }
10958 }
10959
10960 #endif // _LP64
10961
10962 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10963 switch (cond) {
10964 // Note some conditions are synonyms for others
10965 case Assembler::zero: return Assembler::notZero;
10966 case Assembler::notZero: return Assembler::zero;
10967 case Assembler::less: return Assembler::greaterEqual;
10968 case Assembler::lessEqual: return Assembler::greater;
10969 case Assembler::greater: return Assembler::lessEqual;
10970 case Assembler::greaterEqual: return Assembler::less;
10971 case Assembler::below: return Assembler::aboveEqual;
10972 case Assembler::belowEqual: return Assembler::above;
10973 case Assembler::above: return Assembler::belowEqual;
10974 case Assembler::aboveEqual: return Assembler::below;
10975 case Assembler::overflow: return Assembler::noOverflow;
10976 case Assembler::noOverflow: return Assembler::overflow;
10977 case Assembler::negative: return Assembler::positive;
10978 case Assembler::positive: return Assembler::negative;
10979 case Assembler::parity: return Assembler::noParity;
10980 case Assembler::noParity: return Assembler::parity;
10981 }
10982 ShouldNotReachHere(); return Assembler::overflow;
10983 }
10984
10985 SkipIfEqual::SkipIfEqual(
10986 MacroAssembler* masm, const bool* flag_addr, bool value, Register rscratch) {
10987 _masm = masm;
10988 _masm->cmp8(ExternalAddress((address)flag_addr), value, rscratch);
10989 _masm->jcc(Assembler::equal, _label);
10990 }
10991
10992 SkipIfEqual::~SkipIfEqual() {
10993 _masm->bind(_label);
10994 }
10995
10996 // 32-bit Windows has its own fast-path implementation
10997 // of get_thread
10998 #if !defined(WIN32) || defined(_LP64)
10999
11000 // This is simply a call to Thread::current()
11001 void MacroAssembler::get_thread(Register thread) {
11002 if (thread != rax) {
11003 push(rax);
11004 }
11005 LP64_ONLY(push(rdi);)
11006 LP64_ONLY(push(rsi);)
11007 push(rdx);
11008 push(rcx);
11009 #ifdef _LP64
11010 push(r8);
11011 push(r9);
11012 push(r10);
11013 push(r11);
11014 #endif
11015
11016 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
11017
11018 #ifdef _LP64
11019 pop(r11);
11020 pop(r10);
11021 pop(r9);
11022 pop(r8);
11023 #endif
11024 pop(rcx);
11025 pop(rdx);
11026 LP64_ONLY(pop(rsi);)
11027 LP64_ONLY(pop(rdi);)
11028 if (thread != rax) {
11029 mov(thread, rax);
11030 pop(rax);
11031 }
11032 }
11033
11034
11035 #endif // !WIN32 || _LP64
11036
11037 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
11038 Label L_stack_ok;
11039 if (bias == 0) {
11040 testptr(sp, 2 * wordSize - 1);
11041 } else {
11042 // lea(tmp, Address(rsp, bias);
11043 mov(tmp, sp);
11044 addptr(tmp, bias);
11045 testptr(tmp, 2 * wordSize - 1);
11046 }
11047 jcc(Assembler::equal, L_stack_ok);
11048 block_comment(msg);
11049 stop(msg);
11050 bind(L_stack_ok);
11051 }
11052
11053 // Implements lightweight-locking.
11054 //
11055 // obj: the object to be locked
11056 // reg_rax: rax
11057 // thread: the thread which attempts to lock obj
11058 // tmp: a temporary register
11059 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
11060 assert(reg_rax == rax, "");
11061 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
11062
11063 Label push;
11064 const Register top = tmp;
11065
11066 // Preload the markWord. It is important that this is the first
11067 // instruction emitted as it is part of C1's null check semantics.
11068 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
11069
11070 if (UseObjectMonitorTable) {
11071 // Clear cache in case fast locking succeeds.
11072 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
11073 }
11074
11075 // Load top.
11076 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
11077
11078 // Check if the lock-stack is full.
11079 cmpl(top, LockStack::end_offset());
11080 jcc(Assembler::greaterEqual, slow);
11081
11082 // Check for recursion.
11083 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
11084 jcc(Assembler::equal, push);
11085
11086 // Check header for monitor (0b10).
11087 testptr(reg_rax, markWord::monitor_value);
11088 jcc(Assembler::notZero, slow);
11089
11090 // Try to lock. Transition lock bits 0b01 => 0b00
11091 movptr(tmp, reg_rax);
11092 andptr(tmp, ~(int32_t)markWord::unlocked_value);
11093 orptr(reg_rax, markWord::unlocked_value);
11094 if (EnableValhalla) {
11095 // Mask inline_type bit such that we go to the slow path if object is an inline type
11096 andptr(reg_rax, ~((int) markWord::inline_type_bit_in_place));
11097 }
11098 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
11099 jcc(Assembler::notEqual, slow);
11100
11101 // Restore top, CAS clobbers register.
11102 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
11103
11104 bind(push);
11105 // After successful lock, push object on lock-stack.
11106 movptr(Address(thread, top), obj);
11107 incrementl(top, oopSize);
11108 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
11109 }
11110
11111 // Implements lightweight-unlocking.
11112 //
11113 // obj: the object to be unlocked
11114 // reg_rax: rax
11115 // thread: the thread
11116 // tmp: a temporary register
11117 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
11118 assert(reg_rax == rax, "");
11119 assert_different_registers(obj, reg_rax, thread, tmp);
11120
11121 Label unlocked, push_and_slow;
11122 const Register top = tmp;
11123
11124 // Check if obj is top of lock-stack.
11125 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
11126 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
11127 jcc(Assembler::notEqual, slow);
11128
11129 // Pop lock-stack.
11130 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
11131 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
11132
11133 // Check if recursive.
11134 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
11135 jcc(Assembler::equal, unlocked);
11136
11137 // Not recursive. Check header for monitor (0b10).
11138 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
11139 testptr(reg_rax, markWord::monitor_value);
11140 jcc(Assembler::notZero, push_and_slow);
11141
11142 #ifdef ASSERT
11143 // Check header not unlocked (0b01).
11144 Label not_unlocked;
11145 testptr(reg_rax, markWord::unlocked_value);
11146 jcc(Assembler::zero, not_unlocked);
11147 stop("lightweight_unlock already unlocked");
11148 bind(not_unlocked);
11149 #endif
11150
11151 // Try to unlock. Transition lock bits 0b00 => 0b01
11152 movptr(tmp, reg_rax);
11153 orptr(tmp, markWord::unlocked_value);
11154 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
11155 jcc(Assembler::equal, unlocked);
11156
11157 bind(push_and_slow);
11158 // Restore lock-stack and handle the unlock in runtime.
11159 #ifdef ASSERT
11160 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
11161 movptr(Address(thread, top), obj);
11162 #endif
11163 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
11164 jmp(slow);
11165
11166 bind(unlocked);
11167 }
11168
11169 #ifdef _LP64
11170 // Saves legacy GPRs state on stack.
11171 void MacroAssembler::save_legacy_gprs() {
11172 subq(rsp, 16 * wordSize);
11173 movq(Address(rsp, 15 * wordSize), rax);
11174 movq(Address(rsp, 14 * wordSize), rcx);
11175 movq(Address(rsp, 13 * wordSize), rdx);
11176 movq(Address(rsp, 12 * wordSize), rbx);
11177 movq(Address(rsp, 10 * wordSize), rbp);
11178 movq(Address(rsp, 9 * wordSize), rsi);
11179 movq(Address(rsp, 8 * wordSize), rdi);
11180 movq(Address(rsp, 7 * wordSize), r8);
11181 movq(Address(rsp, 6 * wordSize), r9);
11182 movq(Address(rsp, 5 * wordSize), r10);
11183 movq(Address(rsp, 4 * wordSize), r11);
11184 movq(Address(rsp, 3 * wordSize), r12);
11185 movq(Address(rsp, 2 * wordSize), r13);
11186 movq(Address(rsp, wordSize), r14);
11187 movq(Address(rsp, 0), r15);
11188 }
11189
11190 // Resotres back legacy GPRs state from stack.
11191 void MacroAssembler::restore_legacy_gprs() {
11192 movq(r15, Address(rsp, 0));
11193 movq(r14, Address(rsp, wordSize));
11194 movq(r13, Address(rsp, 2 * wordSize));
11195 movq(r12, Address(rsp, 3 * wordSize));
11196 movq(r11, Address(rsp, 4 * wordSize));
11197 movq(r10, Address(rsp, 5 * wordSize));
11198 movq(r9, Address(rsp, 6 * wordSize));
11199 movq(r8, Address(rsp, 7 * wordSize));
11200 movq(rdi, Address(rsp, 8 * wordSize));
11201 movq(rsi, Address(rsp, 9 * wordSize));
11202 movq(rbp, Address(rsp, 10 * wordSize));
11203 movq(rbx, Address(rsp, 12 * wordSize));
11204 movq(rdx, Address(rsp, 13 * wordSize));
11205 movq(rcx, Address(rsp, 14 * wordSize));
11206 movq(rax, Address(rsp, 15 * wordSize));
11207 addq(rsp, 16 * wordSize);
11208 }
11209
11210 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
11211 if (VM_Version::supports_apx_f()) {
11212 esetzucc(comparison, dst);
11213 } else {
11214 setb(comparison, dst);
11215 movzbl(dst, dst);
11216 }
11217 }
11218 #endif