1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/aotCodeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "ci/ciInlineKlass.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "interpreter/interpreterRuntime.hpp"
40 #include "jvm.h"
41 #include "memory/resourceArea.hpp"
42 #include "memory/universe.hpp"
43 #include "oops/accessDecorators.hpp"
44 #include "oops/compressedKlass.inline.hpp"
45 #include "oops/compressedOops.inline.hpp"
46 #include "oops/klass.inline.hpp"
47 #include "oops/resolvedFieldEntry.hpp"
48 #include "prims/methodHandles.hpp"
49 #include "runtime/arguments.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/interfaceSupport.inline.hpp"
52 #include "runtime/javaThread.hpp"
53 #include "runtime/jniHandles.hpp"
54 #include "runtime/objectMonitor.hpp"
55 #include "runtime/os.hpp"
56 #include "runtime/safepoint.hpp"
57 #include "runtime/safepointMechanism.hpp"
58 #include "runtime/sharedRuntime.hpp"
59 #include "runtime/signature_cc.hpp"
60 #include "runtime/stubRoutines.hpp"
61 #include "utilities/checkedCast.hpp"
62 #include "utilities/macros.hpp"
63 #include "vmreg_x86.inline.hpp"
64 #ifdef COMPILER2
65 #include "opto/output.hpp"
66 #endif
67
68 #ifdef PRODUCT
69 #define BLOCK_COMMENT(str) /* nothing */
70 #define STOP(error) stop(error)
71 #else
72 #define BLOCK_COMMENT(str) block_comment(str)
73 #define STOP(error) block_comment(error); stop(error)
74 #endif
75
76 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
77
78 #ifdef ASSERT
79 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
80 #endif
81
82 static const Assembler::Condition reverse[] = {
83 Assembler::noOverflow /* overflow = 0x0 */ ,
84 Assembler::overflow /* noOverflow = 0x1 */ ,
85 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
86 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
87 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
88 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
89 Assembler::above /* belowEqual = 0x6 */ ,
90 Assembler::belowEqual /* above = 0x7 */ ,
91 Assembler::positive /* negative = 0x8 */ ,
92 Assembler::negative /* positive = 0x9 */ ,
93 Assembler::noParity /* parity = 0xa */ ,
94 Assembler::parity /* noParity = 0xb */ ,
95 Assembler::greaterEqual /* less = 0xc */ ,
96 Assembler::less /* greaterEqual = 0xd */ ,
97 Assembler::greater /* lessEqual = 0xe */ ,
98 Assembler::lessEqual /* greater = 0xf, */
99
100 };
101
102
103 // Implementation of MacroAssembler
104
105 Address MacroAssembler::as_Address(AddressLiteral adr) {
106 // amd64 always does this as a pc-rel
107 // we can be absolute or disp based on the instruction type
108 // jmp/call are displacements others are absolute
109 assert(!adr.is_lval(), "must be rval");
110 assert(reachable(adr), "must be");
111 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
112
113 }
114
115 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
116 AddressLiteral base = adr.base();
117 lea(rscratch, base);
118 Address index = adr.index();
119 assert(index._disp == 0, "must not have disp"); // maybe it can?
120 Address array(rscratch, index._index, index._scale, index._disp);
121 return array;
122 }
123
124 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
125 Label L, E;
126
127 #ifdef _WIN64
128 // Windows always allocates space for it's register args
129 assert(num_args <= 4, "only register arguments supported");
130 subq(rsp, frame::arg_reg_save_area_bytes);
131 #endif
132
133 // Align stack if necessary
134 testl(rsp, 15);
135 jcc(Assembler::zero, L);
136
137 subq(rsp, 8);
138 call(RuntimeAddress(entry_point));
139 addq(rsp, 8);
140 jmp(E);
141
142 bind(L);
143 call(RuntimeAddress(entry_point));
144
145 bind(E);
146
147 #ifdef _WIN64
148 // restore stack pointer
149 addq(rsp, frame::arg_reg_save_area_bytes);
150 #endif
151 }
152
153 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
154 assert(!src2.is_lval(), "should use cmpptr");
155 assert(rscratch != noreg || always_reachable(src2), "missing");
156
157 if (reachable(src2)) {
158 cmpq(src1, as_Address(src2));
159 } else {
160 lea(rscratch, src2);
161 Assembler::cmpq(src1, Address(rscratch, 0));
162 }
163 }
164
165 int MacroAssembler::corrected_idivq(Register reg) {
166 // Full implementation of Java ldiv and lrem; checks for special
167 // case as described in JVM spec., p.243 & p.271. The function
168 // returns the (pc) offset of the idivl instruction - may be needed
169 // for implicit exceptions.
170 //
171 // normal case special case
172 //
173 // input : rax: dividend min_long
174 // reg: divisor (may not be eax/edx) -1
175 //
176 // output: rax: quotient (= rax idiv reg) min_long
177 // rdx: remainder (= rax irem reg) 0
178 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
179 static const int64_t min_long = 0x8000000000000000;
180 Label normal_case, special_case;
181
182 // check for special case
183 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
184 jcc(Assembler::notEqual, normal_case);
185 xorl(rdx, rdx); // prepare rdx for possible special case (where
186 // remainder = 0)
187 cmpq(reg, -1);
188 jcc(Assembler::equal, special_case);
189
190 // handle normal case
191 bind(normal_case);
192 cdqq();
193 int idivq_offset = offset();
194 idivq(reg);
195
196 // normal and special case exit
197 bind(special_case);
198
199 return idivq_offset;
200 }
201
202 void MacroAssembler::decrementq(Register reg, int value) {
203 if (value == min_jint) { subq(reg, value); return; }
204 if (value < 0) { incrementq(reg, -value); return; }
205 if (value == 0) { ; return; }
206 if (value == 1 && UseIncDec) { decq(reg) ; return; }
207 /* else */ { subq(reg, value) ; return; }
208 }
209
210 void MacroAssembler::decrementq(Address dst, int value) {
211 if (value == min_jint) { subq(dst, value); return; }
212 if (value < 0) { incrementq(dst, -value); return; }
213 if (value == 0) { ; return; }
214 if (value == 1 && UseIncDec) { decq(dst) ; return; }
215 /* else */ { subq(dst, value) ; return; }
216 }
217
218 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
219 assert(rscratch != noreg || always_reachable(dst), "missing");
220
221 if (reachable(dst)) {
222 incrementq(as_Address(dst));
223 } else {
224 lea(rscratch, dst);
225 incrementq(Address(rscratch, 0));
226 }
227 }
228
229 void MacroAssembler::incrementq(Register reg, int value) {
230 if (value == min_jint) { addq(reg, value); return; }
231 if (value < 0) { decrementq(reg, -value); return; }
232 if (value == 0) { ; return; }
233 if (value == 1 && UseIncDec) { incq(reg) ; return; }
234 /* else */ { addq(reg, value) ; return; }
235 }
236
237 void MacroAssembler::incrementq(Address dst, int value) {
238 if (value == min_jint) { addq(dst, value); return; }
239 if (value < 0) { decrementq(dst, -value); return; }
240 if (value == 0) { ; return; }
241 if (value == 1 && UseIncDec) { incq(dst) ; return; }
242 /* else */ { addq(dst, value) ; return; }
243 }
244
245 // 32bit can do a case table jump in one instruction but we no longer allow the base
246 // to be installed in the Address class
247 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
248 lea(rscratch, entry.base());
249 Address dispatch = entry.index();
250 assert(dispatch._base == noreg, "must be");
251 dispatch._base = rscratch;
252 jmp(dispatch);
253 }
254
255 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
256 ShouldNotReachHere(); // 64bit doesn't use two regs
257 cmpq(x_lo, y_lo);
258 }
259
260 void MacroAssembler::lea(Register dst, AddressLiteral src) {
261 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
262 }
263
264 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
265 lea(rscratch, adr);
266 movptr(dst, rscratch);
267 }
268
269 void MacroAssembler::leave() {
270 // %%% is this really better? Why not on 32bit too?
271 emit_int8((unsigned char)0xC9); // LEAVE
272 }
273
274 void MacroAssembler::lneg(Register hi, Register lo) {
275 ShouldNotReachHere(); // 64bit doesn't use two regs
276 negq(lo);
277 }
278
279 void MacroAssembler::movoop(Register dst, jobject obj) {
280 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
281 }
282
283 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
284 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
285 movq(dst, rscratch);
286 }
287
288 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
289 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
290 }
291
292 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
293 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
294 movq(dst, rscratch);
295 }
296
297 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
298 if (src.is_lval()) {
299 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
300 } else {
301 if (reachable(src)) {
302 movq(dst, as_Address(src));
303 } else {
304 lea(dst, src);
305 movq(dst, Address(dst, 0));
306 }
307 }
308 }
309
310 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
311 movq(as_Address(dst, rscratch), src);
312 }
313
314 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
315 movq(dst, as_Address(src, dst /*rscratch*/));
316 }
317
318 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
319 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
320 if (is_simm32(src)) {
321 movptr(dst, checked_cast<int32_t>(src));
322 } else {
323 mov64(rscratch, src);
324 movq(dst, rscratch);
325 }
326 }
327
328 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
329 movoop(rscratch, obj);
330 push(rscratch);
331 }
332
333 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
334 mov_metadata(rscratch, obj);
335 push(rscratch);
336 }
337
338 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
339 lea(rscratch, src);
340 if (src.is_lval()) {
341 push(rscratch);
342 } else {
343 pushq(Address(rscratch, 0));
344 }
345 }
346
347 static void pass_arg0(MacroAssembler* masm, Register arg) {
348 if (c_rarg0 != arg ) {
349 masm->mov(c_rarg0, arg);
350 }
351 }
352
353 static void pass_arg1(MacroAssembler* masm, Register arg) {
354 if (c_rarg1 != arg ) {
355 masm->mov(c_rarg1, arg);
356 }
357 }
358
359 static void pass_arg2(MacroAssembler* masm, Register arg) {
360 if (c_rarg2 != arg ) {
361 masm->mov(c_rarg2, arg);
362 }
363 }
364
365 static void pass_arg3(MacroAssembler* masm, Register arg) {
366 if (c_rarg3 != arg ) {
367 masm->mov(c_rarg3, arg);
368 }
369 }
370
371 void MacroAssembler::stop(const char* msg) {
372 if (ShowMessageBoxOnError) {
373 address rip = pc();
374 pusha(); // get regs on stack
375 lea(c_rarg1, InternalAddress(rip));
376 movq(c_rarg2, rsp); // pass pointer to regs array
377 }
378 // Skip AOT caching C strings in scratch buffer.
379 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
380 lea(c_rarg0, ExternalAddress((address) str));
381 andq(rsp, -16); // align stack as required by ABI
382 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
383 hlt();
384 }
385
386 void MacroAssembler::warn(const char* msg) {
387 push(rbp);
388 movq(rbp, rsp);
389 andq(rsp, -16); // align stack as required by push_CPU_state and call
390 push_CPU_state(); // keeps alignment at 16 bytes
391
392 #ifdef _WIN64
393 // Windows always allocates space for its register args
394 subq(rsp, frame::arg_reg_save_area_bytes);
395 #endif
396 lea(c_rarg0, ExternalAddress((address) msg));
397 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
398
399 #ifdef _WIN64
400 // restore stack pointer
401 addq(rsp, frame::arg_reg_save_area_bytes);
402 #endif
403 pop_CPU_state();
404 mov(rsp, rbp);
405 pop(rbp);
406 }
407
408 void MacroAssembler::print_state() {
409 address rip = pc();
410 pusha(); // get regs on stack
411 push(rbp);
412 movq(rbp, rsp);
413 andq(rsp, -16); // align stack as required by push_CPU_state and call
414 push_CPU_state(); // keeps alignment at 16 bytes
415
416 lea(c_rarg0, InternalAddress(rip));
417 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
418 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
419
420 pop_CPU_state();
421 mov(rsp, rbp);
422 pop(rbp);
423 popa();
424 }
425
426 #ifndef PRODUCT
427 extern "C" void findpc(intptr_t x);
428 #endif
429
430 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
431 // In order to get locks to work, we need to fake a in_VM state
432 if (ShowMessageBoxOnError) {
433 JavaThread* thread = JavaThread::current();
434 JavaThreadState saved_state = thread->thread_state();
435 thread->set_thread_state(_thread_in_vm);
436 #ifndef PRODUCT
437 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
438 ttyLocker ttyl;
439 BytecodeCounter::print();
440 }
441 #endif
442 // To see where a verify_oop failed, get $ebx+40/X for this frame.
443 // XXX correct this offset for amd64
444 // This is the value of eip which points to where verify_oop will return.
445 if (os::message_box(msg, "Execution stopped, print registers?")) {
446 print_state64(pc, regs);
447 BREAKPOINT;
448 }
449 }
450 fatal("DEBUG MESSAGE: %s", msg);
451 }
452
453 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
454 ttyLocker ttyl;
455 DebuggingContext debugging{};
456 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
457 #ifndef PRODUCT
458 tty->cr();
459 findpc(pc);
460 tty->cr();
461 #endif
462 #define PRINT_REG(rax, value) \
463 { tty->print("%s = ", #rax); os::print_location(tty, value); }
464 PRINT_REG(rax, regs[15]);
465 PRINT_REG(rbx, regs[12]);
466 PRINT_REG(rcx, regs[14]);
467 PRINT_REG(rdx, regs[13]);
468 PRINT_REG(rdi, regs[8]);
469 PRINT_REG(rsi, regs[9]);
470 PRINT_REG(rbp, regs[10]);
471 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
472 PRINT_REG(rsp, (intptr_t)(®s[16]));
473 PRINT_REG(r8 , regs[7]);
474 PRINT_REG(r9 , regs[6]);
475 PRINT_REG(r10, regs[5]);
476 PRINT_REG(r11, regs[4]);
477 PRINT_REG(r12, regs[3]);
478 PRINT_REG(r13, regs[2]);
479 PRINT_REG(r14, regs[1]);
480 PRINT_REG(r15, regs[0]);
481 #undef PRINT_REG
482 // Print some words near the top of the stack.
483 int64_t* rsp = ®s[16];
484 int64_t* dump_sp = rsp;
485 for (int col1 = 0; col1 < 8; col1++) {
486 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
487 os::print_location(tty, *dump_sp++);
488 }
489 for (int row = 0; row < 25; row++) {
490 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
491 for (int col = 0; col < 4; col++) {
492 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
493 }
494 tty->cr();
495 }
496 // Print some instructions around pc:
497 Disassembler::decode((address)pc-64, (address)pc);
498 tty->print_cr("--------");
499 Disassembler::decode((address)pc, (address)pc+32);
500 }
501
502 // The java_calling_convention describes stack locations as ideal slots on
503 // a frame with no abi restrictions. Since we must observe abi restrictions
504 // (like the placement of the register window) the slots must be biased by
505 // the following value.
506 static int reg2offset_in(VMReg r) {
507 // Account for saved rbp and return address
508 // This should really be in_preserve_stack_slots
509 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
510 }
511
512 static int reg2offset_out(VMReg r) {
513 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
514 }
515
516 // A long move
517 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
518
519 // The calling conventions assures us that each VMregpair is either
520 // all really one physical register or adjacent stack slots.
521
522 if (src.is_single_phys_reg() ) {
523 if (dst.is_single_phys_reg()) {
524 if (dst.first() != src.first()) {
525 mov(dst.first()->as_Register(), src.first()->as_Register());
526 }
527 } else {
528 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
529 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
530 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
531 }
532 } else if (dst.is_single_phys_reg()) {
533 assert(src.is_single_reg(), "not a stack pair");
534 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
535 } else {
536 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
537 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
538 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
539 }
540 }
541
542 // A double move
543 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
544
545 // The calling conventions assures us that each VMregpair is either
546 // all really one physical register or adjacent stack slots.
547
548 if (src.is_single_phys_reg() ) {
549 if (dst.is_single_phys_reg()) {
550 // In theory these overlap but the ordering is such that this is likely a nop
551 if ( src.first() != dst.first()) {
552 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
553 }
554 } else {
555 assert(dst.is_single_reg(), "not a stack pair");
556 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
557 }
558 } else if (dst.is_single_phys_reg()) {
559 assert(src.is_single_reg(), "not a stack pair");
560 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
561 } else {
562 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
563 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
564 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
565 }
566 }
567
568
569 // A float arg may have to do float reg int reg conversion
570 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
571 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
572
573 // The calling conventions assures us that each VMregpair is either
574 // all really one physical register or adjacent stack slots.
575
576 if (src.first()->is_stack()) {
577 if (dst.first()->is_stack()) {
578 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
579 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
580 } else {
581 // stack to reg
582 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
583 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
584 }
585 } else if (dst.first()->is_stack()) {
586 // reg to stack
587 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
588 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
589 } else {
590 // reg to reg
591 // In theory these overlap but the ordering is such that this is likely a nop
592 if ( src.first() != dst.first()) {
593 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
594 }
595 }
596 }
597
598 // On 64 bit we will store integer like items to the stack as
599 // 64 bits items (x86_32/64 abi) even though java would only store
600 // 32bits for a parameter. On 32bit it will simply be 32 bits
601 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
602 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
603 if (src.first()->is_stack()) {
604 if (dst.first()->is_stack()) {
605 // stack to stack
606 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
607 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
608 } else {
609 // stack to reg
610 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
611 }
612 } else if (dst.first()->is_stack()) {
613 // reg to stack
614 // Do we really have to sign extend???
615 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
616 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
617 } else {
618 // Do we really have to sign extend???
619 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
620 if (dst.first() != src.first()) {
621 movq(dst.first()->as_Register(), src.first()->as_Register());
622 }
623 }
624 }
625
626 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
627 if (src.first()->is_stack()) {
628 if (dst.first()->is_stack()) {
629 // stack to stack
630 movq(rax, Address(rbp, reg2offset_in(src.first())));
631 movq(Address(rsp, reg2offset_out(dst.first())), rax);
632 } else {
633 // stack to reg
634 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
635 }
636 } else if (dst.first()->is_stack()) {
637 // reg to stack
638 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
639 } else {
640 if (dst.first() != src.first()) {
641 movq(dst.first()->as_Register(), src.first()->as_Register());
642 }
643 }
644 }
645
646 // An oop arg. Must pass a handle not the oop itself
647 void MacroAssembler::object_move(OopMap* map,
648 int oop_handle_offset,
649 int framesize_in_slots,
650 VMRegPair src,
651 VMRegPair dst,
652 bool is_receiver,
653 int* receiver_offset) {
654
655 // must pass a handle. First figure out the location we use as a handle
656
657 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
658
659 // See if oop is null if it is we need no handle
660
661 if (src.first()->is_stack()) {
662
663 // Oop is already on the stack as an argument
664 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
665 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
666 if (is_receiver) {
667 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
668 }
669
670 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
671 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
672 // conditionally move a null
673 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
674 } else {
675
676 // Oop is in a register we must store it to the space we reserve
677 // on the stack for oop_handles and pass a handle if oop is non-null
678
679 const Register rOop = src.first()->as_Register();
680 int oop_slot;
681 if (rOop == j_rarg0)
682 oop_slot = 0;
683 else if (rOop == j_rarg1)
684 oop_slot = 1;
685 else if (rOop == j_rarg2)
686 oop_slot = 2;
687 else if (rOop == j_rarg3)
688 oop_slot = 3;
689 else if (rOop == j_rarg4)
690 oop_slot = 4;
691 else {
692 assert(rOop == j_rarg5, "wrong register");
693 oop_slot = 5;
694 }
695
696 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
697 int offset = oop_slot*VMRegImpl::stack_slot_size;
698
699 map->set_oop(VMRegImpl::stack2reg(oop_slot));
700 // Store oop in handle area, may be null
701 movptr(Address(rsp, offset), rOop);
702 if (is_receiver) {
703 *receiver_offset = offset;
704 }
705
706 cmpptr(rOop, NULL_WORD);
707 lea(rHandle, Address(rsp, offset));
708 // conditionally move a null from the handle area where it was just stored
709 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
710 }
711
712 // If arg is on the stack then place it otherwise it is already in correct reg.
713 if (dst.first()->is_stack()) {
714 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
715 }
716 }
717
718 void MacroAssembler::addptr(Register dst, int32_t imm32) {
719 addq(dst, imm32);
720 }
721
722 void MacroAssembler::addptr(Register dst, Register src) {
723 addq(dst, src);
724 }
725
726 void MacroAssembler::addptr(Address dst, Register src) {
727 addq(dst, src);
728 }
729
730 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
731 assert(rscratch != noreg || always_reachable(src), "missing");
732
733 if (reachable(src)) {
734 Assembler::addsd(dst, as_Address(src));
735 } else {
736 lea(rscratch, src);
737 Assembler::addsd(dst, Address(rscratch, 0));
738 }
739 }
740
741 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
742 assert(rscratch != noreg || always_reachable(src), "missing");
743
744 if (reachable(src)) {
745 addss(dst, as_Address(src));
746 } else {
747 lea(rscratch, src);
748 addss(dst, Address(rscratch, 0));
749 }
750 }
751
752 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
753 assert(rscratch != noreg || always_reachable(src), "missing");
754
755 if (reachable(src)) {
756 Assembler::addpd(dst, as_Address(src));
757 } else {
758 lea(rscratch, src);
759 Assembler::addpd(dst, Address(rscratch, 0));
760 }
761 }
762
763 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
764 // Stub code is generated once and never copied.
765 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
766 void MacroAssembler::align64() {
767 align(64, (uint)(uintptr_t)pc());
768 }
769
770 void MacroAssembler::align32() {
771 align(32, (uint)(uintptr_t)pc());
772 }
773
774 void MacroAssembler::align(uint modulus) {
775 // 8273459: Ensure alignment is possible with current segment alignment
776 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
777 align(modulus, offset());
778 }
779
780 void MacroAssembler::align(uint modulus, uint target) {
781 if (target % modulus != 0) {
782 nop(modulus - (target % modulus));
783 }
784 }
785
786 void MacroAssembler::push_f(XMMRegister r) {
787 subptr(rsp, wordSize);
788 movflt(Address(rsp, 0), r);
789 }
790
791 void MacroAssembler::pop_f(XMMRegister r) {
792 movflt(r, Address(rsp, 0));
793 addptr(rsp, wordSize);
794 }
795
796 void MacroAssembler::push_d(XMMRegister r) {
797 subptr(rsp, 2 * wordSize);
798 movdbl(Address(rsp, 0), r);
799 }
800
801 void MacroAssembler::pop_d(XMMRegister r) {
802 movdbl(r, Address(rsp, 0));
803 addptr(rsp, 2 * Interpreter::stackElementSize);
804 }
805
806 void MacroAssembler::push_ppx(Register src) {
807 if (VM_Version::supports_apx_f()) {
808 pushp(src);
809 } else {
810 Assembler::push(src);
811 }
812 }
813
814 void MacroAssembler::pop_ppx(Register dst) {
815 if (VM_Version::supports_apx_f()) {
816 popp(dst);
817 } else {
818 Assembler::pop(dst);
819 }
820 }
821
822 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
823 // Used in sign-masking with aligned address.
824 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
825 assert(rscratch != noreg || always_reachable(src), "missing");
826
827 if (UseAVX > 2 &&
828 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
829 (dst->encoding() >= 16)) {
830 vpand(dst, dst, src, AVX_512bit, rscratch);
831 } else if (reachable(src)) {
832 Assembler::andpd(dst, as_Address(src));
833 } else {
834 lea(rscratch, src);
835 Assembler::andpd(dst, Address(rscratch, 0));
836 }
837 }
838
839 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
840 // Used in sign-masking with aligned address.
841 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
842 assert(rscratch != noreg || always_reachable(src), "missing");
843
844 if (reachable(src)) {
845 Assembler::andps(dst, as_Address(src));
846 } else {
847 lea(rscratch, src);
848 Assembler::andps(dst, Address(rscratch, 0));
849 }
850 }
851
852 void MacroAssembler::andptr(Register dst, int32_t imm32) {
853 andq(dst, imm32);
854 }
855
856 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
857 assert(rscratch != noreg || always_reachable(src), "missing");
858
859 if (reachable(src)) {
860 andq(dst, as_Address(src));
861 } else {
862 lea(rscratch, src);
863 andq(dst, Address(rscratch, 0));
864 }
865 }
866
867 void MacroAssembler::atomic_incl(Address counter_addr) {
868 lock();
869 incrementl(counter_addr);
870 }
871
872 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
873 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
874
875 if (reachable(counter_addr)) {
876 atomic_incl(as_Address(counter_addr));
877 } else {
878 lea(rscratch, counter_addr);
879 atomic_incl(Address(rscratch, 0));
880 }
881 }
882
883 void MacroAssembler::atomic_incq(Address counter_addr) {
884 lock();
885 incrementq(counter_addr);
886 }
887
888 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
889 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
890
891 if (reachable(counter_addr)) {
892 atomic_incq(as_Address(counter_addr));
893 } else {
894 lea(rscratch, counter_addr);
895 atomic_incq(Address(rscratch, 0));
896 }
897 }
898
899 // Writes to stack successive pages until offset reached to check for
900 // stack overflow + shadow pages. This clobbers tmp.
901 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
902 movptr(tmp, rsp);
903 // Bang stack for total size given plus shadow page size.
904 // Bang one page at a time because large size can bang beyond yellow and
905 // red zones.
906 Label loop;
907 bind(loop);
908 movl(Address(tmp, (-(int)os::vm_page_size())), size );
909 subptr(tmp, (int)os::vm_page_size());
910 subl(size, (int)os::vm_page_size());
911 jcc(Assembler::greater, loop);
912
913 // Bang down shadow pages too.
914 // At this point, (tmp-0) is the last address touched, so don't
915 // touch it again. (It was touched as (tmp-pagesize) but then tmp
916 // was post-decremented.) Skip this address by starting at i=1, and
917 // touch a few more pages below. N.B. It is important to touch all
918 // the way down including all pages in the shadow zone.
919 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
920 // this could be any sized move but this is can be a debugging crumb
921 // so the bigger the better.
922 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
923 }
924 }
925
926 void MacroAssembler::reserved_stack_check() {
927 // testing if reserved zone needs to be enabled
928 Label no_reserved_zone_enabling;
929
930 cmpptr(rsp, Address(r15_thread, JavaThread::reserved_stack_activation_offset()));
931 jcc(Assembler::below, no_reserved_zone_enabling);
932
933 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), r15_thread);
934 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
935 should_not_reach_here();
936
937 bind(no_reserved_zone_enabling);
938 }
939
940 void MacroAssembler::c2bool(Register x) {
941 // implements x == 0 ? 0 : 1
942 // note: must only look at least-significant byte of x
943 // since C-style booleans are stored in one byte
944 // only! (was bug)
945 andl(x, 0xFF);
946 setb(Assembler::notZero, x);
947 }
948
949 // Wouldn't need if AddressLiteral version had new name
950 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
951 Assembler::call(L, rtype);
952 }
953
954 void MacroAssembler::call(Register entry) {
955 Assembler::call(entry);
956 }
957
958 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
959 assert(rscratch != noreg || always_reachable(entry), "missing");
960
961 if (reachable(entry)) {
962 Assembler::call_literal(entry.target(), entry.rspec());
963 } else {
964 lea(rscratch, entry);
965 Assembler::call(rscratch);
966 }
967 }
968
969 void MacroAssembler::ic_call(address entry, jint method_index) {
970 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
971 // Needs full 64-bit immediate for later patching.
972 Assembler::mov64(rax, (int64_t)Universe::non_oop_word());
973 call(AddressLiteral(entry, rh));
974 }
975
976 int MacroAssembler::ic_check_size() {
977 return UseCompactObjectHeaders ? 17 : 14;
978 }
979
980 int MacroAssembler::ic_check(int end_alignment) {
981 Register receiver = j_rarg0;
982 Register data = rax;
983 Register temp = rscratch1;
984
985 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
986 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
987 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
988 // before the inline cache check here, and not after
989 align(end_alignment, offset() + ic_check_size());
990
991 int uep_offset = offset();
992
993 if (UseCompactObjectHeaders) {
994 load_narrow_klass_compact(temp, receiver);
995 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
996 } else if (UseCompressedClassPointers) {
997 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
998 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
999 } else {
1000 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1001 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1002 }
1003
1004 // if inline cache check fails, then jump to runtime routine
1005 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1006 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1007
1008 return uep_offset;
1009 }
1010
1011 void MacroAssembler::emit_static_call_stub() {
1012 // Static stub relocation also tags the Method* in the code-stream.
1013 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1014 // This is recognized as unresolved by relocs/nativeinst/ic code.
1015 jump(RuntimeAddress(pc()));
1016 }
1017
1018 // Implementation of call_VM versions
1019
1020 void MacroAssembler::call_VM(Register oop_result,
1021 address entry_point,
1022 bool check_exceptions) {
1023 Label C, E;
1024 call(C, relocInfo::none);
1025 jmp(E);
1026
1027 bind(C);
1028 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1029 ret(0);
1030
1031 bind(E);
1032 }
1033
1034 void MacroAssembler::call_VM(Register oop_result,
1035 address entry_point,
1036 Register arg_1,
1037 bool check_exceptions) {
1038 Label C, E;
1039 call(C, relocInfo::none);
1040 jmp(E);
1041
1042 bind(C);
1043 pass_arg1(this, arg_1);
1044 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1045 ret(0);
1046
1047 bind(E);
1048 }
1049
1050 void MacroAssembler::call_VM(Register oop_result,
1051 address entry_point,
1052 Register arg_1,
1053 Register arg_2,
1054 bool check_exceptions) {
1055 Label C, E;
1056 call(C, relocInfo::none);
1057 jmp(E);
1058
1059 bind(C);
1060
1061 assert_different_registers(arg_1, c_rarg2);
1062
1063 pass_arg2(this, arg_2);
1064 pass_arg1(this, arg_1);
1065 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1066 ret(0);
1067
1068 bind(E);
1069 }
1070
1071 void MacroAssembler::call_VM(Register oop_result,
1072 address entry_point,
1073 Register arg_1,
1074 Register arg_2,
1075 Register arg_3,
1076 bool check_exceptions) {
1077 Label C, E;
1078 call(C, relocInfo::none);
1079 jmp(E);
1080
1081 bind(C);
1082
1083 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1084 assert_different_registers(arg_2, c_rarg3);
1085 pass_arg3(this, arg_3);
1086 pass_arg2(this, arg_2);
1087 pass_arg1(this, arg_1);
1088 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1089 ret(0);
1090
1091 bind(E);
1092 }
1093
1094 void MacroAssembler::call_VM(Register oop_result,
1095 Register last_java_sp,
1096 address entry_point,
1097 int number_of_arguments,
1098 bool check_exceptions) {
1099 call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1100 }
1101
1102 void MacroAssembler::call_VM(Register oop_result,
1103 Register last_java_sp,
1104 address entry_point,
1105 Register arg_1,
1106 bool check_exceptions) {
1107 pass_arg1(this, arg_1);
1108 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1109 }
1110
1111 void MacroAssembler::call_VM(Register oop_result,
1112 Register last_java_sp,
1113 address entry_point,
1114 Register arg_1,
1115 Register arg_2,
1116 bool check_exceptions) {
1117
1118 assert_different_registers(arg_1, c_rarg2);
1119 pass_arg2(this, arg_2);
1120 pass_arg1(this, arg_1);
1121 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1122 }
1123
1124 void MacroAssembler::call_VM(Register oop_result,
1125 Register last_java_sp,
1126 address entry_point,
1127 Register arg_1,
1128 Register arg_2,
1129 Register arg_3,
1130 bool check_exceptions) {
1131 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1132 assert_different_registers(arg_2, c_rarg3);
1133 pass_arg3(this, arg_3);
1134 pass_arg2(this, arg_2);
1135 pass_arg1(this, arg_1);
1136 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1137 }
1138
1139 void MacroAssembler::super_call_VM(Register oop_result,
1140 Register last_java_sp,
1141 address entry_point,
1142 int number_of_arguments,
1143 bool check_exceptions) {
1144 MacroAssembler::call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1145 }
1146
1147 void MacroAssembler::super_call_VM(Register oop_result,
1148 Register last_java_sp,
1149 address entry_point,
1150 Register arg_1,
1151 bool check_exceptions) {
1152 pass_arg1(this, arg_1);
1153 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1154 }
1155
1156 void MacroAssembler::super_call_VM(Register oop_result,
1157 Register last_java_sp,
1158 address entry_point,
1159 Register arg_1,
1160 Register arg_2,
1161 bool check_exceptions) {
1162
1163 assert_different_registers(arg_1, c_rarg2);
1164 pass_arg2(this, arg_2);
1165 pass_arg1(this, arg_1);
1166 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1167 }
1168
1169 void MacroAssembler::super_call_VM(Register oop_result,
1170 Register last_java_sp,
1171 address entry_point,
1172 Register arg_1,
1173 Register arg_2,
1174 Register arg_3,
1175 bool check_exceptions) {
1176 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1177 assert_different_registers(arg_2, c_rarg3);
1178 pass_arg3(this, arg_3);
1179 pass_arg2(this, arg_2);
1180 pass_arg1(this, arg_1);
1181 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1182 }
1183
1184 void MacroAssembler::call_VM_base(Register oop_result,
1185 Register last_java_sp,
1186 address entry_point,
1187 int number_of_arguments,
1188 bool check_exceptions) {
1189 Register java_thread = r15_thread;
1190
1191 // determine last_java_sp register
1192 if (!last_java_sp->is_valid()) {
1193 last_java_sp = rsp;
1194 }
1195 // debugging support
1196 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1197 #ifdef ASSERT
1198 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1199 // r12 is the heapbase.
1200 if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
1201 #endif // ASSERT
1202
1203 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1204 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1205
1206 // push java thread (becomes first argument of C function)
1207
1208 mov(c_rarg0, r15_thread);
1209
1210 // set last Java frame before call
1211 assert(last_java_sp != rbp, "can't use ebp/rbp");
1212
1213 // Only interpreter should have to set fp
1214 set_last_Java_frame(last_java_sp, rbp, nullptr, rscratch1);
1215
1216 // do the call, remove parameters
1217 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1218
1219 #ifdef ASSERT
1220 // Check that thread register is not clobbered.
1221 guarantee(java_thread != rax, "change this code");
1222 push(rax);
1223 { Label L;
1224 get_thread_slow(rax);
1225 cmpptr(java_thread, rax);
1226 jcc(Assembler::equal, L);
1227 STOP("MacroAssembler::call_VM_base: java_thread not callee saved?");
1228 bind(L);
1229 }
1230 pop(rax);
1231 #endif
1232
1233 // reset last Java frame
1234 // Only interpreter should have to clear fp
1235 reset_last_Java_frame(true);
1236
1237 // C++ interp handles this in the interpreter
1238 check_and_handle_popframe();
1239 check_and_handle_earlyret();
1240
1241 if (check_exceptions) {
1242 // check for pending exceptions (java_thread is set upon return)
1243 cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
1244 // This used to conditionally jump to forward_exception however it is
1245 // possible if we relocate that the branch will not reach. So we must jump
1246 // around so we can always reach
1247
1248 Label ok;
1249 jcc(Assembler::equal, ok);
1250 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1251 bind(ok);
1252 }
1253
1254 // get oop result if there is one and reset the value in the thread
1255 if (oop_result->is_valid()) {
1256 get_vm_result_oop(oop_result);
1257 }
1258 }
1259
1260 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1261 // Calculate the value for last_Java_sp somewhat subtle.
1262 // call_VM does an intermediate call which places a return address on
1263 // the stack just under the stack pointer as the user finished with it.
1264 // This allows use to retrieve last_Java_pc from last_Java_sp[-1].
1265
1266 // We've pushed one address, correct last_Java_sp
1267 lea(rax, Address(rsp, wordSize));
1268
1269 call_VM_base(oop_result, rax, entry_point, number_of_arguments, check_exceptions);
1270 }
1271
1272 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1273 void MacroAssembler::call_VM_leaf0(address entry_point) {
1274 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1275 }
1276
1277 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1278 call_VM_leaf_base(entry_point, number_of_arguments);
1279 }
1280
1281 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1282 pass_arg0(this, arg_0);
1283 call_VM_leaf(entry_point, 1);
1284 }
1285
1286 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1287
1288 assert_different_registers(arg_0, c_rarg1);
1289 pass_arg1(this, arg_1);
1290 pass_arg0(this, arg_0);
1291 call_VM_leaf(entry_point, 2);
1292 }
1293
1294 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1295 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1296 assert_different_registers(arg_1, c_rarg2);
1297 pass_arg2(this, arg_2);
1298 pass_arg1(this, arg_1);
1299 pass_arg0(this, arg_0);
1300 call_VM_leaf(entry_point, 3);
1301 }
1302
1303 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1304 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1305 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1306 assert_different_registers(arg_2, c_rarg3);
1307 pass_arg3(this, arg_3);
1308 pass_arg2(this, arg_2);
1309 pass_arg1(this, arg_1);
1310 pass_arg0(this, arg_0);
1311 call_VM_leaf(entry_point, 3);
1312 }
1313
1314 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1315 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1316 }
1317
1318 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1319 pass_arg0(this, arg_0);
1320 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1321 }
1322
1323 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1324 assert_different_registers(arg_0, c_rarg1);
1325 pass_arg1(this, arg_1);
1326 pass_arg0(this, arg_0);
1327 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1328 }
1329
1330 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1331 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1332 assert_different_registers(arg_1, c_rarg2);
1333 pass_arg2(this, arg_2);
1334 pass_arg1(this, arg_1);
1335 pass_arg0(this, arg_0);
1336 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1337 }
1338
1339 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1340 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1341 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1342 assert_different_registers(arg_2, c_rarg3);
1343 pass_arg3(this, arg_3);
1344 pass_arg2(this, arg_2);
1345 pass_arg1(this, arg_1);
1346 pass_arg0(this, arg_0);
1347 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1348 }
1349
1350 void MacroAssembler::get_vm_result_oop(Register oop_result) {
1351 movptr(oop_result, Address(r15_thread, JavaThread::vm_result_oop_offset()));
1352 movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
1353 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1354 }
1355
1356 void MacroAssembler::get_vm_result_metadata(Register metadata_result) {
1357 movptr(metadata_result, Address(r15_thread, JavaThread::vm_result_metadata_offset()));
1358 movptr(Address(r15_thread, JavaThread::vm_result_metadata_offset()), NULL_WORD);
1359 }
1360
1361 void MacroAssembler::check_and_handle_earlyret() {
1362 }
1363
1364 void MacroAssembler::check_and_handle_popframe() {
1365 }
1366
1367 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1368 assert(rscratch != noreg || always_reachable(src1), "missing");
1369
1370 if (reachable(src1)) {
1371 cmpl(as_Address(src1), imm);
1372 } else {
1373 lea(rscratch, src1);
1374 cmpl(Address(rscratch, 0), imm);
1375 }
1376 }
1377
1378 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1379 assert(!src2.is_lval(), "use cmpptr");
1380 assert(rscratch != noreg || always_reachable(src2), "missing");
1381
1382 if (reachable(src2)) {
1383 cmpl(src1, as_Address(src2));
1384 } else {
1385 lea(rscratch, src2);
1386 cmpl(src1, Address(rscratch, 0));
1387 }
1388 }
1389
1390 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1391 Assembler::cmpl(src1, imm);
1392 }
1393
1394 void MacroAssembler::cmp32(Register src1, Address src2) {
1395 Assembler::cmpl(src1, src2);
1396 }
1397
1398 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1399 ucomisd(opr1, opr2);
1400
1401 Label L;
1402 if (unordered_is_less) {
1403 movl(dst, -1);
1404 jcc(Assembler::parity, L);
1405 jcc(Assembler::below , L);
1406 movl(dst, 0);
1407 jcc(Assembler::equal , L);
1408 increment(dst);
1409 } else { // unordered is greater
1410 movl(dst, 1);
1411 jcc(Assembler::parity, L);
1412 jcc(Assembler::above , L);
1413 movl(dst, 0);
1414 jcc(Assembler::equal , L);
1415 decrementl(dst);
1416 }
1417 bind(L);
1418 }
1419
1420 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1421 ucomiss(opr1, opr2);
1422
1423 Label L;
1424 if (unordered_is_less) {
1425 movl(dst, -1);
1426 jcc(Assembler::parity, L);
1427 jcc(Assembler::below , L);
1428 movl(dst, 0);
1429 jcc(Assembler::equal , L);
1430 increment(dst);
1431 } else { // unordered is greater
1432 movl(dst, 1);
1433 jcc(Assembler::parity, L);
1434 jcc(Assembler::above , L);
1435 movl(dst, 0);
1436 jcc(Assembler::equal , L);
1437 decrementl(dst);
1438 }
1439 bind(L);
1440 }
1441
1442
1443 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1444 assert(rscratch != noreg || always_reachable(src1), "missing");
1445
1446 if (reachable(src1)) {
1447 cmpb(as_Address(src1), imm);
1448 } else {
1449 lea(rscratch, src1);
1450 cmpb(Address(rscratch, 0), imm);
1451 }
1452 }
1453
1454 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1455 assert(rscratch != noreg || always_reachable(src2), "missing");
1456
1457 if (src2.is_lval()) {
1458 movptr(rscratch, src2);
1459 Assembler::cmpq(src1, rscratch);
1460 } else if (reachable(src2)) {
1461 cmpq(src1, as_Address(src2));
1462 } else {
1463 lea(rscratch, src2);
1464 Assembler::cmpq(src1, Address(rscratch, 0));
1465 }
1466 }
1467
1468 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1469 assert(src2.is_lval(), "not a mem-mem compare");
1470 // moves src2's literal address
1471 movptr(rscratch, src2);
1472 Assembler::cmpq(src1, rscratch);
1473 }
1474
1475 void MacroAssembler::cmpoop(Register src1, Register src2) {
1476 cmpptr(src1, src2);
1477 }
1478
1479 void MacroAssembler::cmpoop(Register src1, Address src2) {
1480 cmpptr(src1, src2);
1481 }
1482
1483 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1484 movoop(rscratch, src2);
1485 cmpptr(src1, rscratch);
1486 }
1487
1488 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1489 assert(rscratch != noreg || always_reachable(adr), "missing");
1490
1491 if (reachable(adr)) {
1492 lock();
1493 cmpxchgptr(reg, as_Address(adr));
1494 } else {
1495 lea(rscratch, adr);
1496 lock();
1497 cmpxchgptr(reg, Address(rscratch, 0));
1498 }
1499 }
1500
1501 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1502 cmpxchgq(reg, adr);
1503 }
1504
1505 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1506 assert(rscratch != noreg || always_reachable(src), "missing");
1507
1508 if (reachable(src)) {
1509 Assembler::comisd(dst, as_Address(src));
1510 } else {
1511 lea(rscratch, src);
1512 Assembler::comisd(dst, Address(rscratch, 0));
1513 }
1514 }
1515
1516 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1517 assert(rscratch != noreg || always_reachable(src), "missing");
1518
1519 if (reachable(src)) {
1520 Assembler::comiss(dst, as_Address(src));
1521 } else {
1522 lea(rscratch, src);
1523 Assembler::comiss(dst, Address(rscratch, 0));
1524 }
1525 }
1526
1527
1528 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1529 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1530
1531 Condition negated_cond = negate_condition(cond);
1532 Label L;
1533 jcc(negated_cond, L);
1534 pushf(); // Preserve flags
1535 atomic_incl(counter_addr, rscratch);
1536 popf();
1537 bind(L);
1538 }
1539
1540 int MacroAssembler::corrected_idivl(Register reg) {
1541 // Full implementation of Java idiv and irem; checks for
1542 // special case as described in JVM spec., p.243 & p.271.
1543 // The function returns the (pc) offset of the idivl
1544 // instruction - may be needed for implicit exceptions.
1545 //
1546 // normal case special case
1547 //
1548 // input : rax,: dividend min_int
1549 // reg: divisor (may not be rax,/rdx) -1
1550 //
1551 // output: rax,: quotient (= rax, idiv reg) min_int
1552 // rdx: remainder (= rax, irem reg) 0
1553 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1554 const int min_int = 0x80000000;
1555 Label normal_case, special_case;
1556
1557 // check for special case
1558 cmpl(rax, min_int);
1559 jcc(Assembler::notEqual, normal_case);
1560 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1561 cmpl(reg, -1);
1562 jcc(Assembler::equal, special_case);
1563
1564 // handle normal case
1565 bind(normal_case);
1566 cdql();
1567 int idivl_offset = offset();
1568 idivl(reg);
1569
1570 // normal and special case exit
1571 bind(special_case);
1572
1573 return idivl_offset;
1574 }
1575
1576
1577
1578 void MacroAssembler::decrementl(Register reg, int value) {
1579 if (value == min_jint) {subl(reg, value) ; return; }
1580 if (value < 0) { incrementl(reg, -value); return; }
1581 if (value == 0) { ; return; }
1582 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1583 /* else */ { subl(reg, value) ; return; }
1584 }
1585
1586 void MacroAssembler::decrementl(Address dst, int value) {
1587 if (value == min_jint) {subl(dst, value) ; return; }
1588 if (value < 0) { incrementl(dst, -value); return; }
1589 if (value == 0) { ; return; }
1590 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1591 /* else */ { subl(dst, value) ; return; }
1592 }
1593
1594 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1595 assert(shift_value > 0, "illegal shift value");
1596 Label _is_positive;
1597 testl (reg, reg);
1598 jcc (Assembler::positive, _is_positive);
1599 int offset = (1 << shift_value) - 1 ;
1600
1601 if (offset == 1) {
1602 incrementl(reg);
1603 } else {
1604 addl(reg, offset);
1605 }
1606
1607 bind (_is_positive);
1608 sarl(reg, shift_value);
1609 }
1610
1611 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1612 assert(rscratch != noreg || always_reachable(src), "missing");
1613
1614 if (reachable(src)) {
1615 Assembler::divsd(dst, as_Address(src));
1616 } else {
1617 lea(rscratch, src);
1618 Assembler::divsd(dst, Address(rscratch, 0));
1619 }
1620 }
1621
1622 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1623 assert(rscratch != noreg || always_reachable(src), "missing");
1624
1625 if (reachable(src)) {
1626 Assembler::divss(dst, as_Address(src));
1627 } else {
1628 lea(rscratch, src);
1629 Assembler::divss(dst, Address(rscratch, 0));
1630 }
1631 }
1632
1633 void MacroAssembler::enter() {
1634 push(rbp);
1635 mov(rbp, rsp);
1636 }
1637
1638 void MacroAssembler::post_call_nop() {
1639 if (!Continuations::enabled()) {
1640 return;
1641 }
1642 InstructionMark im(this);
1643 relocate(post_call_nop_Relocation::spec());
1644 InlineSkippedInstructionsCounter skipCounter(this);
1645 emit_int8((uint8_t)0x0f);
1646 emit_int8((uint8_t)0x1f);
1647 emit_int8((uint8_t)0x84);
1648 emit_int8((uint8_t)0x00);
1649 emit_int32(0x00);
1650 }
1651
1652 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1653 assert(rscratch != noreg || always_reachable(src), "missing");
1654 if (reachable(src)) {
1655 Assembler::mulpd(dst, as_Address(src));
1656 } else {
1657 lea(rscratch, src);
1658 Assembler::mulpd(dst, Address(rscratch, 0));
1659 }
1660 }
1661
1662 // dst = c = a * b + c
1663 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1664 Assembler::vfmadd231sd(c, a, b);
1665 if (dst != c) {
1666 movdbl(dst, c);
1667 }
1668 }
1669
1670 // dst = c = a * b + c
1671 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1672 Assembler::vfmadd231ss(c, a, b);
1673 if (dst != c) {
1674 movflt(dst, c);
1675 }
1676 }
1677
1678 // dst = c = a * b + c
1679 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1680 Assembler::vfmadd231pd(c, a, b, vector_len);
1681 if (dst != c) {
1682 vmovdqu(dst, c);
1683 }
1684 }
1685
1686 // dst = c = a * b + c
1687 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1688 Assembler::vfmadd231ps(c, a, b, vector_len);
1689 if (dst != c) {
1690 vmovdqu(dst, c);
1691 }
1692 }
1693
1694 // dst = c = a * b + c
1695 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1696 Assembler::vfmadd231pd(c, a, b, vector_len);
1697 if (dst != c) {
1698 vmovdqu(dst, c);
1699 }
1700 }
1701
1702 // dst = c = a * b + c
1703 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1704 Assembler::vfmadd231ps(c, a, b, vector_len);
1705 if (dst != c) {
1706 vmovdqu(dst, c);
1707 }
1708 }
1709
1710 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
1711 assert(rscratch != noreg || always_reachable(dst), "missing");
1712
1713 if (reachable(dst)) {
1714 incrementl(as_Address(dst));
1715 } else {
1716 lea(rscratch, dst);
1717 incrementl(Address(rscratch, 0));
1718 }
1719 }
1720
1721 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
1722 incrementl(as_Address(dst, rscratch));
1723 }
1724
1725 void MacroAssembler::incrementl(Register reg, int value) {
1726 if (value == min_jint) {addl(reg, value) ; return; }
1727 if (value < 0) { decrementl(reg, -value); return; }
1728 if (value == 0) { ; return; }
1729 if (value == 1 && UseIncDec) { incl(reg) ; return; }
1730 /* else */ { addl(reg, value) ; return; }
1731 }
1732
1733 void MacroAssembler::incrementl(Address dst, int value) {
1734 if (value == min_jint) {addl(dst, value) ; return; }
1735 if (value < 0) { decrementl(dst, -value); return; }
1736 if (value == 0) { ; return; }
1737 if (value == 1 && UseIncDec) { incl(dst) ; return; }
1738 /* else */ { addl(dst, value) ; return; }
1739 }
1740
1741 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
1742 assert(rscratch != noreg || always_reachable(dst), "missing");
1743 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
1744 if (reachable(dst)) {
1745 jmp_literal(dst.target(), dst.rspec());
1746 } else {
1747 lea(rscratch, dst);
1748 jmp(rscratch);
1749 }
1750 }
1751
1752 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
1753 assert(rscratch != noreg || always_reachable(dst), "missing");
1754 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
1755 if (reachable(dst)) {
1756 InstructionMark im(this);
1757 relocate(dst.reloc());
1758 const int short_size = 2;
1759 const int long_size = 6;
1760 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
1761 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
1762 // 0111 tttn #8-bit disp
1763 emit_int8(0x70 | cc);
1764 emit_int8((offs - short_size) & 0xFF);
1765 } else {
1766 // 0000 1111 1000 tttn #32-bit disp
1767 emit_int8(0x0F);
1768 emit_int8((unsigned char)(0x80 | cc));
1769 emit_int32(offs - long_size);
1770 }
1771 } else {
1772 #ifdef ASSERT
1773 warning("reversing conditional branch");
1774 #endif /* ASSERT */
1775 Label skip;
1776 jccb(reverse[cc], skip);
1777 lea(rscratch, dst);
1778 Assembler::jmp(rscratch);
1779 bind(skip);
1780 }
1781 }
1782
1783 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
1784 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
1785 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
1786
1787 stmxcsr(mxcsr_save);
1788 movl(tmp, mxcsr_save);
1789 if (EnableX86ECoreOpts) {
1790 // The mxcsr_std has status bits set for performance on ECore
1791 orl(tmp, 0x003f);
1792 } else {
1793 // Mask out status bits (only check control and mask bits)
1794 andl(tmp, 0xFFC0);
1795 }
1796 cmp32(tmp, mxcsr_std, rscratch);
1797 }
1798
1799 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
1800 assert(rscratch != noreg || always_reachable(src), "missing");
1801
1802 if (reachable(src)) {
1803 Assembler::ldmxcsr(as_Address(src));
1804 } else {
1805 lea(rscratch, src);
1806 Assembler::ldmxcsr(Address(rscratch, 0));
1807 }
1808 }
1809
1810 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1811 int off = offset();
1812 movsbl(dst, src); // movsxb
1813 return off;
1814 }
1815
1816 // Note: load_signed_short used to be called load_signed_word.
1817 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
1818 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
1819 // The term "word" in HotSpot means a 32- or 64-bit machine word.
1820 int MacroAssembler::load_signed_short(Register dst, Address src) {
1821 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
1822 // version but this is what 64bit has always done. This seems to imply
1823 // that users are only using 32bits worth.
1824 int off = offset();
1825 movswl(dst, src); // movsxw
1826 return off;
1827 }
1828
1829 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1830 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1831 // and "3.9 Partial Register Penalties", p. 22).
1832 int off = offset();
1833 movzbl(dst, src); // movzxb
1834 return off;
1835 }
1836
1837 // Note: load_unsigned_short used to be called load_unsigned_word.
1838 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1839 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1840 // and "3.9 Partial Register Penalties", p. 22).
1841 int off = offset();
1842 movzwl(dst, src); // movzxw
1843 return off;
1844 }
1845
1846 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1847 switch (size_in_bytes) {
1848 case 8: movq(dst, src); break;
1849 case 4: movl(dst, src); break;
1850 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1851 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1852 default: ShouldNotReachHere();
1853 }
1854 }
1855
1856 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1857 switch (size_in_bytes) {
1858 case 8: movq(dst, src); break;
1859 case 4: movl(dst, src); break;
1860 case 2: movw(dst, src); break;
1861 case 1: movb(dst, src); break;
1862 default: ShouldNotReachHere();
1863 }
1864 }
1865
1866 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
1867 assert(rscratch != noreg || always_reachable(dst), "missing");
1868
1869 if (reachable(dst)) {
1870 movl(as_Address(dst), src);
1871 } else {
1872 lea(rscratch, dst);
1873 movl(Address(rscratch, 0), src);
1874 }
1875 }
1876
1877 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
1878 if (reachable(src)) {
1879 movl(dst, as_Address(src));
1880 } else {
1881 lea(dst, src);
1882 movl(dst, Address(dst, 0));
1883 }
1884 }
1885
1886 // C++ bool manipulation
1887
1888 void MacroAssembler::movbool(Register dst, Address src) {
1889 if(sizeof(bool) == 1)
1890 movb(dst, src);
1891 else if(sizeof(bool) == 2)
1892 movw(dst, src);
1893 else if(sizeof(bool) == 4)
1894 movl(dst, src);
1895 else
1896 // unsupported
1897 ShouldNotReachHere();
1898 }
1899
1900 void MacroAssembler::movbool(Address dst, bool boolconst) {
1901 if(sizeof(bool) == 1)
1902 movb(dst, (int) boolconst);
1903 else if(sizeof(bool) == 2)
1904 movw(dst, (int) boolconst);
1905 else if(sizeof(bool) == 4)
1906 movl(dst, (int) boolconst);
1907 else
1908 // unsupported
1909 ShouldNotReachHere();
1910 }
1911
1912 void MacroAssembler::movbool(Address dst, Register src) {
1913 if(sizeof(bool) == 1)
1914 movb(dst, src);
1915 else if(sizeof(bool) == 2)
1916 movw(dst, src);
1917 else if(sizeof(bool) == 4)
1918 movl(dst, src);
1919 else
1920 // unsupported
1921 ShouldNotReachHere();
1922 }
1923
1924 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1925 assert(rscratch != noreg || always_reachable(src), "missing");
1926
1927 if (reachable(src)) {
1928 movdl(dst, as_Address(src));
1929 } else {
1930 lea(rscratch, src);
1931 movdl(dst, Address(rscratch, 0));
1932 }
1933 }
1934
1935 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
1936 assert(rscratch != noreg || always_reachable(src), "missing");
1937
1938 if (reachable(src)) {
1939 movq(dst, as_Address(src));
1940 } else {
1941 lea(rscratch, src);
1942 movq(dst, Address(rscratch, 0));
1943 }
1944 }
1945
1946 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1947 assert(rscratch != noreg || always_reachable(src), "missing");
1948
1949 if (reachable(src)) {
1950 if (UseXmmLoadAndClearUpper) {
1951 movsd (dst, as_Address(src));
1952 } else {
1953 movlpd(dst, as_Address(src));
1954 }
1955 } else {
1956 lea(rscratch, src);
1957 if (UseXmmLoadAndClearUpper) {
1958 movsd (dst, Address(rscratch, 0));
1959 } else {
1960 movlpd(dst, Address(rscratch, 0));
1961 }
1962 }
1963 }
1964
1965 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
1966 assert(rscratch != noreg || always_reachable(src), "missing");
1967
1968 if (reachable(src)) {
1969 movss(dst, as_Address(src));
1970 } else {
1971 lea(rscratch, src);
1972 movss(dst, Address(rscratch, 0));
1973 }
1974 }
1975
1976 void MacroAssembler::mov64(Register dst, int64_t imm64) {
1977 if (is_uimm32(imm64)) {
1978 movl(dst, checked_cast<uint32_t>(imm64));
1979 } else if (is_simm32(imm64)) {
1980 movq(dst, checked_cast<int32_t>(imm64));
1981 } else {
1982 Assembler::mov64(dst, imm64);
1983 }
1984 }
1985
1986 void MacroAssembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) {
1987 Assembler::mov64(dst, imm64, rtype, format);
1988 }
1989
1990 void MacroAssembler::movptr(Register dst, Register src) {
1991 movq(dst, src);
1992 }
1993
1994 void MacroAssembler::movptr(Register dst, Address src) {
1995 movq(dst, src);
1996 }
1997
1998 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
1999 void MacroAssembler::movptr(Register dst, intptr_t src) {
2000 mov64(dst, src);
2001 }
2002
2003 void MacroAssembler::movptr(Address dst, Register src) {
2004 movq(dst, src);
2005 }
2006
2007 void MacroAssembler::movptr(Address dst, int32_t src) {
2008 movslq(dst, src);
2009 }
2010
2011 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2012 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2013 Assembler::movdqu(dst, src);
2014 }
2015
2016 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2017 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2018 Assembler::movdqu(dst, src);
2019 }
2020
2021 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2022 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2023 Assembler::movdqu(dst, src);
2024 }
2025
2026 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2027 assert(rscratch != noreg || always_reachable(src), "missing");
2028
2029 if (reachable(src)) {
2030 movdqu(dst, as_Address(src));
2031 } else {
2032 lea(rscratch, src);
2033 movdqu(dst, Address(rscratch, 0));
2034 }
2035 }
2036
2037 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2038 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2039 Assembler::vmovdqu(dst, src);
2040 }
2041
2042 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2043 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2044 Assembler::vmovdqu(dst, src);
2045 }
2046
2047 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2048 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2049 Assembler::vmovdqu(dst, src);
2050 }
2051
2052 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2053 assert(rscratch != noreg || always_reachable(src), "missing");
2054
2055 if (reachable(src)) {
2056 vmovdqu(dst, as_Address(src));
2057 }
2058 else {
2059 lea(rscratch, src);
2060 vmovdqu(dst, Address(rscratch, 0));
2061 }
2062 }
2063
2064 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2065 assert(rscratch != noreg || always_reachable(src), "missing");
2066
2067 if (vector_len == AVX_512bit) {
2068 evmovdquq(dst, src, AVX_512bit, rscratch);
2069 } else if (vector_len == AVX_256bit) {
2070 vmovdqu(dst, src, rscratch);
2071 } else {
2072 movdqu(dst, src, rscratch);
2073 }
2074 }
2075
2076 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2077 if (vector_len == AVX_512bit) {
2078 evmovdquq(dst, src, AVX_512bit);
2079 } else if (vector_len == AVX_256bit) {
2080 vmovdqu(dst, src);
2081 } else {
2082 movdqu(dst, src);
2083 }
2084 }
2085
2086 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2087 if (vector_len == AVX_512bit) {
2088 evmovdquq(dst, src, AVX_512bit);
2089 } else if (vector_len == AVX_256bit) {
2090 vmovdqu(dst, src);
2091 } else {
2092 movdqu(dst, src);
2093 }
2094 }
2095
2096 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2097 if (vector_len == AVX_512bit) {
2098 evmovdquq(dst, src, AVX_512bit);
2099 } else if (vector_len == AVX_256bit) {
2100 vmovdqu(dst, src);
2101 } else {
2102 movdqu(dst, src);
2103 }
2104 }
2105
2106 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2107 assert(rscratch != noreg || always_reachable(src), "missing");
2108
2109 if (reachable(src)) {
2110 vmovdqa(dst, as_Address(src));
2111 }
2112 else {
2113 lea(rscratch, src);
2114 vmovdqa(dst, Address(rscratch, 0));
2115 }
2116 }
2117
2118 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2119 assert(rscratch != noreg || always_reachable(src), "missing");
2120
2121 if (vector_len == AVX_512bit) {
2122 evmovdqaq(dst, src, AVX_512bit, rscratch);
2123 } else if (vector_len == AVX_256bit) {
2124 vmovdqa(dst, src, rscratch);
2125 } else {
2126 movdqa(dst, src, rscratch);
2127 }
2128 }
2129
2130 void MacroAssembler::kmov(KRegister dst, Address src) {
2131 if (VM_Version::supports_avx512bw()) {
2132 kmovql(dst, src);
2133 } else {
2134 assert(VM_Version::supports_evex(), "");
2135 kmovwl(dst, src);
2136 }
2137 }
2138
2139 void MacroAssembler::kmov(Address dst, KRegister src) {
2140 if (VM_Version::supports_avx512bw()) {
2141 kmovql(dst, src);
2142 } else {
2143 assert(VM_Version::supports_evex(), "");
2144 kmovwl(dst, src);
2145 }
2146 }
2147
2148 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2149 if (VM_Version::supports_avx512bw()) {
2150 kmovql(dst, src);
2151 } else {
2152 assert(VM_Version::supports_evex(), "");
2153 kmovwl(dst, src);
2154 }
2155 }
2156
2157 void MacroAssembler::kmov(Register dst, KRegister src) {
2158 if (VM_Version::supports_avx512bw()) {
2159 kmovql(dst, src);
2160 } else {
2161 assert(VM_Version::supports_evex(), "");
2162 kmovwl(dst, src);
2163 }
2164 }
2165
2166 void MacroAssembler::kmov(KRegister dst, Register src) {
2167 if (VM_Version::supports_avx512bw()) {
2168 kmovql(dst, src);
2169 } else {
2170 assert(VM_Version::supports_evex(), "");
2171 kmovwl(dst, src);
2172 }
2173 }
2174
2175 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2176 assert(rscratch != noreg || always_reachable(src), "missing");
2177
2178 if (reachable(src)) {
2179 kmovql(dst, as_Address(src));
2180 } else {
2181 lea(rscratch, src);
2182 kmovql(dst, Address(rscratch, 0));
2183 }
2184 }
2185
2186 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2187 assert(rscratch != noreg || always_reachable(src), "missing");
2188
2189 if (reachable(src)) {
2190 kmovwl(dst, as_Address(src));
2191 } else {
2192 lea(rscratch, src);
2193 kmovwl(dst, Address(rscratch, 0));
2194 }
2195 }
2196
2197 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2198 int vector_len, Register rscratch) {
2199 assert(rscratch != noreg || always_reachable(src), "missing");
2200
2201 if (reachable(src)) {
2202 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2203 } else {
2204 lea(rscratch, src);
2205 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2206 }
2207 }
2208
2209 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2210 int vector_len, Register rscratch) {
2211 assert(rscratch != noreg || always_reachable(src), "missing");
2212
2213 if (reachable(src)) {
2214 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2215 } else {
2216 lea(rscratch, src);
2217 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2218 }
2219 }
2220
2221 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2222 assert(rscratch != noreg || always_reachable(src), "missing");
2223
2224 if (reachable(src)) {
2225 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2226 } else {
2227 lea(rscratch, src);
2228 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2229 }
2230 }
2231
2232 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2233 assert(rscratch != noreg || always_reachable(src), "missing");
2234
2235 if (reachable(src)) {
2236 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2237 } else {
2238 lea(rscratch, src);
2239 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2240 }
2241 }
2242
2243 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2244 assert(rscratch != noreg || always_reachable(src), "missing");
2245
2246 if (reachable(src)) {
2247 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2248 } else {
2249 lea(rscratch, src);
2250 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2251 }
2252 }
2253
2254 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2255 assert(rscratch != noreg || always_reachable(src), "missing");
2256
2257 if (reachable(src)) {
2258 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2259 } else {
2260 lea(rscratch, src);
2261 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2262 }
2263 }
2264
2265 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2266 assert(rscratch != noreg || always_reachable(src), "missing");
2267
2268 if (reachable(src)) {
2269 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2270 } else {
2271 lea(rscratch, src);
2272 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2273 }
2274 }
2275
2276 void MacroAssembler::movapd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2277 assert(rscratch != noreg || always_reachable(src), "missing");
2278
2279 if (reachable(src)) {
2280 Assembler::movapd(dst, as_Address(src));
2281 } else {
2282 lea(rscratch, src);
2283 Assembler::movapd(dst, Address(rscratch, 0));
2284 }
2285 }
2286
2287 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2288 assert(rscratch != noreg || always_reachable(src), "missing");
2289
2290 if (reachable(src)) {
2291 Assembler::movdqa(dst, as_Address(src));
2292 } else {
2293 lea(rscratch, src);
2294 Assembler::movdqa(dst, Address(rscratch, 0));
2295 }
2296 }
2297
2298 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2299 assert(rscratch != noreg || always_reachable(src), "missing");
2300
2301 if (reachable(src)) {
2302 Assembler::movsd(dst, as_Address(src));
2303 } else {
2304 lea(rscratch, src);
2305 Assembler::movsd(dst, Address(rscratch, 0));
2306 }
2307 }
2308
2309 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2310 assert(rscratch != noreg || always_reachable(src), "missing");
2311
2312 if (reachable(src)) {
2313 Assembler::movss(dst, as_Address(src));
2314 } else {
2315 lea(rscratch, src);
2316 Assembler::movss(dst, Address(rscratch, 0));
2317 }
2318 }
2319
2320 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2321 assert(rscratch != noreg || always_reachable(src), "missing");
2322
2323 if (reachable(src)) {
2324 Assembler::movddup(dst, as_Address(src));
2325 } else {
2326 lea(rscratch, src);
2327 Assembler::movddup(dst, Address(rscratch, 0));
2328 }
2329 }
2330
2331 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2332 assert(rscratch != noreg || always_reachable(src), "missing");
2333
2334 if (reachable(src)) {
2335 Assembler::vmovddup(dst, as_Address(src), vector_len);
2336 } else {
2337 lea(rscratch, src);
2338 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2339 }
2340 }
2341
2342 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2343 assert(rscratch != noreg || always_reachable(src), "missing");
2344
2345 if (reachable(src)) {
2346 Assembler::mulsd(dst, as_Address(src));
2347 } else {
2348 lea(rscratch, src);
2349 Assembler::mulsd(dst, Address(rscratch, 0));
2350 }
2351 }
2352
2353 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2354 assert(rscratch != noreg || always_reachable(src), "missing");
2355
2356 if (reachable(src)) {
2357 Assembler::mulss(dst, as_Address(src));
2358 } else {
2359 lea(rscratch, src);
2360 Assembler::mulss(dst, Address(rscratch, 0));
2361 }
2362 }
2363
2364 void MacroAssembler::null_check(Register reg, int offset) {
2365 if (needs_explicit_null_check(offset)) {
2366 // provoke OS null exception if reg is null by
2367 // accessing M[reg] w/o changing any (non-CC) registers
2368 // NOTE: cmpl is plenty here to provoke a segv
2369 cmpptr(rax, Address(reg, 0));
2370 // Note: should probably use testl(rax, Address(reg, 0));
2371 // may be shorter code (however, this version of
2372 // testl needs to be implemented first)
2373 } else {
2374 // nothing to do, (later) access of M[reg + offset]
2375 // will provoke OS null exception if reg is null
2376 }
2377 }
2378
2379 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2380 andptr(markword, markWord::inline_type_mask_in_place);
2381 cmpptr(markword, markWord::inline_type_pattern);
2382 jcc(Assembler::equal, is_inline_type);
2383 }
2384
2385 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null) {
2386 if (can_be_null) {
2387 testptr(object, object);
2388 jcc(Assembler::zero, not_inline_type);
2389 }
2390 const int is_inline_type_mask = markWord::inline_type_pattern;
2391 movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2392 andptr(tmp, is_inline_type_mask);
2393 cmpptr(tmp, is_inline_type_mask);
2394 jcc(Assembler::notEqual, not_inline_type);
2395 }
2396
2397 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2398 movl(temp_reg, flags);
2399 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2400 jcc(Assembler::notEqual, is_null_free_inline_type);
2401 }
2402
2403 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2404 movl(temp_reg, flags);
2405 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2406 jcc(Assembler::equal, not_null_free_inline_type);
2407 }
2408
2409 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2410 movl(temp_reg, flags);
2411 testl(temp_reg, 1 << ResolvedFieldEntry::is_flat_shift);
2412 jcc(Assembler::notEqual, is_flat);
2413 }
2414
2415 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2416 movl(temp_reg, flags);
2417 testl(temp_reg, 1 << ResolvedFieldEntry::has_null_marker_shift);
2418 jcc(Assembler::notEqual, has_null_marker);
2419 }
2420
2421 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2422 Label test_mark_word;
2423 // load mark word
2424 movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2425 // check displaced
2426 testl(temp_reg, markWord::unlocked_value);
2427 jccb(Assembler::notZero, test_mark_word);
2428 // slow path use klass prototype
2429 push(rscratch1);
2430 load_prototype_header(temp_reg, oop, rscratch1);
2431 pop(rscratch1);
2432
2433 bind(test_mark_word);
2434 testl(temp_reg, test_bit);
2435 jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
2436 }
2437
2438 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg,
2439 Label& is_flat_array) {
2440 #ifdef _LP64
2441 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2442 #else
2443 load_klass(temp_reg, oop, noreg);
2444 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
2445 test_flat_array_layout(temp_reg, is_flat_array);
2446 #endif
2447 }
2448
2449 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2450 Label& is_non_flat_array) {
2451 #ifdef _LP64
2452 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2453 #else
2454 load_klass(temp_reg, oop, noreg);
2455 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
2456 test_non_flat_array_layout(temp_reg, is_non_flat_array);
2457 #endif
2458 }
2459
2460 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
2461 #ifdef _LP64
2462 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2463 #else
2464 Unimplemented();
2465 #endif
2466 }
2467
2468 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2469 #ifdef _LP64
2470 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2471 #else
2472 Unimplemented();
2473 #endif
2474 }
2475
2476 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2477 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2478 jcc(Assembler::notZero, is_flat_array);
2479 }
2480
2481 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
2482 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2483 jcc(Assembler::zero, is_non_flat_array);
2484 }
2485
2486 void MacroAssembler::os_breakpoint() {
2487 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2488 // (e.g., MSVC can't call ps() otherwise)
2489 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2490 }
2491
2492 void MacroAssembler::unimplemented(const char* what) {
2493 const char* buf = nullptr;
2494 {
2495 ResourceMark rm;
2496 stringStream ss;
2497 ss.print("unimplemented: %s", what);
2498 buf = code_string(ss.as_string());
2499 }
2500 stop(buf);
2501 }
2502
2503 #define XSTATE_BV 0x200
2504
2505 void MacroAssembler::pop_CPU_state() {
2506 pop_FPU_state();
2507 pop_IU_state();
2508 }
2509
2510 void MacroAssembler::pop_FPU_state() {
2511 fxrstor(Address(rsp, 0));
2512 addptr(rsp, FPUStateSizeInWords * wordSize);
2513 }
2514
2515 void MacroAssembler::pop_IU_state() {
2516 popa();
2517 addq(rsp, 8);
2518 popf();
2519 }
2520
2521 // Save Integer and Float state
2522 // Warning: Stack must be 16 byte aligned (64bit)
2523 void MacroAssembler::push_CPU_state() {
2524 push_IU_state();
2525 push_FPU_state();
2526 }
2527
2528 void MacroAssembler::push_FPU_state() {
2529 subptr(rsp, FPUStateSizeInWords * wordSize);
2530 fxsave(Address(rsp, 0));
2531 }
2532
2533 void MacroAssembler::push_IU_state() {
2534 // Push flags first because pusha kills them
2535 pushf();
2536 // Make sure rsp stays 16-byte aligned
2537 subq(rsp, 8);
2538 pusha();
2539 }
2540
2541 void MacroAssembler::push_cont_fastpath() {
2542 if (!Continuations::enabled()) return;
2543
2544 Label L_done;
2545 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2546 jccb(Assembler::belowEqual, L_done);
2547 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), rsp);
2548 bind(L_done);
2549 }
2550
2551 void MacroAssembler::pop_cont_fastpath() {
2552 if (!Continuations::enabled()) return;
2553
2554 Label L_done;
2555 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2556 jccb(Assembler::below, L_done);
2557 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), 0);
2558 bind(L_done);
2559 }
2560
2561 #ifdef ASSERT
2562 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2563 Label no_cont;
2564 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2565 testl(cont, cont);
2566 jcc(Assembler::zero, no_cont);
2567 stop(name);
2568 bind(no_cont);
2569 }
2570 #endif
2571
2572 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { // determine java_thread register
2573 // we must set sp to zero to clear frame
2574 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2575 // must clear fp, so that compiled frames are not confused; it is
2576 // possible that we need it only for debugging
2577 if (clear_fp) {
2578 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2579 }
2580 // Always clear the pc because it could have been set by make_walkable()
2581 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2582 vzeroupper();
2583 }
2584
2585 void MacroAssembler::round_to(Register reg, int modulus) {
2586 addptr(reg, modulus - 1);
2587 andptr(reg, -modulus);
2588 }
2589
2590 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod) {
2591 if (at_return) {
2592 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2593 // we may safely use rsp instead to perform the stack watermark check.
2594 cmpptr(in_nmethod ? rsp : rbp, Address(r15_thread, JavaThread::polling_word_offset()));
2595 jcc(Assembler::above, slow_path);
2596 return;
2597 }
2598 testb(Address(r15_thread, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2599 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2600 }
2601
2602 // Calls to C land
2603 //
2604 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2605 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2606 // has to be reset to 0. This is required to allow proper stack traversal.
2607 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2608 Register last_java_fp,
2609 address last_java_pc,
2610 Register rscratch) {
2611 vzeroupper();
2612 // determine last_java_sp register
2613 if (!last_java_sp->is_valid()) {
2614 last_java_sp = rsp;
2615 }
2616 // last_java_fp is optional
2617 if (last_java_fp->is_valid()) {
2618 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2619 }
2620 // last_java_pc is optional
2621 if (last_java_pc != nullptr) {
2622 Address java_pc(r15_thread,
2623 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
2624 lea(java_pc, InternalAddress(last_java_pc), rscratch);
2625 }
2626 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2627 }
2628
2629 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2630 Register last_java_fp,
2631 Label &L,
2632 Register scratch) {
2633 lea(scratch, L);
2634 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
2635 set_last_Java_frame(last_java_sp, last_java_fp, nullptr, scratch);
2636 }
2637
2638 void MacroAssembler::shlptr(Register dst, int imm8) {
2639 shlq(dst, imm8);
2640 }
2641
2642 void MacroAssembler::shrptr(Register dst, int imm8) {
2643 shrq(dst, imm8);
2644 }
2645
2646 void MacroAssembler::sign_extend_byte(Register reg) {
2647 movsbl(reg, reg); // movsxb
2648 }
2649
2650 void MacroAssembler::sign_extend_short(Register reg) {
2651 movswl(reg, reg); // movsxw
2652 }
2653
2654 void MacroAssembler::testl(Address dst, int32_t imm32) {
2655 if (imm32 >= 0 && is8bit(imm32)) {
2656 testb(dst, imm32);
2657 } else {
2658 Assembler::testl(dst, imm32);
2659 }
2660 }
2661
2662 void MacroAssembler::testl(Register dst, int32_t imm32) {
2663 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
2664 testb(dst, imm32);
2665 } else {
2666 Assembler::testl(dst, imm32);
2667 }
2668 }
2669
2670 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2671 assert(always_reachable(src), "Address should be reachable");
2672 testl(dst, as_Address(src));
2673 }
2674
2675 void MacroAssembler::testq(Address dst, int32_t imm32) {
2676 if (imm32 >= 0) {
2677 testl(dst, imm32);
2678 } else {
2679 Assembler::testq(dst, imm32);
2680 }
2681 }
2682
2683 void MacroAssembler::testq(Register dst, int32_t imm32) {
2684 if (imm32 >= 0) {
2685 testl(dst, imm32);
2686 } else {
2687 Assembler::testq(dst, imm32);
2688 }
2689 }
2690
2691 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2692 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2693 Assembler::pcmpeqb(dst, src);
2694 }
2695
2696 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2697 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2698 Assembler::pcmpeqw(dst, src);
2699 }
2700
2701 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2702 assert((dst->encoding() < 16),"XMM register should be 0-15");
2703 Assembler::pcmpestri(dst, src, imm8);
2704 }
2705
2706 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2707 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2708 Assembler::pcmpestri(dst, src, imm8);
2709 }
2710
2711 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2712 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2713 Assembler::pmovzxbw(dst, src);
2714 }
2715
2716 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2717 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2718 Assembler::pmovzxbw(dst, src);
2719 }
2720
2721 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2722 assert((src->encoding() < 16),"XMM register should be 0-15");
2723 Assembler::pmovmskb(dst, src);
2724 }
2725
2726 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2727 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2728 Assembler::ptest(dst, src);
2729 }
2730
2731 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2732 assert(rscratch != noreg || always_reachable(src), "missing");
2733
2734 if (reachable(src)) {
2735 Assembler::sqrtss(dst, as_Address(src));
2736 } else {
2737 lea(rscratch, src);
2738 Assembler::sqrtss(dst, Address(rscratch, 0));
2739 }
2740 }
2741
2742 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2743 assert(rscratch != noreg || always_reachable(src), "missing");
2744
2745 if (reachable(src)) {
2746 Assembler::subsd(dst, as_Address(src));
2747 } else {
2748 lea(rscratch, src);
2749 Assembler::subsd(dst, Address(rscratch, 0));
2750 }
2751 }
2752
2753 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
2754 assert(rscratch != noreg || always_reachable(src), "missing");
2755
2756 if (reachable(src)) {
2757 Assembler::roundsd(dst, as_Address(src), rmode);
2758 } else {
2759 lea(rscratch, src);
2760 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
2761 }
2762 }
2763
2764 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2765 assert(rscratch != noreg || always_reachable(src), "missing");
2766
2767 if (reachable(src)) {
2768 Assembler::subss(dst, as_Address(src));
2769 } else {
2770 lea(rscratch, src);
2771 Assembler::subss(dst, Address(rscratch, 0));
2772 }
2773 }
2774
2775 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2776 assert(rscratch != noreg || always_reachable(src), "missing");
2777
2778 if (reachable(src)) {
2779 Assembler::ucomisd(dst, as_Address(src));
2780 } else {
2781 lea(rscratch, src);
2782 Assembler::ucomisd(dst, Address(rscratch, 0));
2783 }
2784 }
2785
2786 void MacroAssembler::vucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2787 assert(rscratch != noreg || always_reachable(src), "missing");
2788
2789 if (reachable(src)) {
2790 Assembler::vucomxsd(dst, as_Address(src));
2791 } else {
2792 lea(rscratch, src);
2793 Assembler::vucomxsd(dst, Address(rscratch, 0));
2794 }
2795 }
2796
2797 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2798 assert(rscratch != noreg || always_reachable(src), "missing");
2799
2800 if (reachable(src)) {
2801 Assembler::ucomiss(dst, as_Address(src));
2802 } else {
2803 lea(rscratch, src);
2804 Assembler::ucomiss(dst, Address(rscratch, 0));
2805 }
2806 }
2807
2808 void MacroAssembler::vucomxss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2809 assert(rscratch != noreg || always_reachable(src), "missing");
2810
2811 if (reachable(src)) {
2812 Assembler::vucomxss(dst, as_Address(src));
2813 } else {
2814 lea(rscratch, src);
2815 Assembler::vucomxss(dst, Address(rscratch, 0));
2816 }
2817 }
2818
2819 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2820 assert(rscratch != noreg || always_reachable(src), "missing");
2821
2822 // Used in sign-bit flipping with aligned address.
2823 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2824
2825 if (UseAVX > 2 &&
2826 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2827 (dst->encoding() >= 16)) {
2828 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2829 } else if (reachable(src)) {
2830 Assembler::xorpd(dst, as_Address(src));
2831 } else {
2832 lea(rscratch, src);
2833 Assembler::xorpd(dst, Address(rscratch, 0));
2834 }
2835 }
2836
2837 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
2838 if (UseAVX > 2 &&
2839 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2840 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2841 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2842 } else {
2843 Assembler::xorpd(dst, src);
2844 }
2845 }
2846
2847 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
2848 if (UseAVX > 2 &&
2849 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2850 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2851 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2852 } else {
2853 Assembler::xorps(dst, src);
2854 }
2855 }
2856
2857 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
2858 assert(rscratch != noreg || always_reachable(src), "missing");
2859
2860 // Used in sign-bit flipping with aligned address.
2861 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2862
2863 if (UseAVX > 2 &&
2864 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2865 (dst->encoding() >= 16)) {
2866 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2867 } else if (reachable(src)) {
2868 Assembler::xorps(dst, as_Address(src));
2869 } else {
2870 lea(rscratch, src);
2871 Assembler::xorps(dst, Address(rscratch, 0));
2872 }
2873 }
2874
2875 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
2876 assert(rscratch != noreg || always_reachable(src), "missing");
2877
2878 // Used in sign-bit flipping with aligned address.
2879 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
2880 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2881 if (reachable(src)) {
2882 Assembler::pshufb(dst, as_Address(src));
2883 } else {
2884 lea(rscratch, src);
2885 Assembler::pshufb(dst, Address(rscratch, 0));
2886 }
2887 }
2888
2889 // AVX 3-operands instructions
2890
2891 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2892 assert(rscratch != noreg || always_reachable(src), "missing");
2893
2894 if (reachable(src)) {
2895 vaddsd(dst, nds, as_Address(src));
2896 } else {
2897 lea(rscratch, src);
2898 vaddsd(dst, nds, Address(rscratch, 0));
2899 }
2900 }
2901
2902 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2903 assert(rscratch != noreg || always_reachable(src), "missing");
2904
2905 if (reachable(src)) {
2906 vaddss(dst, nds, as_Address(src));
2907 } else {
2908 lea(rscratch, src);
2909 vaddss(dst, nds, Address(rscratch, 0));
2910 }
2911 }
2912
2913 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2914 assert(UseAVX > 0, "requires some form of AVX");
2915 assert(rscratch != noreg || always_reachable(src), "missing");
2916
2917 if (reachable(src)) {
2918 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
2919 } else {
2920 lea(rscratch, src);
2921 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
2922 }
2923 }
2924
2925 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2926 assert(UseAVX > 0, "requires some form of AVX");
2927 assert(rscratch != noreg || always_reachable(src), "missing");
2928
2929 if (reachable(src)) {
2930 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
2931 } else {
2932 lea(rscratch, src);
2933 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
2934 }
2935 }
2936
2937 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2938 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2939 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2940
2941 vandps(dst, nds, negate_field, vector_len, rscratch);
2942 }
2943
2944 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2945 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2946 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2947
2948 vandpd(dst, nds, negate_field, vector_len, rscratch);
2949 }
2950
2951 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2952 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2953 Assembler::vpaddb(dst, nds, src, vector_len);
2954 }
2955
2956 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2957 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2958 Assembler::vpaddb(dst, nds, src, vector_len);
2959 }
2960
2961 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2962 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2963 Assembler::vpaddw(dst, nds, src, vector_len);
2964 }
2965
2966 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2967 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2968 Assembler::vpaddw(dst, nds, src, vector_len);
2969 }
2970
2971 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2972 assert(rscratch != noreg || always_reachable(src), "missing");
2973
2974 if (reachable(src)) {
2975 Assembler::vpand(dst, nds, as_Address(src), vector_len);
2976 } else {
2977 lea(rscratch, src);
2978 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
2979 }
2980 }
2981
2982 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2983 assert(rscratch != noreg || always_reachable(src), "missing");
2984
2985 if (reachable(src)) {
2986 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
2987 } else {
2988 lea(rscratch, src);
2989 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
2990 }
2991 }
2992
2993 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2994 assert(rscratch != noreg || always_reachable(src), "missing");
2995
2996 if (reachable(src)) {
2997 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
2998 } else {
2999 lea(rscratch, src);
3000 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3001 }
3002 }
3003
3004 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3005 assert(rscratch != noreg || always_reachable(src), "missing");
3006
3007 if (reachable(src)) {
3008 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3009 } else {
3010 lea(rscratch, src);
3011 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3012 }
3013 }
3014
3015 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3016 assert(rscratch != noreg || always_reachable(src), "missing");
3017
3018 if (reachable(src)) {
3019 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3020 } else {
3021 lea(rscratch, src);
3022 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3023 }
3024 }
3025
3026 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3027 assert(rscratch != noreg || always_reachable(src), "missing");
3028
3029 if (reachable(src)) {
3030 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3031 } else {
3032 lea(rscratch, src);
3033 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3034 }
3035 }
3036
3037 // Vector float blend
3038 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3039 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3040 // WARN: Allow dst == (src1|src2), mask == scratch
3041 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3042 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3043 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3044 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3045 if (blend_emulation && scratch_available && dst_available) {
3046 if (compute_mask) {
3047 vpsrad(scratch, mask, 32, vector_len);
3048 mask = scratch;
3049 }
3050 if (dst == src1) {
3051 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3052 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3053 } else {
3054 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3055 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3056 }
3057 vpor(dst, dst, scratch, vector_len);
3058 } else {
3059 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3060 }
3061 }
3062
3063 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3064 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3065 // WARN: Allow dst == (src1|src2), mask == scratch
3066 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3067 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3068 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3069 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3070 if (blend_emulation && scratch_available && dst_available) {
3071 if (compute_mask) {
3072 vpxor(scratch, scratch, scratch, vector_len);
3073 vpcmpgtq(scratch, scratch, mask, vector_len);
3074 mask = scratch;
3075 }
3076 if (dst == src1) {
3077 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3078 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3079 } else {
3080 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3081 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3082 }
3083 vpor(dst, dst, scratch, vector_len);
3084 } else {
3085 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3086 }
3087 }
3088
3089 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3090 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3091 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3092 }
3093
3094 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3095 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3096 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3097 }
3098
3099 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3100 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3101 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3102 }
3103
3104 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3105 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3106 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3107 }
3108
3109 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3110 assert(rscratch != noreg || always_reachable(src), "missing");
3111
3112 if (reachable(src)) {
3113 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3114 } else {
3115 lea(rscratch, src);
3116 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3117 }
3118 }
3119
3120 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3121 int comparison, bool is_signed, int vector_len, Register rscratch) {
3122 assert(rscratch != noreg || always_reachable(src), "missing");
3123
3124 if (reachable(src)) {
3125 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3126 } else {
3127 lea(rscratch, src);
3128 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3129 }
3130 }
3131
3132 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3133 int comparison, bool is_signed, int vector_len, Register rscratch) {
3134 assert(rscratch != noreg || always_reachable(src), "missing");
3135
3136 if (reachable(src)) {
3137 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3138 } else {
3139 lea(rscratch, src);
3140 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3141 }
3142 }
3143
3144 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3145 int comparison, bool is_signed, int vector_len, Register rscratch) {
3146 assert(rscratch != noreg || always_reachable(src), "missing");
3147
3148 if (reachable(src)) {
3149 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3150 } else {
3151 lea(rscratch, src);
3152 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3153 }
3154 }
3155
3156 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3157 int comparison, bool is_signed, int vector_len, Register rscratch) {
3158 assert(rscratch != noreg || always_reachable(src), "missing");
3159
3160 if (reachable(src)) {
3161 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3162 } else {
3163 lea(rscratch, src);
3164 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3165 }
3166 }
3167
3168 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3169 if (width == Assembler::Q) {
3170 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3171 } else {
3172 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3173 }
3174 }
3175
3176 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3177 int eq_cond_enc = 0x29;
3178 int gt_cond_enc = 0x37;
3179 if (width != Assembler::Q) {
3180 eq_cond_enc = 0x74 + width;
3181 gt_cond_enc = 0x64 + width;
3182 }
3183 switch (cond) {
3184 case eq:
3185 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3186 break;
3187 case neq:
3188 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3189 vallones(xtmp, vector_len);
3190 vpxor(dst, xtmp, dst, vector_len);
3191 break;
3192 case le:
3193 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3194 vallones(xtmp, vector_len);
3195 vpxor(dst, xtmp, dst, vector_len);
3196 break;
3197 case nlt:
3198 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3199 vallones(xtmp, vector_len);
3200 vpxor(dst, xtmp, dst, vector_len);
3201 break;
3202 case lt:
3203 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3204 break;
3205 case nle:
3206 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3207 break;
3208 default:
3209 assert(false, "Should not reach here");
3210 }
3211 }
3212
3213 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3214 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3215 Assembler::vpmovzxbw(dst, src, vector_len);
3216 }
3217
3218 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3219 assert((src->encoding() < 16),"XMM register should be 0-15");
3220 Assembler::vpmovmskb(dst, src, vector_len);
3221 }
3222
3223 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3224 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3225 Assembler::vpmullw(dst, nds, src, vector_len);
3226 }
3227
3228 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3229 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3230 Assembler::vpmullw(dst, nds, src, vector_len);
3231 }
3232
3233 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3234 assert((UseAVX > 0), "AVX support is needed");
3235 assert(rscratch != noreg || always_reachable(src), "missing");
3236
3237 if (reachable(src)) {
3238 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3239 } else {
3240 lea(rscratch, src);
3241 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3242 }
3243 }
3244
3245 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3246 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3247 Assembler::vpsubb(dst, nds, src, vector_len);
3248 }
3249
3250 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3251 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3252 Assembler::vpsubb(dst, nds, src, vector_len);
3253 }
3254
3255 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3256 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3257 Assembler::vpsubw(dst, nds, src, vector_len);
3258 }
3259
3260 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3261 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3262 Assembler::vpsubw(dst, nds, src, vector_len);
3263 }
3264
3265 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3266 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3267 Assembler::vpsraw(dst, nds, shift, vector_len);
3268 }
3269
3270 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3271 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3272 Assembler::vpsraw(dst, nds, shift, vector_len);
3273 }
3274
3275 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3276 assert(UseAVX > 2,"");
3277 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3278 vector_len = 2;
3279 }
3280 Assembler::evpsraq(dst, nds, shift, vector_len);
3281 }
3282
3283 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3284 assert(UseAVX > 2,"");
3285 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3286 vector_len = 2;
3287 }
3288 Assembler::evpsraq(dst, nds, shift, vector_len);
3289 }
3290
3291 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3292 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3293 Assembler::vpsrlw(dst, nds, shift, vector_len);
3294 }
3295
3296 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3297 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3298 Assembler::vpsrlw(dst, nds, shift, vector_len);
3299 }
3300
3301 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3302 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3303 Assembler::vpsllw(dst, nds, shift, vector_len);
3304 }
3305
3306 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3307 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3308 Assembler::vpsllw(dst, nds, shift, vector_len);
3309 }
3310
3311 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3312 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3313 Assembler::vptest(dst, src);
3314 }
3315
3316 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3317 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3318 Assembler::punpcklbw(dst, src);
3319 }
3320
3321 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3322 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3323 Assembler::pshufd(dst, src, mode);
3324 }
3325
3326 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3327 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3328 Assembler::pshuflw(dst, src, mode);
3329 }
3330
3331 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3332 assert(rscratch != noreg || always_reachable(src), "missing");
3333
3334 if (reachable(src)) {
3335 vandpd(dst, nds, as_Address(src), vector_len);
3336 } else {
3337 lea(rscratch, src);
3338 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3339 }
3340 }
3341
3342 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3343 assert(rscratch != noreg || always_reachable(src), "missing");
3344
3345 if (reachable(src)) {
3346 vandps(dst, nds, as_Address(src), vector_len);
3347 } else {
3348 lea(rscratch, src);
3349 vandps(dst, nds, Address(rscratch, 0), vector_len);
3350 }
3351 }
3352
3353 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3354 bool merge, int vector_len, Register rscratch) {
3355 assert(rscratch != noreg || always_reachable(src), "missing");
3356
3357 if (reachable(src)) {
3358 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3359 } else {
3360 lea(rscratch, src);
3361 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3362 }
3363 }
3364
3365 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3366 assert(rscratch != noreg || always_reachable(src), "missing");
3367
3368 if (reachable(src)) {
3369 vdivsd(dst, nds, as_Address(src));
3370 } else {
3371 lea(rscratch, src);
3372 vdivsd(dst, nds, Address(rscratch, 0));
3373 }
3374 }
3375
3376 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3377 assert(rscratch != noreg || always_reachable(src), "missing");
3378
3379 if (reachable(src)) {
3380 vdivss(dst, nds, as_Address(src));
3381 } else {
3382 lea(rscratch, src);
3383 vdivss(dst, nds, Address(rscratch, 0));
3384 }
3385 }
3386
3387 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3388 assert(rscratch != noreg || always_reachable(src), "missing");
3389
3390 if (reachable(src)) {
3391 vmulsd(dst, nds, as_Address(src));
3392 } else {
3393 lea(rscratch, src);
3394 vmulsd(dst, nds, Address(rscratch, 0));
3395 }
3396 }
3397
3398 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3399 assert(rscratch != noreg || always_reachable(src), "missing");
3400
3401 if (reachable(src)) {
3402 vmulss(dst, nds, as_Address(src));
3403 } else {
3404 lea(rscratch, src);
3405 vmulss(dst, nds, Address(rscratch, 0));
3406 }
3407 }
3408
3409 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3410 assert(rscratch != noreg || always_reachable(src), "missing");
3411
3412 if (reachable(src)) {
3413 vsubsd(dst, nds, as_Address(src));
3414 } else {
3415 lea(rscratch, src);
3416 vsubsd(dst, nds, Address(rscratch, 0));
3417 }
3418 }
3419
3420 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3421 assert(rscratch != noreg || always_reachable(src), "missing");
3422
3423 if (reachable(src)) {
3424 vsubss(dst, nds, as_Address(src));
3425 } else {
3426 lea(rscratch, src);
3427 vsubss(dst, nds, Address(rscratch, 0));
3428 }
3429 }
3430
3431 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3432 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3433 assert(rscratch != noreg || always_reachable(src), "missing");
3434
3435 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3436 }
3437
3438 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3439 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3440 assert(rscratch != noreg || always_reachable(src), "missing");
3441
3442 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3443 }
3444
3445 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3446 assert(rscratch != noreg || always_reachable(src), "missing");
3447
3448 if (reachable(src)) {
3449 vxorpd(dst, nds, as_Address(src), vector_len);
3450 } else {
3451 lea(rscratch, src);
3452 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3453 }
3454 }
3455
3456 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3457 assert(rscratch != noreg || always_reachable(src), "missing");
3458
3459 if (reachable(src)) {
3460 vxorps(dst, nds, as_Address(src), vector_len);
3461 } else {
3462 lea(rscratch, src);
3463 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3464 }
3465 }
3466
3467 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3468 assert(rscratch != noreg || always_reachable(src), "missing");
3469
3470 if (UseAVX > 1 || (vector_len < 1)) {
3471 if (reachable(src)) {
3472 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3473 } else {
3474 lea(rscratch, src);
3475 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3476 }
3477 } else {
3478 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3479 }
3480 }
3481
3482 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3483 assert(rscratch != noreg || always_reachable(src), "missing");
3484
3485 if (reachable(src)) {
3486 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3487 } else {
3488 lea(rscratch, src);
3489 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3490 }
3491 }
3492
3493 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3494 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3495 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3496 // The inverted mask is sign-extended
3497 andptr(possibly_non_local, inverted_mask);
3498 }
3499
3500 void MacroAssembler::resolve_jobject(Register value,
3501 Register tmp) {
3502 Register thread = r15_thread;
3503 assert_different_registers(value, thread, tmp);
3504 Label done, tagged, weak_tagged;
3505 testptr(value, value);
3506 jcc(Assembler::zero, done); // Use null as-is.
3507 testptr(value, JNIHandles::tag_mask); // Test for tag.
3508 jcc(Assembler::notZero, tagged);
3509
3510 // Resolve local handle
3511 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp);
3512 verify_oop(value);
3513 jmp(done);
3514
3515 bind(tagged);
3516 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3517 jcc(Assembler::notZero, weak_tagged);
3518
3519 // Resolve global handle
3520 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3521 verify_oop(value);
3522 jmp(done);
3523
3524 bind(weak_tagged);
3525 // Resolve jweak.
3526 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3527 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp);
3528 verify_oop(value);
3529
3530 bind(done);
3531 }
3532
3533 void MacroAssembler::resolve_global_jobject(Register value,
3534 Register tmp) {
3535 Register thread = r15_thread;
3536 assert_different_registers(value, thread, tmp);
3537 Label done;
3538
3539 testptr(value, value);
3540 jcc(Assembler::zero, done); // Use null as-is.
3541
3542 #ifdef ASSERT
3543 {
3544 Label valid_global_tag;
3545 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
3546 jcc(Assembler::notZero, valid_global_tag);
3547 stop("non global jobject using resolve_global_jobject");
3548 bind(valid_global_tag);
3549 }
3550 #endif
3551
3552 // Resolve global handle
3553 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3554 verify_oop(value);
3555
3556 bind(done);
3557 }
3558
3559 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3560 subq(dst, imm32);
3561 }
3562
3563 // Force generation of a 4 byte immediate value even if it fits into 8bit
3564 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3565 subq_imm32(dst, imm32);
3566 }
3567
3568 void MacroAssembler::subptr(Register dst, Register src) {
3569 subq(dst, src);
3570 }
3571
3572 // C++ bool manipulation
3573 void MacroAssembler::testbool(Register dst) {
3574 if(sizeof(bool) == 1)
3575 testb(dst, 0xff);
3576 else if(sizeof(bool) == 2) {
3577 // testw implementation needed for two byte bools
3578 ShouldNotReachHere();
3579 } else if(sizeof(bool) == 4)
3580 testl(dst, dst);
3581 else
3582 // unsupported
3583 ShouldNotReachHere();
3584 }
3585
3586 void MacroAssembler::testptr(Register dst, Register src) {
3587 testq(dst, src);
3588 }
3589
3590 // Object / value buffer allocation...
3591 //
3592 // Kills klass and rsi on LP64
3593 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
3594 Register t1, Register t2,
3595 bool clear_fields, Label& alloc_failed)
3596 {
3597 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
3598 Register layout_size = t1;
3599 assert(new_obj == rax, "needs to be rax");
3600 assert_different_registers(klass, new_obj, t1, t2);
3601
3602 // get instance_size in InstanceKlass (scaled to a count of bytes)
3603 movl(layout_size, Address(klass, Klass::layout_helper_offset()));
3604 // test to see if it is malformed in some way
3605 testl(layout_size, Klass::_lh_instance_slow_path_bit);
3606 jcc(Assembler::notZero, slow_case_no_pop);
3607
3608 // Allocate the instance:
3609 // If TLAB is enabled:
3610 // Try to allocate in the TLAB.
3611 // If fails, go to the slow path.
3612 // Else If inline contiguous allocations are enabled:
3613 // Try to allocate in eden.
3614 // If fails due to heap end, go to slow path.
3615 //
3616 // If TLAB is enabled OR inline contiguous is enabled:
3617 // Initialize the allocation.
3618 // Exit.
3619 //
3620 // Go to slow path.
3621
3622 push(klass);
3623 if (UseTLAB) {
3624 tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case);
3625 if (ZeroTLAB || (!clear_fields)) {
3626 // the fields have been already cleared
3627 jmp(initialize_header);
3628 } else {
3629 // initialize both the header and fields
3630 jmp(initialize_object);
3631 }
3632 } else {
3633 jmp(slow_case);
3634 }
3635
3636 // If UseTLAB is true, the object is created above and there is an initialize need.
3637 // Otherwise, skip and go to the slow path.
3638 if (UseTLAB) {
3639 if (clear_fields) {
3640 // The object is initialized before the header. If the object size is
3641 // zero, go directly to the header initialization.
3642 bind(initialize_object);
3643 if (UseCompactObjectHeaders) {
3644 assert(is_aligned(oopDesc::base_offset_in_bytes(), BytesPerLong), "oop base offset must be 8-byte-aligned");
3645 decrement(layout_size, oopDesc::base_offset_in_bytes());
3646 } else {
3647 decrement(layout_size, sizeof(oopDesc));
3648 }
3649 jcc(Assembler::zero, initialize_header);
3650
3651 // Initialize topmost object field, divide size by 8, check if odd and
3652 // test if zero.
3653 Register zero = klass;
3654 xorl(zero, zero); // use zero reg to clear memory (shorter code)
3655 shrl(layout_size, LogBytesPerLong); // divide by 2*oopSize and set carry flag if odd
3656
3657 #ifdef ASSERT
3658 // make sure instance_size was multiple of 8
3659 Label L;
3660 // Ignore partial flag stall after shrl() since it is debug VM
3661 jcc(Assembler::carryClear, L);
3662 stop("object size is not multiple of 2 - adjust this code");
3663 bind(L);
3664 // must be > 0, no extra check needed here
3665 #endif
3666
3667 // initialize remaining object fields: instance_size was a multiple of 8
3668 {
3669 Label loop;
3670 bind(loop);
3671 int header_size_bytes = oopDesc::header_size() * HeapWordSize;
3672 assert(is_aligned(header_size_bytes, BytesPerLong), "oop header size must be 8-byte-aligned");
3673 movptr(Address(new_obj, layout_size, Address::times_8, header_size_bytes - 1*oopSize), zero);
3674 decrement(layout_size);
3675 jcc(Assembler::notZero, loop);
3676 }
3677 } // clear_fields
3678
3679 // initialize object header only.
3680 bind(initialize_header);
3681 if (UseCompactObjectHeaders || Arguments::is_valhalla_enabled()) {
3682 pop(klass);
3683 Register mark_word = t2;
3684 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
3685 movptr(Address(new_obj, oopDesc::mark_offset_in_bytes ()), mark_word);
3686 } else {
3687 movptr(Address(new_obj, oopDesc::mark_offset_in_bytes()),
3688 (intptr_t)markWord::prototype().value()); // header
3689 pop(klass); // get saved klass back in the register.
3690 }
3691 if (!UseCompactObjectHeaders) {
3692 xorl(rsi, rsi); // use zero reg to clear memory (shorter code)
3693 store_klass_gap(new_obj, rsi); // zero klass gap for compressed oops
3694 movptr(t2, klass); // preserve klass
3695 store_klass(new_obj, t2, rscratch1); // src klass reg is potentially compressed
3696 }
3697 jmp(done);
3698 }
3699
3700 bind(slow_case);
3701 pop(klass);
3702 bind(slow_case_no_pop);
3703 jmp(alloc_failed);
3704
3705 bind(done);
3706 }
3707
3708 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3709 void MacroAssembler::tlab_allocate(Register obj,
3710 Register var_size_in_bytes,
3711 int con_size_in_bytes,
3712 Register t1,
3713 Register t2,
3714 Label& slow_case) {
3715 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3716 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3717 }
3718
3719 RegSet MacroAssembler::call_clobbered_gp_registers() {
3720 RegSet regs;
3721 regs += RegSet::of(rax, rcx, rdx);
3722 #ifndef _WINDOWS
3723 regs += RegSet::of(rsi, rdi);
3724 #endif
3725 regs += RegSet::range(r8, r11);
3726 if (UseAPX) {
3727 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
3728 }
3729 return regs;
3730 }
3731
3732 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3733 int num_xmm_registers = XMMRegister::available_xmm_registers();
3734 #if defined(_WINDOWS)
3735 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3736 if (num_xmm_registers > 16) {
3737 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3738 }
3739 return result;
3740 #else
3741 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3742 #endif
3743 }
3744
3745 // C1 only ever uses the first double/float of the XMM register.
3746 static int xmm_save_size() { return sizeof(double); }
3747
3748 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3749 masm->movdbl(Address(rsp, offset), reg);
3750 }
3751
3752 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3753 masm->movdbl(reg, Address(rsp, offset));
3754 }
3755
3756 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
3757 bool save_fpu, int& gp_area_size, int& xmm_area_size) {
3758
3759 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
3760 StackAlignmentInBytes);
3761 xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
3762
3763 return gp_area_size + xmm_area_size;
3764 }
3765
3766 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3767 block_comment("push_call_clobbered_registers start");
3768 // Regular registers
3769 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3770
3771 int gp_area_size;
3772 int xmm_area_size;
3773 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3774 gp_area_size, xmm_area_size);
3775 subptr(rsp, total_save_size);
3776
3777 push_set(gp_registers_to_push, 0);
3778
3779 if (save_fpu) {
3780 push_set(call_clobbered_xmm_registers(), gp_area_size);
3781 }
3782
3783 block_comment("push_call_clobbered_registers end");
3784 }
3785
3786 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3787 block_comment("pop_call_clobbered_registers start");
3788
3789 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3790
3791 int gp_area_size;
3792 int xmm_area_size;
3793 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3794 gp_area_size, xmm_area_size);
3795
3796 if (restore_fpu) {
3797 pop_set(call_clobbered_xmm_registers(), gp_area_size);
3798 }
3799
3800 pop_set(gp_registers_to_pop, 0);
3801
3802 addptr(rsp, total_save_size);
3803
3804 vzeroupper();
3805
3806 block_comment("pop_call_clobbered_registers end");
3807 }
3808
3809 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3810 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3811 int spill_offset = offset;
3812
3813 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3814 save_xmm_register(this, spill_offset, *it);
3815 spill_offset += xmm_save_size();
3816 }
3817 }
3818
3819 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3820 int restore_size = set.size() * xmm_save_size();
3821 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3822
3823 int restore_offset = offset + restore_size - xmm_save_size();
3824
3825 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3826 restore_xmm_register(this, restore_offset, *it);
3827 restore_offset -= xmm_save_size();
3828 }
3829 }
3830
3831 void MacroAssembler::push_set(RegSet set, int offset) {
3832 int spill_offset;
3833 if (offset == -1) {
3834 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3835 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3836 subptr(rsp, aligned_size);
3837 spill_offset = 0;
3838 } else {
3839 spill_offset = offset;
3840 }
3841
3842 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3843 movptr(Address(rsp, spill_offset), *it);
3844 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3845 }
3846 }
3847
3848 void MacroAssembler::pop_set(RegSet set, int offset) {
3849
3850 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3851 int restore_size = set.size() * gp_reg_size;
3852 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3853
3854 int restore_offset;
3855 if (offset == -1) {
3856 restore_offset = restore_size - gp_reg_size;
3857 } else {
3858 restore_offset = offset + restore_size - gp_reg_size;
3859 }
3860 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3861 movptr(*it, Address(rsp, restore_offset));
3862 restore_offset -= gp_reg_size;
3863 }
3864
3865 if (offset == -1) {
3866 addptr(rsp, aligned_size);
3867 }
3868 }
3869
3870 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3871 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3872 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3873 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3874 Label done;
3875
3876 testptr(length_in_bytes, length_in_bytes);
3877 jcc(Assembler::zero, done);
3878
3879 // initialize topmost word, divide index by 2, check if odd and test if zero
3880 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3881 #ifdef ASSERT
3882 {
3883 Label L;
3884 testptr(length_in_bytes, BytesPerWord - 1);
3885 jcc(Assembler::zero, L);
3886 stop("length must be a multiple of BytesPerWord");
3887 bind(L);
3888 }
3889 #endif
3890 Register index = length_in_bytes;
3891 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3892 if (UseIncDec) {
3893 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3894 } else {
3895 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3896 shrptr(index, 1);
3897 }
3898
3899 // initialize remaining object fields: index is a multiple of 2 now
3900 {
3901 Label loop;
3902 bind(loop);
3903 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3904 decrement(index);
3905 jcc(Assembler::notZero, loop);
3906 }
3907
3908 bind(done);
3909 }
3910
3911 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
3912 movptr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
3913 #ifdef ASSERT
3914 {
3915 Label done;
3916 cmpptr(layout_info, 0);
3917 jcc(Assembler::notEqual, done);
3918 stop("inline_layout_info_array is null");
3919 bind(done);
3920 }
3921 #endif
3922
3923 InlineLayoutInfo array[2];
3924 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
3925 if (is_power_of_2(size)) {
3926 shll(index, log2i_exact(size)); // Scale index by power of 2
3927 } else {
3928 imull(index, index, size); // Scale the index to be the entry index * array_element_size
3929 }
3930 lea(layout_info, Address(layout_info, index, Address::times_1, Array<InlineLayoutInfo>::base_offset_in_bytes()));
3931 }
3932
3933 // Look up the method for a megamorphic invokeinterface call.
3934 // The target method is determined by <intf_klass, itable_index>.
3935 // The receiver klass is in recv_klass.
3936 // On success, the result will be in method_result, and execution falls through.
3937 // On failure, execution transfers to the given label.
3938 void MacroAssembler::lookup_interface_method(Register recv_klass,
3939 Register intf_klass,
3940 RegisterOrConstant itable_index,
3941 Register method_result,
3942 Register scan_temp,
3943 Label& L_no_such_interface,
3944 bool return_method) {
3945 assert_different_registers(recv_klass, intf_klass, scan_temp);
3946 assert_different_registers(method_result, intf_klass, scan_temp);
3947 assert(recv_klass != method_result || !return_method,
3948 "recv_klass can be destroyed when method isn't needed");
3949
3950 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3951 "caller must use same register for non-constant itable index as for method");
3952
3953 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3954 int vtable_base = in_bytes(Klass::vtable_start_offset());
3955 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3956 int scan_step = itableOffsetEntry::size() * wordSize;
3957 int vte_size = vtableEntry::size_in_bytes();
3958 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3959 assert(vte_size == wordSize, "else adjust times_vte_scale");
3960
3961 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3962
3963 // Could store the aligned, prescaled offset in the klass.
3964 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3965
3966 if (return_method) {
3967 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3968 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3969 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3970 }
3971
3972 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
3973 // if (scan->interface() == intf) {
3974 // result = (klass + scan->offset() + itable_index);
3975 // }
3976 // }
3977 Label search, found_method;
3978
3979 for (int peel = 1; peel >= 0; peel--) {
3980 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
3981 cmpptr(intf_klass, method_result);
3982
3983 if (peel) {
3984 jccb(Assembler::equal, found_method);
3985 } else {
3986 jccb(Assembler::notEqual, search);
3987 // (invert the test to fall through to found_method...)
3988 }
3989
3990 if (!peel) break;
3991
3992 bind(search);
3993
3994 // Check that the previous entry is non-null. A null entry means that
3995 // the receiver class doesn't implement the interface, and wasn't the
3996 // same as when the caller was compiled.
3997 testptr(method_result, method_result);
3998 jcc(Assembler::zero, L_no_such_interface);
3999 addptr(scan_temp, scan_step);
4000 }
4001
4002 bind(found_method);
4003
4004 if (return_method) {
4005 // Got a hit.
4006 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4007 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4008 }
4009 }
4010
4011 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4012 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4013 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4014 // The target method is determined by <holder_klass, itable_index>.
4015 // The receiver klass is in recv_klass.
4016 // On success, the result will be in method_result, and execution falls through.
4017 // On failure, execution transfers to the given label.
4018 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4019 Register holder_klass,
4020 Register resolved_klass,
4021 Register method_result,
4022 Register scan_temp,
4023 Register temp_reg2,
4024 Register receiver,
4025 int itable_index,
4026 Label& L_no_such_interface) {
4027 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4028 Register temp_itbl_klass = method_result;
4029 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4030
4031 int vtable_base = in_bytes(Klass::vtable_start_offset());
4032 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4033 int scan_step = itableOffsetEntry::size() * wordSize;
4034 int vte_size = vtableEntry::size_in_bytes();
4035 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4036 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4037 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4038 assert(vte_size == wordSize, "adjust times_vte_scale");
4039
4040 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4041
4042 // temp_itbl_klass = recv_klass.itable[0]
4043 // scan_temp = &recv_klass.itable[0] + step
4044 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4045 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4046 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4047 xorptr(temp_reg, temp_reg);
4048
4049 // Initial checks:
4050 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4051 // - if (itable[0] == 0), no such interface
4052 // - if (itable[0] == holder_klass), shortcut to "holder found"
4053 cmpptr(holder_klass, resolved_klass);
4054 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4055 testptr(temp_itbl_klass, temp_itbl_klass);
4056 jccb(Assembler::zero, L_no_such_interface);
4057 cmpptr(holder_klass, temp_itbl_klass);
4058 jccb(Assembler::equal, L_holder_found);
4059
4060 // Loop: Look for holder_klass record in itable
4061 // do {
4062 // tmp = itable[index];
4063 // index += step;
4064 // if (tmp == holder_klass) {
4065 // goto L_holder_found; // Found!
4066 // }
4067 // } while (tmp != 0);
4068 // goto L_no_such_interface // Not found.
4069 Label L_scan_holder;
4070 bind(L_scan_holder);
4071 movptr(temp_itbl_klass, Address(scan_temp, 0));
4072 addptr(scan_temp, scan_step);
4073 cmpptr(holder_klass, temp_itbl_klass);
4074 jccb(Assembler::equal, L_holder_found);
4075 testptr(temp_itbl_klass, temp_itbl_klass);
4076 jccb(Assembler::notZero, L_scan_holder);
4077
4078 jmpb(L_no_such_interface);
4079
4080 // Loop: Look for resolved_class record in itable
4081 // do {
4082 // tmp = itable[index];
4083 // index += step;
4084 // if (tmp == holder_klass) {
4085 // // Also check if we have met a holder klass
4086 // holder_tmp = itable[index-step-ioffset];
4087 // }
4088 // if (tmp == resolved_klass) {
4089 // goto L_resolved_found; // Found!
4090 // }
4091 // } while (tmp != 0);
4092 // goto L_no_such_interface // Not found.
4093 //
4094 Label L_loop_scan_resolved;
4095 bind(L_loop_scan_resolved);
4096 movptr(temp_itbl_klass, Address(scan_temp, 0));
4097 addptr(scan_temp, scan_step);
4098 bind(L_loop_scan_resolved_entry);
4099 cmpptr(holder_klass, temp_itbl_klass);
4100 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4101 cmpptr(resolved_klass, temp_itbl_klass);
4102 jccb(Assembler::equal, L_resolved_found);
4103 testptr(temp_itbl_klass, temp_itbl_klass);
4104 jccb(Assembler::notZero, L_loop_scan_resolved);
4105
4106 jmpb(L_no_such_interface);
4107
4108 Label L_ready;
4109
4110 // See if we already have a holder klass. If not, go and scan for it.
4111 bind(L_resolved_found);
4112 testptr(temp_reg, temp_reg);
4113 jccb(Assembler::zero, L_scan_holder);
4114 jmpb(L_ready);
4115
4116 bind(L_holder_found);
4117 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4118
4119 // Finally, temp_reg contains holder_klass vtable offset
4120 bind(L_ready);
4121 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4122 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4123 load_klass(scan_temp, receiver, noreg);
4124 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4125 } else {
4126 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4127 }
4128 }
4129
4130
4131 // virtual method calling
4132 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4133 RegisterOrConstant vtable_index,
4134 Register method_result) {
4135 const ByteSize base = Klass::vtable_start_offset();
4136 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4137 Address vtable_entry_addr(recv_klass,
4138 vtable_index, Address::times_ptr,
4139 base + vtableEntry::method_offset());
4140 movptr(method_result, vtable_entry_addr);
4141 }
4142
4143
4144 void MacroAssembler::check_klass_subtype(Register sub_klass,
4145 Register super_klass,
4146 Register temp_reg,
4147 Label& L_success) {
4148 Label L_failure;
4149 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4150 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4151 bind(L_failure);
4152 }
4153
4154
4155 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4156 Register super_klass,
4157 Register temp_reg,
4158 Label* L_success,
4159 Label* L_failure,
4160 Label* L_slow_path,
4161 RegisterOrConstant super_check_offset) {
4162 assert_different_registers(sub_klass, super_klass, temp_reg);
4163 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4164 if (super_check_offset.is_register()) {
4165 assert_different_registers(sub_klass, super_klass,
4166 super_check_offset.as_register());
4167 } else if (must_load_sco) {
4168 assert(temp_reg != noreg, "supply either a temp or a register offset");
4169 }
4170
4171 Label L_fallthrough;
4172 int label_nulls = 0;
4173 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4174 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4175 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4176 assert(label_nulls <= 1, "at most one null in the batch");
4177
4178 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4179 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4180 Address super_check_offset_addr(super_klass, sco_offset);
4181
4182 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4183 // range of a jccb. If this routine grows larger, reconsider at
4184 // least some of these.
4185 #define local_jcc(assembler_cond, label) \
4186 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4187 else jcc( assembler_cond, label) /*omit semi*/
4188
4189 // Hacked jmp, which may only be used just before L_fallthrough.
4190 #define final_jmp(label) \
4191 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4192 else jmp(label) /*omit semi*/
4193
4194 // If the pointers are equal, we are done (e.g., String[] elements).
4195 // This self-check enables sharing of secondary supertype arrays among
4196 // non-primary types such as array-of-interface. Otherwise, each such
4197 // type would need its own customized SSA.
4198 // We move this check to the front of the fast path because many
4199 // type checks are in fact trivially successful in this manner,
4200 // so we get a nicely predicted branch right at the start of the check.
4201 cmpptr(sub_klass, super_klass);
4202 local_jcc(Assembler::equal, *L_success);
4203
4204 // Check the supertype display:
4205 if (must_load_sco) {
4206 // Positive movl does right thing on LP64.
4207 movl(temp_reg, super_check_offset_addr);
4208 super_check_offset = RegisterOrConstant(temp_reg);
4209 }
4210 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4211 cmpptr(super_klass, super_check_addr); // load displayed supertype
4212
4213 // This check has worked decisively for primary supers.
4214 // Secondary supers are sought in the super_cache ('super_cache_addr').
4215 // (Secondary supers are interfaces and very deeply nested subtypes.)
4216 // This works in the same check above because of a tricky aliasing
4217 // between the super_cache and the primary super display elements.
4218 // (The 'super_check_addr' can address either, as the case requires.)
4219 // Note that the cache is updated below if it does not help us find
4220 // what we need immediately.
4221 // So if it was a primary super, we can just fail immediately.
4222 // Otherwise, it's the slow path for us (no success at this point).
4223
4224 if (super_check_offset.is_register()) {
4225 local_jcc(Assembler::equal, *L_success);
4226 cmpl(super_check_offset.as_register(), sc_offset);
4227 if (L_failure == &L_fallthrough) {
4228 local_jcc(Assembler::equal, *L_slow_path);
4229 } else {
4230 local_jcc(Assembler::notEqual, *L_failure);
4231 final_jmp(*L_slow_path);
4232 }
4233 } else if (super_check_offset.as_constant() == sc_offset) {
4234 // Need a slow path; fast failure is impossible.
4235 if (L_slow_path == &L_fallthrough) {
4236 local_jcc(Assembler::equal, *L_success);
4237 } else {
4238 local_jcc(Assembler::notEqual, *L_slow_path);
4239 final_jmp(*L_success);
4240 }
4241 } else {
4242 // No slow path; it's a fast decision.
4243 if (L_failure == &L_fallthrough) {
4244 local_jcc(Assembler::equal, *L_success);
4245 } else {
4246 local_jcc(Assembler::notEqual, *L_failure);
4247 final_jmp(*L_success);
4248 }
4249 }
4250
4251 bind(L_fallthrough);
4252
4253 #undef local_jcc
4254 #undef final_jmp
4255 }
4256
4257
4258 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4259 Register super_klass,
4260 Register temp_reg,
4261 Register temp2_reg,
4262 Label* L_success,
4263 Label* L_failure,
4264 bool set_cond_codes) {
4265 assert_different_registers(sub_klass, super_klass, temp_reg);
4266 if (temp2_reg != noreg)
4267 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4268 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4269
4270 Label L_fallthrough;
4271 int label_nulls = 0;
4272 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4273 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4274 assert(label_nulls <= 1, "at most one null in the batch");
4275
4276 // a couple of useful fields in sub_klass:
4277 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4278 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4279 Address secondary_supers_addr(sub_klass, ss_offset);
4280 Address super_cache_addr( sub_klass, sc_offset);
4281
4282 // Do a linear scan of the secondary super-klass chain.
4283 // This code is rarely used, so simplicity is a virtue here.
4284 // The repne_scan instruction uses fixed registers, which we must spill.
4285 // Don't worry too much about pre-existing connections with the input regs.
4286
4287 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4288 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4289
4290 // Get super_klass value into rax (even if it was in rdi or rcx).
4291 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4292 if (super_klass != rax) {
4293 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4294 mov(rax, super_klass);
4295 }
4296 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4297 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4298
4299 #ifndef PRODUCT
4300 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4301 ExternalAddress pst_counter_addr((address) pst_counter);
4302 lea(rcx, pst_counter_addr);
4303 incrementl(Address(rcx, 0));
4304 #endif //PRODUCT
4305
4306 // We will consult the secondary-super array.
4307 movptr(rdi, secondary_supers_addr);
4308 // Load the array length. (Positive movl does right thing on LP64.)
4309 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4310 // Skip to start of data.
4311 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4312
4313 // Scan RCX words at [RDI] for an occurrence of RAX.
4314 // Set NZ/Z based on last compare.
4315 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4316 // not change flags (only scas instruction which is repeated sets flags).
4317 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4318
4319 testptr(rax,rax); // Set Z = 0
4320 repne_scan();
4321
4322 // Unspill the temp. registers:
4323 if (pushed_rdi) pop(rdi);
4324 if (pushed_rcx) pop(rcx);
4325 if (pushed_rax) pop(rax);
4326
4327 if (set_cond_codes) {
4328 // Special hack for the AD files: rdi is guaranteed non-zero.
4329 assert(!pushed_rdi, "rdi must be left non-null");
4330 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4331 }
4332
4333 if (L_failure == &L_fallthrough)
4334 jccb(Assembler::notEqual, *L_failure);
4335 else jcc(Assembler::notEqual, *L_failure);
4336
4337 // Success. Cache the super we found and proceed in triumph.
4338 movptr(super_cache_addr, super_klass);
4339
4340 if (L_success != &L_fallthrough) {
4341 jmp(*L_success);
4342 }
4343
4344 #undef IS_A_TEMP
4345
4346 bind(L_fallthrough);
4347 }
4348
4349 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4350 Register super_klass,
4351 Register temp_reg,
4352 Register temp2_reg,
4353 Label* L_success,
4354 Label* L_failure,
4355 bool set_cond_codes) {
4356 assert(set_cond_codes == false, "must be false on 64-bit x86");
4357 check_klass_subtype_slow_path
4358 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4359 L_success, L_failure);
4360 }
4361
4362 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4363 Register super_klass,
4364 Register temp_reg,
4365 Register temp2_reg,
4366 Register temp3_reg,
4367 Register temp4_reg,
4368 Label* L_success,
4369 Label* L_failure) {
4370 if (UseSecondarySupersTable) {
4371 check_klass_subtype_slow_path_table
4372 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4373 L_success, L_failure);
4374 } else {
4375 check_klass_subtype_slow_path_linear
4376 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4377 }
4378 }
4379
4380 Register MacroAssembler::allocate_if_noreg(Register r,
4381 RegSetIterator<Register> &available_regs,
4382 RegSet ®s_to_push) {
4383 if (!r->is_valid()) {
4384 r = *available_regs++;
4385 regs_to_push += r;
4386 }
4387 return r;
4388 }
4389
4390 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4391 Register super_klass,
4392 Register temp_reg,
4393 Register temp2_reg,
4394 Register temp3_reg,
4395 Register result_reg,
4396 Label* L_success,
4397 Label* L_failure) {
4398 // NB! Callers may assume that, when temp2_reg is a valid register,
4399 // this code sets it to a nonzero value.
4400 bool temp2_reg_was_valid = temp2_reg->is_valid();
4401
4402 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4403
4404 Label L_fallthrough;
4405 int label_nulls = 0;
4406 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4407 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4408 assert(label_nulls <= 1, "at most one null in the batch");
4409
4410 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4411
4412 RegSetIterator<Register> available_regs
4413 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4414
4415 RegSet pushed_regs;
4416
4417 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4418 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4419 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4420 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4421 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4422
4423 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4424
4425 {
4426
4427 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4428 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4429 subptr(rsp, aligned_size);
4430 push_set(pushed_regs, 0);
4431
4432 lookup_secondary_supers_table_var(sub_klass,
4433 super_klass,
4434 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4435 cmpq(result_reg, 0);
4436
4437 // Unspill the temp. registers:
4438 pop_set(pushed_regs, 0);
4439 // Increment SP but do not clobber flags.
4440 lea(rsp, Address(rsp, aligned_size));
4441 }
4442
4443 if (temp2_reg_was_valid) {
4444 movq(temp2_reg, 1);
4445 }
4446
4447 jcc(Assembler::notEqual, *L_failure);
4448
4449 if (L_success != &L_fallthrough) {
4450 jmp(*L_success);
4451 }
4452
4453 bind(L_fallthrough);
4454 }
4455
4456 // population_count variant for running without the POPCNT
4457 // instruction, which was introduced with SSE4.2 in 2008.
4458 void MacroAssembler::population_count(Register dst, Register src,
4459 Register scratch1, Register scratch2) {
4460 assert_different_registers(src, scratch1, scratch2);
4461 if (UsePopCountInstruction) {
4462 Assembler::popcntq(dst, src);
4463 } else {
4464 assert_different_registers(src, scratch1, scratch2);
4465 assert_different_registers(dst, scratch1, scratch2);
4466 Label loop, done;
4467
4468 mov(scratch1, src);
4469 // dst = 0;
4470 // while(scratch1 != 0) {
4471 // dst++;
4472 // scratch1 &= (scratch1 - 1);
4473 // }
4474 xorl(dst, dst);
4475 testq(scratch1, scratch1);
4476 jccb(Assembler::equal, done);
4477 {
4478 bind(loop);
4479 incq(dst);
4480 movq(scratch2, scratch1);
4481 decq(scratch2);
4482 andq(scratch1, scratch2);
4483 jccb(Assembler::notEqual, loop);
4484 }
4485 bind(done);
4486 }
4487 #ifdef ASSERT
4488 mov64(scratch1, 0xCafeBabeDeadBeef);
4489 movq(scratch2, scratch1);
4490 #endif
4491 }
4492
4493 // Ensure that the inline code and the stub are using the same registers.
4494 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4495 do { \
4496 assert(r_super_klass == rax, "mismatch"); \
4497 assert(r_array_base == rbx, "mismatch"); \
4498 assert(r_array_length == rcx, "mismatch"); \
4499 assert(r_array_index == rdx, "mismatch"); \
4500 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4501 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4502 assert(result == rdi || result == noreg, "mismatch"); \
4503 } while(0)
4504
4505 // Versions of salq and rorq that don't need count to be in rcx
4506
4507 void MacroAssembler::salq(Register dest, Register count) {
4508 if (count == rcx) {
4509 Assembler::salq(dest);
4510 } else {
4511 assert_different_registers(rcx, dest);
4512 xchgq(rcx, count);
4513 Assembler::salq(dest);
4514 xchgq(rcx, count);
4515 }
4516 }
4517
4518 void MacroAssembler::rorq(Register dest, Register count) {
4519 if (count == rcx) {
4520 Assembler::rorq(dest);
4521 } else {
4522 assert_different_registers(rcx, dest);
4523 xchgq(rcx, count);
4524 Assembler::rorq(dest);
4525 xchgq(rcx, count);
4526 }
4527 }
4528
4529 // Return true: we succeeded in generating this code
4530 //
4531 // At runtime, return 0 in result if r_super_klass is a superclass of
4532 // r_sub_klass, otherwise return nonzero. Use this if you know the
4533 // super_klass_slot of the class you're looking for. This is always
4534 // the case for instanceof and checkcast.
4535 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4536 Register r_super_klass,
4537 Register temp1,
4538 Register temp2,
4539 Register temp3,
4540 Register temp4,
4541 Register result,
4542 u1 super_klass_slot) {
4543 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4544
4545 Label L_fallthrough, L_success, L_failure;
4546
4547 BLOCK_COMMENT("lookup_secondary_supers_table {");
4548
4549 const Register
4550 r_array_index = temp1,
4551 r_array_length = temp2,
4552 r_array_base = temp3,
4553 r_bitmap = temp4;
4554
4555 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4556
4557 xorq(result, result); // = 0
4558
4559 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4560 movq(r_array_index, r_bitmap);
4561
4562 // First check the bitmap to see if super_klass might be present. If
4563 // the bit is zero, we are certain that super_klass is not one of
4564 // the secondary supers.
4565 u1 bit = super_klass_slot;
4566 {
4567 // NB: If the count in a x86 shift instruction is 0, the flags are
4568 // not affected, so we do a testq instead.
4569 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4570 if (shift_count != 0) {
4571 salq(r_array_index, shift_count);
4572 } else {
4573 testq(r_array_index, r_array_index);
4574 }
4575 }
4576 // We test the MSB of r_array_index, i.e. its sign bit
4577 jcc(Assembler::positive, L_failure);
4578
4579 // Get the first array index that can contain super_klass into r_array_index.
4580 if (bit != 0) {
4581 population_count(r_array_index, r_array_index, temp2, temp3);
4582 } else {
4583 movl(r_array_index, 1);
4584 }
4585 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4586
4587 // We will consult the secondary-super array.
4588 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4589
4590 // We're asserting that the first word in an Array<Klass*> is the
4591 // length, and the second word is the first word of the data. If
4592 // that ever changes, r_array_base will have to be adjusted here.
4593 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4594 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4595
4596 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4597 jccb(Assembler::equal, L_success);
4598
4599 // Is there another entry to check? Consult the bitmap.
4600 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4601 jccb(Assembler::carryClear, L_failure);
4602
4603 // Linear probe. Rotate the bitmap so that the next bit to test is
4604 // in Bit 1.
4605 if (bit != 0) {
4606 rorq(r_bitmap, bit);
4607 }
4608
4609 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4610 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4611 // Kills: r_array_length.
4612 // Returns: result.
4613 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4614 // Result (0/1) is in rdi
4615 jmpb(L_fallthrough);
4616
4617 bind(L_failure);
4618 incq(result); // 0 => 1
4619
4620 bind(L_success);
4621 // result = 0;
4622
4623 bind(L_fallthrough);
4624 BLOCK_COMMENT("} lookup_secondary_supers_table");
4625
4626 if (VerifySecondarySupers) {
4627 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4628 temp1, temp2, temp3);
4629 }
4630 }
4631
4632 // At runtime, return 0 in result if r_super_klass is a superclass of
4633 // r_sub_klass, otherwise return nonzero. Use this version of
4634 // lookup_secondary_supers_table() if you don't know ahead of time
4635 // which superclass will be searched for. Used by interpreter and
4636 // runtime stubs. It is larger and has somewhat greater latency than
4637 // the version above, which takes a constant super_klass_slot.
4638 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
4639 Register r_super_klass,
4640 Register temp1,
4641 Register temp2,
4642 Register temp3,
4643 Register temp4,
4644 Register result) {
4645 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4646 assert_different_registers(r_sub_klass, r_super_klass, rcx);
4647 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
4648
4649 Label L_fallthrough, L_success, L_failure;
4650
4651 BLOCK_COMMENT("lookup_secondary_supers_table {");
4652
4653 RegSetIterator<Register> available_regs = (temps - rcx).begin();
4654
4655 // FIXME. Once we are sure that all paths reaching this point really
4656 // do pass rcx as one of our temps we can get rid of the following
4657 // workaround.
4658 assert(temps.contains(rcx), "fix this code");
4659
4660 // We prefer to have our shift count in rcx. If rcx is one of our
4661 // temps, use it for slot. If not, pick any of our temps.
4662 Register slot;
4663 if (!temps.contains(rcx)) {
4664 slot = *available_regs++;
4665 } else {
4666 slot = rcx;
4667 }
4668
4669 const Register r_array_index = *available_regs++;
4670 const Register r_bitmap = *available_regs++;
4671
4672 // The logic above guarantees this property, but we state it here.
4673 assert_different_registers(r_array_index, r_bitmap, rcx);
4674
4675 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4676 movq(r_array_index, r_bitmap);
4677
4678 // First check the bitmap to see if super_klass might be present. If
4679 // the bit is zero, we are certain that super_klass is not one of
4680 // the secondary supers.
4681 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4682 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
4683 salq(r_array_index, slot);
4684
4685 testq(r_array_index, r_array_index);
4686 // We test the MSB of r_array_index, i.e. its sign bit
4687 jcc(Assembler::positive, L_failure);
4688
4689 const Register r_array_base = *available_regs++;
4690
4691 // Get the first array index that can contain super_klass into r_array_index.
4692 // Note: Clobbers r_array_base and slot.
4693 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
4694
4695 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4696
4697 // We will consult the secondary-super array.
4698 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4699
4700 // We're asserting that the first word in an Array<Klass*> is the
4701 // length, and the second word is the first word of the data. If
4702 // that ever changes, r_array_base will have to be adjusted here.
4703 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4704 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4705
4706 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4707 jccb(Assembler::equal, L_success);
4708
4709 // Restore slot to its true value
4710 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4711
4712 // Linear probe. Rotate the bitmap so that the next bit to test is
4713 // in Bit 1.
4714 rorq(r_bitmap, slot);
4715
4716 // Is there another entry to check? Consult the bitmap.
4717 btq(r_bitmap, 1);
4718 jccb(Assembler::carryClear, L_failure);
4719
4720 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4721 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4722 // Kills: r_array_length.
4723 // Returns: result.
4724 lookup_secondary_supers_table_slow_path(r_super_klass,
4725 r_array_base,
4726 r_array_index,
4727 r_bitmap,
4728 /*temp1*/result,
4729 /*temp2*/slot,
4730 &L_success,
4731 nullptr);
4732
4733 bind(L_failure);
4734 movq(result, 1);
4735 jmpb(L_fallthrough);
4736
4737 bind(L_success);
4738 xorq(result, result); // = 0
4739
4740 bind(L_fallthrough);
4741 BLOCK_COMMENT("} lookup_secondary_supers_table");
4742
4743 if (VerifySecondarySupers) {
4744 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4745 temp1, temp2, temp3);
4746 }
4747 }
4748
4749 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4750 Label* L_success, Label* L_failure) {
4751 Label L_loop, L_fallthrough;
4752 {
4753 int label_nulls = 0;
4754 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4755 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4756 assert(label_nulls <= 1, "at most one null in the batch");
4757 }
4758 bind(L_loop);
4759 cmpq(value, Address(addr, count, Address::times_8));
4760 jcc(Assembler::equal, *L_success);
4761 addl(count, 1);
4762 cmpl(count, limit);
4763 jcc(Assembler::less, L_loop);
4764
4765 if (&L_fallthrough != L_failure) {
4766 jmp(*L_failure);
4767 }
4768 bind(L_fallthrough);
4769 }
4770
4771 // Called by code generated by check_klass_subtype_slow_path
4772 // above. This is called when there is a collision in the hashed
4773 // lookup in the secondary supers array.
4774 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4775 Register r_array_base,
4776 Register r_array_index,
4777 Register r_bitmap,
4778 Register temp1,
4779 Register temp2,
4780 Label* L_success,
4781 Label* L_failure) {
4782 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4783
4784 const Register
4785 r_array_length = temp1,
4786 r_sub_klass = noreg,
4787 result = noreg;
4788
4789 Label L_fallthrough;
4790 int label_nulls = 0;
4791 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4792 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4793 assert(label_nulls <= 1, "at most one null in the batch");
4794
4795 // Load the array length.
4796 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4797 // And adjust the array base to point to the data.
4798 // NB! Effectively increments current slot index by 1.
4799 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4800 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4801
4802 // Linear probe
4803 Label L_huge;
4804
4805 // The bitmap is full to bursting.
4806 // Implicit invariant: BITMAP_FULL implies (length > 0)
4807 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
4808 jcc(Assembler::greater, L_huge);
4809
4810 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4811 // current slot (at secondary_supers[r_array_index]) has not yet
4812 // been inspected, and r_array_index may be out of bounds if we
4813 // wrapped around the end of the array.
4814
4815 { // This is conventional linear probing, but instead of terminating
4816 // when a null entry is found in the table, we maintain a bitmap
4817 // in which a 0 indicates missing entries.
4818 // The check above guarantees there are 0s in the bitmap, so the loop
4819 // eventually terminates.
4820
4821 xorl(temp2, temp2); // = 0;
4822
4823 Label L_again;
4824 bind(L_again);
4825
4826 // Check for array wraparound.
4827 cmpl(r_array_index, r_array_length);
4828 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4829
4830 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4831 jcc(Assembler::equal, *L_success);
4832
4833 // If the next bit in bitmap is zero, we're done.
4834 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4835 jcc(Assembler::carryClear, *L_failure);
4836
4837 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4838 addl(r_array_index, 1);
4839
4840 jmp(L_again);
4841 }
4842
4843 { // Degenerate case: more than 64 secondary supers.
4844 // FIXME: We could do something smarter here, maybe a vectorized
4845 // comparison or a binary search, but is that worth any added
4846 // complexity?
4847 bind(L_huge);
4848 xorl(r_array_index, r_array_index); // = 0
4849 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4850 L_success,
4851 (&L_fallthrough != L_failure ? L_failure : nullptr));
4852
4853 bind(L_fallthrough);
4854 }
4855 }
4856
4857 struct VerifyHelperArguments {
4858 Klass* _super;
4859 Klass* _sub;
4860 intptr_t _linear_result;
4861 intptr_t _table_result;
4862 };
4863
4864 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
4865 Klass::on_secondary_supers_verification_failure(args->_super,
4866 args->_sub,
4867 args->_linear_result,
4868 args->_table_result,
4869 msg);
4870 }
4871
4872 // Make sure that the hashed lookup and a linear scan agree.
4873 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
4874 Register r_super_klass,
4875 Register result,
4876 Register temp1,
4877 Register temp2,
4878 Register temp3) {
4879 const Register
4880 r_array_index = temp1,
4881 r_array_length = temp2,
4882 r_array_base = temp3,
4883 r_bitmap = noreg;
4884
4885 BLOCK_COMMENT("verify_secondary_supers_table {");
4886
4887 Label L_success, L_failure, L_check, L_done;
4888
4889 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4890 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4891 // And adjust the array base to point to the data.
4892 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4893
4894 testl(r_array_length, r_array_length); // array_length == 0?
4895 jcc(Assembler::zero, L_failure);
4896
4897 movl(r_array_index, 0);
4898 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
4899 // fall through to L_failure
4900
4901 const Register linear_result = r_array_index; // reuse temp1
4902
4903 bind(L_failure); // not present
4904 movl(linear_result, 1);
4905 jmp(L_check);
4906
4907 bind(L_success); // present
4908 movl(linear_result, 0);
4909
4910 bind(L_check);
4911 cmpl(linear_result, result);
4912 jcc(Assembler::equal, L_done);
4913
4914 { // To avoid calling convention issues, build a record on the stack
4915 // and pass the pointer to that instead.
4916 push(result);
4917 push(linear_result);
4918 push(r_sub_klass);
4919 push(r_super_klass);
4920 movptr(c_rarg1, rsp);
4921 movptr(c_rarg0, (uintptr_t) "mismatch");
4922 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
4923 should_not_reach_here();
4924 }
4925 bind(L_done);
4926
4927 BLOCK_COMMENT("} verify_secondary_supers_table");
4928 }
4929
4930 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
4931
4932 void MacroAssembler::clinit_barrier(Register klass, Label* L_fast_path, Label* L_slow_path) {
4933 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
4934
4935 Label L_fallthrough;
4936 if (L_fast_path == nullptr) {
4937 L_fast_path = &L_fallthrough;
4938 } else if (L_slow_path == nullptr) {
4939 L_slow_path = &L_fallthrough;
4940 }
4941
4942 // Fast path check: class is fully initialized.
4943 // init_state needs acquire, but x86 is TSO, and so we are already good.
4944 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4945 jcc(Assembler::equal, *L_fast_path);
4946
4947 // Fast path check: current thread is initializer thread
4948 cmpptr(r15_thread, Address(klass, InstanceKlass::init_thread_offset()));
4949 if (L_slow_path == &L_fallthrough) {
4950 jcc(Assembler::equal, *L_fast_path);
4951 bind(*L_slow_path);
4952 } else if (L_fast_path == &L_fallthrough) {
4953 jcc(Assembler::notEqual, *L_slow_path);
4954 bind(*L_fast_path);
4955 } else {
4956 Unimplemented();
4957 }
4958 }
4959
4960 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4961 if (VM_Version::supports_cmov()) {
4962 cmovl(cc, dst, src);
4963 } else {
4964 Label L;
4965 jccb(negate_condition(cc), L);
4966 movl(dst, src);
4967 bind(L);
4968 }
4969 }
4970
4971 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4972 if (VM_Version::supports_cmov()) {
4973 cmovl(cc, dst, src);
4974 } else {
4975 Label L;
4976 jccb(negate_condition(cc), L);
4977 movl(dst, src);
4978 bind(L);
4979 }
4980 }
4981
4982 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4983 if (!VerifyOops || VerifyAdapterSharing) {
4984 // Below address of the code string confuses VerifyAdapterSharing
4985 // because it may differ between otherwise equivalent adapters.
4986 return;
4987 }
4988
4989 BLOCK_COMMENT("verify_oop {");
4990 push(rscratch1);
4991 push(rax); // save rax
4992 push(reg); // pass register argument
4993
4994 // Pass register number to verify_oop_subroutine
4995 const char* b = nullptr;
4996 {
4997 ResourceMark rm;
4998 stringStream ss;
4999 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5000 b = code_string(ss.as_string());
5001 }
5002 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5003 pushptr(buffer.addr(), rscratch1);
5004
5005 // call indirectly to solve generation ordering problem
5006 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5007 call(rax);
5008 // Caller pops the arguments (oop, message) and restores rax, r10
5009 BLOCK_COMMENT("} verify_oop");
5010 }
5011
5012 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5013 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5014 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5015 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5016 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5017 } else if (VM_Version::supports_avx()) {
5018 vpcmpeqd(dst, dst, dst, vector_len);
5019 } else {
5020 pcmpeqd(dst, dst);
5021 }
5022 }
5023
5024 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5025 int extra_slot_offset) {
5026 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5027 int stackElementSize = Interpreter::stackElementSize;
5028 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5029 #ifdef ASSERT
5030 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5031 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5032 #endif
5033 Register scale_reg = noreg;
5034 Address::ScaleFactor scale_factor = Address::no_scale;
5035 if (arg_slot.is_constant()) {
5036 offset += arg_slot.as_constant() * stackElementSize;
5037 } else {
5038 scale_reg = arg_slot.as_register();
5039 scale_factor = Address::times(stackElementSize);
5040 }
5041 offset += wordSize; // return PC is on stack
5042 return Address(rsp, scale_reg, scale_factor, offset);
5043 }
5044
5045 // Handle the receiver type profile update given the "recv" klass.
5046 //
5047 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
5048 // If there are no matching or claimable receiver entries in RD, updates
5049 // the polymorphic counter.
5050 //
5051 // This code expected to run by either the interpreter or JIT-ed code, without
5052 // extra synchronization. For safety, receiver cells are claimed atomically, which
5053 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
5054 // counter updates are not atomic.
5055 //
5056 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
5057 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
5058 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
5059 int poly_count_offset = in_bytes(CounterData::count_offset());
5060 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
5061 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
5062
5063 // Adjust for MDP offsets. Slots are pointer-sized, so is the global offset.
5064 assert(is_aligned(mdp_offset, BytesPerWord), "sanity");
5065 base_receiver_offset += mdp_offset;
5066 end_receiver_offset += mdp_offset;
5067 poly_count_offset += mdp_offset;
5068
5069 // Scale down to optimize encoding. Slots are pointer-sized.
5070 assert(is_aligned(base_receiver_offset, BytesPerWord), "sanity");
5071 assert(is_aligned(end_receiver_offset, BytesPerWord), "sanity");
5072 assert(is_aligned(poly_count_offset, BytesPerWord), "sanity");
5073 assert(is_aligned(receiver_step, BytesPerWord), "sanity");
5074 assert(is_aligned(receiver_to_count_step, BytesPerWord), "sanity");
5075 base_receiver_offset >>= LogBytesPerWord;
5076 end_receiver_offset >>= LogBytesPerWord;
5077 poly_count_offset >>= LogBytesPerWord;
5078 receiver_step >>= LogBytesPerWord;
5079 receiver_to_count_step >>= LogBytesPerWord;
5080
5081 #ifdef ASSERT
5082 // We are about to walk the MDO slots without asking for offsets.
5083 // Check that our math hits all the right spots.
5084 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
5085 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
5086 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
5087 int offset = base_receiver_offset + receiver_step*c;
5088 int count_offset = offset + receiver_to_count_step;
5089 assert((offset << LogBytesPerWord) == real_recv_offset, "receiver slot math");
5090 assert((count_offset << LogBytesPerWord) == real_count_offset, "receiver count math");
5091 }
5092 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
5093 assert(poly_count_offset << LogBytesPerWord == real_poly_count_offset, "poly counter math");
5094 #endif
5095
5096 // Corner case: no profile table. Increment poly counter and exit.
5097 if (ReceiverTypeData::row_limit() == 0) {
5098 addptr(Address(mdp, poly_count_offset, Address::times_ptr), DataLayout::counter_increment);
5099 return;
5100 }
5101
5102 Register offset = rscratch1;
5103
5104 Label L_loop_search_receiver, L_loop_search_empty;
5105 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
5106
5107 // The code here recognizes three major cases:
5108 // A. Fastest: receiver found in the table
5109 // B. Fast: no receiver in the table, and the table is full
5110 // C. Slow: no receiver in the table, free slots in the table
5111 //
5112 // The case A performance is most important, as perfectly-behaved code would end up
5113 // there, especially with larger TypeProfileWidth. The case B performance is
5114 // important as well, this is where bulk of code would land for normally megamorphic
5115 // cases. The case C performance is not essential, its job is to deal with installation
5116 // races, we optimize for code density instead. Case C needs to make sure that receiver
5117 // rows are only claimed once. This makes sure we never overwrite a row for another
5118 // receiver and never duplicate the receivers in the list, making profile type-accurate.
5119 //
5120 // It is very tempting to handle these cases in a single loop, and claim the first slot
5121 // without checking the rest of the table. But, profiling code should tolerate free slots
5122 // in the table, as class unloading can clear them. After such cleanup, the receiver
5123 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
5124 // to complete, before trying to install new slots. Splitting the code in several tight
5125 // loops also helpfully optimizes for cases A and B.
5126 //
5127 // This code is effectively:
5128 //
5129 // restart:
5130 // // Fastest: receiver is already installed
5131 // for (i = 0; i < receiver_count(); i++) {
5132 // if (receiver(i) == recv) goto found_recv(i);
5133 // }
5134 //
5135 // // Fast: no receiver, but profile is full
5136 // for (i = 0; i < receiver_count(); i++) {
5137 // if (receiver(i) == null) goto found_null(i);
5138 // }
5139 // goto polymorphic
5140 //
5141 // // Slow: try to install receiver
5142 // found_null(i):
5143 // CAS(&receiver(i), null, recv);
5144 // goto restart
5145 //
5146 // polymorphic:
5147 // count++;
5148 // return
5149 //
5150 // found_recv(i):
5151 // *receiver_count(i)++
5152 //
5153
5154 bind(L_restart);
5155
5156 // Fastest: receiver is already installed
5157 movptr(offset, base_receiver_offset);
5158 bind(L_loop_search_receiver);
5159 cmpptr(recv, Address(mdp, offset, Address::times_ptr));
5160 jccb(Assembler::equal, L_found_recv);
5161 addptr(offset, receiver_step);
5162 cmpptr(offset, end_receiver_offset);
5163 jccb(Assembler::notEqual, L_loop_search_receiver);
5164
5165 // Fast: no receiver, but profile is full
5166 movptr(offset, base_receiver_offset);
5167 bind(L_loop_search_empty);
5168 cmpptr(Address(mdp, offset, Address::times_ptr), NULL_WORD);
5169 jccb(Assembler::equal, L_found_empty);
5170 addptr(offset, receiver_step);
5171 cmpptr(offset, end_receiver_offset);
5172 jccb(Assembler::notEqual, L_loop_search_empty);
5173 jmpb(L_polymorphic);
5174
5175 // Slow: try to install receiver
5176 bind(L_found_empty);
5177
5178 // Atomically swing receiver slot: null -> recv.
5179 //
5180 // The update code uses CAS, which wants RAX register specifically, *and* it needs
5181 // other important registers untouched, as they form the address. Therefore, we need
5182 // to shift any important registers from RAX into some other spare register. If we
5183 // have a spare register, we are forced to save it on stack here.
5184
5185 Register spare_reg = noreg;
5186 Register shifted_mdp = mdp;
5187 Register shifted_recv = recv;
5188 if (recv == rax || mdp == rax) {
5189 spare_reg = (recv != rbx && mdp != rbx) ? rbx :
5190 (recv != rcx && mdp != rcx) ? rcx :
5191 rdx;
5192 assert_different_registers(mdp, recv, offset, spare_reg);
5193
5194 push(spare_reg);
5195 if (recv == rax) {
5196 movptr(spare_reg, recv);
5197 shifted_recv = spare_reg;
5198 } else {
5199 assert(mdp == rax, "Remaining case");
5200 movptr(spare_reg, mdp);
5201 shifted_mdp = spare_reg;
5202 }
5203 } else {
5204 push(rax);
5205 }
5206
5207 // None of the important registers are in RAX after this shuffle.
5208 assert_different_registers(rax, shifted_mdp, shifted_recv, offset);
5209
5210 xorptr(rax, rax);
5211 cmpxchgptr(shifted_recv, Address(shifted_mdp, offset, Address::times_ptr));
5212
5213 // Unshift registers.
5214 if (recv == rax || mdp == rax) {
5215 movptr(rax, spare_reg);
5216 pop(spare_reg);
5217 } else {
5218 pop(rax);
5219 }
5220
5221 // CAS success means the slot now has the receiver we want. CAS failure means
5222 // something had claimed the slot concurrently: it can be the same receiver we want,
5223 // or something else. Since this is a slow path, we can optimize for code density,
5224 // and just restart the search from the beginning.
5225 jmpb(L_restart);
5226
5227 // Counter updates:
5228
5229 // Increment polymorphic counter instead of receiver slot.
5230 bind(L_polymorphic);
5231 movptr(offset, poly_count_offset);
5232 jmpb(L_count_update);
5233
5234 // Found a receiver, convert its slot offset to corresponding count offset.
5235 bind(L_found_recv);
5236 addptr(offset, receiver_to_count_step);
5237
5238 bind(L_count_update);
5239 addptr(Address(mdp, offset, Address::times_ptr), DataLayout::counter_increment);
5240 }
5241
5242 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5243 if (!VerifyOops || VerifyAdapterSharing) {
5244 // Below address of the code string confuses VerifyAdapterSharing
5245 // because it may differ between otherwise equivalent adapters.
5246 return;
5247 }
5248
5249 push(rscratch1);
5250 push(rax); // save rax,
5251 // addr may contain rsp so we will have to adjust it based on the push
5252 // we just did (and on 64 bit we do two pushes)
5253 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5254 // stores rax into addr which is backwards of what was intended.
5255 if (addr.uses(rsp)) {
5256 lea(rax, addr);
5257 pushptr(Address(rax, 2 * BytesPerWord));
5258 } else {
5259 pushptr(addr);
5260 }
5261
5262 // Pass register number to verify_oop_subroutine
5263 const char* b = nullptr;
5264 {
5265 ResourceMark rm;
5266 stringStream ss;
5267 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5268 b = code_string(ss.as_string());
5269 }
5270 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5271 pushptr(buffer.addr(), rscratch1);
5272
5273 // call indirectly to solve generation ordering problem
5274 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5275 call(rax);
5276 // Caller pops the arguments (addr, message) and restores rax, r10.
5277 }
5278
5279 void MacroAssembler::verify_tlab() {
5280 #ifdef ASSERT
5281 if (UseTLAB && VerifyOops) {
5282 Label next, ok;
5283 Register t1 = rsi;
5284
5285 push(t1);
5286
5287 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5288 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
5289 jcc(Assembler::aboveEqual, next);
5290 STOP("assert(top >= start)");
5291 should_not_reach_here();
5292
5293 bind(next);
5294 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
5295 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5296 jcc(Assembler::aboveEqual, ok);
5297 STOP("assert(top <= end)");
5298 should_not_reach_here();
5299
5300 bind(ok);
5301 pop(t1);
5302 }
5303 #endif
5304 }
5305
5306 class ControlWord {
5307 public:
5308 int32_t _value;
5309
5310 int rounding_control() const { return (_value >> 10) & 3 ; }
5311 int precision_control() const { return (_value >> 8) & 3 ; }
5312 bool precision() const { return ((_value >> 5) & 1) != 0; }
5313 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5314 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5315 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5316 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5317 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5318
5319 void print() const {
5320 // rounding control
5321 const char* rc;
5322 switch (rounding_control()) {
5323 case 0: rc = "round near"; break;
5324 case 1: rc = "round down"; break;
5325 case 2: rc = "round up "; break;
5326 case 3: rc = "chop "; break;
5327 default:
5328 rc = nullptr; // silence compiler warnings
5329 fatal("Unknown rounding control: %d", rounding_control());
5330 };
5331 // precision control
5332 const char* pc;
5333 switch (precision_control()) {
5334 case 0: pc = "24 bits "; break;
5335 case 1: pc = "reserved"; break;
5336 case 2: pc = "53 bits "; break;
5337 case 3: pc = "64 bits "; break;
5338 default:
5339 pc = nullptr; // silence compiler warnings
5340 fatal("Unknown precision control: %d", precision_control());
5341 };
5342 // flags
5343 char f[9];
5344 f[0] = ' ';
5345 f[1] = ' ';
5346 f[2] = (precision ()) ? 'P' : 'p';
5347 f[3] = (underflow ()) ? 'U' : 'u';
5348 f[4] = (overflow ()) ? 'O' : 'o';
5349 f[5] = (zero_divide ()) ? 'Z' : 'z';
5350 f[6] = (denormalized()) ? 'D' : 'd';
5351 f[7] = (invalid ()) ? 'I' : 'i';
5352 f[8] = '\x0';
5353 // output
5354 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5355 }
5356
5357 };
5358
5359 class StatusWord {
5360 public:
5361 int32_t _value;
5362
5363 bool busy() const { return ((_value >> 15) & 1) != 0; }
5364 bool C3() const { return ((_value >> 14) & 1) != 0; }
5365 bool C2() const { return ((_value >> 10) & 1) != 0; }
5366 bool C1() const { return ((_value >> 9) & 1) != 0; }
5367 bool C0() const { return ((_value >> 8) & 1) != 0; }
5368 int top() const { return (_value >> 11) & 7 ; }
5369 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5370 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5371 bool precision() const { return ((_value >> 5) & 1) != 0; }
5372 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5373 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5374 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5375 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5376 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5377
5378 void print() const {
5379 // condition codes
5380 char c[5];
5381 c[0] = (C3()) ? '3' : '-';
5382 c[1] = (C2()) ? '2' : '-';
5383 c[2] = (C1()) ? '1' : '-';
5384 c[3] = (C0()) ? '0' : '-';
5385 c[4] = '\x0';
5386 // flags
5387 char f[9];
5388 f[0] = (error_status()) ? 'E' : '-';
5389 f[1] = (stack_fault ()) ? 'S' : '-';
5390 f[2] = (precision ()) ? 'P' : '-';
5391 f[3] = (underflow ()) ? 'U' : '-';
5392 f[4] = (overflow ()) ? 'O' : '-';
5393 f[5] = (zero_divide ()) ? 'Z' : '-';
5394 f[6] = (denormalized()) ? 'D' : '-';
5395 f[7] = (invalid ()) ? 'I' : '-';
5396 f[8] = '\x0';
5397 // output
5398 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5399 }
5400
5401 };
5402
5403 class TagWord {
5404 public:
5405 int32_t _value;
5406
5407 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5408
5409 void print() const {
5410 printf("%04x", _value & 0xFFFF);
5411 }
5412
5413 };
5414
5415 class FPU_Register {
5416 public:
5417 int32_t _m0;
5418 int32_t _m1;
5419 int16_t _ex;
5420
5421 bool is_indefinite() const {
5422 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5423 }
5424
5425 void print() const {
5426 char sign = (_ex < 0) ? '-' : '+';
5427 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5428 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5429 };
5430
5431 };
5432
5433 class FPU_State {
5434 public:
5435 enum {
5436 register_size = 10,
5437 number_of_registers = 8,
5438 register_mask = 7
5439 };
5440
5441 ControlWord _control_word;
5442 StatusWord _status_word;
5443 TagWord _tag_word;
5444 int32_t _error_offset;
5445 int32_t _error_selector;
5446 int32_t _data_offset;
5447 int32_t _data_selector;
5448 int8_t _register[register_size * number_of_registers];
5449
5450 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5451 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5452
5453 const char* tag_as_string(int tag) const {
5454 switch (tag) {
5455 case 0: return "valid";
5456 case 1: return "zero";
5457 case 2: return "special";
5458 case 3: return "empty";
5459 }
5460 ShouldNotReachHere();
5461 return nullptr;
5462 }
5463
5464 void print() const {
5465 // print computation registers
5466 { int t = _status_word.top();
5467 for (int i = 0; i < number_of_registers; i++) {
5468 int j = (i - t) & register_mask;
5469 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5470 st(j)->print();
5471 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5472 }
5473 }
5474 printf("\n");
5475 // print control registers
5476 printf("ctrl = "); _control_word.print(); printf("\n");
5477 printf("stat = "); _status_word .print(); printf("\n");
5478 printf("tags = "); _tag_word .print(); printf("\n");
5479 }
5480
5481 };
5482
5483 class Flag_Register {
5484 public:
5485 int32_t _value;
5486
5487 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5488 bool direction() const { return ((_value >> 10) & 1) != 0; }
5489 bool sign() const { return ((_value >> 7) & 1) != 0; }
5490 bool zero() const { return ((_value >> 6) & 1) != 0; }
5491 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5492 bool parity() const { return ((_value >> 2) & 1) != 0; }
5493 bool carry() const { return ((_value >> 0) & 1) != 0; }
5494
5495 void print() const {
5496 // flags
5497 char f[8];
5498 f[0] = (overflow ()) ? 'O' : '-';
5499 f[1] = (direction ()) ? 'D' : '-';
5500 f[2] = (sign ()) ? 'S' : '-';
5501 f[3] = (zero ()) ? 'Z' : '-';
5502 f[4] = (auxiliary_carry()) ? 'A' : '-';
5503 f[5] = (parity ()) ? 'P' : '-';
5504 f[6] = (carry ()) ? 'C' : '-';
5505 f[7] = '\x0';
5506 // output
5507 printf("%08x flags = %s", _value, f);
5508 }
5509
5510 };
5511
5512 class IU_Register {
5513 public:
5514 int32_t _value;
5515
5516 void print() const {
5517 printf("%08x %11d", _value, _value);
5518 }
5519
5520 };
5521
5522 class IU_State {
5523 public:
5524 Flag_Register _eflags;
5525 IU_Register _rdi;
5526 IU_Register _rsi;
5527 IU_Register _rbp;
5528 IU_Register _rsp;
5529 IU_Register _rbx;
5530 IU_Register _rdx;
5531 IU_Register _rcx;
5532 IU_Register _rax;
5533
5534 void print() const {
5535 // computation registers
5536 printf("rax, = "); _rax.print(); printf("\n");
5537 printf("rbx, = "); _rbx.print(); printf("\n");
5538 printf("rcx = "); _rcx.print(); printf("\n");
5539 printf("rdx = "); _rdx.print(); printf("\n");
5540 printf("rdi = "); _rdi.print(); printf("\n");
5541 printf("rsi = "); _rsi.print(); printf("\n");
5542 printf("rbp, = "); _rbp.print(); printf("\n");
5543 printf("rsp = "); _rsp.print(); printf("\n");
5544 printf("\n");
5545 // control registers
5546 printf("flgs = "); _eflags.print(); printf("\n");
5547 }
5548 };
5549
5550
5551 class CPU_State {
5552 public:
5553 FPU_State _fpu_state;
5554 IU_State _iu_state;
5555
5556 void print() const {
5557 printf("--------------------------------------------------\n");
5558 _iu_state .print();
5559 printf("\n");
5560 _fpu_state.print();
5561 printf("--------------------------------------------------\n");
5562 }
5563
5564 };
5565
5566
5567 static void _print_CPU_state(CPU_State* state) {
5568 state->print();
5569 };
5570
5571
5572 void MacroAssembler::print_CPU_state() {
5573 push_CPU_state();
5574 push(rsp); // pass CPU state
5575 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5576 addptr(rsp, wordSize); // discard argument
5577 pop_CPU_state();
5578 }
5579
5580 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5581 // Either restore the MXCSR register after returning from the JNI Call
5582 // or verify that it wasn't changed (with -Xcheck:jni flag).
5583 if (VM_Version::supports_sse()) {
5584 if (RestoreMXCSROnJNICalls) {
5585 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5586 } else if (CheckJNICalls) {
5587 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5588 }
5589 }
5590 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5591 vzeroupper();
5592 }
5593
5594 // ((OopHandle)result).resolve();
5595 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5596 assert_different_registers(result, tmp);
5597
5598 // Only 64 bit platforms support GCs that require a tmp register
5599 // Only IN_HEAP loads require a thread_tmp register
5600 // OopHandle::resolve is an indirection like jobject.
5601 access_load_at(T_OBJECT, IN_NATIVE,
5602 result, Address(result, 0), tmp);
5603 }
5604
5605 // ((WeakHandle)result).resolve();
5606 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5607 assert_different_registers(rresult, rtmp);
5608 Label resolved;
5609
5610 // A null weak handle resolves to null.
5611 cmpptr(rresult, 0);
5612 jcc(Assembler::equal, resolved);
5613
5614 // Only 64 bit platforms support GCs that require a tmp register
5615 // Only IN_HEAP loads require a thread_tmp register
5616 // WeakHandle::resolve is an indirection like jweak.
5617 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5618 rresult, Address(rresult, 0), rtmp);
5619 bind(resolved);
5620 }
5621
5622 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5623 // get mirror
5624 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5625 load_method_holder(mirror, method);
5626 movptr(mirror, Address(mirror, mirror_offset));
5627 resolve_oop_handle(mirror, tmp);
5628 }
5629
5630 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5631 load_method_holder(rresult, rmethod);
5632 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5633 }
5634
5635 void MacroAssembler::load_method_holder(Register holder, Register method) {
5636 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5637 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5638 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5639 }
5640
5641 void MacroAssembler::load_metadata(Register dst, Register src) {
5642 if (UseCompactObjectHeaders) {
5643 load_narrow_klass_compact(dst, src);
5644 } else if (UseCompressedClassPointers) {
5645 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5646 } else {
5647 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5648 }
5649 }
5650
5651 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5652 assert(UseCompactObjectHeaders, "expect compact object headers");
5653 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5654 shrq(dst, markWord::klass_shift);
5655 }
5656
5657 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5658 assert_different_registers(src, tmp);
5659 assert_different_registers(dst, tmp);
5660
5661 if (UseCompactObjectHeaders) {
5662 load_narrow_klass_compact(dst, src);
5663 decode_klass_not_null(dst, tmp);
5664 } else if (UseCompressedClassPointers) {
5665 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5666 decode_klass_not_null(dst, tmp);
5667 } else {
5668 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5669 }
5670 }
5671
5672 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
5673 load_klass(dst, src, tmp);
5674 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5675 }
5676
5677 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5678 assert(!UseCompactObjectHeaders, "not with compact headers");
5679 assert_different_registers(src, tmp);
5680 assert_different_registers(dst, tmp);
5681 if (UseCompressedClassPointers) {
5682 encode_klass_not_null(src, tmp);
5683 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5684 } else {
5685 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5686 }
5687 }
5688
5689 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5690 if (UseCompactObjectHeaders) {
5691 assert(tmp != noreg, "need tmp");
5692 assert_different_registers(klass, obj, tmp);
5693 load_narrow_klass_compact(tmp, obj);
5694 cmpl(klass, tmp);
5695 } else if (UseCompressedClassPointers) {
5696 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5697 } else {
5698 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5699 }
5700 }
5701
5702 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5703 if (UseCompactObjectHeaders) {
5704 assert(tmp2 != noreg, "need tmp2");
5705 assert_different_registers(obj1, obj2, tmp1, tmp2);
5706 load_narrow_klass_compact(tmp1, obj1);
5707 load_narrow_klass_compact(tmp2, obj2);
5708 cmpl(tmp1, tmp2);
5709 } else if (UseCompressedClassPointers) {
5710 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5711 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5712 } else {
5713 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5714 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5715 }
5716 }
5717
5718 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5719 Register tmp1) {
5720 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5721 decorators = AccessInternal::decorator_fixup(decorators, type);
5722 bool as_raw = (decorators & AS_RAW) != 0;
5723 if (as_raw) {
5724 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1);
5725 } else {
5726 bs->load_at(this, decorators, type, dst, src, tmp1);
5727 }
5728 }
5729
5730 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5731 Register tmp1, Register tmp2, Register tmp3) {
5732 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5733 decorators = AccessInternal::decorator_fixup(decorators, type);
5734 bool as_raw = (decorators & AS_RAW) != 0;
5735 if (as_raw) {
5736 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5737 } else {
5738 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5739 }
5740 }
5741
5742 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5743 Register inline_layout_info) {
5744 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5745 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5746 }
5747
5748 void MacroAssembler::payload_offset(Register inline_klass, Register offset) {
5749 movptr(offset, Address(inline_klass, InlineKlass::adr_members_offset()));
5750 movl(offset, Address(offset, InlineKlass::payload_offset_offset()));
5751 }
5752
5753 void MacroAssembler::payload_addr(Register oop, Register data, Register inline_klass) {
5754 // ((address) (void*) o) + vk->payload_offset();
5755 Register offset = (data == oop) ? rscratch1 : data;
5756 payload_offset(inline_klass, offset);
5757 if (data == oop) {
5758 addptr(data, offset);
5759 } else {
5760 lea(data, Address(oop, offset));
5761 }
5762 }
5763
5764 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
5765 Register index, Register data) {
5766 assert(index != rcx, "index needs to shift by rcx");
5767 assert_different_registers(array, array_klass, index);
5768 assert_different_registers(rcx, array, index);
5769
5770 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
5771 movl(rcx, Address(array_klass, Klass::layout_helper_offset()));
5772
5773 // Klass::layout_helper_log2_element_size(lh)
5774 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
5775 shrl(rcx, Klass::_lh_log2_element_size_shift);
5776 andl(rcx, Klass::_lh_log2_element_size_mask);
5777 shlptr(index); // index << rcx
5778
5779 lea(data, Address(array, index, Address::times_1, arrayOopDesc::base_offset_in_bytes(T_FLAT_ELEMENT)));
5780 }
5781
5782 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5783 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1);
5784 }
5785
5786 // Doesn't do verification, generates fixed size code
5787 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5788 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1);
5789 }
5790
5791 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5792 Register tmp2, Register tmp3, DecoratorSet decorators) {
5793 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5794 }
5795
5796 // Used for storing nulls.
5797 void MacroAssembler::store_heap_oop_null(Address dst) {
5798 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5799 }
5800
5801 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5802 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5803 if (UseCompressedClassPointers) {
5804 // Store to klass gap in destination
5805 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5806 }
5807 }
5808
5809 #ifdef ASSERT
5810 void MacroAssembler::verify_heapbase(const char* msg) {
5811 assert (UseCompressedOops, "should be compressed");
5812 assert (Universe::heap() != nullptr, "java heap should be initialized");
5813 if (CheckCompressedOops) {
5814 Label ok;
5815 ExternalAddress src2(CompressedOops::base_addr());
5816 const bool is_src2_reachable = reachable(src2);
5817 if (!is_src2_reachable) {
5818 push(rscratch1); // cmpptr trashes rscratch1
5819 }
5820 cmpptr(r12_heapbase, src2, rscratch1);
5821 jcc(Assembler::equal, ok);
5822 STOP(msg);
5823 bind(ok);
5824 if (!is_src2_reachable) {
5825 pop(rscratch1);
5826 }
5827 }
5828 }
5829 #endif
5830
5831 // Algorithm must match oop.inline.hpp encode_heap_oop.
5832 void MacroAssembler::encode_heap_oop(Register r) {
5833 #ifdef ASSERT
5834 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5835 #endif
5836 verify_oop_msg(r, "broken oop in encode_heap_oop");
5837 if (CompressedOops::base() == nullptr) {
5838 if (CompressedOops::shift() != 0) {
5839 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5840 shrq(r, LogMinObjAlignmentInBytes);
5841 }
5842 return;
5843 }
5844 testq(r, r);
5845 cmovq(Assembler::equal, r, r12_heapbase);
5846 subq(r, r12_heapbase);
5847 shrq(r, LogMinObjAlignmentInBytes);
5848 }
5849
5850 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5851 #ifdef ASSERT
5852 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5853 if (CheckCompressedOops) {
5854 Label ok;
5855 testq(r, r);
5856 jcc(Assembler::notEqual, ok);
5857 STOP("null oop passed to encode_heap_oop_not_null");
5858 bind(ok);
5859 }
5860 #endif
5861 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5862 if (CompressedOops::base() != nullptr) {
5863 subq(r, r12_heapbase);
5864 }
5865 if (CompressedOops::shift() != 0) {
5866 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5867 shrq(r, LogMinObjAlignmentInBytes);
5868 }
5869 }
5870
5871 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5872 #ifdef ASSERT
5873 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5874 if (CheckCompressedOops) {
5875 Label ok;
5876 testq(src, src);
5877 jcc(Assembler::notEqual, ok);
5878 STOP("null oop passed to encode_heap_oop_not_null2");
5879 bind(ok);
5880 }
5881 #endif
5882 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5883 if (dst != src) {
5884 movq(dst, src);
5885 }
5886 if (CompressedOops::base() != nullptr) {
5887 subq(dst, r12_heapbase);
5888 }
5889 if (CompressedOops::shift() != 0) {
5890 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5891 shrq(dst, LogMinObjAlignmentInBytes);
5892 }
5893 }
5894
5895 void MacroAssembler::decode_heap_oop(Register r) {
5896 #ifdef ASSERT
5897 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5898 #endif
5899 if (CompressedOops::base() == nullptr) {
5900 if (CompressedOops::shift() != 0) {
5901 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5902 shlq(r, LogMinObjAlignmentInBytes);
5903 }
5904 } else {
5905 Label done;
5906 shlq(r, LogMinObjAlignmentInBytes);
5907 jccb(Assembler::equal, done);
5908 addq(r, r12_heapbase);
5909 bind(done);
5910 }
5911 verify_oop_msg(r, "broken oop in decode_heap_oop");
5912 }
5913
5914 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5915 // Note: it will change flags
5916 assert (UseCompressedOops, "should only be used for compressed headers");
5917 assert (Universe::heap() != nullptr, "java heap should be initialized");
5918 // Cannot assert, unverified entry point counts instructions (see .ad file)
5919 // vtableStubs also counts instructions in pd_code_size_limit.
5920 // Also do not verify_oop as this is called by verify_oop.
5921 if (CompressedOops::shift() != 0) {
5922 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5923 shlq(r, LogMinObjAlignmentInBytes);
5924 if (CompressedOops::base() != nullptr) {
5925 addq(r, r12_heapbase);
5926 }
5927 } else {
5928 assert (CompressedOops::base() == nullptr, "sanity");
5929 }
5930 }
5931
5932 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5933 // Note: it will change flags
5934 assert (UseCompressedOops, "should only be used for compressed headers");
5935 assert (Universe::heap() != nullptr, "java heap should be initialized");
5936 // Cannot assert, unverified entry point counts instructions (see .ad file)
5937 // vtableStubs also counts instructions in pd_code_size_limit.
5938 // Also do not verify_oop as this is called by verify_oop.
5939 if (CompressedOops::shift() != 0) {
5940 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5941 if (LogMinObjAlignmentInBytes == Address::times_8) {
5942 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5943 } else {
5944 if (dst != src) {
5945 movq(dst, src);
5946 }
5947 shlq(dst, LogMinObjAlignmentInBytes);
5948 if (CompressedOops::base() != nullptr) {
5949 addq(dst, r12_heapbase);
5950 }
5951 }
5952 } else {
5953 assert (CompressedOops::base() == nullptr, "sanity");
5954 if (dst != src) {
5955 movq(dst, src);
5956 }
5957 }
5958 }
5959
5960 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5961 BLOCK_COMMENT("encode_klass_not_null {");
5962 assert_different_registers(r, tmp);
5963 if (CompressedKlassPointers::base() != nullptr) {
5964 if (AOTCodeCache::is_on_for_dump()) {
5965 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5966 } else {
5967 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5968 }
5969 subq(r, tmp);
5970 }
5971 if (CompressedKlassPointers::shift() != 0) {
5972 shrq(r, CompressedKlassPointers::shift());
5973 }
5974 BLOCK_COMMENT("} encode_klass_not_null");
5975 }
5976
5977 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5978 BLOCK_COMMENT("encode_and_move_klass_not_null {");
5979 assert_different_registers(src, dst);
5980 if (CompressedKlassPointers::base() != nullptr) {
5981 movptr(dst, -(intptr_t)CompressedKlassPointers::base());
5982 addq(dst, src);
5983 } else {
5984 movptr(dst, src);
5985 }
5986 if (CompressedKlassPointers::shift() != 0) {
5987 shrq(dst, CompressedKlassPointers::shift());
5988 }
5989 BLOCK_COMMENT("} encode_and_move_klass_not_null");
5990 }
5991
5992 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5993 BLOCK_COMMENT("decode_klass_not_null {");
5994 assert_different_registers(r, tmp);
5995 // Note: it will change flags
5996 assert(UseCompressedClassPointers, "should only be used for compressed headers");
5997 // Cannot assert, unverified entry point counts instructions (see .ad file)
5998 // vtableStubs also counts instructions in pd_code_size_limit.
5999 // Also do not verify_oop as this is called by verify_oop.
6000 if (CompressedKlassPointers::shift() != 0) {
6001 shlq(r, CompressedKlassPointers::shift());
6002 }
6003 if (CompressedKlassPointers::base() != nullptr) {
6004 if (AOTCodeCache::is_on_for_dump()) {
6005 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
6006 } else {
6007 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
6008 }
6009 addq(r, tmp);
6010 }
6011 BLOCK_COMMENT("} decode_klass_not_null");
6012 }
6013
6014 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
6015 BLOCK_COMMENT("decode_and_move_klass_not_null {");
6016 assert_different_registers(src, dst);
6017 // Note: it will change flags
6018 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6019 // Cannot assert, unverified entry point counts instructions (see .ad file)
6020 // vtableStubs also counts instructions in pd_code_size_limit.
6021 // Also do not verify_oop as this is called by verify_oop.
6022
6023 if (CompressedKlassPointers::base() == nullptr &&
6024 CompressedKlassPointers::shift() == 0) {
6025 // The best case scenario is that there is no base or shift. Then it is already
6026 // a pointer that needs nothing but a register rename.
6027 movl(dst, src);
6028 } else {
6029 if (CompressedKlassPointers::shift() <= Address::times_8) {
6030 if (CompressedKlassPointers::base() != nullptr) {
6031 movptr(dst, (intptr_t)CompressedKlassPointers::base());
6032 } else {
6033 xorq(dst, dst);
6034 }
6035 if (CompressedKlassPointers::shift() != 0) {
6036 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
6037 leaq(dst, Address(dst, src, Address::times_8, 0));
6038 } else {
6039 addq(dst, src);
6040 }
6041 } else {
6042 if (CompressedKlassPointers::base() != nullptr) {
6043 const intptr_t base_right_shifted =
6044 (intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
6045 movptr(dst, base_right_shifted);
6046 } else {
6047 xorq(dst, dst);
6048 }
6049 addq(dst, src);
6050 shlq(dst, CompressedKlassPointers::shift());
6051 }
6052 }
6053 BLOCK_COMMENT("} decode_and_move_klass_not_null");
6054 }
6055
6056 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6057 assert (UseCompressedOops, "should only be used for compressed headers");
6058 assert (Universe::heap() != nullptr, "java heap should be initialized");
6059 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6060 int oop_index = oop_recorder()->find_index(obj);
6061 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6062 mov_narrow_oop(dst, oop_index, rspec);
6063 }
6064
6065 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6066 assert (UseCompressedOops, "should only be used for compressed headers");
6067 assert (Universe::heap() != nullptr, "java heap should be initialized");
6068 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6069 int oop_index = oop_recorder()->find_index(obj);
6070 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6071 mov_narrow_oop(dst, oop_index, rspec);
6072 }
6073
6074 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6075 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6076 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6077 int klass_index = oop_recorder()->find_index(k);
6078 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6079 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6080 }
6081
6082 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6083 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6084 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6085 int klass_index = oop_recorder()->find_index(k);
6086 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6087 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6088 }
6089
6090 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6091 assert (UseCompressedOops, "should only be used for compressed headers");
6092 assert (Universe::heap() != nullptr, "java heap should be initialized");
6093 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6094 int oop_index = oop_recorder()->find_index(obj);
6095 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6096 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6097 }
6098
6099 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6100 assert (UseCompressedOops, "should only be used for compressed headers");
6101 assert (Universe::heap() != nullptr, "java heap should be initialized");
6102 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6103 int oop_index = oop_recorder()->find_index(obj);
6104 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6105 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6106 }
6107
6108 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6109 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6110 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6111 int klass_index = oop_recorder()->find_index(k);
6112 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6113 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6114 }
6115
6116 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6117 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6118 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6119 int klass_index = oop_recorder()->find_index(k);
6120 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6121 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6122 }
6123
6124 void MacroAssembler::reinit_heapbase() {
6125 if (UseCompressedOops) {
6126 if (Universe::heap() != nullptr) {
6127 if (CompressedOops::base() == nullptr) {
6128 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6129 } else {
6130 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6131 }
6132 } else {
6133 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6134 }
6135 }
6136 }
6137
6138 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6139 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6140 // An inline type might be returned. If fields are in registers we
6141 // need to allocate an inline type instance and initialize it with
6142 // the value of the fields.
6143 Label skip;
6144 // We only need a new buffered inline type if a new one is not returned
6145 testptr(rax, 1);
6146 jcc(Assembler::zero, skip);
6147 int call_offset = -1;
6148
6149 #ifdef _LP64
6150 // The following code is similar to allocate_instance but has some slight differences,
6151 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6152 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
6153 Label slow_case;
6154 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6155 mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
6156 if (vk != nullptr) {
6157 // Called from C1, where the return type is statically known.
6158 movptr(rbx, (intptr_t)vk->get_InlineKlass());
6159 jint lh = vk->layout_helper();
6160 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6161 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6162 tlab_allocate(rax, noreg, lh, r13, r14, slow_case);
6163 } else {
6164 jmp(slow_case);
6165 }
6166 } else {
6167 // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
6168 mov(rbx, rax);
6169 andptr(rbx, -2);
6170 if (UseTLAB) {
6171 movl(r14, Address(rbx, Klass::layout_helper_offset()));
6172 testl(r14, Klass::_lh_instance_slow_path_bit);
6173 jcc(Assembler::notZero, slow_case);
6174 tlab_allocate(rax, r14, 0, r13, r14, slow_case);
6175 } else {
6176 jmp(slow_case);
6177 }
6178 }
6179 if (UseTLAB) {
6180 // 2. Initialize buffered inline instance header
6181 Register buffer_obj = rax;
6182 Register klass = rbx;
6183 if (UseCompactObjectHeaders) {
6184 Register mark_word = r13;
6185 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
6186 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), mark_word);
6187 } else {
6188 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
6189 xorl(r13, r13);
6190 store_klass_gap(buffer_obj, r13);
6191 if (vk == nullptr) {
6192 // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
6193 mov(r13, klass);
6194 }
6195 store_klass(buffer_obj, klass, rscratch1);
6196 klass = r13;
6197 }
6198 // 3. Initialize its fields with an inline class specific handler
6199 if (vk != nullptr) {
6200 call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6201 } else {
6202 movptr(rbx, Address(klass, InlineKlass::adr_members_offset()));
6203 movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
6204 call(rbx);
6205 }
6206 jmp(skip);
6207 }
6208 bind(slow_case);
6209 // We failed to allocate a new inline type, fall back to a runtime
6210 // call. Some oop field may be live in some registers but we can't
6211 // tell. That runtime call will take care of preserving them
6212 // across a GC if there's one.
6213 mov(rax, rscratch1);
6214 #endif
6215
6216 if (from_interpreter) {
6217 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6218 } else {
6219 call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6220 call_offset = offset();
6221 }
6222
6223 bind(skip);
6224 return call_offset;
6225 }
6226
6227 // Move a value between registers/stack slots and update the reg_state
6228 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6229 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6230 if (reg_state[to->value()] == reg_written) {
6231 return true; // Already written
6232 }
6233 if (from != to && bt != T_VOID) {
6234 if (reg_state[to->value()] == reg_readonly) {
6235 return false; // Not yet writable
6236 }
6237 if (from->is_reg()) {
6238 if (to->is_reg()) {
6239 if (from->is_XMMRegister()) {
6240 if (bt == T_DOUBLE) {
6241 movdbl(to->as_XMMRegister(), from->as_XMMRegister());
6242 } else {
6243 assert(bt == T_FLOAT, "must be float");
6244 movflt(to->as_XMMRegister(), from->as_XMMRegister());
6245 }
6246 } else {
6247 movq(to->as_Register(), from->as_Register());
6248 }
6249 } else {
6250 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6251 Address to_addr = Address(rsp, st_off);
6252 if (from->is_XMMRegister()) {
6253 if (bt == T_DOUBLE) {
6254 movdbl(to_addr, from->as_XMMRegister());
6255 } else {
6256 assert(bt == T_FLOAT, "must be float");
6257 movflt(to_addr, from->as_XMMRegister());
6258 }
6259 } else {
6260 movq(to_addr, from->as_Register());
6261 }
6262 }
6263 } else {
6264 Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
6265 if (to->is_reg()) {
6266 if (to->is_XMMRegister()) {
6267 if (bt == T_DOUBLE) {
6268 movdbl(to->as_XMMRegister(), from_addr);
6269 } else {
6270 assert(bt == T_FLOAT, "must be float");
6271 movflt(to->as_XMMRegister(), from_addr);
6272 }
6273 } else {
6274 movq(to->as_Register(), from_addr);
6275 }
6276 } else {
6277 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6278 movq(r13, from_addr);
6279 movq(Address(rsp, st_off), r13);
6280 }
6281 }
6282 }
6283 // Update register states
6284 reg_state[from->value()] = reg_writable;
6285 reg_state[to->value()] = reg_written;
6286 return true;
6287 }
6288
6289 // Calculate the extra stack space required for packing or unpacking inline
6290 // args and adjust the stack pointer (see MacroAssembler::remove_frame).
6291 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6292 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
6293 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6294 assert(sp_inc > 0, "sanity");
6295 // Two additional slots to account for return address
6296 sp_inc += 2 * VMRegImpl::stack_slot_size;
6297
6298 push(rbp);
6299 subptr(rsp, sp_inc);
6300 #ifdef ASSERT
6301 movl(Address(rsp, 0), badRegWordVal);
6302 movl(Address(rsp, VMRegImpl::stack_slot_size), badRegWordVal);
6303 #endif
6304 return sp_inc + wordSize; // account for rbp space
6305 }
6306
6307 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
6308 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6309 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6310 RegState reg_state[]) {
6311 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6312 assert(from->is_valid(), "source must be valid");
6313 bool progress = false;
6314 #ifdef ASSERT
6315 const int start_offset = offset();
6316 #endif
6317
6318 Label L_null, L_notNull;
6319 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6320 Register tmp1 = r10;
6321 Register tmp2 = r13;
6322 Register fromReg = noreg;
6323 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, true);
6324 bool done = true;
6325 bool mark_done = true;
6326 VMReg toReg;
6327 BasicType bt;
6328 // Check if argument requires a null check
6329 bool null_check = false;
6330 VMReg nullCheckReg;
6331 while (stream.next(nullCheckReg, bt)) {
6332 if (sig->at(stream.sig_index())._offset == -1) {
6333 null_check = true;
6334 break;
6335 }
6336 }
6337 stream.reset(sig_index, to_index);
6338 while (stream.next(toReg, bt)) {
6339 assert(toReg->is_valid(), "destination must be valid");
6340 int idx = (int)toReg->value();
6341 if (reg_state[idx] == reg_readonly) {
6342 if (idx != from->value()) {
6343 mark_done = false;
6344 }
6345 done = false;
6346 continue;
6347 } else if (reg_state[idx] == reg_written) {
6348 continue;
6349 }
6350 assert(reg_state[idx] == reg_writable, "must be writable");
6351 reg_state[idx] = reg_written;
6352 progress = true;
6353
6354 if (fromReg == noreg) {
6355 if (from->is_reg()) {
6356 fromReg = from->as_Register();
6357 } else {
6358 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6359 movq(tmp1, Address(rsp, st_off));
6360 fromReg = tmp1;
6361 }
6362 if (null_check) {
6363 // Nullable inline type argument, emit null check
6364 testptr(fromReg, fromReg);
6365 jcc(Assembler::zero, L_null);
6366 }
6367 }
6368 int off = sig->at(stream.sig_index())._offset;
6369 if (off == -1) {
6370 assert(null_check, "Missing null check at");
6371 if (toReg->is_stack()) {
6372 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6373 movq(Address(rsp, st_off), 1);
6374 } else {
6375 movq(toReg->as_Register(), 1);
6376 }
6377 continue;
6378 }
6379 if (sig->at(stream.sig_index())._vt_oop) {
6380 if (toReg->is_stack()) {
6381 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6382 movq(Address(rsp, st_off), fromReg);
6383 } else {
6384 movq(toReg->as_Register(), fromReg);
6385 }
6386 continue;
6387 }
6388 assert(off > 0, "offset in object should be positive");
6389 Address fromAddr = Address(fromReg, off);
6390 if (!toReg->is_XMMRegister()) {
6391 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
6392 if (is_reference_type(bt)) {
6393 load_heap_oop(dst, fromAddr);
6394 } else {
6395 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
6396 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
6397 }
6398 if (toReg->is_stack()) {
6399 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6400 movq(Address(rsp, st_off), dst);
6401 }
6402 } else if (bt == T_DOUBLE) {
6403 movdbl(toReg->as_XMMRegister(), fromAddr);
6404 } else {
6405 assert(bt == T_FLOAT, "must be float");
6406 movflt(toReg->as_XMMRegister(), fromAddr);
6407 }
6408 }
6409 if (progress && null_check) {
6410 if (done) {
6411 jmp(L_notNull);
6412 bind(L_null);
6413 // Set null marker to zero to signal that the argument is null.
6414 // Also set all fields to zero since the runtime requires a canonical
6415 // representation of a flat null.
6416 stream.reset(sig_index, to_index);
6417 while (stream.next(toReg, bt)) {
6418 if (toReg->is_stack()) {
6419 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6420 movq(Address(rsp, st_off), 0);
6421 } else if (toReg->is_XMMRegister()) {
6422 xorps(toReg->as_XMMRegister(), toReg->as_XMMRegister());
6423 } else {
6424 xorl(toReg->as_Register(), toReg->as_Register());
6425 }
6426 }
6427 bind(L_notNull);
6428 } else {
6429 bind(L_null);
6430 }
6431 }
6432
6433 sig_index = stream.sig_index();
6434 to_index = stream.regs_index();
6435
6436 if (mark_done && reg_state[from->value()] != reg_written) {
6437 // This is okay because no one else will write to that slot
6438 reg_state[from->value()] = reg_writable;
6439 }
6440 from_index--;
6441 assert(progress || (start_offset == offset()), "should not emit code");
6442 return done;
6443 }
6444
6445 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
6446 VMRegPair* from, int from_count, int& from_index, VMReg to,
6447 RegState reg_state[], Register val_array) {
6448 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
6449 assert(to->is_valid(), "destination must be valid");
6450
6451 if (reg_state[to->value()] == reg_written) {
6452 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6453 return true; // Already written
6454 }
6455
6456 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
6457 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
6458 Register val_obj_tmp = r11;
6459 Register from_reg_tmp = r14;
6460 Register tmp1 = r10;
6461 Register tmp2 = r13;
6462 Register tmp3 = rbx;
6463 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
6464
6465 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
6466
6467 if (reg_state[to->value()] == reg_readonly) {
6468 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
6469 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6470 return false; // Not yet writable
6471 }
6472 val_obj = val_obj_tmp;
6473 }
6474
6475 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
6476 VMReg fromReg;
6477 BasicType bt;
6478 Label L_null;
6479 while (stream.next(fromReg, bt)) {
6480 assert(fromReg->is_valid(), "source must be valid");
6481 reg_state[fromReg->value()] = reg_writable;
6482
6483 int off = sig->at(stream.sig_index())._offset;
6484 if (off == -1) {
6485 // Nullable inline type argument, emit null check
6486 Label L_notNull;
6487 if (fromReg->is_stack()) {
6488 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6489 testb(Address(rsp, ld_off), 1);
6490 } else {
6491 testb(fromReg->as_Register(), 1);
6492 }
6493 jcc(Assembler::notZero, L_notNull);
6494 movptr(val_obj, 0);
6495 jmp(L_null);
6496 bind(L_notNull);
6497 continue;
6498 }
6499 if (sig->at(stream.sig_index())._vt_oop) {
6500 // buffer argument: use if non null
6501 if (fromReg->is_stack()) {
6502 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6503 movptr(val_obj, Address(rsp, ld_off));
6504 } else {
6505 movptr(val_obj, fromReg->as_Register());
6506 }
6507 testptr(val_obj, val_obj);
6508 jcc(Assembler::notEqual, L_null);
6509 // otherwise get the buffer from the just allocated pool of buffers
6510 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
6511 load_heap_oop(val_obj, Address(val_array, index));
6512 continue;
6513 }
6514
6515 assert(off > 0, "offset in object should be positive");
6516 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
6517
6518 // Pack the scalarized field into the value object.
6519 Address dst(val_obj, off);
6520 if (!fromReg->is_XMMRegister()) {
6521 Register src;
6522 if (fromReg->is_stack()) {
6523 src = from_reg_tmp;
6524 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6525 load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
6526 } else {
6527 src = fromReg->as_Register();
6528 }
6529 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
6530 if (is_reference_type(bt)) {
6531 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep val_obj valid.
6532 mov(tmp3, val_obj);
6533 Address dst_with_tmp3(tmp3, off);
6534 store_heap_oop(dst_with_tmp3, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
6535 } else {
6536 store_sized_value(dst, src, size_in_bytes);
6537 }
6538 } else if (bt == T_DOUBLE) {
6539 movdbl(dst, fromReg->as_XMMRegister());
6540 } else {
6541 assert(bt == T_FLOAT, "must be float");
6542 movflt(dst, fromReg->as_XMMRegister());
6543 }
6544 }
6545 bind(L_null);
6546 sig_index = stream.sig_index();
6547 from_index = stream.regs_index();
6548
6549 assert(reg_state[to->value()] == reg_writable, "must have already been read");
6550 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6551 assert(success, "to register must be writeable");
6552 return true;
6553 }
6554
6555 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6556 return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
6557 }
6558
6559 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
6560 assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6561 if (needs_stack_repair) {
6562 // The method has a scalarized entry point (where fields of value object arguments
6563 // are passed through registers and stack), and a non-scalarized entry point (where
6564 // value object arguments are given as oops). The non-scalarized entry point will
6565 // first load each field of value object arguments and store them in registers and on
6566 // the stack in a way compatible with the scalarized entry point. To do so, some extra
6567 // stack space might be reserved (if argument registers are not enough). On leaving the
6568 // method, this space must be freed.
6569 //
6570 // In case we used the non-scalarized entry point the stack looks like this:
6571 //
6572 // | Arguments from caller |
6573 // |---------------------------| <-- caller's SP
6574 // | Return address #1 |
6575 // | Saved RBP #1 |
6576 // |---------------------------|
6577 // | Extension space for |
6578 // | inline arg (un)packing |
6579 // |---------------------------| <-- start of this method's frame
6580 // | Return address #2 |
6581 // | Saved RBP #2 |
6582 // |---------------------------| <-- RBP (with -XX:+PreserveFramePointer)
6583 // | sp_inc |
6584 // | method locals |
6585 // |---------------------------| <-- SP
6586 //
6587 // Space for the return pc and saved rbp is reserved twice. But only the #1 copies
6588 // contain the real values of return pc and saved rbp. The #2 copies are not reliable
6589 // and should not be used. They are mostly needed to add space between the extension
6590 // space and the locals, as there would be between the real arguments and the locals
6591 // if we don't need to do unpacking (from the scalarized entry point).
6592 //
6593 // When leaving, one must load RBP #1 into RBP, and use the copy #1 of the return address,
6594 // while keeping in mind that from the scalarized entry point, there will be only one
6595 // copy. Indeed, in the case we used the scalarized calling convention, the stack looks like this:
6596 //
6597 // | Arguments from caller |
6598 // |---------------------------| <-- caller's SP
6599 // | Return address |
6600 // | Saved RBP |
6601 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer)
6602 // | sp_inc |
6603 // | method locals |
6604 // |---------------------------| <-- SP
6605 //
6606 // The sp_inc stack slot holds the total size of the frame, including the extension
6607 // space and copies #2 of the return address and the saved RBP (but never the copies
6608 // #1 of the return address and saved RBP). That is how to find the copies #1 of the
6609 // return address and saved rbp. This size is expressed in bytes. Be careful when using
6610 // it from C++ in pointer arithmetic you might need to divide it by wordSize.
6611
6612 // The stack increment resides just below the saved rbp
6613 addq(rsp, Address(rsp, initial_framesize - wordSize));
6614 pop(rbp);
6615 } else {
6616 if (initial_framesize > 0) {
6617 addq(rsp, initial_framesize);
6618 }
6619 pop(rbp);
6620 }
6621 }
6622
6623 #if COMPILER2_OR_JVMCI
6624
6625 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6626 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
6627 // cnt - number of qwords (8-byte words).
6628 // base - start address, qword aligned.
6629 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6630 bool use64byteVector = (MaxVectorSize == 64) && (CopyAVX3Threshold == 0);
6631 if (use64byteVector) {
6632 evpbroadcastq(xtmp, val, AVX_512bit);
6633 } else if (MaxVectorSize >= 32) {
6634 movdq(xtmp, val);
6635 punpcklqdq(xtmp, xtmp);
6636 vinserti128_high(xtmp, xtmp);
6637 } else {
6638 movdq(xtmp, val);
6639 punpcklqdq(xtmp, xtmp);
6640 }
6641 jmp(L_zero_64_bytes);
6642
6643 BIND(L_loop);
6644 if (MaxVectorSize >= 32) {
6645 fill64(base, 0, xtmp, use64byteVector);
6646 } else {
6647 movdqu(Address(base, 0), xtmp);
6648 movdqu(Address(base, 16), xtmp);
6649 movdqu(Address(base, 32), xtmp);
6650 movdqu(Address(base, 48), xtmp);
6651 }
6652 addptr(base, 64);
6653
6654 BIND(L_zero_64_bytes);
6655 subptr(cnt, 8);
6656 jccb(Assembler::greaterEqual, L_loop);
6657
6658 // Copy trailing 64 bytes
6659 if (use64byteVector) {
6660 addptr(cnt, 8);
6661 jccb(Assembler::equal, L_end);
6662 fill64_masked(3, base, 0, xtmp, mask, cnt, val, true);
6663 jmp(L_end);
6664 } else {
6665 addptr(cnt, 4);
6666 jccb(Assembler::less, L_tail);
6667 if (MaxVectorSize >= 32) {
6668 vmovdqu(Address(base, 0), xtmp);
6669 } else {
6670 movdqu(Address(base, 0), xtmp);
6671 movdqu(Address(base, 16), xtmp);
6672 }
6673 }
6674 addptr(base, 32);
6675 subptr(cnt, 4);
6676
6677 BIND(L_tail);
6678 addptr(cnt, 4);
6679 jccb(Assembler::lessEqual, L_end);
6680 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6681 fill32_masked(3, base, 0, xtmp, mask, cnt, val);
6682 } else {
6683 decrement(cnt);
6684
6685 BIND(L_sloop);
6686 movq(Address(base, 0), xtmp);
6687 addptr(base, 8);
6688 decrement(cnt);
6689 jccb(Assembler::greaterEqual, L_sloop);
6690 }
6691 BIND(L_end);
6692 }
6693
6694 // Clearing constant sized memory using YMM/ZMM registers.
6695 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6696 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6697 bool use64byteVector = (MaxVectorSize > 32) && (CopyAVX3Threshold == 0);
6698
6699 int vector64_count = (cnt & (~0x7)) >> 3;
6700 cnt = cnt & 0x7;
6701 const int fill64_per_loop = 4;
6702 const int max_unrolled_fill64 = 8;
6703
6704 // 64 byte initialization loop.
6705 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6706 int start64 = 0;
6707 if (vector64_count > max_unrolled_fill64) {
6708 Label LOOP;
6709 Register index = rtmp;
6710
6711 start64 = vector64_count - (vector64_count % fill64_per_loop);
6712
6713 movl(index, 0);
6714 BIND(LOOP);
6715 for (int i = 0; i < fill64_per_loop; i++) {
6716 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6717 }
6718 addl(index, fill64_per_loop * 64);
6719 cmpl(index, start64 * 64);
6720 jccb(Assembler::less, LOOP);
6721 }
6722 for (int i = start64; i < vector64_count; i++) {
6723 fill64(base, i * 64, xtmp, use64byteVector);
6724 }
6725
6726 // Clear remaining 64 byte tail.
6727 int disp = vector64_count * 64;
6728 if (cnt) {
6729 switch (cnt) {
6730 case 1:
6731 movq(Address(base, disp), xtmp);
6732 break;
6733 case 2:
6734 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6735 break;
6736 case 3:
6737 movl(rtmp, 0x7);
6738 kmovwl(mask, rtmp);
6739 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6740 break;
6741 case 4:
6742 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6743 break;
6744 case 5:
6745 if (use64byteVector) {
6746 movl(rtmp, 0x1F);
6747 kmovwl(mask, rtmp);
6748 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6749 } else {
6750 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6751 movq(Address(base, disp + 32), xtmp);
6752 }
6753 break;
6754 case 6:
6755 if (use64byteVector) {
6756 movl(rtmp, 0x3F);
6757 kmovwl(mask, rtmp);
6758 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6759 } else {
6760 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6761 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6762 }
6763 break;
6764 case 7:
6765 if (use64byteVector) {
6766 movl(rtmp, 0x7F);
6767 kmovwl(mask, rtmp);
6768 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6769 } else {
6770 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6771 movl(rtmp, 0x7);
6772 kmovwl(mask, rtmp);
6773 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6774 }
6775 break;
6776 default:
6777 fatal("Unexpected length : %d\n",cnt);
6778 break;
6779 }
6780 }
6781 }
6782
6783 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
6784 bool is_large, bool word_copy_only, KRegister mask) {
6785 // cnt - number of qwords (8-byte words).
6786 // base - start address, qword aligned.
6787 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6788 assert(base==rdi, "base register must be edi for rep stos");
6789 assert(val==rax, "val register must be eax for rep stos");
6790 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6791 assert(InitArrayShortSize % BytesPerLong == 0,
6792 "InitArrayShortSize should be the multiple of BytesPerLong");
6793
6794 Label DONE;
6795
6796 if (!is_large) {
6797 Label LOOP, LONG;
6798 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6799 jccb(Assembler::greater, LONG);
6800
6801 decrement(cnt);
6802 jccb(Assembler::negative, DONE); // Zero length
6803
6804 // Use individual pointer-sized stores for small counts:
6805 BIND(LOOP);
6806 movptr(Address(base, cnt, Address::times_ptr), val);
6807 decrement(cnt);
6808 jccb(Assembler::greaterEqual, LOOP);
6809 jmpb(DONE);
6810
6811 BIND(LONG);
6812 }
6813
6814 // Use longer rep-prefixed ops for non-small counts:
6815 if (UseFastStosb && !word_copy_only) {
6816 shlptr(cnt, 3); // convert to number of bytes
6817 rep_stosb();
6818 } else if (UseXMMForObjInit) {
6819 xmm_clear_mem(base, cnt, val, xtmp, mask);
6820 } else {
6821 rep_stos();
6822 }
6823
6824 BIND(DONE);
6825 }
6826
6827 #endif //COMPILER2_OR_JVMCI
6828
6829
6830 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6831 Register to, Register value, Register count,
6832 Register rtmp, XMMRegister xtmp) {
6833 ShortBranchVerifier sbv(this);
6834 assert_different_registers(to, value, count, rtmp);
6835 Label L_exit;
6836 Label L_fill_2_bytes, L_fill_4_bytes;
6837
6838 #if defined(COMPILER2)
6839 if(MaxVectorSize >=32 &&
6840 VM_Version::supports_avx512vlbw() &&
6841 VM_Version::supports_bmi2()) {
6842 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6843 return;
6844 }
6845 #endif
6846
6847 int shift = -1;
6848 switch (t) {
6849 case T_BYTE:
6850 shift = 2;
6851 break;
6852 case T_SHORT:
6853 shift = 1;
6854 break;
6855 case T_INT:
6856 shift = 0;
6857 break;
6858 default: ShouldNotReachHere();
6859 }
6860
6861 if (t == T_BYTE) {
6862 andl(value, 0xff);
6863 movl(rtmp, value);
6864 shll(rtmp, 8);
6865 orl(value, rtmp);
6866 }
6867 if (t == T_SHORT) {
6868 andl(value, 0xffff);
6869 }
6870 if (t == T_BYTE || t == T_SHORT) {
6871 movl(rtmp, value);
6872 shll(rtmp, 16);
6873 orl(value, rtmp);
6874 }
6875
6876 cmpptr(count, 8 << shift); // Short arrays (< 32 bytes) fill by element
6877 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6878 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6879 Label L_skip_align2;
6880 // align source address at 4 bytes address boundary
6881 if (t == T_BYTE) {
6882 Label L_skip_align1;
6883 // One byte misalignment happens only for byte arrays
6884 testptr(to, 1);
6885 jccb(Assembler::zero, L_skip_align1);
6886 movb(Address(to, 0), value);
6887 increment(to);
6888 decrement(count);
6889 BIND(L_skip_align1);
6890 }
6891 // Two bytes misalignment happens only for byte and short (char) arrays
6892 testptr(to, 2);
6893 jccb(Assembler::zero, L_skip_align2);
6894 movw(Address(to, 0), value);
6895 addptr(to, 2);
6896 subptr(count, 1<<(shift-1));
6897 BIND(L_skip_align2);
6898 }
6899 {
6900 Label L_fill_32_bytes;
6901 if (!UseUnalignedLoadStores) {
6902 // align to 8 bytes, we know we are 4 byte aligned to start
6903 testptr(to, 4);
6904 jccb(Assembler::zero, L_fill_32_bytes);
6905 movl(Address(to, 0), value);
6906 addptr(to, 4);
6907 subptr(count, 1<<shift);
6908 }
6909 BIND(L_fill_32_bytes);
6910 {
6911 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6912 movdl(xtmp, value);
6913 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6914 Label L_check_fill_32_bytes;
6915 if (UseAVX > 2) {
6916 // Fill 64-byte chunks
6917 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6918
6919 // If number of bytes to fill < CopyAVX3Threshold, perform fill using AVX2
6920 cmpptr(count, CopyAVX3Threshold);
6921 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6922
6923 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6924
6925 subptr(count, 16 << shift);
6926 jcc(Assembler::less, L_check_fill_32_bytes);
6927 align(16);
6928
6929 BIND(L_fill_64_bytes_loop_avx3);
6930 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6931 addptr(to, 64);
6932 subptr(count, 16 << shift);
6933 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6934 jmpb(L_check_fill_32_bytes);
6935
6936 BIND(L_check_fill_64_bytes_avx2);
6937 }
6938 // Fill 64-byte chunks
6939 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6940
6941 subptr(count, 16 << shift);
6942 jcc(Assembler::less, L_check_fill_32_bytes);
6943
6944 // align data for 64-byte chunks
6945 Label L_fill_64_bytes_loop, L_align_64_bytes_loop;
6946 if (EnableX86ECoreOpts) {
6947 // align 'big' arrays to cache lines to minimize split_stores
6948 cmpptr(count, 96 << shift);
6949 jcc(Assembler::below, L_fill_64_bytes_loop);
6950
6951 // Find the bytes needed for alignment
6952 movptr(rtmp, to);
6953 andptr(rtmp, 0x1c);
6954 jcc(Assembler::zero, L_fill_64_bytes_loop);
6955 negptr(rtmp); // number of bytes to fill 32-rtmp. it filled by 2 mov by 32
6956 addptr(rtmp, 32);
6957 shrptr(rtmp, 2 - shift);// get number of elements from bytes
6958 subptr(count, rtmp); // adjust count by number of elements
6959
6960 align(16);
6961 BIND(L_align_64_bytes_loop);
6962 movdl(Address(to, 0), xtmp);
6963 addptr(to, 4);
6964 subptr(rtmp, 1 << shift);
6965 jcc(Assembler::greater, L_align_64_bytes_loop);
6966 }
6967
6968 align(16);
6969 BIND(L_fill_64_bytes_loop);
6970 vmovdqu(Address(to, 0), xtmp);
6971 vmovdqu(Address(to, 32), xtmp);
6972 addptr(to, 64);
6973 subptr(count, 16 << shift);
6974 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6975
6976 align(16);
6977 BIND(L_check_fill_32_bytes);
6978 addptr(count, 8 << shift);
6979 jccb(Assembler::less, L_check_fill_8_bytes);
6980 vmovdqu(Address(to, 0), xtmp);
6981 addptr(to, 32);
6982 subptr(count, 8 << shift);
6983
6984 BIND(L_check_fill_8_bytes);
6985 // clean upper bits of YMM registers
6986 movdl(xtmp, value);
6987 pshufd(xtmp, xtmp, 0);
6988 } else {
6989 // Fill 32-byte chunks
6990 pshufd(xtmp, xtmp, 0);
6991
6992 subptr(count, 8 << shift);
6993 jcc(Assembler::less, L_check_fill_8_bytes);
6994 align(16);
6995
6996 BIND(L_fill_32_bytes_loop);
6997
6998 if (UseUnalignedLoadStores) {
6999 movdqu(Address(to, 0), xtmp);
7000 movdqu(Address(to, 16), xtmp);
7001 } else {
7002 movq(Address(to, 0), xtmp);
7003 movq(Address(to, 8), xtmp);
7004 movq(Address(to, 16), xtmp);
7005 movq(Address(to, 24), xtmp);
7006 }
7007
7008 addptr(to, 32);
7009 subptr(count, 8 << shift);
7010 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7011
7012 BIND(L_check_fill_8_bytes);
7013 }
7014 addptr(count, 8 << shift);
7015 jccb(Assembler::zero, L_exit);
7016 jmpb(L_fill_8_bytes);
7017
7018 //
7019 // length is too short, just fill qwords
7020 //
7021 align(16);
7022 BIND(L_fill_8_bytes_loop);
7023 movq(Address(to, 0), xtmp);
7024 addptr(to, 8);
7025 BIND(L_fill_8_bytes);
7026 subptr(count, 1 << (shift + 1));
7027 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7028 }
7029 }
7030
7031 Label L_fill_4_bytes_loop;
7032 testl(count, 1 << shift);
7033 jccb(Assembler::zero, L_fill_2_bytes);
7034
7035 align(16);
7036 BIND(L_fill_4_bytes_loop);
7037 movl(Address(to, 0), value);
7038 addptr(to, 4);
7039
7040 BIND(L_fill_4_bytes);
7041 subptr(count, 1 << shift);
7042 jccb(Assembler::greaterEqual, L_fill_4_bytes_loop);
7043
7044 if (t == T_BYTE || t == T_SHORT) {
7045 Label L_fill_byte;
7046 BIND(L_fill_2_bytes);
7047 // fill trailing 2 bytes
7048 testl(count, 1<<(shift-1));
7049 jccb(Assembler::zero, L_fill_byte);
7050 movw(Address(to, 0), value);
7051 if (t == T_BYTE) {
7052 addptr(to, 2);
7053 BIND(L_fill_byte);
7054 // fill trailing byte
7055 testl(count, 1);
7056 jccb(Assembler::zero, L_exit);
7057 movb(Address(to, 0), value);
7058 } else {
7059 BIND(L_fill_byte);
7060 }
7061 } else {
7062 BIND(L_fill_2_bytes);
7063 }
7064 BIND(L_exit);
7065 }
7066
7067 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
7068 switch(type) {
7069 case T_BYTE:
7070 case T_BOOLEAN:
7071 evpbroadcastb(dst, src, vector_len);
7072 break;
7073 case T_SHORT:
7074 case T_CHAR:
7075 evpbroadcastw(dst, src, vector_len);
7076 break;
7077 case T_INT:
7078 case T_FLOAT:
7079 evpbroadcastd(dst, src, vector_len);
7080 break;
7081 case T_LONG:
7082 case T_DOUBLE:
7083 evpbroadcastq(dst, src, vector_len);
7084 break;
7085 default:
7086 fatal("Unhandled type : %s", type2name(type));
7087 break;
7088 }
7089 }
7090
7091 // Encode given char[]/byte[] to byte[] in ISO_8859_1 or ASCII
7092 //
7093 // @IntrinsicCandidate
7094 // int sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(
7095 // char[] sa, int sp, byte[] da, int dp, int len) {
7096 // int i = 0;
7097 // for (; i < len; i++) {
7098 // char c = sa[sp++];
7099 // if (c > '\u00FF')
7100 // break;
7101 // da[dp++] = (byte) c;
7102 // }
7103 // return i;
7104 // }
7105 //
7106 // @IntrinsicCandidate
7107 // int java.lang.StringCoding.encodeISOArray0(
7108 // byte[] sa, int sp, byte[] da, int dp, int len) {
7109 // int i = 0;
7110 // for (; i < len; i++) {
7111 // char c = StringUTF16.getChar(sa, sp++);
7112 // if (c > '\u00FF')
7113 // break;
7114 // da[dp++] = (byte) c;
7115 // }
7116 // return i;
7117 // }
7118 //
7119 // @IntrinsicCandidate
7120 // int java.lang.StringCoding.encodeAsciiArray0(
7121 // char[] sa, int sp, byte[] da, int dp, int len) {
7122 // int i = 0;
7123 // for (; i < len; i++) {
7124 // char c = sa[sp++];
7125 // if (c >= '\u0080')
7126 // break;
7127 // da[dp++] = (byte) c;
7128 // }
7129 // return i;
7130 // }
7131 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7132 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7133 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7134 Register tmp5, Register result, bool ascii) {
7135
7136 // rsi: src
7137 // rdi: dst
7138 // rdx: len
7139 // rcx: tmp5
7140 // rax: result
7141 ShortBranchVerifier sbv(this);
7142 assert_different_registers(src, dst, len, tmp5, result);
7143 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7144
7145 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
7146 int short_mask = ascii ? 0xff80 : 0xff00;
7147
7148 // set result
7149 xorl(result, result);
7150 // check for zero length
7151 testl(len, len);
7152 jcc(Assembler::zero, L_done);
7153
7154 movl(result, len);
7155
7156 // Setup pointers
7157 lea(src, Address(src, len, Address::times_2)); // char[]
7158 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7159 negptr(len);
7160
7161 if (UseSSE42Intrinsics || UseAVX >= 2) {
7162 Label L_copy_8_chars, L_copy_8_chars_exit;
7163 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7164
7165 if (UseAVX >= 2) {
7166 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7167 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7168 movdl(tmp1Reg, tmp5);
7169 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7170 jmp(L_chars_32_check);
7171
7172 bind(L_copy_32_chars);
7173 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7174 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7175 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7176 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7177 jccb(Assembler::notZero, L_copy_32_chars_exit);
7178 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7179 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7180 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7181
7182 bind(L_chars_32_check);
7183 addptr(len, 32);
7184 jcc(Assembler::lessEqual, L_copy_32_chars);
7185
7186 bind(L_copy_32_chars_exit);
7187 subptr(len, 16);
7188 jccb(Assembler::greater, L_copy_16_chars_exit);
7189
7190 } else if (UseSSE42Intrinsics) {
7191 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7192 movdl(tmp1Reg, tmp5);
7193 pshufd(tmp1Reg, tmp1Reg, 0);
7194 jmpb(L_chars_16_check);
7195 }
7196
7197 bind(L_copy_16_chars);
7198 if (UseAVX >= 2) {
7199 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7200 vptest(tmp2Reg, tmp1Reg);
7201 jcc(Assembler::notZero, L_copy_16_chars_exit);
7202 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7203 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7204 } else {
7205 if (UseAVX > 0) {
7206 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7207 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7208 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7209 } else {
7210 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7211 por(tmp2Reg, tmp3Reg);
7212 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7213 por(tmp2Reg, tmp4Reg);
7214 }
7215 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7216 jccb(Assembler::notZero, L_copy_16_chars_exit);
7217 packuswb(tmp3Reg, tmp4Reg);
7218 }
7219 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7220
7221 bind(L_chars_16_check);
7222 addptr(len, 16);
7223 jcc(Assembler::lessEqual, L_copy_16_chars);
7224
7225 bind(L_copy_16_chars_exit);
7226 if (UseAVX >= 2) {
7227 // clean upper bits of YMM registers
7228 vpxor(tmp2Reg, tmp2Reg);
7229 vpxor(tmp3Reg, tmp3Reg);
7230 vpxor(tmp4Reg, tmp4Reg);
7231 movdl(tmp1Reg, tmp5);
7232 pshufd(tmp1Reg, tmp1Reg, 0);
7233 }
7234 subptr(len, 8);
7235 jccb(Assembler::greater, L_copy_8_chars_exit);
7236
7237 bind(L_copy_8_chars);
7238 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7239 ptest(tmp3Reg, tmp1Reg);
7240 jccb(Assembler::notZero, L_copy_8_chars_exit);
7241 packuswb(tmp3Reg, tmp1Reg);
7242 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7243 addptr(len, 8);
7244 jccb(Assembler::lessEqual, L_copy_8_chars);
7245
7246 bind(L_copy_8_chars_exit);
7247 subptr(len, 8);
7248 jccb(Assembler::zero, L_done);
7249 }
7250
7251 bind(L_copy_1_char);
7252 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7253 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7254 jccb(Assembler::notZero, L_copy_1_char_exit);
7255 movb(Address(dst, len, Address::times_1, 0), tmp5);
7256 addptr(len, 1);
7257 jccb(Assembler::less, L_copy_1_char);
7258
7259 bind(L_copy_1_char_exit);
7260 addptr(result, len); // len is negative count of not processed elements
7261
7262 bind(L_done);
7263 }
7264
7265 /**
7266 * Helper for multiply_to_len().
7267 */
7268 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7269 addq(dest_lo, src1);
7270 adcq(dest_hi, 0);
7271 addq(dest_lo, src2);
7272 adcq(dest_hi, 0);
7273 }
7274
7275 /**
7276 * Multiply 64 bit by 64 bit first loop.
7277 */
7278 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7279 Register y, Register y_idx, Register z,
7280 Register carry, Register product,
7281 Register idx, Register kdx) {
7282 //
7283 // jlong carry, x[], y[], z[];
7284 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7285 // huge_128 product = y[idx] * x[xstart] + carry;
7286 // z[kdx] = (jlong)product;
7287 // carry = (jlong)(product >>> 64);
7288 // }
7289 // z[xstart] = carry;
7290 //
7291
7292 Label L_first_loop, L_first_loop_exit;
7293 Label L_one_x, L_one_y, L_multiply;
7294
7295 decrementl(xstart);
7296 jcc(Assembler::negative, L_one_x);
7297
7298 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7299 rorq(x_xstart, 32); // convert big-endian to little-endian
7300
7301 bind(L_first_loop);
7302 decrementl(idx);
7303 jcc(Assembler::negative, L_first_loop_exit);
7304 decrementl(idx);
7305 jcc(Assembler::negative, L_one_y);
7306 movq(y_idx, Address(y, idx, Address::times_4, 0));
7307 rorq(y_idx, 32); // convert big-endian to little-endian
7308 bind(L_multiply);
7309 movq(product, x_xstart);
7310 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7311 addq(product, carry);
7312 adcq(rdx, 0);
7313 subl(kdx, 2);
7314 movl(Address(z, kdx, Address::times_4, 4), product);
7315 shrq(product, 32);
7316 movl(Address(z, kdx, Address::times_4, 0), product);
7317 movq(carry, rdx);
7318 jmp(L_first_loop);
7319
7320 bind(L_one_y);
7321 movl(y_idx, Address(y, 0));
7322 jmp(L_multiply);
7323
7324 bind(L_one_x);
7325 movl(x_xstart, Address(x, 0));
7326 jmp(L_first_loop);
7327
7328 bind(L_first_loop_exit);
7329 }
7330
7331 /**
7332 * Multiply 64 bit by 64 bit and add 128 bit.
7333 */
7334 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7335 Register yz_idx, Register idx,
7336 Register carry, Register product, int offset) {
7337 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7338 // z[kdx] = (jlong)product;
7339
7340 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7341 rorq(yz_idx, 32); // convert big-endian to little-endian
7342 movq(product, x_xstart);
7343 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7344 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7345 rorq(yz_idx, 32); // convert big-endian to little-endian
7346
7347 add2_with_carry(rdx, product, carry, yz_idx);
7348
7349 movl(Address(z, idx, Address::times_4, offset+4), product);
7350 shrq(product, 32);
7351 movl(Address(z, idx, Address::times_4, offset), product);
7352
7353 }
7354
7355 /**
7356 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7357 */
7358 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7359 Register yz_idx, Register idx, Register jdx,
7360 Register carry, Register product,
7361 Register carry2) {
7362 // jlong carry, x[], y[], z[];
7363 // int kdx = ystart+1;
7364 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7365 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7366 // z[kdx+idx+1] = (jlong)product;
7367 // jlong carry2 = (jlong)(product >>> 64);
7368 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7369 // z[kdx+idx] = (jlong)product;
7370 // carry = (jlong)(product >>> 64);
7371 // }
7372 // idx += 2;
7373 // if (idx > 0) {
7374 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7375 // z[kdx+idx] = (jlong)product;
7376 // carry = (jlong)(product >>> 64);
7377 // }
7378 //
7379
7380 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7381
7382 movl(jdx, idx);
7383 andl(jdx, 0xFFFFFFFC);
7384 shrl(jdx, 2);
7385
7386 bind(L_third_loop);
7387 subl(jdx, 1);
7388 jcc(Assembler::negative, L_third_loop_exit);
7389 subl(idx, 4);
7390
7391 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7392 movq(carry2, rdx);
7393
7394 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7395 movq(carry, rdx);
7396 jmp(L_third_loop);
7397
7398 bind (L_third_loop_exit);
7399
7400 andl (idx, 0x3);
7401 jcc(Assembler::zero, L_post_third_loop_done);
7402
7403 Label L_check_1;
7404 subl(idx, 2);
7405 jcc(Assembler::negative, L_check_1);
7406
7407 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7408 movq(carry, rdx);
7409
7410 bind (L_check_1);
7411 addl (idx, 0x2);
7412 andl (idx, 0x1);
7413 subl(idx, 1);
7414 jcc(Assembler::negative, L_post_third_loop_done);
7415
7416 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7417 movq(product, x_xstart);
7418 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7419 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7420
7421 add2_with_carry(rdx, product, yz_idx, carry);
7422
7423 movl(Address(z, idx, Address::times_4, 0), product);
7424 shrq(product, 32);
7425
7426 shlq(rdx, 32);
7427 orq(product, rdx);
7428 movq(carry, product);
7429
7430 bind(L_post_third_loop_done);
7431 }
7432
7433 /**
7434 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7435 *
7436 */
7437 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7438 Register carry, Register carry2,
7439 Register idx, Register jdx,
7440 Register yz_idx1, Register yz_idx2,
7441 Register tmp, Register tmp3, Register tmp4) {
7442 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7443
7444 // jlong carry, x[], y[], z[];
7445 // int kdx = ystart+1;
7446 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7447 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7448 // jlong carry2 = (jlong)(tmp3 >>> 64);
7449 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7450 // carry = (jlong)(tmp4 >>> 64);
7451 // z[kdx+idx+1] = (jlong)tmp3;
7452 // z[kdx+idx] = (jlong)tmp4;
7453 // }
7454 // idx += 2;
7455 // if (idx > 0) {
7456 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7457 // z[kdx+idx] = (jlong)yz_idx1;
7458 // carry = (jlong)(yz_idx1 >>> 64);
7459 // }
7460 //
7461
7462 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7463
7464 movl(jdx, idx);
7465 andl(jdx, 0xFFFFFFFC);
7466 shrl(jdx, 2);
7467
7468 bind(L_third_loop);
7469 subl(jdx, 1);
7470 jcc(Assembler::negative, L_third_loop_exit);
7471 subl(idx, 4);
7472
7473 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7474 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7475 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7476 rorxq(yz_idx2, yz_idx2, 32);
7477
7478 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7479 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7480
7481 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7482 rorxq(yz_idx1, yz_idx1, 32);
7483 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7484 rorxq(yz_idx2, yz_idx2, 32);
7485
7486 if (VM_Version::supports_adx()) {
7487 adcxq(tmp3, carry);
7488 adoxq(tmp3, yz_idx1);
7489
7490 adcxq(tmp4, tmp);
7491 adoxq(tmp4, yz_idx2);
7492
7493 movl(carry, 0); // does not affect flags
7494 adcxq(carry2, carry);
7495 adoxq(carry2, carry);
7496 } else {
7497 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7498 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7499 }
7500 movq(carry, carry2);
7501
7502 movl(Address(z, idx, Address::times_4, 12), tmp3);
7503 shrq(tmp3, 32);
7504 movl(Address(z, idx, Address::times_4, 8), tmp3);
7505
7506 movl(Address(z, idx, Address::times_4, 4), tmp4);
7507 shrq(tmp4, 32);
7508 movl(Address(z, idx, Address::times_4, 0), tmp4);
7509
7510 jmp(L_third_loop);
7511
7512 bind (L_third_loop_exit);
7513
7514 andl (idx, 0x3);
7515 jcc(Assembler::zero, L_post_third_loop_done);
7516
7517 Label L_check_1;
7518 subl(idx, 2);
7519 jcc(Assembler::negative, L_check_1);
7520
7521 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7522 rorxq(yz_idx1, yz_idx1, 32);
7523 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7524 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7525 rorxq(yz_idx2, yz_idx2, 32);
7526
7527 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7528
7529 movl(Address(z, idx, Address::times_4, 4), tmp3);
7530 shrq(tmp3, 32);
7531 movl(Address(z, idx, Address::times_4, 0), tmp3);
7532 movq(carry, tmp4);
7533
7534 bind (L_check_1);
7535 addl (idx, 0x2);
7536 andl (idx, 0x1);
7537 subl(idx, 1);
7538 jcc(Assembler::negative, L_post_third_loop_done);
7539 movl(tmp4, Address(y, idx, Address::times_4, 0));
7540 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7541 movl(tmp4, Address(z, idx, Address::times_4, 0));
7542
7543 add2_with_carry(carry2, tmp3, tmp4, carry);
7544
7545 movl(Address(z, idx, Address::times_4, 0), tmp3);
7546 shrq(tmp3, 32);
7547
7548 shlq(carry2, 32);
7549 orq(tmp3, carry2);
7550 movq(carry, tmp3);
7551
7552 bind(L_post_third_loop_done);
7553 }
7554
7555 /**
7556 * Code for BigInteger::multiplyToLen() intrinsic.
7557 *
7558 * rdi: x
7559 * rax: xlen
7560 * rsi: y
7561 * rcx: ylen
7562 * r8: z
7563 * r11: tmp0
7564 * r12: tmp1
7565 * r13: tmp2
7566 * r14: tmp3
7567 * r15: tmp4
7568 * rbx: tmp5
7569 *
7570 */
7571 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7572 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7573 ShortBranchVerifier sbv(this);
7574 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7575
7576 push(tmp0);
7577 push(tmp1);
7578 push(tmp2);
7579 push(tmp3);
7580 push(tmp4);
7581 push(tmp5);
7582
7583 push(xlen);
7584
7585 const Register idx = tmp1;
7586 const Register kdx = tmp2;
7587 const Register xstart = tmp3;
7588
7589 const Register y_idx = tmp4;
7590 const Register carry = tmp5;
7591 const Register product = xlen;
7592 const Register x_xstart = tmp0;
7593
7594 // First Loop.
7595 //
7596 // final static long LONG_MASK = 0xffffffffL;
7597 // int xstart = xlen - 1;
7598 // int ystart = ylen - 1;
7599 // long carry = 0;
7600 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7601 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7602 // z[kdx] = (int)product;
7603 // carry = product >>> 32;
7604 // }
7605 // z[xstart] = (int)carry;
7606 //
7607
7608 movl(idx, ylen); // idx = ylen;
7609 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7610 xorq(carry, carry); // carry = 0;
7611
7612 Label L_done;
7613
7614 movl(xstart, xlen);
7615 decrementl(xstart);
7616 jcc(Assembler::negative, L_done);
7617
7618 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7619
7620 Label L_second_loop;
7621 testl(kdx, kdx);
7622 jcc(Assembler::zero, L_second_loop);
7623
7624 Label L_carry;
7625 subl(kdx, 1);
7626 jcc(Assembler::zero, L_carry);
7627
7628 movl(Address(z, kdx, Address::times_4, 0), carry);
7629 shrq(carry, 32);
7630 subl(kdx, 1);
7631
7632 bind(L_carry);
7633 movl(Address(z, kdx, Address::times_4, 0), carry);
7634
7635 // Second and third (nested) loops.
7636 //
7637 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7638 // carry = 0;
7639 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7640 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7641 // (z[k] & LONG_MASK) + carry;
7642 // z[k] = (int)product;
7643 // carry = product >>> 32;
7644 // }
7645 // z[i] = (int)carry;
7646 // }
7647 //
7648 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7649
7650 const Register jdx = tmp1;
7651
7652 bind(L_second_loop);
7653 xorl(carry, carry); // carry = 0;
7654 movl(jdx, ylen); // j = ystart+1
7655
7656 subl(xstart, 1); // i = xstart-1;
7657 jcc(Assembler::negative, L_done);
7658
7659 push (z);
7660
7661 Label L_last_x;
7662 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7663 subl(xstart, 1); // i = xstart-1;
7664 jcc(Assembler::negative, L_last_x);
7665
7666 if (UseBMI2Instructions) {
7667 movq(rdx, Address(x, xstart, Address::times_4, 0));
7668 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7669 } else {
7670 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7671 rorq(x_xstart, 32); // convert big-endian to little-endian
7672 }
7673
7674 Label L_third_loop_prologue;
7675 bind(L_third_loop_prologue);
7676
7677 push (x);
7678 push (xstart);
7679 push (ylen);
7680
7681
7682 if (UseBMI2Instructions) {
7683 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7684 } else { // !UseBMI2Instructions
7685 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7686 }
7687
7688 pop(ylen);
7689 pop(xlen);
7690 pop(x);
7691 pop(z);
7692
7693 movl(tmp3, xlen);
7694 addl(tmp3, 1);
7695 movl(Address(z, tmp3, Address::times_4, 0), carry);
7696 subl(tmp3, 1);
7697 jccb(Assembler::negative, L_done);
7698
7699 shrq(carry, 32);
7700 movl(Address(z, tmp3, Address::times_4, 0), carry);
7701 jmp(L_second_loop);
7702
7703 // Next infrequent code is moved outside loops.
7704 bind(L_last_x);
7705 if (UseBMI2Instructions) {
7706 movl(rdx, Address(x, 0));
7707 } else {
7708 movl(x_xstart, Address(x, 0));
7709 }
7710 jmp(L_third_loop_prologue);
7711
7712 bind(L_done);
7713
7714 pop(xlen);
7715
7716 pop(tmp5);
7717 pop(tmp4);
7718 pop(tmp3);
7719 pop(tmp2);
7720 pop(tmp1);
7721 pop(tmp0);
7722 }
7723
7724 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7725 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7726 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7727 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7728 Label VECTOR8_TAIL, VECTOR4_TAIL;
7729 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7730 Label SAME_TILL_END, DONE;
7731 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7732
7733 //scale is in rcx in both Win64 and Unix
7734 ShortBranchVerifier sbv(this);
7735
7736 shlq(length);
7737 xorq(result, result);
7738
7739 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7740 VM_Version::supports_avx512vlbw()) {
7741 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7742
7743 cmpq(length, 64);
7744 jcc(Assembler::less, VECTOR32_TAIL);
7745
7746 movq(tmp1, length);
7747 andq(tmp1, 0x3F); // tail count
7748 andq(length, ~(0x3F)); //vector count
7749
7750 bind(VECTOR64_LOOP);
7751 // AVX512 code to compare 64 byte vectors.
7752 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7753 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7754 kortestql(k7, k7);
7755 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7756 addq(result, 64);
7757 subq(length, 64);
7758 jccb(Assembler::notZero, VECTOR64_LOOP);
7759
7760 //bind(VECTOR64_TAIL);
7761 testq(tmp1, tmp1);
7762 jcc(Assembler::zero, SAME_TILL_END);
7763
7764 //bind(VECTOR64_TAIL);
7765 // AVX512 code to compare up to 63 byte vectors.
7766 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7767 shlxq(tmp2, tmp2, tmp1);
7768 notq(tmp2);
7769 kmovql(k3, tmp2);
7770
7771 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7772 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7773
7774 ktestql(k7, k3);
7775 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7776
7777 bind(VECTOR64_NOT_EQUAL);
7778 kmovql(tmp1, k7);
7779 notq(tmp1);
7780 tzcntq(tmp1, tmp1);
7781 addq(result, tmp1);
7782 shrq(result);
7783 jmp(DONE);
7784 bind(VECTOR32_TAIL);
7785 }
7786
7787 cmpq(length, 8);
7788 jcc(Assembler::equal, VECTOR8_LOOP);
7789 jcc(Assembler::less, VECTOR4_TAIL);
7790
7791 if (UseAVX >= 2) {
7792 Label VECTOR16_TAIL, VECTOR32_LOOP;
7793
7794 cmpq(length, 16);
7795 jcc(Assembler::equal, VECTOR16_LOOP);
7796 jcc(Assembler::less, VECTOR8_LOOP);
7797
7798 cmpq(length, 32);
7799 jccb(Assembler::less, VECTOR16_TAIL);
7800
7801 subq(length, 32);
7802 bind(VECTOR32_LOOP);
7803 vmovdqu(rymm0, Address(obja, result));
7804 vmovdqu(rymm1, Address(objb, result));
7805 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7806 vptest(rymm2, rymm2);
7807 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7808 addq(result, 32);
7809 subq(length, 32);
7810 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7811 addq(length, 32);
7812 jcc(Assembler::equal, SAME_TILL_END);
7813 //falling through if less than 32 bytes left //close the branch here.
7814
7815 bind(VECTOR16_TAIL);
7816 cmpq(length, 16);
7817 jccb(Assembler::less, VECTOR8_TAIL);
7818 bind(VECTOR16_LOOP);
7819 movdqu(rymm0, Address(obja, result));
7820 movdqu(rymm1, Address(objb, result));
7821 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7822 ptest(rymm2, rymm2);
7823 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7824 addq(result, 16);
7825 subq(length, 16);
7826 jcc(Assembler::equal, SAME_TILL_END);
7827 //falling through if less than 16 bytes left
7828 } else {//regular intrinsics
7829
7830 cmpq(length, 16);
7831 jccb(Assembler::less, VECTOR8_TAIL);
7832
7833 subq(length, 16);
7834 bind(VECTOR16_LOOP);
7835 movdqu(rymm0, Address(obja, result));
7836 movdqu(rymm1, Address(objb, result));
7837 pxor(rymm0, rymm1);
7838 ptest(rymm0, rymm0);
7839 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7840 addq(result, 16);
7841 subq(length, 16);
7842 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7843 addq(length, 16);
7844 jcc(Assembler::equal, SAME_TILL_END);
7845 //falling through if less than 16 bytes left
7846 }
7847
7848 bind(VECTOR8_TAIL);
7849 cmpq(length, 8);
7850 jccb(Assembler::less, VECTOR4_TAIL);
7851 bind(VECTOR8_LOOP);
7852 movq(tmp1, Address(obja, result));
7853 movq(tmp2, Address(objb, result));
7854 xorq(tmp1, tmp2);
7855 testq(tmp1, tmp1);
7856 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7857 addq(result, 8);
7858 subq(length, 8);
7859 jcc(Assembler::equal, SAME_TILL_END);
7860 //falling through if less than 8 bytes left
7861
7862 bind(VECTOR4_TAIL);
7863 cmpq(length, 4);
7864 jccb(Assembler::less, BYTES_TAIL);
7865 bind(VECTOR4_LOOP);
7866 movl(tmp1, Address(obja, result));
7867 xorl(tmp1, Address(objb, result));
7868 testl(tmp1, tmp1);
7869 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7870 addq(result, 4);
7871 subq(length, 4);
7872 jcc(Assembler::equal, SAME_TILL_END);
7873 //falling through if less than 4 bytes left
7874
7875 bind(BYTES_TAIL);
7876 bind(BYTES_LOOP);
7877 load_unsigned_byte(tmp1, Address(obja, result));
7878 load_unsigned_byte(tmp2, Address(objb, result));
7879 xorl(tmp1, tmp2);
7880 testl(tmp1, tmp1);
7881 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7882 decq(length);
7883 jcc(Assembler::zero, SAME_TILL_END);
7884 incq(result);
7885 load_unsigned_byte(tmp1, Address(obja, result));
7886 load_unsigned_byte(tmp2, Address(objb, result));
7887 xorl(tmp1, tmp2);
7888 testl(tmp1, tmp1);
7889 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7890 decq(length);
7891 jcc(Assembler::zero, SAME_TILL_END);
7892 incq(result);
7893 load_unsigned_byte(tmp1, Address(obja, result));
7894 load_unsigned_byte(tmp2, Address(objb, result));
7895 xorl(tmp1, tmp2);
7896 testl(tmp1, tmp1);
7897 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7898 jmp(SAME_TILL_END);
7899
7900 if (UseAVX >= 2) {
7901 bind(VECTOR32_NOT_EQUAL);
7902 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7903 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7904 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7905 vpmovmskb(tmp1, rymm0);
7906 bsfq(tmp1, tmp1);
7907 addq(result, tmp1);
7908 shrq(result);
7909 jmp(DONE);
7910 }
7911
7912 bind(VECTOR16_NOT_EQUAL);
7913 if (UseAVX >= 2) {
7914 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7915 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7916 pxor(rymm0, rymm2);
7917 } else {
7918 pcmpeqb(rymm2, rymm2);
7919 pxor(rymm0, rymm1);
7920 pcmpeqb(rymm0, rymm1);
7921 pxor(rymm0, rymm2);
7922 }
7923 pmovmskb(tmp1, rymm0);
7924 bsfq(tmp1, tmp1);
7925 addq(result, tmp1);
7926 shrq(result);
7927 jmpb(DONE);
7928
7929 bind(VECTOR8_NOT_EQUAL);
7930 bind(VECTOR4_NOT_EQUAL);
7931 bsfq(tmp1, tmp1);
7932 shrq(tmp1, 3);
7933 addq(result, tmp1);
7934 bind(BYTES_NOT_EQUAL);
7935 shrq(result);
7936 jmpb(DONE);
7937
7938 bind(SAME_TILL_END);
7939 mov64(result, -1);
7940
7941 bind(DONE);
7942 }
7943
7944 //Helper functions for square_to_len()
7945
7946 /**
7947 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7948 * Preserves x and z and modifies rest of the registers.
7949 */
7950 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7951 // Perform square and right shift by 1
7952 // Handle odd xlen case first, then for even xlen do the following
7953 // jlong carry = 0;
7954 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7955 // huge_128 product = x[j:j+1] * x[j:j+1];
7956 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7957 // z[i+2:i+3] = (jlong)(product >>> 1);
7958 // carry = (jlong)product;
7959 // }
7960
7961 xorq(tmp5, tmp5); // carry
7962 xorq(rdxReg, rdxReg);
7963 xorl(tmp1, tmp1); // index for x
7964 xorl(tmp4, tmp4); // index for z
7965
7966 Label L_first_loop, L_first_loop_exit;
7967
7968 testl(xlen, 1);
7969 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7970
7971 // Square and right shift by 1 the odd element using 32 bit multiply
7972 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7973 imulq(raxReg, raxReg);
7974 shrq(raxReg, 1);
7975 adcq(tmp5, 0);
7976 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7977 incrementl(tmp1);
7978 addl(tmp4, 2);
7979
7980 // Square and right shift by 1 the rest using 64 bit multiply
7981 bind(L_first_loop);
7982 cmpptr(tmp1, xlen);
7983 jccb(Assembler::equal, L_first_loop_exit);
7984
7985 // Square
7986 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7987 rorq(raxReg, 32); // convert big-endian to little-endian
7988 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7989
7990 // Right shift by 1 and save carry
7991 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7992 rcrq(rdxReg, 1);
7993 rcrq(raxReg, 1);
7994 adcq(tmp5, 0);
7995
7996 // Store result in z
7997 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7998 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7999
8000 // Update indices for x and z
8001 addl(tmp1, 2);
8002 addl(tmp4, 4);
8003 jmp(L_first_loop);
8004
8005 bind(L_first_loop_exit);
8006 }
8007
8008
8009 /**
8010 * Perform the following multiply add operation using BMI2 instructions
8011 * carry:sum = sum + op1*op2 + carry
8012 * op2 should be in rdx
8013 * op2 is preserved, all other registers are modified
8014 */
8015 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
8016 // assert op2 is rdx
8017 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
8018 addq(sum, carry);
8019 adcq(tmp2, 0);
8020 addq(sum, op1);
8021 adcq(tmp2, 0);
8022 movq(carry, tmp2);
8023 }
8024
8025 /**
8026 * Perform the following multiply add operation:
8027 * carry:sum = sum + op1*op2 + carry
8028 * Preserves op1, op2 and modifies rest of registers
8029 */
8030 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8031 // rdx:rax = op1 * op2
8032 movq(raxReg, op2);
8033 mulq(op1);
8034
8035 // rdx:rax = sum + carry + rdx:rax
8036 addq(sum, carry);
8037 adcq(rdxReg, 0);
8038 addq(sum, raxReg);
8039 adcq(rdxReg, 0);
8040
8041 // carry:sum = rdx:sum
8042 movq(carry, rdxReg);
8043 }
8044
8045 /**
8046 * Add 64 bit long carry into z[] with carry propagation.
8047 * Preserves z and carry register values and modifies rest of registers.
8048 *
8049 */
8050 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8051 Label L_fourth_loop, L_fourth_loop_exit;
8052
8053 movl(tmp1, 1);
8054 subl(zlen, 2);
8055 addq(Address(z, zlen, Address::times_4, 0), carry);
8056
8057 bind(L_fourth_loop);
8058 jccb(Assembler::carryClear, L_fourth_loop_exit);
8059 subl(zlen, 2);
8060 jccb(Assembler::negative, L_fourth_loop_exit);
8061 addq(Address(z, zlen, Address::times_4, 0), tmp1);
8062 jmp(L_fourth_loop);
8063 bind(L_fourth_loop_exit);
8064 }
8065
8066 /**
8067 * Shift z[] left by 1 bit.
8068 * Preserves x, len, z and zlen registers and modifies rest of the registers.
8069 *
8070 */
8071 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8072
8073 Label L_fifth_loop, L_fifth_loop_exit;
8074
8075 // Fifth loop
8076 // Perform primitiveLeftShift(z, zlen, 1)
8077
8078 const Register prev_carry = tmp1;
8079 const Register new_carry = tmp4;
8080 const Register value = tmp2;
8081 const Register zidx = tmp3;
8082
8083 // int zidx, carry;
8084 // long value;
8085 // carry = 0;
8086 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8087 // (carry:value) = (z[i] << 1) | carry ;
8088 // z[i] = value;
8089 // }
8090
8091 movl(zidx, zlen);
8092 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8093
8094 bind(L_fifth_loop);
8095 decl(zidx); // Use decl to preserve carry flag
8096 decl(zidx);
8097 jccb(Assembler::negative, L_fifth_loop_exit);
8098
8099 if (UseBMI2Instructions) {
8100 movq(value, Address(z, zidx, Address::times_4, 0));
8101 rclq(value, 1);
8102 rorxq(value, value, 32);
8103 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8104 }
8105 else {
8106 // clear new_carry
8107 xorl(new_carry, new_carry);
8108
8109 // Shift z[i] by 1, or in previous carry and save new carry
8110 movq(value, Address(z, zidx, Address::times_4, 0));
8111 shlq(value, 1);
8112 adcl(new_carry, 0);
8113
8114 orq(value, prev_carry);
8115 rorq(value, 0x20);
8116 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8117
8118 // Set previous carry = new carry
8119 movl(prev_carry, new_carry);
8120 }
8121 jmp(L_fifth_loop);
8122
8123 bind(L_fifth_loop_exit);
8124 }
8125
8126
8127 /**
8128 * Code for BigInteger::squareToLen() intrinsic
8129 *
8130 * rdi: x
8131 * rsi: len
8132 * r8: z
8133 * rcx: zlen
8134 * r12: tmp1
8135 * r13: tmp2
8136 * r14: tmp3
8137 * r15: tmp4
8138 * rbx: tmp5
8139 *
8140 */
8141 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8142
8143 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8144 push(tmp1);
8145 push(tmp2);
8146 push(tmp3);
8147 push(tmp4);
8148 push(tmp5);
8149
8150 // First loop
8151 // Store the squares, right shifted one bit (i.e., divided by 2).
8152 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8153
8154 // Add in off-diagonal sums.
8155 //
8156 // Second, third (nested) and fourth loops.
8157 // zlen +=2;
8158 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8159 // carry = 0;
8160 // long op2 = x[xidx:xidx+1];
8161 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8162 // k -= 2;
8163 // long op1 = x[j:j+1];
8164 // long sum = z[k:k+1];
8165 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8166 // z[k:k+1] = sum;
8167 // }
8168 // add_one_64(z, k, carry, tmp_regs);
8169 // }
8170
8171 const Register carry = tmp5;
8172 const Register sum = tmp3;
8173 const Register op1 = tmp4;
8174 Register op2 = tmp2;
8175
8176 push(zlen);
8177 push(len);
8178 addl(zlen,2);
8179 bind(L_second_loop);
8180 xorq(carry, carry);
8181 subl(zlen, 4);
8182 subl(len, 2);
8183 push(zlen);
8184 push(len);
8185 cmpl(len, 0);
8186 jccb(Assembler::lessEqual, L_second_loop_exit);
8187
8188 // Multiply an array by one 64 bit long.
8189 if (UseBMI2Instructions) {
8190 op2 = rdxReg;
8191 movq(op2, Address(x, len, Address::times_4, 0));
8192 rorxq(op2, op2, 32);
8193 }
8194 else {
8195 movq(op2, Address(x, len, Address::times_4, 0));
8196 rorq(op2, 32);
8197 }
8198
8199 bind(L_third_loop);
8200 decrementl(len);
8201 jccb(Assembler::negative, L_third_loop_exit);
8202 decrementl(len);
8203 jccb(Assembler::negative, L_last_x);
8204
8205 movq(op1, Address(x, len, Address::times_4, 0));
8206 rorq(op1, 32);
8207
8208 bind(L_multiply);
8209 subl(zlen, 2);
8210 movq(sum, Address(z, zlen, Address::times_4, 0));
8211
8212 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8213 if (UseBMI2Instructions) {
8214 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8215 }
8216 else {
8217 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8218 }
8219
8220 movq(Address(z, zlen, Address::times_4, 0), sum);
8221
8222 jmp(L_third_loop);
8223 bind(L_third_loop_exit);
8224
8225 // Fourth loop
8226 // Add 64 bit long carry into z with carry propagation.
8227 // Uses offsetted zlen.
8228 add_one_64(z, zlen, carry, tmp1);
8229
8230 pop(len);
8231 pop(zlen);
8232 jmp(L_second_loop);
8233
8234 // Next infrequent code is moved outside loops.
8235 bind(L_last_x);
8236 movl(op1, Address(x, 0));
8237 jmp(L_multiply);
8238
8239 bind(L_second_loop_exit);
8240 pop(len);
8241 pop(zlen);
8242 pop(len);
8243 pop(zlen);
8244
8245 // Fifth loop
8246 // Shift z left 1 bit.
8247 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8248
8249 // z[zlen-1] |= x[len-1] & 1;
8250 movl(tmp3, Address(x, len, Address::times_4, -4));
8251 andl(tmp3, 1);
8252 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8253
8254 pop(tmp5);
8255 pop(tmp4);
8256 pop(tmp3);
8257 pop(tmp2);
8258 pop(tmp1);
8259 }
8260
8261 /**
8262 * Helper function for mul_add()
8263 * Multiply the in[] by int k and add to out[] starting at offset offs using
8264 * 128 bit by 32 bit multiply and return the carry in tmp5.
8265 * Only quad int aligned length of in[] is operated on in this function.
8266 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8267 * This function preserves out, in and k registers.
8268 * len and offset point to the appropriate index in "in" & "out" correspondingly
8269 * tmp5 has the carry.
8270 * other registers are temporary and are modified.
8271 *
8272 */
8273 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8274 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8275 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8276
8277 Label L_first_loop, L_first_loop_exit;
8278
8279 movl(tmp1, len);
8280 shrl(tmp1, 2);
8281
8282 bind(L_first_loop);
8283 subl(tmp1, 1);
8284 jccb(Assembler::negative, L_first_loop_exit);
8285
8286 subl(len, 4);
8287 subl(offset, 4);
8288
8289 Register op2 = tmp2;
8290 const Register sum = tmp3;
8291 const Register op1 = tmp4;
8292 const Register carry = tmp5;
8293
8294 if (UseBMI2Instructions) {
8295 op2 = rdxReg;
8296 }
8297
8298 movq(op1, Address(in, len, Address::times_4, 8));
8299 rorq(op1, 32);
8300 movq(sum, Address(out, offset, Address::times_4, 8));
8301 rorq(sum, 32);
8302 if (UseBMI2Instructions) {
8303 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8304 }
8305 else {
8306 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8307 }
8308 // Store back in big endian from little endian
8309 rorq(sum, 0x20);
8310 movq(Address(out, offset, Address::times_4, 8), sum);
8311
8312 movq(op1, Address(in, len, Address::times_4, 0));
8313 rorq(op1, 32);
8314 movq(sum, Address(out, offset, Address::times_4, 0));
8315 rorq(sum, 32);
8316 if (UseBMI2Instructions) {
8317 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8318 }
8319 else {
8320 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8321 }
8322 // Store back in big endian from little endian
8323 rorq(sum, 0x20);
8324 movq(Address(out, offset, Address::times_4, 0), sum);
8325
8326 jmp(L_first_loop);
8327 bind(L_first_loop_exit);
8328 }
8329
8330 /**
8331 * Code for BigInteger::mulAdd() intrinsic
8332 *
8333 * rdi: out
8334 * rsi: in
8335 * r11: offs (out.length - offset)
8336 * rcx: len
8337 * r8: k
8338 * r12: tmp1
8339 * r13: tmp2
8340 * r14: tmp3
8341 * r15: tmp4
8342 * rbx: tmp5
8343 * Multiply the in[] by word k and add to out[], return the carry in rax
8344 */
8345 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8346 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8347 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8348
8349 Label L_carry, L_last_in, L_done;
8350
8351 // carry = 0;
8352 // for (int j=len-1; j >= 0; j--) {
8353 // long product = (in[j] & LONG_MASK) * kLong +
8354 // (out[offs] & LONG_MASK) + carry;
8355 // out[offs--] = (int)product;
8356 // carry = product >>> 32;
8357 // }
8358 //
8359 push(tmp1);
8360 push(tmp2);
8361 push(tmp3);
8362 push(tmp4);
8363 push(tmp5);
8364
8365 Register op2 = tmp2;
8366 const Register sum = tmp3;
8367 const Register op1 = tmp4;
8368 const Register carry = tmp5;
8369
8370 if (UseBMI2Instructions) {
8371 op2 = rdxReg;
8372 movl(op2, k);
8373 }
8374 else {
8375 movl(op2, k);
8376 }
8377
8378 xorq(carry, carry);
8379
8380 //First loop
8381
8382 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8383 //The carry is in tmp5
8384 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8385
8386 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8387 decrementl(len);
8388 jccb(Assembler::negative, L_carry);
8389 decrementl(len);
8390 jccb(Assembler::negative, L_last_in);
8391
8392 movq(op1, Address(in, len, Address::times_4, 0));
8393 rorq(op1, 32);
8394
8395 subl(offs, 2);
8396 movq(sum, Address(out, offs, Address::times_4, 0));
8397 rorq(sum, 32);
8398
8399 if (UseBMI2Instructions) {
8400 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8401 }
8402 else {
8403 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8404 }
8405
8406 // Store back in big endian from little endian
8407 rorq(sum, 0x20);
8408 movq(Address(out, offs, Address::times_4, 0), sum);
8409
8410 testl(len, len);
8411 jccb(Assembler::zero, L_carry);
8412
8413 //Multiply the last in[] entry, if any
8414 bind(L_last_in);
8415 movl(op1, Address(in, 0));
8416 movl(sum, Address(out, offs, Address::times_4, -4));
8417
8418 movl(raxReg, k);
8419 mull(op1); //tmp4 * eax -> edx:eax
8420 addl(sum, carry);
8421 adcl(rdxReg, 0);
8422 addl(sum, raxReg);
8423 adcl(rdxReg, 0);
8424 movl(carry, rdxReg);
8425
8426 movl(Address(out, offs, Address::times_4, -4), sum);
8427
8428 bind(L_carry);
8429 //return tmp5/carry as carry in rax
8430 movl(rax, carry);
8431
8432 bind(L_done);
8433 pop(tmp5);
8434 pop(tmp4);
8435 pop(tmp3);
8436 pop(tmp2);
8437 pop(tmp1);
8438 }
8439
8440 /**
8441 * Emits code to update CRC-32 with a byte value according to constants in table
8442 *
8443 * @param [in,out]crc Register containing the crc.
8444 * @param [in]val Register containing the byte to fold into the CRC.
8445 * @param [in]table Register containing the table of crc constants.
8446 *
8447 * uint32_t crc;
8448 * val = crc_table[(val ^ crc) & 0xFF];
8449 * crc = val ^ (crc >> 8);
8450 *
8451 */
8452 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8453 xorl(val, crc);
8454 andl(val, 0xFF);
8455 shrl(crc, 8); // unsigned shift
8456 xorl(crc, Address(table, val, Address::times_4, 0));
8457 }
8458
8459 /**
8460 * Fold 128-bit data chunk
8461 */
8462 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8463 if (UseAVX > 0) {
8464 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8465 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8466 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8467 pxor(xcrc, xtmp);
8468 } else {
8469 movdqa(xtmp, xcrc);
8470 pclmulhdq(xtmp, xK); // [123:64]
8471 pclmulldq(xcrc, xK); // [63:0]
8472 pxor(xcrc, xtmp);
8473 movdqu(xtmp, Address(buf, offset));
8474 pxor(xcrc, xtmp);
8475 }
8476 }
8477
8478 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8479 if (UseAVX > 0) {
8480 vpclmulhdq(xtmp, xK, xcrc);
8481 vpclmulldq(xcrc, xK, xcrc);
8482 pxor(xcrc, xbuf);
8483 pxor(xcrc, xtmp);
8484 } else {
8485 movdqa(xtmp, xcrc);
8486 pclmulhdq(xtmp, xK);
8487 pclmulldq(xcrc, xK);
8488 pxor(xcrc, xbuf);
8489 pxor(xcrc, xtmp);
8490 }
8491 }
8492
8493 /**
8494 * 8-bit folds to compute 32-bit CRC
8495 *
8496 * uint64_t xcrc;
8497 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8498 */
8499 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8500 movdl(tmp, xcrc);
8501 andl(tmp, 0xFF);
8502 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8503 psrldq(xcrc, 1); // unsigned shift one byte
8504 pxor(xcrc, xtmp);
8505 }
8506
8507 /**
8508 * uint32_t crc;
8509 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8510 */
8511 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8512 movl(tmp, crc);
8513 andl(tmp, 0xFF);
8514 shrl(crc, 8);
8515 xorl(crc, Address(table, tmp, Address::times_4, 0));
8516 }
8517
8518 /**
8519 * @param crc register containing existing CRC (32-bit)
8520 * @param buf register pointing to input byte buffer (byte*)
8521 * @param len register containing number of bytes
8522 * @param table register that will contain address of CRC table
8523 * @param tmp scratch register
8524 */
8525 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8526 assert_different_registers(crc, buf, len, table, tmp, rax);
8527
8528 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8529 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8530
8531 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8532 // context for the registers used, where all instructions below are using 128-bit mode
8533 // On EVEX without VL and BW, these instructions will all be AVX.
8534 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8535 notl(crc); // ~crc
8536 cmpl(len, 16);
8537 jcc(Assembler::less, L_tail);
8538
8539 // Align buffer to 16 bytes
8540 movl(tmp, buf);
8541 andl(tmp, 0xF);
8542 jccb(Assembler::zero, L_aligned);
8543 subl(tmp, 16);
8544 addl(len, tmp);
8545
8546 align(4);
8547 BIND(L_align_loop);
8548 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8549 update_byte_crc32(crc, rax, table);
8550 increment(buf);
8551 incrementl(tmp);
8552 jccb(Assembler::less, L_align_loop);
8553
8554 BIND(L_aligned);
8555 movl(tmp, len); // save
8556 shrl(len, 4);
8557 jcc(Assembler::zero, L_tail_restore);
8558
8559 // Fold crc into first bytes of vector
8560 movdqa(xmm1, Address(buf, 0));
8561 movdl(rax, xmm1);
8562 xorl(crc, rax);
8563 if (VM_Version::supports_sse4_1()) {
8564 pinsrd(xmm1, crc, 0);
8565 } else {
8566 pinsrw(xmm1, crc, 0);
8567 shrl(crc, 16);
8568 pinsrw(xmm1, crc, 1);
8569 }
8570 addptr(buf, 16);
8571 subl(len, 4); // len > 0
8572 jcc(Assembler::less, L_fold_tail);
8573
8574 movdqa(xmm2, Address(buf, 0));
8575 movdqa(xmm3, Address(buf, 16));
8576 movdqa(xmm4, Address(buf, 32));
8577 addptr(buf, 48);
8578 subl(len, 3);
8579 jcc(Assembler::lessEqual, L_fold_512b);
8580
8581 // Fold total 512 bits of polynomial on each iteration,
8582 // 128 bits per each of 4 parallel streams.
8583 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8584
8585 align32();
8586 BIND(L_fold_512b_loop);
8587 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8588 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8589 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8590 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8591 addptr(buf, 64);
8592 subl(len, 4);
8593 jcc(Assembler::greater, L_fold_512b_loop);
8594
8595 // Fold 512 bits to 128 bits.
8596 BIND(L_fold_512b);
8597 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8598 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8599 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8600 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8601
8602 // Fold the rest of 128 bits data chunks
8603 BIND(L_fold_tail);
8604 addl(len, 3);
8605 jccb(Assembler::lessEqual, L_fold_128b);
8606 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8607
8608 BIND(L_fold_tail_loop);
8609 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8610 addptr(buf, 16);
8611 decrementl(len);
8612 jccb(Assembler::greater, L_fold_tail_loop);
8613
8614 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8615 BIND(L_fold_128b);
8616 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8617 if (UseAVX > 0) {
8618 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8619 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8620 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8621 } else {
8622 movdqa(xmm2, xmm0);
8623 pclmulqdq(xmm2, xmm1, 0x1);
8624 movdqa(xmm3, xmm0);
8625 pand(xmm3, xmm2);
8626 pclmulqdq(xmm0, xmm3, 0x1);
8627 }
8628 psrldq(xmm1, 8);
8629 psrldq(xmm2, 4);
8630 pxor(xmm0, xmm1);
8631 pxor(xmm0, xmm2);
8632
8633 // 8 8-bit folds to compute 32-bit CRC.
8634 for (int j = 0; j < 4; j++) {
8635 fold_8bit_crc32(xmm0, table, xmm1, rax);
8636 }
8637 movdl(crc, xmm0); // mov 32 bits to general register
8638 for (int j = 0; j < 4; j++) {
8639 fold_8bit_crc32(crc, table, rax);
8640 }
8641
8642 BIND(L_tail_restore);
8643 movl(len, tmp); // restore
8644 BIND(L_tail);
8645 andl(len, 0xf);
8646 jccb(Assembler::zero, L_exit);
8647
8648 // Fold the rest of bytes
8649 align(4);
8650 BIND(L_tail_loop);
8651 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8652 update_byte_crc32(crc, rax, table);
8653 increment(buf);
8654 decrementl(len);
8655 jccb(Assembler::greater, L_tail_loop);
8656
8657 BIND(L_exit);
8658 notl(crc); // ~c
8659 }
8660
8661 // Helper function for AVX 512 CRC32
8662 // Fold 512-bit data chunks
8663 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8664 Register pos, int offset) {
8665 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8666 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8667 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8668 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8669 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8670 }
8671
8672 // Helper function for AVX 512 CRC32
8673 // Compute CRC32 for < 256B buffers
8674 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8675 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8676 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8677
8678 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8679 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8680 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8681
8682 // check if there is enough buffer to be able to fold 16B at a time
8683 cmpl(len, 32);
8684 jcc(Assembler::less, L_less_than_32);
8685
8686 // if there is, load the constants
8687 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8688 movdl(xmm0, crc); // get the initial crc value
8689 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8690 pxor(xmm7, xmm0);
8691
8692 // update the buffer pointer
8693 addl(pos, 16);
8694 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8695 subl(len, 32);
8696 jmp(L_16B_reduction_loop);
8697
8698 bind(L_less_than_32);
8699 //mov initial crc to the return value. this is necessary for zero - length buffers.
8700 movl(rax, crc);
8701 testl(len, len);
8702 jcc(Assembler::equal, L_cleanup);
8703
8704 movdl(xmm0, crc); //get the initial crc value
8705
8706 cmpl(len, 16);
8707 jcc(Assembler::equal, L_exact_16_left);
8708 jcc(Assembler::less, L_less_than_16_left);
8709
8710 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8711 pxor(xmm7, xmm0); //xor the initial crc value
8712 addl(pos, 16);
8713 subl(len, 16);
8714 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8715 jmp(L_get_last_two_xmms);
8716
8717 bind(L_less_than_16_left);
8718 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8719 pxor(xmm1, xmm1);
8720 movptr(tmp1, rsp);
8721 movdqu(Address(tmp1, 0 * 16), xmm1);
8722
8723 cmpl(len, 4);
8724 jcc(Assembler::less, L_only_less_than_4);
8725
8726 //backup the counter value
8727 movl(tmp2, len);
8728 cmpl(len, 8);
8729 jcc(Assembler::less, L_less_than_8_left);
8730
8731 //load 8 Bytes
8732 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8733 movq(Address(tmp1, 0 * 16), rax);
8734 addptr(tmp1, 8);
8735 subl(len, 8);
8736 addl(pos, 8);
8737
8738 bind(L_less_than_8_left);
8739 cmpl(len, 4);
8740 jcc(Assembler::less, L_less_than_4_left);
8741
8742 //load 4 Bytes
8743 movl(rax, Address(buf, pos, Address::times_1, 0));
8744 movl(Address(tmp1, 0 * 16), rax);
8745 addptr(tmp1, 4);
8746 subl(len, 4);
8747 addl(pos, 4);
8748
8749 bind(L_less_than_4_left);
8750 cmpl(len, 2);
8751 jcc(Assembler::less, L_less_than_2_left);
8752
8753 // load 2 Bytes
8754 movw(rax, Address(buf, pos, Address::times_1, 0));
8755 movl(Address(tmp1, 0 * 16), rax);
8756 addptr(tmp1, 2);
8757 subl(len, 2);
8758 addl(pos, 2);
8759
8760 bind(L_less_than_2_left);
8761 cmpl(len, 1);
8762 jcc(Assembler::less, L_zero_left);
8763
8764 // load 1 Byte
8765 movb(rax, Address(buf, pos, Address::times_1, 0));
8766 movb(Address(tmp1, 0 * 16), rax);
8767
8768 bind(L_zero_left);
8769 movdqu(xmm7, Address(rsp, 0));
8770 pxor(xmm7, xmm0); //xor the initial crc value
8771
8772 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8773 movdqu(xmm0, Address(rax, tmp2));
8774 pshufb(xmm7, xmm0);
8775 jmp(L_128_done);
8776
8777 bind(L_exact_16_left);
8778 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8779 pxor(xmm7, xmm0); //xor the initial crc value
8780 jmp(L_128_done);
8781
8782 bind(L_only_less_than_4);
8783 cmpl(len, 3);
8784 jcc(Assembler::less, L_only_less_than_3);
8785
8786 // load 3 Bytes
8787 movb(rax, Address(buf, pos, Address::times_1, 0));
8788 movb(Address(tmp1, 0), rax);
8789
8790 movb(rax, Address(buf, pos, Address::times_1, 1));
8791 movb(Address(tmp1, 1), rax);
8792
8793 movb(rax, Address(buf, pos, Address::times_1, 2));
8794 movb(Address(tmp1, 2), rax);
8795
8796 movdqu(xmm7, Address(rsp, 0));
8797 pxor(xmm7, xmm0); //xor the initial crc value
8798
8799 pslldq(xmm7, 0x5);
8800 jmp(L_barrett);
8801 bind(L_only_less_than_3);
8802 cmpl(len, 2);
8803 jcc(Assembler::less, L_only_less_than_2);
8804
8805 // load 2 Bytes
8806 movb(rax, Address(buf, pos, Address::times_1, 0));
8807 movb(Address(tmp1, 0), rax);
8808
8809 movb(rax, Address(buf, pos, Address::times_1, 1));
8810 movb(Address(tmp1, 1), rax);
8811
8812 movdqu(xmm7, Address(rsp, 0));
8813 pxor(xmm7, xmm0); //xor the initial crc value
8814
8815 pslldq(xmm7, 0x6);
8816 jmp(L_barrett);
8817
8818 bind(L_only_less_than_2);
8819 //load 1 Byte
8820 movb(rax, Address(buf, pos, Address::times_1, 0));
8821 movb(Address(tmp1, 0), rax);
8822
8823 movdqu(xmm7, Address(rsp, 0));
8824 pxor(xmm7, xmm0); //xor the initial crc value
8825
8826 pslldq(xmm7, 0x7);
8827 }
8828
8829 /**
8830 * Compute CRC32 using AVX512 instructions
8831 * param crc register containing existing CRC (32-bit)
8832 * param buf register pointing to input byte buffer (byte*)
8833 * param len register containing number of bytes
8834 * param table address of crc or crc32c table
8835 * param tmp1 scratch register
8836 * param tmp2 scratch register
8837 * return rax result register
8838 *
8839 * This routine is identical for crc32c with the exception of the precomputed constant
8840 * table which will be passed as the table argument. The calculation steps are
8841 * the same for both variants.
8842 */
8843 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8844 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8845
8846 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8847 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8848 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8849 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8850 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8851
8852 const Register pos = r12;
8853 push(r12);
8854 subptr(rsp, 16 * 2 + 8);
8855
8856 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8857 // context for the registers used, where all instructions below are using 128-bit mode
8858 // On EVEX without VL and BW, these instructions will all be AVX.
8859 movl(pos, 0);
8860
8861 // check if smaller than 256B
8862 cmpl(len, 256);
8863 jcc(Assembler::less, L_less_than_256);
8864
8865 // load the initial crc value
8866 movdl(xmm10, crc);
8867
8868 // receive the initial 64B data, xor the initial crc value
8869 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8870 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8871 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8872 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8873
8874 subl(len, 256);
8875 cmpl(len, 256);
8876 jcc(Assembler::less, L_fold_128_B_loop);
8877
8878 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8879 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8880 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8881 subl(len, 256);
8882
8883 bind(L_fold_256_B_loop);
8884 addl(pos, 256);
8885 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8886 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8887 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8888 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8889
8890 subl(len, 256);
8891 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8892
8893 // Fold 256 into 128
8894 addl(pos, 256);
8895 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8896 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8897 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8898
8899 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8900 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8901 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8902
8903 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8904 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8905
8906 addl(len, 128);
8907 jmp(L_fold_128_B_register);
8908
8909 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8910 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8911
8912 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8913 bind(L_fold_128_B_loop);
8914 addl(pos, 128);
8915 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8916 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8917
8918 subl(len, 128);
8919 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8920
8921 addl(pos, 128);
8922
8923 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8924 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8925 bind(L_fold_128_B_register);
8926 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8927 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8928 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8929 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8930 // save last that has no multiplicand
8931 vextracti64x2(xmm7, xmm4, 3);
8932
8933 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8934 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8935 // Needed later in reduction loop
8936 movdqu(xmm10, Address(table, 1 * 16));
8937 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8938 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8939
8940 // Swap 1,0,3,2 - 01 00 11 10
8941 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8942 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8943 vextracti128(xmm5, xmm8, 1);
8944 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8945
8946 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8947 // instead of a cmp instruction, we use the negative flag with the jl instruction
8948 addl(len, 128 - 16);
8949 jcc(Assembler::less, L_final_reduction_for_128);
8950
8951 bind(L_16B_reduction_loop);
8952 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8953 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8954 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8955 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8956 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8957 addl(pos, 16);
8958 subl(len, 16);
8959 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8960
8961 bind(L_final_reduction_for_128);
8962 addl(len, 16);
8963 jcc(Assembler::equal, L_128_done);
8964
8965 bind(L_get_last_two_xmms);
8966 movdqu(xmm2, xmm7);
8967 addl(pos, len);
8968 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8969 subl(pos, len);
8970
8971 // get rid of the extra data that was loaded before
8972 // load the shift constant
8973 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8974 movdqu(xmm0, Address(rax, len));
8975 addl(rax, len);
8976
8977 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8978 //Change mask to 512
8979 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8980 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8981
8982 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8983 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8984 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8985 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8986 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8987
8988 bind(L_128_done);
8989 // compute crc of a 128-bit value
8990 movdqu(xmm10, Address(table, 3 * 16));
8991 movdqu(xmm0, xmm7);
8992
8993 // 64b fold
8994 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8995 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8996 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8997
8998 // 32b fold
8999 movdqu(xmm0, xmm7);
9000 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
9001 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
9002 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
9003 jmp(L_barrett);
9004
9005 bind(L_less_than_256);
9006 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
9007
9008 //barrett reduction
9009 bind(L_barrett);
9010 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
9011 movdqu(xmm1, xmm7);
9012 movdqu(xmm2, xmm7);
9013 movdqu(xmm10, Address(table, 4 * 16));
9014
9015 pclmulqdq(xmm7, xmm10, 0x0);
9016 pxor(xmm7, xmm2);
9017 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
9018 movdqu(xmm2, xmm7);
9019 pclmulqdq(xmm7, xmm10, 0x10);
9020 pxor(xmm7, xmm2);
9021 pxor(xmm7, xmm1);
9022 pextrd(crc, xmm7, 2);
9023
9024 bind(L_cleanup);
9025 addptr(rsp, 16 * 2 + 8);
9026 pop(r12);
9027 }
9028
9029 // S. Gueron / Information Processing Letters 112 (2012) 184
9030 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
9031 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
9032 // Output: the 64-bit carry-less product of B * CONST
9033 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
9034 Register tmp1, Register tmp2, Register tmp3) {
9035 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9036 if (n > 0) {
9037 addq(tmp3, n * 256 * 8);
9038 }
9039 // Q1 = TABLEExt[n][B & 0xFF];
9040 movl(tmp1, in);
9041 andl(tmp1, 0x000000FF);
9042 shll(tmp1, 3);
9043 addq(tmp1, tmp3);
9044 movq(tmp1, Address(tmp1, 0));
9045
9046 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9047 movl(tmp2, in);
9048 shrl(tmp2, 8);
9049 andl(tmp2, 0x000000FF);
9050 shll(tmp2, 3);
9051 addq(tmp2, tmp3);
9052 movq(tmp2, Address(tmp2, 0));
9053
9054 shlq(tmp2, 8);
9055 xorq(tmp1, tmp2);
9056
9057 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9058 movl(tmp2, in);
9059 shrl(tmp2, 16);
9060 andl(tmp2, 0x000000FF);
9061 shll(tmp2, 3);
9062 addq(tmp2, tmp3);
9063 movq(tmp2, Address(tmp2, 0));
9064
9065 shlq(tmp2, 16);
9066 xorq(tmp1, tmp2);
9067
9068 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9069 shrl(in, 24);
9070 andl(in, 0x000000FF);
9071 shll(in, 3);
9072 addq(in, tmp3);
9073 movq(in, Address(in, 0));
9074
9075 shlq(in, 24);
9076 xorq(in, tmp1);
9077 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9078 }
9079
9080 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9081 Register in_out,
9082 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9083 XMMRegister w_xtmp2,
9084 Register tmp1,
9085 Register n_tmp2, Register n_tmp3) {
9086 if (is_pclmulqdq_supported) {
9087 movdl(w_xtmp1, in_out); // modified blindly
9088
9089 movl(tmp1, const_or_pre_comp_const_index);
9090 movdl(w_xtmp2, tmp1);
9091 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9092
9093 movdq(in_out, w_xtmp1);
9094 } else {
9095 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
9096 }
9097 }
9098
9099 // Recombination Alternative 2: No bit-reflections
9100 // T1 = (CRC_A * U1) << 1
9101 // T2 = (CRC_B * U2) << 1
9102 // C1 = T1 >> 32
9103 // C2 = T2 >> 32
9104 // T1 = T1 & 0xFFFFFFFF
9105 // T2 = T2 & 0xFFFFFFFF
9106 // T1 = CRC32(0, T1)
9107 // T2 = CRC32(0, T2)
9108 // C1 = C1 ^ T1
9109 // C2 = C2 ^ T2
9110 // CRC = C1 ^ C2 ^ CRC_C
9111 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9112 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9113 Register tmp1, Register tmp2,
9114 Register n_tmp3) {
9115 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9116 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9117 shlq(in_out, 1);
9118 movl(tmp1, in_out);
9119 shrq(in_out, 32);
9120 xorl(tmp2, tmp2);
9121 crc32(tmp2, tmp1, 4);
9122 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9123 shlq(in1, 1);
9124 movl(tmp1, in1);
9125 shrq(in1, 32);
9126 xorl(tmp2, tmp2);
9127 crc32(tmp2, tmp1, 4);
9128 xorl(in1, tmp2);
9129 xorl(in_out, in1);
9130 xorl(in_out, in2);
9131 }
9132
9133 // Set N to predefined value
9134 // Subtract from a length of a buffer
9135 // execute in a loop:
9136 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9137 // for i = 1 to N do
9138 // CRC_A = CRC32(CRC_A, A[i])
9139 // CRC_B = CRC32(CRC_B, B[i])
9140 // CRC_C = CRC32(CRC_C, C[i])
9141 // end for
9142 // Recombine
9143 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9144 Register in_out1, Register in_out2, Register in_out3,
9145 Register tmp1, Register tmp2, Register tmp3,
9146 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9147 Register tmp4, Register tmp5,
9148 Register n_tmp6) {
9149 Label L_processPartitions;
9150 Label L_processPartition;
9151 Label L_exit;
9152
9153 bind(L_processPartitions);
9154 cmpl(in_out1, 3 * size);
9155 jcc(Assembler::less, L_exit);
9156 xorl(tmp1, tmp1);
9157 xorl(tmp2, tmp2);
9158 movq(tmp3, in_out2);
9159 addq(tmp3, size);
9160
9161 bind(L_processPartition);
9162 crc32(in_out3, Address(in_out2, 0), 8);
9163 crc32(tmp1, Address(in_out2, size), 8);
9164 crc32(tmp2, Address(in_out2, size * 2), 8);
9165 addq(in_out2, 8);
9166 cmpq(in_out2, tmp3);
9167 jcc(Assembler::less, L_processPartition);
9168 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9169 w_xtmp1, w_xtmp2, w_xtmp3,
9170 tmp4, tmp5,
9171 n_tmp6);
9172 addq(in_out2, 2 * size);
9173 subl(in_out1, 3 * size);
9174 jmp(L_processPartitions);
9175
9176 bind(L_exit);
9177 }
9178
9179 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9180 // Input: A buffer I of L bytes.
9181 // Output: the CRC32C value of the buffer.
9182 // Notations:
9183 // Write L = 24N + r, with N = floor (L/24).
9184 // r = L mod 24 (0 <= r < 24).
9185 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9186 // N quadwords, and R consists of r bytes.
9187 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9188 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9189 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9190 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9191 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9192 Register tmp1, Register tmp2, Register tmp3,
9193 Register tmp4, Register tmp5, Register tmp6,
9194 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9195 bool is_pclmulqdq_supported) {
9196 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9197 Label L_wordByWord;
9198 Label L_byteByByteProlog;
9199 Label L_byteByByte;
9200 Label L_exit;
9201
9202 if (is_pclmulqdq_supported ) {
9203 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9204 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9205
9206 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9207 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9208
9209 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9210 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9211 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9212 } else {
9213 const_or_pre_comp_const_index[0] = 1;
9214 const_or_pre_comp_const_index[1] = 0;
9215
9216 const_or_pre_comp_const_index[2] = 3;
9217 const_or_pre_comp_const_index[3] = 2;
9218
9219 const_or_pre_comp_const_index[4] = 5;
9220 const_or_pre_comp_const_index[5] = 4;
9221 }
9222 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9223 in2, in1, in_out,
9224 tmp1, tmp2, tmp3,
9225 w_xtmp1, w_xtmp2, w_xtmp3,
9226 tmp4, tmp5,
9227 tmp6);
9228 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9229 in2, in1, in_out,
9230 tmp1, tmp2, tmp3,
9231 w_xtmp1, w_xtmp2, w_xtmp3,
9232 tmp4, tmp5,
9233 tmp6);
9234 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9235 in2, in1, in_out,
9236 tmp1, tmp2, tmp3,
9237 w_xtmp1, w_xtmp2, w_xtmp3,
9238 tmp4, tmp5,
9239 tmp6);
9240 movl(tmp1, in2);
9241 andl(tmp1, 0x00000007);
9242 negl(tmp1);
9243 addl(tmp1, in2);
9244 addq(tmp1, in1);
9245
9246 cmpq(in1, tmp1);
9247 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9248 align(16);
9249 BIND(L_wordByWord);
9250 crc32(in_out, Address(in1, 0), 8);
9251 addq(in1, 8);
9252 cmpq(in1, tmp1);
9253 jcc(Assembler::less, L_wordByWord);
9254
9255 BIND(L_byteByByteProlog);
9256 andl(in2, 0x00000007);
9257 movl(tmp2, 1);
9258
9259 cmpl(tmp2, in2);
9260 jccb(Assembler::greater, L_exit);
9261 BIND(L_byteByByte);
9262 crc32(in_out, Address(in1, 0), 1);
9263 incq(in1);
9264 incl(tmp2);
9265 cmpl(tmp2, in2);
9266 jcc(Assembler::lessEqual, L_byteByByte);
9267
9268 BIND(L_exit);
9269 }
9270 #undef BIND
9271 #undef BLOCK_COMMENT
9272
9273 // Compress char[] array to byte[].
9274 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9275 // Return the array length if every element in array can be encoded,
9276 // otherwise, the index of first non-latin1 (> 0xff) character.
9277 // @IntrinsicCandidate
9278 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9279 // for (int i = 0; i < len; i++) {
9280 // char c = src[srcOff];
9281 // if (c > 0xff) {
9282 // return i; // return index of non-latin1 char
9283 // }
9284 // dst[dstOff] = (byte)c;
9285 // srcOff++;
9286 // dstOff++;
9287 // }
9288 // return len;
9289 // }
9290 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9291 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9292 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9293 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9294 Label copy_chars_loop, done, reset_sp, copy_tail;
9295
9296 // rsi: src
9297 // rdi: dst
9298 // rdx: len
9299 // rcx: tmp5
9300 // rax: result
9301
9302 // rsi holds start addr of source char[] to be compressed
9303 // rdi holds start addr of destination byte[]
9304 // rdx holds length
9305
9306 assert(len != result, "");
9307
9308 // save length for return
9309 movl(result, len);
9310
9311 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9312 VM_Version::supports_avx512vlbw() &&
9313 VM_Version::supports_bmi2()) {
9314
9315 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9316
9317 // alignment
9318 Label post_alignment;
9319
9320 // if length of the string is less than 32, handle it the old fashioned way
9321 testl(len, -32);
9322 jcc(Assembler::zero, below_threshold);
9323
9324 // First check whether a character is compressible ( <= 0xFF).
9325 // Create mask to test for Unicode chars inside zmm vector
9326 movl(tmp5, 0x00FF);
9327 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9328
9329 testl(len, -64);
9330 jccb(Assembler::zero, post_alignment);
9331
9332 movl(tmp5, dst);
9333 andl(tmp5, (32 - 1));
9334 negl(tmp5);
9335 andl(tmp5, (32 - 1));
9336
9337 // bail out when there is nothing to be done
9338 testl(tmp5, 0xFFFFFFFF);
9339 jccb(Assembler::zero, post_alignment);
9340
9341 // ~(~0 << len), where len is the # of remaining elements to process
9342 movl(len, 0xFFFFFFFF);
9343 shlxl(len, len, tmp5);
9344 notl(len);
9345 kmovdl(mask2, len);
9346 movl(len, result);
9347
9348 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9349 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9350 ktestd(mask1, mask2);
9351 jcc(Assembler::carryClear, copy_tail);
9352
9353 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9354
9355 addptr(src, tmp5);
9356 addptr(src, tmp5);
9357 addptr(dst, tmp5);
9358 subl(len, tmp5);
9359
9360 bind(post_alignment);
9361 // end of alignment
9362
9363 movl(tmp5, len);
9364 andl(tmp5, (32 - 1)); // tail count (in chars)
9365 andl(len, ~(32 - 1)); // vector count (in chars)
9366 jccb(Assembler::zero, copy_loop_tail);
9367
9368 lea(src, Address(src, len, Address::times_2));
9369 lea(dst, Address(dst, len, Address::times_1));
9370 negptr(len);
9371
9372 bind(copy_32_loop);
9373 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9374 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9375 kortestdl(mask1, mask1);
9376 jccb(Assembler::carryClear, reset_for_copy_tail);
9377
9378 // All elements in current processed chunk are valid candidates for
9379 // compression. Write a truncated byte elements to the memory.
9380 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9381 addptr(len, 32);
9382 jccb(Assembler::notZero, copy_32_loop);
9383
9384 bind(copy_loop_tail);
9385 // bail out when there is nothing to be done
9386 testl(tmp5, 0xFFFFFFFF);
9387 jcc(Assembler::zero, done);
9388
9389 movl(len, tmp5);
9390
9391 // ~(~0 << len), where len is the # of remaining elements to process
9392 movl(tmp5, 0xFFFFFFFF);
9393 shlxl(tmp5, tmp5, len);
9394 notl(tmp5);
9395
9396 kmovdl(mask2, tmp5);
9397
9398 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9399 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9400 ktestd(mask1, mask2);
9401 jcc(Assembler::carryClear, copy_tail);
9402
9403 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9404 jmp(done);
9405
9406 bind(reset_for_copy_tail);
9407 lea(src, Address(src, tmp5, Address::times_2));
9408 lea(dst, Address(dst, tmp5, Address::times_1));
9409 subptr(len, tmp5);
9410 jmp(copy_chars_loop);
9411
9412 bind(below_threshold);
9413 }
9414
9415 if (UseSSE42Intrinsics) {
9416 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9417
9418 // vectored compression
9419 testl(len, 0xfffffff8);
9420 jcc(Assembler::zero, copy_tail);
9421
9422 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9423 movdl(tmp1Reg, tmp5);
9424 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9425
9426 andl(len, 0xfffffff0);
9427 jccb(Assembler::zero, copy_16);
9428
9429 // compress 16 chars per iter
9430 pxor(tmp4Reg, tmp4Reg);
9431
9432 lea(src, Address(src, len, Address::times_2));
9433 lea(dst, Address(dst, len, Address::times_1));
9434 negptr(len);
9435
9436 bind(copy_32_loop);
9437 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9438 por(tmp4Reg, tmp2Reg);
9439 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9440 por(tmp4Reg, tmp3Reg);
9441 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9442 jccb(Assembler::notZero, reset_for_copy_tail);
9443 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9444 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9445 addptr(len, 16);
9446 jccb(Assembler::notZero, copy_32_loop);
9447
9448 // compress next vector of 8 chars (if any)
9449 bind(copy_16);
9450 // len = 0
9451 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9452 jccb(Assembler::zero, copy_tail_sse);
9453
9454 pxor(tmp3Reg, tmp3Reg);
9455
9456 movdqu(tmp2Reg, Address(src, 0));
9457 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9458 jccb(Assembler::notZero, reset_for_copy_tail);
9459 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9460 movq(Address(dst, 0), tmp2Reg);
9461 addptr(src, 16);
9462 addptr(dst, 8);
9463 jmpb(copy_tail_sse);
9464
9465 bind(reset_for_copy_tail);
9466 movl(tmp5, result);
9467 andl(tmp5, 0x0000000f);
9468 lea(src, Address(src, tmp5, Address::times_2));
9469 lea(dst, Address(dst, tmp5, Address::times_1));
9470 subptr(len, tmp5);
9471 jmpb(copy_chars_loop);
9472
9473 bind(copy_tail_sse);
9474 movl(len, result);
9475 andl(len, 0x00000007); // tail count (in chars)
9476 }
9477 // compress 1 char per iter
9478 bind(copy_tail);
9479 testl(len, len);
9480 jccb(Assembler::zero, done);
9481 lea(src, Address(src, len, Address::times_2));
9482 lea(dst, Address(dst, len, Address::times_1));
9483 negptr(len);
9484
9485 bind(copy_chars_loop);
9486 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9487 testl(tmp5, 0xff00); // check if Unicode char
9488 jccb(Assembler::notZero, reset_sp);
9489 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9490 increment(len);
9491 jccb(Assembler::notZero, copy_chars_loop);
9492
9493 // add len then return (len will be zero if compress succeeded, otherwise negative)
9494 bind(reset_sp);
9495 addl(result, len);
9496
9497 bind(done);
9498 }
9499
9500 // Inflate byte[] array to char[].
9501 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9502 // @IntrinsicCandidate
9503 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9504 // for (int i = 0; i < len; i++) {
9505 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9506 // }
9507 // }
9508 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9509 XMMRegister tmp1, Register tmp2, KRegister mask) {
9510 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9511 // rsi: src
9512 // rdi: dst
9513 // rdx: len
9514 // rcx: tmp2
9515
9516 // rsi holds start addr of source byte[] to be inflated
9517 // rdi holds start addr of destination char[]
9518 // rdx holds length
9519 assert_different_registers(src, dst, len, tmp2);
9520 movl(tmp2, len);
9521 if ((UseAVX > 2) && // AVX512
9522 VM_Version::supports_avx512vlbw() &&
9523 VM_Version::supports_bmi2()) {
9524
9525 Label copy_32_loop, copy_tail;
9526 Register tmp3_aliased = len;
9527
9528 // if length of the string is less than 16, handle it in an old fashioned way
9529 testl(len, -16);
9530 jcc(Assembler::zero, below_threshold);
9531
9532 testl(len, -1 * AVX3Threshold);
9533 jcc(Assembler::zero, avx3_threshold);
9534
9535 // In order to use only one arithmetic operation for the main loop we use
9536 // this pre-calculation
9537 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9538 andl(len, -32); // vector count
9539 jccb(Assembler::zero, copy_tail);
9540
9541 lea(src, Address(src, len, Address::times_1));
9542 lea(dst, Address(dst, len, Address::times_2));
9543 negptr(len);
9544
9545
9546 // inflate 32 chars per iter
9547 bind(copy_32_loop);
9548 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9549 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9550 addptr(len, 32);
9551 jcc(Assembler::notZero, copy_32_loop);
9552
9553 bind(copy_tail);
9554 // bail out when there is nothing to be done
9555 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9556 jcc(Assembler::zero, done);
9557
9558 // ~(~0 << length), where length is the # of remaining elements to process
9559 movl(tmp3_aliased, -1);
9560 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9561 notl(tmp3_aliased);
9562 kmovdl(mask, tmp3_aliased);
9563 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9564 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9565
9566 jmp(done);
9567 bind(avx3_threshold);
9568 }
9569 if (UseSSE42Intrinsics) {
9570 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9571
9572 if (UseAVX > 1) {
9573 andl(tmp2, (16 - 1));
9574 andl(len, -16);
9575 jccb(Assembler::zero, copy_new_tail);
9576 } else {
9577 andl(tmp2, 0x00000007); // tail count (in chars)
9578 andl(len, 0xfffffff8); // vector count (in chars)
9579 jccb(Assembler::zero, copy_tail);
9580 }
9581
9582 // vectored inflation
9583 lea(src, Address(src, len, Address::times_1));
9584 lea(dst, Address(dst, len, Address::times_2));
9585 negptr(len);
9586
9587 if (UseAVX > 1) {
9588 bind(copy_16_loop);
9589 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9590 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9591 addptr(len, 16);
9592 jcc(Assembler::notZero, copy_16_loop);
9593
9594 bind(below_threshold);
9595 bind(copy_new_tail);
9596 movl(len, tmp2);
9597 andl(tmp2, 0x00000007);
9598 andl(len, 0xFFFFFFF8);
9599 jccb(Assembler::zero, copy_tail);
9600
9601 pmovzxbw(tmp1, Address(src, 0));
9602 movdqu(Address(dst, 0), tmp1);
9603 addptr(src, 8);
9604 addptr(dst, 2 * 8);
9605
9606 jmp(copy_tail, true);
9607 }
9608
9609 // inflate 8 chars per iter
9610 bind(copy_8_loop);
9611 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9612 movdqu(Address(dst, len, Address::times_2), tmp1);
9613 addptr(len, 8);
9614 jcc(Assembler::notZero, copy_8_loop);
9615
9616 bind(copy_tail);
9617 movl(len, tmp2);
9618
9619 cmpl(len, 4);
9620 jccb(Assembler::less, copy_bytes);
9621
9622 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9623 pmovzxbw(tmp1, tmp1);
9624 movq(Address(dst, 0), tmp1);
9625 subptr(len, 4);
9626 addptr(src, 4);
9627 addptr(dst, 8);
9628
9629 bind(copy_bytes);
9630 } else {
9631 bind(below_threshold);
9632 }
9633
9634 testl(len, len);
9635 jccb(Assembler::zero, done);
9636 lea(src, Address(src, len, Address::times_1));
9637 lea(dst, Address(dst, len, Address::times_2));
9638 negptr(len);
9639
9640 // inflate 1 char per iter
9641 bind(copy_chars_loop);
9642 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9643 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9644 increment(len);
9645 jcc(Assembler::notZero, copy_chars_loop);
9646
9647 bind(done);
9648 }
9649
9650 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9651 switch(type) {
9652 case T_BYTE:
9653 case T_BOOLEAN:
9654 evmovdqub(dst, kmask, src, merge, vector_len);
9655 break;
9656 case T_CHAR:
9657 case T_SHORT:
9658 evmovdquw(dst, kmask, src, merge, vector_len);
9659 break;
9660 case T_INT:
9661 case T_FLOAT:
9662 evmovdqul(dst, kmask, src, merge, vector_len);
9663 break;
9664 case T_LONG:
9665 case T_DOUBLE:
9666 evmovdquq(dst, kmask, src, merge, vector_len);
9667 break;
9668 default:
9669 fatal("Unexpected type argument %s", type2name(type));
9670 break;
9671 }
9672 }
9673
9674
9675 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9676 switch(type) {
9677 case T_BYTE:
9678 case T_BOOLEAN:
9679 evmovdqub(dst, kmask, src, merge, vector_len);
9680 break;
9681 case T_CHAR:
9682 case T_SHORT:
9683 evmovdquw(dst, kmask, src, merge, vector_len);
9684 break;
9685 case T_INT:
9686 case T_FLOAT:
9687 evmovdqul(dst, kmask, src, merge, vector_len);
9688 break;
9689 case T_LONG:
9690 case T_DOUBLE:
9691 evmovdquq(dst, kmask, src, merge, vector_len);
9692 break;
9693 default:
9694 fatal("Unexpected type argument %s", type2name(type));
9695 break;
9696 }
9697 }
9698
9699 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9700 switch(type) {
9701 case T_BYTE:
9702 case T_BOOLEAN:
9703 evmovdqub(dst, kmask, src, merge, vector_len);
9704 break;
9705 case T_CHAR:
9706 case T_SHORT:
9707 evmovdquw(dst, kmask, src, merge, vector_len);
9708 break;
9709 case T_INT:
9710 case T_FLOAT:
9711 evmovdqul(dst, kmask, src, merge, vector_len);
9712 break;
9713 case T_LONG:
9714 case T_DOUBLE:
9715 evmovdquq(dst, kmask, src, merge, vector_len);
9716 break;
9717 default:
9718 fatal("Unexpected type argument %s", type2name(type));
9719 break;
9720 }
9721 }
9722
9723 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9724 switch(masklen) {
9725 case 2:
9726 knotbl(dst, src);
9727 movl(rtmp, 3);
9728 kmovbl(ktmp, rtmp);
9729 kandbl(dst, ktmp, dst);
9730 break;
9731 case 4:
9732 knotbl(dst, src);
9733 movl(rtmp, 15);
9734 kmovbl(ktmp, rtmp);
9735 kandbl(dst, ktmp, dst);
9736 break;
9737 case 8:
9738 knotbl(dst, src);
9739 break;
9740 case 16:
9741 knotwl(dst, src);
9742 break;
9743 case 32:
9744 knotdl(dst, src);
9745 break;
9746 case 64:
9747 knotql(dst, src);
9748 break;
9749 default:
9750 fatal("Unexpected vector length %d", masklen);
9751 break;
9752 }
9753 }
9754
9755 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9756 switch(type) {
9757 case T_BOOLEAN:
9758 case T_BYTE:
9759 kandbl(dst, src1, src2);
9760 break;
9761 case T_CHAR:
9762 case T_SHORT:
9763 kandwl(dst, src1, src2);
9764 break;
9765 case T_INT:
9766 case T_FLOAT:
9767 kanddl(dst, src1, src2);
9768 break;
9769 case T_LONG:
9770 case T_DOUBLE:
9771 kandql(dst, src1, src2);
9772 break;
9773 default:
9774 fatal("Unexpected type argument %s", type2name(type));
9775 break;
9776 }
9777 }
9778
9779 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9780 switch(type) {
9781 case T_BOOLEAN:
9782 case T_BYTE:
9783 korbl(dst, src1, src2);
9784 break;
9785 case T_CHAR:
9786 case T_SHORT:
9787 korwl(dst, src1, src2);
9788 break;
9789 case T_INT:
9790 case T_FLOAT:
9791 kordl(dst, src1, src2);
9792 break;
9793 case T_LONG:
9794 case T_DOUBLE:
9795 korql(dst, src1, src2);
9796 break;
9797 default:
9798 fatal("Unexpected type argument %s", type2name(type));
9799 break;
9800 }
9801 }
9802
9803 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9804 switch(type) {
9805 case T_BOOLEAN:
9806 case T_BYTE:
9807 kxorbl(dst, src1, src2);
9808 break;
9809 case T_CHAR:
9810 case T_SHORT:
9811 kxorwl(dst, src1, src2);
9812 break;
9813 case T_INT:
9814 case T_FLOAT:
9815 kxordl(dst, src1, src2);
9816 break;
9817 case T_LONG:
9818 case T_DOUBLE:
9819 kxorql(dst, src1, src2);
9820 break;
9821 default:
9822 fatal("Unexpected type argument %s", type2name(type));
9823 break;
9824 }
9825 }
9826
9827 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9828 switch(type) {
9829 case T_BOOLEAN:
9830 case T_BYTE:
9831 evpermb(dst, mask, nds, src, merge, vector_len); break;
9832 case T_CHAR:
9833 case T_SHORT:
9834 evpermw(dst, mask, nds, src, merge, vector_len); break;
9835 case T_INT:
9836 case T_FLOAT:
9837 evpermd(dst, mask, nds, src, merge, vector_len); break;
9838 case T_LONG:
9839 case T_DOUBLE:
9840 evpermq(dst, mask, nds, src, merge, vector_len); break;
9841 default:
9842 fatal("Unexpected type argument %s", type2name(type)); break;
9843 }
9844 }
9845
9846 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9847 switch(type) {
9848 case T_BOOLEAN:
9849 case T_BYTE:
9850 evpermb(dst, mask, nds, src, merge, vector_len); break;
9851 case T_CHAR:
9852 case T_SHORT:
9853 evpermw(dst, mask, nds, src, merge, vector_len); break;
9854 case T_INT:
9855 case T_FLOAT:
9856 evpermd(dst, mask, nds, src, merge, vector_len); break;
9857 case T_LONG:
9858 case T_DOUBLE:
9859 evpermq(dst, mask, nds, src, merge, vector_len); break;
9860 default:
9861 fatal("Unexpected type argument %s", type2name(type)); break;
9862 }
9863 }
9864
9865 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9866 switch(type) {
9867 case T_BYTE:
9868 evpminub(dst, mask, nds, src, merge, vector_len); break;
9869 case T_SHORT:
9870 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9871 case T_INT:
9872 evpminud(dst, mask, nds, src, merge, vector_len); break;
9873 case T_LONG:
9874 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9875 default:
9876 fatal("Unexpected type argument %s", type2name(type)); break;
9877 }
9878 }
9879
9880 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9881 switch(type) {
9882 case T_BYTE:
9883 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9884 case T_SHORT:
9885 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9886 case T_INT:
9887 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9888 case T_LONG:
9889 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9890 default:
9891 fatal("Unexpected type argument %s", type2name(type)); break;
9892 }
9893 }
9894
9895 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9896 switch(type) {
9897 case T_BYTE:
9898 evpminub(dst, mask, nds, src, merge, vector_len); break;
9899 case T_SHORT:
9900 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9901 case T_INT:
9902 evpminud(dst, mask, nds, src, merge, vector_len); break;
9903 case T_LONG:
9904 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9905 default:
9906 fatal("Unexpected type argument %s", type2name(type)); break;
9907 }
9908 }
9909
9910 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9911 switch(type) {
9912 case T_BYTE:
9913 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9914 case T_SHORT:
9915 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9916 case T_INT:
9917 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9918 case T_LONG:
9919 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9920 default:
9921 fatal("Unexpected type argument %s", type2name(type)); break;
9922 }
9923 }
9924
9925 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9926 switch(type) {
9927 case T_BYTE:
9928 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9929 case T_SHORT:
9930 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9931 case T_INT:
9932 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9933 case T_LONG:
9934 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9935 case T_FLOAT:
9936 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9937 case T_DOUBLE:
9938 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9939 default:
9940 fatal("Unexpected type argument %s", type2name(type)); break;
9941 }
9942 }
9943
9944 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9945 switch(type) {
9946 case T_BYTE:
9947 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9948 case T_SHORT:
9949 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9950 case T_INT:
9951 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9952 case T_LONG:
9953 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9954 case T_FLOAT:
9955 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9956 case T_DOUBLE:
9957 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9958 default:
9959 fatal("Unexpected type argument %s", type2name(type)); break;
9960 }
9961 }
9962
9963 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9964 switch(type) {
9965 case T_BYTE:
9966 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9967 case T_SHORT:
9968 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9969 case T_INT:
9970 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9971 case T_LONG:
9972 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9973 case T_FLOAT:
9974 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9975 case T_DOUBLE:
9976 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9977 default:
9978 fatal("Unexpected type argument %s", type2name(type)); break;
9979 }
9980 }
9981
9982 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9983 switch(type) {
9984 case T_BYTE:
9985 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9986 case T_SHORT:
9987 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9988 case T_INT:
9989 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9990 case T_LONG:
9991 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9992 case T_FLOAT:
9993 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9994 case T_DOUBLE:
9995 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9996 default:
9997 fatal("Unexpected type argument %s", type2name(type)); break;
9998 }
9999 }
10000
10001 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10002 switch(type) {
10003 case T_INT:
10004 evpxord(dst, mask, nds, src, merge, vector_len); break;
10005 case T_LONG:
10006 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10007 default:
10008 fatal("Unexpected type argument %s", type2name(type)); break;
10009 }
10010 }
10011
10012 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10013 switch(type) {
10014 case T_INT:
10015 evpxord(dst, mask, nds, src, merge, vector_len); break;
10016 case T_LONG:
10017 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10018 default:
10019 fatal("Unexpected type argument %s", type2name(type)); break;
10020 }
10021 }
10022
10023 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10024 switch(type) {
10025 case T_INT:
10026 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10027 case T_LONG:
10028 evporq(dst, mask, nds, src, merge, vector_len); break;
10029 default:
10030 fatal("Unexpected type argument %s", type2name(type)); break;
10031 }
10032 }
10033
10034 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10035 switch(type) {
10036 case T_INT:
10037 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10038 case T_LONG:
10039 evporq(dst, mask, nds, src, merge, vector_len); break;
10040 default:
10041 fatal("Unexpected type argument %s", type2name(type)); break;
10042 }
10043 }
10044
10045 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10046 switch(type) {
10047 case T_INT:
10048 evpandd(dst, mask, nds, src, merge, vector_len); break;
10049 case T_LONG:
10050 evpandq(dst, mask, nds, src, merge, vector_len); break;
10051 default:
10052 fatal("Unexpected type argument %s", type2name(type)); break;
10053 }
10054 }
10055
10056 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10057 switch(type) {
10058 case T_INT:
10059 evpandd(dst, mask, nds, src, merge, vector_len); break;
10060 case T_LONG:
10061 evpandq(dst, mask, nds, src, merge, vector_len); break;
10062 default:
10063 fatal("Unexpected type argument %s", type2name(type)); break;
10064 }
10065 }
10066
10067 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
10068 switch(masklen) {
10069 case 8:
10070 kortestbl(src1, src2);
10071 break;
10072 case 16:
10073 kortestwl(src1, src2);
10074 break;
10075 case 32:
10076 kortestdl(src1, src2);
10077 break;
10078 case 64:
10079 kortestql(src1, src2);
10080 break;
10081 default:
10082 fatal("Unexpected mask length %d", masklen);
10083 break;
10084 }
10085 }
10086
10087
10088 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
10089 switch(masklen) {
10090 case 8:
10091 ktestbl(src1, src2);
10092 break;
10093 case 16:
10094 ktestwl(src1, src2);
10095 break;
10096 case 32:
10097 ktestdl(src1, src2);
10098 break;
10099 case 64:
10100 ktestql(src1, src2);
10101 break;
10102 default:
10103 fatal("Unexpected mask length %d", masklen);
10104 break;
10105 }
10106 }
10107
10108 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10109 switch(type) {
10110 case T_INT:
10111 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10112 case T_LONG:
10113 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10114 default:
10115 fatal("Unexpected type argument %s", type2name(type)); break;
10116 break;
10117 }
10118 }
10119
10120 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10121 switch(type) {
10122 case T_INT:
10123 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10124 case T_LONG:
10125 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10126 default:
10127 fatal("Unexpected type argument %s", type2name(type)); break;
10128 }
10129 }
10130
10131 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10132 switch(type) {
10133 case T_INT:
10134 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10135 case T_LONG:
10136 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10137 default:
10138 fatal("Unexpected type argument %s", type2name(type)); break;
10139 }
10140 }
10141
10142 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10143 switch(type) {
10144 case T_INT:
10145 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10146 case T_LONG:
10147 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10148 default:
10149 fatal("Unexpected type argument %s", type2name(type)); break;
10150 }
10151 }
10152
10153 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10154 assert(rscratch != noreg || always_reachable(src), "missing");
10155
10156 if (reachable(src)) {
10157 evpandq(dst, nds, as_Address(src), vector_len);
10158 } else {
10159 lea(rscratch, src);
10160 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10161 }
10162 }
10163
10164 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10165 assert(rscratch != noreg || always_reachable(src), "missing");
10166
10167 if (reachable(src)) {
10168 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10169 } else {
10170 lea(rscratch, src);
10171 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10172 }
10173 }
10174
10175 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10176 assert(rscratch != noreg || always_reachable(src), "missing");
10177
10178 if (reachable(src)) {
10179 evporq(dst, nds, as_Address(src), vector_len);
10180 } else {
10181 lea(rscratch, src);
10182 evporq(dst, nds, Address(rscratch, 0), vector_len);
10183 }
10184 }
10185
10186 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10187 assert(rscratch != noreg || always_reachable(src), "missing");
10188
10189 if (reachable(src)) {
10190 vpshufb(dst, nds, as_Address(src), vector_len);
10191 } else {
10192 lea(rscratch, src);
10193 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10194 }
10195 }
10196
10197 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10198 assert(rscratch != noreg || always_reachable(src), "missing");
10199
10200 if (reachable(src)) {
10201 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10202 } else {
10203 lea(rscratch, src);
10204 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10205 }
10206 }
10207
10208 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10209 assert(rscratch != noreg || always_reachable(src3), "missing");
10210
10211 if (reachable(src3)) {
10212 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10213 } else {
10214 lea(rscratch, src3);
10215 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10216 }
10217 }
10218
10219 #if COMPILER2_OR_JVMCI
10220
10221 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10222 Register length, Register temp, int vec_enc) {
10223 // Computing mask for predicated vector store.
10224 movptr(temp, -1);
10225 bzhiq(temp, temp, length);
10226 kmov(mask, temp);
10227 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10228 }
10229
10230 // Set memory operation for length "less than" 64 bytes.
10231 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10232 XMMRegister xmm, KRegister mask, Register length,
10233 Register temp, bool use64byteVector) {
10234 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10235 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10236 if (!use64byteVector) {
10237 fill32(dst, disp, xmm);
10238 subptr(length, 32 >> shift);
10239 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10240 } else {
10241 assert(MaxVectorSize == 64, "vector length != 64");
10242 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10243 }
10244 }
10245
10246
10247 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10248 XMMRegister xmm, KRegister mask, Register length,
10249 Register temp) {
10250 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10251 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10252 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10253 }
10254
10255
10256 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10257 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10258 vmovdqu(dst, xmm);
10259 }
10260
10261 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10262 fill32(Address(dst, disp), xmm);
10263 }
10264
10265 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10266 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10267 if (!use64byteVector) {
10268 fill32(dst, xmm);
10269 fill32(dst.plus_disp(32), xmm);
10270 } else {
10271 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10272 }
10273 }
10274
10275 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10276 fill64(Address(dst, disp), xmm, use64byteVector);
10277 }
10278
10279 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10280 Register count, Register rtmp, XMMRegister xtmp) {
10281 Label L_exit;
10282 Label L_fill_start;
10283 Label L_fill_64_bytes;
10284 Label L_fill_96_bytes;
10285 Label L_fill_128_bytes;
10286 Label L_fill_128_bytes_loop;
10287 Label L_fill_128_loop_header;
10288 Label L_fill_128_bytes_loop_header;
10289 Label L_fill_128_bytes_loop_pre_header;
10290 Label L_fill_zmm_sequence;
10291
10292 int shift = -1;
10293 switch(type) {
10294 case T_BYTE: shift = 0;
10295 break;
10296 case T_SHORT: shift = 1;
10297 break;
10298 case T_INT: shift = 2;
10299 break;
10300 /* Uncomment when LONG fill stubs are supported.
10301 case T_LONG: shift = 3;
10302 break;
10303 */
10304 default:
10305 fatal("Unhandled type: %s\n", type2name(type));
10306 }
10307
10308 if ((CopyAVX3Threshold != 0) || (MaxVectorSize == 32)) {
10309
10310 if (MaxVectorSize == 64) {
10311 cmpq(count, CopyAVX3Threshold >> shift);
10312 jcc(Assembler::greater, L_fill_zmm_sequence);
10313 }
10314
10315 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10316
10317 bind(L_fill_start);
10318
10319 cmpq(count, 32 >> shift);
10320 jccb(Assembler::greater, L_fill_64_bytes);
10321 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10322 jmp(L_exit);
10323
10324 bind(L_fill_64_bytes);
10325 cmpq(count, 64 >> shift);
10326 jccb(Assembler::greater, L_fill_96_bytes);
10327 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10328 jmp(L_exit);
10329
10330 bind(L_fill_96_bytes);
10331 cmpq(count, 96 >> shift);
10332 jccb(Assembler::greater, L_fill_128_bytes);
10333 fill64(to, 0, xtmp);
10334 subq(count, 64 >> shift);
10335 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10336 jmp(L_exit);
10337
10338 bind(L_fill_128_bytes);
10339 cmpq(count, 128 >> shift);
10340 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10341 fill64(to, 0, xtmp);
10342 fill32(to, 64, xtmp);
10343 subq(count, 96 >> shift);
10344 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10345 jmp(L_exit);
10346
10347 bind(L_fill_128_bytes_loop_pre_header);
10348 {
10349 mov(rtmp, to);
10350 andq(rtmp, 31);
10351 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10352 negq(rtmp);
10353 addq(rtmp, 32);
10354 mov64(r8, -1L);
10355 bzhiq(r8, r8, rtmp);
10356 kmovql(k2, r8);
10357 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10358 addq(to, rtmp);
10359 shrq(rtmp, shift);
10360 subq(count, rtmp);
10361 }
10362
10363 cmpq(count, 128 >> shift);
10364 jcc(Assembler::less, L_fill_start);
10365
10366 bind(L_fill_128_bytes_loop_header);
10367 subq(count, 128 >> shift);
10368
10369 align32();
10370 bind(L_fill_128_bytes_loop);
10371 fill64(to, 0, xtmp);
10372 fill64(to, 64, xtmp);
10373 addq(to, 128);
10374 subq(count, 128 >> shift);
10375 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10376
10377 addq(count, 128 >> shift);
10378 jcc(Assembler::zero, L_exit);
10379 jmp(L_fill_start);
10380 }
10381
10382 if (MaxVectorSize == 64) {
10383 // Sequence using 64 byte ZMM register.
10384 Label L_fill_128_bytes_zmm;
10385 Label L_fill_192_bytes_zmm;
10386 Label L_fill_192_bytes_loop_zmm;
10387 Label L_fill_192_bytes_loop_header_zmm;
10388 Label L_fill_192_bytes_loop_pre_header_zmm;
10389 Label L_fill_start_zmm_sequence;
10390
10391 bind(L_fill_zmm_sequence);
10392 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10393
10394 bind(L_fill_start_zmm_sequence);
10395 cmpq(count, 64 >> shift);
10396 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10397 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10398 jmp(L_exit);
10399
10400 bind(L_fill_128_bytes_zmm);
10401 cmpq(count, 128 >> shift);
10402 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10403 fill64(to, 0, xtmp, true);
10404 subq(count, 64 >> shift);
10405 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10406 jmp(L_exit);
10407
10408 bind(L_fill_192_bytes_zmm);
10409 cmpq(count, 192 >> shift);
10410 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10411 fill64(to, 0, xtmp, true);
10412 fill64(to, 64, xtmp, true);
10413 subq(count, 128 >> shift);
10414 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10415 jmp(L_exit);
10416
10417 bind(L_fill_192_bytes_loop_pre_header_zmm);
10418 {
10419 movq(rtmp, to);
10420 andq(rtmp, 63);
10421 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10422 negq(rtmp);
10423 addq(rtmp, 64);
10424 mov64(r8, -1L);
10425 bzhiq(r8, r8, rtmp);
10426 kmovql(k2, r8);
10427 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10428 addq(to, rtmp);
10429 shrq(rtmp, shift);
10430 subq(count, rtmp);
10431 }
10432
10433 cmpq(count, 192 >> shift);
10434 jcc(Assembler::less, L_fill_start_zmm_sequence);
10435
10436 bind(L_fill_192_bytes_loop_header_zmm);
10437 subq(count, 192 >> shift);
10438
10439 align32();
10440 bind(L_fill_192_bytes_loop_zmm);
10441 fill64(to, 0, xtmp, true);
10442 fill64(to, 64, xtmp, true);
10443 fill64(to, 128, xtmp, true);
10444 addq(to, 192);
10445 subq(count, 192 >> shift);
10446 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10447
10448 addq(count, 192 >> shift);
10449 jcc(Assembler::zero, L_exit);
10450 jmp(L_fill_start_zmm_sequence);
10451 }
10452 bind(L_exit);
10453 }
10454 #endif //COMPILER2_OR_JVMCI
10455
10456
10457 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10458 Label done;
10459 cvttss2sil(dst, src);
10460 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10461 cmpl(dst, 0x80000000); // float_sign_flip
10462 jccb(Assembler::notEqual, done);
10463 subptr(rsp, 8);
10464 movflt(Address(rsp, 0), src);
10465 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10466 pop(dst);
10467 bind(done);
10468 }
10469
10470 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10471 Label done;
10472 cvttsd2sil(dst, src);
10473 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10474 cmpl(dst, 0x80000000); // float_sign_flip
10475 jccb(Assembler::notEqual, done);
10476 subptr(rsp, 8);
10477 movdbl(Address(rsp, 0), src);
10478 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10479 pop(dst);
10480 bind(done);
10481 }
10482
10483 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10484 Label done;
10485 cvttss2siq(dst, src);
10486 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10487 jccb(Assembler::notEqual, done);
10488 subptr(rsp, 8);
10489 movflt(Address(rsp, 0), src);
10490 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10491 pop(dst);
10492 bind(done);
10493 }
10494
10495 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10496 // Following code is line by line assembly translation rounding algorithm.
10497 // Please refer to java.lang.Math.round(float) algorithm for details.
10498 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10499 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10500 const int32_t FloatConsts_EXP_BIAS = 127;
10501 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10502 const int32_t MINUS_32 = 0xFFFFFFE0;
10503 Label L_special_case, L_block1, L_exit;
10504 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10505 movdl(dst, src);
10506 andl(dst, rtmp);
10507 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10508 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10509 subl(rtmp, dst);
10510 movl(rcx, rtmp);
10511 movl(dst, MINUS_32);
10512 testl(rtmp, dst);
10513 jccb(Assembler::notEqual, L_special_case);
10514 movdl(dst, src);
10515 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10516 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10517 movdl(rtmp, src);
10518 testl(rtmp, rtmp);
10519 jccb(Assembler::greaterEqual, L_block1);
10520 negl(dst);
10521 bind(L_block1);
10522 sarl(dst);
10523 addl(dst, 0x1);
10524 sarl(dst, 0x1);
10525 jmp(L_exit);
10526 bind(L_special_case);
10527 convert_f2i(dst, src);
10528 bind(L_exit);
10529 }
10530
10531 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10532 // Following code is line by line assembly translation rounding algorithm.
10533 // Please refer to java.lang.Math.round(double) algorithm for details.
10534 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10535 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10536 const int64_t DoubleConsts_EXP_BIAS = 1023;
10537 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10538 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10539 Label L_special_case, L_block1, L_exit;
10540 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10541 movq(dst, src);
10542 andq(dst, rtmp);
10543 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10544 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10545 subq(rtmp, dst);
10546 movq(rcx, rtmp);
10547 mov64(dst, MINUS_64);
10548 testq(rtmp, dst);
10549 jccb(Assembler::notEqual, L_special_case);
10550 movq(dst, src);
10551 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10552 andq(dst, rtmp);
10553 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10554 orq(dst, rtmp);
10555 movq(rtmp, src);
10556 testq(rtmp, rtmp);
10557 jccb(Assembler::greaterEqual, L_block1);
10558 negq(dst);
10559 bind(L_block1);
10560 sarq(dst);
10561 addq(dst, 0x1);
10562 sarq(dst, 0x1);
10563 jmp(L_exit);
10564 bind(L_special_case);
10565 convert_d2l(dst, src);
10566 bind(L_exit);
10567 }
10568
10569 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10570 Label done;
10571 cvttsd2siq(dst, src);
10572 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10573 jccb(Assembler::notEqual, done);
10574 subptr(rsp, 8);
10575 movdbl(Address(rsp, 0), src);
10576 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10577 pop(dst);
10578 bind(done);
10579 }
10580
10581 void MacroAssembler::cache_wb(Address line)
10582 {
10583 // 64 bit cpus always support clflush
10584 assert(VM_Version::supports_clflush(), "clflush should be available");
10585 bool optimized = VM_Version::supports_clflushopt();
10586 bool no_evict = VM_Version::supports_clwb();
10587
10588 // prefer clwb (writeback without evict) otherwise
10589 // prefer clflushopt (potentially parallel writeback with evict)
10590 // otherwise fallback on clflush (serial writeback with evict)
10591
10592 if (optimized) {
10593 if (no_evict) {
10594 clwb(line);
10595 } else {
10596 clflushopt(line);
10597 }
10598 } else {
10599 // no need for fence when using CLFLUSH
10600 clflush(line);
10601 }
10602 }
10603
10604 void MacroAssembler::cache_wbsync(bool is_pre)
10605 {
10606 assert(VM_Version::supports_clflush(), "clflush should be available");
10607 bool optimized = VM_Version::supports_clflushopt();
10608 bool no_evict = VM_Version::supports_clwb();
10609
10610 // pick the correct implementation
10611
10612 if (!is_pre && (optimized || no_evict)) {
10613 // need an sfence for post flush when using clflushopt or clwb
10614 // otherwise no no need for any synchroniaztion
10615
10616 sfence();
10617 }
10618 }
10619
10620 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10621 switch (cond) {
10622 // Note some conditions are synonyms for others
10623 case Assembler::zero: return Assembler::notZero;
10624 case Assembler::notZero: return Assembler::zero;
10625 case Assembler::less: return Assembler::greaterEqual;
10626 case Assembler::lessEqual: return Assembler::greater;
10627 case Assembler::greater: return Assembler::lessEqual;
10628 case Assembler::greaterEqual: return Assembler::less;
10629 case Assembler::below: return Assembler::aboveEqual;
10630 case Assembler::belowEqual: return Assembler::above;
10631 case Assembler::above: return Assembler::belowEqual;
10632 case Assembler::aboveEqual: return Assembler::below;
10633 case Assembler::overflow: return Assembler::noOverflow;
10634 case Assembler::noOverflow: return Assembler::overflow;
10635 case Assembler::negative: return Assembler::positive;
10636 case Assembler::positive: return Assembler::negative;
10637 case Assembler::parity: return Assembler::noParity;
10638 case Assembler::noParity: return Assembler::parity;
10639 }
10640 ShouldNotReachHere(); return Assembler::overflow;
10641 }
10642
10643 // This is simply a call to Thread::current()
10644 void MacroAssembler::get_thread_slow(Register thread) {
10645 if (thread != rax) {
10646 push(rax);
10647 }
10648 push(rdi);
10649 push(rsi);
10650 push(rdx);
10651 push(rcx);
10652 push(r8);
10653 push(r9);
10654 push(r10);
10655 push(r11);
10656
10657 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10658
10659 pop(r11);
10660 pop(r10);
10661 pop(r9);
10662 pop(r8);
10663 pop(rcx);
10664 pop(rdx);
10665 pop(rsi);
10666 pop(rdi);
10667 if (thread != rax) {
10668 mov(thread, rax);
10669 pop(rax);
10670 }
10671 }
10672
10673 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10674 Label L_stack_ok;
10675 if (bias == 0) {
10676 testptr(sp, 2 * wordSize - 1);
10677 } else {
10678 // lea(tmp, Address(rsp, bias);
10679 mov(tmp, sp);
10680 addptr(tmp, bias);
10681 testptr(tmp, 2 * wordSize - 1);
10682 }
10683 jcc(Assembler::equal, L_stack_ok);
10684 block_comment(msg);
10685 stop(msg);
10686 bind(L_stack_ok);
10687 }
10688
10689 // Implements fast-locking.
10690 //
10691 // obj: the object to be locked
10692 // reg_rax: rax
10693 // thread: the thread which attempts to lock obj
10694 // tmp: a temporary register
10695 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow) {
10696 Register thread = r15_thread;
10697
10698 assert(reg_rax == rax, "");
10699 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10700
10701 Label push;
10702 const Register top = tmp;
10703
10704 // Preload the markWord. It is important that this is the first
10705 // instruction emitted as it is part of C1's null check semantics.
10706 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10707
10708 if (UseObjectMonitorTable) {
10709 // Clear cache in case fast locking succeeds or we need to take the slow-path.
10710 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10711 }
10712
10713 if (DiagnoseSyncOnValueBasedClasses != 0) {
10714 load_klass(tmp, obj, rscratch1);
10715 testb(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
10716 jcc(Assembler::notZero, slow);
10717 }
10718
10719 // Load top.
10720 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10721
10722 // Check if the lock-stack is full.
10723 cmpl(top, LockStack::end_offset());
10724 jcc(Assembler::greaterEqual, slow);
10725
10726 // Check for recursion.
10727 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10728 jcc(Assembler::equal, push);
10729
10730 // Check header for monitor (0b10).
10731 testptr(reg_rax, markWord::monitor_value);
10732 jcc(Assembler::notZero, slow);
10733
10734 // Try to lock. Transition lock bits 0b01 => 0b00
10735 movptr(tmp, reg_rax);
10736 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10737 orptr(reg_rax, markWord::unlocked_value);
10738 // Mask inline_type bit such that we go to the slow path if object is an inline type
10739 andptr(reg_rax, ~((int) markWord::inline_type_bit_in_place));
10740
10741 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10742 jcc(Assembler::notEqual, slow);
10743
10744 // Restore top, CAS clobbers register.
10745 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10746
10747 bind(push);
10748 // After successful lock, push object on lock-stack.
10749 movptr(Address(thread, top), obj);
10750 incrementl(top, oopSize);
10751 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10752 }
10753
10754 // Implements fast-unlocking.
10755 //
10756 // obj: the object to be unlocked
10757 // reg_rax: rax
10758 // thread: the thread
10759 // tmp: a temporary register
10760 void MacroAssembler::fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow) {
10761 Register thread = r15_thread;
10762
10763 assert(reg_rax == rax, "");
10764 assert_different_registers(obj, reg_rax, thread, tmp);
10765
10766 Label unlocked, push_and_slow;
10767 const Register top = tmp;
10768
10769 // Check if obj is top of lock-stack.
10770 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10771 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10772 jcc(Assembler::notEqual, slow);
10773
10774 // Pop lock-stack.
10775 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10776 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10777
10778 // Check if recursive.
10779 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10780 jcc(Assembler::equal, unlocked);
10781
10782 // Not recursive. Check header for monitor (0b10).
10783 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10784 testptr(reg_rax, markWord::monitor_value);
10785 jcc(Assembler::notZero, push_and_slow);
10786
10787 #ifdef ASSERT
10788 // Check header not unlocked (0b01).
10789 Label not_unlocked;
10790 testptr(reg_rax, markWord::unlocked_value);
10791 jcc(Assembler::zero, not_unlocked);
10792 stop("fast_unlock already unlocked");
10793 bind(not_unlocked);
10794 #endif
10795
10796 // Try to unlock. Transition lock bits 0b00 => 0b01
10797 movptr(tmp, reg_rax);
10798 orptr(tmp, markWord::unlocked_value);
10799 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10800 jcc(Assembler::equal, unlocked);
10801
10802 bind(push_and_slow);
10803 // Restore lock-stack and handle the unlock in runtime.
10804 #ifdef ASSERT
10805 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10806 movptr(Address(thread, top), obj);
10807 #endif
10808 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10809 jmp(slow);
10810
10811 bind(unlocked);
10812 }
10813
10814 // Saves legacy GPRs state on stack.
10815 void MacroAssembler::save_legacy_gprs() {
10816 subq(rsp, 16 * wordSize);
10817 movq(Address(rsp, 15 * wordSize), rax);
10818 movq(Address(rsp, 14 * wordSize), rcx);
10819 movq(Address(rsp, 13 * wordSize), rdx);
10820 movq(Address(rsp, 12 * wordSize), rbx);
10821 movq(Address(rsp, 10 * wordSize), rbp);
10822 movq(Address(rsp, 9 * wordSize), rsi);
10823 movq(Address(rsp, 8 * wordSize), rdi);
10824 movq(Address(rsp, 7 * wordSize), r8);
10825 movq(Address(rsp, 6 * wordSize), r9);
10826 movq(Address(rsp, 5 * wordSize), r10);
10827 movq(Address(rsp, 4 * wordSize), r11);
10828 movq(Address(rsp, 3 * wordSize), r12);
10829 movq(Address(rsp, 2 * wordSize), r13);
10830 movq(Address(rsp, wordSize), r14);
10831 movq(Address(rsp, 0), r15);
10832 }
10833
10834 // Resotres back legacy GPRs state from stack.
10835 void MacroAssembler::restore_legacy_gprs() {
10836 movq(r15, Address(rsp, 0));
10837 movq(r14, Address(rsp, wordSize));
10838 movq(r13, Address(rsp, 2 * wordSize));
10839 movq(r12, Address(rsp, 3 * wordSize));
10840 movq(r11, Address(rsp, 4 * wordSize));
10841 movq(r10, Address(rsp, 5 * wordSize));
10842 movq(r9, Address(rsp, 6 * wordSize));
10843 movq(r8, Address(rsp, 7 * wordSize));
10844 movq(rdi, Address(rsp, 8 * wordSize));
10845 movq(rsi, Address(rsp, 9 * wordSize));
10846 movq(rbp, Address(rsp, 10 * wordSize));
10847 movq(rbx, Address(rsp, 12 * wordSize));
10848 movq(rdx, Address(rsp, 13 * wordSize));
10849 movq(rcx, Address(rsp, 14 * wordSize));
10850 movq(rax, Address(rsp, 15 * wordSize));
10851 addq(rsp, 16 * wordSize);
10852 }
10853
10854 void MacroAssembler::load_aotrc_address(Register reg, address a) {
10855 #if INCLUDE_CDS
10856 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
10857 if (AOTCodeCache::is_on_for_dump()) {
10858 // all aotrc field addresses should be registered in the AOTCodeCache address table
10859 lea(reg, ExternalAddress(a));
10860 } else {
10861 mov64(reg, (uint64_t)a);
10862 }
10863 #else
10864 ShouldNotReachHere();
10865 #endif
10866 }
10867
10868 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10869 if (VM_Version::supports_apx_f()) {
10870 esetzucc(comparison, dst);
10871 } else {
10872 setb(comparison, dst);
10873 movzbl(dst, dst);
10874 }
10875 }