1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/aotCodeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "ci/ciInlineKlass.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "interpreter/interpreterRuntime.hpp"
40 #include "jvm.h"
41 #include "memory/resourceArea.hpp"
42 #include "memory/universe.hpp"
43 #include "oops/accessDecorators.hpp"
44 #include "oops/compressedKlass.inline.hpp"
45 #include "oops/compressedOops.inline.hpp"
46 #include "oops/klass.inline.hpp"
47 #include "oops/resolvedFieldEntry.hpp"
48 #include "prims/methodHandles.hpp"
49 #include "runtime/arguments.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/interfaceSupport.inline.hpp"
52 #include "runtime/javaThread.hpp"
53 #include "runtime/jniHandles.hpp"
54 #include "runtime/objectMonitor.hpp"
55 #include "runtime/os.hpp"
56 #include "runtime/safepoint.hpp"
57 #include "runtime/safepointMechanism.hpp"
58 #include "runtime/sharedRuntime.hpp"
59 #include "runtime/signature_cc.hpp"
60 #include "runtime/stubRoutines.hpp"
61 #include "utilities/checkedCast.hpp"
62 #include "utilities/macros.hpp"
63 #include "vmreg_x86.inline.hpp"
64 #ifdef COMPILER2
65 #include "opto/output.hpp"
66 #endif
67
68 #ifdef PRODUCT
69 #define BLOCK_COMMENT(str) /* nothing */
70 #define STOP(error) stop(error)
71 #else
72 #define BLOCK_COMMENT(str) block_comment(str)
73 #define STOP(error) block_comment(error); stop(error)
74 #endif
75
76 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
77
78 #ifdef ASSERT
79 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
80 #endif
81
82 static const Assembler::Condition reverse[] = {
83 Assembler::noOverflow /* overflow = 0x0 */ ,
84 Assembler::overflow /* noOverflow = 0x1 */ ,
85 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
86 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
87 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
88 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
89 Assembler::above /* belowEqual = 0x6 */ ,
90 Assembler::belowEqual /* above = 0x7 */ ,
91 Assembler::positive /* negative = 0x8 */ ,
92 Assembler::negative /* positive = 0x9 */ ,
93 Assembler::noParity /* parity = 0xa */ ,
94 Assembler::parity /* noParity = 0xb */ ,
95 Assembler::greaterEqual /* less = 0xc */ ,
96 Assembler::less /* greaterEqual = 0xd */ ,
97 Assembler::greater /* lessEqual = 0xe */ ,
98 Assembler::lessEqual /* greater = 0xf, */
99
100 };
101
102
103 // Implementation of MacroAssembler
104
105 Address MacroAssembler::as_Address(AddressLiteral adr) {
106 // amd64 always does this as a pc-rel
107 // we can be absolute or disp based on the instruction type
108 // jmp/call are displacements others are absolute
109 assert(!adr.is_lval(), "must be rval");
110 assert(reachable(adr), "must be");
111 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
112
113 }
114
115 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
116 AddressLiteral base = adr.base();
117 lea(rscratch, base);
118 Address index = adr.index();
119 assert(index._disp == 0, "must not have disp"); // maybe it can?
120 Address array(rscratch, index._index, index._scale, index._disp);
121 return array;
122 }
123
124 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
125 Label L, E;
126
127 #ifdef _WIN64
128 // Windows always allocates space for it's register args
129 assert(num_args <= 4, "only register arguments supported");
130 subq(rsp, frame::arg_reg_save_area_bytes);
131 #endif
132
133 // Align stack if necessary
134 testl(rsp, 15);
135 jcc(Assembler::zero, L);
136
137 subq(rsp, 8);
138 call(RuntimeAddress(entry_point));
139 addq(rsp, 8);
140 jmp(E);
141
142 bind(L);
143 call(RuntimeAddress(entry_point));
144
145 bind(E);
146
147 #ifdef _WIN64
148 // restore stack pointer
149 addq(rsp, frame::arg_reg_save_area_bytes);
150 #endif
151 }
152
153 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
154 assert(!src2.is_lval(), "should use cmpptr");
155 assert(rscratch != noreg || always_reachable(src2), "missing");
156
157 if (reachable(src2)) {
158 cmpq(src1, as_Address(src2));
159 } else {
160 lea(rscratch, src2);
161 Assembler::cmpq(src1, Address(rscratch, 0));
162 }
163 }
164
165 int MacroAssembler::corrected_idivq(Register reg) {
166 // Full implementation of Java ldiv and lrem; checks for special
167 // case as described in JVM spec., p.243 & p.271. The function
168 // returns the (pc) offset of the idivl instruction - may be needed
169 // for implicit exceptions.
170 //
171 // normal case special case
172 //
173 // input : rax: dividend min_long
174 // reg: divisor (may not be eax/edx) -1
175 //
176 // output: rax: quotient (= rax idiv reg) min_long
177 // rdx: remainder (= rax irem reg) 0
178 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
179 static const int64_t min_long = 0x8000000000000000;
180 Label normal_case, special_case;
181
182 // check for special case
183 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
184 jcc(Assembler::notEqual, normal_case);
185 xorl(rdx, rdx); // prepare rdx for possible special case (where
186 // remainder = 0)
187 cmpq(reg, -1);
188 jcc(Assembler::equal, special_case);
189
190 // handle normal case
191 bind(normal_case);
192 cdqq();
193 int idivq_offset = offset();
194 idivq(reg);
195
196 // normal and special case exit
197 bind(special_case);
198
199 return idivq_offset;
200 }
201
202 void MacroAssembler::decrementq(Register reg, int value) {
203 if (value == min_jint) { subq(reg, value); return; }
204 if (value < 0) { incrementq(reg, -value); return; }
205 if (value == 0) { ; return; }
206 if (value == 1 && UseIncDec) { decq(reg) ; return; }
207 /* else */ { subq(reg, value) ; return; }
208 }
209
210 void MacroAssembler::decrementq(Address dst, int value) {
211 if (value == min_jint) { subq(dst, value); return; }
212 if (value < 0) { incrementq(dst, -value); return; }
213 if (value == 0) { ; return; }
214 if (value == 1 && UseIncDec) { decq(dst) ; return; }
215 /* else */ { subq(dst, value) ; return; }
216 }
217
218 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
219 assert(rscratch != noreg || always_reachable(dst), "missing");
220
221 if (reachable(dst)) {
222 incrementq(as_Address(dst));
223 } else {
224 lea(rscratch, dst);
225 incrementq(Address(rscratch, 0));
226 }
227 }
228
229 void MacroAssembler::incrementq(Register reg, int value) {
230 if (value == min_jint) { addq(reg, value); return; }
231 if (value < 0) { decrementq(reg, -value); return; }
232 if (value == 0) { ; return; }
233 if (value == 1 && UseIncDec) { incq(reg) ; return; }
234 /* else */ { addq(reg, value) ; return; }
235 }
236
237 void MacroAssembler::incrementq(Address dst, int value) {
238 if (value == min_jint) { addq(dst, value); return; }
239 if (value < 0) { decrementq(dst, -value); return; }
240 if (value == 0) { ; return; }
241 if (value == 1 && UseIncDec) { incq(dst) ; return; }
242 /* else */ { addq(dst, value) ; return; }
243 }
244
245 // 32bit can do a case table jump in one instruction but we no longer allow the base
246 // to be installed in the Address class
247 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
248 lea(rscratch, entry.base());
249 Address dispatch = entry.index();
250 assert(dispatch._base == noreg, "must be");
251 dispatch._base = rscratch;
252 jmp(dispatch);
253 }
254
255 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
256 ShouldNotReachHere(); // 64bit doesn't use two regs
257 cmpq(x_lo, y_lo);
258 }
259
260 void MacroAssembler::lea(Register dst, AddressLiteral src) {
261 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
262 }
263
264 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
265 lea(rscratch, adr);
266 movptr(dst, rscratch);
267 }
268
269 void MacroAssembler::leave() {
270 // %%% is this really better? Why not on 32bit too?
271 emit_int8((unsigned char)0xC9); // LEAVE
272 }
273
274 void MacroAssembler::lneg(Register hi, Register lo) {
275 ShouldNotReachHere(); // 64bit doesn't use two regs
276 negq(lo);
277 }
278
279 void MacroAssembler::movoop(Register dst, jobject obj) {
280 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
281 }
282
283 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
284 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
285 movq(dst, rscratch);
286 }
287
288 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
289 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
290 }
291
292 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
293 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
294 movq(dst, rscratch);
295 }
296
297 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
298 if (src.is_lval()) {
299 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
300 } else {
301 if (reachable(src)) {
302 movq(dst, as_Address(src));
303 } else {
304 lea(dst, src);
305 movq(dst, Address(dst, 0));
306 }
307 }
308 }
309
310 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
311 movq(as_Address(dst, rscratch), src);
312 }
313
314 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
315 movq(dst, as_Address(src, dst /*rscratch*/));
316 }
317
318 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
319 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
320 if (is_simm32(src)) {
321 movptr(dst, checked_cast<int32_t>(src));
322 } else {
323 mov64(rscratch, src);
324 movq(dst, rscratch);
325 }
326 }
327
328 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
329 movoop(rscratch, obj);
330 push(rscratch);
331 }
332
333 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
334 mov_metadata(rscratch, obj);
335 push(rscratch);
336 }
337
338 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
339 lea(rscratch, src);
340 if (src.is_lval()) {
341 push(rscratch);
342 } else {
343 pushq(Address(rscratch, 0));
344 }
345 }
346
347 static void pass_arg0(MacroAssembler* masm, Register arg) {
348 if (c_rarg0 != arg ) {
349 masm->mov(c_rarg0, arg);
350 }
351 }
352
353 static void pass_arg1(MacroAssembler* masm, Register arg) {
354 if (c_rarg1 != arg ) {
355 masm->mov(c_rarg1, arg);
356 }
357 }
358
359 static void pass_arg2(MacroAssembler* masm, Register arg) {
360 if (c_rarg2 != arg ) {
361 masm->mov(c_rarg2, arg);
362 }
363 }
364
365 static void pass_arg3(MacroAssembler* masm, Register arg) {
366 if (c_rarg3 != arg ) {
367 masm->mov(c_rarg3, arg);
368 }
369 }
370
371 void MacroAssembler::stop(const char* msg) {
372 if (ShowMessageBoxOnError) {
373 address rip = pc();
374 pusha(); // get regs on stack
375 lea(c_rarg1, InternalAddress(rip));
376 movq(c_rarg2, rsp); // pass pointer to regs array
377 }
378 // Skip AOT caching C strings in scratch buffer.
379 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
380 lea(c_rarg0, ExternalAddress((address) str));
381 andq(rsp, -16); // align stack as required by ABI
382 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
383 hlt();
384 }
385
386 void MacroAssembler::warn(const char* msg) {
387 push(rbp);
388 movq(rbp, rsp);
389 andq(rsp, -16); // align stack as required by push_CPU_state and call
390 push_CPU_state(); // keeps alignment at 16 bytes
391
392 #ifdef _WIN64
393 // Windows always allocates space for its register args
394 subq(rsp, frame::arg_reg_save_area_bytes);
395 #endif
396 lea(c_rarg0, ExternalAddress((address) msg));
397 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
398
399 #ifdef _WIN64
400 // restore stack pointer
401 addq(rsp, frame::arg_reg_save_area_bytes);
402 #endif
403 pop_CPU_state();
404 mov(rsp, rbp);
405 pop(rbp);
406 }
407
408 void MacroAssembler::print_state() {
409 address rip = pc();
410 pusha(); // get regs on stack
411 push(rbp);
412 movq(rbp, rsp);
413 andq(rsp, -16); // align stack as required by push_CPU_state and call
414 push_CPU_state(); // keeps alignment at 16 bytes
415
416 lea(c_rarg0, InternalAddress(rip));
417 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
418 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
419
420 pop_CPU_state();
421 mov(rsp, rbp);
422 pop(rbp);
423 popa();
424 }
425
426 #ifndef PRODUCT
427 extern "C" void findpc(intptr_t x);
428 #endif
429
430 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
431 // In order to get locks to work, we need to fake a in_VM state
432 if (ShowMessageBoxOnError) {
433 JavaThread* thread = JavaThread::current();
434 JavaThreadState saved_state = thread->thread_state();
435 thread->set_thread_state(_thread_in_vm);
436 #ifndef PRODUCT
437 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
438 ttyLocker ttyl;
439 BytecodeCounter::print();
440 }
441 #endif
442 // To see where a verify_oop failed, get $ebx+40/X for this frame.
443 // XXX correct this offset for amd64
444 // This is the value of eip which points to where verify_oop will return.
445 if (os::message_box(msg, "Execution stopped, print registers?")) {
446 print_state64(pc, regs);
447 BREAKPOINT;
448 }
449 }
450 fatal("DEBUG MESSAGE: %s", msg);
451 }
452
453 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
454 ttyLocker ttyl;
455 DebuggingContext debugging{};
456 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
457 #ifndef PRODUCT
458 tty->cr();
459 findpc(pc);
460 tty->cr();
461 #endif
462 #define PRINT_REG(rax, value) \
463 { tty->print("%s = ", #rax); os::print_location(tty, value); }
464 PRINT_REG(rax, regs[15]);
465 PRINT_REG(rbx, regs[12]);
466 PRINT_REG(rcx, regs[14]);
467 PRINT_REG(rdx, regs[13]);
468 PRINT_REG(rdi, regs[8]);
469 PRINT_REG(rsi, regs[9]);
470 PRINT_REG(rbp, regs[10]);
471 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
472 PRINT_REG(rsp, (intptr_t)(®s[16]));
473 PRINT_REG(r8 , regs[7]);
474 PRINT_REG(r9 , regs[6]);
475 PRINT_REG(r10, regs[5]);
476 PRINT_REG(r11, regs[4]);
477 PRINT_REG(r12, regs[3]);
478 PRINT_REG(r13, regs[2]);
479 PRINT_REG(r14, regs[1]);
480 PRINT_REG(r15, regs[0]);
481 #undef PRINT_REG
482 // Print some words near the top of the stack.
483 int64_t* rsp = ®s[16];
484 int64_t* dump_sp = rsp;
485 for (int col1 = 0; col1 < 8; col1++) {
486 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
487 os::print_location(tty, *dump_sp++);
488 }
489 for (int row = 0; row < 25; row++) {
490 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
491 for (int col = 0; col < 4; col++) {
492 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
493 }
494 tty->cr();
495 }
496 // Print some instructions around pc:
497 Disassembler::decode((address)pc-64, (address)pc);
498 tty->print_cr("--------");
499 Disassembler::decode((address)pc, (address)pc+32);
500 }
501
502 // The java_calling_convention describes stack locations as ideal slots on
503 // a frame with no abi restrictions. Since we must observe abi restrictions
504 // (like the placement of the register window) the slots must be biased by
505 // the following value.
506 static int reg2offset_in(VMReg r) {
507 // Account for saved rbp and return address
508 // This should really be in_preserve_stack_slots
509 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
510 }
511
512 static int reg2offset_out(VMReg r) {
513 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
514 }
515
516 // A long move
517 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
518
519 // The calling conventions assures us that each VMregpair is either
520 // all really one physical register or adjacent stack slots.
521
522 if (src.is_single_phys_reg() ) {
523 if (dst.is_single_phys_reg()) {
524 if (dst.first() != src.first()) {
525 mov(dst.first()->as_Register(), src.first()->as_Register());
526 }
527 } else {
528 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
529 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
530 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
531 }
532 } else if (dst.is_single_phys_reg()) {
533 assert(src.is_single_reg(), "not a stack pair");
534 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
535 } else {
536 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
537 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
538 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
539 }
540 }
541
542 // A double move
543 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
544
545 // The calling conventions assures us that each VMregpair is either
546 // all really one physical register or adjacent stack slots.
547
548 if (src.is_single_phys_reg() ) {
549 if (dst.is_single_phys_reg()) {
550 // In theory these overlap but the ordering is such that this is likely a nop
551 if ( src.first() != dst.first()) {
552 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
553 }
554 } else {
555 assert(dst.is_single_reg(), "not a stack pair");
556 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
557 }
558 } else if (dst.is_single_phys_reg()) {
559 assert(src.is_single_reg(), "not a stack pair");
560 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
561 } else {
562 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
563 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
564 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
565 }
566 }
567
568
569 // A float arg may have to do float reg int reg conversion
570 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
571 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
572
573 // The calling conventions assures us that each VMregpair is either
574 // all really one physical register or adjacent stack slots.
575
576 if (src.first()->is_stack()) {
577 if (dst.first()->is_stack()) {
578 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
579 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
580 } else {
581 // stack to reg
582 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
583 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
584 }
585 } else if (dst.first()->is_stack()) {
586 // reg to stack
587 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
588 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
589 } else {
590 // reg to reg
591 // In theory these overlap but the ordering is such that this is likely a nop
592 if ( src.first() != dst.first()) {
593 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
594 }
595 }
596 }
597
598 // On 64 bit we will store integer like items to the stack as
599 // 64 bits items (x86_32/64 abi) even though java would only store
600 // 32bits for a parameter. On 32bit it will simply be 32 bits
601 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
602 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
603 if (src.first()->is_stack()) {
604 if (dst.first()->is_stack()) {
605 // stack to stack
606 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
607 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
608 } else {
609 // stack to reg
610 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
611 }
612 } else if (dst.first()->is_stack()) {
613 // reg to stack
614 // Do we really have to sign extend???
615 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
616 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
617 } else {
618 // Do we really have to sign extend???
619 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
620 if (dst.first() != src.first()) {
621 movq(dst.first()->as_Register(), src.first()->as_Register());
622 }
623 }
624 }
625
626 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
627 if (src.first()->is_stack()) {
628 if (dst.first()->is_stack()) {
629 // stack to stack
630 movq(rax, Address(rbp, reg2offset_in(src.first())));
631 movq(Address(rsp, reg2offset_out(dst.first())), rax);
632 } else {
633 // stack to reg
634 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
635 }
636 } else if (dst.first()->is_stack()) {
637 // reg to stack
638 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
639 } else {
640 if (dst.first() != src.first()) {
641 movq(dst.first()->as_Register(), src.first()->as_Register());
642 }
643 }
644 }
645
646 // An oop arg. Must pass a handle not the oop itself
647 void MacroAssembler::object_move(OopMap* map,
648 int oop_handle_offset,
649 int framesize_in_slots,
650 VMRegPair src,
651 VMRegPair dst,
652 bool is_receiver,
653 int* receiver_offset) {
654
655 // must pass a handle. First figure out the location we use as a handle
656
657 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
658
659 // See if oop is null if it is we need no handle
660
661 if (src.first()->is_stack()) {
662
663 // Oop is already on the stack as an argument
664 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
665 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
666 if (is_receiver) {
667 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
668 }
669
670 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
671 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
672 // conditionally move a null
673 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
674 } else {
675
676 // Oop is in a register we must store it to the space we reserve
677 // on the stack for oop_handles and pass a handle if oop is non-null
678
679 const Register rOop = src.first()->as_Register();
680 int oop_slot;
681 if (rOop == j_rarg0)
682 oop_slot = 0;
683 else if (rOop == j_rarg1)
684 oop_slot = 1;
685 else if (rOop == j_rarg2)
686 oop_slot = 2;
687 else if (rOop == j_rarg3)
688 oop_slot = 3;
689 else if (rOop == j_rarg4)
690 oop_slot = 4;
691 else {
692 assert(rOop == j_rarg5, "wrong register");
693 oop_slot = 5;
694 }
695
696 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
697 int offset = oop_slot*VMRegImpl::stack_slot_size;
698
699 map->set_oop(VMRegImpl::stack2reg(oop_slot));
700 // Store oop in handle area, may be null
701 movptr(Address(rsp, offset), rOop);
702 if (is_receiver) {
703 *receiver_offset = offset;
704 }
705
706 cmpptr(rOop, NULL_WORD);
707 lea(rHandle, Address(rsp, offset));
708 // conditionally move a null from the handle area where it was just stored
709 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
710 }
711
712 // If arg is on the stack then place it otherwise it is already in correct reg.
713 if (dst.first()->is_stack()) {
714 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
715 }
716 }
717
718 void MacroAssembler::addptr(Register dst, int32_t imm32) {
719 addq(dst, imm32);
720 }
721
722 void MacroAssembler::addptr(Register dst, Register src) {
723 addq(dst, src);
724 }
725
726 void MacroAssembler::addptr(Address dst, Register src) {
727 addq(dst, src);
728 }
729
730 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
731 assert(rscratch != noreg || always_reachable(src), "missing");
732
733 if (reachable(src)) {
734 Assembler::addsd(dst, as_Address(src));
735 } else {
736 lea(rscratch, src);
737 Assembler::addsd(dst, Address(rscratch, 0));
738 }
739 }
740
741 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
742 assert(rscratch != noreg || always_reachable(src), "missing");
743
744 if (reachable(src)) {
745 addss(dst, as_Address(src));
746 } else {
747 lea(rscratch, src);
748 addss(dst, Address(rscratch, 0));
749 }
750 }
751
752 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
753 assert(rscratch != noreg || always_reachable(src), "missing");
754
755 if (reachable(src)) {
756 Assembler::addpd(dst, as_Address(src));
757 } else {
758 lea(rscratch, src);
759 Assembler::addpd(dst, Address(rscratch, 0));
760 }
761 }
762
763 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
764 // Stub code is generated once and never copied.
765 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
766 void MacroAssembler::align64() {
767 align(64, (uint)(uintptr_t)pc());
768 }
769
770 void MacroAssembler::align32() {
771 align(32, (uint)(uintptr_t)pc());
772 }
773
774 void MacroAssembler::align(uint modulus) {
775 // 8273459: Ensure alignment is possible with current segment alignment
776 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
777 align(modulus, offset());
778 }
779
780 void MacroAssembler::align(uint modulus, uint target) {
781 if (target % modulus != 0) {
782 nop(modulus - (target % modulus));
783 }
784 }
785
786 void MacroAssembler::push_f(XMMRegister r) {
787 subptr(rsp, wordSize);
788 movflt(Address(rsp, 0), r);
789 }
790
791 void MacroAssembler::pop_f(XMMRegister r) {
792 movflt(r, Address(rsp, 0));
793 addptr(rsp, wordSize);
794 }
795
796 void MacroAssembler::push_d(XMMRegister r) {
797 subptr(rsp, 2 * wordSize);
798 movdbl(Address(rsp, 0), r);
799 }
800
801 void MacroAssembler::pop_d(XMMRegister r) {
802 movdbl(r, Address(rsp, 0));
803 addptr(rsp, 2 * Interpreter::stackElementSize);
804 }
805
806 void MacroAssembler::push_ppx(Register src) {
807 if (VM_Version::supports_apx_f()) {
808 pushp(src);
809 } else {
810 Assembler::push(src);
811 }
812 }
813
814 void MacroAssembler::pop_ppx(Register dst) {
815 if (VM_Version::supports_apx_f()) {
816 popp(dst);
817 } else {
818 Assembler::pop(dst);
819 }
820 }
821
822 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
823 // Used in sign-masking with aligned address.
824 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
825 assert(rscratch != noreg || always_reachable(src), "missing");
826
827 if (UseAVX > 2 &&
828 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
829 (dst->encoding() >= 16)) {
830 vpand(dst, dst, src, AVX_512bit, rscratch);
831 } else if (reachable(src)) {
832 Assembler::andpd(dst, as_Address(src));
833 } else {
834 lea(rscratch, src);
835 Assembler::andpd(dst, Address(rscratch, 0));
836 }
837 }
838
839 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
840 // Used in sign-masking with aligned address.
841 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
842 assert(rscratch != noreg || always_reachable(src), "missing");
843
844 if (reachable(src)) {
845 Assembler::andps(dst, as_Address(src));
846 } else {
847 lea(rscratch, src);
848 Assembler::andps(dst, Address(rscratch, 0));
849 }
850 }
851
852 void MacroAssembler::andptr(Register dst, int32_t imm32) {
853 andq(dst, imm32);
854 }
855
856 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
857 assert(rscratch != noreg || always_reachable(src), "missing");
858
859 if (reachable(src)) {
860 andq(dst, as_Address(src));
861 } else {
862 lea(rscratch, src);
863 andq(dst, Address(rscratch, 0));
864 }
865 }
866
867 void MacroAssembler::atomic_incl(Address counter_addr) {
868 lock();
869 incrementl(counter_addr);
870 }
871
872 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
873 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
874
875 if (reachable(counter_addr)) {
876 atomic_incl(as_Address(counter_addr));
877 } else {
878 lea(rscratch, counter_addr);
879 atomic_incl(Address(rscratch, 0));
880 }
881 }
882
883 void MacroAssembler::atomic_incq(Address counter_addr) {
884 lock();
885 incrementq(counter_addr);
886 }
887
888 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
889 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
890
891 if (reachable(counter_addr)) {
892 atomic_incq(as_Address(counter_addr));
893 } else {
894 lea(rscratch, counter_addr);
895 atomic_incq(Address(rscratch, 0));
896 }
897 }
898
899 // Writes to stack successive pages until offset reached to check for
900 // stack overflow + shadow pages. This clobbers tmp.
901 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
902 movptr(tmp, rsp);
903 // Bang stack for total size given plus shadow page size.
904 // Bang one page at a time because large size can bang beyond yellow and
905 // red zones.
906 Label loop;
907 bind(loop);
908 movl(Address(tmp, (-(int)os::vm_page_size())), size );
909 subptr(tmp, (int)os::vm_page_size());
910 subl(size, (int)os::vm_page_size());
911 jcc(Assembler::greater, loop);
912
913 // Bang down shadow pages too.
914 // At this point, (tmp-0) is the last address touched, so don't
915 // touch it again. (It was touched as (tmp-pagesize) but then tmp
916 // was post-decremented.) Skip this address by starting at i=1, and
917 // touch a few more pages below. N.B. It is important to touch all
918 // the way down including all pages in the shadow zone.
919 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
920 // this could be any sized move but this is can be a debugging crumb
921 // so the bigger the better.
922 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
923 }
924 }
925
926 void MacroAssembler::reserved_stack_check() {
927 // testing if reserved zone needs to be enabled
928 Label no_reserved_zone_enabling;
929
930 cmpptr(rsp, Address(r15_thread, JavaThread::reserved_stack_activation_offset()));
931 jcc(Assembler::below, no_reserved_zone_enabling);
932
933 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), r15_thread);
934 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
935 should_not_reach_here();
936
937 bind(no_reserved_zone_enabling);
938 }
939
940 void MacroAssembler::c2bool(Register x) {
941 // implements x == 0 ? 0 : 1
942 // note: must only look at least-significant byte of x
943 // since C-style booleans are stored in one byte
944 // only! (was bug)
945 andl(x, 0xFF);
946 setb(Assembler::notZero, x);
947 }
948
949 // Wouldn't need if AddressLiteral version had new name
950 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
951 Assembler::call(L, rtype);
952 }
953
954 void MacroAssembler::call(Register entry) {
955 Assembler::call(entry);
956 }
957
958 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
959 assert(rscratch != noreg || always_reachable(entry), "missing");
960
961 if (reachable(entry)) {
962 Assembler::call_literal(entry.target(), entry.rspec());
963 } else {
964 lea(rscratch, entry);
965 Assembler::call(rscratch);
966 }
967 }
968
969 void MacroAssembler::ic_call(address entry, jint method_index) {
970 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
971 // Needs full 64-bit immediate for later patching.
972 mov64(rax, (int64_t)Universe::non_oop_word());
973 call(AddressLiteral(entry, rh));
974 }
975
976 int MacroAssembler::ic_check_size() {
977 return UseCompactObjectHeaders ? 17 : 14;
978 }
979
980 int MacroAssembler::ic_check(int end_alignment) {
981 Register receiver = j_rarg0;
982 Register data = rax;
983 Register temp = rscratch1;
984
985 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
986 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
987 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
988 // before the inline cache check here, and not after
989 align(end_alignment, offset() + ic_check_size());
990
991 int uep_offset = offset();
992
993 if (UseCompactObjectHeaders) {
994 load_narrow_klass_compact(temp, receiver);
995 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
996 } else if (UseCompressedClassPointers) {
997 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
998 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
999 } else {
1000 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1001 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1002 }
1003
1004 // if inline cache check fails, then jump to runtime routine
1005 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1006 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1007
1008 return uep_offset;
1009 }
1010
1011 void MacroAssembler::emit_static_call_stub() {
1012 // Static stub relocation also tags the Method* in the code-stream.
1013 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1014 // This is recognized as unresolved by relocs/nativeinst/ic code.
1015 jump(RuntimeAddress(pc()));
1016 }
1017
1018 // Implementation of call_VM versions
1019
1020 void MacroAssembler::call_VM(Register oop_result,
1021 address entry_point,
1022 bool check_exceptions) {
1023 Label C, E;
1024 call(C, relocInfo::none);
1025 jmp(E);
1026
1027 bind(C);
1028 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1029 ret(0);
1030
1031 bind(E);
1032 }
1033
1034 void MacroAssembler::call_VM(Register oop_result,
1035 address entry_point,
1036 Register arg_1,
1037 bool check_exceptions) {
1038 Label C, E;
1039 call(C, relocInfo::none);
1040 jmp(E);
1041
1042 bind(C);
1043 pass_arg1(this, arg_1);
1044 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1045 ret(0);
1046
1047 bind(E);
1048 }
1049
1050 void MacroAssembler::call_VM(Register oop_result,
1051 address entry_point,
1052 Register arg_1,
1053 Register arg_2,
1054 bool check_exceptions) {
1055 Label C, E;
1056 call(C, relocInfo::none);
1057 jmp(E);
1058
1059 bind(C);
1060
1061 assert_different_registers(arg_1, c_rarg2);
1062
1063 pass_arg2(this, arg_2);
1064 pass_arg1(this, arg_1);
1065 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1066 ret(0);
1067
1068 bind(E);
1069 }
1070
1071 void MacroAssembler::call_VM(Register oop_result,
1072 address entry_point,
1073 Register arg_1,
1074 Register arg_2,
1075 Register arg_3,
1076 bool check_exceptions) {
1077 Label C, E;
1078 call(C, relocInfo::none);
1079 jmp(E);
1080
1081 bind(C);
1082
1083 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1084 assert_different_registers(arg_2, c_rarg3);
1085 pass_arg3(this, arg_3);
1086 pass_arg2(this, arg_2);
1087 pass_arg1(this, arg_1);
1088 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1089 ret(0);
1090
1091 bind(E);
1092 }
1093
1094 void MacroAssembler::call_VM(Register oop_result,
1095 Register last_java_sp,
1096 address entry_point,
1097 int number_of_arguments,
1098 bool check_exceptions) {
1099 call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1100 }
1101
1102 void MacroAssembler::call_VM(Register oop_result,
1103 Register last_java_sp,
1104 address entry_point,
1105 Register arg_1,
1106 bool check_exceptions) {
1107 pass_arg1(this, arg_1);
1108 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1109 }
1110
1111 void MacroAssembler::call_VM(Register oop_result,
1112 Register last_java_sp,
1113 address entry_point,
1114 Register arg_1,
1115 Register arg_2,
1116 bool check_exceptions) {
1117
1118 assert_different_registers(arg_1, c_rarg2);
1119 pass_arg2(this, arg_2);
1120 pass_arg1(this, arg_1);
1121 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1122 }
1123
1124 void MacroAssembler::call_VM(Register oop_result,
1125 Register last_java_sp,
1126 address entry_point,
1127 Register arg_1,
1128 Register arg_2,
1129 Register arg_3,
1130 bool check_exceptions) {
1131 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1132 assert_different_registers(arg_2, c_rarg3);
1133 pass_arg3(this, arg_3);
1134 pass_arg2(this, arg_2);
1135 pass_arg1(this, arg_1);
1136 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1137 }
1138
1139 void MacroAssembler::super_call_VM(Register oop_result,
1140 Register last_java_sp,
1141 address entry_point,
1142 int number_of_arguments,
1143 bool check_exceptions) {
1144 MacroAssembler::call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1145 }
1146
1147 void MacroAssembler::super_call_VM(Register oop_result,
1148 Register last_java_sp,
1149 address entry_point,
1150 Register arg_1,
1151 bool check_exceptions) {
1152 pass_arg1(this, arg_1);
1153 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1154 }
1155
1156 void MacroAssembler::super_call_VM(Register oop_result,
1157 Register last_java_sp,
1158 address entry_point,
1159 Register arg_1,
1160 Register arg_2,
1161 bool check_exceptions) {
1162
1163 assert_different_registers(arg_1, c_rarg2);
1164 pass_arg2(this, arg_2);
1165 pass_arg1(this, arg_1);
1166 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1167 }
1168
1169 void MacroAssembler::super_call_VM(Register oop_result,
1170 Register last_java_sp,
1171 address entry_point,
1172 Register arg_1,
1173 Register arg_2,
1174 Register arg_3,
1175 bool check_exceptions) {
1176 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1177 assert_different_registers(arg_2, c_rarg3);
1178 pass_arg3(this, arg_3);
1179 pass_arg2(this, arg_2);
1180 pass_arg1(this, arg_1);
1181 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1182 }
1183
1184 void MacroAssembler::call_VM_base(Register oop_result,
1185 Register last_java_sp,
1186 address entry_point,
1187 int number_of_arguments,
1188 bool check_exceptions) {
1189 Register java_thread = r15_thread;
1190
1191 // determine last_java_sp register
1192 if (!last_java_sp->is_valid()) {
1193 last_java_sp = rsp;
1194 }
1195 // debugging support
1196 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1197 #ifdef ASSERT
1198 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1199 // r12 is the heapbase.
1200 if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
1201 #endif // ASSERT
1202
1203 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1204 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1205
1206 // push java thread (becomes first argument of C function)
1207
1208 mov(c_rarg0, r15_thread);
1209
1210 // set last Java frame before call
1211 assert(last_java_sp != rbp, "can't use ebp/rbp");
1212
1213 // Only interpreter should have to set fp
1214 set_last_Java_frame(last_java_sp, rbp, nullptr, rscratch1);
1215
1216 // do the call, remove parameters
1217 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1218
1219 #ifdef ASSERT
1220 // Check that thread register is not clobbered.
1221 guarantee(java_thread != rax, "change this code");
1222 push(rax);
1223 { Label L;
1224 get_thread_slow(rax);
1225 cmpptr(java_thread, rax);
1226 jcc(Assembler::equal, L);
1227 STOP("MacroAssembler::call_VM_base: java_thread not callee saved?");
1228 bind(L);
1229 }
1230 pop(rax);
1231 #endif
1232
1233 // reset last Java frame
1234 // Only interpreter should have to clear fp
1235 reset_last_Java_frame(true);
1236
1237 // C++ interp handles this in the interpreter
1238 check_and_handle_popframe();
1239 check_and_handle_earlyret();
1240
1241 if (check_exceptions) {
1242 // check for pending exceptions (java_thread is set upon return)
1243 cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
1244 // This used to conditionally jump to forward_exception however it is
1245 // possible if we relocate that the branch will not reach. So we must jump
1246 // around so we can always reach
1247
1248 Label ok;
1249 jcc(Assembler::equal, ok);
1250 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1251 bind(ok);
1252 }
1253
1254 // get oop result if there is one and reset the value in the thread
1255 if (oop_result->is_valid()) {
1256 get_vm_result_oop(oop_result);
1257 }
1258 }
1259
1260 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1261 // Calculate the value for last_Java_sp somewhat subtle.
1262 // call_VM does an intermediate call which places a return address on
1263 // the stack just under the stack pointer as the user finished with it.
1264 // This allows use to retrieve last_Java_pc from last_Java_sp[-1].
1265
1266 // We've pushed one address, correct last_Java_sp
1267 lea(rax, Address(rsp, wordSize));
1268
1269 call_VM_base(oop_result, rax, entry_point, number_of_arguments, check_exceptions);
1270 }
1271
1272 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1273 void MacroAssembler::call_VM_leaf0(address entry_point) {
1274 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1275 }
1276
1277 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1278 call_VM_leaf_base(entry_point, number_of_arguments);
1279 }
1280
1281 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1282 pass_arg0(this, arg_0);
1283 call_VM_leaf(entry_point, 1);
1284 }
1285
1286 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1287
1288 assert_different_registers(arg_0, c_rarg1);
1289 pass_arg1(this, arg_1);
1290 pass_arg0(this, arg_0);
1291 call_VM_leaf(entry_point, 2);
1292 }
1293
1294 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1295 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1296 assert_different_registers(arg_1, c_rarg2);
1297 pass_arg2(this, arg_2);
1298 pass_arg1(this, arg_1);
1299 pass_arg0(this, arg_0);
1300 call_VM_leaf(entry_point, 3);
1301 }
1302
1303 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1304 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1305 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1306 assert_different_registers(arg_2, c_rarg3);
1307 pass_arg3(this, arg_3);
1308 pass_arg2(this, arg_2);
1309 pass_arg1(this, arg_1);
1310 pass_arg0(this, arg_0);
1311 call_VM_leaf(entry_point, 3);
1312 }
1313
1314 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1315 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1316 }
1317
1318 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1319 pass_arg0(this, arg_0);
1320 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1321 }
1322
1323 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1324 assert_different_registers(arg_0, c_rarg1);
1325 pass_arg1(this, arg_1);
1326 pass_arg0(this, arg_0);
1327 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1328 }
1329
1330 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1331 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1332 assert_different_registers(arg_1, c_rarg2);
1333 pass_arg2(this, arg_2);
1334 pass_arg1(this, arg_1);
1335 pass_arg0(this, arg_0);
1336 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1337 }
1338
1339 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1340 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1341 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1342 assert_different_registers(arg_2, c_rarg3);
1343 pass_arg3(this, arg_3);
1344 pass_arg2(this, arg_2);
1345 pass_arg1(this, arg_1);
1346 pass_arg0(this, arg_0);
1347 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1348 }
1349
1350 void MacroAssembler::get_vm_result_oop(Register oop_result) {
1351 movptr(oop_result, Address(r15_thread, JavaThread::vm_result_oop_offset()));
1352 movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
1353 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1354 }
1355
1356 void MacroAssembler::get_vm_result_metadata(Register metadata_result) {
1357 movptr(metadata_result, Address(r15_thread, JavaThread::vm_result_metadata_offset()));
1358 movptr(Address(r15_thread, JavaThread::vm_result_metadata_offset()), NULL_WORD);
1359 }
1360
1361 void MacroAssembler::check_and_handle_earlyret() {
1362 }
1363
1364 void MacroAssembler::check_and_handle_popframe() {
1365 }
1366
1367 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1368 assert(rscratch != noreg || always_reachable(src1), "missing");
1369
1370 if (reachable(src1)) {
1371 cmpl(as_Address(src1), imm);
1372 } else {
1373 lea(rscratch, src1);
1374 cmpl(Address(rscratch, 0), imm);
1375 }
1376 }
1377
1378 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1379 assert(!src2.is_lval(), "use cmpptr");
1380 assert(rscratch != noreg || always_reachable(src2), "missing");
1381
1382 if (reachable(src2)) {
1383 cmpl(src1, as_Address(src2));
1384 } else {
1385 lea(rscratch, src2);
1386 cmpl(src1, Address(rscratch, 0));
1387 }
1388 }
1389
1390 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1391 Assembler::cmpl(src1, imm);
1392 }
1393
1394 void MacroAssembler::cmp32(Register src1, Address src2) {
1395 Assembler::cmpl(src1, src2);
1396 }
1397
1398 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1399 ucomisd(opr1, opr2);
1400
1401 Label L;
1402 if (unordered_is_less) {
1403 movl(dst, -1);
1404 jcc(Assembler::parity, L);
1405 jcc(Assembler::below , L);
1406 movl(dst, 0);
1407 jcc(Assembler::equal , L);
1408 increment(dst);
1409 } else { // unordered is greater
1410 movl(dst, 1);
1411 jcc(Assembler::parity, L);
1412 jcc(Assembler::above , L);
1413 movl(dst, 0);
1414 jcc(Assembler::equal , L);
1415 decrementl(dst);
1416 }
1417 bind(L);
1418 }
1419
1420 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1421 ucomiss(opr1, opr2);
1422
1423 Label L;
1424 if (unordered_is_less) {
1425 movl(dst, -1);
1426 jcc(Assembler::parity, L);
1427 jcc(Assembler::below , L);
1428 movl(dst, 0);
1429 jcc(Assembler::equal , L);
1430 increment(dst);
1431 } else { // unordered is greater
1432 movl(dst, 1);
1433 jcc(Assembler::parity, L);
1434 jcc(Assembler::above , L);
1435 movl(dst, 0);
1436 jcc(Assembler::equal , L);
1437 decrementl(dst);
1438 }
1439 bind(L);
1440 }
1441
1442
1443 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1444 assert(rscratch != noreg || always_reachable(src1), "missing");
1445
1446 if (reachable(src1)) {
1447 cmpb(as_Address(src1), imm);
1448 } else {
1449 lea(rscratch, src1);
1450 cmpb(Address(rscratch, 0), imm);
1451 }
1452 }
1453
1454 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1455 assert(rscratch != noreg || always_reachable(src2), "missing");
1456
1457 if (src2.is_lval()) {
1458 movptr(rscratch, src2);
1459 Assembler::cmpq(src1, rscratch);
1460 } else if (reachable(src2)) {
1461 cmpq(src1, as_Address(src2));
1462 } else {
1463 lea(rscratch, src2);
1464 Assembler::cmpq(src1, Address(rscratch, 0));
1465 }
1466 }
1467
1468 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1469 assert(src2.is_lval(), "not a mem-mem compare");
1470 // moves src2's literal address
1471 movptr(rscratch, src2);
1472 Assembler::cmpq(src1, rscratch);
1473 }
1474
1475 void MacroAssembler::cmpoop(Register src1, Register src2) {
1476 cmpptr(src1, src2);
1477 }
1478
1479 void MacroAssembler::cmpoop(Register src1, Address src2) {
1480 cmpptr(src1, src2);
1481 }
1482
1483 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1484 movoop(rscratch, src2);
1485 cmpptr(src1, rscratch);
1486 }
1487
1488 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1489 assert(rscratch != noreg || always_reachable(adr), "missing");
1490
1491 if (reachable(adr)) {
1492 lock();
1493 cmpxchgptr(reg, as_Address(adr));
1494 } else {
1495 lea(rscratch, adr);
1496 lock();
1497 cmpxchgptr(reg, Address(rscratch, 0));
1498 }
1499 }
1500
1501 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1502 cmpxchgq(reg, adr);
1503 }
1504
1505 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1506 assert(rscratch != noreg || always_reachable(src), "missing");
1507
1508 if (reachable(src)) {
1509 Assembler::comisd(dst, as_Address(src));
1510 } else {
1511 lea(rscratch, src);
1512 Assembler::comisd(dst, Address(rscratch, 0));
1513 }
1514 }
1515
1516 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1517 assert(rscratch != noreg || always_reachable(src), "missing");
1518
1519 if (reachable(src)) {
1520 Assembler::comiss(dst, as_Address(src));
1521 } else {
1522 lea(rscratch, src);
1523 Assembler::comiss(dst, Address(rscratch, 0));
1524 }
1525 }
1526
1527
1528 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1529 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1530
1531 Condition negated_cond = negate_condition(cond);
1532 Label L;
1533 jcc(negated_cond, L);
1534 pushf(); // Preserve flags
1535 atomic_incl(counter_addr, rscratch);
1536 popf();
1537 bind(L);
1538 }
1539
1540 int MacroAssembler::corrected_idivl(Register reg) {
1541 // Full implementation of Java idiv and irem; checks for
1542 // special case as described in JVM spec., p.243 & p.271.
1543 // The function returns the (pc) offset of the idivl
1544 // instruction - may be needed for implicit exceptions.
1545 //
1546 // normal case special case
1547 //
1548 // input : rax,: dividend min_int
1549 // reg: divisor (may not be rax,/rdx) -1
1550 //
1551 // output: rax,: quotient (= rax, idiv reg) min_int
1552 // rdx: remainder (= rax, irem reg) 0
1553 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1554 const int min_int = 0x80000000;
1555 Label normal_case, special_case;
1556
1557 // check for special case
1558 cmpl(rax, min_int);
1559 jcc(Assembler::notEqual, normal_case);
1560 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1561 cmpl(reg, -1);
1562 jcc(Assembler::equal, special_case);
1563
1564 // handle normal case
1565 bind(normal_case);
1566 cdql();
1567 int idivl_offset = offset();
1568 idivl(reg);
1569
1570 // normal and special case exit
1571 bind(special_case);
1572
1573 return idivl_offset;
1574 }
1575
1576
1577
1578 void MacroAssembler::decrementl(Register reg, int value) {
1579 if (value == min_jint) {subl(reg, value) ; return; }
1580 if (value < 0) { incrementl(reg, -value); return; }
1581 if (value == 0) { ; return; }
1582 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1583 /* else */ { subl(reg, value) ; return; }
1584 }
1585
1586 void MacroAssembler::decrementl(Address dst, int value) {
1587 if (value == min_jint) {subl(dst, value) ; return; }
1588 if (value < 0) { incrementl(dst, -value); return; }
1589 if (value == 0) { ; return; }
1590 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1591 /* else */ { subl(dst, value) ; return; }
1592 }
1593
1594 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1595 assert(shift_value > 0, "illegal shift value");
1596 Label _is_positive;
1597 testl (reg, reg);
1598 jcc (Assembler::positive, _is_positive);
1599 int offset = (1 << shift_value) - 1 ;
1600
1601 if (offset == 1) {
1602 incrementl(reg);
1603 } else {
1604 addl(reg, offset);
1605 }
1606
1607 bind (_is_positive);
1608 sarl(reg, shift_value);
1609 }
1610
1611 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1612 assert(rscratch != noreg || always_reachable(src), "missing");
1613
1614 if (reachable(src)) {
1615 Assembler::divsd(dst, as_Address(src));
1616 } else {
1617 lea(rscratch, src);
1618 Assembler::divsd(dst, Address(rscratch, 0));
1619 }
1620 }
1621
1622 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1623 assert(rscratch != noreg || always_reachable(src), "missing");
1624
1625 if (reachable(src)) {
1626 Assembler::divss(dst, as_Address(src));
1627 } else {
1628 lea(rscratch, src);
1629 Assembler::divss(dst, Address(rscratch, 0));
1630 }
1631 }
1632
1633 void MacroAssembler::enter() {
1634 push(rbp);
1635 mov(rbp, rsp);
1636 }
1637
1638 void MacroAssembler::post_call_nop() {
1639 if (!Continuations::enabled()) {
1640 return;
1641 }
1642 InstructionMark im(this);
1643 relocate(post_call_nop_Relocation::spec());
1644 InlineSkippedInstructionsCounter skipCounter(this);
1645 emit_int8((uint8_t)0x0f);
1646 emit_int8((uint8_t)0x1f);
1647 emit_int8((uint8_t)0x84);
1648 emit_int8((uint8_t)0x00);
1649 emit_int32(0x00);
1650 }
1651
1652 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1653 assert(rscratch != noreg || always_reachable(src), "missing");
1654 if (reachable(src)) {
1655 Assembler::mulpd(dst, as_Address(src));
1656 } else {
1657 lea(rscratch, src);
1658 Assembler::mulpd(dst, Address(rscratch, 0));
1659 }
1660 }
1661
1662 // dst = c = a * b + c
1663 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1664 Assembler::vfmadd231sd(c, a, b);
1665 if (dst != c) {
1666 movdbl(dst, c);
1667 }
1668 }
1669
1670 // dst = c = a * b + c
1671 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1672 Assembler::vfmadd231ss(c, a, b);
1673 if (dst != c) {
1674 movflt(dst, c);
1675 }
1676 }
1677
1678 // dst = c = a * b + c
1679 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1680 Assembler::vfmadd231pd(c, a, b, vector_len);
1681 if (dst != c) {
1682 vmovdqu(dst, c);
1683 }
1684 }
1685
1686 // dst = c = a * b + c
1687 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1688 Assembler::vfmadd231ps(c, a, b, vector_len);
1689 if (dst != c) {
1690 vmovdqu(dst, c);
1691 }
1692 }
1693
1694 // dst = c = a * b + c
1695 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1696 Assembler::vfmadd231pd(c, a, b, vector_len);
1697 if (dst != c) {
1698 vmovdqu(dst, c);
1699 }
1700 }
1701
1702 // dst = c = a * b + c
1703 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1704 Assembler::vfmadd231ps(c, a, b, vector_len);
1705 if (dst != c) {
1706 vmovdqu(dst, c);
1707 }
1708 }
1709
1710 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
1711 assert(rscratch != noreg || always_reachable(dst), "missing");
1712
1713 if (reachable(dst)) {
1714 incrementl(as_Address(dst));
1715 } else {
1716 lea(rscratch, dst);
1717 incrementl(Address(rscratch, 0));
1718 }
1719 }
1720
1721 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
1722 incrementl(as_Address(dst, rscratch));
1723 }
1724
1725 void MacroAssembler::incrementl(Register reg, int value) {
1726 if (value == min_jint) {addl(reg, value) ; return; }
1727 if (value < 0) { decrementl(reg, -value); return; }
1728 if (value == 0) { ; return; }
1729 if (value == 1 && UseIncDec) { incl(reg) ; return; }
1730 /* else */ { addl(reg, value) ; return; }
1731 }
1732
1733 void MacroAssembler::incrementl(Address dst, int value) {
1734 if (value == min_jint) {addl(dst, value) ; return; }
1735 if (value < 0) { decrementl(dst, -value); return; }
1736 if (value == 0) { ; return; }
1737 if (value == 1 && UseIncDec) { incl(dst) ; return; }
1738 /* else */ { addl(dst, value) ; return; }
1739 }
1740
1741 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
1742 assert(rscratch != noreg || always_reachable(dst), "missing");
1743 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
1744 if (reachable(dst)) {
1745 jmp_literal(dst.target(), dst.rspec());
1746 } else {
1747 lea(rscratch, dst);
1748 jmp(rscratch);
1749 }
1750 }
1751
1752 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
1753 assert(rscratch != noreg || always_reachable(dst), "missing");
1754 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
1755 if (reachable(dst)) {
1756 InstructionMark im(this);
1757 relocate(dst.reloc());
1758 const int short_size = 2;
1759 const int long_size = 6;
1760 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
1761 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
1762 // 0111 tttn #8-bit disp
1763 emit_int8(0x70 | cc);
1764 emit_int8((offs - short_size) & 0xFF);
1765 } else {
1766 // 0000 1111 1000 tttn #32-bit disp
1767 emit_int8(0x0F);
1768 emit_int8((unsigned char)(0x80 | cc));
1769 emit_int32(offs - long_size);
1770 }
1771 } else {
1772 #ifdef ASSERT
1773 warning("reversing conditional branch");
1774 #endif /* ASSERT */
1775 Label skip;
1776 jccb(reverse[cc], skip);
1777 lea(rscratch, dst);
1778 Assembler::jmp(rscratch);
1779 bind(skip);
1780 }
1781 }
1782
1783 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
1784 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
1785 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
1786
1787 stmxcsr(mxcsr_save);
1788 movl(tmp, mxcsr_save);
1789 if (EnableX86ECoreOpts) {
1790 // The mxcsr_std has status bits set for performance on ECore
1791 orl(tmp, 0x003f);
1792 } else {
1793 // Mask out status bits (only check control and mask bits)
1794 andl(tmp, 0xFFC0);
1795 }
1796 cmp32(tmp, mxcsr_std, rscratch);
1797 }
1798
1799 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
1800 assert(rscratch != noreg || always_reachable(src), "missing");
1801
1802 if (reachable(src)) {
1803 Assembler::ldmxcsr(as_Address(src));
1804 } else {
1805 lea(rscratch, src);
1806 Assembler::ldmxcsr(Address(rscratch, 0));
1807 }
1808 }
1809
1810 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1811 int off = offset();
1812 movsbl(dst, src); // movsxb
1813 return off;
1814 }
1815
1816 // Note: load_signed_short used to be called load_signed_word.
1817 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
1818 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
1819 // The term "word" in HotSpot means a 32- or 64-bit machine word.
1820 int MacroAssembler::load_signed_short(Register dst, Address src) {
1821 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
1822 // version but this is what 64bit has always done. This seems to imply
1823 // that users are only using 32bits worth.
1824 int off = offset();
1825 movswl(dst, src); // movsxw
1826 return off;
1827 }
1828
1829 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1830 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1831 // and "3.9 Partial Register Penalties", p. 22).
1832 int off = offset();
1833 movzbl(dst, src); // movzxb
1834 return off;
1835 }
1836
1837 // Note: load_unsigned_short used to be called load_unsigned_word.
1838 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1839 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1840 // and "3.9 Partial Register Penalties", p. 22).
1841 int off = offset();
1842 movzwl(dst, src); // movzxw
1843 return off;
1844 }
1845
1846 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1847 switch (size_in_bytes) {
1848 case 8: movq(dst, src); break;
1849 case 4: movl(dst, src); break;
1850 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1851 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1852 default: ShouldNotReachHere();
1853 }
1854 }
1855
1856 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1857 switch (size_in_bytes) {
1858 case 8: movq(dst, src); break;
1859 case 4: movl(dst, src); break;
1860 case 2: movw(dst, src); break;
1861 case 1: movb(dst, src); break;
1862 default: ShouldNotReachHere();
1863 }
1864 }
1865
1866 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
1867 assert(rscratch != noreg || always_reachable(dst), "missing");
1868
1869 if (reachable(dst)) {
1870 movl(as_Address(dst), src);
1871 } else {
1872 lea(rscratch, dst);
1873 movl(Address(rscratch, 0), src);
1874 }
1875 }
1876
1877 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
1878 if (reachable(src)) {
1879 movl(dst, as_Address(src));
1880 } else {
1881 lea(dst, src);
1882 movl(dst, Address(dst, 0));
1883 }
1884 }
1885
1886 // C++ bool manipulation
1887
1888 void MacroAssembler::movbool(Register dst, Address src) {
1889 if(sizeof(bool) == 1)
1890 movb(dst, src);
1891 else if(sizeof(bool) == 2)
1892 movw(dst, src);
1893 else if(sizeof(bool) == 4)
1894 movl(dst, src);
1895 else
1896 // unsupported
1897 ShouldNotReachHere();
1898 }
1899
1900 void MacroAssembler::movbool(Address dst, bool boolconst) {
1901 if(sizeof(bool) == 1)
1902 movb(dst, (int) boolconst);
1903 else if(sizeof(bool) == 2)
1904 movw(dst, (int) boolconst);
1905 else if(sizeof(bool) == 4)
1906 movl(dst, (int) boolconst);
1907 else
1908 // unsupported
1909 ShouldNotReachHere();
1910 }
1911
1912 void MacroAssembler::movbool(Address dst, Register src) {
1913 if(sizeof(bool) == 1)
1914 movb(dst, src);
1915 else if(sizeof(bool) == 2)
1916 movw(dst, src);
1917 else if(sizeof(bool) == 4)
1918 movl(dst, src);
1919 else
1920 // unsupported
1921 ShouldNotReachHere();
1922 }
1923
1924 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1925 assert(rscratch != noreg || always_reachable(src), "missing");
1926
1927 if (reachable(src)) {
1928 movdl(dst, as_Address(src));
1929 } else {
1930 lea(rscratch, src);
1931 movdl(dst, Address(rscratch, 0));
1932 }
1933 }
1934
1935 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
1936 assert(rscratch != noreg || always_reachable(src), "missing");
1937
1938 if (reachable(src)) {
1939 movq(dst, as_Address(src));
1940 } else {
1941 lea(rscratch, src);
1942 movq(dst, Address(rscratch, 0));
1943 }
1944 }
1945
1946 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1947 assert(rscratch != noreg || always_reachable(src), "missing");
1948
1949 if (reachable(src)) {
1950 if (UseXmmLoadAndClearUpper) {
1951 movsd (dst, as_Address(src));
1952 } else {
1953 movlpd(dst, as_Address(src));
1954 }
1955 } else {
1956 lea(rscratch, src);
1957 if (UseXmmLoadAndClearUpper) {
1958 movsd (dst, Address(rscratch, 0));
1959 } else {
1960 movlpd(dst, Address(rscratch, 0));
1961 }
1962 }
1963 }
1964
1965 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
1966 assert(rscratch != noreg || always_reachable(src), "missing");
1967
1968 if (reachable(src)) {
1969 movss(dst, as_Address(src));
1970 } else {
1971 lea(rscratch, src);
1972 movss(dst, Address(rscratch, 0));
1973 }
1974 }
1975
1976 void MacroAssembler::movptr(Register dst, Register src) {
1977 movq(dst, src);
1978 }
1979
1980 void MacroAssembler::movptr(Register dst, Address src) {
1981 movq(dst, src);
1982 }
1983
1984 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
1985 void MacroAssembler::movptr(Register dst, intptr_t src) {
1986 if (is_uimm32(src)) {
1987 movl(dst, checked_cast<uint32_t>(src));
1988 } else if (is_simm32(src)) {
1989 movq(dst, checked_cast<int32_t>(src));
1990 } else {
1991 mov64(dst, src);
1992 }
1993 }
1994
1995 void MacroAssembler::movptr(Address dst, Register src) {
1996 movq(dst, src);
1997 }
1998
1999 void MacroAssembler::movptr(Address dst, int32_t src) {
2000 movslq(dst, src);
2001 }
2002
2003 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2004 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2005 Assembler::movdqu(dst, src);
2006 }
2007
2008 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2009 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2010 Assembler::movdqu(dst, src);
2011 }
2012
2013 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2014 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2015 Assembler::movdqu(dst, src);
2016 }
2017
2018 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2019 assert(rscratch != noreg || always_reachable(src), "missing");
2020
2021 if (reachable(src)) {
2022 movdqu(dst, as_Address(src));
2023 } else {
2024 lea(rscratch, src);
2025 movdqu(dst, Address(rscratch, 0));
2026 }
2027 }
2028
2029 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2030 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2031 Assembler::vmovdqu(dst, src);
2032 }
2033
2034 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2035 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2036 Assembler::vmovdqu(dst, src);
2037 }
2038
2039 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2040 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2041 Assembler::vmovdqu(dst, src);
2042 }
2043
2044 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2045 assert(rscratch != noreg || always_reachable(src), "missing");
2046
2047 if (reachable(src)) {
2048 vmovdqu(dst, as_Address(src));
2049 }
2050 else {
2051 lea(rscratch, src);
2052 vmovdqu(dst, Address(rscratch, 0));
2053 }
2054 }
2055
2056 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2057 assert(rscratch != noreg || always_reachable(src), "missing");
2058
2059 if (vector_len == AVX_512bit) {
2060 evmovdquq(dst, src, AVX_512bit, rscratch);
2061 } else if (vector_len == AVX_256bit) {
2062 vmovdqu(dst, src, rscratch);
2063 } else {
2064 movdqu(dst, src, rscratch);
2065 }
2066 }
2067
2068 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2069 if (vector_len == AVX_512bit) {
2070 evmovdquq(dst, src, AVX_512bit);
2071 } else if (vector_len == AVX_256bit) {
2072 vmovdqu(dst, src);
2073 } else {
2074 movdqu(dst, src);
2075 }
2076 }
2077
2078 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2079 if (vector_len == AVX_512bit) {
2080 evmovdquq(dst, src, AVX_512bit);
2081 } else if (vector_len == AVX_256bit) {
2082 vmovdqu(dst, src);
2083 } else {
2084 movdqu(dst, src);
2085 }
2086 }
2087
2088 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2089 if (vector_len == AVX_512bit) {
2090 evmovdquq(dst, src, AVX_512bit);
2091 } else if (vector_len == AVX_256bit) {
2092 vmovdqu(dst, src);
2093 } else {
2094 movdqu(dst, src);
2095 }
2096 }
2097
2098 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2099 assert(rscratch != noreg || always_reachable(src), "missing");
2100
2101 if (reachable(src)) {
2102 vmovdqa(dst, as_Address(src));
2103 }
2104 else {
2105 lea(rscratch, src);
2106 vmovdqa(dst, Address(rscratch, 0));
2107 }
2108 }
2109
2110 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2111 assert(rscratch != noreg || always_reachable(src), "missing");
2112
2113 if (vector_len == AVX_512bit) {
2114 evmovdqaq(dst, src, AVX_512bit, rscratch);
2115 } else if (vector_len == AVX_256bit) {
2116 vmovdqa(dst, src, rscratch);
2117 } else {
2118 movdqa(dst, src, rscratch);
2119 }
2120 }
2121
2122 void MacroAssembler::kmov(KRegister dst, Address src) {
2123 if (VM_Version::supports_avx512bw()) {
2124 kmovql(dst, src);
2125 } else {
2126 assert(VM_Version::supports_evex(), "");
2127 kmovwl(dst, src);
2128 }
2129 }
2130
2131 void MacroAssembler::kmov(Address dst, KRegister src) {
2132 if (VM_Version::supports_avx512bw()) {
2133 kmovql(dst, src);
2134 } else {
2135 assert(VM_Version::supports_evex(), "");
2136 kmovwl(dst, src);
2137 }
2138 }
2139
2140 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2141 if (VM_Version::supports_avx512bw()) {
2142 kmovql(dst, src);
2143 } else {
2144 assert(VM_Version::supports_evex(), "");
2145 kmovwl(dst, src);
2146 }
2147 }
2148
2149 void MacroAssembler::kmov(Register dst, KRegister src) {
2150 if (VM_Version::supports_avx512bw()) {
2151 kmovql(dst, src);
2152 } else {
2153 assert(VM_Version::supports_evex(), "");
2154 kmovwl(dst, src);
2155 }
2156 }
2157
2158 void MacroAssembler::kmov(KRegister dst, Register src) {
2159 if (VM_Version::supports_avx512bw()) {
2160 kmovql(dst, src);
2161 } else {
2162 assert(VM_Version::supports_evex(), "");
2163 kmovwl(dst, src);
2164 }
2165 }
2166
2167 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2168 assert(rscratch != noreg || always_reachable(src), "missing");
2169
2170 if (reachable(src)) {
2171 kmovql(dst, as_Address(src));
2172 } else {
2173 lea(rscratch, src);
2174 kmovql(dst, Address(rscratch, 0));
2175 }
2176 }
2177
2178 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2179 assert(rscratch != noreg || always_reachable(src), "missing");
2180
2181 if (reachable(src)) {
2182 kmovwl(dst, as_Address(src));
2183 } else {
2184 lea(rscratch, src);
2185 kmovwl(dst, Address(rscratch, 0));
2186 }
2187 }
2188
2189 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2190 int vector_len, Register rscratch) {
2191 assert(rscratch != noreg || always_reachable(src), "missing");
2192
2193 if (reachable(src)) {
2194 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2195 } else {
2196 lea(rscratch, src);
2197 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2198 }
2199 }
2200
2201 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2202 int vector_len, Register rscratch) {
2203 assert(rscratch != noreg || always_reachable(src), "missing");
2204
2205 if (reachable(src)) {
2206 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2207 } else {
2208 lea(rscratch, src);
2209 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2210 }
2211 }
2212
2213 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2214 assert(rscratch != noreg || always_reachable(src), "missing");
2215
2216 if (reachable(src)) {
2217 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2218 } else {
2219 lea(rscratch, src);
2220 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2221 }
2222 }
2223
2224 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2225 assert(rscratch != noreg || always_reachable(src), "missing");
2226
2227 if (reachable(src)) {
2228 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2229 } else {
2230 lea(rscratch, src);
2231 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2232 }
2233 }
2234
2235 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2236 assert(rscratch != noreg || always_reachable(src), "missing");
2237
2238 if (reachable(src)) {
2239 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2240 } else {
2241 lea(rscratch, src);
2242 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2243 }
2244 }
2245
2246 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2247 assert(rscratch != noreg || always_reachable(src), "missing");
2248
2249 if (reachable(src)) {
2250 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2251 } else {
2252 lea(rscratch, src);
2253 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2254 }
2255 }
2256
2257 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2258 assert(rscratch != noreg || always_reachable(src), "missing");
2259
2260 if (reachable(src)) {
2261 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2262 } else {
2263 lea(rscratch, src);
2264 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2265 }
2266 }
2267
2268 void MacroAssembler::movapd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2269 assert(rscratch != noreg || always_reachable(src), "missing");
2270
2271 if (reachable(src)) {
2272 Assembler::movapd(dst, as_Address(src));
2273 } else {
2274 lea(rscratch, src);
2275 Assembler::movapd(dst, Address(rscratch, 0));
2276 }
2277 }
2278
2279 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2280 assert(rscratch != noreg || always_reachable(src), "missing");
2281
2282 if (reachable(src)) {
2283 Assembler::movdqa(dst, as_Address(src));
2284 } else {
2285 lea(rscratch, src);
2286 Assembler::movdqa(dst, Address(rscratch, 0));
2287 }
2288 }
2289
2290 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2291 assert(rscratch != noreg || always_reachable(src), "missing");
2292
2293 if (reachable(src)) {
2294 Assembler::movsd(dst, as_Address(src));
2295 } else {
2296 lea(rscratch, src);
2297 Assembler::movsd(dst, Address(rscratch, 0));
2298 }
2299 }
2300
2301 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2302 assert(rscratch != noreg || always_reachable(src), "missing");
2303
2304 if (reachable(src)) {
2305 Assembler::movss(dst, as_Address(src));
2306 } else {
2307 lea(rscratch, src);
2308 Assembler::movss(dst, Address(rscratch, 0));
2309 }
2310 }
2311
2312 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2313 assert(rscratch != noreg || always_reachable(src), "missing");
2314
2315 if (reachable(src)) {
2316 Assembler::movddup(dst, as_Address(src));
2317 } else {
2318 lea(rscratch, src);
2319 Assembler::movddup(dst, Address(rscratch, 0));
2320 }
2321 }
2322
2323 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2324 assert(rscratch != noreg || always_reachable(src), "missing");
2325
2326 if (reachable(src)) {
2327 Assembler::vmovddup(dst, as_Address(src), vector_len);
2328 } else {
2329 lea(rscratch, src);
2330 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2331 }
2332 }
2333
2334 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2335 assert(rscratch != noreg || always_reachable(src), "missing");
2336
2337 if (reachable(src)) {
2338 Assembler::mulsd(dst, as_Address(src));
2339 } else {
2340 lea(rscratch, src);
2341 Assembler::mulsd(dst, Address(rscratch, 0));
2342 }
2343 }
2344
2345 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2346 assert(rscratch != noreg || always_reachable(src), "missing");
2347
2348 if (reachable(src)) {
2349 Assembler::mulss(dst, as_Address(src));
2350 } else {
2351 lea(rscratch, src);
2352 Assembler::mulss(dst, Address(rscratch, 0));
2353 }
2354 }
2355
2356 void MacroAssembler::null_check(Register reg, int offset) {
2357 if (needs_explicit_null_check(offset)) {
2358 // provoke OS null exception if reg is null by
2359 // accessing M[reg] w/o changing any (non-CC) registers
2360 // NOTE: cmpl is plenty here to provoke a segv
2361 cmpptr(rax, Address(reg, 0));
2362 // Note: should probably use testl(rax, Address(reg, 0));
2363 // may be shorter code (however, this version of
2364 // testl needs to be implemented first)
2365 } else {
2366 // nothing to do, (later) access of M[reg + offset]
2367 // will provoke OS null exception if reg is null
2368 }
2369 }
2370
2371 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2372 andptr(markword, markWord::inline_type_mask_in_place);
2373 cmpptr(markword, markWord::inline_type_pattern);
2374 jcc(Assembler::equal, is_inline_type);
2375 }
2376
2377 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null) {
2378 if (can_be_null) {
2379 testptr(object, object);
2380 jcc(Assembler::zero, not_inline_type);
2381 }
2382 const int is_inline_type_mask = markWord::inline_type_pattern;
2383 movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2384 andptr(tmp, is_inline_type_mask);
2385 cmpptr(tmp, is_inline_type_mask);
2386 jcc(Assembler::notEqual, not_inline_type);
2387 }
2388
2389 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2390 movl(temp_reg, flags);
2391 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2392 jcc(Assembler::notEqual, is_null_free_inline_type);
2393 }
2394
2395 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2396 movl(temp_reg, flags);
2397 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2398 jcc(Assembler::equal, not_null_free_inline_type);
2399 }
2400
2401 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2402 movl(temp_reg, flags);
2403 testl(temp_reg, 1 << ResolvedFieldEntry::is_flat_shift);
2404 jcc(Assembler::notEqual, is_flat);
2405 }
2406
2407 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2408 movl(temp_reg, flags);
2409 testl(temp_reg, 1 << ResolvedFieldEntry::has_null_marker_shift);
2410 jcc(Assembler::notEqual, has_null_marker);
2411 }
2412
2413 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2414 Label test_mark_word;
2415 // load mark word
2416 movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2417 // check displaced
2418 testl(temp_reg, markWord::unlocked_value);
2419 jccb(Assembler::notZero, test_mark_word);
2420 // slow path use klass prototype
2421 push(rscratch1);
2422 load_prototype_header(temp_reg, oop, rscratch1);
2423 pop(rscratch1);
2424
2425 bind(test_mark_word);
2426 testl(temp_reg, test_bit);
2427 jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
2428 }
2429
2430 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg,
2431 Label& is_flat_array) {
2432 #ifdef _LP64
2433 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2434 #else
2435 load_klass(temp_reg, oop, noreg);
2436 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
2437 test_flat_array_layout(temp_reg, is_flat_array);
2438 #endif
2439 }
2440
2441 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2442 Label& is_non_flat_array) {
2443 #ifdef _LP64
2444 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2445 #else
2446 load_klass(temp_reg, oop, noreg);
2447 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
2448 test_non_flat_array_layout(temp_reg, is_non_flat_array);
2449 #endif
2450 }
2451
2452 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
2453 #ifdef _LP64
2454 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2455 #else
2456 Unimplemented();
2457 #endif
2458 }
2459
2460 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2461 #ifdef _LP64
2462 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2463 #else
2464 Unimplemented();
2465 #endif
2466 }
2467
2468 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2469 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2470 jcc(Assembler::notZero, is_flat_array);
2471 }
2472
2473 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
2474 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2475 jcc(Assembler::zero, is_non_flat_array);
2476 }
2477
2478 void MacroAssembler::os_breakpoint() {
2479 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2480 // (e.g., MSVC can't call ps() otherwise)
2481 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2482 }
2483
2484 void MacroAssembler::unimplemented(const char* what) {
2485 const char* buf = nullptr;
2486 {
2487 ResourceMark rm;
2488 stringStream ss;
2489 ss.print("unimplemented: %s", what);
2490 buf = code_string(ss.as_string());
2491 }
2492 stop(buf);
2493 }
2494
2495 #define XSTATE_BV 0x200
2496
2497 void MacroAssembler::pop_CPU_state() {
2498 pop_FPU_state();
2499 pop_IU_state();
2500 }
2501
2502 void MacroAssembler::pop_FPU_state() {
2503 fxrstor(Address(rsp, 0));
2504 addptr(rsp, FPUStateSizeInWords * wordSize);
2505 }
2506
2507 void MacroAssembler::pop_IU_state() {
2508 popa();
2509 addq(rsp, 8);
2510 popf();
2511 }
2512
2513 // Save Integer and Float state
2514 // Warning: Stack must be 16 byte aligned (64bit)
2515 void MacroAssembler::push_CPU_state() {
2516 push_IU_state();
2517 push_FPU_state();
2518 }
2519
2520 void MacroAssembler::push_FPU_state() {
2521 subptr(rsp, FPUStateSizeInWords * wordSize);
2522 fxsave(Address(rsp, 0));
2523 }
2524
2525 void MacroAssembler::push_IU_state() {
2526 // Push flags first because pusha kills them
2527 pushf();
2528 // Make sure rsp stays 16-byte aligned
2529 subq(rsp, 8);
2530 pusha();
2531 }
2532
2533 void MacroAssembler::push_cont_fastpath() {
2534 if (!Continuations::enabled()) return;
2535
2536 Label L_done;
2537 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2538 jccb(Assembler::belowEqual, L_done);
2539 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), rsp);
2540 bind(L_done);
2541 }
2542
2543 void MacroAssembler::pop_cont_fastpath() {
2544 if (!Continuations::enabled()) return;
2545
2546 Label L_done;
2547 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2548 jccb(Assembler::below, L_done);
2549 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), 0);
2550 bind(L_done);
2551 }
2552
2553 #ifdef ASSERT
2554 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2555 Label no_cont;
2556 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2557 testl(cont, cont);
2558 jcc(Assembler::zero, no_cont);
2559 stop(name);
2560 bind(no_cont);
2561 }
2562 #endif
2563
2564 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { // determine java_thread register
2565 // we must set sp to zero to clear frame
2566 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2567 // must clear fp, so that compiled frames are not confused; it is
2568 // possible that we need it only for debugging
2569 if (clear_fp) {
2570 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2571 }
2572 // Always clear the pc because it could have been set by make_walkable()
2573 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2574 vzeroupper();
2575 }
2576
2577 void MacroAssembler::round_to(Register reg, int modulus) {
2578 addptr(reg, modulus - 1);
2579 andptr(reg, -modulus);
2580 }
2581
2582 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod) {
2583 if (at_return) {
2584 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2585 // we may safely use rsp instead to perform the stack watermark check.
2586 cmpptr(in_nmethod ? rsp : rbp, Address(r15_thread, JavaThread::polling_word_offset()));
2587 jcc(Assembler::above, slow_path);
2588 return;
2589 }
2590 testb(Address(r15_thread, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2591 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2592 }
2593
2594 // Calls to C land
2595 //
2596 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2597 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2598 // has to be reset to 0. This is required to allow proper stack traversal.
2599 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2600 Register last_java_fp,
2601 address last_java_pc,
2602 Register rscratch) {
2603 vzeroupper();
2604 // determine last_java_sp register
2605 if (!last_java_sp->is_valid()) {
2606 last_java_sp = rsp;
2607 }
2608 // last_java_fp is optional
2609 if (last_java_fp->is_valid()) {
2610 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2611 }
2612 // last_java_pc is optional
2613 if (last_java_pc != nullptr) {
2614 Address java_pc(r15_thread,
2615 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
2616 lea(java_pc, InternalAddress(last_java_pc), rscratch);
2617 }
2618 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2619 }
2620
2621 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2622 Register last_java_fp,
2623 Label &L,
2624 Register scratch) {
2625 lea(scratch, L);
2626 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
2627 set_last_Java_frame(last_java_sp, last_java_fp, nullptr, scratch);
2628 }
2629
2630 void MacroAssembler::shlptr(Register dst, int imm8) {
2631 shlq(dst, imm8);
2632 }
2633
2634 void MacroAssembler::shrptr(Register dst, int imm8) {
2635 shrq(dst, imm8);
2636 }
2637
2638 void MacroAssembler::sign_extend_byte(Register reg) {
2639 movsbl(reg, reg); // movsxb
2640 }
2641
2642 void MacroAssembler::sign_extend_short(Register reg) {
2643 movswl(reg, reg); // movsxw
2644 }
2645
2646 void MacroAssembler::testl(Address dst, int32_t imm32) {
2647 if (imm32 >= 0 && is8bit(imm32)) {
2648 testb(dst, imm32);
2649 } else {
2650 Assembler::testl(dst, imm32);
2651 }
2652 }
2653
2654 void MacroAssembler::testl(Register dst, int32_t imm32) {
2655 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
2656 testb(dst, imm32);
2657 } else {
2658 Assembler::testl(dst, imm32);
2659 }
2660 }
2661
2662 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2663 assert(always_reachable(src), "Address should be reachable");
2664 testl(dst, as_Address(src));
2665 }
2666
2667 void MacroAssembler::testq(Address dst, int32_t imm32) {
2668 if (imm32 >= 0) {
2669 testl(dst, imm32);
2670 } else {
2671 Assembler::testq(dst, imm32);
2672 }
2673 }
2674
2675 void MacroAssembler::testq(Register dst, int32_t imm32) {
2676 if (imm32 >= 0) {
2677 testl(dst, imm32);
2678 } else {
2679 Assembler::testq(dst, imm32);
2680 }
2681 }
2682
2683 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2684 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2685 Assembler::pcmpeqb(dst, src);
2686 }
2687
2688 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2689 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2690 Assembler::pcmpeqw(dst, src);
2691 }
2692
2693 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2694 assert((dst->encoding() < 16),"XMM register should be 0-15");
2695 Assembler::pcmpestri(dst, src, imm8);
2696 }
2697
2698 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2699 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2700 Assembler::pcmpestri(dst, src, imm8);
2701 }
2702
2703 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2704 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2705 Assembler::pmovzxbw(dst, src);
2706 }
2707
2708 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2709 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2710 Assembler::pmovzxbw(dst, src);
2711 }
2712
2713 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2714 assert((src->encoding() < 16),"XMM register should be 0-15");
2715 Assembler::pmovmskb(dst, src);
2716 }
2717
2718 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2719 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2720 Assembler::ptest(dst, src);
2721 }
2722
2723 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2724 assert(rscratch != noreg || always_reachable(src), "missing");
2725
2726 if (reachable(src)) {
2727 Assembler::sqrtss(dst, as_Address(src));
2728 } else {
2729 lea(rscratch, src);
2730 Assembler::sqrtss(dst, Address(rscratch, 0));
2731 }
2732 }
2733
2734 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2735 assert(rscratch != noreg || always_reachable(src), "missing");
2736
2737 if (reachable(src)) {
2738 Assembler::subsd(dst, as_Address(src));
2739 } else {
2740 lea(rscratch, src);
2741 Assembler::subsd(dst, Address(rscratch, 0));
2742 }
2743 }
2744
2745 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
2746 assert(rscratch != noreg || always_reachable(src), "missing");
2747
2748 if (reachable(src)) {
2749 Assembler::roundsd(dst, as_Address(src), rmode);
2750 } else {
2751 lea(rscratch, src);
2752 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
2753 }
2754 }
2755
2756 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2757 assert(rscratch != noreg || always_reachable(src), "missing");
2758
2759 if (reachable(src)) {
2760 Assembler::subss(dst, as_Address(src));
2761 } else {
2762 lea(rscratch, src);
2763 Assembler::subss(dst, Address(rscratch, 0));
2764 }
2765 }
2766
2767 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2768 assert(rscratch != noreg || always_reachable(src), "missing");
2769
2770 if (reachable(src)) {
2771 Assembler::ucomisd(dst, as_Address(src));
2772 } else {
2773 lea(rscratch, src);
2774 Assembler::ucomisd(dst, Address(rscratch, 0));
2775 }
2776 }
2777
2778 void MacroAssembler::vucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2779 assert(rscratch != noreg || always_reachable(src), "missing");
2780
2781 if (reachable(src)) {
2782 Assembler::vucomxsd(dst, as_Address(src));
2783 } else {
2784 lea(rscratch, src);
2785 Assembler::vucomxsd(dst, Address(rscratch, 0));
2786 }
2787 }
2788
2789 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2790 assert(rscratch != noreg || always_reachable(src), "missing");
2791
2792 if (reachable(src)) {
2793 Assembler::ucomiss(dst, as_Address(src));
2794 } else {
2795 lea(rscratch, src);
2796 Assembler::ucomiss(dst, Address(rscratch, 0));
2797 }
2798 }
2799
2800 void MacroAssembler::vucomxss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2801 assert(rscratch != noreg || always_reachable(src), "missing");
2802
2803 if (reachable(src)) {
2804 Assembler::vucomxss(dst, as_Address(src));
2805 } else {
2806 lea(rscratch, src);
2807 Assembler::vucomxss(dst, Address(rscratch, 0));
2808 }
2809 }
2810
2811 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2812 assert(rscratch != noreg || always_reachable(src), "missing");
2813
2814 // Used in sign-bit flipping with aligned address.
2815 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2816
2817 if (UseAVX > 2 &&
2818 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2819 (dst->encoding() >= 16)) {
2820 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2821 } else if (reachable(src)) {
2822 Assembler::xorpd(dst, as_Address(src));
2823 } else {
2824 lea(rscratch, src);
2825 Assembler::xorpd(dst, Address(rscratch, 0));
2826 }
2827 }
2828
2829 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
2830 if (UseAVX > 2 &&
2831 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2832 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2833 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2834 } else {
2835 Assembler::xorpd(dst, src);
2836 }
2837 }
2838
2839 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
2840 if (UseAVX > 2 &&
2841 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2842 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2843 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2844 } else {
2845 Assembler::xorps(dst, src);
2846 }
2847 }
2848
2849 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
2850 assert(rscratch != noreg || always_reachable(src), "missing");
2851
2852 // Used in sign-bit flipping with aligned address.
2853 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2854
2855 if (UseAVX > 2 &&
2856 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2857 (dst->encoding() >= 16)) {
2858 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2859 } else if (reachable(src)) {
2860 Assembler::xorps(dst, as_Address(src));
2861 } else {
2862 lea(rscratch, src);
2863 Assembler::xorps(dst, Address(rscratch, 0));
2864 }
2865 }
2866
2867 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
2868 assert(rscratch != noreg || always_reachable(src), "missing");
2869
2870 // Used in sign-bit flipping with aligned address.
2871 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
2872 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2873 if (reachable(src)) {
2874 Assembler::pshufb(dst, as_Address(src));
2875 } else {
2876 lea(rscratch, src);
2877 Assembler::pshufb(dst, Address(rscratch, 0));
2878 }
2879 }
2880
2881 // AVX 3-operands instructions
2882
2883 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2884 assert(rscratch != noreg || always_reachable(src), "missing");
2885
2886 if (reachable(src)) {
2887 vaddsd(dst, nds, as_Address(src));
2888 } else {
2889 lea(rscratch, src);
2890 vaddsd(dst, nds, Address(rscratch, 0));
2891 }
2892 }
2893
2894 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2895 assert(rscratch != noreg || always_reachable(src), "missing");
2896
2897 if (reachable(src)) {
2898 vaddss(dst, nds, as_Address(src));
2899 } else {
2900 lea(rscratch, src);
2901 vaddss(dst, nds, Address(rscratch, 0));
2902 }
2903 }
2904
2905 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2906 assert(UseAVX > 0, "requires some form of AVX");
2907 assert(rscratch != noreg || always_reachable(src), "missing");
2908
2909 if (reachable(src)) {
2910 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
2911 } else {
2912 lea(rscratch, src);
2913 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
2914 }
2915 }
2916
2917 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2918 assert(UseAVX > 0, "requires some form of AVX");
2919 assert(rscratch != noreg || always_reachable(src), "missing");
2920
2921 if (reachable(src)) {
2922 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
2923 } else {
2924 lea(rscratch, src);
2925 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
2926 }
2927 }
2928
2929 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2930 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2931 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2932
2933 vandps(dst, nds, negate_field, vector_len, rscratch);
2934 }
2935
2936 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2937 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2938 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2939
2940 vandpd(dst, nds, negate_field, vector_len, rscratch);
2941 }
2942
2943 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2944 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2945 Assembler::vpaddb(dst, nds, src, vector_len);
2946 }
2947
2948 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2949 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2950 Assembler::vpaddb(dst, nds, src, vector_len);
2951 }
2952
2953 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2954 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2955 Assembler::vpaddw(dst, nds, src, vector_len);
2956 }
2957
2958 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2959 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2960 Assembler::vpaddw(dst, nds, src, vector_len);
2961 }
2962
2963 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2964 assert(rscratch != noreg || always_reachable(src), "missing");
2965
2966 if (reachable(src)) {
2967 Assembler::vpand(dst, nds, as_Address(src), vector_len);
2968 } else {
2969 lea(rscratch, src);
2970 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
2971 }
2972 }
2973
2974 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2975 assert(rscratch != noreg || always_reachable(src), "missing");
2976
2977 if (reachable(src)) {
2978 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
2979 } else {
2980 lea(rscratch, src);
2981 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
2982 }
2983 }
2984
2985 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2986 assert(rscratch != noreg || always_reachable(src), "missing");
2987
2988 if (reachable(src)) {
2989 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
2990 } else {
2991 lea(rscratch, src);
2992 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
2993 }
2994 }
2995
2996 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2997 assert(rscratch != noreg || always_reachable(src), "missing");
2998
2999 if (reachable(src)) {
3000 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3001 } else {
3002 lea(rscratch, src);
3003 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3004 }
3005 }
3006
3007 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3008 assert(rscratch != noreg || always_reachable(src), "missing");
3009
3010 if (reachable(src)) {
3011 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3012 } else {
3013 lea(rscratch, src);
3014 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3015 }
3016 }
3017
3018 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3019 assert(rscratch != noreg || always_reachable(src), "missing");
3020
3021 if (reachable(src)) {
3022 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3023 } else {
3024 lea(rscratch, src);
3025 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3026 }
3027 }
3028
3029 // Vector float blend
3030 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3031 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3032 // WARN: Allow dst == (src1|src2), mask == scratch
3033 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3034 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3035 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3036 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3037 if (blend_emulation && scratch_available && dst_available) {
3038 if (compute_mask) {
3039 vpsrad(scratch, mask, 32, vector_len);
3040 mask = scratch;
3041 }
3042 if (dst == src1) {
3043 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3044 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3045 } else {
3046 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3047 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3048 }
3049 vpor(dst, dst, scratch, vector_len);
3050 } else {
3051 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3052 }
3053 }
3054
3055 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3056 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3057 // WARN: Allow dst == (src1|src2), mask == scratch
3058 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3059 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3060 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3061 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3062 if (blend_emulation && scratch_available && dst_available) {
3063 if (compute_mask) {
3064 vpxor(scratch, scratch, scratch, vector_len);
3065 vpcmpgtq(scratch, scratch, mask, vector_len);
3066 mask = scratch;
3067 }
3068 if (dst == src1) {
3069 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3070 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3071 } else {
3072 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3073 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3074 }
3075 vpor(dst, dst, scratch, vector_len);
3076 } else {
3077 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3078 }
3079 }
3080
3081 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3082 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3083 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3084 }
3085
3086 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3087 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3088 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3089 }
3090
3091 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3092 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3093 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3094 }
3095
3096 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3097 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3098 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3099 }
3100
3101 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3102 assert(rscratch != noreg || always_reachable(src), "missing");
3103
3104 if (reachable(src)) {
3105 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3106 } else {
3107 lea(rscratch, src);
3108 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3109 }
3110 }
3111
3112 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3113 int comparison, bool is_signed, int vector_len, Register rscratch) {
3114 assert(rscratch != noreg || always_reachable(src), "missing");
3115
3116 if (reachable(src)) {
3117 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3118 } else {
3119 lea(rscratch, src);
3120 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3121 }
3122 }
3123
3124 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3125 int comparison, bool is_signed, int vector_len, Register rscratch) {
3126 assert(rscratch != noreg || always_reachable(src), "missing");
3127
3128 if (reachable(src)) {
3129 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3130 } else {
3131 lea(rscratch, src);
3132 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3133 }
3134 }
3135
3136 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3137 int comparison, bool is_signed, int vector_len, Register rscratch) {
3138 assert(rscratch != noreg || always_reachable(src), "missing");
3139
3140 if (reachable(src)) {
3141 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3142 } else {
3143 lea(rscratch, src);
3144 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3145 }
3146 }
3147
3148 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3149 int comparison, bool is_signed, int vector_len, Register rscratch) {
3150 assert(rscratch != noreg || always_reachable(src), "missing");
3151
3152 if (reachable(src)) {
3153 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3154 } else {
3155 lea(rscratch, src);
3156 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3157 }
3158 }
3159
3160 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3161 if (width == Assembler::Q) {
3162 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3163 } else {
3164 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3165 }
3166 }
3167
3168 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3169 int eq_cond_enc = 0x29;
3170 int gt_cond_enc = 0x37;
3171 if (width != Assembler::Q) {
3172 eq_cond_enc = 0x74 + width;
3173 gt_cond_enc = 0x64 + width;
3174 }
3175 switch (cond) {
3176 case eq:
3177 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3178 break;
3179 case neq:
3180 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3181 vallones(xtmp, vector_len);
3182 vpxor(dst, xtmp, dst, vector_len);
3183 break;
3184 case le:
3185 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3186 vallones(xtmp, vector_len);
3187 vpxor(dst, xtmp, dst, vector_len);
3188 break;
3189 case nlt:
3190 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3191 vallones(xtmp, vector_len);
3192 vpxor(dst, xtmp, dst, vector_len);
3193 break;
3194 case lt:
3195 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3196 break;
3197 case nle:
3198 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3199 break;
3200 default:
3201 assert(false, "Should not reach here");
3202 }
3203 }
3204
3205 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3206 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3207 Assembler::vpmovzxbw(dst, src, vector_len);
3208 }
3209
3210 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3211 assert((src->encoding() < 16),"XMM register should be 0-15");
3212 Assembler::vpmovmskb(dst, src, vector_len);
3213 }
3214
3215 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3216 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3217 Assembler::vpmullw(dst, nds, src, vector_len);
3218 }
3219
3220 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3221 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3222 Assembler::vpmullw(dst, nds, src, vector_len);
3223 }
3224
3225 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3226 assert((UseAVX > 0), "AVX support is needed");
3227 assert(rscratch != noreg || always_reachable(src), "missing");
3228
3229 if (reachable(src)) {
3230 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3231 } else {
3232 lea(rscratch, src);
3233 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3234 }
3235 }
3236
3237 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3238 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3239 Assembler::vpsubb(dst, nds, src, vector_len);
3240 }
3241
3242 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3243 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3244 Assembler::vpsubb(dst, nds, src, vector_len);
3245 }
3246
3247 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3248 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3249 Assembler::vpsubw(dst, nds, src, vector_len);
3250 }
3251
3252 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3253 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3254 Assembler::vpsubw(dst, nds, src, vector_len);
3255 }
3256
3257 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3258 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3259 Assembler::vpsraw(dst, nds, shift, vector_len);
3260 }
3261
3262 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3263 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3264 Assembler::vpsraw(dst, nds, shift, vector_len);
3265 }
3266
3267 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3268 assert(UseAVX > 2,"");
3269 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3270 vector_len = 2;
3271 }
3272 Assembler::evpsraq(dst, nds, shift, vector_len);
3273 }
3274
3275 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3276 assert(UseAVX > 2,"");
3277 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3278 vector_len = 2;
3279 }
3280 Assembler::evpsraq(dst, nds, shift, vector_len);
3281 }
3282
3283 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3284 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3285 Assembler::vpsrlw(dst, nds, shift, vector_len);
3286 }
3287
3288 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3289 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3290 Assembler::vpsrlw(dst, nds, shift, vector_len);
3291 }
3292
3293 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3294 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3295 Assembler::vpsllw(dst, nds, shift, vector_len);
3296 }
3297
3298 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3299 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3300 Assembler::vpsllw(dst, nds, shift, vector_len);
3301 }
3302
3303 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3304 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3305 Assembler::vptest(dst, src);
3306 }
3307
3308 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3309 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3310 Assembler::punpcklbw(dst, src);
3311 }
3312
3313 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3314 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3315 Assembler::pshufd(dst, src, mode);
3316 }
3317
3318 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3319 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3320 Assembler::pshuflw(dst, src, mode);
3321 }
3322
3323 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3324 assert(rscratch != noreg || always_reachable(src), "missing");
3325
3326 if (reachable(src)) {
3327 vandpd(dst, nds, as_Address(src), vector_len);
3328 } else {
3329 lea(rscratch, src);
3330 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3331 }
3332 }
3333
3334 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3335 assert(rscratch != noreg || always_reachable(src), "missing");
3336
3337 if (reachable(src)) {
3338 vandps(dst, nds, as_Address(src), vector_len);
3339 } else {
3340 lea(rscratch, src);
3341 vandps(dst, nds, Address(rscratch, 0), vector_len);
3342 }
3343 }
3344
3345 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3346 bool merge, int vector_len, Register rscratch) {
3347 assert(rscratch != noreg || always_reachable(src), "missing");
3348
3349 if (reachable(src)) {
3350 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3351 } else {
3352 lea(rscratch, src);
3353 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3354 }
3355 }
3356
3357 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3358 assert(rscratch != noreg || always_reachable(src), "missing");
3359
3360 if (reachable(src)) {
3361 vdivsd(dst, nds, as_Address(src));
3362 } else {
3363 lea(rscratch, src);
3364 vdivsd(dst, nds, Address(rscratch, 0));
3365 }
3366 }
3367
3368 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3369 assert(rscratch != noreg || always_reachable(src), "missing");
3370
3371 if (reachable(src)) {
3372 vdivss(dst, nds, as_Address(src));
3373 } else {
3374 lea(rscratch, src);
3375 vdivss(dst, nds, Address(rscratch, 0));
3376 }
3377 }
3378
3379 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3380 assert(rscratch != noreg || always_reachable(src), "missing");
3381
3382 if (reachable(src)) {
3383 vmulsd(dst, nds, as_Address(src));
3384 } else {
3385 lea(rscratch, src);
3386 vmulsd(dst, nds, Address(rscratch, 0));
3387 }
3388 }
3389
3390 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3391 assert(rscratch != noreg || always_reachable(src), "missing");
3392
3393 if (reachable(src)) {
3394 vmulss(dst, nds, as_Address(src));
3395 } else {
3396 lea(rscratch, src);
3397 vmulss(dst, nds, Address(rscratch, 0));
3398 }
3399 }
3400
3401 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3402 assert(rscratch != noreg || always_reachable(src), "missing");
3403
3404 if (reachable(src)) {
3405 vsubsd(dst, nds, as_Address(src));
3406 } else {
3407 lea(rscratch, src);
3408 vsubsd(dst, nds, Address(rscratch, 0));
3409 }
3410 }
3411
3412 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3413 assert(rscratch != noreg || always_reachable(src), "missing");
3414
3415 if (reachable(src)) {
3416 vsubss(dst, nds, as_Address(src));
3417 } else {
3418 lea(rscratch, src);
3419 vsubss(dst, nds, Address(rscratch, 0));
3420 }
3421 }
3422
3423 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3424 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3425 assert(rscratch != noreg || always_reachable(src), "missing");
3426
3427 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3428 }
3429
3430 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3431 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3432 assert(rscratch != noreg || always_reachable(src), "missing");
3433
3434 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3435 }
3436
3437 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3438 assert(rscratch != noreg || always_reachable(src), "missing");
3439
3440 if (reachable(src)) {
3441 vxorpd(dst, nds, as_Address(src), vector_len);
3442 } else {
3443 lea(rscratch, src);
3444 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3445 }
3446 }
3447
3448 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3449 assert(rscratch != noreg || always_reachable(src), "missing");
3450
3451 if (reachable(src)) {
3452 vxorps(dst, nds, as_Address(src), vector_len);
3453 } else {
3454 lea(rscratch, src);
3455 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3456 }
3457 }
3458
3459 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3460 assert(rscratch != noreg || always_reachable(src), "missing");
3461
3462 if (UseAVX > 1 || (vector_len < 1)) {
3463 if (reachable(src)) {
3464 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3465 } else {
3466 lea(rscratch, src);
3467 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3468 }
3469 } else {
3470 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3471 }
3472 }
3473
3474 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3475 assert(rscratch != noreg || always_reachable(src), "missing");
3476
3477 if (reachable(src)) {
3478 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3479 } else {
3480 lea(rscratch, src);
3481 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3482 }
3483 }
3484
3485 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3486 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3487 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3488 // The inverted mask is sign-extended
3489 andptr(possibly_non_local, inverted_mask);
3490 }
3491
3492 void MacroAssembler::resolve_jobject(Register value,
3493 Register tmp) {
3494 Register thread = r15_thread;
3495 assert_different_registers(value, thread, tmp);
3496 Label done, tagged, weak_tagged;
3497 testptr(value, value);
3498 jcc(Assembler::zero, done); // Use null as-is.
3499 testptr(value, JNIHandles::tag_mask); // Test for tag.
3500 jcc(Assembler::notZero, tagged);
3501
3502 // Resolve local handle
3503 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp);
3504 verify_oop(value);
3505 jmp(done);
3506
3507 bind(tagged);
3508 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3509 jcc(Assembler::notZero, weak_tagged);
3510
3511 // Resolve global handle
3512 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3513 verify_oop(value);
3514 jmp(done);
3515
3516 bind(weak_tagged);
3517 // Resolve jweak.
3518 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3519 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp);
3520 verify_oop(value);
3521
3522 bind(done);
3523 }
3524
3525 void MacroAssembler::resolve_global_jobject(Register value,
3526 Register tmp) {
3527 Register thread = r15_thread;
3528 assert_different_registers(value, thread, tmp);
3529 Label done;
3530
3531 testptr(value, value);
3532 jcc(Assembler::zero, done); // Use null as-is.
3533
3534 #ifdef ASSERT
3535 {
3536 Label valid_global_tag;
3537 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
3538 jcc(Assembler::notZero, valid_global_tag);
3539 stop("non global jobject using resolve_global_jobject");
3540 bind(valid_global_tag);
3541 }
3542 #endif
3543
3544 // Resolve global handle
3545 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3546 verify_oop(value);
3547
3548 bind(done);
3549 }
3550
3551 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3552 subq(dst, imm32);
3553 }
3554
3555 // Force generation of a 4 byte immediate value even if it fits into 8bit
3556 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3557 subq_imm32(dst, imm32);
3558 }
3559
3560 void MacroAssembler::subptr(Register dst, Register src) {
3561 subq(dst, src);
3562 }
3563
3564 // C++ bool manipulation
3565 void MacroAssembler::testbool(Register dst) {
3566 if(sizeof(bool) == 1)
3567 testb(dst, 0xff);
3568 else if(sizeof(bool) == 2) {
3569 // testw implementation needed for two byte bools
3570 ShouldNotReachHere();
3571 } else if(sizeof(bool) == 4)
3572 testl(dst, dst);
3573 else
3574 // unsupported
3575 ShouldNotReachHere();
3576 }
3577
3578 void MacroAssembler::testptr(Register dst, Register src) {
3579 testq(dst, src);
3580 }
3581
3582 // Object / value buffer allocation...
3583 //
3584 // Kills klass and rsi on LP64
3585 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
3586 Register t1, Register t2,
3587 bool clear_fields, Label& alloc_failed)
3588 {
3589 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
3590 Register layout_size = t1;
3591 assert(new_obj == rax, "needs to be rax");
3592 assert_different_registers(klass, new_obj, t1, t2);
3593
3594 // get instance_size in InstanceKlass (scaled to a count of bytes)
3595 movl(layout_size, Address(klass, Klass::layout_helper_offset()));
3596 // test to see if it is malformed in some way
3597 testl(layout_size, Klass::_lh_instance_slow_path_bit);
3598 jcc(Assembler::notZero, slow_case_no_pop);
3599
3600 // Allocate the instance:
3601 // If TLAB is enabled:
3602 // Try to allocate in the TLAB.
3603 // If fails, go to the slow path.
3604 // Else If inline contiguous allocations are enabled:
3605 // Try to allocate in eden.
3606 // If fails due to heap end, go to slow path.
3607 //
3608 // If TLAB is enabled OR inline contiguous is enabled:
3609 // Initialize the allocation.
3610 // Exit.
3611 //
3612 // Go to slow path.
3613
3614 push(klass);
3615 if (UseTLAB) {
3616 tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case);
3617 if (ZeroTLAB || (!clear_fields)) {
3618 // the fields have been already cleared
3619 jmp(initialize_header);
3620 } else {
3621 // initialize both the header and fields
3622 jmp(initialize_object);
3623 }
3624 } else {
3625 jmp(slow_case);
3626 }
3627
3628 // If UseTLAB is true, the object is created above and there is an initialize need.
3629 // Otherwise, skip and go to the slow path.
3630 if (UseTLAB) {
3631 if (clear_fields) {
3632 // The object is initialized before the header. If the object size is
3633 // zero, go directly to the header initialization.
3634 bind(initialize_object);
3635 if (UseCompactObjectHeaders) {
3636 assert(is_aligned(oopDesc::base_offset_in_bytes(), BytesPerLong), "oop base offset must be 8-byte-aligned");
3637 decrement(layout_size, oopDesc::base_offset_in_bytes());
3638 } else {
3639 decrement(layout_size, sizeof(oopDesc));
3640 }
3641 jcc(Assembler::zero, initialize_header);
3642
3643 // Initialize topmost object field, divide size by 8, check if odd and
3644 // test if zero.
3645 Register zero = klass;
3646 xorl(zero, zero); // use zero reg to clear memory (shorter code)
3647 shrl(layout_size, LogBytesPerLong); // divide by 2*oopSize and set carry flag if odd
3648
3649 #ifdef ASSERT
3650 // make sure instance_size was multiple of 8
3651 Label L;
3652 // Ignore partial flag stall after shrl() since it is debug VM
3653 jcc(Assembler::carryClear, L);
3654 stop("object size is not multiple of 2 - adjust this code");
3655 bind(L);
3656 // must be > 0, no extra check needed here
3657 #endif
3658
3659 // initialize remaining object fields: instance_size was a multiple of 8
3660 {
3661 Label loop;
3662 bind(loop);
3663 int header_size_bytes = oopDesc::header_size() * HeapWordSize;
3664 assert(is_aligned(header_size_bytes, BytesPerLong), "oop header size must be 8-byte-aligned");
3665 movptr(Address(new_obj, layout_size, Address::times_8, header_size_bytes - 1*oopSize), zero);
3666 decrement(layout_size);
3667 jcc(Assembler::notZero, loop);
3668 }
3669 } // clear_fields
3670
3671 // initialize object header only.
3672 bind(initialize_header);
3673 if (UseCompactObjectHeaders || Arguments::is_valhalla_enabled()) {
3674 pop(klass);
3675 Register mark_word = t2;
3676 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
3677 movptr(Address(new_obj, oopDesc::mark_offset_in_bytes ()), mark_word);
3678 } else {
3679 movptr(Address(new_obj, oopDesc::mark_offset_in_bytes()),
3680 (intptr_t)markWord::prototype().value()); // header
3681 pop(klass); // get saved klass back in the register.
3682 }
3683 if (!UseCompactObjectHeaders) {
3684 xorl(rsi, rsi); // use zero reg to clear memory (shorter code)
3685 store_klass_gap(new_obj, rsi); // zero klass gap for compressed oops
3686 movptr(t2, klass); // preserve klass
3687 store_klass(new_obj, t2, rscratch1); // src klass reg is potentially compressed
3688 }
3689 jmp(done);
3690 }
3691
3692 bind(slow_case);
3693 pop(klass);
3694 bind(slow_case_no_pop);
3695 jmp(alloc_failed);
3696
3697 bind(done);
3698 }
3699
3700 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3701 void MacroAssembler::tlab_allocate(Register obj,
3702 Register var_size_in_bytes,
3703 int con_size_in_bytes,
3704 Register t1,
3705 Register t2,
3706 Label& slow_case) {
3707 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3708 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3709 }
3710
3711 RegSet MacroAssembler::call_clobbered_gp_registers() {
3712 RegSet regs;
3713 regs += RegSet::of(rax, rcx, rdx);
3714 #ifndef _WINDOWS
3715 regs += RegSet::of(rsi, rdi);
3716 #endif
3717 regs += RegSet::range(r8, r11);
3718 if (UseAPX) {
3719 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
3720 }
3721 return regs;
3722 }
3723
3724 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3725 int num_xmm_registers = XMMRegister::available_xmm_registers();
3726 #if defined(_WINDOWS)
3727 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3728 if (num_xmm_registers > 16) {
3729 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3730 }
3731 return result;
3732 #else
3733 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3734 #endif
3735 }
3736
3737 // C1 only ever uses the first double/float of the XMM register.
3738 static int xmm_save_size() { return sizeof(double); }
3739
3740 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3741 masm->movdbl(Address(rsp, offset), reg);
3742 }
3743
3744 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3745 masm->movdbl(reg, Address(rsp, offset));
3746 }
3747
3748 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
3749 bool save_fpu, int& gp_area_size, int& xmm_area_size) {
3750
3751 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
3752 StackAlignmentInBytes);
3753 xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
3754
3755 return gp_area_size + xmm_area_size;
3756 }
3757
3758 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3759 block_comment("push_call_clobbered_registers start");
3760 // Regular registers
3761 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3762
3763 int gp_area_size;
3764 int xmm_area_size;
3765 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3766 gp_area_size, xmm_area_size);
3767 subptr(rsp, total_save_size);
3768
3769 push_set(gp_registers_to_push, 0);
3770
3771 if (save_fpu) {
3772 push_set(call_clobbered_xmm_registers(), gp_area_size);
3773 }
3774
3775 block_comment("push_call_clobbered_registers end");
3776 }
3777
3778 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3779 block_comment("pop_call_clobbered_registers start");
3780
3781 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3782
3783 int gp_area_size;
3784 int xmm_area_size;
3785 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3786 gp_area_size, xmm_area_size);
3787
3788 if (restore_fpu) {
3789 pop_set(call_clobbered_xmm_registers(), gp_area_size);
3790 }
3791
3792 pop_set(gp_registers_to_pop, 0);
3793
3794 addptr(rsp, total_save_size);
3795
3796 vzeroupper();
3797
3798 block_comment("pop_call_clobbered_registers end");
3799 }
3800
3801 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3802 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3803 int spill_offset = offset;
3804
3805 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3806 save_xmm_register(this, spill_offset, *it);
3807 spill_offset += xmm_save_size();
3808 }
3809 }
3810
3811 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3812 int restore_size = set.size() * xmm_save_size();
3813 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3814
3815 int restore_offset = offset + restore_size - xmm_save_size();
3816
3817 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3818 restore_xmm_register(this, restore_offset, *it);
3819 restore_offset -= xmm_save_size();
3820 }
3821 }
3822
3823 void MacroAssembler::push_set(RegSet set, int offset) {
3824 int spill_offset;
3825 if (offset == -1) {
3826 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3827 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3828 subptr(rsp, aligned_size);
3829 spill_offset = 0;
3830 } else {
3831 spill_offset = offset;
3832 }
3833
3834 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3835 movptr(Address(rsp, spill_offset), *it);
3836 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3837 }
3838 }
3839
3840 void MacroAssembler::pop_set(RegSet set, int offset) {
3841
3842 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3843 int restore_size = set.size() * gp_reg_size;
3844 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3845
3846 int restore_offset;
3847 if (offset == -1) {
3848 restore_offset = restore_size - gp_reg_size;
3849 } else {
3850 restore_offset = offset + restore_size - gp_reg_size;
3851 }
3852 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3853 movptr(*it, Address(rsp, restore_offset));
3854 restore_offset -= gp_reg_size;
3855 }
3856
3857 if (offset == -1) {
3858 addptr(rsp, aligned_size);
3859 }
3860 }
3861
3862 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3863 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3864 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3865 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3866 Label done;
3867
3868 testptr(length_in_bytes, length_in_bytes);
3869 jcc(Assembler::zero, done);
3870
3871 // initialize topmost word, divide index by 2, check if odd and test if zero
3872 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3873 #ifdef ASSERT
3874 {
3875 Label L;
3876 testptr(length_in_bytes, BytesPerWord - 1);
3877 jcc(Assembler::zero, L);
3878 stop("length must be a multiple of BytesPerWord");
3879 bind(L);
3880 }
3881 #endif
3882 Register index = length_in_bytes;
3883 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3884 if (UseIncDec) {
3885 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3886 } else {
3887 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3888 shrptr(index, 1);
3889 }
3890
3891 // initialize remaining object fields: index is a multiple of 2 now
3892 {
3893 Label loop;
3894 bind(loop);
3895 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3896 decrement(index);
3897 jcc(Assembler::notZero, loop);
3898 }
3899
3900 bind(done);
3901 }
3902
3903 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
3904 movptr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
3905 #ifdef ASSERT
3906 {
3907 Label done;
3908 cmpptr(layout_info, 0);
3909 jcc(Assembler::notEqual, done);
3910 stop("inline_layout_info_array is null");
3911 bind(done);
3912 }
3913 #endif
3914
3915 InlineLayoutInfo array[2];
3916 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
3917 if (is_power_of_2(size)) {
3918 shll(index, log2i_exact(size)); // Scale index by power of 2
3919 } else {
3920 imull(index, index, size); // Scale the index to be the entry index * array_element_size
3921 }
3922 lea(layout_info, Address(layout_info, index, Address::times_1, Array<InlineLayoutInfo>::base_offset_in_bytes()));
3923 }
3924
3925 // Look up the method for a megamorphic invokeinterface call.
3926 // The target method is determined by <intf_klass, itable_index>.
3927 // The receiver klass is in recv_klass.
3928 // On success, the result will be in method_result, and execution falls through.
3929 // On failure, execution transfers to the given label.
3930 void MacroAssembler::lookup_interface_method(Register recv_klass,
3931 Register intf_klass,
3932 RegisterOrConstant itable_index,
3933 Register method_result,
3934 Register scan_temp,
3935 Label& L_no_such_interface,
3936 bool return_method) {
3937 assert_different_registers(recv_klass, intf_klass, scan_temp);
3938 assert_different_registers(method_result, intf_klass, scan_temp);
3939 assert(recv_klass != method_result || !return_method,
3940 "recv_klass can be destroyed when method isn't needed");
3941
3942 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3943 "caller must use same register for non-constant itable index as for method");
3944
3945 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3946 int vtable_base = in_bytes(Klass::vtable_start_offset());
3947 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3948 int scan_step = itableOffsetEntry::size() * wordSize;
3949 int vte_size = vtableEntry::size_in_bytes();
3950 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3951 assert(vte_size == wordSize, "else adjust times_vte_scale");
3952
3953 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3954
3955 // Could store the aligned, prescaled offset in the klass.
3956 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3957
3958 if (return_method) {
3959 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3960 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3961 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3962 }
3963
3964 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
3965 // if (scan->interface() == intf) {
3966 // result = (klass + scan->offset() + itable_index);
3967 // }
3968 // }
3969 Label search, found_method;
3970
3971 for (int peel = 1; peel >= 0; peel--) {
3972 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
3973 cmpptr(intf_klass, method_result);
3974
3975 if (peel) {
3976 jccb(Assembler::equal, found_method);
3977 } else {
3978 jccb(Assembler::notEqual, search);
3979 // (invert the test to fall through to found_method...)
3980 }
3981
3982 if (!peel) break;
3983
3984 bind(search);
3985
3986 // Check that the previous entry is non-null. A null entry means that
3987 // the receiver class doesn't implement the interface, and wasn't the
3988 // same as when the caller was compiled.
3989 testptr(method_result, method_result);
3990 jcc(Assembler::zero, L_no_such_interface);
3991 addptr(scan_temp, scan_step);
3992 }
3993
3994 bind(found_method);
3995
3996 if (return_method) {
3997 // Got a hit.
3998 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
3999 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4000 }
4001 }
4002
4003 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4004 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4005 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4006 // The target method is determined by <holder_klass, itable_index>.
4007 // The receiver klass is in recv_klass.
4008 // On success, the result will be in method_result, and execution falls through.
4009 // On failure, execution transfers to the given label.
4010 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4011 Register holder_klass,
4012 Register resolved_klass,
4013 Register method_result,
4014 Register scan_temp,
4015 Register temp_reg2,
4016 Register receiver,
4017 int itable_index,
4018 Label& L_no_such_interface) {
4019 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4020 Register temp_itbl_klass = method_result;
4021 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4022
4023 int vtable_base = in_bytes(Klass::vtable_start_offset());
4024 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4025 int scan_step = itableOffsetEntry::size() * wordSize;
4026 int vte_size = vtableEntry::size_in_bytes();
4027 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4028 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4029 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4030 assert(vte_size == wordSize, "adjust times_vte_scale");
4031
4032 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4033
4034 // temp_itbl_klass = recv_klass.itable[0]
4035 // scan_temp = &recv_klass.itable[0] + step
4036 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4037 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4038 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4039 xorptr(temp_reg, temp_reg);
4040
4041 // Initial checks:
4042 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4043 // - if (itable[0] == 0), no such interface
4044 // - if (itable[0] == holder_klass), shortcut to "holder found"
4045 cmpptr(holder_klass, resolved_klass);
4046 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4047 testptr(temp_itbl_klass, temp_itbl_klass);
4048 jccb(Assembler::zero, L_no_such_interface);
4049 cmpptr(holder_klass, temp_itbl_klass);
4050 jccb(Assembler::equal, L_holder_found);
4051
4052 // Loop: Look for holder_klass record in itable
4053 // do {
4054 // tmp = itable[index];
4055 // index += step;
4056 // if (tmp == holder_klass) {
4057 // goto L_holder_found; // Found!
4058 // }
4059 // } while (tmp != 0);
4060 // goto L_no_such_interface // Not found.
4061 Label L_scan_holder;
4062 bind(L_scan_holder);
4063 movptr(temp_itbl_klass, Address(scan_temp, 0));
4064 addptr(scan_temp, scan_step);
4065 cmpptr(holder_klass, temp_itbl_klass);
4066 jccb(Assembler::equal, L_holder_found);
4067 testptr(temp_itbl_klass, temp_itbl_klass);
4068 jccb(Assembler::notZero, L_scan_holder);
4069
4070 jmpb(L_no_such_interface);
4071
4072 // Loop: Look for resolved_class record in itable
4073 // do {
4074 // tmp = itable[index];
4075 // index += step;
4076 // if (tmp == holder_klass) {
4077 // // Also check if we have met a holder klass
4078 // holder_tmp = itable[index-step-ioffset];
4079 // }
4080 // if (tmp == resolved_klass) {
4081 // goto L_resolved_found; // Found!
4082 // }
4083 // } while (tmp != 0);
4084 // goto L_no_such_interface // Not found.
4085 //
4086 Label L_loop_scan_resolved;
4087 bind(L_loop_scan_resolved);
4088 movptr(temp_itbl_klass, Address(scan_temp, 0));
4089 addptr(scan_temp, scan_step);
4090 bind(L_loop_scan_resolved_entry);
4091 cmpptr(holder_klass, temp_itbl_klass);
4092 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4093 cmpptr(resolved_klass, temp_itbl_klass);
4094 jccb(Assembler::equal, L_resolved_found);
4095 testptr(temp_itbl_klass, temp_itbl_klass);
4096 jccb(Assembler::notZero, L_loop_scan_resolved);
4097
4098 jmpb(L_no_such_interface);
4099
4100 Label L_ready;
4101
4102 // See if we already have a holder klass. If not, go and scan for it.
4103 bind(L_resolved_found);
4104 testptr(temp_reg, temp_reg);
4105 jccb(Assembler::zero, L_scan_holder);
4106 jmpb(L_ready);
4107
4108 bind(L_holder_found);
4109 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4110
4111 // Finally, temp_reg contains holder_klass vtable offset
4112 bind(L_ready);
4113 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4114 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4115 load_klass(scan_temp, receiver, noreg);
4116 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4117 } else {
4118 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4119 }
4120 }
4121
4122
4123 // virtual method calling
4124 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4125 RegisterOrConstant vtable_index,
4126 Register method_result) {
4127 const ByteSize base = Klass::vtable_start_offset();
4128 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4129 Address vtable_entry_addr(recv_klass,
4130 vtable_index, Address::times_ptr,
4131 base + vtableEntry::method_offset());
4132 movptr(method_result, vtable_entry_addr);
4133 }
4134
4135
4136 void MacroAssembler::check_klass_subtype(Register sub_klass,
4137 Register super_klass,
4138 Register temp_reg,
4139 Label& L_success) {
4140 Label L_failure;
4141 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4142 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4143 bind(L_failure);
4144 }
4145
4146
4147 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4148 Register super_klass,
4149 Register temp_reg,
4150 Label* L_success,
4151 Label* L_failure,
4152 Label* L_slow_path,
4153 RegisterOrConstant super_check_offset) {
4154 assert_different_registers(sub_klass, super_klass, temp_reg);
4155 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4156 if (super_check_offset.is_register()) {
4157 assert_different_registers(sub_klass, super_klass,
4158 super_check_offset.as_register());
4159 } else if (must_load_sco) {
4160 assert(temp_reg != noreg, "supply either a temp or a register offset");
4161 }
4162
4163 Label L_fallthrough;
4164 int label_nulls = 0;
4165 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4166 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4167 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4168 assert(label_nulls <= 1, "at most one null in the batch");
4169
4170 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4171 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4172 Address super_check_offset_addr(super_klass, sco_offset);
4173
4174 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4175 // range of a jccb. If this routine grows larger, reconsider at
4176 // least some of these.
4177 #define local_jcc(assembler_cond, label) \
4178 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4179 else jcc( assembler_cond, label) /*omit semi*/
4180
4181 // Hacked jmp, which may only be used just before L_fallthrough.
4182 #define final_jmp(label) \
4183 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4184 else jmp(label) /*omit semi*/
4185
4186 // If the pointers are equal, we are done (e.g., String[] elements).
4187 // This self-check enables sharing of secondary supertype arrays among
4188 // non-primary types such as array-of-interface. Otherwise, each such
4189 // type would need its own customized SSA.
4190 // We move this check to the front of the fast path because many
4191 // type checks are in fact trivially successful in this manner,
4192 // so we get a nicely predicted branch right at the start of the check.
4193 cmpptr(sub_klass, super_klass);
4194 local_jcc(Assembler::equal, *L_success);
4195
4196 // Check the supertype display:
4197 if (must_load_sco) {
4198 // Positive movl does right thing on LP64.
4199 movl(temp_reg, super_check_offset_addr);
4200 super_check_offset = RegisterOrConstant(temp_reg);
4201 }
4202 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4203 cmpptr(super_klass, super_check_addr); // load displayed supertype
4204
4205 // This check has worked decisively for primary supers.
4206 // Secondary supers are sought in the super_cache ('super_cache_addr').
4207 // (Secondary supers are interfaces and very deeply nested subtypes.)
4208 // This works in the same check above because of a tricky aliasing
4209 // between the super_cache and the primary super display elements.
4210 // (The 'super_check_addr' can address either, as the case requires.)
4211 // Note that the cache is updated below if it does not help us find
4212 // what we need immediately.
4213 // So if it was a primary super, we can just fail immediately.
4214 // Otherwise, it's the slow path for us (no success at this point).
4215
4216 if (super_check_offset.is_register()) {
4217 local_jcc(Assembler::equal, *L_success);
4218 cmpl(super_check_offset.as_register(), sc_offset);
4219 if (L_failure == &L_fallthrough) {
4220 local_jcc(Assembler::equal, *L_slow_path);
4221 } else {
4222 local_jcc(Assembler::notEqual, *L_failure);
4223 final_jmp(*L_slow_path);
4224 }
4225 } else if (super_check_offset.as_constant() == sc_offset) {
4226 // Need a slow path; fast failure is impossible.
4227 if (L_slow_path == &L_fallthrough) {
4228 local_jcc(Assembler::equal, *L_success);
4229 } else {
4230 local_jcc(Assembler::notEqual, *L_slow_path);
4231 final_jmp(*L_success);
4232 }
4233 } else {
4234 // No slow path; it's a fast decision.
4235 if (L_failure == &L_fallthrough) {
4236 local_jcc(Assembler::equal, *L_success);
4237 } else {
4238 local_jcc(Assembler::notEqual, *L_failure);
4239 final_jmp(*L_success);
4240 }
4241 }
4242
4243 bind(L_fallthrough);
4244
4245 #undef local_jcc
4246 #undef final_jmp
4247 }
4248
4249
4250 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4251 Register super_klass,
4252 Register temp_reg,
4253 Register temp2_reg,
4254 Label* L_success,
4255 Label* L_failure,
4256 bool set_cond_codes) {
4257 assert_different_registers(sub_klass, super_klass, temp_reg);
4258 if (temp2_reg != noreg)
4259 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4260 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4261
4262 Label L_fallthrough;
4263 int label_nulls = 0;
4264 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4265 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4266 assert(label_nulls <= 1, "at most one null in the batch");
4267
4268 // a couple of useful fields in sub_klass:
4269 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4270 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4271 Address secondary_supers_addr(sub_klass, ss_offset);
4272 Address super_cache_addr( sub_klass, sc_offset);
4273
4274 // Do a linear scan of the secondary super-klass chain.
4275 // This code is rarely used, so simplicity is a virtue here.
4276 // The repne_scan instruction uses fixed registers, which we must spill.
4277 // Don't worry too much about pre-existing connections with the input regs.
4278
4279 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4280 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4281
4282 // Get super_klass value into rax (even if it was in rdi or rcx).
4283 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4284 if (super_klass != rax) {
4285 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4286 mov(rax, super_klass);
4287 }
4288 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4289 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4290
4291 #ifndef PRODUCT
4292 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4293 ExternalAddress pst_counter_addr((address) pst_counter);
4294 lea(rcx, pst_counter_addr);
4295 incrementl(Address(rcx, 0));
4296 #endif //PRODUCT
4297
4298 // We will consult the secondary-super array.
4299 movptr(rdi, secondary_supers_addr);
4300 // Load the array length. (Positive movl does right thing on LP64.)
4301 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4302 // Skip to start of data.
4303 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4304
4305 // Scan RCX words at [RDI] for an occurrence of RAX.
4306 // Set NZ/Z based on last compare.
4307 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4308 // not change flags (only scas instruction which is repeated sets flags).
4309 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4310
4311 testptr(rax,rax); // Set Z = 0
4312 repne_scan();
4313
4314 // Unspill the temp. registers:
4315 if (pushed_rdi) pop(rdi);
4316 if (pushed_rcx) pop(rcx);
4317 if (pushed_rax) pop(rax);
4318
4319 if (set_cond_codes) {
4320 // Special hack for the AD files: rdi is guaranteed non-zero.
4321 assert(!pushed_rdi, "rdi must be left non-null");
4322 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4323 }
4324
4325 if (L_failure == &L_fallthrough)
4326 jccb(Assembler::notEqual, *L_failure);
4327 else jcc(Assembler::notEqual, *L_failure);
4328
4329 // Success. Cache the super we found and proceed in triumph.
4330 movptr(super_cache_addr, super_klass);
4331
4332 if (L_success != &L_fallthrough) {
4333 jmp(*L_success);
4334 }
4335
4336 #undef IS_A_TEMP
4337
4338 bind(L_fallthrough);
4339 }
4340
4341 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4342 Register super_klass,
4343 Register temp_reg,
4344 Register temp2_reg,
4345 Label* L_success,
4346 Label* L_failure,
4347 bool set_cond_codes) {
4348 assert(set_cond_codes == false, "must be false on 64-bit x86");
4349 check_klass_subtype_slow_path
4350 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4351 L_success, L_failure);
4352 }
4353
4354 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4355 Register super_klass,
4356 Register temp_reg,
4357 Register temp2_reg,
4358 Register temp3_reg,
4359 Register temp4_reg,
4360 Label* L_success,
4361 Label* L_failure) {
4362 if (UseSecondarySupersTable) {
4363 check_klass_subtype_slow_path_table
4364 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4365 L_success, L_failure);
4366 } else {
4367 check_klass_subtype_slow_path_linear
4368 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4369 }
4370 }
4371
4372 Register MacroAssembler::allocate_if_noreg(Register r,
4373 RegSetIterator<Register> &available_regs,
4374 RegSet ®s_to_push) {
4375 if (!r->is_valid()) {
4376 r = *available_regs++;
4377 regs_to_push += r;
4378 }
4379 return r;
4380 }
4381
4382 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4383 Register super_klass,
4384 Register temp_reg,
4385 Register temp2_reg,
4386 Register temp3_reg,
4387 Register result_reg,
4388 Label* L_success,
4389 Label* L_failure) {
4390 // NB! Callers may assume that, when temp2_reg is a valid register,
4391 // this code sets it to a nonzero value.
4392 bool temp2_reg_was_valid = temp2_reg->is_valid();
4393
4394 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4395
4396 Label L_fallthrough;
4397 int label_nulls = 0;
4398 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4399 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4400 assert(label_nulls <= 1, "at most one null in the batch");
4401
4402 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4403
4404 RegSetIterator<Register> available_regs
4405 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4406
4407 RegSet pushed_regs;
4408
4409 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4410 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4411 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4412 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4413 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4414
4415 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4416
4417 {
4418
4419 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4420 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4421 subptr(rsp, aligned_size);
4422 push_set(pushed_regs, 0);
4423
4424 lookup_secondary_supers_table_var(sub_klass,
4425 super_klass,
4426 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4427 cmpq(result_reg, 0);
4428
4429 // Unspill the temp. registers:
4430 pop_set(pushed_regs, 0);
4431 // Increment SP but do not clobber flags.
4432 lea(rsp, Address(rsp, aligned_size));
4433 }
4434
4435 if (temp2_reg_was_valid) {
4436 movq(temp2_reg, 1);
4437 }
4438
4439 jcc(Assembler::notEqual, *L_failure);
4440
4441 if (L_success != &L_fallthrough) {
4442 jmp(*L_success);
4443 }
4444
4445 bind(L_fallthrough);
4446 }
4447
4448 // population_count variant for running without the POPCNT
4449 // instruction, which was introduced with SSE4.2 in 2008.
4450 void MacroAssembler::population_count(Register dst, Register src,
4451 Register scratch1, Register scratch2) {
4452 assert_different_registers(src, scratch1, scratch2);
4453 if (UsePopCountInstruction) {
4454 Assembler::popcntq(dst, src);
4455 } else {
4456 assert_different_registers(src, scratch1, scratch2);
4457 assert_different_registers(dst, scratch1, scratch2);
4458 Label loop, done;
4459
4460 mov(scratch1, src);
4461 // dst = 0;
4462 // while(scratch1 != 0) {
4463 // dst++;
4464 // scratch1 &= (scratch1 - 1);
4465 // }
4466 xorl(dst, dst);
4467 testq(scratch1, scratch1);
4468 jccb(Assembler::equal, done);
4469 {
4470 bind(loop);
4471 incq(dst);
4472 movq(scratch2, scratch1);
4473 decq(scratch2);
4474 andq(scratch1, scratch2);
4475 jccb(Assembler::notEqual, loop);
4476 }
4477 bind(done);
4478 }
4479 #ifdef ASSERT
4480 mov64(scratch1, 0xCafeBabeDeadBeef);
4481 movq(scratch2, scratch1);
4482 #endif
4483 }
4484
4485 // Ensure that the inline code and the stub are using the same registers.
4486 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4487 do { \
4488 assert(r_super_klass == rax, "mismatch"); \
4489 assert(r_array_base == rbx, "mismatch"); \
4490 assert(r_array_length == rcx, "mismatch"); \
4491 assert(r_array_index == rdx, "mismatch"); \
4492 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4493 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4494 assert(result == rdi || result == noreg, "mismatch"); \
4495 } while(0)
4496
4497 // Versions of salq and rorq that don't need count to be in rcx
4498
4499 void MacroAssembler::salq(Register dest, Register count) {
4500 if (count == rcx) {
4501 Assembler::salq(dest);
4502 } else {
4503 assert_different_registers(rcx, dest);
4504 xchgq(rcx, count);
4505 Assembler::salq(dest);
4506 xchgq(rcx, count);
4507 }
4508 }
4509
4510 void MacroAssembler::rorq(Register dest, Register count) {
4511 if (count == rcx) {
4512 Assembler::rorq(dest);
4513 } else {
4514 assert_different_registers(rcx, dest);
4515 xchgq(rcx, count);
4516 Assembler::rorq(dest);
4517 xchgq(rcx, count);
4518 }
4519 }
4520
4521 // Return true: we succeeded in generating this code
4522 //
4523 // At runtime, return 0 in result if r_super_klass is a superclass of
4524 // r_sub_klass, otherwise return nonzero. Use this if you know the
4525 // super_klass_slot of the class you're looking for. This is always
4526 // the case for instanceof and checkcast.
4527 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4528 Register r_super_klass,
4529 Register temp1,
4530 Register temp2,
4531 Register temp3,
4532 Register temp4,
4533 Register result,
4534 u1 super_klass_slot) {
4535 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4536
4537 Label L_fallthrough, L_success, L_failure;
4538
4539 BLOCK_COMMENT("lookup_secondary_supers_table {");
4540
4541 const Register
4542 r_array_index = temp1,
4543 r_array_length = temp2,
4544 r_array_base = temp3,
4545 r_bitmap = temp4;
4546
4547 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4548
4549 xorq(result, result); // = 0
4550
4551 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4552 movq(r_array_index, r_bitmap);
4553
4554 // First check the bitmap to see if super_klass might be present. If
4555 // the bit is zero, we are certain that super_klass is not one of
4556 // the secondary supers.
4557 u1 bit = super_klass_slot;
4558 {
4559 // NB: If the count in a x86 shift instruction is 0, the flags are
4560 // not affected, so we do a testq instead.
4561 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4562 if (shift_count != 0) {
4563 salq(r_array_index, shift_count);
4564 } else {
4565 testq(r_array_index, r_array_index);
4566 }
4567 }
4568 // We test the MSB of r_array_index, i.e. its sign bit
4569 jcc(Assembler::positive, L_failure);
4570
4571 // Get the first array index that can contain super_klass into r_array_index.
4572 if (bit != 0) {
4573 population_count(r_array_index, r_array_index, temp2, temp3);
4574 } else {
4575 movl(r_array_index, 1);
4576 }
4577 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4578
4579 // We will consult the secondary-super array.
4580 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4581
4582 // We're asserting that the first word in an Array<Klass*> is the
4583 // length, and the second word is the first word of the data. If
4584 // that ever changes, r_array_base will have to be adjusted here.
4585 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4586 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4587
4588 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4589 jccb(Assembler::equal, L_success);
4590
4591 // Is there another entry to check? Consult the bitmap.
4592 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4593 jccb(Assembler::carryClear, L_failure);
4594
4595 // Linear probe. Rotate the bitmap so that the next bit to test is
4596 // in Bit 1.
4597 if (bit != 0) {
4598 rorq(r_bitmap, bit);
4599 }
4600
4601 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4602 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4603 // Kills: r_array_length.
4604 // Returns: result.
4605 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4606 // Result (0/1) is in rdi
4607 jmpb(L_fallthrough);
4608
4609 bind(L_failure);
4610 incq(result); // 0 => 1
4611
4612 bind(L_success);
4613 // result = 0;
4614
4615 bind(L_fallthrough);
4616 BLOCK_COMMENT("} lookup_secondary_supers_table");
4617
4618 if (VerifySecondarySupers) {
4619 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4620 temp1, temp2, temp3);
4621 }
4622 }
4623
4624 // At runtime, return 0 in result if r_super_klass is a superclass of
4625 // r_sub_klass, otherwise return nonzero. Use this version of
4626 // lookup_secondary_supers_table() if you don't know ahead of time
4627 // which superclass will be searched for. Used by interpreter and
4628 // runtime stubs. It is larger and has somewhat greater latency than
4629 // the version above, which takes a constant super_klass_slot.
4630 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
4631 Register r_super_klass,
4632 Register temp1,
4633 Register temp2,
4634 Register temp3,
4635 Register temp4,
4636 Register result) {
4637 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4638 assert_different_registers(r_sub_klass, r_super_klass, rcx);
4639 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
4640
4641 Label L_fallthrough, L_success, L_failure;
4642
4643 BLOCK_COMMENT("lookup_secondary_supers_table {");
4644
4645 RegSetIterator<Register> available_regs = (temps - rcx).begin();
4646
4647 // FIXME. Once we are sure that all paths reaching this point really
4648 // do pass rcx as one of our temps we can get rid of the following
4649 // workaround.
4650 assert(temps.contains(rcx), "fix this code");
4651
4652 // We prefer to have our shift count in rcx. If rcx is one of our
4653 // temps, use it for slot. If not, pick any of our temps.
4654 Register slot;
4655 if (!temps.contains(rcx)) {
4656 slot = *available_regs++;
4657 } else {
4658 slot = rcx;
4659 }
4660
4661 const Register r_array_index = *available_regs++;
4662 const Register r_bitmap = *available_regs++;
4663
4664 // The logic above guarantees this property, but we state it here.
4665 assert_different_registers(r_array_index, r_bitmap, rcx);
4666
4667 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4668 movq(r_array_index, r_bitmap);
4669
4670 // First check the bitmap to see if super_klass might be present. If
4671 // the bit is zero, we are certain that super_klass is not one of
4672 // the secondary supers.
4673 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4674 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
4675 salq(r_array_index, slot);
4676
4677 testq(r_array_index, r_array_index);
4678 // We test the MSB of r_array_index, i.e. its sign bit
4679 jcc(Assembler::positive, L_failure);
4680
4681 const Register r_array_base = *available_regs++;
4682
4683 // Get the first array index that can contain super_klass into r_array_index.
4684 // Note: Clobbers r_array_base and slot.
4685 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
4686
4687 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4688
4689 // We will consult the secondary-super array.
4690 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4691
4692 // We're asserting that the first word in an Array<Klass*> is the
4693 // length, and the second word is the first word of the data. If
4694 // that ever changes, r_array_base will have to be adjusted here.
4695 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4696 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4697
4698 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4699 jccb(Assembler::equal, L_success);
4700
4701 // Restore slot to its true value
4702 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4703
4704 // Linear probe. Rotate the bitmap so that the next bit to test is
4705 // in Bit 1.
4706 rorq(r_bitmap, slot);
4707
4708 // Is there another entry to check? Consult the bitmap.
4709 btq(r_bitmap, 1);
4710 jccb(Assembler::carryClear, L_failure);
4711
4712 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4713 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4714 // Kills: r_array_length.
4715 // Returns: result.
4716 lookup_secondary_supers_table_slow_path(r_super_klass,
4717 r_array_base,
4718 r_array_index,
4719 r_bitmap,
4720 /*temp1*/result,
4721 /*temp2*/slot,
4722 &L_success,
4723 nullptr);
4724
4725 bind(L_failure);
4726 movq(result, 1);
4727 jmpb(L_fallthrough);
4728
4729 bind(L_success);
4730 xorq(result, result); // = 0
4731
4732 bind(L_fallthrough);
4733 BLOCK_COMMENT("} lookup_secondary_supers_table");
4734
4735 if (VerifySecondarySupers) {
4736 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4737 temp1, temp2, temp3);
4738 }
4739 }
4740
4741 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4742 Label* L_success, Label* L_failure) {
4743 Label L_loop, L_fallthrough;
4744 {
4745 int label_nulls = 0;
4746 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4747 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4748 assert(label_nulls <= 1, "at most one null in the batch");
4749 }
4750 bind(L_loop);
4751 cmpq(value, Address(addr, count, Address::times_8));
4752 jcc(Assembler::equal, *L_success);
4753 addl(count, 1);
4754 cmpl(count, limit);
4755 jcc(Assembler::less, L_loop);
4756
4757 if (&L_fallthrough != L_failure) {
4758 jmp(*L_failure);
4759 }
4760 bind(L_fallthrough);
4761 }
4762
4763 // Called by code generated by check_klass_subtype_slow_path
4764 // above. This is called when there is a collision in the hashed
4765 // lookup in the secondary supers array.
4766 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4767 Register r_array_base,
4768 Register r_array_index,
4769 Register r_bitmap,
4770 Register temp1,
4771 Register temp2,
4772 Label* L_success,
4773 Label* L_failure) {
4774 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4775
4776 const Register
4777 r_array_length = temp1,
4778 r_sub_klass = noreg,
4779 result = noreg;
4780
4781 Label L_fallthrough;
4782 int label_nulls = 0;
4783 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4784 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4785 assert(label_nulls <= 1, "at most one null in the batch");
4786
4787 // Load the array length.
4788 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4789 // And adjust the array base to point to the data.
4790 // NB! Effectively increments current slot index by 1.
4791 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4792 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4793
4794 // Linear probe
4795 Label L_huge;
4796
4797 // The bitmap is full to bursting.
4798 // Implicit invariant: BITMAP_FULL implies (length > 0)
4799 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
4800 jcc(Assembler::greater, L_huge);
4801
4802 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4803 // current slot (at secondary_supers[r_array_index]) has not yet
4804 // been inspected, and r_array_index may be out of bounds if we
4805 // wrapped around the end of the array.
4806
4807 { // This is conventional linear probing, but instead of terminating
4808 // when a null entry is found in the table, we maintain a bitmap
4809 // in which a 0 indicates missing entries.
4810 // The check above guarantees there are 0s in the bitmap, so the loop
4811 // eventually terminates.
4812
4813 xorl(temp2, temp2); // = 0;
4814
4815 Label L_again;
4816 bind(L_again);
4817
4818 // Check for array wraparound.
4819 cmpl(r_array_index, r_array_length);
4820 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4821
4822 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4823 jcc(Assembler::equal, *L_success);
4824
4825 // If the next bit in bitmap is zero, we're done.
4826 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4827 jcc(Assembler::carryClear, *L_failure);
4828
4829 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4830 addl(r_array_index, 1);
4831
4832 jmp(L_again);
4833 }
4834
4835 { // Degenerate case: more than 64 secondary supers.
4836 // FIXME: We could do something smarter here, maybe a vectorized
4837 // comparison or a binary search, but is that worth any added
4838 // complexity?
4839 bind(L_huge);
4840 xorl(r_array_index, r_array_index); // = 0
4841 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4842 L_success,
4843 (&L_fallthrough != L_failure ? L_failure : nullptr));
4844
4845 bind(L_fallthrough);
4846 }
4847 }
4848
4849 struct VerifyHelperArguments {
4850 Klass* _super;
4851 Klass* _sub;
4852 intptr_t _linear_result;
4853 intptr_t _table_result;
4854 };
4855
4856 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
4857 Klass::on_secondary_supers_verification_failure(args->_super,
4858 args->_sub,
4859 args->_linear_result,
4860 args->_table_result,
4861 msg);
4862 }
4863
4864 // Make sure that the hashed lookup and a linear scan agree.
4865 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
4866 Register r_super_klass,
4867 Register result,
4868 Register temp1,
4869 Register temp2,
4870 Register temp3) {
4871 const Register
4872 r_array_index = temp1,
4873 r_array_length = temp2,
4874 r_array_base = temp3,
4875 r_bitmap = noreg;
4876
4877 BLOCK_COMMENT("verify_secondary_supers_table {");
4878
4879 Label L_success, L_failure, L_check, L_done;
4880
4881 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4882 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4883 // And adjust the array base to point to the data.
4884 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4885
4886 testl(r_array_length, r_array_length); // array_length == 0?
4887 jcc(Assembler::zero, L_failure);
4888
4889 movl(r_array_index, 0);
4890 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
4891 // fall through to L_failure
4892
4893 const Register linear_result = r_array_index; // reuse temp1
4894
4895 bind(L_failure); // not present
4896 movl(linear_result, 1);
4897 jmp(L_check);
4898
4899 bind(L_success); // present
4900 movl(linear_result, 0);
4901
4902 bind(L_check);
4903 cmpl(linear_result, result);
4904 jcc(Assembler::equal, L_done);
4905
4906 { // To avoid calling convention issues, build a record on the stack
4907 // and pass the pointer to that instead.
4908 push(result);
4909 push(linear_result);
4910 push(r_sub_klass);
4911 push(r_super_klass);
4912 movptr(c_rarg1, rsp);
4913 movptr(c_rarg0, (uintptr_t) "mismatch");
4914 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
4915 should_not_reach_here();
4916 }
4917 bind(L_done);
4918
4919 BLOCK_COMMENT("} verify_secondary_supers_table");
4920 }
4921
4922 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
4923
4924 void MacroAssembler::clinit_barrier(Register klass, Label* L_fast_path, Label* L_slow_path) {
4925 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
4926
4927 Label L_fallthrough;
4928 if (L_fast_path == nullptr) {
4929 L_fast_path = &L_fallthrough;
4930 } else if (L_slow_path == nullptr) {
4931 L_slow_path = &L_fallthrough;
4932 }
4933
4934 // Fast path check: class is fully initialized.
4935 // init_state needs acquire, but x86 is TSO, and so we are already good.
4936 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4937 jcc(Assembler::equal, *L_fast_path);
4938
4939 // Fast path check: current thread is initializer thread
4940 cmpptr(r15_thread, Address(klass, InstanceKlass::init_thread_offset()));
4941 if (L_slow_path == &L_fallthrough) {
4942 jcc(Assembler::equal, *L_fast_path);
4943 bind(*L_slow_path);
4944 } else if (L_fast_path == &L_fallthrough) {
4945 jcc(Assembler::notEqual, *L_slow_path);
4946 bind(*L_fast_path);
4947 } else {
4948 Unimplemented();
4949 }
4950 }
4951
4952 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4953 if (VM_Version::supports_cmov()) {
4954 cmovl(cc, dst, src);
4955 } else {
4956 Label L;
4957 jccb(negate_condition(cc), L);
4958 movl(dst, src);
4959 bind(L);
4960 }
4961 }
4962
4963 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4964 if (VM_Version::supports_cmov()) {
4965 cmovl(cc, dst, src);
4966 } else {
4967 Label L;
4968 jccb(negate_condition(cc), L);
4969 movl(dst, src);
4970 bind(L);
4971 }
4972 }
4973
4974 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4975 if (!VerifyOops || VerifyAdapterSharing) {
4976 // Below address of the code string confuses VerifyAdapterSharing
4977 // because it may differ between otherwise equivalent adapters.
4978 return;
4979 }
4980
4981 BLOCK_COMMENT("verify_oop {");
4982 push(rscratch1);
4983 push(rax); // save rax
4984 push(reg); // pass register argument
4985
4986 // Pass register number to verify_oop_subroutine
4987 const char* b = nullptr;
4988 {
4989 ResourceMark rm;
4990 stringStream ss;
4991 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4992 b = code_string(ss.as_string());
4993 }
4994 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
4995 pushptr(buffer.addr(), rscratch1);
4996
4997 // call indirectly to solve generation ordering problem
4998 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4999 call(rax);
5000 // Caller pops the arguments (oop, message) and restores rax, r10
5001 BLOCK_COMMENT("} verify_oop");
5002 }
5003
5004 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5005 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5006 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5007 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5008 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5009 } else if (VM_Version::supports_avx()) {
5010 vpcmpeqd(dst, dst, dst, vector_len);
5011 } else {
5012 pcmpeqd(dst, dst);
5013 }
5014 }
5015
5016 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5017 int extra_slot_offset) {
5018 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5019 int stackElementSize = Interpreter::stackElementSize;
5020 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5021 #ifdef ASSERT
5022 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5023 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5024 #endif
5025 Register scale_reg = noreg;
5026 Address::ScaleFactor scale_factor = Address::no_scale;
5027 if (arg_slot.is_constant()) {
5028 offset += arg_slot.as_constant() * stackElementSize;
5029 } else {
5030 scale_reg = arg_slot.as_register();
5031 scale_factor = Address::times(stackElementSize);
5032 }
5033 offset += wordSize; // return PC is on stack
5034 return Address(rsp, scale_reg, scale_factor, offset);
5035 }
5036
5037 // Handle the receiver type profile update given the "recv" klass.
5038 //
5039 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
5040 // If there are no matching or claimable receiver entries in RD, updates
5041 // the polymorphic counter.
5042 //
5043 // This code expected to run by either the interpreter or JIT-ed code, without
5044 // extra synchronization. For safety, receiver cells are claimed atomically, which
5045 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
5046 // counter updates are not atomic.
5047 //
5048 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
5049 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
5050 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
5051 int poly_count_offset = in_bytes(CounterData::count_offset());
5052 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
5053 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
5054
5055 // Adjust for MDP offsets. Slots are pointer-sized, so is the global offset.
5056 assert(is_aligned(mdp_offset, BytesPerWord), "sanity");
5057 base_receiver_offset += mdp_offset;
5058 end_receiver_offset += mdp_offset;
5059 poly_count_offset += mdp_offset;
5060
5061 // Scale down to optimize encoding. Slots are pointer-sized.
5062 assert(is_aligned(base_receiver_offset, BytesPerWord), "sanity");
5063 assert(is_aligned(end_receiver_offset, BytesPerWord), "sanity");
5064 assert(is_aligned(poly_count_offset, BytesPerWord), "sanity");
5065 assert(is_aligned(receiver_step, BytesPerWord), "sanity");
5066 assert(is_aligned(receiver_to_count_step, BytesPerWord), "sanity");
5067 base_receiver_offset >>= LogBytesPerWord;
5068 end_receiver_offset >>= LogBytesPerWord;
5069 poly_count_offset >>= LogBytesPerWord;
5070 receiver_step >>= LogBytesPerWord;
5071 receiver_to_count_step >>= LogBytesPerWord;
5072
5073 #ifdef ASSERT
5074 // We are about to walk the MDO slots without asking for offsets.
5075 // Check that our math hits all the right spots.
5076 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
5077 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
5078 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
5079 int offset = base_receiver_offset + receiver_step*c;
5080 int count_offset = offset + receiver_to_count_step;
5081 assert((offset << LogBytesPerWord) == real_recv_offset, "receiver slot math");
5082 assert((count_offset << LogBytesPerWord) == real_count_offset, "receiver count math");
5083 }
5084 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
5085 assert(poly_count_offset << LogBytesPerWord == real_poly_count_offset, "poly counter math");
5086 #endif
5087
5088 // Corner case: no profile table. Increment poly counter and exit.
5089 if (ReceiverTypeData::row_limit() == 0) {
5090 addptr(Address(mdp, poly_count_offset, Address::times_ptr), DataLayout::counter_increment);
5091 return;
5092 }
5093
5094 Register offset = rscratch1;
5095
5096 Label L_loop_search_receiver, L_loop_search_empty;
5097 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
5098
5099 // The code here recognizes three major cases:
5100 // A. Fastest: receiver found in the table
5101 // B. Fast: no receiver in the table, and the table is full
5102 // C. Slow: no receiver in the table, free slots in the table
5103 //
5104 // The case A performance is most important, as perfectly-behaved code would end up
5105 // there, especially with larger TypeProfileWidth. The case B performance is
5106 // important as well, this is where bulk of code would land for normally megamorphic
5107 // cases. The case C performance is not essential, its job is to deal with installation
5108 // races, we optimize for code density instead. Case C needs to make sure that receiver
5109 // rows are only claimed once. This makes sure we never overwrite a row for another
5110 // receiver and never duplicate the receivers in the list, making profile type-accurate.
5111 //
5112 // It is very tempting to handle these cases in a single loop, and claim the first slot
5113 // without checking the rest of the table. But, profiling code should tolerate free slots
5114 // in the table, as class unloading can clear them. After such cleanup, the receiver
5115 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
5116 // to complete, before trying to install new slots. Splitting the code in several tight
5117 // loops also helpfully optimizes for cases A and B.
5118 //
5119 // This code is effectively:
5120 //
5121 // restart:
5122 // // Fastest: receiver is already installed
5123 // for (i = 0; i < receiver_count(); i++) {
5124 // if (receiver(i) == recv) goto found_recv(i);
5125 // }
5126 //
5127 // // Fast: no receiver, but profile is full
5128 // for (i = 0; i < receiver_count(); i++) {
5129 // if (receiver(i) == null) goto found_null(i);
5130 // }
5131 // goto polymorphic
5132 //
5133 // // Slow: try to install receiver
5134 // found_null(i):
5135 // CAS(&receiver(i), null, recv);
5136 // goto restart
5137 //
5138 // polymorphic:
5139 // count++;
5140 // return
5141 //
5142 // found_recv(i):
5143 // *receiver_count(i)++
5144 //
5145
5146 bind(L_restart);
5147
5148 // Fastest: receiver is already installed
5149 movptr(offset, base_receiver_offset);
5150 bind(L_loop_search_receiver);
5151 cmpptr(recv, Address(mdp, offset, Address::times_ptr));
5152 jccb(Assembler::equal, L_found_recv);
5153 addptr(offset, receiver_step);
5154 cmpptr(offset, end_receiver_offset);
5155 jccb(Assembler::notEqual, L_loop_search_receiver);
5156
5157 // Fast: no receiver, but profile is full
5158 movptr(offset, base_receiver_offset);
5159 bind(L_loop_search_empty);
5160 cmpptr(Address(mdp, offset, Address::times_ptr), NULL_WORD);
5161 jccb(Assembler::equal, L_found_empty);
5162 addptr(offset, receiver_step);
5163 cmpptr(offset, end_receiver_offset);
5164 jccb(Assembler::notEqual, L_loop_search_empty);
5165 jmpb(L_polymorphic);
5166
5167 // Slow: try to install receiver
5168 bind(L_found_empty);
5169
5170 // Atomically swing receiver slot: null -> recv.
5171 //
5172 // The update code uses CAS, which wants RAX register specifically, *and* it needs
5173 // other important registers untouched, as they form the address. Therefore, we need
5174 // to shift any important registers from RAX into some other spare register. If we
5175 // have a spare register, we are forced to save it on stack here.
5176
5177 Register spare_reg = noreg;
5178 Register shifted_mdp = mdp;
5179 Register shifted_recv = recv;
5180 if (recv == rax || mdp == rax) {
5181 spare_reg = (recv != rbx && mdp != rbx) ? rbx :
5182 (recv != rcx && mdp != rcx) ? rcx :
5183 rdx;
5184 assert_different_registers(mdp, recv, offset, spare_reg);
5185
5186 push(spare_reg);
5187 if (recv == rax) {
5188 movptr(spare_reg, recv);
5189 shifted_recv = spare_reg;
5190 } else {
5191 assert(mdp == rax, "Remaining case");
5192 movptr(spare_reg, mdp);
5193 shifted_mdp = spare_reg;
5194 }
5195 } else {
5196 push(rax);
5197 }
5198
5199 // None of the important registers are in RAX after this shuffle.
5200 assert_different_registers(rax, shifted_mdp, shifted_recv, offset);
5201
5202 xorptr(rax, rax);
5203 cmpxchgptr(shifted_recv, Address(shifted_mdp, offset, Address::times_ptr));
5204
5205 // Unshift registers.
5206 if (recv == rax || mdp == rax) {
5207 movptr(rax, spare_reg);
5208 pop(spare_reg);
5209 } else {
5210 pop(rax);
5211 }
5212
5213 // CAS success means the slot now has the receiver we want. CAS failure means
5214 // something had claimed the slot concurrently: it can be the same receiver we want,
5215 // or something else. Since this is a slow path, we can optimize for code density,
5216 // and just restart the search from the beginning.
5217 jmpb(L_restart);
5218
5219 // Counter updates:
5220
5221 // Increment polymorphic counter instead of receiver slot.
5222 bind(L_polymorphic);
5223 movptr(offset, poly_count_offset);
5224 jmpb(L_count_update);
5225
5226 // Found a receiver, convert its slot offset to corresponding count offset.
5227 bind(L_found_recv);
5228 addptr(offset, receiver_to_count_step);
5229
5230 bind(L_count_update);
5231 addptr(Address(mdp, offset, Address::times_ptr), DataLayout::counter_increment);
5232 }
5233
5234 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5235 if (!VerifyOops || VerifyAdapterSharing) {
5236 // Below address of the code string confuses VerifyAdapterSharing
5237 // because it may differ between otherwise equivalent adapters.
5238 return;
5239 }
5240
5241 push(rscratch1);
5242 push(rax); // save rax,
5243 // addr may contain rsp so we will have to adjust it based on the push
5244 // we just did (and on 64 bit we do two pushes)
5245 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5246 // stores rax into addr which is backwards of what was intended.
5247 if (addr.uses(rsp)) {
5248 lea(rax, addr);
5249 pushptr(Address(rax, 2 * BytesPerWord));
5250 } else {
5251 pushptr(addr);
5252 }
5253
5254 // Pass register number to verify_oop_subroutine
5255 const char* b = nullptr;
5256 {
5257 ResourceMark rm;
5258 stringStream ss;
5259 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5260 b = code_string(ss.as_string());
5261 }
5262 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5263 pushptr(buffer.addr(), rscratch1);
5264
5265 // call indirectly to solve generation ordering problem
5266 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5267 call(rax);
5268 // Caller pops the arguments (addr, message) and restores rax, r10.
5269 }
5270
5271 void MacroAssembler::verify_tlab() {
5272 #ifdef ASSERT
5273 if (UseTLAB && VerifyOops) {
5274 Label next, ok;
5275 Register t1 = rsi;
5276
5277 push(t1);
5278
5279 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5280 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
5281 jcc(Assembler::aboveEqual, next);
5282 STOP("assert(top >= start)");
5283 should_not_reach_here();
5284
5285 bind(next);
5286 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
5287 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5288 jcc(Assembler::aboveEqual, ok);
5289 STOP("assert(top <= end)");
5290 should_not_reach_here();
5291
5292 bind(ok);
5293 pop(t1);
5294 }
5295 #endif
5296 }
5297
5298 class ControlWord {
5299 public:
5300 int32_t _value;
5301
5302 int rounding_control() const { return (_value >> 10) & 3 ; }
5303 int precision_control() const { return (_value >> 8) & 3 ; }
5304 bool precision() const { return ((_value >> 5) & 1) != 0; }
5305 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5306 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5307 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5308 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5309 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5310
5311 void print() const {
5312 // rounding control
5313 const char* rc;
5314 switch (rounding_control()) {
5315 case 0: rc = "round near"; break;
5316 case 1: rc = "round down"; break;
5317 case 2: rc = "round up "; break;
5318 case 3: rc = "chop "; break;
5319 default:
5320 rc = nullptr; // silence compiler warnings
5321 fatal("Unknown rounding control: %d", rounding_control());
5322 };
5323 // precision control
5324 const char* pc;
5325 switch (precision_control()) {
5326 case 0: pc = "24 bits "; break;
5327 case 1: pc = "reserved"; break;
5328 case 2: pc = "53 bits "; break;
5329 case 3: pc = "64 bits "; break;
5330 default:
5331 pc = nullptr; // silence compiler warnings
5332 fatal("Unknown precision control: %d", precision_control());
5333 };
5334 // flags
5335 char f[9];
5336 f[0] = ' ';
5337 f[1] = ' ';
5338 f[2] = (precision ()) ? 'P' : 'p';
5339 f[3] = (underflow ()) ? 'U' : 'u';
5340 f[4] = (overflow ()) ? 'O' : 'o';
5341 f[5] = (zero_divide ()) ? 'Z' : 'z';
5342 f[6] = (denormalized()) ? 'D' : 'd';
5343 f[7] = (invalid ()) ? 'I' : 'i';
5344 f[8] = '\x0';
5345 // output
5346 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5347 }
5348
5349 };
5350
5351 class StatusWord {
5352 public:
5353 int32_t _value;
5354
5355 bool busy() const { return ((_value >> 15) & 1) != 0; }
5356 bool C3() const { return ((_value >> 14) & 1) != 0; }
5357 bool C2() const { return ((_value >> 10) & 1) != 0; }
5358 bool C1() const { return ((_value >> 9) & 1) != 0; }
5359 bool C0() const { return ((_value >> 8) & 1) != 0; }
5360 int top() const { return (_value >> 11) & 7 ; }
5361 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5362 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5363 bool precision() const { return ((_value >> 5) & 1) != 0; }
5364 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5365 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5366 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5367 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5368 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5369
5370 void print() const {
5371 // condition codes
5372 char c[5];
5373 c[0] = (C3()) ? '3' : '-';
5374 c[1] = (C2()) ? '2' : '-';
5375 c[2] = (C1()) ? '1' : '-';
5376 c[3] = (C0()) ? '0' : '-';
5377 c[4] = '\x0';
5378 // flags
5379 char f[9];
5380 f[0] = (error_status()) ? 'E' : '-';
5381 f[1] = (stack_fault ()) ? 'S' : '-';
5382 f[2] = (precision ()) ? 'P' : '-';
5383 f[3] = (underflow ()) ? 'U' : '-';
5384 f[4] = (overflow ()) ? 'O' : '-';
5385 f[5] = (zero_divide ()) ? 'Z' : '-';
5386 f[6] = (denormalized()) ? 'D' : '-';
5387 f[7] = (invalid ()) ? 'I' : '-';
5388 f[8] = '\x0';
5389 // output
5390 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5391 }
5392
5393 };
5394
5395 class TagWord {
5396 public:
5397 int32_t _value;
5398
5399 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5400
5401 void print() const {
5402 printf("%04x", _value & 0xFFFF);
5403 }
5404
5405 };
5406
5407 class FPU_Register {
5408 public:
5409 int32_t _m0;
5410 int32_t _m1;
5411 int16_t _ex;
5412
5413 bool is_indefinite() const {
5414 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5415 }
5416
5417 void print() const {
5418 char sign = (_ex < 0) ? '-' : '+';
5419 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5420 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5421 };
5422
5423 };
5424
5425 class FPU_State {
5426 public:
5427 enum {
5428 register_size = 10,
5429 number_of_registers = 8,
5430 register_mask = 7
5431 };
5432
5433 ControlWord _control_word;
5434 StatusWord _status_word;
5435 TagWord _tag_word;
5436 int32_t _error_offset;
5437 int32_t _error_selector;
5438 int32_t _data_offset;
5439 int32_t _data_selector;
5440 int8_t _register[register_size * number_of_registers];
5441
5442 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5443 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5444
5445 const char* tag_as_string(int tag) const {
5446 switch (tag) {
5447 case 0: return "valid";
5448 case 1: return "zero";
5449 case 2: return "special";
5450 case 3: return "empty";
5451 }
5452 ShouldNotReachHere();
5453 return nullptr;
5454 }
5455
5456 void print() const {
5457 // print computation registers
5458 { int t = _status_word.top();
5459 for (int i = 0; i < number_of_registers; i++) {
5460 int j = (i - t) & register_mask;
5461 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5462 st(j)->print();
5463 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5464 }
5465 }
5466 printf("\n");
5467 // print control registers
5468 printf("ctrl = "); _control_word.print(); printf("\n");
5469 printf("stat = "); _status_word .print(); printf("\n");
5470 printf("tags = "); _tag_word .print(); printf("\n");
5471 }
5472
5473 };
5474
5475 class Flag_Register {
5476 public:
5477 int32_t _value;
5478
5479 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5480 bool direction() const { return ((_value >> 10) & 1) != 0; }
5481 bool sign() const { return ((_value >> 7) & 1) != 0; }
5482 bool zero() const { return ((_value >> 6) & 1) != 0; }
5483 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5484 bool parity() const { return ((_value >> 2) & 1) != 0; }
5485 bool carry() const { return ((_value >> 0) & 1) != 0; }
5486
5487 void print() const {
5488 // flags
5489 char f[8];
5490 f[0] = (overflow ()) ? 'O' : '-';
5491 f[1] = (direction ()) ? 'D' : '-';
5492 f[2] = (sign ()) ? 'S' : '-';
5493 f[3] = (zero ()) ? 'Z' : '-';
5494 f[4] = (auxiliary_carry()) ? 'A' : '-';
5495 f[5] = (parity ()) ? 'P' : '-';
5496 f[6] = (carry ()) ? 'C' : '-';
5497 f[7] = '\x0';
5498 // output
5499 printf("%08x flags = %s", _value, f);
5500 }
5501
5502 };
5503
5504 class IU_Register {
5505 public:
5506 int32_t _value;
5507
5508 void print() const {
5509 printf("%08x %11d", _value, _value);
5510 }
5511
5512 };
5513
5514 class IU_State {
5515 public:
5516 Flag_Register _eflags;
5517 IU_Register _rdi;
5518 IU_Register _rsi;
5519 IU_Register _rbp;
5520 IU_Register _rsp;
5521 IU_Register _rbx;
5522 IU_Register _rdx;
5523 IU_Register _rcx;
5524 IU_Register _rax;
5525
5526 void print() const {
5527 // computation registers
5528 printf("rax, = "); _rax.print(); printf("\n");
5529 printf("rbx, = "); _rbx.print(); printf("\n");
5530 printf("rcx = "); _rcx.print(); printf("\n");
5531 printf("rdx = "); _rdx.print(); printf("\n");
5532 printf("rdi = "); _rdi.print(); printf("\n");
5533 printf("rsi = "); _rsi.print(); printf("\n");
5534 printf("rbp, = "); _rbp.print(); printf("\n");
5535 printf("rsp = "); _rsp.print(); printf("\n");
5536 printf("\n");
5537 // control registers
5538 printf("flgs = "); _eflags.print(); printf("\n");
5539 }
5540 };
5541
5542
5543 class CPU_State {
5544 public:
5545 FPU_State _fpu_state;
5546 IU_State _iu_state;
5547
5548 void print() const {
5549 printf("--------------------------------------------------\n");
5550 _iu_state .print();
5551 printf("\n");
5552 _fpu_state.print();
5553 printf("--------------------------------------------------\n");
5554 }
5555
5556 };
5557
5558
5559 static void _print_CPU_state(CPU_State* state) {
5560 state->print();
5561 };
5562
5563
5564 void MacroAssembler::print_CPU_state() {
5565 push_CPU_state();
5566 push(rsp); // pass CPU state
5567 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5568 addptr(rsp, wordSize); // discard argument
5569 pop_CPU_state();
5570 }
5571
5572 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5573 // Either restore the MXCSR register after returning from the JNI Call
5574 // or verify that it wasn't changed (with -Xcheck:jni flag).
5575 if (VM_Version::supports_sse()) {
5576 if (RestoreMXCSROnJNICalls) {
5577 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5578 } else if (CheckJNICalls) {
5579 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5580 }
5581 }
5582 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5583 vzeroupper();
5584 }
5585
5586 // ((OopHandle)result).resolve();
5587 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5588 assert_different_registers(result, tmp);
5589
5590 // Only 64 bit platforms support GCs that require a tmp register
5591 // Only IN_HEAP loads require a thread_tmp register
5592 // OopHandle::resolve is an indirection like jobject.
5593 access_load_at(T_OBJECT, IN_NATIVE,
5594 result, Address(result, 0), tmp);
5595 }
5596
5597 // ((WeakHandle)result).resolve();
5598 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5599 assert_different_registers(rresult, rtmp);
5600 Label resolved;
5601
5602 // A null weak handle resolves to null.
5603 cmpptr(rresult, 0);
5604 jcc(Assembler::equal, resolved);
5605
5606 // Only 64 bit platforms support GCs that require a tmp register
5607 // Only IN_HEAP loads require a thread_tmp register
5608 // WeakHandle::resolve is an indirection like jweak.
5609 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5610 rresult, Address(rresult, 0), rtmp);
5611 bind(resolved);
5612 }
5613
5614 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5615 // get mirror
5616 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5617 load_method_holder(mirror, method);
5618 movptr(mirror, Address(mirror, mirror_offset));
5619 resolve_oop_handle(mirror, tmp);
5620 }
5621
5622 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5623 load_method_holder(rresult, rmethod);
5624 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5625 }
5626
5627 void MacroAssembler::load_method_holder(Register holder, Register method) {
5628 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5629 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5630 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5631 }
5632
5633 void MacroAssembler::load_metadata(Register dst, Register src) {
5634 if (UseCompactObjectHeaders) {
5635 load_narrow_klass_compact(dst, src);
5636 } else if (UseCompressedClassPointers) {
5637 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5638 } else {
5639 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5640 }
5641 }
5642
5643 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5644 assert(UseCompactObjectHeaders, "expect compact object headers");
5645 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5646 shrq(dst, markWord::klass_shift);
5647 }
5648
5649 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5650 assert_different_registers(src, tmp);
5651 assert_different_registers(dst, tmp);
5652
5653 if (UseCompactObjectHeaders) {
5654 load_narrow_klass_compact(dst, src);
5655 decode_klass_not_null(dst, tmp);
5656 } else if (UseCompressedClassPointers) {
5657 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5658 decode_klass_not_null(dst, tmp);
5659 } else {
5660 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5661 }
5662 }
5663
5664 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
5665 load_klass(dst, src, tmp);
5666 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5667 }
5668
5669 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5670 assert(!UseCompactObjectHeaders, "not with compact headers");
5671 assert_different_registers(src, tmp);
5672 assert_different_registers(dst, tmp);
5673 if (UseCompressedClassPointers) {
5674 encode_klass_not_null(src, tmp);
5675 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5676 } else {
5677 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5678 }
5679 }
5680
5681 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5682 if (UseCompactObjectHeaders) {
5683 assert(tmp != noreg, "need tmp");
5684 assert_different_registers(klass, obj, tmp);
5685 load_narrow_klass_compact(tmp, obj);
5686 cmpl(klass, tmp);
5687 } else if (UseCompressedClassPointers) {
5688 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5689 } else {
5690 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5691 }
5692 }
5693
5694 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5695 if (UseCompactObjectHeaders) {
5696 assert(tmp2 != noreg, "need tmp2");
5697 assert_different_registers(obj1, obj2, tmp1, tmp2);
5698 load_narrow_klass_compact(tmp1, obj1);
5699 load_narrow_klass_compact(tmp2, obj2);
5700 cmpl(tmp1, tmp2);
5701 } else if (UseCompressedClassPointers) {
5702 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5703 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5704 } else {
5705 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5706 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5707 }
5708 }
5709
5710 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5711 Register tmp1) {
5712 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5713 decorators = AccessInternal::decorator_fixup(decorators, type);
5714 bool as_raw = (decorators & AS_RAW) != 0;
5715 if (as_raw) {
5716 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1);
5717 } else {
5718 bs->load_at(this, decorators, type, dst, src, tmp1);
5719 }
5720 }
5721
5722 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5723 Register tmp1, Register tmp2, Register tmp3) {
5724 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5725 decorators = AccessInternal::decorator_fixup(decorators, type);
5726 bool as_raw = (decorators & AS_RAW) != 0;
5727 if (as_raw) {
5728 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5729 } else {
5730 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5731 }
5732 }
5733
5734 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5735 Register inline_layout_info) {
5736 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5737 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5738 }
5739
5740 void MacroAssembler::payload_offset(Register inline_klass, Register offset) {
5741 movptr(offset, Address(inline_klass, InlineKlass::adr_members_offset()));
5742 movl(offset, Address(offset, InlineKlass::payload_offset_offset()));
5743 }
5744
5745 void MacroAssembler::payload_addr(Register oop, Register data, Register inline_klass) {
5746 // ((address) (void*) o) + vk->payload_offset();
5747 Register offset = (data == oop) ? rscratch1 : data;
5748 payload_offset(inline_klass, offset);
5749 if (data == oop) {
5750 addptr(data, offset);
5751 } else {
5752 lea(data, Address(oop, offset));
5753 }
5754 }
5755
5756 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
5757 Register index, Register data) {
5758 assert(index != rcx, "index needs to shift by rcx");
5759 assert_different_registers(array, array_klass, index);
5760 assert_different_registers(rcx, array, index);
5761
5762 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
5763 movl(rcx, Address(array_klass, Klass::layout_helper_offset()));
5764
5765 // Klass::layout_helper_log2_element_size(lh)
5766 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
5767 shrl(rcx, Klass::_lh_log2_element_size_shift);
5768 andl(rcx, Klass::_lh_log2_element_size_mask);
5769 shlptr(index); // index << rcx
5770
5771 lea(data, Address(array, index, Address::times_1, arrayOopDesc::base_offset_in_bytes(T_FLAT_ELEMENT)));
5772 }
5773
5774 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5775 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1);
5776 }
5777
5778 // Doesn't do verification, generates fixed size code
5779 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5780 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1);
5781 }
5782
5783 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5784 Register tmp2, Register tmp3, DecoratorSet decorators) {
5785 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5786 }
5787
5788 // Used for storing nulls.
5789 void MacroAssembler::store_heap_oop_null(Address dst) {
5790 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5791 }
5792
5793 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5794 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5795 if (UseCompressedClassPointers) {
5796 // Store to klass gap in destination
5797 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5798 }
5799 }
5800
5801 #ifdef ASSERT
5802 void MacroAssembler::verify_heapbase(const char* msg) {
5803 assert (UseCompressedOops, "should be compressed");
5804 assert (Universe::heap() != nullptr, "java heap should be initialized");
5805 if (CheckCompressedOops) {
5806 Label ok;
5807 ExternalAddress src2(CompressedOops::base_addr());
5808 const bool is_src2_reachable = reachable(src2);
5809 if (!is_src2_reachable) {
5810 push(rscratch1); // cmpptr trashes rscratch1
5811 }
5812 cmpptr(r12_heapbase, src2, rscratch1);
5813 jcc(Assembler::equal, ok);
5814 STOP(msg);
5815 bind(ok);
5816 if (!is_src2_reachable) {
5817 pop(rscratch1);
5818 }
5819 }
5820 }
5821 #endif
5822
5823 // Algorithm must match oop.inline.hpp encode_heap_oop.
5824 void MacroAssembler::encode_heap_oop(Register r) {
5825 #ifdef ASSERT
5826 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5827 #endif
5828 verify_oop_msg(r, "broken oop in encode_heap_oop");
5829 if (CompressedOops::base() == nullptr) {
5830 if (CompressedOops::shift() != 0) {
5831 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5832 shrq(r, LogMinObjAlignmentInBytes);
5833 }
5834 return;
5835 }
5836 testq(r, r);
5837 cmovq(Assembler::equal, r, r12_heapbase);
5838 subq(r, r12_heapbase);
5839 shrq(r, LogMinObjAlignmentInBytes);
5840 }
5841
5842 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5843 #ifdef ASSERT
5844 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5845 if (CheckCompressedOops) {
5846 Label ok;
5847 testq(r, r);
5848 jcc(Assembler::notEqual, ok);
5849 STOP("null oop passed to encode_heap_oop_not_null");
5850 bind(ok);
5851 }
5852 #endif
5853 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5854 if (CompressedOops::base() != nullptr) {
5855 subq(r, r12_heapbase);
5856 }
5857 if (CompressedOops::shift() != 0) {
5858 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5859 shrq(r, LogMinObjAlignmentInBytes);
5860 }
5861 }
5862
5863 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5864 #ifdef ASSERT
5865 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5866 if (CheckCompressedOops) {
5867 Label ok;
5868 testq(src, src);
5869 jcc(Assembler::notEqual, ok);
5870 STOP("null oop passed to encode_heap_oop_not_null2");
5871 bind(ok);
5872 }
5873 #endif
5874 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5875 if (dst != src) {
5876 movq(dst, src);
5877 }
5878 if (CompressedOops::base() != nullptr) {
5879 subq(dst, r12_heapbase);
5880 }
5881 if (CompressedOops::shift() != 0) {
5882 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5883 shrq(dst, LogMinObjAlignmentInBytes);
5884 }
5885 }
5886
5887 void MacroAssembler::decode_heap_oop(Register r) {
5888 #ifdef ASSERT
5889 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5890 #endif
5891 if (CompressedOops::base() == nullptr) {
5892 if (CompressedOops::shift() != 0) {
5893 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5894 shlq(r, LogMinObjAlignmentInBytes);
5895 }
5896 } else {
5897 Label done;
5898 shlq(r, LogMinObjAlignmentInBytes);
5899 jccb(Assembler::equal, done);
5900 addq(r, r12_heapbase);
5901 bind(done);
5902 }
5903 verify_oop_msg(r, "broken oop in decode_heap_oop");
5904 }
5905
5906 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5907 // Note: it will change flags
5908 assert (UseCompressedOops, "should only be used for compressed headers");
5909 assert (Universe::heap() != nullptr, "java heap should be initialized");
5910 // Cannot assert, unverified entry point counts instructions (see .ad file)
5911 // vtableStubs also counts instructions in pd_code_size_limit.
5912 // Also do not verify_oop as this is called by verify_oop.
5913 if (CompressedOops::shift() != 0) {
5914 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5915 shlq(r, LogMinObjAlignmentInBytes);
5916 if (CompressedOops::base() != nullptr) {
5917 addq(r, r12_heapbase);
5918 }
5919 } else {
5920 assert (CompressedOops::base() == nullptr, "sanity");
5921 }
5922 }
5923
5924 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5925 // Note: it will change flags
5926 assert (UseCompressedOops, "should only be used for compressed headers");
5927 assert (Universe::heap() != nullptr, "java heap should be initialized");
5928 // Cannot assert, unverified entry point counts instructions (see .ad file)
5929 // vtableStubs also counts instructions in pd_code_size_limit.
5930 // Also do not verify_oop as this is called by verify_oop.
5931 if (CompressedOops::shift() != 0) {
5932 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5933 if (LogMinObjAlignmentInBytes == Address::times_8) {
5934 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5935 } else {
5936 if (dst != src) {
5937 movq(dst, src);
5938 }
5939 shlq(dst, LogMinObjAlignmentInBytes);
5940 if (CompressedOops::base() != nullptr) {
5941 addq(dst, r12_heapbase);
5942 }
5943 }
5944 } else {
5945 assert (CompressedOops::base() == nullptr, "sanity");
5946 if (dst != src) {
5947 movq(dst, src);
5948 }
5949 }
5950 }
5951
5952 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5953 BLOCK_COMMENT("encode_klass_not_null {");
5954 assert_different_registers(r, tmp);
5955 if (CompressedKlassPointers::base() != nullptr) {
5956 if (AOTCodeCache::is_on_for_dump()) {
5957 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5958 } else {
5959 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5960 }
5961 subq(r, tmp);
5962 }
5963 if (CompressedKlassPointers::shift() != 0) {
5964 shrq(r, CompressedKlassPointers::shift());
5965 }
5966 BLOCK_COMMENT("} encode_klass_not_null");
5967 }
5968
5969 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5970 BLOCK_COMMENT("encode_and_move_klass_not_null {");
5971 assert_different_registers(src, dst);
5972 if (CompressedKlassPointers::base() != nullptr) {
5973 movptr(dst, -(intptr_t)CompressedKlassPointers::base());
5974 addq(dst, src);
5975 } else {
5976 movptr(dst, src);
5977 }
5978 if (CompressedKlassPointers::shift() != 0) {
5979 shrq(dst, CompressedKlassPointers::shift());
5980 }
5981 BLOCK_COMMENT("} encode_and_move_klass_not_null");
5982 }
5983
5984 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5985 BLOCK_COMMENT("decode_klass_not_null {");
5986 assert_different_registers(r, tmp);
5987 // Note: it will change flags
5988 assert(UseCompressedClassPointers, "should only be used for compressed headers");
5989 // Cannot assert, unverified entry point counts instructions (see .ad file)
5990 // vtableStubs also counts instructions in pd_code_size_limit.
5991 // Also do not verify_oop as this is called by verify_oop.
5992 if (CompressedKlassPointers::shift() != 0) {
5993 shlq(r, CompressedKlassPointers::shift());
5994 }
5995 if (CompressedKlassPointers::base() != nullptr) {
5996 if (AOTCodeCache::is_on_for_dump()) {
5997 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5998 } else {
5999 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
6000 }
6001 addq(r, tmp);
6002 }
6003 BLOCK_COMMENT("} decode_klass_not_null");
6004 }
6005
6006 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
6007 BLOCK_COMMENT("decode_and_move_klass_not_null {");
6008 assert_different_registers(src, dst);
6009 // Note: it will change flags
6010 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6011 // Cannot assert, unverified entry point counts instructions (see .ad file)
6012 // vtableStubs also counts instructions in pd_code_size_limit.
6013 // Also do not verify_oop as this is called by verify_oop.
6014
6015 if (CompressedKlassPointers::base() == nullptr &&
6016 CompressedKlassPointers::shift() == 0) {
6017 // The best case scenario is that there is no base or shift. Then it is already
6018 // a pointer that needs nothing but a register rename.
6019 movl(dst, src);
6020 } else {
6021 if (CompressedKlassPointers::shift() <= Address::times_8) {
6022 if (CompressedKlassPointers::base() != nullptr) {
6023 movptr(dst, (intptr_t)CompressedKlassPointers::base());
6024 } else {
6025 xorq(dst, dst);
6026 }
6027 if (CompressedKlassPointers::shift() != 0) {
6028 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
6029 leaq(dst, Address(dst, src, Address::times_8, 0));
6030 } else {
6031 addq(dst, src);
6032 }
6033 } else {
6034 if (CompressedKlassPointers::base() != nullptr) {
6035 const intptr_t base_right_shifted =
6036 (intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
6037 movptr(dst, base_right_shifted);
6038 } else {
6039 xorq(dst, dst);
6040 }
6041 addq(dst, src);
6042 shlq(dst, CompressedKlassPointers::shift());
6043 }
6044 }
6045 BLOCK_COMMENT("} decode_and_move_klass_not_null");
6046 }
6047
6048 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6049 assert (UseCompressedOops, "should only be used for compressed headers");
6050 assert (Universe::heap() != nullptr, "java heap should be initialized");
6051 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6052 int oop_index = oop_recorder()->find_index(obj);
6053 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6054 mov_narrow_oop(dst, oop_index, rspec);
6055 }
6056
6057 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6058 assert (UseCompressedOops, "should only be used for compressed headers");
6059 assert (Universe::heap() != nullptr, "java heap should be initialized");
6060 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6061 int oop_index = oop_recorder()->find_index(obj);
6062 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6063 mov_narrow_oop(dst, oop_index, rspec);
6064 }
6065
6066 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6067 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6068 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6069 int klass_index = oop_recorder()->find_index(k);
6070 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6071 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6072 }
6073
6074 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6075 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6076 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6077 int klass_index = oop_recorder()->find_index(k);
6078 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6079 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6080 }
6081
6082 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6083 assert (UseCompressedOops, "should only be used for compressed headers");
6084 assert (Universe::heap() != nullptr, "java heap should be initialized");
6085 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6086 int oop_index = oop_recorder()->find_index(obj);
6087 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6088 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6089 }
6090
6091 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6092 assert (UseCompressedOops, "should only be used for compressed headers");
6093 assert (Universe::heap() != nullptr, "java heap should be initialized");
6094 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6095 int oop_index = oop_recorder()->find_index(obj);
6096 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6097 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6098 }
6099
6100 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6101 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6102 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6103 int klass_index = oop_recorder()->find_index(k);
6104 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6105 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6106 }
6107
6108 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6109 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6110 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6111 int klass_index = oop_recorder()->find_index(k);
6112 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6113 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6114 }
6115
6116 void MacroAssembler::reinit_heapbase() {
6117 if (UseCompressedOops) {
6118 if (Universe::heap() != nullptr) {
6119 if (CompressedOops::base() == nullptr) {
6120 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6121 } else {
6122 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6123 }
6124 } else {
6125 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6126 }
6127 }
6128 }
6129
6130 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6131 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6132 // An inline type might be returned. If fields are in registers we
6133 // need to allocate an inline type instance and initialize it with
6134 // the value of the fields.
6135 Label skip;
6136 // We only need a new buffered inline type if a new one is not returned
6137 testptr(rax, 1);
6138 jcc(Assembler::zero, skip);
6139 int call_offset = -1;
6140
6141 #ifdef _LP64
6142 // The following code is similar to allocate_instance but has some slight differences,
6143 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6144 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
6145 Label slow_case;
6146 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6147 mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
6148 if (vk != nullptr) {
6149 // Called from C1, where the return type is statically known.
6150 movptr(rbx, (intptr_t)vk->get_InlineKlass());
6151 jint lh = vk->layout_helper();
6152 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6153 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6154 tlab_allocate(rax, noreg, lh, r13, r14, slow_case);
6155 } else {
6156 jmp(slow_case);
6157 }
6158 } else {
6159 // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
6160 mov(rbx, rax);
6161 andptr(rbx, -2);
6162 if (UseTLAB) {
6163 movl(r14, Address(rbx, Klass::layout_helper_offset()));
6164 testl(r14, Klass::_lh_instance_slow_path_bit);
6165 jcc(Assembler::notZero, slow_case);
6166 tlab_allocate(rax, r14, 0, r13, r14, slow_case);
6167 } else {
6168 jmp(slow_case);
6169 }
6170 }
6171 if (UseTLAB) {
6172 // 2. Initialize buffered inline instance header
6173 Register buffer_obj = rax;
6174 Register klass = rbx;
6175 if (UseCompactObjectHeaders) {
6176 Register mark_word = r13;
6177 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
6178 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), mark_word);
6179 } else {
6180 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
6181 xorl(r13, r13);
6182 store_klass_gap(buffer_obj, r13);
6183 if (vk == nullptr) {
6184 // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
6185 mov(r13, klass);
6186 }
6187 store_klass(buffer_obj, klass, rscratch1);
6188 klass = r13;
6189 }
6190 // 3. Initialize its fields with an inline class specific handler
6191 if (vk != nullptr) {
6192 call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6193 } else {
6194 movptr(rbx, Address(klass, InlineKlass::adr_members_offset()));
6195 movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
6196 call(rbx);
6197 }
6198 jmp(skip);
6199 }
6200 bind(slow_case);
6201 // We failed to allocate a new inline type, fall back to a runtime
6202 // call. Some oop field may be live in some registers but we can't
6203 // tell. That runtime call will take care of preserving them
6204 // across a GC if there's one.
6205 mov(rax, rscratch1);
6206 #endif
6207
6208 if (from_interpreter) {
6209 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6210 } else {
6211 call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6212 call_offset = offset();
6213 }
6214
6215 bind(skip);
6216 return call_offset;
6217 }
6218
6219 // Move a value between registers/stack slots and update the reg_state
6220 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6221 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6222 if (reg_state[to->value()] == reg_written) {
6223 return true; // Already written
6224 }
6225 if (from != to && bt != T_VOID) {
6226 if (reg_state[to->value()] == reg_readonly) {
6227 return false; // Not yet writable
6228 }
6229 if (from->is_reg()) {
6230 if (to->is_reg()) {
6231 if (from->is_XMMRegister()) {
6232 if (bt == T_DOUBLE) {
6233 movdbl(to->as_XMMRegister(), from->as_XMMRegister());
6234 } else {
6235 assert(bt == T_FLOAT, "must be float");
6236 movflt(to->as_XMMRegister(), from->as_XMMRegister());
6237 }
6238 } else {
6239 movq(to->as_Register(), from->as_Register());
6240 }
6241 } else {
6242 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6243 Address to_addr = Address(rsp, st_off);
6244 if (from->is_XMMRegister()) {
6245 if (bt == T_DOUBLE) {
6246 movdbl(to_addr, from->as_XMMRegister());
6247 } else {
6248 assert(bt == T_FLOAT, "must be float");
6249 movflt(to_addr, from->as_XMMRegister());
6250 }
6251 } else {
6252 movq(to_addr, from->as_Register());
6253 }
6254 }
6255 } else {
6256 Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
6257 if (to->is_reg()) {
6258 if (to->is_XMMRegister()) {
6259 if (bt == T_DOUBLE) {
6260 movdbl(to->as_XMMRegister(), from_addr);
6261 } else {
6262 assert(bt == T_FLOAT, "must be float");
6263 movflt(to->as_XMMRegister(), from_addr);
6264 }
6265 } else {
6266 movq(to->as_Register(), from_addr);
6267 }
6268 } else {
6269 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6270 movq(r13, from_addr);
6271 movq(Address(rsp, st_off), r13);
6272 }
6273 }
6274 }
6275 // Update register states
6276 reg_state[from->value()] = reg_writable;
6277 reg_state[to->value()] = reg_written;
6278 return true;
6279 }
6280
6281 // Calculate the extra stack space required for packing or unpacking inline
6282 // args and adjust the stack pointer (see MacroAssembler::remove_frame).
6283 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6284 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
6285 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6286 assert(sp_inc > 0, "sanity");
6287 // Two additional slots to account for return address
6288 sp_inc += 2 * VMRegImpl::stack_slot_size;
6289
6290 push(rbp);
6291 subptr(rsp, sp_inc);
6292 #ifdef ASSERT
6293 movl(Address(rsp, 0), badRegWordVal);
6294 movl(Address(rsp, VMRegImpl::stack_slot_size), badRegWordVal);
6295 #endif
6296 return sp_inc + wordSize; // account for rbp space
6297 }
6298
6299 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
6300 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6301 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6302 RegState reg_state[]) {
6303 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6304 assert(from->is_valid(), "source must be valid");
6305 bool progress = false;
6306 #ifdef ASSERT
6307 const int start_offset = offset();
6308 #endif
6309
6310 Label L_null, L_notNull;
6311 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6312 Register tmp1 = r10;
6313 Register tmp2 = r13;
6314 Register fromReg = noreg;
6315 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, true);
6316 bool done = true;
6317 bool mark_done = true;
6318 VMReg toReg;
6319 BasicType bt;
6320 // Check if argument requires a null check
6321 bool null_check = false;
6322 VMReg nullCheckReg;
6323 while (stream.next(nullCheckReg, bt)) {
6324 if (sig->at(stream.sig_index())._offset == -1) {
6325 null_check = true;
6326 break;
6327 }
6328 }
6329 stream.reset(sig_index, to_index);
6330 while (stream.next(toReg, bt)) {
6331 assert(toReg->is_valid(), "destination must be valid");
6332 int idx = (int)toReg->value();
6333 if (reg_state[idx] == reg_readonly) {
6334 if (idx != from->value()) {
6335 mark_done = false;
6336 }
6337 done = false;
6338 continue;
6339 } else if (reg_state[idx] == reg_written) {
6340 continue;
6341 }
6342 assert(reg_state[idx] == reg_writable, "must be writable");
6343 reg_state[idx] = reg_written;
6344 progress = true;
6345
6346 if (fromReg == noreg) {
6347 if (from->is_reg()) {
6348 fromReg = from->as_Register();
6349 } else {
6350 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6351 movq(tmp1, Address(rsp, st_off));
6352 fromReg = tmp1;
6353 }
6354 if (null_check) {
6355 // Nullable inline type argument, emit null check
6356 testptr(fromReg, fromReg);
6357 jcc(Assembler::zero, L_null);
6358 }
6359 }
6360 int off = sig->at(stream.sig_index())._offset;
6361 if (off == -1) {
6362 assert(null_check, "Missing null check at");
6363 if (toReg->is_stack()) {
6364 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6365 movq(Address(rsp, st_off), 1);
6366 } else {
6367 movq(toReg->as_Register(), 1);
6368 }
6369 continue;
6370 }
6371 assert(off > 0, "offset in object should be positive");
6372 Address fromAddr = Address(fromReg, off);
6373 if (!toReg->is_XMMRegister()) {
6374 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
6375 if (is_reference_type(bt)) {
6376 load_heap_oop(dst, fromAddr);
6377 } else {
6378 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
6379 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
6380 }
6381 if (toReg->is_stack()) {
6382 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6383 movq(Address(rsp, st_off), dst);
6384 }
6385 } else if (bt == T_DOUBLE) {
6386 movdbl(toReg->as_XMMRegister(), fromAddr);
6387 } else {
6388 assert(bt == T_FLOAT, "must be float");
6389 movflt(toReg->as_XMMRegister(), fromAddr);
6390 }
6391 }
6392 if (progress && null_check) {
6393 if (done) {
6394 jmp(L_notNull);
6395 bind(L_null);
6396 // Set null marker to zero to signal that the argument is null.
6397 // Also set all fields to zero since the runtime requires a canonical
6398 // representation of a flat null.
6399 stream.reset(sig_index, to_index);
6400 while (stream.next(toReg, bt)) {
6401 if (toReg->is_stack()) {
6402 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6403 movq(Address(rsp, st_off), 0);
6404 } else if (toReg->is_XMMRegister()) {
6405 xorps(toReg->as_XMMRegister(), toReg->as_XMMRegister());
6406 } else {
6407 xorl(toReg->as_Register(), toReg->as_Register());
6408 }
6409 }
6410 bind(L_notNull);
6411 } else {
6412 bind(L_null);
6413 }
6414 }
6415
6416 sig_index = stream.sig_index();
6417 to_index = stream.regs_index();
6418
6419 if (mark_done && reg_state[from->value()] != reg_written) {
6420 // This is okay because no one else will write to that slot
6421 reg_state[from->value()] = reg_writable;
6422 }
6423 from_index--;
6424 assert(progress || (start_offset == offset()), "should not emit code");
6425 return done;
6426 }
6427
6428 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
6429 VMRegPair* from, int from_count, int& from_index, VMReg to,
6430 RegState reg_state[], Register val_array) {
6431 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
6432 assert(to->is_valid(), "destination must be valid");
6433
6434 if (reg_state[to->value()] == reg_written) {
6435 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6436 return true; // Already written
6437 }
6438
6439 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
6440 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
6441 Register val_obj_tmp = r11;
6442 Register from_reg_tmp = r14;
6443 Register tmp1 = r10;
6444 Register tmp2 = r13;
6445 Register tmp3 = rbx;
6446 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
6447
6448 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
6449
6450 if (reg_state[to->value()] == reg_readonly) {
6451 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
6452 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6453 return false; // Not yet writable
6454 }
6455 val_obj = val_obj_tmp;
6456 }
6457
6458 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
6459 load_heap_oop(val_obj, Address(val_array, index));
6460
6461 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
6462 VMReg fromReg;
6463 BasicType bt;
6464 Label L_null;
6465 while (stream.next(fromReg, bt)) {
6466 assert(fromReg->is_valid(), "source must be valid");
6467 reg_state[fromReg->value()] = reg_writable;
6468
6469 int off = sig->at(stream.sig_index())._offset;
6470 if (off == -1) {
6471 // Nullable inline type argument, emit null check
6472 Label L_notNull;
6473 if (fromReg->is_stack()) {
6474 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6475 testb(Address(rsp, ld_off), 1);
6476 } else {
6477 testb(fromReg->as_Register(), 1);
6478 }
6479 jcc(Assembler::notZero, L_notNull);
6480 movptr(val_obj, 0);
6481 jmp(L_null);
6482 bind(L_notNull);
6483 continue;
6484 }
6485
6486 assert(off > 0, "offset in object should be positive");
6487 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
6488
6489 // Pack the scalarized field into the value object.
6490 Address dst(val_obj, off);
6491 if (!fromReg->is_XMMRegister()) {
6492 Register src;
6493 if (fromReg->is_stack()) {
6494 src = from_reg_tmp;
6495 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6496 load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
6497 } else {
6498 src = fromReg->as_Register();
6499 }
6500 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
6501 if (is_reference_type(bt)) {
6502 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep val_obj valid.
6503 mov(tmp3, val_obj);
6504 Address dst_with_tmp3(tmp3, off);
6505 store_heap_oop(dst_with_tmp3, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
6506 } else {
6507 store_sized_value(dst, src, size_in_bytes);
6508 }
6509 } else if (bt == T_DOUBLE) {
6510 movdbl(dst, fromReg->as_XMMRegister());
6511 } else {
6512 assert(bt == T_FLOAT, "must be float");
6513 movflt(dst, fromReg->as_XMMRegister());
6514 }
6515 }
6516 bind(L_null);
6517 sig_index = stream.sig_index();
6518 from_index = stream.regs_index();
6519
6520 assert(reg_state[to->value()] == reg_writable, "must have already been read");
6521 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6522 assert(success, "to register must be writeable");
6523 return true;
6524 }
6525
6526 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6527 return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
6528 }
6529
6530 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
6531 assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6532 if (needs_stack_repair) {
6533 // The method has a scalarized entry point (where fields of value object arguments
6534 // are passed through registers and stack), and a non-scalarized entry point (where
6535 // value object arguments are given as oops). The non-scalarized entry point will
6536 // first load each field of value object arguments and store them in registers and on
6537 // the stack in a way compatible with the scalarized entry point. To do so, some extra
6538 // stack space might be reserved (if argument registers are not enough). On leaving the
6539 // method, this space must be freed.
6540 //
6541 // In case we used the non-scalarized entry point the stack looks like this:
6542 //
6543 // | Arguments from caller |
6544 // |---------------------------| <-- caller's SP
6545 // | Return address #1 |
6546 // | Saved RBP #1 |
6547 // |---------------------------|
6548 // | Extension space for |
6549 // | inline arg (un)packing |
6550 // |---------------------------| <-- start of this method's frame
6551 // | Return address #2 |
6552 // | Saved RBP #2 |
6553 // |---------------------------| <-- RBP (with -XX:+PreserveFramePointer)
6554 // | sp_inc |
6555 // | method locals |
6556 // |---------------------------| <-- SP
6557 //
6558 // Space for the return pc and saved rbp is reserved twice. But only the #1 copies
6559 // contain the real values of return pc and saved rbp. The #2 copies are not reliable
6560 // and should not be used. They are mostly needed to add space between the extension
6561 // space and the locals, as there would be between the real arguments and the locals
6562 // if we don't need to do unpacking (from the scalarized entry point).
6563 //
6564 // When leaving, one must load RBP #1 into RBP, and use the copy #1 of the return address,
6565 // while keeping in mind that from the scalarized entry point, there will be only one
6566 // copy. Indeed, in the case we used the scalarized calling convention, the stack looks like this:
6567 //
6568 // | Arguments from caller |
6569 // |---------------------------| <-- caller's SP
6570 // | Return address |
6571 // | Saved RBP |
6572 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer)
6573 // | sp_inc |
6574 // | method locals |
6575 // |---------------------------| <-- SP
6576 //
6577 // The sp_inc stack slot holds the total size of the frame, including the extension
6578 // space and copies #2 of the return address and the saved RBP (but never the copies
6579 // #1 of the return address and saved RBP). That is how to find the copies #1 of the
6580 // return address and saved rbp. This size is expressed in bytes. Be careful when using
6581 // it from C++ in pointer arithmetic you might need to divide it by wordSize.
6582
6583 // The stack increment resides just below the saved rbp
6584 addq(rsp, Address(rsp, initial_framesize - wordSize));
6585 pop(rbp);
6586 } else {
6587 if (initial_framesize > 0) {
6588 addq(rsp, initial_framesize);
6589 }
6590 pop(rbp);
6591 }
6592 }
6593
6594 #if COMPILER2_OR_JVMCI
6595
6596 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6597 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
6598 // cnt - number of qwords (8-byte words).
6599 // base - start address, qword aligned.
6600 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6601 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6602 if (use64byteVector) {
6603 evpbroadcastq(xtmp, val, AVX_512bit);
6604 } else if (MaxVectorSize >= 32) {
6605 movdq(xtmp, val);
6606 punpcklqdq(xtmp, xtmp);
6607 vinserti128_high(xtmp, xtmp);
6608 } else {
6609 movdq(xtmp, val);
6610 punpcklqdq(xtmp, xtmp);
6611 }
6612 jmp(L_zero_64_bytes);
6613
6614 BIND(L_loop);
6615 if (MaxVectorSize >= 32) {
6616 fill64(base, 0, xtmp, use64byteVector);
6617 } else {
6618 movdqu(Address(base, 0), xtmp);
6619 movdqu(Address(base, 16), xtmp);
6620 movdqu(Address(base, 32), xtmp);
6621 movdqu(Address(base, 48), xtmp);
6622 }
6623 addptr(base, 64);
6624
6625 BIND(L_zero_64_bytes);
6626 subptr(cnt, 8);
6627 jccb(Assembler::greaterEqual, L_loop);
6628
6629 // Copy trailing 64 bytes
6630 if (use64byteVector) {
6631 addptr(cnt, 8);
6632 jccb(Assembler::equal, L_end);
6633 fill64_masked(3, base, 0, xtmp, mask, cnt, val, true);
6634 jmp(L_end);
6635 } else {
6636 addptr(cnt, 4);
6637 jccb(Assembler::less, L_tail);
6638 if (MaxVectorSize >= 32) {
6639 vmovdqu(Address(base, 0), xtmp);
6640 } else {
6641 movdqu(Address(base, 0), xtmp);
6642 movdqu(Address(base, 16), xtmp);
6643 }
6644 }
6645 addptr(base, 32);
6646 subptr(cnt, 4);
6647
6648 BIND(L_tail);
6649 addptr(cnt, 4);
6650 jccb(Assembler::lessEqual, L_end);
6651 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6652 fill32_masked(3, base, 0, xtmp, mask, cnt, val);
6653 } else {
6654 decrement(cnt);
6655
6656 BIND(L_sloop);
6657 movq(Address(base, 0), xtmp);
6658 addptr(base, 8);
6659 decrement(cnt);
6660 jccb(Assembler::greaterEqual, L_sloop);
6661 }
6662 BIND(L_end);
6663 }
6664
6665 // Clearing constant sized memory using YMM/ZMM registers.
6666 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6667 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6668 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6669
6670 int vector64_count = (cnt & (~0x7)) >> 3;
6671 cnt = cnt & 0x7;
6672 const int fill64_per_loop = 4;
6673 const int max_unrolled_fill64 = 8;
6674
6675 // 64 byte initialization loop.
6676 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6677 int start64 = 0;
6678 if (vector64_count > max_unrolled_fill64) {
6679 Label LOOP;
6680 Register index = rtmp;
6681
6682 start64 = vector64_count - (vector64_count % fill64_per_loop);
6683
6684 movl(index, 0);
6685 BIND(LOOP);
6686 for (int i = 0; i < fill64_per_loop; i++) {
6687 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6688 }
6689 addl(index, fill64_per_loop * 64);
6690 cmpl(index, start64 * 64);
6691 jccb(Assembler::less, LOOP);
6692 }
6693 for (int i = start64; i < vector64_count; i++) {
6694 fill64(base, i * 64, xtmp, use64byteVector);
6695 }
6696
6697 // Clear remaining 64 byte tail.
6698 int disp = vector64_count * 64;
6699 if (cnt) {
6700 switch (cnt) {
6701 case 1:
6702 movq(Address(base, disp), xtmp);
6703 break;
6704 case 2:
6705 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6706 break;
6707 case 3:
6708 movl(rtmp, 0x7);
6709 kmovwl(mask, rtmp);
6710 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6711 break;
6712 case 4:
6713 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6714 break;
6715 case 5:
6716 if (use64byteVector) {
6717 movl(rtmp, 0x1F);
6718 kmovwl(mask, rtmp);
6719 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6720 } else {
6721 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6722 movq(Address(base, disp + 32), xtmp);
6723 }
6724 break;
6725 case 6:
6726 if (use64byteVector) {
6727 movl(rtmp, 0x3F);
6728 kmovwl(mask, rtmp);
6729 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6730 } else {
6731 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6732 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6733 }
6734 break;
6735 case 7:
6736 if (use64byteVector) {
6737 movl(rtmp, 0x7F);
6738 kmovwl(mask, rtmp);
6739 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6740 } else {
6741 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6742 movl(rtmp, 0x7);
6743 kmovwl(mask, rtmp);
6744 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6745 }
6746 break;
6747 default:
6748 fatal("Unexpected length : %d\n",cnt);
6749 break;
6750 }
6751 }
6752 }
6753
6754 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
6755 bool is_large, bool word_copy_only, KRegister mask) {
6756 // cnt - number of qwords (8-byte words).
6757 // base - start address, qword aligned.
6758 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6759 assert(base==rdi, "base register must be edi for rep stos");
6760 assert(val==rax, "val register must be eax for rep stos");
6761 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6762 assert(InitArrayShortSize % BytesPerLong == 0,
6763 "InitArrayShortSize should be the multiple of BytesPerLong");
6764
6765 Label DONE;
6766
6767 if (!is_large) {
6768 Label LOOP, LONG;
6769 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6770 jccb(Assembler::greater, LONG);
6771
6772 decrement(cnt);
6773 jccb(Assembler::negative, DONE); // Zero length
6774
6775 // Use individual pointer-sized stores for small counts:
6776 BIND(LOOP);
6777 movptr(Address(base, cnt, Address::times_ptr), val);
6778 decrement(cnt);
6779 jccb(Assembler::greaterEqual, LOOP);
6780 jmpb(DONE);
6781
6782 BIND(LONG);
6783 }
6784
6785 // Use longer rep-prefixed ops for non-small counts:
6786 if (UseFastStosb && !word_copy_only) {
6787 shlptr(cnt, 3); // convert to number of bytes
6788 rep_stosb();
6789 } else if (UseXMMForObjInit) {
6790 xmm_clear_mem(base, cnt, val, xtmp, mask);
6791 } else {
6792 rep_stos();
6793 }
6794
6795 BIND(DONE);
6796 }
6797
6798 #endif //COMPILER2_OR_JVMCI
6799
6800
6801 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6802 Register to, Register value, Register count,
6803 Register rtmp, XMMRegister xtmp) {
6804 ShortBranchVerifier sbv(this);
6805 assert_different_registers(to, value, count, rtmp);
6806 Label L_exit;
6807 Label L_fill_2_bytes, L_fill_4_bytes;
6808
6809 #if defined(COMPILER2)
6810 if(MaxVectorSize >=32 &&
6811 VM_Version::supports_avx512vlbw() &&
6812 VM_Version::supports_bmi2()) {
6813 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6814 return;
6815 }
6816 #endif
6817
6818 int shift = -1;
6819 switch (t) {
6820 case T_BYTE:
6821 shift = 2;
6822 break;
6823 case T_SHORT:
6824 shift = 1;
6825 break;
6826 case T_INT:
6827 shift = 0;
6828 break;
6829 default: ShouldNotReachHere();
6830 }
6831
6832 if (t == T_BYTE) {
6833 andl(value, 0xff);
6834 movl(rtmp, value);
6835 shll(rtmp, 8);
6836 orl(value, rtmp);
6837 }
6838 if (t == T_SHORT) {
6839 andl(value, 0xffff);
6840 }
6841 if (t == T_BYTE || t == T_SHORT) {
6842 movl(rtmp, value);
6843 shll(rtmp, 16);
6844 orl(value, rtmp);
6845 }
6846
6847 cmpptr(count, 8 << shift); // Short arrays (< 32 bytes) fill by element
6848 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6849 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6850 Label L_skip_align2;
6851 // align source address at 4 bytes address boundary
6852 if (t == T_BYTE) {
6853 Label L_skip_align1;
6854 // One byte misalignment happens only for byte arrays
6855 testptr(to, 1);
6856 jccb(Assembler::zero, L_skip_align1);
6857 movb(Address(to, 0), value);
6858 increment(to);
6859 decrement(count);
6860 BIND(L_skip_align1);
6861 }
6862 // Two bytes misalignment happens only for byte and short (char) arrays
6863 testptr(to, 2);
6864 jccb(Assembler::zero, L_skip_align2);
6865 movw(Address(to, 0), value);
6866 addptr(to, 2);
6867 subptr(count, 1<<(shift-1));
6868 BIND(L_skip_align2);
6869 }
6870 {
6871 Label L_fill_32_bytes;
6872 if (!UseUnalignedLoadStores) {
6873 // align to 8 bytes, we know we are 4 byte aligned to start
6874 testptr(to, 4);
6875 jccb(Assembler::zero, L_fill_32_bytes);
6876 movl(Address(to, 0), value);
6877 addptr(to, 4);
6878 subptr(count, 1<<shift);
6879 }
6880 BIND(L_fill_32_bytes);
6881 {
6882 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6883 movdl(xtmp, value);
6884 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6885 Label L_check_fill_32_bytes;
6886 if (UseAVX > 2) {
6887 // Fill 64-byte chunks
6888 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6889
6890 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6891 cmpptr(count, VM_Version::avx3_threshold());
6892 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6893
6894 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6895
6896 subptr(count, 16 << shift);
6897 jcc(Assembler::less, L_check_fill_32_bytes);
6898 align(16);
6899
6900 BIND(L_fill_64_bytes_loop_avx3);
6901 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6902 addptr(to, 64);
6903 subptr(count, 16 << shift);
6904 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6905 jmpb(L_check_fill_32_bytes);
6906
6907 BIND(L_check_fill_64_bytes_avx2);
6908 }
6909 // Fill 64-byte chunks
6910 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6911
6912 subptr(count, 16 << shift);
6913 jcc(Assembler::less, L_check_fill_32_bytes);
6914
6915 // align data for 64-byte chunks
6916 Label L_fill_64_bytes_loop, L_align_64_bytes_loop;
6917 if (EnableX86ECoreOpts) {
6918 // align 'big' arrays to cache lines to minimize split_stores
6919 cmpptr(count, 96 << shift);
6920 jcc(Assembler::below, L_fill_64_bytes_loop);
6921
6922 // Find the bytes needed for alignment
6923 movptr(rtmp, to);
6924 andptr(rtmp, 0x1c);
6925 jcc(Assembler::zero, L_fill_64_bytes_loop);
6926 negptr(rtmp); // number of bytes to fill 32-rtmp. it filled by 2 mov by 32
6927 addptr(rtmp, 32);
6928 shrptr(rtmp, 2 - shift);// get number of elements from bytes
6929 subptr(count, rtmp); // adjust count by number of elements
6930
6931 align(16);
6932 BIND(L_align_64_bytes_loop);
6933 movdl(Address(to, 0), xtmp);
6934 addptr(to, 4);
6935 subptr(rtmp, 1 << shift);
6936 jcc(Assembler::greater, L_align_64_bytes_loop);
6937 }
6938
6939 align(16);
6940 BIND(L_fill_64_bytes_loop);
6941 vmovdqu(Address(to, 0), xtmp);
6942 vmovdqu(Address(to, 32), xtmp);
6943 addptr(to, 64);
6944 subptr(count, 16 << shift);
6945 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6946
6947 align(16);
6948 BIND(L_check_fill_32_bytes);
6949 addptr(count, 8 << shift);
6950 jccb(Assembler::less, L_check_fill_8_bytes);
6951 vmovdqu(Address(to, 0), xtmp);
6952 addptr(to, 32);
6953 subptr(count, 8 << shift);
6954
6955 BIND(L_check_fill_8_bytes);
6956 // clean upper bits of YMM registers
6957 movdl(xtmp, value);
6958 pshufd(xtmp, xtmp, 0);
6959 } else {
6960 // Fill 32-byte chunks
6961 pshufd(xtmp, xtmp, 0);
6962
6963 subptr(count, 8 << shift);
6964 jcc(Assembler::less, L_check_fill_8_bytes);
6965 align(16);
6966
6967 BIND(L_fill_32_bytes_loop);
6968
6969 if (UseUnalignedLoadStores) {
6970 movdqu(Address(to, 0), xtmp);
6971 movdqu(Address(to, 16), xtmp);
6972 } else {
6973 movq(Address(to, 0), xtmp);
6974 movq(Address(to, 8), xtmp);
6975 movq(Address(to, 16), xtmp);
6976 movq(Address(to, 24), xtmp);
6977 }
6978
6979 addptr(to, 32);
6980 subptr(count, 8 << shift);
6981 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6982
6983 BIND(L_check_fill_8_bytes);
6984 }
6985 addptr(count, 8 << shift);
6986 jccb(Assembler::zero, L_exit);
6987 jmpb(L_fill_8_bytes);
6988
6989 //
6990 // length is too short, just fill qwords
6991 //
6992 align(16);
6993 BIND(L_fill_8_bytes_loop);
6994 movq(Address(to, 0), xtmp);
6995 addptr(to, 8);
6996 BIND(L_fill_8_bytes);
6997 subptr(count, 1 << (shift + 1));
6998 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6999 }
7000 }
7001
7002 Label L_fill_4_bytes_loop;
7003 testl(count, 1 << shift);
7004 jccb(Assembler::zero, L_fill_2_bytes);
7005
7006 align(16);
7007 BIND(L_fill_4_bytes_loop);
7008 movl(Address(to, 0), value);
7009 addptr(to, 4);
7010
7011 BIND(L_fill_4_bytes);
7012 subptr(count, 1 << shift);
7013 jccb(Assembler::greaterEqual, L_fill_4_bytes_loop);
7014
7015 if (t == T_BYTE || t == T_SHORT) {
7016 Label L_fill_byte;
7017 BIND(L_fill_2_bytes);
7018 // fill trailing 2 bytes
7019 testl(count, 1<<(shift-1));
7020 jccb(Assembler::zero, L_fill_byte);
7021 movw(Address(to, 0), value);
7022 if (t == T_BYTE) {
7023 addptr(to, 2);
7024 BIND(L_fill_byte);
7025 // fill trailing byte
7026 testl(count, 1);
7027 jccb(Assembler::zero, L_exit);
7028 movb(Address(to, 0), value);
7029 } else {
7030 BIND(L_fill_byte);
7031 }
7032 } else {
7033 BIND(L_fill_2_bytes);
7034 }
7035 BIND(L_exit);
7036 }
7037
7038 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
7039 switch(type) {
7040 case T_BYTE:
7041 case T_BOOLEAN:
7042 evpbroadcastb(dst, src, vector_len);
7043 break;
7044 case T_SHORT:
7045 case T_CHAR:
7046 evpbroadcastw(dst, src, vector_len);
7047 break;
7048 case T_INT:
7049 case T_FLOAT:
7050 evpbroadcastd(dst, src, vector_len);
7051 break;
7052 case T_LONG:
7053 case T_DOUBLE:
7054 evpbroadcastq(dst, src, vector_len);
7055 break;
7056 default:
7057 fatal("Unhandled type : %s", type2name(type));
7058 break;
7059 }
7060 }
7061
7062 // Encode given char[]/byte[] to byte[] in ISO_8859_1 or ASCII
7063 //
7064 // @IntrinsicCandidate
7065 // int sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(
7066 // char[] sa, int sp, byte[] da, int dp, int len) {
7067 // int i = 0;
7068 // for (; i < len; i++) {
7069 // char c = sa[sp++];
7070 // if (c > '\u00FF')
7071 // break;
7072 // da[dp++] = (byte) c;
7073 // }
7074 // return i;
7075 // }
7076 //
7077 // @IntrinsicCandidate
7078 // int java.lang.StringCoding.encodeISOArray0(
7079 // byte[] sa, int sp, byte[] da, int dp, int len) {
7080 // int i = 0;
7081 // for (; i < len; i++) {
7082 // char c = StringUTF16.getChar(sa, sp++);
7083 // if (c > '\u00FF')
7084 // break;
7085 // da[dp++] = (byte) c;
7086 // }
7087 // return i;
7088 // }
7089 //
7090 // @IntrinsicCandidate
7091 // int java.lang.StringCoding.encodeAsciiArray0(
7092 // char[] sa, int sp, byte[] da, int dp, int len) {
7093 // int i = 0;
7094 // for (; i < len; i++) {
7095 // char c = sa[sp++];
7096 // if (c >= '\u0080')
7097 // break;
7098 // da[dp++] = (byte) c;
7099 // }
7100 // return i;
7101 // }
7102 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7103 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7104 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7105 Register tmp5, Register result, bool ascii) {
7106
7107 // rsi: src
7108 // rdi: dst
7109 // rdx: len
7110 // rcx: tmp5
7111 // rax: result
7112 ShortBranchVerifier sbv(this);
7113 assert_different_registers(src, dst, len, tmp5, result);
7114 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7115
7116 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
7117 int short_mask = ascii ? 0xff80 : 0xff00;
7118
7119 // set result
7120 xorl(result, result);
7121 // check for zero length
7122 testl(len, len);
7123 jcc(Assembler::zero, L_done);
7124
7125 movl(result, len);
7126
7127 // Setup pointers
7128 lea(src, Address(src, len, Address::times_2)); // char[]
7129 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7130 negptr(len);
7131
7132 if (UseSSE42Intrinsics || UseAVX >= 2) {
7133 Label L_copy_8_chars, L_copy_8_chars_exit;
7134 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7135
7136 if (UseAVX >= 2) {
7137 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7138 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7139 movdl(tmp1Reg, tmp5);
7140 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7141 jmp(L_chars_32_check);
7142
7143 bind(L_copy_32_chars);
7144 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7145 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7146 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7147 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7148 jccb(Assembler::notZero, L_copy_32_chars_exit);
7149 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7150 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7151 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7152
7153 bind(L_chars_32_check);
7154 addptr(len, 32);
7155 jcc(Assembler::lessEqual, L_copy_32_chars);
7156
7157 bind(L_copy_32_chars_exit);
7158 subptr(len, 16);
7159 jccb(Assembler::greater, L_copy_16_chars_exit);
7160
7161 } else if (UseSSE42Intrinsics) {
7162 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7163 movdl(tmp1Reg, tmp5);
7164 pshufd(tmp1Reg, tmp1Reg, 0);
7165 jmpb(L_chars_16_check);
7166 }
7167
7168 bind(L_copy_16_chars);
7169 if (UseAVX >= 2) {
7170 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7171 vptest(tmp2Reg, tmp1Reg);
7172 jcc(Assembler::notZero, L_copy_16_chars_exit);
7173 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7174 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7175 } else {
7176 if (UseAVX > 0) {
7177 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7178 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7179 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7180 } else {
7181 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7182 por(tmp2Reg, tmp3Reg);
7183 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7184 por(tmp2Reg, tmp4Reg);
7185 }
7186 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7187 jccb(Assembler::notZero, L_copy_16_chars_exit);
7188 packuswb(tmp3Reg, tmp4Reg);
7189 }
7190 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7191
7192 bind(L_chars_16_check);
7193 addptr(len, 16);
7194 jcc(Assembler::lessEqual, L_copy_16_chars);
7195
7196 bind(L_copy_16_chars_exit);
7197 if (UseAVX >= 2) {
7198 // clean upper bits of YMM registers
7199 vpxor(tmp2Reg, tmp2Reg);
7200 vpxor(tmp3Reg, tmp3Reg);
7201 vpxor(tmp4Reg, tmp4Reg);
7202 movdl(tmp1Reg, tmp5);
7203 pshufd(tmp1Reg, tmp1Reg, 0);
7204 }
7205 subptr(len, 8);
7206 jccb(Assembler::greater, L_copy_8_chars_exit);
7207
7208 bind(L_copy_8_chars);
7209 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7210 ptest(tmp3Reg, tmp1Reg);
7211 jccb(Assembler::notZero, L_copy_8_chars_exit);
7212 packuswb(tmp3Reg, tmp1Reg);
7213 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7214 addptr(len, 8);
7215 jccb(Assembler::lessEqual, L_copy_8_chars);
7216
7217 bind(L_copy_8_chars_exit);
7218 subptr(len, 8);
7219 jccb(Assembler::zero, L_done);
7220 }
7221
7222 bind(L_copy_1_char);
7223 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7224 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7225 jccb(Assembler::notZero, L_copy_1_char_exit);
7226 movb(Address(dst, len, Address::times_1, 0), tmp5);
7227 addptr(len, 1);
7228 jccb(Assembler::less, L_copy_1_char);
7229
7230 bind(L_copy_1_char_exit);
7231 addptr(result, len); // len is negative count of not processed elements
7232
7233 bind(L_done);
7234 }
7235
7236 /**
7237 * Helper for multiply_to_len().
7238 */
7239 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7240 addq(dest_lo, src1);
7241 adcq(dest_hi, 0);
7242 addq(dest_lo, src2);
7243 adcq(dest_hi, 0);
7244 }
7245
7246 /**
7247 * Multiply 64 bit by 64 bit first loop.
7248 */
7249 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7250 Register y, Register y_idx, Register z,
7251 Register carry, Register product,
7252 Register idx, Register kdx) {
7253 //
7254 // jlong carry, x[], y[], z[];
7255 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7256 // huge_128 product = y[idx] * x[xstart] + carry;
7257 // z[kdx] = (jlong)product;
7258 // carry = (jlong)(product >>> 64);
7259 // }
7260 // z[xstart] = carry;
7261 //
7262
7263 Label L_first_loop, L_first_loop_exit;
7264 Label L_one_x, L_one_y, L_multiply;
7265
7266 decrementl(xstart);
7267 jcc(Assembler::negative, L_one_x);
7268
7269 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7270 rorq(x_xstart, 32); // convert big-endian to little-endian
7271
7272 bind(L_first_loop);
7273 decrementl(idx);
7274 jcc(Assembler::negative, L_first_loop_exit);
7275 decrementl(idx);
7276 jcc(Assembler::negative, L_one_y);
7277 movq(y_idx, Address(y, idx, Address::times_4, 0));
7278 rorq(y_idx, 32); // convert big-endian to little-endian
7279 bind(L_multiply);
7280 movq(product, x_xstart);
7281 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7282 addq(product, carry);
7283 adcq(rdx, 0);
7284 subl(kdx, 2);
7285 movl(Address(z, kdx, Address::times_4, 4), product);
7286 shrq(product, 32);
7287 movl(Address(z, kdx, Address::times_4, 0), product);
7288 movq(carry, rdx);
7289 jmp(L_first_loop);
7290
7291 bind(L_one_y);
7292 movl(y_idx, Address(y, 0));
7293 jmp(L_multiply);
7294
7295 bind(L_one_x);
7296 movl(x_xstart, Address(x, 0));
7297 jmp(L_first_loop);
7298
7299 bind(L_first_loop_exit);
7300 }
7301
7302 /**
7303 * Multiply 64 bit by 64 bit and add 128 bit.
7304 */
7305 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7306 Register yz_idx, Register idx,
7307 Register carry, Register product, int offset) {
7308 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7309 // z[kdx] = (jlong)product;
7310
7311 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7312 rorq(yz_idx, 32); // convert big-endian to little-endian
7313 movq(product, x_xstart);
7314 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7315 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7316 rorq(yz_idx, 32); // convert big-endian to little-endian
7317
7318 add2_with_carry(rdx, product, carry, yz_idx);
7319
7320 movl(Address(z, idx, Address::times_4, offset+4), product);
7321 shrq(product, 32);
7322 movl(Address(z, idx, Address::times_4, offset), product);
7323
7324 }
7325
7326 /**
7327 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7328 */
7329 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7330 Register yz_idx, Register idx, Register jdx,
7331 Register carry, Register product,
7332 Register carry2) {
7333 // jlong carry, x[], y[], z[];
7334 // int kdx = ystart+1;
7335 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7336 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7337 // z[kdx+idx+1] = (jlong)product;
7338 // jlong carry2 = (jlong)(product >>> 64);
7339 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7340 // z[kdx+idx] = (jlong)product;
7341 // carry = (jlong)(product >>> 64);
7342 // }
7343 // idx += 2;
7344 // if (idx > 0) {
7345 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7346 // z[kdx+idx] = (jlong)product;
7347 // carry = (jlong)(product >>> 64);
7348 // }
7349 //
7350
7351 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7352
7353 movl(jdx, idx);
7354 andl(jdx, 0xFFFFFFFC);
7355 shrl(jdx, 2);
7356
7357 bind(L_third_loop);
7358 subl(jdx, 1);
7359 jcc(Assembler::negative, L_third_loop_exit);
7360 subl(idx, 4);
7361
7362 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7363 movq(carry2, rdx);
7364
7365 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7366 movq(carry, rdx);
7367 jmp(L_third_loop);
7368
7369 bind (L_third_loop_exit);
7370
7371 andl (idx, 0x3);
7372 jcc(Assembler::zero, L_post_third_loop_done);
7373
7374 Label L_check_1;
7375 subl(idx, 2);
7376 jcc(Assembler::negative, L_check_1);
7377
7378 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7379 movq(carry, rdx);
7380
7381 bind (L_check_1);
7382 addl (idx, 0x2);
7383 andl (idx, 0x1);
7384 subl(idx, 1);
7385 jcc(Assembler::negative, L_post_third_loop_done);
7386
7387 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7388 movq(product, x_xstart);
7389 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7390 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7391
7392 add2_with_carry(rdx, product, yz_idx, carry);
7393
7394 movl(Address(z, idx, Address::times_4, 0), product);
7395 shrq(product, 32);
7396
7397 shlq(rdx, 32);
7398 orq(product, rdx);
7399 movq(carry, product);
7400
7401 bind(L_post_third_loop_done);
7402 }
7403
7404 /**
7405 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7406 *
7407 */
7408 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7409 Register carry, Register carry2,
7410 Register idx, Register jdx,
7411 Register yz_idx1, Register yz_idx2,
7412 Register tmp, Register tmp3, Register tmp4) {
7413 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7414
7415 // jlong carry, x[], y[], z[];
7416 // int kdx = ystart+1;
7417 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7418 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7419 // jlong carry2 = (jlong)(tmp3 >>> 64);
7420 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7421 // carry = (jlong)(tmp4 >>> 64);
7422 // z[kdx+idx+1] = (jlong)tmp3;
7423 // z[kdx+idx] = (jlong)tmp4;
7424 // }
7425 // idx += 2;
7426 // if (idx > 0) {
7427 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7428 // z[kdx+idx] = (jlong)yz_idx1;
7429 // carry = (jlong)(yz_idx1 >>> 64);
7430 // }
7431 //
7432
7433 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7434
7435 movl(jdx, idx);
7436 andl(jdx, 0xFFFFFFFC);
7437 shrl(jdx, 2);
7438
7439 bind(L_third_loop);
7440 subl(jdx, 1);
7441 jcc(Assembler::negative, L_third_loop_exit);
7442 subl(idx, 4);
7443
7444 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7445 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7446 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7447 rorxq(yz_idx2, yz_idx2, 32);
7448
7449 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7450 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7451
7452 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7453 rorxq(yz_idx1, yz_idx1, 32);
7454 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7455 rorxq(yz_idx2, yz_idx2, 32);
7456
7457 if (VM_Version::supports_adx()) {
7458 adcxq(tmp3, carry);
7459 adoxq(tmp3, yz_idx1);
7460
7461 adcxq(tmp4, tmp);
7462 adoxq(tmp4, yz_idx2);
7463
7464 movl(carry, 0); // does not affect flags
7465 adcxq(carry2, carry);
7466 adoxq(carry2, carry);
7467 } else {
7468 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7469 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7470 }
7471 movq(carry, carry2);
7472
7473 movl(Address(z, idx, Address::times_4, 12), tmp3);
7474 shrq(tmp3, 32);
7475 movl(Address(z, idx, Address::times_4, 8), tmp3);
7476
7477 movl(Address(z, idx, Address::times_4, 4), tmp4);
7478 shrq(tmp4, 32);
7479 movl(Address(z, idx, Address::times_4, 0), tmp4);
7480
7481 jmp(L_third_loop);
7482
7483 bind (L_third_loop_exit);
7484
7485 andl (idx, 0x3);
7486 jcc(Assembler::zero, L_post_third_loop_done);
7487
7488 Label L_check_1;
7489 subl(idx, 2);
7490 jcc(Assembler::negative, L_check_1);
7491
7492 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7493 rorxq(yz_idx1, yz_idx1, 32);
7494 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7495 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7496 rorxq(yz_idx2, yz_idx2, 32);
7497
7498 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7499
7500 movl(Address(z, idx, Address::times_4, 4), tmp3);
7501 shrq(tmp3, 32);
7502 movl(Address(z, idx, Address::times_4, 0), tmp3);
7503 movq(carry, tmp4);
7504
7505 bind (L_check_1);
7506 addl (idx, 0x2);
7507 andl (idx, 0x1);
7508 subl(idx, 1);
7509 jcc(Assembler::negative, L_post_third_loop_done);
7510 movl(tmp4, Address(y, idx, Address::times_4, 0));
7511 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7512 movl(tmp4, Address(z, idx, Address::times_4, 0));
7513
7514 add2_with_carry(carry2, tmp3, tmp4, carry);
7515
7516 movl(Address(z, idx, Address::times_4, 0), tmp3);
7517 shrq(tmp3, 32);
7518
7519 shlq(carry2, 32);
7520 orq(tmp3, carry2);
7521 movq(carry, tmp3);
7522
7523 bind(L_post_third_loop_done);
7524 }
7525
7526 /**
7527 * Code for BigInteger::multiplyToLen() intrinsic.
7528 *
7529 * rdi: x
7530 * rax: xlen
7531 * rsi: y
7532 * rcx: ylen
7533 * r8: z
7534 * r11: tmp0
7535 * r12: tmp1
7536 * r13: tmp2
7537 * r14: tmp3
7538 * r15: tmp4
7539 * rbx: tmp5
7540 *
7541 */
7542 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7543 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7544 ShortBranchVerifier sbv(this);
7545 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7546
7547 push(tmp0);
7548 push(tmp1);
7549 push(tmp2);
7550 push(tmp3);
7551 push(tmp4);
7552 push(tmp5);
7553
7554 push(xlen);
7555
7556 const Register idx = tmp1;
7557 const Register kdx = tmp2;
7558 const Register xstart = tmp3;
7559
7560 const Register y_idx = tmp4;
7561 const Register carry = tmp5;
7562 const Register product = xlen;
7563 const Register x_xstart = tmp0;
7564
7565 // First Loop.
7566 //
7567 // final static long LONG_MASK = 0xffffffffL;
7568 // int xstart = xlen - 1;
7569 // int ystart = ylen - 1;
7570 // long carry = 0;
7571 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7572 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7573 // z[kdx] = (int)product;
7574 // carry = product >>> 32;
7575 // }
7576 // z[xstart] = (int)carry;
7577 //
7578
7579 movl(idx, ylen); // idx = ylen;
7580 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7581 xorq(carry, carry); // carry = 0;
7582
7583 Label L_done;
7584
7585 movl(xstart, xlen);
7586 decrementl(xstart);
7587 jcc(Assembler::negative, L_done);
7588
7589 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7590
7591 Label L_second_loop;
7592 testl(kdx, kdx);
7593 jcc(Assembler::zero, L_second_loop);
7594
7595 Label L_carry;
7596 subl(kdx, 1);
7597 jcc(Assembler::zero, L_carry);
7598
7599 movl(Address(z, kdx, Address::times_4, 0), carry);
7600 shrq(carry, 32);
7601 subl(kdx, 1);
7602
7603 bind(L_carry);
7604 movl(Address(z, kdx, Address::times_4, 0), carry);
7605
7606 // Second and third (nested) loops.
7607 //
7608 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7609 // carry = 0;
7610 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7611 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7612 // (z[k] & LONG_MASK) + carry;
7613 // z[k] = (int)product;
7614 // carry = product >>> 32;
7615 // }
7616 // z[i] = (int)carry;
7617 // }
7618 //
7619 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7620
7621 const Register jdx = tmp1;
7622
7623 bind(L_second_loop);
7624 xorl(carry, carry); // carry = 0;
7625 movl(jdx, ylen); // j = ystart+1
7626
7627 subl(xstart, 1); // i = xstart-1;
7628 jcc(Assembler::negative, L_done);
7629
7630 push (z);
7631
7632 Label L_last_x;
7633 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7634 subl(xstart, 1); // i = xstart-1;
7635 jcc(Assembler::negative, L_last_x);
7636
7637 if (UseBMI2Instructions) {
7638 movq(rdx, Address(x, xstart, Address::times_4, 0));
7639 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7640 } else {
7641 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7642 rorq(x_xstart, 32); // convert big-endian to little-endian
7643 }
7644
7645 Label L_third_loop_prologue;
7646 bind(L_third_loop_prologue);
7647
7648 push (x);
7649 push (xstart);
7650 push (ylen);
7651
7652
7653 if (UseBMI2Instructions) {
7654 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7655 } else { // !UseBMI2Instructions
7656 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7657 }
7658
7659 pop(ylen);
7660 pop(xlen);
7661 pop(x);
7662 pop(z);
7663
7664 movl(tmp3, xlen);
7665 addl(tmp3, 1);
7666 movl(Address(z, tmp3, Address::times_4, 0), carry);
7667 subl(tmp3, 1);
7668 jccb(Assembler::negative, L_done);
7669
7670 shrq(carry, 32);
7671 movl(Address(z, tmp3, Address::times_4, 0), carry);
7672 jmp(L_second_loop);
7673
7674 // Next infrequent code is moved outside loops.
7675 bind(L_last_x);
7676 if (UseBMI2Instructions) {
7677 movl(rdx, Address(x, 0));
7678 } else {
7679 movl(x_xstart, Address(x, 0));
7680 }
7681 jmp(L_third_loop_prologue);
7682
7683 bind(L_done);
7684
7685 pop(xlen);
7686
7687 pop(tmp5);
7688 pop(tmp4);
7689 pop(tmp3);
7690 pop(tmp2);
7691 pop(tmp1);
7692 pop(tmp0);
7693 }
7694
7695 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7696 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7697 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7698 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7699 Label VECTOR8_TAIL, VECTOR4_TAIL;
7700 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7701 Label SAME_TILL_END, DONE;
7702 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7703
7704 //scale is in rcx in both Win64 and Unix
7705 ShortBranchVerifier sbv(this);
7706
7707 shlq(length);
7708 xorq(result, result);
7709
7710 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7711 VM_Version::supports_avx512vlbw()) {
7712 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7713
7714 cmpq(length, 64);
7715 jcc(Assembler::less, VECTOR32_TAIL);
7716
7717 movq(tmp1, length);
7718 andq(tmp1, 0x3F); // tail count
7719 andq(length, ~(0x3F)); //vector count
7720
7721 bind(VECTOR64_LOOP);
7722 // AVX512 code to compare 64 byte vectors.
7723 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7724 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7725 kortestql(k7, k7);
7726 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7727 addq(result, 64);
7728 subq(length, 64);
7729 jccb(Assembler::notZero, VECTOR64_LOOP);
7730
7731 //bind(VECTOR64_TAIL);
7732 testq(tmp1, tmp1);
7733 jcc(Assembler::zero, SAME_TILL_END);
7734
7735 //bind(VECTOR64_TAIL);
7736 // AVX512 code to compare up to 63 byte vectors.
7737 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7738 shlxq(tmp2, tmp2, tmp1);
7739 notq(tmp2);
7740 kmovql(k3, tmp2);
7741
7742 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7743 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7744
7745 ktestql(k7, k3);
7746 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7747
7748 bind(VECTOR64_NOT_EQUAL);
7749 kmovql(tmp1, k7);
7750 notq(tmp1);
7751 tzcntq(tmp1, tmp1);
7752 addq(result, tmp1);
7753 shrq(result);
7754 jmp(DONE);
7755 bind(VECTOR32_TAIL);
7756 }
7757
7758 cmpq(length, 8);
7759 jcc(Assembler::equal, VECTOR8_LOOP);
7760 jcc(Assembler::less, VECTOR4_TAIL);
7761
7762 if (UseAVX >= 2) {
7763 Label VECTOR16_TAIL, VECTOR32_LOOP;
7764
7765 cmpq(length, 16);
7766 jcc(Assembler::equal, VECTOR16_LOOP);
7767 jcc(Assembler::less, VECTOR8_LOOP);
7768
7769 cmpq(length, 32);
7770 jccb(Assembler::less, VECTOR16_TAIL);
7771
7772 subq(length, 32);
7773 bind(VECTOR32_LOOP);
7774 vmovdqu(rymm0, Address(obja, result));
7775 vmovdqu(rymm1, Address(objb, result));
7776 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7777 vptest(rymm2, rymm2);
7778 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7779 addq(result, 32);
7780 subq(length, 32);
7781 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7782 addq(length, 32);
7783 jcc(Assembler::equal, SAME_TILL_END);
7784 //falling through if less than 32 bytes left //close the branch here.
7785
7786 bind(VECTOR16_TAIL);
7787 cmpq(length, 16);
7788 jccb(Assembler::less, VECTOR8_TAIL);
7789 bind(VECTOR16_LOOP);
7790 movdqu(rymm0, Address(obja, result));
7791 movdqu(rymm1, Address(objb, result));
7792 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7793 ptest(rymm2, rymm2);
7794 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7795 addq(result, 16);
7796 subq(length, 16);
7797 jcc(Assembler::equal, SAME_TILL_END);
7798 //falling through if less than 16 bytes left
7799 } else {//regular intrinsics
7800
7801 cmpq(length, 16);
7802 jccb(Assembler::less, VECTOR8_TAIL);
7803
7804 subq(length, 16);
7805 bind(VECTOR16_LOOP);
7806 movdqu(rymm0, Address(obja, result));
7807 movdqu(rymm1, Address(objb, result));
7808 pxor(rymm0, rymm1);
7809 ptest(rymm0, rymm0);
7810 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7811 addq(result, 16);
7812 subq(length, 16);
7813 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7814 addq(length, 16);
7815 jcc(Assembler::equal, SAME_TILL_END);
7816 //falling through if less than 16 bytes left
7817 }
7818
7819 bind(VECTOR8_TAIL);
7820 cmpq(length, 8);
7821 jccb(Assembler::less, VECTOR4_TAIL);
7822 bind(VECTOR8_LOOP);
7823 movq(tmp1, Address(obja, result));
7824 movq(tmp2, Address(objb, result));
7825 xorq(tmp1, tmp2);
7826 testq(tmp1, tmp1);
7827 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7828 addq(result, 8);
7829 subq(length, 8);
7830 jcc(Assembler::equal, SAME_TILL_END);
7831 //falling through if less than 8 bytes left
7832
7833 bind(VECTOR4_TAIL);
7834 cmpq(length, 4);
7835 jccb(Assembler::less, BYTES_TAIL);
7836 bind(VECTOR4_LOOP);
7837 movl(tmp1, Address(obja, result));
7838 xorl(tmp1, Address(objb, result));
7839 testl(tmp1, tmp1);
7840 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7841 addq(result, 4);
7842 subq(length, 4);
7843 jcc(Assembler::equal, SAME_TILL_END);
7844 //falling through if less than 4 bytes left
7845
7846 bind(BYTES_TAIL);
7847 bind(BYTES_LOOP);
7848 load_unsigned_byte(tmp1, Address(obja, result));
7849 load_unsigned_byte(tmp2, Address(objb, result));
7850 xorl(tmp1, tmp2);
7851 testl(tmp1, tmp1);
7852 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7853 decq(length);
7854 jcc(Assembler::zero, SAME_TILL_END);
7855 incq(result);
7856 load_unsigned_byte(tmp1, Address(obja, result));
7857 load_unsigned_byte(tmp2, Address(objb, result));
7858 xorl(tmp1, tmp2);
7859 testl(tmp1, tmp1);
7860 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7861 decq(length);
7862 jcc(Assembler::zero, SAME_TILL_END);
7863 incq(result);
7864 load_unsigned_byte(tmp1, Address(obja, result));
7865 load_unsigned_byte(tmp2, Address(objb, result));
7866 xorl(tmp1, tmp2);
7867 testl(tmp1, tmp1);
7868 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7869 jmp(SAME_TILL_END);
7870
7871 if (UseAVX >= 2) {
7872 bind(VECTOR32_NOT_EQUAL);
7873 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7874 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7875 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7876 vpmovmskb(tmp1, rymm0);
7877 bsfq(tmp1, tmp1);
7878 addq(result, tmp1);
7879 shrq(result);
7880 jmp(DONE);
7881 }
7882
7883 bind(VECTOR16_NOT_EQUAL);
7884 if (UseAVX >= 2) {
7885 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7886 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7887 pxor(rymm0, rymm2);
7888 } else {
7889 pcmpeqb(rymm2, rymm2);
7890 pxor(rymm0, rymm1);
7891 pcmpeqb(rymm0, rymm1);
7892 pxor(rymm0, rymm2);
7893 }
7894 pmovmskb(tmp1, rymm0);
7895 bsfq(tmp1, tmp1);
7896 addq(result, tmp1);
7897 shrq(result);
7898 jmpb(DONE);
7899
7900 bind(VECTOR8_NOT_EQUAL);
7901 bind(VECTOR4_NOT_EQUAL);
7902 bsfq(tmp1, tmp1);
7903 shrq(tmp1, 3);
7904 addq(result, tmp1);
7905 bind(BYTES_NOT_EQUAL);
7906 shrq(result);
7907 jmpb(DONE);
7908
7909 bind(SAME_TILL_END);
7910 mov64(result, -1);
7911
7912 bind(DONE);
7913 }
7914
7915 //Helper functions for square_to_len()
7916
7917 /**
7918 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7919 * Preserves x and z and modifies rest of the registers.
7920 */
7921 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7922 // Perform square and right shift by 1
7923 // Handle odd xlen case first, then for even xlen do the following
7924 // jlong carry = 0;
7925 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7926 // huge_128 product = x[j:j+1] * x[j:j+1];
7927 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7928 // z[i+2:i+3] = (jlong)(product >>> 1);
7929 // carry = (jlong)product;
7930 // }
7931
7932 xorq(tmp5, tmp5); // carry
7933 xorq(rdxReg, rdxReg);
7934 xorl(tmp1, tmp1); // index for x
7935 xorl(tmp4, tmp4); // index for z
7936
7937 Label L_first_loop, L_first_loop_exit;
7938
7939 testl(xlen, 1);
7940 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7941
7942 // Square and right shift by 1 the odd element using 32 bit multiply
7943 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7944 imulq(raxReg, raxReg);
7945 shrq(raxReg, 1);
7946 adcq(tmp5, 0);
7947 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7948 incrementl(tmp1);
7949 addl(tmp4, 2);
7950
7951 // Square and right shift by 1 the rest using 64 bit multiply
7952 bind(L_first_loop);
7953 cmpptr(tmp1, xlen);
7954 jccb(Assembler::equal, L_first_loop_exit);
7955
7956 // Square
7957 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7958 rorq(raxReg, 32); // convert big-endian to little-endian
7959 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7960
7961 // Right shift by 1 and save carry
7962 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7963 rcrq(rdxReg, 1);
7964 rcrq(raxReg, 1);
7965 adcq(tmp5, 0);
7966
7967 // Store result in z
7968 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7969 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7970
7971 // Update indices for x and z
7972 addl(tmp1, 2);
7973 addl(tmp4, 4);
7974 jmp(L_first_loop);
7975
7976 bind(L_first_loop_exit);
7977 }
7978
7979
7980 /**
7981 * Perform the following multiply add operation using BMI2 instructions
7982 * carry:sum = sum + op1*op2 + carry
7983 * op2 should be in rdx
7984 * op2 is preserved, all other registers are modified
7985 */
7986 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7987 // assert op2 is rdx
7988 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7989 addq(sum, carry);
7990 adcq(tmp2, 0);
7991 addq(sum, op1);
7992 adcq(tmp2, 0);
7993 movq(carry, tmp2);
7994 }
7995
7996 /**
7997 * Perform the following multiply add operation:
7998 * carry:sum = sum + op1*op2 + carry
7999 * Preserves op1, op2 and modifies rest of registers
8000 */
8001 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8002 // rdx:rax = op1 * op2
8003 movq(raxReg, op2);
8004 mulq(op1);
8005
8006 // rdx:rax = sum + carry + rdx:rax
8007 addq(sum, carry);
8008 adcq(rdxReg, 0);
8009 addq(sum, raxReg);
8010 adcq(rdxReg, 0);
8011
8012 // carry:sum = rdx:sum
8013 movq(carry, rdxReg);
8014 }
8015
8016 /**
8017 * Add 64 bit long carry into z[] with carry propagation.
8018 * Preserves z and carry register values and modifies rest of registers.
8019 *
8020 */
8021 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8022 Label L_fourth_loop, L_fourth_loop_exit;
8023
8024 movl(tmp1, 1);
8025 subl(zlen, 2);
8026 addq(Address(z, zlen, Address::times_4, 0), carry);
8027
8028 bind(L_fourth_loop);
8029 jccb(Assembler::carryClear, L_fourth_loop_exit);
8030 subl(zlen, 2);
8031 jccb(Assembler::negative, L_fourth_loop_exit);
8032 addq(Address(z, zlen, Address::times_4, 0), tmp1);
8033 jmp(L_fourth_loop);
8034 bind(L_fourth_loop_exit);
8035 }
8036
8037 /**
8038 * Shift z[] left by 1 bit.
8039 * Preserves x, len, z and zlen registers and modifies rest of the registers.
8040 *
8041 */
8042 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8043
8044 Label L_fifth_loop, L_fifth_loop_exit;
8045
8046 // Fifth loop
8047 // Perform primitiveLeftShift(z, zlen, 1)
8048
8049 const Register prev_carry = tmp1;
8050 const Register new_carry = tmp4;
8051 const Register value = tmp2;
8052 const Register zidx = tmp3;
8053
8054 // int zidx, carry;
8055 // long value;
8056 // carry = 0;
8057 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8058 // (carry:value) = (z[i] << 1) | carry ;
8059 // z[i] = value;
8060 // }
8061
8062 movl(zidx, zlen);
8063 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8064
8065 bind(L_fifth_loop);
8066 decl(zidx); // Use decl to preserve carry flag
8067 decl(zidx);
8068 jccb(Assembler::negative, L_fifth_loop_exit);
8069
8070 if (UseBMI2Instructions) {
8071 movq(value, Address(z, zidx, Address::times_4, 0));
8072 rclq(value, 1);
8073 rorxq(value, value, 32);
8074 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8075 }
8076 else {
8077 // clear new_carry
8078 xorl(new_carry, new_carry);
8079
8080 // Shift z[i] by 1, or in previous carry and save new carry
8081 movq(value, Address(z, zidx, Address::times_4, 0));
8082 shlq(value, 1);
8083 adcl(new_carry, 0);
8084
8085 orq(value, prev_carry);
8086 rorq(value, 0x20);
8087 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8088
8089 // Set previous carry = new carry
8090 movl(prev_carry, new_carry);
8091 }
8092 jmp(L_fifth_loop);
8093
8094 bind(L_fifth_loop_exit);
8095 }
8096
8097
8098 /**
8099 * Code for BigInteger::squareToLen() intrinsic
8100 *
8101 * rdi: x
8102 * rsi: len
8103 * r8: z
8104 * rcx: zlen
8105 * r12: tmp1
8106 * r13: tmp2
8107 * r14: tmp3
8108 * r15: tmp4
8109 * rbx: tmp5
8110 *
8111 */
8112 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8113
8114 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8115 push(tmp1);
8116 push(tmp2);
8117 push(tmp3);
8118 push(tmp4);
8119 push(tmp5);
8120
8121 // First loop
8122 // Store the squares, right shifted one bit (i.e., divided by 2).
8123 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8124
8125 // Add in off-diagonal sums.
8126 //
8127 // Second, third (nested) and fourth loops.
8128 // zlen +=2;
8129 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8130 // carry = 0;
8131 // long op2 = x[xidx:xidx+1];
8132 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8133 // k -= 2;
8134 // long op1 = x[j:j+1];
8135 // long sum = z[k:k+1];
8136 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8137 // z[k:k+1] = sum;
8138 // }
8139 // add_one_64(z, k, carry, tmp_regs);
8140 // }
8141
8142 const Register carry = tmp5;
8143 const Register sum = tmp3;
8144 const Register op1 = tmp4;
8145 Register op2 = tmp2;
8146
8147 push(zlen);
8148 push(len);
8149 addl(zlen,2);
8150 bind(L_second_loop);
8151 xorq(carry, carry);
8152 subl(zlen, 4);
8153 subl(len, 2);
8154 push(zlen);
8155 push(len);
8156 cmpl(len, 0);
8157 jccb(Assembler::lessEqual, L_second_loop_exit);
8158
8159 // Multiply an array by one 64 bit long.
8160 if (UseBMI2Instructions) {
8161 op2 = rdxReg;
8162 movq(op2, Address(x, len, Address::times_4, 0));
8163 rorxq(op2, op2, 32);
8164 }
8165 else {
8166 movq(op2, Address(x, len, Address::times_4, 0));
8167 rorq(op2, 32);
8168 }
8169
8170 bind(L_third_loop);
8171 decrementl(len);
8172 jccb(Assembler::negative, L_third_loop_exit);
8173 decrementl(len);
8174 jccb(Assembler::negative, L_last_x);
8175
8176 movq(op1, Address(x, len, Address::times_4, 0));
8177 rorq(op1, 32);
8178
8179 bind(L_multiply);
8180 subl(zlen, 2);
8181 movq(sum, Address(z, zlen, Address::times_4, 0));
8182
8183 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8184 if (UseBMI2Instructions) {
8185 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8186 }
8187 else {
8188 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8189 }
8190
8191 movq(Address(z, zlen, Address::times_4, 0), sum);
8192
8193 jmp(L_third_loop);
8194 bind(L_third_loop_exit);
8195
8196 // Fourth loop
8197 // Add 64 bit long carry into z with carry propagation.
8198 // Uses offsetted zlen.
8199 add_one_64(z, zlen, carry, tmp1);
8200
8201 pop(len);
8202 pop(zlen);
8203 jmp(L_second_loop);
8204
8205 // Next infrequent code is moved outside loops.
8206 bind(L_last_x);
8207 movl(op1, Address(x, 0));
8208 jmp(L_multiply);
8209
8210 bind(L_second_loop_exit);
8211 pop(len);
8212 pop(zlen);
8213 pop(len);
8214 pop(zlen);
8215
8216 // Fifth loop
8217 // Shift z left 1 bit.
8218 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8219
8220 // z[zlen-1] |= x[len-1] & 1;
8221 movl(tmp3, Address(x, len, Address::times_4, -4));
8222 andl(tmp3, 1);
8223 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8224
8225 pop(tmp5);
8226 pop(tmp4);
8227 pop(tmp3);
8228 pop(tmp2);
8229 pop(tmp1);
8230 }
8231
8232 /**
8233 * Helper function for mul_add()
8234 * Multiply the in[] by int k and add to out[] starting at offset offs using
8235 * 128 bit by 32 bit multiply and return the carry in tmp5.
8236 * Only quad int aligned length of in[] is operated on in this function.
8237 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8238 * This function preserves out, in and k registers.
8239 * len and offset point to the appropriate index in "in" & "out" correspondingly
8240 * tmp5 has the carry.
8241 * other registers are temporary and are modified.
8242 *
8243 */
8244 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8245 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8246 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8247
8248 Label L_first_loop, L_first_loop_exit;
8249
8250 movl(tmp1, len);
8251 shrl(tmp1, 2);
8252
8253 bind(L_first_loop);
8254 subl(tmp1, 1);
8255 jccb(Assembler::negative, L_first_loop_exit);
8256
8257 subl(len, 4);
8258 subl(offset, 4);
8259
8260 Register op2 = tmp2;
8261 const Register sum = tmp3;
8262 const Register op1 = tmp4;
8263 const Register carry = tmp5;
8264
8265 if (UseBMI2Instructions) {
8266 op2 = rdxReg;
8267 }
8268
8269 movq(op1, Address(in, len, Address::times_4, 8));
8270 rorq(op1, 32);
8271 movq(sum, Address(out, offset, Address::times_4, 8));
8272 rorq(sum, 32);
8273 if (UseBMI2Instructions) {
8274 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8275 }
8276 else {
8277 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8278 }
8279 // Store back in big endian from little endian
8280 rorq(sum, 0x20);
8281 movq(Address(out, offset, Address::times_4, 8), sum);
8282
8283 movq(op1, Address(in, len, Address::times_4, 0));
8284 rorq(op1, 32);
8285 movq(sum, Address(out, offset, Address::times_4, 0));
8286 rorq(sum, 32);
8287 if (UseBMI2Instructions) {
8288 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8289 }
8290 else {
8291 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8292 }
8293 // Store back in big endian from little endian
8294 rorq(sum, 0x20);
8295 movq(Address(out, offset, Address::times_4, 0), sum);
8296
8297 jmp(L_first_loop);
8298 bind(L_first_loop_exit);
8299 }
8300
8301 /**
8302 * Code for BigInteger::mulAdd() intrinsic
8303 *
8304 * rdi: out
8305 * rsi: in
8306 * r11: offs (out.length - offset)
8307 * rcx: len
8308 * r8: k
8309 * r12: tmp1
8310 * r13: tmp2
8311 * r14: tmp3
8312 * r15: tmp4
8313 * rbx: tmp5
8314 * Multiply the in[] by word k and add to out[], return the carry in rax
8315 */
8316 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8317 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8318 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8319
8320 Label L_carry, L_last_in, L_done;
8321
8322 // carry = 0;
8323 // for (int j=len-1; j >= 0; j--) {
8324 // long product = (in[j] & LONG_MASK) * kLong +
8325 // (out[offs] & LONG_MASK) + carry;
8326 // out[offs--] = (int)product;
8327 // carry = product >>> 32;
8328 // }
8329 //
8330 push(tmp1);
8331 push(tmp2);
8332 push(tmp3);
8333 push(tmp4);
8334 push(tmp5);
8335
8336 Register op2 = tmp2;
8337 const Register sum = tmp3;
8338 const Register op1 = tmp4;
8339 const Register carry = tmp5;
8340
8341 if (UseBMI2Instructions) {
8342 op2 = rdxReg;
8343 movl(op2, k);
8344 }
8345 else {
8346 movl(op2, k);
8347 }
8348
8349 xorq(carry, carry);
8350
8351 //First loop
8352
8353 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8354 //The carry is in tmp5
8355 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8356
8357 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8358 decrementl(len);
8359 jccb(Assembler::negative, L_carry);
8360 decrementl(len);
8361 jccb(Assembler::negative, L_last_in);
8362
8363 movq(op1, Address(in, len, Address::times_4, 0));
8364 rorq(op1, 32);
8365
8366 subl(offs, 2);
8367 movq(sum, Address(out, offs, Address::times_4, 0));
8368 rorq(sum, 32);
8369
8370 if (UseBMI2Instructions) {
8371 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8372 }
8373 else {
8374 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8375 }
8376
8377 // Store back in big endian from little endian
8378 rorq(sum, 0x20);
8379 movq(Address(out, offs, Address::times_4, 0), sum);
8380
8381 testl(len, len);
8382 jccb(Assembler::zero, L_carry);
8383
8384 //Multiply the last in[] entry, if any
8385 bind(L_last_in);
8386 movl(op1, Address(in, 0));
8387 movl(sum, Address(out, offs, Address::times_4, -4));
8388
8389 movl(raxReg, k);
8390 mull(op1); //tmp4 * eax -> edx:eax
8391 addl(sum, carry);
8392 adcl(rdxReg, 0);
8393 addl(sum, raxReg);
8394 adcl(rdxReg, 0);
8395 movl(carry, rdxReg);
8396
8397 movl(Address(out, offs, Address::times_4, -4), sum);
8398
8399 bind(L_carry);
8400 //return tmp5/carry as carry in rax
8401 movl(rax, carry);
8402
8403 bind(L_done);
8404 pop(tmp5);
8405 pop(tmp4);
8406 pop(tmp3);
8407 pop(tmp2);
8408 pop(tmp1);
8409 }
8410
8411 /**
8412 * Emits code to update CRC-32 with a byte value according to constants in table
8413 *
8414 * @param [in,out]crc Register containing the crc.
8415 * @param [in]val Register containing the byte to fold into the CRC.
8416 * @param [in]table Register containing the table of crc constants.
8417 *
8418 * uint32_t crc;
8419 * val = crc_table[(val ^ crc) & 0xFF];
8420 * crc = val ^ (crc >> 8);
8421 *
8422 */
8423 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8424 xorl(val, crc);
8425 andl(val, 0xFF);
8426 shrl(crc, 8); // unsigned shift
8427 xorl(crc, Address(table, val, Address::times_4, 0));
8428 }
8429
8430 /**
8431 * Fold 128-bit data chunk
8432 */
8433 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8434 if (UseAVX > 0) {
8435 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8436 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8437 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8438 pxor(xcrc, xtmp);
8439 } else {
8440 movdqa(xtmp, xcrc);
8441 pclmulhdq(xtmp, xK); // [123:64]
8442 pclmulldq(xcrc, xK); // [63:0]
8443 pxor(xcrc, xtmp);
8444 movdqu(xtmp, Address(buf, offset));
8445 pxor(xcrc, xtmp);
8446 }
8447 }
8448
8449 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8450 if (UseAVX > 0) {
8451 vpclmulhdq(xtmp, xK, xcrc);
8452 vpclmulldq(xcrc, xK, xcrc);
8453 pxor(xcrc, xbuf);
8454 pxor(xcrc, xtmp);
8455 } else {
8456 movdqa(xtmp, xcrc);
8457 pclmulhdq(xtmp, xK);
8458 pclmulldq(xcrc, xK);
8459 pxor(xcrc, xbuf);
8460 pxor(xcrc, xtmp);
8461 }
8462 }
8463
8464 /**
8465 * 8-bit folds to compute 32-bit CRC
8466 *
8467 * uint64_t xcrc;
8468 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8469 */
8470 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8471 movdl(tmp, xcrc);
8472 andl(tmp, 0xFF);
8473 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8474 psrldq(xcrc, 1); // unsigned shift one byte
8475 pxor(xcrc, xtmp);
8476 }
8477
8478 /**
8479 * uint32_t crc;
8480 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8481 */
8482 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8483 movl(tmp, crc);
8484 andl(tmp, 0xFF);
8485 shrl(crc, 8);
8486 xorl(crc, Address(table, tmp, Address::times_4, 0));
8487 }
8488
8489 /**
8490 * @param crc register containing existing CRC (32-bit)
8491 * @param buf register pointing to input byte buffer (byte*)
8492 * @param len register containing number of bytes
8493 * @param table register that will contain address of CRC table
8494 * @param tmp scratch register
8495 */
8496 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8497 assert_different_registers(crc, buf, len, table, tmp, rax);
8498
8499 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8500 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8501
8502 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8503 // context for the registers used, where all instructions below are using 128-bit mode
8504 // On EVEX without VL and BW, these instructions will all be AVX.
8505 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8506 notl(crc); // ~crc
8507 cmpl(len, 16);
8508 jcc(Assembler::less, L_tail);
8509
8510 // Align buffer to 16 bytes
8511 movl(tmp, buf);
8512 andl(tmp, 0xF);
8513 jccb(Assembler::zero, L_aligned);
8514 subl(tmp, 16);
8515 addl(len, tmp);
8516
8517 align(4);
8518 BIND(L_align_loop);
8519 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8520 update_byte_crc32(crc, rax, table);
8521 increment(buf);
8522 incrementl(tmp);
8523 jccb(Assembler::less, L_align_loop);
8524
8525 BIND(L_aligned);
8526 movl(tmp, len); // save
8527 shrl(len, 4);
8528 jcc(Assembler::zero, L_tail_restore);
8529
8530 // Fold crc into first bytes of vector
8531 movdqa(xmm1, Address(buf, 0));
8532 movdl(rax, xmm1);
8533 xorl(crc, rax);
8534 if (VM_Version::supports_sse4_1()) {
8535 pinsrd(xmm1, crc, 0);
8536 } else {
8537 pinsrw(xmm1, crc, 0);
8538 shrl(crc, 16);
8539 pinsrw(xmm1, crc, 1);
8540 }
8541 addptr(buf, 16);
8542 subl(len, 4); // len > 0
8543 jcc(Assembler::less, L_fold_tail);
8544
8545 movdqa(xmm2, Address(buf, 0));
8546 movdqa(xmm3, Address(buf, 16));
8547 movdqa(xmm4, Address(buf, 32));
8548 addptr(buf, 48);
8549 subl(len, 3);
8550 jcc(Assembler::lessEqual, L_fold_512b);
8551
8552 // Fold total 512 bits of polynomial on each iteration,
8553 // 128 bits per each of 4 parallel streams.
8554 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8555
8556 align32();
8557 BIND(L_fold_512b_loop);
8558 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8559 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8560 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8561 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8562 addptr(buf, 64);
8563 subl(len, 4);
8564 jcc(Assembler::greater, L_fold_512b_loop);
8565
8566 // Fold 512 bits to 128 bits.
8567 BIND(L_fold_512b);
8568 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8569 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8570 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8571 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8572
8573 // Fold the rest of 128 bits data chunks
8574 BIND(L_fold_tail);
8575 addl(len, 3);
8576 jccb(Assembler::lessEqual, L_fold_128b);
8577 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8578
8579 BIND(L_fold_tail_loop);
8580 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8581 addptr(buf, 16);
8582 decrementl(len);
8583 jccb(Assembler::greater, L_fold_tail_loop);
8584
8585 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8586 BIND(L_fold_128b);
8587 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8588 if (UseAVX > 0) {
8589 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8590 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8591 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8592 } else {
8593 movdqa(xmm2, xmm0);
8594 pclmulqdq(xmm2, xmm1, 0x1);
8595 movdqa(xmm3, xmm0);
8596 pand(xmm3, xmm2);
8597 pclmulqdq(xmm0, xmm3, 0x1);
8598 }
8599 psrldq(xmm1, 8);
8600 psrldq(xmm2, 4);
8601 pxor(xmm0, xmm1);
8602 pxor(xmm0, xmm2);
8603
8604 // 8 8-bit folds to compute 32-bit CRC.
8605 for (int j = 0; j < 4; j++) {
8606 fold_8bit_crc32(xmm0, table, xmm1, rax);
8607 }
8608 movdl(crc, xmm0); // mov 32 bits to general register
8609 for (int j = 0; j < 4; j++) {
8610 fold_8bit_crc32(crc, table, rax);
8611 }
8612
8613 BIND(L_tail_restore);
8614 movl(len, tmp); // restore
8615 BIND(L_tail);
8616 andl(len, 0xf);
8617 jccb(Assembler::zero, L_exit);
8618
8619 // Fold the rest of bytes
8620 align(4);
8621 BIND(L_tail_loop);
8622 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8623 update_byte_crc32(crc, rax, table);
8624 increment(buf);
8625 decrementl(len);
8626 jccb(Assembler::greater, L_tail_loop);
8627
8628 BIND(L_exit);
8629 notl(crc); // ~c
8630 }
8631
8632 // Helper function for AVX 512 CRC32
8633 // Fold 512-bit data chunks
8634 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8635 Register pos, int offset) {
8636 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8637 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8638 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8639 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8640 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8641 }
8642
8643 // Helper function for AVX 512 CRC32
8644 // Compute CRC32 for < 256B buffers
8645 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8646 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8647 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8648
8649 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8650 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8651 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8652
8653 // check if there is enough buffer to be able to fold 16B at a time
8654 cmpl(len, 32);
8655 jcc(Assembler::less, L_less_than_32);
8656
8657 // if there is, load the constants
8658 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8659 movdl(xmm0, crc); // get the initial crc value
8660 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8661 pxor(xmm7, xmm0);
8662
8663 // update the buffer pointer
8664 addl(pos, 16);
8665 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8666 subl(len, 32);
8667 jmp(L_16B_reduction_loop);
8668
8669 bind(L_less_than_32);
8670 //mov initial crc to the return value. this is necessary for zero - length buffers.
8671 movl(rax, crc);
8672 testl(len, len);
8673 jcc(Assembler::equal, L_cleanup);
8674
8675 movdl(xmm0, crc); //get the initial crc value
8676
8677 cmpl(len, 16);
8678 jcc(Assembler::equal, L_exact_16_left);
8679 jcc(Assembler::less, L_less_than_16_left);
8680
8681 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8682 pxor(xmm7, xmm0); //xor the initial crc value
8683 addl(pos, 16);
8684 subl(len, 16);
8685 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8686 jmp(L_get_last_two_xmms);
8687
8688 bind(L_less_than_16_left);
8689 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8690 pxor(xmm1, xmm1);
8691 movptr(tmp1, rsp);
8692 movdqu(Address(tmp1, 0 * 16), xmm1);
8693
8694 cmpl(len, 4);
8695 jcc(Assembler::less, L_only_less_than_4);
8696
8697 //backup the counter value
8698 movl(tmp2, len);
8699 cmpl(len, 8);
8700 jcc(Assembler::less, L_less_than_8_left);
8701
8702 //load 8 Bytes
8703 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8704 movq(Address(tmp1, 0 * 16), rax);
8705 addptr(tmp1, 8);
8706 subl(len, 8);
8707 addl(pos, 8);
8708
8709 bind(L_less_than_8_left);
8710 cmpl(len, 4);
8711 jcc(Assembler::less, L_less_than_4_left);
8712
8713 //load 4 Bytes
8714 movl(rax, Address(buf, pos, Address::times_1, 0));
8715 movl(Address(tmp1, 0 * 16), rax);
8716 addptr(tmp1, 4);
8717 subl(len, 4);
8718 addl(pos, 4);
8719
8720 bind(L_less_than_4_left);
8721 cmpl(len, 2);
8722 jcc(Assembler::less, L_less_than_2_left);
8723
8724 // load 2 Bytes
8725 movw(rax, Address(buf, pos, Address::times_1, 0));
8726 movl(Address(tmp1, 0 * 16), rax);
8727 addptr(tmp1, 2);
8728 subl(len, 2);
8729 addl(pos, 2);
8730
8731 bind(L_less_than_2_left);
8732 cmpl(len, 1);
8733 jcc(Assembler::less, L_zero_left);
8734
8735 // load 1 Byte
8736 movb(rax, Address(buf, pos, Address::times_1, 0));
8737 movb(Address(tmp1, 0 * 16), rax);
8738
8739 bind(L_zero_left);
8740 movdqu(xmm7, Address(rsp, 0));
8741 pxor(xmm7, xmm0); //xor the initial crc value
8742
8743 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8744 movdqu(xmm0, Address(rax, tmp2));
8745 pshufb(xmm7, xmm0);
8746 jmp(L_128_done);
8747
8748 bind(L_exact_16_left);
8749 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8750 pxor(xmm7, xmm0); //xor the initial crc value
8751 jmp(L_128_done);
8752
8753 bind(L_only_less_than_4);
8754 cmpl(len, 3);
8755 jcc(Assembler::less, L_only_less_than_3);
8756
8757 // load 3 Bytes
8758 movb(rax, Address(buf, pos, Address::times_1, 0));
8759 movb(Address(tmp1, 0), rax);
8760
8761 movb(rax, Address(buf, pos, Address::times_1, 1));
8762 movb(Address(tmp1, 1), rax);
8763
8764 movb(rax, Address(buf, pos, Address::times_1, 2));
8765 movb(Address(tmp1, 2), rax);
8766
8767 movdqu(xmm7, Address(rsp, 0));
8768 pxor(xmm7, xmm0); //xor the initial crc value
8769
8770 pslldq(xmm7, 0x5);
8771 jmp(L_barrett);
8772 bind(L_only_less_than_3);
8773 cmpl(len, 2);
8774 jcc(Assembler::less, L_only_less_than_2);
8775
8776 // load 2 Bytes
8777 movb(rax, Address(buf, pos, Address::times_1, 0));
8778 movb(Address(tmp1, 0), rax);
8779
8780 movb(rax, Address(buf, pos, Address::times_1, 1));
8781 movb(Address(tmp1, 1), rax);
8782
8783 movdqu(xmm7, Address(rsp, 0));
8784 pxor(xmm7, xmm0); //xor the initial crc value
8785
8786 pslldq(xmm7, 0x6);
8787 jmp(L_barrett);
8788
8789 bind(L_only_less_than_2);
8790 //load 1 Byte
8791 movb(rax, Address(buf, pos, Address::times_1, 0));
8792 movb(Address(tmp1, 0), rax);
8793
8794 movdqu(xmm7, Address(rsp, 0));
8795 pxor(xmm7, xmm0); //xor the initial crc value
8796
8797 pslldq(xmm7, 0x7);
8798 }
8799
8800 /**
8801 * Compute CRC32 using AVX512 instructions
8802 * param crc register containing existing CRC (32-bit)
8803 * param buf register pointing to input byte buffer (byte*)
8804 * param len register containing number of bytes
8805 * param table address of crc or crc32c table
8806 * param tmp1 scratch register
8807 * param tmp2 scratch register
8808 * return rax result register
8809 *
8810 * This routine is identical for crc32c with the exception of the precomputed constant
8811 * table which will be passed as the table argument. The calculation steps are
8812 * the same for both variants.
8813 */
8814 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8815 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8816
8817 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8818 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8819 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8820 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8821 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8822
8823 const Register pos = r12;
8824 push(r12);
8825 subptr(rsp, 16 * 2 + 8);
8826
8827 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8828 // context for the registers used, where all instructions below are using 128-bit mode
8829 // On EVEX without VL and BW, these instructions will all be AVX.
8830 movl(pos, 0);
8831
8832 // check if smaller than 256B
8833 cmpl(len, 256);
8834 jcc(Assembler::less, L_less_than_256);
8835
8836 // load the initial crc value
8837 movdl(xmm10, crc);
8838
8839 // receive the initial 64B data, xor the initial crc value
8840 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8841 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8842 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8843 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8844
8845 subl(len, 256);
8846 cmpl(len, 256);
8847 jcc(Assembler::less, L_fold_128_B_loop);
8848
8849 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8850 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8851 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8852 subl(len, 256);
8853
8854 bind(L_fold_256_B_loop);
8855 addl(pos, 256);
8856 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8857 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8858 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8859 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8860
8861 subl(len, 256);
8862 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8863
8864 // Fold 256 into 128
8865 addl(pos, 256);
8866 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8867 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8868 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8869
8870 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8871 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8872 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8873
8874 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8875 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8876
8877 addl(len, 128);
8878 jmp(L_fold_128_B_register);
8879
8880 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8881 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8882
8883 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8884 bind(L_fold_128_B_loop);
8885 addl(pos, 128);
8886 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8887 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8888
8889 subl(len, 128);
8890 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8891
8892 addl(pos, 128);
8893
8894 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8895 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8896 bind(L_fold_128_B_register);
8897 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8898 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8899 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8900 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8901 // save last that has no multiplicand
8902 vextracti64x2(xmm7, xmm4, 3);
8903
8904 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8905 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8906 // Needed later in reduction loop
8907 movdqu(xmm10, Address(table, 1 * 16));
8908 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8909 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8910
8911 // Swap 1,0,3,2 - 01 00 11 10
8912 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8913 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8914 vextracti128(xmm5, xmm8, 1);
8915 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8916
8917 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8918 // instead of a cmp instruction, we use the negative flag with the jl instruction
8919 addl(len, 128 - 16);
8920 jcc(Assembler::less, L_final_reduction_for_128);
8921
8922 bind(L_16B_reduction_loop);
8923 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8924 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8925 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8926 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8927 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8928 addl(pos, 16);
8929 subl(len, 16);
8930 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8931
8932 bind(L_final_reduction_for_128);
8933 addl(len, 16);
8934 jcc(Assembler::equal, L_128_done);
8935
8936 bind(L_get_last_two_xmms);
8937 movdqu(xmm2, xmm7);
8938 addl(pos, len);
8939 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8940 subl(pos, len);
8941
8942 // get rid of the extra data that was loaded before
8943 // load the shift constant
8944 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8945 movdqu(xmm0, Address(rax, len));
8946 addl(rax, len);
8947
8948 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8949 //Change mask to 512
8950 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8951 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8952
8953 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8954 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8955 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8956 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8957 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8958
8959 bind(L_128_done);
8960 // compute crc of a 128-bit value
8961 movdqu(xmm10, Address(table, 3 * 16));
8962 movdqu(xmm0, xmm7);
8963
8964 // 64b fold
8965 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8966 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8967 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8968
8969 // 32b fold
8970 movdqu(xmm0, xmm7);
8971 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8972 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8973 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8974 jmp(L_barrett);
8975
8976 bind(L_less_than_256);
8977 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8978
8979 //barrett reduction
8980 bind(L_barrett);
8981 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8982 movdqu(xmm1, xmm7);
8983 movdqu(xmm2, xmm7);
8984 movdqu(xmm10, Address(table, 4 * 16));
8985
8986 pclmulqdq(xmm7, xmm10, 0x0);
8987 pxor(xmm7, xmm2);
8988 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8989 movdqu(xmm2, xmm7);
8990 pclmulqdq(xmm7, xmm10, 0x10);
8991 pxor(xmm7, xmm2);
8992 pxor(xmm7, xmm1);
8993 pextrd(crc, xmm7, 2);
8994
8995 bind(L_cleanup);
8996 addptr(rsp, 16 * 2 + 8);
8997 pop(r12);
8998 }
8999
9000 // S. Gueron / Information Processing Letters 112 (2012) 184
9001 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
9002 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
9003 // Output: the 64-bit carry-less product of B * CONST
9004 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
9005 Register tmp1, Register tmp2, Register tmp3) {
9006 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9007 if (n > 0) {
9008 addq(tmp3, n * 256 * 8);
9009 }
9010 // Q1 = TABLEExt[n][B & 0xFF];
9011 movl(tmp1, in);
9012 andl(tmp1, 0x000000FF);
9013 shll(tmp1, 3);
9014 addq(tmp1, tmp3);
9015 movq(tmp1, Address(tmp1, 0));
9016
9017 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9018 movl(tmp2, in);
9019 shrl(tmp2, 8);
9020 andl(tmp2, 0x000000FF);
9021 shll(tmp2, 3);
9022 addq(tmp2, tmp3);
9023 movq(tmp2, Address(tmp2, 0));
9024
9025 shlq(tmp2, 8);
9026 xorq(tmp1, tmp2);
9027
9028 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9029 movl(tmp2, in);
9030 shrl(tmp2, 16);
9031 andl(tmp2, 0x000000FF);
9032 shll(tmp2, 3);
9033 addq(tmp2, tmp3);
9034 movq(tmp2, Address(tmp2, 0));
9035
9036 shlq(tmp2, 16);
9037 xorq(tmp1, tmp2);
9038
9039 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9040 shrl(in, 24);
9041 andl(in, 0x000000FF);
9042 shll(in, 3);
9043 addq(in, tmp3);
9044 movq(in, Address(in, 0));
9045
9046 shlq(in, 24);
9047 xorq(in, tmp1);
9048 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9049 }
9050
9051 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9052 Register in_out,
9053 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9054 XMMRegister w_xtmp2,
9055 Register tmp1,
9056 Register n_tmp2, Register n_tmp3) {
9057 if (is_pclmulqdq_supported) {
9058 movdl(w_xtmp1, in_out); // modified blindly
9059
9060 movl(tmp1, const_or_pre_comp_const_index);
9061 movdl(w_xtmp2, tmp1);
9062 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9063
9064 movdq(in_out, w_xtmp1);
9065 } else {
9066 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
9067 }
9068 }
9069
9070 // Recombination Alternative 2: No bit-reflections
9071 // T1 = (CRC_A * U1) << 1
9072 // T2 = (CRC_B * U2) << 1
9073 // C1 = T1 >> 32
9074 // C2 = T2 >> 32
9075 // T1 = T1 & 0xFFFFFFFF
9076 // T2 = T2 & 0xFFFFFFFF
9077 // T1 = CRC32(0, T1)
9078 // T2 = CRC32(0, T2)
9079 // C1 = C1 ^ T1
9080 // C2 = C2 ^ T2
9081 // CRC = C1 ^ C2 ^ CRC_C
9082 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9083 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9084 Register tmp1, Register tmp2,
9085 Register n_tmp3) {
9086 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9087 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9088 shlq(in_out, 1);
9089 movl(tmp1, in_out);
9090 shrq(in_out, 32);
9091 xorl(tmp2, tmp2);
9092 crc32(tmp2, tmp1, 4);
9093 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9094 shlq(in1, 1);
9095 movl(tmp1, in1);
9096 shrq(in1, 32);
9097 xorl(tmp2, tmp2);
9098 crc32(tmp2, tmp1, 4);
9099 xorl(in1, tmp2);
9100 xorl(in_out, in1);
9101 xorl(in_out, in2);
9102 }
9103
9104 // Set N to predefined value
9105 // Subtract from a length of a buffer
9106 // execute in a loop:
9107 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9108 // for i = 1 to N do
9109 // CRC_A = CRC32(CRC_A, A[i])
9110 // CRC_B = CRC32(CRC_B, B[i])
9111 // CRC_C = CRC32(CRC_C, C[i])
9112 // end for
9113 // Recombine
9114 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9115 Register in_out1, Register in_out2, Register in_out3,
9116 Register tmp1, Register tmp2, Register tmp3,
9117 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9118 Register tmp4, Register tmp5,
9119 Register n_tmp6) {
9120 Label L_processPartitions;
9121 Label L_processPartition;
9122 Label L_exit;
9123
9124 bind(L_processPartitions);
9125 cmpl(in_out1, 3 * size);
9126 jcc(Assembler::less, L_exit);
9127 xorl(tmp1, tmp1);
9128 xorl(tmp2, tmp2);
9129 movq(tmp3, in_out2);
9130 addq(tmp3, size);
9131
9132 bind(L_processPartition);
9133 crc32(in_out3, Address(in_out2, 0), 8);
9134 crc32(tmp1, Address(in_out2, size), 8);
9135 crc32(tmp2, Address(in_out2, size * 2), 8);
9136 addq(in_out2, 8);
9137 cmpq(in_out2, tmp3);
9138 jcc(Assembler::less, L_processPartition);
9139 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9140 w_xtmp1, w_xtmp2, w_xtmp3,
9141 tmp4, tmp5,
9142 n_tmp6);
9143 addq(in_out2, 2 * size);
9144 subl(in_out1, 3 * size);
9145 jmp(L_processPartitions);
9146
9147 bind(L_exit);
9148 }
9149
9150 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9151 // Input: A buffer I of L bytes.
9152 // Output: the CRC32C value of the buffer.
9153 // Notations:
9154 // Write L = 24N + r, with N = floor (L/24).
9155 // r = L mod 24 (0 <= r < 24).
9156 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9157 // N quadwords, and R consists of r bytes.
9158 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9159 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9160 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9161 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9162 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9163 Register tmp1, Register tmp2, Register tmp3,
9164 Register tmp4, Register tmp5, Register tmp6,
9165 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9166 bool is_pclmulqdq_supported) {
9167 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9168 Label L_wordByWord;
9169 Label L_byteByByteProlog;
9170 Label L_byteByByte;
9171 Label L_exit;
9172
9173 if (is_pclmulqdq_supported ) {
9174 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9175 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9176
9177 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9178 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9179
9180 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9181 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9182 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9183 } else {
9184 const_or_pre_comp_const_index[0] = 1;
9185 const_or_pre_comp_const_index[1] = 0;
9186
9187 const_or_pre_comp_const_index[2] = 3;
9188 const_or_pre_comp_const_index[3] = 2;
9189
9190 const_or_pre_comp_const_index[4] = 5;
9191 const_or_pre_comp_const_index[5] = 4;
9192 }
9193 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9194 in2, in1, in_out,
9195 tmp1, tmp2, tmp3,
9196 w_xtmp1, w_xtmp2, w_xtmp3,
9197 tmp4, tmp5,
9198 tmp6);
9199 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9200 in2, in1, in_out,
9201 tmp1, tmp2, tmp3,
9202 w_xtmp1, w_xtmp2, w_xtmp3,
9203 tmp4, tmp5,
9204 tmp6);
9205 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9206 in2, in1, in_out,
9207 tmp1, tmp2, tmp3,
9208 w_xtmp1, w_xtmp2, w_xtmp3,
9209 tmp4, tmp5,
9210 tmp6);
9211 movl(tmp1, in2);
9212 andl(tmp1, 0x00000007);
9213 negl(tmp1);
9214 addl(tmp1, in2);
9215 addq(tmp1, in1);
9216
9217 cmpq(in1, tmp1);
9218 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9219 align(16);
9220 BIND(L_wordByWord);
9221 crc32(in_out, Address(in1, 0), 8);
9222 addq(in1, 8);
9223 cmpq(in1, tmp1);
9224 jcc(Assembler::less, L_wordByWord);
9225
9226 BIND(L_byteByByteProlog);
9227 andl(in2, 0x00000007);
9228 movl(tmp2, 1);
9229
9230 cmpl(tmp2, in2);
9231 jccb(Assembler::greater, L_exit);
9232 BIND(L_byteByByte);
9233 crc32(in_out, Address(in1, 0), 1);
9234 incq(in1);
9235 incl(tmp2);
9236 cmpl(tmp2, in2);
9237 jcc(Assembler::lessEqual, L_byteByByte);
9238
9239 BIND(L_exit);
9240 }
9241 #undef BIND
9242 #undef BLOCK_COMMENT
9243
9244 // Compress char[] array to byte[].
9245 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9246 // Return the array length if every element in array can be encoded,
9247 // otherwise, the index of first non-latin1 (> 0xff) character.
9248 // @IntrinsicCandidate
9249 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9250 // for (int i = 0; i < len; i++) {
9251 // char c = src[srcOff];
9252 // if (c > 0xff) {
9253 // return i; // return index of non-latin1 char
9254 // }
9255 // dst[dstOff] = (byte)c;
9256 // srcOff++;
9257 // dstOff++;
9258 // }
9259 // return len;
9260 // }
9261 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9262 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9263 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9264 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9265 Label copy_chars_loop, done, reset_sp, copy_tail;
9266
9267 // rsi: src
9268 // rdi: dst
9269 // rdx: len
9270 // rcx: tmp5
9271 // rax: result
9272
9273 // rsi holds start addr of source char[] to be compressed
9274 // rdi holds start addr of destination byte[]
9275 // rdx holds length
9276
9277 assert(len != result, "");
9278
9279 // save length for return
9280 movl(result, len);
9281
9282 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9283 VM_Version::supports_avx512vlbw() &&
9284 VM_Version::supports_bmi2()) {
9285
9286 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9287
9288 // alignment
9289 Label post_alignment;
9290
9291 // if length of the string is less than 32, handle it the old fashioned way
9292 testl(len, -32);
9293 jcc(Assembler::zero, below_threshold);
9294
9295 // First check whether a character is compressible ( <= 0xFF).
9296 // Create mask to test for Unicode chars inside zmm vector
9297 movl(tmp5, 0x00FF);
9298 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9299
9300 testl(len, -64);
9301 jccb(Assembler::zero, post_alignment);
9302
9303 movl(tmp5, dst);
9304 andl(tmp5, (32 - 1));
9305 negl(tmp5);
9306 andl(tmp5, (32 - 1));
9307
9308 // bail out when there is nothing to be done
9309 testl(tmp5, 0xFFFFFFFF);
9310 jccb(Assembler::zero, post_alignment);
9311
9312 // ~(~0 << len), where len is the # of remaining elements to process
9313 movl(len, 0xFFFFFFFF);
9314 shlxl(len, len, tmp5);
9315 notl(len);
9316 kmovdl(mask2, len);
9317 movl(len, result);
9318
9319 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9320 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9321 ktestd(mask1, mask2);
9322 jcc(Assembler::carryClear, copy_tail);
9323
9324 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9325
9326 addptr(src, tmp5);
9327 addptr(src, tmp5);
9328 addptr(dst, tmp5);
9329 subl(len, tmp5);
9330
9331 bind(post_alignment);
9332 // end of alignment
9333
9334 movl(tmp5, len);
9335 andl(tmp5, (32 - 1)); // tail count (in chars)
9336 andl(len, ~(32 - 1)); // vector count (in chars)
9337 jccb(Assembler::zero, copy_loop_tail);
9338
9339 lea(src, Address(src, len, Address::times_2));
9340 lea(dst, Address(dst, len, Address::times_1));
9341 negptr(len);
9342
9343 bind(copy_32_loop);
9344 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9345 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9346 kortestdl(mask1, mask1);
9347 jccb(Assembler::carryClear, reset_for_copy_tail);
9348
9349 // All elements in current processed chunk are valid candidates for
9350 // compression. Write a truncated byte elements to the memory.
9351 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9352 addptr(len, 32);
9353 jccb(Assembler::notZero, copy_32_loop);
9354
9355 bind(copy_loop_tail);
9356 // bail out when there is nothing to be done
9357 testl(tmp5, 0xFFFFFFFF);
9358 jcc(Assembler::zero, done);
9359
9360 movl(len, tmp5);
9361
9362 // ~(~0 << len), where len is the # of remaining elements to process
9363 movl(tmp5, 0xFFFFFFFF);
9364 shlxl(tmp5, tmp5, len);
9365 notl(tmp5);
9366
9367 kmovdl(mask2, tmp5);
9368
9369 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9370 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9371 ktestd(mask1, mask2);
9372 jcc(Assembler::carryClear, copy_tail);
9373
9374 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9375 jmp(done);
9376
9377 bind(reset_for_copy_tail);
9378 lea(src, Address(src, tmp5, Address::times_2));
9379 lea(dst, Address(dst, tmp5, Address::times_1));
9380 subptr(len, tmp5);
9381 jmp(copy_chars_loop);
9382
9383 bind(below_threshold);
9384 }
9385
9386 if (UseSSE42Intrinsics) {
9387 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9388
9389 // vectored compression
9390 testl(len, 0xfffffff8);
9391 jcc(Assembler::zero, copy_tail);
9392
9393 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9394 movdl(tmp1Reg, tmp5);
9395 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9396
9397 andl(len, 0xfffffff0);
9398 jccb(Assembler::zero, copy_16);
9399
9400 // compress 16 chars per iter
9401 pxor(tmp4Reg, tmp4Reg);
9402
9403 lea(src, Address(src, len, Address::times_2));
9404 lea(dst, Address(dst, len, Address::times_1));
9405 negptr(len);
9406
9407 bind(copy_32_loop);
9408 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9409 por(tmp4Reg, tmp2Reg);
9410 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9411 por(tmp4Reg, tmp3Reg);
9412 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9413 jccb(Assembler::notZero, reset_for_copy_tail);
9414 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9415 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9416 addptr(len, 16);
9417 jccb(Assembler::notZero, copy_32_loop);
9418
9419 // compress next vector of 8 chars (if any)
9420 bind(copy_16);
9421 // len = 0
9422 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9423 jccb(Assembler::zero, copy_tail_sse);
9424
9425 pxor(tmp3Reg, tmp3Reg);
9426
9427 movdqu(tmp2Reg, Address(src, 0));
9428 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9429 jccb(Assembler::notZero, reset_for_copy_tail);
9430 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9431 movq(Address(dst, 0), tmp2Reg);
9432 addptr(src, 16);
9433 addptr(dst, 8);
9434 jmpb(copy_tail_sse);
9435
9436 bind(reset_for_copy_tail);
9437 movl(tmp5, result);
9438 andl(tmp5, 0x0000000f);
9439 lea(src, Address(src, tmp5, Address::times_2));
9440 lea(dst, Address(dst, tmp5, Address::times_1));
9441 subptr(len, tmp5);
9442 jmpb(copy_chars_loop);
9443
9444 bind(copy_tail_sse);
9445 movl(len, result);
9446 andl(len, 0x00000007); // tail count (in chars)
9447 }
9448 // compress 1 char per iter
9449 bind(copy_tail);
9450 testl(len, len);
9451 jccb(Assembler::zero, done);
9452 lea(src, Address(src, len, Address::times_2));
9453 lea(dst, Address(dst, len, Address::times_1));
9454 negptr(len);
9455
9456 bind(copy_chars_loop);
9457 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9458 testl(tmp5, 0xff00); // check if Unicode char
9459 jccb(Assembler::notZero, reset_sp);
9460 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9461 increment(len);
9462 jccb(Assembler::notZero, copy_chars_loop);
9463
9464 // add len then return (len will be zero if compress succeeded, otherwise negative)
9465 bind(reset_sp);
9466 addl(result, len);
9467
9468 bind(done);
9469 }
9470
9471 // Inflate byte[] array to char[].
9472 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9473 // @IntrinsicCandidate
9474 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9475 // for (int i = 0; i < len; i++) {
9476 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9477 // }
9478 // }
9479 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9480 XMMRegister tmp1, Register tmp2, KRegister mask) {
9481 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9482 // rsi: src
9483 // rdi: dst
9484 // rdx: len
9485 // rcx: tmp2
9486
9487 // rsi holds start addr of source byte[] to be inflated
9488 // rdi holds start addr of destination char[]
9489 // rdx holds length
9490 assert_different_registers(src, dst, len, tmp2);
9491 movl(tmp2, len);
9492 if ((UseAVX > 2) && // AVX512
9493 VM_Version::supports_avx512vlbw() &&
9494 VM_Version::supports_bmi2()) {
9495
9496 Label copy_32_loop, copy_tail;
9497 Register tmp3_aliased = len;
9498
9499 // if length of the string is less than 16, handle it in an old fashioned way
9500 testl(len, -16);
9501 jcc(Assembler::zero, below_threshold);
9502
9503 testl(len, -1 * AVX3Threshold);
9504 jcc(Assembler::zero, avx3_threshold);
9505
9506 // In order to use only one arithmetic operation for the main loop we use
9507 // this pre-calculation
9508 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9509 andl(len, -32); // vector count
9510 jccb(Assembler::zero, copy_tail);
9511
9512 lea(src, Address(src, len, Address::times_1));
9513 lea(dst, Address(dst, len, Address::times_2));
9514 negptr(len);
9515
9516
9517 // inflate 32 chars per iter
9518 bind(copy_32_loop);
9519 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9520 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9521 addptr(len, 32);
9522 jcc(Assembler::notZero, copy_32_loop);
9523
9524 bind(copy_tail);
9525 // bail out when there is nothing to be done
9526 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9527 jcc(Assembler::zero, done);
9528
9529 // ~(~0 << length), where length is the # of remaining elements to process
9530 movl(tmp3_aliased, -1);
9531 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9532 notl(tmp3_aliased);
9533 kmovdl(mask, tmp3_aliased);
9534 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9535 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9536
9537 jmp(done);
9538 bind(avx3_threshold);
9539 }
9540 if (UseSSE42Intrinsics) {
9541 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9542
9543 if (UseAVX > 1) {
9544 andl(tmp2, (16 - 1));
9545 andl(len, -16);
9546 jccb(Assembler::zero, copy_new_tail);
9547 } else {
9548 andl(tmp2, 0x00000007); // tail count (in chars)
9549 andl(len, 0xfffffff8); // vector count (in chars)
9550 jccb(Assembler::zero, copy_tail);
9551 }
9552
9553 // vectored inflation
9554 lea(src, Address(src, len, Address::times_1));
9555 lea(dst, Address(dst, len, Address::times_2));
9556 negptr(len);
9557
9558 if (UseAVX > 1) {
9559 bind(copy_16_loop);
9560 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9561 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9562 addptr(len, 16);
9563 jcc(Assembler::notZero, copy_16_loop);
9564
9565 bind(below_threshold);
9566 bind(copy_new_tail);
9567 movl(len, tmp2);
9568 andl(tmp2, 0x00000007);
9569 andl(len, 0xFFFFFFF8);
9570 jccb(Assembler::zero, copy_tail);
9571
9572 pmovzxbw(tmp1, Address(src, 0));
9573 movdqu(Address(dst, 0), tmp1);
9574 addptr(src, 8);
9575 addptr(dst, 2 * 8);
9576
9577 jmp(copy_tail, true);
9578 }
9579
9580 // inflate 8 chars per iter
9581 bind(copy_8_loop);
9582 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9583 movdqu(Address(dst, len, Address::times_2), tmp1);
9584 addptr(len, 8);
9585 jcc(Assembler::notZero, copy_8_loop);
9586
9587 bind(copy_tail);
9588 movl(len, tmp2);
9589
9590 cmpl(len, 4);
9591 jccb(Assembler::less, copy_bytes);
9592
9593 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9594 pmovzxbw(tmp1, tmp1);
9595 movq(Address(dst, 0), tmp1);
9596 subptr(len, 4);
9597 addptr(src, 4);
9598 addptr(dst, 8);
9599
9600 bind(copy_bytes);
9601 } else {
9602 bind(below_threshold);
9603 }
9604
9605 testl(len, len);
9606 jccb(Assembler::zero, done);
9607 lea(src, Address(src, len, Address::times_1));
9608 lea(dst, Address(dst, len, Address::times_2));
9609 negptr(len);
9610
9611 // inflate 1 char per iter
9612 bind(copy_chars_loop);
9613 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9614 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9615 increment(len);
9616 jcc(Assembler::notZero, copy_chars_loop);
9617
9618 bind(done);
9619 }
9620
9621 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9622 switch(type) {
9623 case T_BYTE:
9624 case T_BOOLEAN:
9625 evmovdqub(dst, kmask, src, merge, vector_len);
9626 break;
9627 case T_CHAR:
9628 case T_SHORT:
9629 evmovdquw(dst, kmask, src, merge, vector_len);
9630 break;
9631 case T_INT:
9632 case T_FLOAT:
9633 evmovdqul(dst, kmask, src, merge, vector_len);
9634 break;
9635 case T_LONG:
9636 case T_DOUBLE:
9637 evmovdquq(dst, kmask, src, merge, vector_len);
9638 break;
9639 default:
9640 fatal("Unexpected type argument %s", type2name(type));
9641 break;
9642 }
9643 }
9644
9645
9646 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9647 switch(type) {
9648 case T_BYTE:
9649 case T_BOOLEAN:
9650 evmovdqub(dst, kmask, src, merge, vector_len);
9651 break;
9652 case T_CHAR:
9653 case T_SHORT:
9654 evmovdquw(dst, kmask, src, merge, vector_len);
9655 break;
9656 case T_INT:
9657 case T_FLOAT:
9658 evmovdqul(dst, kmask, src, merge, vector_len);
9659 break;
9660 case T_LONG:
9661 case T_DOUBLE:
9662 evmovdquq(dst, kmask, src, merge, vector_len);
9663 break;
9664 default:
9665 fatal("Unexpected type argument %s", type2name(type));
9666 break;
9667 }
9668 }
9669
9670 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9671 switch(type) {
9672 case T_BYTE:
9673 case T_BOOLEAN:
9674 evmovdqub(dst, kmask, src, merge, vector_len);
9675 break;
9676 case T_CHAR:
9677 case T_SHORT:
9678 evmovdquw(dst, kmask, src, merge, vector_len);
9679 break;
9680 case T_INT:
9681 case T_FLOAT:
9682 evmovdqul(dst, kmask, src, merge, vector_len);
9683 break;
9684 case T_LONG:
9685 case T_DOUBLE:
9686 evmovdquq(dst, kmask, src, merge, vector_len);
9687 break;
9688 default:
9689 fatal("Unexpected type argument %s", type2name(type));
9690 break;
9691 }
9692 }
9693
9694 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9695 switch(masklen) {
9696 case 2:
9697 knotbl(dst, src);
9698 movl(rtmp, 3);
9699 kmovbl(ktmp, rtmp);
9700 kandbl(dst, ktmp, dst);
9701 break;
9702 case 4:
9703 knotbl(dst, src);
9704 movl(rtmp, 15);
9705 kmovbl(ktmp, rtmp);
9706 kandbl(dst, ktmp, dst);
9707 break;
9708 case 8:
9709 knotbl(dst, src);
9710 break;
9711 case 16:
9712 knotwl(dst, src);
9713 break;
9714 case 32:
9715 knotdl(dst, src);
9716 break;
9717 case 64:
9718 knotql(dst, src);
9719 break;
9720 default:
9721 fatal("Unexpected vector length %d", masklen);
9722 break;
9723 }
9724 }
9725
9726 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9727 switch(type) {
9728 case T_BOOLEAN:
9729 case T_BYTE:
9730 kandbl(dst, src1, src2);
9731 break;
9732 case T_CHAR:
9733 case T_SHORT:
9734 kandwl(dst, src1, src2);
9735 break;
9736 case T_INT:
9737 case T_FLOAT:
9738 kanddl(dst, src1, src2);
9739 break;
9740 case T_LONG:
9741 case T_DOUBLE:
9742 kandql(dst, src1, src2);
9743 break;
9744 default:
9745 fatal("Unexpected type argument %s", type2name(type));
9746 break;
9747 }
9748 }
9749
9750 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9751 switch(type) {
9752 case T_BOOLEAN:
9753 case T_BYTE:
9754 korbl(dst, src1, src2);
9755 break;
9756 case T_CHAR:
9757 case T_SHORT:
9758 korwl(dst, src1, src2);
9759 break;
9760 case T_INT:
9761 case T_FLOAT:
9762 kordl(dst, src1, src2);
9763 break;
9764 case T_LONG:
9765 case T_DOUBLE:
9766 korql(dst, src1, src2);
9767 break;
9768 default:
9769 fatal("Unexpected type argument %s", type2name(type));
9770 break;
9771 }
9772 }
9773
9774 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9775 switch(type) {
9776 case T_BOOLEAN:
9777 case T_BYTE:
9778 kxorbl(dst, src1, src2);
9779 break;
9780 case T_CHAR:
9781 case T_SHORT:
9782 kxorwl(dst, src1, src2);
9783 break;
9784 case T_INT:
9785 case T_FLOAT:
9786 kxordl(dst, src1, src2);
9787 break;
9788 case T_LONG:
9789 case T_DOUBLE:
9790 kxorql(dst, src1, src2);
9791 break;
9792 default:
9793 fatal("Unexpected type argument %s", type2name(type));
9794 break;
9795 }
9796 }
9797
9798 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9799 switch(type) {
9800 case T_BOOLEAN:
9801 case T_BYTE:
9802 evpermb(dst, mask, nds, src, merge, vector_len); break;
9803 case T_CHAR:
9804 case T_SHORT:
9805 evpermw(dst, mask, nds, src, merge, vector_len); break;
9806 case T_INT:
9807 case T_FLOAT:
9808 evpermd(dst, mask, nds, src, merge, vector_len); break;
9809 case T_LONG:
9810 case T_DOUBLE:
9811 evpermq(dst, mask, nds, src, merge, vector_len); break;
9812 default:
9813 fatal("Unexpected type argument %s", type2name(type)); break;
9814 }
9815 }
9816
9817 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9818 switch(type) {
9819 case T_BOOLEAN:
9820 case T_BYTE:
9821 evpermb(dst, mask, nds, src, merge, vector_len); break;
9822 case T_CHAR:
9823 case T_SHORT:
9824 evpermw(dst, mask, nds, src, merge, vector_len); break;
9825 case T_INT:
9826 case T_FLOAT:
9827 evpermd(dst, mask, nds, src, merge, vector_len); break;
9828 case T_LONG:
9829 case T_DOUBLE:
9830 evpermq(dst, mask, nds, src, merge, vector_len); break;
9831 default:
9832 fatal("Unexpected type argument %s", type2name(type)); break;
9833 }
9834 }
9835
9836 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9837 switch(type) {
9838 case T_BYTE:
9839 evpminub(dst, mask, nds, src, merge, vector_len); break;
9840 case T_SHORT:
9841 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9842 case T_INT:
9843 evpminud(dst, mask, nds, src, merge, vector_len); break;
9844 case T_LONG:
9845 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9846 default:
9847 fatal("Unexpected type argument %s", type2name(type)); break;
9848 }
9849 }
9850
9851 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9852 switch(type) {
9853 case T_BYTE:
9854 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9855 case T_SHORT:
9856 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9857 case T_INT:
9858 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9859 case T_LONG:
9860 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9861 default:
9862 fatal("Unexpected type argument %s", type2name(type)); break;
9863 }
9864 }
9865
9866 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9867 switch(type) {
9868 case T_BYTE:
9869 evpminub(dst, mask, nds, src, merge, vector_len); break;
9870 case T_SHORT:
9871 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9872 case T_INT:
9873 evpminud(dst, mask, nds, src, merge, vector_len); break;
9874 case T_LONG:
9875 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9876 default:
9877 fatal("Unexpected type argument %s", type2name(type)); break;
9878 }
9879 }
9880
9881 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9882 switch(type) {
9883 case T_BYTE:
9884 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9885 case T_SHORT:
9886 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9887 case T_INT:
9888 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9889 case T_LONG:
9890 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9891 default:
9892 fatal("Unexpected type argument %s", type2name(type)); break;
9893 }
9894 }
9895
9896 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9897 switch(type) {
9898 case T_BYTE:
9899 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9900 case T_SHORT:
9901 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9902 case T_INT:
9903 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9904 case T_LONG:
9905 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9906 case T_FLOAT:
9907 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9908 case T_DOUBLE:
9909 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9910 default:
9911 fatal("Unexpected type argument %s", type2name(type)); break;
9912 }
9913 }
9914
9915 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9916 switch(type) {
9917 case T_BYTE:
9918 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9919 case T_SHORT:
9920 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9921 case T_INT:
9922 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9923 case T_LONG:
9924 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9925 case T_FLOAT:
9926 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9927 case T_DOUBLE:
9928 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9929 default:
9930 fatal("Unexpected type argument %s", type2name(type)); break;
9931 }
9932 }
9933
9934 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9935 switch(type) {
9936 case T_BYTE:
9937 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9938 case T_SHORT:
9939 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9940 case T_INT:
9941 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9942 case T_LONG:
9943 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9944 case T_FLOAT:
9945 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9946 case T_DOUBLE:
9947 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9948 default:
9949 fatal("Unexpected type argument %s", type2name(type)); break;
9950 }
9951 }
9952
9953 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9954 switch(type) {
9955 case T_BYTE:
9956 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9957 case T_SHORT:
9958 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9959 case T_INT:
9960 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9961 case T_LONG:
9962 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9963 case T_FLOAT:
9964 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9965 case T_DOUBLE:
9966 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9967 default:
9968 fatal("Unexpected type argument %s", type2name(type)); break;
9969 }
9970 }
9971
9972 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9973 switch(type) {
9974 case T_INT:
9975 evpxord(dst, mask, nds, src, merge, vector_len); break;
9976 case T_LONG:
9977 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9978 default:
9979 fatal("Unexpected type argument %s", type2name(type)); break;
9980 }
9981 }
9982
9983 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9984 switch(type) {
9985 case T_INT:
9986 evpxord(dst, mask, nds, src, merge, vector_len); break;
9987 case T_LONG:
9988 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9989 default:
9990 fatal("Unexpected type argument %s", type2name(type)); break;
9991 }
9992 }
9993
9994 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9995 switch(type) {
9996 case T_INT:
9997 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9998 case T_LONG:
9999 evporq(dst, mask, nds, src, merge, vector_len); break;
10000 default:
10001 fatal("Unexpected type argument %s", type2name(type)); break;
10002 }
10003 }
10004
10005 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10006 switch(type) {
10007 case T_INT:
10008 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10009 case T_LONG:
10010 evporq(dst, mask, nds, src, merge, vector_len); break;
10011 default:
10012 fatal("Unexpected type argument %s", type2name(type)); break;
10013 }
10014 }
10015
10016 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10017 switch(type) {
10018 case T_INT:
10019 evpandd(dst, mask, nds, src, merge, vector_len); break;
10020 case T_LONG:
10021 evpandq(dst, mask, nds, src, merge, vector_len); break;
10022 default:
10023 fatal("Unexpected type argument %s", type2name(type)); break;
10024 }
10025 }
10026
10027 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10028 switch(type) {
10029 case T_INT:
10030 evpandd(dst, mask, nds, src, merge, vector_len); break;
10031 case T_LONG:
10032 evpandq(dst, mask, nds, src, merge, vector_len); break;
10033 default:
10034 fatal("Unexpected type argument %s", type2name(type)); break;
10035 }
10036 }
10037
10038 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
10039 switch(masklen) {
10040 case 8:
10041 kortestbl(src1, src2);
10042 break;
10043 case 16:
10044 kortestwl(src1, src2);
10045 break;
10046 case 32:
10047 kortestdl(src1, src2);
10048 break;
10049 case 64:
10050 kortestql(src1, src2);
10051 break;
10052 default:
10053 fatal("Unexpected mask length %d", masklen);
10054 break;
10055 }
10056 }
10057
10058
10059 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
10060 switch(masklen) {
10061 case 8:
10062 ktestbl(src1, src2);
10063 break;
10064 case 16:
10065 ktestwl(src1, src2);
10066 break;
10067 case 32:
10068 ktestdl(src1, src2);
10069 break;
10070 case 64:
10071 ktestql(src1, src2);
10072 break;
10073 default:
10074 fatal("Unexpected mask length %d", masklen);
10075 break;
10076 }
10077 }
10078
10079 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10080 switch(type) {
10081 case T_INT:
10082 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10083 case T_LONG:
10084 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10085 default:
10086 fatal("Unexpected type argument %s", type2name(type)); break;
10087 break;
10088 }
10089 }
10090
10091 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10092 switch(type) {
10093 case T_INT:
10094 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10095 case T_LONG:
10096 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10097 default:
10098 fatal("Unexpected type argument %s", type2name(type)); break;
10099 }
10100 }
10101
10102 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10103 switch(type) {
10104 case T_INT:
10105 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10106 case T_LONG:
10107 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10108 default:
10109 fatal("Unexpected type argument %s", type2name(type)); break;
10110 }
10111 }
10112
10113 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10114 switch(type) {
10115 case T_INT:
10116 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10117 case T_LONG:
10118 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10119 default:
10120 fatal("Unexpected type argument %s", type2name(type)); break;
10121 }
10122 }
10123
10124 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10125 assert(rscratch != noreg || always_reachable(src), "missing");
10126
10127 if (reachable(src)) {
10128 evpandq(dst, nds, as_Address(src), vector_len);
10129 } else {
10130 lea(rscratch, src);
10131 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10132 }
10133 }
10134
10135 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10136 assert(rscratch != noreg || always_reachable(src), "missing");
10137
10138 if (reachable(src)) {
10139 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10140 } else {
10141 lea(rscratch, src);
10142 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10143 }
10144 }
10145
10146 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10147 assert(rscratch != noreg || always_reachable(src), "missing");
10148
10149 if (reachable(src)) {
10150 evporq(dst, nds, as_Address(src), vector_len);
10151 } else {
10152 lea(rscratch, src);
10153 evporq(dst, nds, Address(rscratch, 0), vector_len);
10154 }
10155 }
10156
10157 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10158 assert(rscratch != noreg || always_reachable(src), "missing");
10159
10160 if (reachable(src)) {
10161 vpshufb(dst, nds, as_Address(src), vector_len);
10162 } else {
10163 lea(rscratch, src);
10164 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10165 }
10166 }
10167
10168 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10169 assert(rscratch != noreg || always_reachable(src), "missing");
10170
10171 if (reachable(src)) {
10172 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10173 } else {
10174 lea(rscratch, src);
10175 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10176 }
10177 }
10178
10179 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10180 assert(rscratch != noreg || always_reachable(src3), "missing");
10181
10182 if (reachable(src3)) {
10183 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10184 } else {
10185 lea(rscratch, src3);
10186 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10187 }
10188 }
10189
10190 #if COMPILER2_OR_JVMCI
10191
10192 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10193 Register length, Register temp, int vec_enc) {
10194 // Computing mask for predicated vector store.
10195 movptr(temp, -1);
10196 bzhiq(temp, temp, length);
10197 kmov(mask, temp);
10198 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10199 }
10200
10201 // Set memory operation for length "less than" 64 bytes.
10202 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10203 XMMRegister xmm, KRegister mask, Register length,
10204 Register temp, bool use64byteVector) {
10205 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10206 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10207 if (!use64byteVector) {
10208 fill32(dst, disp, xmm);
10209 subptr(length, 32 >> shift);
10210 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10211 } else {
10212 assert(MaxVectorSize == 64, "vector length != 64");
10213 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10214 }
10215 }
10216
10217
10218 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10219 XMMRegister xmm, KRegister mask, Register length,
10220 Register temp) {
10221 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10222 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10223 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10224 }
10225
10226
10227 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10228 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10229 vmovdqu(dst, xmm);
10230 }
10231
10232 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10233 fill32(Address(dst, disp), xmm);
10234 }
10235
10236 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10237 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10238 if (!use64byteVector) {
10239 fill32(dst, xmm);
10240 fill32(dst.plus_disp(32), xmm);
10241 } else {
10242 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10243 }
10244 }
10245
10246 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10247 fill64(Address(dst, disp), xmm, use64byteVector);
10248 }
10249
10250 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10251 Register count, Register rtmp, XMMRegister xtmp) {
10252 Label L_exit;
10253 Label L_fill_start;
10254 Label L_fill_64_bytes;
10255 Label L_fill_96_bytes;
10256 Label L_fill_128_bytes;
10257 Label L_fill_128_bytes_loop;
10258 Label L_fill_128_loop_header;
10259 Label L_fill_128_bytes_loop_header;
10260 Label L_fill_128_bytes_loop_pre_header;
10261 Label L_fill_zmm_sequence;
10262
10263 int shift = -1;
10264 int avx3threshold = VM_Version::avx3_threshold();
10265 switch(type) {
10266 case T_BYTE: shift = 0;
10267 break;
10268 case T_SHORT: shift = 1;
10269 break;
10270 case T_INT: shift = 2;
10271 break;
10272 /* Uncomment when LONG fill stubs are supported.
10273 case T_LONG: shift = 3;
10274 break;
10275 */
10276 default:
10277 fatal("Unhandled type: %s\n", type2name(type));
10278 }
10279
10280 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
10281
10282 if (MaxVectorSize == 64) {
10283 cmpq(count, avx3threshold >> shift);
10284 jcc(Assembler::greater, L_fill_zmm_sequence);
10285 }
10286
10287 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10288
10289 bind(L_fill_start);
10290
10291 cmpq(count, 32 >> shift);
10292 jccb(Assembler::greater, L_fill_64_bytes);
10293 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10294 jmp(L_exit);
10295
10296 bind(L_fill_64_bytes);
10297 cmpq(count, 64 >> shift);
10298 jccb(Assembler::greater, L_fill_96_bytes);
10299 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10300 jmp(L_exit);
10301
10302 bind(L_fill_96_bytes);
10303 cmpq(count, 96 >> shift);
10304 jccb(Assembler::greater, L_fill_128_bytes);
10305 fill64(to, 0, xtmp);
10306 subq(count, 64 >> shift);
10307 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10308 jmp(L_exit);
10309
10310 bind(L_fill_128_bytes);
10311 cmpq(count, 128 >> shift);
10312 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10313 fill64(to, 0, xtmp);
10314 fill32(to, 64, xtmp);
10315 subq(count, 96 >> shift);
10316 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10317 jmp(L_exit);
10318
10319 bind(L_fill_128_bytes_loop_pre_header);
10320 {
10321 mov(rtmp, to);
10322 andq(rtmp, 31);
10323 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10324 negq(rtmp);
10325 addq(rtmp, 32);
10326 mov64(r8, -1L);
10327 bzhiq(r8, r8, rtmp);
10328 kmovql(k2, r8);
10329 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10330 addq(to, rtmp);
10331 shrq(rtmp, shift);
10332 subq(count, rtmp);
10333 }
10334
10335 cmpq(count, 128 >> shift);
10336 jcc(Assembler::less, L_fill_start);
10337
10338 bind(L_fill_128_bytes_loop_header);
10339 subq(count, 128 >> shift);
10340
10341 align32();
10342 bind(L_fill_128_bytes_loop);
10343 fill64(to, 0, xtmp);
10344 fill64(to, 64, xtmp);
10345 addq(to, 128);
10346 subq(count, 128 >> shift);
10347 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10348
10349 addq(count, 128 >> shift);
10350 jcc(Assembler::zero, L_exit);
10351 jmp(L_fill_start);
10352 }
10353
10354 if (MaxVectorSize == 64) {
10355 // Sequence using 64 byte ZMM register.
10356 Label L_fill_128_bytes_zmm;
10357 Label L_fill_192_bytes_zmm;
10358 Label L_fill_192_bytes_loop_zmm;
10359 Label L_fill_192_bytes_loop_header_zmm;
10360 Label L_fill_192_bytes_loop_pre_header_zmm;
10361 Label L_fill_start_zmm_sequence;
10362
10363 bind(L_fill_zmm_sequence);
10364 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10365
10366 bind(L_fill_start_zmm_sequence);
10367 cmpq(count, 64 >> shift);
10368 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10369 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10370 jmp(L_exit);
10371
10372 bind(L_fill_128_bytes_zmm);
10373 cmpq(count, 128 >> shift);
10374 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10375 fill64(to, 0, xtmp, true);
10376 subq(count, 64 >> shift);
10377 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10378 jmp(L_exit);
10379
10380 bind(L_fill_192_bytes_zmm);
10381 cmpq(count, 192 >> shift);
10382 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10383 fill64(to, 0, xtmp, true);
10384 fill64(to, 64, xtmp, true);
10385 subq(count, 128 >> shift);
10386 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10387 jmp(L_exit);
10388
10389 bind(L_fill_192_bytes_loop_pre_header_zmm);
10390 {
10391 movq(rtmp, to);
10392 andq(rtmp, 63);
10393 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10394 negq(rtmp);
10395 addq(rtmp, 64);
10396 mov64(r8, -1L);
10397 bzhiq(r8, r8, rtmp);
10398 kmovql(k2, r8);
10399 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10400 addq(to, rtmp);
10401 shrq(rtmp, shift);
10402 subq(count, rtmp);
10403 }
10404
10405 cmpq(count, 192 >> shift);
10406 jcc(Assembler::less, L_fill_start_zmm_sequence);
10407
10408 bind(L_fill_192_bytes_loop_header_zmm);
10409 subq(count, 192 >> shift);
10410
10411 align32();
10412 bind(L_fill_192_bytes_loop_zmm);
10413 fill64(to, 0, xtmp, true);
10414 fill64(to, 64, xtmp, true);
10415 fill64(to, 128, xtmp, true);
10416 addq(to, 192);
10417 subq(count, 192 >> shift);
10418 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10419
10420 addq(count, 192 >> shift);
10421 jcc(Assembler::zero, L_exit);
10422 jmp(L_fill_start_zmm_sequence);
10423 }
10424 bind(L_exit);
10425 }
10426 #endif //COMPILER2_OR_JVMCI
10427
10428
10429 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10430 Label done;
10431 cvttss2sil(dst, src);
10432 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10433 cmpl(dst, 0x80000000); // float_sign_flip
10434 jccb(Assembler::notEqual, done);
10435 subptr(rsp, 8);
10436 movflt(Address(rsp, 0), src);
10437 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10438 pop(dst);
10439 bind(done);
10440 }
10441
10442 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10443 Label done;
10444 cvttsd2sil(dst, src);
10445 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10446 cmpl(dst, 0x80000000); // float_sign_flip
10447 jccb(Assembler::notEqual, done);
10448 subptr(rsp, 8);
10449 movdbl(Address(rsp, 0), src);
10450 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10451 pop(dst);
10452 bind(done);
10453 }
10454
10455 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10456 Label done;
10457 cvttss2siq(dst, src);
10458 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10459 jccb(Assembler::notEqual, done);
10460 subptr(rsp, 8);
10461 movflt(Address(rsp, 0), src);
10462 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10463 pop(dst);
10464 bind(done);
10465 }
10466
10467 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10468 // Following code is line by line assembly translation rounding algorithm.
10469 // Please refer to java.lang.Math.round(float) algorithm for details.
10470 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10471 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10472 const int32_t FloatConsts_EXP_BIAS = 127;
10473 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10474 const int32_t MINUS_32 = 0xFFFFFFE0;
10475 Label L_special_case, L_block1, L_exit;
10476 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10477 movdl(dst, src);
10478 andl(dst, rtmp);
10479 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10480 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10481 subl(rtmp, dst);
10482 movl(rcx, rtmp);
10483 movl(dst, MINUS_32);
10484 testl(rtmp, dst);
10485 jccb(Assembler::notEqual, L_special_case);
10486 movdl(dst, src);
10487 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10488 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10489 movdl(rtmp, src);
10490 testl(rtmp, rtmp);
10491 jccb(Assembler::greaterEqual, L_block1);
10492 negl(dst);
10493 bind(L_block1);
10494 sarl(dst);
10495 addl(dst, 0x1);
10496 sarl(dst, 0x1);
10497 jmp(L_exit);
10498 bind(L_special_case);
10499 convert_f2i(dst, src);
10500 bind(L_exit);
10501 }
10502
10503 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10504 // Following code is line by line assembly translation rounding algorithm.
10505 // Please refer to java.lang.Math.round(double) algorithm for details.
10506 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10507 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10508 const int64_t DoubleConsts_EXP_BIAS = 1023;
10509 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10510 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10511 Label L_special_case, L_block1, L_exit;
10512 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10513 movq(dst, src);
10514 andq(dst, rtmp);
10515 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10516 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10517 subq(rtmp, dst);
10518 movq(rcx, rtmp);
10519 mov64(dst, MINUS_64);
10520 testq(rtmp, dst);
10521 jccb(Assembler::notEqual, L_special_case);
10522 movq(dst, src);
10523 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10524 andq(dst, rtmp);
10525 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10526 orq(dst, rtmp);
10527 movq(rtmp, src);
10528 testq(rtmp, rtmp);
10529 jccb(Assembler::greaterEqual, L_block1);
10530 negq(dst);
10531 bind(L_block1);
10532 sarq(dst);
10533 addq(dst, 0x1);
10534 sarq(dst, 0x1);
10535 jmp(L_exit);
10536 bind(L_special_case);
10537 convert_d2l(dst, src);
10538 bind(L_exit);
10539 }
10540
10541 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10542 Label done;
10543 cvttsd2siq(dst, src);
10544 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10545 jccb(Assembler::notEqual, done);
10546 subptr(rsp, 8);
10547 movdbl(Address(rsp, 0), src);
10548 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10549 pop(dst);
10550 bind(done);
10551 }
10552
10553 void MacroAssembler::cache_wb(Address line)
10554 {
10555 // 64 bit cpus always support clflush
10556 assert(VM_Version::supports_clflush(), "clflush should be available");
10557 bool optimized = VM_Version::supports_clflushopt();
10558 bool no_evict = VM_Version::supports_clwb();
10559
10560 // prefer clwb (writeback without evict) otherwise
10561 // prefer clflushopt (potentially parallel writeback with evict)
10562 // otherwise fallback on clflush (serial writeback with evict)
10563
10564 if (optimized) {
10565 if (no_evict) {
10566 clwb(line);
10567 } else {
10568 clflushopt(line);
10569 }
10570 } else {
10571 // no need for fence when using CLFLUSH
10572 clflush(line);
10573 }
10574 }
10575
10576 void MacroAssembler::cache_wbsync(bool is_pre)
10577 {
10578 assert(VM_Version::supports_clflush(), "clflush should be available");
10579 bool optimized = VM_Version::supports_clflushopt();
10580 bool no_evict = VM_Version::supports_clwb();
10581
10582 // pick the correct implementation
10583
10584 if (!is_pre && (optimized || no_evict)) {
10585 // need an sfence for post flush when using clflushopt or clwb
10586 // otherwise no no need for any synchroniaztion
10587
10588 sfence();
10589 }
10590 }
10591
10592 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10593 switch (cond) {
10594 // Note some conditions are synonyms for others
10595 case Assembler::zero: return Assembler::notZero;
10596 case Assembler::notZero: return Assembler::zero;
10597 case Assembler::less: return Assembler::greaterEqual;
10598 case Assembler::lessEqual: return Assembler::greater;
10599 case Assembler::greater: return Assembler::lessEqual;
10600 case Assembler::greaterEqual: return Assembler::less;
10601 case Assembler::below: return Assembler::aboveEqual;
10602 case Assembler::belowEqual: return Assembler::above;
10603 case Assembler::above: return Assembler::belowEqual;
10604 case Assembler::aboveEqual: return Assembler::below;
10605 case Assembler::overflow: return Assembler::noOverflow;
10606 case Assembler::noOverflow: return Assembler::overflow;
10607 case Assembler::negative: return Assembler::positive;
10608 case Assembler::positive: return Assembler::negative;
10609 case Assembler::parity: return Assembler::noParity;
10610 case Assembler::noParity: return Assembler::parity;
10611 }
10612 ShouldNotReachHere(); return Assembler::overflow;
10613 }
10614
10615 // This is simply a call to Thread::current()
10616 void MacroAssembler::get_thread_slow(Register thread) {
10617 if (thread != rax) {
10618 push(rax);
10619 }
10620 push(rdi);
10621 push(rsi);
10622 push(rdx);
10623 push(rcx);
10624 push(r8);
10625 push(r9);
10626 push(r10);
10627 push(r11);
10628
10629 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10630
10631 pop(r11);
10632 pop(r10);
10633 pop(r9);
10634 pop(r8);
10635 pop(rcx);
10636 pop(rdx);
10637 pop(rsi);
10638 pop(rdi);
10639 if (thread != rax) {
10640 mov(thread, rax);
10641 pop(rax);
10642 }
10643 }
10644
10645 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10646 Label L_stack_ok;
10647 if (bias == 0) {
10648 testptr(sp, 2 * wordSize - 1);
10649 } else {
10650 // lea(tmp, Address(rsp, bias);
10651 mov(tmp, sp);
10652 addptr(tmp, bias);
10653 testptr(tmp, 2 * wordSize - 1);
10654 }
10655 jcc(Assembler::equal, L_stack_ok);
10656 block_comment(msg);
10657 stop(msg);
10658 bind(L_stack_ok);
10659 }
10660
10661 // Implements fast-locking.
10662 //
10663 // obj: the object to be locked
10664 // reg_rax: rax
10665 // thread: the thread which attempts to lock obj
10666 // tmp: a temporary register
10667 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow) {
10668 Register thread = r15_thread;
10669
10670 assert(reg_rax == rax, "");
10671 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10672
10673 Label push;
10674 const Register top = tmp;
10675
10676 // Preload the markWord. It is important that this is the first
10677 // instruction emitted as it is part of C1's null check semantics.
10678 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10679
10680 if (UseObjectMonitorTable) {
10681 // Clear cache in case fast locking succeeds or we need to take the slow-path.
10682 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10683 }
10684
10685 if (DiagnoseSyncOnValueBasedClasses != 0) {
10686 load_klass(tmp, obj, rscratch1);
10687 testb(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
10688 jcc(Assembler::notZero, slow);
10689 }
10690
10691 // Load top.
10692 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10693
10694 // Check if the lock-stack is full.
10695 cmpl(top, LockStack::end_offset());
10696 jcc(Assembler::greaterEqual, slow);
10697
10698 // Check for recursion.
10699 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10700 jcc(Assembler::equal, push);
10701
10702 // Check header for monitor (0b10).
10703 testptr(reg_rax, markWord::monitor_value);
10704 jcc(Assembler::notZero, slow);
10705
10706 // Try to lock. Transition lock bits 0b01 => 0b00
10707 movptr(tmp, reg_rax);
10708 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10709 orptr(reg_rax, markWord::unlocked_value);
10710 // Mask inline_type bit such that we go to the slow path if object is an inline type
10711 andptr(reg_rax, ~((int) markWord::inline_type_bit_in_place));
10712
10713 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10714 jcc(Assembler::notEqual, slow);
10715
10716 // Restore top, CAS clobbers register.
10717 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10718
10719 bind(push);
10720 // After successful lock, push object on lock-stack.
10721 movptr(Address(thread, top), obj);
10722 incrementl(top, oopSize);
10723 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10724 }
10725
10726 // Implements fast-unlocking.
10727 //
10728 // obj: the object to be unlocked
10729 // reg_rax: rax
10730 // thread: the thread
10731 // tmp: a temporary register
10732 void MacroAssembler::fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow) {
10733 Register thread = r15_thread;
10734
10735 assert(reg_rax == rax, "");
10736 assert_different_registers(obj, reg_rax, thread, tmp);
10737
10738 Label unlocked, push_and_slow;
10739 const Register top = tmp;
10740
10741 // Check if obj is top of lock-stack.
10742 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10743 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10744 jcc(Assembler::notEqual, slow);
10745
10746 // Pop lock-stack.
10747 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10748 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10749
10750 // Check if recursive.
10751 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10752 jcc(Assembler::equal, unlocked);
10753
10754 // Not recursive. Check header for monitor (0b10).
10755 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10756 testptr(reg_rax, markWord::monitor_value);
10757 jcc(Assembler::notZero, push_and_slow);
10758
10759 #ifdef ASSERT
10760 // Check header not unlocked (0b01).
10761 Label not_unlocked;
10762 testptr(reg_rax, markWord::unlocked_value);
10763 jcc(Assembler::zero, not_unlocked);
10764 stop("fast_unlock already unlocked");
10765 bind(not_unlocked);
10766 #endif
10767
10768 // Try to unlock. Transition lock bits 0b00 => 0b01
10769 movptr(tmp, reg_rax);
10770 orptr(tmp, markWord::unlocked_value);
10771 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10772 jcc(Assembler::equal, unlocked);
10773
10774 bind(push_and_slow);
10775 // Restore lock-stack and handle the unlock in runtime.
10776 #ifdef ASSERT
10777 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10778 movptr(Address(thread, top), obj);
10779 #endif
10780 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10781 jmp(slow);
10782
10783 bind(unlocked);
10784 }
10785
10786 // Saves legacy GPRs state on stack.
10787 void MacroAssembler::save_legacy_gprs() {
10788 subq(rsp, 16 * wordSize);
10789 movq(Address(rsp, 15 * wordSize), rax);
10790 movq(Address(rsp, 14 * wordSize), rcx);
10791 movq(Address(rsp, 13 * wordSize), rdx);
10792 movq(Address(rsp, 12 * wordSize), rbx);
10793 movq(Address(rsp, 10 * wordSize), rbp);
10794 movq(Address(rsp, 9 * wordSize), rsi);
10795 movq(Address(rsp, 8 * wordSize), rdi);
10796 movq(Address(rsp, 7 * wordSize), r8);
10797 movq(Address(rsp, 6 * wordSize), r9);
10798 movq(Address(rsp, 5 * wordSize), r10);
10799 movq(Address(rsp, 4 * wordSize), r11);
10800 movq(Address(rsp, 3 * wordSize), r12);
10801 movq(Address(rsp, 2 * wordSize), r13);
10802 movq(Address(rsp, wordSize), r14);
10803 movq(Address(rsp, 0), r15);
10804 }
10805
10806 // Resotres back legacy GPRs state from stack.
10807 void MacroAssembler::restore_legacy_gprs() {
10808 movq(r15, Address(rsp, 0));
10809 movq(r14, Address(rsp, wordSize));
10810 movq(r13, Address(rsp, 2 * wordSize));
10811 movq(r12, Address(rsp, 3 * wordSize));
10812 movq(r11, Address(rsp, 4 * wordSize));
10813 movq(r10, Address(rsp, 5 * wordSize));
10814 movq(r9, Address(rsp, 6 * wordSize));
10815 movq(r8, Address(rsp, 7 * wordSize));
10816 movq(rdi, Address(rsp, 8 * wordSize));
10817 movq(rsi, Address(rsp, 9 * wordSize));
10818 movq(rbp, Address(rsp, 10 * wordSize));
10819 movq(rbx, Address(rsp, 12 * wordSize));
10820 movq(rdx, Address(rsp, 13 * wordSize));
10821 movq(rcx, Address(rsp, 14 * wordSize));
10822 movq(rax, Address(rsp, 15 * wordSize));
10823 addq(rsp, 16 * wordSize);
10824 }
10825
10826 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10827 if (VM_Version::supports_apx_f()) {
10828 esetzucc(comparison, dst);
10829 } else {
10830 setb(comparison, dst);
10831 movzbl(dst, dst);
10832 }
10833 }