1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/aotCodeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "ci/ciInlineKlass.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "interpreter/interpreterRuntime.hpp"
40 #include "jvm.h"
41 #include "memory/resourceArea.hpp"
42 #include "memory/universe.hpp"
43 #include "oops/accessDecorators.hpp"
44 #include "oops/compressedKlass.inline.hpp"
45 #include "oops/compressedOops.inline.hpp"
46 #include "oops/klass.inline.hpp"
47 #include "oops/resolvedFieldEntry.hpp"
48 #include "prims/methodHandles.hpp"
49 #include "runtime/arguments.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/interfaceSupport.inline.hpp"
52 #include "runtime/javaThread.hpp"
53 #include "runtime/jniHandles.hpp"
54 #include "runtime/objectMonitor.hpp"
55 #include "runtime/os.hpp"
56 #include "runtime/safepoint.hpp"
57 #include "runtime/safepointMechanism.hpp"
58 #include "runtime/sharedRuntime.hpp"
59 #include "runtime/signature_cc.hpp"
60 #include "runtime/stubRoutines.hpp"
61 #include "utilities/checkedCast.hpp"
62 #include "utilities/globalDefinitions.hpp"
63 #include "utilities/macros.hpp"
64 #include "vmreg_x86.inline.hpp"
65 #ifdef COMPILER2
66 #include "opto/output.hpp"
67 #endif
68
69 #ifdef PRODUCT
70 #define BLOCK_COMMENT(str) /* nothing */
71 #define STOP(error) stop(error)
72 #else
73 #define BLOCK_COMMENT(str) block_comment(str)
74 #define STOP(error) block_comment(error); stop(error)
75 #endif
76
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
79 #ifdef ASSERT
80 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
81 #endif
82
83 static const Assembler::Condition reverse[] = {
84 Assembler::noOverflow /* overflow = 0x0 */ ,
85 Assembler::overflow /* noOverflow = 0x1 */ ,
86 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
87 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
88 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
89 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
90 Assembler::above /* belowEqual = 0x6 */ ,
91 Assembler::belowEqual /* above = 0x7 */ ,
92 Assembler::positive /* negative = 0x8 */ ,
93 Assembler::negative /* positive = 0x9 */ ,
94 Assembler::noParity /* parity = 0xa */ ,
95 Assembler::parity /* noParity = 0xb */ ,
96 Assembler::greaterEqual /* less = 0xc */ ,
97 Assembler::less /* greaterEqual = 0xd */ ,
98 Assembler::greater /* lessEqual = 0xe */ ,
99 Assembler::lessEqual /* greater = 0xf, */
100
101 };
102
103
104 // Implementation of MacroAssembler
105
106 Address MacroAssembler::as_Address(AddressLiteral adr) {
107 // amd64 always does this as a pc-rel
108 // we can be absolute or disp based on the instruction type
109 // jmp/call are displacements others are absolute
110 assert(!adr.is_lval(), "must be rval");
111 assert(reachable(adr), "must be");
112 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
113
114 }
115
116 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
117 AddressLiteral base = adr.base();
118 lea(rscratch, base);
119 Address index = adr.index();
120 assert(index._disp == 0, "must not have disp"); // maybe it can?
121 Address array(rscratch, index._index, index._scale, index._disp);
122 return array;
123 }
124
125 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
126 Label L, E;
127
128 #ifdef _WIN64
129 // Windows always allocates space for it's register args
130 assert(num_args <= 4, "only register arguments supported");
131 subq(rsp, frame::arg_reg_save_area_bytes);
132 #endif
133
134 // Align stack if necessary
135 testl(rsp, 15);
136 jcc(Assembler::zero, L);
137
138 subq(rsp, 8);
139 call(RuntimeAddress(entry_point));
140 addq(rsp, 8);
141 jmp(E);
142
143 bind(L);
144 call(RuntimeAddress(entry_point));
145
146 bind(E);
147
148 #ifdef _WIN64
149 // restore stack pointer
150 addq(rsp, frame::arg_reg_save_area_bytes);
151 #endif
152 }
153
154 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
155 assert(!src2.is_lval(), "should use cmpptr");
156 assert(rscratch != noreg || always_reachable(src2), "missing");
157
158 if (reachable(src2)) {
159 cmpq(src1, as_Address(src2));
160 } else {
161 lea(rscratch, src2);
162 Assembler::cmpq(src1, Address(rscratch, 0));
163 }
164 }
165
166 int MacroAssembler::corrected_idivq(Register reg) {
167 // Full implementation of Java ldiv and lrem; checks for special
168 // case as described in JVM spec., p.243 & p.271. The function
169 // returns the (pc) offset of the idivl instruction - may be needed
170 // for implicit exceptions.
171 //
172 // normal case special case
173 //
174 // input : rax: dividend min_long
175 // reg: divisor (may not be eax/edx) -1
176 //
177 // output: rax: quotient (= rax idiv reg) min_long
178 // rdx: remainder (= rax irem reg) 0
179 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
180 static const int64_t min_long = 0x8000000000000000;
181 Label normal_case, special_case;
182
183 // check for special case
184 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
185 jcc(Assembler::notEqual, normal_case);
186 xorl(rdx, rdx); // prepare rdx for possible special case (where
187 // remainder = 0)
188 cmpq(reg, -1);
189 jcc(Assembler::equal, special_case);
190
191 // handle normal case
192 bind(normal_case);
193 cdqq();
194 int idivq_offset = offset();
195 idivq(reg);
196
197 // normal and special case exit
198 bind(special_case);
199
200 return idivq_offset;
201 }
202
203 void MacroAssembler::decrementq(Register reg, int value) {
204 if (value == min_jint) { subq(reg, value); return; }
205 if (value < 0) { incrementq(reg, -value); return; }
206 if (value == 0) { ; return; }
207 if (value == 1 && UseIncDec) { decq(reg) ; return; }
208 /* else */ { subq(reg, value) ; return; }
209 }
210
211 void MacroAssembler::decrementq(Address dst, int value) {
212 if (value == min_jint) { subq(dst, value); return; }
213 if (value < 0) { incrementq(dst, -value); return; }
214 if (value == 0) { ; return; }
215 if (value == 1 && UseIncDec) { decq(dst) ; return; }
216 /* else */ { subq(dst, value) ; return; }
217 }
218
219 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
220 assert(rscratch != noreg || always_reachable(dst), "missing");
221
222 if (reachable(dst)) {
223 incrementq(as_Address(dst));
224 } else {
225 lea(rscratch, dst);
226 incrementq(Address(rscratch, 0));
227 }
228 }
229
230 void MacroAssembler::incrementq(Register reg, int value) {
231 if (value == min_jint) { addq(reg, value); return; }
232 if (value < 0) { decrementq(reg, -value); return; }
233 if (value == 0) { ; return; }
234 if (value == 1 && UseIncDec) { incq(reg) ; return; }
235 /* else */ { addq(reg, value) ; return; }
236 }
237
238 void MacroAssembler::incrementq(Address dst, int value) {
239 if (value == min_jint) { addq(dst, value); return; }
240 if (value < 0) { decrementq(dst, -value); return; }
241 if (value == 0) { ; return; }
242 if (value == 1 && UseIncDec) { incq(dst) ; return; }
243 /* else */ { addq(dst, value) ; return; }
244 }
245
246 // 32bit can do a case table jump in one instruction but we no longer allow the base
247 // to be installed in the Address class
248 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
249 lea(rscratch, entry.base());
250 Address dispatch = entry.index();
251 assert(dispatch._base == noreg, "must be");
252 dispatch._base = rscratch;
253 jmp(dispatch);
254 }
255
256 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
257 ShouldNotReachHere(); // 64bit doesn't use two regs
258 cmpq(x_lo, y_lo);
259 }
260
261 void MacroAssembler::lea(Register dst, AddressLiteral src) {
262 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
263 }
264
265 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
266 lea(rscratch, adr);
267 movptr(dst, rscratch);
268 }
269
270 void MacroAssembler::leave() {
271 // %%% is this really better? Why not on 32bit too?
272 emit_int8((unsigned char)0xC9); // LEAVE
273 }
274
275 void MacroAssembler::lneg(Register hi, Register lo) {
276 ShouldNotReachHere(); // 64bit doesn't use two regs
277 negq(lo);
278 }
279
280 void MacroAssembler::movoop(Register dst, jobject obj) {
281 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
282 }
283
284 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
285 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
286 movq(dst, rscratch);
287 }
288
289 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
290 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
291 }
292
293 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
294 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
295 movq(dst, rscratch);
296 }
297
298 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
299 if (src.is_lval()) {
300 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
301 } else {
302 if (reachable(src)) {
303 movq(dst, as_Address(src));
304 } else {
305 lea(dst, src);
306 movq(dst, Address(dst, 0));
307 }
308 }
309 }
310
311 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
312 movq(as_Address(dst, rscratch), src);
313 }
314
315 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
316 movq(dst, as_Address(src, dst /*rscratch*/));
317 }
318
319 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
320 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
321 if (is_simm32(src)) {
322 movptr(dst, checked_cast<int32_t>(src));
323 } else {
324 mov64(rscratch, src);
325 movq(dst, rscratch);
326 }
327 }
328
329 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
330 movoop(rscratch, obj);
331 push(rscratch);
332 }
333
334 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
335 mov_metadata(rscratch, obj);
336 push(rscratch);
337 }
338
339 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
340 lea(rscratch, src);
341 if (src.is_lval()) {
342 push(rscratch);
343 } else {
344 pushq(Address(rscratch, 0));
345 }
346 }
347
348 static void pass_arg0(MacroAssembler* masm, Register arg) {
349 if (c_rarg0 != arg ) {
350 masm->mov(c_rarg0, arg);
351 }
352 }
353
354 static void pass_arg1(MacroAssembler* masm, Register arg) {
355 if (c_rarg1 != arg ) {
356 masm->mov(c_rarg1, arg);
357 }
358 }
359
360 static void pass_arg2(MacroAssembler* masm, Register arg) {
361 if (c_rarg2 != arg ) {
362 masm->mov(c_rarg2, arg);
363 }
364 }
365
366 static void pass_arg3(MacroAssembler* masm, Register arg) {
367 if (c_rarg3 != arg ) {
368 masm->mov(c_rarg3, arg);
369 }
370 }
371
372 void MacroAssembler::stop(const char* msg) {
373 if (ShowMessageBoxOnError) {
374 address rip = pc();
375 pusha(); // get regs on stack
376 lea(c_rarg1, InternalAddress(rip));
377 movq(c_rarg2, rsp); // pass pointer to regs array
378 }
379 // Skip AOT caching C strings in scratch buffer.
380 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
381 lea(c_rarg0, ExternalAddress((address) str));
382 andq(rsp, -16); // align stack as required by ABI
383 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
384 hlt();
385 }
386
387 void MacroAssembler::warn(const char* msg) {
388 push(rbp);
389 movq(rbp, rsp);
390 andq(rsp, -16); // align stack as required by push_CPU_state and call
391 push_CPU_state(); // keeps alignment at 16 bytes
392
393 #ifdef _WIN64
394 // Windows always allocates space for its register args
395 subq(rsp, frame::arg_reg_save_area_bytes);
396 #endif
397 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
398 lea(c_rarg0, ExternalAddress((address) str));
399 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
400
401 #ifdef _WIN64
402 // restore stack pointer
403 addq(rsp, frame::arg_reg_save_area_bytes);
404 #endif
405 pop_CPU_state();
406 mov(rsp, rbp);
407 pop(rbp);
408 }
409
410 void MacroAssembler::print_state() {
411 address rip = pc();
412 pusha(); // get regs on stack
413 push(rbp);
414 movq(rbp, rsp);
415 andq(rsp, -16); // align stack as required by push_CPU_state and call
416 push_CPU_state(); // keeps alignment at 16 bytes
417
418 lea(c_rarg0, InternalAddress(rip));
419 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
420 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
421
422 pop_CPU_state();
423 mov(rsp, rbp);
424 pop(rbp);
425 popa();
426 }
427
428 #ifndef PRODUCT
429 extern "C" void findpc(intptr_t x);
430 #endif
431
432 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
433 // In order to get locks to work, we need to fake a in_VM state
434 if (ShowMessageBoxOnError) {
435 JavaThread* thread = JavaThread::current();
436 JavaThreadState saved_state = thread->thread_state();
437 thread->set_thread_state(_thread_in_vm);
438 #ifndef PRODUCT
439 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
440 ttyLocker ttyl;
441 BytecodeCounter::print();
442 }
443 #endif
444 // To see where a verify_oop failed, get $ebx+40/X for this frame.
445 // XXX correct this offset for amd64
446 // This is the value of eip which points to where verify_oop will return.
447 if (os::message_box(msg, "Execution stopped, print registers?")) {
448 print_state64(pc, regs);
449 BREAKPOINT;
450 }
451 }
452 fatal("DEBUG MESSAGE: %s", msg);
453 }
454
455 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
456 ttyLocker ttyl;
457 DebuggingContext debugging{};
458 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
459 #ifndef PRODUCT
460 tty->cr();
461 findpc(pc);
462 tty->cr();
463 #endif
464 #define PRINT_REG(rax, value) \
465 { tty->print("%s = ", #rax); os::print_location(tty, value); }
466 PRINT_REG(rax, regs[15]);
467 PRINT_REG(rbx, regs[12]);
468 PRINT_REG(rcx, regs[14]);
469 PRINT_REG(rdx, regs[13]);
470 PRINT_REG(rdi, regs[8]);
471 PRINT_REG(rsi, regs[9]);
472 PRINT_REG(rbp, regs[10]);
473 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
474 PRINT_REG(rsp, (intptr_t)(®s[16]));
475 PRINT_REG(r8 , regs[7]);
476 PRINT_REG(r9 , regs[6]);
477 PRINT_REG(r10, regs[5]);
478 PRINT_REG(r11, regs[4]);
479 PRINT_REG(r12, regs[3]);
480 PRINT_REG(r13, regs[2]);
481 PRINT_REG(r14, regs[1]);
482 PRINT_REG(r15, regs[0]);
483 #undef PRINT_REG
484 // Print some words near the top of the stack.
485 int64_t* rsp = ®s[16];
486 int64_t* dump_sp = rsp;
487 for (int col1 = 0; col1 < 8; col1++) {
488 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
489 os::print_location(tty, *dump_sp++);
490 }
491 for (int row = 0; row < 25; row++) {
492 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
493 for (int col = 0; col < 4; col++) {
494 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
495 }
496 tty->cr();
497 }
498 // Print some instructions around pc:
499 Disassembler::decode((address)pc-64, (address)pc);
500 tty->print_cr("--------");
501 Disassembler::decode((address)pc, (address)pc+32);
502 }
503
504 // The java_calling_convention describes stack locations as ideal slots on
505 // a frame with no abi restrictions. Since we must observe abi restrictions
506 // (like the placement of the register window) the slots must be biased by
507 // the following value.
508 static int reg2offset_in(VMReg r) {
509 // Account for saved rbp and return address
510 // This should really be in_preserve_stack_slots
511 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
512 }
513
514 static int reg2offset_out(VMReg r) {
515 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
516 }
517
518 // A long move
519 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
520
521 // The calling conventions assures us that each VMregpair is either
522 // all really one physical register or adjacent stack slots.
523
524 if (src.is_single_phys_reg() ) {
525 if (dst.is_single_phys_reg()) {
526 if (dst.first() != src.first()) {
527 mov(dst.first()->as_Register(), src.first()->as_Register());
528 }
529 } else {
530 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
531 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
532 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
533 }
534 } else if (dst.is_single_phys_reg()) {
535 assert(src.is_single_reg(), "not a stack pair");
536 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
537 } else {
538 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
539 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
540 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
541 }
542 }
543
544 // A double move
545 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
546
547 // The calling conventions assures us that each VMregpair is either
548 // all really one physical register or adjacent stack slots.
549
550 if (src.is_single_phys_reg() ) {
551 if (dst.is_single_phys_reg()) {
552 // In theory these overlap but the ordering is such that this is likely a nop
553 if ( src.first() != dst.first()) {
554 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
555 }
556 } else {
557 assert(dst.is_single_reg(), "not a stack pair");
558 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
559 }
560 } else if (dst.is_single_phys_reg()) {
561 assert(src.is_single_reg(), "not a stack pair");
562 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
563 } else {
564 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
565 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
566 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
567 }
568 }
569
570
571 // A float arg may have to do float reg int reg conversion
572 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
573 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
574
575 // The calling conventions assures us that each VMregpair is either
576 // all really one physical register or adjacent stack slots.
577
578 if (src.first()->is_stack()) {
579 if (dst.first()->is_stack()) {
580 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
581 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
582 } else {
583 // stack to reg
584 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
585 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
586 }
587 } else if (dst.first()->is_stack()) {
588 // reg to stack
589 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
590 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
591 } else {
592 // reg to reg
593 // In theory these overlap but the ordering is such that this is likely a nop
594 if ( src.first() != dst.first()) {
595 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
596 }
597 }
598 }
599
600 // On 64 bit we will store integer like items to the stack as
601 // 64 bits items (x86_32/64 abi) even though java would only store
602 // 32bits for a parameter. On 32bit it will simply be 32 bits
603 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
604 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
605 if (src.first()->is_stack()) {
606 if (dst.first()->is_stack()) {
607 // stack to stack
608 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
609 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
610 } else {
611 // stack to reg
612 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
613 }
614 } else if (dst.first()->is_stack()) {
615 // reg to stack
616 // Do we really have to sign extend???
617 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
618 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
619 } else {
620 // Do we really have to sign extend???
621 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
622 if (dst.first() != src.first()) {
623 movq(dst.first()->as_Register(), src.first()->as_Register());
624 }
625 }
626 }
627
628 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
629 if (src.first()->is_stack()) {
630 if (dst.first()->is_stack()) {
631 // stack to stack
632 movq(rax, Address(rbp, reg2offset_in(src.first())));
633 movq(Address(rsp, reg2offset_out(dst.first())), rax);
634 } else {
635 // stack to reg
636 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
637 }
638 } else if (dst.first()->is_stack()) {
639 // reg to stack
640 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
641 } else {
642 if (dst.first() != src.first()) {
643 movq(dst.first()->as_Register(), src.first()->as_Register());
644 }
645 }
646 }
647
648 // An oop arg. Must pass a handle not the oop itself
649 void MacroAssembler::object_move(OopMap* map,
650 int oop_handle_offset,
651 int framesize_in_slots,
652 VMRegPair src,
653 VMRegPair dst,
654 bool is_receiver,
655 int* receiver_offset) {
656
657 // must pass a handle. First figure out the location we use as a handle
658
659 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
660
661 // See if oop is null if it is we need no handle
662
663 if (src.first()->is_stack()) {
664
665 // Oop is already on the stack as an argument
666 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
667 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
668 if (is_receiver) {
669 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
670 }
671
672 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
673 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
674 // conditionally move a null
675 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
676 } else {
677
678 // Oop is in a register we must store it to the space we reserve
679 // on the stack for oop_handles and pass a handle if oop is non-null
680
681 const Register rOop = src.first()->as_Register();
682 int oop_slot;
683 if (rOop == j_rarg0)
684 oop_slot = 0;
685 else if (rOop == j_rarg1)
686 oop_slot = 1;
687 else if (rOop == j_rarg2)
688 oop_slot = 2;
689 else if (rOop == j_rarg3)
690 oop_slot = 3;
691 else if (rOop == j_rarg4)
692 oop_slot = 4;
693 else {
694 assert(rOop == j_rarg5, "wrong register");
695 oop_slot = 5;
696 }
697
698 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
699 int offset = oop_slot*VMRegImpl::stack_slot_size;
700
701 map->set_oop(VMRegImpl::stack2reg(oop_slot));
702 // Store oop in handle area, may be null
703 movptr(Address(rsp, offset), rOop);
704 if (is_receiver) {
705 *receiver_offset = offset;
706 }
707
708 cmpptr(rOop, NULL_WORD);
709 lea(rHandle, Address(rsp, offset));
710 // conditionally move a null from the handle area where it was just stored
711 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
712 }
713
714 // If arg is on the stack then place it otherwise it is already in correct reg.
715 if (dst.first()->is_stack()) {
716 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
717 }
718 }
719
720 void MacroAssembler::addptr(Register dst, int32_t imm32) {
721 addq(dst, imm32);
722 }
723
724 void MacroAssembler::addptr(Register dst, Register src) {
725 addq(dst, src);
726 }
727
728 void MacroAssembler::addptr(Address dst, Register src) {
729 addq(dst, src);
730 }
731
732 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
733 assert(rscratch != noreg || always_reachable(src), "missing");
734
735 if (reachable(src)) {
736 Assembler::addsd(dst, as_Address(src));
737 } else {
738 lea(rscratch, src);
739 Assembler::addsd(dst, Address(rscratch, 0));
740 }
741 }
742
743 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
744 assert(rscratch != noreg || always_reachable(src), "missing");
745
746 if (reachable(src)) {
747 addss(dst, as_Address(src));
748 } else {
749 lea(rscratch, src);
750 addss(dst, Address(rscratch, 0));
751 }
752 }
753
754 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
755 assert(rscratch != noreg || always_reachable(src), "missing");
756
757 if (reachable(src)) {
758 Assembler::addpd(dst, as_Address(src));
759 } else {
760 lea(rscratch, src);
761 Assembler::addpd(dst, Address(rscratch, 0));
762 }
763 }
764
765 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
766 // Stub code is generated once and never copied.
767 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
768 void MacroAssembler::align64() {
769 align(64, (uint)(uintptr_t)pc());
770 }
771
772 void MacroAssembler::align32() {
773 align(32, (uint)(uintptr_t)pc());
774 }
775
776 void MacroAssembler::align(uint modulus) {
777 // 8273459: Ensure alignment is possible with current segment alignment
778 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
779 align(modulus, offset());
780 }
781
782 void MacroAssembler::align(uint modulus, uint target) {
783 if (target % modulus != 0) {
784 nop(modulus - (target % modulus));
785 }
786 }
787
788 void MacroAssembler::push_f(XMMRegister r) {
789 subptr(rsp, wordSize);
790 movflt(Address(rsp, 0), r);
791 }
792
793 void MacroAssembler::pop_f(XMMRegister r) {
794 movflt(r, Address(rsp, 0));
795 addptr(rsp, wordSize);
796 }
797
798 void MacroAssembler::push_d(XMMRegister r) {
799 subptr(rsp, 2 * wordSize);
800 movdbl(Address(rsp, 0), r);
801 }
802
803 void MacroAssembler::pop_d(XMMRegister r) {
804 movdbl(r, Address(rsp, 0));
805 addptr(rsp, 2 * Interpreter::stackElementSize);
806 }
807
808 void MacroAssembler::push_ppx(Register src) {
809 if (VM_Version::supports_apx_f()) {
810 pushp(src);
811 } else {
812 Assembler::push(src);
813 }
814 }
815
816 void MacroAssembler::pop_ppx(Register dst) {
817 if (VM_Version::supports_apx_f()) {
818 popp(dst);
819 } else {
820 Assembler::pop(dst);
821 }
822 }
823
824 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
825 // Used in sign-masking with aligned address.
826 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
827 assert(rscratch != noreg || always_reachable(src), "missing");
828
829 if (UseAVX > 2 &&
830 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
831 (dst->encoding() >= 16)) {
832 vpand(dst, dst, src, AVX_512bit, rscratch);
833 } else if (reachable(src)) {
834 Assembler::andpd(dst, as_Address(src));
835 } else {
836 lea(rscratch, src);
837 Assembler::andpd(dst, Address(rscratch, 0));
838 }
839 }
840
841 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
842 // Used in sign-masking with aligned address.
843 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
844 assert(rscratch != noreg || always_reachable(src), "missing");
845
846 if (reachable(src)) {
847 Assembler::andps(dst, as_Address(src));
848 } else {
849 lea(rscratch, src);
850 Assembler::andps(dst, Address(rscratch, 0));
851 }
852 }
853
854 void MacroAssembler::andptr(Register dst, int32_t imm32) {
855 andq(dst, imm32);
856 }
857
858 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
859 assert(rscratch != noreg || always_reachable(src), "missing");
860
861 if (reachable(src)) {
862 andq(dst, as_Address(src));
863 } else {
864 lea(rscratch, src);
865 andq(dst, Address(rscratch, 0));
866 }
867 }
868
869 void MacroAssembler::atomic_incl(Address counter_addr) {
870 lock();
871 incrementl(counter_addr);
872 }
873
874 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
875 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
876
877 if (reachable(counter_addr)) {
878 atomic_incl(as_Address(counter_addr));
879 } else {
880 lea(rscratch, counter_addr);
881 atomic_incl(Address(rscratch, 0));
882 }
883 }
884
885 void MacroAssembler::atomic_incq(Address counter_addr) {
886 lock();
887 incrementq(counter_addr);
888 }
889
890 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
891 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
892
893 if (reachable(counter_addr)) {
894 atomic_incq(as_Address(counter_addr));
895 } else {
896 lea(rscratch, counter_addr);
897 atomic_incq(Address(rscratch, 0));
898 }
899 }
900
901 // Writes to stack successive pages until offset reached to check for
902 // stack overflow + shadow pages. This clobbers tmp.
903 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
904 movptr(tmp, rsp);
905 // Bang stack for total size given plus shadow page size.
906 // Bang one page at a time because large size can bang beyond yellow and
907 // red zones.
908 Label loop;
909 bind(loop);
910 movl(Address(tmp, (-(int)os::vm_page_size())), size );
911 subptr(tmp, (int)os::vm_page_size());
912 subl(size, (int)os::vm_page_size());
913 jcc(Assembler::greater, loop);
914
915 // Bang down shadow pages too.
916 // At this point, (tmp-0) is the last address touched, so don't
917 // touch it again. (It was touched as (tmp-pagesize) but then tmp
918 // was post-decremented.) Skip this address by starting at i=1, and
919 // touch a few more pages below. N.B. It is important to touch all
920 // the way down including all pages in the shadow zone.
921 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
922 // this could be any sized move but this is can be a debugging crumb
923 // so the bigger the better.
924 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
925 }
926 }
927
928 void MacroAssembler::reserved_stack_check() {
929 // testing if reserved zone needs to be enabled
930 Label no_reserved_zone_enabling;
931
932 cmpptr(rsp, Address(r15_thread, JavaThread::reserved_stack_activation_offset()));
933 jcc(Assembler::below, no_reserved_zone_enabling);
934
935 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), r15_thread);
936 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
937 should_not_reach_here();
938
939 bind(no_reserved_zone_enabling);
940 }
941
942 void MacroAssembler::c2bool(Register x) {
943 // implements x == 0 ? 0 : 1
944 // note: must only look at least-significant byte of x
945 // since C-style booleans are stored in one byte
946 // only! (was bug)
947 andl(x, 0xFF);
948 setb(Assembler::notZero, x);
949 }
950
951 // Wouldn't need if AddressLiteral version had new name
952 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
953 Assembler::call(L, rtype);
954 }
955
956 void MacroAssembler::call(Register entry) {
957 Assembler::call(entry);
958 }
959
960 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
961 assert(rscratch != noreg || always_reachable(entry), "missing");
962
963 if (reachable(entry)) {
964 Assembler::call_literal(entry.target(), entry.rspec());
965 } else {
966 lea(rscratch, entry);
967 Assembler::call(rscratch);
968 }
969 }
970
971 void MacroAssembler::ic_call(address entry, jint method_index) {
972 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
973 // Needs full 64-bit immediate for later patching.
974 Assembler::mov64(rax, (int64_t)Universe::non_oop_word());
975 call(AddressLiteral(entry, rh));
976 }
977
978 int MacroAssembler::ic_check_size() {
979 return UseCompactObjectHeaders ? 17 : 14;
980 }
981
982 int MacroAssembler::ic_check(int end_alignment) {
983 Register receiver = j_rarg0;
984 Register data = rax;
985 Register temp = rscratch1;
986
987 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
988 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
989 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
990 // before the inline cache check here, and not after
991 align(end_alignment, offset() + ic_check_size());
992
993 int uep_offset = offset();
994
995 if (UseCompactObjectHeaders) {
996 load_narrow_klass_compact(temp, receiver);
997 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
998 } else {
999 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1000 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1001 }
1002
1003 // if inline cache check fails, then jump to runtime routine
1004 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1005 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1006
1007 return uep_offset;
1008 }
1009
1010 void MacroAssembler::emit_static_call_stub() {
1011 // Static stub relocation also tags the Method* in the code-stream.
1012 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1013 // This is recognized as unresolved by relocs/nativeinst/ic code.
1014 jump(RuntimeAddress(pc()));
1015 }
1016
1017 // Implementation of call_VM versions
1018
1019 void MacroAssembler::call_VM(Register oop_result,
1020 address entry_point,
1021 bool check_exceptions) {
1022 Label C, E;
1023 call(C, relocInfo::none);
1024 jmp(E);
1025
1026 bind(C);
1027 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1028 ret(0);
1029
1030 bind(E);
1031 }
1032
1033 void MacroAssembler::call_VM(Register oop_result,
1034 address entry_point,
1035 Register arg_1,
1036 bool check_exceptions) {
1037 Label C, E;
1038 call(C, relocInfo::none);
1039 jmp(E);
1040
1041 bind(C);
1042 pass_arg1(this, arg_1);
1043 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1044 ret(0);
1045
1046 bind(E);
1047 }
1048
1049 void MacroAssembler::call_VM(Register oop_result,
1050 address entry_point,
1051 Register arg_1,
1052 Register arg_2,
1053 bool check_exceptions) {
1054 Label C, E;
1055 call(C, relocInfo::none);
1056 jmp(E);
1057
1058 bind(C);
1059
1060 assert_different_registers(arg_1, c_rarg2);
1061
1062 pass_arg2(this, arg_2);
1063 pass_arg1(this, arg_1);
1064 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1065 ret(0);
1066
1067 bind(E);
1068 }
1069
1070 void MacroAssembler::call_VM(Register oop_result,
1071 address entry_point,
1072 Register arg_1,
1073 Register arg_2,
1074 Register arg_3,
1075 bool check_exceptions) {
1076 Label C, E;
1077 call(C, relocInfo::none);
1078 jmp(E);
1079
1080 bind(C);
1081
1082 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1083 assert_different_registers(arg_2, c_rarg3);
1084 pass_arg3(this, arg_3);
1085 pass_arg2(this, arg_2);
1086 pass_arg1(this, arg_1);
1087 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1088 ret(0);
1089
1090 bind(E);
1091 }
1092
1093 void MacroAssembler::call_VM(Register oop_result,
1094 Register last_java_sp,
1095 address entry_point,
1096 int number_of_arguments,
1097 bool check_exceptions) {
1098 call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1099 }
1100
1101 void MacroAssembler::call_VM(Register oop_result,
1102 Register last_java_sp,
1103 address entry_point,
1104 Register arg_1,
1105 bool check_exceptions) {
1106 pass_arg1(this, arg_1);
1107 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1108 }
1109
1110 void MacroAssembler::call_VM(Register oop_result,
1111 Register last_java_sp,
1112 address entry_point,
1113 Register arg_1,
1114 Register arg_2,
1115 bool check_exceptions) {
1116
1117 assert_different_registers(arg_1, c_rarg2);
1118 pass_arg2(this, arg_2);
1119 pass_arg1(this, arg_1);
1120 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1121 }
1122
1123 void MacroAssembler::call_VM(Register oop_result,
1124 Register last_java_sp,
1125 address entry_point,
1126 Register arg_1,
1127 Register arg_2,
1128 Register arg_3,
1129 bool check_exceptions) {
1130 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1131 assert_different_registers(arg_2, c_rarg3);
1132 pass_arg3(this, arg_3);
1133 pass_arg2(this, arg_2);
1134 pass_arg1(this, arg_1);
1135 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1136 }
1137
1138 void MacroAssembler::super_call_VM(Register oop_result,
1139 Register last_java_sp,
1140 address entry_point,
1141 int number_of_arguments,
1142 bool check_exceptions) {
1143 MacroAssembler::call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1144 }
1145
1146 void MacroAssembler::super_call_VM(Register oop_result,
1147 Register last_java_sp,
1148 address entry_point,
1149 Register arg_1,
1150 bool check_exceptions) {
1151 pass_arg1(this, arg_1);
1152 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1153 }
1154
1155 void MacroAssembler::super_call_VM(Register oop_result,
1156 Register last_java_sp,
1157 address entry_point,
1158 Register arg_1,
1159 Register arg_2,
1160 bool check_exceptions) {
1161
1162 assert_different_registers(arg_1, c_rarg2);
1163 pass_arg2(this, arg_2);
1164 pass_arg1(this, arg_1);
1165 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1166 }
1167
1168 void MacroAssembler::super_call_VM(Register oop_result,
1169 Register last_java_sp,
1170 address entry_point,
1171 Register arg_1,
1172 Register arg_2,
1173 Register arg_3,
1174 bool check_exceptions) {
1175 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1176 assert_different_registers(arg_2, c_rarg3);
1177 pass_arg3(this, arg_3);
1178 pass_arg2(this, arg_2);
1179 pass_arg1(this, arg_1);
1180 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1181 }
1182
1183 void MacroAssembler::call_VM_base(Register oop_result,
1184 Register last_java_sp,
1185 address entry_point,
1186 int number_of_arguments,
1187 bool check_exceptions) {
1188 Register java_thread = r15_thread;
1189
1190 // determine last_java_sp register
1191 if (!last_java_sp->is_valid()) {
1192 last_java_sp = rsp;
1193 }
1194 // debugging support
1195 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1196 #ifdef ASSERT
1197 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1198 // r12 is the heapbase.
1199 if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
1200 #endif // ASSERT
1201
1202 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1203 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1204
1205 // push java thread (becomes first argument of C function)
1206
1207 mov(c_rarg0, r15_thread);
1208
1209 // set last Java frame before call
1210 assert(last_java_sp != rbp, "can't use ebp/rbp");
1211
1212 // Only interpreter should have to set fp
1213 set_last_Java_frame(last_java_sp, rbp, nullptr, rscratch1);
1214
1215 // do the call, remove parameters
1216 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1217
1218 #ifdef ASSERT
1219 // Check that thread register is not clobbered.
1220 guarantee(java_thread != rax, "change this code");
1221 push(rax);
1222 { Label L;
1223 get_thread_slow(rax);
1224 cmpptr(java_thread, rax);
1225 jcc(Assembler::equal, L);
1226 STOP("MacroAssembler::call_VM_base: java_thread not callee saved?");
1227 bind(L);
1228 }
1229 pop(rax);
1230 #endif
1231
1232 // reset last Java frame
1233 // Only interpreter should have to clear fp
1234 reset_last_Java_frame(true);
1235
1236 // C++ interp handles this in the interpreter
1237 check_and_handle_popframe();
1238 check_and_handle_earlyret();
1239
1240 if (check_exceptions) {
1241 // check for pending exceptions (java_thread is set upon return)
1242 cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
1243 // This used to conditionally jump to forward_exception however it is
1244 // possible if we relocate that the branch will not reach. So we must jump
1245 // around so we can always reach
1246
1247 Label ok;
1248 jcc(Assembler::equal, ok);
1249 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1250 bind(ok);
1251 }
1252
1253 // get oop result if there is one and reset the value in the thread
1254 if (oop_result->is_valid()) {
1255 get_vm_result_oop(oop_result);
1256 }
1257 }
1258
1259 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1260 // Calculate the value for last_Java_sp somewhat subtle.
1261 // call_VM does an intermediate call which places a return address on
1262 // the stack just under the stack pointer as the user finished with it.
1263 // This allows use to retrieve last_Java_pc from last_Java_sp[-1].
1264
1265 // We've pushed one address, correct last_Java_sp
1266 lea(rax, Address(rsp, wordSize));
1267
1268 call_VM_base(oop_result, rax, entry_point, number_of_arguments, check_exceptions);
1269 }
1270
1271 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1272 void MacroAssembler::call_VM_leaf0(address entry_point) {
1273 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1274 }
1275
1276 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1277 call_VM_leaf_base(entry_point, number_of_arguments);
1278 }
1279
1280 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1281 pass_arg0(this, arg_0);
1282 call_VM_leaf(entry_point, 1);
1283 }
1284
1285 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1286
1287 assert_different_registers(arg_0, c_rarg1);
1288 pass_arg1(this, arg_1);
1289 pass_arg0(this, arg_0);
1290 call_VM_leaf(entry_point, 2);
1291 }
1292
1293 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1294 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1295 assert_different_registers(arg_1, c_rarg2);
1296 pass_arg2(this, arg_2);
1297 pass_arg1(this, arg_1);
1298 pass_arg0(this, arg_0);
1299 call_VM_leaf(entry_point, 3);
1300 }
1301
1302 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1303 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1304 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1305 assert_different_registers(arg_2, c_rarg3);
1306 pass_arg3(this, arg_3);
1307 pass_arg2(this, arg_2);
1308 pass_arg1(this, arg_1);
1309 pass_arg0(this, arg_0);
1310 call_VM_leaf(entry_point, 3);
1311 }
1312
1313 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1314 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1315 }
1316
1317 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1318 pass_arg0(this, arg_0);
1319 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1320 }
1321
1322 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1323 assert_different_registers(arg_0, c_rarg1);
1324 pass_arg1(this, arg_1);
1325 pass_arg0(this, arg_0);
1326 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1327 }
1328
1329 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1330 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1331 assert_different_registers(arg_1, c_rarg2);
1332 pass_arg2(this, arg_2);
1333 pass_arg1(this, arg_1);
1334 pass_arg0(this, arg_0);
1335 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1336 }
1337
1338 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1339 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1340 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1341 assert_different_registers(arg_2, c_rarg3);
1342 pass_arg3(this, arg_3);
1343 pass_arg2(this, arg_2);
1344 pass_arg1(this, arg_1);
1345 pass_arg0(this, arg_0);
1346 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1347 }
1348
1349 void MacroAssembler::get_vm_result_oop(Register oop_result) {
1350 movptr(oop_result, Address(r15_thread, JavaThread::vm_result_oop_offset()));
1351 movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
1352 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1353 }
1354
1355 void MacroAssembler::get_vm_result_metadata(Register metadata_result) {
1356 movptr(metadata_result, Address(r15_thread, JavaThread::vm_result_metadata_offset()));
1357 movptr(Address(r15_thread, JavaThread::vm_result_metadata_offset()), NULL_WORD);
1358 }
1359
1360 void MacroAssembler::check_and_handle_earlyret() {
1361 }
1362
1363 void MacroAssembler::check_and_handle_popframe() {
1364 }
1365
1366 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1367 assert(rscratch != noreg || always_reachable(src1), "missing");
1368
1369 if (reachable(src1)) {
1370 cmpl(as_Address(src1), imm);
1371 } else {
1372 lea(rscratch, src1);
1373 cmpl(Address(rscratch, 0), imm);
1374 }
1375 }
1376
1377 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1378 assert(!src2.is_lval(), "use cmpptr");
1379 assert(rscratch != noreg || always_reachable(src2), "missing");
1380
1381 if (reachable(src2)) {
1382 cmpl(src1, as_Address(src2));
1383 } else {
1384 lea(rscratch, src2);
1385 cmpl(src1, Address(rscratch, 0));
1386 }
1387 }
1388
1389 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1390 Assembler::cmpl(src1, imm);
1391 }
1392
1393 void MacroAssembler::cmp32(Register src1, Address src2) {
1394 Assembler::cmpl(src1, src2);
1395 }
1396
1397 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1398 ucomisd(opr1, opr2);
1399
1400 Label L;
1401 if (unordered_is_less) {
1402 movl(dst, -1);
1403 jcc(Assembler::parity, L);
1404 jcc(Assembler::below , L);
1405 movl(dst, 0);
1406 jcc(Assembler::equal , L);
1407 increment(dst);
1408 } else { // unordered is greater
1409 movl(dst, 1);
1410 jcc(Assembler::parity, L);
1411 jcc(Assembler::above , L);
1412 movl(dst, 0);
1413 jcc(Assembler::equal , L);
1414 decrementl(dst);
1415 }
1416 bind(L);
1417 }
1418
1419 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1420 ucomiss(opr1, opr2);
1421
1422 Label L;
1423 if (unordered_is_less) {
1424 movl(dst, -1);
1425 jcc(Assembler::parity, L);
1426 jcc(Assembler::below , L);
1427 movl(dst, 0);
1428 jcc(Assembler::equal , L);
1429 increment(dst);
1430 } else { // unordered is greater
1431 movl(dst, 1);
1432 jcc(Assembler::parity, L);
1433 jcc(Assembler::above , L);
1434 movl(dst, 0);
1435 jcc(Assembler::equal , L);
1436 decrementl(dst);
1437 }
1438 bind(L);
1439 }
1440
1441
1442 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1443 assert(rscratch != noreg || always_reachable(src1), "missing");
1444
1445 if (reachable(src1)) {
1446 cmpb(as_Address(src1), imm);
1447 } else {
1448 lea(rscratch, src1);
1449 cmpb(Address(rscratch, 0), imm);
1450 }
1451 }
1452
1453 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1454 assert(rscratch != noreg || always_reachable(src2), "missing");
1455
1456 if (src2.is_lval()) {
1457 movptr(rscratch, src2);
1458 Assembler::cmpq(src1, rscratch);
1459 } else if (reachable(src2)) {
1460 cmpq(src1, as_Address(src2));
1461 } else {
1462 lea(rscratch, src2);
1463 Assembler::cmpq(src1, Address(rscratch, 0));
1464 }
1465 }
1466
1467 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1468 assert(src2.is_lval(), "not a mem-mem compare");
1469 // moves src2's literal address
1470 movptr(rscratch, src2);
1471 Assembler::cmpq(src1, rscratch);
1472 }
1473
1474 void MacroAssembler::cmpoop(Register src1, Register src2) {
1475 cmpptr(src1, src2);
1476 }
1477
1478 void MacroAssembler::cmpoop(Register src1, Address src2) {
1479 cmpptr(src1, src2);
1480 }
1481
1482 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1483 movoop(rscratch, src2);
1484 cmpptr(src1, rscratch);
1485 }
1486
1487 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1488 assert(rscratch != noreg || always_reachable(adr), "missing");
1489
1490 if (reachable(adr)) {
1491 lock();
1492 cmpxchgptr(reg, as_Address(adr));
1493 } else {
1494 lea(rscratch, adr);
1495 lock();
1496 cmpxchgptr(reg, Address(rscratch, 0));
1497 }
1498 }
1499
1500 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1501 cmpxchgq(reg, adr);
1502 }
1503
1504 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1505 assert(rscratch != noreg || always_reachable(src), "missing");
1506
1507 if (reachable(src)) {
1508 Assembler::comisd(dst, as_Address(src));
1509 } else {
1510 lea(rscratch, src);
1511 Assembler::comisd(dst, Address(rscratch, 0));
1512 }
1513 }
1514
1515 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1516 assert(rscratch != noreg || always_reachable(src), "missing");
1517
1518 if (reachable(src)) {
1519 Assembler::comiss(dst, as_Address(src));
1520 } else {
1521 lea(rscratch, src);
1522 Assembler::comiss(dst, Address(rscratch, 0));
1523 }
1524 }
1525
1526
1527 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1528 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1529
1530 Condition negated_cond = negate_condition(cond);
1531 Label L;
1532 jcc(negated_cond, L);
1533 pushf(); // Preserve flags
1534 atomic_incl(counter_addr, rscratch);
1535 popf();
1536 bind(L);
1537 }
1538
1539 int MacroAssembler::corrected_idivl(Register reg) {
1540 // Full implementation of Java idiv and irem; checks for
1541 // special case as described in JVM spec., p.243 & p.271.
1542 // The function returns the (pc) offset of the idivl
1543 // instruction - may be needed for implicit exceptions.
1544 //
1545 // normal case special case
1546 //
1547 // input : rax,: dividend min_int
1548 // reg: divisor (may not be rax,/rdx) -1
1549 //
1550 // output: rax,: quotient (= rax, idiv reg) min_int
1551 // rdx: remainder (= rax, irem reg) 0
1552 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1553 const int min_int = 0x80000000;
1554 Label normal_case, special_case;
1555
1556 // check for special case
1557 cmpl(rax, min_int);
1558 jcc(Assembler::notEqual, normal_case);
1559 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1560 cmpl(reg, -1);
1561 jcc(Assembler::equal, special_case);
1562
1563 // handle normal case
1564 bind(normal_case);
1565 cdql();
1566 int idivl_offset = offset();
1567 idivl(reg);
1568
1569 // normal and special case exit
1570 bind(special_case);
1571
1572 return idivl_offset;
1573 }
1574
1575
1576
1577 void MacroAssembler::decrementl(Register reg, int value) {
1578 if (value == min_jint) {subl(reg, value) ; return; }
1579 if (value < 0) { incrementl(reg, -value); return; }
1580 if (value == 0) { ; return; }
1581 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1582 /* else */ { subl(reg, value) ; return; }
1583 }
1584
1585 void MacroAssembler::decrementl(Address dst, int value) {
1586 if (value == min_jint) {subl(dst, value) ; return; }
1587 if (value < 0) { incrementl(dst, -value); return; }
1588 if (value == 0) { ; return; }
1589 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1590 /* else */ { subl(dst, value) ; return; }
1591 }
1592
1593 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1594 assert(shift_value > 0, "illegal shift value");
1595 Label _is_positive;
1596 testl (reg, reg);
1597 jcc (Assembler::positive, _is_positive);
1598 int offset = (1 << shift_value) - 1 ;
1599
1600 if (offset == 1) {
1601 incrementl(reg);
1602 } else {
1603 addl(reg, offset);
1604 }
1605
1606 bind (_is_positive);
1607 sarl(reg, shift_value);
1608 }
1609
1610 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1611 assert(rscratch != noreg || always_reachable(src), "missing");
1612
1613 if (reachable(src)) {
1614 Assembler::divsd(dst, as_Address(src));
1615 } else {
1616 lea(rscratch, src);
1617 Assembler::divsd(dst, Address(rscratch, 0));
1618 }
1619 }
1620
1621 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1622 assert(rscratch != noreg || always_reachable(src), "missing");
1623
1624 if (reachable(src)) {
1625 Assembler::divss(dst, as_Address(src));
1626 } else {
1627 lea(rscratch, src);
1628 Assembler::divss(dst, Address(rscratch, 0));
1629 }
1630 }
1631
1632 void MacroAssembler::enter() {
1633 push(rbp);
1634 mov(rbp, rsp);
1635 }
1636
1637 void MacroAssembler::post_call_nop() {
1638 if (!Continuations::enabled()) {
1639 return;
1640 }
1641 InstructionMark im(this);
1642 relocate(post_call_nop_Relocation::spec());
1643 InlineSkippedInstructionsCounter skipCounter(this);
1644 emit_int8((uint8_t)0x0f);
1645 emit_int8((uint8_t)0x1f);
1646 emit_int8((uint8_t)0x84);
1647 emit_int8((uint8_t)0x00);
1648 emit_int32(0x00);
1649 }
1650
1651 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1652 assert(rscratch != noreg || always_reachable(src), "missing");
1653 if (reachable(src)) {
1654 Assembler::mulpd(dst, as_Address(src));
1655 } else {
1656 lea(rscratch, src);
1657 Assembler::mulpd(dst, Address(rscratch, 0));
1658 }
1659 }
1660
1661 // dst = c = a * b + c
1662 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1663 Assembler::vfmadd231sd(c, a, b);
1664 if (dst != c) {
1665 movdbl(dst, c);
1666 }
1667 }
1668
1669 // dst = c = a * b + c
1670 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1671 Assembler::vfmadd231ss(c, a, b);
1672 if (dst != c) {
1673 movflt(dst, c);
1674 }
1675 }
1676
1677 // dst = c = a * b + c
1678 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1679 Assembler::vfmadd231pd(c, a, b, vector_len);
1680 if (dst != c) {
1681 vmovdqu(dst, c);
1682 }
1683 }
1684
1685 // dst = c = a * b + c
1686 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1687 Assembler::vfmadd231ps(c, a, b, vector_len);
1688 if (dst != c) {
1689 vmovdqu(dst, c);
1690 }
1691 }
1692
1693 // dst = c = a * b + c
1694 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1695 Assembler::vfmadd231pd(c, a, b, vector_len);
1696 if (dst != c) {
1697 vmovdqu(dst, c);
1698 }
1699 }
1700
1701 // dst = c = a * b + c
1702 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1703 Assembler::vfmadd231ps(c, a, b, vector_len);
1704 if (dst != c) {
1705 vmovdqu(dst, c);
1706 }
1707 }
1708
1709 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
1710 assert(rscratch != noreg || always_reachable(dst), "missing");
1711
1712 if (reachable(dst)) {
1713 incrementl(as_Address(dst));
1714 } else {
1715 lea(rscratch, dst);
1716 incrementl(Address(rscratch, 0));
1717 }
1718 }
1719
1720 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
1721 incrementl(as_Address(dst, rscratch));
1722 }
1723
1724 void MacroAssembler::incrementl(Register reg, int value) {
1725 if (value == min_jint) {addl(reg, value) ; return; }
1726 if (value < 0) { decrementl(reg, -value); return; }
1727 if (value == 0) { ; return; }
1728 if (value == 1 && UseIncDec) { incl(reg) ; return; }
1729 /* else */ { addl(reg, value) ; return; }
1730 }
1731
1732 void MacroAssembler::incrementl(Address dst, int value) {
1733 if (value == min_jint) {addl(dst, value) ; return; }
1734 if (value < 0) { decrementl(dst, -value); return; }
1735 if (value == 0) { ; return; }
1736 if (value == 1 && UseIncDec) { incl(dst) ; return; }
1737 /* else */ { addl(dst, value) ; return; }
1738 }
1739
1740 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
1741 assert(rscratch != noreg || always_reachable(dst), "missing");
1742 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
1743 if (reachable(dst)) {
1744 jmp_literal(dst.target(), dst.rspec());
1745 } else {
1746 lea(rscratch, dst);
1747 jmp(rscratch);
1748 }
1749 }
1750
1751 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
1752 assert(rscratch != noreg || always_reachable(dst), "missing");
1753 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
1754 if (reachable(dst)) {
1755 InstructionMark im(this);
1756 relocate(dst.reloc());
1757 const int short_size = 2;
1758 const int long_size = 6;
1759 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
1760 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
1761 // 0111 tttn #8-bit disp
1762 emit_int8(0x70 | cc);
1763 emit_int8((offs - short_size) & 0xFF);
1764 } else {
1765 // 0000 1111 1000 tttn #32-bit disp
1766 emit_int8(0x0F);
1767 emit_int8((unsigned char)(0x80 | cc));
1768 emit_int32(offs - long_size);
1769 }
1770 } else {
1771 #ifdef ASSERT
1772 warning("reversing conditional branch");
1773 #endif /* ASSERT */
1774 Label skip;
1775 jccb(reverse[cc], skip);
1776 lea(rscratch, dst);
1777 Assembler::jmp(rscratch);
1778 bind(skip);
1779 }
1780 }
1781
1782 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
1783 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
1784 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
1785
1786 stmxcsr(mxcsr_save);
1787 movl(tmp, mxcsr_save);
1788 if (EnableX86ECoreOpts) {
1789 // The mxcsr_std has status bits set for performance on ECore
1790 orl(tmp, 0x003f);
1791 } else {
1792 // Mask out status bits (only check control and mask bits)
1793 andl(tmp, 0xFFC0);
1794 }
1795 cmp32(tmp, mxcsr_std, rscratch);
1796 }
1797
1798 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
1799 assert(rscratch != noreg || always_reachable(src), "missing");
1800
1801 if (reachable(src)) {
1802 Assembler::ldmxcsr(as_Address(src));
1803 } else {
1804 lea(rscratch, src);
1805 Assembler::ldmxcsr(Address(rscratch, 0));
1806 }
1807 }
1808
1809 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1810 int off = offset();
1811 movsbl(dst, src); // movsxb
1812 return off;
1813 }
1814
1815 // Note: load_signed_short used to be called load_signed_word.
1816 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
1817 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
1818 // The term "word" in HotSpot means a 32- or 64-bit machine word.
1819 int MacroAssembler::load_signed_short(Register dst, Address src) {
1820 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
1821 // version but this is what 64bit has always done. This seems to imply
1822 // that users are only using 32bits worth.
1823 int off = offset();
1824 movswl(dst, src); // movsxw
1825 return off;
1826 }
1827
1828 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1829 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1830 // and "3.9 Partial Register Penalties", p. 22).
1831 int off = offset();
1832 movzbl(dst, src); // movzxb
1833 return off;
1834 }
1835
1836 // Note: load_unsigned_short used to be called load_unsigned_word.
1837 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1838 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1839 // and "3.9 Partial Register Penalties", p. 22).
1840 int off = offset();
1841 movzwl(dst, src); // movzxw
1842 return off;
1843 }
1844
1845 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1846 switch (size_in_bytes) {
1847 case 8: movq(dst, src); break;
1848 case 4: movl(dst, src); break;
1849 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1850 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1851 default: ShouldNotReachHere();
1852 }
1853 }
1854
1855 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1856 switch (size_in_bytes) {
1857 case 8: movq(dst, src); break;
1858 case 4: movl(dst, src); break;
1859 case 2: movw(dst, src); break;
1860 case 1: movb(dst, src); break;
1861 default: ShouldNotReachHere();
1862 }
1863 }
1864
1865 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
1866 assert(rscratch != noreg || always_reachable(dst), "missing");
1867
1868 if (reachable(dst)) {
1869 movl(as_Address(dst), src);
1870 } else {
1871 lea(rscratch, dst);
1872 movl(Address(rscratch, 0), src);
1873 }
1874 }
1875
1876 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
1877 if (reachable(src)) {
1878 movl(dst, as_Address(src));
1879 } else {
1880 lea(dst, src);
1881 movl(dst, Address(dst, 0));
1882 }
1883 }
1884
1885 // C++ bool manipulation
1886
1887 void MacroAssembler::movbool(Register dst, Address src) {
1888 if(sizeof(bool) == 1)
1889 movb(dst, src);
1890 else if(sizeof(bool) == 2)
1891 movw(dst, src);
1892 else if(sizeof(bool) == 4)
1893 movl(dst, src);
1894 else
1895 // unsupported
1896 ShouldNotReachHere();
1897 }
1898
1899 void MacroAssembler::movbool(Address dst, bool boolconst) {
1900 if(sizeof(bool) == 1)
1901 movb(dst, (int) boolconst);
1902 else if(sizeof(bool) == 2)
1903 movw(dst, (int) boolconst);
1904 else if(sizeof(bool) == 4)
1905 movl(dst, (int) boolconst);
1906 else
1907 // unsupported
1908 ShouldNotReachHere();
1909 }
1910
1911 void MacroAssembler::movbool(Address dst, Register src) {
1912 if(sizeof(bool) == 1)
1913 movb(dst, src);
1914 else if(sizeof(bool) == 2)
1915 movw(dst, src);
1916 else if(sizeof(bool) == 4)
1917 movl(dst, src);
1918 else
1919 // unsupported
1920 ShouldNotReachHere();
1921 }
1922
1923 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1924 assert(rscratch != noreg || always_reachable(src), "missing");
1925
1926 if (reachable(src)) {
1927 movdl(dst, as_Address(src));
1928 } else {
1929 lea(rscratch, src);
1930 movdl(dst, Address(rscratch, 0));
1931 }
1932 }
1933
1934 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
1935 assert(rscratch != noreg || always_reachable(src), "missing");
1936
1937 if (reachable(src)) {
1938 movq(dst, as_Address(src));
1939 } else {
1940 lea(rscratch, src);
1941 movq(dst, Address(rscratch, 0));
1942 }
1943 }
1944
1945 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1946 assert(rscratch != noreg || always_reachable(src), "missing");
1947
1948 if (reachable(src)) {
1949 if (UseXmmLoadAndClearUpper) {
1950 movsd (dst, as_Address(src));
1951 } else {
1952 movlpd(dst, as_Address(src));
1953 }
1954 } else {
1955 lea(rscratch, src);
1956 if (UseXmmLoadAndClearUpper) {
1957 movsd (dst, Address(rscratch, 0));
1958 } else {
1959 movlpd(dst, Address(rscratch, 0));
1960 }
1961 }
1962 }
1963
1964 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
1965 assert(rscratch != noreg || always_reachable(src), "missing");
1966
1967 if (reachable(src)) {
1968 movss(dst, as_Address(src));
1969 } else {
1970 lea(rscratch, src);
1971 movss(dst, Address(rscratch, 0));
1972 }
1973 }
1974
1975 void MacroAssembler::movhlf(XMMRegister dst, XMMRegister src, Register rscratch) {
1976 if (VM_Version::supports_avx10_2()) {
1977 evmovw(dst, src);
1978 } else {
1979 assert(rscratch != noreg, "missing");
1980 evmovw(rscratch, src);
1981 evmovw(dst, rscratch);
1982 }
1983 }
1984
1985 void MacroAssembler::mov64(Register dst, int64_t imm64) {
1986 if (is_uimm32(imm64)) {
1987 movl(dst, checked_cast<uint32_t>(imm64));
1988 } else if (is_simm32(imm64)) {
1989 movq(dst, checked_cast<int32_t>(imm64));
1990 } else {
1991 Assembler::mov64(dst, imm64);
1992 }
1993 }
1994
1995 void MacroAssembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) {
1996 Assembler::mov64(dst, imm64, rtype, format);
1997 }
1998
1999 void MacroAssembler::movptr(Register dst, Register src) {
2000 movq(dst, src);
2001 }
2002
2003 void MacroAssembler::movptr(Register dst, Address src) {
2004 movq(dst, src);
2005 }
2006
2007 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2008 void MacroAssembler::movptr(Register dst, intptr_t src) {
2009 mov64(dst, src);
2010 }
2011
2012 void MacroAssembler::movptr(Address dst, Register src) {
2013 movq(dst, src);
2014 }
2015
2016 void MacroAssembler::movptr(Address dst, int32_t src) {
2017 movslq(dst, src);
2018 }
2019
2020 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2021 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2022 Assembler::movdqu(dst, src);
2023 }
2024
2025 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2026 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2027 Assembler::movdqu(dst, src);
2028 }
2029
2030 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2031 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2032 Assembler::movdqu(dst, src);
2033 }
2034
2035 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2036 assert(rscratch != noreg || always_reachable(src), "missing");
2037
2038 if (reachable(src)) {
2039 movdqu(dst, as_Address(src));
2040 } else {
2041 lea(rscratch, src);
2042 movdqu(dst, Address(rscratch, 0));
2043 }
2044 }
2045
2046 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2047 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2048 Assembler::vmovdqu(dst, src);
2049 }
2050
2051 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2052 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2053 Assembler::vmovdqu(dst, src);
2054 }
2055
2056 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2057 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2058 Assembler::vmovdqu(dst, src);
2059 }
2060
2061 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2062 assert(rscratch != noreg || always_reachable(src), "missing");
2063
2064 if (reachable(src)) {
2065 vmovdqu(dst, as_Address(src));
2066 }
2067 else {
2068 lea(rscratch, src);
2069 vmovdqu(dst, Address(rscratch, 0));
2070 }
2071 }
2072
2073 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2074 assert(rscratch != noreg || always_reachable(src), "missing");
2075
2076 if (vector_len == AVX_512bit) {
2077 evmovdquq(dst, src, AVX_512bit, rscratch);
2078 } else if (vector_len == AVX_256bit) {
2079 vmovdqu(dst, src, rscratch);
2080 } else {
2081 movdqu(dst, src, rscratch);
2082 }
2083 }
2084
2085 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2086 if (vector_len == AVX_512bit) {
2087 evmovdquq(dst, src, AVX_512bit);
2088 } else if (vector_len == AVX_256bit) {
2089 vmovdqu(dst, src);
2090 } else {
2091 movdqu(dst, src);
2092 }
2093 }
2094
2095 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2096 if (vector_len == AVX_512bit) {
2097 evmovdquq(dst, src, AVX_512bit);
2098 } else if (vector_len == AVX_256bit) {
2099 vmovdqu(dst, src);
2100 } else {
2101 movdqu(dst, src);
2102 }
2103 }
2104
2105 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2106 if (vector_len == AVX_512bit) {
2107 evmovdquq(dst, src, AVX_512bit);
2108 } else if (vector_len == AVX_256bit) {
2109 vmovdqu(dst, src);
2110 } else {
2111 movdqu(dst, src);
2112 }
2113 }
2114
2115 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2116 assert(rscratch != noreg || always_reachable(src), "missing");
2117
2118 if (reachable(src)) {
2119 vmovdqa(dst, as_Address(src));
2120 }
2121 else {
2122 lea(rscratch, src);
2123 vmovdqa(dst, Address(rscratch, 0));
2124 }
2125 }
2126
2127 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2128 assert(rscratch != noreg || always_reachable(src), "missing");
2129
2130 if (vector_len == AVX_512bit) {
2131 evmovdqaq(dst, src, AVX_512bit, rscratch);
2132 } else if (vector_len == AVX_256bit) {
2133 vmovdqa(dst, src, rscratch);
2134 } else {
2135 movdqa(dst, src, rscratch);
2136 }
2137 }
2138
2139 void MacroAssembler::kmov(KRegister dst, Address src) {
2140 if (VM_Version::supports_avx512bw()) {
2141 kmovql(dst, src);
2142 } else {
2143 assert(VM_Version::supports_evex(), "");
2144 kmovwl(dst, src);
2145 }
2146 }
2147
2148 void MacroAssembler::kmov(Address dst, KRegister src) {
2149 if (VM_Version::supports_avx512bw()) {
2150 kmovql(dst, src);
2151 } else {
2152 assert(VM_Version::supports_evex(), "");
2153 kmovwl(dst, src);
2154 }
2155 }
2156
2157 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2158 if (VM_Version::supports_avx512bw()) {
2159 kmovql(dst, src);
2160 } else {
2161 assert(VM_Version::supports_evex(), "");
2162 kmovwl(dst, src);
2163 }
2164 }
2165
2166 void MacroAssembler::kmov(Register dst, KRegister src) {
2167 if (VM_Version::supports_avx512bw()) {
2168 kmovql(dst, src);
2169 } else {
2170 assert(VM_Version::supports_evex(), "");
2171 kmovwl(dst, src);
2172 }
2173 }
2174
2175 void MacroAssembler::kmov(KRegister dst, Register src) {
2176 if (VM_Version::supports_avx512bw()) {
2177 kmovql(dst, src);
2178 } else {
2179 assert(VM_Version::supports_evex(), "");
2180 kmovwl(dst, src);
2181 }
2182 }
2183
2184 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2185 assert(rscratch != noreg || always_reachable(src), "missing");
2186
2187 if (reachable(src)) {
2188 kmovql(dst, as_Address(src));
2189 } else {
2190 lea(rscratch, src);
2191 kmovql(dst, Address(rscratch, 0));
2192 }
2193 }
2194
2195 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2196 assert(rscratch != noreg || always_reachable(src), "missing");
2197
2198 if (reachable(src)) {
2199 kmovwl(dst, as_Address(src));
2200 } else {
2201 lea(rscratch, src);
2202 kmovwl(dst, Address(rscratch, 0));
2203 }
2204 }
2205
2206 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2207 int vector_len, Register rscratch) {
2208 assert(rscratch != noreg || always_reachable(src), "missing");
2209
2210 if (reachable(src)) {
2211 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2212 } else {
2213 lea(rscratch, src);
2214 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2215 }
2216 }
2217
2218 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2219 int vector_len, Register rscratch) {
2220 assert(rscratch != noreg || always_reachable(src), "missing");
2221
2222 if (reachable(src)) {
2223 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2224 } else {
2225 lea(rscratch, src);
2226 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2227 }
2228 }
2229
2230 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2231 assert(rscratch != noreg || always_reachable(src), "missing");
2232
2233 if (reachable(src)) {
2234 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2235 } else {
2236 lea(rscratch, src);
2237 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2238 }
2239 }
2240
2241 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2242 assert(rscratch != noreg || always_reachable(src), "missing");
2243
2244 if (reachable(src)) {
2245 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2246 } else {
2247 lea(rscratch, src);
2248 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2249 }
2250 }
2251
2252 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2253 assert(rscratch != noreg || always_reachable(src), "missing");
2254
2255 if (reachable(src)) {
2256 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2257 } else {
2258 lea(rscratch, src);
2259 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2260 }
2261 }
2262
2263 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2264 assert(rscratch != noreg || always_reachable(src), "missing");
2265
2266 if (reachable(src)) {
2267 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2268 } else {
2269 lea(rscratch, src);
2270 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2271 }
2272 }
2273
2274 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2275 assert(rscratch != noreg || always_reachable(src), "missing");
2276
2277 if (reachable(src)) {
2278 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2279 } else {
2280 lea(rscratch, src);
2281 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2282 }
2283 }
2284
2285 void MacroAssembler::movapd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2286 assert(rscratch != noreg || always_reachable(src), "missing");
2287
2288 if (reachable(src)) {
2289 Assembler::movapd(dst, as_Address(src));
2290 } else {
2291 lea(rscratch, src);
2292 Assembler::movapd(dst, Address(rscratch, 0));
2293 }
2294 }
2295
2296 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2297 assert(rscratch != noreg || always_reachable(src), "missing");
2298
2299 if (reachable(src)) {
2300 Assembler::movdqa(dst, as_Address(src));
2301 } else {
2302 lea(rscratch, src);
2303 Assembler::movdqa(dst, Address(rscratch, 0));
2304 }
2305 }
2306
2307 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2308 assert(rscratch != noreg || always_reachable(src), "missing");
2309
2310 if (reachable(src)) {
2311 Assembler::movsd(dst, as_Address(src));
2312 } else {
2313 lea(rscratch, src);
2314 Assembler::movsd(dst, Address(rscratch, 0));
2315 }
2316 }
2317
2318 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2319 assert(rscratch != noreg || always_reachable(src), "missing");
2320
2321 if (reachable(src)) {
2322 Assembler::movss(dst, as_Address(src));
2323 } else {
2324 lea(rscratch, src);
2325 Assembler::movss(dst, Address(rscratch, 0));
2326 }
2327 }
2328
2329 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2330 assert(rscratch != noreg || always_reachable(src), "missing");
2331
2332 if (reachable(src)) {
2333 Assembler::movddup(dst, as_Address(src));
2334 } else {
2335 lea(rscratch, src);
2336 Assembler::movddup(dst, Address(rscratch, 0));
2337 }
2338 }
2339
2340 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2341 assert(rscratch != noreg || always_reachable(src), "missing");
2342
2343 if (reachable(src)) {
2344 Assembler::vmovddup(dst, as_Address(src), vector_len);
2345 } else {
2346 lea(rscratch, src);
2347 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2348 }
2349 }
2350
2351 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2352 assert(rscratch != noreg || always_reachable(src), "missing");
2353
2354 if (reachable(src)) {
2355 Assembler::mulsd(dst, as_Address(src));
2356 } else {
2357 lea(rscratch, src);
2358 Assembler::mulsd(dst, Address(rscratch, 0));
2359 }
2360 }
2361
2362 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2363 assert(rscratch != noreg || always_reachable(src), "missing");
2364
2365 if (reachable(src)) {
2366 Assembler::mulss(dst, as_Address(src));
2367 } else {
2368 lea(rscratch, src);
2369 Assembler::mulss(dst, Address(rscratch, 0));
2370 }
2371 }
2372
2373 void MacroAssembler::null_check(Register reg, int offset) {
2374 if (needs_explicit_null_check(offset)) {
2375 // provoke OS null exception if reg is null by
2376 // accessing M[reg] w/o changing any (non-CC) registers
2377 // NOTE: cmpl is plenty here to provoke a segv
2378 cmpptr(rax, Address(reg, 0));
2379 // Note: should probably use testl(rax, Address(reg, 0));
2380 // may be shorter code (however, this version of
2381 // testl needs to be implemented first)
2382 } else {
2383 // nothing to do, (later) access of M[reg + offset]
2384 // will provoke OS null exception if reg is null
2385 }
2386 }
2387
2388 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2389 andptr(markword, markWord::inline_type_pattern_mask);
2390 cmpptr(markword, markWord::inline_type_pattern);
2391 jcc(Assembler::equal, is_inline_type);
2392 }
2393
2394 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null) {
2395 if (can_be_null) {
2396 testptr(object, object);
2397 jcc(Assembler::zero, not_inline_type);
2398 }
2399 const int is_inline_type_mask = markWord::inline_type_pattern;
2400 movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2401 andptr(tmp, is_inline_type_mask);
2402 cmpptr(tmp, is_inline_type_mask);
2403 jcc(Assembler::notEqual, not_inline_type);
2404 }
2405
2406 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2407 movl(temp_reg, flags);
2408 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2409 jcc(Assembler::notEqual, is_null_free_inline_type);
2410 }
2411
2412 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2413 movl(temp_reg, flags);
2414 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2415 jcc(Assembler::equal, not_null_free_inline_type);
2416 }
2417
2418 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2419 movl(temp_reg, flags);
2420 testl(temp_reg, 1 << ResolvedFieldEntry::is_flat_shift);
2421 jcc(Assembler::notEqual, is_flat);
2422 }
2423
2424 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2425 movl(temp_reg, flags);
2426 testl(temp_reg, 1 << ResolvedFieldEntry::has_null_marker_shift);
2427 jcc(Assembler::notEqual, has_null_marker);
2428 }
2429
2430 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2431 Label test_mark_word;
2432 // load mark word
2433 movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2434 // check displaced
2435 testl(temp_reg, markWord::unlocked_value);
2436 jccb(Assembler::notZero, test_mark_word);
2437 // slow path use klass prototype
2438 push(rscratch1);
2439 load_prototype_header(temp_reg, oop, rscratch1);
2440 pop(rscratch1);
2441
2442 bind(test_mark_word);
2443 testl(temp_reg, test_bit);
2444 jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
2445 }
2446
2447 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg,
2448 Label& is_flat_array) {
2449 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2450 }
2451
2452 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2453 Label& is_non_flat_array) {
2454 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2455 }
2456
2457 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
2458 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2459 }
2460
2461 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2462 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2463 }
2464
2465 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2466 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2467 jcc(Assembler::notZero, is_flat_array);
2468 }
2469
2470 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
2471 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2472 jcc(Assembler::zero, is_non_flat_array);
2473 }
2474
2475 void MacroAssembler::os_breakpoint() {
2476 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2477 // (e.g., MSVC can't call ps() otherwise)
2478 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2479 }
2480
2481 void MacroAssembler::unimplemented(const char* what) {
2482 const char* buf = nullptr;
2483 {
2484 ResourceMark rm;
2485 stringStream ss;
2486 ss.print("unimplemented: %s", what);
2487 buf = code_string(ss.as_string());
2488 }
2489 stop(buf);
2490 }
2491
2492 #define XSTATE_BV 0x200
2493
2494 void MacroAssembler::pop_CPU_state() {
2495 pop_FPU_state();
2496 pop_IU_state();
2497 }
2498
2499 void MacroAssembler::pop_FPU_state() {
2500 fxrstor(Address(rsp, 0));
2501 addptr(rsp, FPUStateSizeInWords * wordSize);
2502 }
2503
2504 void MacroAssembler::pop_IU_state() {
2505 popa();
2506 addq(rsp, 8);
2507 popf();
2508 }
2509
2510 // Save Integer and Float state
2511 // Warning: Stack must be 16 byte aligned (64bit)
2512 void MacroAssembler::push_CPU_state() {
2513 push_IU_state();
2514 push_FPU_state();
2515 }
2516
2517 void MacroAssembler::push_FPU_state() {
2518 subptr(rsp, FPUStateSizeInWords * wordSize);
2519 fxsave(Address(rsp, 0));
2520 }
2521
2522 void MacroAssembler::push_IU_state() {
2523 // Push flags first because pusha kills them
2524 pushf();
2525 // Make sure rsp stays 16-byte aligned
2526 subq(rsp, 8);
2527 pusha();
2528 }
2529
2530 void MacroAssembler::push_cont_fastpath() {
2531 if (!Continuations::enabled()) return;
2532
2533 Label L_done;
2534 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2535 jccb(Assembler::belowEqual, L_done);
2536 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), rsp);
2537 bind(L_done);
2538 }
2539
2540 void MacroAssembler::pop_cont_fastpath() {
2541 if (!Continuations::enabled()) return;
2542
2543 Label L_done;
2544 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2545 jccb(Assembler::below, L_done);
2546 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), 0);
2547 bind(L_done);
2548 }
2549
2550 #ifdef ASSERT
2551 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2552 Label no_cont;
2553 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2554 testl(cont, cont);
2555 jcc(Assembler::zero, no_cont);
2556 stop(name);
2557 bind(no_cont);
2558 }
2559 #endif
2560
2561 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { // determine java_thread register
2562 // we must set sp to zero to clear frame
2563 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2564 // must clear fp, so that compiled frames are not confused; it is
2565 // possible that we need it only for debugging
2566 if (clear_fp) {
2567 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2568 }
2569 // Always clear the pc because it could have been set by make_walkable()
2570 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2571 vzeroupper();
2572 }
2573
2574 void MacroAssembler::round_to(Register reg, int modulus) {
2575 addptr(reg, modulus - 1);
2576 andptr(reg, -modulus);
2577 }
2578
2579 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod) {
2580 if (at_return) {
2581 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2582 // we may safely use rsp instead to perform the stack watermark check.
2583 cmpptr(in_nmethod ? rsp : rbp, Address(r15_thread, JavaThread::polling_word_offset()));
2584 jcc(Assembler::above, slow_path);
2585 return;
2586 }
2587 testb(Address(r15_thread, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2588 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2589 }
2590
2591 // Calls to C land
2592 //
2593 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2594 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2595 // has to be reset to 0. This is required to allow proper stack traversal.
2596 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2597 Register last_java_fp,
2598 address last_java_pc,
2599 Register rscratch) {
2600 vzeroupper();
2601 // determine last_java_sp register
2602 if (!last_java_sp->is_valid()) {
2603 last_java_sp = rsp;
2604 }
2605 // last_java_fp is optional
2606 if (last_java_fp->is_valid()) {
2607 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2608 }
2609 // last_java_pc is optional
2610 if (last_java_pc != nullptr) {
2611 Address java_pc(r15_thread,
2612 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
2613 lea(java_pc, InternalAddress(last_java_pc), rscratch);
2614 }
2615 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2616 }
2617
2618 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2619 Register last_java_fp,
2620 Label &L,
2621 Register scratch) {
2622 lea(scratch, L);
2623 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
2624 set_last_Java_frame(last_java_sp, last_java_fp, nullptr, scratch);
2625 }
2626
2627 void MacroAssembler::shlptr(Register dst, int imm8) {
2628 shlq(dst, imm8);
2629 }
2630
2631 void MacroAssembler::shrptr(Register dst, int imm8) {
2632 shrq(dst, imm8);
2633 }
2634
2635 void MacroAssembler::sign_extend_byte(Register reg) {
2636 movsbl(reg, reg); // movsxb
2637 }
2638
2639 void MacroAssembler::sign_extend_short(Register reg) {
2640 movswl(reg, reg); // movsxw
2641 }
2642
2643 void MacroAssembler::narrow_subword_type(Register reg, BasicType bt) {
2644 assert(is_subword_type(bt), "required");
2645 switch (bt) {
2646 case T_BOOLEAN: andl(reg, 1); break;
2647 case T_BYTE: movsbl(reg, reg); break;
2648 case T_CHAR: movzwl(reg, reg); break;
2649 case T_SHORT: movswl(reg, reg); break;
2650 default: ShouldNotReachHere();
2651 }
2652 }
2653
2654 void MacroAssembler::testl(Address dst, int32_t imm32) {
2655 if (imm32 >= 0 && is8bit(imm32)) {
2656 testb(dst, imm32);
2657 } else {
2658 Assembler::testl(dst, imm32);
2659 }
2660 }
2661
2662 void MacroAssembler::testl(Register dst, int32_t imm32) {
2663 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
2664 testb(dst, imm32);
2665 } else {
2666 Assembler::testl(dst, imm32);
2667 }
2668 }
2669
2670 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2671 assert(always_reachable(src), "Address should be reachable");
2672 testl(dst, as_Address(src));
2673 }
2674
2675 void MacroAssembler::testq(Address dst, int32_t imm32) {
2676 if (imm32 >= 0) {
2677 testl(dst, imm32);
2678 } else {
2679 Assembler::testq(dst, imm32);
2680 }
2681 }
2682
2683 void MacroAssembler::testq(Register dst, int32_t imm32) {
2684 if (imm32 >= 0) {
2685 testl(dst, imm32);
2686 } else {
2687 Assembler::testq(dst, imm32);
2688 }
2689 }
2690
2691 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2692 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2693 Assembler::pcmpeqb(dst, src);
2694 }
2695
2696 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2697 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2698 Assembler::pcmpeqw(dst, src);
2699 }
2700
2701 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2702 assert((dst->encoding() < 16),"XMM register should be 0-15");
2703 Assembler::pcmpestri(dst, src, imm8);
2704 }
2705
2706 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2707 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2708 Assembler::pcmpestri(dst, src, imm8);
2709 }
2710
2711 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2712 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2713 Assembler::pmovzxbw(dst, src);
2714 }
2715
2716 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2717 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2718 Assembler::pmovzxbw(dst, src);
2719 }
2720
2721 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2722 assert((src->encoding() < 16),"XMM register should be 0-15");
2723 Assembler::pmovmskb(dst, src);
2724 }
2725
2726 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2727 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2728 Assembler::ptest(dst, src);
2729 }
2730
2731 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2732 assert(rscratch != noreg || always_reachable(src), "missing");
2733
2734 if (reachable(src)) {
2735 Assembler::sqrtss(dst, as_Address(src));
2736 } else {
2737 lea(rscratch, src);
2738 Assembler::sqrtss(dst, Address(rscratch, 0));
2739 }
2740 }
2741
2742 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2743 assert(rscratch != noreg || always_reachable(src), "missing");
2744
2745 if (reachable(src)) {
2746 Assembler::subsd(dst, as_Address(src));
2747 } else {
2748 lea(rscratch, src);
2749 Assembler::subsd(dst, Address(rscratch, 0));
2750 }
2751 }
2752
2753 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
2754 assert(rscratch != noreg || always_reachable(src), "missing");
2755
2756 if (reachable(src)) {
2757 Assembler::roundsd(dst, as_Address(src), rmode);
2758 } else {
2759 lea(rscratch, src);
2760 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
2761 }
2762 }
2763
2764 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2765 assert(rscratch != noreg || always_reachable(src), "missing");
2766
2767 if (reachable(src)) {
2768 Assembler::subss(dst, as_Address(src));
2769 } else {
2770 lea(rscratch, src);
2771 Assembler::subss(dst, Address(rscratch, 0));
2772 }
2773 }
2774
2775 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2776 assert(rscratch != noreg || always_reachable(src), "missing");
2777
2778 if (reachable(src)) {
2779 Assembler::ucomisd(dst, as_Address(src));
2780 } else {
2781 lea(rscratch, src);
2782 Assembler::ucomisd(dst, Address(rscratch, 0));
2783 }
2784 }
2785
2786 void MacroAssembler::evucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2787 assert(rscratch != noreg || always_reachable(src), "missing");
2788
2789 if (reachable(src)) {
2790 Assembler::evucomxsd(dst, as_Address(src));
2791 } else {
2792 lea(rscratch, src);
2793 Assembler::evucomxsd(dst, Address(rscratch, 0));
2794 }
2795 }
2796
2797 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2798 assert(rscratch != noreg || always_reachable(src), "missing");
2799
2800 if (reachable(src)) {
2801 Assembler::ucomiss(dst, as_Address(src));
2802 } else {
2803 lea(rscratch, src);
2804 Assembler::ucomiss(dst, Address(rscratch, 0));
2805 }
2806 }
2807
2808 void MacroAssembler::evucomxss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2809 assert(rscratch != noreg || always_reachable(src), "missing");
2810
2811 if (reachable(src)) {
2812 Assembler::evucomxss(dst, as_Address(src));
2813 } else {
2814 lea(rscratch, src);
2815 Assembler::evucomxss(dst, Address(rscratch, 0));
2816 }
2817 }
2818
2819 void MacroAssembler::evucomish(XMMRegister dst, AddressLiteral src, Register rscratch) {
2820 assert(rscratch != noreg || always_reachable(src), "missing");
2821
2822 if (reachable(src)) {
2823 Assembler::evucomish(dst, as_Address(src));
2824 } else {
2825 lea(rscratch, src);
2826 Assembler::evucomish(dst, Address(rscratch, 0));
2827 }
2828 }
2829
2830 void MacroAssembler::evucomxsh(XMMRegister dst, AddressLiteral src, Register rscratch) {
2831 assert(rscratch != noreg || always_reachable(src), "missing");
2832
2833 if (reachable(src)) {
2834 Assembler::evucomxsh(dst, as_Address(src));
2835 } else {
2836 lea(rscratch, src);
2837 Assembler::evucomxsh(dst, Address(rscratch, 0));
2838 }
2839 }
2840
2841 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2842 assert(rscratch != noreg || always_reachable(src), "missing");
2843
2844 // Used in sign-bit flipping with aligned address.
2845 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2846
2847 if (UseAVX > 2 &&
2848 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2849 (dst->encoding() >= 16)) {
2850 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2851 } else if (reachable(src)) {
2852 Assembler::xorpd(dst, as_Address(src));
2853 } else {
2854 lea(rscratch, src);
2855 Assembler::xorpd(dst, Address(rscratch, 0));
2856 }
2857 }
2858
2859 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
2860 if (UseAVX > 2 &&
2861 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2862 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2863 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2864 } else {
2865 Assembler::xorpd(dst, src);
2866 }
2867 }
2868
2869 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
2870 if (UseAVX > 2 &&
2871 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2872 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2873 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2874 } else {
2875 Assembler::xorps(dst, src);
2876 }
2877 }
2878
2879 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
2880 assert(rscratch != noreg || always_reachable(src), "missing");
2881
2882 // Used in sign-bit flipping with aligned address.
2883 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2884
2885 if (UseAVX > 2 &&
2886 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2887 (dst->encoding() >= 16)) {
2888 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2889 } else if (reachable(src)) {
2890 Assembler::xorps(dst, as_Address(src));
2891 } else {
2892 lea(rscratch, src);
2893 Assembler::xorps(dst, Address(rscratch, 0));
2894 }
2895 }
2896
2897 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
2898 assert(rscratch != noreg || always_reachable(src), "missing");
2899
2900 // Used in sign-bit flipping with aligned address.
2901 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
2902 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2903 if (reachable(src)) {
2904 Assembler::pshufb(dst, as_Address(src));
2905 } else {
2906 lea(rscratch, src);
2907 Assembler::pshufb(dst, Address(rscratch, 0));
2908 }
2909 }
2910
2911 // AVX 3-operands instructions
2912
2913 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2914 assert(rscratch != noreg || always_reachable(src), "missing");
2915
2916 if (reachable(src)) {
2917 vaddsd(dst, nds, as_Address(src));
2918 } else {
2919 lea(rscratch, src);
2920 vaddsd(dst, nds, Address(rscratch, 0));
2921 }
2922 }
2923
2924 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2925 assert(rscratch != noreg || always_reachable(src), "missing");
2926
2927 if (reachable(src)) {
2928 vaddss(dst, nds, as_Address(src));
2929 } else {
2930 lea(rscratch, src);
2931 vaddss(dst, nds, Address(rscratch, 0));
2932 }
2933 }
2934
2935 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2936 assert(UseAVX > 0, "requires some form of AVX");
2937 assert(rscratch != noreg || always_reachable(src), "missing");
2938
2939 if (reachable(src)) {
2940 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
2941 } else {
2942 lea(rscratch, src);
2943 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
2944 }
2945 }
2946
2947 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2948 assert(UseAVX > 0, "requires some form of AVX");
2949 assert(rscratch != noreg || always_reachable(src), "missing");
2950
2951 if (reachable(src)) {
2952 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
2953 } else {
2954 lea(rscratch, src);
2955 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
2956 }
2957 }
2958
2959 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2960 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2961 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2962
2963 vandps(dst, nds, negate_field, vector_len, rscratch);
2964 }
2965
2966 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2967 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2968 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2969
2970 vandpd(dst, nds, negate_field, vector_len, rscratch);
2971 }
2972
2973 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2974 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2975 Assembler::vpaddb(dst, nds, src, vector_len);
2976 }
2977
2978 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2979 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2980 Assembler::vpaddb(dst, nds, src, vector_len);
2981 }
2982
2983 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2984 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2985 Assembler::vpaddw(dst, nds, src, vector_len);
2986 }
2987
2988 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2989 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2990 Assembler::vpaddw(dst, nds, src, vector_len);
2991 }
2992
2993 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2994 assert(rscratch != noreg || always_reachable(src), "missing");
2995
2996 if (reachable(src)) {
2997 Assembler::vpand(dst, nds, as_Address(src), vector_len);
2998 } else {
2999 lea(rscratch, src);
3000 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3001 }
3002 }
3003
3004 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3005 assert(rscratch != noreg || always_reachable(src), "missing");
3006
3007 if (reachable(src)) {
3008 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3009 } else {
3010 lea(rscratch, src);
3011 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3012 }
3013 }
3014
3015 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3016 assert(rscratch != noreg || always_reachable(src), "missing");
3017
3018 if (reachable(src)) {
3019 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3020 } else {
3021 lea(rscratch, src);
3022 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3023 }
3024 }
3025
3026 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3027 assert(rscratch != noreg || always_reachable(src), "missing");
3028
3029 if (reachable(src)) {
3030 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3031 } else {
3032 lea(rscratch, src);
3033 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3034 }
3035 }
3036
3037 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3038 assert(rscratch != noreg || always_reachable(src), "missing");
3039
3040 if (reachable(src)) {
3041 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3042 } else {
3043 lea(rscratch, src);
3044 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3045 }
3046 }
3047
3048 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3049 assert(rscratch != noreg || always_reachable(src), "missing");
3050
3051 if (reachable(src)) {
3052 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3053 } else {
3054 lea(rscratch, src);
3055 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3056 }
3057 }
3058
3059 // Vector float blend
3060 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3061 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3062 // WARN: Allow dst == (src1|src2), mask == scratch
3063 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3064 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3065 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3066 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3067 if (blend_emulation && scratch_available && dst_available) {
3068 if (compute_mask) {
3069 vpsrad(scratch, mask, 32, vector_len);
3070 mask = scratch;
3071 }
3072 if (dst == src1) {
3073 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3074 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3075 } else {
3076 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3077 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3078 }
3079 vpor(dst, dst, scratch, vector_len);
3080 } else {
3081 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3082 }
3083 }
3084
3085 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3086 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3087 // WARN: Allow dst == (src1|src2), mask == scratch
3088 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3089 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3090 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3091 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3092 if (blend_emulation && scratch_available && dst_available) {
3093 if (compute_mask) {
3094 vpxor(scratch, scratch, scratch, vector_len);
3095 vpcmpgtq(scratch, scratch, mask, vector_len);
3096 mask = scratch;
3097 }
3098 if (dst == src1) {
3099 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3100 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3101 } else {
3102 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3103 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3104 }
3105 vpor(dst, dst, scratch, vector_len);
3106 } else {
3107 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3108 }
3109 }
3110
3111 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3112 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3113 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3114 }
3115
3116 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3117 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3118 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3119 }
3120
3121 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3122 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3123 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3124 }
3125
3126 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3127 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3128 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3129 }
3130
3131 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3132 assert(rscratch != noreg || always_reachable(src), "missing");
3133
3134 if (reachable(src)) {
3135 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3136 } else {
3137 lea(rscratch, src);
3138 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3139 }
3140 }
3141
3142 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3143 int comparison, bool is_signed, int vector_len, Register rscratch) {
3144 assert(rscratch != noreg || always_reachable(src), "missing");
3145
3146 if (reachable(src)) {
3147 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3148 } else {
3149 lea(rscratch, src);
3150 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3151 }
3152 }
3153
3154 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3155 int comparison, bool is_signed, int vector_len, Register rscratch) {
3156 assert(rscratch != noreg || always_reachable(src), "missing");
3157
3158 if (reachable(src)) {
3159 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3160 } else {
3161 lea(rscratch, src);
3162 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3163 }
3164 }
3165
3166 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3167 int comparison, bool is_signed, int vector_len, Register rscratch) {
3168 assert(rscratch != noreg || always_reachable(src), "missing");
3169
3170 if (reachable(src)) {
3171 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3172 } else {
3173 lea(rscratch, src);
3174 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3175 }
3176 }
3177
3178 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3179 int comparison, bool is_signed, int vector_len, Register rscratch) {
3180 assert(rscratch != noreg || always_reachable(src), "missing");
3181
3182 if (reachable(src)) {
3183 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3184 } else {
3185 lea(rscratch, src);
3186 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3187 }
3188 }
3189
3190 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3191 if (width == Assembler::Q) {
3192 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3193 } else {
3194 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3195 }
3196 }
3197
3198 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3199 int eq_cond_enc = 0x29;
3200 int gt_cond_enc = 0x37;
3201 if (width != Assembler::Q) {
3202 eq_cond_enc = 0x74 + width;
3203 gt_cond_enc = 0x64 + width;
3204 }
3205 switch (cond) {
3206 case eq:
3207 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3208 break;
3209 case neq:
3210 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3211 vallones(xtmp, vector_len);
3212 vpxor(dst, xtmp, dst, vector_len);
3213 break;
3214 case le:
3215 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3216 vallones(xtmp, vector_len);
3217 vpxor(dst, xtmp, dst, vector_len);
3218 break;
3219 case nlt:
3220 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3221 vallones(xtmp, vector_len);
3222 vpxor(dst, xtmp, dst, vector_len);
3223 break;
3224 case lt:
3225 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3226 break;
3227 case nle:
3228 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3229 break;
3230 default:
3231 assert(false, "Should not reach here");
3232 }
3233 }
3234
3235 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3236 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3237 Assembler::vpmovzxbw(dst, src, vector_len);
3238 }
3239
3240 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3241 assert((src->encoding() < 16),"XMM register should be 0-15");
3242 Assembler::vpmovmskb(dst, src, vector_len);
3243 }
3244
3245 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3246 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3247 Assembler::vpmullw(dst, nds, src, vector_len);
3248 }
3249
3250 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3251 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3252 Assembler::vpmullw(dst, nds, src, vector_len);
3253 }
3254
3255 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3256 assert((UseAVX > 0), "AVX support is needed");
3257 assert(rscratch != noreg || always_reachable(src), "missing");
3258
3259 if (reachable(src)) {
3260 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3261 } else {
3262 lea(rscratch, src);
3263 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3264 }
3265 }
3266
3267 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3268 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3269 Assembler::vpsubb(dst, nds, src, vector_len);
3270 }
3271
3272 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3273 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3274 Assembler::vpsubb(dst, nds, src, vector_len);
3275 }
3276
3277 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3278 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3279 Assembler::vpsubw(dst, nds, src, vector_len);
3280 }
3281
3282 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3283 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3284 Assembler::vpsubw(dst, nds, src, vector_len);
3285 }
3286
3287 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3288 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3289 Assembler::vpsraw(dst, nds, shift, vector_len);
3290 }
3291
3292 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3293 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3294 Assembler::vpsraw(dst, nds, shift, vector_len);
3295 }
3296
3297 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3298 assert(UseAVX > 2,"");
3299 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3300 vector_len = 2;
3301 }
3302 Assembler::evpsraq(dst, nds, shift, vector_len);
3303 }
3304
3305 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3306 assert(UseAVX > 2,"");
3307 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3308 vector_len = 2;
3309 }
3310 Assembler::evpsraq(dst, nds, shift, vector_len);
3311 }
3312
3313 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3314 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3315 Assembler::vpsrlw(dst, nds, shift, vector_len);
3316 }
3317
3318 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3319 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3320 Assembler::vpsrlw(dst, nds, shift, vector_len);
3321 }
3322
3323 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3324 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3325 Assembler::vpsllw(dst, nds, shift, vector_len);
3326 }
3327
3328 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3329 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3330 Assembler::vpsllw(dst, nds, shift, vector_len);
3331 }
3332
3333 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3334 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3335 Assembler::vptest(dst, src);
3336 }
3337
3338 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3339 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3340 Assembler::punpcklbw(dst, src);
3341 }
3342
3343 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3344 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3345 Assembler::pshufd(dst, src, mode);
3346 }
3347
3348 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3349 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3350 Assembler::pshuflw(dst, src, mode);
3351 }
3352
3353 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3354 assert(rscratch != noreg || always_reachable(src), "missing");
3355
3356 if (reachable(src)) {
3357 vandpd(dst, nds, as_Address(src), vector_len);
3358 } else {
3359 lea(rscratch, src);
3360 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3361 }
3362 }
3363
3364 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3365 assert(rscratch != noreg || always_reachable(src), "missing");
3366
3367 if (reachable(src)) {
3368 vandps(dst, nds, as_Address(src), vector_len);
3369 } else {
3370 lea(rscratch, src);
3371 vandps(dst, nds, Address(rscratch, 0), vector_len);
3372 }
3373 }
3374
3375 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3376 bool merge, int vector_len, Register rscratch) {
3377 assert(rscratch != noreg || always_reachable(src), "missing");
3378
3379 if (reachable(src)) {
3380 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3381 } else {
3382 lea(rscratch, src);
3383 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3384 }
3385 }
3386
3387 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3388 assert(rscratch != noreg || always_reachable(src), "missing");
3389
3390 if (reachable(src)) {
3391 vdivsd(dst, nds, as_Address(src));
3392 } else {
3393 lea(rscratch, src);
3394 vdivsd(dst, nds, Address(rscratch, 0));
3395 }
3396 }
3397
3398 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3399 assert(rscratch != noreg || always_reachable(src), "missing");
3400
3401 if (reachable(src)) {
3402 vdivss(dst, nds, as_Address(src));
3403 } else {
3404 lea(rscratch, src);
3405 vdivss(dst, nds, Address(rscratch, 0));
3406 }
3407 }
3408
3409 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3410 assert(rscratch != noreg || always_reachable(src), "missing");
3411
3412 if (reachable(src)) {
3413 vmulsd(dst, nds, as_Address(src));
3414 } else {
3415 lea(rscratch, src);
3416 vmulsd(dst, nds, Address(rscratch, 0));
3417 }
3418 }
3419
3420 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3421 assert(rscratch != noreg || always_reachable(src), "missing");
3422
3423 if (reachable(src)) {
3424 vmulss(dst, nds, as_Address(src));
3425 } else {
3426 lea(rscratch, src);
3427 vmulss(dst, nds, Address(rscratch, 0));
3428 }
3429 }
3430
3431 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3432 assert(rscratch != noreg || always_reachable(src), "missing");
3433
3434 if (reachable(src)) {
3435 vsubsd(dst, nds, as_Address(src));
3436 } else {
3437 lea(rscratch, src);
3438 vsubsd(dst, nds, Address(rscratch, 0));
3439 }
3440 }
3441
3442 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3443 assert(rscratch != noreg || always_reachable(src), "missing");
3444
3445 if (reachable(src)) {
3446 vsubss(dst, nds, as_Address(src));
3447 } else {
3448 lea(rscratch, src);
3449 vsubss(dst, nds, Address(rscratch, 0));
3450 }
3451 }
3452
3453 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3454 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3455 assert(rscratch != noreg || always_reachable(src), "missing");
3456
3457 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3458 }
3459
3460 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3461 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3462 assert(rscratch != noreg || always_reachable(src), "missing");
3463
3464 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3465 }
3466
3467 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3468 assert(rscratch != noreg || always_reachable(src), "missing");
3469
3470 if (reachable(src)) {
3471 vxorpd(dst, nds, as_Address(src), vector_len);
3472 } else {
3473 lea(rscratch, src);
3474 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3475 }
3476 }
3477
3478 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3479 assert(rscratch != noreg || always_reachable(src), "missing");
3480
3481 if (reachable(src)) {
3482 vxorps(dst, nds, as_Address(src), vector_len);
3483 } else {
3484 lea(rscratch, src);
3485 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3486 }
3487 }
3488
3489 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3490 assert(rscratch != noreg || always_reachable(src), "missing");
3491
3492 if (UseAVX > 1 || (vector_len < 1)) {
3493 if (reachable(src)) {
3494 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3495 } else {
3496 lea(rscratch, src);
3497 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3498 }
3499 } else {
3500 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3501 }
3502 }
3503
3504 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3505 assert(rscratch != noreg || always_reachable(src), "missing");
3506
3507 if (reachable(src)) {
3508 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3509 } else {
3510 lea(rscratch, src);
3511 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3512 }
3513 }
3514
3515 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3516 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3517 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3518 // The inverted mask is sign-extended
3519 andptr(possibly_non_local, inverted_mask);
3520 }
3521
3522 void MacroAssembler::resolve_jobject(Register value,
3523 Register tmp) {
3524 Register thread = r15_thread;
3525 assert_different_registers(value, thread, tmp);
3526 Label done, tagged, weak_tagged;
3527 testptr(value, value);
3528 jcc(Assembler::zero, done); // Use null as-is.
3529 testptr(value, JNIHandles::tag_mask); // Test for tag.
3530 jcc(Assembler::notZero, tagged);
3531
3532 // Resolve local handle
3533 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp);
3534 verify_oop(value);
3535 jmp(done);
3536
3537 bind(tagged);
3538 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3539 jcc(Assembler::notZero, weak_tagged);
3540
3541 // Resolve global handle
3542 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3543 verify_oop(value);
3544 jmp(done);
3545
3546 bind(weak_tagged);
3547 // Resolve jweak.
3548 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3549 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp);
3550 verify_oop(value);
3551
3552 bind(done);
3553 }
3554
3555 void MacroAssembler::resolve_global_jobject(Register value,
3556 Register tmp) {
3557 Register thread = r15_thread;
3558 assert_different_registers(value, thread, tmp);
3559 Label done;
3560
3561 testptr(value, value);
3562 jcc(Assembler::zero, done); // Use null as-is.
3563
3564 #ifdef ASSERT
3565 {
3566 Label valid_global_tag;
3567 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
3568 jcc(Assembler::notZero, valid_global_tag);
3569 stop("non global jobject using resolve_global_jobject");
3570 bind(valid_global_tag);
3571 }
3572 #endif
3573
3574 // Resolve global handle
3575 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3576 verify_oop(value);
3577
3578 bind(done);
3579 }
3580
3581 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3582 subq(dst, imm32);
3583 }
3584
3585 // Force generation of a 4 byte immediate value even if it fits into 8bit
3586 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3587 subq_imm32(dst, imm32);
3588 }
3589
3590 void MacroAssembler::subptr(Register dst, Register src) {
3591 subq(dst, src);
3592 }
3593
3594 // C++ bool manipulation
3595 void MacroAssembler::testbool(Register dst) {
3596 if(sizeof(bool) == 1)
3597 testb(dst, 0xff);
3598 else if(sizeof(bool) == 2) {
3599 // testw implementation needed for two byte bools
3600 ShouldNotReachHere();
3601 } else if(sizeof(bool) == 4)
3602 testl(dst, dst);
3603 else
3604 // unsupported
3605 ShouldNotReachHere();
3606 }
3607
3608 void MacroAssembler::testptr(Register dst, Register src) {
3609 testq(dst, src);
3610 }
3611
3612 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3613 void MacroAssembler::tlab_allocate(Register obj,
3614 Register var_size_in_bytes,
3615 int con_size_in_bytes,
3616 Register t1,
3617 Register t2,
3618 Label& slow_case) {
3619 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3620 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3621 }
3622
3623 RegSet MacroAssembler::call_clobbered_gp_registers() {
3624 RegSet regs;
3625 regs += RegSet::of(rax, rcx, rdx);
3626 #ifndef _WINDOWS
3627 regs += RegSet::of(rsi, rdi);
3628 #endif
3629 regs += RegSet::range(r8, r11);
3630 if (UseAPX) {
3631 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
3632 }
3633 return regs;
3634 }
3635
3636 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3637 int num_xmm_registers = XMMRegister::available_xmm_registers();
3638 #if defined(_WINDOWS)
3639 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3640 if (num_xmm_registers > 16) {
3641 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3642 }
3643 return result;
3644 #else
3645 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3646 #endif
3647 }
3648
3649 // C1 only ever uses the first double/float of the XMM register.
3650 static int xmm_save_size() { return sizeof(double); }
3651
3652 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3653 masm->movdbl(Address(rsp, offset), reg);
3654 }
3655
3656 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3657 masm->movdbl(reg, Address(rsp, offset));
3658 }
3659
3660 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
3661 bool save_fpu, int& gp_area_size, int& xmm_area_size) {
3662
3663 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
3664 StackAlignmentInBytes);
3665 xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
3666
3667 return gp_area_size + xmm_area_size;
3668 }
3669
3670 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3671 block_comment("push_call_clobbered_registers start");
3672 // Regular registers
3673 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3674
3675 int gp_area_size;
3676 int xmm_area_size;
3677 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3678 gp_area_size, xmm_area_size);
3679 subptr(rsp, total_save_size);
3680
3681 push_set(gp_registers_to_push, 0);
3682
3683 if (save_fpu) {
3684 push_set(call_clobbered_xmm_registers(), gp_area_size);
3685 }
3686
3687 block_comment("push_call_clobbered_registers end");
3688 }
3689
3690 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3691 block_comment("pop_call_clobbered_registers start");
3692
3693 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3694
3695 int gp_area_size;
3696 int xmm_area_size;
3697 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3698 gp_area_size, xmm_area_size);
3699
3700 if (restore_fpu) {
3701 pop_set(call_clobbered_xmm_registers(), gp_area_size);
3702 }
3703
3704 pop_set(gp_registers_to_pop, 0);
3705
3706 addptr(rsp, total_save_size);
3707
3708 vzeroupper();
3709
3710 block_comment("pop_call_clobbered_registers end");
3711 }
3712
3713 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3714 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3715 int spill_offset = offset;
3716
3717 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3718 save_xmm_register(this, spill_offset, *it);
3719 spill_offset += xmm_save_size();
3720 }
3721 }
3722
3723 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3724 int restore_size = set.size() * xmm_save_size();
3725 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3726
3727 int restore_offset = offset + restore_size - xmm_save_size();
3728
3729 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3730 restore_xmm_register(this, restore_offset, *it);
3731 restore_offset -= xmm_save_size();
3732 }
3733 }
3734
3735 void MacroAssembler::push_set(RegSet set, int offset) {
3736 int spill_offset;
3737 if (offset == -1) {
3738 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3739 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3740 subptr(rsp, aligned_size);
3741 spill_offset = 0;
3742 } else {
3743 spill_offset = offset;
3744 }
3745
3746 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3747 movptr(Address(rsp, spill_offset), *it);
3748 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3749 }
3750 }
3751
3752 void MacroAssembler::pop_set(RegSet set, int offset) {
3753
3754 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3755 int restore_size = set.size() * gp_reg_size;
3756 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3757
3758 int restore_offset;
3759 if (offset == -1) {
3760 restore_offset = restore_size - gp_reg_size;
3761 } else {
3762 restore_offset = offset + restore_size - gp_reg_size;
3763 }
3764 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3765 movptr(*it, Address(rsp, restore_offset));
3766 restore_offset -= gp_reg_size;
3767 }
3768
3769 if (offset == -1) {
3770 addptr(rsp, aligned_size);
3771 }
3772 }
3773
3774 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3775 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3776 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3777 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3778 Label done;
3779
3780 testptr(length_in_bytes, length_in_bytes);
3781 jcc(Assembler::zero, done);
3782
3783 // initialize topmost word, divide index by 2, check if odd and test if zero
3784 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3785 #ifdef ASSERT
3786 {
3787 Label L;
3788 testptr(length_in_bytes, BytesPerWord - 1);
3789 jcc(Assembler::zero, L);
3790 stop("length must be a multiple of BytesPerWord");
3791 bind(L);
3792 }
3793 #endif
3794 Register index = length_in_bytes;
3795 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3796 if (UseIncDec) {
3797 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3798 } else {
3799 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3800 shrptr(index, 1);
3801 }
3802
3803 // initialize remaining object fields: index is a multiple of 2 now
3804 {
3805 Label loop;
3806 bind(loop);
3807 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3808 decrement(index);
3809 jcc(Assembler::notZero, loop);
3810 }
3811
3812 bind(done);
3813 }
3814
3815 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
3816 movptr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
3817 #ifdef ASSERT
3818 {
3819 Label done;
3820 cmpptr(layout_info, 0);
3821 jcc(Assembler::notEqual, done);
3822 stop("inline_layout_info_array is null");
3823 bind(done);
3824 }
3825 #endif
3826
3827 InlineLayoutInfo array[2];
3828 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
3829 if (is_power_of_2(size)) {
3830 shll(index, log2i_exact(size)); // Scale index by power of 2
3831 } else {
3832 imull(index, index, size); // Scale the index to be the entry index * array_element_size
3833 }
3834 lea(layout_info, Address(layout_info, index, Address::times_1, Array<InlineLayoutInfo>::base_offset_in_bytes()));
3835 }
3836
3837 // Look up the method for a megamorphic invokeinterface call.
3838 // The target method is determined by <intf_klass, itable_index>.
3839 // The receiver klass is in recv_klass.
3840 // On success, the result will be in method_result, and execution falls through.
3841 // On failure, execution transfers to the given label.
3842 void MacroAssembler::lookup_interface_method(Register recv_klass,
3843 Register intf_klass,
3844 RegisterOrConstant itable_index,
3845 Register method_result,
3846 Register scan_temp,
3847 Label& L_no_such_interface,
3848 bool return_method) {
3849 assert_different_registers(recv_klass, intf_klass, scan_temp);
3850 assert_different_registers(method_result, intf_klass, scan_temp);
3851 assert(recv_klass != method_result || !return_method,
3852 "recv_klass can be destroyed when method isn't needed");
3853
3854 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3855 "caller must use same register for non-constant itable index as for method");
3856
3857 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3858 int vtable_base = in_bytes(Klass::vtable_start_offset());
3859 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3860 int scan_step = itableOffsetEntry::size() * wordSize;
3861 int vte_size = vtableEntry::size_in_bytes();
3862 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3863 assert(vte_size == wordSize, "else adjust times_vte_scale");
3864
3865 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3866
3867 // Could store the aligned, prescaled offset in the klass.
3868 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3869
3870 if (return_method) {
3871 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3872 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3873 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3874 }
3875
3876 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
3877 // if (scan->interface() == intf) {
3878 // result = (klass + scan->offset() + itable_index);
3879 // }
3880 // }
3881 Label search, found_method;
3882
3883 for (int peel = 1; peel >= 0; peel--) {
3884 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
3885 cmpptr(intf_klass, method_result);
3886
3887 if (peel) {
3888 jccb(Assembler::equal, found_method);
3889 } else {
3890 jccb(Assembler::notEqual, search);
3891 // (invert the test to fall through to found_method...)
3892 }
3893
3894 if (!peel) break;
3895
3896 bind(search);
3897
3898 // Check that the previous entry is non-null. A null entry means that
3899 // the receiver class doesn't implement the interface, and wasn't the
3900 // same as when the caller was compiled.
3901 testptr(method_result, method_result);
3902 jcc(Assembler::zero, L_no_such_interface);
3903 addptr(scan_temp, scan_step);
3904 }
3905
3906 bind(found_method);
3907
3908 if (return_method) {
3909 // Got a hit.
3910 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
3911 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3912 }
3913 }
3914
3915 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
3916 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
3917 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
3918 // The target method is determined by <holder_klass, itable_index>.
3919 // The receiver klass is in recv_klass.
3920 // On success, the result will be in method_result, and execution falls through.
3921 // On failure, execution transfers to the given label.
3922 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
3923 Register holder_klass,
3924 Register resolved_klass,
3925 Register method_result,
3926 Register scan_temp,
3927 Register temp_reg2,
3928 Register receiver,
3929 int itable_index,
3930 Label& L_no_such_interface) {
3931 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
3932 Register temp_itbl_klass = method_result;
3933 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
3934
3935 int vtable_base = in_bytes(Klass::vtable_start_offset());
3936 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3937 int scan_step = itableOffsetEntry::size() * wordSize;
3938 int vte_size = vtableEntry::size_in_bytes();
3939 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
3940 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
3941 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3942 assert(vte_size == wordSize, "adjust times_vte_scale");
3943
3944 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
3945
3946 // temp_itbl_klass = recv_klass.itable[0]
3947 // scan_temp = &recv_klass.itable[0] + step
3948 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3949 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
3950 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
3951 xorptr(temp_reg, temp_reg);
3952
3953 // Initial checks:
3954 // - if (holder_klass != resolved_klass), go to "scan for resolved"
3955 // - if (itable[0] == 0), no such interface
3956 // - if (itable[0] == holder_klass), shortcut to "holder found"
3957 cmpptr(holder_klass, resolved_klass);
3958 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
3959 testptr(temp_itbl_klass, temp_itbl_klass);
3960 jccb(Assembler::zero, L_no_such_interface);
3961 cmpptr(holder_klass, temp_itbl_klass);
3962 jccb(Assembler::equal, L_holder_found);
3963
3964 // Loop: Look for holder_klass record in itable
3965 // do {
3966 // tmp = itable[index];
3967 // index += step;
3968 // if (tmp == holder_klass) {
3969 // goto L_holder_found; // Found!
3970 // }
3971 // } while (tmp != 0);
3972 // goto L_no_such_interface // Not found.
3973 Label L_scan_holder;
3974 bind(L_scan_holder);
3975 movptr(temp_itbl_klass, Address(scan_temp, 0));
3976 addptr(scan_temp, scan_step);
3977 cmpptr(holder_klass, temp_itbl_klass);
3978 jccb(Assembler::equal, L_holder_found);
3979 testptr(temp_itbl_klass, temp_itbl_klass);
3980 jccb(Assembler::notZero, L_scan_holder);
3981
3982 jmpb(L_no_such_interface);
3983
3984 // Loop: Look for resolved_class record in itable
3985 // do {
3986 // tmp = itable[index];
3987 // index += step;
3988 // if (tmp == holder_klass) {
3989 // // Also check if we have met a holder klass
3990 // holder_tmp = itable[index-step-ioffset];
3991 // }
3992 // if (tmp == resolved_klass) {
3993 // goto L_resolved_found; // Found!
3994 // }
3995 // } while (tmp != 0);
3996 // goto L_no_such_interface // Not found.
3997 //
3998 Label L_loop_scan_resolved;
3999 bind(L_loop_scan_resolved);
4000 movptr(temp_itbl_klass, Address(scan_temp, 0));
4001 addptr(scan_temp, scan_step);
4002 bind(L_loop_scan_resolved_entry);
4003 cmpptr(holder_klass, temp_itbl_klass);
4004 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4005 cmpptr(resolved_klass, temp_itbl_klass);
4006 jccb(Assembler::equal, L_resolved_found);
4007 testptr(temp_itbl_klass, temp_itbl_klass);
4008 jccb(Assembler::notZero, L_loop_scan_resolved);
4009
4010 jmpb(L_no_such_interface);
4011
4012 Label L_ready;
4013
4014 // See if we already have a holder klass. If not, go and scan for it.
4015 bind(L_resolved_found);
4016 testptr(temp_reg, temp_reg);
4017 jccb(Assembler::zero, L_scan_holder);
4018 jmpb(L_ready);
4019
4020 bind(L_holder_found);
4021 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4022
4023 // Finally, temp_reg contains holder_klass vtable offset
4024 bind(L_ready);
4025 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4026 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4027 load_klass(scan_temp, receiver, noreg);
4028 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4029 } else {
4030 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4031 }
4032 }
4033
4034
4035 // virtual method calling
4036 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4037 RegisterOrConstant vtable_index,
4038 Register method_result) {
4039 const ByteSize base = Klass::vtable_start_offset();
4040 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4041 Address vtable_entry_addr(recv_klass,
4042 vtable_index, Address::times_ptr,
4043 base + vtableEntry::method_offset());
4044 movptr(method_result, vtable_entry_addr);
4045 }
4046
4047
4048 void MacroAssembler::check_klass_subtype(Register sub_klass,
4049 Register super_klass,
4050 Register temp_reg,
4051 Label& L_success) {
4052 Label L_failure;
4053 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4054 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4055 bind(L_failure);
4056 }
4057
4058
4059 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4060 Register super_klass,
4061 Register temp_reg,
4062 Label* L_success,
4063 Label* L_failure,
4064 Label* L_slow_path,
4065 RegisterOrConstant super_check_offset) {
4066 assert_different_registers(sub_klass, super_klass, temp_reg);
4067 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4068 if (super_check_offset.is_register()) {
4069 assert_different_registers(sub_klass, super_klass,
4070 super_check_offset.as_register());
4071 } else if (must_load_sco) {
4072 assert(temp_reg != noreg, "supply either a temp or a register offset");
4073 }
4074
4075 Label L_fallthrough;
4076 int label_nulls = 0;
4077 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4078 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4079 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4080 assert(label_nulls <= 1, "at most one null in the batch");
4081
4082 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4083 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4084 Address super_check_offset_addr(super_klass, sco_offset);
4085
4086 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4087 // range of a jccb. If this routine grows larger, reconsider at
4088 // least some of these.
4089 #define local_jcc(assembler_cond, label) \
4090 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4091 else jcc( assembler_cond, label) /*omit semi*/
4092
4093 // Hacked jmp, which may only be used just before L_fallthrough.
4094 #define final_jmp(label) \
4095 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4096 else jmp(label) /*omit semi*/
4097
4098 // If the pointers are equal, we are done (e.g., String[] elements).
4099 // This self-check enables sharing of secondary supertype arrays among
4100 // non-primary types such as array-of-interface. Otherwise, each such
4101 // type would need its own customized SSA.
4102 // We move this check to the front of the fast path because many
4103 // type checks are in fact trivially successful in this manner,
4104 // so we get a nicely predicted branch right at the start of the check.
4105 cmpptr(sub_klass, super_klass);
4106 local_jcc(Assembler::equal, *L_success);
4107
4108 // Check the supertype display:
4109 if (must_load_sco) {
4110 // Positive movl does right thing on LP64.
4111 movl(temp_reg, super_check_offset_addr);
4112 super_check_offset = RegisterOrConstant(temp_reg);
4113 }
4114 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4115 cmpptr(super_klass, super_check_addr); // load displayed supertype
4116
4117 // This check has worked decisively for primary supers.
4118 // Secondary supers are sought in the super_cache ('super_cache_addr').
4119 // (Secondary supers are interfaces and very deeply nested subtypes.)
4120 // This works in the same check above because of a tricky aliasing
4121 // between the super_cache and the primary super display elements.
4122 // (The 'super_check_addr' can address either, as the case requires.)
4123 // Note that the cache is updated below if it does not help us find
4124 // what we need immediately.
4125 // So if it was a primary super, we can just fail immediately.
4126 // Otherwise, it's the slow path for us (no success at this point).
4127
4128 if (super_check_offset.is_register()) {
4129 local_jcc(Assembler::equal, *L_success);
4130 cmpl(super_check_offset.as_register(), sc_offset);
4131 if (L_failure == &L_fallthrough) {
4132 local_jcc(Assembler::equal, *L_slow_path);
4133 } else {
4134 local_jcc(Assembler::notEqual, *L_failure);
4135 final_jmp(*L_slow_path);
4136 }
4137 } else if (super_check_offset.as_constant() == sc_offset) {
4138 // Need a slow path; fast failure is impossible.
4139 if (L_slow_path == &L_fallthrough) {
4140 local_jcc(Assembler::equal, *L_success);
4141 } else {
4142 local_jcc(Assembler::notEqual, *L_slow_path);
4143 final_jmp(*L_success);
4144 }
4145 } else {
4146 // No slow path; it's a fast decision.
4147 if (L_failure == &L_fallthrough) {
4148 local_jcc(Assembler::equal, *L_success);
4149 } else {
4150 local_jcc(Assembler::notEqual, *L_failure);
4151 final_jmp(*L_success);
4152 }
4153 }
4154
4155 bind(L_fallthrough);
4156
4157 #undef local_jcc
4158 #undef final_jmp
4159 }
4160
4161
4162 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4163 Register super_klass,
4164 Register temp_reg,
4165 Register temp2_reg,
4166 Label* L_success,
4167 Label* L_failure,
4168 bool set_cond_codes) {
4169 assert_different_registers(sub_klass, super_klass, temp_reg);
4170 if (temp2_reg != noreg)
4171 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4172 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4173
4174 Label L_fallthrough;
4175 int label_nulls = 0;
4176 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4177 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4178 assert(label_nulls <= 1, "at most one null in the batch");
4179
4180 // a couple of useful fields in sub_klass:
4181 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4182 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4183 Address secondary_supers_addr(sub_klass, ss_offset);
4184 Address super_cache_addr( sub_klass, sc_offset);
4185
4186 // Do a linear scan of the secondary super-klass chain.
4187 // This code is rarely used, so simplicity is a virtue here.
4188 // The repne_scan instruction uses fixed registers, which we must spill.
4189 // Don't worry too much about pre-existing connections with the input regs.
4190
4191 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4192 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4193
4194 // Get super_klass value into rax (even if it was in rdi or rcx).
4195 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4196 if (super_klass != rax) {
4197 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4198 mov(rax, super_klass);
4199 }
4200 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4201 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4202
4203 #ifndef PRODUCT
4204 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4205 ExternalAddress pst_counter_addr((address) pst_counter);
4206 lea(rcx, pst_counter_addr);
4207 incrementl(Address(rcx, 0));
4208 #endif //PRODUCT
4209
4210 // We will consult the secondary-super array.
4211 movptr(rdi, secondary_supers_addr);
4212 // Load the array length. (Positive movl does right thing on LP64.)
4213 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4214 // Skip to start of data.
4215 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4216
4217 // Scan RCX words at [RDI] for an occurrence of RAX.
4218 // Set NZ/Z based on last compare.
4219 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4220 // not change flags (only scas instruction which is repeated sets flags).
4221 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4222
4223 testptr(rax,rax); // Set Z = 0
4224 repne_scan();
4225
4226 // Unspill the temp. registers:
4227 if (pushed_rdi) pop(rdi);
4228 if (pushed_rcx) pop(rcx);
4229 if (pushed_rax) pop(rax);
4230
4231 if (set_cond_codes) {
4232 // Special hack for the AD files: rdi is guaranteed non-zero.
4233 assert(!pushed_rdi, "rdi must be left non-null");
4234 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4235 }
4236
4237 if (L_failure == &L_fallthrough)
4238 jccb(Assembler::notEqual, *L_failure);
4239 else jcc(Assembler::notEqual, *L_failure);
4240
4241 // Success. Cache the super we found and proceed in triumph.
4242 movptr(super_cache_addr, super_klass);
4243
4244 if (L_success != &L_fallthrough) {
4245 jmp(*L_success);
4246 }
4247
4248 #undef IS_A_TEMP
4249
4250 bind(L_fallthrough);
4251 }
4252
4253 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4254 Register super_klass,
4255 Register temp_reg,
4256 Register temp2_reg,
4257 Label* L_success,
4258 Label* L_failure,
4259 bool set_cond_codes) {
4260 assert(set_cond_codes == false, "must be false on 64-bit x86");
4261 check_klass_subtype_slow_path
4262 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4263 L_success, L_failure);
4264 }
4265
4266 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4267 Register super_klass,
4268 Register temp_reg,
4269 Register temp2_reg,
4270 Register temp3_reg,
4271 Register temp4_reg,
4272 Label* L_success,
4273 Label* L_failure) {
4274 if (UseSecondarySupersTable) {
4275 check_klass_subtype_slow_path_table
4276 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4277 L_success, L_failure);
4278 } else {
4279 check_klass_subtype_slow_path_linear
4280 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4281 }
4282 }
4283
4284 Register MacroAssembler::allocate_if_noreg(Register r,
4285 RegSetIterator<Register> &available_regs,
4286 RegSet ®s_to_push) {
4287 if (!r->is_valid()) {
4288 r = *available_regs++;
4289 regs_to_push += r;
4290 }
4291 return r;
4292 }
4293
4294 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4295 Register super_klass,
4296 Register temp_reg,
4297 Register temp2_reg,
4298 Register temp3_reg,
4299 Register result_reg,
4300 Label* L_success,
4301 Label* L_failure) {
4302 // NB! Callers may assume that, when temp2_reg is a valid register,
4303 // this code sets it to a nonzero value.
4304 bool temp2_reg_was_valid = temp2_reg->is_valid();
4305
4306 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4307
4308 Label L_fallthrough;
4309 int label_nulls = 0;
4310 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4311 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4312 assert(label_nulls <= 1, "at most one null in the batch");
4313
4314 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4315
4316 RegSetIterator<Register> available_regs
4317 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4318
4319 RegSet pushed_regs;
4320
4321 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4322 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4323 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4324 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4325 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4326
4327 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4328
4329 {
4330
4331 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4332 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4333 subptr(rsp, aligned_size);
4334 push_set(pushed_regs, 0);
4335
4336 lookup_secondary_supers_table_var(sub_klass,
4337 super_klass,
4338 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4339 cmpq(result_reg, 0);
4340
4341 // Unspill the temp. registers:
4342 pop_set(pushed_regs, 0);
4343 // Increment SP but do not clobber flags.
4344 lea(rsp, Address(rsp, aligned_size));
4345 }
4346
4347 if (temp2_reg_was_valid) {
4348 movq(temp2_reg, 1);
4349 }
4350
4351 jcc(Assembler::notEqual, *L_failure);
4352
4353 if (L_success != &L_fallthrough) {
4354 jmp(*L_success);
4355 }
4356
4357 bind(L_fallthrough);
4358 }
4359
4360 // population_count variant for running without the POPCNT
4361 // instruction, which was introduced with SSE4.2 in 2008.
4362 void MacroAssembler::population_count(Register dst, Register src,
4363 Register scratch1, Register scratch2) {
4364 assert_different_registers(src, scratch1, scratch2);
4365 if (UsePopCountInstruction) {
4366 Assembler::popcntq(dst, src);
4367 } else {
4368 assert_different_registers(src, scratch1, scratch2);
4369 assert_different_registers(dst, scratch1, scratch2);
4370 Label loop, done;
4371
4372 mov(scratch1, src);
4373 // dst = 0;
4374 // while(scratch1 != 0) {
4375 // dst++;
4376 // scratch1 &= (scratch1 - 1);
4377 // }
4378 xorl(dst, dst);
4379 testq(scratch1, scratch1);
4380 jccb(Assembler::equal, done);
4381 {
4382 bind(loop);
4383 incq(dst);
4384 movq(scratch2, scratch1);
4385 decq(scratch2);
4386 andq(scratch1, scratch2);
4387 jccb(Assembler::notEqual, loop);
4388 }
4389 bind(done);
4390 }
4391 #ifdef ASSERT
4392 mov64(scratch1, 0xCafeBabeDeadBeef);
4393 movq(scratch2, scratch1);
4394 #endif
4395 }
4396
4397 // Ensure that the inline code and the stub are using the same registers.
4398 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4399 do { \
4400 assert(r_super_klass == rax, "mismatch"); \
4401 assert(r_array_base == rbx, "mismatch"); \
4402 assert(r_array_length == rcx, "mismatch"); \
4403 assert(r_array_index == rdx, "mismatch"); \
4404 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4405 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4406 assert(result == rdi || result == noreg, "mismatch"); \
4407 } while(0)
4408
4409 // Versions of salq and rorq that don't need count to be in rcx
4410
4411 void MacroAssembler::salq(Register dest, Register count) {
4412 if (count == rcx) {
4413 Assembler::salq(dest);
4414 } else {
4415 assert_different_registers(rcx, dest);
4416 xchgq(rcx, count);
4417 Assembler::salq(dest);
4418 xchgq(rcx, count);
4419 }
4420 }
4421
4422 void MacroAssembler::rorq(Register dest, Register count) {
4423 if (count == rcx) {
4424 Assembler::rorq(dest);
4425 } else {
4426 assert_different_registers(rcx, dest);
4427 xchgq(rcx, count);
4428 Assembler::rorq(dest);
4429 xchgq(rcx, count);
4430 }
4431 }
4432
4433 // Return true: we succeeded in generating this code
4434 //
4435 // At runtime, return 0 in result if r_super_klass is a superclass of
4436 // r_sub_klass, otherwise return nonzero. Use this if you know the
4437 // super_klass_slot of the class you're looking for. This is always
4438 // the case for instanceof and checkcast.
4439 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4440 Register r_super_klass,
4441 Register temp1,
4442 Register temp2,
4443 Register temp3,
4444 Register temp4,
4445 Register result,
4446 u1 super_klass_slot) {
4447 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4448
4449 Label L_fallthrough, L_success, L_failure;
4450
4451 BLOCK_COMMENT("lookup_secondary_supers_table {");
4452
4453 const Register
4454 r_array_index = temp1,
4455 r_array_length = temp2,
4456 r_array_base = temp3,
4457 r_bitmap = temp4;
4458
4459 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4460
4461 xorq(result, result); // = 0
4462
4463 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4464 movq(r_array_index, r_bitmap);
4465
4466 // First check the bitmap to see if super_klass might be present. If
4467 // the bit is zero, we are certain that super_klass is not one of
4468 // the secondary supers.
4469 u1 bit = super_klass_slot;
4470 {
4471 // NB: If the count in a x86 shift instruction is 0, the flags are
4472 // not affected, so we do a testq instead.
4473 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4474 if (shift_count != 0) {
4475 salq(r_array_index, shift_count);
4476 } else {
4477 testq(r_array_index, r_array_index);
4478 }
4479 }
4480 // We test the MSB of r_array_index, i.e. its sign bit
4481 jcc(Assembler::positive, L_failure);
4482
4483 // Get the first array index that can contain super_klass into r_array_index.
4484 if (bit != 0) {
4485 population_count(r_array_index, r_array_index, temp2, temp3);
4486 } else {
4487 movl(r_array_index, 1);
4488 }
4489 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4490
4491 // We will consult the secondary-super array.
4492 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4493
4494 // We're asserting that the first word in an Array<Klass*> is the
4495 // length, and the second word is the first word of the data. If
4496 // that ever changes, r_array_base will have to be adjusted here.
4497 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4498 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4499
4500 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4501 jccb(Assembler::equal, L_success);
4502
4503 // Is there another entry to check? Consult the bitmap.
4504 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4505 jccb(Assembler::carryClear, L_failure);
4506
4507 // Linear probe. Rotate the bitmap so that the next bit to test is
4508 // in Bit 1.
4509 if (bit != 0) {
4510 rorq(r_bitmap, bit);
4511 }
4512
4513 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4514 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4515 // Kills: r_array_length.
4516 // Returns: result.
4517 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4518 // Result (0/1) is in rdi
4519 jmpb(L_fallthrough);
4520
4521 bind(L_failure);
4522 incq(result); // 0 => 1
4523
4524 bind(L_success);
4525 // result = 0;
4526
4527 bind(L_fallthrough);
4528 BLOCK_COMMENT("} lookup_secondary_supers_table");
4529
4530 if (VerifySecondarySupers) {
4531 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4532 temp1, temp2, temp3);
4533 }
4534 }
4535
4536 // At runtime, return 0 in result if r_super_klass is a superclass of
4537 // r_sub_klass, otherwise return nonzero. Use this version of
4538 // lookup_secondary_supers_table() if you don't know ahead of time
4539 // which superclass will be searched for. Used by interpreter and
4540 // runtime stubs. It is larger and has somewhat greater latency than
4541 // the version above, which takes a constant super_klass_slot.
4542 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
4543 Register r_super_klass,
4544 Register temp1,
4545 Register temp2,
4546 Register temp3,
4547 Register temp4,
4548 Register result) {
4549 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4550 assert_different_registers(r_sub_klass, r_super_klass, rcx);
4551 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
4552
4553 Label L_fallthrough, L_success, L_failure;
4554
4555 BLOCK_COMMENT("lookup_secondary_supers_table {");
4556
4557 RegSetIterator<Register> available_regs = (temps - rcx).begin();
4558
4559 // FIXME. Once we are sure that all paths reaching this point really
4560 // do pass rcx as one of our temps we can get rid of the following
4561 // workaround.
4562 assert(temps.contains(rcx), "fix this code");
4563
4564 // We prefer to have our shift count in rcx. If rcx is one of our
4565 // temps, use it for slot. If not, pick any of our temps.
4566 Register slot;
4567 if (!temps.contains(rcx)) {
4568 slot = *available_regs++;
4569 } else {
4570 slot = rcx;
4571 }
4572
4573 const Register r_array_index = *available_regs++;
4574 const Register r_bitmap = *available_regs++;
4575
4576 // The logic above guarantees this property, but we state it here.
4577 assert_different_registers(r_array_index, r_bitmap, rcx);
4578
4579 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4580 movq(r_array_index, r_bitmap);
4581
4582 // First check the bitmap to see if super_klass might be present. If
4583 // the bit is zero, we are certain that super_klass is not one of
4584 // the secondary supers.
4585 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4586 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
4587 salq(r_array_index, slot);
4588
4589 testq(r_array_index, r_array_index);
4590 // We test the MSB of r_array_index, i.e. its sign bit
4591 jcc(Assembler::positive, L_failure);
4592
4593 const Register r_array_base = *available_regs++;
4594
4595 // Get the first array index that can contain super_klass into r_array_index.
4596 // Note: Clobbers r_array_base and slot.
4597 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
4598
4599 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4600
4601 // We will consult the secondary-super array.
4602 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4603
4604 // We're asserting that the first word in an Array<Klass*> is the
4605 // length, and the second word is the first word of the data. If
4606 // that ever changes, r_array_base will have to be adjusted here.
4607 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4608 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4609
4610 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4611 jccb(Assembler::equal, L_success);
4612
4613 // Restore slot to its true value
4614 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4615
4616 // Linear probe. Rotate the bitmap so that the next bit to test is
4617 // in Bit 1.
4618 rorq(r_bitmap, slot);
4619
4620 // Is there another entry to check? Consult the bitmap.
4621 btq(r_bitmap, 1);
4622 jccb(Assembler::carryClear, L_failure);
4623
4624 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4625 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4626 // Kills: r_array_length.
4627 // Returns: result.
4628 lookup_secondary_supers_table_slow_path(r_super_klass,
4629 r_array_base,
4630 r_array_index,
4631 r_bitmap,
4632 /*temp1*/result,
4633 /*temp2*/slot,
4634 &L_success,
4635 nullptr);
4636
4637 bind(L_failure);
4638 movq(result, 1);
4639 jmpb(L_fallthrough);
4640
4641 bind(L_success);
4642 xorq(result, result); // = 0
4643
4644 bind(L_fallthrough);
4645 BLOCK_COMMENT("} lookup_secondary_supers_table");
4646
4647 if (VerifySecondarySupers) {
4648 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4649 temp1, temp2, temp3);
4650 }
4651 }
4652
4653 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4654 Label* L_success, Label* L_failure) {
4655 Label L_loop, L_fallthrough;
4656 {
4657 int label_nulls = 0;
4658 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4659 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4660 assert(label_nulls <= 1, "at most one null in the batch");
4661 }
4662 bind(L_loop);
4663 cmpq(value, Address(addr, count, Address::times_8));
4664 jcc(Assembler::equal, *L_success);
4665 addl(count, 1);
4666 cmpl(count, limit);
4667 jcc(Assembler::less, L_loop);
4668
4669 if (&L_fallthrough != L_failure) {
4670 jmp(*L_failure);
4671 }
4672 bind(L_fallthrough);
4673 }
4674
4675 // Called by code generated by check_klass_subtype_slow_path
4676 // above. This is called when there is a collision in the hashed
4677 // lookup in the secondary supers array.
4678 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4679 Register r_array_base,
4680 Register r_array_index,
4681 Register r_bitmap,
4682 Register temp1,
4683 Register temp2,
4684 Label* L_success,
4685 Label* L_failure) {
4686 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4687
4688 const Register
4689 r_array_length = temp1,
4690 r_sub_klass = noreg,
4691 result = noreg;
4692
4693 Label L_fallthrough;
4694 int label_nulls = 0;
4695 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4696 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4697 assert(label_nulls <= 1, "at most one null in the batch");
4698
4699 // Load the array length.
4700 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4701 // And adjust the array base to point to the data.
4702 // NB! Effectively increments current slot index by 1.
4703 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4704 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4705
4706 // Linear probe
4707 Label L_huge;
4708
4709 // The bitmap is full to bursting.
4710 // Implicit invariant: BITMAP_FULL implies (length > 0)
4711 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
4712 jcc(Assembler::greater, L_huge);
4713
4714 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4715 // current slot (at secondary_supers[r_array_index]) has not yet
4716 // been inspected, and r_array_index may be out of bounds if we
4717 // wrapped around the end of the array.
4718
4719 { // This is conventional linear probing, but instead of terminating
4720 // when a null entry is found in the table, we maintain a bitmap
4721 // in which a 0 indicates missing entries.
4722 // The check above guarantees there are 0s in the bitmap, so the loop
4723 // eventually terminates.
4724
4725 xorl(temp2, temp2); // = 0;
4726
4727 Label L_again;
4728 bind(L_again);
4729
4730 // Check for array wraparound.
4731 cmpl(r_array_index, r_array_length);
4732 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4733
4734 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4735 jcc(Assembler::equal, *L_success);
4736
4737 // If the next bit in bitmap is zero, we're done.
4738 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4739 jcc(Assembler::carryClear, *L_failure);
4740
4741 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4742 addl(r_array_index, 1);
4743
4744 jmp(L_again);
4745 }
4746
4747 { // Degenerate case: more than 64 secondary supers.
4748 // FIXME: We could do something smarter here, maybe a vectorized
4749 // comparison or a binary search, but is that worth any added
4750 // complexity?
4751 bind(L_huge);
4752 xorl(r_array_index, r_array_index); // = 0
4753 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4754 L_success,
4755 (&L_fallthrough != L_failure ? L_failure : nullptr));
4756
4757 bind(L_fallthrough);
4758 }
4759 }
4760
4761 struct VerifyHelperArguments {
4762 Klass* _super;
4763 Klass* _sub;
4764 intptr_t _linear_result;
4765 intptr_t _table_result;
4766 };
4767
4768 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
4769 Klass::on_secondary_supers_verification_failure(args->_super,
4770 args->_sub,
4771 args->_linear_result,
4772 args->_table_result,
4773 msg);
4774 }
4775
4776 // Make sure that the hashed lookup and a linear scan agree.
4777 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
4778 Register r_super_klass,
4779 Register result,
4780 Register temp1,
4781 Register temp2,
4782 Register temp3) {
4783 const Register
4784 r_array_index = temp1,
4785 r_array_length = temp2,
4786 r_array_base = temp3,
4787 r_bitmap = noreg;
4788
4789 BLOCK_COMMENT("verify_secondary_supers_table {");
4790
4791 Label L_success, L_failure, L_check, L_done;
4792
4793 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4794 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4795 // And adjust the array base to point to the data.
4796 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4797
4798 testl(r_array_length, r_array_length); // array_length == 0?
4799 jcc(Assembler::zero, L_failure);
4800
4801 movl(r_array_index, 0);
4802 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
4803 // fall through to L_failure
4804
4805 const Register linear_result = r_array_index; // reuse temp1
4806
4807 bind(L_failure); // not present
4808 movl(linear_result, 1);
4809 jmp(L_check);
4810
4811 bind(L_success); // present
4812 movl(linear_result, 0);
4813
4814 bind(L_check);
4815 cmpl(linear_result, result);
4816 jcc(Assembler::equal, L_done);
4817
4818 { // To avoid calling convention issues, build a record on the stack
4819 // and pass the pointer to that instead.
4820 push(result);
4821 push(linear_result);
4822 push(r_sub_klass);
4823 push(r_super_klass);
4824 movptr(c_rarg1, rsp);
4825 movptr(c_rarg0, (uintptr_t) "mismatch");
4826 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
4827 should_not_reach_here();
4828 }
4829 bind(L_done);
4830
4831 BLOCK_COMMENT("} verify_secondary_supers_table");
4832 }
4833
4834 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
4835
4836 void MacroAssembler::clinit_barrier(Register klass, Label* L_fast_path, Label* L_slow_path) {
4837 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
4838
4839 Label L_fallthrough;
4840 if (L_fast_path == nullptr) {
4841 L_fast_path = &L_fallthrough;
4842 } else if (L_slow_path == nullptr) {
4843 L_slow_path = &L_fallthrough;
4844 }
4845
4846 // Fast path check: class is fully initialized.
4847 // init_state needs acquire, but x86 is TSO, and so we are already good.
4848 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4849 jcc(Assembler::equal, *L_fast_path);
4850
4851 // Fast path check: current thread is initializer thread
4852 cmpptr(r15_thread, Address(klass, InstanceKlass::init_thread_offset()));
4853 if (L_slow_path == &L_fallthrough) {
4854 jcc(Assembler::equal, *L_fast_path);
4855 bind(*L_slow_path);
4856 } else if (L_fast_path == &L_fallthrough) {
4857 jcc(Assembler::notEqual, *L_slow_path);
4858 bind(*L_fast_path);
4859 } else {
4860 Unimplemented();
4861 }
4862 }
4863
4864 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4865 if (VM_Version::supports_cmov()) {
4866 cmovl(cc, dst, src);
4867 } else {
4868 Label L;
4869 jccb(negate_condition(cc), L);
4870 movl(dst, src);
4871 bind(L);
4872 }
4873 }
4874
4875 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4876 if (VM_Version::supports_cmov()) {
4877 cmovl(cc, dst, src);
4878 } else {
4879 Label L;
4880 jccb(negate_condition(cc), L);
4881 movl(dst, src);
4882 bind(L);
4883 }
4884 }
4885
4886 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4887 if (!VerifyOops || VerifyAdapterSharing) {
4888 // Below address of the code string confuses VerifyAdapterSharing
4889 // because it may differ between otherwise equivalent adapters.
4890 return;
4891 }
4892
4893 BLOCK_COMMENT("verify_oop {");
4894 push(rscratch1);
4895 push(rax); // save rax
4896 push(reg); // pass register argument
4897
4898 // Pass register number to verify_oop_subroutine
4899 const char* b = nullptr;
4900 {
4901 ResourceMark rm;
4902 stringStream ss;
4903 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4904 b = code_string(ss.as_string());
4905 }
4906 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
4907 pushptr(buffer.addr(), rscratch1);
4908
4909 // call indirectly to solve generation ordering problem
4910 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4911 call(rax);
4912 // Caller pops the arguments (oop, message) and restores rax, r10
4913 BLOCK_COMMENT("} verify_oop");
4914 }
4915
4916 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4917 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4918 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
4919 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
4920 vpternlogd(dst, 0xFF, dst, dst, vector_len);
4921 } else if (VM_Version::supports_avx()) {
4922 vpcmpeqd(dst, dst, dst, vector_len);
4923 } else {
4924 pcmpeqd(dst, dst);
4925 }
4926 }
4927
4928 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4929 int extra_slot_offset) {
4930 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4931 int stackElementSize = Interpreter::stackElementSize;
4932 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4933 #ifdef ASSERT
4934 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4935 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4936 #endif
4937 Register scale_reg = noreg;
4938 Address::ScaleFactor scale_factor = Address::no_scale;
4939 if (arg_slot.is_constant()) {
4940 offset += arg_slot.as_constant() * stackElementSize;
4941 } else {
4942 scale_reg = arg_slot.as_register();
4943 scale_factor = Address::times(stackElementSize);
4944 }
4945 offset += wordSize; // return PC is on stack
4946 return Address(rsp, scale_reg, scale_factor, offset);
4947 }
4948
4949 // Handle the receiver type profile update given the "recv" klass.
4950 //
4951 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
4952 // If there are no matching or claimable receiver entries in RD, updates
4953 // the polymorphic counter.
4954 //
4955 // This code expected to run by either the interpreter or JIT-ed code, without
4956 // extra synchronization. For safety, receiver cells are claimed atomically, which
4957 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
4958 // counter updates are not atomic.
4959 //
4960 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
4961 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
4962 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
4963 int poly_count_offset = in_bytes(CounterData::count_offset());
4964 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
4965 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
4966
4967 // Adjust for MDP offsets. Slots are pointer-sized, so is the global offset.
4968 assert(is_aligned(mdp_offset, BytesPerWord), "sanity");
4969 base_receiver_offset += mdp_offset;
4970 end_receiver_offset += mdp_offset;
4971 poly_count_offset += mdp_offset;
4972
4973 // Scale down to optimize encoding. Slots are pointer-sized.
4974 assert(is_aligned(base_receiver_offset, BytesPerWord), "sanity");
4975 assert(is_aligned(end_receiver_offset, BytesPerWord), "sanity");
4976 assert(is_aligned(poly_count_offset, BytesPerWord), "sanity");
4977 assert(is_aligned(receiver_step, BytesPerWord), "sanity");
4978 assert(is_aligned(receiver_to_count_step, BytesPerWord), "sanity");
4979 base_receiver_offset >>= LogBytesPerWord;
4980 end_receiver_offset >>= LogBytesPerWord;
4981 poly_count_offset >>= LogBytesPerWord;
4982 receiver_step >>= LogBytesPerWord;
4983 receiver_to_count_step >>= LogBytesPerWord;
4984
4985 #ifdef ASSERT
4986 // We are about to walk the MDO slots without asking for offsets.
4987 // Check that our math hits all the right spots.
4988 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
4989 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
4990 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
4991 int offset = base_receiver_offset + receiver_step*c;
4992 int count_offset = offset + receiver_to_count_step;
4993 assert((offset << LogBytesPerWord) == real_recv_offset, "receiver slot math");
4994 assert((count_offset << LogBytesPerWord) == real_count_offset, "receiver count math");
4995 }
4996 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
4997 assert(poly_count_offset << LogBytesPerWord == real_poly_count_offset, "poly counter math");
4998 #endif
4999
5000 // Corner case: no profile table. Increment poly counter and exit.
5001 if (ReceiverTypeData::row_limit() == 0) {
5002 addptr(Address(mdp, poly_count_offset, Address::times_ptr), DataLayout::counter_increment);
5003 return;
5004 }
5005
5006 Register offset = rscratch1;
5007
5008 Label L_loop_search_receiver, L_loop_search_empty;
5009 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
5010
5011 // The code here recognizes three major cases:
5012 // A. Fastest: receiver found in the table
5013 // B. Fast: no receiver in the table, and the table is full
5014 // C. Slow: no receiver in the table, free slots in the table
5015 //
5016 // The case A performance is most important, as perfectly-behaved code would end up
5017 // there, especially with larger TypeProfileWidth. The case B performance is
5018 // important as well, this is where bulk of code would land for normally megamorphic
5019 // cases. The case C performance is not essential, its job is to deal with installation
5020 // races, we optimize for code density instead. Case C needs to make sure that receiver
5021 // rows are only claimed once. This makes sure we never overwrite a row for another
5022 // receiver and never duplicate the receivers in the list, making profile type-accurate.
5023 //
5024 // It is very tempting to handle these cases in a single loop, and claim the first slot
5025 // without checking the rest of the table. But, profiling code should tolerate free slots
5026 // in the table, as class unloading can clear them. After such cleanup, the receiver
5027 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
5028 // to complete, before trying to install new slots. Splitting the code in several tight
5029 // loops also helpfully optimizes for cases A and B.
5030 //
5031 // This code is effectively:
5032 //
5033 // restart:
5034 // // Fastest: receiver is already installed
5035 // for (i = 0; i < receiver_count(); i++) {
5036 // if (receiver(i) == recv) goto found_recv(i);
5037 // }
5038 //
5039 // // Fast: no receiver, but profile is full
5040 // for (i = 0; i < receiver_count(); i++) {
5041 // if (receiver(i) == null) goto found_null(i);
5042 // }
5043 // goto polymorphic
5044 //
5045 // // Slow: try to install receiver
5046 // found_null(i):
5047 // CAS(&receiver(i), null, recv);
5048 // goto restart
5049 //
5050 // polymorphic:
5051 // count++;
5052 // return
5053 //
5054 // found_recv(i):
5055 // *receiver_count(i)++
5056 //
5057
5058 bind(L_restart);
5059
5060 // Fastest: receiver is already installed
5061 movptr(offset, base_receiver_offset);
5062 bind(L_loop_search_receiver);
5063 cmpptr(recv, Address(mdp, offset, Address::times_ptr));
5064 jccb(Assembler::equal, L_found_recv);
5065 addptr(offset, receiver_step);
5066 cmpptr(offset, end_receiver_offset);
5067 jccb(Assembler::notEqual, L_loop_search_receiver);
5068
5069 // Fast: no receiver, but profile is full
5070 movptr(offset, base_receiver_offset);
5071 bind(L_loop_search_empty);
5072 cmpptr(Address(mdp, offset, Address::times_ptr), NULL_WORD);
5073 jccb(Assembler::equal, L_found_empty);
5074 addptr(offset, receiver_step);
5075 cmpptr(offset, end_receiver_offset);
5076 jccb(Assembler::notEqual, L_loop_search_empty);
5077 jmpb(L_polymorphic);
5078
5079 // Slow: try to install receiver
5080 bind(L_found_empty);
5081
5082 // Atomically swing receiver slot: null -> recv.
5083 //
5084 // The update code uses CAS, which wants RAX register specifically, *and* it needs
5085 // other important registers untouched, as they form the address. Therefore, we need
5086 // to shift any important registers from RAX into some other spare register. If we
5087 // have a spare register, we are forced to save it on stack here.
5088
5089 Register spare_reg = noreg;
5090 Register shifted_mdp = mdp;
5091 Register shifted_recv = recv;
5092 if (recv == rax || mdp == rax) {
5093 spare_reg = (recv != rbx && mdp != rbx) ? rbx :
5094 (recv != rcx && mdp != rcx) ? rcx :
5095 rdx;
5096 assert_different_registers(mdp, recv, offset, spare_reg);
5097
5098 push(spare_reg);
5099 if (recv == rax) {
5100 movptr(spare_reg, recv);
5101 shifted_recv = spare_reg;
5102 } else {
5103 assert(mdp == rax, "Remaining case");
5104 movptr(spare_reg, mdp);
5105 shifted_mdp = spare_reg;
5106 }
5107 } else {
5108 push(rax);
5109 }
5110
5111 // None of the important registers are in RAX after this shuffle.
5112 assert_different_registers(rax, shifted_mdp, shifted_recv, offset);
5113
5114 xorptr(rax, rax);
5115 cmpxchgptr(shifted_recv, Address(shifted_mdp, offset, Address::times_ptr));
5116
5117 // Unshift registers.
5118 if (recv == rax || mdp == rax) {
5119 movptr(rax, spare_reg);
5120 pop(spare_reg);
5121 } else {
5122 pop(rax);
5123 }
5124
5125 // CAS success means the slot now has the receiver we want. CAS failure means
5126 // something had claimed the slot concurrently: it can be the same receiver we want,
5127 // or something else. Since this is a slow path, we can optimize for code density,
5128 // and just restart the search from the beginning.
5129 jmpb(L_restart);
5130
5131 // Counter updates:
5132
5133 // Increment polymorphic counter instead of receiver slot.
5134 bind(L_polymorphic);
5135 movptr(offset, poly_count_offset);
5136 jmpb(L_count_update);
5137
5138 // Found a receiver, convert its slot offset to corresponding count offset.
5139 bind(L_found_recv);
5140 addptr(offset, receiver_to_count_step);
5141
5142 bind(L_count_update);
5143 addptr(Address(mdp, offset, Address::times_ptr), DataLayout::counter_increment);
5144 }
5145
5146 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5147 if (!VerifyOops || VerifyAdapterSharing) {
5148 // Below address of the code string confuses VerifyAdapterSharing
5149 // because it may differ between otherwise equivalent adapters.
5150 return;
5151 }
5152
5153 push(rscratch1);
5154 push(rax); // save rax,
5155 // addr may contain rsp so we will have to adjust it based on the push
5156 // we just did (and on 64 bit we do two pushes)
5157 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5158 // stores rax into addr which is backwards of what was intended.
5159 if (addr.uses(rsp)) {
5160 lea(rax, addr);
5161 pushptr(Address(rax, 2 * BytesPerWord));
5162 } else {
5163 pushptr(addr);
5164 }
5165
5166 // Pass register number to verify_oop_subroutine
5167 const char* b = nullptr;
5168 {
5169 ResourceMark rm;
5170 stringStream ss;
5171 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5172 b = code_string(ss.as_string());
5173 }
5174 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5175 pushptr(buffer.addr(), rscratch1);
5176
5177 // call indirectly to solve generation ordering problem
5178 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5179 call(rax);
5180 // Caller pops the arguments (addr, message) and restores rax, r10.
5181 }
5182
5183 void MacroAssembler::verify_tlab() {
5184 #ifdef ASSERT
5185 if (UseTLAB && VerifyOops) {
5186 Label next, ok;
5187 Register t1 = rsi;
5188
5189 push(t1);
5190
5191 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5192 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
5193 jcc(Assembler::aboveEqual, next);
5194 STOP("assert(top >= start)");
5195 should_not_reach_here();
5196
5197 bind(next);
5198 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
5199 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5200 jcc(Assembler::aboveEqual, ok);
5201 STOP("assert(top <= end)");
5202 should_not_reach_here();
5203
5204 bind(ok);
5205 pop(t1);
5206 }
5207 #endif
5208 }
5209
5210 class ControlWord {
5211 public:
5212 int32_t _value;
5213
5214 int rounding_control() const { return (_value >> 10) & 3 ; }
5215 int precision_control() const { return (_value >> 8) & 3 ; }
5216 bool precision() const { return ((_value >> 5) & 1) != 0; }
5217 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5218 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5219 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5220 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5221 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5222
5223 void print() const {
5224 // rounding control
5225 const char* rc;
5226 switch (rounding_control()) {
5227 case 0: rc = "round near"; break;
5228 case 1: rc = "round down"; break;
5229 case 2: rc = "round up "; break;
5230 case 3: rc = "chop "; break;
5231 default:
5232 rc = nullptr; // silence compiler warnings
5233 fatal("Unknown rounding control: %d", rounding_control());
5234 };
5235 // precision control
5236 const char* pc;
5237 switch (precision_control()) {
5238 case 0: pc = "24 bits "; break;
5239 case 1: pc = "reserved"; break;
5240 case 2: pc = "53 bits "; break;
5241 case 3: pc = "64 bits "; break;
5242 default:
5243 pc = nullptr; // silence compiler warnings
5244 fatal("Unknown precision control: %d", precision_control());
5245 };
5246 // flags
5247 char f[9];
5248 f[0] = ' ';
5249 f[1] = ' ';
5250 f[2] = (precision ()) ? 'P' : 'p';
5251 f[3] = (underflow ()) ? 'U' : 'u';
5252 f[4] = (overflow ()) ? 'O' : 'o';
5253 f[5] = (zero_divide ()) ? 'Z' : 'z';
5254 f[6] = (denormalized()) ? 'D' : 'd';
5255 f[7] = (invalid ()) ? 'I' : 'i';
5256 f[8] = '\x0';
5257 // output
5258 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5259 }
5260
5261 };
5262
5263 class StatusWord {
5264 public:
5265 int32_t _value;
5266
5267 bool busy() const { return ((_value >> 15) & 1) != 0; }
5268 bool C3() const { return ((_value >> 14) & 1) != 0; }
5269 bool C2() const { return ((_value >> 10) & 1) != 0; }
5270 bool C1() const { return ((_value >> 9) & 1) != 0; }
5271 bool C0() const { return ((_value >> 8) & 1) != 0; }
5272 int top() const { return (_value >> 11) & 7 ; }
5273 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5274 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5275 bool precision() const { return ((_value >> 5) & 1) != 0; }
5276 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5277 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5278 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5279 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5280 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5281
5282 void print() const {
5283 // condition codes
5284 char c[5];
5285 c[0] = (C3()) ? '3' : '-';
5286 c[1] = (C2()) ? '2' : '-';
5287 c[2] = (C1()) ? '1' : '-';
5288 c[3] = (C0()) ? '0' : '-';
5289 c[4] = '\x0';
5290 // flags
5291 char f[9];
5292 f[0] = (error_status()) ? 'E' : '-';
5293 f[1] = (stack_fault ()) ? 'S' : '-';
5294 f[2] = (precision ()) ? 'P' : '-';
5295 f[3] = (underflow ()) ? 'U' : '-';
5296 f[4] = (overflow ()) ? 'O' : '-';
5297 f[5] = (zero_divide ()) ? 'Z' : '-';
5298 f[6] = (denormalized()) ? 'D' : '-';
5299 f[7] = (invalid ()) ? 'I' : '-';
5300 f[8] = '\x0';
5301 // output
5302 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5303 }
5304
5305 };
5306
5307 class TagWord {
5308 public:
5309 int32_t _value;
5310
5311 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5312
5313 void print() const {
5314 printf("%04x", _value & 0xFFFF);
5315 }
5316
5317 };
5318
5319 class FPU_Register {
5320 public:
5321 int32_t _m0;
5322 int32_t _m1;
5323 int16_t _ex;
5324
5325 bool is_indefinite() const {
5326 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5327 }
5328
5329 void print() const {
5330 char sign = (_ex < 0) ? '-' : '+';
5331 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5332 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5333 };
5334
5335 };
5336
5337 class FPU_State {
5338 public:
5339 enum {
5340 register_size = 10,
5341 number_of_registers = 8,
5342 register_mask = 7
5343 };
5344
5345 ControlWord _control_word;
5346 StatusWord _status_word;
5347 TagWord _tag_word;
5348 int32_t _error_offset;
5349 int32_t _error_selector;
5350 int32_t _data_offset;
5351 int32_t _data_selector;
5352 int8_t _register[register_size * number_of_registers];
5353
5354 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5355 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5356
5357 const char* tag_as_string(int tag) const {
5358 switch (tag) {
5359 case 0: return "valid";
5360 case 1: return "zero";
5361 case 2: return "special";
5362 case 3: return "empty";
5363 }
5364 ShouldNotReachHere();
5365 return nullptr;
5366 }
5367
5368 void print() const {
5369 // print computation registers
5370 { int t = _status_word.top();
5371 for (int i = 0; i < number_of_registers; i++) {
5372 int j = (i - t) & register_mask;
5373 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5374 st(j)->print();
5375 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5376 }
5377 }
5378 printf("\n");
5379 // print control registers
5380 printf("ctrl = "); _control_word.print(); printf("\n");
5381 printf("stat = "); _status_word .print(); printf("\n");
5382 printf("tags = "); _tag_word .print(); printf("\n");
5383 }
5384
5385 };
5386
5387 class Flag_Register {
5388 public:
5389 int32_t _value;
5390
5391 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5392 bool direction() const { return ((_value >> 10) & 1) != 0; }
5393 bool sign() const { return ((_value >> 7) & 1) != 0; }
5394 bool zero() const { return ((_value >> 6) & 1) != 0; }
5395 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5396 bool parity() const { return ((_value >> 2) & 1) != 0; }
5397 bool carry() const { return ((_value >> 0) & 1) != 0; }
5398
5399 void print() const {
5400 // flags
5401 char f[8];
5402 f[0] = (overflow ()) ? 'O' : '-';
5403 f[1] = (direction ()) ? 'D' : '-';
5404 f[2] = (sign ()) ? 'S' : '-';
5405 f[3] = (zero ()) ? 'Z' : '-';
5406 f[4] = (auxiliary_carry()) ? 'A' : '-';
5407 f[5] = (parity ()) ? 'P' : '-';
5408 f[6] = (carry ()) ? 'C' : '-';
5409 f[7] = '\x0';
5410 // output
5411 printf("%08x flags = %s", _value, f);
5412 }
5413
5414 };
5415
5416 class IU_Register {
5417 public:
5418 int32_t _value;
5419
5420 void print() const {
5421 printf("%08x %11d", _value, _value);
5422 }
5423
5424 };
5425
5426 class IU_State {
5427 public:
5428 Flag_Register _eflags;
5429 IU_Register _rdi;
5430 IU_Register _rsi;
5431 IU_Register _rbp;
5432 IU_Register _rsp;
5433 IU_Register _rbx;
5434 IU_Register _rdx;
5435 IU_Register _rcx;
5436 IU_Register _rax;
5437
5438 void print() const {
5439 // computation registers
5440 printf("rax, = "); _rax.print(); printf("\n");
5441 printf("rbx, = "); _rbx.print(); printf("\n");
5442 printf("rcx = "); _rcx.print(); printf("\n");
5443 printf("rdx = "); _rdx.print(); printf("\n");
5444 printf("rdi = "); _rdi.print(); printf("\n");
5445 printf("rsi = "); _rsi.print(); printf("\n");
5446 printf("rbp, = "); _rbp.print(); printf("\n");
5447 printf("rsp = "); _rsp.print(); printf("\n");
5448 printf("\n");
5449 // control registers
5450 printf("flgs = "); _eflags.print(); printf("\n");
5451 }
5452 };
5453
5454
5455 class CPU_State {
5456 public:
5457 FPU_State _fpu_state;
5458 IU_State _iu_state;
5459
5460 void print() const {
5461 printf("--------------------------------------------------\n");
5462 _iu_state .print();
5463 printf("\n");
5464 _fpu_state.print();
5465 printf("--------------------------------------------------\n");
5466 }
5467
5468 };
5469
5470
5471 static void _print_CPU_state(CPU_State* state) {
5472 state->print();
5473 };
5474
5475
5476 void MacroAssembler::print_CPU_state() {
5477 push_CPU_state();
5478 push(rsp); // pass CPU state
5479 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5480 addptr(rsp, wordSize); // discard argument
5481 pop_CPU_state();
5482 }
5483
5484 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5485 // Either restore the MXCSR register after returning from the JNI Call
5486 // or verify that it wasn't changed (with -Xcheck:jni flag).
5487 if (RestoreMXCSROnJNICalls) {
5488 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5489 } else if (CheckJNICalls) {
5490 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5491 }
5492 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5493 vzeroupper();
5494 }
5495
5496 // ((OopHandle)result).resolve();
5497 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5498 assert_different_registers(result, tmp);
5499
5500 // Only 64 bit platforms support GCs that require a tmp register
5501 // Only IN_HEAP loads require a thread_tmp register
5502 // OopHandle::resolve is an indirection like jobject.
5503 access_load_at(T_OBJECT, IN_NATIVE,
5504 result, Address(result, 0), tmp);
5505 }
5506
5507 // ((WeakHandle)result).resolve();
5508 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5509 assert_different_registers(rresult, rtmp);
5510 Label resolved;
5511
5512 // A null weak handle resolves to null.
5513 cmpptr(rresult, 0);
5514 jcc(Assembler::equal, resolved);
5515
5516 // Only 64 bit platforms support GCs that require a tmp register
5517 // Only IN_HEAP loads require a thread_tmp register
5518 // WeakHandle::resolve is an indirection like jweak.
5519 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5520 rresult, Address(rresult, 0), rtmp);
5521 bind(resolved);
5522 }
5523
5524 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5525 // get mirror
5526 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5527 load_method_holder(mirror, method);
5528 movptr(mirror, Address(mirror, mirror_offset));
5529 resolve_oop_handle(mirror, tmp);
5530 }
5531
5532 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5533 load_method_holder(rresult, rmethod);
5534 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5535 }
5536
5537 void MacroAssembler::load_method_holder(Register holder, Register method) {
5538 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5539 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5540 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5541 }
5542
5543 void MacroAssembler::load_metadata(Register dst, Register src) {
5544 if (UseCompactObjectHeaders) {
5545 load_narrow_klass_compact(dst, src);
5546 } else {
5547 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5548 }
5549 }
5550
5551 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5552 assert(UseCompactObjectHeaders, "expect compact object headers");
5553 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5554 shrq(dst, markWord::klass_shift);
5555 }
5556
5557 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5558 assert_different_registers(src, tmp);
5559 assert_different_registers(dst, tmp);
5560
5561 if (UseCompactObjectHeaders) {
5562 load_narrow_klass_compact(dst, src);
5563 decode_klass_not_null(dst, tmp);
5564 } else {
5565 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5566 decode_klass_not_null(dst, tmp);
5567 }
5568 }
5569
5570 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
5571 load_klass(dst, src, tmp);
5572 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5573 }
5574
5575 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5576 assert(!UseCompactObjectHeaders, "not with compact headers");
5577 assert_different_registers(src, tmp);
5578 assert_different_registers(dst, tmp);
5579 encode_klass_not_null(src, tmp);
5580 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5581 }
5582
5583 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5584 if (UseCompactObjectHeaders) {
5585 assert(tmp != noreg, "need tmp");
5586 assert_different_registers(klass, obj, tmp);
5587 load_narrow_klass_compact(tmp, obj);
5588 cmpl(klass, tmp);
5589 } else {
5590 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5591 }
5592 }
5593
5594 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5595 if (UseCompactObjectHeaders) {
5596 assert(tmp2 != noreg, "need tmp2");
5597 assert_different_registers(obj1, obj2, tmp1, tmp2);
5598 load_narrow_klass_compact(tmp1, obj1);
5599 load_narrow_klass_compact(tmp2, obj2);
5600 cmpl(tmp1, tmp2);
5601 } else {
5602 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5603 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5604 }
5605 }
5606
5607 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5608 Register tmp1) {
5609 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5610 decorators = AccessInternal::decorator_fixup(decorators, type);
5611 bool as_raw = (decorators & AS_RAW) != 0;
5612 if (as_raw) {
5613 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1);
5614 } else {
5615 bs->load_at(this, decorators, type, dst, src, tmp1);
5616 }
5617 }
5618
5619 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5620 Register tmp1, Register tmp2, Register tmp3) {
5621 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5622 decorators = AccessInternal::decorator_fixup(decorators, type);
5623 bool as_raw = (decorators & AS_RAW) != 0;
5624 if (as_raw) {
5625 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5626 } else {
5627 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5628 }
5629 }
5630
5631 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5632 Register inline_layout_info) {
5633 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5634 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5635 }
5636
5637 void MacroAssembler::payload_offset(Register inline_klass, Register offset) {
5638 movptr(offset, Address(inline_klass, InlineKlass::adr_members_offset()));
5639 movl(offset, Address(offset, InlineKlass::payload_offset_offset()));
5640 }
5641
5642 void MacroAssembler::payload_addr(Register oop, Register data, Register inline_klass) {
5643 // ((address) (void*) o) + vk->payload_offset();
5644 Register offset = (data == oop) ? rscratch1 : data;
5645 payload_offset(inline_klass, offset);
5646 if (data == oop) {
5647 addptr(data, offset);
5648 } else {
5649 lea(data, Address(oop, offset));
5650 }
5651 }
5652
5653 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
5654 Register index, Register data) {
5655 assert(index != rcx, "index needs to shift by rcx");
5656 assert_different_registers(array, array_klass, index);
5657 assert_different_registers(rcx, array, index);
5658
5659 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
5660 movl(rcx, Address(array_klass, Klass::layout_helper_offset()));
5661
5662 // Klass::layout_helper_log2_element_size(lh)
5663 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
5664 shrl(rcx, Klass::_lh_log2_element_size_shift);
5665 andl(rcx, Klass::_lh_log2_element_size_mask);
5666 shlptr(index); // index << rcx
5667
5668 lea(data, Address(array, index, Address::times_1, arrayOopDesc::base_offset_in_bytes(T_FLAT_ELEMENT)));
5669 }
5670
5671 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5672 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1);
5673 }
5674
5675 // Doesn't do verification, generates fixed size code
5676 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5677 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1);
5678 }
5679
5680 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5681 Register tmp2, Register tmp3, DecoratorSet decorators) {
5682 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5683 }
5684
5685 // Used for storing nulls.
5686 void MacroAssembler::store_heap_oop_null(Address dst) {
5687 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5688 }
5689
5690 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5691 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5692 // Store to klass gap in destination
5693 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5694 }
5695
5696 #ifdef ASSERT
5697 void MacroAssembler::verify_heapbase(const char* msg) {
5698 assert (UseCompressedOops, "should be compressed");
5699 assert (Universe::heap() != nullptr, "java heap should be initialized");
5700 if (CheckCompressedOops) {
5701 Label ok;
5702 ExternalAddress src2(CompressedOops::base_addr());
5703 const bool is_src2_reachable = reachable(src2);
5704 if (!is_src2_reachable) {
5705 push(rscratch1); // cmpptr trashes rscratch1
5706 }
5707 cmpptr(r12_heapbase, src2, rscratch1);
5708 jcc(Assembler::equal, ok);
5709 STOP(msg);
5710 bind(ok);
5711 if (!is_src2_reachable) {
5712 pop(rscratch1);
5713 }
5714 }
5715 }
5716 #endif
5717
5718 // Algorithm must match oop.inline.hpp encode_heap_oop.
5719 void MacroAssembler::encode_heap_oop(Register r) {
5720 #ifdef ASSERT
5721 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5722 #endif
5723 verify_oop_msg(r, "broken oop in encode_heap_oop");
5724 if (CompressedOops::base() == nullptr) {
5725 if (CompressedOops::shift() != 0) {
5726 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5727 shrq(r, LogMinObjAlignmentInBytes);
5728 }
5729 return;
5730 }
5731 testq(r, r);
5732 cmovq(Assembler::equal, r, r12_heapbase);
5733 subq(r, r12_heapbase);
5734 shrq(r, LogMinObjAlignmentInBytes);
5735 }
5736
5737 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5738 #ifdef ASSERT
5739 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5740 if (CheckCompressedOops) {
5741 Label ok;
5742 testq(r, r);
5743 jcc(Assembler::notEqual, ok);
5744 STOP("null oop passed to encode_heap_oop_not_null");
5745 bind(ok);
5746 }
5747 #endif
5748 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5749 if (CompressedOops::base() != nullptr) {
5750 subq(r, r12_heapbase);
5751 }
5752 if (CompressedOops::shift() != 0) {
5753 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5754 shrq(r, LogMinObjAlignmentInBytes);
5755 }
5756 }
5757
5758 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5759 #ifdef ASSERT
5760 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5761 if (CheckCompressedOops) {
5762 Label ok;
5763 testq(src, src);
5764 jcc(Assembler::notEqual, ok);
5765 STOP("null oop passed to encode_heap_oop_not_null2");
5766 bind(ok);
5767 }
5768 #endif
5769 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5770 if (dst != src) {
5771 movq(dst, src);
5772 }
5773 if (CompressedOops::base() != nullptr) {
5774 subq(dst, r12_heapbase);
5775 }
5776 if (CompressedOops::shift() != 0) {
5777 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5778 shrq(dst, LogMinObjAlignmentInBytes);
5779 }
5780 }
5781
5782 void MacroAssembler::decode_heap_oop(Register r) {
5783 #ifdef ASSERT
5784 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5785 #endif
5786 if (CompressedOops::base() == nullptr) {
5787 if (CompressedOops::shift() != 0) {
5788 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5789 shlq(r, LogMinObjAlignmentInBytes);
5790 }
5791 } else {
5792 Label done;
5793 shlq(r, LogMinObjAlignmentInBytes);
5794 jccb(Assembler::equal, done);
5795 addq(r, r12_heapbase);
5796 bind(done);
5797 }
5798 verify_oop_msg(r, "broken oop in decode_heap_oop");
5799 }
5800
5801 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5802 // Note: it will change flags
5803 assert (UseCompressedOops, "should only be used for compressed headers");
5804 assert (Universe::heap() != nullptr, "java heap should be initialized");
5805 // Cannot assert, unverified entry point counts instructions (see .ad file)
5806 // vtableStubs also counts instructions in pd_code_size_limit.
5807 // Also do not verify_oop as this is called by verify_oop.
5808 if (CompressedOops::shift() != 0) {
5809 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5810 shlq(r, LogMinObjAlignmentInBytes);
5811 if (CompressedOops::base() != nullptr) {
5812 addq(r, r12_heapbase);
5813 }
5814 } else {
5815 assert (CompressedOops::base() == nullptr, "sanity");
5816 }
5817 }
5818
5819 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5820 // Note: it will change flags
5821 assert (UseCompressedOops, "should only be used for compressed headers");
5822 assert (Universe::heap() != nullptr, "java heap should be initialized");
5823 // Cannot assert, unverified entry point counts instructions (see .ad file)
5824 // vtableStubs also counts instructions in pd_code_size_limit.
5825 // Also do not verify_oop as this is called by verify_oop.
5826 if (CompressedOops::shift() != 0) {
5827 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5828 if (LogMinObjAlignmentInBytes == Address::times_8) {
5829 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5830 } else {
5831 if (dst != src) {
5832 movq(dst, src);
5833 }
5834 shlq(dst, LogMinObjAlignmentInBytes);
5835 if (CompressedOops::base() != nullptr) {
5836 addq(dst, r12_heapbase);
5837 }
5838 }
5839 } else {
5840 assert (CompressedOops::base() == nullptr, "sanity");
5841 if (dst != src) {
5842 movq(dst, src);
5843 }
5844 }
5845 }
5846
5847 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5848 BLOCK_COMMENT("encode_klass_not_null {");
5849 assert_different_registers(r, tmp);
5850 if (CompressedKlassPointers::base() != nullptr) {
5851 if (AOTCodeCache::is_on_for_dump()) {
5852 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5853 } else {
5854 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5855 }
5856 subq(r, tmp);
5857 }
5858 if (CompressedKlassPointers::shift() != 0) {
5859 shrq(r, CompressedKlassPointers::shift());
5860 }
5861 BLOCK_COMMENT("} encode_klass_not_null");
5862 }
5863
5864 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5865 BLOCK_COMMENT("encode_and_move_klass_not_null {");
5866 assert_different_registers(src, dst);
5867 if (CompressedKlassPointers::base() != nullptr) {
5868 if (AOTCodeCache::is_on_for_dump()) {
5869 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5870 negq(dst);
5871 } else {
5872 movptr(dst, -(intptr_t)CompressedKlassPointers::base());
5873 }
5874 addq(dst, src);
5875 } else {
5876 movptr(dst, src);
5877 }
5878 if (CompressedKlassPointers::shift() != 0) {
5879 shrq(dst, CompressedKlassPointers::shift());
5880 }
5881 BLOCK_COMMENT("} encode_and_move_klass_not_null");
5882 }
5883
5884 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5885 BLOCK_COMMENT("decode_klass_not_null {");
5886 assert_different_registers(r, tmp);
5887 // Note: it will change flags
5888 // Cannot assert, unverified entry point counts instructions (see .ad file)
5889 // vtableStubs also counts instructions in pd_code_size_limit.
5890 // Also do not verify_oop as this is called by verify_oop.
5891 if (CompressedKlassPointers::shift() != 0) {
5892 shlq(r, CompressedKlassPointers::shift());
5893 }
5894 if (CompressedKlassPointers::base() != nullptr) {
5895 if (AOTCodeCache::is_on_for_dump()) {
5896 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5897 } else {
5898 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5899 }
5900 addq(r, tmp);
5901 }
5902 BLOCK_COMMENT("} decode_klass_not_null");
5903 }
5904
5905 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5906 BLOCK_COMMENT("decode_and_move_klass_not_null {");
5907 assert_different_registers(src, dst);
5908 // Note: it will change flags
5909 // Cannot assert, unverified entry point counts instructions (see .ad file)
5910 // vtableStubs also counts instructions in pd_code_size_limit.
5911 // Also do not verify_oop as this is called by verify_oop.
5912
5913 if (CompressedKlassPointers::base() == nullptr &&
5914 CompressedKlassPointers::shift() == 0) {
5915 // The best case scenario is that there is no base or shift. Then it is already
5916 // a pointer that needs nothing but a register rename.
5917 movl(dst, src);
5918 } else {
5919 if (CompressedKlassPointers::shift() <= Address::times_8) {
5920 if (CompressedKlassPointers::base() != nullptr) {
5921 if (AOTCodeCache::is_on_for_dump()) {
5922 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5923 } else {
5924 movptr(dst, (intptr_t)CompressedKlassPointers::base());
5925 }
5926 } else {
5927 xorq(dst, dst);
5928 }
5929 if (CompressedKlassPointers::shift() != 0) {
5930 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
5931 leaq(dst, Address(dst, src, Address::times_8, 0));
5932 } else {
5933 addq(dst, src);
5934 }
5935 } else {
5936 if (CompressedKlassPointers::base() != nullptr) {
5937 if (AOTCodeCache::is_on_for_dump()) {
5938 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5939 shrq(dst, CompressedKlassPointers::shift());
5940 } else {
5941 const intptr_t base_right_shifted =
5942 (intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5943 movptr(dst, base_right_shifted);
5944 }
5945 } else {
5946 xorq(dst, dst);
5947 }
5948 addq(dst, src);
5949 shlq(dst, CompressedKlassPointers::shift());
5950 }
5951 }
5952 BLOCK_COMMENT("} decode_and_move_klass_not_null");
5953 }
5954
5955 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5956 assert (UseCompressedOops, "should only be used for compressed headers");
5957 assert (Universe::heap() != nullptr, "java heap should be initialized");
5958 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5959 int oop_index = oop_recorder()->find_index(obj);
5960 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5961 mov_narrow_oop(dst, oop_index, rspec);
5962 }
5963
5964 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5965 assert (UseCompressedOops, "should only be used for compressed headers");
5966 assert (Universe::heap() != nullptr, "java heap should be initialized");
5967 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5968 int oop_index = oop_recorder()->find_index(obj);
5969 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5970 mov_narrow_oop(dst, oop_index, rspec);
5971 }
5972
5973 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5974 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5975 int klass_index = oop_recorder()->find_index(k);
5976 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5977 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5978 }
5979
5980 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5981 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5982 int klass_index = oop_recorder()->find_index(k);
5983 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5984 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5985 }
5986
5987 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5988 assert (UseCompressedOops, "should only be used for compressed headers");
5989 assert (Universe::heap() != nullptr, "java heap should be initialized");
5990 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5991 int oop_index = oop_recorder()->find_index(obj);
5992 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5993 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5994 }
5995
5996 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5997 assert (UseCompressedOops, "should only be used for compressed headers");
5998 assert (Universe::heap() != nullptr, "java heap should be initialized");
5999 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6000 int oop_index = oop_recorder()->find_index(obj);
6001 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6002 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6003 }
6004
6005 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6006 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6007 int klass_index = oop_recorder()->find_index(k);
6008 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6009 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6010 }
6011
6012 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6013 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6014 int klass_index = oop_recorder()->find_index(k);
6015 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6016 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6017 }
6018
6019 void MacroAssembler::reinit_heapbase() {
6020 if (UseCompressedOops) {
6021 if (Universe::heap() != nullptr && !AOTCodeCache::is_on_for_dump()) {
6022 if (CompressedOops::base() == nullptr) {
6023 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6024 } else {
6025 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6026 }
6027 } else {
6028 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6029 }
6030 }
6031 }
6032
6033 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6034 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6035 // An inline type might be returned. If fields are in registers we
6036 // need to allocate an inline type instance and initialize it with
6037 // the value of the fields.
6038 Label skip;
6039 // We only need a new buffered inline type if a new one is not returned
6040 testptr(rax, 1);
6041 jcc(Assembler::zero, skip);
6042 int call_offset = -1;
6043
6044 // The following code is similar to allocation code in TemplateTable::_new but has some slight differences,
6045 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6046 // allocating is not necessary if vk != nullptr, etc.
6047 Label slow_case;
6048 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6049 mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
6050 if (vk != nullptr) {
6051 // Called from C1, where the return type is statically known.
6052 movptr(rbx, (intptr_t)vk->get_InlineKlass());
6053 jint lh = vk->layout_helper();
6054 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6055 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6056 tlab_allocate(rax, noreg, lh, r13, r14, slow_case);
6057 } else {
6058 jmp(slow_case);
6059 }
6060 } else {
6061 // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
6062 mov(rbx, rax);
6063 andptr(rbx, -2);
6064 if (UseTLAB) {
6065 movl(r14, Address(rbx, Klass::layout_helper_offset()));
6066 testl(r14, Klass::_lh_instance_slow_path_bit);
6067 jcc(Assembler::notZero, slow_case);
6068 tlab_allocate(rax, r14, 0, r13, r14, slow_case);
6069 } else {
6070 jmp(slow_case);
6071 }
6072 }
6073 if (UseTLAB) {
6074 // 2. Initialize buffered inline instance header
6075 Register buffer_obj = rax;
6076 Register klass = rbx;
6077 if (UseCompactObjectHeaders) {
6078 Register mark_word = r13;
6079 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
6080 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), mark_word);
6081 } else {
6082 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
6083 xorl(r13, r13);
6084 store_klass_gap(buffer_obj, r13);
6085 if (vk == nullptr) {
6086 // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
6087 mov(r13, klass);
6088 }
6089 store_klass(buffer_obj, klass, rscratch1);
6090 klass = r13;
6091 }
6092 // 3. Initialize its fields with an inline class specific handler
6093 if (vk != nullptr) {
6094 call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6095 } else {
6096 movptr(rbx, Address(klass, InlineKlass::adr_members_offset()));
6097 movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
6098 call(rbx);
6099 }
6100 jmp(skip);
6101 }
6102 bind(slow_case);
6103 // We failed to allocate a new inline type, fall back to a runtime
6104 // call. Some oop field may be live in some registers but we can't
6105 // tell. That runtime call will take care of preserving them
6106 // across a GC if there's one.
6107 mov(rax, rscratch1);
6108
6109 if (from_interpreter) {
6110 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6111 } else {
6112 call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6113 call_offset = offset();
6114 }
6115
6116 bind(skip);
6117 return call_offset;
6118 }
6119
6120 // Move a value between registers/stack slots and update the reg_state
6121 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6122 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6123 if (reg_state[to->value()] == reg_written) {
6124 return true; // Already written
6125 }
6126 if (from != to && bt != T_VOID) {
6127 if (reg_state[to->value()] == reg_readonly) {
6128 return false; // Not yet writable
6129 }
6130 if (from->is_reg()) {
6131 if (to->is_reg()) {
6132 if (from->is_XMMRegister()) {
6133 if (bt == T_DOUBLE) {
6134 movdbl(to->as_XMMRegister(), from->as_XMMRegister());
6135 } else {
6136 assert(bt == T_FLOAT, "must be float");
6137 movflt(to->as_XMMRegister(), from->as_XMMRegister());
6138 }
6139 } else {
6140 movq(to->as_Register(), from->as_Register());
6141 }
6142 } else {
6143 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6144 Address to_addr = Address(rsp, st_off);
6145 if (from->is_XMMRegister()) {
6146 if (bt == T_DOUBLE) {
6147 movdbl(to_addr, from->as_XMMRegister());
6148 } else {
6149 assert(bt == T_FLOAT, "must be float");
6150 movflt(to_addr, from->as_XMMRegister());
6151 }
6152 } else {
6153 movq(to_addr, from->as_Register());
6154 }
6155 }
6156 } else {
6157 Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
6158 if (to->is_reg()) {
6159 if (to->is_XMMRegister()) {
6160 if (bt == T_DOUBLE) {
6161 movdbl(to->as_XMMRegister(), from_addr);
6162 } else {
6163 assert(bt == T_FLOAT, "must be float");
6164 movflt(to->as_XMMRegister(), from_addr);
6165 }
6166 } else {
6167 movq(to->as_Register(), from_addr);
6168 }
6169 } else {
6170 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6171 movq(r13, from_addr);
6172 movq(Address(rsp, st_off), r13);
6173 }
6174 }
6175 }
6176 // Update register states
6177 reg_state[from->value()] = reg_writable;
6178 reg_state[to->value()] = reg_written;
6179 return true;
6180 }
6181
6182 // Calculate the extra stack space required for packing or unpacking inline
6183 // args and adjust the stack pointer (see MacroAssembler::remove_frame).
6184 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6185 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
6186 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6187 assert(sp_inc > 0, "sanity");
6188 // Two additional slots to account for return address
6189 sp_inc += 2 * VMRegImpl::stack_slot_size;
6190
6191 push(rbp);
6192 subptr(rsp, sp_inc);
6193 #ifdef ASSERT
6194 movl(Address(rsp, 0), badRegWordVal);
6195 movl(Address(rsp, VMRegImpl::stack_slot_size), badRegWordVal);
6196 #endif
6197 return sp_inc + wordSize; // account for rbp space
6198 }
6199
6200 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
6201 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6202 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6203 RegState reg_state[]) {
6204 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6205 assert(from->is_valid(), "source must be valid");
6206 bool progress = false;
6207 #ifdef ASSERT
6208 const int start_offset = offset();
6209 #endif
6210
6211 Label L_null, L_notNull;
6212 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6213 Register tmp1 = r10;
6214 Register tmp2 = r13;
6215 Register fromReg = noreg;
6216 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, true);
6217 bool done = true;
6218 bool mark_done = true;
6219 VMReg toReg;
6220 BasicType bt;
6221 // Check if argument requires a null check
6222 bool null_check = false;
6223 VMReg nullCheckReg;
6224 while (stream.next(nullCheckReg, bt)) {
6225 if (sig->at(stream.sig_index())._offset == -1) {
6226 null_check = true;
6227 break;
6228 }
6229 }
6230 stream.reset(sig_index, to_index);
6231 while (stream.next(toReg, bt)) {
6232 assert(toReg->is_valid(), "destination must be valid");
6233 int idx = (int)toReg->value();
6234 if (reg_state[idx] == reg_readonly) {
6235 if (idx != from->value()) {
6236 mark_done = false;
6237 }
6238 done = false;
6239 continue;
6240 } else if (reg_state[idx] == reg_written) {
6241 continue;
6242 }
6243 assert(reg_state[idx] == reg_writable, "must be writable");
6244 reg_state[idx] = reg_written;
6245 progress = true;
6246
6247 if (fromReg == noreg) {
6248 if (from->is_reg()) {
6249 fromReg = from->as_Register();
6250 } else {
6251 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6252 movq(tmp1, Address(rsp, st_off));
6253 fromReg = tmp1;
6254 }
6255 if (null_check) {
6256 // Nullable inline type argument, emit null check
6257 testptr(fromReg, fromReg);
6258 jcc(Assembler::zero, L_null);
6259 }
6260 }
6261 int off = sig->at(stream.sig_index())._offset;
6262 if (off == -1) {
6263 assert(null_check, "Missing null check at");
6264 if (toReg->is_stack()) {
6265 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6266 movq(Address(rsp, st_off), 1);
6267 } else {
6268 movq(toReg->as_Register(), 1);
6269 }
6270 continue;
6271 }
6272 if (sig->at(stream.sig_index())._vt_oop) {
6273 if (toReg->is_stack()) {
6274 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6275 movq(Address(rsp, st_off), fromReg);
6276 } else {
6277 movq(toReg->as_Register(), fromReg);
6278 }
6279 continue;
6280 }
6281 assert(off > 0, "offset in object should be positive");
6282 Address fromAddr = Address(fromReg, off);
6283 if (!toReg->is_XMMRegister()) {
6284 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
6285 if (is_reference_type(bt)) {
6286 load_heap_oop(dst, fromAddr);
6287 } else {
6288 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
6289 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
6290 }
6291 if (toReg->is_stack()) {
6292 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6293 movq(Address(rsp, st_off), dst);
6294 }
6295 } else if (bt == T_DOUBLE) {
6296 movdbl(toReg->as_XMMRegister(), fromAddr);
6297 } else {
6298 assert(bt == T_FLOAT, "must be float");
6299 movflt(toReg->as_XMMRegister(), fromAddr);
6300 }
6301 }
6302 if (progress && null_check) {
6303 if (done) {
6304 jmp(L_notNull);
6305 bind(L_null);
6306 // Set null marker to zero to signal that the argument is null.
6307 // Also set all fields to zero since the runtime requires a canonical
6308 // representation of a flat null.
6309 stream.reset(sig_index, to_index);
6310 while (stream.next(toReg, bt)) {
6311 if (toReg->is_stack()) {
6312 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6313 movq(Address(rsp, st_off), 0);
6314 } else if (toReg->is_XMMRegister()) {
6315 xorps(toReg->as_XMMRegister(), toReg->as_XMMRegister());
6316 } else {
6317 xorl(toReg->as_Register(), toReg->as_Register());
6318 }
6319 }
6320 bind(L_notNull);
6321 } else {
6322 bind(L_null);
6323 }
6324 }
6325
6326 sig_index = stream.sig_index();
6327 to_index = stream.regs_index();
6328
6329 if (mark_done && reg_state[from->value()] != reg_written) {
6330 // This is okay because no one else will write to that slot
6331 reg_state[from->value()] = reg_writable;
6332 }
6333 from_index--;
6334 assert(progress || (start_offset == offset()), "should not emit code");
6335 return done;
6336 }
6337
6338 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
6339 VMRegPair* from, int from_count, int& from_index, VMReg to,
6340 RegState reg_state[], Register val_array) {
6341 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
6342 assert(to->is_valid(), "destination must be valid");
6343
6344 if (reg_state[to->value()] == reg_written) {
6345 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6346 return true; // Already written
6347 }
6348
6349 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
6350 Register val_obj_tmp = r11;
6351 Register from_reg_tmp = r14;
6352 Register tmp1 = r10;
6353 Register tmp2 = r13;
6354 Register tmp3 = rbx;
6355 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
6356
6357 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
6358
6359 if (reg_state[to->value()] == reg_readonly) {
6360 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
6361 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6362 return false; // Not yet writable
6363 }
6364 val_obj = val_obj_tmp;
6365 }
6366
6367 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
6368 VMReg fromReg;
6369 BasicType bt;
6370 Label L_null;
6371 while (stream.next(fromReg, bt)) {
6372 assert(fromReg->is_valid(), "source must be valid");
6373 reg_state[fromReg->value()] = reg_writable;
6374
6375 int off = sig->at(stream.sig_index())._offset;
6376 if (off == -1) {
6377 // Nullable inline type argument, emit null check
6378 Label L_notNull;
6379 if (fromReg->is_stack()) {
6380 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6381 testb(Address(rsp, ld_off), 1);
6382 } else {
6383 testb(fromReg->as_Register(), 1);
6384 }
6385 jcc(Assembler::notZero, L_notNull);
6386 movptr(val_obj, 0);
6387 jmp(L_null);
6388 bind(L_notNull);
6389 continue;
6390 }
6391 if (sig->at(stream.sig_index())._vt_oop) {
6392 // buffer argument: use if non null
6393 if (fromReg->is_stack()) {
6394 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6395 movptr(val_obj, Address(rsp, ld_off));
6396 } else {
6397 movptr(val_obj, fromReg->as_Register());
6398 }
6399 testptr(val_obj, val_obj);
6400 jcc(Assembler::notEqual, L_null);
6401 // otherwise get the buffer from the just allocated pool of buffers
6402 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
6403 load_heap_oop(val_obj, Address(val_array, index));
6404 continue;
6405 }
6406
6407 assert(off > 0, "offset in object should be positive");
6408 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
6409
6410 // Pack the scalarized field into the value object.
6411 Address dst(val_obj, off);
6412 if (!fromReg->is_XMMRegister()) {
6413 Register src;
6414 if (fromReg->is_stack()) {
6415 src = from_reg_tmp;
6416 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6417 load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
6418 } else {
6419 src = fromReg->as_Register();
6420 }
6421 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
6422 if (is_reference_type(bt)) {
6423 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep val_obj valid.
6424 mov(tmp3, val_obj);
6425 Address dst_with_tmp3(tmp3, off);
6426 store_heap_oop(dst_with_tmp3, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
6427 } else {
6428 store_sized_value(dst, src, size_in_bytes);
6429 }
6430 } else if (bt == T_DOUBLE) {
6431 movdbl(dst, fromReg->as_XMMRegister());
6432 } else {
6433 assert(bt == T_FLOAT, "must be float");
6434 movflt(dst, fromReg->as_XMMRegister());
6435 }
6436 }
6437 bind(L_null);
6438 sig_index = stream.sig_index();
6439 from_index = stream.regs_index();
6440
6441 assert(reg_state[to->value()] == reg_writable, "must have already been read");
6442 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6443 assert(success, "to register must be writeable");
6444 return true;
6445 }
6446
6447 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6448 return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
6449 }
6450
6451 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
6452 assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6453 if (needs_stack_repair) {
6454 // The method has a scalarized entry point (where fields of value object arguments
6455 // are passed through registers and stack), and a non-scalarized entry point (where
6456 // value object arguments are given as oops). The non-scalarized entry point will
6457 // first load each field of value object arguments and store them in registers and on
6458 // the stack in a way compatible with the scalarized entry point. To do so, some extra
6459 // stack space might be reserved (if argument registers are not enough). On leaving the
6460 // method, this space must be freed.
6461 //
6462 // In case we used the non-scalarized entry point the stack looks like this:
6463 //
6464 // | Arguments from caller |
6465 // |---------------------------| <-- caller's SP
6466 // | Return address #1 |
6467 // | Saved RBP #1 |
6468 // |---------------------------|
6469 // | Extension space for |
6470 // | inline arg (un)packing |
6471 // |---------------------------| <-- start of this method's frame
6472 // | Return address #2 |
6473 // | Saved RBP #2 |
6474 // |---------------------------| <-- RBP (with -XX:+PreserveFramePointer)
6475 // | sp_inc |
6476 // | method locals |
6477 // |---------------------------| <-- SP
6478 //
6479 // Space for the return pc and saved rbp is reserved twice. But only the #1 copies
6480 // contain the real values of return pc and saved rbp. The #2 copies are not reliable
6481 // and should not be used. They are mostly needed to add space between the extension
6482 // space and the locals, as there would be between the real arguments and the locals
6483 // if we don't need to do unpacking (from the scalarized entry point).
6484 //
6485 // When leaving, one must load RBP #1 into RBP, and use the copy #1 of the return address,
6486 // while keeping in mind that from the scalarized entry point, there will be only one
6487 // copy. Indeed, in the case we used the scalarized calling convention, the stack looks like this:
6488 //
6489 // | Arguments from caller |
6490 // |---------------------------| <-- caller's SP
6491 // | Return address |
6492 // | Saved RBP |
6493 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer)
6494 // | sp_inc |
6495 // | method locals |
6496 // |---------------------------| <-- SP
6497 //
6498 // The sp_inc stack slot holds the total size of the frame, including the extension
6499 // space and copies #2 of the return address and the saved RBP (but never the copies
6500 // #1 of the return address and saved RBP). That is how to find the copies #1 of the
6501 // return address and saved rbp. This size is expressed in bytes. Be careful when using
6502 // it from C++ in pointer arithmetic you might need to divide it by wordSize.
6503
6504 // The stack increment resides just below the saved rbp
6505 addq(rsp, Address(rsp, initial_framesize - wordSize));
6506 pop(rbp);
6507 } else {
6508 if (initial_framesize > 0) {
6509 addq(rsp, initial_framesize);
6510 }
6511 pop(rbp);
6512 }
6513 }
6514
6515 #if COMPILER2_OR_JVMCI
6516
6517 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6518 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
6519 // cnt - number of qwords (8-byte words).
6520 // base - start address, qword aligned.
6521 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6522 bool use64byteVector = (MaxVectorSize == 64) && (CopyAVX3Threshold == 0);
6523 if (use64byteVector) {
6524 evpbroadcastq(xtmp, val, AVX_512bit);
6525 } else if (MaxVectorSize >= 32) {
6526 movdq(xtmp, val);
6527 punpcklqdq(xtmp, xtmp);
6528 vinserti128_high(xtmp, xtmp);
6529 } else {
6530 movdq(xtmp, val);
6531 punpcklqdq(xtmp, xtmp);
6532 }
6533 jmp(L_zero_64_bytes);
6534
6535 BIND(L_loop);
6536 if (MaxVectorSize >= 32) {
6537 fill64(base, 0, xtmp, use64byteVector);
6538 } else {
6539 movdqu(Address(base, 0), xtmp);
6540 movdqu(Address(base, 16), xtmp);
6541 movdqu(Address(base, 32), xtmp);
6542 movdqu(Address(base, 48), xtmp);
6543 }
6544 addptr(base, 64);
6545
6546 BIND(L_zero_64_bytes);
6547 subptr(cnt, 8);
6548 jccb(Assembler::greaterEqual, L_loop);
6549
6550 // Copy trailing 64 bytes
6551 if (use64byteVector) {
6552 addptr(cnt, 8);
6553 jccb(Assembler::equal, L_end);
6554 fill64_masked(3, base, 0, xtmp, mask, cnt, val, true);
6555 jmp(L_end);
6556 } else {
6557 addptr(cnt, 4);
6558 jccb(Assembler::less, L_tail);
6559 if (MaxVectorSize >= 32) {
6560 vmovdqu(Address(base, 0), xtmp);
6561 } else {
6562 movdqu(Address(base, 0), xtmp);
6563 movdqu(Address(base, 16), xtmp);
6564 }
6565 }
6566 addptr(base, 32);
6567 subptr(cnt, 4);
6568
6569 BIND(L_tail);
6570 addptr(cnt, 4);
6571 jccb(Assembler::lessEqual, L_end);
6572 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6573 fill32_masked(3, base, 0, xtmp, mask, cnt, val);
6574 } else {
6575 decrement(cnt);
6576
6577 BIND(L_sloop);
6578 movq(Address(base, 0), xtmp);
6579 addptr(base, 8);
6580 decrement(cnt);
6581 jccb(Assembler::greaterEqual, L_sloop);
6582 }
6583 BIND(L_end);
6584 }
6585
6586 // Clearing constant sized memory using YMM/ZMM registers.
6587 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6588 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6589 bool use64byteVector = (MaxVectorSize > 32) && (CopyAVX3Threshold == 0);
6590
6591 int vector64_count = (cnt & (~0x7)) >> 3;
6592 cnt = cnt & 0x7;
6593 const int fill64_per_loop = 4;
6594 const int max_unrolled_fill64 = 8;
6595
6596 // 64 byte initialization loop.
6597 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6598 int start64 = 0;
6599 if (vector64_count > max_unrolled_fill64) {
6600 Label LOOP;
6601 Register index = rtmp;
6602
6603 start64 = vector64_count - (vector64_count % fill64_per_loop);
6604
6605 movl(index, 0);
6606 BIND(LOOP);
6607 for (int i = 0; i < fill64_per_loop; i++) {
6608 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6609 }
6610 addl(index, fill64_per_loop * 64);
6611 cmpl(index, start64 * 64);
6612 jccb(Assembler::less, LOOP);
6613 }
6614 for (int i = start64; i < vector64_count; i++) {
6615 fill64(base, i * 64, xtmp, use64byteVector);
6616 }
6617
6618 // Clear remaining 64 byte tail.
6619 int disp = vector64_count * 64;
6620 if (cnt) {
6621 switch (cnt) {
6622 case 1:
6623 movq(Address(base, disp), xtmp);
6624 break;
6625 case 2:
6626 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6627 break;
6628 case 3:
6629 movl(rtmp, 0x7);
6630 kmovwl(mask, rtmp);
6631 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6632 break;
6633 case 4:
6634 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6635 break;
6636 case 5:
6637 if (use64byteVector) {
6638 movl(rtmp, 0x1F);
6639 kmovwl(mask, rtmp);
6640 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6641 } else {
6642 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6643 movq(Address(base, disp + 32), xtmp);
6644 }
6645 break;
6646 case 6:
6647 if (use64byteVector) {
6648 movl(rtmp, 0x3F);
6649 kmovwl(mask, rtmp);
6650 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6651 } else {
6652 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6653 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6654 }
6655 break;
6656 case 7:
6657 if (use64byteVector) {
6658 movl(rtmp, 0x7F);
6659 kmovwl(mask, rtmp);
6660 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6661 } else {
6662 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6663 movl(rtmp, 0x7);
6664 kmovwl(mask, rtmp);
6665 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6666 }
6667 break;
6668 default:
6669 fatal("Unexpected length : %d\n",cnt);
6670 break;
6671 }
6672 }
6673 }
6674
6675 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
6676 bool is_large, bool word_copy_only, KRegister mask) {
6677 // cnt - number of qwords (8-byte words).
6678 // base - start address, qword aligned.
6679 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6680 assert(base==rdi, "base register must be edi for rep stos");
6681 assert(val==rax, "val register must be eax for rep stos");
6682 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6683 assert(InitArrayShortSize % BytesPerLong == 0,
6684 "InitArrayShortSize should be the multiple of BytesPerLong");
6685
6686 Label DONE;
6687
6688 if (!is_large) {
6689 Label LOOP, LONG;
6690 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6691 jccb(Assembler::greater, LONG);
6692
6693 decrement(cnt);
6694 jccb(Assembler::negative, DONE); // Zero length
6695
6696 // Use individual pointer-sized stores for small counts:
6697 BIND(LOOP);
6698 movptr(Address(base, cnt, Address::times_ptr), val);
6699 decrement(cnt);
6700 jccb(Assembler::greaterEqual, LOOP);
6701 jmpb(DONE);
6702
6703 BIND(LONG);
6704 }
6705
6706 // Use longer rep-prefixed ops for non-small counts:
6707 if (UseFastStosb && !word_copy_only) {
6708 shlptr(cnt, 3); // convert to number of bytes
6709 rep_stosb();
6710 } else if (UseXMMForObjInit) {
6711 xmm_clear_mem(base, cnt, val, xtmp, mask);
6712 } else {
6713 rep_stos();
6714 }
6715
6716 BIND(DONE);
6717 }
6718
6719 #endif //COMPILER2_OR_JVMCI
6720
6721
6722 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6723 Register to, Register value, Register count,
6724 Register rtmp, XMMRegister xtmp) {
6725 ShortBranchVerifier sbv(this);
6726 assert_different_registers(to, value, count, rtmp);
6727 Label L_exit;
6728 Label L_fill_2_bytes, L_fill_4_bytes;
6729
6730 #if defined(COMPILER2)
6731 if(MaxVectorSize >=32 &&
6732 VM_Version::supports_avx512vlbw() &&
6733 VM_Version::supports_bmi2()) {
6734 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6735 return;
6736 }
6737 #endif
6738
6739 int shift = -1;
6740 switch (t) {
6741 case T_BYTE:
6742 shift = 2;
6743 break;
6744 case T_SHORT:
6745 shift = 1;
6746 break;
6747 case T_INT:
6748 shift = 0;
6749 break;
6750 default: ShouldNotReachHere();
6751 }
6752
6753 if (t == T_BYTE) {
6754 andl(value, 0xff);
6755 movl(rtmp, value);
6756 shll(rtmp, 8);
6757 orl(value, rtmp);
6758 }
6759 if (t == T_SHORT) {
6760 andl(value, 0xffff);
6761 }
6762 if (t == T_BYTE || t == T_SHORT) {
6763 movl(rtmp, value);
6764 shll(rtmp, 16);
6765 orl(value, rtmp);
6766 }
6767
6768 cmpptr(count, 8 << shift); // Short arrays (< 32 bytes) fill by element
6769 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6770 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6771 Label L_skip_align2;
6772 // align source address at 4 bytes address boundary
6773 if (t == T_BYTE) {
6774 Label L_skip_align1;
6775 // One byte misalignment happens only for byte arrays
6776 testptr(to, 1);
6777 jccb(Assembler::zero, L_skip_align1);
6778 movb(Address(to, 0), value);
6779 increment(to);
6780 decrement(count);
6781 BIND(L_skip_align1);
6782 }
6783 // Two bytes misalignment happens only for byte and short (char) arrays
6784 testptr(to, 2);
6785 jccb(Assembler::zero, L_skip_align2);
6786 movw(Address(to, 0), value);
6787 addptr(to, 2);
6788 subptr(count, 1<<(shift-1));
6789 BIND(L_skip_align2);
6790 }
6791 {
6792 Label L_fill_32_bytes;
6793 if (!UseUnalignedLoadStores) {
6794 // align to 8 bytes, we know we are 4 byte aligned to start
6795 testptr(to, 4);
6796 jccb(Assembler::zero, L_fill_32_bytes);
6797 movl(Address(to, 0), value);
6798 addptr(to, 4);
6799 subptr(count, 1<<shift);
6800 }
6801 BIND(L_fill_32_bytes);
6802 {
6803 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6804 movdl(xtmp, value);
6805 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6806 Label L_check_fill_32_bytes;
6807 if (UseAVX > 2) {
6808 // Fill 64-byte chunks
6809 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6810
6811 // If number of bytes to fill < CopyAVX3Threshold, perform fill using AVX2
6812 cmpptr(count, CopyAVX3Threshold);
6813 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6814
6815 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6816
6817 subptr(count, 16 << shift);
6818 jcc(Assembler::less, L_check_fill_32_bytes);
6819 align(16);
6820
6821 BIND(L_fill_64_bytes_loop_avx3);
6822 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6823 addptr(to, 64);
6824 subptr(count, 16 << shift);
6825 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6826 jmpb(L_check_fill_32_bytes);
6827
6828 BIND(L_check_fill_64_bytes_avx2);
6829 }
6830 // Fill 64-byte chunks
6831 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6832
6833 subptr(count, 16 << shift);
6834 jcc(Assembler::less, L_check_fill_32_bytes);
6835
6836 // align data for 64-byte chunks
6837 Label L_fill_64_bytes_loop, L_align_64_bytes_loop;
6838 if (EnableX86ECoreOpts) {
6839 // align 'big' arrays to cache lines to minimize split_stores
6840 cmpptr(count, 96 << shift);
6841 jcc(Assembler::below, L_fill_64_bytes_loop);
6842
6843 // Find the bytes needed for alignment
6844 movptr(rtmp, to);
6845 andptr(rtmp, 0x1c);
6846 jcc(Assembler::zero, L_fill_64_bytes_loop);
6847 negptr(rtmp); // number of bytes to fill 32-rtmp. it filled by 2 mov by 32
6848 addptr(rtmp, 32);
6849 shrptr(rtmp, 2 - shift);// get number of elements from bytes
6850 subptr(count, rtmp); // adjust count by number of elements
6851
6852 align(16);
6853 BIND(L_align_64_bytes_loop);
6854 movdl(Address(to, 0), xtmp);
6855 addptr(to, 4);
6856 subptr(rtmp, 1 << shift);
6857 jcc(Assembler::greater, L_align_64_bytes_loop);
6858 }
6859
6860 align(16);
6861 BIND(L_fill_64_bytes_loop);
6862 vmovdqu(Address(to, 0), xtmp);
6863 vmovdqu(Address(to, 32), xtmp);
6864 addptr(to, 64);
6865 subptr(count, 16 << shift);
6866 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6867
6868 align(16);
6869 BIND(L_check_fill_32_bytes);
6870 addptr(count, 8 << shift);
6871 jccb(Assembler::less, L_check_fill_8_bytes);
6872 vmovdqu(Address(to, 0), xtmp);
6873 addptr(to, 32);
6874 subptr(count, 8 << shift);
6875
6876 BIND(L_check_fill_8_bytes);
6877 // clean upper bits of YMM registers
6878 movdl(xtmp, value);
6879 pshufd(xtmp, xtmp, 0);
6880 } else {
6881 // Fill 32-byte chunks
6882 pshufd(xtmp, xtmp, 0);
6883
6884 subptr(count, 8 << shift);
6885 jcc(Assembler::less, L_check_fill_8_bytes);
6886 align(16);
6887
6888 BIND(L_fill_32_bytes_loop);
6889
6890 if (UseUnalignedLoadStores) {
6891 movdqu(Address(to, 0), xtmp);
6892 movdqu(Address(to, 16), xtmp);
6893 } else {
6894 movq(Address(to, 0), xtmp);
6895 movq(Address(to, 8), xtmp);
6896 movq(Address(to, 16), xtmp);
6897 movq(Address(to, 24), xtmp);
6898 }
6899
6900 addptr(to, 32);
6901 subptr(count, 8 << shift);
6902 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6903
6904 BIND(L_check_fill_8_bytes);
6905 }
6906 addptr(count, 8 << shift);
6907 jccb(Assembler::zero, L_exit);
6908 jmpb(L_fill_8_bytes);
6909
6910 //
6911 // length is too short, just fill qwords
6912 //
6913 align(16);
6914 BIND(L_fill_8_bytes_loop);
6915 movq(Address(to, 0), xtmp);
6916 addptr(to, 8);
6917 BIND(L_fill_8_bytes);
6918 subptr(count, 1 << (shift + 1));
6919 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6920 }
6921 }
6922
6923 Label L_fill_4_bytes_loop;
6924 testl(count, 1 << shift);
6925 jccb(Assembler::zero, L_fill_2_bytes);
6926
6927 align(16);
6928 BIND(L_fill_4_bytes_loop);
6929 movl(Address(to, 0), value);
6930 addptr(to, 4);
6931
6932 BIND(L_fill_4_bytes);
6933 subptr(count, 1 << shift);
6934 jccb(Assembler::greaterEqual, L_fill_4_bytes_loop);
6935
6936 if (t == T_BYTE || t == T_SHORT) {
6937 Label L_fill_byte;
6938 BIND(L_fill_2_bytes);
6939 // fill trailing 2 bytes
6940 testl(count, 1<<(shift-1));
6941 jccb(Assembler::zero, L_fill_byte);
6942 movw(Address(to, 0), value);
6943 if (t == T_BYTE) {
6944 addptr(to, 2);
6945 BIND(L_fill_byte);
6946 // fill trailing byte
6947 testl(count, 1);
6948 jccb(Assembler::zero, L_exit);
6949 movb(Address(to, 0), value);
6950 } else {
6951 BIND(L_fill_byte);
6952 }
6953 } else {
6954 BIND(L_fill_2_bytes);
6955 }
6956 BIND(L_exit);
6957 }
6958
6959 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6960 switch(type) {
6961 case T_BYTE:
6962 case T_BOOLEAN:
6963 evpbroadcastb(dst, src, vector_len);
6964 break;
6965 case T_SHORT:
6966 case T_CHAR:
6967 evpbroadcastw(dst, src, vector_len);
6968 break;
6969 case T_INT:
6970 case T_FLOAT:
6971 evpbroadcastd(dst, src, vector_len);
6972 break;
6973 case T_LONG:
6974 case T_DOUBLE:
6975 evpbroadcastq(dst, src, vector_len);
6976 break;
6977 default:
6978 fatal("Unhandled type : %s", type2name(type));
6979 break;
6980 }
6981 }
6982
6983 // Encode given char[]/byte[] to byte[] in ISO_8859_1 or ASCII
6984 //
6985 // @IntrinsicCandidate
6986 // int sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(
6987 // char[] sa, int sp, byte[] da, int dp, int len) {
6988 // int i = 0;
6989 // for (; i < len; i++) {
6990 // char c = sa[sp++];
6991 // if (c > '\u00FF')
6992 // break;
6993 // da[dp++] = (byte) c;
6994 // }
6995 // return i;
6996 // }
6997 //
6998 // @IntrinsicCandidate
6999 // int java.lang.StringCoding.encodeISOArray0(
7000 // byte[] sa, int sp, byte[] da, int dp, int len) {
7001 // int i = 0;
7002 // for (; i < len; i++) {
7003 // char c = StringUTF16.getChar(sa, sp++);
7004 // if (c > '\u00FF')
7005 // break;
7006 // da[dp++] = (byte) c;
7007 // }
7008 // return i;
7009 // }
7010 //
7011 // @IntrinsicCandidate
7012 // int java.lang.StringCoding.encodeAsciiArray0(
7013 // char[] sa, int sp, byte[] da, int dp, int len) {
7014 // int i = 0;
7015 // for (; i < len; i++) {
7016 // char c = sa[sp++];
7017 // if (c >= '\u0080')
7018 // break;
7019 // da[dp++] = (byte) c;
7020 // }
7021 // return i;
7022 // }
7023 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7024 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7025 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7026 Register tmp5, Register result, bool ascii) {
7027
7028 // rsi: src
7029 // rdi: dst
7030 // rdx: len
7031 // rcx: tmp5
7032 // rax: result
7033 ShortBranchVerifier sbv(this);
7034 assert_different_registers(src, dst, len, tmp5, result);
7035 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7036
7037 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
7038 int short_mask = ascii ? 0xff80 : 0xff00;
7039
7040 // set result
7041 xorl(result, result);
7042 // check for zero length
7043 testl(len, len);
7044 jcc(Assembler::zero, L_done);
7045
7046 movl(result, len);
7047
7048 // Setup pointers
7049 lea(src, Address(src, len, Address::times_2)); // char[]
7050 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7051 negptr(len);
7052
7053 if (UseSSE42Intrinsics || UseAVX >= 2) {
7054 Label L_copy_8_chars, L_copy_8_chars_exit;
7055 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7056
7057 if (UseAVX >= 2) {
7058 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7059 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7060 movdl(tmp1Reg, tmp5);
7061 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7062 jmp(L_chars_32_check);
7063
7064 bind(L_copy_32_chars);
7065 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7066 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7067 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7068 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7069 jccb(Assembler::notZero, L_copy_32_chars_exit);
7070 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7071 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7072 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7073
7074 bind(L_chars_32_check);
7075 addptr(len, 32);
7076 jcc(Assembler::lessEqual, L_copy_32_chars);
7077
7078 bind(L_copy_32_chars_exit);
7079 subptr(len, 16);
7080 jccb(Assembler::greater, L_copy_16_chars_exit);
7081
7082 } else if (UseSSE42Intrinsics) {
7083 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7084 movdl(tmp1Reg, tmp5);
7085 pshufd(tmp1Reg, tmp1Reg, 0);
7086 jmpb(L_chars_16_check);
7087 }
7088
7089 bind(L_copy_16_chars);
7090 if (UseAVX >= 2) {
7091 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7092 vptest(tmp2Reg, tmp1Reg);
7093 jcc(Assembler::notZero, L_copy_16_chars_exit);
7094 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7095 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7096 } else {
7097 if (UseAVX > 0) {
7098 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7099 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7100 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7101 } else {
7102 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7103 por(tmp2Reg, tmp3Reg);
7104 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7105 por(tmp2Reg, tmp4Reg);
7106 }
7107 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7108 jccb(Assembler::notZero, L_copy_16_chars_exit);
7109 packuswb(tmp3Reg, tmp4Reg);
7110 }
7111 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7112
7113 bind(L_chars_16_check);
7114 addptr(len, 16);
7115 jcc(Assembler::lessEqual, L_copy_16_chars);
7116
7117 bind(L_copy_16_chars_exit);
7118 if (UseAVX >= 2) {
7119 // clean upper bits of YMM registers
7120 vpxor(tmp2Reg, tmp2Reg);
7121 vpxor(tmp3Reg, tmp3Reg);
7122 vpxor(tmp4Reg, tmp4Reg);
7123 movdl(tmp1Reg, tmp5);
7124 pshufd(tmp1Reg, tmp1Reg, 0);
7125 }
7126 subptr(len, 8);
7127 jccb(Assembler::greater, L_copy_8_chars_exit);
7128
7129 bind(L_copy_8_chars);
7130 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7131 ptest(tmp3Reg, tmp1Reg);
7132 jccb(Assembler::notZero, L_copy_8_chars_exit);
7133 packuswb(tmp3Reg, tmp1Reg);
7134 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7135 addptr(len, 8);
7136 jccb(Assembler::lessEqual, L_copy_8_chars);
7137
7138 bind(L_copy_8_chars_exit);
7139 subptr(len, 8);
7140 jccb(Assembler::zero, L_done);
7141 }
7142
7143 bind(L_copy_1_char);
7144 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7145 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7146 jccb(Assembler::notZero, L_copy_1_char_exit);
7147 movb(Address(dst, len, Address::times_1, 0), tmp5);
7148 addptr(len, 1);
7149 jccb(Assembler::less, L_copy_1_char);
7150
7151 bind(L_copy_1_char_exit);
7152 addptr(result, len); // len is negative count of not processed elements
7153
7154 bind(L_done);
7155 }
7156
7157 /**
7158 * Helper for multiply_to_len().
7159 */
7160 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7161 addq(dest_lo, src1);
7162 adcq(dest_hi, 0);
7163 addq(dest_lo, src2);
7164 adcq(dest_hi, 0);
7165 }
7166
7167 /**
7168 * Multiply 64 bit by 64 bit first loop.
7169 */
7170 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7171 Register y, Register y_idx, Register z,
7172 Register carry, Register product,
7173 Register idx, Register kdx) {
7174 //
7175 // jlong carry, x[], y[], z[];
7176 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7177 // huge_128 product = y[idx] * x[xstart] + carry;
7178 // z[kdx] = (jlong)product;
7179 // carry = (jlong)(product >>> 64);
7180 // }
7181 // z[xstart] = carry;
7182 //
7183
7184 Label L_first_loop, L_first_loop_exit;
7185 Label L_one_x, L_one_y, L_multiply;
7186
7187 decrementl(xstart);
7188 jcc(Assembler::negative, L_one_x);
7189
7190 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7191 rorq(x_xstart, 32); // convert big-endian to little-endian
7192
7193 bind(L_first_loop);
7194 decrementl(idx);
7195 jcc(Assembler::negative, L_first_loop_exit);
7196 decrementl(idx);
7197 jcc(Assembler::negative, L_one_y);
7198 movq(y_idx, Address(y, idx, Address::times_4, 0));
7199 rorq(y_idx, 32); // convert big-endian to little-endian
7200 bind(L_multiply);
7201 movq(product, x_xstart);
7202 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7203 addq(product, carry);
7204 adcq(rdx, 0);
7205 subl(kdx, 2);
7206 movl(Address(z, kdx, Address::times_4, 4), product);
7207 shrq(product, 32);
7208 movl(Address(z, kdx, Address::times_4, 0), product);
7209 movq(carry, rdx);
7210 jmp(L_first_loop);
7211
7212 bind(L_one_y);
7213 movl(y_idx, Address(y, 0));
7214 jmp(L_multiply);
7215
7216 bind(L_one_x);
7217 movl(x_xstart, Address(x, 0));
7218 jmp(L_first_loop);
7219
7220 bind(L_first_loop_exit);
7221 }
7222
7223 /**
7224 * Multiply 64 bit by 64 bit and add 128 bit.
7225 */
7226 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7227 Register yz_idx, Register idx,
7228 Register carry, Register product, int offset) {
7229 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7230 // z[kdx] = (jlong)product;
7231
7232 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7233 rorq(yz_idx, 32); // convert big-endian to little-endian
7234 movq(product, x_xstart);
7235 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7236 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7237 rorq(yz_idx, 32); // convert big-endian to little-endian
7238
7239 add2_with_carry(rdx, product, carry, yz_idx);
7240
7241 movl(Address(z, idx, Address::times_4, offset+4), product);
7242 shrq(product, 32);
7243 movl(Address(z, idx, Address::times_4, offset), product);
7244
7245 }
7246
7247 /**
7248 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7249 */
7250 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7251 Register yz_idx, Register idx, Register jdx,
7252 Register carry, Register product,
7253 Register carry2) {
7254 // jlong carry, x[], y[], z[];
7255 // int kdx = ystart+1;
7256 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7257 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7258 // z[kdx+idx+1] = (jlong)product;
7259 // jlong carry2 = (jlong)(product >>> 64);
7260 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7261 // z[kdx+idx] = (jlong)product;
7262 // carry = (jlong)(product >>> 64);
7263 // }
7264 // idx += 2;
7265 // if (idx > 0) {
7266 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7267 // z[kdx+idx] = (jlong)product;
7268 // carry = (jlong)(product >>> 64);
7269 // }
7270 //
7271
7272 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7273
7274 movl(jdx, idx);
7275 andl(jdx, 0xFFFFFFFC);
7276 shrl(jdx, 2);
7277
7278 bind(L_third_loop);
7279 subl(jdx, 1);
7280 jcc(Assembler::negative, L_third_loop_exit);
7281 subl(idx, 4);
7282
7283 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7284 movq(carry2, rdx);
7285
7286 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7287 movq(carry, rdx);
7288 jmp(L_third_loop);
7289
7290 bind (L_third_loop_exit);
7291
7292 andl (idx, 0x3);
7293 jcc(Assembler::zero, L_post_third_loop_done);
7294
7295 Label L_check_1;
7296 subl(idx, 2);
7297 jcc(Assembler::negative, L_check_1);
7298
7299 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7300 movq(carry, rdx);
7301
7302 bind (L_check_1);
7303 addl (idx, 0x2);
7304 andl (idx, 0x1);
7305 subl(idx, 1);
7306 jcc(Assembler::negative, L_post_third_loop_done);
7307
7308 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7309 movq(product, x_xstart);
7310 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7311 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7312
7313 add2_with_carry(rdx, product, yz_idx, carry);
7314
7315 movl(Address(z, idx, Address::times_4, 0), product);
7316 shrq(product, 32);
7317
7318 shlq(rdx, 32);
7319 orq(product, rdx);
7320 movq(carry, product);
7321
7322 bind(L_post_third_loop_done);
7323 }
7324
7325 /**
7326 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7327 *
7328 */
7329 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7330 Register carry, Register carry2,
7331 Register idx, Register jdx,
7332 Register yz_idx1, Register yz_idx2,
7333 Register tmp, Register tmp3, Register tmp4) {
7334 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7335
7336 // jlong carry, x[], y[], z[];
7337 // int kdx = ystart+1;
7338 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7339 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7340 // jlong carry2 = (jlong)(tmp3 >>> 64);
7341 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7342 // carry = (jlong)(tmp4 >>> 64);
7343 // z[kdx+idx+1] = (jlong)tmp3;
7344 // z[kdx+idx] = (jlong)tmp4;
7345 // }
7346 // idx += 2;
7347 // if (idx > 0) {
7348 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7349 // z[kdx+idx] = (jlong)yz_idx1;
7350 // carry = (jlong)(yz_idx1 >>> 64);
7351 // }
7352 //
7353
7354 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7355
7356 movl(jdx, idx);
7357 andl(jdx, 0xFFFFFFFC);
7358 shrl(jdx, 2);
7359
7360 bind(L_third_loop);
7361 subl(jdx, 1);
7362 jcc(Assembler::negative, L_third_loop_exit);
7363 subl(idx, 4);
7364
7365 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7366 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7367 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7368 rorxq(yz_idx2, yz_idx2, 32);
7369
7370 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7371 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7372
7373 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7374 rorxq(yz_idx1, yz_idx1, 32);
7375 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7376 rorxq(yz_idx2, yz_idx2, 32);
7377
7378 if (VM_Version::supports_adx()) {
7379 adcxq(tmp3, carry);
7380 adoxq(tmp3, yz_idx1);
7381
7382 adcxq(tmp4, tmp);
7383 adoxq(tmp4, yz_idx2);
7384
7385 movl(carry, 0); // does not affect flags
7386 adcxq(carry2, carry);
7387 adoxq(carry2, carry);
7388 } else {
7389 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7390 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7391 }
7392 movq(carry, carry2);
7393
7394 movl(Address(z, idx, Address::times_4, 12), tmp3);
7395 shrq(tmp3, 32);
7396 movl(Address(z, idx, Address::times_4, 8), tmp3);
7397
7398 movl(Address(z, idx, Address::times_4, 4), tmp4);
7399 shrq(tmp4, 32);
7400 movl(Address(z, idx, Address::times_4, 0), tmp4);
7401
7402 jmp(L_third_loop);
7403
7404 bind (L_third_loop_exit);
7405
7406 andl (idx, 0x3);
7407 jcc(Assembler::zero, L_post_third_loop_done);
7408
7409 Label L_check_1;
7410 subl(idx, 2);
7411 jcc(Assembler::negative, L_check_1);
7412
7413 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7414 rorxq(yz_idx1, yz_idx1, 32);
7415 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7416 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7417 rorxq(yz_idx2, yz_idx2, 32);
7418
7419 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7420
7421 movl(Address(z, idx, Address::times_4, 4), tmp3);
7422 shrq(tmp3, 32);
7423 movl(Address(z, idx, Address::times_4, 0), tmp3);
7424 movq(carry, tmp4);
7425
7426 bind (L_check_1);
7427 addl (idx, 0x2);
7428 andl (idx, 0x1);
7429 subl(idx, 1);
7430 jcc(Assembler::negative, L_post_third_loop_done);
7431 movl(tmp4, Address(y, idx, Address::times_4, 0));
7432 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7433 movl(tmp4, Address(z, idx, Address::times_4, 0));
7434
7435 add2_with_carry(carry2, tmp3, tmp4, carry);
7436
7437 movl(Address(z, idx, Address::times_4, 0), tmp3);
7438 shrq(tmp3, 32);
7439
7440 shlq(carry2, 32);
7441 orq(tmp3, carry2);
7442 movq(carry, tmp3);
7443
7444 bind(L_post_third_loop_done);
7445 }
7446
7447 /**
7448 * Code for BigInteger::multiplyToLen() intrinsic.
7449 *
7450 * rdi: x
7451 * rax: xlen
7452 * rsi: y
7453 * rcx: ylen
7454 * r8: z
7455 * r11: tmp0
7456 * r12: tmp1
7457 * r13: tmp2
7458 * r14: tmp3
7459 * r15: tmp4
7460 * rbx: tmp5
7461 *
7462 */
7463 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7464 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7465 ShortBranchVerifier sbv(this);
7466 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7467
7468 push(tmp0);
7469 push(tmp1);
7470 push(tmp2);
7471 push(tmp3);
7472 push(tmp4);
7473 push(tmp5);
7474
7475 push(xlen);
7476
7477 const Register idx = tmp1;
7478 const Register kdx = tmp2;
7479 const Register xstart = tmp3;
7480
7481 const Register y_idx = tmp4;
7482 const Register carry = tmp5;
7483 const Register product = xlen;
7484 const Register x_xstart = tmp0;
7485
7486 // First Loop.
7487 //
7488 // final static long LONG_MASK = 0xffffffffL;
7489 // int xstart = xlen - 1;
7490 // int ystart = ylen - 1;
7491 // long carry = 0;
7492 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7493 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7494 // z[kdx] = (int)product;
7495 // carry = product >>> 32;
7496 // }
7497 // z[xstart] = (int)carry;
7498 //
7499
7500 movl(idx, ylen); // idx = ylen;
7501 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7502 xorq(carry, carry); // carry = 0;
7503
7504 Label L_done;
7505
7506 movl(xstart, xlen);
7507 decrementl(xstart);
7508 jcc(Assembler::negative, L_done);
7509
7510 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7511
7512 Label L_second_loop;
7513 testl(kdx, kdx);
7514 jcc(Assembler::zero, L_second_loop);
7515
7516 Label L_carry;
7517 subl(kdx, 1);
7518 jcc(Assembler::zero, L_carry);
7519
7520 movl(Address(z, kdx, Address::times_4, 0), carry);
7521 shrq(carry, 32);
7522 subl(kdx, 1);
7523
7524 bind(L_carry);
7525 movl(Address(z, kdx, Address::times_4, 0), carry);
7526
7527 // Second and third (nested) loops.
7528 //
7529 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7530 // carry = 0;
7531 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7532 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7533 // (z[k] & LONG_MASK) + carry;
7534 // z[k] = (int)product;
7535 // carry = product >>> 32;
7536 // }
7537 // z[i] = (int)carry;
7538 // }
7539 //
7540 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7541
7542 const Register jdx = tmp1;
7543
7544 bind(L_second_loop);
7545 xorl(carry, carry); // carry = 0;
7546 movl(jdx, ylen); // j = ystart+1
7547
7548 subl(xstart, 1); // i = xstart-1;
7549 jcc(Assembler::negative, L_done);
7550
7551 push (z);
7552
7553 Label L_last_x;
7554 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7555 subl(xstart, 1); // i = xstart-1;
7556 jcc(Assembler::negative, L_last_x);
7557
7558 if (UseBMI2Instructions) {
7559 movq(rdx, Address(x, xstart, Address::times_4, 0));
7560 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7561 } else {
7562 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7563 rorq(x_xstart, 32); // convert big-endian to little-endian
7564 }
7565
7566 Label L_third_loop_prologue;
7567 bind(L_third_loop_prologue);
7568
7569 push (x);
7570 push (xstart);
7571 push (ylen);
7572
7573
7574 if (UseBMI2Instructions) {
7575 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7576 } else { // !UseBMI2Instructions
7577 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7578 }
7579
7580 pop(ylen);
7581 pop(xlen);
7582 pop(x);
7583 pop(z);
7584
7585 movl(tmp3, xlen);
7586 addl(tmp3, 1);
7587 movl(Address(z, tmp3, Address::times_4, 0), carry);
7588 subl(tmp3, 1);
7589 jccb(Assembler::negative, L_done);
7590
7591 shrq(carry, 32);
7592 movl(Address(z, tmp3, Address::times_4, 0), carry);
7593 jmp(L_second_loop);
7594
7595 // Next infrequent code is moved outside loops.
7596 bind(L_last_x);
7597 if (UseBMI2Instructions) {
7598 movl(rdx, Address(x, 0));
7599 } else {
7600 movl(x_xstart, Address(x, 0));
7601 }
7602 jmp(L_third_loop_prologue);
7603
7604 bind(L_done);
7605
7606 pop(xlen);
7607
7608 pop(tmp5);
7609 pop(tmp4);
7610 pop(tmp3);
7611 pop(tmp2);
7612 pop(tmp1);
7613 pop(tmp0);
7614 }
7615
7616 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7617 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7618 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7619 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7620 Label VECTOR8_TAIL, VECTOR4_TAIL;
7621 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7622 Label SAME_TILL_END, DONE;
7623 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7624
7625 //scale is in rcx in both Win64 and Unix
7626 ShortBranchVerifier sbv(this);
7627
7628 shlq(length);
7629 xorq(result, result);
7630
7631 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7632 VM_Version::supports_avx512vlbw() && UseCountTrailingZerosInstruction) {
7633 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7634
7635 cmpq(length, 64);
7636 jcc(Assembler::less, VECTOR32_TAIL);
7637
7638 movq(tmp1, length);
7639 andq(tmp1, 0x3F); // tail count
7640 andq(length, ~(0x3F)); //vector count
7641
7642 bind(VECTOR64_LOOP);
7643 // AVX512 code to compare 64 byte vectors.
7644 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7645 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7646 kortestql(k7, k7);
7647 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7648 addq(result, 64);
7649 subq(length, 64);
7650 jccb(Assembler::notZero, VECTOR64_LOOP);
7651
7652 //bind(VECTOR64_TAIL);
7653 testq(tmp1, tmp1);
7654 jcc(Assembler::zero, SAME_TILL_END);
7655
7656 //bind(VECTOR64_TAIL);
7657 // AVX512 code to compare up to 63 byte vectors.
7658 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7659 shlxq(tmp2, tmp2, tmp1);
7660 notq(tmp2);
7661 kmovql(k3, tmp2);
7662
7663 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7664 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7665
7666 ktestql(k7, k3);
7667 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7668
7669 bind(VECTOR64_NOT_EQUAL);
7670 kmovql(tmp1, k7);
7671 notq(tmp1);
7672 tzcntq(tmp1, tmp1);
7673 addq(result, tmp1);
7674 shrq(result);
7675 jmp(DONE);
7676 bind(VECTOR32_TAIL);
7677 }
7678
7679 cmpq(length, 8);
7680 jcc(Assembler::equal, VECTOR8_LOOP);
7681 jcc(Assembler::less, VECTOR4_TAIL);
7682
7683 if (UseAVX >= 2) {
7684 Label VECTOR16_TAIL, VECTOR32_LOOP;
7685
7686 cmpq(length, 16);
7687 jcc(Assembler::equal, VECTOR16_LOOP);
7688 jcc(Assembler::less, VECTOR8_LOOP);
7689
7690 cmpq(length, 32);
7691 jccb(Assembler::less, VECTOR16_TAIL);
7692
7693 subq(length, 32);
7694 bind(VECTOR32_LOOP);
7695 vmovdqu(rymm0, Address(obja, result));
7696 vmovdqu(rymm1, Address(objb, result));
7697 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7698 vptest(rymm2, rymm2);
7699 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7700 addq(result, 32);
7701 subq(length, 32);
7702 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7703 addq(length, 32);
7704 jcc(Assembler::equal, SAME_TILL_END);
7705 //falling through if less than 32 bytes left //close the branch here.
7706
7707 bind(VECTOR16_TAIL);
7708 cmpq(length, 16);
7709 jccb(Assembler::less, VECTOR8_TAIL);
7710 bind(VECTOR16_LOOP);
7711 movdqu(rymm0, Address(obja, result));
7712 movdqu(rymm1, Address(objb, result));
7713 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7714 ptest(rymm2, rymm2);
7715 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7716 addq(result, 16);
7717 subq(length, 16);
7718 jcc(Assembler::equal, SAME_TILL_END);
7719 //falling through if less than 16 bytes left
7720 } else {//regular intrinsics
7721
7722 cmpq(length, 16);
7723 jccb(Assembler::less, VECTOR8_TAIL);
7724
7725 subq(length, 16);
7726 bind(VECTOR16_LOOP);
7727 movdqu(rymm0, Address(obja, result));
7728 movdqu(rymm1, Address(objb, result));
7729 pxor(rymm0, rymm1);
7730 ptest(rymm0, rymm0);
7731 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7732 addq(result, 16);
7733 subq(length, 16);
7734 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7735 addq(length, 16);
7736 jcc(Assembler::equal, SAME_TILL_END);
7737 //falling through if less than 16 bytes left
7738 }
7739
7740 bind(VECTOR8_TAIL);
7741 cmpq(length, 8);
7742 jccb(Assembler::less, VECTOR4_TAIL);
7743 bind(VECTOR8_LOOP);
7744 movq(tmp1, Address(obja, result));
7745 movq(tmp2, Address(objb, result));
7746 xorq(tmp1, tmp2);
7747 testq(tmp1, tmp1);
7748 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7749 addq(result, 8);
7750 subq(length, 8);
7751 jcc(Assembler::equal, SAME_TILL_END);
7752 //falling through if less than 8 bytes left
7753
7754 bind(VECTOR4_TAIL);
7755 cmpq(length, 4);
7756 jccb(Assembler::less, BYTES_TAIL);
7757 bind(VECTOR4_LOOP);
7758 movl(tmp1, Address(obja, result));
7759 xorl(tmp1, Address(objb, result));
7760 testl(tmp1, tmp1);
7761 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7762 addq(result, 4);
7763 subq(length, 4);
7764 jcc(Assembler::equal, SAME_TILL_END);
7765 //falling through if less than 4 bytes left
7766
7767 bind(BYTES_TAIL);
7768 bind(BYTES_LOOP);
7769 load_unsigned_byte(tmp1, Address(obja, result));
7770 load_unsigned_byte(tmp2, Address(objb, result));
7771 xorl(tmp1, tmp2);
7772 testl(tmp1, tmp1);
7773 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7774 decq(length);
7775 jcc(Assembler::zero, SAME_TILL_END);
7776 incq(result);
7777 load_unsigned_byte(tmp1, Address(obja, result));
7778 load_unsigned_byte(tmp2, Address(objb, result));
7779 xorl(tmp1, tmp2);
7780 testl(tmp1, tmp1);
7781 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7782 decq(length);
7783 jcc(Assembler::zero, SAME_TILL_END);
7784 incq(result);
7785 load_unsigned_byte(tmp1, Address(obja, result));
7786 load_unsigned_byte(tmp2, Address(objb, result));
7787 xorl(tmp1, tmp2);
7788 testl(tmp1, tmp1);
7789 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7790 jmp(SAME_TILL_END);
7791
7792 if (UseAVX >= 2) {
7793 bind(VECTOR32_NOT_EQUAL);
7794 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7795 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7796 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7797 vpmovmskb(tmp1, rymm0);
7798 bsfq(tmp1, tmp1);
7799 addq(result, tmp1);
7800 shrq(result);
7801 jmp(DONE);
7802 }
7803
7804 bind(VECTOR16_NOT_EQUAL);
7805 if (UseAVX >= 2) {
7806 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7807 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7808 pxor(rymm0, rymm2);
7809 } else {
7810 pcmpeqb(rymm2, rymm2);
7811 pxor(rymm0, rymm1);
7812 pcmpeqb(rymm0, rymm1);
7813 pxor(rymm0, rymm2);
7814 }
7815 pmovmskb(tmp1, rymm0);
7816 bsfq(tmp1, tmp1);
7817 addq(result, tmp1);
7818 shrq(result);
7819 jmpb(DONE);
7820
7821 bind(VECTOR8_NOT_EQUAL);
7822 bind(VECTOR4_NOT_EQUAL);
7823 bsfq(tmp1, tmp1);
7824 shrq(tmp1, 3);
7825 addq(result, tmp1);
7826 bind(BYTES_NOT_EQUAL);
7827 shrq(result);
7828 jmpb(DONE);
7829
7830 bind(SAME_TILL_END);
7831 mov64(result, -1);
7832
7833 bind(DONE);
7834 }
7835
7836 //Helper functions for square_to_len()
7837
7838 /**
7839 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7840 * Preserves x and z and modifies rest of the registers.
7841 */
7842 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7843 // Perform square and right shift by 1
7844 // Handle odd xlen case first, then for even xlen do the following
7845 // jlong carry = 0;
7846 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7847 // huge_128 product = x[j:j+1] * x[j:j+1];
7848 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7849 // z[i+2:i+3] = (jlong)(product >>> 1);
7850 // carry = (jlong)product;
7851 // }
7852
7853 xorq(tmp5, tmp5); // carry
7854 xorq(rdxReg, rdxReg);
7855 xorl(tmp1, tmp1); // index for x
7856 xorl(tmp4, tmp4); // index for z
7857
7858 Label L_first_loop, L_first_loop_exit;
7859
7860 testl(xlen, 1);
7861 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7862
7863 // Square and right shift by 1 the odd element using 32 bit multiply
7864 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7865 imulq(raxReg, raxReg);
7866 shrq(raxReg, 1);
7867 adcq(tmp5, 0);
7868 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7869 incrementl(tmp1);
7870 addl(tmp4, 2);
7871
7872 // Square and right shift by 1 the rest using 64 bit multiply
7873 bind(L_first_loop);
7874 cmpptr(tmp1, xlen);
7875 jccb(Assembler::equal, L_first_loop_exit);
7876
7877 // Square
7878 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7879 rorq(raxReg, 32); // convert big-endian to little-endian
7880 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7881
7882 // Right shift by 1 and save carry
7883 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7884 rcrq(rdxReg, 1);
7885 rcrq(raxReg, 1);
7886 adcq(tmp5, 0);
7887
7888 // Store result in z
7889 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7890 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7891
7892 // Update indices for x and z
7893 addl(tmp1, 2);
7894 addl(tmp4, 4);
7895 jmp(L_first_loop);
7896
7897 bind(L_first_loop_exit);
7898 }
7899
7900
7901 /**
7902 * Perform the following multiply add operation using BMI2 instructions
7903 * carry:sum = sum + op1*op2 + carry
7904 * op2 should be in rdx
7905 * op2 is preserved, all other registers are modified
7906 */
7907 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7908 // assert op2 is rdx
7909 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7910 addq(sum, carry);
7911 adcq(tmp2, 0);
7912 addq(sum, op1);
7913 adcq(tmp2, 0);
7914 movq(carry, tmp2);
7915 }
7916
7917 /**
7918 * Perform the following multiply add operation:
7919 * carry:sum = sum + op1*op2 + carry
7920 * Preserves op1, op2 and modifies rest of registers
7921 */
7922 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7923 // rdx:rax = op1 * op2
7924 movq(raxReg, op2);
7925 mulq(op1);
7926
7927 // rdx:rax = sum + carry + rdx:rax
7928 addq(sum, carry);
7929 adcq(rdxReg, 0);
7930 addq(sum, raxReg);
7931 adcq(rdxReg, 0);
7932
7933 // carry:sum = rdx:sum
7934 movq(carry, rdxReg);
7935 }
7936
7937 /**
7938 * Add 64 bit long carry into z[] with carry propagation.
7939 * Preserves z and carry register values and modifies rest of registers.
7940 *
7941 */
7942 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7943 Label L_fourth_loop, L_fourth_loop_exit;
7944
7945 movl(tmp1, 1);
7946 subl(zlen, 2);
7947 addq(Address(z, zlen, Address::times_4, 0), carry);
7948
7949 bind(L_fourth_loop);
7950 jccb(Assembler::carryClear, L_fourth_loop_exit);
7951 subl(zlen, 2);
7952 jccb(Assembler::negative, L_fourth_loop_exit);
7953 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7954 jmp(L_fourth_loop);
7955 bind(L_fourth_loop_exit);
7956 }
7957
7958 /**
7959 * Shift z[] left by 1 bit.
7960 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7961 *
7962 */
7963 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7964
7965 Label L_fifth_loop, L_fifth_loop_exit;
7966
7967 // Fifth loop
7968 // Perform primitiveLeftShift(z, zlen, 1)
7969
7970 const Register prev_carry = tmp1;
7971 const Register new_carry = tmp4;
7972 const Register value = tmp2;
7973 const Register zidx = tmp3;
7974
7975 // int zidx, carry;
7976 // long value;
7977 // carry = 0;
7978 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7979 // (carry:value) = (z[i] << 1) | carry ;
7980 // z[i] = value;
7981 // }
7982
7983 movl(zidx, zlen);
7984 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7985
7986 bind(L_fifth_loop);
7987 decl(zidx); // Use decl to preserve carry flag
7988 decl(zidx);
7989 jccb(Assembler::negative, L_fifth_loop_exit);
7990
7991 if (UseBMI2Instructions) {
7992 movq(value, Address(z, zidx, Address::times_4, 0));
7993 rclq(value, 1);
7994 rorxq(value, value, 32);
7995 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7996 }
7997 else {
7998 // clear new_carry
7999 xorl(new_carry, new_carry);
8000
8001 // Shift z[i] by 1, or in previous carry and save new carry
8002 movq(value, Address(z, zidx, Address::times_4, 0));
8003 shlq(value, 1);
8004 adcl(new_carry, 0);
8005
8006 orq(value, prev_carry);
8007 rorq(value, 0x20);
8008 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8009
8010 // Set previous carry = new carry
8011 movl(prev_carry, new_carry);
8012 }
8013 jmp(L_fifth_loop);
8014
8015 bind(L_fifth_loop_exit);
8016 }
8017
8018
8019 /**
8020 * Code for BigInteger::squareToLen() intrinsic
8021 *
8022 * rdi: x
8023 * rsi: len
8024 * r8: z
8025 * rcx: zlen
8026 * r12: tmp1
8027 * r13: tmp2
8028 * r14: tmp3
8029 * r15: tmp4
8030 * rbx: tmp5
8031 *
8032 */
8033 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8034
8035 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8036 push(tmp1);
8037 push(tmp2);
8038 push(tmp3);
8039 push(tmp4);
8040 push(tmp5);
8041
8042 // First loop
8043 // Store the squares, right shifted one bit (i.e., divided by 2).
8044 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8045
8046 // Add in off-diagonal sums.
8047 //
8048 // Second, third (nested) and fourth loops.
8049 // zlen +=2;
8050 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8051 // carry = 0;
8052 // long op2 = x[xidx:xidx+1];
8053 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8054 // k -= 2;
8055 // long op1 = x[j:j+1];
8056 // long sum = z[k:k+1];
8057 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8058 // z[k:k+1] = sum;
8059 // }
8060 // add_one_64(z, k, carry, tmp_regs);
8061 // }
8062
8063 const Register carry = tmp5;
8064 const Register sum = tmp3;
8065 const Register op1 = tmp4;
8066 Register op2 = tmp2;
8067
8068 push(zlen);
8069 push(len);
8070 addl(zlen,2);
8071 bind(L_second_loop);
8072 xorq(carry, carry);
8073 subl(zlen, 4);
8074 subl(len, 2);
8075 push(zlen);
8076 push(len);
8077 cmpl(len, 0);
8078 jccb(Assembler::lessEqual, L_second_loop_exit);
8079
8080 // Multiply an array by one 64 bit long.
8081 if (UseBMI2Instructions) {
8082 op2 = rdxReg;
8083 movq(op2, Address(x, len, Address::times_4, 0));
8084 rorxq(op2, op2, 32);
8085 }
8086 else {
8087 movq(op2, Address(x, len, Address::times_4, 0));
8088 rorq(op2, 32);
8089 }
8090
8091 bind(L_third_loop);
8092 decrementl(len);
8093 jccb(Assembler::negative, L_third_loop_exit);
8094 decrementl(len);
8095 jccb(Assembler::negative, L_last_x);
8096
8097 movq(op1, Address(x, len, Address::times_4, 0));
8098 rorq(op1, 32);
8099
8100 bind(L_multiply);
8101 subl(zlen, 2);
8102 movq(sum, Address(z, zlen, Address::times_4, 0));
8103
8104 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8105 if (UseBMI2Instructions) {
8106 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8107 }
8108 else {
8109 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8110 }
8111
8112 movq(Address(z, zlen, Address::times_4, 0), sum);
8113
8114 jmp(L_third_loop);
8115 bind(L_third_loop_exit);
8116
8117 // Fourth loop
8118 // Add 64 bit long carry into z with carry propagation.
8119 // Uses offsetted zlen.
8120 add_one_64(z, zlen, carry, tmp1);
8121
8122 pop(len);
8123 pop(zlen);
8124 jmp(L_second_loop);
8125
8126 // Next infrequent code is moved outside loops.
8127 bind(L_last_x);
8128 movl(op1, Address(x, 0));
8129 jmp(L_multiply);
8130
8131 bind(L_second_loop_exit);
8132 pop(len);
8133 pop(zlen);
8134 pop(len);
8135 pop(zlen);
8136
8137 // Fifth loop
8138 // Shift z left 1 bit.
8139 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8140
8141 // z[zlen-1] |= x[len-1] & 1;
8142 movl(tmp3, Address(x, len, Address::times_4, -4));
8143 andl(tmp3, 1);
8144 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8145
8146 pop(tmp5);
8147 pop(tmp4);
8148 pop(tmp3);
8149 pop(tmp2);
8150 pop(tmp1);
8151 }
8152
8153 /**
8154 * Helper function for mul_add()
8155 * Multiply the in[] by int k and add to out[] starting at offset offs using
8156 * 128 bit by 32 bit multiply and return the carry in tmp5.
8157 * Only quad int aligned length of in[] is operated on in this function.
8158 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8159 * This function preserves out, in and k registers.
8160 * len and offset point to the appropriate index in "in" & "out" correspondingly
8161 * tmp5 has the carry.
8162 * other registers are temporary and are modified.
8163 *
8164 */
8165 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8166 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8167 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8168
8169 Label L_first_loop, L_first_loop_exit;
8170
8171 movl(tmp1, len);
8172 shrl(tmp1, 2);
8173
8174 bind(L_first_loop);
8175 subl(tmp1, 1);
8176 jccb(Assembler::negative, L_first_loop_exit);
8177
8178 subl(len, 4);
8179 subl(offset, 4);
8180
8181 Register op2 = tmp2;
8182 const Register sum = tmp3;
8183 const Register op1 = tmp4;
8184 const Register carry = tmp5;
8185
8186 if (UseBMI2Instructions) {
8187 op2 = rdxReg;
8188 }
8189
8190 movq(op1, Address(in, len, Address::times_4, 8));
8191 rorq(op1, 32);
8192 movq(sum, Address(out, offset, Address::times_4, 8));
8193 rorq(sum, 32);
8194 if (UseBMI2Instructions) {
8195 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8196 }
8197 else {
8198 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8199 }
8200 // Store back in big endian from little endian
8201 rorq(sum, 0x20);
8202 movq(Address(out, offset, Address::times_4, 8), sum);
8203
8204 movq(op1, Address(in, len, Address::times_4, 0));
8205 rorq(op1, 32);
8206 movq(sum, Address(out, offset, Address::times_4, 0));
8207 rorq(sum, 32);
8208 if (UseBMI2Instructions) {
8209 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8210 }
8211 else {
8212 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8213 }
8214 // Store back in big endian from little endian
8215 rorq(sum, 0x20);
8216 movq(Address(out, offset, Address::times_4, 0), sum);
8217
8218 jmp(L_first_loop);
8219 bind(L_first_loop_exit);
8220 }
8221
8222 /**
8223 * Code for BigInteger::mulAdd() intrinsic
8224 *
8225 * rdi: out
8226 * rsi: in
8227 * r11: offs (out.length - offset)
8228 * rcx: len
8229 * r8: k
8230 * r12: tmp1
8231 * r13: tmp2
8232 * r14: tmp3
8233 * r15: tmp4
8234 * rbx: tmp5
8235 * Multiply the in[] by word k and add to out[], return the carry in rax
8236 */
8237 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8238 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8239 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8240
8241 Label L_carry, L_last_in, L_done;
8242
8243 // carry = 0;
8244 // for (int j=len-1; j >= 0; j--) {
8245 // long product = (in[j] & LONG_MASK) * kLong +
8246 // (out[offs] & LONG_MASK) + carry;
8247 // out[offs--] = (int)product;
8248 // carry = product >>> 32;
8249 // }
8250 //
8251 push(tmp1);
8252 push(tmp2);
8253 push(tmp3);
8254 push(tmp4);
8255 push(tmp5);
8256
8257 Register op2 = tmp2;
8258 const Register sum = tmp3;
8259 const Register op1 = tmp4;
8260 const Register carry = tmp5;
8261
8262 if (UseBMI2Instructions) {
8263 op2 = rdxReg;
8264 movl(op2, k);
8265 }
8266 else {
8267 movl(op2, k);
8268 }
8269
8270 xorq(carry, carry);
8271
8272 //First loop
8273
8274 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8275 //The carry is in tmp5
8276 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8277
8278 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8279 decrementl(len);
8280 jccb(Assembler::negative, L_carry);
8281 decrementl(len);
8282 jccb(Assembler::negative, L_last_in);
8283
8284 movq(op1, Address(in, len, Address::times_4, 0));
8285 rorq(op1, 32);
8286
8287 subl(offs, 2);
8288 movq(sum, Address(out, offs, Address::times_4, 0));
8289 rorq(sum, 32);
8290
8291 if (UseBMI2Instructions) {
8292 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8293 }
8294 else {
8295 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8296 }
8297
8298 // Store back in big endian from little endian
8299 rorq(sum, 0x20);
8300 movq(Address(out, offs, Address::times_4, 0), sum);
8301
8302 testl(len, len);
8303 jccb(Assembler::zero, L_carry);
8304
8305 //Multiply the last in[] entry, if any
8306 bind(L_last_in);
8307 movl(op1, Address(in, 0));
8308 movl(sum, Address(out, offs, Address::times_4, -4));
8309
8310 movl(raxReg, k);
8311 mull(op1); //tmp4 * eax -> edx:eax
8312 addl(sum, carry);
8313 adcl(rdxReg, 0);
8314 addl(sum, raxReg);
8315 adcl(rdxReg, 0);
8316 movl(carry, rdxReg);
8317
8318 movl(Address(out, offs, Address::times_4, -4), sum);
8319
8320 bind(L_carry);
8321 //return tmp5/carry as carry in rax
8322 movl(rax, carry);
8323
8324 bind(L_done);
8325 pop(tmp5);
8326 pop(tmp4);
8327 pop(tmp3);
8328 pop(tmp2);
8329 pop(tmp1);
8330 }
8331
8332 /**
8333 * Emits code to update CRC-32 with a byte value according to constants in table
8334 *
8335 * @param [in,out]crc Register containing the crc.
8336 * @param [in]val Register containing the byte to fold into the CRC.
8337 * @param [in]table Register containing the table of crc constants.
8338 *
8339 * uint32_t crc;
8340 * val = crc_table[(val ^ crc) & 0xFF];
8341 * crc = val ^ (crc >> 8);
8342 *
8343 */
8344 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8345 xorl(val, crc);
8346 andl(val, 0xFF);
8347 shrl(crc, 8); // unsigned shift
8348 xorl(crc, Address(table, val, Address::times_4, 0));
8349 }
8350
8351 /**
8352 * Fold 128-bit data chunk
8353 */
8354 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8355 if (UseAVX > 0) {
8356 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8357 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8358 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8359 pxor(xcrc, xtmp);
8360 } else {
8361 movdqa(xtmp, xcrc);
8362 pclmulhdq(xtmp, xK); // [123:64]
8363 pclmulldq(xcrc, xK); // [63:0]
8364 pxor(xcrc, xtmp);
8365 movdqu(xtmp, Address(buf, offset));
8366 pxor(xcrc, xtmp);
8367 }
8368 }
8369
8370 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8371 if (UseAVX > 0) {
8372 vpclmulhdq(xtmp, xK, xcrc);
8373 vpclmulldq(xcrc, xK, xcrc);
8374 pxor(xcrc, xbuf);
8375 pxor(xcrc, xtmp);
8376 } else {
8377 movdqa(xtmp, xcrc);
8378 pclmulhdq(xtmp, xK);
8379 pclmulldq(xcrc, xK);
8380 pxor(xcrc, xbuf);
8381 pxor(xcrc, xtmp);
8382 }
8383 }
8384
8385 /**
8386 * 8-bit folds to compute 32-bit CRC
8387 *
8388 * uint64_t xcrc;
8389 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8390 */
8391 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8392 movdl(tmp, xcrc);
8393 andl(tmp, 0xFF);
8394 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8395 psrldq(xcrc, 1); // unsigned shift one byte
8396 pxor(xcrc, xtmp);
8397 }
8398
8399 /**
8400 * uint32_t crc;
8401 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8402 */
8403 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8404 movl(tmp, crc);
8405 andl(tmp, 0xFF);
8406 shrl(crc, 8);
8407 xorl(crc, Address(table, tmp, Address::times_4, 0));
8408 }
8409
8410 /**
8411 * @param crc register containing existing CRC (32-bit)
8412 * @param buf register pointing to input byte buffer (byte*)
8413 * @param len register containing number of bytes
8414 * @param table register that will contain address of CRC table
8415 * @param tmp scratch register
8416 */
8417 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8418 assert_different_registers(crc, buf, len, table, tmp, rax);
8419
8420 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8421 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8422
8423 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8424 // context for the registers used, where all instructions below are using 128-bit mode
8425 // On EVEX without VL and BW, these instructions will all be AVX.
8426 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8427 notl(crc); // ~crc
8428 cmpl(len, 16);
8429 jcc(Assembler::less, L_tail);
8430
8431 // Align buffer to 16 bytes
8432 movl(tmp, buf);
8433 andl(tmp, 0xF);
8434 jccb(Assembler::zero, L_aligned);
8435 subl(tmp, 16);
8436 addl(len, tmp);
8437
8438 align(4);
8439 BIND(L_align_loop);
8440 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8441 update_byte_crc32(crc, rax, table);
8442 increment(buf);
8443 incrementl(tmp);
8444 jccb(Assembler::less, L_align_loop);
8445
8446 BIND(L_aligned);
8447 movl(tmp, len); // save
8448 shrl(len, 4);
8449 jcc(Assembler::zero, L_tail_restore);
8450
8451 // Fold crc into first bytes of vector
8452 movdqa(xmm1, Address(buf, 0));
8453 movdl(rax, xmm1);
8454 xorl(crc, rax);
8455 if (VM_Version::supports_sse4_1()) {
8456 pinsrd(xmm1, crc, 0);
8457 } else {
8458 pinsrw(xmm1, crc, 0);
8459 shrl(crc, 16);
8460 pinsrw(xmm1, crc, 1);
8461 }
8462 addptr(buf, 16);
8463 subl(len, 4); // len > 0
8464 jcc(Assembler::less, L_fold_tail);
8465
8466 movdqa(xmm2, Address(buf, 0));
8467 movdqa(xmm3, Address(buf, 16));
8468 movdqa(xmm4, Address(buf, 32));
8469 addptr(buf, 48);
8470 subl(len, 3);
8471 jcc(Assembler::lessEqual, L_fold_512b);
8472
8473 // Fold total 512 bits of polynomial on each iteration,
8474 // 128 bits per each of 4 parallel streams.
8475 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8476
8477 align32();
8478 BIND(L_fold_512b_loop);
8479 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8480 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8481 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8482 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8483 addptr(buf, 64);
8484 subl(len, 4);
8485 jcc(Assembler::greater, L_fold_512b_loop);
8486
8487 // Fold 512 bits to 128 bits.
8488 BIND(L_fold_512b);
8489 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8490 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8491 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8492 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8493
8494 // Fold the rest of 128 bits data chunks
8495 BIND(L_fold_tail);
8496 addl(len, 3);
8497 jccb(Assembler::lessEqual, L_fold_128b);
8498 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8499
8500 BIND(L_fold_tail_loop);
8501 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8502 addptr(buf, 16);
8503 decrementl(len);
8504 jccb(Assembler::greater, L_fold_tail_loop);
8505
8506 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8507 BIND(L_fold_128b);
8508 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8509 if (UseAVX > 0) {
8510 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8511 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8512 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8513 } else {
8514 movdqa(xmm2, xmm0);
8515 pclmulqdq(xmm2, xmm1, 0x1);
8516 movdqa(xmm3, xmm0);
8517 pand(xmm3, xmm2);
8518 pclmulqdq(xmm0, xmm3, 0x1);
8519 }
8520 psrldq(xmm1, 8);
8521 psrldq(xmm2, 4);
8522 pxor(xmm0, xmm1);
8523 pxor(xmm0, xmm2);
8524
8525 // 8 8-bit folds to compute 32-bit CRC.
8526 for (int j = 0; j < 4; j++) {
8527 fold_8bit_crc32(xmm0, table, xmm1, rax);
8528 }
8529 movdl(crc, xmm0); // mov 32 bits to general register
8530 for (int j = 0; j < 4; j++) {
8531 fold_8bit_crc32(crc, table, rax);
8532 }
8533
8534 BIND(L_tail_restore);
8535 movl(len, tmp); // restore
8536 BIND(L_tail);
8537 andl(len, 0xf);
8538 jccb(Assembler::zero, L_exit);
8539
8540 // Fold the rest of bytes
8541 align(4);
8542 BIND(L_tail_loop);
8543 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8544 update_byte_crc32(crc, rax, table);
8545 increment(buf);
8546 decrementl(len);
8547 jccb(Assembler::greater, L_tail_loop);
8548
8549 BIND(L_exit);
8550 notl(crc); // ~c
8551 }
8552
8553 // Helper function for AVX 512 CRC32
8554 // Fold 512-bit data chunks
8555 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8556 Register pos, int offset) {
8557 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8558 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8559 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8560 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8561 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8562 }
8563
8564 // Helper function for AVX 512 CRC32
8565 // Compute CRC32 for < 256B buffers
8566 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8567 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8568 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8569
8570 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8571 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8572 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8573
8574 // check if there is enough buffer to be able to fold 16B at a time
8575 cmpl(len, 32);
8576 jcc(Assembler::less, L_less_than_32);
8577
8578 // if there is, load the constants
8579 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8580 movdl(xmm0, crc); // get the initial crc value
8581 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8582 pxor(xmm7, xmm0);
8583
8584 // update the buffer pointer
8585 addl(pos, 16);
8586 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8587 subl(len, 32);
8588 jmp(L_16B_reduction_loop);
8589
8590 bind(L_less_than_32);
8591 //mov initial crc to the return value. this is necessary for zero - length buffers.
8592 movl(rax, crc);
8593 testl(len, len);
8594 jcc(Assembler::equal, L_cleanup);
8595
8596 movdl(xmm0, crc); //get the initial crc value
8597
8598 cmpl(len, 16);
8599 jcc(Assembler::equal, L_exact_16_left);
8600 jcc(Assembler::less, L_less_than_16_left);
8601
8602 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8603 pxor(xmm7, xmm0); //xor the initial crc value
8604 addl(pos, 16);
8605 subl(len, 16);
8606 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8607 jmp(L_get_last_two_xmms);
8608
8609 bind(L_less_than_16_left);
8610 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8611 pxor(xmm1, xmm1);
8612 movptr(tmp1, rsp);
8613 movdqu(Address(tmp1, 0 * 16), xmm1);
8614
8615 cmpl(len, 4);
8616 jcc(Assembler::less, L_only_less_than_4);
8617
8618 //backup the counter value
8619 movl(tmp2, len);
8620 cmpl(len, 8);
8621 jcc(Assembler::less, L_less_than_8_left);
8622
8623 //load 8 Bytes
8624 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8625 movq(Address(tmp1, 0 * 16), rax);
8626 addptr(tmp1, 8);
8627 subl(len, 8);
8628 addl(pos, 8);
8629
8630 bind(L_less_than_8_left);
8631 cmpl(len, 4);
8632 jcc(Assembler::less, L_less_than_4_left);
8633
8634 //load 4 Bytes
8635 movl(rax, Address(buf, pos, Address::times_1, 0));
8636 movl(Address(tmp1, 0 * 16), rax);
8637 addptr(tmp1, 4);
8638 subl(len, 4);
8639 addl(pos, 4);
8640
8641 bind(L_less_than_4_left);
8642 cmpl(len, 2);
8643 jcc(Assembler::less, L_less_than_2_left);
8644
8645 // load 2 Bytes
8646 movw(rax, Address(buf, pos, Address::times_1, 0));
8647 movl(Address(tmp1, 0 * 16), rax);
8648 addptr(tmp1, 2);
8649 subl(len, 2);
8650 addl(pos, 2);
8651
8652 bind(L_less_than_2_left);
8653 cmpl(len, 1);
8654 jcc(Assembler::less, L_zero_left);
8655
8656 // load 1 Byte
8657 movb(rax, Address(buf, pos, Address::times_1, 0));
8658 movb(Address(tmp1, 0 * 16), rax);
8659
8660 bind(L_zero_left);
8661 movdqu(xmm7, Address(rsp, 0));
8662 pxor(xmm7, xmm0); //xor the initial crc value
8663
8664 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8665 movdqu(xmm0, Address(rax, tmp2));
8666 pshufb(xmm7, xmm0);
8667 jmp(L_128_done);
8668
8669 bind(L_exact_16_left);
8670 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8671 pxor(xmm7, xmm0); //xor the initial crc value
8672 jmp(L_128_done);
8673
8674 bind(L_only_less_than_4);
8675 cmpl(len, 3);
8676 jcc(Assembler::less, L_only_less_than_3);
8677
8678 // load 3 Bytes
8679 movb(rax, Address(buf, pos, Address::times_1, 0));
8680 movb(Address(tmp1, 0), rax);
8681
8682 movb(rax, Address(buf, pos, Address::times_1, 1));
8683 movb(Address(tmp1, 1), rax);
8684
8685 movb(rax, Address(buf, pos, Address::times_1, 2));
8686 movb(Address(tmp1, 2), rax);
8687
8688 movdqu(xmm7, Address(rsp, 0));
8689 pxor(xmm7, xmm0); //xor the initial crc value
8690
8691 pslldq(xmm7, 0x5);
8692 jmp(L_barrett);
8693 bind(L_only_less_than_3);
8694 cmpl(len, 2);
8695 jcc(Assembler::less, L_only_less_than_2);
8696
8697 // load 2 Bytes
8698 movb(rax, Address(buf, pos, Address::times_1, 0));
8699 movb(Address(tmp1, 0), rax);
8700
8701 movb(rax, Address(buf, pos, Address::times_1, 1));
8702 movb(Address(tmp1, 1), rax);
8703
8704 movdqu(xmm7, Address(rsp, 0));
8705 pxor(xmm7, xmm0); //xor the initial crc value
8706
8707 pslldq(xmm7, 0x6);
8708 jmp(L_barrett);
8709
8710 bind(L_only_less_than_2);
8711 //load 1 Byte
8712 movb(rax, Address(buf, pos, Address::times_1, 0));
8713 movb(Address(tmp1, 0), rax);
8714
8715 movdqu(xmm7, Address(rsp, 0));
8716 pxor(xmm7, xmm0); //xor the initial crc value
8717
8718 pslldq(xmm7, 0x7);
8719 }
8720
8721 /**
8722 * Compute CRC32 using AVX512 instructions
8723 * param crc register containing existing CRC (32-bit)
8724 * param buf register pointing to input byte buffer (byte*)
8725 * param len register containing number of bytes
8726 * param table address of crc or crc32c table
8727 * param tmp1 scratch register
8728 * param tmp2 scratch register
8729 * return rax result register
8730 *
8731 * This routine is identical for crc32c with the exception of the precomputed constant
8732 * table which will be passed as the table argument. The calculation steps are
8733 * the same for both variants.
8734 */
8735 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8736 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8737
8738 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8739 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8740 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8741 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8742 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8743
8744 const Register pos = r12;
8745 push(r12);
8746 subptr(rsp, 16 * 2 + 8);
8747
8748 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8749 // context for the registers used, where all instructions below are using 128-bit mode
8750 // On EVEX without VL and BW, these instructions will all be AVX.
8751 movl(pos, 0);
8752
8753 // check if smaller than 256B
8754 cmpl(len, 256);
8755 jcc(Assembler::less, L_less_than_256);
8756
8757 // load the initial crc value
8758 movdl(xmm10, crc);
8759
8760 // receive the initial 64B data, xor the initial crc value
8761 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8762 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8763 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8764 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8765
8766 subl(len, 256);
8767 cmpl(len, 256);
8768 jcc(Assembler::less, L_fold_128_B_loop);
8769
8770 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8771 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8772 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8773 subl(len, 256);
8774
8775 bind(L_fold_256_B_loop);
8776 addl(pos, 256);
8777 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8778 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8779 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8780 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8781
8782 subl(len, 256);
8783 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8784
8785 // Fold 256 into 128
8786 addl(pos, 256);
8787 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8788 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8789 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8790
8791 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8792 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8793 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8794
8795 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8796 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8797
8798 addl(len, 128);
8799 jmp(L_fold_128_B_register);
8800
8801 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8802 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8803
8804 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8805 bind(L_fold_128_B_loop);
8806 addl(pos, 128);
8807 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8808 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8809
8810 subl(len, 128);
8811 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8812
8813 addl(pos, 128);
8814
8815 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8816 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8817 bind(L_fold_128_B_register);
8818 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8819 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8820 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8821 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8822 // save last that has no multiplicand
8823 vextracti64x2(xmm7, xmm4, 3);
8824
8825 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8826 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8827 // Needed later in reduction loop
8828 movdqu(xmm10, Address(table, 1 * 16));
8829 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8830 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8831
8832 // Swap 1,0,3,2 - 01 00 11 10
8833 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8834 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8835 vextracti128(xmm5, xmm8, 1);
8836 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8837
8838 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8839 // instead of a cmp instruction, we use the negative flag with the jl instruction
8840 addl(len, 128 - 16);
8841 jcc(Assembler::less, L_final_reduction_for_128);
8842
8843 bind(L_16B_reduction_loop);
8844 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8845 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8846 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8847 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8848 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8849 addl(pos, 16);
8850 subl(len, 16);
8851 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8852
8853 bind(L_final_reduction_for_128);
8854 addl(len, 16);
8855 jcc(Assembler::equal, L_128_done);
8856
8857 bind(L_get_last_two_xmms);
8858 movdqu(xmm2, xmm7);
8859 addl(pos, len);
8860 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8861 subl(pos, len);
8862
8863 // get rid of the extra data that was loaded before
8864 // load the shift constant
8865 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8866 movdqu(xmm0, Address(rax, len));
8867 addl(rax, len);
8868
8869 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8870 //Change mask to 512
8871 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8872 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8873
8874 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8875 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8876 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8877 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8878 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8879
8880 bind(L_128_done);
8881 // compute crc of a 128-bit value
8882 movdqu(xmm10, Address(table, 3 * 16));
8883 movdqu(xmm0, xmm7);
8884
8885 // 64b fold
8886 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8887 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8888 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8889
8890 // 32b fold
8891 movdqu(xmm0, xmm7);
8892 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8893 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8894 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8895 jmp(L_barrett);
8896
8897 bind(L_less_than_256);
8898 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8899
8900 //barrett reduction
8901 bind(L_barrett);
8902 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8903 movdqu(xmm1, xmm7);
8904 movdqu(xmm2, xmm7);
8905 movdqu(xmm10, Address(table, 4 * 16));
8906
8907 pclmulqdq(xmm7, xmm10, 0x0);
8908 pxor(xmm7, xmm2);
8909 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8910 movdqu(xmm2, xmm7);
8911 pclmulqdq(xmm7, xmm10, 0x10);
8912 pxor(xmm7, xmm2);
8913 pxor(xmm7, xmm1);
8914 pextrd(crc, xmm7, 2);
8915
8916 bind(L_cleanup);
8917 addptr(rsp, 16 * 2 + 8);
8918 pop(r12);
8919 }
8920
8921 // S. Gueron / Information Processing Letters 112 (2012) 184
8922 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8923 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8924 // Output: the 64-bit carry-less product of B * CONST
8925 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8926 Register tmp1, Register tmp2, Register tmp3) {
8927 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8928 if (n > 0) {
8929 addq(tmp3, n * 256 * 8);
8930 }
8931 // Q1 = TABLEExt[n][B & 0xFF];
8932 movl(tmp1, in);
8933 andl(tmp1, 0x000000FF);
8934 shll(tmp1, 3);
8935 addq(tmp1, tmp3);
8936 movq(tmp1, Address(tmp1, 0));
8937
8938 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8939 movl(tmp2, in);
8940 shrl(tmp2, 8);
8941 andl(tmp2, 0x000000FF);
8942 shll(tmp2, 3);
8943 addq(tmp2, tmp3);
8944 movq(tmp2, Address(tmp2, 0));
8945
8946 shlq(tmp2, 8);
8947 xorq(tmp1, tmp2);
8948
8949 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8950 movl(tmp2, in);
8951 shrl(tmp2, 16);
8952 andl(tmp2, 0x000000FF);
8953 shll(tmp2, 3);
8954 addq(tmp2, tmp3);
8955 movq(tmp2, Address(tmp2, 0));
8956
8957 shlq(tmp2, 16);
8958 xorq(tmp1, tmp2);
8959
8960 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8961 shrl(in, 24);
8962 andl(in, 0x000000FF);
8963 shll(in, 3);
8964 addq(in, tmp3);
8965 movq(in, Address(in, 0));
8966
8967 shlq(in, 24);
8968 xorq(in, tmp1);
8969 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8970 }
8971
8972 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8973 Register in_out,
8974 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8975 XMMRegister w_xtmp2,
8976 Register tmp1,
8977 Register n_tmp2, Register n_tmp3) {
8978 if (is_pclmulqdq_supported) {
8979 movdl(w_xtmp1, in_out); // modified blindly
8980
8981 movl(tmp1, const_or_pre_comp_const_index);
8982 movdl(w_xtmp2, tmp1);
8983 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8984
8985 movdq(in_out, w_xtmp1);
8986 } else {
8987 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8988 }
8989 }
8990
8991 // Recombination Alternative 2: No bit-reflections
8992 // T1 = (CRC_A * U1) << 1
8993 // T2 = (CRC_B * U2) << 1
8994 // C1 = T1 >> 32
8995 // C2 = T2 >> 32
8996 // T1 = T1 & 0xFFFFFFFF
8997 // T2 = T2 & 0xFFFFFFFF
8998 // T1 = CRC32(0, T1)
8999 // T2 = CRC32(0, T2)
9000 // C1 = C1 ^ T1
9001 // C2 = C2 ^ T2
9002 // CRC = C1 ^ C2 ^ CRC_C
9003 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9004 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9005 Register tmp1, Register tmp2,
9006 Register n_tmp3) {
9007 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9008 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9009 shlq(in_out, 1);
9010 movl(tmp1, in_out);
9011 shrq(in_out, 32);
9012 xorl(tmp2, tmp2);
9013 crc32(tmp2, tmp1, 4);
9014 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9015 shlq(in1, 1);
9016 movl(tmp1, in1);
9017 shrq(in1, 32);
9018 xorl(tmp2, tmp2);
9019 crc32(tmp2, tmp1, 4);
9020 xorl(in1, tmp2);
9021 xorl(in_out, in1);
9022 xorl(in_out, in2);
9023 }
9024
9025 // Set N to predefined value
9026 // Subtract from a length of a buffer
9027 // execute in a loop:
9028 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9029 // for i = 1 to N do
9030 // CRC_A = CRC32(CRC_A, A[i])
9031 // CRC_B = CRC32(CRC_B, B[i])
9032 // CRC_C = CRC32(CRC_C, C[i])
9033 // end for
9034 // Recombine
9035 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9036 Register in_out1, Register in_out2, Register in_out3,
9037 Register tmp1, Register tmp2, Register tmp3,
9038 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9039 Register tmp4, Register tmp5,
9040 Register n_tmp6) {
9041 Label L_processPartitions;
9042 Label L_processPartition;
9043 Label L_exit;
9044
9045 bind(L_processPartitions);
9046 cmpl(in_out1, 3 * size);
9047 jcc(Assembler::less, L_exit);
9048 xorl(tmp1, tmp1);
9049 xorl(tmp2, tmp2);
9050 movq(tmp3, in_out2);
9051 addq(tmp3, size);
9052
9053 bind(L_processPartition);
9054 crc32(in_out3, Address(in_out2, 0), 8);
9055 crc32(tmp1, Address(in_out2, size), 8);
9056 crc32(tmp2, Address(in_out2, size * 2), 8);
9057 addq(in_out2, 8);
9058 cmpq(in_out2, tmp3);
9059 jcc(Assembler::less, L_processPartition);
9060 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9061 w_xtmp1, w_xtmp2, w_xtmp3,
9062 tmp4, tmp5,
9063 n_tmp6);
9064 addq(in_out2, 2 * size);
9065 subl(in_out1, 3 * size);
9066 jmp(L_processPartitions);
9067
9068 bind(L_exit);
9069 }
9070
9071 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9072 // Input: A buffer I of L bytes.
9073 // Output: the CRC32C value of the buffer.
9074 // Notations:
9075 // Write L = 24N + r, with N = floor (L/24).
9076 // r = L mod 24 (0 <= r < 24).
9077 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9078 // N quadwords, and R consists of r bytes.
9079 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9080 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9081 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9082 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9083 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9084 Register tmp1, Register tmp2, Register tmp3,
9085 Register tmp4, Register tmp5, Register tmp6,
9086 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9087 bool is_pclmulqdq_supported) {
9088 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9089 Label L_wordByWord;
9090 Label L_byteByByteProlog;
9091 Label L_byteByByte;
9092 Label L_exit;
9093
9094 if (is_pclmulqdq_supported ) {
9095 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9096 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9097
9098 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9099 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9100
9101 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9102 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9103 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9104 } else {
9105 const_or_pre_comp_const_index[0] = 1;
9106 const_or_pre_comp_const_index[1] = 0;
9107
9108 const_or_pre_comp_const_index[2] = 3;
9109 const_or_pre_comp_const_index[3] = 2;
9110
9111 const_or_pre_comp_const_index[4] = 5;
9112 const_or_pre_comp_const_index[5] = 4;
9113 }
9114 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9115 in2, in1, in_out,
9116 tmp1, tmp2, tmp3,
9117 w_xtmp1, w_xtmp2, w_xtmp3,
9118 tmp4, tmp5,
9119 tmp6);
9120 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9121 in2, in1, in_out,
9122 tmp1, tmp2, tmp3,
9123 w_xtmp1, w_xtmp2, w_xtmp3,
9124 tmp4, tmp5,
9125 tmp6);
9126 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9127 in2, in1, in_out,
9128 tmp1, tmp2, tmp3,
9129 w_xtmp1, w_xtmp2, w_xtmp3,
9130 tmp4, tmp5,
9131 tmp6);
9132 movl(tmp1, in2);
9133 andl(tmp1, 0x00000007);
9134 negl(tmp1);
9135 addl(tmp1, in2);
9136 addq(tmp1, in1);
9137
9138 cmpq(in1, tmp1);
9139 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9140 align(16);
9141 BIND(L_wordByWord);
9142 crc32(in_out, Address(in1, 0), 8);
9143 addq(in1, 8);
9144 cmpq(in1, tmp1);
9145 jcc(Assembler::less, L_wordByWord);
9146
9147 BIND(L_byteByByteProlog);
9148 andl(in2, 0x00000007);
9149 movl(tmp2, 1);
9150
9151 cmpl(tmp2, in2);
9152 jccb(Assembler::greater, L_exit);
9153 BIND(L_byteByByte);
9154 crc32(in_out, Address(in1, 0), 1);
9155 incq(in1);
9156 incl(tmp2);
9157 cmpl(tmp2, in2);
9158 jcc(Assembler::lessEqual, L_byteByByte);
9159
9160 BIND(L_exit);
9161 }
9162 #undef BIND
9163 #undef BLOCK_COMMENT
9164
9165 // Compress char[] array to byte[].
9166 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9167 // Return the array length if every element in array can be encoded,
9168 // otherwise, the index of first non-latin1 (> 0xff) character.
9169 // @IntrinsicCandidate
9170 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9171 // for (int i = 0; i < len; i++) {
9172 // char c = src[srcOff];
9173 // if (c > 0xff) {
9174 // return i; // return index of non-latin1 char
9175 // }
9176 // dst[dstOff] = (byte)c;
9177 // srcOff++;
9178 // dstOff++;
9179 // }
9180 // return len;
9181 // }
9182 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9183 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9184 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9185 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9186 Label copy_chars_loop, done, reset_sp, copy_tail;
9187
9188 // rsi: src
9189 // rdi: dst
9190 // rdx: len
9191 // rcx: tmp5
9192 // rax: result
9193
9194 // rsi holds start addr of source char[] to be compressed
9195 // rdi holds start addr of destination byte[]
9196 // rdx holds length
9197
9198 assert(len != result, "");
9199
9200 // save length for return
9201 movl(result, len);
9202
9203 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9204 VM_Version::supports_avx512vlbw() &&
9205 VM_Version::supports_bmi2()) {
9206
9207 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9208
9209 // alignment
9210 Label post_alignment;
9211
9212 // if length of the string is less than 32, handle it the old fashioned way
9213 testl(len, -32);
9214 jcc(Assembler::zero, below_threshold);
9215
9216 // First check whether a character is compressible ( <= 0xFF).
9217 // Create mask to test for Unicode chars inside zmm vector
9218 movl(tmp5, 0x00FF);
9219 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9220
9221 testl(len, -64);
9222 jccb(Assembler::zero, post_alignment);
9223
9224 movl(tmp5, dst);
9225 andl(tmp5, (32 - 1));
9226 negl(tmp5);
9227 andl(tmp5, (32 - 1));
9228
9229 // bail out when there is nothing to be done
9230 testl(tmp5, 0xFFFFFFFF);
9231 jccb(Assembler::zero, post_alignment);
9232
9233 // ~(~0 << len), where len is the # of remaining elements to process
9234 movl(len, 0xFFFFFFFF);
9235 shlxl(len, len, tmp5);
9236 notl(len);
9237 kmovdl(mask2, len);
9238 movl(len, result);
9239
9240 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9241 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9242 ktestd(mask1, mask2);
9243 jcc(Assembler::carryClear, copy_tail);
9244
9245 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9246
9247 addptr(src, tmp5);
9248 addptr(src, tmp5);
9249 addptr(dst, tmp5);
9250 subl(len, tmp5);
9251
9252 bind(post_alignment);
9253 // end of alignment
9254
9255 movl(tmp5, len);
9256 andl(tmp5, (32 - 1)); // tail count (in chars)
9257 andl(len, ~(32 - 1)); // vector count (in chars)
9258 jccb(Assembler::zero, copy_loop_tail);
9259
9260 lea(src, Address(src, len, Address::times_2));
9261 lea(dst, Address(dst, len, Address::times_1));
9262 negptr(len);
9263
9264 bind(copy_32_loop);
9265 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9266 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9267 kortestdl(mask1, mask1);
9268 jccb(Assembler::carryClear, reset_for_copy_tail);
9269
9270 // All elements in current processed chunk are valid candidates for
9271 // compression. Write a truncated byte elements to the memory.
9272 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9273 addptr(len, 32);
9274 jccb(Assembler::notZero, copy_32_loop);
9275
9276 bind(copy_loop_tail);
9277 // bail out when there is nothing to be done
9278 testl(tmp5, 0xFFFFFFFF);
9279 jcc(Assembler::zero, done);
9280
9281 movl(len, tmp5);
9282
9283 // ~(~0 << len), where len is the # of remaining elements to process
9284 movl(tmp5, 0xFFFFFFFF);
9285 shlxl(tmp5, tmp5, len);
9286 notl(tmp5);
9287
9288 kmovdl(mask2, tmp5);
9289
9290 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9291 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9292 ktestd(mask1, mask2);
9293 jcc(Assembler::carryClear, copy_tail);
9294
9295 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9296 jmp(done);
9297
9298 bind(reset_for_copy_tail);
9299 lea(src, Address(src, tmp5, Address::times_2));
9300 lea(dst, Address(dst, tmp5, Address::times_1));
9301 subptr(len, tmp5);
9302 jmp(copy_chars_loop);
9303
9304 bind(below_threshold);
9305 }
9306
9307 if (UseSSE42Intrinsics) {
9308 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9309
9310 // vectored compression
9311 testl(len, 0xfffffff8);
9312 jcc(Assembler::zero, copy_tail);
9313
9314 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9315 movdl(tmp1Reg, tmp5);
9316 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9317
9318 andl(len, 0xfffffff0);
9319 jccb(Assembler::zero, copy_16);
9320
9321 // compress 16 chars per iter
9322 pxor(tmp4Reg, tmp4Reg);
9323
9324 lea(src, Address(src, len, Address::times_2));
9325 lea(dst, Address(dst, len, Address::times_1));
9326 negptr(len);
9327
9328 bind(copy_32_loop);
9329 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9330 por(tmp4Reg, tmp2Reg);
9331 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9332 por(tmp4Reg, tmp3Reg);
9333 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9334 jccb(Assembler::notZero, reset_for_copy_tail);
9335 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9336 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9337 addptr(len, 16);
9338 jccb(Assembler::notZero, copy_32_loop);
9339
9340 // compress next vector of 8 chars (if any)
9341 bind(copy_16);
9342 // len = 0
9343 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9344 jccb(Assembler::zero, copy_tail_sse);
9345
9346 pxor(tmp3Reg, tmp3Reg);
9347
9348 movdqu(tmp2Reg, Address(src, 0));
9349 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9350 jccb(Assembler::notZero, reset_for_copy_tail);
9351 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9352 movq(Address(dst, 0), tmp2Reg);
9353 addptr(src, 16);
9354 addptr(dst, 8);
9355 jmpb(copy_tail_sse);
9356
9357 bind(reset_for_copy_tail);
9358 movl(tmp5, result);
9359 andl(tmp5, 0x0000000f);
9360 lea(src, Address(src, tmp5, Address::times_2));
9361 lea(dst, Address(dst, tmp5, Address::times_1));
9362 subptr(len, tmp5);
9363 jmpb(copy_chars_loop);
9364
9365 bind(copy_tail_sse);
9366 movl(len, result);
9367 andl(len, 0x00000007); // tail count (in chars)
9368 }
9369 // compress 1 char per iter
9370 bind(copy_tail);
9371 testl(len, len);
9372 jccb(Assembler::zero, done);
9373 lea(src, Address(src, len, Address::times_2));
9374 lea(dst, Address(dst, len, Address::times_1));
9375 negptr(len);
9376
9377 bind(copy_chars_loop);
9378 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9379 testl(tmp5, 0xff00); // check if Unicode char
9380 jccb(Assembler::notZero, reset_sp);
9381 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9382 increment(len);
9383 jccb(Assembler::notZero, copy_chars_loop);
9384
9385 // add len then return (len will be zero if compress succeeded, otherwise negative)
9386 bind(reset_sp);
9387 addl(result, len);
9388
9389 bind(done);
9390 }
9391
9392 // Inflate byte[] array to char[].
9393 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9394 // @IntrinsicCandidate
9395 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9396 // for (int i = 0; i < len; i++) {
9397 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9398 // }
9399 // }
9400 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9401 XMMRegister tmp1, Register tmp2, KRegister mask) {
9402 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9403 // rsi: src
9404 // rdi: dst
9405 // rdx: len
9406 // rcx: tmp2
9407
9408 // rsi holds start addr of source byte[] to be inflated
9409 // rdi holds start addr of destination char[]
9410 // rdx holds length
9411 assert_different_registers(src, dst, len, tmp2);
9412 movl(tmp2, len);
9413 if ((UseAVX > 2) && // AVX512
9414 VM_Version::supports_avx512vlbw() &&
9415 VM_Version::supports_bmi2()) {
9416
9417 Label copy_32_loop, copy_tail;
9418 Register tmp3_aliased = len;
9419
9420 // if length of the string is less than 16, handle it in an old fashioned way
9421 testl(len, -16);
9422 jcc(Assembler::zero, below_threshold);
9423
9424 testl(len, -1 * AVX3Threshold);
9425 jcc(Assembler::zero, avx3_threshold);
9426
9427 // In order to use only one arithmetic operation for the main loop we use
9428 // this pre-calculation
9429 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9430 andl(len, -32); // vector count
9431 jccb(Assembler::zero, copy_tail);
9432
9433 lea(src, Address(src, len, Address::times_1));
9434 lea(dst, Address(dst, len, Address::times_2));
9435 negptr(len);
9436
9437
9438 // inflate 32 chars per iter
9439 bind(copy_32_loop);
9440 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9441 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9442 addptr(len, 32);
9443 jcc(Assembler::notZero, copy_32_loop);
9444
9445 bind(copy_tail);
9446 // bail out when there is nothing to be done
9447 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9448 jcc(Assembler::zero, done);
9449
9450 // ~(~0 << length), where length is the # of remaining elements to process
9451 movl(tmp3_aliased, -1);
9452 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9453 notl(tmp3_aliased);
9454 kmovdl(mask, tmp3_aliased);
9455 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9456 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9457
9458 jmp(done);
9459 bind(avx3_threshold);
9460 }
9461 if (UseSSE42Intrinsics) {
9462 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9463
9464 if (UseAVX > 1) {
9465 andl(tmp2, (16 - 1));
9466 andl(len, -16);
9467 jccb(Assembler::zero, copy_new_tail);
9468 } else {
9469 andl(tmp2, 0x00000007); // tail count (in chars)
9470 andl(len, 0xfffffff8); // vector count (in chars)
9471 jccb(Assembler::zero, copy_tail);
9472 }
9473
9474 // vectored inflation
9475 lea(src, Address(src, len, Address::times_1));
9476 lea(dst, Address(dst, len, Address::times_2));
9477 negptr(len);
9478
9479 if (UseAVX > 1) {
9480 bind(copy_16_loop);
9481 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9482 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9483 addptr(len, 16);
9484 jcc(Assembler::notZero, copy_16_loop);
9485
9486 bind(below_threshold);
9487 bind(copy_new_tail);
9488 movl(len, tmp2);
9489 andl(tmp2, 0x00000007);
9490 andl(len, 0xFFFFFFF8);
9491 jccb(Assembler::zero, copy_tail);
9492
9493 pmovzxbw(tmp1, Address(src, 0));
9494 movdqu(Address(dst, 0), tmp1);
9495 addptr(src, 8);
9496 addptr(dst, 2 * 8);
9497
9498 jmp(copy_tail, true);
9499 }
9500
9501 // inflate 8 chars per iter
9502 bind(copy_8_loop);
9503 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9504 movdqu(Address(dst, len, Address::times_2), tmp1);
9505 addptr(len, 8);
9506 jcc(Assembler::notZero, copy_8_loop);
9507
9508 bind(copy_tail);
9509 movl(len, tmp2);
9510
9511 cmpl(len, 4);
9512 jccb(Assembler::less, copy_bytes);
9513
9514 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9515 pmovzxbw(tmp1, tmp1);
9516 movq(Address(dst, 0), tmp1);
9517 subptr(len, 4);
9518 addptr(src, 4);
9519 addptr(dst, 8);
9520
9521 bind(copy_bytes);
9522 } else {
9523 bind(below_threshold);
9524 }
9525
9526 testl(len, len);
9527 jccb(Assembler::zero, done);
9528 lea(src, Address(src, len, Address::times_1));
9529 lea(dst, Address(dst, len, Address::times_2));
9530 negptr(len);
9531
9532 // inflate 1 char per iter
9533 bind(copy_chars_loop);
9534 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9535 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9536 increment(len);
9537 jcc(Assembler::notZero, copy_chars_loop);
9538
9539 bind(done);
9540 }
9541
9542 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9543 switch(type) {
9544 case T_BYTE:
9545 case T_BOOLEAN:
9546 evmovdqub(dst, kmask, src, merge, vector_len);
9547 break;
9548 case T_CHAR:
9549 case T_SHORT:
9550 evmovdquw(dst, kmask, src, merge, vector_len);
9551 break;
9552 case T_INT:
9553 case T_FLOAT:
9554 evmovdqul(dst, kmask, src, merge, vector_len);
9555 break;
9556 case T_LONG:
9557 case T_DOUBLE:
9558 evmovdquq(dst, kmask, src, merge, vector_len);
9559 break;
9560 default:
9561 fatal("Unexpected type argument %s", type2name(type));
9562 break;
9563 }
9564 }
9565
9566
9567 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9568 switch(type) {
9569 case T_BYTE:
9570 case T_BOOLEAN:
9571 evmovdqub(dst, kmask, src, merge, vector_len);
9572 break;
9573 case T_CHAR:
9574 case T_SHORT:
9575 evmovdquw(dst, kmask, src, merge, vector_len);
9576 break;
9577 case T_INT:
9578 case T_FLOAT:
9579 evmovdqul(dst, kmask, src, merge, vector_len);
9580 break;
9581 case T_LONG:
9582 case T_DOUBLE:
9583 evmovdquq(dst, kmask, src, merge, vector_len);
9584 break;
9585 default:
9586 fatal("Unexpected type argument %s", type2name(type));
9587 break;
9588 }
9589 }
9590
9591 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9592 switch(type) {
9593 case T_BYTE:
9594 case T_BOOLEAN:
9595 evmovdqub(dst, kmask, src, merge, vector_len);
9596 break;
9597 case T_CHAR:
9598 case T_SHORT:
9599 evmovdquw(dst, kmask, src, merge, vector_len);
9600 break;
9601 case T_INT:
9602 case T_FLOAT:
9603 evmovdqul(dst, kmask, src, merge, vector_len);
9604 break;
9605 case T_LONG:
9606 case T_DOUBLE:
9607 evmovdquq(dst, kmask, src, merge, vector_len);
9608 break;
9609 default:
9610 fatal("Unexpected type argument %s", type2name(type));
9611 break;
9612 }
9613 }
9614
9615 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9616 switch(masklen) {
9617 case 2:
9618 knotbl(dst, src);
9619 movl(rtmp, 3);
9620 kmovbl(ktmp, rtmp);
9621 kandbl(dst, ktmp, dst);
9622 break;
9623 case 4:
9624 knotbl(dst, src);
9625 movl(rtmp, 15);
9626 kmovbl(ktmp, rtmp);
9627 kandbl(dst, ktmp, dst);
9628 break;
9629 case 8:
9630 knotbl(dst, src);
9631 break;
9632 case 16:
9633 knotwl(dst, src);
9634 break;
9635 case 32:
9636 knotdl(dst, src);
9637 break;
9638 case 64:
9639 knotql(dst, src);
9640 break;
9641 default:
9642 fatal("Unexpected vector length %d", masklen);
9643 break;
9644 }
9645 }
9646
9647 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9648 switch(type) {
9649 case T_BOOLEAN:
9650 case T_BYTE:
9651 kandbl(dst, src1, src2);
9652 break;
9653 case T_CHAR:
9654 case T_SHORT:
9655 kandwl(dst, src1, src2);
9656 break;
9657 case T_INT:
9658 case T_FLOAT:
9659 kanddl(dst, src1, src2);
9660 break;
9661 case T_LONG:
9662 case T_DOUBLE:
9663 kandql(dst, src1, src2);
9664 break;
9665 default:
9666 fatal("Unexpected type argument %s", type2name(type));
9667 break;
9668 }
9669 }
9670
9671 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9672 switch(type) {
9673 case T_BOOLEAN:
9674 case T_BYTE:
9675 korbl(dst, src1, src2);
9676 break;
9677 case T_CHAR:
9678 case T_SHORT:
9679 korwl(dst, src1, src2);
9680 break;
9681 case T_INT:
9682 case T_FLOAT:
9683 kordl(dst, src1, src2);
9684 break;
9685 case T_LONG:
9686 case T_DOUBLE:
9687 korql(dst, src1, src2);
9688 break;
9689 default:
9690 fatal("Unexpected type argument %s", type2name(type));
9691 break;
9692 }
9693 }
9694
9695 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9696 switch(type) {
9697 case T_BOOLEAN:
9698 case T_BYTE:
9699 kxorbl(dst, src1, src2);
9700 break;
9701 case T_CHAR:
9702 case T_SHORT:
9703 kxorwl(dst, src1, src2);
9704 break;
9705 case T_INT:
9706 case T_FLOAT:
9707 kxordl(dst, src1, src2);
9708 break;
9709 case T_LONG:
9710 case T_DOUBLE:
9711 kxorql(dst, src1, src2);
9712 break;
9713 default:
9714 fatal("Unexpected type argument %s", type2name(type));
9715 break;
9716 }
9717 }
9718
9719 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9720 switch(type) {
9721 case T_BOOLEAN:
9722 case T_BYTE:
9723 evpermb(dst, mask, nds, src, merge, vector_len); break;
9724 case T_CHAR:
9725 case T_SHORT:
9726 evpermw(dst, mask, nds, src, merge, vector_len); break;
9727 case T_INT:
9728 case T_FLOAT:
9729 evpermd(dst, mask, nds, src, merge, vector_len); break;
9730 case T_LONG:
9731 case T_DOUBLE:
9732 evpermq(dst, mask, nds, src, merge, vector_len); break;
9733 default:
9734 fatal("Unexpected type argument %s", type2name(type)); break;
9735 }
9736 }
9737
9738 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9739 switch(type) {
9740 case T_BOOLEAN:
9741 case T_BYTE:
9742 evpermb(dst, mask, nds, src, merge, vector_len); break;
9743 case T_CHAR:
9744 case T_SHORT:
9745 evpermw(dst, mask, nds, src, merge, vector_len); break;
9746 case T_INT:
9747 case T_FLOAT:
9748 evpermd(dst, mask, nds, src, merge, vector_len); break;
9749 case T_LONG:
9750 case T_DOUBLE:
9751 evpermq(dst, mask, nds, src, merge, vector_len); break;
9752 default:
9753 fatal("Unexpected type argument %s", type2name(type)); break;
9754 }
9755 }
9756
9757 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9758 switch(type) {
9759 case T_BYTE:
9760 evpminub(dst, mask, nds, src, merge, vector_len); break;
9761 case T_SHORT:
9762 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9763 case T_INT:
9764 evpminud(dst, mask, nds, src, merge, vector_len); break;
9765 case T_LONG:
9766 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9767 default:
9768 fatal("Unexpected type argument %s", type2name(type)); break;
9769 }
9770 }
9771
9772 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9773 switch(type) {
9774 case T_BYTE:
9775 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9776 case T_SHORT:
9777 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9778 case T_INT:
9779 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9780 case T_LONG:
9781 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9782 default:
9783 fatal("Unexpected type argument %s", type2name(type)); break;
9784 }
9785 }
9786
9787 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9788 switch(type) {
9789 case T_BYTE:
9790 evpminub(dst, mask, nds, src, merge, vector_len); break;
9791 case T_SHORT:
9792 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9793 case T_INT:
9794 evpminud(dst, mask, nds, src, merge, vector_len); break;
9795 case T_LONG:
9796 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9797 default:
9798 fatal("Unexpected type argument %s", type2name(type)); break;
9799 }
9800 }
9801
9802 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9803 switch(type) {
9804 case T_BYTE:
9805 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9806 case T_SHORT:
9807 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9808 case T_INT:
9809 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9810 case T_LONG:
9811 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9812 default:
9813 fatal("Unexpected type argument %s", type2name(type)); break;
9814 }
9815 }
9816
9817 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9818 switch(type) {
9819 case T_BYTE:
9820 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9821 case T_SHORT:
9822 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9823 case T_INT:
9824 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9825 case T_LONG:
9826 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9827 case T_FLOAT:
9828 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9829 case T_DOUBLE:
9830 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9831 default:
9832 fatal("Unexpected type argument %s", type2name(type)); break;
9833 }
9834 }
9835
9836 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9837 switch(type) {
9838 case T_BYTE:
9839 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9840 case T_SHORT:
9841 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9842 case T_INT:
9843 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9844 case T_LONG:
9845 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9846 case T_FLOAT:
9847 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9848 case T_DOUBLE:
9849 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9850 default:
9851 fatal("Unexpected type argument %s", type2name(type)); break;
9852 }
9853 }
9854
9855 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9856 switch(type) {
9857 case T_BYTE:
9858 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9859 case T_SHORT:
9860 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9861 case T_INT:
9862 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9863 case T_LONG:
9864 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9865 case T_FLOAT:
9866 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9867 case T_DOUBLE:
9868 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9869 default:
9870 fatal("Unexpected type argument %s", type2name(type)); break;
9871 }
9872 }
9873
9874 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9875 switch(type) {
9876 case T_BYTE:
9877 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9878 case T_SHORT:
9879 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9880 case T_INT:
9881 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9882 case T_LONG:
9883 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9884 case T_FLOAT:
9885 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9886 case T_DOUBLE:
9887 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9888 default:
9889 fatal("Unexpected type argument %s", type2name(type)); break;
9890 }
9891 }
9892
9893 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9894 switch(type) {
9895 case T_INT:
9896 evpxord(dst, mask, nds, src, merge, vector_len); break;
9897 case T_LONG:
9898 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9899 default:
9900 fatal("Unexpected type argument %s", type2name(type)); break;
9901 }
9902 }
9903
9904 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9905 switch(type) {
9906 case T_INT:
9907 evpxord(dst, mask, nds, src, merge, vector_len); break;
9908 case T_LONG:
9909 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9910 default:
9911 fatal("Unexpected type argument %s", type2name(type)); break;
9912 }
9913 }
9914
9915 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9916 switch(type) {
9917 case T_INT:
9918 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9919 case T_LONG:
9920 evporq(dst, mask, nds, src, merge, vector_len); break;
9921 default:
9922 fatal("Unexpected type argument %s", type2name(type)); break;
9923 }
9924 }
9925
9926 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9927 switch(type) {
9928 case T_INT:
9929 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9930 case T_LONG:
9931 evporq(dst, mask, nds, src, merge, vector_len); break;
9932 default:
9933 fatal("Unexpected type argument %s", type2name(type)); break;
9934 }
9935 }
9936
9937 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9938 switch(type) {
9939 case T_INT:
9940 evpandd(dst, mask, nds, src, merge, vector_len); break;
9941 case T_LONG:
9942 evpandq(dst, mask, nds, src, merge, vector_len); break;
9943 default:
9944 fatal("Unexpected type argument %s", type2name(type)); break;
9945 }
9946 }
9947
9948 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9949 switch(type) {
9950 case T_INT:
9951 evpandd(dst, mask, nds, src, merge, vector_len); break;
9952 case T_LONG:
9953 evpandq(dst, mask, nds, src, merge, vector_len); break;
9954 default:
9955 fatal("Unexpected type argument %s", type2name(type)); break;
9956 }
9957 }
9958
9959 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
9960 switch(masklen) {
9961 case 8:
9962 kortestbl(src1, src2);
9963 break;
9964 case 16:
9965 kortestwl(src1, src2);
9966 break;
9967 case 32:
9968 kortestdl(src1, src2);
9969 break;
9970 case 64:
9971 kortestql(src1, src2);
9972 break;
9973 default:
9974 fatal("Unexpected mask length %d", masklen);
9975 break;
9976 }
9977 }
9978
9979
9980 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
9981 switch(masklen) {
9982 case 8:
9983 ktestbl(src1, src2);
9984 break;
9985 case 16:
9986 ktestwl(src1, src2);
9987 break;
9988 case 32:
9989 ktestdl(src1, src2);
9990 break;
9991 case 64:
9992 ktestql(src1, src2);
9993 break;
9994 default:
9995 fatal("Unexpected mask length %d", masklen);
9996 break;
9997 }
9998 }
9999
10000 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10001 switch(type) {
10002 case T_INT:
10003 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10004 case T_LONG:
10005 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10006 default:
10007 fatal("Unexpected type argument %s", type2name(type)); break;
10008 break;
10009 }
10010 }
10011
10012 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10013 switch(type) {
10014 case T_INT:
10015 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10016 case T_LONG:
10017 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10018 default:
10019 fatal("Unexpected type argument %s", type2name(type)); break;
10020 }
10021 }
10022
10023 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10024 switch(type) {
10025 case T_INT:
10026 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10027 case T_LONG:
10028 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10029 default:
10030 fatal("Unexpected type argument %s", type2name(type)); break;
10031 }
10032 }
10033
10034 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10035 switch(type) {
10036 case T_INT:
10037 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10038 case T_LONG:
10039 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10040 default:
10041 fatal("Unexpected type argument %s", type2name(type)); break;
10042 }
10043 }
10044
10045 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10046 assert(rscratch != noreg || always_reachable(src), "missing");
10047
10048 if (reachable(src)) {
10049 evpandq(dst, nds, as_Address(src), vector_len);
10050 } else {
10051 lea(rscratch, src);
10052 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10053 }
10054 }
10055
10056 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10057 assert(rscratch != noreg || always_reachable(src), "missing");
10058
10059 if (reachable(src)) {
10060 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10061 } else {
10062 lea(rscratch, src);
10063 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10064 }
10065 }
10066
10067 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10068 assert(rscratch != noreg || always_reachable(src), "missing");
10069
10070 if (reachable(src)) {
10071 evporq(dst, nds, as_Address(src), vector_len);
10072 } else {
10073 lea(rscratch, src);
10074 evporq(dst, nds, Address(rscratch, 0), vector_len);
10075 }
10076 }
10077
10078 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10079 assert(rscratch != noreg || always_reachable(src), "missing");
10080
10081 if (reachable(src)) {
10082 vpshufb(dst, nds, as_Address(src), vector_len);
10083 } else {
10084 lea(rscratch, src);
10085 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10086 }
10087 }
10088
10089 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10090 assert(rscratch != noreg || always_reachable(src), "missing");
10091
10092 if (reachable(src)) {
10093 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10094 } else {
10095 lea(rscratch, src);
10096 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10097 }
10098 }
10099
10100 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10101 assert(rscratch != noreg || always_reachable(src3), "missing");
10102
10103 if (reachable(src3)) {
10104 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10105 } else {
10106 lea(rscratch, src3);
10107 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10108 }
10109 }
10110
10111 #if COMPILER2_OR_JVMCI
10112
10113 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10114 Register length, Register temp, int vec_enc) {
10115 // Computing mask for predicated vector store.
10116 movptr(temp, -1);
10117 bzhiq(temp, temp, length);
10118 kmov(mask, temp);
10119 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10120 }
10121
10122 // Set memory operation for length "less than" 64 bytes.
10123 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10124 XMMRegister xmm, KRegister mask, Register length,
10125 Register temp, bool use64byteVector) {
10126 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10127 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10128 if (!use64byteVector) {
10129 fill32(dst, disp, xmm);
10130 subptr(length, 32 >> shift);
10131 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10132 } else {
10133 assert(MaxVectorSize == 64, "vector length != 64");
10134 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10135 }
10136 }
10137
10138
10139 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10140 XMMRegister xmm, KRegister mask, Register length,
10141 Register temp) {
10142 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10143 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10144 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10145 }
10146
10147
10148 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10149 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10150 vmovdqu(dst, xmm);
10151 }
10152
10153 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10154 fill32(Address(dst, disp), xmm);
10155 }
10156
10157 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10158 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10159 if (!use64byteVector) {
10160 fill32(dst, xmm);
10161 fill32(dst.plus_disp(32), xmm);
10162 } else {
10163 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10164 }
10165 }
10166
10167 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10168 fill64(Address(dst, disp), xmm, use64byteVector);
10169 }
10170
10171 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10172 Register count, Register rtmp, XMMRegister xtmp) {
10173 Label L_exit;
10174 Label L_fill_start;
10175 Label L_fill_64_bytes;
10176 Label L_fill_96_bytes;
10177 Label L_fill_128_bytes;
10178 Label L_fill_128_bytes_loop;
10179 Label L_fill_128_loop_header;
10180 Label L_fill_128_bytes_loop_header;
10181 Label L_fill_128_bytes_loop_pre_header;
10182 Label L_fill_zmm_sequence;
10183
10184 int shift = -1;
10185 switch(type) {
10186 case T_BYTE: shift = 0;
10187 break;
10188 case T_SHORT: shift = 1;
10189 break;
10190 case T_INT: shift = 2;
10191 break;
10192 /* Uncomment when LONG fill stubs are supported.
10193 case T_LONG: shift = 3;
10194 break;
10195 */
10196 default:
10197 fatal("Unhandled type: %s\n", type2name(type));
10198 }
10199
10200 if ((CopyAVX3Threshold != 0) || (MaxVectorSize == 32)) {
10201
10202 if (MaxVectorSize == 64) {
10203 cmpq(count, CopyAVX3Threshold >> shift);
10204 jcc(Assembler::greater, L_fill_zmm_sequence);
10205 }
10206
10207 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10208
10209 bind(L_fill_start);
10210
10211 cmpq(count, 32 >> shift);
10212 jccb(Assembler::greater, L_fill_64_bytes);
10213 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10214 jmp(L_exit);
10215
10216 bind(L_fill_64_bytes);
10217 cmpq(count, 64 >> shift);
10218 jccb(Assembler::greater, L_fill_96_bytes);
10219 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10220 jmp(L_exit);
10221
10222 bind(L_fill_96_bytes);
10223 cmpq(count, 96 >> shift);
10224 jccb(Assembler::greater, L_fill_128_bytes);
10225 fill64(to, 0, xtmp);
10226 subq(count, 64 >> shift);
10227 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10228 jmp(L_exit);
10229
10230 bind(L_fill_128_bytes);
10231 cmpq(count, 128 >> shift);
10232 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10233 fill64(to, 0, xtmp);
10234 fill32(to, 64, xtmp);
10235 subq(count, 96 >> shift);
10236 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10237 jmp(L_exit);
10238
10239 bind(L_fill_128_bytes_loop_pre_header);
10240 {
10241 mov(rtmp, to);
10242 andq(rtmp, 31);
10243 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10244 negq(rtmp);
10245 addq(rtmp, 32);
10246 mov64(r8, -1L);
10247 bzhiq(r8, r8, rtmp);
10248 kmovql(k2, r8);
10249 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10250 addq(to, rtmp);
10251 shrq(rtmp, shift);
10252 subq(count, rtmp);
10253 }
10254
10255 cmpq(count, 128 >> shift);
10256 jcc(Assembler::less, L_fill_start);
10257
10258 bind(L_fill_128_bytes_loop_header);
10259 subq(count, 128 >> shift);
10260
10261 align32();
10262 bind(L_fill_128_bytes_loop);
10263 fill64(to, 0, xtmp);
10264 fill64(to, 64, xtmp);
10265 addq(to, 128);
10266 subq(count, 128 >> shift);
10267 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10268
10269 addq(count, 128 >> shift);
10270 jcc(Assembler::zero, L_exit);
10271 jmp(L_fill_start);
10272 }
10273
10274 if (MaxVectorSize == 64) {
10275 // Sequence using 64 byte ZMM register.
10276 Label L_fill_128_bytes_zmm;
10277 Label L_fill_192_bytes_zmm;
10278 Label L_fill_192_bytes_loop_zmm;
10279 Label L_fill_192_bytes_loop_header_zmm;
10280 Label L_fill_192_bytes_loop_pre_header_zmm;
10281 Label L_fill_start_zmm_sequence;
10282
10283 bind(L_fill_zmm_sequence);
10284 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10285
10286 bind(L_fill_start_zmm_sequence);
10287 cmpq(count, 64 >> shift);
10288 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10289 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10290 jmp(L_exit);
10291
10292 bind(L_fill_128_bytes_zmm);
10293 cmpq(count, 128 >> shift);
10294 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10295 fill64(to, 0, xtmp, true);
10296 subq(count, 64 >> shift);
10297 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10298 jmp(L_exit);
10299
10300 bind(L_fill_192_bytes_zmm);
10301 cmpq(count, 192 >> shift);
10302 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10303 fill64(to, 0, xtmp, true);
10304 fill64(to, 64, xtmp, true);
10305 subq(count, 128 >> shift);
10306 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10307 jmp(L_exit);
10308
10309 bind(L_fill_192_bytes_loop_pre_header_zmm);
10310 {
10311 movq(rtmp, to);
10312 andq(rtmp, 63);
10313 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10314 negq(rtmp);
10315 addq(rtmp, 64);
10316 mov64(r8, -1L);
10317 bzhiq(r8, r8, rtmp);
10318 kmovql(k2, r8);
10319 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10320 addq(to, rtmp);
10321 shrq(rtmp, shift);
10322 subq(count, rtmp);
10323 }
10324
10325 cmpq(count, 192 >> shift);
10326 jcc(Assembler::less, L_fill_start_zmm_sequence);
10327
10328 bind(L_fill_192_bytes_loop_header_zmm);
10329 subq(count, 192 >> shift);
10330
10331 align32();
10332 bind(L_fill_192_bytes_loop_zmm);
10333 fill64(to, 0, xtmp, true);
10334 fill64(to, 64, xtmp, true);
10335 fill64(to, 128, xtmp, true);
10336 addq(to, 192);
10337 subq(count, 192 >> shift);
10338 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10339
10340 addq(count, 192 >> shift);
10341 jcc(Assembler::zero, L_exit);
10342 jmp(L_fill_start_zmm_sequence);
10343 }
10344 bind(L_exit);
10345 }
10346 #endif //COMPILER2_OR_JVMCI
10347
10348
10349 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10350 Label done;
10351 cvttss2sil(dst, src);
10352 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10353 cmpl(dst, 0x80000000); // float_sign_flip
10354 jccb(Assembler::notEqual, done);
10355 subptr(rsp, 8);
10356 movflt(Address(rsp, 0), src);
10357 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10358 pop(dst);
10359 bind(done);
10360 }
10361
10362 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10363 Label done;
10364 cvttsd2sil(dst, src);
10365 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10366 cmpl(dst, 0x80000000); // float_sign_flip
10367 jccb(Assembler::notEqual, done);
10368 subptr(rsp, 8);
10369 movdbl(Address(rsp, 0), src);
10370 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10371 pop(dst);
10372 bind(done);
10373 }
10374
10375 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10376 Label done;
10377 cvttss2siq(dst, src);
10378 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10379 jccb(Assembler::notEqual, done);
10380 subptr(rsp, 8);
10381 movflt(Address(rsp, 0), src);
10382 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10383 pop(dst);
10384 bind(done);
10385 }
10386
10387 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10388 // Following code is line by line assembly translation rounding algorithm.
10389 // Please refer to java.lang.Math.round(float) algorithm for details.
10390 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10391 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10392 const int32_t FloatConsts_EXP_BIAS = 127;
10393 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10394 const int32_t MINUS_32 = 0xFFFFFFE0;
10395 Label L_special_case, L_block1, L_exit;
10396 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10397 movdl(dst, src);
10398 andl(dst, rtmp);
10399 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10400 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10401 subl(rtmp, dst);
10402 movl(rcx, rtmp);
10403 movl(dst, MINUS_32);
10404 testl(rtmp, dst);
10405 jccb(Assembler::notEqual, L_special_case);
10406 movdl(dst, src);
10407 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10408 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10409 movdl(rtmp, src);
10410 testl(rtmp, rtmp);
10411 jccb(Assembler::greaterEqual, L_block1);
10412 negl(dst);
10413 bind(L_block1);
10414 sarl(dst);
10415 addl(dst, 0x1);
10416 sarl(dst, 0x1);
10417 jmp(L_exit);
10418 bind(L_special_case);
10419 convert_f2i(dst, src);
10420 bind(L_exit);
10421 }
10422
10423 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10424 // Following code is line by line assembly translation rounding algorithm.
10425 // Please refer to java.lang.Math.round(double) algorithm for details.
10426 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10427 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10428 const int64_t DoubleConsts_EXP_BIAS = 1023;
10429 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10430 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10431 Label L_special_case, L_block1, L_exit;
10432 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10433 movq(dst, src);
10434 andq(dst, rtmp);
10435 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10436 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10437 subq(rtmp, dst);
10438 movq(rcx, rtmp);
10439 mov64(dst, MINUS_64);
10440 testq(rtmp, dst);
10441 jccb(Assembler::notEqual, L_special_case);
10442 movq(dst, src);
10443 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10444 andq(dst, rtmp);
10445 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10446 orq(dst, rtmp);
10447 movq(rtmp, src);
10448 testq(rtmp, rtmp);
10449 jccb(Assembler::greaterEqual, L_block1);
10450 negq(dst);
10451 bind(L_block1);
10452 sarq(dst);
10453 addq(dst, 0x1);
10454 sarq(dst, 0x1);
10455 jmp(L_exit);
10456 bind(L_special_case);
10457 convert_d2l(dst, src);
10458 bind(L_exit);
10459 }
10460
10461 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10462 Label done;
10463 cvttsd2siq(dst, src);
10464 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10465 jccb(Assembler::notEqual, done);
10466 subptr(rsp, 8);
10467 movdbl(Address(rsp, 0), src);
10468 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10469 pop(dst);
10470 bind(done);
10471 }
10472
10473 void MacroAssembler::cache_wb(Address line)
10474 {
10475 // 64 bit cpus always support clflush
10476 bool optimized = VM_Version::supports_clflushopt();
10477 bool no_evict = VM_Version::supports_clwb();
10478
10479 // prefer clwb (writeback without evict) otherwise
10480 // prefer clflushopt (potentially parallel writeback with evict)
10481 // otherwise fallback on clflush (serial writeback with evict)
10482
10483 if (optimized) {
10484 if (no_evict) {
10485 clwb(line);
10486 } else {
10487 clflushopt(line);
10488 }
10489 } else {
10490 // no need for fence when using CLFLUSH
10491 clflush(line);
10492 }
10493 }
10494
10495 void MacroAssembler::cache_wbsync(bool is_pre)
10496 {
10497 bool optimized = VM_Version::supports_clflushopt();
10498 bool no_evict = VM_Version::supports_clwb();
10499
10500 // pick the correct implementation
10501
10502 if (!is_pre && (optimized || no_evict)) {
10503 // need an sfence for post flush when using clflushopt or clwb
10504 // otherwise no no need for any synchroniaztion
10505
10506 sfence();
10507 }
10508 }
10509
10510 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10511 switch (cond) {
10512 // Note some conditions are synonyms for others
10513 case Assembler::zero: return Assembler::notZero;
10514 case Assembler::notZero: return Assembler::zero;
10515 case Assembler::less: return Assembler::greaterEqual;
10516 case Assembler::lessEqual: return Assembler::greater;
10517 case Assembler::greater: return Assembler::lessEqual;
10518 case Assembler::greaterEqual: return Assembler::less;
10519 case Assembler::below: return Assembler::aboveEqual;
10520 case Assembler::belowEqual: return Assembler::above;
10521 case Assembler::above: return Assembler::belowEqual;
10522 case Assembler::aboveEqual: return Assembler::below;
10523 case Assembler::overflow: return Assembler::noOverflow;
10524 case Assembler::noOverflow: return Assembler::overflow;
10525 case Assembler::negative: return Assembler::positive;
10526 case Assembler::positive: return Assembler::negative;
10527 case Assembler::parity: return Assembler::noParity;
10528 case Assembler::noParity: return Assembler::parity;
10529 }
10530 ShouldNotReachHere(); return Assembler::overflow;
10531 }
10532
10533 // This is simply a call to Thread::current()
10534 void MacroAssembler::get_thread_slow(Register thread) {
10535 if (thread != rax) {
10536 push(rax);
10537 }
10538 push(rdi);
10539 push(rsi);
10540 push(rdx);
10541 push(rcx);
10542 push(r8);
10543 push(r9);
10544 push(r10);
10545 push(r11);
10546
10547 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10548
10549 pop(r11);
10550 pop(r10);
10551 pop(r9);
10552 pop(r8);
10553 pop(rcx);
10554 pop(rdx);
10555 pop(rsi);
10556 pop(rdi);
10557 if (thread != rax) {
10558 mov(thread, rax);
10559 pop(rax);
10560 }
10561 }
10562
10563 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10564 Label L_stack_ok;
10565 if (bias == 0) {
10566 testptr(sp, 2 * wordSize - 1);
10567 } else {
10568 // lea(tmp, Address(rsp, bias);
10569 mov(tmp, sp);
10570 addptr(tmp, bias);
10571 testptr(tmp, 2 * wordSize - 1);
10572 }
10573 jcc(Assembler::equal, L_stack_ok);
10574 block_comment(msg);
10575 stop(msg);
10576 bind(L_stack_ok);
10577 }
10578
10579 // Implements fast-locking.
10580 //
10581 // obj: the object to be locked
10582 // reg_rax: rax
10583 // thread: the thread which attempts to lock obj
10584 // tmp: a temporary register
10585 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow) {
10586 Register thread = r15_thread;
10587
10588 assert(reg_rax == rax, "");
10589 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10590
10591 Label push;
10592 const Register top = tmp;
10593
10594 // Preload the markWord. It is important that this is the first
10595 // instruction emitted as it is part of C1's null check semantics.
10596 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10597
10598 if (UseObjectMonitorTable) {
10599 // Clear cache in case fast locking succeeds or we need to take the slow-path.
10600 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10601 }
10602
10603 if (DiagnoseSyncOnValueBasedClasses != 0) {
10604 load_klass(tmp, obj, rscratch1);
10605 testb(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
10606 jcc(Assembler::notZero, slow);
10607 }
10608
10609 // Load top.
10610 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10611
10612 // Check if the lock-stack is full.
10613 cmpl(top, LockStack::end_offset());
10614 jcc(Assembler::greaterEqual, slow);
10615
10616 // Check for recursion.
10617 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10618 jcc(Assembler::equal, push);
10619
10620 // Check header for monitor (0b10).
10621 testptr(reg_rax, markWord::monitor_value);
10622 jcc(Assembler::notZero, slow);
10623
10624 // Try to lock. Transition lock bits 0b01 => 0b00
10625 movptr(tmp, reg_rax);
10626 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10627 orptr(reg_rax, markWord::unlocked_value);
10628 // Mask inline_type bit such that we go to the slow path if object is an inline type
10629 andptr(reg_rax, ~((int) markWord::inline_type_bit_in_place));
10630
10631 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10632 jcc(Assembler::notEqual, slow);
10633
10634 // Restore top, CAS clobbers register.
10635 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10636
10637 bind(push);
10638 // After successful lock, push object on lock-stack.
10639 movptr(Address(thread, top), obj);
10640 incrementl(top, oopSize);
10641 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10642 }
10643
10644 // Implements fast-unlocking.
10645 //
10646 // obj: the object to be unlocked
10647 // reg_rax: rax
10648 // thread: the thread
10649 // tmp: a temporary register
10650 void MacroAssembler::fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow) {
10651 Register thread = r15_thread;
10652
10653 assert(reg_rax == rax, "");
10654 assert_different_registers(obj, reg_rax, thread, tmp);
10655
10656 Label unlocked, push_and_slow;
10657 const Register top = tmp;
10658
10659 // Check if obj is top of lock-stack.
10660 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10661 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10662 jcc(Assembler::notEqual, slow);
10663
10664 // Pop lock-stack.
10665 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10666 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10667
10668 // Check if recursive.
10669 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10670 jcc(Assembler::equal, unlocked);
10671
10672 // Not recursive. Check header for monitor (0b10).
10673 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10674 testptr(reg_rax, markWord::monitor_value);
10675 jcc(Assembler::notZero, push_and_slow);
10676
10677 #ifdef ASSERT
10678 // Check header not unlocked (0b01).
10679 Label not_unlocked;
10680 testptr(reg_rax, markWord::unlocked_value);
10681 jcc(Assembler::zero, not_unlocked);
10682 stop("fast_unlock already unlocked");
10683 bind(not_unlocked);
10684 #endif
10685
10686 // Try to unlock. Transition lock bits 0b00 => 0b01
10687 movptr(tmp, reg_rax);
10688 orptr(tmp, markWord::unlocked_value);
10689 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10690 jcc(Assembler::equal, unlocked);
10691
10692 bind(push_and_slow);
10693 // Restore lock-stack and handle the unlock in runtime.
10694 #ifdef ASSERT
10695 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10696 movptr(Address(thread, top), obj);
10697 #endif
10698 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10699 jmp(slow);
10700
10701 bind(unlocked);
10702 }
10703
10704 // Saves legacy GPRs state on stack.
10705 void MacroAssembler::save_legacy_gprs() {
10706 subq(rsp, 16 * wordSize);
10707 movq(Address(rsp, 15 * wordSize), rax);
10708 movq(Address(rsp, 14 * wordSize), rcx);
10709 movq(Address(rsp, 13 * wordSize), rdx);
10710 movq(Address(rsp, 12 * wordSize), rbx);
10711 movq(Address(rsp, 10 * wordSize), rbp);
10712 movq(Address(rsp, 9 * wordSize), rsi);
10713 movq(Address(rsp, 8 * wordSize), rdi);
10714 movq(Address(rsp, 7 * wordSize), r8);
10715 movq(Address(rsp, 6 * wordSize), r9);
10716 movq(Address(rsp, 5 * wordSize), r10);
10717 movq(Address(rsp, 4 * wordSize), r11);
10718 movq(Address(rsp, 3 * wordSize), r12);
10719 movq(Address(rsp, 2 * wordSize), r13);
10720 movq(Address(rsp, wordSize), r14);
10721 movq(Address(rsp, 0), r15);
10722 }
10723
10724 // Resotres back legacy GPRs state from stack.
10725 void MacroAssembler::restore_legacy_gprs() {
10726 movq(r15, Address(rsp, 0));
10727 movq(r14, Address(rsp, wordSize));
10728 movq(r13, Address(rsp, 2 * wordSize));
10729 movq(r12, Address(rsp, 3 * wordSize));
10730 movq(r11, Address(rsp, 4 * wordSize));
10731 movq(r10, Address(rsp, 5 * wordSize));
10732 movq(r9, Address(rsp, 6 * wordSize));
10733 movq(r8, Address(rsp, 7 * wordSize));
10734 movq(rdi, Address(rsp, 8 * wordSize));
10735 movq(rsi, Address(rsp, 9 * wordSize));
10736 movq(rbp, Address(rsp, 10 * wordSize));
10737 movq(rbx, Address(rsp, 12 * wordSize));
10738 movq(rdx, Address(rsp, 13 * wordSize));
10739 movq(rcx, Address(rsp, 14 * wordSize));
10740 movq(rax, Address(rsp, 15 * wordSize));
10741 addq(rsp, 16 * wordSize);
10742 }
10743
10744 void MacroAssembler::load_aotrc_address(Register reg, address a) {
10745 #if INCLUDE_CDS
10746 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
10747 if (AOTCodeCache::is_on_for_dump()) {
10748 // all aotrc field addresses should be registered in the AOTCodeCache address table
10749 lea(reg, ExternalAddress(a));
10750 } else {
10751 mov64(reg, (uint64_t)a);
10752 }
10753 #else
10754 ShouldNotReachHere();
10755 #endif
10756 }
10757
10758 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10759 if (VM_Version::supports_apx_f()) {
10760 esetzucc(comparison, dst);
10761 } else {
10762 setb(comparison, dst);
10763 movzbl(dst, dst);
10764 }
10765 }