1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/aotCodeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "ci/ciInlineKlass.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "interpreter/interpreterRuntime.hpp"
40 #include "jvm.h"
41 #include "memory/resourceArea.hpp"
42 #include "memory/universe.hpp"
43 #include "oops/accessDecorators.hpp"
44 #include "oops/compressedKlass.inline.hpp"
45 #include "oops/compressedOops.inline.hpp"
46 #include "oops/klass.inline.hpp"
47 #include "oops/resolvedFieldEntry.hpp"
48 #include "prims/methodHandles.hpp"
49 #include "runtime/arguments.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/interfaceSupport.inline.hpp"
52 #include "runtime/javaThread.hpp"
53 #include "runtime/jniHandles.hpp"
54 #include "runtime/objectMonitor.hpp"
55 #include "runtime/os.hpp"
56 #include "runtime/safepoint.hpp"
57 #include "runtime/safepointMechanism.hpp"
58 #include "runtime/sharedRuntime.hpp"
59 #include "runtime/signature_cc.hpp"
60 #include "runtime/stubRoutines.hpp"
61 #include "utilities/checkedCast.hpp"
62 #include "utilities/globalDefinitions.hpp"
63 #include "utilities/macros.hpp"
64 #include "vmreg_x86.inline.hpp"
65 #ifdef COMPILER2
66 #include "opto/output.hpp"
67 #endif
68
69 #ifdef PRODUCT
70 #define BLOCK_COMMENT(str) /* nothing */
71 #define STOP(error) stop(error)
72 #else
73 #define BLOCK_COMMENT(str) block_comment(str)
74 #define STOP(error) block_comment(error); stop(error)
75 #endif
76
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
79 #ifdef ASSERT
80 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
81 #endif
82
83 static const Assembler::Condition reverse[] = {
84 Assembler::noOverflow /* overflow = 0x0 */ ,
85 Assembler::overflow /* noOverflow = 0x1 */ ,
86 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
87 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
88 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
89 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
90 Assembler::above /* belowEqual = 0x6 */ ,
91 Assembler::belowEqual /* above = 0x7 */ ,
92 Assembler::positive /* negative = 0x8 */ ,
93 Assembler::negative /* positive = 0x9 */ ,
94 Assembler::noParity /* parity = 0xa */ ,
95 Assembler::parity /* noParity = 0xb */ ,
96 Assembler::greaterEqual /* less = 0xc */ ,
97 Assembler::less /* greaterEqual = 0xd */ ,
98 Assembler::greater /* lessEqual = 0xe */ ,
99 Assembler::lessEqual /* greater = 0xf, */
100
101 };
102
103
104 // Implementation of MacroAssembler
105
106 Address MacroAssembler::as_Address(AddressLiteral adr) {
107 // amd64 always does this as a pc-rel
108 // we can be absolute or disp based on the instruction type
109 // jmp/call are displacements others are absolute
110 assert(!adr.is_lval(), "must be rval");
111 assert(reachable(adr), "must be");
112 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
113
114 }
115
116 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
117 AddressLiteral base = adr.base();
118 lea(rscratch, base);
119 Address index = adr.index();
120 assert(index._disp == 0, "must not have disp"); // maybe it can?
121 Address array(rscratch, index._index, index._scale, index._disp);
122 return array;
123 }
124
125 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
126 Label L, E;
127
128 #ifdef _WIN64
129 // Windows always allocates space for it's register args
130 assert(num_args <= 4, "only register arguments supported");
131 subq(rsp, frame::arg_reg_save_area_bytes);
132 #endif
133
134 // Align stack if necessary
135 testl(rsp, 15);
136 jcc(Assembler::zero, L);
137
138 subq(rsp, 8);
139 call(RuntimeAddress(entry_point));
140 addq(rsp, 8);
141 jmp(E);
142
143 bind(L);
144 call(RuntimeAddress(entry_point));
145
146 bind(E);
147
148 #ifdef _WIN64
149 // restore stack pointer
150 addq(rsp, frame::arg_reg_save_area_bytes);
151 #endif
152 }
153
154 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
155 assert(!src2.is_lval(), "should use cmpptr");
156 assert(rscratch != noreg || always_reachable(src2), "missing");
157
158 if (reachable(src2)) {
159 cmpq(src1, as_Address(src2));
160 } else {
161 lea(rscratch, src2);
162 Assembler::cmpq(src1, Address(rscratch, 0));
163 }
164 }
165
166 int MacroAssembler::corrected_idivq(Register reg) {
167 // Full implementation of Java ldiv and lrem; checks for special
168 // case as described in JVM spec., p.243 & p.271. The function
169 // returns the (pc) offset of the idivl instruction - may be needed
170 // for implicit exceptions.
171 //
172 // normal case special case
173 //
174 // input : rax: dividend min_long
175 // reg: divisor (may not be eax/edx) -1
176 //
177 // output: rax: quotient (= rax idiv reg) min_long
178 // rdx: remainder (= rax irem reg) 0
179 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
180 static const int64_t min_long = 0x8000000000000000;
181 Label normal_case, special_case;
182
183 // check for special case
184 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
185 jcc(Assembler::notEqual, normal_case);
186 xorl(rdx, rdx); // prepare rdx for possible special case (where
187 // remainder = 0)
188 cmpq(reg, -1);
189 jcc(Assembler::equal, special_case);
190
191 // handle normal case
192 bind(normal_case);
193 cdqq();
194 int idivq_offset = offset();
195 idivq(reg);
196
197 // normal and special case exit
198 bind(special_case);
199
200 return idivq_offset;
201 }
202
203 void MacroAssembler::decrementq(Register reg, int value) {
204 if (value == min_jint) { subq(reg, value); return; }
205 if (value < 0) { incrementq(reg, -value); return; }
206 if (value == 0) { ; return; }
207 if (value == 1 && UseIncDec) { decq(reg) ; return; }
208 /* else */ { subq(reg, value) ; return; }
209 }
210
211 void MacroAssembler::decrementq(Address dst, int value) {
212 if (value == min_jint) { subq(dst, value); return; }
213 if (value < 0) { incrementq(dst, -value); return; }
214 if (value == 0) { ; return; }
215 if (value == 1 && UseIncDec) { decq(dst) ; return; }
216 /* else */ { subq(dst, value) ; return; }
217 }
218
219 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
220 assert(rscratch != noreg || always_reachable(dst), "missing");
221
222 if (reachable(dst)) {
223 incrementq(as_Address(dst));
224 } else {
225 lea(rscratch, dst);
226 incrementq(Address(rscratch, 0));
227 }
228 }
229
230 void MacroAssembler::incrementq(Register reg, int value) {
231 if (value == min_jint) { addq(reg, value); return; }
232 if (value < 0) { decrementq(reg, -value); return; }
233 if (value == 0) { ; return; }
234 if (value == 1 && UseIncDec) { incq(reg) ; return; }
235 /* else */ { addq(reg, value) ; return; }
236 }
237
238 void MacroAssembler::incrementq(Address dst, int value) {
239 if (value == min_jint) { addq(dst, value); return; }
240 if (value < 0) { decrementq(dst, -value); return; }
241 if (value == 0) { ; return; }
242 if (value == 1 && UseIncDec) { incq(dst) ; return; }
243 /* else */ { addq(dst, value) ; return; }
244 }
245
246 // 32bit can do a case table jump in one instruction but we no longer allow the base
247 // to be installed in the Address class
248 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
249 lea(rscratch, entry.base());
250 Address dispatch = entry.index();
251 assert(dispatch._base == noreg, "must be");
252 dispatch._base = rscratch;
253 jmp(dispatch);
254 }
255
256 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
257 ShouldNotReachHere(); // 64bit doesn't use two regs
258 cmpq(x_lo, y_lo);
259 }
260
261 void MacroAssembler::lea(Register dst, AddressLiteral src) {
262 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
263 }
264
265 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
266 lea(rscratch, adr);
267 movptr(dst, rscratch);
268 }
269
270 void MacroAssembler::leave() {
271 // %%% is this really better? Why not on 32bit too?
272 emit_int8((unsigned char)0xC9); // LEAVE
273 }
274
275 void MacroAssembler::lneg(Register hi, Register lo) {
276 ShouldNotReachHere(); // 64bit doesn't use two regs
277 negq(lo);
278 }
279
280 void MacroAssembler::movoop(Register dst, jobject obj) {
281 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
282 }
283
284 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
285 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
286 movq(dst, rscratch);
287 }
288
289 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
290 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
291 }
292
293 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
294 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
295 movq(dst, rscratch);
296 }
297
298 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
299 if (src.is_lval()) {
300 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
301 } else {
302 if (reachable(src)) {
303 movq(dst, as_Address(src));
304 } else {
305 lea(dst, src);
306 movq(dst, Address(dst, 0));
307 }
308 }
309 }
310
311 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
312 movq(as_Address(dst, rscratch), src);
313 }
314
315 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
316 movq(dst, as_Address(src, dst /*rscratch*/));
317 }
318
319 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
320 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
321 if (is_simm32(src)) {
322 movptr(dst, checked_cast<int32_t>(src));
323 } else {
324 mov64(rscratch, src);
325 movq(dst, rscratch);
326 }
327 }
328
329 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
330 movoop(rscratch, obj);
331 push(rscratch);
332 }
333
334 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
335 mov_metadata(rscratch, obj);
336 push(rscratch);
337 }
338
339 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
340 lea(rscratch, src);
341 if (src.is_lval()) {
342 push(rscratch);
343 } else {
344 pushq(Address(rscratch, 0));
345 }
346 }
347
348 static void pass_arg0(MacroAssembler* masm, Register arg) {
349 if (c_rarg0 != arg ) {
350 masm->mov(c_rarg0, arg);
351 }
352 }
353
354 static void pass_arg1(MacroAssembler* masm, Register arg) {
355 if (c_rarg1 != arg ) {
356 masm->mov(c_rarg1, arg);
357 }
358 }
359
360 static void pass_arg2(MacroAssembler* masm, Register arg) {
361 if (c_rarg2 != arg ) {
362 masm->mov(c_rarg2, arg);
363 }
364 }
365
366 static void pass_arg3(MacroAssembler* masm, Register arg) {
367 if (c_rarg3 != arg ) {
368 masm->mov(c_rarg3, arg);
369 }
370 }
371
372 void MacroAssembler::stop(const char* msg) {
373 if (ShowMessageBoxOnError) {
374 address rip = pc();
375 pusha(); // get regs on stack
376 lea(c_rarg1, InternalAddress(rip));
377 movq(c_rarg2, rsp); // pass pointer to regs array
378 }
379 // Skip AOT caching C strings in scratch buffer.
380 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
381 lea(c_rarg0, ExternalAddress((address) str));
382 andq(rsp, -16); // align stack as required by ABI
383 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
384 hlt();
385 }
386
387 void MacroAssembler::warn(const char* msg) {
388 push(rbp);
389 movq(rbp, rsp);
390 andq(rsp, -16); // align stack as required by push_CPU_state and call
391 push_CPU_state(); // keeps alignment at 16 bytes
392
393 #ifdef _WIN64
394 // Windows always allocates space for its register args
395 subq(rsp, frame::arg_reg_save_area_bytes);
396 #endif
397 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
398 lea(c_rarg0, ExternalAddress((address) str));
399 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
400
401 #ifdef _WIN64
402 // restore stack pointer
403 addq(rsp, frame::arg_reg_save_area_bytes);
404 #endif
405 pop_CPU_state();
406 mov(rsp, rbp);
407 pop(rbp);
408 }
409
410 void MacroAssembler::print_state() {
411 address rip = pc();
412 pusha(); // get regs on stack
413 push(rbp);
414 movq(rbp, rsp);
415 andq(rsp, -16); // align stack as required by push_CPU_state and call
416 push_CPU_state(); // keeps alignment at 16 bytes
417
418 lea(c_rarg0, InternalAddress(rip));
419 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
420 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
421
422 pop_CPU_state();
423 mov(rsp, rbp);
424 pop(rbp);
425 popa();
426 }
427
428 #ifndef PRODUCT
429 extern "C" void findpc(intptr_t x);
430 #endif
431
432 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
433 // In order to get locks to work, we need to fake a in_VM state
434 if (ShowMessageBoxOnError) {
435 JavaThread* thread = JavaThread::current();
436 JavaThreadState saved_state = thread->thread_state();
437 thread->set_thread_state(_thread_in_vm);
438 #ifndef PRODUCT
439 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
440 ttyLocker ttyl;
441 BytecodeCounter::print();
442 }
443 #endif
444 // To see where a verify_oop failed, get $ebx+40/X for this frame.
445 // XXX correct this offset for amd64
446 // This is the value of eip which points to where verify_oop will return.
447 if (os::message_box(msg, "Execution stopped, print registers?")) {
448 print_state64(pc, regs);
449 BREAKPOINT;
450 }
451 }
452 fatal("DEBUG MESSAGE: %s", msg);
453 }
454
455 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
456 ttyLocker ttyl;
457 DebuggingContext debugging{};
458 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
459 #ifndef PRODUCT
460 tty->cr();
461 findpc(pc);
462 tty->cr();
463 #endif
464 #define PRINT_REG(rax, value) \
465 { tty->print("%s = ", #rax); os::print_location(tty, value); }
466 PRINT_REG(rax, regs[15]);
467 PRINT_REG(rbx, regs[12]);
468 PRINT_REG(rcx, regs[14]);
469 PRINT_REG(rdx, regs[13]);
470 PRINT_REG(rdi, regs[8]);
471 PRINT_REG(rsi, regs[9]);
472 PRINT_REG(rbp, regs[10]);
473 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
474 PRINT_REG(rsp, (intptr_t)(®s[16]));
475 PRINT_REG(r8 , regs[7]);
476 PRINT_REG(r9 , regs[6]);
477 PRINT_REG(r10, regs[5]);
478 PRINT_REG(r11, regs[4]);
479 PRINT_REG(r12, regs[3]);
480 PRINT_REG(r13, regs[2]);
481 PRINT_REG(r14, regs[1]);
482 PRINT_REG(r15, regs[0]);
483 #undef PRINT_REG
484 // Print some words near the top of the stack.
485 int64_t* rsp = ®s[16];
486 int64_t* dump_sp = rsp;
487 for (int col1 = 0; col1 < 8; col1++) {
488 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
489 os::print_location(tty, *dump_sp++);
490 }
491 for (int row = 0; row < 25; row++) {
492 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
493 for (int col = 0; col < 4; col++) {
494 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
495 }
496 tty->cr();
497 }
498 // Print some instructions around pc:
499 Disassembler::decode((address)pc-64, (address)pc);
500 tty->print_cr("--------");
501 Disassembler::decode((address)pc, (address)pc+32);
502 }
503
504 // The java_calling_convention describes stack locations as ideal slots on
505 // a frame with no abi restrictions. Since we must observe abi restrictions
506 // (like the placement of the register window) the slots must be biased by
507 // the following value.
508 static int reg2offset_in(VMReg r) {
509 // Account for saved rbp and return address
510 // This should really be in_preserve_stack_slots
511 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
512 }
513
514 static int reg2offset_out(VMReg r) {
515 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
516 }
517
518 // A long move
519 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
520
521 // The calling conventions assures us that each VMregpair is either
522 // all really one physical register or adjacent stack slots.
523
524 if (src.is_single_phys_reg() ) {
525 if (dst.is_single_phys_reg()) {
526 if (dst.first() != src.first()) {
527 mov(dst.first()->as_Register(), src.first()->as_Register());
528 }
529 } else {
530 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
531 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
532 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
533 }
534 } else if (dst.is_single_phys_reg()) {
535 assert(src.is_single_reg(), "not a stack pair");
536 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
537 } else {
538 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
539 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
540 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
541 }
542 }
543
544 // A double move
545 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
546
547 // The calling conventions assures us that each VMregpair is either
548 // all really one physical register or adjacent stack slots.
549
550 if (src.is_single_phys_reg() ) {
551 if (dst.is_single_phys_reg()) {
552 // In theory these overlap but the ordering is such that this is likely a nop
553 if ( src.first() != dst.first()) {
554 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
555 }
556 } else {
557 assert(dst.is_single_reg(), "not a stack pair");
558 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
559 }
560 } else if (dst.is_single_phys_reg()) {
561 assert(src.is_single_reg(), "not a stack pair");
562 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
563 } else {
564 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
565 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
566 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
567 }
568 }
569
570
571 // A float arg may have to do float reg int reg conversion
572 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
573 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
574
575 // The calling conventions assures us that each VMregpair is either
576 // all really one physical register or adjacent stack slots.
577
578 if (src.first()->is_stack()) {
579 if (dst.first()->is_stack()) {
580 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
581 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
582 } else {
583 // stack to reg
584 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
585 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
586 }
587 } else if (dst.first()->is_stack()) {
588 // reg to stack
589 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
590 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
591 } else {
592 // reg to reg
593 // In theory these overlap but the ordering is such that this is likely a nop
594 if ( src.first() != dst.first()) {
595 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
596 }
597 }
598 }
599
600 // On 64 bit we will store integer like items to the stack as
601 // 64 bits items (x86_32/64 abi) even though java would only store
602 // 32bits for a parameter. On 32bit it will simply be 32 bits
603 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
604 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
605 if (src.first()->is_stack()) {
606 if (dst.first()->is_stack()) {
607 // stack to stack
608 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
609 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
610 } else {
611 // stack to reg
612 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
613 }
614 } else if (dst.first()->is_stack()) {
615 // reg to stack
616 // Do we really have to sign extend???
617 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
618 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
619 } else {
620 // Do we really have to sign extend???
621 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
622 if (dst.first() != src.first()) {
623 movq(dst.first()->as_Register(), src.first()->as_Register());
624 }
625 }
626 }
627
628 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
629 if (src.first()->is_stack()) {
630 if (dst.first()->is_stack()) {
631 // stack to stack
632 movq(rax, Address(rbp, reg2offset_in(src.first())));
633 movq(Address(rsp, reg2offset_out(dst.first())), rax);
634 } else {
635 // stack to reg
636 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
637 }
638 } else if (dst.first()->is_stack()) {
639 // reg to stack
640 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
641 } else {
642 if (dst.first() != src.first()) {
643 movq(dst.first()->as_Register(), src.first()->as_Register());
644 }
645 }
646 }
647
648 // An oop arg. Must pass a handle not the oop itself
649 void MacroAssembler::object_move(OopMap* map,
650 int oop_handle_offset,
651 int framesize_in_slots,
652 VMRegPair src,
653 VMRegPair dst,
654 bool is_receiver,
655 int* receiver_offset) {
656
657 // must pass a handle. First figure out the location we use as a handle
658
659 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
660
661 // See if oop is null if it is we need no handle
662
663 if (src.first()->is_stack()) {
664
665 // Oop is already on the stack as an argument
666 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
667 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
668 if (is_receiver) {
669 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
670 }
671
672 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
673 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
674 // conditionally move a null
675 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
676 } else {
677
678 // Oop is in a register we must store it to the space we reserve
679 // on the stack for oop_handles and pass a handle if oop is non-null
680
681 const Register rOop = src.first()->as_Register();
682 int oop_slot;
683 if (rOop == j_rarg0)
684 oop_slot = 0;
685 else if (rOop == j_rarg1)
686 oop_slot = 1;
687 else if (rOop == j_rarg2)
688 oop_slot = 2;
689 else if (rOop == j_rarg3)
690 oop_slot = 3;
691 else if (rOop == j_rarg4)
692 oop_slot = 4;
693 else {
694 assert(rOop == j_rarg5, "wrong register");
695 oop_slot = 5;
696 }
697
698 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
699 int offset = oop_slot*VMRegImpl::stack_slot_size;
700
701 map->set_oop(VMRegImpl::stack2reg(oop_slot));
702 // Store oop in handle area, may be null
703 movptr(Address(rsp, offset), rOop);
704 if (is_receiver) {
705 *receiver_offset = offset;
706 }
707
708 cmpptr(rOop, NULL_WORD);
709 lea(rHandle, Address(rsp, offset));
710 // conditionally move a null from the handle area where it was just stored
711 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
712 }
713
714 // If arg is on the stack then place it otherwise it is already in correct reg.
715 if (dst.first()->is_stack()) {
716 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
717 }
718 }
719
720 void MacroAssembler::addptr(Register dst, int32_t imm32) {
721 addq(dst, imm32);
722 }
723
724 void MacroAssembler::addptr(Register dst, Register src) {
725 addq(dst, src);
726 }
727
728 void MacroAssembler::addptr(Address dst, Register src) {
729 addq(dst, src);
730 }
731
732 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
733 assert(rscratch != noreg || always_reachable(src), "missing");
734
735 if (reachable(src)) {
736 Assembler::addsd(dst, as_Address(src));
737 } else {
738 lea(rscratch, src);
739 Assembler::addsd(dst, Address(rscratch, 0));
740 }
741 }
742
743 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
744 assert(rscratch != noreg || always_reachable(src), "missing");
745
746 if (reachable(src)) {
747 addss(dst, as_Address(src));
748 } else {
749 lea(rscratch, src);
750 addss(dst, Address(rscratch, 0));
751 }
752 }
753
754 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
755 assert(rscratch != noreg || always_reachable(src), "missing");
756
757 if (reachable(src)) {
758 Assembler::addpd(dst, as_Address(src));
759 } else {
760 lea(rscratch, src);
761 Assembler::addpd(dst, Address(rscratch, 0));
762 }
763 }
764
765 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
766 // Stub code is generated once and never copied.
767 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
768 void MacroAssembler::align64() {
769 align(64, (uint)(uintptr_t)pc());
770 }
771
772 void MacroAssembler::align32() {
773 align(32, (uint)(uintptr_t)pc());
774 }
775
776 void MacroAssembler::align(uint modulus) {
777 // 8273459: Ensure alignment is possible with current segment alignment
778 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
779 align(modulus, offset());
780 }
781
782 void MacroAssembler::align(uint modulus, uint target) {
783 if (target % modulus != 0) {
784 nop(modulus - (target % modulus));
785 }
786 }
787
788 void MacroAssembler::push_f(XMMRegister r) {
789 subptr(rsp, wordSize);
790 movflt(Address(rsp, 0), r);
791 }
792
793 void MacroAssembler::pop_f(XMMRegister r) {
794 movflt(r, Address(rsp, 0));
795 addptr(rsp, wordSize);
796 }
797
798 void MacroAssembler::push_d(XMMRegister r) {
799 subptr(rsp, 2 * wordSize);
800 movdbl(Address(rsp, 0), r);
801 }
802
803 void MacroAssembler::pop_d(XMMRegister r) {
804 movdbl(r, Address(rsp, 0));
805 addptr(rsp, 2 * Interpreter::stackElementSize);
806 }
807
808 void MacroAssembler::push_ppx(Register src) {
809 if (VM_Version::supports_apx_f()) {
810 pushp(src);
811 } else {
812 Assembler::push(src);
813 }
814 }
815
816 void MacroAssembler::pop_ppx(Register dst) {
817 if (VM_Version::supports_apx_f()) {
818 popp(dst);
819 } else {
820 Assembler::pop(dst);
821 }
822 }
823
824 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
825 // Used in sign-masking with aligned address.
826 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
827 assert(rscratch != noreg || always_reachable(src), "missing");
828
829 if (UseAVX > 2 &&
830 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
831 (dst->encoding() >= 16)) {
832 vpand(dst, dst, src, AVX_512bit, rscratch);
833 } else if (reachable(src)) {
834 Assembler::andpd(dst, as_Address(src));
835 } else {
836 lea(rscratch, src);
837 Assembler::andpd(dst, Address(rscratch, 0));
838 }
839 }
840
841 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
842 // Used in sign-masking with aligned address.
843 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
844 assert(rscratch != noreg || always_reachable(src), "missing");
845
846 if (reachable(src)) {
847 Assembler::andps(dst, as_Address(src));
848 } else {
849 lea(rscratch, src);
850 Assembler::andps(dst, Address(rscratch, 0));
851 }
852 }
853
854 void MacroAssembler::andptr(Register dst, int32_t imm32) {
855 andq(dst, imm32);
856 }
857
858 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
859 assert(rscratch != noreg || always_reachable(src), "missing");
860
861 if (reachable(src)) {
862 andq(dst, as_Address(src));
863 } else {
864 lea(rscratch, src);
865 andq(dst, Address(rscratch, 0));
866 }
867 }
868
869 void MacroAssembler::atomic_incl(Address counter_addr) {
870 lock();
871 incrementl(counter_addr);
872 }
873
874 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
875 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
876
877 if (reachable(counter_addr)) {
878 atomic_incl(as_Address(counter_addr));
879 } else {
880 lea(rscratch, counter_addr);
881 atomic_incl(Address(rscratch, 0));
882 }
883 }
884
885 void MacroAssembler::atomic_incq(Address counter_addr) {
886 lock();
887 incrementq(counter_addr);
888 }
889
890 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
891 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
892
893 if (reachable(counter_addr)) {
894 atomic_incq(as_Address(counter_addr));
895 } else {
896 lea(rscratch, counter_addr);
897 atomic_incq(Address(rscratch, 0));
898 }
899 }
900
901 // Writes to stack successive pages until offset reached to check for
902 // stack overflow + shadow pages. This clobbers tmp.
903 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
904 movptr(tmp, rsp);
905 // Bang stack for total size given plus shadow page size.
906 // Bang one page at a time because large size can bang beyond yellow and
907 // red zones.
908 Label loop;
909 bind(loop);
910 movl(Address(tmp, (-(int)os::vm_page_size())), size );
911 subptr(tmp, (int)os::vm_page_size());
912 subl(size, (int)os::vm_page_size());
913 jcc(Assembler::greater, loop);
914
915 // Bang down shadow pages too.
916 // At this point, (tmp-0) is the last address touched, so don't
917 // touch it again. (It was touched as (tmp-pagesize) but then tmp
918 // was post-decremented.) Skip this address by starting at i=1, and
919 // touch a few more pages below. N.B. It is important to touch all
920 // the way down including all pages in the shadow zone.
921 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
922 // this could be any sized move but this is can be a debugging crumb
923 // so the bigger the better.
924 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
925 }
926 }
927
928 void MacroAssembler::reserved_stack_check() {
929 // testing if reserved zone needs to be enabled
930 Label no_reserved_zone_enabling;
931
932 cmpptr(rsp, Address(r15_thread, JavaThread::reserved_stack_activation_offset()));
933 jcc(Assembler::below, no_reserved_zone_enabling);
934
935 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), r15_thread);
936 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
937 should_not_reach_here();
938
939 bind(no_reserved_zone_enabling);
940 }
941
942 void MacroAssembler::c2bool(Register x) {
943 // implements x == 0 ? 0 : 1
944 // note: must only look at least-significant byte of x
945 // since C-style booleans are stored in one byte
946 // only! (was bug)
947 andl(x, 0xFF);
948 setb(Assembler::notZero, x);
949 }
950
951 // Wouldn't need if AddressLiteral version had new name
952 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
953 Assembler::call(L, rtype);
954 }
955
956 void MacroAssembler::call(Register entry) {
957 Assembler::call(entry);
958 }
959
960 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
961 assert(rscratch != noreg || always_reachable(entry), "missing");
962
963 if (reachable(entry)) {
964 Assembler::call_literal(entry.target(), entry.rspec());
965 } else {
966 lea(rscratch, entry);
967 Assembler::call(rscratch);
968 }
969 }
970
971 void MacroAssembler::ic_call(address entry, jint method_index) {
972 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
973 // Needs full 64-bit immediate for later patching.
974 Assembler::mov64(rax, (int64_t)Universe::non_oop_word());
975 call(AddressLiteral(entry, rh));
976 }
977
978 int MacroAssembler::ic_check_size() {
979 return UseCompactObjectHeaders ? 17 : 14;
980 }
981
982 int MacroAssembler::ic_check(int end_alignment) {
983 Register receiver = j_rarg0;
984 Register data = rax;
985 Register temp = rscratch1;
986
987 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
988 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
989 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
990 // before the inline cache check here, and not after
991 align(end_alignment, offset() + ic_check_size());
992
993 int uep_offset = offset();
994
995 if (UseCompactObjectHeaders) {
996 load_narrow_klass_compact(temp, receiver);
997 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
998 } else {
999 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1000 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1001 }
1002
1003 // if inline cache check fails, then jump to runtime routine
1004 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1005 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1006
1007 return uep_offset;
1008 }
1009
1010 void MacroAssembler::emit_static_call_stub() {
1011 // Static stub relocation also tags the Method* in the code-stream.
1012 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1013 // This is recognized as unresolved by relocs/nativeinst/ic code.
1014 jump(RuntimeAddress(pc()));
1015 }
1016
1017 // Implementation of call_VM versions
1018
1019 void MacroAssembler::call_VM(Register oop_result,
1020 address entry_point,
1021 bool check_exceptions) {
1022 Label C, E;
1023 call(C, relocInfo::none);
1024 jmp(E);
1025
1026 bind(C);
1027 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1028 ret(0);
1029
1030 bind(E);
1031 }
1032
1033 void MacroAssembler::call_VM(Register oop_result,
1034 address entry_point,
1035 Register arg_1,
1036 bool check_exceptions) {
1037 Label C, E;
1038 call(C, relocInfo::none);
1039 jmp(E);
1040
1041 bind(C);
1042 pass_arg1(this, arg_1);
1043 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1044 ret(0);
1045
1046 bind(E);
1047 }
1048
1049 void MacroAssembler::call_VM(Register oop_result,
1050 address entry_point,
1051 Register arg_1,
1052 Register arg_2,
1053 bool check_exceptions) {
1054 Label C, E;
1055 call(C, relocInfo::none);
1056 jmp(E);
1057
1058 bind(C);
1059
1060 assert_different_registers(arg_1, c_rarg2);
1061
1062 pass_arg2(this, arg_2);
1063 pass_arg1(this, arg_1);
1064 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1065 ret(0);
1066
1067 bind(E);
1068 }
1069
1070 void MacroAssembler::call_VM(Register oop_result,
1071 address entry_point,
1072 Register arg_1,
1073 Register arg_2,
1074 Register arg_3,
1075 bool check_exceptions) {
1076 Label C, E;
1077 call(C, relocInfo::none);
1078 jmp(E);
1079
1080 bind(C);
1081
1082 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1083 assert_different_registers(arg_2, c_rarg3);
1084 pass_arg3(this, arg_3);
1085 pass_arg2(this, arg_2);
1086 pass_arg1(this, arg_1);
1087 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1088 ret(0);
1089
1090 bind(E);
1091 }
1092
1093 void MacroAssembler::call_VM(Register oop_result,
1094 Register last_java_sp,
1095 address entry_point,
1096 int number_of_arguments,
1097 bool check_exceptions) {
1098 call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1099 }
1100
1101 void MacroAssembler::call_VM(Register oop_result,
1102 Register last_java_sp,
1103 address entry_point,
1104 Register arg_1,
1105 bool check_exceptions) {
1106 pass_arg1(this, arg_1);
1107 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1108 }
1109
1110 void MacroAssembler::call_VM(Register oop_result,
1111 Register last_java_sp,
1112 address entry_point,
1113 Register arg_1,
1114 Register arg_2,
1115 bool check_exceptions) {
1116
1117 assert_different_registers(arg_1, c_rarg2);
1118 pass_arg2(this, arg_2);
1119 pass_arg1(this, arg_1);
1120 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1121 }
1122
1123 void MacroAssembler::call_VM(Register oop_result,
1124 Register last_java_sp,
1125 address entry_point,
1126 Register arg_1,
1127 Register arg_2,
1128 Register arg_3,
1129 bool check_exceptions) {
1130 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1131 assert_different_registers(arg_2, c_rarg3);
1132 pass_arg3(this, arg_3);
1133 pass_arg2(this, arg_2);
1134 pass_arg1(this, arg_1);
1135 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1136 }
1137
1138 void MacroAssembler::super_call_VM(Register oop_result,
1139 Register last_java_sp,
1140 address entry_point,
1141 int number_of_arguments,
1142 bool check_exceptions) {
1143 MacroAssembler::call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1144 }
1145
1146 void MacroAssembler::super_call_VM(Register oop_result,
1147 Register last_java_sp,
1148 address entry_point,
1149 Register arg_1,
1150 bool check_exceptions) {
1151 pass_arg1(this, arg_1);
1152 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1153 }
1154
1155 void MacroAssembler::super_call_VM(Register oop_result,
1156 Register last_java_sp,
1157 address entry_point,
1158 Register arg_1,
1159 Register arg_2,
1160 bool check_exceptions) {
1161
1162 assert_different_registers(arg_1, c_rarg2);
1163 pass_arg2(this, arg_2);
1164 pass_arg1(this, arg_1);
1165 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1166 }
1167
1168 void MacroAssembler::super_call_VM(Register oop_result,
1169 Register last_java_sp,
1170 address entry_point,
1171 Register arg_1,
1172 Register arg_2,
1173 Register arg_3,
1174 bool check_exceptions) {
1175 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1176 assert_different_registers(arg_2, c_rarg3);
1177 pass_arg3(this, arg_3);
1178 pass_arg2(this, arg_2);
1179 pass_arg1(this, arg_1);
1180 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1181 }
1182
1183 void MacroAssembler::call_VM_base(Register oop_result,
1184 Register last_java_sp,
1185 address entry_point,
1186 int number_of_arguments,
1187 bool check_exceptions) {
1188 Register java_thread = r15_thread;
1189
1190 // determine last_java_sp register
1191 if (!last_java_sp->is_valid()) {
1192 last_java_sp = rsp;
1193 }
1194 // debugging support
1195 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1196 #ifdef ASSERT
1197 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1198 // r12 is the heapbase.
1199 if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
1200 #endif // ASSERT
1201
1202 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1203 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1204
1205 // push java thread (becomes first argument of C function)
1206
1207 mov(c_rarg0, r15_thread);
1208
1209 // set last Java frame before call
1210 assert(last_java_sp != rbp, "can't use ebp/rbp");
1211
1212 // Only interpreter should have to set fp
1213 set_last_Java_frame(last_java_sp, rbp, nullptr, rscratch1);
1214
1215 // do the call, remove parameters
1216 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1217
1218 #ifdef ASSERT
1219 // Check that thread register is not clobbered.
1220 guarantee(java_thread != rax, "change this code");
1221 push(rax);
1222 { Label L;
1223 get_thread_slow(rax);
1224 cmpptr(java_thread, rax);
1225 jcc(Assembler::equal, L);
1226 STOP("MacroAssembler::call_VM_base: java_thread not callee saved?");
1227 bind(L);
1228 }
1229 pop(rax);
1230 #endif
1231
1232 // reset last Java frame
1233 // Only interpreter should have to clear fp
1234 reset_last_Java_frame(true);
1235
1236 // C++ interp handles this in the interpreter
1237 check_and_handle_popframe();
1238 check_and_handle_earlyret();
1239
1240 if (check_exceptions) {
1241 // check for pending exceptions (java_thread is set upon return)
1242 cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
1243 // This used to conditionally jump to forward_exception however it is
1244 // possible if we relocate that the branch will not reach. So we must jump
1245 // around so we can always reach
1246
1247 Label ok;
1248 jcc(Assembler::equal, ok);
1249 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1250 bind(ok);
1251 }
1252
1253 // get oop result if there is one and reset the value in the thread
1254 if (oop_result->is_valid()) {
1255 get_vm_result_oop(oop_result);
1256 }
1257 }
1258
1259 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1260 // Calculate the value for last_Java_sp somewhat subtle.
1261 // call_VM does an intermediate call which places a return address on
1262 // the stack just under the stack pointer as the user finished with it.
1263 // This allows use to retrieve last_Java_pc from last_Java_sp[-1].
1264
1265 // We've pushed one address, correct last_Java_sp
1266 lea(rax, Address(rsp, wordSize));
1267
1268 call_VM_base(oop_result, rax, entry_point, number_of_arguments, check_exceptions);
1269 }
1270
1271 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1272 void MacroAssembler::call_VM_leaf0(address entry_point) {
1273 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1274 }
1275
1276 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1277 call_VM_leaf_base(entry_point, number_of_arguments);
1278 }
1279
1280 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1281 pass_arg0(this, arg_0);
1282 call_VM_leaf(entry_point, 1);
1283 }
1284
1285 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1286
1287 assert_different_registers(arg_0, c_rarg1);
1288 pass_arg1(this, arg_1);
1289 pass_arg0(this, arg_0);
1290 call_VM_leaf(entry_point, 2);
1291 }
1292
1293 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1294 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1295 assert_different_registers(arg_1, c_rarg2);
1296 pass_arg2(this, arg_2);
1297 pass_arg1(this, arg_1);
1298 pass_arg0(this, arg_0);
1299 call_VM_leaf(entry_point, 3);
1300 }
1301
1302 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1303 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1304 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1305 assert_different_registers(arg_2, c_rarg3);
1306 pass_arg3(this, arg_3);
1307 pass_arg2(this, arg_2);
1308 pass_arg1(this, arg_1);
1309 pass_arg0(this, arg_0);
1310 call_VM_leaf(entry_point, 3);
1311 }
1312
1313 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1314 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1315 }
1316
1317 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1318 pass_arg0(this, arg_0);
1319 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1320 }
1321
1322 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1323 assert_different_registers(arg_0, c_rarg1);
1324 pass_arg1(this, arg_1);
1325 pass_arg0(this, arg_0);
1326 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1327 }
1328
1329 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1330 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1331 assert_different_registers(arg_1, c_rarg2);
1332 pass_arg2(this, arg_2);
1333 pass_arg1(this, arg_1);
1334 pass_arg0(this, arg_0);
1335 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1336 }
1337
1338 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1339 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1340 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1341 assert_different_registers(arg_2, c_rarg3);
1342 pass_arg3(this, arg_3);
1343 pass_arg2(this, arg_2);
1344 pass_arg1(this, arg_1);
1345 pass_arg0(this, arg_0);
1346 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1347 }
1348
1349 void MacroAssembler::get_vm_result_oop(Register oop_result) {
1350 movptr(oop_result, Address(r15_thread, JavaThread::vm_result_oop_offset()));
1351 movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
1352 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1353 }
1354
1355 void MacroAssembler::get_vm_result_metadata(Register metadata_result) {
1356 movptr(metadata_result, Address(r15_thread, JavaThread::vm_result_metadata_offset()));
1357 movptr(Address(r15_thread, JavaThread::vm_result_metadata_offset()), NULL_WORD);
1358 }
1359
1360 void MacroAssembler::check_and_handle_earlyret() {
1361 }
1362
1363 void MacroAssembler::check_and_handle_popframe() {
1364 }
1365
1366 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1367 assert(rscratch != noreg || always_reachable(src1), "missing");
1368
1369 if (reachable(src1)) {
1370 cmpl(as_Address(src1), imm);
1371 } else {
1372 lea(rscratch, src1);
1373 cmpl(Address(rscratch, 0), imm);
1374 }
1375 }
1376
1377 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1378 assert(!src2.is_lval(), "use cmpptr");
1379 assert(rscratch != noreg || always_reachable(src2), "missing");
1380
1381 if (reachable(src2)) {
1382 cmpl(src1, as_Address(src2));
1383 } else {
1384 lea(rscratch, src2);
1385 cmpl(src1, Address(rscratch, 0));
1386 }
1387 }
1388
1389 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1390 Assembler::cmpl(src1, imm);
1391 }
1392
1393 void MacroAssembler::cmp32(Register src1, Address src2) {
1394 Assembler::cmpl(src1, src2);
1395 }
1396
1397 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1398 ucomisd(opr1, opr2);
1399
1400 Label L;
1401 if (unordered_is_less) {
1402 movl(dst, -1);
1403 jcc(Assembler::parity, L);
1404 jcc(Assembler::below , L);
1405 movl(dst, 0);
1406 jcc(Assembler::equal , L);
1407 increment(dst);
1408 } else { // unordered is greater
1409 movl(dst, 1);
1410 jcc(Assembler::parity, L);
1411 jcc(Assembler::above , L);
1412 movl(dst, 0);
1413 jcc(Assembler::equal , L);
1414 decrementl(dst);
1415 }
1416 bind(L);
1417 }
1418
1419 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1420 ucomiss(opr1, opr2);
1421
1422 Label L;
1423 if (unordered_is_less) {
1424 movl(dst, -1);
1425 jcc(Assembler::parity, L);
1426 jcc(Assembler::below , L);
1427 movl(dst, 0);
1428 jcc(Assembler::equal , L);
1429 increment(dst);
1430 } else { // unordered is greater
1431 movl(dst, 1);
1432 jcc(Assembler::parity, L);
1433 jcc(Assembler::above , L);
1434 movl(dst, 0);
1435 jcc(Assembler::equal , L);
1436 decrementl(dst);
1437 }
1438 bind(L);
1439 }
1440
1441
1442 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1443 assert(rscratch != noreg || always_reachable(src1), "missing");
1444
1445 if (reachable(src1)) {
1446 cmpb(as_Address(src1), imm);
1447 } else {
1448 lea(rscratch, src1);
1449 cmpb(Address(rscratch, 0), imm);
1450 }
1451 }
1452
1453 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1454 assert(rscratch != noreg || always_reachable(src2), "missing");
1455
1456 if (src2.is_lval()) {
1457 movptr(rscratch, src2);
1458 Assembler::cmpq(src1, rscratch);
1459 } else if (reachable(src2)) {
1460 cmpq(src1, as_Address(src2));
1461 } else {
1462 lea(rscratch, src2);
1463 Assembler::cmpq(src1, Address(rscratch, 0));
1464 }
1465 }
1466
1467 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1468 assert(src2.is_lval(), "not a mem-mem compare");
1469 // moves src2's literal address
1470 movptr(rscratch, src2);
1471 Assembler::cmpq(src1, rscratch);
1472 }
1473
1474 void MacroAssembler::cmpoop(Register src1, Register src2) {
1475 cmpptr(src1, src2);
1476 }
1477
1478 void MacroAssembler::cmpoop(Register src1, Address src2) {
1479 cmpptr(src1, src2);
1480 }
1481
1482 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1483 movoop(rscratch, src2);
1484 cmpptr(src1, rscratch);
1485 }
1486
1487 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1488 assert(rscratch != noreg || always_reachable(adr), "missing");
1489
1490 if (reachable(adr)) {
1491 lock();
1492 cmpxchgptr(reg, as_Address(adr));
1493 } else {
1494 lea(rscratch, adr);
1495 lock();
1496 cmpxchgptr(reg, Address(rscratch, 0));
1497 }
1498 }
1499
1500 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1501 cmpxchgq(reg, adr);
1502 }
1503
1504 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1505 assert(rscratch != noreg || always_reachable(src), "missing");
1506
1507 if (reachable(src)) {
1508 Assembler::comisd(dst, as_Address(src));
1509 } else {
1510 lea(rscratch, src);
1511 Assembler::comisd(dst, Address(rscratch, 0));
1512 }
1513 }
1514
1515 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1516 assert(rscratch != noreg || always_reachable(src), "missing");
1517
1518 if (reachable(src)) {
1519 Assembler::comiss(dst, as_Address(src));
1520 } else {
1521 lea(rscratch, src);
1522 Assembler::comiss(dst, Address(rscratch, 0));
1523 }
1524 }
1525
1526
1527 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1528 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1529
1530 Condition negated_cond = negate_condition(cond);
1531 Label L;
1532 jcc(negated_cond, L);
1533 pushf(); // Preserve flags
1534 atomic_incl(counter_addr, rscratch);
1535 popf();
1536 bind(L);
1537 }
1538
1539 int MacroAssembler::corrected_idivl(Register reg) {
1540 // Full implementation of Java idiv and irem; checks for
1541 // special case as described in JVM spec., p.243 & p.271.
1542 // The function returns the (pc) offset of the idivl
1543 // instruction - may be needed for implicit exceptions.
1544 //
1545 // normal case special case
1546 //
1547 // input : rax,: dividend min_int
1548 // reg: divisor (may not be rax,/rdx) -1
1549 //
1550 // output: rax,: quotient (= rax, idiv reg) min_int
1551 // rdx: remainder (= rax, irem reg) 0
1552 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1553 const int min_int = 0x80000000;
1554 Label normal_case, special_case;
1555
1556 // check for special case
1557 cmpl(rax, min_int);
1558 jcc(Assembler::notEqual, normal_case);
1559 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1560 cmpl(reg, -1);
1561 jcc(Assembler::equal, special_case);
1562
1563 // handle normal case
1564 bind(normal_case);
1565 cdql();
1566 int idivl_offset = offset();
1567 idivl(reg);
1568
1569 // normal and special case exit
1570 bind(special_case);
1571
1572 return idivl_offset;
1573 }
1574
1575
1576
1577 void MacroAssembler::decrementl(Register reg, int value) {
1578 if (value == min_jint) {subl(reg, value) ; return; }
1579 if (value < 0) { incrementl(reg, -value); return; }
1580 if (value == 0) { ; return; }
1581 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1582 /* else */ { subl(reg, value) ; return; }
1583 }
1584
1585 void MacroAssembler::decrementl(Address dst, int value) {
1586 if (value == min_jint) {subl(dst, value) ; return; }
1587 if (value < 0) { incrementl(dst, -value); return; }
1588 if (value == 0) { ; return; }
1589 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1590 /* else */ { subl(dst, value) ; return; }
1591 }
1592
1593 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1594 assert(shift_value > 0, "illegal shift value");
1595 Label _is_positive;
1596 testl (reg, reg);
1597 jcc (Assembler::positive, _is_positive);
1598 int offset = (1 << shift_value) - 1 ;
1599
1600 if (offset == 1) {
1601 incrementl(reg);
1602 } else {
1603 addl(reg, offset);
1604 }
1605
1606 bind (_is_positive);
1607 sarl(reg, shift_value);
1608 }
1609
1610 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1611 assert(rscratch != noreg || always_reachable(src), "missing");
1612
1613 if (reachable(src)) {
1614 Assembler::divsd(dst, as_Address(src));
1615 } else {
1616 lea(rscratch, src);
1617 Assembler::divsd(dst, Address(rscratch, 0));
1618 }
1619 }
1620
1621 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1622 assert(rscratch != noreg || always_reachable(src), "missing");
1623
1624 if (reachable(src)) {
1625 Assembler::divss(dst, as_Address(src));
1626 } else {
1627 lea(rscratch, src);
1628 Assembler::divss(dst, Address(rscratch, 0));
1629 }
1630 }
1631
1632 void MacroAssembler::enter() {
1633 push(rbp);
1634 mov(rbp, rsp);
1635 }
1636
1637 void MacroAssembler::post_call_nop() {
1638 if (!Continuations::enabled()) {
1639 return;
1640 }
1641 InstructionMark im(this);
1642 relocate(post_call_nop_Relocation::spec());
1643 InlineSkippedInstructionsCounter skipCounter(this);
1644 emit_int8((uint8_t)0x0f);
1645 emit_int8((uint8_t)0x1f);
1646 emit_int8((uint8_t)0x84);
1647 emit_int8((uint8_t)0x00);
1648 emit_int32(0x00);
1649 }
1650
1651 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1652 assert(rscratch != noreg || always_reachable(src), "missing");
1653 if (reachable(src)) {
1654 Assembler::mulpd(dst, as_Address(src));
1655 } else {
1656 lea(rscratch, src);
1657 Assembler::mulpd(dst, Address(rscratch, 0));
1658 }
1659 }
1660
1661 // dst = c = a * b + c
1662 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1663 Assembler::vfmadd231sd(c, a, b);
1664 if (dst != c) {
1665 movdbl(dst, c);
1666 }
1667 }
1668
1669 // dst = c = a * b + c
1670 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1671 Assembler::vfmadd231ss(c, a, b);
1672 if (dst != c) {
1673 movflt(dst, c);
1674 }
1675 }
1676
1677 // dst = c = a * b + c
1678 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1679 Assembler::vfmadd231pd(c, a, b, vector_len);
1680 if (dst != c) {
1681 vmovdqu(dst, c);
1682 }
1683 }
1684
1685 // dst = c = a * b + c
1686 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1687 Assembler::vfmadd231ps(c, a, b, vector_len);
1688 if (dst != c) {
1689 vmovdqu(dst, c);
1690 }
1691 }
1692
1693 // dst = c = a * b + c
1694 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1695 Assembler::vfmadd231pd(c, a, b, vector_len);
1696 if (dst != c) {
1697 vmovdqu(dst, c);
1698 }
1699 }
1700
1701 // dst = c = a * b + c
1702 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1703 Assembler::vfmadd231ps(c, a, b, vector_len);
1704 if (dst != c) {
1705 vmovdqu(dst, c);
1706 }
1707 }
1708
1709 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
1710 assert(rscratch != noreg || always_reachable(dst), "missing");
1711
1712 if (reachable(dst)) {
1713 incrementl(as_Address(dst));
1714 } else {
1715 lea(rscratch, dst);
1716 incrementl(Address(rscratch, 0));
1717 }
1718 }
1719
1720 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
1721 incrementl(as_Address(dst, rscratch));
1722 }
1723
1724 void MacroAssembler::incrementl(Register reg, int value) {
1725 if (value == min_jint) {addl(reg, value) ; return; }
1726 if (value < 0) { decrementl(reg, -value); return; }
1727 if (value == 0) { ; return; }
1728 if (value == 1 && UseIncDec) { incl(reg) ; return; }
1729 /* else */ { addl(reg, value) ; return; }
1730 }
1731
1732 void MacroAssembler::incrementl(Address dst, int value) {
1733 if (value == min_jint) {addl(dst, value) ; return; }
1734 if (value < 0) { decrementl(dst, -value); return; }
1735 if (value == 0) { ; return; }
1736 if (value == 1 && UseIncDec) { incl(dst) ; return; }
1737 /* else */ { addl(dst, value) ; return; }
1738 }
1739
1740 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
1741 assert(rscratch != noreg || always_reachable(dst), "missing");
1742 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
1743 if (reachable(dst)) {
1744 jmp_literal(dst.target(), dst.rspec());
1745 } else {
1746 lea(rscratch, dst);
1747 jmp(rscratch);
1748 }
1749 }
1750
1751 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
1752 assert(rscratch != noreg || always_reachable(dst), "missing");
1753 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
1754 if (reachable(dst)) {
1755 InstructionMark im(this);
1756 relocate(dst.reloc());
1757 const int short_size = 2;
1758 const int long_size = 6;
1759 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
1760 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
1761 // 0111 tttn #8-bit disp
1762 emit_int8(0x70 | cc);
1763 emit_int8((offs - short_size) & 0xFF);
1764 } else {
1765 // 0000 1111 1000 tttn #32-bit disp
1766 emit_int8(0x0F);
1767 emit_int8((unsigned char)(0x80 | cc));
1768 emit_int32(offs - long_size);
1769 }
1770 } else {
1771 #ifdef ASSERT
1772 warning("reversing conditional branch");
1773 #endif /* ASSERT */
1774 Label skip;
1775 jccb(reverse[cc], skip);
1776 lea(rscratch, dst);
1777 Assembler::jmp(rscratch);
1778 bind(skip);
1779 }
1780 }
1781
1782 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
1783 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
1784 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
1785
1786 stmxcsr(mxcsr_save);
1787 movl(tmp, mxcsr_save);
1788 if (EnableX86ECoreOpts) {
1789 // The mxcsr_std has status bits set for performance on ECore
1790 orl(tmp, 0x003f);
1791 } else {
1792 // Mask out status bits (only check control and mask bits)
1793 andl(tmp, 0xFFC0);
1794 }
1795 cmp32(tmp, mxcsr_std, rscratch);
1796 }
1797
1798 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
1799 assert(rscratch != noreg || always_reachable(src), "missing");
1800
1801 if (reachable(src)) {
1802 Assembler::ldmxcsr(as_Address(src));
1803 } else {
1804 lea(rscratch, src);
1805 Assembler::ldmxcsr(Address(rscratch, 0));
1806 }
1807 }
1808
1809 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1810 int off = offset();
1811 movsbl(dst, src); // movsxb
1812 return off;
1813 }
1814
1815 // Note: load_signed_short used to be called load_signed_word.
1816 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
1817 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
1818 // The term "word" in HotSpot means a 32- or 64-bit machine word.
1819 int MacroAssembler::load_signed_short(Register dst, Address src) {
1820 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
1821 // version but this is what 64bit has always done. This seems to imply
1822 // that users are only using 32bits worth.
1823 int off = offset();
1824 movswl(dst, src); // movsxw
1825 return off;
1826 }
1827
1828 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1829 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1830 // and "3.9 Partial Register Penalties", p. 22).
1831 int off = offset();
1832 movzbl(dst, src); // movzxb
1833 return off;
1834 }
1835
1836 // Note: load_unsigned_short used to be called load_unsigned_word.
1837 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1838 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1839 // and "3.9 Partial Register Penalties", p. 22).
1840 int off = offset();
1841 movzwl(dst, src); // movzxw
1842 return off;
1843 }
1844
1845 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1846 switch (size_in_bytes) {
1847 case 8: movq(dst, src); break;
1848 case 4: movl(dst, src); break;
1849 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1850 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1851 default: ShouldNotReachHere();
1852 }
1853 }
1854
1855 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1856 switch (size_in_bytes) {
1857 case 8: movq(dst, src); break;
1858 case 4: movl(dst, src); break;
1859 case 2: movw(dst, src); break;
1860 case 1: movb(dst, src); break;
1861 default: ShouldNotReachHere();
1862 }
1863 }
1864
1865 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
1866 assert(rscratch != noreg || always_reachable(dst), "missing");
1867
1868 if (reachable(dst)) {
1869 movl(as_Address(dst), src);
1870 } else {
1871 lea(rscratch, dst);
1872 movl(Address(rscratch, 0), src);
1873 }
1874 }
1875
1876 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
1877 if (reachable(src)) {
1878 movl(dst, as_Address(src));
1879 } else {
1880 lea(dst, src);
1881 movl(dst, Address(dst, 0));
1882 }
1883 }
1884
1885 // C++ bool manipulation
1886
1887 void MacroAssembler::movbool(Register dst, Address src) {
1888 if(sizeof(bool) == 1)
1889 movb(dst, src);
1890 else if(sizeof(bool) == 2)
1891 movw(dst, src);
1892 else if(sizeof(bool) == 4)
1893 movl(dst, src);
1894 else
1895 // unsupported
1896 ShouldNotReachHere();
1897 }
1898
1899 void MacroAssembler::movbool(Address dst, bool boolconst) {
1900 if(sizeof(bool) == 1)
1901 movb(dst, (int) boolconst);
1902 else if(sizeof(bool) == 2)
1903 movw(dst, (int) boolconst);
1904 else if(sizeof(bool) == 4)
1905 movl(dst, (int) boolconst);
1906 else
1907 // unsupported
1908 ShouldNotReachHere();
1909 }
1910
1911 void MacroAssembler::movbool(Address dst, Register src) {
1912 if(sizeof(bool) == 1)
1913 movb(dst, src);
1914 else if(sizeof(bool) == 2)
1915 movw(dst, src);
1916 else if(sizeof(bool) == 4)
1917 movl(dst, src);
1918 else
1919 // unsupported
1920 ShouldNotReachHere();
1921 }
1922
1923 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1924 assert(rscratch != noreg || always_reachable(src), "missing");
1925
1926 if (reachable(src)) {
1927 movdl(dst, as_Address(src));
1928 } else {
1929 lea(rscratch, src);
1930 movdl(dst, Address(rscratch, 0));
1931 }
1932 }
1933
1934 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
1935 assert(rscratch != noreg || always_reachable(src), "missing");
1936
1937 if (reachable(src)) {
1938 movq(dst, as_Address(src));
1939 } else {
1940 lea(rscratch, src);
1941 movq(dst, Address(rscratch, 0));
1942 }
1943 }
1944
1945 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1946 assert(rscratch != noreg || always_reachable(src), "missing");
1947
1948 if (reachable(src)) {
1949 if (UseXmmLoadAndClearUpper) {
1950 movsd (dst, as_Address(src));
1951 } else {
1952 movlpd(dst, as_Address(src));
1953 }
1954 } else {
1955 lea(rscratch, src);
1956 if (UseXmmLoadAndClearUpper) {
1957 movsd (dst, Address(rscratch, 0));
1958 } else {
1959 movlpd(dst, Address(rscratch, 0));
1960 }
1961 }
1962 }
1963
1964 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
1965 assert(rscratch != noreg || always_reachable(src), "missing");
1966
1967 if (reachable(src)) {
1968 movss(dst, as_Address(src));
1969 } else {
1970 lea(rscratch, src);
1971 movss(dst, Address(rscratch, 0));
1972 }
1973 }
1974
1975 void MacroAssembler::movhlf(XMMRegister dst, XMMRegister src, Register rscratch) {
1976 if (VM_Version::supports_avx10_2()) {
1977 evmovw(dst, src);
1978 } else {
1979 assert(rscratch != noreg, "missing");
1980 evmovw(rscratch, src);
1981 evmovw(dst, rscratch);
1982 }
1983 }
1984
1985 void MacroAssembler::mov64(Register dst, int64_t imm64) {
1986 if (is_uimm32(imm64)) {
1987 movl(dst, checked_cast<uint32_t>(imm64));
1988 } else if (is_simm32(imm64)) {
1989 movq(dst, checked_cast<int32_t>(imm64));
1990 } else {
1991 Assembler::mov64(dst, imm64);
1992 }
1993 }
1994
1995 void MacroAssembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) {
1996 Assembler::mov64(dst, imm64, rtype, format);
1997 }
1998
1999 void MacroAssembler::movptr(Register dst, Register src) {
2000 movq(dst, src);
2001 }
2002
2003 void MacroAssembler::movptr(Register dst, Address src) {
2004 movq(dst, src);
2005 }
2006
2007 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2008 void MacroAssembler::movptr(Register dst, intptr_t src) {
2009 mov64(dst, src);
2010 }
2011
2012 void MacroAssembler::movptr(Address dst, Register src) {
2013 movq(dst, src);
2014 }
2015
2016 void MacroAssembler::movptr(Address dst, int32_t src) {
2017 movslq(dst, src);
2018 }
2019
2020 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2021 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2022 Assembler::movdqu(dst, src);
2023 }
2024
2025 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2026 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2027 Assembler::movdqu(dst, src);
2028 }
2029
2030 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2031 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2032 Assembler::movdqu(dst, src);
2033 }
2034
2035 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2036 assert(rscratch != noreg || always_reachable(src), "missing");
2037
2038 if (reachable(src)) {
2039 movdqu(dst, as_Address(src));
2040 } else {
2041 lea(rscratch, src);
2042 movdqu(dst, Address(rscratch, 0));
2043 }
2044 }
2045
2046 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2047 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2048 Assembler::vmovdqu(dst, src);
2049 }
2050
2051 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2052 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2053 Assembler::vmovdqu(dst, src);
2054 }
2055
2056 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2057 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2058 Assembler::vmovdqu(dst, src);
2059 }
2060
2061 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2062 assert(rscratch != noreg || always_reachable(src), "missing");
2063
2064 if (reachable(src)) {
2065 vmovdqu(dst, as_Address(src));
2066 }
2067 else {
2068 lea(rscratch, src);
2069 vmovdqu(dst, Address(rscratch, 0));
2070 }
2071 }
2072
2073 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2074 assert(rscratch != noreg || always_reachable(src), "missing");
2075
2076 if (vector_len == AVX_512bit) {
2077 evmovdquq(dst, src, AVX_512bit, rscratch);
2078 } else if (vector_len == AVX_256bit) {
2079 vmovdqu(dst, src, rscratch);
2080 } else {
2081 movdqu(dst, src, rscratch);
2082 }
2083 }
2084
2085 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2086 if (vector_len == AVX_512bit) {
2087 evmovdquq(dst, src, AVX_512bit);
2088 } else if (vector_len == AVX_256bit) {
2089 vmovdqu(dst, src);
2090 } else {
2091 movdqu(dst, src);
2092 }
2093 }
2094
2095 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2096 if (vector_len == AVX_512bit) {
2097 evmovdquq(dst, src, AVX_512bit);
2098 } else if (vector_len == AVX_256bit) {
2099 vmovdqu(dst, src);
2100 } else {
2101 movdqu(dst, src);
2102 }
2103 }
2104
2105 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2106 if (vector_len == AVX_512bit) {
2107 evmovdquq(dst, src, AVX_512bit);
2108 } else if (vector_len == AVX_256bit) {
2109 vmovdqu(dst, src);
2110 } else {
2111 movdqu(dst, src);
2112 }
2113 }
2114
2115 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2116 assert(rscratch != noreg || always_reachable(src), "missing");
2117
2118 if (reachable(src)) {
2119 vmovdqa(dst, as_Address(src));
2120 }
2121 else {
2122 lea(rscratch, src);
2123 vmovdqa(dst, Address(rscratch, 0));
2124 }
2125 }
2126
2127 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2128 assert(rscratch != noreg || always_reachable(src), "missing");
2129
2130 if (vector_len == AVX_512bit) {
2131 evmovdqaq(dst, src, AVX_512bit, rscratch);
2132 } else if (vector_len == AVX_256bit) {
2133 vmovdqa(dst, src, rscratch);
2134 } else {
2135 movdqa(dst, src, rscratch);
2136 }
2137 }
2138
2139 void MacroAssembler::vmovdqa(XMMRegister dst, Address src, int vector_len) {
2140 if (vector_len == AVX_512bit) {
2141 Assembler::evmovdqaq(dst, src, AVX_512bit);
2142 } else if (vector_len == AVX_256bit) {
2143 Assembler::vmovdqa(dst, src);
2144 } else {
2145 Assembler::movdqa(dst, src);
2146 }
2147 }
2148
2149 void MacroAssembler::vmovdqa(Address dst, XMMRegister src, int vector_len) {
2150 if (vector_len == AVX_512bit) {
2151 Assembler::evmovdqaq(dst, src, AVX_512bit);
2152 } else if (vector_len == AVX_256bit) {
2153 Assembler::vmovdqa(dst, src);
2154 } else {
2155 Assembler::movdqa(dst, src);
2156 }
2157 }
2158
2159 void MacroAssembler::kmov(KRegister dst, Address src) {
2160 if (VM_Version::supports_avx512bw()) {
2161 kmovql(dst, src);
2162 } else {
2163 assert(VM_Version::supports_evex(), "");
2164 kmovwl(dst, src);
2165 }
2166 }
2167
2168 void MacroAssembler::kmov(Address dst, KRegister src) {
2169 if (VM_Version::supports_avx512bw()) {
2170 kmovql(dst, src);
2171 } else {
2172 assert(VM_Version::supports_evex(), "");
2173 kmovwl(dst, src);
2174 }
2175 }
2176
2177 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2178 if (VM_Version::supports_avx512bw()) {
2179 kmovql(dst, src);
2180 } else {
2181 assert(VM_Version::supports_evex(), "");
2182 kmovwl(dst, src);
2183 }
2184 }
2185
2186 void MacroAssembler::kmov(Register dst, KRegister src) {
2187 if (VM_Version::supports_avx512bw()) {
2188 kmovql(dst, src);
2189 } else {
2190 assert(VM_Version::supports_evex(), "");
2191 kmovwl(dst, src);
2192 }
2193 }
2194
2195 void MacroAssembler::kmov(KRegister dst, Register src) {
2196 if (VM_Version::supports_avx512bw()) {
2197 kmovql(dst, src);
2198 } else {
2199 assert(VM_Version::supports_evex(), "");
2200 kmovwl(dst, src);
2201 }
2202 }
2203
2204 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2205 assert(rscratch != noreg || always_reachable(src), "missing");
2206
2207 if (reachable(src)) {
2208 kmovql(dst, as_Address(src));
2209 } else {
2210 lea(rscratch, src);
2211 kmovql(dst, Address(rscratch, 0));
2212 }
2213 }
2214
2215 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2216 assert(rscratch != noreg || always_reachable(src), "missing");
2217
2218 if (reachable(src)) {
2219 kmovwl(dst, as_Address(src));
2220 } else {
2221 lea(rscratch, src);
2222 kmovwl(dst, Address(rscratch, 0));
2223 }
2224 }
2225
2226 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2227 int vector_len, Register rscratch) {
2228 assert(rscratch != noreg || always_reachable(src), "missing");
2229
2230 if (reachable(src)) {
2231 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2232 } else {
2233 lea(rscratch, src);
2234 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2235 }
2236 }
2237
2238 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2239 int vector_len, Register rscratch) {
2240 assert(rscratch != noreg || always_reachable(src), "missing");
2241
2242 if (reachable(src)) {
2243 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2244 } else {
2245 lea(rscratch, src);
2246 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2247 }
2248 }
2249
2250 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2251 assert(rscratch != noreg || always_reachable(src), "missing");
2252
2253 if (reachable(src)) {
2254 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2255 } else {
2256 lea(rscratch, src);
2257 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2258 }
2259 }
2260
2261 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2262 assert(rscratch != noreg || always_reachable(src), "missing");
2263
2264 if (reachable(src)) {
2265 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2266 } else {
2267 lea(rscratch, src);
2268 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2269 }
2270 }
2271
2272 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2273 assert(rscratch != noreg || always_reachable(src), "missing");
2274
2275 if (reachable(src)) {
2276 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2277 } else {
2278 lea(rscratch, src);
2279 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2280 }
2281 }
2282
2283 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2284 assert(rscratch != noreg || always_reachable(src), "missing");
2285
2286 if (reachable(src)) {
2287 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2288 } else {
2289 lea(rscratch, src);
2290 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2291 }
2292 }
2293
2294 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2295 assert(rscratch != noreg || always_reachable(src), "missing");
2296
2297 if (reachable(src)) {
2298 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2299 } else {
2300 lea(rscratch, src);
2301 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2302 }
2303 }
2304
2305 void MacroAssembler::movapd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2306 assert(rscratch != noreg || always_reachable(src), "missing");
2307
2308 if (reachable(src)) {
2309 Assembler::movapd(dst, as_Address(src));
2310 } else {
2311 lea(rscratch, src);
2312 Assembler::movapd(dst, Address(rscratch, 0));
2313 }
2314 }
2315
2316 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2317 assert(rscratch != noreg || always_reachable(src), "missing");
2318
2319 if (reachable(src)) {
2320 Assembler::movdqa(dst, as_Address(src));
2321 } else {
2322 lea(rscratch, src);
2323 Assembler::movdqa(dst, Address(rscratch, 0));
2324 }
2325 }
2326
2327 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2328 assert(rscratch != noreg || always_reachable(src), "missing");
2329
2330 if (reachable(src)) {
2331 Assembler::movsd(dst, as_Address(src));
2332 } else {
2333 lea(rscratch, src);
2334 Assembler::movsd(dst, Address(rscratch, 0));
2335 }
2336 }
2337
2338 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2339 assert(rscratch != noreg || always_reachable(src), "missing");
2340
2341 if (reachable(src)) {
2342 Assembler::movss(dst, as_Address(src));
2343 } else {
2344 lea(rscratch, src);
2345 Assembler::movss(dst, Address(rscratch, 0));
2346 }
2347 }
2348
2349 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2350 assert(rscratch != noreg || always_reachable(src), "missing");
2351
2352 if (reachable(src)) {
2353 Assembler::movddup(dst, as_Address(src));
2354 } else {
2355 lea(rscratch, src);
2356 Assembler::movddup(dst, Address(rscratch, 0));
2357 }
2358 }
2359
2360 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2361 assert(rscratch != noreg || always_reachable(src), "missing");
2362
2363 if (reachable(src)) {
2364 Assembler::vmovddup(dst, as_Address(src), vector_len);
2365 } else {
2366 lea(rscratch, src);
2367 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2368 }
2369 }
2370
2371 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2372 assert(rscratch != noreg || always_reachable(src), "missing");
2373
2374 if (reachable(src)) {
2375 Assembler::mulsd(dst, as_Address(src));
2376 } else {
2377 lea(rscratch, src);
2378 Assembler::mulsd(dst, Address(rscratch, 0));
2379 }
2380 }
2381
2382 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2383 assert(rscratch != noreg || always_reachable(src), "missing");
2384
2385 if (reachable(src)) {
2386 Assembler::mulss(dst, as_Address(src));
2387 } else {
2388 lea(rscratch, src);
2389 Assembler::mulss(dst, Address(rscratch, 0));
2390 }
2391 }
2392
2393 void MacroAssembler::null_check(Register reg, int offset) {
2394 if (needs_explicit_null_check(offset)) {
2395 // provoke OS null exception if reg is null by
2396 // accessing M[reg] w/o changing any (non-CC) registers
2397 // NOTE: cmpl is plenty here to provoke a segv
2398 cmpptr(rax, Address(reg, 0));
2399 // Note: should probably use testl(rax, Address(reg, 0));
2400 // may be shorter code (however, this version of
2401 // testl needs to be implemented first)
2402 } else {
2403 // nothing to do, (later) access of M[reg + offset]
2404 // will provoke OS null exception if reg is null
2405 }
2406 }
2407
2408 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2409 andptr(markword, markWord::inline_type_pattern_mask);
2410 cmpptr(markword, markWord::inline_type_pattern);
2411 jcc(Assembler::equal, is_inline_type);
2412 }
2413
2414 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null) {
2415 if (can_be_null) {
2416 testptr(object, object);
2417 jcc(Assembler::zero, not_inline_type);
2418 }
2419 const int is_inline_type_mask = markWord::inline_type_pattern;
2420 movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2421 andptr(tmp, is_inline_type_mask);
2422 cmpptr(tmp, is_inline_type_mask);
2423 jcc(Assembler::notEqual, not_inline_type);
2424 }
2425
2426 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2427 movl(temp_reg, flags);
2428 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2429 jcc(Assembler::notEqual, is_null_free_inline_type);
2430 }
2431
2432 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2433 movl(temp_reg, flags);
2434 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2435 jcc(Assembler::equal, not_null_free_inline_type);
2436 }
2437
2438 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2439 movl(temp_reg, flags);
2440 testl(temp_reg, 1 << ResolvedFieldEntry::is_flat_shift);
2441 jcc(Assembler::notEqual, is_flat);
2442 }
2443
2444 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2445 Label test_mark_word;
2446 // load mark word
2447 movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2448 // check displaced
2449 testl(temp_reg, markWord::unlocked_value);
2450 jccb(Assembler::notZero, test_mark_word);
2451 // slow path use klass prototype
2452 push(rscratch1);
2453 load_prototype_header(temp_reg, oop, rscratch1);
2454 pop(rscratch1);
2455
2456 bind(test_mark_word);
2457 testl(temp_reg, test_bit);
2458 jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
2459 }
2460
2461 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg,
2462 Label& is_flat_array) {
2463 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2464 }
2465
2466 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2467 Label& is_non_flat_array) {
2468 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2469 }
2470
2471 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
2472 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2473 }
2474
2475 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2476 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2477 }
2478
2479 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2480 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2481 jcc(Assembler::notZero, is_flat_array);
2482 }
2483
2484 void MacroAssembler::os_breakpoint() {
2485 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2486 // (e.g., MSVC can't call ps() otherwise)
2487 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2488 }
2489
2490 void MacroAssembler::unimplemented(const char* what) {
2491 const char* buf = nullptr;
2492 {
2493 ResourceMark rm;
2494 stringStream ss;
2495 ss.print("unimplemented: %s", what);
2496 buf = code_string(ss.as_string());
2497 }
2498 stop(buf);
2499 }
2500
2501 #define XSTATE_BV 0x200
2502
2503 void MacroAssembler::pop_CPU_state() {
2504 pop_FPU_state();
2505 pop_IU_state();
2506 }
2507
2508 void MacroAssembler::pop_FPU_state() {
2509 fxrstor(Address(rsp, 0));
2510 addptr(rsp, FPUStateSizeInWords * wordSize);
2511 }
2512
2513 void MacroAssembler::pop_IU_state() {
2514 popa();
2515 addq(rsp, 8);
2516 popf();
2517 }
2518
2519 // Save Integer and Float state
2520 // Warning: Stack must be 16 byte aligned (64bit)
2521 void MacroAssembler::push_CPU_state() {
2522 push_IU_state();
2523 push_FPU_state();
2524 }
2525
2526 void MacroAssembler::push_FPU_state() {
2527 subptr(rsp, FPUStateSizeInWords * wordSize);
2528 fxsave(Address(rsp, 0));
2529 }
2530
2531 void MacroAssembler::push_IU_state() {
2532 // Push flags first because pusha kills them
2533 pushf();
2534 // Make sure rsp stays 16-byte aligned
2535 subq(rsp, 8);
2536 pusha();
2537 }
2538
2539 void MacroAssembler::push_cont_fastpath() {
2540 if (!Continuations::enabled()) return;
2541
2542 Label L_done;
2543 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2544 jccb(Assembler::belowEqual, L_done);
2545 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), rsp);
2546 bind(L_done);
2547 }
2548
2549 void MacroAssembler::pop_cont_fastpath() {
2550 if (!Continuations::enabled()) return;
2551
2552 Label L_done;
2553 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2554 jccb(Assembler::below, L_done);
2555 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), 0);
2556 bind(L_done);
2557 }
2558
2559 #ifdef ASSERT
2560 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2561 Label no_cont;
2562 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2563 testl(cont, cont);
2564 jcc(Assembler::zero, no_cont);
2565 stop(name);
2566 bind(no_cont);
2567 }
2568 #endif
2569
2570 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { // determine java_thread register
2571 // we must set sp to zero to clear frame
2572 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2573 // must clear fp, so that compiled frames are not confused; it is
2574 // possible that we need it only for debugging
2575 if (clear_fp) {
2576 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2577 }
2578 // Always clear the pc because it could have been set by make_walkable()
2579 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2580 vzeroupper();
2581 }
2582
2583 void MacroAssembler::round_to(Register reg, int modulus) {
2584 addptr(reg, modulus - 1);
2585 andptr(reg, -modulus);
2586 }
2587
2588 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod) {
2589 if (at_return) {
2590 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2591 // we may safely use rsp instead to perform the stack watermark check.
2592 cmpptr(in_nmethod ? rsp : rbp, Address(r15_thread, JavaThread::polling_word_offset()));
2593 jcc(Assembler::above, slow_path);
2594 return;
2595 }
2596 testb(Address(r15_thread, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2597 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2598 }
2599
2600 // Calls to C land
2601 //
2602 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2603 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2604 // has to be reset to 0. This is required to allow proper stack traversal.
2605 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2606 Register last_java_fp,
2607 address last_java_pc,
2608 Register rscratch) {
2609 vzeroupper();
2610 // determine last_java_sp register
2611 if (!last_java_sp->is_valid()) {
2612 last_java_sp = rsp;
2613 }
2614 // last_java_fp is optional
2615 if (last_java_fp->is_valid()) {
2616 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2617 }
2618 // last_java_pc is optional
2619 if (last_java_pc != nullptr) {
2620 Address java_pc(r15_thread,
2621 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
2622 lea(java_pc, InternalAddress(last_java_pc), rscratch);
2623 }
2624 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2625 }
2626
2627 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2628 Register last_java_fp,
2629 Label &L,
2630 Register scratch) {
2631 lea(scratch, L);
2632 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
2633 set_last_Java_frame(last_java_sp, last_java_fp, nullptr, scratch);
2634 }
2635
2636 void MacroAssembler::shlptr(Register dst, int imm8) {
2637 shlq(dst, imm8);
2638 }
2639
2640 void MacroAssembler::shrptr(Register dst, int imm8) {
2641 shrq(dst, imm8);
2642 }
2643
2644 void MacroAssembler::sign_extend_byte(Register reg) {
2645 movsbl(reg, reg); // movsxb
2646 }
2647
2648 void MacroAssembler::sign_extend_short(Register reg) {
2649 movswl(reg, reg); // movsxw
2650 }
2651
2652 void MacroAssembler::narrow_subword_type(Register reg, BasicType bt) {
2653 assert(is_subword_type(bt), "required");
2654 switch (bt) {
2655 case T_BOOLEAN: andl(reg, 1); break;
2656 case T_BYTE: movsbl(reg, reg); break;
2657 case T_CHAR: movzwl(reg, reg); break;
2658 case T_SHORT: movswl(reg, reg); break;
2659 default: ShouldNotReachHere();
2660 }
2661 }
2662
2663 void MacroAssembler::testl(Address dst, int32_t imm32) {
2664 if (imm32 >= 0 && is8bit(imm32)) {
2665 testb(dst, imm32);
2666 } else {
2667 Assembler::testl(dst, imm32);
2668 }
2669 }
2670
2671 void MacroAssembler::testl(Register dst, int32_t imm32) {
2672 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
2673 testb(dst, imm32);
2674 } else {
2675 Assembler::testl(dst, imm32);
2676 }
2677 }
2678
2679 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2680 assert(always_reachable(src), "Address should be reachable");
2681 testl(dst, as_Address(src));
2682 }
2683
2684 void MacroAssembler::testq(Address dst, int32_t imm32) {
2685 if (imm32 >= 0) {
2686 testl(dst, imm32);
2687 } else {
2688 Assembler::testq(dst, imm32);
2689 }
2690 }
2691
2692 void MacroAssembler::testq(Register dst, int32_t imm32) {
2693 if (imm32 >= 0) {
2694 testl(dst, imm32);
2695 } else {
2696 Assembler::testq(dst, imm32);
2697 }
2698 }
2699
2700 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2701 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2702 Assembler::pcmpeqb(dst, src);
2703 }
2704
2705 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2706 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2707 Assembler::pcmpeqw(dst, src);
2708 }
2709
2710 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2711 assert((dst->encoding() < 16),"XMM register should be 0-15");
2712 Assembler::pcmpestri(dst, src, imm8);
2713 }
2714
2715 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2716 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2717 Assembler::pcmpestri(dst, src, imm8);
2718 }
2719
2720 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2721 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2722 Assembler::pmovzxbw(dst, src);
2723 }
2724
2725 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2726 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2727 Assembler::pmovzxbw(dst, src);
2728 }
2729
2730 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2731 assert((src->encoding() < 16),"XMM register should be 0-15");
2732 Assembler::pmovmskb(dst, src);
2733 }
2734
2735 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2736 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2737 Assembler::ptest(dst, src);
2738 }
2739
2740 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2741 assert(rscratch != noreg || always_reachable(src), "missing");
2742
2743 if (reachable(src)) {
2744 Assembler::sqrtss(dst, as_Address(src));
2745 } else {
2746 lea(rscratch, src);
2747 Assembler::sqrtss(dst, Address(rscratch, 0));
2748 }
2749 }
2750
2751 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2752 assert(rscratch != noreg || always_reachable(src), "missing");
2753
2754 if (reachable(src)) {
2755 Assembler::subsd(dst, as_Address(src));
2756 } else {
2757 lea(rscratch, src);
2758 Assembler::subsd(dst, Address(rscratch, 0));
2759 }
2760 }
2761
2762 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
2763 assert(rscratch != noreg || always_reachable(src), "missing");
2764
2765 if (reachable(src)) {
2766 Assembler::roundsd(dst, as_Address(src), rmode);
2767 } else {
2768 lea(rscratch, src);
2769 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
2770 }
2771 }
2772
2773 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2774 assert(rscratch != noreg || always_reachable(src), "missing");
2775
2776 if (reachable(src)) {
2777 Assembler::subss(dst, as_Address(src));
2778 } else {
2779 lea(rscratch, src);
2780 Assembler::subss(dst, Address(rscratch, 0));
2781 }
2782 }
2783
2784 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2785 assert(rscratch != noreg || always_reachable(src), "missing");
2786
2787 if (reachable(src)) {
2788 Assembler::ucomisd(dst, as_Address(src));
2789 } else {
2790 lea(rscratch, src);
2791 Assembler::ucomisd(dst, Address(rscratch, 0));
2792 }
2793 }
2794
2795 void MacroAssembler::evucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2796 assert(rscratch != noreg || always_reachable(src), "missing");
2797
2798 if (reachable(src)) {
2799 Assembler::evucomxsd(dst, as_Address(src));
2800 } else {
2801 lea(rscratch, src);
2802 Assembler::evucomxsd(dst, Address(rscratch, 0));
2803 }
2804 }
2805
2806 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2807 assert(rscratch != noreg || always_reachable(src), "missing");
2808
2809 if (reachable(src)) {
2810 Assembler::ucomiss(dst, as_Address(src));
2811 } else {
2812 lea(rscratch, src);
2813 Assembler::ucomiss(dst, Address(rscratch, 0));
2814 }
2815 }
2816
2817 void MacroAssembler::evucomxss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2818 assert(rscratch != noreg || always_reachable(src), "missing");
2819
2820 if (reachable(src)) {
2821 Assembler::evucomxss(dst, as_Address(src));
2822 } else {
2823 lea(rscratch, src);
2824 Assembler::evucomxss(dst, Address(rscratch, 0));
2825 }
2826 }
2827
2828 void MacroAssembler::evucomish(XMMRegister dst, AddressLiteral src, Register rscratch) {
2829 assert(rscratch != noreg || always_reachable(src), "missing");
2830
2831 if (reachable(src)) {
2832 Assembler::evucomish(dst, as_Address(src));
2833 } else {
2834 lea(rscratch, src);
2835 Assembler::evucomish(dst, Address(rscratch, 0));
2836 }
2837 }
2838
2839 void MacroAssembler::evucomxsh(XMMRegister dst, AddressLiteral src, Register rscratch) {
2840 assert(rscratch != noreg || always_reachable(src), "missing");
2841
2842 if (reachable(src)) {
2843 Assembler::evucomxsh(dst, as_Address(src));
2844 } else {
2845 lea(rscratch, src);
2846 Assembler::evucomxsh(dst, Address(rscratch, 0));
2847 }
2848 }
2849
2850 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2851 assert(rscratch != noreg || always_reachable(src), "missing");
2852
2853 // Used in sign-bit flipping with aligned address.
2854 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2855
2856 if (UseAVX > 2 &&
2857 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2858 (dst->encoding() >= 16)) {
2859 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2860 } else if (reachable(src)) {
2861 Assembler::xorpd(dst, as_Address(src));
2862 } else {
2863 lea(rscratch, src);
2864 Assembler::xorpd(dst, Address(rscratch, 0));
2865 }
2866 }
2867
2868 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
2869 if (UseAVX > 2 &&
2870 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2871 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2872 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2873 } else {
2874 Assembler::xorpd(dst, src);
2875 }
2876 }
2877
2878 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
2879 if (UseAVX > 2 &&
2880 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2881 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2882 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2883 } else {
2884 Assembler::xorps(dst, src);
2885 }
2886 }
2887
2888 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
2889 assert(rscratch != noreg || always_reachable(src), "missing");
2890
2891 // Used in sign-bit flipping with aligned address.
2892 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2893
2894 if (UseAVX > 2 &&
2895 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2896 (dst->encoding() >= 16)) {
2897 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2898 } else if (reachable(src)) {
2899 Assembler::xorps(dst, as_Address(src));
2900 } else {
2901 lea(rscratch, src);
2902 Assembler::xorps(dst, Address(rscratch, 0));
2903 }
2904 }
2905
2906 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
2907 assert(rscratch != noreg || always_reachable(src), "missing");
2908
2909 // Used in sign-bit flipping with aligned address.
2910 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
2911 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2912 if (reachable(src)) {
2913 Assembler::pshufb(dst, as_Address(src));
2914 } else {
2915 lea(rscratch, src);
2916 Assembler::pshufb(dst, Address(rscratch, 0));
2917 }
2918 }
2919
2920 // AVX 3-operands instructions
2921
2922 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2923 assert(rscratch != noreg || always_reachable(src), "missing");
2924
2925 if (reachable(src)) {
2926 vaddsd(dst, nds, as_Address(src));
2927 } else {
2928 lea(rscratch, src);
2929 vaddsd(dst, nds, Address(rscratch, 0));
2930 }
2931 }
2932
2933 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2934 assert(rscratch != noreg || always_reachable(src), "missing");
2935
2936 if (reachable(src)) {
2937 vaddss(dst, nds, as_Address(src));
2938 } else {
2939 lea(rscratch, src);
2940 vaddss(dst, nds, Address(rscratch, 0));
2941 }
2942 }
2943
2944 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2945 assert(UseAVX > 0, "requires some form of AVX");
2946 assert(rscratch != noreg || always_reachable(src), "missing");
2947
2948 if (reachable(src)) {
2949 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
2950 } else {
2951 lea(rscratch, src);
2952 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
2953 }
2954 }
2955
2956 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2957 assert(UseAVX > 0, "requires some form of AVX");
2958 assert(rscratch != noreg || always_reachable(src), "missing");
2959
2960 if (reachable(src)) {
2961 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
2962 } else {
2963 lea(rscratch, src);
2964 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
2965 }
2966 }
2967
2968 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2969 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2970 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2971
2972 vandps(dst, nds, negate_field, vector_len, rscratch);
2973 }
2974
2975 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2976 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2977 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2978
2979 vandpd(dst, nds, negate_field, vector_len, rscratch);
2980 }
2981
2982 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2983 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2984 Assembler::vpaddb(dst, nds, src, vector_len);
2985 }
2986
2987 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2988 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2989 Assembler::vpaddb(dst, nds, src, vector_len);
2990 }
2991
2992 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2993 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2994 Assembler::vpaddw(dst, nds, src, vector_len);
2995 }
2996
2997 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2998 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2999 Assembler::vpaddw(dst, nds, src, vector_len);
3000 }
3001
3002 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3003 assert(rscratch != noreg || always_reachable(src), "missing");
3004
3005 if (reachable(src)) {
3006 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3007 } else {
3008 lea(rscratch, src);
3009 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3010 }
3011 }
3012
3013 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3014 assert(rscratch != noreg || always_reachable(src), "missing");
3015
3016 if (reachable(src)) {
3017 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3018 } else {
3019 lea(rscratch, src);
3020 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3021 }
3022 }
3023
3024 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3025 assert(rscratch != noreg || always_reachable(src), "missing");
3026
3027 if (reachable(src)) {
3028 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3029 } else {
3030 lea(rscratch, src);
3031 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3032 }
3033 }
3034
3035 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3036 assert(rscratch != noreg || always_reachable(src), "missing");
3037
3038 if (reachable(src)) {
3039 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3040 } else {
3041 lea(rscratch, src);
3042 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3043 }
3044 }
3045
3046 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3047 assert(rscratch != noreg || always_reachable(src), "missing");
3048
3049 if (reachable(src)) {
3050 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3051 } else {
3052 lea(rscratch, src);
3053 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3054 }
3055 }
3056
3057 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3058 assert(rscratch != noreg || always_reachable(src), "missing");
3059
3060 if (reachable(src)) {
3061 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3062 } else {
3063 lea(rscratch, src);
3064 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3065 }
3066 }
3067
3068 // Vector float blend
3069 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3070 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3071 // WARN: Allow dst == (src1|src2), mask == scratch
3072 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3073 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3074 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3075 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3076 if (blend_emulation && scratch_available && dst_available) {
3077 if (compute_mask) {
3078 vpsrad(scratch, mask, 32, vector_len);
3079 mask = scratch;
3080 }
3081 if (dst == src1) {
3082 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3083 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3084 } else {
3085 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3086 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3087 }
3088 vpor(dst, dst, scratch, vector_len);
3089 } else {
3090 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3091 }
3092 }
3093
3094 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3095 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3096 // WARN: Allow dst == (src1|src2), mask == scratch
3097 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3098 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3099 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3100 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3101 if (blend_emulation && scratch_available && dst_available) {
3102 if (compute_mask) {
3103 vpxor(scratch, scratch, scratch, vector_len);
3104 vpcmpgtq(scratch, scratch, mask, vector_len);
3105 mask = scratch;
3106 }
3107 if (dst == src1) {
3108 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3109 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3110 } else {
3111 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3112 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3113 }
3114 vpor(dst, dst, scratch, vector_len);
3115 } else {
3116 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3117 }
3118 }
3119
3120 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3121 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3122 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3123 }
3124
3125 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3126 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3127 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3128 }
3129
3130 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3131 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3132 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3133 }
3134
3135 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3136 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3137 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3138 }
3139
3140 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3141 assert(rscratch != noreg || always_reachable(src), "missing");
3142
3143 if (reachable(src)) {
3144 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3145 } else {
3146 lea(rscratch, src);
3147 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3148 }
3149 }
3150
3151 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3152 int comparison, bool is_signed, int vector_len, Register rscratch) {
3153 assert(rscratch != noreg || always_reachable(src), "missing");
3154
3155 if (reachable(src)) {
3156 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3157 } else {
3158 lea(rscratch, src);
3159 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3160 }
3161 }
3162
3163 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3164 int comparison, bool is_signed, int vector_len, Register rscratch) {
3165 assert(rscratch != noreg || always_reachable(src), "missing");
3166
3167 if (reachable(src)) {
3168 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3169 } else {
3170 lea(rscratch, src);
3171 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3172 }
3173 }
3174
3175 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3176 int comparison, bool is_signed, int vector_len, Register rscratch) {
3177 assert(rscratch != noreg || always_reachable(src), "missing");
3178
3179 if (reachable(src)) {
3180 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3181 } else {
3182 lea(rscratch, src);
3183 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3184 }
3185 }
3186
3187 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3188 int comparison, bool is_signed, int vector_len, Register rscratch) {
3189 assert(rscratch != noreg || always_reachable(src), "missing");
3190
3191 if (reachable(src)) {
3192 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3193 } else {
3194 lea(rscratch, src);
3195 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3196 }
3197 }
3198
3199 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3200 if (width == Assembler::Q) {
3201 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3202 } else {
3203 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3204 }
3205 }
3206
3207 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3208 int eq_cond_enc = 0x29;
3209 int gt_cond_enc = 0x37;
3210 if (width != Assembler::Q) {
3211 eq_cond_enc = 0x74 + width;
3212 gt_cond_enc = 0x64 + width;
3213 }
3214 switch (cond) {
3215 case eq:
3216 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3217 break;
3218 case neq:
3219 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3220 vallones(xtmp, vector_len);
3221 vpxor(dst, xtmp, dst, vector_len);
3222 break;
3223 case le:
3224 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3225 vallones(xtmp, vector_len);
3226 vpxor(dst, xtmp, dst, vector_len);
3227 break;
3228 case nlt:
3229 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3230 vallones(xtmp, vector_len);
3231 vpxor(dst, xtmp, dst, vector_len);
3232 break;
3233 case lt:
3234 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3235 break;
3236 case nle:
3237 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3238 break;
3239 default:
3240 assert(false, "Should not reach here");
3241 }
3242 }
3243
3244 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3245 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3246 Assembler::vpmovzxbw(dst, src, vector_len);
3247 }
3248
3249 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3250 assert((src->encoding() < 16),"XMM register should be 0-15");
3251 Assembler::vpmovmskb(dst, src, vector_len);
3252 }
3253
3254 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3255 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3256 Assembler::vpmullw(dst, nds, src, vector_len);
3257 }
3258
3259 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3260 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3261 Assembler::vpmullw(dst, nds, src, vector_len);
3262 }
3263
3264 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3265 assert((UseAVX > 0), "AVX support is needed");
3266 assert(rscratch != noreg || always_reachable(src), "missing");
3267
3268 if (reachable(src)) {
3269 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3270 } else {
3271 lea(rscratch, src);
3272 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3273 }
3274 }
3275
3276 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3277 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3278 Assembler::vpsubb(dst, nds, src, vector_len);
3279 }
3280
3281 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3282 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3283 Assembler::vpsubb(dst, nds, src, vector_len);
3284 }
3285
3286 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3287 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3288 Assembler::vpsubw(dst, nds, src, vector_len);
3289 }
3290
3291 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3292 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3293 Assembler::vpsubw(dst, nds, src, vector_len);
3294 }
3295
3296 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3297 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3298 Assembler::vpsraw(dst, nds, shift, vector_len);
3299 }
3300
3301 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3302 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3303 Assembler::vpsraw(dst, nds, shift, vector_len);
3304 }
3305
3306 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3307 assert(UseAVX > 2,"");
3308 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3309 vector_len = 2;
3310 }
3311 Assembler::evpsraq(dst, nds, shift, vector_len);
3312 }
3313
3314 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3315 assert(UseAVX > 2,"");
3316 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3317 vector_len = 2;
3318 }
3319 Assembler::evpsraq(dst, nds, shift, vector_len);
3320 }
3321
3322 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3323 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3324 Assembler::vpsrlw(dst, nds, shift, vector_len);
3325 }
3326
3327 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3328 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3329 Assembler::vpsrlw(dst, nds, shift, vector_len);
3330 }
3331
3332 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3333 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3334 Assembler::vpsllw(dst, nds, shift, vector_len);
3335 }
3336
3337 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3338 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3339 Assembler::vpsllw(dst, nds, shift, vector_len);
3340 }
3341
3342 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3343 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3344 Assembler::vptest(dst, src);
3345 }
3346
3347 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3348 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3349 Assembler::punpcklbw(dst, src);
3350 }
3351
3352 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3353 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3354 Assembler::pshufd(dst, src, mode);
3355 }
3356
3357 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3358 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3359 Assembler::pshuflw(dst, src, mode);
3360 }
3361
3362 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3363 assert(rscratch != noreg || always_reachable(src), "missing");
3364
3365 if (reachable(src)) {
3366 vandpd(dst, nds, as_Address(src), vector_len);
3367 } else {
3368 lea(rscratch, src);
3369 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3370 }
3371 }
3372
3373 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3374 assert(rscratch != noreg || always_reachable(src), "missing");
3375
3376 if (reachable(src)) {
3377 vandps(dst, nds, as_Address(src), vector_len);
3378 } else {
3379 lea(rscratch, src);
3380 vandps(dst, nds, Address(rscratch, 0), vector_len);
3381 }
3382 }
3383
3384 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3385 bool merge, int vector_len, Register rscratch) {
3386 assert(rscratch != noreg || always_reachable(src), "missing");
3387
3388 if (reachable(src)) {
3389 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3390 } else {
3391 lea(rscratch, src);
3392 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3393 }
3394 }
3395
3396 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3397 assert(rscratch != noreg || always_reachable(src), "missing");
3398
3399 if (reachable(src)) {
3400 vdivsd(dst, nds, as_Address(src));
3401 } else {
3402 lea(rscratch, src);
3403 vdivsd(dst, nds, Address(rscratch, 0));
3404 }
3405 }
3406
3407 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3408 assert(rscratch != noreg || always_reachable(src), "missing");
3409
3410 if (reachable(src)) {
3411 vdivss(dst, nds, as_Address(src));
3412 } else {
3413 lea(rscratch, src);
3414 vdivss(dst, nds, Address(rscratch, 0));
3415 }
3416 }
3417
3418 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3419 assert(rscratch != noreg || always_reachable(src), "missing");
3420
3421 if (reachable(src)) {
3422 vmulsd(dst, nds, as_Address(src));
3423 } else {
3424 lea(rscratch, src);
3425 vmulsd(dst, nds, Address(rscratch, 0));
3426 }
3427 }
3428
3429 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3430 assert(rscratch != noreg || always_reachable(src), "missing");
3431
3432 if (reachable(src)) {
3433 vmulss(dst, nds, as_Address(src));
3434 } else {
3435 lea(rscratch, src);
3436 vmulss(dst, nds, Address(rscratch, 0));
3437 }
3438 }
3439
3440 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3441 assert(rscratch != noreg || always_reachable(src), "missing");
3442
3443 if (reachable(src)) {
3444 vsubsd(dst, nds, as_Address(src));
3445 } else {
3446 lea(rscratch, src);
3447 vsubsd(dst, nds, Address(rscratch, 0));
3448 }
3449 }
3450
3451 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3452 assert(rscratch != noreg || always_reachable(src), "missing");
3453
3454 if (reachable(src)) {
3455 vsubss(dst, nds, as_Address(src));
3456 } else {
3457 lea(rscratch, src);
3458 vsubss(dst, nds, Address(rscratch, 0));
3459 }
3460 }
3461
3462 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3463 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3464 assert(rscratch != noreg || always_reachable(src), "missing");
3465
3466 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3467 }
3468
3469 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3470 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3471 assert(rscratch != noreg || always_reachable(src), "missing");
3472
3473 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3474 }
3475
3476 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3477 assert(rscratch != noreg || always_reachable(src), "missing");
3478
3479 if (reachable(src)) {
3480 vxorpd(dst, nds, as_Address(src), vector_len);
3481 } else {
3482 lea(rscratch, src);
3483 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3484 }
3485 }
3486
3487 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3488 assert(rscratch != noreg || always_reachable(src), "missing");
3489
3490 if (reachable(src)) {
3491 vxorps(dst, nds, as_Address(src), vector_len);
3492 } else {
3493 lea(rscratch, src);
3494 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3495 }
3496 }
3497
3498 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3499 assert(rscratch != noreg || always_reachable(src), "missing");
3500
3501 if (UseAVX > 1 || (vector_len < 1)) {
3502 if (reachable(src)) {
3503 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3504 } else {
3505 lea(rscratch, src);
3506 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3507 }
3508 } else {
3509 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3510 }
3511 }
3512
3513 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3514 assert(rscratch != noreg || always_reachable(src), "missing");
3515
3516 if (reachable(src)) {
3517 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3518 } else {
3519 lea(rscratch, src);
3520 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3521 }
3522 }
3523
3524 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3525 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3526 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3527 // The inverted mask is sign-extended
3528 andptr(possibly_non_local, inverted_mask);
3529 }
3530
3531 void MacroAssembler::resolve_jobject(Register value,
3532 Register tmp) {
3533 Register thread = r15_thread;
3534 assert_different_registers(value, thread, tmp);
3535 Label done, tagged, weak_tagged;
3536 testptr(value, value);
3537 jcc(Assembler::zero, done); // Use null as-is.
3538 testptr(value, JNIHandles::tag_mask); // Test for tag.
3539 jcc(Assembler::notZero, tagged);
3540
3541 // Resolve local handle
3542 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp);
3543 verify_oop(value);
3544 jmp(done);
3545
3546 bind(tagged);
3547 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3548 jcc(Assembler::notZero, weak_tagged);
3549
3550 // Resolve global handle
3551 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3552 verify_oop(value);
3553 jmp(done);
3554
3555 bind(weak_tagged);
3556 // Resolve jweak.
3557 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3558 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp);
3559 verify_oop(value);
3560
3561 bind(done);
3562 }
3563
3564 void MacroAssembler::resolve_global_jobject(Register value,
3565 Register tmp) {
3566 Register thread = r15_thread;
3567 assert_different_registers(value, thread, tmp);
3568 Label done;
3569
3570 testptr(value, value);
3571 jcc(Assembler::zero, done); // Use null as-is.
3572
3573 #ifdef ASSERT
3574 {
3575 Label valid_global_tag;
3576 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
3577 jcc(Assembler::notZero, valid_global_tag);
3578 stop("non global jobject using resolve_global_jobject");
3579 bind(valid_global_tag);
3580 }
3581 #endif
3582
3583 // Resolve global handle
3584 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3585 verify_oop(value);
3586
3587 bind(done);
3588 }
3589
3590 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3591 subq(dst, imm32);
3592 }
3593
3594 // Force generation of a 4 byte immediate value even if it fits into 8bit
3595 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3596 subq_imm32(dst, imm32);
3597 }
3598
3599 void MacroAssembler::subptr(Register dst, Register src) {
3600 subq(dst, src);
3601 }
3602
3603 // C++ bool manipulation
3604 void MacroAssembler::testbool(Register dst) {
3605 if(sizeof(bool) == 1)
3606 testb(dst, 0xff);
3607 else if(sizeof(bool) == 2) {
3608 // testw implementation needed for two byte bools
3609 ShouldNotReachHere();
3610 } else if(sizeof(bool) == 4)
3611 testl(dst, dst);
3612 else
3613 // unsupported
3614 ShouldNotReachHere();
3615 }
3616
3617 void MacroAssembler::testptr(Register dst, Register src) {
3618 testq(dst, src);
3619 }
3620
3621 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3622 void MacroAssembler::tlab_allocate(Register obj,
3623 Register var_size_in_bytes,
3624 int con_size_in_bytes,
3625 Register t1,
3626 Register t2,
3627 Label& slow_case) {
3628 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3629 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3630 }
3631
3632 RegSet MacroAssembler::call_clobbered_gp_registers() {
3633 RegSet regs;
3634 regs += RegSet::of(rax, rcx, rdx);
3635 #ifndef _WINDOWS
3636 regs += RegSet::of(rsi, rdi);
3637 #endif
3638 regs += RegSet::range(r8, r11);
3639 if (UseAPX) {
3640 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
3641 }
3642 return regs;
3643 }
3644
3645 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3646 int num_xmm_registers = XMMRegister::available_xmm_registers();
3647 #if defined(_WINDOWS)
3648 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3649 if (num_xmm_registers > 16) {
3650 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3651 }
3652 return result;
3653 #else
3654 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3655 #endif
3656 }
3657
3658 // C1 only ever uses the first double/float of the XMM register.
3659 static int xmm_save_size() { return sizeof(double); }
3660
3661 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3662 masm->movdbl(Address(rsp, offset), reg);
3663 }
3664
3665 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3666 masm->movdbl(reg, Address(rsp, offset));
3667 }
3668
3669 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
3670 bool save_fpu, int& gp_area_size, int& xmm_area_size) {
3671
3672 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
3673 StackAlignmentInBytes);
3674 xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
3675
3676 return gp_area_size + xmm_area_size;
3677 }
3678
3679 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3680 block_comment("push_call_clobbered_registers start");
3681 // Regular registers
3682 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3683
3684 int gp_area_size;
3685 int xmm_area_size;
3686 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3687 gp_area_size, xmm_area_size);
3688 subptr(rsp, total_save_size);
3689
3690 push_set(gp_registers_to_push, 0);
3691
3692 if (save_fpu) {
3693 push_set(call_clobbered_xmm_registers(), gp_area_size);
3694 }
3695
3696 block_comment("push_call_clobbered_registers end");
3697 }
3698
3699 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3700 block_comment("pop_call_clobbered_registers start");
3701
3702 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3703
3704 int gp_area_size;
3705 int xmm_area_size;
3706 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3707 gp_area_size, xmm_area_size);
3708
3709 if (restore_fpu) {
3710 pop_set(call_clobbered_xmm_registers(), gp_area_size);
3711 }
3712
3713 pop_set(gp_registers_to_pop, 0);
3714
3715 addptr(rsp, total_save_size);
3716
3717 vzeroupper();
3718
3719 block_comment("pop_call_clobbered_registers end");
3720 }
3721
3722 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3723 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3724 int spill_offset = offset;
3725
3726 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3727 save_xmm_register(this, spill_offset, *it);
3728 spill_offset += xmm_save_size();
3729 }
3730 }
3731
3732 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3733 int restore_size = set.size() * xmm_save_size();
3734 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3735
3736 int restore_offset = offset + restore_size - xmm_save_size();
3737
3738 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3739 restore_xmm_register(this, restore_offset, *it);
3740 restore_offset -= xmm_save_size();
3741 }
3742 }
3743
3744 void MacroAssembler::push_set(RegSet set, int offset) {
3745 int spill_offset;
3746 if (offset == -1) {
3747 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3748 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3749 subptr(rsp, aligned_size);
3750 spill_offset = 0;
3751 } else {
3752 spill_offset = offset;
3753 }
3754
3755 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3756 movptr(Address(rsp, spill_offset), *it);
3757 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3758 }
3759 }
3760
3761 void MacroAssembler::pop_set(RegSet set, int offset) {
3762
3763 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3764 int restore_size = set.size() * gp_reg_size;
3765 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3766
3767 int restore_offset;
3768 if (offset == -1) {
3769 restore_offset = restore_size - gp_reg_size;
3770 } else {
3771 restore_offset = offset + restore_size - gp_reg_size;
3772 }
3773 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3774 movptr(*it, Address(rsp, restore_offset));
3775 restore_offset -= gp_reg_size;
3776 }
3777
3778 if (offset == -1) {
3779 addptr(rsp, aligned_size);
3780 }
3781 }
3782
3783 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3784 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3785 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3786 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3787 Label done;
3788
3789 testptr(length_in_bytes, length_in_bytes);
3790 jcc(Assembler::zero, done);
3791
3792 // initialize topmost word, divide index by 2, check if odd and test if zero
3793 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3794 #ifdef ASSERT
3795 {
3796 Label L;
3797 testptr(length_in_bytes, BytesPerWord - 1);
3798 jcc(Assembler::zero, L);
3799 stop("length must be a multiple of BytesPerWord");
3800 bind(L);
3801 }
3802 #endif
3803 Register index = length_in_bytes;
3804 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3805 if (UseIncDec) {
3806 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3807 } else {
3808 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3809 shrptr(index, 1);
3810 }
3811
3812 // initialize remaining object fields: index is a multiple of 2 now
3813 {
3814 Label loop;
3815 bind(loop);
3816 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3817 decrement(index);
3818 jcc(Assembler::notZero, loop);
3819 }
3820
3821 bind(done);
3822 }
3823
3824 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
3825 movptr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
3826 #ifdef ASSERT
3827 {
3828 Label done;
3829 cmpptr(layout_info, 0);
3830 jcc(Assembler::notEqual, done);
3831 stop("inline_layout_info_array is null");
3832 bind(done);
3833 }
3834 #endif
3835
3836 InlineLayoutInfo array[2];
3837 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
3838 if (is_power_of_2(size)) {
3839 shll(index, log2i_exact(size)); // Scale index by power of 2
3840 } else {
3841 imull(index, index, size); // Scale the index to be the entry index * array_element_size
3842 }
3843 lea(layout_info, Address(layout_info, index, Address::times_1, Array<InlineLayoutInfo>::base_offset_in_bytes()));
3844 }
3845
3846 // Look up the method for a megamorphic invokeinterface call.
3847 // The target method is determined by <intf_klass, itable_index>.
3848 // The receiver klass is in recv_klass.
3849 // On success, the result will be in method_result, and execution falls through.
3850 // On failure, execution transfers to the given label.
3851 void MacroAssembler::lookup_interface_method(Register recv_klass,
3852 Register intf_klass,
3853 RegisterOrConstant itable_index,
3854 Register method_result,
3855 Register scan_temp,
3856 Label& L_no_such_interface,
3857 bool return_method) {
3858 assert_different_registers(recv_klass, intf_klass, scan_temp);
3859 assert_different_registers(method_result, intf_klass, scan_temp);
3860 assert(recv_klass != method_result || !return_method,
3861 "recv_klass can be destroyed when method isn't needed");
3862
3863 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3864 "caller must use same register for non-constant itable index as for method");
3865
3866 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3867 int vtable_base = in_bytes(Klass::vtable_start_offset());
3868 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3869 int scan_step = itableOffsetEntry::size() * wordSize;
3870 int vte_size = vtableEntry::size_in_bytes();
3871 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3872 assert(vte_size == wordSize, "else adjust times_vte_scale");
3873
3874 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3875
3876 // Could store the aligned, prescaled offset in the klass.
3877 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3878
3879 if (return_method) {
3880 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3881 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3882 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3883 }
3884
3885 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
3886 // if (scan->interface() == intf) {
3887 // result = (klass + scan->offset() + itable_index);
3888 // }
3889 // }
3890 Label search, found_method;
3891
3892 for (int peel = 1; peel >= 0; peel--) {
3893 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
3894 cmpptr(intf_klass, method_result);
3895
3896 if (peel) {
3897 jccb(Assembler::equal, found_method);
3898 } else {
3899 jccb(Assembler::notEqual, search);
3900 // (invert the test to fall through to found_method...)
3901 }
3902
3903 if (!peel) break;
3904
3905 bind(search);
3906
3907 // Check that the previous entry is non-null. A null entry means that
3908 // the receiver class doesn't implement the interface, and wasn't the
3909 // same as when the caller was compiled.
3910 testptr(method_result, method_result);
3911 jcc(Assembler::zero, L_no_such_interface);
3912 addptr(scan_temp, scan_step);
3913 }
3914
3915 bind(found_method);
3916
3917 if (return_method) {
3918 // Got a hit.
3919 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
3920 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3921 }
3922 }
3923
3924 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
3925 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
3926 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
3927 // The target method is determined by <holder_klass, itable_index>.
3928 // The receiver klass is in recv_klass.
3929 // On success, the result will be in method_result, and execution falls through.
3930 // On failure, execution transfers to the given label.
3931 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
3932 Register holder_klass,
3933 Register resolved_klass,
3934 Register method_result,
3935 Register scan_temp,
3936 Register temp_reg2,
3937 Register receiver,
3938 int itable_index,
3939 Label& L_no_such_interface) {
3940 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
3941 Register temp_itbl_klass = method_result;
3942 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
3943
3944 int vtable_base = in_bytes(Klass::vtable_start_offset());
3945 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3946 int scan_step = itableOffsetEntry::size() * wordSize;
3947 int vte_size = vtableEntry::size_in_bytes();
3948 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
3949 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
3950 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3951 assert(vte_size == wordSize, "adjust times_vte_scale");
3952
3953 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
3954
3955 // temp_itbl_klass = recv_klass.itable[0]
3956 // scan_temp = &recv_klass.itable[0] + step
3957 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3958 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
3959 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
3960 xorptr(temp_reg, temp_reg);
3961
3962 // Initial checks:
3963 // - if (holder_klass != resolved_klass), go to "scan for resolved"
3964 // - if (itable[0] == 0), no such interface
3965 // - if (itable[0] == holder_klass), shortcut to "holder found"
3966 cmpptr(holder_klass, resolved_klass);
3967 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
3968 testptr(temp_itbl_klass, temp_itbl_klass);
3969 jccb(Assembler::zero, L_no_such_interface);
3970 cmpptr(holder_klass, temp_itbl_klass);
3971 jccb(Assembler::equal, L_holder_found);
3972
3973 // Loop: Look for holder_klass record in itable
3974 // do {
3975 // tmp = itable[index];
3976 // index += step;
3977 // if (tmp == holder_klass) {
3978 // goto L_holder_found; // Found!
3979 // }
3980 // } while (tmp != 0);
3981 // goto L_no_such_interface // Not found.
3982 Label L_scan_holder;
3983 bind(L_scan_holder);
3984 movptr(temp_itbl_klass, Address(scan_temp, 0));
3985 addptr(scan_temp, scan_step);
3986 cmpptr(holder_klass, temp_itbl_klass);
3987 jccb(Assembler::equal, L_holder_found);
3988 testptr(temp_itbl_klass, temp_itbl_klass);
3989 jccb(Assembler::notZero, L_scan_holder);
3990
3991 jmpb(L_no_such_interface);
3992
3993 // Loop: Look for resolved_class record in itable
3994 // do {
3995 // tmp = itable[index];
3996 // index += step;
3997 // if (tmp == holder_klass) {
3998 // // Also check if we have met a holder klass
3999 // holder_tmp = itable[index-step-ioffset];
4000 // }
4001 // if (tmp == resolved_klass) {
4002 // goto L_resolved_found; // Found!
4003 // }
4004 // } while (tmp != 0);
4005 // goto L_no_such_interface // Not found.
4006 //
4007 Label L_loop_scan_resolved;
4008 bind(L_loop_scan_resolved);
4009 movptr(temp_itbl_klass, Address(scan_temp, 0));
4010 addptr(scan_temp, scan_step);
4011 bind(L_loop_scan_resolved_entry);
4012 cmpptr(holder_klass, temp_itbl_klass);
4013 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4014 cmpptr(resolved_klass, temp_itbl_klass);
4015 jccb(Assembler::equal, L_resolved_found);
4016 testptr(temp_itbl_klass, temp_itbl_klass);
4017 jccb(Assembler::notZero, L_loop_scan_resolved);
4018
4019 jmpb(L_no_such_interface);
4020
4021 Label L_ready;
4022
4023 // See if we already have a holder klass. If not, go and scan for it.
4024 bind(L_resolved_found);
4025 testptr(temp_reg, temp_reg);
4026 jccb(Assembler::zero, L_scan_holder);
4027 jmpb(L_ready);
4028
4029 bind(L_holder_found);
4030 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4031
4032 // Finally, temp_reg contains holder_klass vtable offset
4033 bind(L_ready);
4034 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4035 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4036 load_klass(scan_temp, receiver, noreg);
4037 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4038 } else {
4039 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4040 }
4041 }
4042
4043
4044 // virtual method calling
4045 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4046 RegisterOrConstant vtable_index,
4047 Register method_result) {
4048 const ByteSize base = Klass::vtable_start_offset();
4049 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4050 Address vtable_entry_addr(recv_klass,
4051 vtable_index, Address::times_ptr,
4052 base + vtableEntry::method_offset());
4053 movptr(method_result, vtable_entry_addr);
4054 }
4055
4056
4057 void MacroAssembler::check_klass_subtype(Register sub_klass,
4058 Register super_klass,
4059 Register temp_reg,
4060 Label& L_success) {
4061 Label L_failure;
4062 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4063 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4064 bind(L_failure);
4065 }
4066
4067
4068 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4069 Register super_klass,
4070 Register temp_reg,
4071 Label* L_success,
4072 Label* L_failure,
4073 Label* L_slow_path,
4074 RegisterOrConstant super_check_offset) {
4075 assert_different_registers(sub_klass, super_klass, temp_reg);
4076 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4077 if (super_check_offset.is_register()) {
4078 assert_different_registers(sub_klass, super_klass,
4079 super_check_offset.as_register());
4080 } else if (must_load_sco) {
4081 assert(temp_reg != noreg, "supply either a temp or a register offset");
4082 }
4083
4084 Label L_fallthrough;
4085 int label_nulls = 0;
4086 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4087 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4088 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4089 assert(label_nulls <= 1, "at most one null in the batch");
4090
4091 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4092 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4093 Address super_check_offset_addr(super_klass, sco_offset);
4094
4095 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4096 // range of a jccb. If this routine grows larger, reconsider at
4097 // least some of these.
4098 #define local_jcc(assembler_cond, label) \
4099 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4100 else jcc( assembler_cond, label) /*omit semi*/
4101
4102 // Hacked jmp, which may only be used just before L_fallthrough.
4103 #define final_jmp(label) \
4104 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4105 else jmp(label) /*omit semi*/
4106
4107 // If the pointers are equal, we are done (e.g., String[] elements).
4108 // This self-check enables sharing of secondary supertype arrays among
4109 // non-primary types such as array-of-interface. Otherwise, each such
4110 // type would need its own customized SSA.
4111 // We move this check to the front of the fast path because many
4112 // type checks are in fact trivially successful in this manner,
4113 // so we get a nicely predicted branch right at the start of the check.
4114 cmpptr(sub_klass, super_klass);
4115 local_jcc(Assembler::equal, *L_success);
4116
4117 // Check the supertype display:
4118 if (must_load_sco) {
4119 // Positive movl does right thing on LP64.
4120 movl(temp_reg, super_check_offset_addr);
4121 super_check_offset = RegisterOrConstant(temp_reg);
4122 }
4123 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4124 cmpptr(super_klass, super_check_addr); // load displayed supertype
4125
4126 // This check has worked decisively for primary supers.
4127 // Secondary supers are sought in the super_cache ('super_cache_addr').
4128 // (Secondary supers are interfaces and very deeply nested subtypes.)
4129 // This works in the same check above because of a tricky aliasing
4130 // between the super_cache and the primary super display elements.
4131 // (The 'super_check_addr' can address either, as the case requires.)
4132 // Note that the cache is updated below if it does not help us find
4133 // what we need immediately.
4134 // So if it was a primary super, we can just fail immediately.
4135 // Otherwise, it's the slow path for us (no success at this point).
4136
4137 if (super_check_offset.is_register()) {
4138 local_jcc(Assembler::equal, *L_success);
4139 cmpl(super_check_offset.as_register(), sc_offset);
4140 if (L_failure == &L_fallthrough) {
4141 local_jcc(Assembler::equal, *L_slow_path);
4142 } else {
4143 local_jcc(Assembler::notEqual, *L_failure);
4144 final_jmp(*L_slow_path);
4145 }
4146 } else if (super_check_offset.as_constant() == sc_offset) {
4147 // Need a slow path; fast failure is impossible.
4148 if (L_slow_path == &L_fallthrough) {
4149 local_jcc(Assembler::equal, *L_success);
4150 } else {
4151 local_jcc(Assembler::notEqual, *L_slow_path);
4152 final_jmp(*L_success);
4153 }
4154 } else {
4155 // No slow path; it's a fast decision.
4156 if (L_failure == &L_fallthrough) {
4157 local_jcc(Assembler::equal, *L_success);
4158 } else {
4159 local_jcc(Assembler::notEqual, *L_failure);
4160 final_jmp(*L_success);
4161 }
4162 }
4163
4164 bind(L_fallthrough);
4165
4166 #undef local_jcc
4167 #undef final_jmp
4168 }
4169
4170
4171 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4172 Register super_klass,
4173 Register temp_reg,
4174 Register temp2_reg,
4175 Label* L_success,
4176 Label* L_failure,
4177 bool set_cond_codes) {
4178 assert_different_registers(sub_klass, super_klass, temp_reg);
4179 if (temp2_reg != noreg)
4180 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4181 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4182
4183 Label L_fallthrough;
4184 int label_nulls = 0;
4185 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4186 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4187 assert(label_nulls <= 1, "at most one null in the batch");
4188
4189 // a couple of useful fields in sub_klass:
4190 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4191 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4192 Address secondary_supers_addr(sub_klass, ss_offset);
4193 Address super_cache_addr( sub_klass, sc_offset);
4194
4195 // Do a linear scan of the secondary super-klass chain.
4196 // This code is rarely used, so simplicity is a virtue here.
4197 // The repne_scan instruction uses fixed registers, which we must spill.
4198 // Don't worry too much about pre-existing connections with the input regs.
4199
4200 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4201 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4202
4203 // Get super_klass value into rax (even if it was in rdi or rcx).
4204 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4205 if (super_klass != rax) {
4206 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4207 mov(rax, super_klass);
4208 }
4209 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4210 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4211
4212 #ifndef PRODUCT
4213 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4214 ExternalAddress pst_counter_addr((address) pst_counter);
4215 lea(rcx, pst_counter_addr);
4216 incrementl(Address(rcx, 0));
4217 #endif //PRODUCT
4218
4219 // We will consult the secondary-super array.
4220 movptr(rdi, secondary_supers_addr);
4221 // Load the array length. (Positive movl does right thing on LP64.)
4222 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4223 // Skip to start of data.
4224 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4225
4226 // Scan RCX words at [RDI] for an occurrence of RAX.
4227 // Set NZ/Z based on last compare.
4228 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4229 // not change flags (only scas instruction which is repeated sets flags).
4230 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4231
4232 testptr(rax,rax); // Set Z = 0
4233 repne_scan();
4234
4235 // Unspill the temp. registers:
4236 if (pushed_rdi) pop(rdi);
4237 if (pushed_rcx) pop(rcx);
4238 if (pushed_rax) pop(rax);
4239
4240 if (set_cond_codes) {
4241 // Special hack for the AD files: rdi is guaranteed non-zero.
4242 assert(!pushed_rdi, "rdi must be left non-null");
4243 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4244 }
4245
4246 if (L_failure == &L_fallthrough)
4247 jccb(Assembler::notEqual, *L_failure);
4248 else jcc(Assembler::notEqual, *L_failure);
4249
4250 // Success. Cache the super we found and proceed in triumph.
4251 movptr(super_cache_addr, super_klass);
4252
4253 if (L_success != &L_fallthrough) {
4254 jmp(*L_success);
4255 }
4256
4257 #undef IS_A_TEMP
4258
4259 bind(L_fallthrough);
4260 }
4261
4262 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4263 Register super_klass,
4264 Register temp_reg,
4265 Register temp2_reg,
4266 Label* L_success,
4267 Label* L_failure,
4268 bool set_cond_codes) {
4269 assert(set_cond_codes == false, "must be false on 64-bit x86");
4270 check_klass_subtype_slow_path
4271 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4272 L_success, L_failure);
4273 }
4274
4275 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4276 Register super_klass,
4277 Register temp_reg,
4278 Register temp2_reg,
4279 Register temp3_reg,
4280 Register temp4_reg,
4281 Label* L_success,
4282 Label* L_failure) {
4283 if (UseSecondarySupersTable) {
4284 check_klass_subtype_slow_path_table
4285 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4286 L_success, L_failure);
4287 } else {
4288 check_klass_subtype_slow_path_linear
4289 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4290 }
4291 }
4292
4293 Register MacroAssembler::allocate_if_noreg(Register r,
4294 RegSetIterator<Register> &available_regs,
4295 RegSet ®s_to_push) {
4296 if (!r->is_valid()) {
4297 r = *available_regs++;
4298 regs_to_push += r;
4299 }
4300 return r;
4301 }
4302
4303 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4304 Register super_klass,
4305 Register temp_reg,
4306 Register temp2_reg,
4307 Register temp3_reg,
4308 Register result_reg,
4309 Label* L_success,
4310 Label* L_failure) {
4311 // NB! Callers may assume that, when temp2_reg is a valid register,
4312 // this code sets it to a nonzero value.
4313 bool temp2_reg_was_valid = temp2_reg->is_valid();
4314
4315 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4316
4317 Label L_fallthrough;
4318 int label_nulls = 0;
4319 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4320 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4321 assert(label_nulls <= 1, "at most one null in the batch");
4322
4323 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4324
4325 RegSetIterator<Register> available_regs
4326 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4327
4328 RegSet pushed_regs;
4329
4330 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4331 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4332 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4333 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4334 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4335
4336 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4337
4338 {
4339
4340 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4341 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4342 subptr(rsp, aligned_size);
4343 push_set(pushed_regs, 0);
4344
4345 lookup_secondary_supers_table_var(sub_klass,
4346 super_klass,
4347 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4348 cmpq(result_reg, 0);
4349
4350 // Unspill the temp. registers:
4351 pop_set(pushed_regs, 0);
4352 // Increment SP but do not clobber flags.
4353 lea(rsp, Address(rsp, aligned_size));
4354 }
4355
4356 if (temp2_reg_was_valid) {
4357 movq(temp2_reg, 1);
4358 }
4359
4360 jcc(Assembler::notEqual, *L_failure);
4361
4362 if (L_success != &L_fallthrough) {
4363 jmp(*L_success);
4364 }
4365
4366 bind(L_fallthrough);
4367 }
4368
4369 // population_count variant for running without the POPCNT
4370 // instruction, which was introduced with SSE4.2 in 2008.
4371 void MacroAssembler::population_count(Register dst, Register src,
4372 Register scratch1, Register scratch2) {
4373 assert_different_registers(src, scratch1, scratch2);
4374 if (UsePopCountInstruction) {
4375 Assembler::popcntq(dst, src);
4376 } else {
4377 assert_different_registers(src, scratch1, scratch2);
4378 assert_different_registers(dst, scratch1, scratch2);
4379 Label loop, done;
4380
4381 mov(scratch1, src);
4382 // dst = 0;
4383 // while(scratch1 != 0) {
4384 // dst++;
4385 // scratch1 &= (scratch1 - 1);
4386 // }
4387 xorl(dst, dst);
4388 testq(scratch1, scratch1);
4389 jccb(Assembler::equal, done);
4390 {
4391 bind(loop);
4392 incq(dst);
4393 movq(scratch2, scratch1);
4394 decq(scratch2);
4395 andq(scratch1, scratch2);
4396 jccb(Assembler::notEqual, loop);
4397 }
4398 bind(done);
4399 }
4400 #ifdef ASSERT
4401 mov64(scratch1, 0xCafeBabeDeadBeef);
4402 movq(scratch2, scratch1);
4403 #endif
4404 }
4405
4406 // Ensure that the inline code and the stub are using the same registers.
4407 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4408 do { \
4409 assert(r_super_klass == rax, "mismatch"); \
4410 assert(r_array_base == rbx, "mismatch"); \
4411 assert(r_array_length == rcx, "mismatch"); \
4412 assert(r_array_index == rdx, "mismatch"); \
4413 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4414 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4415 assert(result == rdi || result == noreg, "mismatch"); \
4416 } while(0)
4417
4418 // Versions of salq and rorq that don't need count to be in rcx
4419
4420 void MacroAssembler::salq(Register dest, Register count) {
4421 if (count == rcx) {
4422 Assembler::salq(dest);
4423 } else {
4424 assert_different_registers(rcx, dest);
4425 xchgq(rcx, count);
4426 Assembler::salq(dest);
4427 xchgq(rcx, count);
4428 }
4429 }
4430
4431 void MacroAssembler::rorq(Register dest, Register count) {
4432 if (count == rcx) {
4433 Assembler::rorq(dest);
4434 } else {
4435 assert_different_registers(rcx, dest);
4436 xchgq(rcx, count);
4437 Assembler::rorq(dest);
4438 xchgq(rcx, count);
4439 }
4440 }
4441
4442 // Return true: we succeeded in generating this code
4443 //
4444 // At runtime, return 0 in result if r_super_klass is a superclass of
4445 // r_sub_klass, otherwise return nonzero. Use this if you know the
4446 // super_klass_slot of the class you're looking for. This is always
4447 // the case for instanceof and checkcast.
4448 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4449 Register r_super_klass,
4450 Register temp1,
4451 Register temp2,
4452 Register temp3,
4453 Register temp4,
4454 Register result,
4455 u1 super_klass_slot) {
4456 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4457
4458 Label L_fallthrough, L_success, L_failure;
4459
4460 BLOCK_COMMENT("lookup_secondary_supers_table {");
4461
4462 const Register
4463 r_array_index = temp1,
4464 r_array_length = temp2,
4465 r_array_base = temp3,
4466 r_bitmap = temp4;
4467
4468 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4469
4470 xorq(result, result); // = 0
4471
4472 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4473 movq(r_array_index, r_bitmap);
4474
4475 // First check the bitmap to see if super_klass might be present. If
4476 // the bit is zero, we are certain that super_klass is not one of
4477 // the secondary supers.
4478 u1 bit = super_klass_slot;
4479 {
4480 // NB: If the count in a x86 shift instruction is 0, the flags are
4481 // not affected, so we do a testq instead.
4482 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4483 if (shift_count != 0) {
4484 salq(r_array_index, shift_count);
4485 } else {
4486 testq(r_array_index, r_array_index);
4487 }
4488 }
4489 // We test the MSB of r_array_index, i.e. its sign bit
4490 jcc(Assembler::positive, L_failure);
4491
4492 // Get the first array index that can contain super_klass into r_array_index.
4493 if (bit != 0) {
4494 population_count(r_array_index, r_array_index, temp2, temp3);
4495 } else {
4496 movl(r_array_index, 1);
4497 }
4498 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4499
4500 // We will consult the secondary-super array.
4501 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4502
4503 // We're asserting that the first word in an Array<Klass*> is the
4504 // length, and the second word is the first word of the data. If
4505 // that ever changes, r_array_base will have to be adjusted here.
4506 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4507 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4508
4509 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4510 jccb(Assembler::equal, L_success);
4511
4512 // Is there another entry to check? Consult the bitmap.
4513 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4514 jccb(Assembler::carryClear, L_failure);
4515
4516 // Linear probe. Rotate the bitmap so that the next bit to test is
4517 // in Bit 1.
4518 if (bit != 0) {
4519 rorq(r_bitmap, bit);
4520 }
4521
4522 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4523 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4524 // Kills: r_array_length.
4525 // Returns: result.
4526 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4527 // Result (0/1) is in rdi
4528 jmpb(L_fallthrough);
4529
4530 bind(L_failure);
4531 incq(result); // 0 => 1
4532
4533 bind(L_success);
4534 // result = 0;
4535
4536 bind(L_fallthrough);
4537 BLOCK_COMMENT("} lookup_secondary_supers_table");
4538
4539 if (VerifySecondarySupers) {
4540 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4541 temp1, temp2, temp3);
4542 }
4543 }
4544
4545 // At runtime, return 0 in result if r_super_klass is a superclass of
4546 // r_sub_klass, otherwise return nonzero. Use this version of
4547 // lookup_secondary_supers_table() if you don't know ahead of time
4548 // which superclass will be searched for. Used by interpreter and
4549 // runtime stubs. It is larger and has somewhat greater latency than
4550 // the version above, which takes a constant super_klass_slot.
4551 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
4552 Register r_super_klass,
4553 Register temp1,
4554 Register temp2,
4555 Register temp3,
4556 Register temp4,
4557 Register result) {
4558 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4559 assert_different_registers(r_sub_klass, r_super_klass, rcx);
4560 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
4561
4562 Label L_fallthrough, L_success, L_failure;
4563
4564 BLOCK_COMMENT("lookup_secondary_supers_table {");
4565
4566 RegSetIterator<Register> available_regs = (temps - rcx).begin();
4567
4568 // FIXME. Once we are sure that all paths reaching this point really
4569 // do pass rcx as one of our temps we can get rid of the following
4570 // workaround.
4571 assert(temps.contains(rcx), "fix this code");
4572
4573 // We prefer to have our shift count in rcx. If rcx is one of our
4574 // temps, use it for slot. If not, pick any of our temps.
4575 Register slot;
4576 if (!temps.contains(rcx)) {
4577 slot = *available_regs++;
4578 } else {
4579 slot = rcx;
4580 }
4581
4582 const Register r_array_index = *available_regs++;
4583 const Register r_bitmap = *available_regs++;
4584
4585 // The logic above guarantees this property, but we state it here.
4586 assert_different_registers(r_array_index, r_bitmap, rcx);
4587
4588 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4589 movq(r_array_index, r_bitmap);
4590
4591 // First check the bitmap to see if super_klass might be present. If
4592 // the bit is zero, we are certain that super_klass is not one of
4593 // the secondary supers.
4594 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4595 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
4596 salq(r_array_index, slot);
4597
4598 testq(r_array_index, r_array_index);
4599 // We test the MSB of r_array_index, i.e. its sign bit
4600 jcc(Assembler::positive, L_failure);
4601
4602 const Register r_array_base = *available_regs++;
4603
4604 // Get the first array index that can contain super_klass into r_array_index.
4605 // Note: Clobbers r_array_base and slot.
4606 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
4607
4608 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4609
4610 // We will consult the secondary-super array.
4611 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4612
4613 // We're asserting that the first word in an Array<Klass*> is the
4614 // length, and the second word is the first word of the data. If
4615 // that ever changes, r_array_base will have to be adjusted here.
4616 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4617 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4618
4619 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4620 jccb(Assembler::equal, L_success);
4621
4622 // Restore slot to its true value
4623 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4624
4625 // Linear probe. Rotate the bitmap so that the next bit to test is
4626 // in Bit 1.
4627 rorq(r_bitmap, slot);
4628
4629 // Is there another entry to check? Consult the bitmap.
4630 btq(r_bitmap, 1);
4631 jccb(Assembler::carryClear, L_failure);
4632
4633 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4634 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4635 // Kills: r_array_length.
4636 // Returns: result.
4637 lookup_secondary_supers_table_slow_path(r_super_klass,
4638 r_array_base,
4639 r_array_index,
4640 r_bitmap,
4641 /*temp1*/result,
4642 /*temp2*/slot,
4643 &L_success,
4644 nullptr);
4645
4646 bind(L_failure);
4647 movq(result, 1);
4648 jmpb(L_fallthrough);
4649
4650 bind(L_success);
4651 xorq(result, result); // = 0
4652
4653 bind(L_fallthrough);
4654 BLOCK_COMMENT("} lookup_secondary_supers_table");
4655
4656 if (VerifySecondarySupers) {
4657 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4658 temp1, temp2, temp3);
4659 }
4660 }
4661
4662 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4663 Label* L_success, Label* L_failure) {
4664 Label L_loop, L_fallthrough;
4665 {
4666 int label_nulls = 0;
4667 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4668 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4669 assert(label_nulls <= 1, "at most one null in the batch");
4670 }
4671 bind(L_loop);
4672 cmpq(value, Address(addr, count, Address::times_8));
4673 jcc(Assembler::equal, *L_success);
4674 addl(count, 1);
4675 cmpl(count, limit);
4676 jcc(Assembler::less, L_loop);
4677
4678 if (&L_fallthrough != L_failure) {
4679 jmp(*L_failure);
4680 }
4681 bind(L_fallthrough);
4682 }
4683
4684 // Called by code generated by check_klass_subtype_slow_path
4685 // above. This is called when there is a collision in the hashed
4686 // lookup in the secondary supers array.
4687 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4688 Register r_array_base,
4689 Register r_array_index,
4690 Register r_bitmap,
4691 Register temp1,
4692 Register temp2,
4693 Label* L_success,
4694 Label* L_failure) {
4695 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4696
4697 const Register
4698 r_array_length = temp1,
4699 r_sub_klass = noreg,
4700 result = noreg;
4701
4702 Label L_fallthrough;
4703 int label_nulls = 0;
4704 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4705 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4706 assert(label_nulls <= 1, "at most one null in the batch");
4707
4708 // Load the array length.
4709 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4710 // And adjust the array base to point to the data.
4711 // NB! Effectively increments current slot index by 1.
4712 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4713 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4714
4715 // Linear probe
4716 Label L_huge;
4717
4718 // The bitmap is full to bursting.
4719 // Implicit invariant: BITMAP_FULL implies (length > 0)
4720 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
4721 jcc(Assembler::greater, L_huge);
4722
4723 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4724 // current slot (at secondary_supers[r_array_index]) has not yet
4725 // been inspected, and r_array_index may be out of bounds if we
4726 // wrapped around the end of the array.
4727
4728 { // This is conventional linear probing, but instead of terminating
4729 // when a null entry is found in the table, we maintain a bitmap
4730 // in which a 0 indicates missing entries.
4731 // The check above guarantees there are 0s in the bitmap, so the loop
4732 // eventually terminates.
4733
4734 xorl(temp2, temp2); // = 0;
4735
4736 Label L_again;
4737 bind(L_again);
4738
4739 // Check for array wraparound.
4740 cmpl(r_array_index, r_array_length);
4741 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4742
4743 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4744 jcc(Assembler::equal, *L_success);
4745
4746 // If the next bit in bitmap is zero, we're done.
4747 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4748 jcc(Assembler::carryClear, *L_failure);
4749
4750 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4751 addl(r_array_index, 1);
4752
4753 jmp(L_again);
4754 }
4755
4756 { // Degenerate case: more than 64 secondary supers.
4757 // FIXME: We could do something smarter here, maybe a vectorized
4758 // comparison or a binary search, but is that worth any added
4759 // complexity?
4760 bind(L_huge);
4761 xorl(r_array_index, r_array_index); // = 0
4762 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4763 L_success,
4764 (&L_fallthrough != L_failure ? L_failure : nullptr));
4765
4766 bind(L_fallthrough);
4767 }
4768 }
4769
4770 struct VerifyHelperArguments {
4771 Klass* _super;
4772 Klass* _sub;
4773 intptr_t _linear_result;
4774 intptr_t _table_result;
4775 };
4776
4777 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
4778 Klass::on_secondary_supers_verification_failure(args->_super,
4779 args->_sub,
4780 args->_linear_result,
4781 args->_table_result,
4782 msg);
4783 }
4784
4785 // Make sure that the hashed lookup and a linear scan agree.
4786 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
4787 Register r_super_klass,
4788 Register result,
4789 Register temp1,
4790 Register temp2,
4791 Register temp3) {
4792 const Register
4793 r_array_index = temp1,
4794 r_array_length = temp2,
4795 r_array_base = temp3,
4796 r_bitmap = noreg;
4797
4798 BLOCK_COMMENT("verify_secondary_supers_table {");
4799
4800 Label L_success, L_failure, L_check, L_done;
4801
4802 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4803 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4804 // And adjust the array base to point to the data.
4805 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4806
4807 testl(r_array_length, r_array_length); // array_length == 0?
4808 jcc(Assembler::zero, L_failure);
4809
4810 movl(r_array_index, 0);
4811 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
4812 // fall through to L_failure
4813
4814 const Register linear_result = r_array_index; // reuse temp1
4815
4816 bind(L_failure); // not present
4817 movl(linear_result, 1);
4818 jmp(L_check);
4819
4820 bind(L_success); // present
4821 movl(linear_result, 0);
4822
4823 bind(L_check);
4824 cmpl(linear_result, result);
4825 jcc(Assembler::equal, L_done);
4826
4827 { // To avoid calling convention issues, build a record on the stack
4828 // and pass the pointer to that instead.
4829 push(result);
4830 push(linear_result);
4831 push(r_sub_klass);
4832 push(r_super_klass);
4833 movptr(c_rarg1, rsp);
4834 movptr(c_rarg0, (uintptr_t) "mismatch");
4835 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
4836 should_not_reach_here();
4837 }
4838 bind(L_done);
4839
4840 BLOCK_COMMENT("} verify_secondary_supers_table");
4841 }
4842
4843 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
4844
4845 void MacroAssembler::clinit_barrier(Register klass, Label* L_fast_path, Label* L_slow_path) {
4846 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
4847
4848 Label L_fallthrough;
4849 if (L_fast_path == nullptr) {
4850 L_fast_path = &L_fallthrough;
4851 } else if (L_slow_path == nullptr) {
4852 L_slow_path = &L_fallthrough;
4853 }
4854
4855 // Fast path check: class is fully initialized.
4856 // init_state needs acquire, but x86 is TSO, and so we are already good.
4857 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4858 jcc(Assembler::equal, *L_fast_path);
4859
4860 // Fast path check: current thread is initializer thread
4861 cmpptr(r15_thread, Address(klass, InstanceKlass::init_thread_offset()));
4862 if (L_slow_path == &L_fallthrough) {
4863 jcc(Assembler::equal, *L_fast_path);
4864 bind(*L_slow_path);
4865 } else if (L_fast_path == &L_fallthrough) {
4866 jcc(Assembler::notEqual, *L_slow_path);
4867 bind(*L_fast_path);
4868 } else {
4869 Unimplemented();
4870 }
4871 }
4872
4873 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4874 if (VM_Version::supports_cmov()) {
4875 cmovl(cc, dst, src);
4876 } else {
4877 Label L;
4878 jccb(negate_condition(cc), L);
4879 movl(dst, src);
4880 bind(L);
4881 }
4882 }
4883
4884 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4885 if (VM_Version::supports_cmov()) {
4886 cmovl(cc, dst, src);
4887 } else {
4888 Label L;
4889 jccb(negate_condition(cc), L);
4890 movl(dst, src);
4891 bind(L);
4892 }
4893 }
4894
4895 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4896 if (!VerifyOops || VerifyAdapterSharing) {
4897 // Below address of the code string confuses VerifyAdapterSharing
4898 // because it may differ between otherwise equivalent adapters.
4899 return;
4900 }
4901
4902 BLOCK_COMMENT("verify_oop {");
4903 push(rscratch1);
4904 push(rax); // save rax
4905 push(reg); // pass register argument
4906
4907 // Pass register number to verify_oop_subroutine
4908 const char* b = nullptr;
4909 {
4910 ResourceMark rm;
4911 stringStream ss;
4912 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4913 b = code_string(ss.as_string());
4914 }
4915 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
4916 pushptr(buffer.addr(), rscratch1);
4917
4918 // call indirectly to solve generation ordering problem
4919 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4920 call(rax);
4921 // Caller pops the arguments (oop, message) and restores rax, r10
4922 BLOCK_COMMENT("} verify_oop");
4923 }
4924
4925 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4926 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4927 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
4928 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
4929 vpternlogd(dst, 0xFF, dst, dst, vector_len);
4930 } else if (VM_Version::supports_avx()) {
4931 vpcmpeqd(dst, dst, dst, vector_len);
4932 } else {
4933 pcmpeqd(dst, dst);
4934 }
4935 }
4936
4937 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4938 int extra_slot_offset) {
4939 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4940 int stackElementSize = Interpreter::stackElementSize;
4941 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4942 #ifdef ASSERT
4943 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4944 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4945 #endif
4946 Register scale_reg = noreg;
4947 Address::ScaleFactor scale_factor = Address::no_scale;
4948 if (arg_slot.is_constant()) {
4949 offset += arg_slot.as_constant() * stackElementSize;
4950 } else {
4951 scale_reg = arg_slot.as_register();
4952 scale_factor = Address::times(stackElementSize);
4953 }
4954 offset += wordSize; // return PC is on stack
4955 return Address(rsp, scale_reg, scale_factor, offset);
4956 }
4957
4958 // Handle the receiver type profile update given the "recv" klass.
4959 //
4960 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
4961 // If there are no matching or claimable receiver entries in RD, updates
4962 // the polymorphic counter.
4963 //
4964 // This code expected to run by either the interpreter or JIT-ed code, without
4965 // extra synchronization. For safety, receiver cells are claimed atomically, which
4966 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
4967 // counter updates are not atomic.
4968 //
4969 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
4970 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
4971 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
4972 int poly_count_offset = in_bytes(CounterData::count_offset());
4973 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
4974 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
4975
4976 // Adjust for MDP offsets. Slots are pointer-sized, so is the global offset.
4977 assert(is_aligned(mdp_offset, BytesPerWord), "sanity");
4978 base_receiver_offset += mdp_offset;
4979 end_receiver_offset += mdp_offset;
4980 poly_count_offset += mdp_offset;
4981
4982 // Scale down to optimize encoding. Slots are pointer-sized.
4983 assert(is_aligned(base_receiver_offset, BytesPerWord), "sanity");
4984 assert(is_aligned(end_receiver_offset, BytesPerWord), "sanity");
4985 assert(is_aligned(poly_count_offset, BytesPerWord), "sanity");
4986 assert(is_aligned(receiver_step, BytesPerWord), "sanity");
4987 assert(is_aligned(receiver_to_count_step, BytesPerWord), "sanity");
4988 base_receiver_offset >>= LogBytesPerWord;
4989 end_receiver_offset >>= LogBytesPerWord;
4990 poly_count_offset >>= LogBytesPerWord;
4991 receiver_step >>= LogBytesPerWord;
4992 receiver_to_count_step >>= LogBytesPerWord;
4993
4994 #ifdef ASSERT
4995 // We are about to walk the MDO slots without asking for offsets.
4996 // Check that our math hits all the right spots.
4997 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
4998 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
4999 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
5000 int offset = base_receiver_offset + receiver_step*c;
5001 int count_offset = offset + receiver_to_count_step;
5002 assert((offset << LogBytesPerWord) == real_recv_offset, "receiver slot math");
5003 assert((count_offset << LogBytesPerWord) == real_count_offset, "receiver count math");
5004 }
5005 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
5006 assert(poly_count_offset << LogBytesPerWord == real_poly_count_offset, "poly counter math");
5007 #endif
5008
5009 // Corner case: no profile table. Increment poly counter and exit.
5010 if (ReceiverTypeData::row_limit() == 0) {
5011 addptr(Address(mdp, poly_count_offset, Address::times_ptr), DataLayout::counter_increment);
5012 return;
5013 }
5014
5015 Register offset = rscratch1;
5016
5017 Label L_loop_search_receiver, L_loop_search_empty;
5018 Label L_restart, L_found_recv, L_found_empty, L_count_update;
5019
5020 // The code here recognizes three major cases:
5021 // A. Fastest: receiver found in the table
5022 // B. Fast: no receiver in the table, and the table is full
5023 // C. Slow: no receiver in the table, free slots in the table
5024 //
5025 // The case A performance is most important, as perfectly-behaved code would end up
5026 // there, especially with larger TypeProfileWidth. The case B performance is
5027 // important as well, this is where bulk of code would land for normally megamorphic
5028 // cases. The case C performance is not essential, its job is to deal with installation
5029 // races, we optimize for code density instead. Case C needs to make sure that receiver
5030 // rows are only claimed once. This makes sure we never overwrite a row for another
5031 // receiver and never duplicate the receivers in the list, making profile type-accurate.
5032 //
5033 // It is very tempting to handle these cases in a single loop, and claim the first slot
5034 // without checking the rest of the table. But, profiling code should tolerate free slots
5035 // in the table, as class unloading can clear them. After such cleanup, the receiver
5036 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
5037 // to complete, before trying to install new slots. Splitting the code in several tight
5038 // loops also helpfully optimizes for cases A and B.
5039 //
5040 // This code is effectively:
5041 //
5042 // restart:
5043 // // Fastest: receiver is already installed
5044 // for (i = 0; i < receiver_count(); i++) {
5045 // if (receiver(i) == recv) goto found_recv(i);
5046 // }
5047 //
5048 // // Fast: no receiver, but profile is not full
5049 // for (i = 0; i < receiver_count(); i++) {
5050 // if (receiver(i) == null) goto found_null(i);
5051 // }
5052 //
5053 // // Slow: profile is full, polymorphic case
5054 // count++;
5055 // return
5056 //
5057 // // Slow: try to install receiver
5058 // found_null(i):
5059 // CAS(&receiver(i), null, recv);
5060 // goto restart
5061 //
5062 // found_recv(i):
5063 // *receiver_count(i)++
5064 //
5065
5066 bind(L_restart);
5067
5068 // Fastest: receiver is already installed
5069 movptr(offset, base_receiver_offset);
5070 bind(L_loop_search_receiver);
5071 cmpptr(recv, Address(mdp, offset, Address::times_ptr));
5072 jccb(Assembler::equal, L_found_recv);
5073 addptr(offset, receiver_step);
5074 cmpptr(offset, end_receiver_offset);
5075 jccb(Assembler::notEqual, L_loop_search_receiver);
5076
5077 // Fast: no receiver, but profile is not full
5078 movptr(offset, base_receiver_offset);
5079 bind(L_loop_search_empty);
5080 cmpptr(Address(mdp, offset, Address::times_ptr), NULL_WORD);
5081 jccb(Assembler::equal, L_found_empty);
5082 addptr(offset, receiver_step);
5083 cmpptr(offset, end_receiver_offset);
5084 jccb(Assembler::notEqual, L_loop_search_empty);
5085
5086 // Slow: Receiver is not found and table is full.
5087 // Increment polymorphic counter instead of receiver slot.
5088 movptr(offset, poly_count_offset);
5089 jmpb(L_count_update);
5090
5091 // Slowest: try to install receiver
5092 bind(L_found_empty);
5093
5094 // Atomically swing receiver slot: null -> recv.
5095 //
5096 // The update code uses CAS, which wants RAX register specifically, *and* it needs
5097 // other important registers untouched, as they form the address. Therefore, we need
5098 // to shift any important registers from RAX into some other spare register. If we
5099 // have a spare register, we are forced to save it on stack here.
5100
5101 Register spare_reg = noreg;
5102 Register shifted_mdp = mdp;
5103 Register shifted_recv = recv;
5104 if (recv == rax || mdp == rax) {
5105 spare_reg = (recv != rbx && mdp != rbx) ? rbx :
5106 (recv != rcx && mdp != rcx) ? rcx :
5107 rdx;
5108 assert_different_registers(mdp, recv, offset, spare_reg);
5109
5110 push(spare_reg);
5111 if (recv == rax) {
5112 movptr(spare_reg, recv);
5113 shifted_recv = spare_reg;
5114 } else {
5115 assert(mdp == rax, "Remaining case");
5116 movptr(spare_reg, mdp);
5117 shifted_mdp = spare_reg;
5118 }
5119 } else {
5120 push(rax);
5121 }
5122
5123 // None of the important registers are in RAX after this shuffle.
5124 assert_different_registers(rax, shifted_mdp, shifted_recv, offset);
5125
5126 xorptr(rax, rax);
5127 cmpxchgptr(shifted_recv, Address(shifted_mdp, offset, Address::times_ptr));
5128
5129 // Unshift registers.
5130 if (recv == rax || mdp == rax) {
5131 movptr(rax, spare_reg);
5132 pop(spare_reg);
5133 } else {
5134 pop(rax);
5135 }
5136
5137 // CAS success means the slot now has the receiver we want. CAS failure means
5138 // something had claimed the slot concurrently: it can be the same receiver we want,
5139 // or something else. Since this is a slow path, we can optimize for code density,
5140 // and just restart the search from the beginning.
5141 jmpb(L_restart);
5142
5143 // Found a receiver, convert its slot offset to corresponding count offset.
5144 bind(L_found_recv);
5145 addptr(offset, receiver_to_count_step);
5146
5147 // Finally, update the counter
5148 bind(L_count_update);
5149 addptr(Address(mdp, offset, Address::times_ptr), DataLayout::counter_increment);
5150 }
5151
5152 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5153 if (!VerifyOops || VerifyAdapterSharing) {
5154 // Below address of the code string confuses VerifyAdapterSharing
5155 // because it may differ between otherwise equivalent adapters.
5156 return;
5157 }
5158
5159 push(rscratch1);
5160 push(rax); // save rax,
5161 // addr may contain rsp so we will have to adjust it based on the push
5162 // we just did (and on 64 bit we do two pushes)
5163 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5164 // stores rax into addr which is backwards of what was intended.
5165 if (addr.uses(rsp)) {
5166 lea(rax, addr);
5167 pushptr(Address(rax, 2 * BytesPerWord));
5168 } else {
5169 pushptr(addr);
5170 }
5171
5172 // Pass register number to verify_oop_subroutine
5173 const char* b = nullptr;
5174 {
5175 ResourceMark rm;
5176 stringStream ss;
5177 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5178 b = code_string(ss.as_string());
5179 }
5180 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5181 pushptr(buffer.addr(), rscratch1);
5182
5183 // call indirectly to solve generation ordering problem
5184 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5185 call(rax);
5186 // Caller pops the arguments (addr, message) and restores rax, r10.
5187 }
5188
5189 void MacroAssembler::verify_tlab() {
5190 #ifdef ASSERT
5191 if (UseTLAB && VerifyOops) {
5192 Label next, ok;
5193 Register t1 = rsi;
5194
5195 push(t1);
5196
5197 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5198 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
5199 jcc(Assembler::aboveEqual, next);
5200 STOP("assert(top >= start)");
5201 should_not_reach_here();
5202
5203 bind(next);
5204 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
5205 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5206 jcc(Assembler::aboveEqual, ok);
5207 STOP("assert(top <= end)");
5208 should_not_reach_here();
5209
5210 bind(ok);
5211 pop(t1);
5212 }
5213 #endif
5214 }
5215
5216 class ControlWord {
5217 public:
5218 int32_t _value;
5219
5220 int rounding_control() const { return (_value >> 10) & 3 ; }
5221 int precision_control() const { return (_value >> 8) & 3 ; }
5222 bool precision() const { return ((_value >> 5) & 1) != 0; }
5223 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5224 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5225 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5226 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5227 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5228
5229 void print() const {
5230 // rounding control
5231 const char* rc;
5232 switch (rounding_control()) {
5233 case 0: rc = "round near"; break;
5234 case 1: rc = "round down"; break;
5235 case 2: rc = "round up "; break;
5236 case 3: rc = "chop "; break;
5237 default:
5238 rc = nullptr; // silence compiler warnings
5239 fatal("Unknown rounding control: %d", rounding_control());
5240 };
5241 // precision control
5242 const char* pc;
5243 switch (precision_control()) {
5244 case 0: pc = "24 bits "; break;
5245 case 1: pc = "reserved"; break;
5246 case 2: pc = "53 bits "; break;
5247 case 3: pc = "64 bits "; break;
5248 default:
5249 pc = nullptr; // silence compiler warnings
5250 fatal("Unknown precision control: %d", precision_control());
5251 };
5252 // flags
5253 char f[9];
5254 f[0] = ' ';
5255 f[1] = ' ';
5256 f[2] = (precision ()) ? 'P' : 'p';
5257 f[3] = (underflow ()) ? 'U' : 'u';
5258 f[4] = (overflow ()) ? 'O' : 'o';
5259 f[5] = (zero_divide ()) ? 'Z' : 'z';
5260 f[6] = (denormalized()) ? 'D' : 'd';
5261 f[7] = (invalid ()) ? 'I' : 'i';
5262 f[8] = '\x0';
5263 // output
5264 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5265 }
5266
5267 };
5268
5269 class StatusWord {
5270 public:
5271 int32_t _value;
5272
5273 bool busy() const { return ((_value >> 15) & 1) != 0; }
5274 bool C3() const { return ((_value >> 14) & 1) != 0; }
5275 bool C2() const { return ((_value >> 10) & 1) != 0; }
5276 bool C1() const { return ((_value >> 9) & 1) != 0; }
5277 bool C0() const { return ((_value >> 8) & 1) != 0; }
5278 int top() const { return (_value >> 11) & 7 ; }
5279 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5280 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5281 bool precision() const { return ((_value >> 5) & 1) != 0; }
5282 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5283 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5284 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5285 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5286 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5287
5288 void print() const {
5289 // condition codes
5290 char c[5];
5291 c[0] = (C3()) ? '3' : '-';
5292 c[1] = (C2()) ? '2' : '-';
5293 c[2] = (C1()) ? '1' : '-';
5294 c[3] = (C0()) ? '0' : '-';
5295 c[4] = '\x0';
5296 // flags
5297 char f[9];
5298 f[0] = (error_status()) ? 'E' : '-';
5299 f[1] = (stack_fault ()) ? 'S' : '-';
5300 f[2] = (precision ()) ? 'P' : '-';
5301 f[3] = (underflow ()) ? 'U' : '-';
5302 f[4] = (overflow ()) ? 'O' : '-';
5303 f[5] = (zero_divide ()) ? 'Z' : '-';
5304 f[6] = (denormalized()) ? 'D' : '-';
5305 f[7] = (invalid ()) ? 'I' : '-';
5306 f[8] = '\x0';
5307 // output
5308 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5309 }
5310
5311 };
5312
5313 class TagWord {
5314 public:
5315 int32_t _value;
5316
5317 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5318
5319 void print() const {
5320 printf("%04x", _value & 0xFFFF);
5321 }
5322
5323 };
5324
5325 class FPU_Register {
5326 public:
5327 int32_t _m0;
5328 int32_t _m1;
5329 int16_t _ex;
5330
5331 bool is_indefinite() const {
5332 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5333 }
5334
5335 void print() const {
5336 char sign = (_ex < 0) ? '-' : '+';
5337 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5338 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5339 };
5340
5341 };
5342
5343 class FPU_State {
5344 public:
5345 enum {
5346 register_size = 10,
5347 number_of_registers = 8,
5348 register_mask = 7
5349 };
5350
5351 ControlWord _control_word;
5352 StatusWord _status_word;
5353 TagWord _tag_word;
5354 int32_t _error_offset;
5355 int32_t _error_selector;
5356 int32_t _data_offset;
5357 int32_t _data_selector;
5358 int8_t _register[register_size * number_of_registers];
5359
5360 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5361 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5362
5363 const char* tag_as_string(int tag) const {
5364 switch (tag) {
5365 case 0: return "valid";
5366 case 1: return "zero";
5367 case 2: return "special";
5368 case 3: return "empty";
5369 }
5370 ShouldNotReachHere();
5371 return nullptr;
5372 }
5373
5374 void print() const {
5375 // print computation registers
5376 { int t = _status_word.top();
5377 for (int i = 0; i < number_of_registers; i++) {
5378 int j = (i - t) & register_mask;
5379 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5380 st(j)->print();
5381 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5382 }
5383 }
5384 printf("\n");
5385 // print control registers
5386 printf("ctrl = "); _control_word.print(); printf("\n");
5387 printf("stat = "); _status_word .print(); printf("\n");
5388 printf("tags = "); _tag_word .print(); printf("\n");
5389 }
5390
5391 };
5392
5393 class Flag_Register {
5394 public:
5395 int32_t _value;
5396
5397 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5398 bool direction() const { return ((_value >> 10) & 1) != 0; }
5399 bool sign() const { return ((_value >> 7) & 1) != 0; }
5400 bool zero() const { return ((_value >> 6) & 1) != 0; }
5401 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5402 bool parity() const { return ((_value >> 2) & 1) != 0; }
5403 bool carry() const { return ((_value >> 0) & 1) != 0; }
5404
5405 void print() const {
5406 // flags
5407 char f[8];
5408 f[0] = (overflow ()) ? 'O' : '-';
5409 f[1] = (direction ()) ? 'D' : '-';
5410 f[2] = (sign ()) ? 'S' : '-';
5411 f[3] = (zero ()) ? 'Z' : '-';
5412 f[4] = (auxiliary_carry()) ? 'A' : '-';
5413 f[5] = (parity ()) ? 'P' : '-';
5414 f[6] = (carry ()) ? 'C' : '-';
5415 f[7] = '\x0';
5416 // output
5417 printf("%08x flags = %s", _value, f);
5418 }
5419
5420 };
5421
5422 class IU_Register {
5423 public:
5424 int32_t _value;
5425
5426 void print() const {
5427 printf("%08x %11d", _value, _value);
5428 }
5429
5430 };
5431
5432 class IU_State {
5433 public:
5434 Flag_Register _eflags;
5435 IU_Register _rdi;
5436 IU_Register _rsi;
5437 IU_Register _rbp;
5438 IU_Register _rsp;
5439 IU_Register _rbx;
5440 IU_Register _rdx;
5441 IU_Register _rcx;
5442 IU_Register _rax;
5443
5444 void print() const {
5445 // computation registers
5446 printf("rax, = "); _rax.print(); printf("\n");
5447 printf("rbx, = "); _rbx.print(); printf("\n");
5448 printf("rcx = "); _rcx.print(); printf("\n");
5449 printf("rdx = "); _rdx.print(); printf("\n");
5450 printf("rdi = "); _rdi.print(); printf("\n");
5451 printf("rsi = "); _rsi.print(); printf("\n");
5452 printf("rbp, = "); _rbp.print(); printf("\n");
5453 printf("rsp = "); _rsp.print(); printf("\n");
5454 printf("\n");
5455 // control registers
5456 printf("flgs = "); _eflags.print(); printf("\n");
5457 }
5458 };
5459
5460
5461 class CPU_State {
5462 public:
5463 FPU_State _fpu_state;
5464 IU_State _iu_state;
5465
5466 void print() const {
5467 printf("--------------------------------------------------\n");
5468 _iu_state .print();
5469 printf("\n");
5470 _fpu_state.print();
5471 printf("--------------------------------------------------\n");
5472 }
5473
5474 };
5475
5476
5477 static void _print_CPU_state(CPU_State* state) {
5478 state->print();
5479 };
5480
5481
5482 void MacroAssembler::print_CPU_state() {
5483 push_CPU_state();
5484 push(rsp); // pass CPU state
5485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5486 addptr(rsp, wordSize); // discard argument
5487 pop_CPU_state();
5488 }
5489
5490 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5491 // Either restore the MXCSR register after returning from the JNI Call
5492 // or verify that it wasn't changed (with -Xcheck:jni flag).
5493 if (RestoreMXCSROnJNICalls) {
5494 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5495 } else if (CheckJNICalls) {
5496 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5497 }
5498 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5499 vzeroupper();
5500 }
5501
5502 // ((OopHandle)result).resolve();
5503 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5504 assert_different_registers(result, tmp);
5505
5506 // Only 64 bit platforms support GCs that require a tmp register
5507 // Only IN_HEAP loads require a thread_tmp register
5508 // OopHandle::resolve is an indirection like jobject.
5509 access_load_at(T_OBJECT, IN_NATIVE,
5510 result, Address(result, 0), tmp);
5511 }
5512
5513 // ((WeakHandle)result).resolve();
5514 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5515 assert_different_registers(rresult, rtmp);
5516 Label resolved;
5517
5518 // A null weak handle resolves to null.
5519 cmpptr(rresult, 0);
5520 jcc(Assembler::equal, resolved);
5521
5522 // Only 64 bit platforms support GCs that require a tmp register
5523 // Only IN_HEAP loads require a thread_tmp register
5524 // WeakHandle::resolve is an indirection like jweak.
5525 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5526 rresult, Address(rresult, 0), rtmp);
5527 bind(resolved);
5528 }
5529
5530 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5531 // get mirror
5532 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5533 load_method_holder(mirror, method);
5534 movptr(mirror, Address(mirror, mirror_offset));
5535 resolve_oop_handle(mirror, tmp);
5536 }
5537
5538 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5539 load_method_holder(rresult, rmethod);
5540 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5541 }
5542
5543 void MacroAssembler::load_method_holder(Register holder, Register method) {
5544 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5545 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5546 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5547 }
5548
5549 void MacroAssembler::load_metadata(Register dst, Register src) {
5550 if (UseCompactObjectHeaders) {
5551 load_narrow_klass_compact(dst, src);
5552 } else {
5553 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5554 }
5555 }
5556
5557 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5558 assert(UseCompactObjectHeaders, "expect compact object headers");
5559 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5560 shrq(dst, markWord::klass_shift);
5561 }
5562
5563 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5564 assert_different_registers(src, tmp);
5565 assert_different_registers(dst, tmp);
5566
5567 if (UseCompactObjectHeaders) {
5568 load_narrow_klass_compact(dst, src);
5569 decode_klass_not_null(dst, tmp);
5570 } else {
5571 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5572 decode_klass_not_null(dst, tmp);
5573 }
5574 }
5575
5576 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
5577 load_klass(dst, src, tmp);
5578 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5579 }
5580
5581 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5582 assert(!UseCompactObjectHeaders, "not with compact headers");
5583 assert_different_registers(src, tmp);
5584 assert_different_registers(dst, tmp);
5585 encode_klass_not_null(src, tmp);
5586 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5587 }
5588
5589 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5590 if (UseCompactObjectHeaders) {
5591 assert(tmp != noreg, "need tmp");
5592 assert_different_registers(klass, obj, tmp);
5593 load_narrow_klass_compact(tmp, obj);
5594 cmpl(klass, tmp);
5595 } else {
5596 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5597 }
5598 }
5599
5600 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5601 if (UseCompactObjectHeaders) {
5602 assert(tmp2 != noreg, "need tmp2");
5603 assert_different_registers(obj1, obj2, tmp1, tmp2);
5604 load_narrow_klass_compact(tmp1, obj1);
5605 load_narrow_klass_compact(tmp2, obj2);
5606 cmpl(tmp1, tmp2);
5607 } else {
5608 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5609 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5610 }
5611 }
5612
5613 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5614 Register tmp1) {
5615 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5616 decorators = AccessInternal::decorator_fixup(decorators, type);
5617 bool as_raw = (decorators & AS_RAW) != 0;
5618 if (as_raw) {
5619 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1);
5620 } else {
5621 bs->load_at(this, decorators, type, dst, src, tmp1);
5622 }
5623 }
5624
5625 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5626 Register tmp1, Register tmp2, Register tmp3) {
5627 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5628 decorators = AccessInternal::decorator_fixup(decorators, type);
5629 bool as_raw = (decorators & AS_RAW) != 0;
5630 if (as_raw) {
5631 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5632 } else {
5633 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5634 }
5635 }
5636
5637 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5638 Register inline_layout_info) {
5639 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5640 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5641 }
5642
5643 void MacroAssembler::payload_offset(Register inline_klass, Register offset) {
5644 movptr(offset, Address(inline_klass, InlineKlass::adr_members_offset()));
5645 movl(offset, Address(offset, InlineKlass::payload_offset_offset()));
5646 }
5647
5648 void MacroAssembler::payload_addr(Register oop, Register data, Register inline_klass) {
5649 // ((address) (void*) o) + vk->payload_offset();
5650 Register offset = (data == oop) ? rscratch1 : data;
5651 payload_offset(inline_klass, offset);
5652 if (data == oop) {
5653 addptr(data, offset);
5654 } else {
5655 lea(data, Address(oop, offset));
5656 }
5657 }
5658
5659 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5660 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1);
5661 }
5662
5663 // Doesn't do verification, generates fixed size code
5664 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5665 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1);
5666 }
5667
5668 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5669 Register tmp2, Register tmp3, DecoratorSet decorators) {
5670 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5671 }
5672
5673 // Used for storing nulls.
5674 void MacroAssembler::store_heap_oop_null(Address dst) {
5675 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5676 }
5677
5678 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5679 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5680 // Store to klass gap in destination
5681 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5682 }
5683
5684 #ifdef ASSERT
5685 void MacroAssembler::verify_heapbase(const char* msg) {
5686 assert (UseCompressedOops, "should be compressed");
5687 assert (Universe::heap() != nullptr, "java heap should be initialized");
5688 if (CheckCompressedOops) {
5689 Label ok;
5690 ExternalAddress src2(CompressedOops::base_addr());
5691 const bool is_src2_reachable = reachable(src2);
5692 if (!is_src2_reachable) {
5693 push(rscratch1); // cmpptr trashes rscratch1
5694 }
5695 cmpptr(r12_heapbase, src2, rscratch1);
5696 jcc(Assembler::equal, ok);
5697 STOP(msg);
5698 bind(ok);
5699 if (!is_src2_reachable) {
5700 pop(rscratch1);
5701 }
5702 }
5703 }
5704 #endif
5705
5706 // Algorithm must match oop.inline.hpp encode_heap_oop.
5707 void MacroAssembler::encode_heap_oop(Register r) {
5708 #ifdef ASSERT
5709 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5710 #endif
5711 verify_oop_msg(r, "broken oop in encode_heap_oop");
5712 if (CompressedOops::base() == nullptr) {
5713 if (CompressedOops::shift() != 0) {
5714 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5715 shrq(r, LogMinObjAlignmentInBytes);
5716 }
5717 return;
5718 }
5719 testq(r, r);
5720 cmovq(Assembler::equal, r, r12_heapbase);
5721 subq(r, r12_heapbase);
5722 shrq(r, LogMinObjAlignmentInBytes);
5723 }
5724
5725 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5726 #ifdef ASSERT
5727 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5728 if (CheckCompressedOops) {
5729 Label ok;
5730 testq(r, r);
5731 jcc(Assembler::notEqual, ok);
5732 STOP("null oop passed to encode_heap_oop_not_null");
5733 bind(ok);
5734 }
5735 #endif
5736 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5737 if (CompressedOops::base() != nullptr) {
5738 subq(r, r12_heapbase);
5739 }
5740 if (CompressedOops::shift() != 0) {
5741 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5742 shrq(r, LogMinObjAlignmentInBytes);
5743 }
5744 }
5745
5746 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5747 #ifdef ASSERT
5748 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5749 if (CheckCompressedOops) {
5750 Label ok;
5751 testq(src, src);
5752 jcc(Assembler::notEqual, ok);
5753 STOP("null oop passed to encode_heap_oop_not_null2");
5754 bind(ok);
5755 }
5756 #endif
5757 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5758 if (dst != src) {
5759 movq(dst, src);
5760 }
5761 if (CompressedOops::base() != nullptr) {
5762 subq(dst, r12_heapbase);
5763 }
5764 if (CompressedOops::shift() != 0) {
5765 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5766 shrq(dst, LogMinObjAlignmentInBytes);
5767 }
5768 }
5769
5770 void MacroAssembler::decode_heap_oop(Register r) {
5771 #ifdef ASSERT
5772 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5773 #endif
5774 if (CompressedOops::base() == nullptr) {
5775 if (CompressedOops::shift() != 0) {
5776 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5777 shlq(r, LogMinObjAlignmentInBytes);
5778 }
5779 } else {
5780 Label done;
5781 shlq(r, LogMinObjAlignmentInBytes);
5782 jccb(Assembler::equal, done);
5783 addq(r, r12_heapbase);
5784 bind(done);
5785 }
5786 verify_oop_msg(r, "broken oop in decode_heap_oop");
5787 }
5788
5789 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5790 // Note: it will change flags
5791 assert (UseCompressedOops, "should only be used for compressed headers");
5792 assert (Universe::heap() != nullptr, "java heap should be initialized");
5793 // Cannot assert, unverified entry point counts instructions (see .ad file)
5794 // vtableStubs also counts instructions in pd_code_size_limit.
5795 // Also do not verify_oop as this is called by verify_oop.
5796 if (CompressedOops::shift() != 0) {
5797 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5798 shlq(r, LogMinObjAlignmentInBytes);
5799 if (CompressedOops::base() != nullptr) {
5800 addq(r, r12_heapbase);
5801 }
5802 } else {
5803 assert (CompressedOops::base() == nullptr, "sanity");
5804 }
5805 }
5806
5807 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5808 // Note: it will change flags
5809 assert (UseCompressedOops, "should only be used for compressed headers");
5810 assert (Universe::heap() != nullptr, "java heap should be initialized");
5811 // Cannot assert, unverified entry point counts instructions (see .ad file)
5812 // vtableStubs also counts instructions in pd_code_size_limit.
5813 // Also do not verify_oop as this is called by verify_oop.
5814 if (CompressedOops::shift() != 0) {
5815 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5816 if (LogMinObjAlignmentInBytes == Address::times_8) {
5817 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5818 } else {
5819 if (dst != src) {
5820 movq(dst, src);
5821 }
5822 shlq(dst, LogMinObjAlignmentInBytes);
5823 if (CompressedOops::base() != nullptr) {
5824 addq(dst, r12_heapbase);
5825 }
5826 }
5827 } else {
5828 assert (CompressedOops::base() == nullptr, "sanity");
5829 if (dst != src) {
5830 movq(dst, src);
5831 }
5832 }
5833 }
5834
5835 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5836 BLOCK_COMMENT("encode_klass_not_null {");
5837 assert_different_registers(r, tmp);
5838 if (CompressedKlassPointers::base() != nullptr) {
5839 if (AOTCodeCache::is_on_for_dump()) {
5840 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5841 } else {
5842 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5843 }
5844 subq(r, tmp);
5845 }
5846 if (CompressedKlassPointers::shift() != 0) {
5847 shrq(r, CompressedKlassPointers::shift());
5848 }
5849 BLOCK_COMMENT("} encode_klass_not_null");
5850 }
5851
5852 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5853 BLOCK_COMMENT("encode_and_move_klass_not_null {");
5854 assert_different_registers(src, dst);
5855 if (CompressedKlassPointers::base() != nullptr) {
5856 if (AOTCodeCache::is_on_for_dump()) {
5857 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5858 negq(dst);
5859 } else {
5860 movptr(dst, -(intptr_t)CompressedKlassPointers::base());
5861 }
5862 addq(dst, src);
5863 } else {
5864 movptr(dst, src);
5865 }
5866 if (CompressedKlassPointers::shift() != 0) {
5867 shrq(dst, CompressedKlassPointers::shift());
5868 }
5869 BLOCK_COMMENT("} encode_and_move_klass_not_null");
5870 }
5871
5872 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5873 BLOCK_COMMENT("decode_klass_not_null {");
5874 assert_different_registers(r, tmp);
5875 // Note: it will change flags
5876 // Cannot assert, unverified entry point counts instructions (see .ad file)
5877 // vtableStubs also counts instructions in pd_code_size_limit.
5878 // Also do not verify_oop as this is called by verify_oop.
5879 if (CompressedKlassPointers::shift() != 0) {
5880 shlq(r, CompressedKlassPointers::shift());
5881 }
5882 if (CompressedKlassPointers::base() != nullptr) {
5883 if (AOTCodeCache::is_on_for_dump()) {
5884 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5885 } else {
5886 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5887 }
5888 addq(r, tmp);
5889 }
5890 BLOCK_COMMENT("} decode_klass_not_null");
5891 }
5892
5893 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5894 BLOCK_COMMENT("decode_and_move_klass_not_null {");
5895 assert_different_registers(src, dst);
5896 // Note: it will change flags
5897 // Cannot assert, unverified entry point counts instructions (see .ad file)
5898 // vtableStubs also counts instructions in pd_code_size_limit.
5899 // Also do not verify_oop as this is called by verify_oop.
5900
5901 if (CompressedKlassPointers::base() == nullptr &&
5902 CompressedKlassPointers::shift() == 0) {
5903 // The best case scenario is that there is no base or shift. Then it is already
5904 // a pointer that needs nothing but a register rename.
5905 movl(dst, src);
5906 } else {
5907 if (CompressedKlassPointers::shift() <= Address::times_8) {
5908 if (CompressedKlassPointers::base() != nullptr) {
5909 if (AOTCodeCache::is_on_for_dump()) {
5910 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5911 } else {
5912 movptr(dst, (intptr_t)CompressedKlassPointers::base());
5913 }
5914 } else {
5915 xorq(dst, dst);
5916 }
5917 if (CompressedKlassPointers::shift() != 0) {
5918 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
5919 leaq(dst, Address(dst, src, Address::times_8, 0));
5920 } else {
5921 addq(dst, src);
5922 }
5923 } else {
5924 if (CompressedKlassPointers::base() != nullptr) {
5925 if (AOTCodeCache::is_on_for_dump()) {
5926 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5927 shrq(dst, CompressedKlassPointers::shift());
5928 } else {
5929 const intptr_t base_right_shifted =
5930 (intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5931 movptr(dst, base_right_shifted);
5932 }
5933 } else {
5934 xorq(dst, dst);
5935 }
5936 addq(dst, src);
5937 shlq(dst, CompressedKlassPointers::shift());
5938 }
5939 }
5940 BLOCK_COMMENT("} decode_and_move_klass_not_null");
5941 }
5942
5943 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5944 assert (UseCompressedOops, "should only be used for compressed headers");
5945 assert (Universe::heap() != nullptr, "java heap should be initialized");
5946 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5947 int oop_index = oop_recorder()->find_index(obj);
5948 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5949 mov_narrow_oop(dst, oop_index, rspec);
5950 }
5951
5952 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5953 assert (UseCompressedOops, "should only be used for compressed headers");
5954 assert (Universe::heap() != nullptr, "java heap should be initialized");
5955 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5956 int oop_index = oop_recorder()->find_index(obj);
5957 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5958 mov_narrow_oop(dst, oop_index, rspec);
5959 }
5960
5961 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5962 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5963 int klass_index = oop_recorder()->find_index(k);
5964 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5965 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5966 }
5967
5968 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5969 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5970 int klass_index = oop_recorder()->find_index(k);
5971 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5972 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5973 }
5974
5975 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5976 assert (UseCompressedOops, "should only be used for compressed headers");
5977 assert (Universe::heap() != nullptr, "java heap should be initialized");
5978 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5979 int oop_index = oop_recorder()->find_index(obj);
5980 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5981 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5982 }
5983
5984 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5985 assert (UseCompressedOops, "should only be used for compressed headers");
5986 assert (Universe::heap() != nullptr, "java heap should be initialized");
5987 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5988 int oop_index = oop_recorder()->find_index(obj);
5989 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5990 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5991 }
5992
5993 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5994 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5995 int klass_index = oop_recorder()->find_index(k);
5996 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5997 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5998 }
5999
6000 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6001 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6002 int klass_index = oop_recorder()->find_index(k);
6003 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6004 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6005 }
6006
6007 void MacroAssembler::reinit_heapbase() {
6008 if (UseCompressedOops) {
6009 if (Universe::heap() != nullptr && !AOTCodeCache::is_on_for_dump()) {
6010 if (CompressedOops::base() == nullptr) {
6011 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6012 } else {
6013 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6014 }
6015 } else {
6016 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6017 }
6018 }
6019 }
6020
6021 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6022 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6023 // An inline type might be returned. If fields are in registers we
6024 // need to allocate an inline type instance and initialize it with
6025 // the value of the fields.
6026 Label skip;
6027 // We only need a new buffered inline type if a new one is not returned
6028 testptr(rax, 1);
6029 jcc(Assembler::zero, skip);
6030 int call_offset = -1;
6031
6032 // The following code is similar to allocation code in TemplateTable::_new but has some slight differences,
6033 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6034 // allocating is not necessary if vk != nullptr, etc.
6035 Label slow_case;
6036 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6037 mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
6038 if (vk != nullptr) {
6039 // Called from C1, where the return type is statically known.
6040 movptr(rbx, (intptr_t)vk->get_InlineKlass());
6041 jint lh = vk->layout_helper();
6042 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6043 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6044 tlab_allocate(rax, noreg, lh, r13, r14, slow_case);
6045 } else {
6046 jmp(slow_case);
6047 }
6048 } else {
6049 // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
6050 mov(rbx, rax);
6051 andptr(rbx, -2);
6052 if (UseTLAB) {
6053 movl(r14, Address(rbx, Klass::layout_helper_offset()));
6054 testl(r14, Klass::_lh_instance_slow_path_bit);
6055 jcc(Assembler::notZero, slow_case);
6056 tlab_allocate(rax, r14, 0, r13, r14, slow_case);
6057 } else {
6058 jmp(slow_case);
6059 }
6060 }
6061 if (UseTLAB) {
6062 // 2. Initialize buffered inline instance header
6063 Register buffer_obj = rax;
6064 Register klass = rbx;
6065 if (UseCompactObjectHeaders) {
6066 Register mark_word = r13;
6067 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
6068 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), mark_word);
6069 } else {
6070 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
6071 xorl(r13, r13);
6072 store_klass_gap(buffer_obj, r13);
6073 if (vk == nullptr) {
6074 // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
6075 mov(r13, klass);
6076 }
6077 store_klass(buffer_obj, klass, rscratch1);
6078 klass = r13;
6079 }
6080 // 3. Initialize its fields with an inline class specific handler
6081 if (vk != nullptr) {
6082 call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6083 } else {
6084 movptr(rbx, Address(klass, InlineKlass::adr_members_offset()));
6085 movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
6086 call(rbx);
6087 }
6088 jmp(skip);
6089 }
6090 bind(slow_case);
6091 // We failed to allocate a new inline type, fall back to a runtime
6092 // call. Some oop field may be live in some registers but we can't
6093 // tell. That runtime call will take care of preserving them
6094 // across a GC if there's one.
6095 mov(rax, rscratch1);
6096
6097 if (from_interpreter) {
6098 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6099 } else {
6100 call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6101 call_offset = offset();
6102 }
6103
6104 bind(skip);
6105 return call_offset;
6106 }
6107
6108 // Move a value between registers/stack slots and update the reg_state
6109 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6110 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6111 if (reg_state[to->value()] == reg_written) {
6112 return true; // Already written
6113 }
6114 if (from != to && bt != T_VOID) {
6115 if (reg_state[to->value()] == reg_readonly) {
6116 return false; // Not yet writable
6117 }
6118 if (from->is_reg()) {
6119 if (to->is_reg()) {
6120 if (from->is_XMMRegister()) {
6121 if (bt == T_DOUBLE) {
6122 movdbl(to->as_XMMRegister(), from->as_XMMRegister());
6123 } else {
6124 assert(bt == T_FLOAT, "must be float");
6125 movflt(to->as_XMMRegister(), from->as_XMMRegister());
6126 }
6127 } else {
6128 movq(to->as_Register(), from->as_Register());
6129 }
6130 } else {
6131 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6132 Address to_addr = Address(rsp, st_off);
6133 if (from->is_XMMRegister()) {
6134 if (bt == T_DOUBLE) {
6135 movdbl(to_addr, from->as_XMMRegister());
6136 } else {
6137 assert(bt == T_FLOAT, "must be float");
6138 movflt(to_addr, from->as_XMMRegister());
6139 }
6140 } else {
6141 movq(to_addr, from->as_Register());
6142 }
6143 }
6144 } else {
6145 Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
6146 if (to->is_reg()) {
6147 if (to->is_XMMRegister()) {
6148 if (bt == T_DOUBLE) {
6149 movdbl(to->as_XMMRegister(), from_addr);
6150 } else {
6151 assert(bt == T_FLOAT, "must be float");
6152 movflt(to->as_XMMRegister(), from_addr);
6153 }
6154 } else {
6155 movq(to->as_Register(), from_addr);
6156 }
6157 } else {
6158 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6159 movq(r13, from_addr);
6160 movq(Address(rsp, st_off), r13);
6161 }
6162 }
6163 }
6164 // Update register states
6165 reg_state[from->value()] = reg_writable;
6166 reg_state[to->value()] = reg_written;
6167 return true;
6168 }
6169
6170 // Calculate the extra stack space required for packing or unpacking inline
6171 // args and adjust the stack pointer (see MacroAssembler::remove_frame).
6172 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6173 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
6174 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6175 assert(sp_inc > 0, "sanity");
6176 // Two additional slots to account for return address
6177 sp_inc += 2 * VMRegImpl::stack_slot_size;
6178
6179 push(rbp);
6180 subptr(rsp, sp_inc);
6181 #ifdef ASSERT
6182 movl(Address(rsp, 0), badRegWordVal);
6183 movl(Address(rsp, VMRegImpl::stack_slot_size), badRegWordVal);
6184 #endif
6185 return sp_inc + wordSize; // account for rbp space
6186 }
6187
6188 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
6189 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6190 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6191 RegState reg_state[]) {
6192 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6193 assert(from->is_valid(), "source must be valid");
6194 bool progress = false;
6195 #ifdef ASSERT
6196 const int start_offset = offset();
6197 #endif
6198
6199 Label L_null, L_notNull;
6200 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6201 Register tmp1 = r10;
6202 Register tmp2 = r13;
6203 Register fromReg = noreg;
6204 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, true);
6205 bool done = true;
6206 bool mark_done = true;
6207 VMReg toReg;
6208 BasicType bt;
6209 // Check if argument requires a null check
6210 bool null_check = false;
6211 VMReg nullCheckReg;
6212 while (stream.next(nullCheckReg, bt)) {
6213 if (sig->at(stream.sig_index())._offset == -1) {
6214 null_check = true;
6215 break;
6216 }
6217 }
6218 stream.reset(sig_index, to_index);
6219 while (stream.next(toReg, bt)) {
6220 assert(toReg->is_valid(), "destination must be valid");
6221 int idx = (int)toReg->value();
6222 if (reg_state[idx] == reg_readonly) {
6223 if (idx != from->value()) {
6224 mark_done = false;
6225 }
6226 done = false;
6227 continue;
6228 } else if (reg_state[idx] == reg_written) {
6229 continue;
6230 }
6231 assert(reg_state[idx] == reg_writable, "must be writable");
6232 reg_state[idx] = reg_written;
6233 progress = true;
6234
6235 if (fromReg == noreg) {
6236 if (from->is_reg()) {
6237 fromReg = from->as_Register();
6238 } else {
6239 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6240 movq(tmp1, Address(rsp, st_off));
6241 fromReg = tmp1;
6242 }
6243 if (null_check) {
6244 // Nullable inline type argument, emit null check
6245 testptr(fromReg, fromReg);
6246 jcc(Assembler::zero, L_null);
6247 }
6248 }
6249 int off = sig->at(stream.sig_index())._offset;
6250 if (off == -1) {
6251 assert(null_check, "Missing null check at");
6252 if (toReg->is_stack()) {
6253 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6254 movq(Address(rsp, st_off), 1);
6255 } else {
6256 movq(toReg->as_Register(), 1);
6257 }
6258 continue;
6259 }
6260 if (sig->at(stream.sig_index())._vt_oop) {
6261 if (toReg->is_stack()) {
6262 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6263 movq(Address(rsp, st_off), fromReg);
6264 } else {
6265 movq(toReg->as_Register(), fromReg);
6266 }
6267 continue;
6268 }
6269 assert(off > 0, "offset in object should be positive");
6270 Address fromAddr = Address(fromReg, off);
6271 if (!toReg->is_XMMRegister()) {
6272 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
6273 if (is_reference_type(bt)) {
6274 load_heap_oop(dst, fromAddr);
6275 } else {
6276 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
6277 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
6278 }
6279 if (toReg->is_stack()) {
6280 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6281 movq(Address(rsp, st_off), dst);
6282 }
6283 } else if (bt == T_DOUBLE) {
6284 movdbl(toReg->as_XMMRegister(), fromAddr);
6285 } else {
6286 assert(bt == T_FLOAT, "must be float");
6287 movflt(toReg->as_XMMRegister(), fromAddr);
6288 }
6289 }
6290 if (progress && null_check) {
6291 if (done) {
6292 jmp(L_notNull);
6293 bind(L_null);
6294 // Set null marker to zero to signal that the argument is null.
6295 // Also set all fields to zero since the runtime requires a canonical
6296 // representation of a flat null.
6297 stream.reset(sig_index, to_index);
6298 while (stream.next(toReg, bt)) {
6299 if (toReg->is_stack()) {
6300 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6301 movq(Address(rsp, st_off), 0);
6302 } else if (toReg->is_XMMRegister()) {
6303 xorps(toReg->as_XMMRegister(), toReg->as_XMMRegister());
6304 } else {
6305 xorl(toReg->as_Register(), toReg->as_Register());
6306 }
6307 }
6308 bind(L_notNull);
6309 } else {
6310 bind(L_null);
6311 }
6312 }
6313
6314 sig_index = stream.sig_index();
6315 to_index = stream.regs_index();
6316
6317 if (mark_done && reg_state[from->value()] != reg_written) {
6318 // This is okay because no one else will write to that slot
6319 reg_state[from->value()] = reg_writable;
6320 }
6321 from_index--;
6322 assert(progress || (start_offset == offset()), "should not emit code");
6323 return done;
6324 }
6325
6326 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
6327 VMRegPair* from, int from_count, int& from_index, VMReg to,
6328 RegState reg_state[], Register val_array) {
6329 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
6330 assert(to->is_valid(), "destination must be valid");
6331
6332 if (reg_state[to->value()] == reg_written) {
6333 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6334 return true; // Already written
6335 }
6336
6337 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
6338 Register val_obj_tmp = r11;
6339 Register from_reg_tmp = r14;
6340 Register tmp1 = r10;
6341 Register tmp2 = r13;
6342 Register tmp3 = rbx;
6343 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
6344
6345 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
6346
6347 if (reg_state[to->value()] == reg_readonly) {
6348 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
6349 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6350 return false; // Not yet writable
6351 }
6352 val_obj = val_obj_tmp;
6353 }
6354
6355 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
6356 VMReg fromReg;
6357 BasicType bt;
6358 Label L_null;
6359 while (stream.next(fromReg, bt)) {
6360 assert(fromReg->is_valid(), "source must be valid");
6361 reg_state[fromReg->value()] = reg_writable;
6362
6363 int off = sig->at(stream.sig_index())._offset;
6364 if (off == -1) {
6365 // Nullable inline type argument, emit null check
6366 Label L_notNull;
6367 if (fromReg->is_stack()) {
6368 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6369 testb(Address(rsp, ld_off), 1);
6370 } else {
6371 testb(fromReg->as_Register(), 1);
6372 }
6373 jcc(Assembler::notZero, L_notNull);
6374 movptr(val_obj, 0);
6375 jmp(L_null);
6376 bind(L_notNull);
6377 continue;
6378 }
6379 if (sig->at(stream.sig_index())._vt_oop) {
6380 // buffer argument: use if non null
6381 if (fromReg->is_stack()) {
6382 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6383 movptr(val_obj, Address(rsp, ld_off));
6384 } else {
6385 movptr(val_obj, fromReg->as_Register());
6386 }
6387 testptr(val_obj, val_obj);
6388 jcc(Assembler::notEqual, L_null);
6389 // otherwise get the buffer from the just allocated pool of buffers
6390 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
6391 load_heap_oop(val_obj, Address(val_array, index));
6392 continue;
6393 }
6394
6395 assert(off > 0, "offset in object should be positive");
6396 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
6397
6398 // Pack the scalarized field into the value object.
6399 Address dst(val_obj, off);
6400 if (!fromReg->is_XMMRegister()) {
6401 Register src;
6402 if (fromReg->is_stack()) {
6403 src = from_reg_tmp;
6404 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6405 load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
6406 } else {
6407 src = fromReg->as_Register();
6408 }
6409 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
6410 if (is_reference_type(bt)) {
6411 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep val_obj valid.
6412 mov(tmp3, val_obj);
6413 Address dst_with_tmp3(tmp3, off);
6414 store_heap_oop(dst_with_tmp3, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
6415 } else {
6416 store_sized_value(dst, src, size_in_bytes);
6417 }
6418 } else if (bt == T_DOUBLE) {
6419 movdbl(dst, fromReg->as_XMMRegister());
6420 } else {
6421 assert(bt == T_FLOAT, "must be float");
6422 movflt(dst, fromReg->as_XMMRegister());
6423 }
6424 }
6425 bind(L_null);
6426 sig_index = stream.sig_index();
6427 from_index = stream.regs_index();
6428
6429 assert(reg_state[to->value()] == reg_writable, "must have already been read");
6430 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6431 assert(success, "to register must be writable");
6432 return true;
6433 }
6434
6435 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6436 return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
6437 }
6438
6439 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
6440 assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6441 if (needs_stack_repair) {
6442 // The method has a scalarized entry point (where fields of value object arguments
6443 // are passed through registers and stack), and a non-scalarized entry point (where
6444 // value object arguments are given as oops). The non-scalarized entry point will
6445 // first load each field of value object arguments and store them in registers and on
6446 // the stack in a way compatible with the scalarized entry point. To do so, some extra
6447 // stack space might be reserved (if argument registers are not enough). On leaving the
6448 // method, this space must be freed.
6449 //
6450 // In case we used the non-scalarized entry point the stack looks like this:
6451 //
6452 // | Arguments from caller |
6453 // |---------------------------| <-- caller's SP
6454 // | Return address #1 |
6455 // | Saved RBP #1 |
6456 // |---------------------------|
6457 // | Extension space for |
6458 // | inline arg (un)packing |
6459 // |---------------------------| <-- start of this method's frame
6460 // | Return address #2 |
6461 // | Saved RBP #2 |
6462 // |---------------------------| <-- RBP (with -XX:+PreserveFramePointer)
6463 // | sp_inc |
6464 // | method locals |
6465 // |---------------------------| <-- SP
6466 //
6467 // Space for the return pc and saved rbp is reserved twice. But only the #1 copies
6468 // contain the real values of return pc and saved rbp. The #2 copies are not reliable
6469 // and should not be used. They are mostly needed to add space between the extension
6470 // space and the locals, as there would be between the real arguments and the locals
6471 // if we don't need to do unpacking (from the scalarized entry point).
6472 //
6473 // When leaving, one must load RBP #1 into RBP, and use the copy #1 of the return address,
6474 // while keeping in mind that from the scalarized entry point, there will be only one
6475 // copy. Indeed, in the case we used the scalarized calling convention, the stack looks like this:
6476 //
6477 // | Arguments from caller |
6478 // |---------------------------| <-- caller's SP
6479 // | Return address |
6480 // | Saved RBP |
6481 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer)
6482 // | sp_inc |
6483 // | method locals |
6484 // |---------------------------| <-- SP
6485 //
6486 // The sp_inc stack slot holds the total size of the frame, including the extension
6487 // space and copies #2 of the return address and the saved RBP (but never the copies
6488 // #1 of the return address and saved RBP). That is how to find the copies #1 of the
6489 // return address and saved rbp. This size is expressed in bytes. Be careful when using
6490 // it from C++ in pointer arithmetic you might need to divide it by wordSize.
6491
6492 // The stack increment resides just below the saved rbp
6493 addq(rsp, Address(rsp, initial_framesize - wordSize));
6494 pop(rbp);
6495 } else {
6496 if (initial_framesize > 0) {
6497 addq(rsp, initial_framesize);
6498 }
6499 pop(rbp);
6500 }
6501 }
6502
6503 #ifdef COMPILER2
6504
6505 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6506 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
6507 // cnt - number of qwords (8-byte words).
6508 // base - start address, qword aligned.
6509 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6510 bool use64byteVector = (MaxVectorSize == 64) && (CopyAVX3Threshold == 0);
6511 if (use64byteVector) {
6512 evpbroadcastq(xtmp, val, AVX_512bit);
6513 } else if (MaxVectorSize >= 32) {
6514 movdq(xtmp, val);
6515 punpcklqdq(xtmp, xtmp);
6516 vinserti128_high(xtmp, xtmp);
6517 } else {
6518 movdq(xtmp, val);
6519 punpcklqdq(xtmp, xtmp);
6520 }
6521 jmp(L_zero_64_bytes);
6522
6523 BIND(L_loop);
6524 if (MaxVectorSize >= 32) {
6525 fill64(base, 0, xtmp, use64byteVector);
6526 } else {
6527 movdqu(Address(base, 0), xtmp);
6528 movdqu(Address(base, 16), xtmp);
6529 movdqu(Address(base, 32), xtmp);
6530 movdqu(Address(base, 48), xtmp);
6531 }
6532 addptr(base, 64);
6533
6534 BIND(L_zero_64_bytes);
6535 subptr(cnt, 8);
6536 jccb(Assembler::greaterEqual, L_loop);
6537
6538 // Copy trailing 64 bytes
6539 if (use64byteVector) {
6540 addptr(cnt, 8);
6541 jccb(Assembler::equal, L_end);
6542 fill64_masked(3, base, 0, xtmp, mask, cnt, val, true);
6543 jmp(L_end);
6544 } else {
6545 addptr(cnt, 4);
6546 jccb(Assembler::less, L_tail);
6547 if (MaxVectorSize >= 32) {
6548 vmovdqu(Address(base, 0), xtmp);
6549 } else {
6550 movdqu(Address(base, 0), xtmp);
6551 movdqu(Address(base, 16), xtmp);
6552 }
6553 }
6554 addptr(base, 32);
6555 subptr(cnt, 4);
6556
6557 BIND(L_tail);
6558 addptr(cnt, 4);
6559 jccb(Assembler::lessEqual, L_end);
6560 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6561 fill32_masked(3, base, 0, xtmp, mask, cnt, val);
6562 } else {
6563 decrement(cnt);
6564
6565 BIND(L_sloop);
6566 movq(Address(base, 0), xtmp);
6567 addptr(base, 8);
6568 decrement(cnt);
6569 jccb(Assembler::greaterEqual, L_sloop);
6570 }
6571 BIND(L_end);
6572 }
6573
6574 // Clearing constant sized memory using YMM/ZMM registers.
6575 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6576 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6577 bool use64byteVector = (MaxVectorSize > 32) && (CopyAVX3Threshold == 0);
6578
6579 int vector64_count = (cnt & (~0x7)) >> 3;
6580 cnt = cnt & 0x7;
6581 const int fill64_per_loop = 4;
6582 const int max_unrolled_fill64 = 8;
6583
6584 // 64 byte initialization loop.
6585 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6586 int start64 = 0;
6587 if (vector64_count > max_unrolled_fill64) {
6588 Label LOOP;
6589 Register index = rtmp;
6590
6591 start64 = vector64_count - (vector64_count % fill64_per_loop);
6592
6593 movl(index, 0);
6594 BIND(LOOP);
6595 for (int i = 0; i < fill64_per_loop; i++) {
6596 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6597 }
6598 addl(index, fill64_per_loop * 64);
6599 cmpl(index, start64 * 64);
6600 jccb(Assembler::less, LOOP);
6601 }
6602 for (int i = start64; i < vector64_count; i++) {
6603 fill64(base, i * 64, xtmp, use64byteVector);
6604 }
6605
6606 // Clear remaining 64 byte tail.
6607 int disp = vector64_count * 64;
6608 if (cnt) {
6609 switch (cnt) {
6610 case 1:
6611 movq(Address(base, disp), xtmp);
6612 break;
6613 case 2:
6614 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6615 break;
6616 case 3:
6617 movl(rtmp, 0x7);
6618 kmovwl(mask, rtmp);
6619 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6620 break;
6621 case 4:
6622 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6623 break;
6624 case 5:
6625 if (use64byteVector) {
6626 movl(rtmp, 0x1F);
6627 kmovwl(mask, rtmp);
6628 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6629 } else {
6630 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6631 movq(Address(base, disp + 32), xtmp);
6632 }
6633 break;
6634 case 6:
6635 if (use64byteVector) {
6636 movl(rtmp, 0x3F);
6637 kmovwl(mask, rtmp);
6638 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6639 } else {
6640 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6641 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6642 }
6643 break;
6644 case 7:
6645 if (use64byteVector) {
6646 movl(rtmp, 0x7F);
6647 kmovwl(mask, rtmp);
6648 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6649 } else {
6650 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6651 movl(rtmp, 0x7);
6652 kmovwl(mask, rtmp);
6653 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6654 }
6655 break;
6656 default:
6657 fatal("Unexpected length : %d\n",cnt);
6658 break;
6659 }
6660 }
6661 }
6662
6663 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
6664 bool is_large, bool word_copy_only, KRegister mask) {
6665 // cnt - number of qwords (8-byte words).
6666 // base - start address, qword aligned.
6667 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6668 assert(base==rdi, "base register must be edi for rep stos");
6669 assert(val==rax, "val register must be eax for rep stos");
6670 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6671 assert(InitArrayShortSize % BytesPerLong == 0,
6672 "InitArrayShortSize should be the multiple of BytesPerLong");
6673
6674 Label DONE;
6675
6676 if (!is_large) {
6677 Label LOOP, LONG;
6678 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6679 jccb(Assembler::greater, LONG);
6680
6681 decrement(cnt);
6682 jccb(Assembler::negative, DONE); // Zero length
6683
6684 // Use individual pointer-sized stores for small counts:
6685 BIND(LOOP);
6686 movptr(Address(base, cnt, Address::times_ptr), val);
6687 decrement(cnt);
6688 jccb(Assembler::greaterEqual, LOOP);
6689 jmpb(DONE);
6690
6691 BIND(LONG);
6692 }
6693
6694 // Use longer rep-prefixed ops for non-small counts:
6695 if (UseFastStosb && !word_copy_only) {
6696 shlptr(cnt, 3); // convert to number of bytes
6697 rep_stosb();
6698 } else if (UseXMMForObjInit) {
6699 xmm_clear_mem(base, cnt, val, xtmp, mask);
6700 } else {
6701 rep_stos();
6702 }
6703
6704 BIND(DONE);
6705 }
6706
6707 #endif //COMPILER2
6708
6709
6710 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6711 Register to, Register value, Register count,
6712 Register rtmp, XMMRegister xtmp) {
6713 ShortBranchVerifier sbv(this);
6714 assert_different_registers(to, value, count, rtmp);
6715 Label L_exit;
6716 Label L_fill_2_bytes, L_fill_4_bytes;
6717
6718 #if defined(COMPILER2)
6719 if(MaxVectorSize >=32 &&
6720 VM_Version::supports_avx512vlbw() &&
6721 VM_Version::supports_bmi2()) {
6722 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6723 return;
6724 }
6725 #endif
6726
6727 int shift = -1;
6728 switch (t) {
6729 case T_BYTE:
6730 shift = 2;
6731 break;
6732 case T_SHORT:
6733 shift = 1;
6734 break;
6735 case T_INT:
6736 shift = 0;
6737 break;
6738 default: ShouldNotReachHere();
6739 }
6740
6741 if (t == T_BYTE) {
6742 andl(value, 0xff);
6743 movl(rtmp, value);
6744 shll(rtmp, 8);
6745 orl(value, rtmp);
6746 }
6747 if (t == T_SHORT) {
6748 andl(value, 0xffff);
6749 }
6750 if (t == T_BYTE || t == T_SHORT) {
6751 movl(rtmp, value);
6752 shll(rtmp, 16);
6753 orl(value, rtmp);
6754 }
6755
6756 cmpptr(count, 8 << shift); // Short arrays (< 32 bytes) fill by element
6757 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6758 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6759 Label L_skip_align2;
6760 // align source address at 4 bytes address boundary
6761 if (t == T_BYTE) {
6762 Label L_skip_align1;
6763 // One byte misalignment happens only for byte arrays
6764 testptr(to, 1);
6765 jccb(Assembler::zero, L_skip_align1);
6766 movb(Address(to, 0), value);
6767 increment(to);
6768 decrement(count);
6769 BIND(L_skip_align1);
6770 }
6771 // Two bytes misalignment happens only for byte and short (char) arrays
6772 testptr(to, 2);
6773 jccb(Assembler::zero, L_skip_align2);
6774 movw(Address(to, 0), value);
6775 addptr(to, 2);
6776 subptr(count, 1<<(shift-1));
6777 BIND(L_skip_align2);
6778 }
6779 {
6780 Label L_fill_32_bytes;
6781 if (!UseUnalignedLoadStores) {
6782 // align to 8 bytes, we know we are 4 byte aligned to start
6783 testptr(to, 4);
6784 jccb(Assembler::zero, L_fill_32_bytes);
6785 movl(Address(to, 0), value);
6786 addptr(to, 4);
6787 subptr(count, 1<<shift);
6788 }
6789 BIND(L_fill_32_bytes);
6790 {
6791 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6792 movdl(xtmp, value);
6793 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6794 Label L_check_fill_32_bytes;
6795 if (UseAVX > 2) {
6796 // Fill 64-byte chunks
6797 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6798
6799 // If number of bytes to fill < CopyAVX3Threshold, perform fill using AVX2
6800 cmpptr(count, CopyAVX3Threshold);
6801 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6802
6803 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6804
6805 subptr(count, 16 << shift);
6806 jcc(Assembler::less, L_check_fill_32_bytes);
6807 align(16);
6808
6809 BIND(L_fill_64_bytes_loop_avx3);
6810 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6811 addptr(to, 64);
6812 subptr(count, 16 << shift);
6813 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6814 jmpb(L_check_fill_32_bytes);
6815
6816 BIND(L_check_fill_64_bytes_avx2);
6817 }
6818 // Fill 64-byte chunks
6819 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6820
6821 subptr(count, 16 << shift);
6822 jcc(Assembler::less, L_check_fill_32_bytes);
6823
6824 // align data for 64-byte chunks
6825 Label L_fill_64_bytes_loop, L_align_64_bytes_loop;
6826 if (EnableX86ECoreOpts) {
6827 // align 'big' arrays to cache lines to minimize split_stores
6828 cmpptr(count, 96 << shift);
6829 jcc(Assembler::below, L_fill_64_bytes_loop);
6830
6831 // Find the bytes needed for alignment
6832 movptr(rtmp, to);
6833 andptr(rtmp, 0x1c);
6834 jcc(Assembler::zero, L_fill_64_bytes_loop);
6835 negptr(rtmp); // number of bytes to fill 32-rtmp. it filled by 2 mov by 32
6836 addptr(rtmp, 32);
6837 shrptr(rtmp, 2 - shift);// get number of elements from bytes
6838 subptr(count, rtmp); // adjust count by number of elements
6839
6840 align(16);
6841 BIND(L_align_64_bytes_loop);
6842 movdl(Address(to, 0), xtmp);
6843 addptr(to, 4);
6844 subptr(rtmp, 1 << shift);
6845 jcc(Assembler::greater, L_align_64_bytes_loop);
6846 }
6847
6848 align(16);
6849 BIND(L_fill_64_bytes_loop);
6850 vmovdqu(Address(to, 0), xtmp);
6851 vmovdqu(Address(to, 32), xtmp);
6852 addptr(to, 64);
6853 subptr(count, 16 << shift);
6854 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6855
6856 align(16);
6857 BIND(L_check_fill_32_bytes);
6858 addptr(count, 8 << shift);
6859 jccb(Assembler::less, L_check_fill_8_bytes);
6860 vmovdqu(Address(to, 0), xtmp);
6861 addptr(to, 32);
6862 subptr(count, 8 << shift);
6863
6864 BIND(L_check_fill_8_bytes);
6865 // clean upper bits of YMM registers
6866 movdl(xtmp, value);
6867 pshufd(xtmp, xtmp, 0);
6868 } else {
6869 // Fill 32-byte chunks
6870 pshufd(xtmp, xtmp, 0);
6871
6872 subptr(count, 8 << shift);
6873 jcc(Assembler::less, L_check_fill_8_bytes);
6874 align(16);
6875
6876 BIND(L_fill_32_bytes_loop);
6877
6878 if (UseUnalignedLoadStores) {
6879 movdqu(Address(to, 0), xtmp);
6880 movdqu(Address(to, 16), xtmp);
6881 } else {
6882 movq(Address(to, 0), xtmp);
6883 movq(Address(to, 8), xtmp);
6884 movq(Address(to, 16), xtmp);
6885 movq(Address(to, 24), xtmp);
6886 }
6887
6888 addptr(to, 32);
6889 subptr(count, 8 << shift);
6890 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6891
6892 BIND(L_check_fill_8_bytes);
6893 }
6894 addptr(count, 8 << shift);
6895 jccb(Assembler::zero, L_exit);
6896 jmpb(L_fill_8_bytes);
6897
6898 //
6899 // length is too short, just fill qwords
6900 //
6901 align(16);
6902 BIND(L_fill_8_bytes_loop);
6903 movq(Address(to, 0), xtmp);
6904 addptr(to, 8);
6905 BIND(L_fill_8_bytes);
6906 subptr(count, 1 << (shift + 1));
6907 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6908 }
6909 }
6910
6911 Label L_fill_4_bytes_loop;
6912 testl(count, 1 << shift);
6913 jccb(Assembler::zero, L_fill_2_bytes);
6914
6915 align(16);
6916 BIND(L_fill_4_bytes_loop);
6917 movl(Address(to, 0), value);
6918 addptr(to, 4);
6919
6920 BIND(L_fill_4_bytes);
6921 subptr(count, 1 << shift);
6922 jccb(Assembler::greaterEqual, L_fill_4_bytes_loop);
6923
6924 if (t == T_BYTE || t == T_SHORT) {
6925 Label L_fill_byte;
6926 BIND(L_fill_2_bytes);
6927 // fill trailing 2 bytes
6928 testl(count, 1<<(shift-1));
6929 jccb(Assembler::zero, L_fill_byte);
6930 movw(Address(to, 0), value);
6931 if (t == T_BYTE) {
6932 addptr(to, 2);
6933 BIND(L_fill_byte);
6934 // fill trailing byte
6935 testl(count, 1);
6936 jccb(Assembler::zero, L_exit);
6937 movb(Address(to, 0), value);
6938 } else {
6939 BIND(L_fill_byte);
6940 }
6941 } else {
6942 BIND(L_fill_2_bytes);
6943 }
6944 BIND(L_exit);
6945 }
6946
6947 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6948 switch(type) {
6949 case T_BYTE:
6950 case T_BOOLEAN:
6951 evpbroadcastb(dst, src, vector_len);
6952 break;
6953 case T_SHORT:
6954 case T_CHAR:
6955 evpbroadcastw(dst, src, vector_len);
6956 break;
6957 case T_INT:
6958 case T_FLOAT:
6959 evpbroadcastd(dst, src, vector_len);
6960 break;
6961 case T_LONG:
6962 case T_DOUBLE:
6963 evpbroadcastq(dst, src, vector_len);
6964 break;
6965 default:
6966 fatal("Unhandled type : %s", type2name(type));
6967 break;
6968 }
6969 }
6970
6971 // Encode given char[]/byte[] to byte[] in ISO_8859_1 or ASCII
6972 //
6973 // @IntrinsicCandidate
6974 // int sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(
6975 // char[] sa, int sp, byte[] da, int dp, int len) {
6976 // int i = 0;
6977 // for (; i < len; i++) {
6978 // char c = sa[sp++];
6979 // if (c > '\u00FF')
6980 // break;
6981 // da[dp++] = (byte) c;
6982 // }
6983 // return i;
6984 // }
6985 //
6986 // @IntrinsicCandidate
6987 // int java.lang.StringCoding.encodeISOArray0(
6988 // byte[] sa, int sp, byte[] da, int dp, int len) {
6989 // int i = 0;
6990 // for (; i < len; i++) {
6991 // char c = StringUTF16.getChar(sa, sp++);
6992 // if (c > '\u00FF')
6993 // break;
6994 // da[dp++] = (byte) c;
6995 // }
6996 // return i;
6997 // }
6998 //
6999 // @IntrinsicCandidate
7000 // int java.lang.StringCoding.encodeAsciiArray0(
7001 // char[] sa, int sp, byte[] da, int dp, int len) {
7002 // int i = 0;
7003 // for (; i < len; i++) {
7004 // char c = sa[sp++];
7005 // if (c >= '\u0080')
7006 // break;
7007 // da[dp++] = (byte) c;
7008 // }
7009 // return i;
7010 // }
7011 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7012 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7013 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7014 Register tmp5, Register result, bool ascii) {
7015
7016 // rsi: src
7017 // rdi: dst
7018 // rdx: len
7019 // rcx: tmp5
7020 // rax: result
7021 ShortBranchVerifier sbv(this);
7022 assert_different_registers(src, dst, len, tmp5, result);
7023 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7024
7025 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
7026 int short_mask = ascii ? 0xff80 : 0xff00;
7027
7028 // set result
7029 xorl(result, result);
7030 // check for zero length
7031 testl(len, len);
7032 jcc(Assembler::zero, L_done);
7033
7034 movl(result, len);
7035
7036 // Setup pointers
7037 lea(src, Address(src, len, Address::times_2)); // char[]
7038 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7039 negptr(len);
7040
7041 if (UseSSE42Intrinsics || UseAVX >= 2) {
7042 Label L_copy_8_chars, L_copy_8_chars_exit;
7043 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7044
7045 if (UseAVX >= 2) {
7046 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7047 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7048 movdl(tmp1Reg, tmp5);
7049 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7050 jmp(L_chars_32_check);
7051
7052 bind(L_copy_32_chars);
7053 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7054 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7055 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7056 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7057 jccb(Assembler::notZero, L_copy_32_chars_exit);
7058 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7059 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7060 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7061
7062 bind(L_chars_32_check);
7063 addptr(len, 32);
7064 jcc(Assembler::lessEqual, L_copy_32_chars);
7065
7066 bind(L_copy_32_chars_exit);
7067 subptr(len, 16);
7068 jccb(Assembler::greater, L_copy_16_chars_exit);
7069
7070 } else if (UseSSE42Intrinsics) {
7071 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7072 movdl(tmp1Reg, tmp5);
7073 pshufd(tmp1Reg, tmp1Reg, 0);
7074 jmpb(L_chars_16_check);
7075 }
7076
7077 bind(L_copy_16_chars);
7078 if (UseAVX >= 2) {
7079 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7080 vptest(tmp2Reg, tmp1Reg);
7081 jcc(Assembler::notZero, L_copy_16_chars_exit);
7082 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7083 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7084 } else {
7085 if (UseAVX > 0) {
7086 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7087 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7088 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7089 } else {
7090 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7091 por(tmp2Reg, tmp3Reg);
7092 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7093 por(tmp2Reg, tmp4Reg);
7094 }
7095 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7096 jccb(Assembler::notZero, L_copy_16_chars_exit);
7097 packuswb(tmp3Reg, tmp4Reg);
7098 }
7099 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7100
7101 bind(L_chars_16_check);
7102 addptr(len, 16);
7103 jcc(Assembler::lessEqual, L_copy_16_chars);
7104
7105 bind(L_copy_16_chars_exit);
7106 if (UseAVX >= 2) {
7107 // clean upper bits of YMM registers
7108 vpxor(tmp2Reg, tmp2Reg);
7109 vpxor(tmp3Reg, tmp3Reg);
7110 vpxor(tmp4Reg, tmp4Reg);
7111 movdl(tmp1Reg, tmp5);
7112 pshufd(tmp1Reg, tmp1Reg, 0);
7113 }
7114 subptr(len, 8);
7115 jccb(Assembler::greater, L_copy_8_chars_exit);
7116
7117 bind(L_copy_8_chars);
7118 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7119 ptest(tmp3Reg, tmp1Reg);
7120 jccb(Assembler::notZero, L_copy_8_chars_exit);
7121 packuswb(tmp3Reg, tmp1Reg);
7122 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7123 addptr(len, 8);
7124 jccb(Assembler::lessEqual, L_copy_8_chars);
7125
7126 bind(L_copy_8_chars_exit);
7127 subptr(len, 8);
7128 jccb(Assembler::zero, L_done);
7129 }
7130
7131 bind(L_copy_1_char);
7132 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7133 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7134 jccb(Assembler::notZero, L_copy_1_char_exit);
7135 movb(Address(dst, len, Address::times_1, 0), tmp5);
7136 addptr(len, 1);
7137 jccb(Assembler::less, L_copy_1_char);
7138
7139 bind(L_copy_1_char_exit);
7140 addptr(result, len); // len is negative count of not processed elements
7141
7142 bind(L_done);
7143 }
7144
7145 /**
7146 * Helper for multiply_to_len().
7147 */
7148 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7149 addq(dest_lo, src1);
7150 adcq(dest_hi, 0);
7151 addq(dest_lo, src2);
7152 adcq(dest_hi, 0);
7153 }
7154
7155 /**
7156 * Multiply 64 bit by 64 bit first loop.
7157 */
7158 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7159 Register y, Register y_idx, Register z,
7160 Register carry, Register product,
7161 Register idx, Register kdx) {
7162 //
7163 // jlong carry, x[], y[], z[];
7164 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7165 // huge_128 product = y[idx] * x[xstart] + carry;
7166 // z[kdx] = (jlong)product;
7167 // carry = (jlong)(product >>> 64);
7168 // }
7169 // z[xstart] = carry;
7170 //
7171
7172 Label L_first_loop, L_first_loop_exit;
7173 Label L_one_x, L_one_y, L_multiply;
7174
7175 decrementl(xstart);
7176 jcc(Assembler::negative, L_one_x);
7177
7178 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7179 rorq(x_xstart, 32); // convert big-endian to little-endian
7180
7181 bind(L_first_loop);
7182 decrementl(idx);
7183 jcc(Assembler::negative, L_first_loop_exit);
7184 decrementl(idx);
7185 jcc(Assembler::negative, L_one_y);
7186 movq(y_idx, Address(y, idx, Address::times_4, 0));
7187 rorq(y_idx, 32); // convert big-endian to little-endian
7188 bind(L_multiply);
7189 movq(product, x_xstart);
7190 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7191 addq(product, carry);
7192 adcq(rdx, 0);
7193 subl(kdx, 2);
7194 movl(Address(z, kdx, Address::times_4, 4), product);
7195 shrq(product, 32);
7196 movl(Address(z, kdx, Address::times_4, 0), product);
7197 movq(carry, rdx);
7198 jmp(L_first_loop);
7199
7200 bind(L_one_y);
7201 movl(y_idx, Address(y, 0));
7202 jmp(L_multiply);
7203
7204 bind(L_one_x);
7205 movl(x_xstart, Address(x, 0));
7206 jmp(L_first_loop);
7207
7208 bind(L_first_loop_exit);
7209 }
7210
7211 /**
7212 * Multiply 64 bit by 64 bit and add 128 bit.
7213 */
7214 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7215 Register yz_idx, Register idx,
7216 Register carry, Register product, int offset) {
7217 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7218 // z[kdx] = (jlong)product;
7219
7220 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7221 rorq(yz_idx, 32); // convert big-endian to little-endian
7222 movq(product, x_xstart);
7223 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7224 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7225 rorq(yz_idx, 32); // convert big-endian to little-endian
7226
7227 add2_with_carry(rdx, product, carry, yz_idx);
7228
7229 movl(Address(z, idx, Address::times_4, offset+4), product);
7230 shrq(product, 32);
7231 movl(Address(z, idx, Address::times_4, offset), product);
7232
7233 }
7234
7235 /**
7236 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7237 */
7238 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7239 Register yz_idx, Register idx, Register jdx,
7240 Register carry, Register product,
7241 Register carry2) {
7242 // jlong carry, x[], y[], z[];
7243 // int kdx = ystart+1;
7244 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7245 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7246 // z[kdx+idx+1] = (jlong)product;
7247 // jlong carry2 = (jlong)(product >>> 64);
7248 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7249 // z[kdx+idx] = (jlong)product;
7250 // carry = (jlong)(product >>> 64);
7251 // }
7252 // idx += 2;
7253 // if (idx > 0) {
7254 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7255 // z[kdx+idx] = (jlong)product;
7256 // carry = (jlong)(product >>> 64);
7257 // }
7258 //
7259
7260 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7261
7262 movl(jdx, idx);
7263 andl(jdx, 0xFFFFFFFC);
7264 shrl(jdx, 2);
7265
7266 bind(L_third_loop);
7267 subl(jdx, 1);
7268 jcc(Assembler::negative, L_third_loop_exit);
7269 subl(idx, 4);
7270
7271 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7272 movq(carry2, rdx);
7273
7274 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7275 movq(carry, rdx);
7276 jmp(L_third_loop);
7277
7278 bind (L_third_loop_exit);
7279
7280 andl (idx, 0x3);
7281 jcc(Assembler::zero, L_post_third_loop_done);
7282
7283 Label L_check_1;
7284 subl(idx, 2);
7285 jcc(Assembler::negative, L_check_1);
7286
7287 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7288 movq(carry, rdx);
7289
7290 bind (L_check_1);
7291 addl (idx, 0x2);
7292 andl (idx, 0x1);
7293 subl(idx, 1);
7294 jcc(Assembler::negative, L_post_third_loop_done);
7295
7296 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7297 movq(product, x_xstart);
7298 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7299 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7300
7301 add2_with_carry(rdx, product, yz_idx, carry);
7302
7303 movl(Address(z, idx, Address::times_4, 0), product);
7304 shrq(product, 32);
7305
7306 shlq(rdx, 32);
7307 orq(product, rdx);
7308 movq(carry, product);
7309
7310 bind(L_post_third_loop_done);
7311 }
7312
7313 /**
7314 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7315 *
7316 */
7317 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7318 Register carry, Register carry2,
7319 Register idx, Register jdx,
7320 Register yz_idx1, Register yz_idx2,
7321 Register tmp, Register tmp3, Register tmp4) {
7322 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7323
7324 // jlong carry, x[], y[], z[];
7325 // int kdx = ystart+1;
7326 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7327 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7328 // jlong carry2 = (jlong)(tmp3 >>> 64);
7329 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7330 // carry = (jlong)(tmp4 >>> 64);
7331 // z[kdx+idx+1] = (jlong)tmp3;
7332 // z[kdx+idx] = (jlong)tmp4;
7333 // }
7334 // idx += 2;
7335 // if (idx > 0) {
7336 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7337 // z[kdx+idx] = (jlong)yz_idx1;
7338 // carry = (jlong)(yz_idx1 >>> 64);
7339 // }
7340 //
7341
7342 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7343
7344 movl(jdx, idx);
7345 andl(jdx, 0xFFFFFFFC);
7346 shrl(jdx, 2);
7347
7348 bind(L_third_loop);
7349 subl(jdx, 1);
7350 jcc(Assembler::negative, L_third_loop_exit);
7351 subl(idx, 4);
7352
7353 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7354 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7355 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7356 rorxq(yz_idx2, yz_idx2, 32);
7357
7358 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7359 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7360
7361 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7362 rorxq(yz_idx1, yz_idx1, 32);
7363 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7364 rorxq(yz_idx2, yz_idx2, 32);
7365
7366 if (VM_Version::supports_adx()) {
7367 adcxq(tmp3, carry);
7368 adoxq(tmp3, yz_idx1);
7369
7370 adcxq(tmp4, tmp);
7371 adoxq(tmp4, yz_idx2);
7372
7373 movl(carry, 0); // does not affect flags
7374 adcxq(carry2, carry);
7375 adoxq(carry2, carry);
7376 } else {
7377 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7378 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7379 }
7380 movq(carry, carry2);
7381
7382 movl(Address(z, idx, Address::times_4, 12), tmp3);
7383 shrq(tmp3, 32);
7384 movl(Address(z, idx, Address::times_4, 8), tmp3);
7385
7386 movl(Address(z, idx, Address::times_4, 4), tmp4);
7387 shrq(tmp4, 32);
7388 movl(Address(z, idx, Address::times_4, 0), tmp4);
7389
7390 jmp(L_third_loop);
7391
7392 bind (L_third_loop_exit);
7393
7394 andl (idx, 0x3);
7395 jcc(Assembler::zero, L_post_third_loop_done);
7396
7397 Label L_check_1;
7398 subl(idx, 2);
7399 jcc(Assembler::negative, L_check_1);
7400
7401 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7402 rorxq(yz_idx1, yz_idx1, 32);
7403 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7404 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7405 rorxq(yz_idx2, yz_idx2, 32);
7406
7407 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7408
7409 movl(Address(z, idx, Address::times_4, 4), tmp3);
7410 shrq(tmp3, 32);
7411 movl(Address(z, idx, Address::times_4, 0), tmp3);
7412 movq(carry, tmp4);
7413
7414 bind (L_check_1);
7415 addl (idx, 0x2);
7416 andl (idx, 0x1);
7417 subl(idx, 1);
7418 jcc(Assembler::negative, L_post_third_loop_done);
7419 movl(tmp4, Address(y, idx, Address::times_4, 0));
7420 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7421 movl(tmp4, Address(z, idx, Address::times_4, 0));
7422
7423 add2_with_carry(carry2, tmp3, tmp4, carry);
7424
7425 movl(Address(z, idx, Address::times_4, 0), tmp3);
7426 shrq(tmp3, 32);
7427
7428 shlq(carry2, 32);
7429 orq(tmp3, carry2);
7430 movq(carry, tmp3);
7431
7432 bind(L_post_third_loop_done);
7433 }
7434
7435 /**
7436 * Code for BigInteger::multiplyToLen() intrinsic.
7437 *
7438 * rdi: x
7439 * rax: xlen
7440 * rsi: y
7441 * rcx: ylen
7442 * r8: z
7443 * r11: tmp0
7444 * r12: tmp1
7445 * r13: tmp2
7446 * r14: tmp3
7447 * r15: tmp4
7448 * rbx: tmp5
7449 *
7450 */
7451 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7452 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7453 ShortBranchVerifier sbv(this);
7454 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7455
7456 push(tmp0);
7457 push(tmp1);
7458 push(tmp2);
7459 push(tmp3);
7460 push(tmp4);
7461 push(tmp5);
7462
7463 push(xlen);
7464
7465 const Register idx = tmp1;
7466 const Register kdx = tmp2;
7467 const Register xstart = tmp3;
7468
7469 const Register y_idx = tmp4;
7470 const Register carry = tmp5;
7471 const Register product = xlen;
7472 const Register x_xstart = tmp0;
7473
7474 // First Loop.
7475 //
7476 // final static long LONG_MASK = 0xffffffffL;
7477 // int xstart = xlen - 1;
7478 // int ystart = ylen - 1;
7479 // long carry = 0;
7480 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7481 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7482 // z[kdx] = (int)product;
7483 // carry = product >>> 32;
7484 // }
7485 // z[xstart] = (int)carry;
7486 //
7487
7488 movl(idx, ylen); // idx = ylen;
7489 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7490 xorq(carry, carry); // carry = 0;
7491
7492 Label L_done;
7493
7494 movl(xstart, xlen);
7495 decrementl(xstart);
7496 jcc(Assembler::negative, L_done);
7497
7498 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7499
7500 Label L_second_loop;
7501 testl(kdx, kdx);
7502 jcc(Assembler::zero, L_second_loop);
7503
7504 Label L_carry;
7505 subl(kdx, 1);
7506 jcc(Assembler::zero, L_carry);
7507
7508 movl(Address(z, kdx, Address::times_4, 0), carry);
7509 shrq(carry, 32);
7510 subl(kdx, 1);
7511
7512 bind(L_carry);
7513 movl(Address(z, kdx, Address::times_4, 0), carry);
7514
7515 // Second and third (nested) loops.
7516 //
7517 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7518 // carry = 0;
7519 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7520 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7521 // (z[k] & LONG_MASK) + carry;
7522 // z[k] = (int)product;
7523 // carry = product >>> 32;
7524 // }
7525 // z[i] = (int)carry;
7526 // }
7527 //
7528 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7529
7530 const Register jdx = tmp1;
7531
7532 bind(L_second_loop);
7533 xorl(carry, carry); // carry = 0;
7534 movl(jdx, ylen); // j = ystart+1
7535
7536 subl(xstart, 1); // i = xstart-1;
7537 jcc(Assembler::negative, L_done);
7538
7539 push (z);
7540
7541 Label L_last_x;
7542 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7543 subl(xstart, 1); // i = xstart-1;
7544 jcc(Assembler::negative, L_last_x);
7545
7546 if (UseBMI2Instructions) {
7547 movq(rdx, Address(x, xstart, Address::times_4, 0));
7548 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7549 } else {
7550 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7551 rorq(x_xstart, 32); // convert big-endian to little-endian
7552 }
7553
7554 Label L_third_loop_prologue;
7555 bind(L_third_loop_prologue);
7556
7557 push (x);
7558 push (xstart);
7559 push (ylen);
7560
7561
7562 if (UseBMI2Instructions) {
7563 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7564 } else { // !UseBMI2Instructions
7565 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7566 }
7567
7568 pop(ylen);
7569 pop(xlen);
7570 pop(x);
7571 pop(z);
7572
7573 movl(tmp3, xlen);
7574 addl(tmp3, 1);
7575 movl(Address(z, tmp3, Address::times_4, 0), carry);
7576 subl(tmp3, 1);
7577 jccb(Assembler::negative, L_done);
7578
7579 shrq(carry, 32);
7580 movl(Address(z, tmp3, Address::times_4, 0), carry);
7581 jmp(L_second_loop);
7582
7583 // Next infrequent code is moved outside loops.
7584 bind(L_last_x);
7585 if (UseBMI2Instructions) {
7586 movl(rdx, Address(x, 0));
7587 } else {
7588 movl(x_xstart, Address(x, 0));
7589 }
7590 jmp(L_third_loop_prologue);
7591
7592 bind(L_done);
7593
7594 pop(xlen);
7595
7596 pop(tmp5);
7597 pop(tmp4);
7598 pop(tmp3);
7599 pop(tmp2);
7600 pop(tmp1);
7601 pop(tmp0);
7602 }
7603
7604 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7605 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7606 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7607 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7608 Label VECTOR8_TAIL, VECTOR4_TAIL;
7609 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7610 Label SAME_TILL_END, DONE;
7611 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7612
7613 //scale is in rcx in both Win64 and Unix
7614 ShortBranchVerifier sbv(this);
7615
7616 shlq(length);
7617 xorq(result, result);
7618
7619 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7620 VM_Version::supports_avx512vlbw() && UseCountTrailingZerosInstruction) {
7621 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7622
7623 cmpq(length, 64);
7624 jcc(Assembler::less, VECTOR32_TAIL);
7625
7626 movq(tmp1, length);
7627 andq(tmp1, 0x3F); // tail count
7628 andq(length, ~(0x3F)); //vector count
7629
7630 bind(VECTOR64_LOOP);
7631 // AVX512 code to compare 64 byte vectors.
7632 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7633 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7634 kortestql(k7, k7);
7635 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7636 addq(result, 64);
7637 subq(length, 64);
7638 jccb(Assembler::notZero, VECTOR64_LOOP);
7639
7640 //bind(VECTOR64_TAIL);
7641 testq(tmp1, tmp1);
7642 jcc(Assembler::zero, SAME_TILL_END);
7643
7644 //bind(VECTOR64_TAIL);
7645 // AVX512 code to compare up to 63 byte vectors.
7646 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7647 shlxq(tmp2, tmp2, tmp1);
7648 notq(tmp2);
7649 kmovql(k3, tmp2);
7650
7651 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7652 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7653
7654 ktestql(k7, k3);
7655 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7656
7657 bind(VECTOR64_NOT_EQUAL);
7658 kmovql(tmp1, k7);
7659 notq(tmp1);
7660 tzcntq(tmp1, tmp1);
7661 addq(result, tmp1);
7662 shrq(result);
7663 jmp(DONE);
7664 bind(VECTOR32_TAIL);
7665 }
7666
7667 cmpq(length, 8);
7668 jcc(Assembler::equal, VECTOR8_LOOP);
7669 jcc(Assembler::less, VECTOR4_TAIL);
7670
7671 if (UseAVX >= 2) {
7672 Label VECTOR16_TAIL, VECTOR32_LOOP;
7673
7674 cmpq(length, 16);
7675 jcc(Assembler::equal, VECTOR16_LOOP);
7676 jcc(Assembler::less, VECTOR8_LOOP);
7677
7678 cmpq(length, 32);
7679 jccb(Assembler::less, VECTOR16_TAIL);
7680
7681 subq(length, 32);
7682 bind(VECTOR32_LOOP);
7683 vmovdqu(rymm0, Address(obja, result));
7684 vmovdqu(rymm1, Address(objb, result));
7685 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7686 vptest(rymm2, rymm2);
7687 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7688 addq(result, 32);
7689 subq(length, 32);
7690 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7691 addq(length, 32);
7692 jcc(Assembler::equal, SAME_TILL_END);
7693 //falling through if less than 32 bytes left //close the branch here.
7694
7695 bind(VECTOR16_TAIL);
7696 cmpq(length, 16);
7697 jccb(Assembler::less, VECTOR8_TAIL);
7698 bind(VECTOR16_LOOP);
7699 movdqu(rymm0, Address(obja, result));
7700 movdqu(rymm1, Address(objb, result));
7701 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7702 ptest(rymm2, rymm2);
7703 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7704 addq(result, 16);
7705 subq(length, 16);
7706 jcc(Assembler::equal, SAME_TILL_END);
7707 //falling through if less than 16 bytes left
7708 } else {//regular intrinsics
7709
7710 cmpq(length, 16);
7711 jccb(Assembler::less, VECTOR8_TAIL);
7712
7713 subq(length, 16);
7714 bind(VECTOR16_LOOP);
7715 movdqu(rymm0, Address(obja, result));
7716 movdqu(rymm1, Address(objb, result));
7717 pxor(rymm0, rymm1);
7718 ptest(rymm0, rymm0);
7719 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7720 addq(result, 16);
7721 subq(length, 16);
7722 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7723 addq(length, 16);
7724 jcc(Assembler::equal, SAME_TILL_END);
7725 //falling through if less than 16 bytes left
7726 }
7727
7728 bind(VECTOR8_TAIL);
7729 cmpq(length, 8);
7730 jccb(Assembler::less, VECTOR4_TAIL);
7731 bind(VECTOR8_LOOP);
7732 movq(tmp1, Address(obja, result));
7733 movq(tmp2, Address(objb, result));
7734 xorq(tmp1, tmp2);
7735 testq(tmp1, tmp1);
7736 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7737 addq(result, 8);
7738 subq(length, 8);
7739 jcc(Assembler::equal, SAME_TILL_END);
7740 //falling through if less than 8 bytes left
7741
7742 bind(VECTOR4_TAIL);
7743 cmpq(length, 4);
7744 jccb(Assembler::less, BYTES_TAIL);
7745 bind(VECTOR4_LOOP);
7746 movl(tmp1, Address(obja, result));
7747 xorl(tmp1, Address(objb, result));
7748 testl(tmp1, tmp1);
7749 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7750 addq(result, 4);
7751 subq(length, 4);
7752 jcc(Assembler::equal, SAME_TILL_END);
7753 //falling through if less than 4 bytes left
7754
7755 bind(BYTES_TAIL);
7756 bind(BYTES_LOOP);
7757 load_unsigned_byte(tmp1, Address(obja, result));
7758 load_unsigned_byte(tmp2, Address(objb, result));
7759 xorl(tmp1, tmp2);
7760 testl(tmp1, tmp1);
7761 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7762 decq(length);
7763 jcc(Assembler::zero, SAME_TILL_END);
7764 incq(result);
7765 load_unsigned_byte(tmp1, Address(obja, result));
7766 load_unsigned_byte(tmp2, Address(objb, result));
7767 xorl(tmp1, tmp2);
7768 testl(tmp1, tmp1);
7769 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7770 decq(length);
7771 jcc(Assembler::zero, SAME_TILL_END);
7772 incq(result);
7773 load_unsigned_byte(tmp1, Address(obja, result));
7774 load_unsigned_byte(tmp2, Address(objb, result));
7775 xorl(tmp1, tmp2);
7776 testl(tmp1, tmp1);
7777 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7778 jmp(SAME_TILL_END);
7779
7780 if (UseAVX >= 2) {
7781 bind(VECTOR32_NOT_EQUAL);
7782 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7783 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7784 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7785 vpmovmskb(tmp1, rymm0);
7786 bsfq(tmp1, tmp1);
7787 addq(result, tmp1);
7788 shrq(result);
7789 jmp(DONE);
7790 }
7791
7792 bind(VECTOR16_NOT_EQUAL);
7793 if (UseAVX >= 2) {
7794 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7795 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7796 pxor(rymm0, rymm2);
7797 } else {
7798 pcmpeqb(rymm2, rymm2);
7799 pxor(rymm0, rymm1);
7800 pcmpeqb(rymm0, rymm1);
7801 pxor(rymm0, rymm2);
7802 }
7803 pmovmskb(tmp1, rymm0);
7804 bsfq(tmp1, tmp1);
7805 addq(result, tmp1);
7806 shrq(result);
7807 jmpb(DONE);
7808
7809 bind(VECTOR8_NOT_EQUAL);
7810 bind(VECTOR4_NOT_EQUAL);
7811 bsfq(tmp1, tmp1);
7812 shrq(tmp1, 3);
7813 addq(result, tmp1);
7814 bind(BYTES_NOT_EQUAL);
7815 shrq(result);
7816 jmpb(DONE);
7817
7818 bind(SAME_TILL_END);
7819 mov64(result, -1);
7820
7821 bind(DONE);
7822 }
7823
7824 //Helper functions for square_to_len()
7825
7826 /**
7827 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7828 * Preserves x and z and modifies rest of the registers.
7829 */
7830 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7831 // Perform square and right shift by 1
7832 // Handle odd xlen case first, then for even xlen do the following
7833 // jlong carry = 0;
7834 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7835 // huge_128 product = x[j:j+1] * x[j:j+1];
7836 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7837 // z[i+2:i+3] = (jlong)(product >>> 1);
7838 // carry = (jlong)product;
7839 // }
7840
7841 xorq(tmp5, tmp5); // carry
7842 xorq(rdxReg, rdxReg);
7843 xorl(tmp1, tmp1); // index for x
7844 xorl(tmp4, tmp4); // index for z
7845
7846 Label L_first_loop, L_first_loop_exit;
7847
7848 testl(xlen, 1);
7849 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7850
7851 // Square and right shift by 1 the odd element using 32 bit multiply
7852 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7853 imulq(raxReg, raxReg);
7854 shrq(raxReg, 1);
7855 adcq(tmp5, 0);
7856 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7857 incrementl(tmp1);
7858 addl(tmp4, 2);
7859
7860 // Square and right shift by 1 the rest using 64 bit multiply
7861 bind(L_first_loop);
7862 cmpptr(tmp1, xlen);
7863 jccb(Assembler::equal, L_first_loop_exit);
7864
7865 // Square
7866 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7867 rorq(raxReg, 32); // convert big-endian to little-endian
7868 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7869
7870 // Right shift by 1 and save carry
7871 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7872 rcrq(rdxReg, 1);
7873 rcrq(raxReg, 1);
7874 adcq(tmp5, 0);
7875
7876 // Store result in z
7877 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7878 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7879
7880 // Update indices for x and z
7881 addl(tmp1, 2);
7882 addl(tmp4, 4);
7883 jmp(L_first_loop);
7884
7885 bind(L_first_loop_exit);
7886 }
7887
7888
7889 /**
7890 * Perform the following multiply add operation using BMI2 instructions
7891 * carry:sum = sum + op1*op2 + carry
7892 * op2 should be in rdx
7893 * op2 is preserved, all other registers are modified
7894 */
7895 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7896 // assert op2 is rdx
7897 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7898 addq(sum, carry);
7899 adcq(tmp2, 0);
7900 addq(sum, op1);
7901 adcq(tmp2, 0);
7902 movq(carry, tmp2);
7903 }
7904
7905 /**
7906 * Perform the following multiply add operation:
7907 * carry:sum = sum + op1*op2 + carry
7908 * Preserves op1, op2 and modifies rest of registers
7909 */
7910 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7911 // rdx:rax = op1 * op2
7912 movq(raxReg, op2);
7913 mulq(op1);
7914
7915 // rdx:rax = sum + carry + rdx:rax
7916 addq(sum, carry);
7917 adcq(rdxReg, 0);
7918 addq(sum, raxReg);
7919 adcq(rdxReg, 0);
7920
7921 // carry:sum = rdx:sum
7922 movq(carry, rdxReg);
7923 }
7924
7925 /**
7926 * Add 64 bit long carry into z[] with carry propagation.
7927 * Preserves z and carry register values and modifies rest of registers.
7928 *
7929 */
7930 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7931 Label L_fourth_loop, L_fourth_loop_exit;
7932
7933 movl(tmp1, 1);
7934 subl(zlen, 2);
7935 addq(Address(z, zlen, Address::times_4, 0), carry);
7936
7937 bind(L_fourth_loop);
7938 jccb(Assembler::carryClear, L_fourth_loop_exit);
7939 subl(zlen, 2);
7940 jccb(Assembler::negative, L_fourth_loop_exit);
7941 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7942 jmp(L_fourth_loop);
7943 bind(L_fourth_loop_exit);
7944 }
7945
7946 /**
7947 * Shift z[] left by 1 bit.
7948 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7949 *
7950 */
7951 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7952
7953 Label L_fifth_loop, L_fifth_loop_exit;
7954
7955 // Fifth loop
7956 // Perform primitiveLeftShift(z, zlen, 1)
7957
7958 const Register prev_carry = tmp1;
7959 const Register new_carry = tmp4;
7960 const Register value = tmp2;
7961 const Register zidx = tmp3;
7962
7963 // int zidx, carry;
7964 // long value;
7965 // carry = 0;
7966 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7967 // (carry:value) = (z[i] << 1) | carry ;
7968 // z[i] = value;
7969 // }
7970
7971 movl(zidx, zlen);
7972 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7973
7974 bind(L_fifth_loop);
7975 decl(zidx); // Use decl to preserve carry flag
7976 decl(zidx);
7977 jccb(Assembler::negative, L_fifth_loop_exit);
7978
7979 if (UseBMI2Instructions) {
7980 movq(value, Address(z, zidx, Address::times_4, 0));
7981 rclq(value, 1);
7982 rorxq(value, value, 32);
7983 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7984 }
7985 else {
7986 // clear new_carry
7987 xorl(new_carry, new_carry);
7988
7989 // Shift z[i] by 1, or in previous carry and save new carry
7990 movq(value, Address(z, zidx, Address::times_4, 0));
7991 shlq(value, 1);
7992 adcl(new_carry, 0);
7993
7994 orq(value, prev_carry);
7995 rorq(value, 0x20);
7996 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7997
7998 // Set previous carry = new carry
7999 movl(prev_carry, new_carry);
8000 }
8001 jmp(L_fifth_loop);
8002
8003 bind(L_fifth_loop_exit);
8004 }
8005
8006
8007 /**
8008 * Code for BigInteger::squareToLen() intrinsic
8009 *
8010 * rdi: x
8011 * rsi: len
8012 * r8: z
8013 * rcx: zlen
8014 * r12: tmp1
8015 * r13: tmp2
8016 * r14: tmp3
8017 * r15: tmp4
8018 * rbx: tmp5
8019 *
8020 */
8021 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8022
8023 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8024 push(tmp1);
8025 push(tmp2);
8026 push(tmp3);
8027 push(tmp4);
8028 push(tmp5);
8029
8030 // First loop
8031 // Store the squares, right shifted one bit (i.e., divided by 2).
8032 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8033
8034 // Add in off-diagonal sums.
8035 //
8036 // Second, third (nested) and fourth loops.
8037 // zlen +=2;
8038 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8039 // carry = 0;
8040 // long op2 = x[xidx:xidx+1];
8041 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8042 // k -= 2;
8043 // long op1 = x[j:j+1];
8044 // long sum = z[k:k+1];
8045 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8046 // z[k:k+1] = sum;
8047 // }
8048 // add_one_64(z, k, carry, tmp_regs);
8049 // }
8050
8051 const Register carry = tmp5;
8052 const Register sum = tmp3;
8053 const Register op1 = tmp4;
8054 Register op2 = tmp2;
8055
8056 push(zlen);
8057 push(len);
8058 addl(zlen,2);
8059 bind(L_second_loop);
8060 xorq(carry, carry);
8061 subl(zlen, 4);
8062 subl(len, 2);
8063 push(zlen);
8064 push(len);
8065 cmpl(len, 0);
8066 jccb(Assembler::lessEqual, L_second_loop_exit);
8067
8068 // Multiply an array by one 64 bit long.
8069 if (UseBMI2Instructions) {
8070 op2 = rdxReg;
8071 movq(op2, Address(x, len, Address::times_4, 0));
8072 rorxq(op2, op2, 32);
8073 }
8074 else {
8075 movq(op2, Address(x, len, Address::times_4, 0));
8076 rorq(op2, 32);
8077 }
8078
8079 bind(L_third_loop);
8080 decrementl(len);
8081 jccb(Assembler::negative, L_third_loop_exit);
8082 decrementl(len);
8083 jccb(Assembler::negative, L_last_x);
8084
8085 movq(op1, Address(x, len, Address::times_4, 0));
8086 rorq(op1, 32);
8087
8088 bind(L_multiply);
8089 subl(zlen, 2);
8090 movq(sum, Address(z, zlen, Address::times_4, 0));
8091
8092 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8093 if (UseBMI2Instructions) {
8094 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8095 }
8096 else {
8097 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8098 }
8099
8100 movq(Address(z, zlen, Address::times_4, 0), sum);
8101
8102 jmp(L_third_loop);
8103 bind(L_third_loop_exit);
8104
8105 // Fourth loop
8106 // Add 64 bit long carry into z with carry propagation.
8107 // Uses offsetted zlen.
8108 add_one_64(z, zlen, carry, tmp1);
8109
8110 pop(len);
8111 pop(zlen);
8112 jmp(L_second_loop);
8113
8114 // Next infrequent code is moved outside loops.
8115 bind(L_last_x);
8116 movl(op1, Address(x, 0));
8117 jmp(L_multiply);
8118
8119 bind(L_second_loop_exit);
8120 pop(len);
8121 pop(zlen);
8122 pop(len);
8123 pop(zlen);
8124
8125 // Fifth loop
8126 // Shift z left 1 bit.
8127 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8128
8129 // z[zlen-1] |= x[len-1] & 1;
8130 movl(tmp3, Address(x, len, Address::times_4, -4));
8131 andl(tmp3, 1);
8132 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8133
8134 pop(tmp5);
8135 pop(tmp4);
8136 pop(tmp3);
8137 pop(tmp2);
8138 pop(tmp1);
8139 }
8140
8141 /**
8142 * Helper function for mul_add()
8143 * Multiply the in[] by int k and add to out[] starting at offset offs using
8144 * 128 bit by 32 bit multiply and return the carry in tmp5.
8145 * Only quad int aligned length of in[] is operated on in this function.
8146 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8147 * This function preserves out, in and k registers.
8148 * len and offset point to the appropriate index in "in" & "out" correspondingly
8149 * tmp5 has the carry.
8150 * other registers are temporary and are modified.
8151 *
8152 */
8153 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8154 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8155 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8156
8157 Label L_first_loop, L_first_loop_exit;
8158
8159 movl(tmp1, len);
8160 shrl(tmp1, 2);
8161
8162 bind(L_first_loop);
8163 subl(tmp1, 1);
8164 jccb(Assembler::negative, L_first_loop_exit);
8165
8166 subl(len, 4);
8167 subl(offset, 4);
8168
8169 Register op2 = tmp2;
8170 const Register sum = tmp3;
8171 const Register op1 = tmp4;
8172 const Register carry = tmp5;
8173
8174 if (UseBMI2Instructions) {
8175 op2 = rdxReg;
8176 }
8177
8178 movq(op1, Address(in, len, Address::times_4, 8));
8179 rorq(op1, 32);
8180 movq(sum, Address(out, offset, Address::times_4, 8));
8181 rorq(sum, 32);
8182 if (UseBMI2Instructions) {
8183 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8184 }
8185 else {
8186 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8187 }
8188 // Store back in big endian from little endian
8189 rorq(sum, 0x20);
8190 movq(Address(out, offset, Address::times_4, 8), sum);
8191
8192 movq(op1, Address(in, len, Address::times_4, 0));
8193 rorq(op1, 32);
8194 movq(sum, Address(out, offset, Address::times_4, 0));
8195 rorq(sum, 32);
8196 if (UseBMI2Instructions) {
8197 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8198 }
8199 else {
8200 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8201 }
8202 // Store back in big endian from little endian
8203 rorq(sum, 0x20);
8204 movq(Address(out, offset, Address::times_4, 0), sum);
8205
8206 jmp(L_first_loop);
8207 bind(L_first_loop_exit);
8208 }
8209
8210 /**
8211 * Code for BigInteger::mulAdd() intrinsic
8212 *
8213 * rdi: out
8214 * rsi: in
8215 * r11: offs (out.length - offset)
8216 * rcx: len
8217 * r8: k
8218 * r12: tmp1
8219 * r13: tmp2
8220 * r14: tmp3
8221 * r15: tmp4
8222 * rbx: tmp5
8223 * Multiply the in[] by word k and add to out[], return the carry in rax
8224 */
8225 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8226 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8227 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8228
8229 Label L_carry, L_last_in, L_done;
8230
8231 // carry = 0;
8232 // for (int j=len-1; j >= 0; j--) {
8233 // long product = (in[j] & LONG_MASK) * kLong +
8234 // (out[offs] & LONG_MASK) + carry;
8235 // out[offs--] = (int)product;
8236 // carry = product >>> 32;
8237 // }
8238 //
8239 push(tmp1);
8240 push(tmp2);
8241 push(tmp3);
8242 push(tmp4);
8243 push(tmp5);
8244
8245 Register op2 = tmp2;
8246 const Register sum = tmp3;
8247 const Register op1 = tmp4;
8248 const Register carry = tmp5;
8249
8250 if (UseBMI2Instructions) {
8251 op2 = rdxReg;
8252 movl(op2, k);
8253 }
8254 else {
8255 movl(op2, k);
8256 }
8257
8258 xorq(carry, carry);
8259
8260 //First loop
8261
8262 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8263 //The carry is in tmp5
8264 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8265
8266 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8267 decrementl(len);
8268 jccb(Assembler::negative, L_carry);
8269 decrementl(len);
8270 jccb(Assembler::negative, L_last_in);
8271
8272 movq(op1, Address(in, len, Address::times_4, 0));
8273 rorq(op1, 32);
8274
8275 subl(offs, 2);
8276 movq(sum, Address(out, offs, Address::times_4, 0));
8277 rorq(sum, 32);
8278
8279 if (UseBMI2Instructions) {
8280 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8281 }
8282 else {
8283 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8284 }
8285
8286 // Store back in big endian from little endian
8287 rorq(sum, 0x20);
8288 movq(Address(out, offs, Address::times_4, 0), sum);
8289
8290 testl(len, len);
8291 jccb(Assembler::zero, L_carry);
8292
8293 //Multiply the last in[] entry, if any
8294 bind(L_last_in);
8295 movl(op1, Address(in, 0));
8296 movl(sum, Address(out, offs, Address::times_4, -4));
8297
8298 movl(raxReg, k);
8299 mull(op1); //tmp4 * eax -> edx:eax
8300 addl(sum, carry);
8301 adcl(rdxReg, 0);
8302 addl(sum, raxReg);
8303 adcl(rdxReg, 0);
8304 movl(carry, rdxReg);
8305
8306 movl(Address(out, offs, Address::times_4, -4), sum);
8307
8308 bind(L_carry);
8309 //return tmp5/carry as carry in rax
8310 movl(rax, carry);
8311
8312 bind(L_done);
8313 pop(tmp5);
8314 pop(tmp4);
8315 pop(tmp3);
8316 pop(tmp2);
8317 pop(tmp1);
8318 }
8319
8320 /**
8321 * Emits code to update CRC-32 with a byte value according to constants in table
8322 *
8323 * @param [in,out]crc Register containing the crc.
8324 * @param [in]val Register containing the byte to fold into the CRC.
8325 * @param [in]table Register containing the table of crc constants.
8326 *
8327 * uint32_t crc;
8328 * val = crc_table[(val ^ crc) & 0xFF];
8329 * crc = val ^ (crc >> 8);
8330 *
8331 */
8332 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8333 xorl(val, crc);
8334 andl(val, 0xFF);
8335 shrl(crc, 8); // unsigned shift
8336 xorl(crc, Address(table, val, Address::times_4, 0));
8337 }
8338
8339 /**
8340 * Fold 128-bit data chunk
8341 */
8342 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8343 if (UseAVX > 0) {
8344 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8345 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8346 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8347 pxor(xcrc, xtmp);
8348 } else {
8349 movdqa(xtmp, xcrc);
8350 pclmulhdq(xtmp, xK); // [123:64]
8351 pclmulldq(xcrc, xK); // [63:0]
8352 pxor(xcrc, xtmp);
8353 movdqu(xtmp, Address(buf, offset));
8354 pxor(xcrc, xtmp);
8355 }
8356 }
8357
8358 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8359 if (UseAVX > 0) {
8360 vpclmulhdq(xtmp, xK, xcrc);
8361 vpclmulldq(xcrc, xK, xcrc);
8362 pxor(xcrc, xbuf);
8363 pxor(xcrc, xtmp);
8364 } else {
8365 movdqa(xtmp, xcrc);
8366 pclmulhdq(xtmp, xK);
8367 pclmulldq(xcrc, xK);
8368 pxor(xcrc, xbuf);
8369 pxor(xcrc, xtmp);
8370 }
8371 }
8372
8373 /**
8374 * 8-bit folds to compute 32-bit CRC
8375 *
8376 * uint64_t xcrc;
8377 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8378 */
8379 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8380 movdl(tmp, xcrc);
8381 andl(tmp, 0xFF);
8382 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8383 psrldq(xcrc, 1); // unsigned shift one byte
8384 pxor(xcrc, xtmp);
8385 }
8386
8387 /**
8388 * uint32_t crc;
8389 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8390 */
8391 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8392 movl(tmp, crc);
8393 andl(tmp, 0xFF);
8394 shrl(crc, 8);
8395 xorl(crc, Address(table, tmp, Address::times_4, 0));
8396 }
8397
8398 /**
8399 * @param crc register containing existing CRC (32-bit)
8400 * @param buf register pointing to input byte buffer (byte*)
8401 * @param len register containing number of bytes
8402 * @param table register that will contain address of CRC table
8403 * @param tmp scratch register
8404 */
8405 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8406 assert_different_registers(crc, buf, len, table, tmp, rax);
8407
8408 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8409 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8410
8411 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8412 // context for the registers used, where all instructions below are using 128-bit mode
8413 // On EVEX without VL and BW, these instructions will all be AVX.
8414 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8415 notl(crc); // ~crc
8416 cmpl(len, 16);
8417 jcc(Assembler::less, L_tail);
8418
8419 // Align buffer to 16 bytes
8420 movl(tmp, buf);
8421 andl(tmp, 0xF);
8422 jccb(Assembler::zero, L_aligned);
8423 subl(tmp, 16);
8424 addl(len, tmp);
8425
8426 align(4);
8427 BIND(L_align_loop);
8428 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8429 update_byte_crc32(crc, rax, table);
8430 increment(buf);
8431 incrementl(tmp);
8432 jccb(Assembler::less, L_align_loop);
8433
8434 BIND(L_aligned);
8435 movl(tmp, len); // save
8436 shrl(len, 4);
8437 jcc(Assembler::zero, L_tail_restore);
8438
8439 // Fold crc into first bytes of vector
8440 movdqa(xmm1, Address(buf, 0));
8441 movdl(rax, xmm1);
8442 xorl(crc, rax);
8443 if (VM_Version::supports_sse4_1()) {
8444 pinsrd(xmm1, crc, 0);
8445 } else {
8446 pinsrw(xmm1, crc, 0);
8447 shrl(crc, 16);
8448 pinsrw(xmm1, crc, 1);
8449 }
8450 addptr(buf, 16);
8451 subl(len, 4); // len > 0
8452 jcc(Assembler::less, L_fold_tail);
8453
8454 movdqa(xmm2, Address(buf, 0));
8455 movdqa(xmm3, Address(buf, 16));
8456 movdqa(xmm4, Address(buf, 32));
8457 addptr(buf, 48);
8458 subl(len, 3);
8459 jcc(Assembler::lessEqual, L_fold_512b);
8460
8461 // Fold total 512 bits of polynomial on each iteration,
8462 // 128 bits per each of 4 parallel streams.
8463 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8464
8465 align32();
8466 BIND(L_fold_512b_loop);
8467 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8468 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8469 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8470 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8471 addptr(buf, 64);
8472 subl(len, 4);
8473 jcc(Assembler::greater, L_fold_512b_loop);
8474
8475 // Fold 512 bits to 128 bits.
8476 BIND(L_fold_512b);
8477 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8478 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8479 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8480 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8481
8482 // Fold the rest of 128 bits data chunks
8483 BIND(L_fold_tail);
8484 addl(len, 3);
8485 jccb(Assembler::lessEqual, L_fold_128b);
8486 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8487
8488 BIND(L_fold_tail_loop);
8489 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8490 addptr(buf, 16);
8491 decrementl(len);
8492 jccb(Assembler::greater, L_fold_tail_loop);
8493
8494 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8495 BIND(L_fold_128b);
8496 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8497 if (UseAVX > 0) {
8498 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8499 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8500 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8501 } else {
8502 movdqa(xmm2, xmm0);
8503 pclmulqdq(xmm2, xmm1, 0x1);
8504 movdqa(xmm3, xmm0);
8505 pand(xmm3, xmm2);
8506 pclmulqdq(xmm0, xmm3, 0x1);
8507 }
8508 psrldq(xmm1, 8);
8509 psrldq(xmm2, 4);
8510 pxor(xmm0, xmm1);
8511 pxor(xmm0, xmm2);
8512
8513 // 8 8-bit folds to compute 32-bit CRC.
8514 for (int j = 0; j < 4; j++) {
8515 fold_8bit_crc32(xmm0, table, xmm1, rax);
8516 }
8517 movdl(crc, xmm0); // mov 32 bits to general register
8518 for (int j = 0; j < 4; j++) {
8519 fold_8bit_crc32(crc, table, rax);
8520 }
8521
8522 BIND(L_tail_restore);
8523 movl(len, tmp); // restore
8524 BIND(L_tail);
8525 andl(len, 0xf);
8526 jccb(Assembler::zero, L_exit);
8527
8528 // Fold the rest of bytes
8529 align(4);
8530 BIND(L_tail_loop);
8531 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8532 update_byte_crc32(crc, rax, table);
8533 increment(buf);
8534 decrementl(len);
8535 jccb(Assembler::greater, L_tail_loop);
8536
8537 BIND(L_exit);
8538 notl(crc); // ~c
8539 }
8540
8541 // Helper function for AVX 512 CRC32
8542 // Fold 512-bit data chunks
8543 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8544 Register pos, int offset) {
8545 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8546 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8547 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8548 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8549 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8550 }
8551
8552 // Helper function for AVX 512 CRC32
8553 // Compute CRC32 for < 256B buffers
8554 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8555 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8556 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8557
8558 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8559 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8560 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8561
8562 // check if there is enough buffer to be able to fold 16B at a time
8563 cmpl(len, 32);
8564 jcc(Assembler::less, L_less_than_32);
8565
8566 // if there is, load the constants
8567 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8568 movdl(xmm0, crc); // get the initial crc value
8569 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8570 pxor(xmm7, xmm0);
8571
8572 // update the buffer pointer
8573 addl(pos, 16);
8574 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8575 subl(len, 32);
8576 jmp(L_16B_reduction_loop);
8577
8578 bind(L_less_than_32);
8579 //mov initial crc to the return value. this is necessary for zero - length buffers.
8580 movl(rax, crc);
8581 testl(len, len);
8582 jcc(Assembler::equal, L_cleanup);
8583
8584 movdl(xmm0, crc); //get the initial crc value
8585
8586 cmpl(len, 16);
8587 jcc(Assembler::equal, L_exact_16_left);
8588 jcc(Assembler::less, L_less_than_16_left);
8589
8590 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8591 pxor(xmm7, xmm0); //xor the initial crc value
8592 addl(pos, 16);
8593 subl(len, 16);
8594 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8595 jmp(L_get_last_two_xmms);
8596
8597 bind(L_less_than_16_left);
8598 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8599 pxor(xmm1, xmm1);
8600 movptr(tmp1, rsp);
8601 movdqu(Address(tmp1, 0 * 16), xmm1);
8602
8603 cmpl(len, 4);
8604 jcc(Assembler::less, L_only_less_than_4);
8605
8606 //backup the counter value
8607 movl(tmp2, len);
8608 cmpl(len, 8);
8609 jcc(Assembler::less, L_less_than_8_left);
8610
8611 //load 8 Bytes
8612 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8613 movq(Address(tmp1, 0 * 16), rax);
8614 addptr(tmp1, 8);
8615 subl(len, 8);
8616 addl(pos, 8);
8617
8618 bind(L_less_than_8_left);
8619 cmpl(len, 4);
8620 jcc(Assembler::less, L_less_than_4_left);
8621
8622 //load 4 Bytes
8623 movl(rax, Address(buf, pos, Address::times_1, 0));
8624 movl(Address(tmp1, 0 * 16), rax);
8625 addptr(tmp1, 4);
8626 subl(len, 4);
8627 addl(pos, 4);
8628
8629 bind(L_less_than_4_left);
8630 cmpl(len, 2);
8631 jcc(Assembler::less, L_less_than_2_left);
8632
8633 // load 2 Bytes
8634 movw(rax, Address(buf, pos, Address::times_1, 0));
8635 movl(Address(tmp1, 0 * 16), rax);
8636 addptr(tmp1, 2);
8637 subl(len, 2);
8638 addl(pos, 2);
8639
8640 bind(L_less_than_2_left);
8641 cmpl(len, 1);
8642 jcc(Assembler::less, L_zero_left);
8643
8644 // load 1 Byte
8645 movb(rax, Address(buf, pos, Address::times_1, 0));
8646 movb(Address(tmp1, 0 * 16), rax);
8647
8648 bind(L_zero_left);
8649 movdqu(xmm7, Address(rsp, 0));
8650 pxor(xmm7, xmm0); //xor the initial crc value
8651
8652 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8653 movdqu(xmm0, Address(rax, tmp2));
8654 pshufb(xmm7, xmm0);
8655 jmp(L_128_done);
8656
8657 bind(L_exact_16_left);
8658 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8659 pxor(xmm7, xmm0); //xor the initial crc value
8660 jmp(L_128_done);
8661
8662 bind(L_only_less_than_4);
8663 cmpl(len, 3);
8664 jcc(Assembler::less, L_only_less_than_3);
8665
8666 // load 3 Bytes
8667 movb(rax, Address(buf, pos, Address::times_1, 0));
8668 movb(Address(tmp1, 0), rax);
8669
8670 movb(rax, Address(buf, pos, Address::times_1, 1));
8671 movb(Address(tmp1, 1), rax);
8672
8673 movb(rax, Address(buf, pos, Address::times_1, 2));
8674 movb(Address(tmp1, 2), rax);
8675
8676 movdqu(xmm7, Address(rsp, 0));
8677 pxor(xmm7, xmm0); //xor the initial crc value
8678
8679 pslldq(xmm7, 0x5);
8680 jmp(L_barrett);
8681 bind(L_only_less_than_3);
8682 cmpl(len, 2);
8683 jcc(Assembler::less, L_only_less_than_2);
8684
8685 // load 2 Bytes
8686 movb(rax, Address(buf, pos, Address::times_1, 0));
8687 movb(Address(tmp1, 0), rax);
8688
8689 movb(rax, Address(buf, pos, Address::times_1, 1));
8690 movb(Address(tmp1, 1), rax);
8691
8692 movdqu(xmm7, Address(rsp, 0));
8693 pxor(xmm7, xmm0); //xor the initial crc value
8694
8695 pslldq(xmm7, 0x6);
8696 jmp(L_barrett);
8697
8698 bind(L_only_less_than_2);
8699 //load 1 Byte
8700 movb(rax, Address(buf, pos, Address::times_1, 0));
8701 movb(Address(tmp1, 0), rax);
8702
8703 movdqu(xmm7, Address(rsp, 0));
8704 pxor(xmm7, xmm0); //xor the initial crc value
8705
8706 pslldq(xmm7, 0x7);
8707 }
8708
8709 /**
8710 * Compute CRC32 using AVX512 instructions
8711 * param crc register containing existing CRC (32-bit)
8712 * param buf register pointing to input byte buffer (byte*)
8713 * param len register containing number of bytes
8714 * param table address of crc or crc32c table
8715 * param tmp1 scratch register
8716 * param tmp2 scratch register
8717 * return rax result register
8718 *
8719 * This routine is identical for crc32c with the exception of the precomputed constant
8720 * table which will be passed as the table argument. The calculation steps are
8721 * the same for both variants.
8722 */
8723 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8724 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8725
8726 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8727 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8728 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8729 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8730 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8731
8732 const Register pos = r12;
8733 push(r12);
8734 subptr(rsp, 16 * 2 + 8);
8735
8736 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8737 // context for the registers used, where all instructions below are using 128-bit mode
8738 // On EVEX without VL and BW, these instructions will all be AVX.
8739 movl(pos, 0);
8740
8741 // check if smaller than 256B
8742 cmpl(len, 256);
8743 jcc(Assembler::less, L_less_than_256);
8744
8745 // load the initial crc value
8746 movdl(xmm10, crc);
8747
8748 // receive the initial 64B data, xor the initial crc value
8749 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8750 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8751 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8752 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8753
8754 subl(len, 256);
8755 cmpl(len, 256);
8756 jcc(Assembler::less, L_fold_128_B_loop);
8757
8758 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8759 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8760 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8761 subl(len, 256);
8762
8763 bind(L_fold_256_B_loop);
8764 addl(pos, 256);
8765 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8766 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8767 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8768 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8769
8770 subl(len, 256);
8771 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8772
8773 // Fold 256 into 128
8774 addl(pos, 256);
8775 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8776 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8777 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8778
8779 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8780 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8781 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8782
8783 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8784 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8785
8786 addl(len, 128);
8787 jmp(L_fold_128_B_register);
8788
8789 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8790 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8791
8792 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8793 bind(L_fold_128_B_loop);
8794 addl(pos, 128);
8795 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8796 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8797
8798 subl(len, 128);
8799 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8800
8801 addl(pos, 128);
8802
8803 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8804 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8805 bind(L_fold_128_B_register);
8806 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8807 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8808 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8809 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8810 // save last that has no multiplicand
8811 vextracti64x2(xmm7, xmm4, 3);
8812
8813 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8814 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8815 // Needed later in reduction loop
8816 movdqu(xmm10, Address(table, 1 * 16));
8817 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8818 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8819
8820 // Swap 1,0,3,2 - 01 00 11 10
8821 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8822 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8823 vextracti128(xmm5, xmm8, 1);
8824 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8825
8826 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8827 // instead of a cmp instruction, we use the negative flag with the jl instruction
8828 addl(len, 128 - 16);
8829 jcc(Assembler::less, L_final_reduction_for_128);
8830
8831 bind(L_16B_reduction_loop);
8832 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8833 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8834 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8835 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8836 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8837 addl(pos, 16);
8838 subl(len, 16);
8839 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8840
8841 bind(L_final_reduction_for_128);
8842 addl(len, 16);
8843 jcc(Assembler::equal, L_128_done);
8844
8845 bind(L_get_last_two_xmms);
8846 movdqu(xmm2, xmm7);
8847 addl(pos, len);
8848 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8849 subl(pos, len);
8850
8851 // get rid of the extra data that was loaded before
8852 // load the shift constant
8853 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8854 movdqu(xmm0, Address(rax, len));
8855 addl(rax, len);
8856
8857 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8858 //Change mask to 512
8859 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8860 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8861
8862 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8863 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8864 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8865 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8866 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8867
8868 bind(L_128_done);
8869 // compute crc of a 128-bit value
8870 movdqu(xmm10, Address(table, 3 * 16));
8871 movdqu(xmm0, xmm7);
8872
8873 // 64b fold
8874 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8875 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8876 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8877
8878 // 32b fold
8879 movdqu(xmm0, xmm7);
8880 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8881 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8882 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8883 jmp(L_barrett);
8884
8885 bind(L_less_than_256);
8886 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8887
8888 //barrett reduction
8889 bind(L_barrett);
8890 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8891 movdqu(xmm1, xmm7);
8892 movdqu(xmm2, xmm7);
8893 movdqu(xmm10, Address(table, 4 * 16));
8894
8895 pclmulqdq(xmm7, xmm10, 0x0);
8896 pxor(xmm7, xmm2);
8897 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8898 movdqu(xmm2, xmm7);
8899 pclmulqdq(xmm7, xmm10, 0x10);
8900 pxor(xmm7, xmm2);
8901 pxor(xmm7, xmm1);
8902 pextrd(crc, xmm7, 2);
8903
8904 bind(L_cleanup);
8905 addptr(rsp, 16 * 2 + 8);
8906 pop(r12);
8907 }
8908
8909 // S. Gueron / Information Processing Letters 112 (2012) 184
8910 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8911 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8912 // Output: the 64-bit carry-less product of B * CONST
8913 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8914 Register tmp1, Register tmp2, Register tmp3) {
8915 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8916 if (n > 0) {
8917 addq(tmp3, n * 256 * 8);
8918 }
8919 // Q1 = TABLEExt[n][B & 0xFF];
8920 movl(tmp1, in);
8921 andl(tmp1, 0x000000FF);
8922 shll(tmp1, 3);
8923 addq(tmp1, tmp3);
8924 movq(tmp1, Address(tmp1, 0));
8925
8926 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8927 movl(tmp2, in);
8928 shrl(tmp2, 8);
8929 andl(tmp2, 0x000000FF);
8930 shll(tmp2, 3);
8931 addq(tmp2, tmp3);
8932 movq(tmp2, Address(tmp2, 0));
8933
8934 shlq(tmp2, 8);
8935 xorq(tmp1, tmp2);
8936
8937 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8938 movl(tmp2, in);
8939 shrl(tmp2, 16);
8940 andl(tmp2, 0x000000FF);
8941 shll(tmp2, 3);
8942 addq(tmp2, tmp3);
8943 movq(tmp2, Address(tmp2, 0));
8944
8945 shlq(tmp2, 16);
8946 xorq(tmp1, tmp2);
8947
8948 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8949 shrl(in, 24);
8950 andl(in, 0x000000FF);
8951 shll(in, 3);
8952 addq(in, tmp3);
8953 movq(in, Address(in, 0));
8954
8955 shlq(in, 24);
8956 xorq(in, tmp1);
8957 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8958 }
8959
8960 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8961 Register in_out,
8962 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8963 XMMRegister w_xtmp2,
8964 Register tmp1,
8965 Register n_tmp2, Register n_tmp3) {
8966 if (is_pclmulqdq_supported) {
8967 movdl(w_xtmp1, in_out); // modified blindly
8968
8969 movl(tmp1, const_or_pre_comp_const_index);
8970 movdl(w_xtmp2, tmp1);
8971 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8972
8973 movdq(in_out, w_xtmp1);
8974 } else {
8975 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8976 }
8977 }
8978
8979 // Recombination Alternative 2: No bit-reflections
8980 // T1 = (CRC_A * U1) << 1
8981 // T2 = (CRC_B * U2) << 1
8982 // C1 = T1 >> 32
8983 // C2 = T2 >> 32
8984 // T1 = T1 & 0xFFFFFFFF
8985 // T2 = T2 & 0xFFFFFFFF
8986 // T1 = CRC32(0, T1)
8987 // T2 = CRC32(0, T2)
8988 // C1 = C1 ^ T1
8989 // C2 = C2 ^ T2
8990 // CRC = C1 ^ C2 ^ CRC_C
8991 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8992 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8993 Register tmp1, Register tmp2,
8994 Register n_tmp3) {
8995 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8996 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8997 shlq(in_out, 1);
8998 movl(tmp1, in_out);
8999 shrq(in_out, 32);
9000 xorl(tmp2, tmp2);
9001 crc32(tmp2, tmp1, 4);
9002 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9003 shlq(in1, 1);
9004 movl(tmp1, in1);
9005 shrq(in1, 32);
9006 xorl(tmp2, tmp2);
9007 crc32(tmp2, tmp1, 4);
9008 xorl(in1, tmp2);
9009 xorl(in_out, in1);
9010 xorl(in_out, in2);
9011 }
9012
9013 // Set N to predefined value
9014 // Subtract from a length of a buffer
9015 // execute in a loop:
9016 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9017 // for i = 1 to N do
9018 // CRC_A = CRC32(CRC_A, A[i])
9019 // CRC_B = CRC32(CRC_B, B[i])
9020 // CRC_C = CRC32(CRC_C, C[i])
9021 // end for
9022 // Recombine
9023 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9024 Register in_out1, Register in_out2, Register in_out3,
9025 Register tmp1, Register tmp2, Register tmp3,
9026 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9027 Register tmp4, Register tmp5,
9028 Register n_tmp6) {
9029 Label L_processPartitions;
9030 Label L_processPartition;
9031 Label L_exit;
9032
9033 bind(L_processPartitions);
9034 cmpl(in_out1, 3 * size);
9035 jcc(Assembler::less, L_exit);
9036 xorl(tmp1, tmp1);
9037 xorl(tmp2, tmp2);
9038 movq(tmp3, in_out2);
9039 addq(tmp3, size);
9040
9041 bind(L_processPartition);
9042 crc32(in_out3, Address(in_out2, 0), 8);
9043 crc32(tmp1, Address(in_out2, size), 8);
9044 crc32(tmp2, Address(in_out2, size * 2), 8);
9045 addq(in_out2, 8);
9046 cmpq(in_out2, tmp3);
9047 jcc(Assembler::less, L_processPartition);
9048 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9049 w_xtmp1, w_xtmp2, w_xtmp3,
9050 tmp4, tmp5,
9051 n_tmp6);
9052 addq(in_out2, 2 * size);
9053 subl(in_out1, 3 * size);
9054 jmp(L_processPartitions);
9055
9056 bind(L_exit);
9057 }
9058
9059 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9060 // Input: A buffer I of L bytes.
9061 // Output: the CRC32C value of the buffer.
9062 // Notations:
9063 // Write L = 24N + r, with N = floor (L/24).
9064 // r = L mod 24 (0 <= r < 24).
9065 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9066 // N quadwords, and R consists of r bytes.
9067 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9068 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9069 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9070 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9071 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9072 Register tmp1, Register tmp2, Register tmp3,
9073 Register tmp4, Register tmp5, Register tmp6,
9074 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9075 bool is_pclmulqdq_supported) {
9076 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9077 Label L_wordByWord;
9078 Label L_byteByByteProlog;
9079 Label L_byteByByte;
9080 Label L_exit;
9081
9082 if (is_pclmulqdq_supported ) {
9083 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9084 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9085
9086 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9087 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9088
9089 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9090 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9091 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9092 } else {
9093 const_or_pre_comp_const_index[0] = 1;
9094 const_or_pre_comp_const_index[1] = 0;
9095
9096 const_or_pre_comp_const_index[2] = 3;
9097 const_or_pre_comp_const_index[3] = 2;
9098
9099 const_or_pre_comp_const_index[4] = 5;
9100 const_or_pre_comp_const_index[5] = 4;
9101 }
9102 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9103 in2, in1, in_out,
9104 tmp1, tmp2, tmp3,
9105 w_xtmp1, w_xtmp2, w_xtmp3,
9106 tmp4, tmp5,
9107 tmp6);
9108 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9109 in2, in1, in_out,
9110 tmp1, tmp2, tmp3,
9111 w_xtmp1, w_xtmp2, w_xtmp3,
9112 tmp4, tmp5,
9113 tmp6);
9114 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9115 in2, in1, in_out,
9116 tmp1, tmp2, tmp3,
9117 w_xtmp1, w_xtmp2, w_xtmp3,
9118 tmp4, tmp5,
9119 tmp6);
9120 movl(tmp1, in2);
9121 andl(tmp1, 0x00000007);
9122 negl(tmp1);
9123 addl(tmp1, in2);
9124 addq(tmp1, in1);
9125
9126 cmpq(in1, tmp1);
9127 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9128 align(16);
9129 BIND(L_wordByWord);
9130 crc32(in_out, Address(in1, 0), 8);
9131 addq(in1, 8);
9132 cmpq(in1, tmp1);
9133 jcc(Assembler::less, L_wordByWord);
9134
9135 BIND(L_byteByByteProlog);
9136 andl(in2, 0x00000007);
9137 movl(tmp2, 1);
9138
9139 cmpl(tmp2, in2);
9140 jccb(Assembler::greater, L_exit);
9141 BIND(L_byteByByte);
9142 crc32(in_out, Address(in1, 0), 1);
9143 incq(in1);
9144 incl(tmp2);
9145 cmpl(tmp2, in2);
9146 jcc(Assembler::lessEqual, L_byteByByte);
9147
9148 BIND(L_exit);
9149 }
9150 #undef BIND
9151 #undef BLOCK_COMMENT
9152
9153 // Compress char[] array to byte[].
9154 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9155 // Return the array length if every element in array can be encoded,
9156 // otherwise, the index of first non-latin1 (> 0xff) character.
9157 // @IntrinsicCandidate
9158 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9159 // for (int i = 0; i < len; i++) {
9160 // char c = src[srcOff];
9161 // if (c > 0xff) {
9162 // return i; // return index of non-latin1 char
9163 // }
9164 // dst[dstOff] = (byte)c;
9165 // srcOff++;
9166 // dstOff++;
9167 // }
9168 // return len;
9169 // }
9170 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9171 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9172 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9173 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9174 Label copy_chars_loop, done, reset_sp, copy_tail;
9175
9176 // rsi: src
9177 // rdi: dst
9178 // rdx: len
9179 // rcx: tmp5
9180 // rax: result
9181
9182 // rsi holds start addr of source char[] to be compressed
9183 // rdi holds start addr of destination byte[]
9184 // rdx holds length
9185
9186 assert(len != result, "");
9187
9188 // save length for return
9189 movl(result, len);
9190
9191 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9192 VM_Version::supports_avx512vlbw() &&
9193 VM_Version::supports_bmi2()) {
9194
9195 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9196
9197 // alignment
9198 Label post_alignment;
9199
9200 // if length of the string is less than 32, handle it the old fashioned way
9201 testl(len, -32);
9202 jcc(Assembler::zero, below_threshold);
9203
9204 // First check whether a character is compressible ( <= 0xFF).
9205 // Create mask to test for Unicode chars inside zmm vector
9206 movl(tmp5, 0x00FF);
9207 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9208
9209 testl(len, -64);
9210 jccb(Assembler::zero, post_alignment);
9211
9212 movl(tmp5, dst);
9213 andl(tmp5, (32 - 1));
9214 negl(tmp5);
9215 andl(tmp5, (32 - 1));
9216
9217 // bail out when there is nothing to be done
9218 testl(tmp5, 0xFFFFFFFF);
9219 jccb(Assembler::zero, post_alignment);
9220
9221 // ~(~0 << len), where len is the # of remaining elements to process
9222 movl(len, 0xFFFFFFFF);
9223 shlxl(len, len, tmp5);
9224 notl(len);
9225 kmovdl(mask2, len);
9226 movl(len, result);
9227
9228 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9229 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9230 ktestd(mask1, mask2);
9231 jcc(Assembler::carryClear, copy_tail);
9232
9233 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9234
9235 addptr(src, tmp5);
9236 addptr(src, tmp5);
9237 addptr(dst, tmp5);
9238 subl(len, tmp5);
9239
9240 bind(post_alignment);
9241 // end of alignment
9242
9243 movl(tmp5, len);
9244 andl(tmp5, (32 - 1)); // tail count (in chars)
9245 andl(len, ~(32 - 1)); // vector count (in chars)
9246 jccb(Assembler::zero, copy_loop_tail);
9247
9248 lea(src, Address(src, len, Address::times_2));
9249 lea(dst, Address(dst, len, Address::times_1));
9250 negptr(len);
9251
9252 bind(copy_32_loop);
9253 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9254 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9255 kortestdl(mask1, mask1);
9256 jccb(Assembler::carryClear, reset_for_copy_tail);
9257
9258 // All elements in current processed chunk are valid candidates for
9259 // compression. Write a truncated byte elements to the memory.
9260 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9261 addptr(len, 32);
9262 jccb(Assembler::notZero, copy_32_loop);
9263
9264 bind(copy_loop_tail);
9265 // bail out when there is nothing to be done
9266 testl(tmp5, 0xFFFFFFFF);
9267 jcc(Assembler::zero, done);
9268
9269 movl(len, tmp5);
9270
9271 // ~(~0 << len), where len is the # of remaining elements to process
9272 movl(tmp5, 0xFFFFFFFF);
9273 shlxl(tmp5, tmp5, len);
9274 notl(tmp5);
9275
9276 kmovdl(mask2, tmp5);
9277
9278 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9279 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9280 ktestd(mask1, mask2);
9281 jcc(Assembler::carryClear, copy_tail);
9282
9283 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9284 jmp(done);
9285
9286 bind(reset_for_copy_tail);
9287 lea(src, Address(src, tmp5, Address::times_2));
9288 lea(dst, Address(dst, tmp5, Address::times_1));
9289 subptr(len, tmp5);
9290 jmp(copy_chars_loop);
9291
9292 bind(below_threshold);
9293 }
9294
9295 if (UseSSE42Intrinsics) {
9296 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9297
9298 // vectored compression
9299 testl(len, 0xfffffff8);
9300 jcc(Assembler::zero, copy_tail);
9301
9302 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9303 movdl(tmp1Reg, tmp5);
9304 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9305
9306 andl(len, 0xfffffff0);
9307 jccb(Assembler::zero, copy_16);
9308
9309 // compress 16 chars per iter
9310 pxor(tmp4Reg, tmp4Reg);
9311
9312 lea(src, Address(src, len, Address::times_2));
9313 lea(dst, Address(dst, len, Address::times_1));
9314 negptr(len);
9315
9316 bind(copy_32_loop);
9317 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9318 por(tmp4Reg, tmp2Reg);
9319 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9320 por(tmp4Reg, tmp3Reg);
9321 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9322 jccb(Assembler::notZero, reset_for_copy_tail);
9323 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9324 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9325 addptr(len, 16);
9326 jccb(Assembler::notZero, copy_32_loop);
9327
9328 // compress next vector of 8 chars (if any)
9329 bind(copy_16);
9330 // len = 0
9331 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9332 jccb(Assembler::zero, copy_tail_sse);
9333
9334 pxor(tmp3Reg, tmp3Reg);
9335
9336 movdqu(tmp2Reg, Address(src, 0));
9337 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9338 jccb(Assembler::notZero, reset_for_copy_tail);
9339 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9340 movq(Address(dst, 0), tmp2Reg);
9341 addptr(src, 16);
9342 addptr(dst, 8);
9343 jmpb(copy_tail_sse);
9344
9345 bind(reset_for_copy_tail);
9346 movl(tmp5, result);
9347 andl(tmp5, 0x0000000f);
9348 lea(src, Address(src, tmp5, Address::times_2));
9349 lea(dst, Address(dst, tmp5, Address::times_1));
9350 subptr(len, tmp5);
9351 jmpb(copy_chars_loop);
9352
9353 bind(copy_tail_sse);
9354 movl(len, result);
9355 andl(len, 0x00000007); // tail count (in chars)
9356 }
9357 // compress 1 char per iter
9358 bind(copy_tail);
9359 testl(len, len);
9360 jccb(Assembler::zero, done);
9361 lea(src, Address(src, len, Address::times_2));
9362 lea(dst, Address(dst, len, Address::times_1));
9363 negptr(len);
9364
9365 bind(copy_chars_loop);
9366 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9367 testl(tmp5, 0xff00); // check if Unicode char
9368 jccb(Assembler::notZero, reset_sp);
9369 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9370 increment(len);
9371 jccb(Assembler::notZero, copy_chars_loop);
9372
9373 // add len then return (len will be zero if compress succeeded, otherwise negative)
9374 bind(reset_sp);
9375 addl(result, len);
9376
9377 bind(done);
9378 }
9379
9380 // Inflate byte[] array to char[].
9381 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9382 // @IntrinsicCandidate
9383 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9384 // for (int i = 0; i < len; i++) {
9385 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9386 // }
9387 // }
9388 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9389 XMMRegister tmp1, Register tmp2, KRegister mask) {
9390 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9391 // rsi: src
9392 // rdi: dst
9393 // rdx: len
9394 // rcx: tmp2
9395
9396 // rsi holds start addr of source byte[] to be inflated
9397 // rdi holds start addr of destination char[]
9398 // rdx holds length
9399 assert_different_registers(src, dst, len, tmp2);
9400 movl(tmp2, len);
9401 if ((UseAVX > 2) && // AVX512
9402 VM_Version::supports_avx512vlbw() &&
9403 VM_Version::supports_bmi2()) {
9404
9405 Label copy_32_loop, copy_tail;
9406 Register tmp3_aliased = len;
9407
9408 // if length of the string is less than 16, handle it in an old fashioned way
9409 testl(len, -16);
9410 jcc(Assembler::zero, below_threshold);
9411
9412 testl(len, -1 * AVX3Threshold);
9413 jcc(Assembler::zero, avx3_threshold);
9414
9415 // In order to use only one arithmetic operation for the main loop we use
9416 // this pre-calculation
9417 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9418 andl(len, -32); // vector count
9419 jccb(Assembler::zero, copy_tail);
9420
9421 lea(src, Address(src, len, Address::times_1));
9422 lea(dst, Address(dst, len, Address::times_2));
9423 negptr(len);
9424
9425
9426 // inflate 32 chars per iter
9427 bind(copy_32_loop);
9428 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9429 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9430 addptr(len, 32);
9431 jcc(Assembler::notZero, copy_32_loop);
9432
9433 bind(copy_tail);
9434 // bail out when there is nothing to be done
9435 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9436 jcc(Assembler::zero, done);
9437
9438 // ~(~0 << length), where length is the # of remaining elements to process
9439 movl(tmp3_aliased, -1);
9440 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9441 notl(tmp3_aliased);
9442 kmovdl(mask, tmp3_aliased);
9443 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9444 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9445
9446 jmp(done);
9447 bind(avx3_threshold);
9448 }
9449 if (UseSSE42Intrinsics) {
9450 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9451
9452 if (UseAVX > 1) {
9453 andl(tmp2, (16 - 1));
9454 andl(len, -16);
9455 jccb(Assembler::zero, copy_new_tail);
9456 } else {
9457 andl(tmp2, 0x00000007); // tail count (in chars)
9458 andl(len, 0xfffffff8); // vector count (in chars)
9459 jccb(Assembler::zero, copy_tail);
9460 }
9461
9462 // vectored inflation
9463 lea(src, Address(src, len, Address::times_1));
9464 lea(dst, Address(dst, len, Address::times_2));
9465 negptr(len);
9466
9467 if (UseAVX > 1) {
9468 bind(copy_16_loop);
9469 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9470 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9471 addptr(len, 16);
9472 jcc(Assembler::notZero, copy_16_loop);
9473
9474 bind(below_threshold);
9475 bind(copy_new_tail);
9476 movl(len, tmp2);
9477 andl(tmp2, 0x00000007);
9478 andl(len, 0xFFFFFFF8);
9479 jccb(Assembler::zero, copy_tail);
9480
9481 pmovzxbw(tmp1, Address(src, 0));
9482 movdqu(Address(dst, 0), tmp1);
9483 addptr(src, 8);
9484 addptr(dst, 2 * 8);
9485
9486 jmp(copy_tail, true);
9487 }
9488
9489 // inflate 8 chars per iter
9490 bind(copy_8_loop);
9491 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9492 movdqu(Address(dst, len, Address::times_2), tmp1);
9493 addptr(len, 8);
9494 jcc(Assembler::notZero, copy_8_loop);
9495
9496 bind(copy_tail);
9497 movl(len, tmp2);
9498
9499 cmpl(len, 4);
9500 jccb(Assembler::less, copy_bytes);
9501
9502 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9503 pmovzxbw(tmp1, tmp1);
9504 movq(Address(dst, 0), tmp1);
9505 subptr(len, 4);
9506 addptr(src, 4);
9507 addptr(dst, 8);
9508
9509 bind(copy_bytes);
9510 } else {
9511 bind(below_threshold);
9512 }
9513
9514 testl(len, len);
9515 jccb(Assembler::zero, done);
9516 lea(src, Address(src, len, Address::times_1));
9517 lea(dst, Address(dst, len, Address::times_2));
9518 negptr(len);
9519
9520 // inflate 1 char per iter
9521 bind(copy_chars_loop);
9522 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9523 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9524 increment(len);
9525 jcc(Assembler::notZero, copy_chars_loop);
9526
9527 bind(done);
9528 }
9529
9530 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9531 switch(type) {
9532 case T_BYTE:
9533 case T_BOOLEAN:
9534 evmovdqub(dst, kmask, src, merge, vector_len);
9535 break;
9536 case T_CHAR:
9537 case T_SHORT:
9538 evmovdquw(dst, kmask, src, merge, vector_len);
9539 break;
9540 case T_INT:
9541 case T_FLOAT:
9542 evmovdqul(dst, kmask, src, merge, vector_len);
9543 break;
9544 case T_LONG:
9545 case T_DOUBLE:
9546 evmovdquq(dst, kmask, src, merge, vector_len);
9547 break;
9548 default:
9549 fatal("Unexpected type argument %s", type2name(type));
9550 break;
9551 }
9552 }
9553
9554
9555 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9556 switch(type) {
9557 case T_BYTE:
9558 case T_BOOLEAN:
9559 evmovdqub(dst, kmask, src, merge, vector_len);
9560 break;
9561 case T_CHAR:
9562 case T_SHORT:
9563 evmovdquw(dst, kmask, src, merge, vector_len);
9564 break;
9565 case T_INT:
9566 case T_FLOAT:
9567 evmovdqul(dst, kmask, src, merge, vector_len);
9568 break;
9569 case T_LONG:
9570 case T_DOUBLE:
9571 evmovdquq(dst, kmask, src, merge, vector_len);
9572 break;
9573 default:
9574 fatal("Unexpected type argument %s", type2name(type));
9575 break;
9576 }
9577 }
9578
9579 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9580 switch(type) {
9581 case T_BYTE:
9582 case T_BOOLEAN:
9583 evmovdqub(dst, kmask, src, merge, vector_len);
9584 break;
9585 case T_CHAR:
9586 case T_SHORT:
9587 evmovdquw(dst, kmask, src, merge, vector_len);
9588 break;
9589 case T_INT:
9590 case T_FLOAT:
9591 evmovdqul(dst, kmask, src, merge, vector_len);
9592 break;
9593 case T_LONG:
9594 case T_DOUBLE:
9595 evmovdquq(dst, kmask, src, merge, vector_len);
9596 break;
9597 default:
9598 fatal("Unexpected type argument %s", type2name(type));
9599 break;
9600 }
9601 }
9602
9603 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9604 switch(masklen) {
9605 case 2:
9606 knotbl(dst, src);
9607 movl(rtmp, 3);
9608 kmovbl(ktmp, rtmp);
9609 kandbl(dst, ktmp, dst);
9610 break;
9611 case 4:
9612 knotbl(dst, src);
9613 movl(rtmp, 15);
9614 kmovbl(ktmp, rtmp);
9615 kandbl(dst, ktmp, dst);
9616 break;
9617 case 8:
9618 knotbl(dst, src);
9619 break;
9620 case 16:
9621 knotwl(dst, src);
9622 break;
9623 case 32:
9624 knotdl(dst, src);
9625 break;
9626 case 64:
9627 knotql(dst, src);
9628 break;
9629 default:
9630 fatal("Unexpected vector length %d", masklen);
9631 break;
9632 }
9633 }
9634
9635 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9636 switch(type) {
9637 case T_BOOLEAN:
9638 case T_BYTE:
9639 kandbl(dst, src1, src2);
9640 break;
9641 case T_CHAR:
9642 case T_SHORT:
9643 kandwl(dst, src1, src2);
9644 break;
9645 case T_INT:
9646 case T_FLOAT:
9647 kanddl(dst, src1, src2);
9648 break;
9649 case T_LONG:
9650 case T_DOUBLE:
9651 kandql(dst, src1, src2);
9652 break;
9653 default:
9654 fatal("Unexpected type argument %s", type2name(type));
9655 break;
9656 }
9657 }
9658
9659 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9660 switch(type) {
9661 case T_BOOLEAN:
9662 case T_BYTE:
9663 korbl(dst, src1, src2);
9664 break;
9665 case T_CHAR:
9666 case T_SHORT:
9667 korwl(dst, src1, src2);
9668 break;
9669 case T_INT:
9670 case T_FLOAT:
9671 kordl(dst, src1, src2);
9672 break;
9673 case T_LONG:
9674 case T_DOUBLE:
9675 korql(dst, src1, src2);
9676 break;
9677 default:
9678 fatal("Unexpected type argument %s", type2name(type));
9679 break;
9680 }
9681 }
9682
9683 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9684 switch(type) {
9685 case T_BOOLEAN:
9686 case T_BYTE:
9687 kxorbl(dst, src1, src2);
9688 break;
9689 case T_CHAR:
9690 case T_SHORT:
9691 kxorwl(dst, src1, src2);
9692 break;
9693 case T_INT:
9694 case T_FLOAT:
9695 kxordl(dst, src1, src2);
9696 break;
9697 case T_LONG:
9698 case T_DOUBLE:
9699 kxorql(dst, src1, src2);
9700 break;
9701 default:
9702 fatal("Unexpected type argument %s", type2name(type));
9703 break;
9704 }
9705 }
9706
9707 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9708 switch(type) {
9709 case T_BOOLEAN:
9710 case T_BYTE:
9711 evpermb(dst, mask, nds, src, merge, vector_len); break;
9712 case T_CHAR:
9713 case T_SHORT:
9714 evpermw(dst, mask, nds, src, merge, vector_len); break;
9715 case T_INT:
9716 case T_FLOAT:
9717 evpermd(dst, mask, nds, src, merge, vector_len); break;
9718 case T_LONG:
9719 case T_DOUBLE:
9720 evpermq(dst, mask, nds, src, merge, vector_len); break;
9721 default:
9722 fatal("Unexpected type argument %s", type2name(type)); break;
9723 }
9724 }
9725
9726 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9727 switch(type) {
9728 case T_BOOLEAN:
9729 case T_BYTE:
9730 evpermb(dst, mask, nds, src, merge, vector_len); break;
9731 case T_CHAR:
9732 case T_SHORT:
9733 evpermw(dst, mask, nds, src, merge, vector_len); break;
9734 case T_INT:
9735 case T_FLOAT:
9736 evpermd(dst, mask, nds, src, merge, vector_len); break;
9737 case T_LONG:
9738 case T_DOUBLE:
9739 evpermq(dst, mask, nds, src, merge, vector_len); break;
9740 default:
9741 fatal("Unexpected type argument %s", type2name(type)); break;
9742 }
9743 }
9744
9745 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9746 switch(type) {
9747 case T_BYTE:
9748 evpminub(dst, mask, nds, src, merge, vector_len); break;
9749 case T_SHORT:
9750 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9751 case T_INT:
9752 evpminud(dst, mask, nds, src, merge, vector_len); break;
9753 case T_LONG:
9754 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9755 default:
9756 fatal("Unexpected type argument %s", type2name(type)); break;
9757 }
9758 }
9759
9760 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9761 switch(type) {
9762 case T_BYTE:
9763 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9764 case T_SHORT:
9765 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9766 case T_INT:
9767 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9768 case T_LONG:
9769 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9770 default:
9771 fatal("Unexpected type argument %s", type2name(type)); break;
9772 }
9773 }
9774
9775 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9776 switch(type) {
9777 case T_BYTE:
9778 evpminub(dst, mask, nds, src, merge, vector_len); break;
9779 case T_SHORT:
9780 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9781 case T_INT:
9782 evpminud(dst, mask, nds, src, merge, vector_len); break;
9783 case T_LONG:
9784 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9785 default:
9786 fatal("Unexpected type argument %s", type2name(type)); break;
9787 }
9788 }
9789
9790 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9791 switch(type) {
9792 case T_BYTE:
9793 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9794 case T_SHORT:
9795 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9796 case T_INT:
9797 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9798 case T_LONG:
9799 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9800 default:
9801 fatal("Unexpected type argument %s", type2name(type)); break;
9802 }
9803 }
9804
9805 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9806 switch(type) {
9807 case T_BYTE:
9808 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9809 case T_SHORT:
9810 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9811 case T_INT:
9812 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9813 case T_LONG:
9814 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9815 case T_FLOAT:
9816 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9817 case T_DOUBLE:
9818 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9819 default:
9820 fatal("Unexpected type argument %s", type2name(type)); break;
9821 }
9822 }
9823
9824 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9825 switch(type) {
9826 case T_BYTE:
9827 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9828 case T_SHORT:
9829 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9830 case T_INT:
9831 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9832 case T_LONG:
9833 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9834 case T_FLOAT:
9835 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9836 case T_DOUBLE:
9837 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9838 default:
9839 fatal("Unexpected type argument %s", type2name(type)); break;
9840 }
9841 }
9842
9843 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9844 switch(type) {
9845 case T_BYTE:
9846 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9847 case T_SHORT:
9848 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9849 case T_INT:
9850 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9851 case T_LONG:
9852 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9853 case T_FLOAT:
9854 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9855 case T_DOUBLE:
9856 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9857 default:
9858 fatal("Unexpected type argument %s", type2name(type)); break;
9859 }
9860 }
9861
9862 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9863 switch(type) {
9864 case T_BYTE:
9865 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9866 case T_SHORT:
9867 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9868 case T_INT:
9869 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9870 case T_LONG:
9871 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9872 case T_FLOAT:
9873 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9874 case T_DOUBLE:
9875 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9876 default:
9877 fatal("Unexpected type argument %s", type2name(type)); break;
9878 }
9879 }
9880
9881 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9882 switch(type) {
9883 case T_INT:
9884 evpxord(dst, mask, nds, src, merge, vector_len); break;
9885 case T_LONG:
9886 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9887 default:
9888 fatal("Unexpected type argument %s", type2name(type)); break;
9889 }
9890 }
9891
9892 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9893 switch(type) {
9894 case T_INT:
9895 evpxord(dst, mask, nds, src, merge, vector_len); break;
9896 case T_LONG:
9897 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9898 default:
9899 fatal("Unexpected type argument %s", type2name(type)); break;
9900 }
9901 }
9902
9903 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9904 switch(type) {
9905 case T_INT:
9906 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9907 case T_LONG:
9908 evporq(dst, mask, nds, src, merge, vector_len); break;
9909 default:
9910 fatal("Unexpected type argument %s", type2name(type)); break;
9911 }
9912 }
9913
9914 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9915 switch(type) {
9916 case T_INT:
9917 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9918 case T_LONG:
9919 evporq(dst, mask, nds, src, merge, vector_len); break;
9920 default:
9921 fatal("Unexpected type argument %s", type2name(type)); break;
9922 }
9923 }
9924
9925 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9926 switch(type) {
9927 case T_INT:
9928 evpandd(dst, mask, nds, src, merge, vector_len); break;
9929 case T_LONG:
9930 evpandq(dst, mask, nds, src, merge, vector_len); break;
9931 default:
9932 fatal("Unexpected type argument %s", type2name(type)); break;
9933 }
9934 }
9935
9936 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9937 switch(type) {
9938 case T_INT:
9939 evpandd(dst, mask, nds, src, merge, vector_len); break;
9940 case T_LONG:
9941 evpandq(dst, mask, nds, src, merge, vector_len); break;
9942 default:
9943 fatal("Unexpected type argument %s", type2name(type)); break;
9944 }
9945 }
9946
9947 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
9948 switch(masklen) {
9949 case 8:
9950 kortestbl(src1, src2);
9951 break;
9952 case 16:
9953 kortestwl(src1, src2);
9954 break;
9955 case 32:
9956 kortestdl(src1, src2);
9957 break;
9958 case 64:
9959 kortestql(src1, src2);
9960 break;
9961 default:
9962 fatal("Unexpected mask length %d", masklen);
9963 break;
9964 }
9965 }
9966
9967
9968 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
9969 switch(masklen) {
9970 case 8:
9971 ktestbl(src1, src2);
9972 break;
9973 case 16:
9974 ktestwl(src1, src2);
9975 break;
9976 case 32:
9977 ktestdl(src1, src2);
9978 break;
9979 case 64:
9980 ktestql(src1, src2);
9981 break;
9982 default:
9983 fatal("Unexpected mask length %d", masklen);
9984 break;
9985 }
9986 }
9987
9988 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9989 switch(type) {
9990 case T_INT:
9991 evprold(dst, mask, src, shift, merge, vlen_enc); break;
9992 case T_LONG:
9993 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
9994 default:
9995 fatal("Unexpected type argument %s", type2name(type)); break;
9996 break;
9997 }
9998 }
9999
10000 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10001 switch(type) {
10002 case T_INT:
10003 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10004 case T_LONG:
10005 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10006 default:
10007 fatal("Unexpected type argument %s", type2name(type)); break;
10008 }
10009 }
10010
10011 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10012 switch(type) {
10013 case T_INT:
10014 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10015 case T_LONG:
10016 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10017 default:
10018 fatal("Unexpected type argument %s", type2name(type)); break;
10019 }
10020 }
10021
10022 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10023 switch(type) {
10024 case T_INT:
10025 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10026 case T_LONG:
10027 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10028 default:
10029 fatal("Unexpected type argument %s", type2name(type)); break;
10030 }
10031 }
10032
10033 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10034 assert(rscratch != noreg || always_reachable(src), "missing");
10035
10036 if (reachable(src)) {
10037 evpandq(dst, nds, as_Address(src), vector_len);
10038 } else {
10039 lea(rscratch, src);
10040 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10041 }
10042 }
10043
10044 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10045 assert(rscratch != noreg || always_reachable(src), "missing");
10046
10047 if (reachable(src)) {
10048 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10049 } else {
10050 lea(rscratch, src);
10051 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10052 }
10053 }
10054
10055 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10056 assert(rscratch != noreg || always_reachable(src), "missing");
10057
10058 if (reachable(src)) {
10059 evporq(dst, nds, as_Address(src), vector_len);
10060 } else {
10061 lea(rscratch, src);
10062 evporq(dst, nds, Address(rscratch, 0), vector_len);
10063 }
10064 }
10065
10066 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10067 assert(rscratch != noreg || always_reachable(src), "missing");
10068
10069 if (reachable(src)) {
10070 vpshufb(dst, nds, as_Address(src), vector_len);
10071 } else {
10072 lea(rscratch, src);
10073 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10074 }
10075 }
10076
10077 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10078 assert(rscratch != noreg || always_reachable(src), "missing");
10079
10080 if (reachable(src)) {
10081 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10082 } else {
10083 lea(rscratch, src);
10084 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10085 }
10086 }
10087
10088 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10089 assert(rscratch != noreg || always_reachable(src3), "missing");
10090
10091 if (reachable(src3)) {
10092 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10093 } else {
10094 lea(rscratch, src3);
10095 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10096 }
10097 }
10098
10099 #ifdef COMPILER2
10100
10101 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10102 Register length, Register temp, int vec_enc) {
10103 // Computing mask for predicated vector store.
10104 movptr(temp, -1);
10105 bzhiq(temp, temp, length);
10106 kmov(mask, temp);
10107 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10108 }
10109
10110 // Set memory operation for length "less than" 64 bytes.
10111 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10112 XMMRegister xmm, KRegister mask, Register length,
10113 Register temp, bool use64byteVector) {
10114 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10115 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10116 if (!use64byteVector) {
10117 fill32(dst, disp, xmm);
10118 subptr(length, 32 >> shift);
10119 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10120 } else {
10121 assert(MaxVectorSize == 64, "vector length != 64");
10122 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10123 }
10124 }
10125
10126
10127 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10128 XMMRegister xmm, KRegister mask, Register length,
10129 Register temp) {
10130 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10131 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10132 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10133 }
10134
10135
10136 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10137 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10138 vmovdqu(dst, xmm);
10139 }
10140
10141 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10142 fill32(Address(dst, disp), xmm);
10143 }
10144
10145 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10146 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10147 if (!use64byteVector) {
10148 fill32(dst, xmm);
10149 fill32(dst.plus_disp(32), xmm);
10150 } else {
10151 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10152 }
10153 }
10154
10155 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10156 fill64(Address(dst, disp), xmm, use64byteVector);
10157 }
10158
10159 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10160 Register count, Register rtmp, XMMRegister xtmp) {
10161 Label L_exit;
10162 Label L_fill_start;
10163 Label L_fill_64_bytes;
10164 Label L_fill_96_bytes;
10165 Label L_fill_128_bytes;
10166 Label L_fill_128_bytes_loop;
10167 Label L_fill_128_loop_header;
10168 Label L_fill_128_bytes_loop_header;
10169 Label L_fill_128_bytes_loop_pre_header;
10170 Label L_fill_zmm_sequence;
10171
10172 int shift = -1;
10173 switch(type) {
10174 case T_BYTE: shift = 0;
10175 break;
10176 case T_SHORT: shift = 1;
10177 break;
10178 case T_INT: shift = 2;
10179 break;
10180 /* Uncomment when LONG fill stubs are supported.
10181 case T_LONG: shift = 3;
10182 break;
10183 */
10184 default:
10185 fatal("Unhandled type: %s\n", type2name(type));
10186 }
10187
10188 if ((CopyAVX3Threshold != 0) || (MaxVectorSize == 32)) {
10189
10190 if (MaxVectorSize == 64) {
10191 cmpq(count, CopyAVX3Threshold >> shift);
10192 jcc(Assembler::greater, L_fill_zmm_sequence);
10193 }
10194
10195 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10196
10197 bind(L_fill_start);
10198
10199 cmpq(count, 32 >> shift);
10200 jccb(Assembler::greater, L_fill_64_bytes);
10201 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10202 jmp(L_exit);
10203
10204 bind(L_fill_64_bytes);
10205 cmpq(count, 64 >> shift);
10206 jccb(Assembler::greater, L_fill_96_bytes);
10207 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10208 jmp(L_exit);
10209
10210 bind(L_fill_96_bytes);
10211 cmpq(count, 96 >> shift);
10212 jccb(Assembler::greater, L_fill_128_bytes);
10213 fill64(to, 0, xtmp);
10214 subq(count, 64 >> shift);
10215 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10216 jmp(L_exit);
10217
10218 bind(L_fill_128_bytes);
10219 cmpq(count, 128 >> shift);
10220 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10221 fill64(to, 0, xtmp);
10222 fill32(to, 64, xtmp);
10223 subq(count, 96 >> shift);
10224 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10225 jmp(L_exit);
10226
10227 bind(L_fill_128_bytes_loop_pre_header);
10228 {
10229 mov(rtmp, to);
10230 andq(rtmp, 31);
10231 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10232 negq(rtmp);
10233 addq(rtmp, 32);
10234 mov64(r8, -1L);
10235 bzhiq(r8, r8, rtmp);
10236 kmovql(k2, r8);
10237 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10238 addq(to, rtmp);
10239 shrq(rtmp, shift);
10240 subq(count, rtmp);
10241 }
10242
10243 cmpq(count, 128 >> shift);
10244 jcc(Assembler::less, L_fill_start);
10245
10246 bind(L_fill_128_bytes_loop_header);
10247 subq(count, 128 >> shift);
10248
10249 align32();
10250 bind(L_fill_128_bytes_loop);
10251 fill64(to, 0, xtmp);
10252 fill64(to, 64, xtmp);
10253 addq(to, 128);
10254 subq(count, 128 >> shift);
10255 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10256
10257 addq(count, 128 >> shift);
10258 jcc(Assembler::zero, L_exit);
10259 jmp(L_fill_start);
10260 }
10261
10262 if (MaxVectorSize == 64) {
10263 // Sequence using 64 byte ZMM register.
10264 Label L_fill_128_bytes_zmm;
10265 Label L_fill_192_bytes_zmm;
10266 Label L_fill_192_bytes_loop_zmm;
10267 Label L_fill_192_bytes_loop_header_zmm;
10268 Label L_fill_192_bytes_loop_pre_header_zmm;
10269 Label L_fill_start_zmm_sequence;
10270
10271 bind(L_fill_zmm_sequence);
10272 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10273
10274 bind(L_fill_start_zmm_sequence);
10275 cmpq(count, 64 >> shift);
10276 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10277 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10278 jmp(L_exit);
10279
10280 bind(L_fill_128_bytes_zmm);
10281 cmpq(count, 128 >> shift);
10282 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10283 fill64(to, 0, xtmp, true);
10284 subq(count, 64 >> shift);
10285 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10286 jmp(L_exit);
10287
10288 bind(L_fill_192_bytes_zmm);
10289 cmpq(count, 192 >> shift);
10290 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10291 fill64(to, 0, xtmp, true);
10292 fill64(to, 64, xtmp, true);
10293 subq(count, 128 >> shift);
10294 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10295 jmp(L_exit);
10296
10297 bind(L_fill_192_bytes_loop_pre_header_zmm);
10298 {
10299 movq(rtmp, to);
10300 andq(rtmp, 63);
10301 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10302 negq(rtmp);
10303 addq(rtmp, 64);
10304 mov64(r8, -1L);
10305 bzhiq(r8, r8, rtmp);
10306 kmovql(k2, r8);
10307 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10308 addq(to, rtmp);
10309 shrq(rtmp, shift);
10310 subq(count, rtmp);
10311 }
10312
10313 cmpq(count, 192 >> shift);
10314 jcc(Assembler::less, L_fill_start_zmm_sequence);
10315
10316 bind(L_fill_192_bytes_loop_header_zmm);
10317 subq(count, 192 >> shift);
10318
10319 align32();
10320 bind(L_fill_192_bytes_loop_zmm);
10321 fill64(to, 0, xtmp, true);
10322 fill64(to, 64, xtmp, true);
10323 fill64(to, 128, xtmp, true);
10324 addq(to, 192);
10325 subq(count, 192 >> shift);
10326 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10327
10328 addq(count, 192 >> shift);
10329 jcc(Assembler::zero, L_exit);
10330 jmp(L_fill_start_zmm_sequence);
10331 }
10332 bind(L_exit);
10333 }
10334 #endif //COMPILER2
10335
10336
10337 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10338 Label done;
10339 cvttss2sil(dst, src);
10340 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10341 cmpl(dst, 0x80000000); // float_sign_flip
10342 jccb(Assembler::notEqual, done);
10343 subptr(rsp, 8);
10344 movflt(Address(rsp, 0), src);
10345 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10346 pop(dst);
10347 bind(done);
10348 }
10349
10350 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10351 Label done;
10352 cvttsd2sil(dst, src);
10353 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10354 cmpl(dst, 0x80000000); // float_sign_flip
10355 jccb(Assembler::notEqual, done);
10356 subptr(rsp, 8);
10357 movdbl(Address(rsp, 0), src);
10358 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10359 pop(dst);
10360 bind(done);
10361 }
10362
10363 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10364 Label done;
10365 cvttss2siq(dst, src);
10366 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10367 jccb(Assembler::notEqual, done);
10368 subptr(rsp, 8);
10369 movflt(Address(rsp, 0), src);
10370 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10371 pop(dst);
10372 bind(done);
10373 }
10374
10375 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10376 // Following code is line by line assembly translation rounding algorithm.
10377 // Please refer to java.lang.Math.round(float) algorithm for details.
10378 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10379 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10380 const int32_t FloatConsts_EXP_BIAS = 127;
10381 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10382 const int32_t MINUS_32 = 0xFFFFFFE0;
10383 Label L_special_case, L_block1, L_exit;
10384 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10385 movdl(dst, src);
10386 andl(dst, rtmp);
10387 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10388 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10389 subl(rtmp, dst);
10390 movl(rcx, rtmp);
10391 movl(dst, MINUS_32);
10392 testl(rtmp, dst);
10393 jccb(Assembler::notEqual, L_special_case);
10394 movdl(dst, src);
10395 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10396 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10397 movdl(rtmp, src);
10398 testl(rtmp, rtmp);
10399 jccb(Assembler::greaterEqual, L_block1);
10400 negl(dst);
10401 bind(L_block1);
10402 sarl(dst);
10403 addl(dst, 0x1);
10404 sarl(dst, 0x1);
10405 jmp(L_exit);
10406 bind(L_special_case);
10407 convert_f2i(dst, src);
10408 bind(L_exit);
10409 }
10410
10411 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10412 // Following code is line by line assembly translation rounding algorithm.
10413 // Please refer to java.lang.Math.round(double) algorithm for details.
10414 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10415 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10416 const int64_t DoubleConsts_EXP_BIAS = 1023;
10417 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10418 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10419 Label L_special_case, L_block1, L_exit;
10420 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10421 movq(dst, src);
10422 andq(dst, rtmp);
10423 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10424 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10425 subq(rtmp, dst);
10426 movq(rcx, rtmp);
10427 mov64(dst, MINUS_64);
10428 testq(rtmp, dst);
10429 jccb(Assembler::notEqual, L_special_case);
10430 movq(dst, src);
10431 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10432 andq(dst, rtmp);
10433 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10434 orq(dst, rtmp);
10435 movq(rtmp, src);
10436 testq(rtmp, rtmp);
10437 jccb(Assembler::greaterEqual, L_block1);
10438 negq(dst);
10439 bind(L_block1);
10440 sarq(dst);
10441 addq(dst, 0x1);
10442 sarq(dst, 0x1);
10443 jmp(L_exit);
10444 bind(L_special_case);
10445 convert_d2l(dst, src);
10446 bind(L_exit);
10447 }
10448
10449 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10450 Label done;
10451 cvttsd2siq(dst, src);
10452 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10453 jccb(Assembler::notEqual, done);
10454 subptr(rsp, 8);
10455 movdbl(Address(rsp, 0), src);
10456 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10457 pop(dst);
10458 bind(done);
10459 }
10460
10461 void MacroAssembler::cache_wb(Address line)
10462 {
10463 // 64 bit cpus always support clflush
10464 bool optimized = VM_Version::supports_clflushopt();
10465 bool no_evict = VM_Version::supports_clwb();
10466
10467 // prefer clwb (writeback without evict) otherwise
10468 // prefer clflushopt (potentially parallel writeback with evict)
10469 // otherwise fallback on clflush (serial writeback with evict)
10470
10471 if (optimized) {
10472 if (no_evict) {
10473 clwb(line);
10474 } else {
10475 clflushopt(line);
10476 }
10477 } else {
10478 // no need for fence when using CLFLUSH
10479 clflush(line);
10480 }
10481 }
10482
10483 void MacroAssembler::cache_wbsync(bool is_pre)
10484 {
10485 bool optimized = VM_Version::supports_clflushopt();
10486 bool no_evict = VM_Version::supports_clwb();
10487
10488 // pick the correct implementation
10489
10490 if (!is_pre && (optimized || no_evict)) {
10491 // need an sfence for post flush when using clflushopt or clwb
10492 // otherwise no no need for any synchroniaztion
10493
10494 sfence();
10495 }
10496 }
10497
10498 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10499 switch (cond) {
10500 // Note some conditions are synonyms for others
10501 case Assembler::zero: return Assembler::notZero;
10502 case Assembler::notZero: return Assembler::zero;
10503 case Assembler::less: return Assembler::greaterEqual;
10504 case Assembler::lessEqual: return Assembler::greater;
10505 case Assembler::greater: return Assembler::lessEqual;
10506 case Assembler::greaterEqual: return Assembler::less;
10507 case Assembler::below: return Assembler::aboveEqual;
10508 case Assembler::belowEqual: return Assembler::above;
10509 case Assembler::above: return Assembler::belowEqual;
10510 case Assembler::aboveEqual: return Assembler::below;
10511 case Assembler::overflow: return Assembler::noOverflow;
10512 case Assembler::noOverflow: return Assembler::overflow;
10513 case Assembler::negative: return Assembler::positive;
10514 case Assembler::positive: return Assembler::negative;
10515 case Assembler::parity: return Assembler::noParity;
10516 case Assembler::noParity: return Assembler::parity;
10517 }
10518 ShouldNotReachHere(); return Assembler::overflow;
10519 }
10520
10521 // This is simply a call to Thread::current()
10522 void MacroAssembler::get_thread_slow(Register thread) {
10523 if (thread != rax) {
10524 push(rax);
10525 }
10526 push(rdi);
10527 push(rsi);
10528 push(rdx);
10529 push(rcx);
10530 push(r8);
10531 push(r9);
10532 push(r10);
10533 push(r11);
10534
10535 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10536
10537 pop(r11);
10538 pop(r10);
10539 pop(r9);
10540 pop(r8);
10541 pop(rcx);
10542 pop(rdx);
10543 pop(rsi);
10544 pop(rdi);
10545 if (thread != rax) {
10546 mov(thread, rax);
10547 pop(rax);
10548 }
10549 }
10550
10551 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10552 Label L_stack_ok;
10553 if (bias == 0) {
10554 testptr(sp, 2 * wordSize - 1);
10555 } else {
10556 // lea(tmp, Address(rsp, bias);
10557 mov(tmp, sp);
10558 addptr(tmp, bias);
10559 testptr(tmp, 2 * wordSize - 1);
10560 }
10561 jcc(Assembler::equal, L_stack_ok);
10562 block_comment(msg);
10563 stop(msg);
10564 bind(L_stack_ok);
10565 }
10566
10567 // Implements fast-locking.
10568 //
10569 // obj: the object to be locked
10570 // reg_rax: rax
10571 // thread: the thread which attempts to lock obj
10572 // tmp: a temporary register
10573 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow) {
10574 Register thread = r15_thread;
10575
10576 assert(reg_rax == rax, "");
10577 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10578
10579 Label push;
10580 const Register top = tmp;
10581
10582 // Preload the markWord. It is important that this is the first
10583 // instruction emitted as it is part of C1's null check semantics.
10584 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10585
10586 if (UseObjectMonitorTable) {
10587 // Clear cache in case fast locking succeeds or we need to take the slow-path.
10588 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10589 }
10590
10591 if (DiagnoseSyncOnValueBasedClasses != 0) {
10592 load_klass(tmp, obj, rscratch1);
10593 testb(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
10594 jcc(Assembler::notZero, slow);
10595 }
10596
10597 // Load top.
10598 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10599
10600 // Check if the lock-stack is full.
10601 cmpl(top, LockStack::end_offset());
10602 jcc(Assembler::greaterEqual, slow);
10603
10604 // Check for recursion.
10605 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10606 jcc(Assembler::equal, push);
10607
10608 // Check header for monitor (0b10).
10609 testptr(reg_rax, markWord::monitor_value);
10610 jcc(Assembler::notZero, slow);
10611
10612 // Try to lock. Transition lock bits 0b01 => 0b00
10613 movptr(tmp, reg_rax);
10614 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10615 orptr(reg_rax, markWord::unlocked_value);
10616 // Mask inline_type bit such that we go to the slow path if object is an inline type
10617 andptr(reg_rax, ~((int) markWord::inline_type_bit_in_place));
10618
10619 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10620 jcc(Assembler::notEqual, slow);
10621
10622 // Restore top, CAS clobbers register.
10623 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10624
10625 bind(push);
10626 // After successful lock, push object on lock-stack.
10627 movptr(Address(thread, top), obj);
10628 incrementl(top, oopSize);
10629 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10630 }
10631
10632 // Implements fast-unlocking.
10633 //
10634 // obj: the object to be unlocked
10635 // reg_rax: rax
10636 // thread: the thread
10637 // tmp: a temporary register
10638 void MacroAssembler::fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow) {
10639 Register thread = r15_thread;
10640
10641 assert(reg_rax == rax, "");
10642 assert_different_registers(obj, reg_rax, thread, tmp);
10643
10644 Label unlocked, push_and_slow;
10645 const Register top = tmp;
10646
10647 // Check if obj is top of lock-stack.
10648 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10649 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10650 jcc(Assembler::notEqual, slow);
10651
10652 // Pop lock-stack.
10653 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10654 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10655
10656 // Check if recursive.
10657 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10658 jcc(Assembler::equal, unlocked);
10659
10660 // Not recursive. Check header for monitor (0b10).
10661 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10662 testptr(reg_rax, markWord::monitor_value);
10663 jcc(Assembler::notZero, push_and_slow);
10664
10665 #ifdef ASSERT
10666 // Check header not unlocked (0b01).
10667 Label not_unlocked;
10668 testptr(reg_rax, markWord::unlocked_value);
10669 jcc(Assembler::zero, not_unlocked);
10670 stop("fast_unlock already unlocked");
10671 bind(not_unlocked);
10672 #endif
10673
10674 // Try to unlock. Transition lock bits 0b00 => 0b01
10675 movptr(tmp, reg_rax);
10676 orptr(tmp, markWord::unlocked_value);
10677 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10678 jcc(Assembler::equal, unlocked);
10679
10680 bind(push_and_slow);
10681 // Restore lock-stack and handle the unlock in runtime.
10682 #ifdef ASSERT
10683 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10684 movptr(Address(thread, top), obj);
10685 #endif
10686 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10687 jmp(slow);
10688
10689 bind(unlocked);
10690 }
10691
10692 // Saves legacy GPRs state on stack.
10693 void MacroAssembler::save_legacy_gprs() {
10694 subq(rsp, 16 * wordSize);
10695 movq(Address(rsp, 15 * wordSize), rax);
10696 movq(Address(rsp, 14 * wordSize), rcx);
10697 movq(Address(rsp, 13 * wordSize), rdx);
10698 movq(Address(rsp, 12 * wordSize), rbx);
10699 movq(Address(rsp, 10 * wordSize), rbp);
10700 movq(Address(rsp, 9 * wordSize), rsi);
10701 movq(Address(rsp, 8 * wordSize), rdi);
10702 movq(Address(rsp, 7 * wordSize), r8);
10703 movq(Address(rsp, 6 * wordSize), r9);
10704 movq(Address(rsp, 5 * wordSize), r10);
10705 movq(Address(rsp, 4 * wordSize), r11);
10706 movq(Address(rsp, 3 * wordSize), r12);
10707 movq(Address(rsp, 2 * wordSize), r13);
10708 movq(Address(rsp, wordSize), r14);
10709 movq(Address(rsp, 0), r15);
10710 }
10711
10712 // Resotres back legacy GPRs state from stack.
10713 void MacroAssembler::restore_legacy_gprs() {
10714 movq(r15, Address(rsp, 0));
10715 movq(r14, Address(rsp, wordSize));
10716 movq(r13, Address(rsp, 2 * wordSize));
10717 movq(r12, Address(rsp, 3 * wordSize));
10718 movq(r11, Address(rsp, 4 * wordSize));
10719 movq(r10, Address(rsp, 5 * wordSize));
10720 movq(r9, Address(rsp, 6 * wordSize));
10721 movq(r8, Address(rsp, 7 * wordSize));
10722 movq(rdi, Address(rsp, 8 * wordSize));
10723 movq(rsi, Address(rsp, 9 * wordSize));
10724 movq(rbp, Address(rsp, 10 * wordSize));
10725 movq(rbx, Address(rsp, 12 * wordSize));
10726 movq(rdx, Address(rsp, 13 * wordSize));
10727 movq(rcx, Address(rsp, 14 * wordSize));
10728 movq(rax, Address(rsp, 15 * wordSize));
10729 addq(rsp, 16 * wordSize);
10730 }
10731
10732 void MacroAssembler::load_aotrc_address(Register reg, address a) {
10733 #if INCLUDE_CDS
10734 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
10735 if (AOTCodeCache::is_on_for_dump()) {
10736 // all aotrc field addresses should be registered in the AOTCodeCache address table
10737 lea(reg, ExternalAddress(a));
10738 } else {
10739 mov64(reg, (uint64_t)a);
10740 }
10741 #else
10742 ShouldNotReachHere();
10743 #endif
10744 }
10745
10746 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10747 if (VM_Version::supports_apx_f()) {
10748 esetzucc(comparison, dst);
10749 } else {
10750 setb(comparison, dst);
10751 movzbl(dst, dst);
10752 }
10753 }