1 /*
   2  * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/assembler.hpp"
  28 #include "asm/assembler.inline.hpp"
  29 #include "compiler/compiler_globals.hpp"
  30 #include "compiler/disassembler.hpp"
  31 #include "ci/ciInlineKlass.hpp"
  32 #include "gc/shared/barrierSet.hpp"
  33 #include "gc/shared/barrierSetAssembler.hpp"
  34 #include "gc/shared/collectedHeap.inline.hpp"
  35 #include "gc/shared/tlab_globals.hpp"
  36 #include "interpreter/bytecodeHistogram.hpp"
  37 #include "interpreter/interpreter.hpp"
  38 #include "memory/resourceArea.hpp"
  39 #include "memory/universe.hpp"
  40 #include "oops/accessDecorators.hpp"
  41 #include "oops/compressedOops.inline.hpp"
  42 #include "oops/klass.inline.hpp"
  43 #include "prims/methodHandles.hpp"
  44 #include "runtime/flags/flagSetting.hpp"
  45 #include "runtime/interfaceSupport.inline.hpp"
  46 #include "runtime/jniHandles.hpp"
  47 #include "runtime/objectMonitor.hpp"
  48 #include "runtime/os.hpp"
  49 #include "runtime/safepoint.hpp"
  50 #include "runtime/safepointMechanism.hpp"
  51 #include "runtime/sharedRuntime.hpp"
  52 #include "runtime/signature_cc.hpp"
  53 #include "runtime/stubRoutines.hpp"
  54 #include "runtime/thread.hpp"
  55 #include "utilities/macros.hpp"
  56 #include "vmreg_x86.inline.hpp"
  57 #include "crc32c.h"
  58 #ifdef COMPILER2
  59 #include "opto/output.hpp"
  60 #endif
  61 
  62 #ifdef PRODUCT
  63 #define BLOCK_COMMENT(str) /* nothing */
  64 #define STOP(error) stop(error)
  65 #else
  66 #define BLOCK_COMMENT(str) block_comment(str)
  67 #define STOP(error) block_comment(error); stop(error)
  68 #endif
  69 
  70 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  71 
  72 #ifdef ASSERT
  73 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
  74 #endif
  75 
  76 static Assembler::Condition reverse[] = {
  77     Assembler::noOverflow     /* overflow      = 0x0 */ ,
  78     Assembler::overflow       /* noOverflow    = 0x1 */ ,
  79     Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
  80     Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
  81     Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
  82     Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
  83     Assembler::above          /* belowEqual    = 0x6 */ ,
  84     Assembler::belowEqual     /* above         = 0x7 */ ,
  85     Assembler::positive       /* negative      = 0x8 */ ,
  86     Assembler::negative       /* positive      = 0x9 */ ,
  87     Assembler::noParity       /* parity        = 0xa */ ,
  88     Assembler::parity         /* noParity      = 0xb */ ,
  89     Assembler::greaterEqual   /* less          = 0xc */ ,
  90     Assembler::less           /* greaterEqual  = 0xd */ ,
  91     Assembler::greater        /* lessEqual     = 0xe */ ,
  92     Assembler::lessEqual      /* greater       = 0xf, */
  93 
  94 };
  95 
  96 
  97 // Implementation of MacroAssembler
  98 
  99 // First all the versions that have distinct versions depending on 32/64 bit
 100 // Unless the difference is trivial (1 line or so).
 101 
 102 #ifndef _LP64
 103 
 104 // 32bit versions
 105 
 106 Address MacroAssembler::as_Address(AddressLiteral adr) {
 107   return Address(adr.target(), adr.rspec());
 108 }
 109 
 110 Address MacroAssembler::as_Address(ArrayAddress adr) {
 111   return Address::make_array(adr);
 112 }
 113 
 114 void MacroAssembler::call_VM_leaf_base(address entry_point,
 115                                        int number_of_arguments) {
 116   call(RuntimeAddress(entry_point));
 117   increment(rsp, number_of_arguments * wordSize);
 118 }
 119 
 120 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
 121   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 122 }
 123 
 124 
 125 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
 126   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 127 }
 128 
 129 void MacroAssembler::cmpoop(Address src1, jobject obj) {
 130   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 131 }
 132 
 133 void MacroAssembler::cmpoop(Register src1, jobject obj) {
 134   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 135 }
 136 
 137 void MacroAssembler::extend_sign(Register hi, Register lo) {
 138   // According to Intel Doc. AP-526, "Integer Divide", p.18.
 139   if (VM_Version::is_P6() && hi == rdx && lo == rax) {
 140     cdql();
 141   } else {
 142     movl(hi, lo);
 143     sarl(hi, 31);
 144   }
 145 }
 146 
 147 void MacroAssembler::jC2(Register tmp, Label& L) {
 148   // set parity bit if FPU flag C2 is set (via rax)
 149   save_rax(tmp);
 150   fwait(); fnstsw_ax();
 151   sahf();
 152   restore_rax(tmp);
 153   // branch
 154   jcc(Assembler::parity, L);
 155 }
 156 
 157 void MacroAssembler::jnC2(Register tmp, Label& L) {
 158   // set parity bit if FPU flag C2 is set (via rax)
 159   save_rax(tmp);
 160   fwait(); fnstsw_ax();
 161   sahf();
 162   restore_rax(tmp);
 163   // branch
 164   jcc(Assembler::noParity, L);
 165 }
 166 
 167 // 32bit can do a case table jump in one instruction but we no longer allow the base
 168 // to be installed in the Address class
 169 void MacroAssembler::jump(ArrayAddress entry) {
 170   jmp(as_Address(entry));
 171 }
 172 
 173 // Note: y_lo will be destroyed
 174 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 175   // Long compare for Java (semantics as described in JVM spec.)
 176   Label high, low, done;
 177 
 178   cmpl(x_hi, y_hi);
 179   jcc(Assembler::less, low);
 180   jcc(Assembler::greater, high);
 181   // x_hi is the return register
 182   xorl(x_hi, x_hi);
 183   cmpl(x_lo, y_lo);
 184   jcc(Assembler::below, low);
 185   jcc(Assembler::equal, done);
 186 
 187   bind(high);
 188   xorl(x_hi, x_hi);
 189   increment(x_hi);
 190   jmp(done);
 191 
 192   bind(low);
 193   xorl(x_hi, x_hi);
 194   decrementl(x_hi);
 195 
 196   bind(done);
 197 }
 198 
 199 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 200     mov_literal32(dst, (int32_t)src.target(), src.rspec());
 201 }
 202 
 203 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 204   // leal(dst, as_Address(adr));
 205   // see note in movl as to why we must use a move
 206   mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
 207 }
 208 
 209 void MacroAssembler::leave() {
 210   mov(rsp, rbp);
 211   pop(rbp);
 212 }
 213 
 214 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
 215   // Multiplication of two Java long values stored on the stack
 216   // as illustrated below. Result is in rdx:rax.
 217   //
 218   // rsp ---> [  ??  ] \               \
 219   //            ....    | y_rsp_offset  |
 220   //          [ y_lo ] /  (in bytes)    | x_rsp_offset
 221   //          [ y_hi ]                  | (in bytes)
 222   //            ....                    |
 223   //          [ x_lo ]                 /
 224   //          [ x_hi ]
 225   //            ....
 226   //
 227   // Basic idea: lo(result) = lo(x_lo * y_lo)
 228   //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
 229   Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
 230   Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
 231   Label quick;
 232   // load x_hi, y_hi and check if quick
 233   // multiplication is possible
 234   movl(rbx, x_hi);
 235   movl(rcx, y_hi);
 236   movl(rax, rbx);
 237   orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
 238   jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
 239   // do full multiplication
 240   // 1st step
 241   mull(y_lo);                                    // x_hi * y_lo
 242   movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
 243   // 2nd step
 244   movl(rax, x_lo);
 245   mull(rcx);                                     // x_lo * y_hi
 246   addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
 247   // 3rd step
 248   bind(quick);                                   // note: rbx, = 0 if quick multiply!
 249   movl(rax, x_lo);
 250   mull(y_lo);                                    // x_lo * y_lo
 251   addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
 252 }
 253 
 254 void MacroAssembler::lneg(Register hi, Register lo) {
 255   negl(lo);
 256   adcl(hi, 0);
 257   negl(hi);
 258 }
 259 
 260 void MacroAssembler::lshl(Register hi, Register lo) {
 261   // Java shift left long support (semantics as described in JVM spec., p.305)
 262   // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
 263   // shift value is in rcx !
 264   assert(hi != rcx, "must not use rcx");
 265   assert(lo != rcx, "must not use rcx");
 266   const Register s = rcx;                        // shift count
 267   const int      n = BitsPerWord;
 268   Label L;
 269   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 270   cmpl(s, n);                                    // if (s < n)
 271   jcc(Assembler::less, L);                       // else (s >= n)
 272   movl(hi, lo);                                  // x := x << n
 273   xorl(lo, lo);
 274   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 275   bind(L);                                       // s (mod n) < n
 276   shldl(hi, lo);                                 // x := x << s
 277   shll(lo);
 278 }
 279 
 280 
 281 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
 282   // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
 283   // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
 284   assert(hi != rcx, "must not use rcx");
 285   assert(lo != rcx, "must not use rcx");
 286   const Register s = rcx;                        // shift count
 287   const int      n = BitsPerWord;
 288   Label L;
 289   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 290   cmpl(s, n);                                    // if (s < n)
 291   jcc(Assembler::less, L);                       // else (s >= n)
 292   movl(lo, hi);                                  // x := x >> n
 293   if (sign_extension) sarl(hi, 31);
 294   else                xorl(hi, hi);
 295   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 296   bind(L);                                       // s (mod n) < n
 297   shrdl(lo, hi);                                 // x := x >> s
 298   if (sign_extension) sarl(hi);
 299   else                shrl(hi);
 300 }
 301 
 302 void MacroAssembler::movoop(Register dst, jobject obj) {
 303   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 304 }
 305 
 306 void MacroAssembler::movoop(Address dst, jobject obj) {
 307   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 308 }
 309 
 310 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 311   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 312 }
 313 
 314 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 315   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 316 }
 317 
 318 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 319   // scratch register is not used,
 320   // it is defined to match parameters of 64-bit version of this method.
 321   if (src.is_lval()) {
 322     mov_literal32(dst, (intptr_t)src.target(), src.rspec());
 323   } else {
 324     movl(dst, as_Address(src));
 325   }
 326 }
 327 
 328 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 329   movl(as_Address(dst), src);
 330 }
 331 
 332 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 333   movl(dst, as_Address(src));
 334 }
 335 
 336 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 337 void MacroAssembler::movptr(Address dst, intptr_t src) {
 338   movl(dst, src);
 339 }
 340 
 341 
 342 void MacroAssembler::pop_callee_saved_registers() {
 343   pop(rcx);
 344   pop(rdx);
 345   pop(rdi);
 346   pop(rsi);
 347 }
 348 
 349 void MacroAssembler::push_callee_saved_registers() {
 350   push(rsi);
 351   push(rdi);
 352   push(rdx);
 353   push(rcx);
 354 }
 355 
 356 void MacroAssembler::pushoop(jobject obj) {
 357   push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
 358 }
 359 
 360 void MacroAssembler::pushklass(Metadata* obj) {
 361   push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
 362 }
 363 
 364 void MacroAssembler::pushptr(AddressLiteral src) {
 365   if (src.is_lval()) {
 366     push_literal32((int32_t)src.target(), src.rspec());
 367   } else {
 368     pushl(as_Address(src));
 369   }
 370 }
 371 
 372 static void pass_arg0(MacroAssembler* masm, Register arg) {
 373   masm->push(arg);
 374 }
 375 
 376 static void pass_arg1(MacroAssembler* masm, Register arg) {
 377   masm->push(arg);
 378 }
 379 
 380 static void pass_arg2(MacroAssembler* masm, Register arg) {
 381   masm->push(arg);
 382 }
 383 
 384 static void pass_arg3(MacroAssembler* masm, Register arg) {
 385   masm->push(arg);
 386 }
 387 
 388 #ifndef PRODUCT
 389 extern "C" void findpc(intptr_t x);
 390 #endif
 391 
 392 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
 393   // In order to get locks to work, we need to fake a in_VM state
 394   JavaThread* thread = JavaThread::current();
 395   JavaThreadState saved_state = thread->thread_state();
 396   thread->set_thread_state(_thread_in_vm);
 397   if (ShowMessageBoxOnError) {
 398     JavaThread* thread = JavaThread::current();
 399     JavaThreadState saved_state = thread->thread_state();
 400     thread->set_thread_state(_thread_in_vm);
 401     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 402       ttyLocker ttyl;
 403       BytecodeCounter::print();
 404     }
 405     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 406     // This is the value of eip which points to where verify_oop will return.
 407     if (os::message_box(msg, "Execution stopped, print registers?")) {
 408       print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
 409       BREAKPOINT;
 410     }
 411   }
 412   fatal("DEBUG MESSAGE: %s", msg);
 413 }
 414 
 415 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
 416   ttyLocker ttyl;
 417   FlagSetting fs(Debugging, true);
 418   tty->print_cr("eip = 0x%08x", eip);
 419 #ifndef PRODUCT
 420   if ((WizardMode || Verbose) && PrintMiscellaneous) {
 421     tty->cr();
 422     findpc(eip);
 423     tty->cr();
 424   }
 425 #endif
 426 #define PRINT_REG(rax) \
 427   { tty->print("%s = ", #rax); os::print_location(tty, rax); }
 428   PRINT_REG(rax);
 429   PRINT_REG(rbx);
 430   PRINT_REG(rcx);
 431   PRINT_REG(rdx);
 432   PRINT_REG(rdi);
 433   PRINT_REG(rsi);
 434   PRINT_REG(rbp);
 435   PRINT_REG(rsp);
 436 #undef PRINT_REG
 437   // Print some words near top of staack.
 438   int* dump_sp = (int*) rsp;
 439   for (int col1 = 0; col1 < 8; col1++) {
 440     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 441     os::print_location(tty, *dump_sp++);
 442   }
 443   for (int row = 0; row < 16; row++) {
 444     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 445     for (int col = 0; col < 8; col++) {
 446       tty->print(" 0x%08x", *dump_sp++);
 447     }
 448     tty->cr();
 449   }
 450   // Print some instructions around pc:
 451   Disassembler::decode((address)eip-64, (address)eip);
 452   tty->print_cr("--------");
 453   Disassembler::decode((address)eip, (address)eip+32);
 454 }
 455 
 456 void MacroAssembler::stop(const char* msg) {
 457   ExternalAddress message((address)msg);
 458   // push address of message
 459   pushptr(message.addr());
 460   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 461   pusha();                                            // push registers
 462   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
 463   hlt();
 464 }
 465 
 466 void MacroAssembler::warn(const char* msg) {
 467   push_CPU_state();
 468 
 469   ExternalAddress message((address) msg);
 470   // push address of message
 471   pushptr(message.addr());
 472 
 473   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
 474   addl(rsp, wordSize);       // discard argument
 475   pop_CPU_state();
 476 }
 477 
 478 void MacroAssembler::print_state() {
 479   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 480   pusha();                                            // push registers
 481 
 482   push_CPU_state();
 483   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
 484   pop_CPU_state();
 485 
 486   popa();
 487   addl(rsp, wordSize);
 488 }
 489 
 490 #else // _LP64
 491 
 492 // 64 bit versions
 493 
 494 Address MacroAssembler::as_Address(AddressLiteral adr) {
 495   // amd64 always does this as a pc-rel
 496   // we can be absolute or disp based on the instruction type
 497   // jmp/call are displacements others are absolute
 498   assert(!adr.is_lval(), "must be rval");
 499   assert(reachable(adr), "must be");
 500   return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
 501 
 502 }
 503 
 504 Address MacroAssembler::as_Address(ArrayAddress adr) {
 505   AddressLiteral base = adr.base();
 506   lea(rscratch1, base);
 507   Address index = adr.index();
 508   assert(index._disp == 0, "must not have disp"); // maybe it can?
 509   Address array(rscratch1, index._index, index._scale, index._disp);
 510   return array;
 511 }
 512 
 513 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
 514   Label L, E;
 515 
 516 #ifdef _WIN64
 517   // Windows always allocates space for it's register args
 518   assert(num_args <= 4, "only register arguments supported");
 519   subq(rsp,  frame::arg_reg_save_area_bytes);
 520 #endif
 521 
 522   // Align stack if necessary
 523   testl(rsp, 15);
 524   jcc(Assembler::zero, L);
 525 
 526   subq(rsp, 8);
 527   {
 528     call(RuntimeAddress(entry_point));
 529   }
 530   addq(rsp, 8);
 531   jmp(E);
 532 
 533   bind(L);
 534   {
 535     call(RuntimeAddress(entry_point));
 536   }
 537 
 538   bind(E);
 539 
 540 #ifdef _WIN64
 541   // restore stack pointer
 542   addq(rsp, frame::arg_reg_save_area_bytes);
 543 #endif
 544 
 545 }
 546 
 547 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
 548   assert(!src2.is_lval(), "should use cmpptr");
 549 
 550   if (reachable(src2)) {
 551     cmpq(src1, as_Address(src2));
 552   } else {
 553     lea(rscratch1, src2);
 554     Assembler::cmpq(src1, Address(rscratch1, 0));
 555   }
 556 }
 557 
 558 int MacroAssembler::corrected_idivq(Register reg) {
 559   // Full implementation of Java ldiv and lrem; checks for special
 560   // case as described in JVM spec., p.243 & p.271.  The function
 561   // returns the (pc) offset of the idivl instruction - may be needed
 562   // for implicit exceptions.
 563   //
 564   //         normal case                           special case
 565   //
 566   // input : rax: dividend                         min_long
 567   //         reg: divisor   (may not be eax/edx)   -1
 568   //
 569   // output: rax: quotient  (= rax idiv reg)       min_long
 570   //         rdx: remainder (= rax irem reg)       0
 571   assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
 572   static const int64_t min_long = 0x8000000000000000;
 573   Label normal_case, special_case;
 574 
 575   // check for special case
 576   cmp64(rax, ExternalAddress((address) &min_long));
 577   jcc(Assembler::notEqual, normal_case);
 578   xorl(rdx, rdx); // prepare rdx for possible special case (where
 579                   // remainder = 0)
 580   cmpq(reg, -1);
 581   jcc(Assembler::equal, special_case);
 582 
 583   // handle normal case
 584   bind(normal_case);
 585   cdqq();
 586   int idivq_offset = offset();
 587   idivq(reg);
 588 
 589   // normal and special case exit
 590   bind(special_case);
 591 
 592   return idivq_offset;
 593 }
 594 
 595 void MacroAssembler::decrementq(Register reg, int value) {
 596   if (value == min_jint) { subq(reg, value); return; }
 597   if (value <  0) { incrementq(reg, -value); return; }
 598   if (value == 0) {                        ; return; }
 599   if (value == 1 && UseIncDec) { decq(reg) ; return; }
 600   /* else */      { subq(reg, value)       ; return; }
 601 }
 602 
 603 void MacroAssembler::decrementq(Address dst, int value) {
 604   if (value == min_jint) { subq(dst, value); return; }
 605   if (value <  0) { incrementq(dst, -value); return; }
 606   if (value == 0) {                        ; return; }
 607   if (value == 1 && UseIncDec) { decq(dst) ; return; }
 608   /* else */      { subq(dst, value)       ; return; }
 609 }
 610 
 611 void MacroAssembler::incrementq(AddressLiteral dst) {
 612   if (reachable(dst)) {
 613     incrementq(as_Address(dst));
 614   } else {
 615     lea(rscratch1, dst);
 616     incrementq(Address(rscratch1, 0));
 617   }
 618 }
 619 
 620 void MacroAssembler::incrementq(Register reg, int value) {
 621   if (value == min_jint) { addq(reg, value); return; }
 622   if (value <  0) { decrementq(reg, -value); return; }
 623   if (value == 0) {                        ; return; }
 624   if (value == 1 && UseIncDec) { incq(reg) ; return; }
 625   /* else */      { addq(reg, value)       ; return; }
 626 }
 627 
 628 void MacroAssembler::incrementq(Address dst, int value) {
 629   if (value == min_jint) { addq(dst, value); return; }
 630   if (value <  0) { decrementq(dst, -value); return; }
 631   if (value == 0) {                        ; return; }
 632   if (value == 1 && UseIncDec) { incq(dst) ; return; }
 633   /* else */      { addq(dst, value)       ; return; }
 634 }
 635 
 636 // 32bit can do a case table jump in one instruction but we no longer allow the base
 637 // to be installed in the Address class
 638 void MacroAssembler::jump(ArrayAddress entry) {
 639   lea(rscratch1, entry.base());
 640   Address dispatch = entry.index();
 641   assert(dispatch._base == noreg, "must be");
 642   dispatch._base = rscratch1;
 643   jmp(dispatch);
 644 }
 645 
 646 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 647   ShouldNotReachHere(); // 64bit doesn't use two regs
 648   cmpq(x_lo, y_lo);
 649 }
 650 
 651 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 652     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 653 }
 654 
 655 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 656   mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
 657   movptr(dst, rscratch1);
 658 }
 659 
 660 void MacroAssembler::leave() {
 661   // %%% is this really better? Why not on 32bit too?
 662   emit_int8((unsigned char)0xC9); // LEAVE
 663 }
 664 
 665 void MacroAssembler::lneg(Register hi, Register lo) {
 666   ShouldNotReachHere(); // 64bit doesn't use two regs
 667   negq(lo);
 668 }
 669 
 670 void MacroAssembler::movoop(Register dst, jobject obj) {
 671   mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 672 }
 673 
 674 void MacroAssembler::movoop(Address dst, jobject obj) {
 675   mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 676   movq(dst, rscratch1);
 677 }
 678 
 679 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 680   mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 681 }
 682 
 683 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 684   mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 685   movq(dst, rscratch1);
 686 }
 687 
 688 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 689   if (src.is_lval()) {
 690     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 691   } else {
 692     if (reachable(src)) {
 693       movq(dst, as_Address(src));
 694     } else {
 695       lea(scratch, src);
 696       movq(dst, Address(scratch, 0));
 697     }
 698   }
 699 }
 700 
 701 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 702   movq(as_Address(dst), src);
 703 }
 704 
 705 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 706   movq(dst, as_Address(src));
 707 }
 708 
 709 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 710 void MacroAssembler::movptr(Address dst, intptr_t src) {
 711   if (is_simm32(src)) {
 712     movptr(dst, checked_cast<int32_t>(src));
 713   } else {
 714     mov64(rscratch1, src);
 715     movq(dst, rscratch1);
 716   }
 717 }
 718 
 719 // These are mostly for initializing NULL
 720 void MacroAssembler::movptr(Address dst, int32_t src) {
 721   movslq(dst, src);
 722 }
 723 
 724 void MacroAssembler::movptr(Register dst, int32_t src) {
 725   mov64(dst, (intptr_t)src);
 726 }
 727 
 728 void MacroAssembler::pushoop(jobject obj) {
 729   movoop(rscratch1, obj);
 730   push(rscratch1);
 731 }
 732 
 733 void MacroAssembler::pushklass(Metadata* obj) {
 734   mov_metadata(rscratch1, obj);
 735   push(rscratch1);
 736 }
 737 
 738 void MacroAssembler::pushptr(AddressLiteral src) {
 739   lea(rscratch1, src);
 740   if (src.is_lval()) {
 741     push(rscratch1);
 742   } else {
 743     pushq(Address(rscratch1, 0));
 744   }
 745 }
 746 
 747 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
 748   reset_last_Java_frame(r15_thread, clear_fp);
 749 }
 750 
 751 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 752                                          Register last_java_fp,
 753                                          address  last_java_pc) {
 754   vzeroupper();
 755   // determine last_java_sp register
 756   if (!last_java_sp->is_valid()) {
 757     last_java_sp = rsp;
 758   }
 759 
 760   // last_java_fp is optional
 761   if (last_java_fp->is_valid()) {
 762     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
 763            last_java_fp);
 764   }
 765 
 766   // last_java_pc is optional
 767   if (last_java_pc != NULL) {
 768     Address java_pc(r15_thread,
 769                     JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
 770     lea(rscratch1, InternalAddress(last_java_pc));
 771     movptr(java_pc, rscratch1);
 772   }
 773 
 774   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
 775 }
 776 
 777 static void pass_arg0(MacroAssembler* masm, Register arg) {
 778   if (c_rarg0 != arg ) {
 779     masm->mov(c_rarg0, arg);
 780   }
 781 }
 782 
 783 static void pass_arg1(MacroAssembler* masm, Register arg) {
 784   if (c_rarg1 != arg ) {
 785     masm->mov(c_rarg1, arg);
 786   }
 787 }
 788 
 789 static void pass_arg2(MacroAssembler* masm, Register arg) {
 790   if (c_rarg2 != arg ) {
 791     masm->mov(c_rarg2, arg);
 792   }
 793 }
 794 
 795 static void pass_arg3(MacroAssembler* masm, Register arg) {
 796   if (c_rarg3 != arg ) {
 797     masm->mov(c_rarg3, arg);
 798   }
 799 }
 800 
 801 void MacroAssembler::stop(const char* msg) {
 802   if (ShowMessageBoxOnError) {
 803     address rip = pc();
 804     pusha(); // get regs on stack
 805     lea(c_rarg1, InternalAddress(rip));
 806     movq(c_rarg2, rsp); // pass pointer to regs array
 807   }
 808   lea(c_rarg0, ExternalAddress((address) msg));
 809   andq(rsp, -16); // align stack as required by ABI
 810   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
 811   hlt();
 812 }
 813 
 814 void MacroAssembler::warn(const char* msg) {
 815   push(rbp);
 816   movq(rbp, rsp);
 817   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 818   push_CPU_state();   // keeps alignment at 16 bytes
 819   lea(c_rarg0, ExternalAddress((address) msg));
 820   lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
 821   call(rax);
 822   pop_CPU_state();
 823   mov(rsp, rbp);
 824   pop(rbp);
 825 }
 826 
 827 void MacroAssembler::print_state() {
 828   address rip = pc();
 829   pusha();            // get regs on stack
 830   push(rbp);
 831   movq(rbp, rsp);
 832   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 833   push_CPU_state();   // keeps alignment at 16 bytes
 834 
 835   lea(c_rarg0, InternalAddress(rip));
 836   lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
 837   call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
 838 
 839   pop_CPU_state();
 840   mov(rsp, rbp);
 841   pop(rbp);
 842   popa();
 843 }
 844 
 845 #ifndef PRODUCT
 846 extern "C" void findpc(intptr_t x);
 847 #endif
 848 
 849 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
 850   // In order to get locks to work, we need to fake a in_VM state
 851   if (ShowMessageBoxOnError) {
 852     JavaThread* thread = JavaThread::current();
 853     JavaThreadState saved_state = thread->thread_state();
 854     thread->set_thread_state(_thread_in_vm);
 855 #ifndef PRODUCT
 856     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 857       ttyLocker ttyl;
 858       BytecodeCounter::print();
 859     }
 860 #endif
 861     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 862     // XXX correct this offset for amd64
 863     // This is the value of eip which points to where verify_oop will return.
 864     if (os::message_box(msg, "Execution stopped, print registers?")) {
 865       print_state64(pc, regs);
 866       BREAKPOINT;
 867     }
 868   }
 869   fatal("DEBUG MESSAGE: %s", msg);
 870 }
 871 
 872 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
 873   ttyLocker ttyl;
 874   FlagSetting fs(Debugging, true);
 875   tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
 876 #ifndef PRODUCT
 877   tty->cr();
 878   findpc(pc);
 879   tty->cr();
 880 #endif
 881 #define PRINT_REG(rax, value) \
 882   { tty->print("%s = ", #rax); os::print_location(tty, value); }
 883   PRINT_REG(rax, regs[15]);
 884   PRINT_REG(rbx, regs[12]);
 885   PRINT_REG(rcx, regs[14]);
 886   PRINT_REG(rdx, regs[13]);
 887   PRINT_REG(rdi, regs[8]);
 888   PRINT_REG(rsi, regs[9]);
 889   PRINT_REG(rbp, regs[10]);
 890   // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
 891   PRINT_REG(rsp, (intptr_t)(&regs[16]));
 892   PRINT_REG(r8 , regs[7]);
 893   PRINT_REG(r9 , regs[6]);
 894   PRINT_REG(r10, regs[5]);
 895   PRINT_REG(r11, regs[4]);
 896   PRINT_REG(r12, regs[3]);
 897   PRINT_REG(r13, regs[2]);
 898   PRINT_REG(r14, regs[1]);
 899   PRINT_REG(r15, regs[0]);
 900 #undef PRINT_REG
 901   // Print some words near the top of the stack.
 902   int64_t* rsp = &regs[16];
 903   int64_t* dump_sp = rsp;
 904   for (int col1 = 0; col1 < 8; col1++) {
 905     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 906     os::print_location(tty, *dump_sp++);
 907   }
 908   for (int row = 0; row < 25; row++) {
 909     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 910     for (int col = 0; col < 4; col++) {
 911       tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
 912     }
 913     tty->cr();
 914   }
 915   // Print some instructions around pc:
 916   Disassembler::decode((address)pc-64, (address)pc);
 917   tty->print_cr("--------");
 918   Disassembler::decode((address)pc, (address)pc+32);
 919 }
 920 
 921 // The java_calling_convention describes stack locations as ideal slots on
 922 // a frame with no abi restrictions. Since we must observe abi restrictions
 923 // (like the placement of the register window) the slots must be biased by
 924 // the following value.
 925 static int reg2offset_in(VMReg r) {
 926   // Account for saved rbp and return address
 927   // This should really be in_preserve_stack_slots
 928   return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
 929 }
 930 
 931 static int reg2offset_out(VMReg r) {
 932   return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
 933 }
 934 
 935 // A long move
 936 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst) {
 937 
 938   // The calling conventions assures us that each VMregpair is either
 939   // all really one physical register or adjacent stack slots.
 940 
 941   if (src.is_single_phys_reg() ) {
 942     if (dst.is_single_phys_reg()) {
 943       if (dst.first() != src.first()) {
 944         mov(dst.first()->as_Register(), src.first()->as_Register());
 945       }
 946     } else {
 947       assert(dst.is_single_reg(), "not a stack pair");
 948       movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
 949     }
 950   } else if (dst.is_single_phys_reg()) {
 951     assert(src.is_single_reg(),  "not a stack pair");
 952     movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
 953   } else {
 954     assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
 955     movq(rax, Address(rbp, reg2offset_in(src.first())));
 956     movq(Address(rsp, reg2offset_out(dst.first())), rax);
 957   }
 958 }
 959 
 960 // A double move
 961 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst) {
 962 
 963   // The calling conventions assures us that each VMregpair is either
 964   // all really one physical register or adjacent stack slots.
 965 
 966   if (src.is_single_phys_reg() ) {
 967     if (dst.is_single_phys_reg()) {
 968       // In theory these overlap but the ordering is such that this is likely a nop
 969       if ( src.first() != dst.first()) {
 970         movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
 971       }
 972     } else {
 973       assert(dst.is_single_reg(), "not a stack pair");
 974       movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
 975     }
 976   } else if (dst.is_single_phys_reg()) {
 977     assert(src.is_single_reg(),  "not a stack pair");
 978     movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
 979   } else {
 980     assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
 981     movq(rax, Address(rbp, reg2offset_in(src.first())));
 982     movq(Address(rsp, reg2offset_out(dst.first())), rax);
 983   }
 984 }
 985 
 986 
 987 // A float arg may have to do float reg int reg conversion
 988 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst) {
 989   assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
 990 
 991   // The calling conventions assures us that each VMregpair is either
 992   // all really one physical register or adjacent stack slots.
 993 
 994   if (src.first()->is_stack()) {
 995     if (dst.first()->is_stack()) {
 996       movl(rax, Address(rbp, reg2offset_in(src.first())));
 997       movptr(Address(rsp, reg2offset_out(dst.first())), rax);
 998     } else {
 999       // stack to reg
1000       assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1001       movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
1002     }
1003   } else if (dst.first()->is_stack()) {
1004     // reg to stack
1005     assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1006     movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1007   } else {
1008     // reg to reg
1009     // In theory these overlap but the ordering is such that this is likely a nop
1010     if ( src.first() != dst.first()) {
1011       movdbl(dst.first()->as_XMMRegister(),  src.first()->as_XMMRegister());
1012     }
1013   }
1014 }
1015 
1016 // On 64 bit we will store integer like items to the stack as
1017 // 64 bits items (x86_32/64 abi) even though java would only store
1018 // 32bits for a parameter. On 32bit it will simply be 32 bits
1019 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1020 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst) {
1021   if (src.first()->is_stack()) {
1022     if (dst.first()->is_stack()) {
1023       // stack to stack
1024       movslq(rax, Address(rbp, reg2offset_in(src.first())));
1025       movq(Address(rsp, reg2offset_out(dst.first())), rax);
1026     } else {
1027       // stack to reg
1028       movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1029     }
1030   } else if (dst.first()->is_stack()) {
1031     // reg to stack
1032     // Do we really have to sign extend???
1033     // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1034     movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1035   } else {
1036     // Do we really have to sign extend???
1037     // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1038     if (dst.first() != src.first()) {
1039       movq(dst.first()->as_Register(), src.first()->as_Register());
1040     }
1041   }
1042 }
1043 
1044 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1045   if (src.first()->is_stack()) {
1046     if (dst.first()->is_stack()) {
1047       // stack to stack
1048       movq(rax, Address(rbp, reg2offset_in(src.first())));
1049       movq(Address(rsp, reg2offset_out(dst.first())), rax);
1050     } else {
1051       // stack to reg
1052       movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1053     }
1054   } else if (dst.first()->is_stack()) {
1055     // reg to stack
1056     movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1057   } else {
1058     if (dst.first() != src.first()) {
1059       movq(dst.first()->as_Register(), src.first()->as_Register());
1060     }
1061   }
1062 }
1063 
1064 // An oop arg. Must pass a handle not the oop itself
1065 void MacroAssembler::object_move(OopMap* map,
1066                         int oop_handle_offset,
1067                         int framesize_in_slots,
1068                         VMRegPair src,
1069                         VMRegPair dst,
1070                         bool is_receiver,
1071                         int* receiver_offset) {
1072 
1073   // must pass a handle. First figure out the location we use as a handle
1074 
1075   Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1076 
1077   // See if oop is NULL if it is we need no handle
1078 
1079   if (src.first()->is_stack()) {
1080 
1081     // Oop is already on the stack as an argument
1082     int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1083     map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1084     if (is_receiver) {
1085       *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1086     }
1087 
1088     cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
1089     lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1090     // conditionally move a NULL
1091     cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1092   } else {
1093 
1094     // Oop is in an a register we must store it to the space we reserve
1095     // on the stack for oop_handles and pass a handle if oop is non-NULL
1096 
1097     const Register rOop = src.first()->as_Register();
1098     int oop_slot;
1099     if (rOop == j_rarg0)
1100       oop_slot = 0;
1101     else if (rOop == j_rarg1)
1102       oop_slot = 1;
1103     else if (rOop == j_rarg2)
1104       oop_slot = 2;
1105     else if (rOop == j_rarg3)
1106       oop_slot = 3;
1107     else if (rOop == j_rarg4)
1108       oop_slot = 4;
1109     else {
1110       assert(rOop == j_rarg5, "wrong register");
1111       oop_slot = 5;
1112     }
1113 
1114     oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1115     int offset = oop_slot*VMRegImpl::stack_slot_size;
1116 
1117     map->set_oop(VMRegImpl::stack2reg(oop_slot));
1118     // Store oop in handle area, may be NULL
1119     movptr(Address(rsp, offset), rOop);
1120     if (is_receiver) {
1121       *receiver_offset = offset;
1122     }
1123 
1124     cmpptr(rOop, (int32_t)NULL_WORD);
1125     lea(rHandle, Address(rsp, offset));
1126     // conditionally move a NULL from the handle area where it was just stored
1127     cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1128   }
1129 
1130   // If arg is on the stack then place it otherwise it is already in correct reg.
1131   if (dst.first()->is_stack()) {
1132     movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1133   }
1134 }
1135 
1136 #endif // _LP64
1137 
1138 // Now versions that are common to 32/64 bit
1139 
1140 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1141   LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1142 }
1143 
1144 void MacroAssembler::addptr(Register dst, Register src) {
1145   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1146 }
1147 
1148 void MacroAssembler::addptr(Address dst, Register src) {
1149   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1150 }
1151 
1152 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
1153   if (reachable(src)) {
1154     Assembler::addsd(dst, as_Address(src));
1155   } else {
1156     lea(rscratch1, src);
1157     Assembler::addsd(dst, Address(rscratch1, 0));
1158   }
1159 }
1160 
1161 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
1162   if (reachable(src)) {
1163     addss(dst, as_Address(src));
1164   } else {
1165     lea(rscratch1, src);
1166     addss(dst, Address(rscratch1, 0));
1167   }
1168 }
1169 
1170 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
1171   if (reachable(src)) {
1172     Assembler::addpd(dst, as_Address(src));
1173   } else {
1174     lea(rscratch1, src);
1175     Assembler::addpd(dst, Address(rscratch1, 0));
1176   }
1177 }
1178 
1179 // See 8273459.  Function for ensuring 64-byte alignment, intended for stubs only.
1180 // Stub code is generated once and never copied.
1181 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1182 void MacroAssembler::align64() {
1183   align(64, (unsigned long long) pc());
1184 }
1185 
1186 void MacroAssembler::align32() {
1187   align(32, (unsigned long long) pc());
1188 }
1189 
1190 void MacroAssembler::align(int modulus) {
1191   // 8273459: Ensure alignment is possible with current segment alignment
1192   assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1193   align(modulus, offset());
1194 }
1195 
1196 void MacroAssembler::align(int modulus, int target) {
1197   if (target % modulus != 0) {
1198     nop(modulus - (target % modulus));
1199   }
1200 }
1201 
1202 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1203   // Used in sign-masking with aligned address.
1204   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1205   if (reachable(src)) {
1206     Assembler::andpd(dst, as_Address(src));
1207   } else {
1208     lea(scratch_reg, src);
1209     Assembler::andpd(dst, Address(scratch_reg, 0));
1210   }
1211 }
1212 
1213 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1214   // Used in sign-masking with aligned address.
1215   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1216   if (reachable(src)) {
1217     Assembler::andps(dst, as_Address(src));
1218   } else {
1219     lea(scratch_reg, src);
1220     Assembler::andps(dst, Address(scratch_reg, 0));
1221   }
1222 }
1223 
1224 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1225   LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1226 }
1227 
1228 void MacroAssembler::atomic_incl(Address counter_addr) {
1229   lock();
1230   incrementl(counter_addr);
1231 }
1232 
1233 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1234   if (reachable(counter_addr)) {
1235     atomic_incl(as_Address(counter_addr));
1236   } else {
1237     lea(scr, counter_addr);
1238     atomic_incl(Address(scr, 0));
1239   }
1240 }
1241 
1242 #ifdef _LP64
1243 void MacroAssembler::atomic_incq(Address counter_addr) {
1244   lock();
1245   incrementq(counter_addr);
1246 }
1247 
1248 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1249   if (reachable(counter_addr)) {
1250     atomic_incq(as_Address(counter_addr));
1251   } else {
1252     lea(scr, counter_addr);
1253     atomic_incq(Address(scr, 0));
1254   }
1255 }
1256 #endif
1257 
1258 // Writes to stack successive pages until offset reached to check for
1259 // stack overflow + shadow pages.  This clobbers tmp.
1260 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1261   movptr(tmp, rsp);
1262   // Bang stack for total size given plus shadow page size.
1263   // Bang one page at a time because large size can bang beyond yellow and
1264   // red zones.
1265   Label loop;
1266   bind(loop);
1267   movl(Address(tmp, (-os::vm_page_size())), size );
1268   subptr(tmp, os::vm_page_size());
1269   subl(size, os::vm_page_size());
1270   jcc(Assembler::greater, loop);
1271 
1272   // Bang down shadow pages too.
1273   // At this point, (tmp-0) is the last address touched, so don't
1274   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
1275   // was post-decremented.)  Skip this address by starting at i=1, and
1276   // touch a few more pages below.  N.B.  It is important to touch all
1277   // the way down including all pages in the shadow zone.
1278   for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1279     // this could be any sized move but this is can be a debugging crumb
1280     // so the bigger the better.
1281     movptr(Address(tmp, (-i*os::vm_page_size())), size );
1282   }
1283 }
1284 
1285 void MacroAssembler::reserved_stack_check() {
1286     // testing if reserved zone needs to be enabled
1287     Label no_reserved_zone_enabling;
1288     Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1289     NOT_LP64(get_thread(rsi);)
1290 
1291     cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1292     jcc(Assembler::below, no_reserved_zone_enabling);
1293 
1294     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1295     jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1296     should_not_reach_here();
1297 
1298     bind(no_reserved_zone_enabling);
1299 }
1300 
1301 void MacroAssembler::c2bool(Register x) {
1302   // implements x == 0 ? 0 : 1
1303   // note: must only look at least-significant byte of x
1304   //       since C-style booleans are stored in one byte
1305   //       only! (was bug)
1306   andl(x, 0xFF);
1307   setb(Assembler::notZero, x);
1308 }
1309 
1310 // Wouldn't need if AddressLiteral version had new name
1311 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1312   Assembler::call(L, rtype);
1313 }
1314 
1315 void MacroAssembler::call(Register entry) {
1316   Assembler::call(entry);
1317 }
1318 
1319 void MacroAssembler::call(AddressLiteral entry) {
1320   if (reachable(entry)) {
1321     Assembler::call_literal(entry.target(), entry.rspec());
1322   } else {
1323     lea(rscratch1, entry);
1324     Assembler::call(rscratch1);
1325   }
1326 }
1327 
1328 void MacroAssembler::ic_call(address entry, jint method_index) {
1329   RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1330   movptr(rax, (intptr_t)Universe::non_oop_word());
1331   call(AddressLiteral(entry, rh));
1332 }
1333 
1334 // Implementation of call_VM versions
1335 
1336 void MacroAssembler::call_VM(Register oop_result,
1337                              address entry_point,
1338                              bool check_exceptions) {
1339   Label C, E;
1340   call(C, relocInfo::none);
1341   jmp(E);
1342 
1343   bind(C);
1344   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1345   ret(0);
1346 
1347   bind(E);
1348 }
1349 
1350 void MacroAssembler::call_VM(Register oop_result,
1351                              address entry_point,
1352                              Register arg_1,
1353                              bool check_exceptions) {
1354   Label C, E;
1355   call(C, relocInfo::none);
1356   jmp(E);
1357 
1358   bind(C);
1359   pass_arg1(this, arg_1);
1360   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1361   ret(0);
1362 
1363   bind(E);
1364 }
1365 
1366 void MacroAssembler::call_VM(Register oop_result,
1367                              address entry_point,
1368                              Register arg_1,
1369                              Register arg_2,
1370                              bool check_exceptions) {
1371   Label C, E;
1372   call(C, relocInfo::none);
1373   jmp(E);
1374 
1375   bind(C);
1376 
1377   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1378 
1379   pass_arg2(this, arg_2);
1380   pass_arg1(this, arg_1);
1381   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1382   ret(0);
1383 
1384   bind(E);
1385 }
1386 
1387 void MacroAssembler::call_VM(Register oop_result,
1388                              address entry_point,
1389                              Register arg_1,
1390                              Register arg_2,
1391                              Register arg_3,
1392                              bool check_exceptions) {
1393   Label C, E;
1394   call(C, relocInfo::none);
1395   jmp(E);
1396 
1397   bind(C);
1398 
1399   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1400   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1401   pass_arg3(this, arg_3);
1402 
1403   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1404   pass_arg2(this, arg_2);
1405 
1406   pass_arg1(this, arg_1);
1407   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1408   ret(0);
1409 
1410   bind(E);
1411 }
1412 
1413 void MacroAssembler::call_VM(Register oop_result,
1414                              Register last_java_sp,
1415                              address entry_point,
1416                              int number_of_arguments,
1417                              bool check_exceptions) {
1418   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1419   call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1420 }
1421 
1422 void MacroAssembler::call_VM(Register oop_result,
1423                              Register last_java_sp,
1424                              address entry_point,
1425                              Register arg_1,
1426                              bool check_exceptions) {
1427   pass_arg1(this, arg_1);
1428   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1429 }
1430 
1431 void MacroAssembler::call_VM(Register oop_result,
1432                              Register last_java_sp,
1433                              address entry_point,
1434                              Register arg_1,
1435                              Register arg_2,
1436                              bool check_exceptions) {
1437 
1438   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1439   pass_arg2(this, arg_2);
1440   pass_arg1(this, arg_1);
1441   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1442 }
1443 
1444 void MacroAssembler::call_VM(Register oop_result,
1445                              Register last_java_sp,
1446                              address entry_point,
1447                              Register arg_1,
1448                              Register arg_2,
1449                              Register arg_3,
1450                              bool check_exceptions) {
1451   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1452   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1453   pass_arg3(this, arg_3);
1454   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1455   pass_arg2(this, arg_2);
1456   pass_arg1(this, arg_1);
1457   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1458 }
1459 
1460 void MacroAssembler::super_call_VM(Register oop_result,
1461                                    Register last_java_sp,
1462                                    address entry_point,
1463                                    int number_of_arguments,
1464                                    bool check_exceptions) {
1465   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1466   MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1467 }
1468 
1469 void MacroAssembler::super_call_VM(Register oop_result,
1470                                    Register last_java_sp,
1471                                    address entry_point,
1472                                    Register arg_1,
1473                                    bool check_exceptions) {
1474   pass_arg1(this, arg_1);
1475   super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1476 }
1477 
1478 void MacroAssembler::super_call_VM(Register oop_result,
1479                                    Register last_java_sp,
1480                                    address entry_point,
1481                                    Register arg_1,
1482                                    Register arg_2,
1483                                    bool check_exceptions) {
1484 
1485   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1486   pass_arg2(this, arg_2);
1487   pass_arg1(this, arg_1);
1488   super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1489 }
1490 
1491 void MacroAssembler::super_call_VM(Register oop_result,
1492                                    Register last_java_sp,
1493                                    address entry_point,
1494                                    Register arg_1,
1495                                    Register arg_2,
1496                                    Register arg_3,
1497                                    bool check_exceptions) {
1498   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1499   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1500   pass_arg3(this, arg_3);
1501   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1502   pass_arg2(this, arg_2);
1503   pass_arg1(this, arg_1);
1504   super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1505 }
1506 
1507 void MacroAssembler::call_VM_base(Register oop_result,
1508                                   Register java_thread,
1509                                   Register last_java_sp,
1510                                   address  entry_point,
1511                                   int      number_of_arguments,
1512                                   bool     check_exceptions) {
1513   // determine java_thread register
1514   if (!java_thread->is_valid()) {
1515 #ifdef _LP64
1516     java_thread = r15_thread;
1517 #else
1518     java_thread = rdi;
1519     get_thread(java_thread);
1520 #endif // LP64
1521   }
1522   // determine last_java_sp register
1523   if (!last_java_sp->is_valid()) {
1524     last_java_sp = rsp;
1525   }
1526   // debugging support
1527   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
1528   LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1529 #ifdef ASSERT
1530   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1531   // r12 is the heapbase.
1532   LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1533 #endif // ASSERT
1534 
1535   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
1536   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1537 
1538   // push java thread (becomes first argument of C function)
1539 
1540   NOT_LP64(push(java_thread); number_of_arguments++);
1541   LP64_ONLY(mov(c_rarg0, r15_thread));
1542 
1543   // set last Java frame before call
1544   assert(last_java_sp != rbp, "can't use ebp/rbp");
1545 
1546   // Only interpreter should have to set fp
1547   set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
1548 
1549   // do the call, remove parameters
1550   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1551 
1552   // restore the thread (cannot use the pushed argument since arguments
1553   // may be overwritten by C code generated by an optimizing compiler);
1554   // however can use the register value directly if it is callee saved.
1555   if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1556     // rdi & rsi (also r15) are callee saved -> nothing to do
1557 #ifdef ASSERT
1558     guarantee(java_thread != rax, "change this code");
1559     push(rax);
1560     { Label L;
1561       get_thread(rax);
1562       cmpptr(java_thread, rax);
1563       jcc(Assembler::equal, L);
1564       STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1565       bind(L);
1566     }
1567     pop(rax);
1568 #endif
1569   } else {
1570     get_thread(java_thread);
1571   }
1572   // reset last Java frame
1573   // Only interpreter should have to clear fp
1574   reset_last_Java_frame(java_thread, true);
1575 
1576    // C++ interp handles this in the interpreter
1577   check_and_handle_popframe(java_thread);
1578   check_and_handle_earlyret(java_thread);
1579 
1580   if (check_exceptions) {
1581     // check for pending exceptions (java_thread is set upon return)
1582     cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
1583 #ifndef _LP64
1584     jump_cc(Assembler::notEqual,
1585             RuntimeAddress(StubRoutines::forward_exception_entry()));
1586 #else
1587     // This used to conditionally jump to forward_exception however it is
1588     // possible if we relocate that the branch will not reach. So we must jump
1589     // around so we can always reach
1590 
1591     Label ok;
1592     jcc(Assembler::equal, ok);
1593     jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1594     bind(ok);
1595 #endif // LP64
1596   }
1597 
1598   // get oop result if there is one and reset the value in the thread
1599   if (oop_result->is_valid()) {
1600     get_vm_result(oop_result, java_thread);
1601   }
1602 }
1603 
1604 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1605 
1606   // Calculate the value for last_Java_sp
1607   // somewhat subtle. call_VM does an intermediate call
1608   // which places a return address on the stack just under the
1609   // stack pointer as the user finsihed with it. This allows
1610   // use to retrieve last_Java_pc from last_Java_sp[-1].
1611   // On 32bit we then have to push additional args on the stack to accomplish
1612   // the actual requested call. On 64bit call_VM only can use register args
1613   // so the only extra space is the return address that call_VM created.
1614   // This hopefully explains the calculations here.
1615 
1616 #ifdef _LP64
1617   // We've pushed one address, correct last_Java_sp
1618   lea(rax, Address(rsp, wordSize));
1619 #else
1620   lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1621 #endif // LP64
1622 
1623   call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1624 
1625 }
1626 
1627 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1628 void MacroAssembler::call_VM_leaf0(address entry_point) {
1629   MacroAssembler::call_VM_leaf_base(entry_point, 0);
1630 }
1631 
1632 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1633   call_VM_leaf_base(entry_point, number_of_arguments);
1634 }
1635 
1636 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1637   pass_arg0(this, arg_0);
1638   call_VM_leaf(entry_point, 1);
1639 }
1640 
1641 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1642 
1643   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1644   pass_arg1(this, arg_1);
1645   pass_arg0(this, arg_0);
1646   call_VM_leaf(entry_point, 2);
1647 }
1648 
1649 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1650   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1651   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1652   pass_arg2(this, arg_2);
1653   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1654   pass_arg1(this, arg_1);
1655   pass_arg0(this, arg_0);
1656   call_VM_leaf(entry_point, 3);
1657 }
1658 
1659 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1660   MacroAssembler::call_VM_leaf_base(entry_point, 1);
1661 }
1662 
1663 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1664   pass_arg0(this, arg_0);
1665   MacroAssembler::call_VM_leaf_base(entry_point, 1);
1666 }
1667 
1668 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1669 
1670   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1671   pass_arg1(this, arg_1);
1672   pass_arg0(this, arg_0);
1673   MacroAssembler::call_VM_leaf_base(entry_point, 2);
1674 }
1675 
1676 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1677   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1678   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1679   pass_arg2(this, arg_2);
1680   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1681   pass_arg1(this, arg_1);
1682   pass_arg0(this, arg_0);
1683   MacroAssembler::call_VM_leaf_base(entry_point, 3);
1684 }
1685 
1686 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1687   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
1688   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1689   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1690   pass_arg3(this, arg_3);
1691   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1692   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1693   pass_arg2(this, arg_2);
1694   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1695   pass_arg1(this, arg_1);
1696   pass_arg0(this, arg_0);
1697   MacroAssembler::call_VM_leaf_base(entry_point, 4);
1698 }
1699 
1700 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1701   movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1702   movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1703   verify_oop_msg(oop_result, "broken oop in call_VM_base");
1704 }
1705 
1706 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1707   movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1708   movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1709 }
1710 
1711 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1712 }
1713 
1714 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1715 }
1716 
1717 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
1718   if (reachable(src1)) {
1719     cmpl(as_Address(src1), imm);
1720   } else {
1721     lea(rscratch1, src1);
1722     cmpl(Address(rscratch1, 0), imm);
1723   }
1724 }
1725 
1726 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
1727   assert(!src2.is_lval(), "use cmpptr");
1728   if (reachable(src2)) {
1729     cmpl(src1, as_Address(src2));
1730   } else {
1731     lea(rscratch1, src2);
1732     cmpl(src1, Address(rscratch1, 0));
1733   }
1734 }
1735 
1736 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1737   Assembler::cmpl(src1, imm);
1738 }
1739 
1740 void MacroAssembler::cmp32(Register src1, Address src2) {
1741   Assembler::cmpl(src1, src2);
1742 }
1743 
1744 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1745   ucomisd(opr1, opr2);
1746 
1747   Label L;
1748   if (unordered_is_less) {
1749     movl(dst, -1);
1750     jcc(Assembler::parity, L);
1751     jcc(Assembler::below , L);
1752     movl(dst, 0);
1753     jcc(Assembler::equal , L);
1754     increment(dst);
1755   } else { // unordered is greater
1756     movl(dst, 1);
1757     jcc(Assembler::parity, L);
1758     jcc(Assembler::above , L);
1759     movl(dst, 0);
1760     jcc(Assembler::equal , L);
1761     decrementl(dst);
1762   }
1763   bind(L);
1764 }
1765 
1766 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1767   ucomiss(opr1, opr2);
1768 
1769   Label L;
1770   if (unordered_is_less) {
1771     movl(dst, -1);
1772     jcc(Assembler::parity, L);
1773     jcc(Assembler::below , L);
1774     movl(dst, 0);
1775     jcc(Assembler::equal , L);
1776     increment(dst);
1777   } else { // unordered is greater
1778     movl(dst, 1);
1779     jcc(Assembler::parity, L);
1780     jcc(Assembler::above , L);
1781     movl(dst, 0);
1782     jcc(Assembler::equal , L);
1783     decrementl(dst);
1784   }
1785   bind(L);
1786 }
1787 
1788 
1789 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
1790   if (reachable(src1)) {
1791     cmpb(as_Address(src1), imm);
1792   } else {
1793     lea(rscratch1, src1);
1794     cmpb(Address(rscratch1, 0), imm);
1795   }
1796 }
1797 
1798 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
1799 #ifdef _LP64
1800   if (src2.is_lval()) {
1801     movptr(rscratch1, src2);
1802     Assembler::cmpq(src1, rscratch1);
1803   } else if (reachable(src2)) {
1804     cmpq(src1, as_Address(src2));
1805   } else {
1806     lea(rscratch1, src2);
1807     Assembler::cmpq(src1, Address(rscratch1, 0));
1808   }
1809 #else
1810   if (src2.is_lval()) {
1811     cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1812   } else {
1813     cmpl(src1, as_Address(src2));
1814   }
1815 #endif // _LP64
1816 }
1817 
1818 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
1819   assert(src2.is_lval(), "not a mem-mem compare");
1820 #ifdef _LP64
1821   // moves src2's literal address
1822   movptr(rscratch1, src2);
1823   Assembler::cmpq(src1, rscratch1);
1824 #else
1825   cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1826 #endif // _LP64
1827 }
1828 
1829 void MacroAssembler::cmpoop(Register src1, Register src2) {
1830   cmpptr(src1, src2);
1831 }
1832 
1833 void MacroAssembler::cmpoop(Register src1, Address src2) {
1834   cmpptr(src1, src2);
1835 }
1836 
1837 #ifdef _LP64
1838 void MacroAssembler::cmpoop(Register src1, jobject src2) {
1839   movoop(rscratch1, src2);
1840   cmpptr(src1, rscratch1);
1841 }
1842 #endif
1843 
1844 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
1845   if (reachable(adr)) {
1846     lock();
1847     cmpxchgptr(reg, as_Address(adr));
1848   } else {
1849     lea(rscratch1, adr);
1850     lock();
1851     cmpxchgptr(reg, Address(rscratch1, 0));
1852   }
1853 }
1854 
1855 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1856   LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1857 }
1858 
1859 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
1860   if (reachable(src)) {
1861     Assembler::comisd(dst, as_Address(src));
1862   } else {
1863     lea(rscratch1, src);
1864     Assembler::comisd(dst, Address(rscratch1, 0));
1865   }
1866 }
1867 
1868 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
1869   if (reachable(src)) {
1870     Assembler::comiss(dst, as_Address(src));
1871   } else {
1872     lea(rscratch1, src);
1873     Assembler::comiss(dst, Address(rscratch1, 0));
1874   }
1875 }
1876 
1877 
1878 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
1879   Condition negated_cond = negate_condition(cond);
1880   Label L;
1881   jcc(negated_cond, L);
1882   pushf(); // Preserve flags
1883   atomic_incl(counter_addr);
1884   popf();
1885   bind(L);
1886 }
1887 
1888 int MacroAssembler::corrected_idivl(Register reg) {
1889   // Full implementation of Java idiv and irem; checks for
1890   // special case as described in JVM spec., p.243 & p.271.
1891   // The function returns the (pc) offset of the idivl
1892   // instruction - may be needed for implicit exceptions.
1893   //
1894   //         normal case                           special case
1895   //
1896   // input : rax,: dividend                         min_int
1897   //         reg: divisor   (may not be rax,/rdx)   -1
1898   //
1899   // output: rax,: quotient  (= rax, idiv reg)       min_int
1900   //         rdx: remainder (= rax, irem reg)       0
1901   assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1902   const int min_int = 0x80000000;
1903   Label normal_case, special_case;
1904 
1905   // check for special case
1906   cmpl(rax, min_int);
1907   jcc(Assembler::notEqual, normal_case);
1908   xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1909   cmpl(reg, -1);
1910   jcc(Assembler::equal, special_case);
1911 
1912   // handle normal case
1913   bind(normal_case);
1914   cdql();
1915   int idivl_offset = offset();
1916   idivl(reg);
1917 
1918   // normal and special case exit
1919   bind(special_case);
1920 
1921   return idivl_offset;
1922 }
1923 
1924 
1925 
1926 void MacroAssembler::decrementl(Register reg, int value) {
1927   if (value == min_jint) {subl(reg, value) ; return; }
1928   if (value <  0) { incrementl(reg, -value); return; }
1929   if (value == 0) {                        ; return; }
1930   if (value == 1 && UseIncDec) { decl(reg) ; return; }
1931   /* else */      { subl(reg, value)       ; return; }
1932 }
1933 
1934 void MacroAssembler::decrementl(Address dst, int value) {
1935   if (value == min_jint) {subl(dst, value) ; return; }
1936   if (value <  0) { incrementl(dst, -value); return; }
1937   if (value == 0) {                        ; return; }
1938   if (value == 1 && UseIncDec) { decl(dst) ; return; }
1939   /* else */      { subl(dst, value)       ; return; }
1940 }
1941 
1942 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1943   assert (shift_value > 0, "illegal shift value");
1944   Label _is_positive;
1945   testl (reg, reg);
1946   jcc (Assembler::positive, _is_positive);
1947   int offset = (1 << shift_value) - 1 ;
1948 
1949   if (offset == 1) {
1950     incrementl(reg);
1951   } else {
1952     addl(reg, offset);
1953   }
1954 
1955   bind (_is_positive);
1956   sarl(reg, shift_value);
1957 }
1958 
1959 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
1960   if (reachable(src)) {
1961     Assembler::divsd(dst, as_Address(src));
1962   } else {
1963     lea(rscratch1, src);
1964     Assembler::divsd(dst, Address(rscratch1, 0));
1965   }
1966 }
1967 
1968 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
1969   if (reachable(src)) {
1970     Assembler::divss(dst, as_Address(src));
1971   } else {
1972     lea(rscratch1, src);
1973     Assembler::divss(dst, Address(rscratch1, 0));
1974   }
1975 }
1976 
1977 void MacroAssembler::enter() {
1978   push(rbp);
1979   mov(rbp, rsp);
1980 }
1981 
1982 // A 5 byte nop that is safe for patching (see patch_verified_entry)
1983 void MacroAssembler::fat_nop() {
1984   if (UseAddressNop) {
1985     addr_nop_5();
1986   } else {
1987     emit_int8(0x26); // es:
1988     emit_int8(0x2e); // cs:
1989     emit_int8(0x64); // fs:
1990     emit_int8(0x65); // gs:
1991     emit_int8((unsigned char)0x90);
1992   }
1993 }
1994 
1995 #ifndef _LP64
1996 void MacroAssembler::fcmp(Register tmp) {
1997   fcmp(tmp, 1, true, true);
1998 }
1999 
2000 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2001   assert(!pop_right || pop_left, "usage error");
2002   if (VM_Version::supports_cmov()) {
2003     assert(tmp == noreg, "unneeded temp");
2004     if (pop_left) {
2005       fucomip(index);
2006     } else {
2007       fucomi(index);
2008     }
2009     if (pop_right) {
2010       fpop();
2011     }
2012   } else {
2013     assert(tmp != noreg, "need temp");
2014     if (pop_left) {
2015       if (pop_right) {
2016         fcompp();
2017       } else {
2018         fcomp(index);
2019       }
2020     } else {
2021       fcom(index);
2022     }
2023     // convert FPU condition into eflags condition via rax,
2024     save_rax(tmp);
2025     fwait(); fnstsw_ax();
2026     sahf();
2027     restore_rax(tmp);
2028   }
2029   // condition codes set as follows:
2030   //
2031   // CF (corresponds to C0) if x < y
2032   // PF (corresponds to C2) if unordered
2033   // ZF (corresponds to C3) if x = y
2034 }
2035 
2036 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2037   fcmp2int(dst, unordered_is_less, 1, true, true);
2038 }
2039 
2040 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2041   fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2042   Label L;
2043   if (unordered_is_less) {
2044     movl(dst, -1);
2045     jcc(Assembler::parity, L);
2046     jcc(Assembler::below , L);
2047     movl(dst, 0);
2048     jcc(Assembler::equal , L);
2049     increment(dst);
2050   } else { // unordered is greater
2051     movl(dst, 1);
2052     jcc(Assembler::parity, L);
2053     jcc(Assembler::above , L);
2054     movl(dst, 0);
2055     jcc(Assembler::equal , L);
2056     decrementl(dst);
2057   }
2058   bind(L);
2059 }
2060 
2061 void MacroAssembler::fld_d(AddressLiteral src) {
2062   fld_d(as_Address(src));
2063 }
2064 
2065 void MacroAssembler::fld_s(AddressLiteral src) {
2066   fld_s(as_Address(src));
2067 }
2068 
2069 void MacroAssembler::fldcw(AddressLiteral src) {
2070   Assembler::fldcw(as_Address(src));
2071 }
2072 
2073 void MacroAssembler::fpop() {
2074   ffree();
2075   fincstp();
2076 }
2077 
2078 void MacroAssembler::fremr(Register tmp) {
2079   save_rax(tmp);
2080   { Label L;
2081     bind(L);
2082     fprem();
2083     fwait(); fnstsw_ax();
2084     sahf();
2085     jcc(Assembler::parity, L);
2086   }
2087   restore_rax(tmp);
2088   // Result is in ST0.
2089   // Note: fxch & fpop to get rid of ST1
2090   // (otherwise FPU stack could overflow eventually)
2091   fxch(1);
2092   fpop();
2093 }
2094 
2095 void MacroAssembler::empty_FPU_stack() {
2096   if (VM_Version::supports_mmx()) {
2097     emms();
2098   } else {
2099     for (int i = 8; i-- > 0; ) ffree(i);
2100   }
2101 }
2102 #endif // !LP64
2103 
2104 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
2105   if (reachable(src)) {
2106     Assembler::mulpd(dst, as_Address(src));
2107   } else {
2108     lea(rscratch1, src);
2109     Assembler::mulpd(dst, Address(rscratch1, 0));
2110   }
2111 }
2112 
2113 void MacroAssembler::load_float(Address src) {
2114 #ifdef _LP64
2115   movflt(xmm0, src);
2116 #else
2117   if (UseSSE >= 1) {
2118     movflt(xmm0, src);
2119   } else {
2120     fld_s(src);
2121   }
2122 #endif // LP64
2123 }
2124 
2125 void MacroAssembler::store_float(Address dst) {
2126 #ifdef _LP64
2127   movflt(dst, xmm0);
2128 #else
2129   if (UseSSE >= 1) {
2130     movflt(dst, xmm0);
2131   } else {
2132     fstp_s(dst);
2133   }
2134 #endif // LP64
2135 }
2136 
2137 void MacroAssembler::load_double(Address src) {
2138 #ifdef _LP64
2139   movdbl(xmm0, src);
2140 #else
2141   if (UseSSE >= 2) {
2142     movdbl(xmm0, src);
2143   } else {
2144     fld_d(src);
2145   }
2146 #endif // LP64
2147 }
2148 
2149 void MacroAssembler::store_double(Address dst) {
2150 #ifdef _LP64
2151   movdbl(dst, xmm0);
2152 #else
2153   if (UseSSE >= 2) {
2154     movdbl(dst, xmm0);
2155   } else {
2156     fstp_d(dst);
2157   }
2158 #endif // LP64
2159 }
2160 
2161 // dst = c = a * b + c
2162 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2163   Assembler::vfmadd231sd(c, a, b);
2164   if (dst != c) {
2165     movdbl(dst, c);
2166   }
2167 }
2168 
2169 // dst = c = a * b + c
2170 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2171   Assembler::vfmadd231ss(c, a, b);
2172   if (dst != c) {
2173     movflt(dst, c);
2174   }
2175 }
2176 
2177 // dst = c = a * b + c
2178 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2179   Assembler::vfmadd231pd(c, a, b, vector_len);
2180   if (dst != c) {
2181     vmovdqu(dst, c);
2182   }
2183 }
2184 
2185 // dst = c = a * b + c
2186 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2187   Assembler::vfmadd231ps(c, a, b, vector_len);
2188   if (dst != c) {
2189     vmovdqu(dst, c);
2190   }
2191 }
2192 
2193 // dst = c = a * b + c
2194 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2195   Assembler::vfmadd231pd(c, a, b, vector_len);
2196   if (dst != c) {
2197     vmovdqu(dst, c);
2198   }
2199 }
2200 
2201 // dst = c = a * b + c
2202 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2203   Assembler::vfmadd231ps(c, a, b, vector_len);
2204   if (dst != c) {
2205     vmovdqu(dst, c);
2206   }
2207 }
2208 
2209 void MacroAssembler::incrementl(AddressLiteral dst) {
2210   if (reachable(dst)) {
2211     incrementl(as_Address(dst));
2212   } else {
2213     lea(rscratch1, dst);
2214     incrementl(Address(rscratch1, 0));
2215   }
2216 }
2217 
2218 void MacroAssembler::incrementl(ArrayAddress dst) {
2219   incrementl(as_Address(dst));
2220 }
2221 
2222 void MacroAssembler::incrementl(Register reg, int value) {
2223   if (value == min_jint) {addl(reg, value) ; return; }
2224   if (value <  0) { decrementl(reg, -value); return; }
2225   if (value == 0) {                        ; return; }
2226   if (value == 1 && UseIncDec) { incl(reg) ; return; }
2227   /* else */      { addl(reg, value)       ; return; }
2228 }
2229 
2230 void MacroAssembler::incrementl(Address dst, int value) {
2231   if (value == min_jint) {addl(dst, value) ; return; }
2232   if (value <  0) { decrementl(dst, -value); return; }
2233   if (value == 0) {                        ; return; }
2234   if (value == 1 && UseIncDec) { incl(dst) ; return; }
2235   /* else */      { addl(dst, value)       ; return; }
2236 }
2237 
2238 void MacroAssembler::jump(AddressLiteral dst) {
2239   if (reachable(dst)) {
2240     jmp_literal(dst.target(), dst.rspec());
2241   } else {
2242     lea(rscratch1, dst);
2243     jmp(rscratch1);
2244   }
2245 }
2246 
2247 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
2248   if (reachable(dst)) {
2249     InstructionMark im(this);
2250     relocate(dst.reloc());
2251     const int short_size = 2;
2252     const int long_size = 6;
2253     int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2254     if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2255       // 0111 tttn #8-bit disp
2256       emit_int8(0x70 | cc);
2257       emit_int8((offs - short_size) & 0xFF);
2258     } else {
2259       // 0000 1111 1000 tttn #32-bit disp
2260       emit_int8(0x0F);
2261       emit_int8((unsigned char)(0x80 | cc));
2262       emit_int32(offs - long_size);
2263     }
2264   } else {
2265 #ifdef ASSERT
2266     warning("reversing conditional branch");
2267 #endif /* ASSERT */
2268     Label skip;
2269     jccb(reverse[cc], skip);
2270     lea(rscratch1, dst);
2271     Assembler::jmp(rscratch1);
2272     bind(skip);
2273   }
2274 }
2275 
2276 void MacroAssembler::fld_x(AddressLiteral src) {
2277   Assembler::fld_x(as_Address(src));
2278 }
2279 
2280 void MacroAssembler::ldmxcsr(AddressLiteral src) {
2281   if (reachable(src)) {
2282     Assembler::ldmxcsr(as_Address(src));
2283   } else {
2284     lea(rscratch1, src);
2285     Assembler::ldmxcsr(Address(rscratch1, 0));
2286   }
2287 }
2288 
2289 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2290   int off;
2291   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2292     off = offset();
2293     movsbl(dst, src); // movsxb
2294   } else {
2295     off = load_unsigned_byte(dst, src);
2296     shll(dst, 24);
2297     sarl(dst, 24);
2298   }
2299   return off;
2300 }
2301 
2302 // Note: load_signed_short used to be called load_signed_word.
2303 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2304 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2305 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2306 int MacroAssembler::load_signed_short(Register dst, Address src) {
2307   int off;
2308   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2309     // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2310     // version but this is what 64bit has always done. This seems to imply
2311     // that users are only using 32bits worth.
2312     off = offset();
2313     movswl(dst, src); // movsxw
2314   } else {
2315     off = load_unsigned_short(dst, src);
2316     shll(dst, 16);
2317     sarl(dst, 16);
2318   }
2319   return off;
2320 }
2321 
2322 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2323   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2324   // and "3.9 Partial Register Penalties", p. 22).
2325   int off;
2326   if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2327     off = offset();
2328     movzbl(dst, src); // movzxb
2329   } else {
2330     xorl(dst, dst);
2331     off = offset();
2332     movb(dst, src);
2333   }
2334   return off;
2335 }
2336 
2337 // Note: load_unsigned_short used to be called load_unsigned_word.
2338 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2339   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2340   // and "3.9 Partial Register Penalties", p. 22).
2341   int off;
2342   if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2343     off = offset();
2344     movzwl(dst, src); // movzxw
2345   } else {
2346     xorl(dst, dst);
2347     off = offset();
2348     movw(dst, src);
2349   }
2350   return off;
2351 }
2352 
2353 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2354   switch (size_in_bytes) {
2355 #ifndef _LP64
2356   case  8:
2357     assert(dst2 != noreg, "second dest register required");
2358     movl(dst,  src);
2359     movl(dst2, src.plus_disp(BytesPerInt));
2360     break;
2361 #else
2362   case  8:  movq(dst, src); break;
2363 #endif
2364   case  4:  movl(dst, src); break;
2365   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2366   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2367   default:  ShouldNotReachHere();
2368   }
2369 }
2370 
2371 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2372   switch (size_in_bytes) {
2373 #ifndef _LP64
2374   case  8:
2375     assert(src2 != noreg, "second source register required");
2376     movl(dst,                        src);
2377     movl(dst.plus_disp(BytesPerInt), src2);
2378     break;
2379 #else
2380   case  8:  movq(dst, src); break;
2381 #endif
2382   case  4:  movl(dst, src); break;
2383   case  2:  movw(dst, src); break;
2384   case  1:  movb(dst, src); break;
2385   default:  ShouldNotReachHere();
2386   }
2387 }
2388 
2389 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
2390   if (reachable(dst)) {
2391     movl(as_Address(dst), src);
2392   } else {
2393     lea(rscratch1, dst);
2394     movl(Address(rscratch1, 0), src);
2395   }
2396 }
2397 
2398 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2399   if (reachable(src)) {
2400     movl(dst, as_Address(src));
2401   } else {
2402     lea(rscratch1, src);
2403     movl(dst, Address(rscratch1, 0));
2404   }
2405 }
2406 
2407 // C++ bool manipulation
2408 
2409 void MacroAssembler::movbool(Register dst, Address src) {
2410   if(sizeof(bool) == 1)
2411     movb(dst, src);
2412   else if(sizeof(bool) == 2)
2413     movw(dst, src);
2414   else if(sizeof(bool) == 4)
2415     movl(dst, src);
2416   else
2417     // unsupported
2418     ShouldNotReachHere();
2419 }
2420 
2421 void MacroAssembler::movbool(Address dst, bool boolconst) {
2422   if(sizeof(bool) == 1)
2423     movb(dst, (int) boolconst);
2424   else if(sizeof(bool) == 2)
2425     movw(dst, (int) boolconst);
2426   else if(sizeof(bool) == 4)
2427     movl(dst, (int) boolconst);
2428   else
2429     // unsupported
2430     ShouldNotReachHere();
2431 }
2432 
2433 void MacroAssembler::movbool(Address dst, Register src) {
2434   if(sizeof(bool) == 1)
2435     movb(dst, src);
2436   else if(sizeof(bool) == 2)
2437     movw(dst, src);
2438   else if(sizeof(bool) == 4)
2439     movl(dst, src);
2440   else
2441     // unsupported
2442     ShouldNotReachHere();
2443 }
2444 
2445 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
2446   movb(as_Address(dst), src);
2447 }
2448 
2449 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
2450   if (reachable(src)) {
2451     movdl(dst, as_Address(src));
2452   } else {
2453     lea(rscratch1, src);
2454     movdl(dst, Address(rscratch1, 0));
2455   }
2456 }
2457 
2458 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
2459   if (reachable(src)) {
2460     movq(dst, as_Address(src));
2461   } else {
2462     lea(rscratch1, src);
2463     movq(dst, Address(rscratch1, 0));
2464   }
2465 }
2466 
2467 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
2468   if (reachable(src)) {
2469     if (UseXmmLoadAndClearUpper) {
2470       movsd (dst, as_Address(src));
2471     } else {
2472       movlpd(dst, as_Address(src));
2473     }
2474   } else {
2475     lea(rscratch1, src);
2476     if (UseXmmLoadAndClearUpper) {
2477       movsd (dst, Address(rscratch1, 0));
2478     } else {
2479       movlpd(dst, Address(rscratch1, 0));
2480     }
2481   }
2482 }
2483 
2484 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
2485   if (reachable(src)) {
2486     movss(dst, as_Address(src));
2487   } else {
2488     lea(rscratch1, src);
2489     movss(dst, Address(rscratch1, 0));
2490   }
2491 }
2492 
2493 void MacroAssembler::movptr(Register dst, Register src) {
2494   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2495 }
2496 
2497 void MacroAssembler::movptr(Register dst, Address src) {
2498   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2499 }
2500 
2501 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2502 void MacroAssembler::movptr(Register dst, intptr_t src) {
2503   LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
2504 }
2505 
2506 void MacroAssembler::movptr(Address dst, Register src) {
2507   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2508 }
2509 
2510 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2511     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2512     Assembler::movdqu(dst, src);
2513 }
2514 
2515 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2516     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2517     Assembler::movdqu(dst, src);
2518 }
2519 
2520 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2521     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2522     Assembler::movdqu(dst, src);
2523 }
2524 
2525 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
2526   if (reachable(src)) {
2527     movdqu(dst, as_Address(src));
2528   } else {
2529     lea(scratchReg, src);
2530     movdqu(dst, Address(scratchReg, 0));
2531   }
2532 }
2533 
2534 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2535     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2536     Assembler::vmovdqu(dst, src);
2537 }
2538 
2539 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2540     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2541     Assembler::vmovdqu(dst, src);
2542 }
2543 
2544 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2545     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2546     Assembler::vmovdqu(dst, src);
2547 }
2548 
2549 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
2550   if (reachable(src)) {
2551     vmovdqu(dst, as_Address(src));
2552   }
2553   else {
2554     lea(scratch_reg, src);
2555     vmovdqu(dst, Address(scratch_reg, 0));
2556   }
2557 }
2558 
2559 void MacroAssembler::kmov(KRegister dst, Address src) {
2560   if (VM_Version::supports_avx512bw()) {
2561     kmovql(dst, src);
2562   } else {
2563     assert(VM_Version::supports_evex(), "");
2564     kmovwl(dst, src);
2565   }
2566 }
2567 
2568 void MacroAssembler::kmov(Address dst, KRegister src) {
2569   if (VM_Version::supports_avx512bw()) {
2570     kmovql(dst, src);
2571   } else {
2572     assert(VM_Version::supports_evex(), "");
2573     kmovwl(dst, src);
2574   }
2575 }
2576 
2577 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2578   if (VM_Version::supports_avx512bw()) {
2579     kmovql(dst, src);
2580   } else {
2581     assert(VM_Version::supports_evex(), "");
2582     kmovwl(dst, src);
2583   }
2584 }
2585 
2586 void MacroAssembler::kmov(Register dst, KRegister src) {
2587   if (VM_Version::supports_avx512bw()) {
2588     kmovql(dst, src);
2589   } else {
2590     assert(VM_Version::supports_evex(), "");
2591     kmovwl(dst, src);
2592   }
2593 }
2594 
2595 void MacroAssembler::kmov(KRegister dst, Register src) {
2596   if (VM_Version::supports_avx512bw()) {
2597     kmovql(dst, src);
2598   } else {
2599     assert(VM_Version::supports_evex(), "");
2600     kmovwl(dst, src);
2601   }
2602 }
2603 
2604 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register scratch_reg) {
2605   if (reachable(src)) {
2606     kmovql(dst, as_Address(src));
2607   } else {
2608     lea(scratch_reg, src);
2609     kmovql(dst, Address(scratch_reg, 0));
2610   }
2611 }
2612 
2613 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register scratch_reg) {
2614   if (reachable(src)) {
2615     kmovwl(dst, as_Address(src));
2616   } else {
2617     lea(scratch_reg, src);
2618     kmovwl(dst, Address(scratch_reg, 0));
2619   }
2620 }
2621 
2622 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2623                                int vector_len, Register scratch_reg) {
2624   if (reachable(src)) {
2625     if (mask == k0) {
2626       Assembler::evmovdqub(dst, as_Address(src), merge, vector_len);
2627     } else {
2628       Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2629     }
2630   } else {
2631     lea(scratch_reg, src);
2632     if (mask == k0) {
2633       Assembler::evmovdqub(dst, Address(scratch_reg, 0), merge, vector_len);
2634     } else {
2635       Assembler::evmovdqub(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2636     }
2637   }
2638 }
2639 
2640 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2641                                int vector_len, Register scratch_reg) {
2642   if (reachable(src)) {
2643     Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2644   } else {
2645     lea(scratch_reg, src);
2646     Assembler::evmovdquw(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2647   }
2648 }
2649 
2650 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2651                                int vector_len, Register scratch_reg) {
2652   if (reachable(src)) {
2653     Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2654   } else {
2655     lea(scratch_reg, src);
2656     Assembler::evmovdqul(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2657   }
2658 }
2659 
2660 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2661                                int vector_len, Register scratch_reg) {
2662   if (reachable(src)) {
2663     Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2664   } else {
2665     lea(scratch_reg, src);
2666     Assembler::evmovdquq(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2667   }
2668 }
2669 
2670 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2671   if (reachable(src)) {
2672     Assembler::evmovdquq(dst, as_Address(src), vector_len);
2673   } else {
2674     lea(rscratch, src);
2675     Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2676   }
2677 }
2678 
2679 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
2680   if (reachable(src)) {
2681     Assembler::movdqa(dst, as_Address(src));
2682   } else {
2683     lea(rscratch1, src);
2684     Assembler::movdqa(dst, Address(rscratch1, 0));
2685   }
2686 }
2687 
2688 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
2689   if (reachable(src)) {
2690     Assembler::movsd(dst, as_Address(src));
2691   } else {
2692     lea(rscratch1, src);
2693     Assembler::movsd(dst, Address(rscratch1, 0));
2694   }
2695 }
2696 
2697 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
2698   if (reachable(src)) {
2699     Assembler::movss(dst, as_Address(src));
2700   } else {
2701     lea(rscratch1, src);
2702     Assembler::movss(dst, Address(rscratch1, 0));
2703   }
2704 }
2705 
2706 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
2707   if (reachable(src)) {
2708     Assembler::mulsd(dst, as_Address(src));
2709   } else {
2710     lea(rscratch1, src);
2711     Assembler::mulsd(dst, Address(rscratch1, 0));
2712   }
2713 }
2714 
2715 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
2716   if (reachable(src)) {
2717     Assembler::mulss(dst, as_Address(src));
2718   } else {
2719     lea(rscratch1, src);
2720     Assembler::mulss(dst, Address(rscratch1, 0));
2721   }
2722 }
2723 
2724 void MacroAssembler::null_check(Register reg, int offset) {
2725   if (needs_explicit_null_check(offset)) {
2726     // provoke OS NULL exception if reg = NULL by
2727     // accessing M[reg] w/o changing any (non-CC) registers
2728     // NOTE: cmpl is plenty here to provoke a segv
2729     cmpptr(rax, Address(reg, 0));
2730     // Note: should probably use testl(rax, Address(reg, 0));
2731     //       may be shorter code (however, this version of
2732     //       testl needs to be implemented first)
2733   } else {
2734     // nothing to do, (later) access of M[reg + offset]
2735     // will provoke OS NULL exception if reg = NULL
2736   }
2737 }
2738 
2739 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2740   andptr(markword, markWord::inline_type_mask_in_place);
2741   cmpptr(markword, markWord::inline_type_pattern);
2742   jcc(Assembler::equal, is_inline_type);
2743 }
2744 
2745 void MacroAssembler::test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type) {
2746   movl(temp_reg, Address(klass, Klass::access_flags_offset()));
2747   testl(temp_reg, JVM_ACC_INLINE);
2748   jcc(Assembler::notZero, is_inline_type);
2749 }
2750 
2751 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type) {
2752   testptr(object, object);
2753   jcc(Assembler::equal, not_inline_type);
2754   const int is_inline_type_mask = markWord::inline_type_pattern;
2755   movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2756   andptr(tmp, is_inline_type_mask);
2757   cmpptr(tmp, is_inline_type_mask);
2758   jcc(Assembler::notEqual, not_inline_type);
2759 }
2760 
2761 void MacroAssembler::test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type) {
2762 #ifdef ASSERT
2763   {
2764     Label done_check;
2765     test_klass_is_inline_type(klass, temp_reg, done_check);
2766     stop("test_klass_is_empty_inline_type with non inline type klass");
2767     bind(done_check);
2768   }
2769 #endif
2770   movl(temp_reg, Address(klass, InstanceKlass::misc_flags_offset()));
2771   testl(temp_reg, InstanceKlass::misc_flags_is_empty_inline_type());
2772   jcc(Assembler::notZero, is_empty_inline_type);
2773 }
2774 
2775 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2776   movl(temp_reg, flags);
2777   shrl(temp_reg, ConstantPoolCacheEntry::is_null_free_inline_type_shift);
2778   andl(temp_reg, 0x1);
2779   testl(temp_reg, temp_reg);
2780   jcc(Assembler::notZero, is_null_free_inline_type);
2781 }
2782 
2783 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2784   movl(temp_reg, flags);
2785   shrl(temp_reg, ConstantPoolCacheEntry::is_null_free_inline_type_shift);
2786   andl(temp_reg, 0x1);
2787   testl(temp_reg, temp_reg);
2788   jcc(Assembler::zero, not_null_free_inline_type);
2789 }
2790 
2791 void MacroAssembler::test_field_is_inlined(Register flags, Register temp_reg, Label& is_inlined) {
2792   movl(temp_reg, flags);
2793   shrl(temp_reg, ConstantPoolCacheEntry::is_inlined_shift);
2794   andl(temp_reg, 0x1);
2795   testl(temp_reg, temp_reg);
2796   jcc(Assembler::notZero, is_inlined);
2797 }
2798 
2799 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2800   Label test_mark_word;
2801   // load mark word
2802   movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2803   // check displaced
2804   testl(temp_reg, markWord::unlocked_value);
2805   jccb(Assembler::notZero, test_mark_word);
2806   // slow path use klass prototype
2807   push(rscratch1);
2808   load_prototype_header(temp_reg, oop, rscratch1);
2809   pop(rscratch1);
2810 
2811   bind(test_mark_word);
2812   testl(temp_reg, test_bit);
2813   jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
2814 }
2815 
2816 void MacroAssembler::test_flattened_array_oop(Register oop, Register temp_reg,
2817                                               Label&is_flattened_array) {
2818 #ifdef _LP64
2819   test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flattened_array);
2820 #else
2821   load_klass(temp_reg, oop, noreg);
2822   movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
2823   test_flattened_array_layout(temp_reg, is_flattened_array);
2824 #endif
2825 }
2826 
2827 void MacroAssembler::test_non_flattened_array_oop(Register oop, Register temp_reg,
2828                                                   Label&is_non_flattened_array) {
2829 #ifdef _LP64
2830   test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flattened_array);
2831 #else
2832   load_klass(temp_reg, oop, noreg);
2833   movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
2834   test_non_flattened_array_layout(temp_reg, is_non_flattened_array);
2835 #endif
2836 }
2837 
2838 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
2839 #ifdef _LP64
2840   test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2841 #else
2842   load_klass(temp_reg, oop, noreg);
2843   movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
2844   test_null_free_array_layout(temp_reg, is_null_free_array);
2845 #endif
2846 }
2847 
2848 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2849 #ifdef _LP64
2850   test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2851 #else
2852   load_klass(temp_reg, oop, noreg);
2853   movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
2854   test_non_null_free_array_layout(temp_reg, is_non_null_free_array);
2855 #endif
2856 }
2857 
2858 void MacroAssembler::test_flattened_array_layout(Register lh, Label& is_flattened_array) {
2859   testl(lh, Klass::_lh_array_tag_vt_value_bit_inplace);
2860   jcc(Assembler::notZero, is_flattened_array);
2861 }
2862 
2863 void MacroAssembler::test_non_flattened_array_layout(Register lh, Label& is_non_flattened_array) {
2864   testl(lh, Klass::_lh_array_tag_vt_value_bit_inplace);
2865   jcc(Assembler::zero, is_non_flattened_array);
2866 }
2867 
2868 void MacroAssembler::test_null_free_array_layout(Register lh, Label& is_null_free_array) {
2869   testl(lh, Klass::_lh_null_free_bit_inplace);
2870   jcc(Assembler::notZero, is_null_free_array);
2871 }
2872 
2873 void MacroAssembler::test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array) {
2874   testl(lh, Klass::_lh_null_free_bit_inplace);
2875   jcc(Assembler::zero, is_non_null_free_array);
2876 }
2877 
2878 
2879 void MacroAssembler::os_breakpoint() {
2880   // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2881   // (e.g., MSVC can't call ps() otherwise)
2882   call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2883 }
2884 
2885 void MacroAssembler::unimplemented(const char* what) {
2886   const char* buf = NULL;
2887   {
2888     ResourceMark rm;
2889     stringStream ss;
2890     ss.print("unimplemented: %s", what);
2891     buf = code_string(ss.as_string());
2892   }
2893   stop(buf);
2894 }
2895 
2896 #ifdef _LP64
2897 #define XSTATE_BV 0x200
2898 #endif
2899 
2900 void MacroAssembler::pop_CPU_state() {
2901   pop_FPU_state();
2902   pop_IU_state();
2903 }
2904 
2905 void MacroAssembler::pop_FPU_state() {
2906 #ifndef _LP64
2907   frstor(Address(rsp, 0));
2908 #else
2909   fxrstor(Address(rsp, 0));
2910 #endif
2911   addptr(rsp, FPUStateSizeInWords * wordSize);
2912 }
2913 
2914 void MacroAssembler::pop_IU_state() {
2915   popa();
2916   LP64_ONLY(addq(rsp, 8));
2917   popf();
2918 }
2919 
2920 // Save Integer and Float state
2921 // Warning: Stack must be 16 byte aligned (64bit)
2922 void MacroAssembler::push_CPU_state() {
2923   push_IU_state();
2924   push_FPU_state();
2925 }
2926 
2927 void MacroAssembler::push_FPU_state() {
2928   subptr(rsp, FPUStateSizeInWords * wordSize);
2929 #ifndef _LP64
2930   fnsave(Address(rsp, 0));
2931   fwait();
2932 #else
2933   fxsave(Address(rsp, 0));
2934 #endif // LP64
2935 }
2936 
2937 void MacroAssembler::push_IU_state() {
2938   // Push flags first because pusha kills them
2939   pushf();
2940   // Make sure rsp stays 16-byte aligned
2941   LP64_ONLY(subq(rsp, 8));
2942   pusha();
2943 }
2944 
2945 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
2946   if (!java_thread->is_valid()) {
2947     java_thread = rdi;
2948     get_thread(java_thread);
2949   }
2950   // we must set sp to zero to clear frame
2951   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2952   // must clear fp, so that compiled frames are not confused; it is
2953   // possible that we need it only for debugging
2954   if (clear_fp) {
2955     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2956   }
2957   // Always clear the pc because it could have been set by make_walkable()
2958   movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2959   vzeroupper();
2960 }
2961 
2962 void MacroAssembler::restore_rax(Register tmp) {
2963   if (tmp == noreg) pop(rax);
2964   else if (tmp != rax) mov(rax, tmp);
2965 }
2966 
2967 void MacroAssembler::round_to(Register reg, int modulus) {
2968   addptr(reg, modulus - 1);
2969   andptr(reg, -modulus);
2970 }
2971 
2972 void MacroAssembler::save_rax(Register tmp) {
2973   if (tmp == noreg) push(rax);
2974   else if (tmp != rax) mov(tmp, rax);
2975 }
2976 
2977 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
2978   if (at_return) {
2979     // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2980     // we may safely use rsp instead to perform the stack watermark check.
2981     cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
2982     jcc(Assembler::above, slow_path);
2983     return;
2984   }
2985   testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2986   jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2987 }
2988 
2989 // Calls to C land
2990 //
2991 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2992 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2993 // has to be reset to 0. This is required to allow proper stack traversal.
2994 void MacroAssembler::set_last_Java_frame(Register java_thread,
2995                                          Register last_java_sp,
2996                                          Register last_java_fp,
2997                                          address  last_java_pc) {
2998   vzeroupper();
2999   // determine java_thread register
3000   if (!java_thread->is_valid()) {
3001     java_thread = rdi;
3002     get_thread(java_thread);
3003   }
3004   // determine last_java_sp register
3005   if (!last_java_sp->is_valid()) {
3006     last_java_sp = rsp;
3007   }
3008 
3009   // last_java_fp is optional
3010 
3011   if (last_java_fp->is_valid()) {
3012     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3013   }
3014 
3015   // last_java_pc is optional
3016 
3017   if (last_java_pc != NULL) {
3018     lea(Address(java_thread,
3019                  JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3020         InternalAddress(last_java_pc));
3021 
3022   }
3023   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3024 }
3025 
3026 void MacroAssembler::shlptr(Register dst, int imm8) {
3027   LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3028 }
3029 
3030 void MacroAssembler::shrptr(Register dst, int imm8) {
3031   LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3032 }
3033 
3034 void MacroAssembler::sign_extend_byte(Register reg) {
3035   if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3036     movsbl(reg, reg); // movsxb
3037   } else {
3038     shll(reg, 24);
3039     sarl(reg, 24);
3040   }
3041 }
3042 
3043 void MacroAssembler::sign_extend_short(Register reg) {
3044   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3045     movswl(reg, reg); // movsxw
3046   } else {
3047     shll(reg, 16);
3048     sarl(reg, 16);
3049   }
3050 }
3051 
3052 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3053   assert(reachable(src), "Address should be reachable");
3054   testl(dst, as_Address(src));
3055 }
3056 
3057 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3058   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3059   Assembler::pcmpeqb(dst, src);
3060 }
3061 
3062 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3063   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3064   Assembler::pcmpeqw(dst, src);
3065 }
3066 
3067 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3068   assert((dst->encoding() < 16),"XMM register should be 0-15");
3069   Assembler::pcmpestri(dst, src, imm8);
3070 }
3071 
3072 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3073   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3074   Assembler::pcmpestri(dst, src, imm8);
3075 }
3076 
3077 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3078   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3079   Assembler::pmovzxbw(dst, src);
3080 }
3081 
3082 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3083   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3084   Assembler::pmovzxbw(dst, src);
3085 }
3086 
3087 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3088   assert((src->encoding() < 16),"XMM register should be 0-15");
3089   Assembler::pmovmskb(dst, src);
3090 }
3091 
3092 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3093   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3094   Assembler::ptest(dst, src);
3095 }
3096 
3097 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3098   if (reachable(src)) {
3099     Assembler::sqrtsd(dst, as_Address(src));
3100   } else {
3101     lea(rscratch1, src);
3102     Assembler::sqrtsd(dst, Address(rscratch1, 0));
3103   }
3104 }
3105 
3106 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3107   if (reachable(src)) {
3108     Assembler::sqrtss(dst, as_Address(src));
3109   } else {
3110     lea(rscratch1, src);
3111     Assembler::sqrtss(dst, Address(rscratch1, 0));
3112   }
3113 }
3114 
3115 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3116   if (reachable(src)) {
3117     Assembler::subsd(dst, as_Address(src));
3118   } else {
3119     lea(rscratch1, src);
3120     Assembler::subsd(dst, Address(rscratch1, 0));
3121   }
3122 }
3123 
3124 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) {
3125   if (reachable(src)) {
3126     Assembler::roundsd(dst, as_Address(src), rmode);
3127   } else {
3128     lea(scratch_reg, src);
3129     Assembler::roundsd(dst, Address(scratch_reg, 0), rmode);
3130   }
3131 }
3132 
3133 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3134   if (reachable(src)) {
3135     Assembler::subss(dst, as_Address(src));
3136   } else {
3137     lea(rscratch1, src);
3138     Assembler::subss(dst, Address(rscratch1, 0));
3139   }
3140 }
3141 
3142 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3143   if (reachable(src)) {
3144     Assembler::ucomisd(dst, as_Address(src));
3145   } else {
3146     lea(rscratch1, src);
3147     Assembler::ucomisd(dst, Address(rscratch1, 0));
3148   }
3149 }
3150 
3151 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3152   if (reachable(src)) {
3153     Assembler::ucomiss(dst, as_Address(src));
3154   } else {
3155     lea(rscratch1, src);
3156     Assembler::ucomiss(dst, Address(rscratch1, 0));
3157   }
3158 }
3159 
3160 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3161   // Used in sign-bit flipping with aligned address.
3162   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3163   if (reachable(src)) {
3164     Assembler::xorpd(dst, as_Address(src));
3165   } else {
3166     lea(scratch_reg, src);
3167     Assembler::xorpd(dst, Address(scratch_reg, 0));
3168   }
3169 }
3170 
3171 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3172   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3173     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3174   }
3175   else {
3176     Assembler::xorpd(dst, src);
3177   }
3178 }
3179 
3180 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3181   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3182     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3183   } else {
3184     Assembler::xorps(dst, src);
3185   }
3186 }
3187 
3188 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3189   // Used in sign-bit flipping with aligned address.
3190   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3191   if (reachable(src)) {
3192     Assembler::xorps(dst, as_Address(src));
3193   } else {
3194     lea(scratch_reg, src);
3195     Assembler::xorps(dst, Address(scratch_reg, 0));
3196   }
3197 }
3198 
3199 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3200   // Used in sign-bit flipping with aligned address.
3201   bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3202   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3203   if (reachable(src)) {
3204     Assembler::pshufb(dst, as_Address(src));
3205   } else {
3206     lea(rscratch1, src);
3207     Assembler::pshufb(dst, Address(rscratch1, 0));
3208   }
3209 }
3210 
3211 // AVX 3-operands instructions
3212 
3213 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3214   if (reachable(src)) {
3215     vaddsd(dst, nds, as_Address(src));
3216   } else {
3217     lea(rscratch1, src);
3218     vaddsd(dst, nds, Address(rscratch1, 0));
3219   }
3220 }
3221 
3222 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3223   if (reachable(src)) {
3224     vaddss(dst, nds, as_Address(src));
3225   } else {
3226     lea(rscratch1, src);
3227     vaddss(dst, nds, Address(rscratch1, 0));
3228   }
3229 }
3230 
3231 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3232   assert(UseAVX > 0, "requires some form of AVX");
3233   if (reachable(src)) {
3234     Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3235   } else {
3236     lea(rscratch, src);
3237     Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3238   }
3239 }
3240 
3241 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3242   assert(UseAVX > 0, "requires some form of AVX");
3243   if (reachable(src)) {
3244     Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3245   } else {
3246     lea(rscratch, src);
3247     Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3248   }
3249 }
3250 
3251 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3252   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3253   vandps(dst, nds, negate_field, vector_len);
3254 }
3255 
3256 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3257   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3258   vandpd(dst, nds, negate_field, vector_len);
3259 }
3260 
3261 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3262   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3263   Assembler::vpaddb(dst, nds, src, vector_len);
3264 }
3265 
3266 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3267   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3268   Assembler::vpaddb(dst, nds, src, vector_len);
3269 }
3270 
3271 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3272   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3273   Assembler::vpaddw(dst, nds, src, vector_len);
3274 }
3275 
3276 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3277   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3278   Assembler::vpaddw(dst, nds, src, vector_len);
3279 }
3280 
3281 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3282   if (reachable(src)) {
3283     Assembler::vpand(dst, nds, as_Address(src), vector_len);
3284   } else {
3285     lea(scratch_reg, src);
3286     Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len);
3287   }
3288 }
3289 
3290 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
3291   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3292   Assembler::vpbroadcastw(dst, src, vector_len);
3293 }
3294 
3295 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3296   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3297   Assembler::vpcmpeqb(dst, nds, src, vector_len);
3298 }
3299 
3300 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3301   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3302   Assembler::vpcmpeqw(dst, nds, src, vector_len);
3303 }
3304 
3305 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds,
3306                                AddressLiteral src, int vector_len, Register scratch_reg) {
3307   if (reachable(src)) {
3308     Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3309   } else {
3310     lea(scratch_reg, src);
3311     Assembler::evpcmpeqd(kdst, mask, nds, Address(scratch_reg, 0), vector_len);
3312   }
3313 }
3314 
3315 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3316                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3317   if (reachable(src)) {
3318     Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3319   } else {
3320     lea(scratch_reg, src);
3321     Assembler::evpcmpd(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3322   }
3323 }
3324 
3325 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3326                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3327   if (reachable(src)) {
3328     Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3329   } else {
3330     lea(scratch_reg, src);
3331     Assembler::evpcmpq(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3332   }
3333 }
3334 
3335 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3336                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3337   if (reachable(src)) {
3338     Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3339   } else {
3340     lea(scratch_reg, src);
3341     Assembler::evpcmpb(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3342   }
3343 }
3344 
3345 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3346                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3347   if (reachable(src)) {
3348     Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3349   } else {
3350     lea(scratch_reg, src);
3351     Assembler::evpcmpw(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3352   }
3353 }
3354 
3355 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3356   if (width == Assembler::Q) {
3357     Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3358   } else {
3359     Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3360   }
3361 }
3362 
3363 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, ComparisonPredicate cond, Width width, int vector_len, Register scratch_reg) {
3364   int eq_cond_enc = 0x29;
3365   int gt_cond_enc = 0x37;
3366   if (width != Assembler::Q) {
3367     eq_cond_enc = 0x74 + width;
3368     gt_cond_enc = 0x64 + width;
3369   }
3370   switch (cond) {
3371   case eq:
3372     vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3373     break;
3374   case neq:
3375     vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3376     vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg);
3377     break;
3378   case le:
3379     vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3380     vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg);
3381     break;
3382   case nlt:
3383     vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3384     vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg);
3385     break;
3386   case lt:
3387     vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3388     break;
3389   case nle:
3390     vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3391     break;
3392   default:
3393     assert(false, "Should not reach here");
3394   }
3395 }
3396 
3397 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3398   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3399   Assembler::vpmovzxbw(dst, src, vector_len);
3400 }
3401 
3402 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3403   assert((src->encoding() < 16),"XMM register should be 0-15");
3404   Assembler::vpmovmskb(dst, src, vector_len);
3405 }
3406 
3407 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3408   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3409   Assembler::vpmullw(dst, nds, src, vector_len);
3410 }
3411 
3412 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3413   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3414   Assembler::vpmullw(dst, nds, src, vector_len);
3415 }
3416 
3417 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3418   assert((UseAVX > 0), "AVX support is needed");
3419   if (reachable(src)) {
3420     Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3421   } else {
3422     lea(scratch_reg, src);
3423     Assembler::vpmulld(dst, nds, Address(scratch_reg, 0), vector_len);
3424   }
3425 }
3426 
3427 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3428   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3429   Assembler::vpsubb(dst, nds, src, vector_len);
3430 }
3431 
3432 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3433   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3434   Assembler::vpsubb(dst, nds, src, vector_len);
3435 }
3436 
3437 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3438   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3439   Assembler::vpsubw(dst, nds, src, vector_len);
3440 }
3441 
3442 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3443   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3444   Assembler::vpsubw(dst, nds, src, vector_len);
3445 }
3446 
3447 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3448   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3449   Assembler::vpsraw(dst, nds, shift, vector_len);
3450 }
3451 
3452 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3453   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3454   Assembler::vpsraw(dst, nds, shift, vector_len);
3455 }
3456 
3457 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3458   assert(UseAVX > 2,"");
3459   if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3460      vector_len = 2;
3461   }
3462   Assembler::evpsraq(dst, nds, shift, vector_len);
3463 }
3464 
3465 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3466   assert(UseAVX > 2,"");
3467   if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3468      vector_len = 2;
3469   }
3470   Assembler::evpsraq(dst, nds, shift, vector_len);
3471 }
3472 
3473 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3474   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3475   Assembler::vpsrlw(dst, nds, shift, vector_len);
3476 }
3477 
3478 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3479   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3480   Assembler::vpsrlw(dst, nds, shift, vector_len);
3481 }
3482 
3483 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3484   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3485   Assembler::vpsllw(dst, nds, shift, vector_len);
3486 }
3487 
3488 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3489   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3490   Assembler::vpsllw(dst, nds, shift, vector_len);
3491 }
3492 
3493 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3494   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3495   Assembler::vptest(dst, src);
3496 }
3497 
3498 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3499   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3500   Assembler::punpcklbw(dst, src);
3501 }
3502 
3503 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3504   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3505   Assembler::pshufd(dst, src, mode);
3506 }
3507 
3508 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3509   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3510   Assembler::pshuflw(dst, src, mode);
3511 }
3512 
3513 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3514   if (reachable(src)) {
3515     vandpd(dst, nds, as_Address(src), vector_len);
3516   } else {
3517     lea(scratch_reg, src);
3518     vandpd(dst, nds, Address(scratch_reg, 0), vector_len);
3519   }
3520 }
3521 
3522 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3523   if (reachable(src)) {
3524     vandps(dst, nds, as_Address(src), vector_len);
3525   } else {
3526     lea(scratch_reg, src);
3527     vandps(dst, nds, Address(scratch_reg, 0), vector_len);
3528   }
3529 }
3530 
3531 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3532                             bool merge, int vector_len, Register scratch_reg) {
3533   if (reachable(src)) {
3534     Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3535   } else {
3536     lea(scratch_reg, src);
3537     Assembler::evpord(dst, mask, nds, Address(scratch_reg, 0), merge, vector_len);
3538   }
3539 }
3540 
3541 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3542   if (reachable(src)) {
3543     vdivsd(dst, nds, as_Address(src));
3544   } else {
3545     lea(rscratch1, src);
3546     vdivsd(dst, nds, Address(rscratch1, 0));
3547   }
3548 }
3549 
3550 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3551   if (reachable(src)) {
3552     vdivss(dst, nds, as_Address(src));
3553   } else {
3554     lea(rscratch1, src);
3555     vdivss(dst, nds, Address(rscratch1, 0));
3556   }
3557 }
3558 
3559 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3560   if (reachable(src)) {
3561     vmulsd(dst, nds, as_Address(src));
3562   } else {
3563     lea(rscratch1, src);
3564     vmulsd(dst, nds, Address(rscratch1, 0));
3565   }
3566 }
3567 
3568 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3569   if (reachable(src)) {
3570     vmulss(dst, nds, as_Address(src));
3571   } else {
3572     lea(rscratch1, src);
3573     vmulss(dst, nds, Address(rscratch1, 0));
3574   }
3575 }
3576 
3577 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3578   if (reachable(src)) {
3579     vsubsd(dst, nds, as_Address(src));
3580   } else {
3581     lea(rscratch1, src);
3582     vsubsd(dst, nds, Address(rscratch1, 0));
3583   }
3584 }
3585 
3586 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3587   if (reachable(src)) {
3588     vsubss(dst, nds, as_Address(src));
3589   } else {
3590     lea(rscratch1, src);
3591     vsubss(dst, nds, Address(rscratch1, 0));
3592   }
3593 }
3594 
3595 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3596   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3597   vxorps(dst, nds, src, Assembler::AVX_128bit);
3598 }
3599 
3600 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3601   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3602   vxorpd(dst, nds, src, Assembler::AVX_128bit);
3603 }
3604 
3605 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3606   if (reachable(src)) {
3607     vxorpd(dst, nds, as_Address(src), vector_len);
3608   } else {
3609     lea(scratch_reg, src);
3610     vxorpd(dst, nds, Address(scratch_reg, 0), vector_len);
3611   }
3612 }
3613 
3614 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3615   if (reachable(src)) {
3616     vxorps(dst, nds, as_Address(src), vector_len);
3617   } else {
3618     lea(scratch_reg, src);
3619     vxorps(dst, nds, Address(scratch_reg, 0), vector_len);
3620   }
3621 }
3622 
3623 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3624   if (UseAVX > 1 || (vector_len < 1)) {
3625     if (reachable(src)) {
3626       Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3627     } else {
3628       lea(scratch_reg, src);
3629       Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len);
3630     }
3631   }
3632   else {
3633     MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg);
3634   }
3635 }
3636 
3637 void MacroAssembler::vpermd(XMMRegister dst,  XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3638   if (reachable(src)) {
3639     Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3640   } else {
3641     lea(scratch_reg, src);
3642     Assembler::vpermd(dst, nds, Address(scratch_reg, 0), vector_len);
3643   }
3644 }
3645 
3646 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
3647   const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
3648   STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
3649   // The inverted mask is sign-extended
3650   andptr(possibly_jweak, inverted_jweak_mask);
3651 }
3652 
3653 void MacroAssembler::resolve_jobject(Register value,
3654                                      Register thread,
3655                                      Register tmp) {
3656   assert_different_registers(value, thread, tmp);
3657   Label done, not_weak;
3658   testptr(value, value);
3659   jcc(Assembler::zero, done);                // Use NULL as-is.
3660   testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
3661   jcc(Assembler::zero, not_weak);
3662   // Resolve jweak.
3663   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3664                  value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
3665   verify_oop(value);
3666   jmp(done);
3667   bind(not_weak);
3668   // Resolve (untagged) jobject.
3669   access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
3670   verify_oop(value);
3671   bind(done);
3672 }
3673 
3674 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3675   LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
3676 }
3677 
3678 // Force generation of a 4 byte immediate value even if it fits into 8bit
3679 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3680   LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
3681 }
3682 
3683 void MacroAssembler::subptr(Register dst, Register src) {
3684   LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
3685 }
3686 
3687 // C++ bool manipulation
3688 void MacroAssembler::testbool(Register dst) {
3689   if(sizeof(bool) == 1)
3690     testb(dst, 0xff);
3691   else if(sizeof(bool) == 2) {
3692     // testw implementation needed for two byte bools
3693     ShouldNotReachHere();
3694   } else if(sizeof(bool) == 4)
3695     testl(dst, dst);
3696   else
3697     // unsupported
3698     ShouldNotReachHere();
3699 }
3700 
3701 void MacroAssembler::testptr(Register dst, Register src) {
3702   LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
3703 }
3704 
3705 // Object / value buffer allocation...
3706 //
3707 // Kills klass and rsi on LP64
3708 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
3709                                        Register t1, Register t2,
3710                                        bool clear_fields, Label& alloc_failed)
3711 {
3712   Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
3713   Register layout_size = t1;
3714   assert(new_obj == rax, "needs to be rax, according to barrier asm eden_allocate");
3715   assert_different_registers(klass, new_obj, t1, t2);
3716 
3717   // get instance_size in InstanceKlass (scaled to a count of bytes)
3718   movl(layout_size, Address(klass, Klass::layout_helper_offset()));
3719   // test to see if it has a finalizer or is malformed in some way
3720   testl(layout_size, Klass::_lh_instance_slow_path_bit);
3721   jcc(Assembler::notZero, slow_case_no_pop);
3722 
3723   // Allocate the instance:
3724   //  If TLAB is enabled:
3725   //    Try to allocate in the TLAB.
3726   //    If fails, go to the slow path.
3727   //  Else If inline contiguous allocations are enabled:
3728   //    Try to allocate in eden.
3729   //    If fails due to heap end, go to slow path.
3730   //
3731   //  If TLAB is enabled OR inline contiguous is enabled:
3732   //    Initialize the allocation.
3733   //    Exit.
3734   //
3735   //  Go to slow path.
3736   const bool allow_shared_alloc =
3737     Universe::heap()->supports_inline_contig_alloc();
3738 
3739   push(klass);
3740   const Register thread = LP64_ONLY(r15_thread) NOT_LP64(klass);
3741 #ifndef _LP64
3742   if (UseTLAB || allow_shared_alloc) {
3743     get_thread(thread);
3744   }
3745 #endif // _LP64
3746 
3747   if (UseTLAB) {
3748     tlab_allocate(thread, new_obj, layout_size, 0, klass, t2, slow_case);
3749     if (ZeroTLAB || (!clear_fields)) {
3750       // the fields have been already cleared
3751       jmp(initialize_header);
3752     } else {
3753       // initialize both the header and fields
3754       jmp(initialize_object);
3755     }
3756   } else {
3757     // Allocation in the shared Eden, if allowed.
3758     //
3759     eden_allocate(thread, new_obj, layout_size, 0, t2, slow_case);
3760   }
3761 
3762   // If UseTLAB or allow_shared_alloc are true, the object is created above and
3763   // there is an initialize need. Otherwise, skip and go to the slow path.
3764   if (UseTLAB || allow_shared_alloc) {
3765     if (clear_fields) {
3766       // The object is initialized before the header.  If the object size is
3767       // zero, go directly to the header initialization.
3768       bind(initialize_object);
3769       decrement(layout_size, sizeof(oopDesc));
3770       jcc(Assembler::zero, initialize_header);
3771 
3772       // Initialize topmost object field, divide size by 8, check if odd and
3773       // test if zero.
3774       Register zero = klass;
3775       xorl(zero, zero);    // use zero reg to clear memory (shorter code)
3776       shrl(layout_size, LogBytesPerLong); // divide by 2*oopSize and set carry flag if odd
3777 
3778   #ifdef ASSERT
3779       // make sure instance_size was multiple of 8
3780       Label L;
3781       // Ignore partial flag stall after shrl() since it is debug VM
3782       jcc(Assembler::carryClear, L);
3783       stop("object size is not multiple of 2 - adjust this code");
3784       bind(L);
3785       // must be > 0, no extra check needed here
3786   #endif
3787 
3788       // initialize remaining object fields: instance_size was a multiple of 8
3789       {
3790         Label loop;
3791         bind(loop);
3792         movptr(Address(new_obj, layout_size, Address::times_8, sizeof(oopDesc) - 1*oopSize), zero);
3793         NOT_LP64(movptr(Address(new_obj, layout_size, Address::times_8, sizeof(oopDesc) - 2*oopSize), zero));
3794         decrement(layout_size);
3795         jcc(Assembler::notZero, loop);
3796       }
3797     } // clear_fields
3798 
3799     // initialize object header only.
3800     bind(initialize_header);
3801     pop(klass);
3802     Register mark_word = t2;
3803     movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
3804     movptr(Address(new_obj, oopDesc::mark_offset_in_bytes ()), mark_word);
3805 #ifdef _LP64
3806     xorl(rsi, rsi);                 // use zero reg to clear memory (shorter code)
3807     store_klass_gap(new_obj, rsi);  // zero klass gap for compressed oops
3808 #endif
3809     movptr(t2, klass);         // preserve klass
3810     Register tmp_store_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
3811     store_klass(new_obj, t2, tmp_store_klass);  // src klass reg is potentially compressed
3812 
3813     jmp(done);
3814   }
3815 
3816   bind(slow_case);
3817   pop(klass);
3818   bind(slow_case_no_pop);
3819   jmp(alloc_failed);
3820 
3821   bind(done);
3822 }
3823 
3824 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3825 void MacroAssembler::tlab_allocate(Register thread, Register obj,
3826                                    Register var_size_in_bytes,
3827                                    int con_size_in_bytes,
3828                                    Register t1,
3829                                    Register t2,
3830                                    Label& slow_case) {
3831   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3832   bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3833 }
3834 
3835 // Defines obj, preserves var_size_in_bytes
3836 void MacroAssembler::eden_allocate(Register thread, Register obj,
3837                                    Register var_size_in_bytes,
3838                                    int con_size_in_bytes,
3839                                    Register t1,
3840                                    Label& slow_case) {
3841   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3842   bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
3843 }
3844 
3845 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3846 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3847   assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3848   assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3849   Label done;
3850 
3851   testptr(length_in_bytes, length_in_bytes);
3852   jcc(Assembler::zero, done);
3853 
3854   // initialize topmost word, divide index by 2, check if odd and test if zero
3855   // note: for the remaining code to work, index must be a multiple of BytesPerWord
3856 #ifdef ASSERT
3857   {
3858     Label L;
3859     testptr(length_in_bytes, BytesPerWord - 1);
3860     jcc(Assembler::zero, L);
3861     stop("length must be a multiple of BytesPerWord");
3862     bind(L);
3863   }
3864 #endif
3865   Register index = length_in_bytes;
3866   xorptr(temp, temp);    // use _zero reg to clear memory (shorter code)
3867   if (UseIncDec) {
3868     shrptr(index, 3);  // divide by 8/16 and set carry flag if bit 2 was set
3869   } else {
3870     shrptr(index, 2);  // use 2 instructions to avoid partial flag stall
3871     shrptr(index, 1);
3872   }
3873 #ifndef _LP64
3874   // index could have not been a multiple of 8 (i.e., bit 2 was set)
3875   {
3876     Label even;
3877     // note: if index was a multiple of 8, then it cannot
3878     //       be 0 now otherwise it must have been 0 before
3879     //       => if it is even, we don't need to check for 0 again
3880     jcc(Assembler::carryClear, even);
3881     // clear topmost word (no jump would be needed if conditional assignment worked here)
3882     movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
3883     // index could be 0 now, must check again
3884     jcc(Assembler::zero, done);
3885     bind(even);
3886   }
3887 #endif // !_LP64
3888   // initialize remaining object fields: index is a multiple of 2 now
3889   {
3890     Label loop;
3891     bind(loop);
3892     movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3893     NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
3894     decrement(index);
3895     jcc(Assembler::notZero, loop);
3896   }
3897 
3898   bind(done);
3899 }
3900 
3901 void MacroAssembler::get_inline_type_field_klass(Register klass, Register index, Register inline_klass) {
3902   movptr(inline_klass, Address(klass, InstanceKlass::inline_type_field_klasses_offset()));
3903 #ifdef ASSERT
3904   {
3905     Label done;
3906     cmpptr(inline_klass, 0);
3907     jcc(Assembler::notEqual, done);
3908     stop("get_inline_type_field_klass contains no inline klass");
3909     bind(done);
3910   }
3911 #endif
3912   movptr(inline_klass, Address(inline_klass, index, Address::times_ptr));
3913 }
3914 
3915 void MacroAssembler::get_default_value_oop(Register inline_klass, Register temp_reg, Register obj) {
3916 #ifdef ASSERT
3917   {
3918     Label done_check;
3919     test_klass_is_inline_type(inline_klass, temp_reg, done_check);
3920     stop("get_default_value_oop from non inline type klass");
3921     bind(done_check);
3922   }
3923 #endif
3924   Register offset = temp_reg;
3925   // Getting the offset of the pre-allocated default value
3926   movptr(offset, Address(inline_klass, in_bytes(InstanceKlass::adr_inlineklass_fixed_block_offset())));
3927   movl(offset, Address(offset, in_bytes(InlineKlass::default_value_offset_offset())));
3928 
3929   // Getting the mirror
3930   movptr(obj, Address(inline_klass, in_bytes(Klass::java_mirror_offset())));
3931   resolve_oop_handle(obj, inline_klass);
3932 
3933   // Getting the pre-allocated default value from the mirror
3934   Address field(obj, offset, Address::times_1);
3935   load_heap_oop(obj, field);
3936 }
3937 
3938 void MacroAssembler::get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj) {
3939 #ifdef ASSERT
3940   {
3941     Label done_check;
3942     test_klass_is_empty_inline_type(inline_klass, temp_reg, done_check);
3943     stop("get_empty_value from non-empty inline klass");
3944     bind(done_check);
3945   }
3946 #endif
3947   get_default_value_oop(inline_klass, temp_reg, obj);
3948 }
3949 
3950 
3951 // Look up the method for a megamorphic invokeinterface call.
3952 // The target method is determined by <intf_klass, itable_index>.
3953 // The receiver klass is in recv_klass.
3954 // On success, the result will be in method_result, and execution falls through.
3955 // On failure, execution transfers to the given label.
3956 void MacroAssembler::lookup_interface_method(Register recv_klass,
3957                                              Register intf_klass,
3958                                              RegisterOrConstant itable_index,
3959                                              Register method_result,
3960                                              Register scan_temp,
3961                                              Label& L_no_such_interface,
3962                                              bool return_method) {
3963   assert_different_registers(recv_klass, intf_klass, scan_temp);
3964   assert_different_registers(method_result, intf_klass, scan_temp);
3965   assert(recv_klass != method_result || !return_method,
3966          "recv_klass can be destroyed when method isn't needed");
3967 
3968   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3969          "caller must use same register for non-constant itable index as for method");
3970 
3971   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3972   int vtable_base = in_bytes(Klass::vtable_start_offset());
3973   int itentry_off = itableMethodEntry::method_offset_in_bytes();
3974   int scan_step   = itableOffsetEntry::size() * wordSize;
3975   int vte_size    = vtableEntry::size_in_bytes();
3976   Address::ScaleFactor times_vte_scale = Address::times_ptr;
3977   assert(vte_size == wordSize, "else adjust times_vte_scale");
3978 
3979   movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3980 
3981   // %%% Could store the aligned, prescaled offset in the klassoop.
3982   lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3983 
3984   if (return_method) {
3985     // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3986     assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3987     lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3988   }
3989 
3990   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
3991   //   if (scan->interface() == intf) {
3992   //     result = (klass + scan->offset() + itable_index);
3993   //   }
3994   // }
3995   Label search, found_method;
3996 
3997   for (int peel = 1; peel >= 0; peel--) {
3998     movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
3999     cmpptr(intf_klass, method_result);
4000 
4001     if (peel) {
4002       jccb(Assembler::equal, found_method);
4003     } else {
4004       jccb(Assembler::notEqual, search);
4005       // (invert the test to fall through to found_method...)
4006     }
4007 
4008     if (!peel)  break;
4009 
4010     bind(search);
4011 
4012     // Check that the previous entry is non-null.  A null entry means that
4013     // the receiver class doesn't implement the interface, and wasn't the
4014     // same as when the caller was compiled.
4015     testptr(method_result, method_result);
4016     jcc(Assembler::zero, L_no_such_interface);
4017     addptr(scan_temp, scan_step);
4018   }
4019 
4020   bind(found_method);
4021 
4022   if (return_method) {
4023     // Got a hit.
4024     movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
4025     movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4026   }
4027 }
4028 
4029 
4030 // virtual method calling
4031 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4032                                            RegisterOrConstant vtable_index,
4033                                            Register method_result) {
4034   const int base = in_bytes(Klass::vtable_start_offset());
4035   assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4036   Address vtable_entry_addr(recv_klass,
4037                             vtable_index, Address::times_ptr,
4038                             base + vtableEntry::method_offset_in_bytes());
4039   movptr(method_result, vtable_entry_addr);
4040 }
4041 
4042 
4043 void MacroAssembler::check_klass_subtype(Register sub_klass,
4044                            Register super_klass,
4045                            Register temp_reg,
4046                            Label& L_success) {
4047   Label L_failure;
4048   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
4049   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
4050   bind(L_failure);
4051 }
4052 
4053 
4054 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4055                                                    Register super_klass,
4056                                                    Register temp_reg,
4057                                                    Label* L_success,
4058                                                    Label* L_failure,
4059                                                    Label* L_slow_path,
4060                                         RegisterOrConstant super_check_offset) {
4061   assert_different_registers(sub_klass, super_klass, temp_reg);
4062   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4063   if (super_check_offset.is_register()) {
4064     assert_different_registers(sub_klass, super_klass,
4065                                super_check_offset.as_register());
4066   } else if (must_load_sco) {
4067     assert(temp_reg != noreg, "supply either a temp or a register offset");
4068   }
4069 
4070   Label L_fallthrough;
4071   int label_nulls = 0;
4072   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
4073   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
4074   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
4075   assert(label_nulls <= 1, "at most one NULL in the batch");
4076 
4077   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4078   int sco_offset = in_bytes(Klass::super_check_offset_offset());
4079   Address super_check_offset_addr(super_klass, sco_offset);
4080 
4081   // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4082   // range of a jccb.  If this routine grows larger, reconsider at
4083   // least some of these.
4084 #define local_jcc(assembler_cond, label)                                \
4085   if (&(label) == &L_fallthrough)  jccb(assembler_cond, label);         \
4086   else                             jcc( assembler_cond, label) /*omit semi*/
4087 
4088   // Hacked jmp, which may only be used just before L_fallthrough.
4089 #define final_jmp(label)                                                \
4090   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
4091   else                            jmp(label)                /*omit semi*/
4092 
4093   // If the pointers are equal, we are done (e.g., String[] elements).
4094   // This self-check enables sharing of secondary supertype arrays among
4095   // non-primary types such as array-of-interface.  Otherwise, each such
4096   // type would need its own customized SSA.
4097   // We move this check to the front of the fast path because many
4098   // type checks are in fact trivially successful in this manner,
4099   // so we get a nicely predicted branch right at the start of the check.
4100   cmpptr(sub_klass, super_klass);
4101   local_jcc(Assembler::equal, *L_success);
4102 
4103   // Check the supertype display:
4104   if (must_load_sco) {
4105     // Positive movl does right thing on LP64.
4106     movl(temp_reg, super_check_offset_addr);
4107     super_check_offset = RegisterOrConstant(temp_reg);
4108   }
4109   Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4110   cmpptr(super_klass, super_check_addr); // load displayed supertype
4111 
4112   // This check has worked decisively for primary supers.
4113   // Secondary supers are sought in the super_cache ('super_cache_addr').
4114   // (Secondary supers are interfaces and very deeply nested subtypes.)
4115   // This works in the same check above because of a tricky aliasing
4116   // between the super_cache and the primary super display elements.
4117   // (The 'super_check_addr' can address either, as the case requires.)
4118   // Note that the cache is updated below if it does not help us find
4119   // what we need immediately.
4120   // So if it was a primary super, we can just fail immediately.
4121   // Otherwise, it's the slow path for us (no success at this point).
4122 
4123   if (super_check_offset.is_register()) {
4124     local_jcc(Assembler::equal, *L_success);
4125     cmpl(super_check_offset.as_register(), sc_offset);
4126     if (L_failure == &L_fallthrough) {
4127       local_jcc(Assembler::equal, *L_slow_path);
4128     } else {
4129       local_jcc(Assembler::notEqual, *L_failure);
4130       final_jmp(*L_slow_path);
4131     }
4132   } else if (super_check_offset.as_constant() == sc_offset) {
4133     // Need a slow path; fast failure is impossible.
4134     if (L_slow_path == &L_fallthrough) {
4135       local_jcc(Assembler::equal, *L_success);
4136     } else {
4137       local_jcc(Assembler::notEqual, *L_slow_path);
4138       final_jmp(*L_success);
4139     }
4140   } else {
4141     // No slow path; it's a fast decision.
4142     if (L_failure == &L_fallthrough) {
4143       local_jcc(Assembler::equal, *L_success);
4144     } else {
4145       local_jcc(Assembler::notEqual, *L_failure);
4146       final_jmp(*L_success);
4147     }
4148   }
4149 
4150   bind(L_fallthrough);
4151 
4152 #undef local_jcc
4153 #undef final_jmp
4154 }
4155 
4156 
4157 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4158                                                    Register super_klass,
4159                                                    Register temp_reg,
4160                                                    Register temp2_reg,
4161                                                    Label* L_success,
4162                                                    Label* L_failure,
4163                                                    bool set_cond_codes) {
4164   assert_different_registers(sub_klass, super_klass, temp_reg);
4165   if (temp2_reg != noreg)
4166     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4167 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4168 
4169   Label L_fallthrough;
4170   int label_nulls = 0;
4171   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
4172   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
4173   assert(label_nulls <= 1, "at most one NULL in the batch");
4174 
4175   // a couple of useful fields in sub_klass:
4176   int ss_offset = in_bytes(Klass::secondary_supers_offset());
4177   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4178   Address secondary_supers_addr(sub_klass, ss_offset);
4179   Address super_cache_addr(     sub_klass, sc_offset);
4180 
4181   // Do a linear scan of the secondary super-klass chain.
4182   // This code is rarely used, so simplicity is a virtue here.
4183   // The repne_scan instruction uses fixed registers, which we must spill.
4184   // Don't worry too much about pre-existing connections with the input regs.
4185 
4186   assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4187   assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4188 
4189   // Get super_klass value into rax (even if it was in rdi or rcx).
4190   bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4191   if (super_klass != rax || UseCompressedOops) {
4192     if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4193     mov(rax, super_klass);
4194   }
4195   if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4196   if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4197 
4198 #ifndef PRODUCT
4199   int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4200   ExternalAddress pst_counter_addr((address) pst_counter);
4201   NOT_LP64(  incrementl(pst_counter_addr) );
4202   LP64_ONLY( lea(rcx, pst_counter_addr) );
4203   LP64_ONLY( incrementl(Address(rcx, 0)) );
4204 #endif //PRODUCT
4205 
4206   // We will consult the secondary-super array.
4207   movptr(rdi, secondary_supers_addr);
4208   // Load the array length.  (Positive movl does right thing on LP64.)
4209   movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4210   // Skip to start of data.
4211   addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4212 
4213   // Scan RCX words at [RDI] for an occurrence of RAX.
4214   // Set NZ/Z based on last compare.
4215   // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4216   // not change flags (only scas instruction which is repeated sets flags).
4217   // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4218 
4219     testptr(rax,rax); // Set Z = 0
4220     repne_scan();
4221 
4222   // Unspill the temp. registers:
4223   if (pushed_rdi)  pop(rdi);
4224   if (pushed_rcx)  pop(rcx);
4225   if (pushed_rax)  pop(rax);
4226 
4227   if (set_cond_codes) {
4228     // Special hack for the AD files:  rdi is guaranteed non-zero.
4229     assert(!pushed_rdi, "rdi must be left non-NULL");
4230     // Also, the condition codes are properly set Z/NZ on succeed/failure.
4231   }
4232 
4233   if (L_failure == &L_fallthrough)
4234         jccb(Assembler::notEqual, *L_failure);
4235   else  jcc(Assembler::notEqual, *L_failure);
4236 
4237   // Success.  Cache the super we found and proceed in triumph.
4238   movptr(super_cache_addr, super_klass);
4239 
4240   if (L_success != &L_fallthrough) {
4241     jmp(*L_success);
4242   }
4243 
4244 #undef IS_A_TEMP
4245 
4246   bind(L_fallthrough);
4247 }
4248 
4249 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
4250   assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
4251 
4252   Label L_fallthrough;
4253   if (L_fast_path == NULL) {
4254     L_fast_path = &L_fallthrough;
4255   } else if (L_slow_path == NULL) {
4256     L_slow_path = &L_fallthrough;
4257   }
4258 
4259   // Fast path check: class is fully initialized
4260   cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4261   jcc(Assembler::equal, *L_fast_path);
4262 
4263   // Fast path check: current thread is initializer thread
4264   cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
4265   if (L_slow_path == &L_fallthrough) {
4266     jcc(Assembler::equal, *L_fast_path);
4267     bind(*L_slow_path);
4268   } else if (L_fast_path == &L_fallthrough) {
4269     jcc(Assembler::notEqual, *L_slow_path);
4270     bind(*L_fast_path);
4271   } else {
4272     Unimplemented();
4273   }
4274 }
4275 
4276 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4277   if (VM_Version::supports_cmov()) {
4278     cmovl(cc, dst, src);
4279   } else {
4280     Label L;
4281     jccb(negate_condition(cc), L);
4282     movl(dst, src);
4283     bind(L);
4284   }
4285 }
4286 
4287 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4288   if (VM_Version::supports_cmov()) {
4289     cmovl(cc, dst, src);
4290   } else {
4291     Label L;
4292     jccb(negate_condition(cc), L);
4293     movl(dst, src);
4294     bind(L);
4295   }
4296 }
4297 
4298 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4299   if (!VerifyOops || VerifyAdapterSharing) {
4300     // Below address of the code string confuses VerifyAdapterSharing
4301     // because it may differ between otherwise equivalent adapters.
4302     return;
4303   }
4304 
4305   // Pass register number to verify_oop_subroutine
4306   const char* b = NULL;
4307   {
4308     ResourceMark rm;
4309     stringStream ss;
4310     ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4311     b = code_string(ss.as_string());
4312   }
4313   BLOCK_COMMENT("verify_oop {");
4314 #ifdef _LP64
4315   push(rscratch1);                    // save r10, trashed by movptr()
4316 #endif
4317   push(rax);                          // save rax,
4318   push(reg);                          // pass register argument
4319   ExternalAddress buffer((address) b);
4320   // avoid using pushptr, as it modifies scratch registers
4321   // and our contract is not to modify anything
4322   movptr(rax, buffer.addr());
4323   push(rax);
4324   // call indirectly to solve generation ordering problem
4325   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4326   call(rax);
4327   // Caller pops the arguments (oop, message) and restores rax, r10
4328   BLOCK_COMMENT("} verify_oop");
4329 }
4330 
4331 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4332   if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4333     vpternlogd(dst, 0xFF, dst, dst, vector_len);
4334   } else {
4335     assert(UseAVX > 0, "");
4336     vpcmpeqb(dst, dst, dst, vector_len);
4337   }
4338 }
4339 
4340 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4341                                          int extra_slot_offset) {
4342   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4343   int stackElementSize = Interpreter::stackElementSize;
4344   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4345 #ifdef ASSERT
4346   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4347   assert(offset1 - offset == stackElementSize, "correct arithmetic");
4348 #endif
4349   Register             scale_reg    = noreg;
4350   Address::ScaleFactor scale_factor = Address::no_scale;
4351   if (arg_slot.is_constant()) {
4352     offset += arg_slot.as_constant() * stackElementSize;
4353   } else {
4354     scale_reg    = arg_slot.as_register();
4355     scale_factor = Address::times(stackElementSize);
4356   }
4357   offset += wordSize;           // return PC is on stack
4358   return Address(rsp, scale_reg, scale_factor, offset);
4359 }
4360 
4361 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
4362   if (!VerifyOops || VerifyAdapterSharing) {
4363     // Below address of the code string confuses VerifyAdapterSharing
4364     // because it may differ between otherwise equivalent adapters.
4365     return;
4366   }
4367 
4368   // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4369   // Pass register number to verify_oop_subroutine
4370   const char* b = NULL;
4371   {
4372     ResourceMark rm;
4373     stringStream ss;
4374     ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
4375     b = code_string(ss.as_string());
4376   }
4377 #ifdef _LP64
4378   push(rscratch1);                    // save r10, trashed by movptr()
4379 #endif
4380   push(rax);                          // save rax,
4381   // addr may contain rsp so we will have to adjust it based on the push
4382   // we just did (and on 64 bit we do two pushes)
4383   // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4384   // stores rax into addr which is backwards of what was intended.
4385   if (addr.uses(rsp)) {
4386     lea(rax, addr);
4387     pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4388   } else {
4389     pushptr(addr);
4390   }
4391 
4392   ExternalAddress buffer((address) b);
4393   // pass msg argument
4394   // avoid using pushptr, as it modifies scratch registers
4395   // and our contract is not to modify anything
4396   movptr(rax, buffer.addr());
4397   push(rax);
4398 
4399   // call indirectly to solve generation ordering problem
4400   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4401   call(rax);
4402   // Caller pops the arguments (addr, message) and restores rax, r10.
4403 }
4404 
4405 void MacroAssembler::verify_tlab() {
4406 #ifdef ASSERT
4407   if (UseTLAB && VerifyOops) {
4408     Label next, ok;
4409     Register t1 = rsi;
4410     Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4411 
4412     push(t1);
4413     NOT_LP64(push(thread_reg));
4414     NOT_LP64(get_thread(thread_reg));
4415 
4416     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4417     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4418     jcc(Assembler::aboveEqual, next);
4419     STOP("assert(top >= start)");
4420     should_not_reach_here();
4421 
4422     bind(next);
4423     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4424     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4425     jcc(Assembler::aboveEqual, ok);
4426     STOP("assert(top <= end)");
4427     should_not_reach_here();
4428 
4429     bind(ok);
4430     NOT_LP64(pop(thread_reg));
4431     pop(t1);
4432   }
4433 #endif
4434 }
4435 
4436 class ControlWord {
4437  public:
4438   int32_t _value;
4439 
4440   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
4441   int  precision_control() const       { return  (_value >>  8) & 3      ; }
4442   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4443   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4444   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4445   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4446   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4447   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4448 
4449   void print() const {
4450     // rounding control
4451     const char* rc;
4452     switch (rounding_control()) {
4453       case 0: rc = "round near"; break;
4454       case 1: rc = "round down"; break;
4455       case 2: rc = "round up  "; break;
4456       case 3: rc = "chop      "; break;
4457       default:
4458         rc = NULL; // silence compiler warnings
4459         fatal("Unknown rounding control: %d", rounding_control());
4460     };
4461     // precision control
4462     const char* pc;
4463     switch (precision_control()) {
4464       case 0: pc = "24 bits "; break;
4465       case 1: pc = "reserved"; break;
4466       case 2: pc = "53 bits "; break;
4467       case 3: pc = "64 bits "; break;
4468       default:
4469         pc = NULL; // silence compiler warnings
4470         fatal("Unknown precision control: %d", precision_control());
4471     };
4472     // flags
4473     char f[9];
4474     f[0] = ' ';
4475     f[1] = ' ';
4476     f[2] = (precision   ()) ? 'P' : 'p';
4477     f[3] = (underflow   ()) ? 'U' : 'u';
4478     f[4] = (overflow    ()) ? 'O' : 'o';
4479     f[5] = (zero_divide ()) ? 'Z' : 'z';
4480     f[6] = (denormalized()) ? 'D' : 'd';
4481     f[7] = (invalid     ()) ? 'I' : 'i';
4482     f[8] = '\x0';
4483     // output
4484     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4485   }
4486 
4487 };
4488 
4489 class StatusWord {
4490  public:
4491   int32_t _value;
4492 
4493   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
4494   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
4495   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
4496   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
4497   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
4498   int  top() const                     { return  (_value >> 11) & 7      ; }
4499   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
4500   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
4501   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4502   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4503   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4504   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4505   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4506   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4507 
4508   void print() const {
4509     // condition codes
4510     char c[5];
4511     c[0] = (C3()) ? '3' : '-';
4512     c[1] = (C2()) ? '2' : '-';
4513     c[2] = (C1()) ? '1' : '-';
4514     c[3] = (C0()) ? '0' : '-';
4515     c[4] = '\x0';
4516     // flags
4517     char f[9];
4518     f[0] = (error_status()) ? 'E' : '-';
4519     f[1] = (stack_fault ()) ? 'S' : '-';
4520     f[2] = (precision   ()) ? 'P' : '-';
4521     f[3] = (underflow   ()) ? 'U' : '-';
4522     f[4] = (overflow    ()) ? 'O' : '-';
4523     f[5] = (zero_divide ()) ? 'Z' : '-';
4524     f[6] = (denormalized()) ? 'D' : '-';
4525     f[7] = (invalid     ()) ? 'I' : '-';
4526     f[8] = '\x0';
4527     // output
4528     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
4529   }
4530 
4531 };
4532 
4533 class TagWord {
4534  public:
4535   int32_t _value;
4536 
4537   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
4538 
4539   void print() const {
4540     printf("%04x", _value & 0xFFFF);
4541   }
4542 
4543 };
4544 
4545 class FPU_Register {
4546  public:
4547   int32_t _m0;
4548   int32_t _m1;
4549   int16_t _ex;
4550 
4551   bool is_indefinite() const           {
4552     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4553   }
4554 
4555   void print() const {
4556     char  sign = (_ex < 0) ? '-' : '+';
4557     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
4558     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
4559   };
4560 
4561 };
4562 
4563 class FPU_State {
4564  public:
4565   enum {
4566     register_size       = 10,
4567     number_of_registers =  8,
4568     register_mask       =  7
4569   };
4570 
4571   ControlWord  _control_word;
4572   StatusWord   _status_word;
4573   TagWord      _tag_word;
4574   int32_t      _error_offset;
4575   int32_t      _error_selector;
4576   int32_t      _data_offset;
4577   int32_t      _data_selector;
4578   int8_t       _register[register_size * number_of_registers];
4579 
4580   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4581   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
4582 
4583   const char* tag_as_string(int tag) const {
4584     switch (tag) {
4585       case 0: return "valid";
4586       case 1: return "zero";
4587       case 2: return "special";
4588       case 3: return "empty";
4589     }
4590     ShouldNotReachHere();
4591     return NULL;
4592   }
4593 
4594   void print() const {
4595     // print computation registers
4596     { int t = _status_word.top();
4597       for (int i = 0; i < number_of_registers; i++) {
4598         int j = (i - t) & register_mask;
4599         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4600         st(j)->print();
4601         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4602       }
4603     }
4604     printf("\n");
4605     // print control registers
4606     printf("ctrl = "); _control_word.print(); printf("\n");
4607     printf("stat = "); _status_word .print(); printf("\n");
4608     printf("tags = "); _tag_word    .print(); printf("\n");
4609   }
4610 
4611 };
4612 
4613 class Flag_Register {
4614  public:
4615   int32_t _value;
4616 
4617   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
4618   bool direction() const               { return ((_value >> 10) & 1) != 0; }
4619   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
4620   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
4621   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
4622   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
4623   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
4624 
4625   void print() const {
4626     // flags
4627     char f[8];
4628     f[0] = (overflow       ()) ? 'O' : '-';
4629     f[1] = (direction      ()) ? 'D' : '-';
4630     f[2] = (sign           ()) ? 'S' : '-';
4631     f[3] = (zero           ()) ? 'Z' : '-';
4632     f[4] = (auxiliary_carry()) ? 'A' : '-';
4633     f[5] = (parity         ()) ? 'P' : '-';
4634     f[6] = (carry          ()) ? 'C' : '-';
4635     f[7] = '\x0';
4636     // output
4637     printf("%08x  flags = %s", _value, f);
4638   }
4639 
4640 };
4641 
4642 class IU_Register {
4643  public:
4644   int32_t _value;
4645 
4646   void print() const {
4647     printf("%08x  %11d", _value, _value);
4648   }
4649 
4650 };
4651 
4652 class IU_State {
4653  public:
4654   Flag_Register _eflags;
4655   IU_Register   _rdi;
4656   IU_Register   _rsi;
4657   IU_Register   _rbp;
4658   IU_Register   _rsp;
4659   IU_Register   _rbx;
4660   IU_Register   _rdx;
4661   IU_Register   _rcx;
4662   IU_Register   _rax;
4663 
4664   void print() const {
4665     // computation registers
4666     printf("rax,  = "); _rax.print(); printf("\n");
4667     printf("rbx,  = "); _rbx.print(); printf("\n");
4668     printf("rcx  = "); _rcx.print(); printf("\n");
4669     printf("rdx  = "); _rdx.print(); printf("\n");
4670     printf("rdi  = "); _rdi.print(); printf("\n");
4671     printf("rsi  = "); _rsi.print(); printf("\n");
4672     printf("rbp,  = "); _rbp.print(); printf("\n");
4673     printf("rsp  = "); _rsp.print(); printf("\n");
4674     printf("\n");
4675     // control registers
4676     printf("flgs = "); _eflags.print(); printf("\n");
4677   }
4678 };
4679 
4680 
4681 class CPU_State {
4682  public:
4683   FPU_State _fpu_state;
4684   IU_State  _iu_state;
4685 
4686   void print() const {
4687     printf("--------------------------------------------------\n");
4688     _iu_state .print();
4689     printf("\n");
4690     _fpu_state.print();
4691     printf("--------------------------------------------------\n");
4692   }
4693 
4694 };
4695 
4696 
4697 static void _print_CPU_state(CPU_State* state) {
4698   state->print();
4699 };
4700 
4701 
4702 void MacroAssembler::print_CPU_state() {
4703   push_CPU_state();
4704   push(rsp);                // pass CPU state
4705   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
4706   addptr(rsp, wordSize);       // discard argument
4707   pop_CPU_state();
4708 }
4709 
4710 
4711 #ifndef _LP64
4712 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
4713   static int counter = 0;
4714   FPU_State* fs = &state->_fpu_state;
4715   counter++;
4716   // For leaf calls, only verify that the top few elements remain empty.
4717   // We only need 1 empty at the top for C2 code.
4718   if( stack_depth < 0 ) {
4719     if( fs->tag_for_st(7) != 3 ) {
4720       printf("FPR7 not empty\n");
4721       state->print();
4722       assert(false, "error");
4723       return false;
4724     }
4725     return true;                // All other stack states do not matter
4726   }
4727 
4728   assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
4729          "bad FPU control word");
4730 
4731   // compute stack depth
4732   int i = 0;
4733   while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
4734   int d = i;
4735   while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
4736   // verify findings
4737   if (i != FPU_State::number_of_registers) {
4738     // stack not contiguous
4739     printf("%s: stack not contiguous at ST%d\n", s, i);
4740     state->print();
4741     assert(false, "error");
4742     return false;
4743   }
4744   // check if computed stack depth corresponds to expected stack depth
4745   if (stack_depth < 0) {
4746     // expected stack depth is -stack_depth or less
4747     if (d > -stack_depth) {
4748       // too many elements on the stack
4749       printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
4750       state->print();
4751       assert(false, "error");
4752       return false;
4753     }
4754   } else {
4755     // expected stack depth is stack_depth
4756     if (d != stack_depth) {
4757       // wrong stack depth
4758       printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
4759       state->print();
4760       assert(false, "error");
4761       return false;
4762     }
4763   }
4764   // everything is cool
4765   return true;
4766 }
4767 
4768 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
4769   if (!VerifyFPU) return;
4770   push_CPU_state();
4771   push(rsp);                // pass CPU state
4772   ExternalAddress msg((address) s);
4773   // pass message string s
4774   pushptr(msg.addr());
4775   push(stack_depth);        // pass stack depth
4776   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
4777   addptr(rsp, 3 * wordSize);   // discard arguments
4778   // check for error
4779   { Label L;
4780     testl(rax, rax);
4781     jcc(Assembler::notZero, L);
4782     int3();                  // break if error condition
4783     bind(L);
4784   }
4785   pop_CPU_state();
4786 }
4787 #endif // _LP64
4788 
4789 void MacroAssembler::restore_cpu_control_state_after_jni() {
4790   // Either restore the MXCSR register after returning from the JNI Call
4791   // or verify that it wasn't changed (with -Xcheck:jni flag).
4792   if (VM_Version::supports_sse()) {
4793     if (RestoreMXCSROnJNICalls) {
4794       ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()));
4795     } else if (CheckJNICalls) {
4796       call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
4797     }
4798   }
4799   // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
4800   vzeroupper();
4801   // Reset k1 to 0xffff.
4802 
4803 #ifdef COMPILER2
4804   if (PostLoopMultiversioning && VM_Version::supports_evex()) {
4805     push(rcx);
4806     movl(rcx, 0xffff);
4807     kmovwl(k1, rcx);
4808     pop(rcx);
4809   }
4810 #endif // COMPILER2
4811 
4812 #ifndef _LP64
4813   // Either restore the x87 floating pointer control word after returning
4814   // from the JNI call or verify that it wasn't changed.
4815   if (CheckJNICalls) {
4816     call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
4817   }
4818 #endif // _LP64
4819 }
4820 
4821 // ((OopHandle)result).resolve();
4822 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
4823   assert_different_registers(result, tmp);
4824 
4825   // Only 64 bit platforms support GCs that require a tmp register
4826   // Only IN_HEAP loads require a thread_tmp register
4827   // OopHandle::resolve is an indirection like jobject.
4828   access_load_at(T_OBJECT, IN_NATIVE,
4829                  result, Address(result, 0), tmp, /*tmp_thread*/noreg);
4830 }
4831 
4832 // ((WeakHandle)result).resolve();
4833 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
4834   assert_different_registers(rresult, rtmp);
4835   Label resolved;
4836 
4837   // A null weak handle resolves to null.
4838   cmpptr(rresult, 0);
4839   jcc(Assembler::equal, resolved);
4840 
4841   // Only 64 bit platforms support GCs that require a tmp register
4842   // Only IN_HEAP loads require a thread_tmp register
4843   // WeakHandle::resolve is an indirection like jweak.
4844   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4845                  rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
4846   bind(resolved);
4847 }
4848 
4849 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
4850   // get mirror
4851   const int mirror_offset = in_bytes(Klass::java_mirror_offset());
4852   load_method_holder(mirror, method);
4853   movptr(mirror, Address(mirror, mirror_offset));
4854   resolve_oop_handle(mirror, tmp);
4855 }
4856 
4857 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4858   load_method_holder(rresult, rmethod);
4859   movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4860 }
4861 
4862 void MacroAssembler::load_method_holder(Register holder, Register method) {
4863   movptr(holder, Address(method, Method::const_offset()));                      // ConstMethod*
4864   movptr(holder, Address(holder, ConstMethod::constants_offset()));             // ConstantPool*
4865   movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
4866 }
4867 
4868 void MacroAssembler::load_metadata(Register dst, Register src) {
4869   if (UseCompressedClassPointers) {
4870     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4871   } else {
4872     movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4873   }
4874 }
4875 
4876 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
4877   assert_different_registers(src, tmp);
4878   assert_different_registers(dst, tmp);
4879 #ifdef _LP64
4880   if (UseCompressedClassPointers) {
4881     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4882     decode_klass_not_null(dst, tmp);
4883   } else
4884 #endif
4885   movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4886 }
4887 
4888 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
4889   load_klass(dst, src, tmp);
4890   movptr(dst, Address(dst, Klass::prototype_header_offset()));
4891 }
4892 
4893 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
4894   assert_different_registers(src, tmp);
4895   assert_different_registers(dst, tmp);
4896 #ifdef _LP64
4897   if (UseCompressedClassPointers) {
4898     encode_klass_not_null(src, tmp);
4899     movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4900   } else
4901 #endif
4902     movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4903 }
4904 
4905 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
4906                                     Register tmp1, Register thread_tmp) {
4907   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4908   decorators = AccessInternal::decorator_fixup(decorators);
4909   bool as_raw = (decorators & AS_RAW) != 0;
4910   if (as_raw) {
4911     bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4912   } else {
4913     bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4914   }
4915 }
4916 
4917 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
4918                                      Register tmp1, Register tmp2, Register tmp3) {
4919   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4920   decorators = AccessInternal::decorator_fixup(decorators);
4921   bool as_raw = (decorators & AS_RAW) != 0;
4922   if (as_raw) {
4923     bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2, tmp3);
4924   } else {
4925     bs->store_at(this, decorators, type, dst, src, tmp1, tmp2, tmp3);
4926   }
4927 }
4928 
4929 void MacroAssembler::access_value_copy(DecoratorSet decorators, Register src, Register dst,
4930                                        Register inline_klass) {
4931   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4932   bs->value_copy(this, decorators, src, dst, inline_klass);
4933 }
4934 
4935 void MacroAssembler::first_field_offset(Register inline_klass, Register offset) {
4936   movptr(offset, Address(inline_klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
4937   movl(offset, Address(offset, InlineKlass::first_field_offset_offset()));
4938 }
4939 
4940 void MacroAssembler::data_for_oop(Register oop, Register data, Register inline_klass) {
4941   // ((address) (void*) o) + vk->first_field_offset();
4942   Register offset = (data == oop) ? rscratch1 : data;
4943   first_field_offset(inline_klass, offset);
4944   if (data == oop) {
4945     addptr(data, offset);
4946   } else {
4947     lea(data, Address(oop, offset));
4948   }
4949 }
4950 
4951 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
4952                                                 Register index, Register data) {
4953   assert(index != rcx, "index needs to shift by rcx");
4954   assert_different_registers(array, array_klass, index);
4955   assert_different_registers(rcx, array, index);
4956 
4957   // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
4958   movl(rcx, Address(array_klass, Klass::layout_helper_offset()));
4959 
4960   // Klass::layout_helper_log2_element_size(lh)
4961   // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
4962   shrl(rcx, Klass::_lh_log2_element_size_shift);
4963   andl(rcx, Klass::_lh_log2_element_size_mask);
4964   shlptr(index); // index << rcx
4965 
4966   lea(data, Address(array, index, Address::times_1, arrayOopDesc::base_offset_in_bytes(T_INLINE_TYPE)));
4967 }
4968 
4969 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
4970                                    Register thread_tmp, DecoratorSet decorators) {
4971   access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
4972 }
4973 
4974 // Doesn't do verfication, generates fixed size code
4975 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4976                                             Register thread_tmp, DecoratorSet decorators) {
4977   access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
4978 }
4979 
4980 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
4981                                     Register tmp2, Register tmp3, DecoratorSet decorators) {
4982   access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2, tmp3);
4983 }
4984 
4985 // Used for storing NULLs.
4986 void MacroAssembler::store_heap_oop_null(Address dst) {
4987   access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
4988 }
4989 
4990 #ifdef _LP64
4991 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4992   if (UseCompressedClassPointers) {
4993     // Store to klass gap in destination
4994     movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
4995   }
4996 }
4997 
4998 #ifdef ASSERT
4999 void MacroAssembler::verify_heapbase(const char* msg) {
5000   assert (UseCompressedOops, "should be compressed");
5001   assert (Universe::heap() != NULL, "java heap should be initialized");
5002   if (CheckCompressedOops) {
5003     Label ok;
5004     push(rscratch1); // cmpptr trashes rscratch1
5005     cmpptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5006     jcc(Assembler::equal, ok);
5007     STOP(msg);
5008     bind(ok);
5009     pop(rscratch1);
5010   }
5011 }
5012 #endif
5013 
5014 // Algorithm must match oop.inline.hpp encode_heap_oop.
5015 void MacroAssembler::encode_heap_oop(Register r) {
5016 #ifdef ASSERT
5017   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5018 #endif
5019   verify_oop_msg(r, "broken oop in encode_heap_oop");
5020   if (CompressedOops::base() == NULL) {
5021     if (CompressedOops::shift() != 0) {
5022       assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5023       shrq(r, LogMinObjAlignmentInBytes);
5024     }
5025     return;
5026   }
5027   testq(r, r);
5028   cmovq(Assembler::equal, r, r12_heapbase);
5029   subq(r, r12_heapbase);
5030   shrq(r, LogMinObjAlignmentInBytes);
5031 }
5032 
5033 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5034 #ifdef ASSERT
5035   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5036   if (CheckCompressedOops) {
5037     Label ok;
5038     testq(r, r);
5039     jcc(Assembler::notEqual, ok);
5040     STOP("null oop passed to encode_heap_oop_not_null");
5041     bind(ok);
5042   }
5043 #endif
5044   verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5045   if (CompressedOops::base() != NULL) {
5046     subq(r, r12_heapbase);
5047   }
5048   if (CompressedOops::shift() != 0) {
5049     assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5050     shrq(r, LogMinObjAlignmentInBytes);
5051   }
5052 }
5053 
5054 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5055 #ifdef ASSERT
5056   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5057   if (CheckCompressedOops) {
5058     Label ok;
5059     testq(src, src);
5060     jcc(Assembler::notEqual, ok);
5061     STOP("null oop passed to encode_heap_oop_not_null2");
5062     bind(ok);
5063   }
5064 #endif
5065   verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5066   if (dst != src) {
5067     movq(dst, src);
5068   }
5069   if (CompressedOops::base() != NULL) {
5070     subq(dst, r12_heapbase);
5071   }
5072   if (CompressedOops::shift() != 0) {
5073     assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5074     shrq(dst, LogMinObjAlignmentInBytes);
5075   }
5076 }
5077 
5078 void  MacroAssembler::decode_heap_oop(Register r) {
5079 #ifdef ASSERT
5080   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5081 #endif
5082   if (CompressedOops::base() == NULL) {
5083     if (CompressedOops::shift() != 0) {
5084       assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5085       shlq(r, LogMinObjAlignmentInBytes);
5086     }
5087   } else {
5088     Label done;
5089     shlq(r, LogMinObjAlignmentInBytes);
5090     jccb(Assembler::equal, done);
5091     addq(r, r12_heapbase);
5092     bind(done);
5093   }
5094   verify_oop_msg(r, "broken oop in decode_heap_oop");
5095 }
5096 
5097 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
5098   // Note: it will change flags
5099   assert (UseCompressedOops, "should only be used for compressed headers");
5100   assert (Universe::heap() != NULL, "java heap should be initialized");
5101   // Cannot assert, unverified entry point counts instructions (see .ad file)
5102   // vtableStubs also counts instructions in pd_code_size_limit.
5103   // Also do not verify_oop as this is called by verify_oop.
5104   if (CompressedOops::shift() != 0) {
5105     assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5106     shlq(r, LogMinObjAlignmentInBytes);
5107     if (CompressedOops::base() != NULL) {
5108       addq(r, r12_heapbase);
5109     }
5110   } else {
5111     assert (CompressedOops::base() == NULL, "sanity");
5112   }
5113 }
5114 
5115 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5116   // Note: it will change flags
5117   assert (UseCompressedOops, "should only be used for compressed headers");
5118   assert (Universe::heap() != NULL, "java heap should be initialized");
5119   // Cannot assert, unverified entry point counts instructions (see .ad file)
5120   // vtableStubs also counts instructions in pd_code_size_limit.
5121   // Also do not verify_oop as this is called by verify_oop.
5122   if (CompressedOops::shift() != 0) {
5123     assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5124     if (LogMinObjAlignmentInBytes == Address::times_8) {
5125       leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5126     } else {
5127       if (dst != src) {
5128         movq(dst, src);
5129       }
5130       shlq(dst, LogMinObjAlignmentInBytes);
5131       if (CompressedOops::base() != NULL) {
5132         addq(dst, r12_heapbase);
5133       }
5134     }
5135   } else {
5136     assert (CompressedOops::base() == NULL, "sanity");
5137     if (dst != src) {
5138       movq(dst, src);
5139     }
5140   }
5141 }
5142 
5143 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5144   assert_different_registers(r, tmp);
5145   if (CompressedKlassPointers::base() != NULL) {
5146     mov64(tmp, (int64_t)CompressedKlassPointers::base());
5147     subq(r, tmp);
5148   }
5149   if (CompressedKlassPointers::shift() != 0) {
5150     assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5151     shrq(r, LogKlassAlignmentInBytes);
5152   }
5153 }
5154 
5155 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5156   assert_different_registers(src, dst);
5157   if (CompressedKlassPointers::base() != NULL) {
5158     mov64(dst, -(int64_t)CompressedKlassPointers::base());
5159     addq(dst, src);
5160   } else {
5161     movptr(dst, src);
5162   }
5163   if (CompressedKlassPointers::shift() != 0) {
5164     assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5165     shrq(dst, LogKlassAlignmentInBytes);
5166   }
5167 }
5168 
5169 // !!! If the instructions that get generated here change then function
5170 // instr_size_for_decode_klass_not_null() needs to get updated.
5171 void  MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5172   assert_different_registers(r, tmp);
5173   // Note: it will change flags
5174   assert(UseCompressedClassPointers, "should only be used for compressed headers");
5175   // Cannot assert, unverified entry point counts instructions (see .ad file)
5176   // vtableStubs also counts instructions in pd_code_size_limit.
5177   // Also do not verify_oop as this is called by verify_oop.
5178   if (CompressedKlassPointers::shift() != 0) {
5179     assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5180     shlq(r, LogKlassAlignmentInBytes);
5181   }
5182   if (CompressedKlassPointers::base() != NULL) {
5183     mov64(tmp, (int64_t)CompressedKlassPointers::base());
5184     addq(r, tmp);
5185   }
5186 }
5187 
5188 void  MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5189   assert_different_registers(src, dst);
5190   // Note: it will change flags
5191   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5192   // Cannot assert, unverified entry point counts instructions (see .ad file)
5193   // vtableStubs also counts instructions in pd_code_size_limit.
5194   // Also do not verify_oop as this is called by verify_oop.
5195 
5196   if (CompressedKlassPointers::base() == NULL &&
5197       CompressedKlassPointers::shift() == 0) {
5198     // The best case scenario is that there is no base or shift. Then it is already
5199     // a pointer that needs nothing but a register rename.
5200     movl(dst, src);
5201   } else {
5202     if (CompressedKlassPointers::base() != NULL) {
5203       mov64(dst, (int64_t)CompressedKlassPointers::base());
5204     } else {
5205       xorq(dst, dst);
5206     }
5207     if (CompressedKlassPointers::shift() != 0) {
5208       assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5209       assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5210       leaq(dst, Address(dst, src, Address::times_8, 0));
5211     } else {
5212       addq(dst, src);
5213     }
5214   }
5215 }
5216 
5217 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5218   assert (UseCompressedOops, "should only be used for compressed headers");
5219   assert (Universe::heap() != NULL, "java heap should be initialized");
5220   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5221   int oop_index = oop_recorder()->find_index(obj);
5222   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5223   mov_narrow_oop(dst, oop_index, rspec);
5224 }
5225 
5226 void  MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5227   assert (UseCompressedOops, "should only be used for compressed headers");
5228   assert (Universe::heap() != NULL, "java heap should be initialized");
5229   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5230   int oop_index = oop_recorder()->find_index(obj);
5231   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5232   mov_narrow_oop(dst, oop_index, rspec);
5233 }
5234 
5235 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5236   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5237   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5238   int klass_index = oop_recorder()->find_index(k);
5239   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5240   mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5241 }
5242 
5243 void  MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5244   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5245   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5246   int klass_index = oop_recorder()->find_index(k);
5247   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5248   mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5249 }
5250 
5251 void  MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5252   assert (UseCompressedOops, "should only be used for compressed headers");
5253   assert (Universe::heap() != NULL, "java heap should be initialized");
5254   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5255   int oop_index = oop_recorder()->find_index(obj);
5256   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5257   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5258 }
5259 
5260 void  MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5261   assert (UseCompressedOops, "should only be used for compressed headers");
5262   assert (Universe::heap() != NULL, "java heap should be initialized");
5263   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5264   int oop_index = oop_recorder()->find_index(obj);
5265   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5266   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5267 }
5268 
5269 void  MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5270   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5271   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5272   int klass_index = oop_recorder()->find_index(k);
5273   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5274   Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5275 }
5276 
5277 void  MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5278   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5279   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5280   int klass_index = oop_recorder()->find_index(k);
5281   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5282   Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5283 }
5284 
5285 void MacroAssembler::reinit_heapbase() {
5286   if (UseCompressedOops) {
5287     if (Universe::heap() != NULL) {
5288       if (CompressedOops::base() == NULL) {
5289         MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5290       } else {
5291         mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
5292       }
5293     } else {
5294       movptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5295     }
5296   }
5297 }
5298 
5299 #endif // _LP64
5300 
5301 #ifdef COMPILER2
5302 // C2 compiled method's prolog code.
5303 void MacroAssembler::verified_entry(Compile* C, int sp_inc) {
5304   int framesize = C->output()->frame_size_in_bytes();
5305   int bangsize = C->output()->bang_size_in_bytes();
5306   bool fp_mode_24b = false;
5307   int stack_bang_size = C->output()->need_stack_bang(bangsize) ? bangsize : 0;
5308 
5309   // WARNING: Initial instruction MUST be 5 bytes or longer so that
5310   // NativeJump::patch_verified_entry will be able to patch out the entry
5311   // code safely. The push to verify stack depth is ok at 5 bytes,
5312   // the frame allocation can be either 3 or 6 bytes. So if we don't do
5313   // stack bang then we must use the 6 byte frame allocation even if
5314   // we have no frame. :-(
5315   assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
5316 
5317   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5318   // Remove word for return addr
5319   framesize -= wordSize;
5320   stack_bang_size -= wordSize;
5321 
5322   // Calls to C2R adapters often do not accept exceptional returns.
5323   // We require that their callers must bang for them.  But be careful, because
5324   // some VM calls (such as call site linkage) can use several kilobytes of
5325   // stack.  But the stack safety zone should account for that.
5326   // See bugs 4446381, 4468289, 4497237.
5327   if (stack_bang_size > 0) {
5328     generate_stack_overflow_check(stack_bang_size);
5329 
5330     // We always push rbp, so that on return to interpreter rbp, will be
5331     // restored correctly and we can correct the stack.
5332     push(rbp);
5333     // Save caller's stack pointer into RBP if the frame pointer is preserved.
5334     if (PreserveFramePointer) {
5335       mov(rbp, rsp);
5336     }
5337     // Remove word for ebp
5338     framesize -= wordSize;
5339 
5340     // Create frame
5341     if (framesize) {
5342       subptr(rsp, framesize);
5343     }
5344   } else {
5345     // Create frame (force generation of a 4 byte immediate value)
5346     subptr_imm32(rsp, framesize);
5347 
5348     // Save RBP register now.
5349     framesize -= wordSize;
5350     movptr(Address(rsp, framesize), rbp);
5351     // Save caller's stack pointer into RBP if the frame pointer is preserved.
5352     if (PreserveFramePointer) {
5353       movptr(rbp, rsp);
5354       if (framesize > 0) {
5355         addptr(rbp, framesize);
5356       }
5357     }
5358   }
5359 
5360   if (C->needs_stack_repair()) {
5361     // Save stack increment just below the saved rbp (also account for fixed framesize and rbp)
5362     assert((sp_inc & (StackAlignmentInBytes-1)) == 0, "stack increment not aligned");
5363     movptr(Address(rsp, framesize - wordSize), sp_inc + framesize + wordSize);
5364   }
5365 
5366   if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5367     framesize -= wordSize;
5368     movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5369   }
5370 
5371 #ifndef _LP64
5372   // If method sets FPU control word do it now
5373   if (fp_mode_24b) {
5374     fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_24()));
5375   }
5376   if (UseSSE >= 2 && VerifyFPU) {
5377     verify_FPU(0, "FPU stack must be clean on entry");
5378   }
5379 #endif
5380 
5381 #ifdef ASSERT
5382   if (VerifyStackAtCalls) {
5383     Label L;
5384     push(rax);
5385     mov(rax, rsp);
5386     andptr(rax, StackAlignmentInBytes-1);
5387     cmpptr(rax, StackAlignmentInBytes-wordSize);
5388     pop(rax);
5389     jcc(Assembler::equal, L);
5390     STOP("Stack is not properly aligned!");
5391     bind(L);
5392   }
5393 #endif
5394 }
5395 #endif // COMPILER2
5396 
5397 #if COMPILER2_OR_JVMCI
5398 
5399 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
5400 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
5401   // cnt - number of qwords (8-byte words).
5402   // base - start address, qword aligned.
5403   Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5404   bool use64byteVector = MaxVectorSize == 64 && AVX3Threshold == 0;
5405   if (use64byteVector) {
5406     evpbroadcastq(xtmp, val, AVX_512bit);
5407   } else if (MaxVectorSize >= 32) {
5408     movdq(xtmp, val);
5409     punpcklqdq(xtmp, xtmp);
5410     vinserti128_high(xtmp, xtmp);
5411   } else {
5412     movdq(xtmp, val);
5413     punpcklqdq(xtmp, xtmp);
5414   }
5415   jmp(L_zero_64_bytes);
5416 
5417   BIND(L_loop);
5418   if (MaxVectorSize >= 32) {
5419     fill64_avx(base, 0, xtmp, use64byteVector);
5420   } else {
5421     movdqu(Address(base,  0), xtmp);
5422     movdqu(Address(base, 16), xtmp);
5423     movdqu(Address(base, 32), xtmp);
5424     movdqu(Address(base, 48), xtmp);
5425   }
5426   addptr(base, 64);
5427 
5428   BIND(L_zero_64_bytes);
5429   subptr(cnt, 8);
5430   jccb(Assembler::greaterEqual, L_loop);
5431 
5432   // Copy trailing 64 bytes
5433   if (use64byteVector) {
5434     addptr(cnt, 8);
5435     jccb(Assembler::equal, L_end);
5436     fill64_masked_avx(3, base, 0, xtmp, mask, cnt, val, true);
5437     jmp(L_end);
5438   } else {
5439     addptr(cnt, 4);
5440     jccb(Assembler::less, L_tail);
5441     if (MaxVectorSize >= 32) {
5442       vmovdqu(Address(base, 0), xtmp);
5443     } else {
5444       movdqu(Address(base,  0), xtmp);
5445       movdqu(Address(base, 16), xtmp);
5446     }
5447   }
5448   addptr(base, 32);
5449   subptr(cnt, 4);
5450 
5451   BIND(L_tail);
5452   addptr(cnt, 4);
5453   jccb(Assembler::lessEqual, L_end);
5454   if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
5455     fill32_masked_avx(3, base, 0, xtmp, mask, cnt, val);
5456   } else {
5457     decrement(cnt);
5458 
5459     BIND(L_sloop);
5460     movq(Address(base, 0), xtmp);
5461     addptr(base, 8);
5462     decrement(cnt);
5463     jccb(Assembler::greaterEqual, L_sloop);
5464   }
5465   BIND(L_end);
5466 }
5467 
5468 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
5469   // An inline type might be returned. If fields are in registers we
5470   // need to allocate an inline type instance and initialize it with
5471   // the value of the fields.
5472   Label skip;
5473   // We only need a new buffered inline type if a new one is not returned
5474   testptr(rax, 1);
5475   jcc(Assembler::zero, skip);
5476   int call_offset = -1;
5477 
5478 #ifdef _LP64
5479   // The following code is similar to allocate_instance but has some slight differences,
5480   // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
5481   // allocating is not necessary if vk != NULL, etc. allocate_instance is not aware of these.
5482   Label slow_case;
5483   // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
5484   mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
5485   if (vk != NULL) {
5486     // Called from C1, where the return type is statically known.
5487     movptr(rbx, (intptr_t)vk->get_InlineKlass());
5488     jint obj_size = vk->layout_helper();
5489     assert(obj_size != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
5490     if (UseTLAB) {
5491       tlab_allocate(r15_thread, rax, noreg, obj_size, r13, r14, slow_case);
5492     } else {
5493       eden_allocate(r15_thread, rax, noreg, obj_size, r13, slow_case);
5494     }
5495   } else {
5496     // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
5497     mov(rbx, rax);
5498     andptr(rbx, -2);
5499     movl(r14, Address(rbx, Klass::layout_helper_offset()));
5500     if (UseTLAB) {
5501       tlab_allocate(r15_thread, rax, r14, 0, r13, r14, slow_case);
5502     } else {
5503       eden_allocate(r15_thread, rax, r14, 0, r13, slow_case);
5504     }
5505   }
5506   if (UseTLAB || Universe::heap()->supports_inline_contig_alloc()) {
5507     // 2. Initialize buffered inline instance header
5508     Register buffer_obj = rax;
5509     movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
5510     xorl(r13, r13);
5511     store_klass_gap(buffer_obj, r13);
5512     if (vk == NULL) {
5513       // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
5514       mov(r13, rbx);
5515     }
5516     Register tmp_store_klass = LP64_ONLY(rscratch1) NOT_LP64(noreg);
5517     store_klass(buffer_obj, rbx, tmp_store_klass);
5518     // 3. Initialize its fields with an inline class specific handler
5519     if (vk != NULL) {
5520       call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
5521     } else {
5522       movptr(rbx, Address(r13, InstanceKlass::adr_inlineklass_fixed_block_offset()));
5523       movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
5524       call(rbx);
5525     }
5526     jmp(skip);
5527   }
5528   bind(slow_case);
5529   // We failed to allocate a new inline type, fall back to a runtime
5530   // call. Some oop field may be live in some registers but we can't
5531   // tell. That runtime call will take care of preserving them
5532   // across a GC if there's one.
5533   mov(rax, rscratch1);
5534 #endif
5535 
5536   if (from_interpreter) {
5537     super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
5538   } else {
5539     call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
5540     call_offset = offset();
5541   }
5542 
5543   bind(skip);
5544   return call_offset;
5545 }
5546 
5547 // Move a value between registers/stack slots and update the reg_state
5548 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
5549   assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
5550   if (reg_state[to->value()] == reg_written) {
5551     return true; // Already written
5552   }
5553   if (from != to && bt != T_VOID) {
5554     if (reg_state[to->value()] == reg_readonly) {
5555       return false; // Not yet writable
5556     }
5557     if (from->is_reg()) {
5558       if (to->is_reg()) {
5559         if (from->is_XMMRegister()) {
5560           if (bt == T_DOUBLE) {
5561             movdbl(to->as_XMMRegister(), from->as_XMMRegister());
5562           } else {
5563             assert(bt == T_FLOAT, "must be float");
5564             movflt(to->as_XMMRegister(), from->as_XMMRegister());
5565           }
5566         } else {
5567           movq(to->as_Register(), from->as_Register());
5568         }
5569       } else {
5570         int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
5571         Address to_addr = Address(rsp, st_off);
5572         if (from->is_XMMRegister()) {
5573           if (bt == T_DOUBLE) {
5574             movdbl(to_addr, from->as_XMMRegister());
5575           } else {
5576             assert(bt == T_FLOAT, "must be float");
5577             movflt(to_addr, from->as_XMMRegister());
5578           }
5579         } else {
5580           movq(to_addr, from->as_Register());
5581         }
5582       }
5583     } else {
5584       Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
5585       if (to->is_reg()) {
5586         if (to->is_XMMRegister()) {
5587           if (bt == T_DOUBLE) {
5588             movdbl(to->as_XMMRegister(), from_addr);
5589           } else {
5590             assert(bt == T_FLOAT, "must be float");
5591             movflt(to->as_XMMRegister(), from_addr);
5592           }
5593         } else {
5594           movq(to->as_Register(), from_addr);
5595         }
5596       } else {
5597         int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
5598         movq(r13, from_addr);
5599         movq(Address(rsp, st_off), r13);
5600       }
5601     }
5602   }
5603   // Update register states
5604   reg_state[from->value()] = reg_writable;
5605   reg_state[to->value()] = reg_written;
5606   return true;
5607 }
5608 
5609 // Calculate the extra stack space required for packing or unpacking inline
5610 // args and adjust the stack pointer
5611 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
5612   // Two additional slots to account for return address
5613   int sp_inc = (args_on_stack + 2) * VMRegImpl::stack_slot_size;
5614   sp_inc = align_up(sp_inc, StackAlignmentInBytes);
5615   // Save the return address, adjust the stack (make sure it is properly
5616   // 16-byte aligned) and copy the return address to the new top of the stack.
5617   // The stack will be repaired on return (see MacroAssembler::remove_frame).
5618   assert(sp_inc > 0, "sanity");
5619   pop(r13);
5620   subptr(rsp, sp_inc);
5621   push(r13);
5622   return sp_inc;
5623 }
5624 
5625 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
5626 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
5627                                           VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
5628                                           RegState reg_state[]) {
5629   assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
5630   assert(from->is_valid(), "source must be valid");
5631   Register fromReg;
5632   if (from->is_reg()) {
5633     fromReg = from->as_Register();
5634   } else {
5635     int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
5636     movq(r10, Address(rsp, st_off));
5637     fromReg = r10;
5638   }
5639 
5640   ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
5641   bool done = true;
5642   bool mark_done = true;
5643   VMReg toReg;
5644   BasicType bt;
5645   while (stream.next(toReg, bt)) {
5646     assert(toReg->is_valid(), "destination must be valid");
5647     int off = sig->at(stream.sig_index())._offset;
5648     assert(off > 0, "offset in object should be positive");
5649     Address fromAddr = Address(fromReg, off);
5650 
5651     int idx = (int)toReg->value();
5652     if (reg_state[idx] == reg_readonly) {
5653      if (idx != from->value()) {
5654        mark_done = false;
5655      }
5656      done = false;
5657      continue;
5658     } else if (reg_state[idx] == reg_written) {
5659       continue;
5660     } else {
5661       assert(reg_state[idx] == reg_writable, "must be writable");
5662       reg_state[idx] = reg_written;
5663     }
5664 
5665     if (!toReg->is_XMMRegister()) {
5666       Register dst = toReg->is_stack() ? r13 : toReg->as_Register();
5667       if (is_reference_type(bt)) {
5668         load_heap_oop(dst, fromAddr);
5669       } else {
5670         bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
5671         load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
5672       }
5673       if (toReg->is_stack()) {
5674         int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
5675         movq(Address(rsp, st_off), dst);
5676       }
5677     } else if (bt == T_DOUBLE) {
5678       movdbl(toReg->as_XMMRegister(), fromAddr);
5679     } else {
5680       assert(bt == T_FLOAT, "must be float");
5681       movflt(toReg->as_XMMRegister(), fromAddr);
5682     }
5683   }
5684   sig_index = stream.sig_index();
5685   to_index = stream.regs_index();
5686 
5687   if (mark_done && reg_state[from->value()] != reg_written) {
5688     // This is okay because no one else will write to that slot
5689     reg_state[from->value()] = reg_writable;
5690   }
5691   from_index--;
5692   return done;
5693 }
5694 
5695 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
5696                                         VMRegPair* from, int from_count, int& from_index, VMReg to,
5697                                         RegState reg_state[], Register val_array) {
5698   assert(sig->at(sig_index)._bt == T_INLINE_TYPE, "should be at end delimiter");
5699   assert(to->is_valid(), "destination must be valid");
5700 
5701   if (reg_state[to->value()] == reg_written) {
5702     skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
5703     return true; // Already written
5704   }
5705 
5706   Register val_obj_tmp = r11;
5707   Register from_reg_tmp = r14; // Be careful with r14 because it's used for spilling
5708   Register tmp1 = r10;
5709   Register tmp2 = r13;
5710   Register tmp3 = rbx;
5711   Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
5712 
5713   assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
5714 
5715   if (reg_state[to->value()] == reg_readonly) {
5716     if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
5717       skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
5718       return false; // Not yet writable
5719     }
5720     val_obj = val_obj_tmp;
5721   }
5722 
5723   int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_INLINE_TYPE);
5724   load_heap_oop(val_obj, Address(val_array, index));
5725 
5726   ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
5727   VMReg fromReg;
5728   BasicType bt;
5729   while (stream.next(fromReg, bt)) {
5730     assert(fromReg->is_valid(), "source must be valid");
5731     int off = sig->at(stream.sig_index())._offset;
5732     assert(off > 0, "offset in object should be positive");
5733     size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
5734 
5735     Address dst(val_obj, off);
5736     if (!fromReg->is_XMMRegister()) {
5737       Register src;
5738       if (fromReg->is_stack()) {
5739         src = from_reg_tmp;
5740         int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
5741         load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
5742       } else {
5743         src = fromReg->as_Register();
5744       }
5745       assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
5746       if (is_reference_type(bt)) {
5747         store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
5748       } else {
5749         store_sized_value(dst, src, size_in_bytes);
5750       }
5751     } else if (bt == T_DOUBLE) {
5752       movdbl(dst, fromReg->as_XMMRegister());
5753     } else {
5754       assert(bt == T_FLOAT, "must be float");
5755       movflt(dst, fromReg->as_XMMRegister());
5756     }
5757     reg_state[fromReg->value()] = reg_writable;
5758   }
5759   sig_index = stream.sig_index();
5760   from_index = stream.regs_index();
5761 
5762   assert(reg_state[to->value()] == reg_writable, "must have already been read");
5763   bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
5764   assert(success, "to register must be writeable");
5765   return true;
5766 }
5767 
5768 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
5769   return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
5770 }
5771 
5772 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
5773   assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5774   if (needs_stack_repair) {
5775     movq(rbp, Address(rsp, initial_framesize));
5776     // The stack increment resides just below the saved rbp
5777     addq(rsp, Address(rsp, initial_framesize - wordSize));
5778   } else {
5779     if (initial_framesize > 0) {
5780       addq(rsp, initial_framesize);
5781     }
5782     pop(rbp);
5783   }
5784 }
5785 
5786 // Clearing constant sized memory using YMM/ZMM registers.
5787 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5788   assert(UseAVX > 2 && VM_Version::supports_avx512vlbw(), "");
5789   bool use64byteVector = MaxVectorSize > 32 && AVX3Threshold == 0;
5790 
5791   int vector64_count = (cnt & (~0x7)) >> 3;
5792   cnt = cnt & 0x7;
5793 
5794   // 64 byte initialization loop.
5795   vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
5796   for (int i = 0; i < vector64_count; i++) {
5797     fill64_avx(base, i * 64, xtmp, use64byteVector);
5798   }
5799 
5800   // Clear remaining 64 byte tail.
5801   int disp = vector64_count * 64;
5802   if (cnt) {
5803     switch (cnt) {
5804       case 1:
5805         movq(Address(base, disp), xtmp);
5806         break;
5807       case 2:
5808         evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_128bit);
5809         break;
5810       case 3:
5811         movl(rtmp, 0x7);
5812         kmovwl(mask, rtmp);
5813         evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_256bit);
5814         break;
5815       case 4:
5816         evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5817         break;
5818       case 5:
5819         if (use64byteVector) {
5820           movl(rtmp, 0x1F);
5821           kmovwl(mask, rtmp);
5822           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5823         } else {
5824           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5825           movq(Address(base, disp + 32), xtmp);
5826         }
5827         break;
5828       case 6:
5829         if (use64byteVector) {
5830           movl(rtmp, 0x3F);
5831           kmovwl(mask, rtmp);
5832           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5833         } else {
5834           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5835           evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, Assembler::AVX_128bit);
5836         }
5837         break;
5838       case 7:
5839         if (use64byteVector) {
5840           movl(rtmp, 0x7F);
5841           kmovwl(mask, rtmp);
5842           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5843         } else {
5844           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5845           movl(rtmp, 0x7);
5846           kmovwl(mask, rtmp);
5847           evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, Assembler::AVX_256bit);
5848         }
5849         break;
5850       default:
5851         fatal("Unexpected length : %d\n",cnt);
5852         break;
5853     }
5854   }
5855 }
5856 
5857 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
5858                                bool is_large, bool word_copy_only, KRegister mask) {
5859   // cnt      - number of qwords (8-byte words).
5860   // base     - start address, qword aligned.
5861   // is_large - if optimizers know cnt is larger than InitArrayShortSize
5862   assert(base==rdi, "base register must be edi for rep stos");
5863   assert(val==rax,   "val register must be eax for rep stos");
5864   assert(cnt==rcx,   "cnt register must be ecx for rep stos");
5865   assert(InitArrayShortSize % BytesPerLong == 0,
5866     "InitArrayShortSize should be the multiple of BytesPerLong");
5867 
5868   Label DONE;
5869 
5870   if (!is_large) {
5871     Label LOOP, LONG;
5872     cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5873     jccb(Assembler::greater, LONG);
5874 
5875     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5876 
5877     decrement(cnt);
5878     jccb(Assembler::negative, DONE); // Zero length
5879 
5880     // Use individual pointer-sized stores for small counts:
5881     BIND(LOOP);
5882     movptr(Address(base, cnt, Address::times_ptr), val);
5883     decrement(cnt);
5884     jccb(Assembler::greaterEqual, LOOP);
5885     jmpb(DONE);
5886 
5887     BIND(LONG);
5888   }
5889 
5890   // Use longer rep-prefixed ops for non-small counts:
5891   if (UseFastStosb && !word_copy_only) {
5892     shlptr(cnt, 3); // convert to number of bytes
5893     rep_stosb();
5894   } else if (UseXMMForObjInit) {
5895     xmm_clear_mem(base, cnt, val, xtmp, mask);
5896   } else {
5897     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5898     rep_stos();
5899   }
5900 
5901   BIND(DONE);
5902 }
5903 
5904 #endif //COMPILER2_OR_JVMCI
5905 
5906 
5907 void MacroAssembler::generate_fill(BasicType t, bool aligned,
5908                                    Register to, Register value, Register count,
5909                                    Register rtmp, XMMRegister xtmp) {
5910   ShortBranchVerifier sbv(this);
5911   assert_different_registers(to, value, count, rtmp);
5912   Label L_exit;
5913   Label L_fill_2_bytes, L_fill_4_bytes;
5914 
5915   int shift = -1;
5916   switch (t) {
5917     case T_BYTE:
5918       shift = 2;
5919       break;
5920     case T_SHORT:
5921       shift = 1;
5922       break;
5923     case T_INT:
5924       shift = 0;
5925       break;
5926     default: ShouldNotReachHere();
5927   }
5928 
5929   if (t == T_BYTE) {
5930     andl(value, 0xff);
5931     movl(rtmp, value);
5932     shll(rtmp, 8);
5933     orl(value, rtmp);
5934   }
5935   if (t == T_SHORT) {
5936     andl(value, 0xffff);
5937   }
5938   if (t == T_BYTE || t == T_SHORT) {
5939     movl(rtmp, value);
5940     shll(rtmp, 16);
5941     orl(value, rtmp);
5942   }
5943 
5944   cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
5945   jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
5946   if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
5947     Label L_skip_align2;
5948     // align source address at 4 bytes address boundary
5949     if (t == T_BYTE) {
5950       Label L_skip_align1;
5951       // One byte misalignment happens only for byte arrays
5952       testptr(to, 1);
5953       jccb(Assembler::zero, L_skip_align1);
5954       movb(Address(to, 0), value);
5955       increment(to);
5956       decrement(count);
5957       BIND(L_skip_align1);
5958     }
5959     // Two bytes misalignment happens only for byte and short (char) arrays
5960     testptr(to, 2);
5961     jccb(Assembler::zero, L_skip_align2);
5962     movw(Address(to, 0), value);
5963     addptr(to, 2);
5964     subl(count, 1<<(shift-1));
5965     BIND(L_skip_align2);
5966   }
5967   if (UseSSE < 2) {
5968     Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
5969     // Fill 32-byte chunks
5970     subl(count, 8 << shift);
5971     jcc(Assembler::less, L_check_fill_8_bytes);
5972     align(16);
5973 
5974     BIND(L_fill_32_bytes_loop);
5975 
5976     for (int i = 0; i < 32; i += 4) {
5977       movl(Address(to, i), value);
5978     }
5979 
5980     addptr(to, 32);
5981     subl(count, 8 << shift);
5982     jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
5983     BIND(L_check_fill_8_bytes);
5984     addl(count, 8 << shift);
5985     jccb(Assembler::zero, L_exit);
5986     jmpb(L_fill_8_bytes);
5987 
5988     //
5989     // length is too short, just fill qwords
5990     //
5991     BIND(L_fill_8_bytes_loop);
5992     movl(Address(to, 0), value);
5993     movl(Address(to, 4), value);
5994     addptr(to, 8);
5995     BIND(L_fill_8_bytes);
5996     subl(count, 1 << (shift + 1));
5997     jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
5998     // fall through to fill 4 bytes
5999   } else {
6000     Label L_fill_32_bytes;
6001     if (!UseUnalignedLoadStores) {
6002       // align to 8 bytes, we know we are 4 byte aligned to start
6003       testptr(to, 4);
6004       jccb(Assembler::zero, L_fill_32_bytes);
6005       movl(Address(to, 0), value);
6006       addptr(to, 4);
6007       subl(count, 1<<shift);
6008     }
6009     BIND(L_fill_32_bytes);
6010     {
6011       assert( UseSSE >= 2, "supported cpu only" );
6012       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6013       movdl(xtmp, value);
6014       if (UseAVX >= 2 && UseUnalignedLoadStores) {
6015         Label L_check_fill_32_bytes;
6016         if (UseAVX > 2) {
6017           // Fill 64-byte chunks
6018           Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6019 
6020           // If number of bytes to fill < AVX3Threshold, perform fill using AVX2
6021           cmpl(count, AVX3Threshold);
6022           jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6023 
6024           vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6025 
6026           subl(count, 16 << shift);
6027           jccb(Assembler::less, L_check_fill_32_bytes);
6028           align(16);
6029 
6030           BIND(L_fill_64_bytes_loop_avx3);
6031           evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6032           addptr(to, 64);
6033           subl(count, 16 << shift);
6034           jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6035           jmpb(L_check_fill_32_bytes);
6036 
6037           BIND(L_check_fill_64_bytes_avx2);
6038         }
6039         // Fill 64-byte chunks
6040         Label L_fill_64_bytes_loop;
6041         vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6042 
6043         subl(count, 16 << shift);
6044         jcc(Assembler::less, L_check_fill_32_bytes);
6045         align(16);
6046 
6047         BIND(L_fill_64_bytes_loop);
6048         vmovdqu(Address(to, 0), xtmp);
6049         vmovdqu(Address(to, 32), xtmp);
6050         addptr(to, 64);
6051         subl(count, 16 << shift);
6052         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6053 
6054         BIND(L_check_fill_32_bytes);
6055         addl(count, 8 << shift);
6056         jccb(Assembler::less, L_check_fill_8_bytes);
6057         vmovdqu(Address(to, 0), xtmp);
6058         addptr(to, 32);
6059         subl(count, 8 << shift);
6060 
6061         BIND(L_check_fill_8_bytes);
6062         // clean upper bits of YMM registers
6063         movdl(xtmp, value);
6064         pshufd(xtmp, xtmp, 0);
6065       } else {
6066         // Fill 32-byte chunks
6067         pshufd(xtmp, xtmp, 0);
6068 
6069         subl(count, 8 << shift);
6070         jcc(Assembler::less, L_check_fill_8_bytes);
6071         align(16);
6072 
6073         BIND(L_fill_32_bytes_loop);
6074 
6075         if (UseUnalignedLoadStores) {
6076           movdqu(Address(to, 0), xtmp);
6077           movdqu(Address(to, 16), xtmp);
6078         } else {
6079           movq(Address(to, 0), xtmp);
6080           movq(Address(to, 8), xtmp);
6081           movq(Address(to, 16), xtmp);
6082           movq(Address(to, 24), xtmp);
6083         }
6084 
6085         addptr(to, 32);
6086         subl(count, 8 << shift);
6087         jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6088 
6089         BIND(L_check_fill_8_bytes);
6090       }
6091       addl(count, 8 << shift);
6092       jccb(Assembler::zero, L_exit);
6093       jmpb(L_fill_8_bytes);
6094 
6095       //
6096       // length is too short, just fill qwords
6097       //
6098       BIND(L_fill_8_bytes_loop);
6099       movq(Address(to, 0), xtmp);
6100       addptr(to, 8);
6101       BIND(L_fill_8_bytes);
6102       subl(count, 1 << (shift + 1));
6103       jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6104     }
6105   }
6106   // fill trailing 4 bytes
6107   BIND(L_fill_4_bytes);
6108   testl(count, 1<<shift);
6109   jccb(Assembler::zero, L_fill_2_bytes);
6110   movl(Address(to, 0), value);
6111   if (t == T_BYTE || t == T_SHORT) {
6112     Label L_fill_byte;
6113     addptr(to, 4);
6114     BIND(L_fill_2_bytes);
6115     // fill trailing 2 bytes
6116     testl(count, 1<<(shift-1));
6117     jccb(Assembler::zero, L_fill_byte);
6118     movw(Address(to, 0), value);
6119     if (t == T_BYTE) {
6120       addptr(to, 2);
6121       BIND(L_fill_byte);
6122       // fill trailing byte
6123       testl(count, 1);
6124       jccb(Assembler::zero, L_exit);
6125       movb(Address(to, 0), value);
6126     } else {
6127       BIND(L_fill_byte);
6128     }
6129   } else {
6130     BIND(L_fill_2_bytes);
6131   }
6132   BIND(L_exit);
6133 }
6134 
6135 // encode char[] to byte[] in ISO_8859_1 or ASCII
6136    //@IntrinsicCandidate
6137    //private static int implEncodeISOArray(byte[] sa, int sp,
6138    //byte[] da, int dp, int len) {
6139    //  int i = 0;
6140    //  for (; i < len; i++) {
6141    //    char c = StringUTF16.getChar(sa, sp++);
6142    //    if (c > '\u00FF')
6143    //      break;
6144    //    da[dp++] = (byte)c;
6145    //  }
6146    //  return i;
6147    //}
6148    //
6149    //@IntrinsicCandidate
6150    //private static int implEncodeAsciiArray(char[] sa, int sp,
6151    //    byte[] da, int dp, int len) {
6152    //  int i = 0;
6153    //  for (; i < len; i++) {
6154    //    char c = sa[sp++];
6155    //    if (c >= '\u0080')
6156    //      break;
6157    //    da[dp++] = (byte)c;
6158    //  }
6159    //  return i;
6160    //}
6161 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6162   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6163   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6164   Register tmp5, Register result, bool ascii) {
6165 
6166   // rsi: src
6167   // rdi: dst
6168   // rdx: len
6169   // rcx: tmp5
6170   // rax: result
6171   ShortBranchVerifier sbv(this);
6172   assert_different_registers(src, dst, len, tmp5, result);
6173   Label L_done, L_copy_1_char, L_copy_1_char_exit;
6174 
6175   int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6176   int short_mask = ascii ? 0xff80 : 0xff00;
6177 
6178   // set result
6179   xorl(result, result);
6180   // check for zero length
6181   testl(len, len);
6182   jcc(Assembler::zero, L_done);
6183 
6184   movl(result, len);
6185 
6186   // Setup pointers
6187   lea(src, Address(src, len, Address::times_2)); // char[]
6188   lea(dst, Address(dst, len, Address::times_1)); // byte[]
6189   negptr(len);
6190 
6191   if (UseSSE42Intrinsics || UseAVX >= 2) {
6192     Label L_copy_8_chars, L_copy_8_chars_exit;
6193     Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6194 
6195     if (UseAVX >= 2) {
6196       Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6197       movl(tmp5, mask);   // create mask to test for Unicode or non-ASCII chars in vector
6198       movdl(tmp1Reg, tmp5);
6199       vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6200       jmp(L_chars_32_check);
6201 
6202       bind(L_copy_32_chars);
6203       vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6204       vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6205       vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6206       vptest(tmp2Reg, tmp1Reg);       // check for Unicode or non-ASCII chars in vector
6207       jccb(Assembler::notZero, L_copy_32_chars_exit);
6208       vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6209       vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6210       vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6211 
6212       bind(L_chars_32_check);
6213       addptr(len, 32);
6214       jcc(Assembler::lessEqual, L_copy_32_chars);
6215 
6216       bind(L_copy_32_chars_exit);
6217       subptr(len, 16);
6218       jccb(Assembler::greater, L_copy_16_chars_exit);
6219 
6220     } else if (UseSSE42Intrinsics) {
6221       movl(tmp5, mask);   // create mask to test for Unicode or non-ASCII chars in vector
6222       movdl(tmp1Reg, tmp5);
6223       pshufd(tmp1Reg, tmp1Reg, 0);
6224       jmpb(L_chars_16_check);
6225     }
6226 
6227     bind(L_copy_16_chars);
6228     if (UseAVX >= 2) {
6229       vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6230       vptest(tmp2Reg, tmp1Reg);
6231       jcc(Assembler::notZero, L_copy_16_chars_exit);
6232       vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6233       vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6234     } else {
6235       if (UseAVX > 0) {
6236         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6237         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6238         vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6239       } else {
6240         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6241         por(tmp2Reg, tmp3Reg);
6242         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6243         por(tmp2Reg, tmp4Reg);
6244       }
6245       ptest(tmp2Reg, tmp1Reg);       // check for Unicode or non-ASCII chars in vector
6246       jccb(Assembler::notZero, L_copy_16_chars_exit);
6247       packuswb(tmp3Reg, tmp4Reg);
6248     }
6249     movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
6250 
6251     bind(L_chars_16_check);
6252     addptr(len, 16);
6253     jcc(Assembler::lessEqual, L_copy_16_chars);
6254 
6255     bind(L_copy_16_chars_exit);
6256     if (UseAVX >= 2) {
6257       // clean upper bits of YMM registers
6258       vpxor(tmp2Reg, tmp2Reg);
6259       vpxor(tmp3Reg, tmp3Reg);
6260       vpxor(tmp4Reg, tmp4Reg);
6261       movdl(tmp1Reg, tmp5);
6262       pshufd(tmp1Reg, tmp1Reg, 0);
6263     }
6264     subptr(len, 8);
6265     jccb(Assembler::greater, L_copy_8_chars_exit);
6266 
6267     bind(L_copy_8_chars);
6268     movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
6269     ptest(tmp3Reg, tmp1Reg);
6270     jccb(Assembler::notZero, L_copy_8_chars_exit);
6271     packuswb(tmp3Reg, tmp1Reg);
6272     movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
6273     addptr(len, 8);
6274     jccb(Assembler::lessEqual, L_copy_8_chars);
6275 
6276     bind(L_copy_8_chars_exit);
6277     subptr(len, 8);
6278     jccb(Assembler::zero, L_done);
6279   }
6280 
6281   bind(L_copy_1_char);
6282   load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
6283   testl(tmp5, short_mask);      // check if Unicode or non-ASCII char
6284   jccb(Assembler::notZero, L_copy_1_char_exit);
6285   movb(Address(dst, len, Address::times_1, 0), tmp5);
6286   addptr(len, 1);
6287   jccb(Assembler::less, L_copy_1_char);
6288 
6289   bind(L_copy_1_char_exit);
6290   addptr(result, len); // len is negative count of not processed elements
6291 
6292   bind(L_done);
6293 }
6294 
6295 #ifdef _LP64
6296 /**
6297  * Helper for multiply_to_len().
6298  */
6299 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
6300   addq(dest_lo, src1);
6301   adcq(dest_hi, 0);
6302   addq(dest_lo, src2);
6303   adcq(dest_hi, 0);
6304 }
6305 
6306 /**
6307  * Multiply 64 bit by 64 bit first loop.
6308  */
6309 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
6310                                            Register y, Register y_idx, Register z,
6311                                            Register carry, Register product,
6312                                            Register idx, Register kdx) {
6313   //
6314   //  jlong carry, x[], y[], z[];
6315   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6316   //    huge_128 product = y[idx] * x[xstart] + carry;
6317   //    z[kdx] = (jlong)product;
6318   //    carry  = (jlong)(product >>> 64);
6319   //  }
6320   //  z[xstart] = carry;
6321   //
6322 
6323   Label L_first_loop, L_first_loop_exit;
6324   Label L_one_x, L_one_y, L_multiply;
6325 
6326   decrementl(xstart);
6327   jcc(Assembler::negative, L_one_x);
6328 
6329   movq(x_xstart, Address(x, xstart, Address::times_4,  0));
6330   rorq(x_xstart, 32); // convert big-endian to little-endian
6331 
6332   bind(L_first_loop);
6333   decrementl(idx);
6334   jcc(Assembler::negative, L_first_loop_exit);
6335   decrementl(idx);
6336   jcc(Assembler::negative, L_one_y);
6337   movq(y_idx, Address(y, idx, Address::times_4,  0));
6338   rorq(y_idx, 32); // convert big-endian to little-endian
6339   bind(L_multiply);
6340   movq(product, x_xstart);
6341   mulq(y_idx); // product(rax) * y_idx -> rdx:rax
6342   addq(product, carry);
6343   adcq(rdx, 0);
6344   subl(kdx, 2);
6345   movl(Address(z, kdx, Address::times_4,  4), product);
6346   shrq(product, 32);
6347   movl(Address(z, kdx, Address::times_4,  0), product);
6348   movq(carry, rdx);
6349   jmp(L_first_loop);
6350 
6351   bind(L_one_y);
6352   movl(y_idx, Address(y,  0));
6353   jmp(L_multiply);
6354 
6355   bind(L_one_x);
6356   movl(x_xstart, Address(x,  0));
6357   jmp(L_first_loop);
6358 
6359   bind(L_first_loop_exit);
6360 }
6361 
6362 /**
6363  * Multiply 64 bit by 64 bit and add 128 bit.
6364  */
6365 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
6366                                             Register yz_idx, Register idx,
6367                                             Register carry, Register product, int offset) {
6368   //     huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
6369   //     z[kdx] = (jlong)product;
6370 
6371   movq(yz_idx, Address(y, idx, Address::times_4,  offset));
6372   rorq(yz_idx, 32); // convert big-endian to little-endian
6373   movq(product, x_xstart);
6374   mulq(yz_idx);     // product(rax) * yz_idx -> rdx:product(rax)
6375   movq(yz_idx, Address(z, idx, Address::times_4,  offset));
6376   rorq(yz_idx, 32); // convert big-endian to little-endian
6377 
6378   add2_with_carry(rdx, product, carry, yz_idx);
6379 
6380   movl(Address(z, idx, Address::times_4,  offset+4), product);
6381   shrq(product, 32);
6382   movl(Address(z, idx, Address::times_4,  offset), product);
6383 
6384 }
6385 
6386 /**
6387  * Multiply 128 bit by 128 bit. Unrolled inner loop.
6388  */
6389 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
6390                                              Register yz_idx, Register idx, Register jdx,
6391                                              Register carry, Register product,
6392                                              Register carry2) {
6393   //   jlong carry, x[], y[], z[];
6394   //   int kdx = ystart+1;
6395   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6396   //     huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
6397   //     z[kdx+idx+1] = (jlong)product;
6398   //     jlong carry2  = (jlong)(product >>> 64);
6399   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
6400   //     z[kdx+idx] = (jlong)product;
6401   //     carry  = (jlong)(product >>> 64);
6402   //   }
6403   //   idx += 2;
6404   //   if (idx > 0) {
6405   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
6406   //     z[kdx+idx] = (jlong)product;
6407   //     carry  = (jlong)(product >>> 64);
6408   //   }
6409   //
6410 
6411   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6412 
6413   movl(jdx, idx);
6414   andl(jdx, 0xFFFFFFFC);
6415   shrl(jdx, 2);
6416 
6417   bind(L_third_loop);
6418   subl(jdx, 1);
6419   jcc(Assembler::negative, L_third_loop_exit);
6420   subl(idx, 4);
6421 
6422   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
6423   movq(carry2, rdx);
6424 
6425   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
6426   movq(carry, rdx);
6427   jmp(L_third_loop);
6428 
6429   bind (L_third_loop_exit);
6430 
6431   andl (idx, 0x3);
6432   jcc(Assembler::zero, L_post_third_loop_done);
6433 
6434   Label L_check_1;
6435   subl(idx, 2);
6436   jcc(Assembler::negative, L_check_1);
6437 
6438   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
6439   movq(carry, rdx);
6440 
6441   bind (L_check_1);
6442   addl (idx, 0x2);
6443   andl (idx, 0x1);
6444   subl(idx, 1);
6445   jcc(Assembler::negative, L_post_third_loop_done);
6446 
6447   movl(yz_idx, Address(y, idx, Address::times_4,  0));
6448   movq(product, x_xstart);
6449   mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6450   movl(yz_idx, Address(z, idx, Address::times_4,  0));
6451 
6452   add2_with_carry(rdx, product, yz_idx, carry);
6453 
6454   movl(Address(z, idx, Address::times_4,  0), product);
6455   shrq(product, 32);
6456 
6457   shlq(rdx, 32);
6458   orq(product, rdx);
6459   movq(carry, product);
6460 
6461   bind(L_post_third_loop_done);
6462 }
6463 
6464 /**
6465  * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
6466  *
6467  */
6468 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
6469                                                   Register carry, Register carry2,
6470                                                   Register idx, Register jdx,
6471                                                   Register yz_idx1, Register yz_idx2,
6472                                                   Register tmp, Register tmp3, Register tmp4) {
6473   assert(UseBMI2Instructions, "should be used only when BMI2 is available");
6474 
6475   //   jlong carry, x[], y[], z[];
6476   //   int kdx = ystart+1;
6477   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6478   //     huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
6479   //     jlong carry2  = (jlong)(tmp3 >>> 64);
6480   //     huge_128 tmp4 = (y[idx]   * rdx) + z[kdx+idx] + carry2;
6481   //     carry  = (jlong)(tmp4 >>> 64);
6482   //     z[kdx+idx+1] = (jlong)tmp3;
6483   //     z[kdx+idx] = (jlong)tmp4;
6484   //   }
6485   //   idx += 2;
6486   //   if (idx > 0) {
6487   //     yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
6488   //     z[kdx+idx] = (jlong)yz_idx1;
6489   //     carry  = (jlong)(yz_idx1 >>> 64);
6490   //   }
6491   //
6492 
6493   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6494 
6495   movl(jdx, idx);
6496   andl(jdx, 0xFFFFFFFC);
6497   shrl(jdx, 2);
6498 
6499   bind(L_third_loop);
6500   subl(jdx, 1);
6501   jcc(Assembler::negative, L_third_loop_exit);
6502   subl(idx, 4);
6503 
6504   movq(yz_idx1,  Address(y, idx, Address::times_4,  8));
6505   rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
6506   movq(yz_idx2, Address(y, idx, Address::times_4,  0));
6507   rorxq(yz_idx2, yz_idx2, 32);
6508 
6509   mulxq(tmp4, tmp3, yz_idx1);  //  yz_idx1 * rdx -> tmp4:tmp3
6510   mulxq(carry2, tmp, yz_idx2); //  yz_idx2 * rdx -> carry2:tmp
6511 
6512   movq(yz_idx1,  Address(z, idx, Address::times_4,  8));
6513   rorxq(yz_idx1, yz_idx1, 32);
6514   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
6515   rorxq(yz_idx2, yz_idx2, 32);
6516 
6517   if (VM_Version::supports_adx()) {
6518     adcxq(tmp3, carry);
6519     adoxq(tmp3, yz_idx1);
6520 
6521     adcxq(tmp4, tmp);
6522     adoxq(tmp4, yz_idx2);
6523 
6524     movl(carry, 0); // does not affect flags
6525     adcxq(carry2, carry);
6526     adoxq(carry2, carry);
6527   } else {
6528     add2_with_carry(tmp4, tmp3, carry, yz_idx1);
6529     add2_with_carry(carry2, tmp4, tmp, yz_idx2);
6530   }
6531   movq(carry, carry2);
6532 
6533   movl(Address(z, idx, Address::times_4, 12), tmp3);
6534   shrq(tmp3, 32);
6535   movl(Address(z, idx, Address::times_4,  8), tmp3);
6536 
6537   movl(Address(z, idx, Address::times_4,  4), tmp4);
6538   shrq(tmp4, 32);
6539   movl(Address(z, idx, Address::times_4,  0), tmp4);
6540 
6541   jmp(L_third_loop);
6542 
6543   bind (L_third_loop_exit);
6544 
6545   andl (idx, 0x3);
6546   jcc(Assembler::zero, L_post_third_loop_done);
6547 
6548   Label L_check_1;
6549   subl(idx, 2);
6550   jcc(Assembler::negative, L_check_1);
6551 
6552   movq(yz_idx1, Address(y, idx, Address::times_4,  0));
6553   rorxq(yz_idx1, yz_idx1, 32);
6554   mulxq(tmp4, tmp3, yz_idx1); //  yz_idx1 * rdx -> tmp4:tmp3
6555   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
6556   rorxq(yz_idx2, yz_idx2, 32);
6557 
6558   add2_with_carry(tmp4, tmp3, carry, yz_idx2);
6559 
6560   movl(Address(z, idx, Address::times_4,  4), tmp3);
6561   shrq(tmp3, 32);
6562   movl(Address(z, idx, Address::times_4,  0), tmp3);
6563   movq(carry, tmp4);
6564 
6565   bind (L_check_1);
6566   addl (idx, 0x2);
6567   andl (idx, 0x1);
6568   subl(idx, 1);
6569   jcc(Assembler::negative, L_post_third_loop_done);
6570   movl(tmp4, Address(y, idx, Address::times_4,  0));
6571   mulxq(carry2, tmp3, tmp4);  //  tmp4 * rdx -> carry2:tmp3
6572   movl(tmp4, Address(z, idx, Address::times_4,  0));
6573 
6574   add2_with_carry(carry2, tmp3, tmp4, carry);
6575 
6576   movl(Address(z, idx, Address::times_4,  0), tmp3);
6577   shrq(tmp3, 32);
6578 
6579   shlq(carry2, 32);
6580   orq(tmp3, carry2);
6581   movq(carry, tmp3);
6582 
6583   bind(L_post_third_loop_done);
6584 }
6585 
6586 /**
6587  * Code for BigInteger::multiplyToLen() instrinsic.
6588  *
6589  * rdi: x
6590  * rax: xlen
6591  * rsi: y
6592  * rcx: ylen
6593  * r8:  z
6594  * r11: zlen
6595  * r12: tmp1
6596  * r13: tmp2
6597  * r14: tmp3
6598  * r15: tmp4
6599  * rbx: tmp5
6600  *
6601  */
6602 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
6603                                      Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
6604   ShortBranchVerifier sbv(this);
6605   assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
6606 
6607   push(tmp1);
6608   push(tmp2);
6609   push(tmp3);
6610   push(tmp4);
6611   push(tmp5);
6612 
6613   push(xlen);
6614   push(zlen);
6615 
6616   const Register idx = tmp1;
6617   const Register kdx = tmp2;
6618   const Register xstart = tmp3;
6619 
6620   const Register y_idx = tmp4;
6621   const Register carry = tmp5;
6622   const Register product  = xlen;
6623   const Register x_xstart = zlen;  // reuse register
6624 
6625   // First Loop.
6626   //
6627   //  final static long LONG_MASK = 0xffffffffL;
6628   //  int xstart = xlen - 1;
6629   //  int ystart = ylen - 1;
6630   //  long carry = 0;
6631   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6632   //    long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
6633   //    z[kdx] = (int)product;
6634   //    carry = product >>> 32;
6635   //  }
6636   //  z[xstart] = (int)carry;
6637   //
6638 
6639   movl(idx, ylen);      // idx = ylen;
6640   movl(kdx, zlen);      // kdx = xlen+ylen;
6641   xorq(carry, carry);   // carry = 0;
6642 
6643   Label L_done;
6644 
6645   movl(xstart, xlen);
6646   decrementl(xstart);
6647   jcc(Assembler::negative, L_done);
6648 
6649   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
6650 
6651   Label L_second_loop;
6652   testl(kdx, kdx);
6653   jcc(Assembler::zero, L_second_loop);
6654 
6655   Label L_carry;
6656   subl(kdx, 1);
6657   jcc(Assembler::zero, L_carry);
6658 
6659   movl(Address(z, kdx, Address::times_4,  0), carry);
6660   shrq(carry, 32);
6661   subl(kdx, 1);
6662 
6663   bind(L_carry);
6664   movl(Address(z, kdx, Address::times_4,  0), carry);
6665 
6666   // Second and third (nested) loops.
6667   //
6668   // for (int i = xstart-1; i >= 0; i--) { // Second loop
6669   //   carry = 0;
6670   //   for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
6671   //     long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
6672   //                    (z[k] & LONG_MASK) + carry;
6673   //     z[k] = (int)product;
6674   //     carry = product >>> 32;
6675   //   }
6676   //   z[i] = (int)carry;
6677   // }
6678   //
6679   // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
6680 
6681   const Register jdx = tmp1;
6682 
6683   bind(L_second_loop);
6684   xorl(carry, carry);    // carry = 0;
6685   movl(jdx, ylen);       // j = ystart+1
6686 
6687   subl(xstart, 1);       // i = xstart-1;
6688   jcc(Assembler::negative, L_done);
6689 
6690   push (z);
6691 
6692   Label L_last_x;
6693   lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
6694   subl(xstart, 1);       // i = xstart-1;
6695   jcc(Assembler::negative, L_last_x);
6696 
6697   if (UseBMI2Instructions) {
6698     movq(rdx,  Address(x, xstart, Address::times_4,  0));
6699     rorxq(rdx, rdx, 32); // convert big-endian to little-endian
6700   } else {
6701     movq(x_xstart, Address(x, xstart, Address::times_4,  0));
6702     rorq(x_xstart, 32);  // convert big-endian to little-endian
6703   }
6704 
6705   Label L_third_loop_prologue;
6706   bind(L_third_loop_prologue);
6707 
6708   push (x);
6709   push (xstart);
6710   push (ylen);
6711 
6712 
6713   if (UseBMI2Instructions) {
6714     multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
6715   } else { // !UseBMI2Instructions
6716     multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
6717   }
6718 
6719   pop(ylen);
6720   pop(xlen);
6721   pop(x);
6722   pop(z);
6723 
6724   movl(tmp3, xlen);
6725   addl(tmp3, 1);
6726   movl(Address(z, tmp3, Address::times_4,  0), carry);
6727   subl(tmp3, 1);
6728   jccb(Assembler::negative, L_done);
6729 
6730   shrq(carry, 32);
6731   movl(Address(z, tmp3, Address::times_4,  0), carry);
6732   jmp(L_second_loop);
6733 
6734   // Next infrequent code is moved outside loops.
6735   bind(L_last_x);
6736   if (UseBMI2Instructions) {
6737     movl(rdx, Address(x,  0));
6738   } else {
6739     movl(x_xstart, Address(x,  0));
6740   }
6741   jmp(L_third_loop_prologue);
6742 
6743   bind(L_done);
6744 
6745   pop(zlen);
6746   pop(xlen);
6747 
6748   pop(tmp5);
6749   pop(tmp4);
6750   pop(tmp3);
6751   pop(tmp2);
6752   pop(tmp1);
6753 }
6754 
6755 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
6756   Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
6757   assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
6758   Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
6759   Label VECTOR8_TAIL, VECTOR4_TAIL;
6760   Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
6761   Label SAME_TILL_END, DONE;
6762   Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
6763 
6764   //scale is in rcx in both Win64 and Unix
6765   ShortBranchVerifier sbv(this);
6766 
6767   shlq(length);
6768   xorq(result, result);
6769 
6770   if ((AVX3Threshold == 0) && (UseAVX > 2) &&
6771       VM_Version::supports_avx512vlbw()) {
6772     Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
6773 
6774     cmpq(length, 64);
6775     jcc(Assembler::less, VECTOR32_TAIL);
6776 
6777     movq(tmp1, length);
6778     andq(tmp1, 0x3F);      // tail count
6779     andq(length, ~(0x3F)); //vector count
6780 
6781     bind(VECTOR64_LOOP);
6782     // AVX512 code to compare 64 byte vectors.
6783     evmovdqub(rymm0, Address(obja, result), false, Assembler::AVX_512bit);
6784     evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
6785     kortestql(k7, k7);
6786     jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL);     // mismatch
6787     addq(result, 64);
6788     subq(length, 64);
6789     jccb(Assembler::notZero, VECTOR64_LOOP);
6790 
6791     //bind(VECTOR64_TAIL);
6792     testq(tmp1, tmp1);
6793     jcc(Assembler::zero, SAME_TILL_END);
6794 
6795     //bind(VECTOR64_TAIL);
6796     // AVX512 code to compare upto 63 byte vectors.
6797     mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
6798     shlxq(tmp2, tmp2, tmp1);
6799     notq(tmp2);
6800     kmovql(k3, tmp2);
6801 
6802     evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
6803     evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
6804 
6805     ktestql(k7, k3);
6806     jcc(Assembler::below, SAME_TILL_END);     // not mismatch
6807 
6808     bind(VECTOR64_NOT_EQUAL);
6809     kmovql(tmp1, k7);
6810     notq(tmp1);
6811     tzcntq(tmp1, tmp1);
6812     addq(result, tmp1);
6813     shrq(result);
6814     jmp(DONE);
6815     bind(VECTOR32_TAIL);
6816   }
6817 
6818   cmpq(length, 8);
6819   jcc(Assembler::equal, VECTOR8_LOOP);
6820   jcc(Assembler::less, VECTOR4_TAIL);
6821 
6822   if (UseAVX >= 2) {
6823     Label VECTOR16_TAIL, VECTOR32_LOOP;
6824 
6825     cmpq(length, 16);
6826     jcc(Assembler::equal, VECTOR16_LOOP);
6827     jcc(Assembler::less, VECTOR8_LOOP);
6828 
6829     cmpq(length, 32);
6830     jccb(Assembler::less, VECTOR16_TAIL);
6831 
6832     subq(length, 32);
6833     bind(VECTOR32_LOOP);
6834     vmovdqu(rymm0, Address(obja, result));
6835     vmovdqu(rymm1, Address(objb, result));
6836     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
6837     vptest(rymm2, rymm2);
6838     jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
6839     addq(result, 32);
6840     subq(length, 32);
6841     jcc(Assembler::greaterEqual, VECTOR32_LOOP);
6842     addq(length, 32);
6843     jcc(Assembler::equal, SAME_TILL_END);
6844     //falling through if less than 32 bytes left //close the branch here.
6845 
6846     bind(VECTOR16_TAIL);
6847     cmpq(length, 16);
6848     jccb(Assembler::less, VECTOR8_TAIL);
6849     bind(VECTOR16_LOOP);
6850     movdqu(rymm0, Address(obja, result));
6851     movdqu(rymm1, Address(objb, result));
6852     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
6853     ptest(rymm2, rymm2);
6854     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6855     addq(result, 16);
6856     subq(length, 16);
6857     jcc(Assembler::equal, SAME_TILL_END);
6858     //falling through if less than 16 bytes left
6859   } else {//regular intrinsics
6860 
6861     cmpq(length, 16);
6862     jccb(Assembler::less, VECTOR8_TAIL);
6863 
6864     subq(length, 16);
6865     bind(VECTOR16_LOOP);
6866     movdqu(rymm0, Address(obja, result));
6867     movdqu(rymm1, Address(objb, result));
6868     pxor(rymm0, rymm1);
6869     ptest(rymm0, rymm0);
6870     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6871     addq(result, 16);
6872     subq(length, 16);
6873     jccb(Assembler::greaterEqual, VECTOR16_LOOP);
6874     addq(length, 16);
6875     jcc(Assembler::equal, SAME_TILL_END);
6876     //falling through if less than 16 bytes left
6877   }
6878 
6879   bind(VECTOR8_TAIL);
6880   cmpq(length, 8);
6881   jccb(Assembler::less, VECTOR4_TAIL);
6882   bind(VECTOR8_LOOP);
6883   movq(tmp1, Address(obja, result));
6884   movq(tmp2, Address(objb, result));
6885   xorq(tmp1, tmp2);
6886   testq(tmp1, tmp1);
6887   jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
6888   addq(result, 8);
6889   subq(length, 8);
6890   jcc(Assembler::equal, SAME_TILL_END);
6891   //falling through if less than 8 bytes left
6892 
6893   bind(VECTOR4_TAIL);
6894   cmpq(length, 4);
6895   jccb(Assembler::less, BYTES_TAIL);
6896   bind(VECTOR4_LOOP);
6897   movl(tmp1, Address(obja, result));
6898   xorl(tmp1, Address(objb, result));
6899   testl(tmp1, tmp1);
6900   jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
6901   addq(result, 4);
6902   subq(length, 4);
6903   jcc(Assembler::equal, SAME_TILL_END);
6904   //falling through if less than 4 bytes left
6905 
6906   bind(BYTES_TAIL);
6907   bind(BYTES_LOOP);
6908   load_unsigned_byte(tmp1, Address(obja, result));
6909   load_unsigned_byte(tmp2, Address(objb, result));
6910   xorl(tmp1, tmp2);
6911   testl(tmp1, tmp1);
6912   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6913   decq(length);
6914   jcc(Assembler::zero, SAME_TILL_END);
6915   incq(result);
6916   load_unsigned_byte(tmp1, Address(obja, result));
6917   load_unsigned_byte(tmp2, Address(objb, result));
6918   xorl(tmp1, tmp2);
6919   testl(tmp1, tmp1);
6920   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6921   decq(length);
6922   jcc(Assembler::zero, SAME_TILL_END);
6923   incq(result);
6924   load_unsigned_byte(tmp1, Address(obja, result));
6925   load_unsigned_byte(tmp2, Address(objb, result));
6926   xorl(tmp1, tmp2);
6927   testl(tmp1, tmp1);
6928   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6929   jmp(SAME_TILL_END);
6930 
6931   if (UseAVX >= 2) {
6932     bind(VECTOR32_NOT_EQUAL);
6933     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
6934     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
6935     vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
6936     vpmovmskb(tmp1, rymm0);
6937     bsfq(tmp1, tmp1);
6938     addq(result, tmp1);
6939     shrq(result);
6940     jmp(DONE);
6941   }
6942 
6943   bind(VECTOR16_NOT_EQUAL);
6944   if (UseAVX >= 2) {
6945     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
6946     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
6947     pxor(rymm0, rymm2);
6948   } else {
6949     pcmpeqb(rymm2, rymm2);
6950     pxor(rymm0, rymm1);
6951     pcmpeqb(rymm0, rymm1);
6952     pxor(rymm0, rymm2);
6953   }
6954   pmovmskb(tmp1, rymm0);
6955   bsfq(tmp1, tmp1);
6956   addq(result, tmp1);
6957   shrq(result);
6958   jmpb(DONE);
6959 
6960   bind(VECTOR8_NOT_EQUAL);
6961   bind(VECTOR4_NOT_EQUAL);
6962   bsfq(tmp1, tmp1);
6963   shrq(tmp1, 3);
6964   addq(result, tmp1);
6965   bind(BYTES_NOT_EQUAL);
6966   shrq(result);
6967   jmpb(DONE);
6968 
6969   bind(SAME_TILL_END);
6970   mov64(result, -1);
6971 
6972   bind(DONE);
6973 }
6974 
6975 //Helper functions for square_to_len()
6976 
6977 /**
6978  * Store the squares of x[], right shifted one bit (divided by 2) into z[]
6979  * Preserves x and z and modifies rest of the registers.
6980  */
6981 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6982   // Perform square and right shift by 1
6983   // Handle odd xlen case first, then for even xlen do the following
6984   // jlong carry = 0;
6985   // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
6986   //     huge_128 product = x[j:j+1] * x[j:j+1];
6987   //     z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
6988   //     z[i+2:i+3] = (jlong)(product >>> 1);
6989   //     carry = (jlong)product;
6990   // }
6991 
6992   xorq(tmp5, tmp5);     // carry
6993   xorq(rdxReg, rdxReg);
6994   xorl(tmp1, tmp1);     // index for x
6995   xorl(tmp4, tmp4);     // index for z
6996 
6997   Label L_first_loop, L_first_loop_exit;
6998 
6999   testl(xlen, 1);
7000   jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7001 
7002   // Square and right shift by 1 the odd element using 32 bit multiply
7003   movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7004   imulq(raxReg, raxReg);
7005   shrq(raxReg, 1);
7006   adcq(tmp5, 0);
7007   movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7008   incrementl(tmp1);
7009   addl(tmp4, 2);
7010 
7011   // Square and  right shift by 1 the rest using 64 bit multiply
7012   bind(L_first_loop);
7013   cmpptr(tmp1, xlen);
7014   jccb(Assembler::equal, L_first_loop_exit);
7015 
7016   // Square
7017   movq(raxReg, Address(x, tmp1, Address::times_4,  0));
7018   rorq(raxReg, 32);    // convert big-endian to little-endian
7019   mulq(raxReg);        // 64-bit multiply rax * rax -> rdx:rax
7020 
7021   // Right shift by 1 and save carry
7022   shrq(tmp5, 1);       // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7023   rcrq(rdxReg, 1);
7024   rcrq(raxReg, 1);
7025   adcq(tmp5, 0);
7026 
7027   // Store result in z
7028   movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7029   movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7030 
7031   // Update indices for x and z
7032   addl(tmp1, 2);
7033   addl(tmp4, 4);
7034   jmp(L_first_loop);
7035 
7036   bind(L_first_loop_exit);
7037 }
7038 
7039 
7040 /**
7041  * Perform the following multiply add operation using BMI2 instructions
7042  * carry:sum = sum + op1*op2 + carry
7043  * op2 should be in rdx
7044  * op2 is preserved, all other registers are modified
7045  */
7046 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7047   // assert op2 is rdx
7048   mulxq(tmp2, op1, op1);  //  op1 * op2 -> tmp2:op1
7049   addq(sum, carry);
7050   adcq(tmp2, 0);
7051   addq(sum, op1);
7052   adcq(tmp2, 0);
7053   movq(carry, tmp2);
7054 }
7055 
7056 /**
7057  * Perform the following multiply add operation:
7058  * carry:sum = sum + op1*op2 + carry
7059  * Preserves op1, op2 and modifies rest of registers
7060  */
7061 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7062   // rdx:rax = op1 * op2
7063   movq(raxReg, op2);
7064   mulq(op1);
7065 
7066   //  rdx:rax = sum + carry + rdx:rax
7067   addq(sum, carry);
7068   adcq(rdxReg, 0);
7069   addq(sum, raxReg);
7070   adcq(rdxReg, 0);
7071 
7072   // carry:sum = rdx:sum
7073   movq(carry, rdxReg);
7074 }
7075 
7076 /**
7077  * Add 64 bit long carry into z[] with carry propogation.
7078  * Preserves z and carry register values and modifies rest of registers.
7079  *
7080  */
7081 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7082   Label L_fourth_loop, L_fourth_loop_exit;
7083 
7084   movl(tmp1, 1);
7085   subl(zlen, 2);
7086   addq(Address(z, zlen, Address::times_4, 0), carry);
7087 
7088   bind(L_fourth_loop);
7089   jccb(Assembler::carryClear, L_fourth_loop_exit);
7090   subl(zlen, 2);
7091   jccb(Assembler::negative, L_fourth_loop_exit);
7092   addq(Address(z, zlen, Address::times_4, 0), tmp1);
7093   jmp(L_fourth_loop);
7094   bind(L_fourth_loop_exit);
7095 }
7096 
7097 /**
7098  * Shift z[] left by 1 bit.
7099  * Preserves x, len, z and zlen registers and modifies rest of the registers.
7100  *
7101  */
7102 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7103 
7104   Label L_fifth_loop, L_fifth_loop_exit;
7105 
7106   // Fifth loop
7107   // Perform primitiveLeftShift(z, zlen, 1)
7108 
7109   const Register prev_carry = tmp1;
7110   const Register new_carry = tmp4;
7111   const Register value = tmp2;
7112   const Register zidx = tmp3;
7113 
7114   // int zidx, carry;
7115   // long value;
7116   // carry = 0;
7117   // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7118   //    (carry:value)  = (z[i] << 1) | carry ;
7119   //    z[i] = value;
7120   // }
7121 
7122   movl(zidx, zlen);
7123   xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7124 
7125   bind(L_fifth_loop);
7126   decl(zidx);  // Use decl to preserve carry flag
7127   decl(zidx);
7128   jccb(Assembler::negative, L_fifth_loop_exit);
7129 
7130   if (UseBMI2Instructions) {
7131      movq(value, Address(z, zidx, Address::times_4, 0));
7132      rclq(value, 1);
7133      rorxq(value, value, 32);
7134      movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
7135   }
7136   else {
7137     // clear new_carry
7138     xorl(new_carry, new_carry);
7139 
7140     // Shift z[i] by 1, or in previous carry and save new carry
7141     movq(value, Address(z, zidx, Address::times_4, 0));
7142     shlq(value, 1);
7143     adcl(new_carry, 0);
7144 
7145     orq(value, prev_carry);
7146     rorq(value, 0x20);
7147     movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
7148 
7149     // Set previous carry = new carry
7150     movl(prev_carry, new_carry);
7151   }
7152   jmp(L_fifth_loop);
7153 
7154   bind(L_fifth_loop_exit);
7155 }
7156 
7157 
7158 /**
7159  * Code for BigInteger::squareToLen() intrinsic
7160  *
7161  * rdi: x
7162  * rsi: len
7163  * r8:  z
7164  * rcx: zlen
7165  * r12: tmp1
7166  * r13: tmp2
7167  * r14: tmp3
7168  * r15: tmp4
7169  * rbx: tmp5
7170  *
7171  */
7172 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7173 
7174   Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7175   push(tmp1);
7176   push(tmp2);
7177   push(tmp3);
7178   push(tmp4);
7179   push(tmp5);
7180 
7181   // First loop
7182   // Store the squares, right shifted one bit (i.e., divided by 2).
7183   square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7184 
7185   // Add in off-diagonal sums.
7186   //
7187   // Second, third (nested) and fourth loops.
7188   // zlen +=2;
7189   // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7190   //    carry = 0;
7191   //    long op2 = x[xidx:xidx+1];
7192   //    for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7193   //       k -= 2;
7194   //       long op1 = x[j:j+1];
7195   //       long sum = z[k:k+1];
7196   //       carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7197   //       z[k:k+1] = sum;
7198   //    }
7199   //    add_one_64(z, k, carry, tmp_regs);
7200   // }
7201 
7202   const Register carry = tmp5;
7203   const Register sum = tmp3;
7204   const Register op1 = tmp4;
7205   Register op2 = tmp2;
7206 
7207   push(zlen);
7208   push(len);
7209   addl(zlen,2);
7210   bind(L_second_loop);
7211   xorq(carry, carry);
7212   subl(zlen, 4);
7213   subl(len, 2);
7214   push(zlen);
7215   push(len);
7216   cmpl(len, 0);
7217   jccb(Assembler::lessEqual, L_second_loop_exit);
7218 
7219   // Multiply an array by one 64 bit long.
7220   if (UseBMI2Instructions) {
7221     op2 = rdxReg;
7222     movq(op2, Address(x, len, Address::times_4,  0));
7223     rorxq(op2, op2, 32);
7224   }
7225   else {
7226     movq(op2, Address(x, len, Address::times_4,  0));
7227     rorq(op2, 32);
7228   }
7229 
7230   bind(L_third_loop);
7231   decrementl(len);
7232   jccb(Assembler::negative, L_third_loop_exit);
7233   decrementl(len);
7234   jccb(Assembler::negative, L_last_x);
7235 
7236   movq(op1, Address(x, len, Address::times_4,  0));
7237   rorq(op1, 32);
7238 
7239   bind(L_multiply);
7240   subl(zlen, 2);
7241   movq(sum, Address(z, zlen, Address::times_4,  0));
7242 
7243   // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
7244   if (UseBMI2Instructions) {
7245     multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
7246   }
7247   else {
7248     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7249   }
7250 
7251   movq(Address(z, zlen, Address::times_4, 0), sum);
7252 
7253   jmp(L_third_loop);
7254   bind(L_third_loop_exit);
7255 
7256   // Fourth loop
7257   // Add 64 bit long carry into z with carry propogation.
7258   // Uses offsetted zlen.
7259   add_one_64(z, zlen, carry, tmp1);
7260 
7261   pop(len);
7262   pop(zlen);
7263   jmp(L_second_loop);
7264 
7265   // Next infrequent code is moved outside loops.
7266   bind(L_last_x);
7267   movl(op1, Address(x, 0));
7268   jmp(L_multiply);
7269 
7270   bind(L_second_loop_exit);
7271   pop(len);
7272   pop(zlen);
7273   pop(len);
7274   pop(zlen);
7275 
7276   // Fifth loop
7277   // Shift z left 1 bit.
7278   lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
7279 
7280   // z[zlen-1] |= x[len-1] & 1;
7281   movl(tmp3, Address(x, len, Address::times_4, -4));
7282   andl(tmp3, 1);
7283   orl(Address(z, zlen, Address::times_4,  -4), tmp3);
7284 
7285   pop(tmp5);
7286   pop(tmp4);
7287   pop(tmp3);
7288   pop(tmp2);
7289   pop(tmp1);
7290 }
7291 
7292 /**
7293  * Helper function for mul_add()
7294  * Multiply the in[] by int k and add to out[] starting at offset offs using
7295  * 128 bit by 32 bit multiply and return the carry in tmp5.
7296  * Only quad int aligned length of in[] is operated on in this function.
7297  * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
7298  * This function preserves out, in and k registers.
7299  * len and offset point to the appropriate index in "in" & "out" correspondingly
7300  * tmp5 has the carry.
7301  * other registers are temporary and are modified.
7302  *
7303  */
7304 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
7305   Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
7306   Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7307 
7308   Label L_first_loop, L_first_loop_exit;
7309 
7310   movl(tmp1, len);
7311   shrl(tmp1, 2);
7312 
7313   bind(L_first_loop);
7314   subl(tmp1, 1);
7315   jccb(Assembler::negative, L_first_loop_exit);
7316 
7317   subl(len, 4);
7318   subl(offset, 4);
7319 
7320   Register op2 = tmp2;
7321   const Register sum = tmp3;
7322   const Register op1 = tmp4;
7323   const Register carry = tmp5;
7324 
7325   if (UseBMI2Instructions) {
7326     op2 = rdxReg;
7327   }
7328 
7329   movq(op1, Address(in, len, Address::times_4,  8));
7330   rorq(op1, 32);
7331   movq(sum, Address(out, offset, Address::times_4,  8));
7332   rorq(sum, 32);
7333   if (UseBMI2Instructions) {
7334     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7335   }
7336   else {
7337     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7338   }
7339   // Store back in big endian from little endian
7340   rorq(sum, 0x20);
7341   movq(Address(out, offset, Address::times_4,  8), sum);
7342 
7343   movq(op1, Address(in, len, Address::times_4,  0));
7344   rorq(op1, 32);
7345   movq(sum, Address(out, offset, Address::times_4,  0));
7346   rorq(sum, 32);
7347   if (UseBMI2Instructions) {
7348     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7349   }
7350   else {
7351     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7352   }
7353   // Store back in big endian from little endian
7354   rorq(sum, 0x20);
7355   movq(Address(out, offset, Address::times_4,  0), sum);
7356 
7357   jmp(L_first_loop);
7358   bind(L_first_loop_exit);
7359 }
7360 
7361 /**
7362  * Code for BigInteger::mulAdd() intrinsic
7363  *
7364  * rdi: out
7365  * rsi: in
7366  * r11: offs (out.length - offset)
7367  * rcx: len
7368  * r8:  k
7369  * r12: tmp1
7370  * r13: tmp2
7371  * r14: tmp3
7372  * r15: tmp4
7373  * rbx: tmp5
7374  * Multiply the in[] by word k and add to out[], return the carry in rax
7375  */
7376 void MacroAssembler::mul_add(Register out, Register in, Register offs,
7377    Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
7378    Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7379 
7380   Label L_carry, L_last_in, L_done;
7381 
7382 // carry = 0;
7383 // for (int j=len-1; j >= 0; j--) {
7384 //    long product = (in[j] & LONG_MASK) * kLong +
7385 //                   (out[offs] & LONG_MASK) + carry;
7386 //    out[offs--] = (int)product;
7387 //    carry = product >>> 32;
7388 // }
7389 //
7390   push(tmp1);
7391   push(tmp2);
7392   push(tmp3);
7393   push(tmp4);
7394   push(tmp5);
7395 
7396   Register op2 = tmp2;
7397   const Register sum = tmp3;
7398   const Register op1 = tmp4;
7399   const Register carry =  tmp5;
7400 
7401   if (UseBMI2Instructions) {
7402     op2 = rdxReg;
7403     movl(op2, k);
7404   }
7405   else {
7406     movl(op2, k);
7407   }
7408 
7409   xorq(carry, carry);
7410 
7411   //First loop
7412 
7413   //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
7414   //The carry is in tmp5
7415   mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
7416 
7417   //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
7418   decrementl(len);
7419   jccb(Assembler::negative, L_carry);
7420   decrementl(len);
7421   jccb(Assembler::negative, L_last_in);
7422 
7423   movq(op1, Address(in, len, Address::times_4,  0));
7424   rorq(op1, 32);
7425 
7426   subl(offs, 2);
7427   movq(sum, Address(out, offs, Address::times_4,  0));
7428   rorq(sum, 32);
7429 
7430   if (UseBMI2Instructions) {
7431     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7432   }
7433   else {
7434     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7435   }
7436 
7437   // Store back in big endian from little endian
7438   rorq(sum, 0x20);
7439   movq(Address(out, offs, Address::times_4,  0), sum);
7440 
7441   testl(len, len);
7442   jccb(Assembler::zero, L_carry);
7443 
7444   //Multiply the last in[] entry, if any
7445   bind(L_last_in);
7446   movl(op1, Address(in, 0));
7447   movl(sum, Address(out, offs, Address::times_4,  -4));
7448 
7449   movl(raxReg, k);
7450   mull(op1); //tmp4 * eax -> edx:eax
7451   addl(sum, carry);
7452   adcl(rdxReg, 0);
7453   addl(sum, raxReg);
7454   adcl(rdxReg, 0);
7455   movl(carry, rdxReg);
7456 
7457   movl(Address(out, offs, Address::times_4,  -4), sum);
7458 
7459   bind(L_carry);
7460   //return tmp5/carry as carry in rax
7461   movl(rax, carry);
7462 
7463   bind(L_done);
7464   pop(tmp5);
7465   pop(tmp4);
7466   pop(tmp3);
7467   pop(tmp2);
7468   pop(tmp1);
7469 }
7470 #endif
7471 
7472 /**
7473  * Emits code to update CRC-32 with a byte value according to constants in table
7474  *
7475  * @param [in,out]crc   Register containing the crc.
7476  * @param [in]val       Register containing the byte to fold into the CRC.
7477  * @param [in]table     Register containing the table of crc constants.
7478  *
7479  * uint32_t crc;
7480  * val = crc_table[(val ^ crc) & 0xFF];
7481  * crc = val ^ (crc >> 8);
7482  *
7483  */
7484 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7485   xorl(val, crc);
7486   andl(val, 0xFF);
7487   shrl(crc, 8); // unsigned shift
7488   xorl(crc, Address(table, val, Address::times_4, 0));
7489 }
7490 
7491 /**
7492  * Fold 128-bit data chunk
7493  */
7494 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7495   if (UseAVX > 0) {
7496     vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7497     vpclmulldq(xcrc, xK, xcrc); // [63:0]
7498     vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
7499     pxor(xcrc, xtmp);
7500   } else {
7501     movdqa(xtmp, xcrc);
7502     pclmulhdq(xtmp, xK);   // [123:64]
7503     pclmulldq(xcrc, xK);   // [63:0]
7504     pxor(xcrc, xtmp);
7505     movdqu(xtmp, Address(buf, offset));
7506     pxor(xcrc, xtmp);
7507   }
7508 }
7509 
7510 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7511   if (UseAVX > 0) {
7512     vpclmulhdq(xtmp, xK, xcrc);
7513     vpclmulldq(xcrc, xK, xcrc);
7514     pxor(xcrc, xbuf);
7515     pxor(xcrc, xtmp);
7516   } else {
7517     movdqa(xtmp, xcrc);
7518     pclmulhdq(xtmp, xK);
7519     pclmulldq(xcrc, xK);
7520     pxor(xcrc, xbuf);
7521     pxor(xcrc, xtmp);
7522   }
7523 }
7524 
7525 /**
7526  * 8-bit folds to compute 32-bit CRC
7527  *
7528  * uint64_t xcrc;
7529  * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7530  */
7531 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7532   movdl(tmp, xcrc);
7533   andl(tmp, 0xFF);
7534   movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7535   psrldq(xcrc, 1); // unsigned shift one byte
7536   pxor(xcrc, xtmp);
7537 }
7538 
7539 /**
7540  * uint32_t crc;
7541  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7542  */
7543 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7544   movl(tmp, crc);
7545   andl(tmp, 0xFF);
7546   shrl(crc, 8);
7547   xorl(crc, Address(table, tmp, Address::times_4, 0));
7548 }
7549 
7550 /**
7551  * @param crc   register containing existing CRC (32-bit)
7552  * @param buf   register pointing to input byte buffer (byte*)
7553  * @param len   register containing number of bytes
7554  * @param table register that will contain address of CRC table
7555  * @param tmp   scratch register
7556  */
7557 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7558   assert_different_registers(crc, buf, len, table, tmp, rax);
7559 
7560   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7561   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7562 
7563   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7564   // context for the registers used, where all instructions below are using 128-bit mode
7565   // On EVEX without VL and BW, these instructions will all be AVX.
7566   lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7567   notl(crc); // ~crc
7568   cmpl(len, 16);
7569   jcc(Assembler::less, L_tail);
7570 
7571   // Align buffer to 16 bytes
7572   movl(tmp, buf);
7573   andl(tmp, 0xF);
7574   jccb(Assembler::zero, L_aligned);
7575   subl(tmp,  16);
7576   addl(len, tmp);
7577 
7578   align(4);
7579   BIND(L_align_loop);
7580   movsbl(rax, Address(buf, 0)); // load byte with sign extension
7581   update_byte_crc32(crc, rax, table);
7582   increment(buf);
7583   incrementl(tmp);
7584   jccb(Assembler::less, L_align_loop);
7585 
7586   BIND(L_aligned);
7587   movl(tmp, len); // save
7588   shrl(len, 4);
7589   jcc(Assembler::zero, L_tail_restore);
7590 
7591   // Fold crc into first bytes of vector
7592   movdqa(xmm1, Address(buf, 0));
7593   movdl(rax, xmm1);
7594   xorl(crc, rax);
7595   if (VM_Version::supports_sse4_1()) {
7596     pinsrd(xmm1, crc, 0);
7597   } else {
7598     pinsrw(xmm1, crc, 0);
7599     shrl(crc, 16);
7600     pinsrw(xmm1, crc, 1);
7601   }
7602   addptr(buf, 16);
7603   subl(len, 4); // len > 0
7604   jcc(Assembler::less, L_fold_tail);
7605 
7606   movdqa(xmm2, Address(buf,  0));
7607   movdqa(xmm3, Address(buf, 16));
7608   movdqa(xmm4, Address(buf, 32));
7609   addptr(buf, 48);
7610   subl(len, 3);
7611   jcc(Assembler::lessEqual, L_fold_512b);
7612 
7613   // Fold total 512 bits of polynomial on each iteration,
7614   // 128 bits per each of 4 parallel streams.
7615   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
7616 
7617   align32();
7618   BIND(L_fold_512b_loop);
7619   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
7620   fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7621   fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7622   fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7623   addptr(buf, 64);
7624   subl(len, 4);
7625   jcc(Assembler::greater, L_fold_512b_loop);
7626 
7627   // Fold 512 bits to 128 bits.
7628   BIND(L_fold_512b);
7629   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7630   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7631   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7632   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7633 
7634   // Fold the rest of 128 bits data chunks
7635   BIND(L_fold_tail);
7636   addl(len, 3);
7637   jccb(Assembler::lessEqual, L_fold_128b);
7638   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7639 
7640   BIND(L_fold_tail_loop);
7641   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
7642   addptr(buf, 16);
7643   decrementl(len);
7644   jccb(Assembler::greater, L_fold_tail_loop);
7645 
7646   // Fold 128 bits in xmm1 down into 32 bits in crc register.
7647   BIND(L_fold_128b);
7648   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
7649   if (UseAVX > 0) {
7650     vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7651     vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
7652     vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7653   } else {
7654     movdqa(xmm2, xmm0);
7655     pclmulqdq(xmm2, xmm1, 0x1);
7656     movdqa(xmm3, xmm0);
7657     pand(xmm3, xmm2);
7658     pclmulqdq(xmm0, xmm3, 0x1);
7659   }
7660   psrldq(xmm1, 8);
7661   psrldq(xmm2, 4);
7662   pxor(xmm0, xmm1);
7663   pxor(xmm0, xmm2);
7664 
7665   // 8 8-bit folds to compute 32-bit CRC.
7666   for (int j = 0; j < 4; j++) {
7667     fold_8bit_crc32(xmm0, table, xmm1, rax);
7668   }
7669   movdl(crc, xmm0); // mov 32 bits to general register
7670   for (int j = 0; j < 4; j++) {
7671     fold_8bit_crc32(crc, table, rax);
7672   }
7673 
7674   BIND(L_tail_restore);
7675   movl(len, tmp); // restore
7676   BIND(L_tail);
7677   andl(len, 0xf);
7678   jccb(Assembler::zero, L_exit);
7679 
7680   // Fold the rest of bytes
7681   align(4);
7682   BIND(L_tail_loop);
7683   movsbl(rax, Address(buf, 0)); // load byte with sign extension
7684   update_byte_crc32(crc, rax, table);
7685   increment(buf);
7686   decrementl(len);
7687   jccb(Assembler::greater, L_tail_loop);
7688 
7689   BIND(L_exit);
7690   notl(crc); // ~c
7691 }
7692 
7693 #ifdef _LP64
7694 // Helper function for AVX 512 CRC32
7695 // Fold 512-bit data chunks
7696 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
7697                                              Register pos, int offset) {
7698   evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
7699   evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
7700   evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
7701   evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
7702   evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
7703 }
7704 
7705 // Helper function for AVX 512 CRC32
7706 // Compute CRC32 for < 256B buffers
7707 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
7708                                               Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
7709                                               Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
7710 
7711   Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
7712   Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
7713   Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
7714 
7715   // check if there is enough buffer to be able to fold 16B at a time
7716   cmpl(len, 32);
7717   jcc(Assembler::less, L_less_than_32);
7718 
7719   // if there is, load the constants
7720   movdqu(xmm10, Address(key, 1 * 16));    //rk1 and rk2 in xmm10
7721   movdl(xmm0, crc);                        // get the initial crc value
7722   movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7723   pxor(xmm7, xmm0);
7724 
7725   // update the buffer pointer
7726   addl(pos, 16);
7727   //update the counter.subtract 32 instead of 16 to save one instruction from the loop
7728   subl(len, 32);
7729   jmp(L_16B_reduction_loop);
7730 
7731   bind(L_less_than_32);
7732   //mov initial crc to the return value. this is necessary for zero - length buffers.
7733   movl(rax, crc);
7734   testl(len, len);
7735   jcc(Assembler::equal, L_cleanup);
7736 
7737   movdl(xmm0, crc);                        //get the initial crc value
7738 
7739   cmpl(len, 16);
7740   jcc(Assembler::equal, L_exact_16_left);
7741   jcc(Assembler::less, L_less_than_16_left);
7742 
7743   movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7744   pxor(xmm7, xmm0);                       //xor the initial crc value
7745   addl(pos, 16);
7746   subl(len, 16);
7747   movdqu(xmm10, Address(key, 1 * 16));    // rk1 and rk2 in xmm10
7748   jmp(L_get_last_two_xmms);
7749 
7750   bind(L_less_than_16_left);
7751   //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
7752   pxor(xmm1, xmm1);
7753   movptr(tmp1, rsp);
7754   movdqu(Address(tmp1, 0 * 16), xmm1);
7755 
7756   cmpl(len, 4);
7757   jcc(Assembler::less, L_only_less_than_4);
7758 
7759   //backup the counter value
7760   movl(tmp2, len);
7761   cmpl(len, 8);
7762   jcc(Assembler::less, L_less_than_8_left);
7763 
7764   //load 8 Bytes
7765   movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
7766   movq(Address(tmp1, 0 * 16), rax);
7767   addptr(tmp1, 8);
7768   subl(len, 8);
7769   addl(pos, 8);
7770 
7771   bind(L_less_than_8_left);
7772   cmpl(len, 4);
7773   jcc(Assembler::less, L_less_than_4_left);
7774 
7775   //load 4 Bytes
7776   movl(rax, Address(buf, pos, Address::times_1, 0));
7777   movl(Address(tmp1, 0 * 16), rax);
7778   addptr(tmp1, 4);
7779   subl(len, 4);
7780   addl(pos, 4);
7781 
7782   bind(L_less_than_4_left);
7783   cmpl(len, 2);
7784   jcc(Assembler::less, L_less_than_2_left);
7785 
7786   // load 2 Bytes
7787   movw(rax, Address(buf, pos, Address::times_1, 0));
7788   movl(Address(tmp1, 0 * 16), rax);
7789   addptr(tmp1, 2);
7790   subl(len, 2);
7791   addl(pos, 2);
7792 
7793   bind(L_less_than_2_left);
7794   cmpl(len, 1);
7795   jcc(Assembler::less, L_zero_left);
7796 
7797   // load 1 Byte
7798   movb(rax, Address(buf, pos, Address::times_1, 0));
7799   movb(Address(tmp1, 0 * 16), rax);
7800 
7801   bind(L_zero_left);
7802   movdqu(xmm7, Address(rsp, 0));
7803   pxor(xmm7, xmm0);                       //xor the initial crc value
7804 
7805   lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7806   movdqu(xmm0, Address(rax, tmp2));
7807   pshufb(xmm7, xmm0);
7808   jmp(L_128_done);
7809 
7810   bind(L_exact_16_left);
7811   movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
7812   pxor(xmm7, xmm0);                       //xor the initial crc value
7813   jmp(L_128_done);
7814 
7815   bind(L_only_less_than_4);
7816   cmpl(len, 3);
7817   jcc(Assembler::less, L_only_less_than_3);
7818 
7819   // load 3 Bytes
7820   movb(rax, Address(buf, pos, Address::times_1, 0));
7821   movb(Address(tmp1, 0), rax);
7822 
7823   movb(rax, Address(buf, pos, Address::times_1, 1));
7824   movb(Address(tmp1, 1), rax);
7825 
7826   movb(rax, Address(buf, pos, Address::times_1, 2));
7827   movb(Address(tmp1, 2), rax);
7828 
7829   movdqu(xmm7, Address(rsp, 0));
7830   pxor(xmm7, xmm0);                     //xor the initial crc value
7831 
7832   pslldq(xmm7, 0x5);
7833   jmp(L_barrett);
7834   bind(L_only_less_than_3);
7835   cmpl(len, 2);
7836   jcc(Assembler::less, L_only_less_than_2);
7837 
7838   // load 2 Bytes
7839   movb(rax, Address(buf, pos, Address::times_1, 0));
7840   movb(Address(tmp1, 0), rax);
7841 
7842   movb(rax, Address(buf, pos, Address::times_1, 1));
7843   movb(Address(tmp1, 1), rax);
7844 
7845   movdqu(xmm7, Address(rsp, 0));
7846   pxor(xmm7, xmm0);                     //xor the initial crc value
7847 
7848   pslldq(xmm7, 0x6);
7849   jmp(L_barrett);
7850 
7851   bind(L_only_less_than_2);
7852   //load 1 Byte
7853   movb(rax, Address(buf, pos, Address::times_1, 0));
7854   movb(Address(tmp1, 0), rax);
7855 
7856   movdqu(xmm7, Address(rsp, 0));
7857   pxor(xmm7, xmm0);                     //xor the initial crc value
7858 
7859   pslldq(xmm7, 0x7);
7860 }
7861 
7862 /**
7863 * Compute CRC32 using AVX512 instructions
7864 * param crc   register containing existing CRC (32-bit)
7865 * param buf   register pointing to input byte buffer (byte*)
7866 * param len   register containing number of bytes
7867 * param tmp1  scratch register
7868 * param tmp2  scratch register
7869 * return rax  result register
7870 */
7871 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register key, Register tmp1, Register tmp2) {
7872   assert_different_registers(crc, buf, len, key, tmp1, tmp2, rax);
7873 
7874   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7875   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7876   Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
7877   Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
7878   Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
7879 
7880   const Register pos = r12;
7881   push(r12);
7882   subptr(rsp, 16 * 2 + 8);
7883 
7884   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7885   // context for the registers used, where all instructions below are using 128-bit mode
7886   // On EVEX without VL and BW, these instructions will all be AVX.
7887   lea(key, ExternalAddress(StubRoutines::x86::crc_table_avx512_addr()));
7888   notl(crc);
7889   movl(pos, 0);
7890 
7891   // check if smaller than 256B
7892   cmpl(len, 256);
7893   jcc(Assembler::less, L_less_than_256);
7894 
7895   // load the initial crc value
7896   movdl(xmm10, crc);
7897 
7898   // receive the initial 64B data, xor the initial crc value
7899   evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
7900   evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
7901   evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
7902   evbroadcasti32x4(xmm10, Address(key, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
7903 
7904   subl(len, 256);
7905   cmpl(len, 256);
7906   jcc(Assembler::less, L_fold_128_B_loop);
7907 
7908   evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
7909   evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
7910   evbroadcasti32x4(xmm16, Address(key, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
7911   subl(len, 256);
7912 
7913   bind(L_fold_256_B_loop);
7914   addl(pos, 256);
7915   fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
7916   fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
7917   fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
7918   fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
7919 
7920   subl(len, 256);
7921   jcc(Assembler::greaterEqual, L_fold_256_B_loop);
7922 
7923   // Fold 256 into 128
7924   addl(pos, 256);
7925   evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
7926   evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
7927   vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
7928 
7929   evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
7930   evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
7931   vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
7932 
7933   evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
7934   evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
7935 
7936   addl(len, 128);
7937   jmp(L_fold_128_B_register);
7938 
7939   // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
7940   // loop will fold 128B at a time until we have 128 + y Bytes of buffer
7941 
7942   // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
7943   bind(L_fold_128_B_loop);
7944   addl(pos, 128);
7945   fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
7946   fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
7947 
7948   subl(len, 128);
7949   jcc(Assembler::greaterEqual, L_fold_128_B_loop);
7950 
7951   addl(pos, 128);
7952 
7953   // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
7954   // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
7955   bind(L_fold_128_B_register);
7956   evmovdquq(xmm16, Address(key, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
7957   evmovdquq(xmm11, Address(key, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
7958   evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
7959   evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
7960   // save last that has no multiplicand
7961   vextracti64x2(xmm7, xmm4, 3);
7962 
7963   evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
7964   evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
7965   // Needed later in reduction loop
7966   movdqu(xmm10, Address(key, 1 * 16));
7967   vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
7968   vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
7969 
7970   // Swap 1,0,3,2 - 01 00 11 10
7971   evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
7972   evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
7973   vextracti128(xmm5, xmm8, 1);
7974   evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
7975 
7976   // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
7977   // instead of a cmp instruction, we use the negative flag with the jl instruction
7978   addl(len, 128 - 16);
7979   jcc(Assembler::less, L_final_reduction_for_128);
7980 
7981   bind(L_16B_reduction_loop);
7982   vpclmulqdq(xmm8, xmm7, xmm10, 0x1);
7983   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7984   vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
7985   movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
7986   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7987   addl(pos, 16);
7988   subl(len, 16);
7989   jcc(Assembler::greaterEqual, L_16B_reduction_loop);
7990 
7991   bind(L_final_reduction_for_128);
7992   addl(len, 16);
7993   jcc(Assembler::equal, L_128_done);
7994 
7995   bind(L_get_last_two_xmms);
7996   movdqu(xmm2, xmm7);
7997   addl(pos, len);
7998   movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
7999   subl(pos, len);
8000 
8001   // get rid of the extra data that was loaded before
8002   // load the shift constant
8003   lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8004   movdqu(xmm0, Address(rax, len));
8005   addl(rax, len);
8006 
8007   vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8008   //Change mask to 512
8009   vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8010   vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8011 
8012   blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8013   vpclmulqdq(xmm8, xmm7, xmm10, 0x1);
8014   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8015   vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8016   vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8017 
8018   bind(L_128_done);
8019   // compute crc of a 128-bit value
8020   movdqu(xmm10, Address(key, 3 * 16));
8021   movdqu(xmm0, xmm7);
8022 
8023   // 64b fold
8024   vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8025   vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8026   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8027 
8028   // 32b fold
8029   movdqu(xmm0, xmm7);
8030   vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8031   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8032   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8033   jmp(L_barrett);
8034 
8035   bind(L_less_than_256);
8036   kernel_crc32_avx512_256B(crc, buf, len, key, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8037 
8038   //barrett reduction
8039   bind(L_barrett);
8040   vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8041   movdqu(xmm1, xmm7);
8042   movdqu(xmm2, xmm7);
8043   movdqu(xmm10, Address(key, 4 * 16));
8044 
8045   pclmulqdq(xmm7, xmm10, 0x0);
8046   pxor(xmm7, xmm2);
8047   vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8048   movdqu(xmm2, xmm7);
8049   pclmulqdq(xmm7, xmm10, 0x10);
8050   pxor(xmm7, xmm2);
8051   pxor(xmm7, xmm1);
8052   pextrd(crc, xmm7, 2);
8053 
8054   bind(L_cleanup);
8055   notl(crc); // ~c
8056   addptr(rsp, 16 * 2 + 8);
8057   pop(r12);
8058 }
8059 
8060 // S. Gueron / Information Processing Letters 112 (2012) 184
8061 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8062 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8063 // Output: the 64-bit carry-less product of B * CONST
8064 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8065                                      Register tmp1, Register tmp2, Register tmp3) {
8066   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8067   if (n > 0) {
8068     addq(tmp3, n * 256 * 8);
8069   }
8070   //    Q1 = TABLEExt[n][B & 0xFF];
8071   movl(tmp1, in);
8072   andl(tmp1, 0x000000FF);
8073   shll(tmp1, 3);
8074   addq(tmp1, tmp3);
8075   movq(tmp1, Address(tmp1, 0));
8076 
8077   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
8078   movl(tmp2, in);
8079   shrl(tmp2, 8);
8080   andl(tmp2, 0x000000FF);
8081   shll(tmp2, 3);
8082   addq(tmp2, tmp3);
8083   movq(tmp2, Address(tmp2, 0));
8084 
8085   shlq(tmp2, 8);
8086   xorq(tmp1, tmp2);
8087 
8088   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
8089   movl(tmp2, in);
8090   shrl(tmp2, 16);
8091   andl(tmp2, 0x000000FF);
8092   shll(tmp2, 3);
8093   addq(tmp2, tmp3);
8094   movq(tmp2, Address(tmp2, 0));
8095 
8096   shlq(tmp2, 16);
8097   xorq(tmp1, tmp2);
8098 
8099   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
8100   shrl(in, 24);
8101   andl(in, 0x000000FF);
8102   shll(in, 3);
8103   addq(in, tmp3);
8104   movq(in, Address(in, 0));
8105 
8106   shlq(in, 24);
8107   xorq(in, tmp1);
8108   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8109 }
8110 
8111 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8112                                       Register in_out,
8113                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8114                                       XMMRegister w_xtmp2,
8115                                       Register tmp1,
8116                                       Register n_tmp2, Register n_tmp3) {
8117   if (is_pclmulqdq_supported) {
8118     movdl(w_xtmp1, in_out); // modified blindly
8119 
8120     movl(tmp1, const_or_pre_comp_const_index);
8121     movdl(w_xtmp2, tmp1);
8122     pclmulqdq(w_xtmp1, w_xtmp2, 0);
8123 
8124     movdq(in_out, w_xtmp1);
8125   } else {
8126     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8127   }
8128 }
8129 
8130 // Recombination Alternative 2: No bit-reflections
8131 // T1 = (CRC_A * U1) << 1
8132 // T2 = (CRC_B * U2) << 1
8133 // C1 = T1 >> 32
8134 // C2 = T2 >> 32
8135 // T1 = T1 & 0xFFFFFFFF
8136 // T2 = T2 & 0xFFFFFFFF
8137 // T1 = CRC32(0, T1)
8138 // T2 = CRC32(0, T2)
8139 // C1 = C1 ^ T1
8140 // C2 = C2 ^ T2
8141 // CRC = C1 ^ C2 ^ CRC_C
8142 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8143                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8144                                      Register tmp1, Register tmp2,
8145                                      Register n_tmp3) {
8146   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8147   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8148   shlq(in_out, 1);
8149   movl(tmp1, in_out);
8150   shrq(in_out, 32);
8151   xorl(tmp2, tmp2);
8152   crc32(tmp2, tmp1, 4);
8153   xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8154   shlq(in1, 1);
8155   movl(tmp1, in1);
8156   shrq(in1, 32);
8157   xorl(tmp2, tmp2);
8158   crc32(tmp2, tmp1, 4);
8159   xorl(in1, tmp2);
8160   xorl(in_out, in1);
8161   xorl(in_out, in2);
8162 }
8163 
8164 // Set N to predefined value
8165 // Subtract from a lenght of a buffer
8166 // execute in a loop:
8167 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8168 // for i = 1 to N do
8169 //  CRC_A = CRC32(CRC_A, A[i])
8170 //  CRC_B = CRC32(CRC_B, B[i])
8171 //  CRC_C = CRC32(CRC_C, C[i])
8172 // end for
8173 // Recombine
8174 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8175                                        Register in_out1, Register in_out2, Register in_out3,
8176                                        Register tmp1, Register tmp2, Register tmp3,
8177                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8178                                        Register tmp4, Register tmp5,
8179                                        Register n_tmp6) {
8180   Label L_processPartitions;
8181   Label L_processPartition;
8182   Label L_exit;
8183 
8184   bind(L_processPartitions);
8185   cmpl(in_out1, 3 * size);
8186   jcc(Assembler::less, L_exit);
8187     xorl(tmp1, tmp1);
8188     xorl(tmp2, tmp2);
8189     movq(tmp3, in_out2);
8190     addq(tmp3, size);
8191 
8192     bind(L_processPartition);
8193       crc32(in_out3, Address(in_out2, 0), 8);
8194       crc32(tmp1, Address(in_out2, size), 8);
8195       crc32(tmp2, Address(in_out2, size * 2), 8);
8196       addq(in_out2, 8);
8197       cmpq(in_out2, tmp3);
8198       jcc(Assembler::less, L_processPartition);
8199     crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8200             w_xtmp1, w_xtmp2, w_xtmp3,
8201             tmp4, tmp5,
8202             n_tmp6);
8203     addq(in_out2, 2 * size);
8204     subl(in_out1, 3 * size);
8205     jmp(L_processPartitions);
8206 
8207   bind(L_exit);
8208 }
8209 #else
8210 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
8211                                      Register tmp1, Register tmp2, Register tmp3,
8212                                      XMMRegister xtmp1, XMMRegister xtmp2) {
8213   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8214   if (n > 0) {
8215     addl(tmp3, n * 256 * 8);
8216   }
8217   //    Q1 = TABLEExt[n][B & 0xFF];
8218   movl(tmp1, in_out);
8219   andl(tmp1, 0x000000FF);
8220   shll(tmp1, 3);
8221   addl(tmp1, tmp3);
8222   movq(xtmp1, Address(tmp1, 0));
8223 
8224   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
8225   movl(tmp2, in_out);
8226   shrl(tmp2, 8);
8227   andl(tmp2, 0x000000FF);
8228   shll(tmp2, 3);
8229   addl(tmp2, tmp3);
8230   movq(xtmp2, Address(tmp2, 0));
8231 
8232   psllq(xtmp2, 8);
8233   pxor(xtmp1, xtmp2);
8234 
8235   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
8236   movl(tmp2, in_out);
8237   shrl(tmp2, 16);
8238   andl(tmp2, 0x000000FF);
8239   shll(tmp2, 3);
8240   addl(tmp2, tmp3);
8241   movq(xtmp2, Address(tmp2, 0));
8242 
8243   psllq(xtmp2, 16);
8244   pxor(xtmp1, xtmp2);
8245 
8246   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
8247   shrl(in_out, 24);
8248   andl(in_out, 0x000000FF);
8249   shll(in_out, 3);
8250   addl(in_out, tmp3);
8251   movq(xtmp2, Address(in_out, 0));
8252 
8253   psllq(xtmp2, 24);
8254   pxor(xtmp1, xtmp2); // Result in CXMM
8255   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8256 }
8257 
8258 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8259                                       Register in_out,
8260                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8261                                       XMMRegister w_xtmp2,
8262                                       Register tmp1,
8263                                       Register n_tmp2, Register n_tmp3) {
8264   if (is_pclmulqdq_supported) {
8265     movdl(w_xtmp1, in_out);
8266 
8267     movl(tmp1, const_or_pre_comp_const_index);
8268     movdl(w_xtmp2, tmp1);
8269     pclmulqdq(w_xtmp1, w_xtmp2, 0);
8270     // Keep result in XMM since GPR is 32 bit in length
8271   } else {
8272     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
8273   }
8274 }
8275 
8276 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8277                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8278                                      Register tmp1, Register tmp2,
8279                                      Register n_tmp3) {
8280   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8281   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8282 
8283   psllq(w_xtmp1, 1);
8284   movdl(tmp1, w_xtmp1);
8285   psrlq(w_xtmp1, 32);
8286   movdl(in_out, w_xtmp1);
8287 
8288   xorl(tmp2, tmp2);
8289   crc32(tmp2, tmp1, 4);
8290   xorl(in_out, tmp2);
8291 
8292   psllq(w_xtmp2, 1);
8293   movdl(tmp1, w_xtmp2);
8294   psrlq(w_xtmp2, 32);
8295   movdl(in1, w_xtmp2);
8296 
8297   xorl(tmp2, tmp2);
8298   crc32(tmp2, tmp1, 4);
8299   xorl(in1, tmp2);
8300   xorl(in_out, in1);
8301   xorl(in_out, in2);
8302 }
8303 
8304 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8305                                        Register in_out1, Register in_out2, Register in_out3,
8306                                        Register tmp1, Register tmp2, Register tmp3,
8307                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8308                                        Register tmp4, Register tmp5,
8309                                        Register n_tmp6) {
8310   Label L_processPartitions;
8311   Label L_processPartition;
8312   Label L_exit;
8313 
8314   bind(L_processPartitions);
8315   cmpl(in_out1, 3 * size);
8316   jcc(Assembler::less, L_exit);
8317     xorl(tmp1, tmp1);
8318     xorl(tmp2, tmp2);
8319     movl(tmp3, in_out2);
8320     addl(tmp3, size);
8321 
8322     bind(L_processPartition);
8323       crc32(in_out3, Address(in_out2, 0), 4);
8324       crc32(tmp1, Address(in_out2, size), 4);
8325       crc32(tmp2, Address(in_out2, size*2), 4);
8326       crc32(in_out3, Address(in_out2, 0+4), 4);
8327       crc32(tmp1, Address(in_out2, size+4), 4);
8328       crc32(tmp2, Address(in_out2, size*2+4), 4);
8329       addl(in_out2, 8);
8330       cmpl(in_out2, tmp3);
8331       jcc(Assembler::less, L_processPartition);
8332 
8333         push(tmp3);
8334         push(in_out1);
8335         push(in_out2);
8336         tmp4 = tmp3;
8337         tmp5 = in_out1;
8338         n_tmp6 = in_out2;
8339 
8340       crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8341             w_xtmp1, w_xtmp2, w_xtmp3,
8342             tmp4, tmp5,
8343             n_tmp6);
8344 
8345         pop(in_out2);
8346         pop(in_out1);
8347         pop(tmp3);
8348 
8349     addl(in_out2, 2 * size);
8350     subl(in_out1, 3 * size);
8351     jmp(L_processPartitions);
8352 
8353   bind(L_exit);
8354 }
8355 #endif //LP64
8356 
8357 #ifdef _LP64
8358 // Algorithm 2: Pipelined usage of the CRC32 instruction.
8359 // Input: A buffer I of L bytes.
8360 // Output: the CRC32C value of the buffer.
8361 // Notations:
8362 // Write L = 24N + r, with N = floor (L/24).
8363 // r = L mod 24 (0 <= r < 24).
8364 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
8365 // N quadwords, and R consists of r bytes.
8366 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
8367 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
8368 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
8369 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
8370 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
8371                                           Register tmp1, Register tmp2, Register tmp3,
8372                                           Register tmp4, Register tmp5, Register tmp6,
8373                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8374                                           bool is_pclmulqdq_supported) {
8375   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
8376   Label L_wordByWord;
8377   Label L_byteByByteProlog;
8378   Label L_byteByByte;
8379   Label L_exit;
8380 
8381   if (is_pclmulqdq_supported ) {
8382     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
8383     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
8384 
8385     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
8386     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
8387 
8388     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
8389     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
8390     assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
8391   } else {
8392     const_or_pre_comp_const_index[0] = 1;
8393     const_or_pre_comp_const_index[1] = 0;
8394 
8395     const_or_pre_comp_const_index[2] = 3;
8396     const_or_pre_comp_const_index[3] = 2;
8397 
8398     const_or_pre_comp_const_index[4] = 5;
8399     const_or_pre_comp_const_index[5] = 4;
8400    }
8401   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8402                     in2, in1, in_out,
8403                     tmp1, tmp2, tmp3,
8404                     w_xtmp1, w_xtmp2, w_xtmp3,
8405                     tmp4, tmp5,
8406                     tmp6);
8407   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8408                     in2, in1, in_out,
8409                     tmp1, tmp2, tmp3,
8410                     w_xtmp1, w_xtmp2, w_xtmp3,
8411                     tmp4, tmp5,
8412                     tmp6);
8413   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8414                     in2, in1, in_out,
8415                     tmp1, tmp2, tmp3,
8416                     w_xtmp1, w_xtmp2, w_xtmp3,
8417                     tmp4, tmp5,
8418                     tmp6);
8419   movl(tmp1, in2);
8420   andl(tmp1, 0x00000007);
8421   negl(tmp1);
8422   addl(tmp1, in2);
8423   addq(tmp1, in1);
8424 
8425   BIND(L_wordByWord);
8426   cmpq(in1, tmp1);
8427   jcc(Assembler::greaterEqual, L_byteByByteProlog);
8428     crc32(in_out, Address(in1, 0), 4);
8429     addq(in1, 4);
8430     jmp(L_wordByWord);
8431 
8432   BIND(L_byteByByteProlog);
8433   andl(in2, 0x00000007);
8434   movl(tmp2, 1);
8435 
8436   BIND(L_byteByByte);
8437   cmpl(tmp2, in2);
8438   jccb(Assembler::greater, L_exit);
8439     crc32(in_out, Address(in1, 0), 1);
8440     incq(in1);
8441     incl(tmp2);
8442     jmp(L_byteByByte);
8443 
8444   BIND(L_exit);
8445 }
8446 #else
8447 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
8448                                           Register tmp1, Register  tmp2, Register tmp3,
8449                                           Register tmp4, Register  tmp5, Register tmp6,
8450                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8451                                           bool is_pclmulqdq_supported) {
8452   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
8453   Label L_wordByWord;
8454   Label L_byteByByteProlog;
8455   Label L_byteByByte;
8456   Label L_exit;
8457 
8458   if (is_pclmulqdq_supported) {
8459     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
8460     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
8461 
8462     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
8463     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
8464 
8465     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
8466     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
8467   } else {
8468     const_or_pre_comp_const_index[0] = 1;
8469     const_or_pre_comp_const_index[1] = 0;
8470 
8471     const_or_pre_comp_const_index[2] = 3;
8472     const_or_pre_comp_const_index[3] = 2;
8473 
8474     const_or_pre_comp_const_index[4] = 5;
8475     const_or_pre_comp_const_index[5] = 4;
8476   }
8477   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8478                     in2, in1, in_out,
8479                     tmp1, tmp2, tmp3,
8480                     w_xtmp1, w_xtmp2, w_xtmp3,
8481                     tmp4, tmp5,
8482                     tmp6);
8483   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8484                     in2, in1, in_out,
8485                     tmp1, tmp2, tmp3,
8486                     w_xtmp1, w_xtmp2, w_xtmp3,
8487                     tmp4, tmp5,
8488                     tmp6);
8489   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8490                     in2, in1, in_out,
8491                     tmp1, tmp2, tmp3,
8492                     w_xtmp1, w_xtmp2, w_xtmp3,
8493                     tmp4, tmp5,
8494                     tmp6);
8495   movl(tmp1, in2);
8496   andl(tmp1, 0x00000007);
8497   negl(tmp1);
8498   addl(tmp1, in2);
8499   addl(tmp1, in1);
8500 
8501   BIND(L_wordByWord);
8502   cmpl(in1, tmp1);
8503   jcc(Assembler::greaterEqual, L_byteByByteProlog);
8504     crc32(in_out, Address(in1,0), 4);
8505     addl(in1, 4);
8506     jmp(L_wordByWord);
8507 
8508   BIND(L_byteByByteProlog);
8509   andl(in2, 0x00000007);
8510   movl(tmp2, 1);
8511 
8512   BIND(L_byteByByte);
8513   cmpl(tmp2, in2);
8514   jccb(Assembler::greater, L_exit);
8515     movb(tmp1, Address(in1, 0));
8516     crc32(in_out, tmp1, 1);
8517     incl(in1);
8518     incl(tmp2);
8519     jmp(L_byteByByte);
8520 
8521   BIND(L_exit);
8522 }
8523 #endif // LP64
8524 #undef BIND
8525 #undef BLOCK_COMMENT
8526 
8527 // Compress char[] array to byte[].
8528 //   ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
8529 //   @IntrinsicCandidate
8530 //   private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
8531 //     for (int i = 0; i < len; i++) {
8532 //       int c = src[srcOff++];
8533 //       if (c >>> 8 != 0) {
8534 //         return 0;
8535 //       }
8536 //       dst[dstOff++] = (byte)c;
8537 //     }
8538 //     return len;
8539 //   }
8540 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
8541   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8542   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8543   Register tmp5, Register result, KRegister mask1, KRegister mask2) {
8544   Label copy_chars_loop, return_length, return_zero, done;
8545 
8546   // rsi: src
8547   // rdi: dst
8548   // rdx: len
8549   // rcx: tmp5
8550   // rax: result
8551 
8552   // rsi holds start addr of source char[] to be compressed
8553   // rdi holds start addr of destination byte[]
8554   // rdx holds length
8555 
8556   assert(len != result, "");
8557 
8558   // save length for return
8559   push(len);
8560 
8561   if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
8562     VM_Version::supports_avx512vlbw() &&
8563     VM_Version::supports_bmi2()) {
8564 
8565     Label copy_32_loop, copy_loop_tail, below_threshold;
8566 
8567     // alignment
8568     Label post_alignment;
8569 
8570     // if length of the string is less than 16, handle it in an old fashioned way
8571     testl(len, -32);
8572     jcc(Assembler::zero, below_threshold);
8573 
8574     // First check whether a character is compressable ( <= 0xFF).
8575     // Create mask to test for Unicode chars inside zmm vector
8576     movl(result, 0x00FF);
8577     evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
8578 
8579     testl(len, -64);
8580     jcc(Assembler::zero, post_alignment);
8581 
8582     movl(tmp5, dst);
8583     andl(tmp5, (32 - 1));
8584     negl(tmp5);
8585     andl(tmp5, (32 - 1));
8586 
8587     // bail out when there is nothing to be done
8588     testl(tmp5, 0xFFFFFFFF);
8589     jcc(Assembler::zero, post_alignment);
8590 
8591     // ~(~0 << len), where len is the # of remaining elements to process
8592     movl(result, 0xFFFFFFFF);
8593     shlxl(result, result, tmp5);
8594     notl(result);
8595     kmovdl(mask2, result);
8596 
8597     evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8598     evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8599     ktestd(mask1, mask2);
8600     jcc(Assembler::carryClear, return_zero);
8601 
8602     evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8603 
8604     addptr(src, tmp5);
8605     addptr(src, tmp5);
8606     addptr(dst, tmp5);
8607     subl(len, tmp5);
8608 
8609     bind(post_alignment);
8610     // end of alignment
8611 
8612     movl(tmp5, len);
8613     andl(tmp5, (32 - 1));    // tail count (in chars)
8614     andl(len, ~(32 - 1));    // vector count (in chars)
8615     jcc(Assembler::zero, copy_loop_tail);
8616 
8617     lea(src, Address(src, len, Address::times_2));
8618     lea(dst, Address(dst, len, Address::times_1));
8619     negptr(len);
8620 
8621     bind(copy_32_loop);
8622     evmovdquw(tmp1Reg, Address(src, len, Address::times_2), /*merge*/ false, Assembler::AVX_512bit);
8623     evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
8624     kortestdl(mask1, mask1);
8625     jcc(Assembler::carryClear, return_zero);
8626 
8627     // All elements in current processed chunk are valid candidates for
8628     // compression. Write a truncated byte elements to the memory.
8629     evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
8630     addptr(len, 32);
8631     jcc(Assembler::notZero, copy_32_loop);
8632 
8633     bind(copy_loop_tail);
8634     // bail out when there is nothing to be done
8635     testl(tmp5, 0xFFFFFFFF);
8636     jcc(Assembler::zero, return_length);
8637 
8638     movl(len, tmp5);
8639 
8640     // ~(~0 << len), where len is the # of remaining elements to process
8641     movl(result, 0xFFFFFFFF);
8642     shlxl(result, result, len);
8643     notl(result);
8644 
8645     kmovdl(mask2, result);
8646 
8647     evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8648     evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8649     ktestd(mask1, mask2);
8650     jcc(Assembler::carryClear, return_zero);
8651 
8652     evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8653     jmp(return_length);
8654 
8655     bind(below_threshold);
8656   }
8657 
8658   if (UseSSE42Intrinsics) {
8659     Label copy_32_loop, copy_16, copy_tail;
8660 
8661     movl(result, len);
8662 
8663     movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vectors
8664 
8665     // vectored compression
8666     andl(len, 0xfffffff0);    // vector count (in chars)
8667     andl(result, 0x0000000f);    // tail count (in chars)
8668     testl(len, len);
8669     jcc(Assembler::zero, copy_16);
8670 
8671     // compress 16 chars per iter
8672     movdl(tmp1Reg, tmp5);
8673     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
8674     pxor(tmp4Reg, tmp4Reg);
8675 
8676     lea(src, Address(src, len, Address::times_2));
8677     lea(dst, Address(dst, len, Address::times_1));
8678     negptr(len);
8679 
8680     bind(copy_32_loop);
8681     movdqu(tmp2Reg, Address(src, len, Address::times_2));     // load 1st 8 characters
8682     por(tmp4Reg, tmp2Reg);
8683     movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
8684     por(tmp4Reg, tmp3Reg);
8685     ptest(tmp4Reg, tmp1Reg);       // check for Unicode chars in next vector
8686     jcc(Assembler::notZero, return_zero);
8687     packuswb(tmp2Reg, tmp3Reg);    // only ASCII chars; compress each to 1 byte
8688     movdqu(Address(dst, len, Address::times_1), tmp2Reg);
8689     addptr(len, 16);
8690     jcc(Assembler::notZero, copy_32_loop);
8691 
8692     // compress next vector of 8 chars (if any)
8693     bind(copy_16);
8694     movl(len, result);
8695     andl(len, 0xfffffff8);    // vector count (in chars)
8696     andl(result, 0x00000007);    // tail count (in chars)
8697     testl(len, len);
8698     jccb(Assembler::zero, copy_tail);
8699 
8700     movdl(tmp1Reg, tmp5);
8701     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
8702     pxor(tmp3Reg, tmp3Reg);
8703 
8704     movdqu(tmp2Reg, Address(src, 0));
8705     ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in vector
8706     jccb(Assembler::notZero, return_zero);
8707     packuswb(tmp2Reg, tmp3Reg);    // only LATIN1 chars; compress each to 1 byte
8708     movq(Address(dst, 0), tmp2Reg);
8709     addptr(src, 16);
8710     addptr(dst, 8);
8711 
8712     bind(copy_tail);
8713     movl(len, result);
8714   }
8715   // compress 1 char per iter
8716   testl(len, len);
8717   jccb(Assembler::zero, return_length);
8718   lea(src, Address(src, len, Address::times_2));
8719   lea(dst, Address(dst, len, Address::times_1));
8720   negptr(len);
8721 
8722   bind(copy_chars_loop);
8723   load_unsigned_short(result, Address(src, len, Address::times_2));
8724   testl(result, 0xff00);      // check if Unicode char
8725   jccb(Assembler::notZero, return_zero);
8726   movb(Address(dst, len, Address::times_1), result);  // ASCII char; compress to 1 byte
8727   increment(len);
8728   jcc(Assembler::notZero, copy_chars_loop);
8729 
8730   // if compression succeeded, return length
8731   bind(return_length);
8732   pop(result);
8733   jmpb(done);
8734 
8735   // if compression failed, return 0
8736   bind(return_zero);
8737   xorl(result, result);
8738   addptr(rsp, wordSize);
8739 
8740   bind(done);
8741 }
8742 
8743 // Inflate byte[] array to char[].
8744 //   ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
8745 //   @IntrinsicCandidate
8746 //   private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
8747 //     for (int i = 0; i < len; i++) {
8748 //       dst[dstOff++] = (char)(src[srcOff++] & 0xff);
8749 //     }
8750 //   }
8751 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
8752   XMMRegister tmp1, Register tmp2, KRegister mask) {
8753   Label copy_chars_loop, done, below_threshold, avx3_threshold;
8754   // rsi: src
8755   // rdi: dst
8756   // rdx: len
8757   // rcx: tmp2
8758 
8759   // rsi holds start addr of source byte[] to be inflated
8760   // rdi holds start addr of destination char[]
8761   // rdx holds length
8762   assert_different_registers(src, dst, len, tmp2);
8763   movl(tmp2, len);
8764   if ((UseAVX > 2) && // AVX512
8765     VM_Version::supports_avx512vlbw() &&
8766     VM_Version::supports_bmi2()) {
8767 
8768     Label copy_32_loop, copy_tail;
8769     Register tmp3_aliased = len;
8770 
8771     // if length of the string is less than 16, handle it in an old fashioned way
8772     testl(len, -16);
8773     jcc(Assembler::zero, below_threshold);
8774 
8775     testl(len, -1 * AVX3Threshold);
8776     jcc(Assembler::zero, avx3_threshold);
8777 
8778     // In order to use only one arithmetic operation for the main loop we use
8779     // this pre-calculation
8780     andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
8781     andl(len, -32);     // vector count
8782     jccb(Assembler::zero, copy_tail);
8783 
8784     lea(src, Address(src, len, Address::times_1));
8785     lea(dst, Address(dst, len, Address::times_2));
8786     negptr(len);
8787 
8788 
8789     // inflate 32 chars per iter
8790     bind(copy_32_loop);
8791     vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
8792     evmovdquw(Address(dst, len, Address::times_2), tmp1, /*merge*/ false, Assembler::AVX_512bit);
8793     addptr(len, 32);
8794     jcc(Assembler::notZero, copy_32_loop);
8795 
8796     bind(copy_tail);
8797     // bail out when there is nothing to be done
8798     testl(tmp2, -1); // we don't destroy the contents of tmp2 here
8799     jcc(Assembler::zero, done);
8800 
8801     // ~(~0 << length), where length is the # of remaining elements to process
8802     movl(tmp3_aliased, -1);
8803     shlxl(tmp3_aliased, tmp3_aliased, tmp2);
8804     notl(tmp3_aliased);
8805     kmovdl(mask, tmp3_aliased);
8806     evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
8807     evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
8808 
8809     jmp(done);
8810     bind(avx3_threshold);
8811   }
8812   if (UseSSE42Intrinsics) {
8813     Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
8814 
8815     if (UseAVX > 1) {
8816       andl(tmp2, (16 - 1));
8817       andl(len, -16);
8818       jccb(Assembler::zero, copy_new_tail);
8819     } else {
8820       andl(tmp2, 0x00000007);   // tail count (in chars)
8821       andl(len, 0xfffffff8);    // vector count (in chars)
8822       jccb(Assembler::zero, copy_tail);
8823     }
8824 
8825     // vectored inflation
8826     lea(src, Address(src, len, Address::times_1));
8827     lea(dst, Address(dst, len, Address::times_2));
8828     negptr(len);
8829 
8830     if (UseAVX > 1) {
8831       bind(copy_16_loop);
8832       vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
8833       vmovdqu(Address(dst, len, Address::times_2), tmp1);
8834       addptr(len, 16);
8835       jcc(Assembler::notZero, copy_16_loop);
8836 
8837       bind(below_threshold);
8838       bind(copy_new_tail);
8839       movl(len, tmp2);
8840       andl(tmp2, 0x00000007);
8841       andl(len, 0xFFFFFFF8);
8842       jccb(Assembler::zero, copy_tail);
8843 
8844       pmovzxbw(tmp1, Address(src, 0));
8845       movdqu(Address(dst, 0), tmp1);
8846       addptr(src, 8);
8847       addptr(dst, 2 * 8);
8848 
8849       jmp(copy_tail, true);
8850     }
8851 
8852     // inflate 8 chars per iter
8853     bind(copy_8_loop);
8854     pmovzxbw(tmp1, Address(src, len, Address::times_1));  // unpack to 8 words
8855     movdqu(Address(dst, len, Address::times_2), tmp1);
8856     addptr(len, 8);
8857     jcc(Assembler::notZero, copy_8_loop);
8858 
8859     bind(copy_tail);
8860     movl(len, tmp2);
8861 
8862     cmpl(len, 4);
8863     jccb(Assembler::less, copy_bytes);
8864 
8865     movdl(tmp1, Address(src, 0));  // load 4 byte chars
8866     pmovzxbw(tmp1, tmp1);
8867     movq(Address(dst, 0), tmp1);
8868     subptr(len, 4);
8869     addptr(src, 4);
8870     addptr(dst, 8);
8871 
8872     bind(copy_bytes);
8873   } else {
8874     bind(below_threshold);
8875   }
8876 
8877   testl(len, len);
8878   jccb(Assembler::zero, done);
8879   lea(src, Address(src, len, Address::times_1));
8880   lea(dst, Address(dst, len, Address::times_2));
8881   negptr(len);
8882 
8883   // inflate 1 char per iter
8884   bind(copy_chars_loop);
8885   load_unsigned_byte(tmp2, Address(src, len, Address::times_1));  // load byte char
8886   movw(Address(dst, len, Address::times_2), tmp2);  // inflate byte char to word
8887   increment(len);
8888   jcc(Assembler::notZero, copy_chars_loop);
8889 
8890   bind(done);
8891 }
8892 
8893 
8894 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, int vector_len) {
8895   switch(type) {
8896     case T_BYTE:
8897     case T_BOOLEAN:
8898       evmovdqub(dst, kmask, src, false, vector_len);
8899       break;
8900     case T_CHAR:
8901     case T_SHORT:
8902       evmovdquw(dst, kmask, src, false, vector_len);
8903       break;
8904     case T_INT:
8905     case T_FLOAT:
8906       evmovdqul(dst, kmask, src, false, vector_len);
8907       break;
8908     case T_LONG:
8909     case T_DOUBLE:
8910       evmovdquq(dst, kmask, src, false, vector_len);
8911       break;
8912     default:
8913       fatal("Unexpected type argument %s", type2name(type));
8914       break;
8915   }
8916 }
8917 
8918 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, int vector_len) {
8919   switch(type) {
8920     case T_BYTE:
8921     case T_BOOLEAN:
8922       evmovdqub(dst, kmask, src, true, vector_len);
8923       break;
8924     case T_CHAR:
8925     case T_SHORT:
8926       evmovdquw(dst, kmask, src, true, vector_len);
8927       break;
8928     case T_INT:
8929     case T_FLOAT:
8930       evmovdqul(dst, kmask, src, true, vector_len);
8931       break;
8932     case T_LONG:
8933     case T_DOUBLE:
8934       evmovdquq(dst, kmask, src, true, vector_len);
8935       break;
8936     default:
8937       fatal("Unexpected type argument %s", type2name(type));
8938       break;
8939   }
8940 }
8941 
8942 #if COMPILER2_OR_JVMCI
8943 
8944 
8945 // Set memory operation for length "less than" 64 bytes.
8946 void MacroAssembler::fill64_masked_avx(uint shift, Register dst, int disp,
8947                                        XMMRegister xmm, KRegister mask, Register length,
8948                                        Register temp, bool use64byteVector) {
8949   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8950   assert(shift != 0, "shift value should be 1 (short),2(int) or 3(long)");
8951   BasicType type[] = { T_BYTE, T_SHORT,  T_INT,   T_LONG};
8952   if (!use64byteVector) {
8953     fill32_avx(dst, disp, xmm);
8954     subptr(length, 32 >> shift);
8955     fill32_masked_avx(shift, dst, disp + 32, xmm, mask, length, temp);
8956   } else {
8957     assert(MaxVectorSize == 64, "vector length != 64");
8958     movl(temp, 1);
8959     shlxl(temp, temp, length);
8960     subptr(temp, 1);
8961     kmovwl(mask, temp);
8962     evmovdqu(type[shift], mask, Address(dst, disp), xmm, Assembler::AVX_512bit);
8963   }
8964 }
8965 
8966 
8967 void MacroAssembler::fill32_masked_avx(uint shift, Register dst, int disp,
8968                                        XMMRegister xmm, KRegister mask, Register length,
8969                                        Register temp) {
8970   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8971   assert(shift != 0, "shift value should be 1 (short), 2(int) or 3(long)");
8972   BasicType type[] = { T_BYTE, T_SHORT,  T_INT,   T_LONG};
8973   movl(temp, 1);
8974   shlxl(temp, temp, length);
8975   subptr(temp, 1);
8976   kmovwl(mask, temp);
8977   evmovdqu(type[shift], mask, Address(dst, disp), xmm, Assembler::AVX_256bit);
8978 }
8979 
8980 
8981 void MacroAssembler::fill32_avx(Register dst, int disp, XMMRegister xmm) {
8982   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8983   vmovdqu(Address(dst, disp), xmm);
8984 }
8985 
8986 void MacroAssembler::fill64_avx(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
8987   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8988   BasicType type[] = {T_BYTE,  T_SHORT,  T_INT,   T_LONG};
8989   if (!use64byteVector) {
8990     fill32_avx(dst, disp, xmm);
8991     fill32_avx(dst, disp + 32, xmm);
8992   } else {
8993     evmovdquq(Address(dst, disp), xmm, Assembler::AVX_512bit);
8994   }
8995 }
8996 
8997 #endif //COMPILER2_OR_JVMCI
8998 
8999 
9000 #ifdef _LP64
9001 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
9002   Label done;
9003   cvttss2sil(dst, src);
9004   // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9005   cmpl(dst, 0x80000000); // float_sign_flip
9006   jccb(Assembler::notEqual, done);
9007   subptr(rsp, 8);
9008   movflt(Address(rsp, 0), src);
9009   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9010   pop(dst);
9011   bind(done);
9012 }
9013 
9014 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
9015   Label done;
9016   cvttsd2sil(dst, src);
9017   // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9018   cmpl(dst, 0x80000000); // float_sign_flip
9019   jccb(Assembler::notEqual, done);
9020   subptr(rsp, 8);
9021   movdbl(Address(rsp, 0), src);
9022   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9023   pop(dst);
9024   bind(done);
9025 }
9026 
9027 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
9028   Label done;
9029   cvttss2siq(dst, src);
9030   cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9031   jccb(Assembler::notEqual, done);
9032   subptr(rsp, 8);
9033   movflt(Address(rsp, 0), src);
9034   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9035   pop(dst);
9036   bind(done);
9037 }
9038 
9039 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
9040   Label done;
9041   cvttsd2siq(dst, src);
9042   cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9043   jccb(Assembler::notEqual, done);
9044   subptr(rsp, 8);
9045   movdbl(Address(rsp, 0), src);
9046   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
9047   pop(dst);
9048   bind(done);
9049 }
9050 
9051 void MacroAssembler::cache_wb(Address line)
9052 {
9053   // 64 bit cpus always support clflush
9054   assert(VM_Version::supports_clflush(), "clflush should be available");
9055   bool optimized = VM_Version::supports_clflushopt();
9056   bool no_evict = VM_Version::supports_clwb();
9057 
9058   // prefer clwb (writeback without evict) otherwise
9059   // prefer clflushopt (potentially parallel writeback with evict)
9060   // otherwise fallback on clflush (serial writeback with evict)
9061 
9062   if (optimized) {
9063     if (no_evict) {
9064       clwb(line);
9065     } else {
9066       clflushopt(line);
9067     }
9068   } else {
9069     // no need for fence when using CLFLUSH
9070     clflush(line);
9071   }
9072 }
9073 
9074 void MacroAssembler::cache_wbsync(bool is_pre)
9075 {
9076   assert(VM_Version::supports_clflush(), "clflush should be available");
9077   bool optimized = VM_Version::supports_clflushopt();
9078   bool no_evict = VM_Version::supports_clwb();
9079 
9080   // pick the correct implementation
9081 
9082   if (!is_pre && (optimized || no_evict)) {
9083     // need an sfence for post flush when using clflushopt or clwb
9084     // otherwise no no need for any synchroniaztion
9085 
9086     sfence();
9087   }
9088 }
9089 
9090 #endif // _LP64
9091 
9092 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9093   switch (cond) {
9094     // Note some conditions are synonyms for others
9095     case Assembler::zero:         return Assembler::notZero;
9096     case Assembler::notZero:      return Assembler::zero;
9097     case Assembler::less:         return Assembler::greaterEqual;
9098     case Assembler::lessEqual:    return Assembler::greater;
9099     case Assembler::greater:      return Assembler::lessEqual;
9100     case Assembler::greaterEqual: return Assembler::less;
9101     case Assembler::below:        return Assembler::aboveEqual;
9102     case Assembler::belowEqual:   return Assembler::above;
9103     case Assembler::above:        return Assembler::belowEqual;
9104     case Assembler::aboveEqual:   return Assembler::below;
9105     case Assembler::overflow:     return Assembler::noOverflow;
9106     case Assembler::noOverflow:   return Assembler::overflow;
9107     case Assembler::negative:     return Assembler::positive;
9108     case Assembler::positive:     return Assembler::negative;
9109     case Assembler::parity:       return Assembler::noParity;
9110     case Assembler::noParity:     return Assembler::parity;
9111   }
9112   ShouldNotReachHere(); return Assembler::overflow;
9113 }
9114 
9115 SkipIfEqual::SkipIfEqual(
9116     MacroAssembler* masm, const bool* flag_addr, bool value) {
9117   _masm = masm;
9118   _masm->cmp8(ExternalAddress((address)flag_addr), value);
9119   _masm->jcc(Assembler::equal, _label);
9120 }
9121 
9122 SkipIfEqual::~SkipIfEqual() {
9123   _masm->bind(_label);
9124 }
9125 
9126 // 32-bit Windows has its own fast-path implementation
9127 // of get_thread
9128 #if !defined(WIN32) || defined(_LP64)
9129 
9130 // This is simply a call to Thread::current()
9131 void MacroAssembler::get_thread(Register thread) {
9132   if (thread != rax) {
9133     push(rax);
9134   }
9135   LP64_ONLY(push(rdi);)
9136   LP64_ONLY(push(rsi);)
9137   push(rdx);
9138   push(rcx);
9139 #ifdef _LP64
9140   push(r8);
9141   push(r9);
9142   push(r10);
9143   push(r11);
9144 #endif
9145 
9146   MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9147 
9148 #ifdef _LP64
9149   pop(r11);
9150   pop(r10);
9151   pop(r9);
9152   pop(r8);
9153 #endif
9154   pop(rcx);
9155   pop(rdx);
9156   LP64_ONLY(pop(rsi);)
9157   LP64_ONLY(pop(rdi);)
9158   if (thread != rax) {
9159     mov(thread, rax);
9160     pop(rax);
9161   }
9162 }
9163 
9164 #endif // !WIN32 || _LP64