1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/aotCodeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "ci/ciInlineKlass.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "interpreter/interpreterRuntime.hpp"
40 #include "jvm.h"
41 #include "memory/resourceArea.hpp"
42 #include "memory/universe.hpp"
43 #include "oops/accessDecorators.hpp"
44 #include "oops/compressedKlass.inline.hpp"
45 #include "oops/compressedOops.inline.hpp"
46 #include "oops/klass.inline.hpp"
47 #include "oops/resolvedFieldEntry.hpp"
48 #include "prims/methodHandles.hpp"
49 #include "runtime/arguments.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/interfaceSupport.inline.hpp"
52 #include "runtime/javaThread.hpp"
53 #include "runtime/jniHandles.hpp"
54 #include "runtime/objectMonitor.hpp"
55 #include "runtime/os.hpp"
56 #include "runtime/safepoint.hpp"
57 #include "runtime/safepointMechanism.hpp"
58 #include "runtime/sharedRuntime.hpp"
59 #include "runtime/signature_cc.hpp"
60 #include "runtime/stubRoutines.hpp"
61 #include "utilities/checkedCast.hpp"
62 #include "utilities/macros.hpp"
63 #include "vmreg_x86.inline.hpp"
64 #ifdef COMPILER2
65 #include "opto/output.hpp"
66 #endif
67
68 #ifdef PRODUCT
69 #define BLOCK_COMMENT(str) /* nothing */
70 #define STOP(error) stop(error)
71 #else
72 #define BLOCK_COMMENT(str) block_comment(str)
73 #define STOP(error) block_comment(error); stop(error)
74 #endif
75
76 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
77
78 #ifdef ASSERT
79 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
80 #endif
81
82 static const Assembler::Condition reverse[] = {
83 Assembler::noOverflow /* overflow = 0x0 */ ,
84 Assembler::overflow /* noOverflow = 0x1 */ ,
85 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
86 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
87 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
88 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
89 Assembler::above /* belowEqual = 0x6 */ ,
90 Assembler::belowEqual /* above = 0x7 */ ,
91 Assembler::positive /* negative = 0x8 */ ,
92 Assembler::negative /* positive = 0x9 */ ,
93 Assembler::noParity /* parity = 0xa */ ,
94 Assembler::parity /* noParity = 0xb */ ,
95 Assembler::greaterEqual /* less = 0xc */ ,
96 Assembler::less /* greaterEqual = 0xd */ ,
97 Assembler::greater /* lessEqual = 0xe */ ,
98 Assembler::lessEqual /* greater = 0xf, */
99
100 };
101
102
103 // Implementation of MacroAssembler
104
105 Address MacroAssembler::as_Address(AddressLiteral adr) {
106 // amd64 always does this as a pc-rel
107 // we can be absolute or disp based on the instruction type
108 // jmp/call are displacements others are absolute
109 assert(!adr.is_lval(), "must be rval");
110 assert(reachable(adr), "must be");
111 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
112
113 }
114
115 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
116 AddressLiteral base = adr.base();
117 lea(rscratch, base);
118 Address index = adr.index();
119 assert(index._disp == 0, "must not have disp"); // maybe it can?
120 Address array(rscratch, index._index, index._scale, index._disp);
121 return array;
122 }
123
124 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
125 Label L, E;
126
127 #ifdef _WIN64
128 // Windows always allocates space for it's register args
129 assert(num_args <= 4, "only register arguments supported");
130 subq(rsp, frame::arg_reg_save_area_bytes);
131 #endif
132
133 // Align stack if necessary
134 testl(rsp, 15);
135 jcc(Assembler::zero, L);
136
137 subq(rsp, 8);
138 call(RuntimeAddress(entry_point));
139 addq(rsp, 8);
140 jmp(E);
141
142 bind(L);
143 call(RuntimeAddress(entry_point));
144
145 bind(E);
146
147 #ifdef _WIN64
148 // restore stack pointer
149 addq(rsp, frame::arg_reg_save_area_bytes);
150 #endif
151 }
152
153 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
154 assert(!src2.is_lval(), "should use cmpptr");
155 assert(rscratch != noreg || always_reachable(src2), "missing");
156
157 if (reachable(src2)) {
158 cmpq(src1, as_Address(src2));
159 } else {
160 lea(rscratch, src2);
161 Assembler::cmpq(src1, Address(rscratch, 0));
162 }
163 }
164
165 int MacroAssembler::corrected_idivq(Register reg) {
166 // Full implementation of Java ldiv and lrem; checks for special
167 // case as described in JVM spec., p.243 & p.271. The function
168 // returns the (pc) offset of the idivl instruction - may be needed
169 // for implicit exceptions.
170 //
171 // normal case special case
172 //
173 // input : rax: dividend min_long
174 // reg: divisor (may not be eax/edx) -1
175 //
176 // output: rax: quotient (= rax idiv reg) min_long
177 // rdx: remainder (= rax irem reg) 0
178 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
179 static const int64_t min_long = 0x8000000000000000;
180 Label normal_case, special_case;
181
182 // check for special case
183 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
184 jcc(Assembler::notEqual, normal_case);
185 xorl(rdx, rdx); // prepare rdx for possible special case (where
186 // remainder = 0)
187 cmpq(reg, -1);
188 jcc(Assembler::equal, special_case);
189
190 // handle normal case
191 bind(normal_case);
192 cdqq();
193 int idivq_offset = offset();
194 idivq(reg);
195
196 // normal and special case exit
197 bind(special_case);
198
199 return idivq_offset;
200 }
201
202 void MacroAssembler::decrementq(Register reg, int value) {
203 if (value == min_jint) { subq(reg, value); return; }
204 if (value < 0) { incrementq(reg, -value); return; }
205 if (value == 0) { ; return; }
206 if (value == 1 && UseIncDec) { decq(reg) ; return; }
207 /* else */ { subq(reg, value) ; return; }
208 }
209
210 void MacroAssembler::decrementq(Address dst, int value) {
211 if (value == min_jint) { subq(dst, value); return; }
212 if (value < 0) { incrementq(dst, -value); return; }
213 if (value == 0) { ; return; }
214 if (value == 1 && UseIncDec) { decq(dst) ; return; }
215 /* else */ { subq(dst, value) ; return; }
216 }
217
218 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
219 assert(rscratch != noreg || always_reachable(dst), "missing");
220
221 if (reachable(dst)) {
222 incrementq(as_Address(dst));
223 } else {
224 lea(rscratch, dst);
225 incrementq(Address(rscratch, 0));
226 }
227 }
228
229 void MacroAssembler::incrementq(Register reg, int value) {
230 if (value == min_jint) { addq(reg, value); return; }
231 if (value < 0) { decrementq(reg, -value); return; }
232 if (value == 0) { ; return; }
233 if (value == 1 && UseIncDec) { incq(reg) ; return; }
234 /* else */ { addq(reg, value) ; return; }
235 }
236
237 void MacroAssembler::incrementq(Address dst, int value) {
238 if (value == min_jint) { addq(dst, value); return; }
239 if (value < 0) { decrementq(dst, -value); return; }
240 if (value == 0) { ; return; }
241 if (value == 1 && UseIncDec) { incq(dst) ; return; }
242 /* else */ { addq(dst, value) ; return; }
243 }
244
245 // 32bit can do a case table jump in one instruction but we no longer allow the base
246 // to be installed in the Address class
247 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
248 lea(rscratch, entry.base());
249 Address dispatch = entry.index();
250 assert(dispatch._base == noreg, "must be");
251 dispatch._base = rscratch;
252 jmp(dispatch);
253 }
254
255 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
256 ShouldNotReachHere(); // 64bit doesn't use two regs
257 cmpq(x_lo, y_lo);
258 }
259
260 void MacroAssembler::lea(Register dst, AddressLiteral src) {
261 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
262 }
263
264 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
265 lea(rscratch, adr);
266 movptr(dst, rscratch);
267 }
268
269 void MacroAssembler::leave() {
270 // %%% is this really better? Why not on 32bit too?
271 emit_int8((unsigned char)0xC9); // LEAVE
272 }
273
274 void MacroAssembler::lneg(Register hi, Register lo) {
275 ShouldNotReachHere(); // 64bit doesn't use two regs
276 negq(lo);
277 }
278
279 void MacroAssembler::movoop(Register dst, jobject obj) {
280 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
281 }
282
283 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
284 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
285 movq(dst, rscratch);
286 }
287
288 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
289 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
290 }
291
292 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
293 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
294 movq(dst, rscratch);
295 }
296
297 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
298 if (src.is_lval()) {
299 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
300 } else {
301 if (reachable(src)) {
302 movq(dst, as_Address(src));
303 } else {
304 lea(dst, src);
305 movq(dst, Address(dst, 0));
306 }
307 }
308 }
309
310 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
311 movq(as_Address(dst, rscratch), src);
312 }
313
314 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
315 movq(dst, as_Address(src, dst /*rscratch*/));
316 }
317
318 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
319 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
320 if (is_simm32(src)) {
321 movptr(dst, checked_cast<int32_t>(src));
322 } else {
323 mov64(rscratch, src);
324 movq(dst, rscratch);
325 }
326 }
327
328 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
329 movoop(rscratch, obj);
330 push(rscratch);
331 }
332
333 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
334 mov_metadata(rscratch, obj);
335 push(rscratch);
336 }
337
338 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
339 lea(rscratch, src);
340 if (src.is_lval()) {
341 push(rscratch);
342 } else {
343 pushq(Address(rscratch, 0));
344 }
345 }
346
347 static void pass_arg0(MacroAssembler* masm, Register arg) {
348 if (c_rarg0 != arg ) {
349 masm->mov(c_rarg0, arg);
350 }
351 }
352
353 static void pass_arg1(MacroAssembler* masm, Register arg) {
354 if (c_rarg1 != arg ) {
355 masm->mov(c_rarg1, arg);
356 }
357 }
358
359 static void pass_arg2(MacroAssembler* masm, Register arg) {
360 if (c_rarg2 != arg ) {
361 masm->mov(c_rarg2, arg);
362 }
363 }
364
365 static void pass_arg3(MacroAssembler* masm, Register arg) {
366 if (c_rarg3 != arg ) {
367 masm->mov(c_rarg3, arg);
368 }
369 }
370
371 void MacroAssembler::stop(const char* msg) {
372 if (ShowMessageBoxOnError) {
373 address rip = pc();
374 pusha(); // get regs on stack
375 lea(c_rarg1, InternalAddress(rip));
376 movq(c_rarg2, rsp); // pass pointer to regs array
377 }
378 // Skip AOT caching C strings in scratch buffer.
379 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
380 lea(c_rarg0, ExternalAddress((address) str));
381 andq(rsp, -16); // align stack as required by ABI
382 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
383 hlt();
384 }
385
386 void MacroAssembler::warn(const char* msg) {
387 push(rbp);
388 movq(rbp, rsp);
389 andq(rsp, -16); // align stack as required by push_CPU_state and call
390 push_CPU_state(); // keeps alignment at 16 bytes
391
392 #ifdef _WIN64
393 // Windows always allocates space for its register args
394 subq(rsp, frame::arg_reg_save_area_bytes);
395 #endif
396 lea(c_rarg0, ExternalAddress((address) msg));
397 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
398
399 #ifdef _WIN64
400 // restore stack pointer
401 addq(rsp, frame::arg_reg_save_area_bytes);
402 #endif
403 pop_CPU_state();
404 mov(rsp, rbp);
405 pop(rbp);
406 }
407
408 void MacroAssembler::print_state() {
409 address rip = pc();
410 pusha(); // get regs on stack
411 push(rbp);
412 movq(rbp, rsp);
413 andq(rsp, -16); // align stack as required by push_CPU_state and call
414 push_CPU_state(); // keeps alignment at 16 bytes
415
416 lea(c_rarg0, InternalAddress(rip));
417 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
418 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
419
420 pop_CPU_state();
421 mov(rsp, rbp);
422 pop(rbp);
423 popa();
424 }
425
426 #ifndef PRODUCT
427 extern "C" void findpc(intptr_t x);
428 #endif
429
430 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
431 // In order to get locks to work, we need to fake a in_VM state
432 if (ShowMessageBoxOnError) {
433 JavaThread* thread = JavaThread::current();
434 JavaThreadState saved_state = thread->thread_state();
435 thread->set_thread_state(_thread_in_vm);
436 #ifndef PRODUCT
437 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
438 ttyLocker ttyl;
439 BytecodeCounter::print();
440 }
441 #endif
442 // To see where a verify_oop failed, get $ebx+40/X for this frame.
443 // XXX correct this offset for amd64
444 // This is the value of eip which points to where verify_oop will return.
445 if (os::message_box(msg, "Execution stopped, print registers?")) {
446 print_state64(pc, regs);
447 BREAKPOINT;
448 }
449 }
450 fatal("DEBUG MESSAGE: %s", msg);
451 }
452
453 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
454 ttyLocker ttyl;
455 DebuggingContext debugging{};
456 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
457 #ifndef PRODUCT
458 tty->cr();
459 findpc(pc);
460 tty->cr();
461 #endif
462 #define PRINT_REG(rax, value) \
463 { tty->print("%s = ", #rax); os::print_location(tty, value); }
464 PRINT_REG(rax, regs[15]);
465 PRINT_REG(rbx, regs[12]);
466 PRINT_REG(rcx, regs[14]);
467 PRINT_REG(rdx, regs[13]);
468 PRINT_REG(rdi, regs[8]);
469 PRINT_REG(rsi, regs[9]);
470 PRINT_REG(rbp, regs[10]);
471 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
472 PRINT_REG(rsp, (intptr_t)(®s[16]));
473 PRINT_REG(r8 , regs[7]);
474 PRINT_REG(r9 , regs[6]);
475 PRINT_REG(r10, regs[5]);
476 PRINT_REG(r11, regs[4]);
477 PRINT_REG(r12, regs[3]);
478 PRINT_REG(r13, regs[2]);
479 PRINT_REG(r14, regs[1]);
480 PRINT_REG(r15, regs[0]);
481 #undef PRINT_REG
482 // Print some words near the top of the stack.
483 int64_t* rsp = ®s[16];
484 int64_t* dump_sp = rsp;
485 for (int col1 = 0; col1 < 8; col1++) {
486 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
487 os::print_location(tty, *dump_sp++);
488 }
489 for (int row = 0; row < 25; row++) {
490 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
491 for (int col = 0; col < 4; col++) {
492 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
493 }
494 tty->cr();
495 }
496 // Print some instructions around pc:
497 Disassembler::decode((address)pc-64, (address)pc);
498 tty->print_cr("--------");
499 Disassembler::decode((address)pc, (address)pc+32);
500 }
501
502 // The java_calling_convention describes stack locations as ideal slots on
503 // a frame with no abi restrictions. Since we must observe abi restrictions
504 // (like the placement of the register window) the slots must be biased by
505 // the following value.
506 static int reg2offset_in(VMReg r) {
507 // Account for saved rbp and return address
508 // This should really be in_preserve_stack_slots
509 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
510 }
511
512 static int reg2offset_out(VMReg r) {
513 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
514 }
515
516 // A long move
517 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
518
519 // The calling conventions assures us that each VMregpair is either
520 // all really one physical register or adjacent stack slots.
521
522 if (src.is_single_phys_reg() ) {
523 if (dst.is_single_phys_reg()) {
524 if (dst.first() != src.first()) {
525 mov(dst.first()->as_Register(), src.first()->as_Register());
526 }
527 } else {
528 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
529 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
530 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
531 }
532 } else if (dst.is_single_phys_reg()) {
533 assert(src.is_single_reg(), "not a stack pair");
534 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
535 } else {
536 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
537 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
538 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
539 }
540 }
541
542 // A double move
543 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
544
545 // The calling conventions assures us that each VMregpair is either
546 // all really one physical register or adjacent stack slots.
547
548 if (src.is_single_phys_reg() ) {
549 if (dst.is_single_phys_reg()) {
550 // In theory these overlap but the ordering is such that this is likely a nop
551 if ( src.first() != dst.first()) {
552 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
553 }
554 } else {
555 assert(dst.is_single_reg(), "not a stack pair");
556 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
557 }
558 } else if (dst.is_single_phys_reg()) {
559 assert(src.is_single_reg(), "not a stack pair");
560 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
561 } else {
562 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
563 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
564 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
565 }
566 }
567
568
569 // A float arg may have to do float reg int reg conversion
570 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
571 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
572
573 // The calling conventions assures us that each VMregpair is either
574 // all really one physical register or adjacent stack slots.
575
576 if (src.first()->is_stack()) {
577 if (dst.first()->is_stack()) {
578 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
579 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
580 } else {
581 // stack to reg
582 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
583 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
584 }
585 } else if (dst.first()->is_stack()) {
586 // reg to stack
587 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
588 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
589 } else {
590 // reg to reg
591 // In theory these overlap but the ordering is such that this is likely a nop
592 if ( src.first() != dst.first()) {
593 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
594 }
595 }
596 }
597
598 // On 64 bit we will store integer like items to the stack as
599 // 64 bits items (x86_32/64 abi) even though java would only store
600 // 32bits for a parameter. On 32bit it will simply be 32 bits
601 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
602 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
603 if (src.first()->is_stack()) {
604 if (dst.first()->is_stack()) {
605 // stack to stack
606 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
607 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
608 } else {
609 // stack to reg
610 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
611 }
612 } else if (dst.first()->is_stack()) {
613 // reg to stack
614 // Do we really have to sign extend???
615 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
616 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
617 } else {
618 // Do we really have to sign extend???
619 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
620 if (dst.first() != src.first()) {
621 movq(dst.first()->as_Register(), src.first()->as_Register());
622 }
623 }
624 }
625
626 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
627 if (src.first()->is_stack()) {
628 if (dst.first()->is_stack()) {
629 // stack to stack
630 movq(rax, Address(rbp, reg2offset_in(src.first())));
631 movq(Address(rsp, reg2offset_out(dst.first())), rax);
632 } else {
633 // stack to reg
634 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
635 }
636 } else if (dst.first()->is_stack()) {
637 // reg to stack
638 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
639 } else {
640 if (dst.first() != src.first()) {
641 movq(dst.first()->as_Register(), src.first()->as_Register());
642 }
643 }
644 }
645
646 // An oop arg. Must pass a handle not the oop itself
647 void MacroAssembler::object_move(OopMap* map,
648 int oop_handle_offset,
649 int framesize_in_slots,
650 VMRegPair src,
651 VMRegPair dst,
652 bool is_receiver,
653 int* receiver_offset) {
654
655 // must pass a handle. First figure out the location we use as a handle
656
657 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
658
659 // See if oop is null if it is we need no handle
660
661 if (src.first()->is_stack()) {
662
663 // Oop is already on the stack as an argument
664 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
665 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
666 if (is_receiver) {
667 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
668 }
669
670 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
671 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
672 // conditionally move a null
673 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
674 } else {
675
676 // Oop is in a register we must store it to the space we reserve
677 // on the stack for oop_handles and pass a handle if oop is non-null
678
679 const Register rOop = src.first()->as_Register();
680 int oop_slot;
681 if (rOop == j_rarg0)
682 oop_slot = 0;
683 else if (rOop == j_rarg1)
684 oop_slot = 1;
685 else if (rOop == j_rarg2)
686 oop_slot = 2;
687 else if (rOop == j_rarg3)
688 oop_slot = 3;
689 else if (rOop == j_rarg4)
690 oop_slot = 4;
691 else {
692 assert(rOop == j_rarg5, "wrong register");
693 oop_slot = 5;
694 }
695
696 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
697 int offset = oop_slot*VMRegImpl::stack_slot_size;
698
699 map->set_oop(VMRegImpl::stack2reg(oop_slot));
700 // Store oop in handle area, may be null
701 movptr(Address(rsp, offset), rOop);
702 if (is_receiver) {
703 *receiver_offset = offset;
704 }
705
706 cmpptr(rOop, NULL_WORD);
707 lea(rHandle, Address(rsp, offset));
708 // conditionally move a null from the handle area where it was just stored
709 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
710 }
711
712 // If arg is on the stack then place it otherwise it is already in correct reg.
713 if (dst.first()->is_stack()) {
714 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
715 }
716 }
717
718 void MacroAssembler::addptr(Register dst, int32_t imm32) {
719 addq(dst, imm32);
720 }
721
722 void MacroAssembler::addptr(Register dst, Register src) {
723 addq(dst, src);
724 }
725
726 void MacroAssembler::addptr(Address dst, Register src) {
727 addq(dst, src);
728 }
729
730 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
731 assert(rscratch != noreg || always_reachable(src), "missing");
732
733 if (reachable(src)) {
734 Assembler::addsd(dst, as_Address(src));
735 } else {
736 lea(rscratch, src);
737 Assembler::addsd(dst, Address(rscratch, 0));
738 }
739 }
740
741 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
742 assert(rscratch != noreg || always_reachable(src), "missing");
743
744 if (reachable(src)) {
745 addss(dst, as_Address(src));
746 } else {
747 lea(rscratch, src);
748 addss(dst, Address(rscratch, 0));
749 }
750 }
751
752 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
753 assert(rscratch != noreg || always_reachable(src), "missing");
754
755 if (reachable(src)) {
756 Assembler::addpd(dst, as_Address(src));
757 } else {
758 lea(rscratch, src);
759 Assembler::addpd(dst, Address(rscratch, 0));
760 }
761 }
762
763 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
764 // Stub code is generated once and never copied.
765 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
766 void MacroAssembler::align64() {
767 align(64, (uint)(uintptr_t)pc());
768 }
769
770 void MacroAssembler::align32() {
771 align(32, (uint)(uintptr_t)pc());
772 }
773
774 void MacroAssembler::align(uint modulus) {
775 // 8273459: Ensure alignment is possible with current segment alignment
776 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
777 align(modulus, offset());
778 }
779
780 void MacroAssembler::align(uint modulus, uint target) {
781 if (target % modulus != 0) {
782 nop(modulus - (target % modulus));
783 }
784 }
785
786 void MacroAssembler::push_f(XMMRegister r) {
787 subptr(rsp, wordSize);
788 movflt(Address(rsp, 0), r);
789 }
790
791 void MacroAssembler::pop_f(XMMRegister r) {
792 movflt(r, Address(rsp, 0));
793 addptr(rsp, wordSize);
794 }
795
796 void MacroAssembler::push_d(XMMRegister r) {
797 subptr(rsp, 2 * wordSize);
798 movdbl(Address(rsp, 0), r);
799 }
800
801 void MacroAssembler::pop_d(XMMRegister r) {
802 movdbl(r, Address(rsp, 0));
803 addptr(rsp, 2 * Interpreter::stackElementSize);
804 }
805
806 void MacroAssembler::push_ppx(Register src) {
807 if (VM_Version::supports_apx_f()) {
808 pushp(src);
809 } else {
810 Assembler::push(src);
811 }
812 }
813
814 void MacroAssembler::pop_ppx(Register dst) {
815 if (VM_Version::supports_apx_f()) {
816 popp(dst);
817 } else {
818 Assembler::pop(dst);
819 }
820 }
821
822 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
823 // Used in sign-masking with aligned address.
824 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
825 assert(rscratch != noreg || always_reachable(src), "missing");
826
827 if (UseAVX > 2 &&
828 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
829 (dst->encoding() >= 16)) {
830 vpand(dst, dst, src, AVX_512bit, rscratch);
831 } else if (reachable(src)) {
832 Assembler::andpd(dst, as_Address(src));
833 } else {
834 lea(rscratch, src);
835 Assembler::andpd(dst, Address(rscratch, 0));
836 }
837 }
838
839 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
840 // Used in sign-masking with aligned address.
841 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
842 assert(rscratch != noreg || always_reachable(src), "missing");
843
844 if (reachable(src)) {
845 Assembler::andps(dst, as_Address(src));
846 } else {
847 lea(rscratch, src);
848 Assembler::andps(dst, Address(rscratch, 0));
849 }
850 }
851
852 void MacroAssembler::andptr(Register dst, int32_t imm32) {
853 andq(dst, imm32);
854 }
855
856 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
857 assert(rscratch != noreg || always_reachable(src), "missing");
858
859 if (reachable(src)) {
860 andq(dst, as_Address(src));
861 } else {
862 lea(rscratch, src);
863 andq(dst, Address(rscratch, 0));
864 }
865 }
866
867 void MacroAssembler::atomic_incl(Address counter_addr) {
868 lock();
869 incrementl(counter_addr);
870 }
871
872 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
873 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
874
875 if (reachable(counter_addr)) {
876 atomic_incl(as_Address(counter_addr));
877 } else {
878 lea(rscratch, counter_addr);
879 atomic_incl(Address(rscratch, 0));
880 }
881 }
882
883 void MacroAssembler::atomic_incq(Address counter_addr) {
884 lock();
885 incrementq(counter_addr);
886 }
887
888 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
889 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
890
891 if (reachable(counter_addr)) {
892 atomic_incq(as_Address(counter_addr));
893 } else {
894 lea(rscratch, counter_addr);
895 atomic_incq(Address(rscratch, 0));
896 }
897 }
898
899 // Writes to stack successive pages until offset reached to check for
900 // stack overflow + shadow pages. This clobbers tmp.
901 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
902 movptr(tmp, rsp);
903 // Bang stack for total size given plus shadow page size.
904 // Bang one page at a time because large size can bang beyond yellow and
905 // red zones.
906 Label loop;
907 bind(loop);
908 movl(Address(tmp, (-(int)os::vm_page_size())), size );
909 subptr(tmp, (int)os::vm_page_size());
910 subl(size, (int)os::vm_page_size());
911 jcc(Assembler::greater, loop);
912
913 // Bang down shadow pages too.
914 // At this point, (tmp-0) is the last address touched, so don't
915 // touch it again. (It was touched as (tmp-pagesize) but then tmp
916 // was post-decremented.) Skip this address by starting at i=1, and
917 // touch a few more pages below. N.B. It is important to touch all
918 // the way down including all pages in the shadow zone.
919 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
920 // this could be any sized move but this is can be a debugging crumb
921 // so the bigger the better.
922 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
923 }
924 }
925
926 void MacroAssembler::reserved_stack_check() {
927 // testing if reserved zone needs to be enabled
928 Label no_reserved_zone_enabling;
929
930 cmpptr(rsp, Address(r15_thread, JavaThread::reserved_stack_activation_offset()));
931 jcc(Assembler::below, no_reserved_zone_enabling);
932
933 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), r15_thread);
934 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
935 should_not_reach_here();
936
937 bind(no_reserved_zone_enabling);
938 }
939
940 void MacroAssembler::c2bool(Register x) {
941 // implements x == 0 ? 0 : 1
942 // note: must only look at least-significant byte of x
943 // since C-style booleans are stored in one byte
944 // only! (was bug)
945 andl(x, 0xFF);
946 setb(Assembler::notZero, x);
947 }
948
949 // Wouldn't need if AddressLiteral version had new name
950 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
951 Assembler::call(L, rtype);
952 }
953
954 void MacroAssembler::call(Register entry) {
955 Assembler::call(entry);
956 }
957
958 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
959 assert(rscratch != noreg || always_reachable(entry), "missing");
960
961 if (reachable(entry)) {
962 Assembler::call_literal(entry.target(), entry.rspec());
963 } else {
964 lea(rscratch, entry);
965 Assembler::call(rscratch);
966 }
967 }
968
969 void MacroAssembler::ic_call(address entry, jint method_index) {
970 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
971 // Needs full 64-bit immediate for later patching.
972 Assembler::mov64(rax, (int64_t)Universe::non_oop_word());
973 call(AddressLiteral(entry, rh));
974 }
975
976 int MacroAssembler::ic_check_size() {
977 return UseCompactObjectHeaders ? 17 : 14;
978 }
979
980 int MacroAssembler::ic_check(int end_alignment) {
981 Register receiver = j_rarg0;
982 Register data = rax;
983 Register temp = rscratch1;
984
985 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
986 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
987 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
988 // before the inline cache check here, and not after
989 align(end_alignment, offset() + ic_check_size());
990
991 int uep_offset = offset();
992
993 if (UseCompactObjectHeaders) {
994 load_narrow_klass_compact(temp, receiver);
995 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
996 } else {
997 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
998 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
999 }
1000
1001 // if inline cache check fails, then jump to runtime routine
1002 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1003 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1004
1005 return uep_offset;
1006 }
1007
1008 void MacroAssembler::emit_static_call_stub() {
1009 // Static stub relocation also tags the Method* in the code-stream.
1010 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1011 // This is recognized as unresolved by relocs/nativeinst/ic code.
1012 jump(RuntimeAddress(pc()));
1013 }
1014
1015 // Implementation of call_VM versions
1016
1017 void MacroAssembler::call_VM(Register oop_result,
1018 address entry_point,
1019 bool check_exceptions) {
1020 Label C, E;
1021 call(C, relocInfo::none);
1022 jmp(E);
1023
1024 bind(C);
1025 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1026 ret(0);
1027
1028 bind(E);
1029 }
1030
1031 void MacroAssembler::call_VM(Register oop_result,
1032 address entry_point,
1033 Register arg_1,
1034 bool check_exceptions) {
1035 Label C, E;
1036 call(C, relocInfo::none);
1037 jmp(E);
1038
1039 bind(C);
1040 pass_arg1(this, arg_1);
1041 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1042 ret(0);
1043
1044 bind(E);
1045 }
1046
1047 void MacroAssembler::call_VM(Register oop_result,
1048 address entry_point,
1049 Register arg_1,
1050 Register arg_2,
1051 bool check_exceptions) {
1052 Label C, E;
1053 call(C, relocInfo::none);
1054 jmp(E);
1055
1056 bind(C);
1057
1058 assert_different_registers(arg_1, c_rarg2);
1059
1060 pass_arg2(this, arg_2);
1061 pass_arg1(this, arg_1);
1062 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1063 ret(0);
1064
1065 bind(E);
1066 }
1067
1068 void MacroAssembler::call_VM(Register oop_result,
1069 address entry_point,
1070 Register arg_1,
1071 Register arg_2,
1072 Register arg_3,
1073 bool check_exceptions) {
1074 Label C, E;
1075 call(C, relocInfo::none);
1076 jmp(E);
1077
1078 bind(C);
1079
1080 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1081 assert_different_registers(arg_2, c_rarg3);
1082 pass_arg3(this, arg_3);
1083 pass_arg2(this, arg_2);
1084 pass_arg1(this, arg_1);
1085 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1086 ret(0);
1087
1088 bind(E);
1089 }
1090
1091 void MacroAssembler::call_VM(Register oop_result,
1092 Register last_java_sp,
1093 address entry_point,
1094 int number_of_arguments,
1095 bool check_exceptions) {
1096 call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1097 }
1098
1099 void MacroAssembler::call_VM(Register oop_result,
1100 Register last_java_sp,
1101 address entry_point,
1102 Register arg_1,
1103 bool check_exceptions) {
1104 pass_arg1(this, arg_1);
1105 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1106 }
1107
1108 void MacroAssembler::call_VM(Register oop_result,
1109 Register last_java_sp,
1110 address entry_point,
1111 Register arg_1,
1112 Register arg_2,
1113 bool check_exceptions) {
1114
1115 assert_different_registers(arg_1, c_rarg2);
1116 pass_arg2(this, arg_2);
1117 pass_arg1(this, arg_1);
1118 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1119 }
1120
1121 void MacroAssembler::call_VM(Register oop_result,
1122 Register last_java_sp,
1123 address entry_point,
1124 Register arg_1,
1125 Register arg_2,
1126 Register arg_3,
1127 bool check_exceptions) {
1128 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1129 assert_different_registers(arg_2, c_rarg3);
1130 pass_arg3(this, arg_3);
1131 pass_arg2(this, arg_2);
1132 pass_arg1(this, arg_1);
1133 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1134 }
1135
1136 void MacroAssembler::super_call_VM(Register oop_result,
1137 Register last_java_sp,
1138 address entry_point,
1139 int number_of_arguments,
1140 bool check_exceptions) {
1141 MacroAssembler::call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1142 }
1143
1144 void MacroAssembler::super_call_VM(Register oop_result,
1145 Register last_java_sp,
1146 address entry_point,
1147 Register arg_1,
1148 bool check_exceptions) {
1149 pass_arg1(this, arg_1);
1150 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1151 }
1152
1153 void MacroAssembler::super_call_VM(Register oop_result,
1154 Register last_java_sp,
1155 address entry_point,
1156 Register arg_1,
1157 Register arg_2,
1158 bool check_exceptions) {
1159
1160 assert_different_registers(arg_1, c_rarg2);
1161 pass_arg2(this, arg_2);
1162 pass_arg1(this, arg_1);
1163 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1164 }
1165
1166 void MacroAssembler::super_call_VM(Register oop_result,
1167 Register last_java_sp,
1168 address entry_point,
1169 Register arg_1,
1170 Register arg_2,
1171 Register arg_3,
1172 bool check_exceptions) {
1173 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1174 assert_different_registers(arg_2, c_rarg3);
1175 pass_arg3(this, arg_3);
1176 pass_arg2(this, arg_2);
1177 pass_arg1(this, arg_1);
1178 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1179 }
1180
1181 void MacroAssembler::call_VM_base(Register oop_result,
1182 Register last_java_sp,
1183 address entry_point,
1184 int number_of_arguments,
1185 bool check_exceptions) {
1186 Register java_thread = r15_thread;
1187
1188 // determine last_java_sp register
1189 if (!last_java_sp->is_valid()) {
1190 last_java_sp = rsp;
1191 }
1192 // debugging support
1193 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1194 #ifdef ASSERT
1195 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1196 // r12 is the heapbase.
1197 if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
1198 #endif // ASSERT
1199
1200 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1201 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1202
1203 // push java thread (becomes first argument of C function)
1204
1205 mov(c_rarg0, r15_thread);
1206
1207 // set last Java frame before call
1208 assert(last_java_sp != rbp, "can't use ebp/rbp");
1209
1210 // Only interpreter should have to set fp
1211 set_last_Java_frame(last_java_sp, rbp, nullptr, rscratch1);
1212
1213 // do the call, remove parameters
1214 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1215
1216 #ifdef ASSERT
1217 // Check that thread register is not clobbered.
1218 guarantee(java_thread != rax, "change this code");
1219 push(rax);
1220 { Label L;
1221 get_thread_slow(rax);
1222 cmpptr(java_thread, rax);
1223 jcc(Assembler::equal, L);
1224 STOP("MacroAssembler::call_VM_base: java_thread not callee saved?");
1225 bind(L);
1226 }
1227 pop(rax);
1228 #endif
1229
1230 // reset last Java frame
1231 // Only interpreter should have to clear fp
1232 reset_last_Java_frame(true);
1233
1234 // C++ interp handles this in the interpreter
1235 check_and_handle_popframe();
1236 check_and_handle_earlyret();
1237
1238 if (check_exceptions) {
1239 // check for pending exceptions (java_thread is set upon return)
1240 cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
1241 // This used to conditionally jump to forward_exception however it is
1242 // possible if we relocate that the branch will not reach. So we must jump
1243 // around so we can always reach
1244
1245 Label ok;
1246 jcc(Assembler::equal, ok);
1247 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1248 bind(ok);
1249 }
1250
1251 // get oop result if there is one and reset the value in the thread
1252 if (oop_result->is_valid()) {
1253 get_vm_result_oop(oop_result);
1254 }
1255 }
1256
1257 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1258 // Calculate the value for last_Java_sp somewhat subtle.
1259 // call_VM does an intermediate call which places a return address on
1260 // the stack just under the stack pointer as the user finished with it.
1261 // This allows use to retrieve last_Java_pc from last_Java_sp[-1].
1262
1263 // We've pushed one address, correct last_Java_sp
1264 lea(rax, Address(rsp, wordSize));
1265
1266 call_VM_base(oop_result, rax, entry_point, number_of_arguments, check_exceptions);
1267 }
1268
1269 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1270 void MacroAssembler::call_VM_leaf0(address entry_point) {
1271 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1272 }
1273
1274 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1275 call_VM_leaf_base(entry_point, number_of_arguments);
1276 }
1277
1278 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1279 pass_arg0(this, arg_0);
1280 call_VM_leaf(entry_point, 1);
1281 }
1282
1283 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1284
1285 assert_different_registers(arg_0, c_rarg1);
1286 pass_arg1(this, arg_1);
1287 pass_arg0(this, arg_0);
1288 call_VM_leaf(entry_point, 2);
1289 }
1290
1291 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1292 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1293 assert_different_registers(arg_1, c_rarg2);
1294 pass_arg2(this, arg_2);
1295 pass_arg1(this, arg_1);
1296 pass_arg0(this, arg_0);
1297 call_VM_leaf(entry_point, 3);
1298 }
1299
1300 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1301 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1302 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1303 assert_different_registers(arg_2, c_rarg3);
1304 pass_arg3(this, arg_3);
1305 pass_arg2(this, arg_2);
1306 pass_arg1(this, arg_1);
1307 pass_arg0(this, arg_0);
1308 call_VM_leaf(entry_point, 3);
1309 }
1310
1311 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1312 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1313 }
1314
1315 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1316 pass_arg0(this, arg_0);
1317 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1318 }
1319
1320 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1321 assert_different_registers(arg_0, c_rarg1);
1322 pass_arg1(this, arg_1);
1323 pass_arg0(this, arg_0);
1324 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1325 }
1326
1327 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1328 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1329 assert_different_registers(arg_1, c_rarg2);
1330 pass_arg2(this, arg_2);
1331 pass_arg1(this, arg_1);
1332 pass_arg0(this, arg_0);
1333 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1334 }
1335
1336 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1337 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1338 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1339 assert_different_registers(arg_2, c_rarg3);
1340 pass_arg3(this, arg_3);
1341 pass_arg2(this, arg_2);
1342 pass_arg1(this, arg_1);
1343 pass_arg0(this, arg_0);
1344 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1345 }
1346
1347 void MacroAssembler::get_vm_result_oop(Register oop_result) {
1348 movptr(oop_result, Address(r15_thread, JavaThread::vm_result_oop_offset()));
1349 movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
1350 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1351 }
1352
1353 void MacroAssembler::get_vm_result_metadata(Register metadata_result) {
1354 movptr(metadata_result, Address(r15_thread, JavaThread::vm_result_metadata_offset()));
1355 movptr(Address(r15_thread, JavaThread::vm_result_metadata_offset()), NULL_WORD);
1356 }
1357
1358 void MacroAssembler::check_and_handle_earlyret() {
1359 }
1360
1361 void MacroAssembler::check_and_handle_popframe() {
1362 }
1363
1364 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1365 assert(rscratch != noreg || always_reachable(src1), "missing");
1366
1367 if (reachable(src1)) {
1368 cmpl(as_Address(src1), imm);
1369 } else {
1370 lea(rscratch, src1);
1371 cmpl(Address(rscratch, 0), imm);
1372 }
1373 }
1374
1375 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1376 assert(!src2.is_lval(), "use cmpptr");
1377 assert(rscratch != noreg || always_reachable(src2), "missing");
1378
1379 if (reachable(src2)) {
1380 cmpl(src1, as_Address(src2));
1381 } else {
1382 lea(rscratch, src2);
1383 cmpl(src1, Address(rscratch, 0));
1384 }
1385 }
1386
1387 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1388 Assembler::cmpl(src1, imm);
1389 }
1390
1391 void MacroAssembler::cmp32(Register src1, Address src2) {
1392 Assembler::cmpl(src1, src2);
1393 }
1394
1395 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1396 ucomisd(opr1, opr2);
1397
1398 Label L;
1399 if (unordered_is_less) {
1400 movl(dst, -1);
1401 jcc(Assembler::parity, L);
1402 jcc(Assembler::below , L);
1403 movl(dst, 0);
1404 jcc(Assembler::equal , L);
1405 increment(dst);
1406 } else { // unordered is greater
1407 movl(dst, 1);
1408 jcc(Assembler::parity, L);
1409 jcc(Assembler::above , L);
1410 movl(dst, 0);
1411 jcc(Assembler::equal , L);
1412 decrementl(dst);
1413 }
1414 bind(L);
1415 }
1416
1417 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1418 ucomiss(opr1, opr2);
1419
1420 Label L;
1421 if (unordered_is_less) {
1422 movl(dst, -1);
1423 jcc(Assembler::parity, L);
1424 jcc(Assembler::below , L);
1425 movl(dst, 0);
1426 jcc(Assembler::equal , L);
1427 increment(dst);
1428 } else { // unordered is greater
1429 movl(dst, 1);
1430 jcc(Assembler::parity, L);
1431 jcc(Assembler::above , L);
1432 movl(dst, 0);
1433 jcc(Assembler::equal , L);
1434 decrementl(dst);
1435 }
1436 bind(L);
1437 }
1438
1439
1440 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1441 assert(rscratch != noreg || always_reachable(src1), "missing");
1442
1443 if (reachable(src1)) {
1444 cmpb(as_Address(src1), imm);
1445 } else {
1446 lea(rscratch, src1);
1447 cmpb(Address(rscratch, 0), imm);
1448 }
1449 }
1450
1451 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1452 assert(rscratch != noreg || always_reachable(src2), "missing");
1453
1454 if (src2.is_lval()) {
1455 movptr(rscratch, src2);
1456 Assembler::cmpq(src1, rscratch);
1457 } else if (reachable(src2)) {
1458 cmpq(src1, as_Address(src2));
1459 } else {
1460 lea(rscratch, src2);
1461 Assembler::cmpq(src1, Address(rscratch, 0));
1462 }
1463 }
1464
1465 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1466 assert(src2.is_lval(), "not a mem-mem compare");
1467 // moves src2's literal address
1468 movptr(rscratch, src2);
1469 Assembler::cmpq(src1, rscratch);
1470 }
1471
1472 void MacroAssembler::cmpoop(Register src1, Register src2) {
1473 cmpptr(src1, src2);
1474 }
1475
1476 void MacroAssembler::cmpoop(Register src1, Address src2) {
1477 cmpptr(src1, src2);
1478 }
1479
1480 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1481 movoop(rscratch, src2);
1482 cmpptr(src1, rscratch);
1483 }
1484
1485 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1486 assert(rscratch != noreg || always_reachable(adr), "missing");
1487
1488 if (reachable(adr)) {
1489 lock();
1490 cmpxchgptr(reg, as_Address(adr));
1491 } else {
1492 lea(rscratch, adr);
1493 lock();
1494 cmpxchgptr(reg, Address(rscratch, 0));
1495 }
1496 }
1497
1498 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1499 cmpxchgq(reg, adr);
1500 }
1501
1502 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1503 assert(rscratch != noreg || always_reachable(src), "missing");
1504
1505 if (reachable(src)) {
1506 Assembler::comisd(dst, as_Address(src));
1507 } else {
1508 lea(rscratch, src);
1509 Assembler::comisd(dst, Address(rscratch, 0));
1510 }
1511 }
1512
1513 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1514 assert(rscratch != noreg || always_reachable(src), "missing");
1515
1516 if (reachable(src)) {
1517 Assembler::comiss(dst, as_Address(src));
1518 } else {
1519 lea(rscratch, src);
1520 Assembler::comiss(dst, Address(rscratch, 0));
1521 }
1522 }
1523
1524
1525 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1526 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1527
1528 Condition negated_cond = negate_condition(cond);
1529 Label L;
1530 jcc(negated_cond, L);
1531 pushf(); // Preserve flags
1532 atomic_incl(counter_addr, rscratch);
1533 popf();
1534 bind(L);
1535 }
1536
1537 int MacroAssembler::corrected_idivl(Register reg) {
1538 // Full implementation of Java idiv and irem; checks for
1539 // special case as described in JVM spec., p.243 & p.271.
1540 // The function returns the (pc) offset of the idivl
1541 // instruction - may be needed for implicit exceptions.
1542 //
1543 // normal case special case
1544 //
1545 // input : rax,: dividend min_int
1546 // reg: divisor (may not be rax,/rdx) -1
1547 //
1548 // output: rax,: quotient (= rax, idiv reg) min_int
1549 // rdx: remainder (= rax, irem reg) 0
1550 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1551 const int min_int = 0x80000000;
1552 Label normal_case, special_case;
1553
1554 // check for special case
1555 cmpl(rax, min_int);
1556 jcc(Assembler::notEqual, normal_case);
1557 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1558 cmpl(reg, -1);
1559 jcc(Assembler::equal, special_case);
1560
1561 // handle normal case
1562 bind(normal_case);
1563 cdql();
1564 int idivl_offset = offset();
1565 idivl(reg);
1566
1567 // normal and special case exit
1568 bind(special_case);
1569
1570 return idivl_offset;
1571 }
1572
1573
1574
1575 void MacroAssembler::decrementl(Register reg, int value) {
1576 if (value == min_jint) {subl(reg, value) ; return; }
1577 if (value < 0) { incrementl(reg, -value); return; }
1578 if (value == 0) { ; return; }
1579 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1580 /* else */ { subl(reg, value) ; return; }
1581 }
1582
1583 void MacroAssembler::decrementl(Address dst, int value) {
1584 if (value == min_jint) {subl(dst, value) ; return; }
1585 if (value < 0) { incrementl(dst, -value); return; }
1586 if (value == 0) { ; return; }
1587 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1588 /* else */ { subl(dst, value) ; return; }
1589 }
1590
1591 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1592 assert(shift_value > 0, "illegal shift value");
1593 Label _is_positive;
1594 testl (reg, reg);
1595 jcc (Assembler::positive, _is_positive);
1596 int offset = (1 << shift_value) - 1 ;
1597
1598 if (offset == 1) {
1599 incrementl(reg);
1600 } else {
1601 addl(reg, offset);
1602 }
1603
1604 bind (_is_positive);
1605 sarl(reg, shift_value);
1606 }
1607
1608 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1609 assert(rscratch != noreg || always_reachable(src), "missing");
1610
1611 if (reachable(src)) {
1612 Assembler::divsd(dst, as_Address(src));
1613 } else {
1614 lea(rscratch, src);
1615 Assembler::divsd(dst, Address(rscratch, 0));
1616 }
1617 }
1618
1619 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1620 assert(rscratch != noreg || always_reachable(src), "missing");
1621
1622 if (reachable(src)) {
1623 Assembler::divss(dst, as_Address(src));
1624 } else {
1625 lea(rscratch, src);
1626 Assembler::divss(dst, Address(rscratch, 0));
1627 }
1628 }
1629
1630 void MacroAssembler::enter() {
1631 push(rbp);
1632 mov(rbp, rsp);
1633 }
1634
1635 void MacroAssembler::post_call_nop() {
1636 if (!Continuations::enabled()) {
1637 return;
1638 }
1639 InstructionMark im(this);
1640 relocate(post_call_nop_Relocation::spec());
1641 InlineSkippedInstructionsCounter skipCounter(this);
1642 emit_int8((uint8_t)0x0f);
1643 emit_int8((uint8_t)0x1f);
1644 emit_int8((uint8_t)0x84);
1645 emit_int8((uint8_t)0x00);
1646 emit_int32(0x00);
1647 }
1648
1649 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1650 assert(rscratch != noreg || always_reachable(src), "missing");
1651 if (reachable(src)) {
1652 Assembler::mulpd(dst, as_Address(src));
1653 } else {
1654 lea(rscratch, src);
1655 Assembler::mulpd(dst, Address(rscratch, 0));
1656 }
1657 }
1658
1659 // dst = c = a * b + c
1660 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1661 Assembler::vfmadd231sd(c, a, b);
1662 if (dst != c) {
1663 movdbl(dst, c);
1664 }
1665 }
1666
1667 // dst = c = a * b + c
1668 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1669 Assembler::vfmadd231ss(c, a, b);
1670 if (dst != c) {
1671 movflt(dst, c);
1672 }
1673 }
1674
1675 // dst = c = a * b + c
1676 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1677 Assembler::vfmadd231pd(c, a, b, vector_len);
1678 if (dst != c) {
1679 vmovdqu(dst, c);
1680 }
1681 }
1682
1683 // dst = c = a * b + c
1684 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1685 Assembler::vfmadd231ps(c, a, b, vector_len);
1686 if (dst != c) {
1687 vmovdqu(dst, c);
1688 }
1689 }
1690
1691 // dst = c = a * b + c
1692 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1693 Assembler::vfmadd231pd(c, a, b, vector_len);
1694 if (dst != c) {
1695 vmovdqu(dst, c);
1696 }
1697 }
1698
1699 // dst = c = a * b + c
1700 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1701 Assembler::vfmadd231ps(c, a, b, vector_len);
1702 if (dst != c) {
1703 vmovdqu(dst, c);
1704 }
1705 }
1706
1707 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
1708 assert(rscratch != noreg || always_reachable(dst), "missing");
1709
1710 if (reachable(dst)) {
1711 incrementl(as_Address(dst));
1712 } else {
1713 lea(rscratch, dst);
1714 incrementl(Address(rscratch, 0));
1715 }
1716 }
1717
1718 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
1719 incrementl(as_Address(dst, rscratch));
1720 }
1721
1722 void MacroAssembler::incrementl(Register reg, int value) {
1723 if (value == min_jint) {addl(reg, value) ; return; }
1724 if (value < 0) { decrementl(reg, -value); return; }
1725 if (value == 0) { ; return; }
1726 if (value == 1 && UseIncDec) { incl(reg) ; return; }
1727 /* else */ { addl(reg, value) ; return; }
1728 }
1729
1730 void MacroAssembler::incrementl(Address dst, int value) {
1731 if (value == min_jint) {addl(dst, value) ; return; }
1732 if (value < 0) { decrementl(dst, -value); return; }
1733 if (value == 0) { ; return; }
1734 if (value == 1 && UseIncDec) { incl(dst) ; return; }
1735 /* else */ { addl(dst, value) ; return; }
1736 }
1737
1738 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
1739 assert(rscratch != noreg || always_reachable(dst), "missing");
1740 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
1741 if (reachable(dst)) {
1742 jmp_literal(dst.target(), dst.rspec());
1743 } else {
1744 lea(rscratch, dst);
1745 jmp(rscratch);
1746 }
1747 }
1748
1749 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
1750 assert(rscratch != noreg || always_reachable(dst), "missing");
1751 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
1752 if (reachable(dst)) {
1753 InstructionMark im(this);
1754 relocate(dst.reloc());
1755 const int short_size = 2;
1756 const int long_size = 6;
1757 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
1758 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
1759 // 0111 tttn #8-bit disp
1760 emit_int8(0x70 | cc);
1761 emit_int8((offs - short_size) & 0xFF);
1762 } else {
1763 // 0000 1111 1000 tttn #32-bit disp
1764 emit_int8(0x0F);
1765 emit_int8((unsigned char)(0x80 | cc));
1766 emit_int32(offs - long_size);
1767 }
1768 } else {
1769 #ifdef ASSERT
1770 warning("reversing conditional branch");
1771 #endif /* ASSERT */
1772 Label skip;
1773 jccb(reverse[cc], skip);
1774 lea(rscratch, dst);
1775 Assembler::jmp(rscratch);
1776 bind(skip);
1777 }
1778 }
1779
1780 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
1781 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
1782 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
1783
1784 stmxcsr(mxcsr_save);
1785 movl(tmp, mxcsr_save);
1786 if (EnableX86ECoreOpts) {
1787 // The mxcsr_std has status bits set for performance on ECore
1788 orl(tmp, 0x003f);
1789 } else {
1790 // Mask out status bits (only check control and mask bits)
1791 andl(tmp, 0xFFC0);
1792 }
1793 cmp32(tmp, mxcsr_std, rscratch);
1794 }
1795
1796 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
1797 assert(rscratch != noreg || always_reachable(src), "missing");
1798
1799 if (reachable(src)) {
1800 Assembler::ldmxcsr(as_Address(src));
1801 } else {
1802 lea(rscratch, src);
1803 Assembler::ldmxcsr(Address(rscratch, 0));
1804 }
1805 }
1806
1807 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1808 int off = offset();
1809 movsbl(dst, src); // movsxb
1810 return off;
1811 }
1812
1813 // Note: load_signed_short used to be called load_signed_word.
1814 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
1815 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
1816 // The term "word" in HotSpot means a 32- or 64-bit machine word.
1817 int MacroAssembler::load_signed_short(Register dst, Address src) {
1818 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
1819 // version but this is what 64bit has always done. This seems to imply
1820 // that users are only using 32bits worth.
1821 int off = offset();
1822 movswl(dst, src); // movsxw
1823 return off;
1824 }
1825
1826 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1827 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1828 // and "3.9 Partial Register Penalties", p. 22).
1829 int off = offset();
1830 movzbl(dst, src); // movzxb
1831 return off;
1832 }
1833
1834 // Note: load_unsigned_short used to be called load_unsigned_word.
1835 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1836 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1837 // and "3.9 Partial Register Penalties", p. 22).
1838 int off = offset();
1839 movzwl(dst, src); // movzxw
1840 return off;
1841 }
1842
1843 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1844 switch (size_in_bytes) {
1845 case 8: movq(dst, src); break;
1846 case 4: movl(dst, src); break;
1847 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1848 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1849 default: ShouldNotReachHere();
1850 }
1851 }
1852
1853 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1854 switch (size_in_bytes) {
1855 case 8: movq(dst, src); break;
1856 case 4: movl(dst, src); break;
1857 case 2: movw(dst, src); break;
1858 case 1: movb(dst, src); break;
1859 default: ShouldNotReachHere();
1860 }
1861 }
1862
1863 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
1864 assert(rscratch != noreg || always_reachable(dst), "missing");
1865
1866 if (reachable(dst)) {
1867 movl(as_Address(dst), src);
1868 } else {
1869 lea(rscratch, dst);
1870 movl(Address(rscratch, 0), src);
1871 }
1872 }
1873
1874 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
1875 if (reachable(src)) {
1876 movl(dst, as_Address(src));
1877 } else {
1878 lea(dst, src);
1879 movl(dst, Address(dst, 0));
1880 }
1881 }
1882
1883 // C++ bool manipulation
1884
1885 void MacroAssembler::movbool(Register dst, Address src) {
1886 if(sizeof(bool) == 1)
1887 movb(dst, src);
1888 else if(sizeof(bool) == 2)
1889 movw(dst, src);
1890 else if(sizeof(bool) == 4)
1891 movl(dst, src);
1892 else
1893 // unsupported
1894 ShouldNotReachHere();
1895 }
1896
1897 void MacroAssembler::movbool(Address dst, bool boolconst) {
1898 if(sizeof(bool) == 1)
1899 movb(dst, (int) boolconst);
1900 else if(sizeof(bool) == 2)
1901 movw(dst, (int) boolconst);
1902 else if(sizeof(bool) == 4)
1903 movl(dst, (int) boolconst);
1904 else
1905 // unsupported
1906 ShouldNotReachHere();
1907 }
1908
1909 void MacroAssembler::movbool(Address dst, Register src) {
1910 if(sizeof(bool) == 1)
1911 movb(dst, src);
1912 else if(sizeof(bool) == 2)
1913 movw(dst, src);
1914 else if(sizeof(bool) == 4)
1915 movl(dst, src);
1916 else
1917 // unsupported
1918 ShouldNotReachHere();
1919 }
1920
1921 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1922 assert(rscratch != noreg || always_reachable(src), "missing");
1923
1924 if (reachable(src)) {
1925 movdl(dst, as_Address(src));
1926 } else {
1927 lea(rscratch, src);
1928 movdl(dst, Address(rscratch, 0));
1929 }
1930 }
1931
1932 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
1933 assert(rscratch != noreg || always_reachable(src), "missing");
1934
1935 if (reachable(src)) {
1936 movq(dst, as_Address(src));
1937 } else {
1938 lea(rscratch, src);
1939 movq(dst, Address(rscratch, 0));
1940 }
1941 }
1942
1943 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1944 assert(rscratch != noreg || always_reachable(src), "missing");
1945
1946 if (reachable(src)) {
1947 if (UseXmmLoadAndClearUpper) {
1948 movsd (dst, as_Address(src));
1949 } else {
1950 movlpd(dst, as_Address(src));
1951 }
1952 } else {
1953 lea(rscratch, src);
1954 if (UseXmmLoadAndClearUpper) {
1955 movsd (dst, Address(rscratch, 0));
1956 } else {
1957 movlpd(dst, Address(rscratch, 0));
1958 }
1959 }
1960 }
1961
1962 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
1963 assert(rscratch != noreg || always_reachable(src), "missing");
1964
1965 if (reachable(src)) {
1966 movss(dst, as_Address(src));
1967 } else {
1968 lea(rscratch, src);
1969 movss(dst, Address(rscratch, 0));
1970 }
1971 }
1972
1973 void MacroAssembler::movhlf(XMMRegister dst, XMMRegister src, Register rscratch) {
1974 if (VM_Version::supports_avx10_2()) {
1975 evmovw(dst, src);
1976 } else {
1977 assert(rscratch != noreg, "missing");
1978 evmovw(rscratch, src);
1979 evmovw(dst, rscratch);
1980 }
1981 }
1982
1983 void MacroAssembler::mov64(Register dst, int64_t imm64) {
1984 if (is_uimm32(imm64)) {
1985 movl(dst, checked_cast<uint32_t>(imm64));
1986 } else if (is_simm32(imm64)) {
1987 movq(dst, checked_cast<int32_t>(imm64));
1988 } else {
1989 Assembler::mov64(dst, imm64);
1990 }
1991 }
1992
1993 void MacroAssembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) {
1994 Assembler::mov64(dst, imm64, rtype, format);
1995 }
1996
1997 void MacroAssembler::movptr(Register dst, Register src) {
1998 movq(dst, src);
1999 }
2000
2001 void MacroAssembler::movptr(Register dst, Address src) {
2002 movq(dst, src);
2003 }
2004
2005 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2006 void MacroAssembler::movptr(Register dst, intptr_t src) {
2007 mov64(dst, src);
2008 }
2009
2010 void MacroAssembler::movptr(Address dst, Register src) {
2011 movq(dst, src);
2012 }
2013
2014 void MacroAssembler::movptr(Address dst, int32_t src) {
2015 movslq(dst, src);
2016 }
2017
2018 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2019 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2020 Assembler::movdqu(dst, src);
2021 }
2022
2023 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2024 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2025 Assembler::movdqu(dst, src);
2026 }
2027
2028 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2029 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2030 Assembler::movdqu(dst, src);
2031 }
2032
2033 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2034 assert(rscratch != noreg || always_reachable(src), "missing");
2035
2036 if (reachable(src)) {
2037 movdqu(dst, as_Address(src));
2038 } else {
2039 lea(rscratch, src);
2040 movdqu(dst, Address(rscratch, 0));
2041 }
2042 }
2043
2044 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2045 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2046 Assembler::vmovdqu(dst, src);
2047 }
2048
2049 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2050 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2051 Assembler::vmovdqu(dst, src);
2052 }
2053
2054 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2055 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2056 Assembler::vmovdqu(dst, src);
2057 }
2058
2059 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2060 assert(rscratch != noreg || always_reachable(src), "missing");
2061
2062 if (reachable(src)) {
2063 vmovdqu(dst, as_Address(src));
2064 }
2065 else {
2066 lea(rscratch, src);
2067 vmovdqu(dst, Address(rscratch, 0));
2068 }
2069 }
2070
2071 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2072 assert(rscratch != noreg || always_reachable(src), "missing");
2073
2074 if (vector_len == AVX_512bit) {
2075 evmovdquq(dst, src, AVX_512bit, rscratch);
2076 } else if (vector_len == AVX_256bit) {
2077 vmovdqu(dst, src, rscratch);
2078 } else {
2079 movdqu(dst, src, rscratch);
2080 }
2081 }
2082
2083 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2084 if (vector_len == AVX_512bit) {
2085 evmovdquq(dst, src, AVX_512bit);
2086 } else if (vector_len == AVX_256bit) {
2087 vmovdqu(dst, src);
2088 } else {
2089 movdqu(dst, src);
2090 }
2091 }
2092
2093 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2094 if (vector_len == AVX_512bit) {
2095 evmovdquq(dst, src, AVX_512bit);
2096 } else if (vector_len == AVX_256bit) {
2097 vmovdqu(dst, src);
2098 } else {
2099 movdqu(dst, src);
2100 }
2101 }
2102
2103 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2104 if (vector_len == AVX_512bit) {
2105 evmovdquq(dst, src, AVX_512bit);
2106 } else if (vector_len == AVX_256bit) {
2107 vmovdqu(dst, src);
2108 } else {
2109 movdqu(dst, src);
2110 }
2111 }
2112
2113 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2114 assert(rscratch != noreg || always_reachable(src), "missing");
2115
2116 if (reachable(src)) {
2117 vmovdqa(dst, as_Address(src));
2118 }
2119 else {
2120 lea(rscratch, src);
2121 vmovdqa(dst, Address(rscratch, 0));
2122 }
2123 }
2124
2125 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2126 assert(rscratch != noreg || always_reachable(src), "missing");
2127
2128 if (vector_len == AVX_512bit) {
2129 evmovdqaq(dst, src, AVX_512bit, rscratch);
2130 } else if (vector_len == AVX_256bit) {
2131 vmovdqa(dst, src, rscratch);
2132 } else {
2133 movdqa(dst, src, rscratch);
2134 }
2135 }
2136
2137 void MacroAssembler::kmov(KRegister dst, Address src) {
2138 if (VM_Version::supports_avx512bw()) {
2139 kmovql(dst, src);
2140 } else {
2141 assert(VM_Version::supports_evex(), "");
2142 kmovwl(dst, src);
2143 }
2144 }
2145
2146 void MacroAssembler::kmov(Address dst, KRegister src) {
2147 if (VM_Version::supports_avx512bw()) {
2148 kmovql(dst, src);
2149 } else {
2150 assert(VM_Version::supports_evex(), "");
2151 kmovwl(dst, src);
2152 }
2153 }
2154
2155 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2156 if (VM_Version::supports_avx512bw()) {
2157 kmovql(dst, src);
2158 } else {
2159 assert(VM_Version::supports_evex(), "");
2160 kmovwl(dst, src);
2161 }
2162 }
2163
2164 void MacroAssembler::kmov(Register dst, KRegister src) {
2165 if (VM_Version::supports_avx512bw()) {
2166 kmovql(dst, src);
2167 } else {
2168 assert(VM_Version::supports_evex(), "");
2169 kmovwl(dst, src);
2170 }
2171 }
2172
2173 void MacroAssembler::kmov(KRegister dst, Register src) {
2174 if (VM_Version::supports_avx512bw()) {
2175 kmovql(dst, src);
2176 } else {
2177 assert(VM_Version::supports_evex(), "");
2178 kmovwl(dst, src);
2179 }
2180 }
2181
2182 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2183 assert(rscratch != noreg || always_reachable(src), "missing");
2184
2185 if (reachable(src)) {
2186 kmovql(dst, as_Address(src));
2187 } else {
2188 lea(rscratch, src);
2189 kmovql(dst, Address(rscratch, 0));
2190 }
2191 }
2192
2193 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2194 assert(rscratch != noreg || always_reachable(src), "missing");
2195
2196 if (reachable(src)) {
2197 kmovwl(dst, as_Address(src));
2198 } else {
2199 lea(rscratch, src);
2200 kmovwl(dst, Address(rscratch, 0));
2201 }
2202 }
2203
2204 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2205 int vector_len, Register rscratch) {
2206 assert(rscratch != noreg || always_reachable(src), "missing");
2207
2208 if (reachable(src)) {
2209 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2210 } else {
2211 lea(rscratch, src);
2212 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2213 }
2214 }
2215
2216 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2217 int vector_len, Register rscratch) {
2218 assert(rscratch != noreg || always_reachable(src), "missing");
2219
2220 if (reachable(src)) {
2221 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2222 } else {
2223 lea(rscratch, src);
2224 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2225 }
2226 }
2227
2228 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2229 assert(rscratch != noreg || always_reachable(src), "missing");
2230
2231 if (reachable(src)) {
2232 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2233 } else {
2234 lea(rscratch, src);
2235 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2236 }
2237 }
2238
2239 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2240 assert(rscratch != noreg || always_reachable(src), "missing");
2241
2242 if (reachable(src)) {
2243 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2244 } else {
2245 lea(rscratch, src);
2246 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2247 }
2248 }
2249
2250 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2251 assert(rscratch != noreg || always_reachable(src), "missing");
2252
2253 if (reachable(src)) {
2254 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2255 } else {
2256 lea(rscratch, src);
2257 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2258 }
2259 }
2260
2261 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2262 assert(rscratch != noreg || always_reachable(src), "missing");
2263
2264 if (reachable(src)) {
2265 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2266 } else {
2267 lea(rscratch, src);
2268 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2269 }
2270 }
2271
2272 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2273 assert(rscratch != noreg || always_reachable(src), "missing");
2274
2275 if (reachable(src)) {
2276 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2277 } else {
2278 lea(rscratch, src);
2279 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2280 }
2281 }
2282
2283 void MacroAssembler::movapd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2284 assert(rscratch != noreg || always_reachable(src), "missing");
2285
2286 if (reachable(src)) {
2287 Assembler::movapd(dst, as_Address(src));
2288 } else {
2289 lea(rscratch, src);
2290 Assembler::movapd(dst, Address(rscratch, 0));
2291 }
2292 }
2293
2294 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2295 assert(rscratch != noreg || always_reachable(src), "missing");
2296
2297 if (reachable(src)) {
2298 Assembler::movdqa(dst, as_Address(src));
2299 } else {
2300 lea(rscratch, src);
2301 Assembler::movdqa(dst, Address(rscratch, 0));
2302 }
2303 }
2304
2305 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2306 assert(rscratch != noreg || always_reachable(src), "missing");
2307
2308 if (reachable(src)) {
2309 Assembler::movsd(dst, as_Address(src));
2310 } else {
2311 lea(rscratch, src);
2312 Assembler::movsd(dst, Address(rscratch, 0));
2313 }
2314 }
2315
2316 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2317 assert(rscratch != noreg || always_reachable(src), "missing");
2318
2319 if (reachable(src)) {
2320 Assembler::movss(dst, as_Address(src));
2321 } else {
2322 lea(rscratch, src);
2323 Assembler::movss(dst, Address(rscratch, 0));
2324 }
2325 }
2326
2327 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2328 assert(rscratch != noreg || always_reachable(src), "missing");
2329
2330 if (reachable(src)) {
2331 Assembler::movddup(dst, as_Address(src));
2332 } else {
2333 lea(rscratch, src);
2334 Assembler::movddup(dst, Address(rscratch, 0));
2335 }
2336 }
2337
2338 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2339 assert(rscratch != noreg || always_reachable(src), "missing");
2340
2341 if (reachable(src)) {
2342 Assembler::vmovddup(dst, as_Address(src), vector_len);
2343 } else {
2344 lea(rscratch, src);
2345 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2346 }
2347 }
2348
2349 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2350 assert(rscratch != noreg || always_reachable(src), "missing");
2351
2352 if (reachable(src)) {
2353 Assembler::mulsd(dst, as_Address(src));
2354 } else {
2355 lea(rscratch, src);
2356 Assembler::mulsd(dst, Address(rscratch, 0));
2357 }
2358 }
2359
2360 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2361 assert(rscratch != noreg || always_reachable(src), "missing");
2362
2363 if (reachable(src)) {
2364 Assembler::mulss(dst, as_Address(src));
2365 } else {
2366 lea(rscratch, src);
2367 Assembler::mulss(dst, Address(rscratch, 0));
2368 }
2369 }
2370
2371 void MacroAssembler::null_check(Register reg, int offset) {
2372 if (needs_explicit_null_check(offset)) {
2373 // provoke OS null exception if reg is null by
2374 // accessing M[reg] w/o changing any (non-CC) registers
2375 // NOTE: cmpl is plenty here to provoke a segv
2376 cmpptr(rax, Address(reg, 0));
2377 // Note: should probably use testl(rax, Address(reg, 0));
2378 // may be shorter code (however, this version of
2379 // testl needs to be implemented first)
2380 } else {
2381 // nothing to do, (later) access of M[reg + offset]
2382 // will provoke OS null exception if reg is null
2383 }
2384 }
2385
2386 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2387 andptr(markword, markWord::inline_type_mask_in_place);
2388 cmpptr(markword, markWord::inline_type_pattern);
2389 jcc(Assembler::equal, is_inline_type);
2390 }
2391
2392 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null) {
2393 if (can_be_null) {
2394 testptr(object, object);
2395 jcc(Assembler::zero, not_inline_type);
2396 }
2397 const int is_inline_type_mask = markWord::inline_type_pattern;
2398 movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2399 andptr(tmp, is_inline_type_mask);
2400 cmpptr(tmp, is_inline_type_mask);
2401 jcc(Assembler::notEqual, not_inline_type);
2402 }
2403
2404 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2405 movl(temp_reg, flags);
2406 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2407 jcc(Assembler::notEqual, is_null_free_inline_type);
2408 }
2409
2410 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2411 movl(temp_reg, flags);
2412 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2413 jcc(Assembler::equal, not_null_free_inline_type);
2414 }
2415
2416 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2417 movl(temp_reg, flags);
2418 testl(temp_reg, 1 << ResolvedFieldEntry::is_flat_shift);
2419 jcc(Assembler::notEqual, is_flat);
2420 }
2421
2422 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2423 movl(temp_reg, flags);
2424 testl(temp_reg, 1 << ResolvedFieldEntry::has_null_marker_shift);
2425 jcc(Assembler::notEqual, has_null_marker);
2426 }
2427
2428 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2429 Label test_mark_word;
2430 // load mark word
2431 movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2432 // check displaced
2433 testl(temp_reg, markWord::unlocked_value);
2434 jccb(Assembler::notZero, test_mark_word);
2435 // slow path use klass prototype
2436 push(rscratch1);
2437 load_prototype_header(temp_reg, oop, rscratch1);
2438 pop(rscratch1);
2439
2440 bind(test_mark_word);
2441 testl(temp_reg, test_bit);
2442 jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
2443 }
2444
2445 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg,
2446 Label& is_flat_array) {
2447 #ifdef _LP64
2448 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2449 #else
2450 load_klass(temp_reg, oop, noreg);
2451 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
2452 test_flat_array_layout(temp_reg, is_flat_array);
2453 #endif
2454 }
2455
2456 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2457 Label& is_non_flat_array) {
2458 #ifdef _LP64
2459 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2460 #else
2461 load_klass(temp_reg, oop, noreg);
2462 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
2463 test_non_flat_array_layout(temp_reg, is_non_flat_array);
2464 #endif
2465 }
2466
2467 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
2468 #ifdef _LP64
2469 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2470 #else
2471 Unimplemented();
2472 #endif
2473 }
2474
2475 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2476 #ifdef _LP64
2477 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2478 #else
2479 Unimplemented();
2480 #endif
2481 }
2482
2483 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2484 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2485 jcc(Assembler::notZero, is_flat_array);
2486 }
2487
2488 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
2489 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2490 jcc(Assembler::zero, is_non_flat_array);
2491 }
2492
2493 void MacroAssembler::os_breakpoint() {
2494 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2495 // (e.g., MSVC can't call ps() otherwise)
2496 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2497 }
2498
2499 void MacroAssembler::unimplemented(const char* what) {
2500 const char* buf = nullptr;
2501 {
2502 ResourceMark rm;
2503 stringStream ss;
2504 ss.print("unimplemented: %s", what);
2505 buf = code_string(ss.as_string());
2506 }
2507 stop(buf);
2508 }
2509
2510 #define XSTATE_BV 0x200
2511
2512 void MacroAssembler::pop_CPU_state() {
2513 pop_FPU_state();
2514 pop_IU_state();
2515 }
2516
2517 void MacroAssembler::pop_FPU_state() {
2518 fxrstor(Address(rsp, 0));
2519 addptr(rsp, FPUStateSizeInWords * wordSize);
2520 }
2521
2522 void MacroAssembler::pop_IU_state() {
2523 popa();
2524 addq(rsp, 8);
2525 popf();
2526 }
2527
2528 // Save Integer and Float state
2529 // Warning: Stack must be 16 byte aligned (64bit)
2530 void MacroAssembler::push_CPU_state() {
2531 push_IU_state();
2532 push_FPU_state();
2533 }
2534
2535 void MacroAssembler::push_FPU_state() {
2536 subptr(rsp, FPUStateSizeInWords * wordSize);
2537 fxsave(Address(rsp, 0));
2538 }
2539
2540 void MacroAssembler::push_IU_state() {
2541 // Push flags first because pusha kills them
2542 pushf();
2543 // Make sure rsp stays 16-byte aligned
2544 subq(rsp, 8);
2545 pusha();
2546 }
2547
2548 void MacroAssembler::push_cont_fastpath() {
2549 if (!Continuations::enabled()) return;
2550
2551 Label L_done;
2552 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2553 jccb(Assembler::belowEqual, L_done);
2554 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), rsp);
2555 bind(L_done);
2556 }
2557
2558 void MacroAssembler::pop_cont_fastpath() {
2559 if (!Continuations::enabled()) return;
2560
2561 Label L_done;
2562 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2563 jccb(Assembler::below, L_done);
2564 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), 0);
2565 bind(L_done);
2566 }
2567
2568 #ifdef ASSERT
2569 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2570 Label no_cont;
2571 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2572 testl(cont, cont);
2573 jcc(Assembler::zero, no_cont);
2574 stop(name);
2575 bind(no_cont);
2576 }
2577 #endif
2578
2579 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { // determine java_thread register
2580 // we must set sp to zero to clear frame
2581 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2582 // must clear fp, so that compiled frames are not confused; it is
2583 // possible that we need it only for debugging
2584 if (clear_fp) {
2585 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2586 }
2587 // Always clear the pc because it could have been set by make_walkable()
2588 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2589 vzeroupper();
2590 }
2591
2592 void MacroAssembler::round_to(Register reg, int modulus) {
2593 addptr(reg, modulus - 1);
2594 andptr(reg, -modulus);
2595 }
2596
2597 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod) {
2598 if (at_return) {
2599 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2600 // we may safely use rsp instead to perform the stack watermark check.
2601 cmpptr(in_nmethod ? rsp : rbp, Address(r15_thread, JavaThread::polling_word_offset()));
2602 jcc(Assembler::above, slow_path);
2603 return;
2604 }
2605 testb(Address(r15_thread, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2606 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2607 }
2608
2609 // Calls to C land
2610 //
2611 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2612 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2613 // has to be reset to 0. This is required to allow proper stack traversal.
2614 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2615 Register last_java_fp,
2616 address last_java_pc,
2617 Register rscratch) {
2618 vzeroupper();
2619 // determine last_java_sp register
2620 if (!last_java_sp->is_valid()) {
2621 last_java_sp = rsp;
2622 }
2623 // last_java_fp is optional
2624 if (last_java_fp->is_valid()) {
2625 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2626 }
2627 // last_java_pc is optional
2628 if (last_java_pc != nullptr) {
2629 Address java_pc(r15_thread,
2630 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
2631 lea(java_pc, InternalAddress(last_java_pc), rscratch);
2632 }
2633 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2634 }
2635
2636 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2637 Register last_java_fp,
2638 Label &L,
2639 Register scratch) {
2640 lea(scratch, L);
2641 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
2642 set_last_Java_frame(last_java_sp, last_java_fp, nullptr, scratch);
2643 }
2644
2645 void MacroAssembler::shlptr(Register dst, int imm8) {
2646 shlq(dst, imm8);
2647 }
2648
2649 void MacroAssembler::shrptr(Register dst, int imm8) {
2650 shrq(dst, imm8);
2651 }
2652
2653 void MacroAssembler::sign_extend_byte(Register reg) {
2654 movsbl(reg, reg); // movsxb
2655 }
2656
2657 void MacroAssembler::sign_extend_short(Register reg) {
2658 movswl(reg, reg); // movsxw
2659 }
2660
2661 void MacroAssembler::testl(Address dst, int32_t imm32) {
2662 if (imm32 >= 0 && is8bit(imm32)) {
2663 testb(dst, imm32);
2664 } else {
2665 Assembler::testl(dst, imm32);
2666 }
2667 }
2668
2669 void MacroAssembler::testl(Register dst, int32_t imm32) {
2670 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
2671 testb(dst, imm32);
2672 } else {
2673 Assembler::testl(dst, imm32);
2674 }
2675 }
2676
2677 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2678 assert(always_reachable(src), "Address should be reachable");
2679 testl(dst, as_Address(src));
2680 }
2681
2682 void MacroAssembler::testq(Address dst, int32_t imm32) {
2683 if (imm32 >= 0) {
2684 testl(dst, imm32);
2685 } else {
2686 Assembler::testq(dst, imm32);
2687 }
2688 }
2689
2690 void MacroAssembler::testq(Register dst, int32_t imm32) {
2691 if (imm32 >= 0) {
2692 testl(dst, imm32);
2693 } else {
2694 Assembler::testq(dst, imm32);
2695 }
2696 }
2697
2698 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2699 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2700 Assembler::pcmpeqb(dst, src);
2701 }
2702
2703 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2704 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2705 Assembler::pcmpeqw(dst, src);
2706 }
2707
2708 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2709 assert((dst->encoding() < 16),"XMM register should be 0-15");
2710 Assembler::pcmpestri(dst, src, imm8);
2711 }
2712
2713 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2714 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2715 Assembler::pcmpestri(dst, src, imm8);
2716 }
2717
2718 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2719 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2720 Assembler::pmovzxbw(dst, src);
2721 }
2722
2723 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2724 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2725 Assembler::pmovzxbw(dst, src);
2726 }
2727
2728 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2729 assert((src->encoding() < 16),"XMM register should be 0-15");
2730 Assembler::pmovmskb(dst, src);
2731 }
2732
2733 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2734 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2735 Assembler::ptest(dst, src);
2736 }
2737
2738 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2739 assert(rscratch != noreg || always_reachable(src), "missing");
2740
2741 if (reachable(src)) {
2742 Assembler::sqrtss(dst, as_Address(src));
2743 } else {
2744 lea(rscratch, src);
2745 Assembler::sqrtss(dst, Address(rscratch, 0));
2746 }
2747 }
2748
2749 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2750 assert(rscratch != noreg || always_reachable(src), "missing");
2751
2752 if (reachable(src)) {
2753 Assembler::subsd(dst, as_Address(src));
2754 } else {
2755 lea(rscratch, src);
2756 Assembler::subsd(dst, Address(rscratch, 0));
2757 }
2758 }
2759
2760 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
2761 assert(rscratch != noreg || always_reachable(src), "missing");
2762
2763 if (reachable(src)) {
2764 Assembler::roundsd(dst, as_Address(src), rmode);
2765 } else {
2766 lea(rscratch, src);
2767 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
2768 }
2769 }
2770
2771 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2772 assert(rscratch != noreg || always_reachable(src), "missing");
2773
2774 if (reachable(src)) {
2775 Assembler::subss(dst, as_Address(src));
2776 } else {
2777 lea(rscratch, src);
2778 Assembler::subss(dst, Address(rscratch, 0));
2779 }
2780 }
2781
2782 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2783 assert(rscratch != noreg || always_reachable(src), "missing");
2784
2785 if (reachable(src)) {
2786 Assembler::ucomisd(dst, as_Address(src));
2787 } else {
2788 lea(rscratch, src);
2789 Assembler::ucomisd(dst, Address(rscratch, 0));
2790 }
2791 }
2792
2793 void MacroAssembler::evucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2794 assert(rscratch != noreg || always_reachable(src), "missing");
2795
2796 if (reachable(src)) {
2797 Assembler::evucomxsd(dst, as_Address(src));
2798 } else {
2799 lea(rscratch, src);
2800 Assembler::evucomxsd(dst, Address(rscratch, 0));
2801 }
2802 }
2803
2804 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2805 assert(rscratch != noreg || always_reachable(src), "missing");
2806
2807 if (reachable(src)) {
2808 Assembler::ucomiss(dst, as_Address(src));
2809 } else {
2810 lea(rscratch, src);
2811 Assembler::ucomiss(dst, Address(rscratch, 0));
2812 }
2813 }
2814
2815 void MacroAssembler::evucomxss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2816 assert(rscratch != noreg || always_reachable(src), "missing");
2817
2818 if (reachable(src)) {
2819 Assembler::evucomxss(dst, as_Address(src));
2820 } else {
2821 lea(rscratch, src);
2822 Assembler::evucomxss(dst, Address(rscratch, 0));
2823 }
2824 }
2825
2826 void MacroAssembler::evucomish(XMMRegister dst, AddressLiteral src, Register rscratch) {
2827 assert(rscratch != noreg || always_reachable(src), "missing");
2828
2829 if (reachable(src)) {
2830 Assembler::evucomish(dst, as_Address(src));
2831 } else {
2832 lea(rscratch, src);
2833 Assembler::evucomish(dst, Address(rscratch, 0));
2834 }
2835 }
2836
2837 void MacroAssembler::evucomxsh(XMMRegister dst, AddressLiteral src, Register rscratch) {
2838 assert(rscratch != noreg || always_reachable(src), "missing");
2839
2840 if (reachable(src)) {
2841 Assembler::evucomxsh(dst, as_Address(src));
2842 } else {
2843 lea(rscratch, src);
2844 Assembler::evucomxsh(dst, Address(rscratch, 0));
2845 }
2846 }
2847
2848 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2849 assert(rscratch != noreg || always_reachable(src), "missing");
2850
2851 // Used in sign-bit flipping with aligned address.
2852 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2853
2854 if (UseAVX > 2 &&
2855 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2856 (dst->encoding() >= 16)) {
2857 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2858 } else if (reachable(src)) {
2859 Assembler::xorpd(dst, as_Address(src));
2860 } else {
2861 lea(rscratch, src);
2862 Assembler::xorpd(dst, Address(rscratch, 0));
2863 }
2864 }
2865
2866 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
2867 if (UseAVX > 2 &&
2868 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2869 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2870 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2871 } else {
2872 Assembler::xorpd(dst, src);
2873 }
2874 }
2875
2876 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
2877 if (UseAVX > 2 &&
2878 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2879 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2880 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2881 } else {
2882 Assembler::xorps(dst, src);
2883 }
2884 }
2885
2886 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
2887 assert(rscratch != noreg || always_reachable(src), "missing");
2888
2889 // Used in sign-bit flipping with aligned address.
2890 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2891
2892 if (UseAVX > 2 &&
2893 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2894 (dst->encoding() >= 16)) {
2895 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2896 } else if (reachable(src)) {
2897 Assembler::xorps(dst, as_Address(src));
2898 } else {
2899 lea(rscratch, src);
2900 Assembler::xorps(dst, Address(rscratch, 0));
2901 }
2902 }
2903
2904 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
2905 assert(rscratch != noreg || always_reachable(src), "missing");
2906
2907 // Used in sign-bit flipping with aligned address.
2908 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
2909 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2910 if (reachable(src)) {
2911 Assembler::pshufb(dst, as_Address(src));
2912 } else {
2913 lea(rscratch, src);
2914 Assembler::pshufb(dst, Address(rscratch, 0));
2915 }
2916 }
2917
2918 // AVX 3-operands instructions
2919
2920 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2921 assert(rscratch != noreg || always_reachable(src), "missing");
2922
2923 if (reachable(src)) {
2924 vaddsd(dst, nds, as_Address(src));
2925 } else {
2926 lea(rscratch, src);
2927 vaddsd(dst, nds, Address(rscratch, 0));
2928 }
2929 }
2930
2931 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2932 assert(rscratch != noreg || always_reachable(src), "missing");
2933
2934 if (reachable(src)) {
2935 vaddss(dst, nds, as_Address(src));
2936 } else {
2937 lea(rscratch, src);
2938 vaddss(dst, nds, Address(rscratch, 0));
2939 }
2940 }
2941
2942 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2943 assert(UseAVX > 0, "requires some form of AVX");
2944 assert(rscratch != noreg || always_reachable(src), "missing");
2945
2946 if (reachable(src)) {
2947 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
2948 } else {
2949 lea(rscratch, src);
2950 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
2951 }
2952 }
2953
2954 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2955 assert(UseAVX > 0, "requires some form of AVX");
2956 assert(rscratch != noreg || always_reachable(src), "missing");
2957
2958 if (reachable(src)) {
2959 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
2960 } else {
2961 lea(rscratch, src);
2962 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
2963 }
2964 }
2965
2966 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2967 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2968 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2969
2970 vandps(dst, nds, negate_field, vector_len, rscratch);
2971 }
2972
2973 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2974 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2975 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2976
2977 vandpd(dst, nds, negate_field, vector_len, rscratch);
2978 }
2979
2980 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2981 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2982 Assembler::vpaddb(dst, nds, src, vector_len);
2983 }
2984
2985 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2986 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2987 Assembler::vpaddb(dst, nds, src, vector_len);
2988 }
2989
2990 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2991 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2992 Assembler::vpaddw(dst, nds, src, vector_len);
2993 }
2994
2995 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2996 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2997 Assembler::vpaddw(dst, nds, src, vector_len);
2998 }
2999
3000 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3001 assert(rscratch != noreg || always_reachable(src), "missing");
3002
3003 if (reachable(src)) {
3004 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3005 } else {
3006 lea(rscratch, src);
3007 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3008 }
3009 }
3010
3011 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3012 assert(rscratch != noreg || always_reachable(src), "missing");
3013
3014 if (reachable(src)) {
3015 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3016 } else {
3017 lea(rscratch, src);
3018 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3019 }
3020 }
3021
3022 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3023 assert(rscratch != noreg || always_reachable(src), "missing");
3024
3025 if (reachable(src)) {
3026 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3027 } else {
3028 lea(rscratch, src);
3029 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3030 }
3031 }
3032
3033 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3034 assert(rscratch != noreg || always_reachable(src), "missing");
3035
3036 if (reachable(src)) {
3037 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3038 } else {
3039 lea(rscratch, src);
3040 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3041 }
3042 }
3043
3044 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3045 assert(rscratch != noreg || always_reachable(src), "missing");
3046
3047 if (reachable(src)) {
3048 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3049 } else {
3050 lea(rscratch, src);
3051 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3052 }
3053 }
3054
3055 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3056 assert(rscratch != noreg || always_reachable(src), "missing");
3057
3058 if (reachable(src)) {
3059 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3060 } else {
3061 lea(rscratch, src);
3062 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3063 }
3064 }
3065
3066 // Vector float blend
3067 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3068 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3069 // WARN: Allow dst == (src1|src2), mask == scratch
3070 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3071 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3072 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3073 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3074 if (blend_emulation && scratch_available && dst_available) {
3075 if (compute_mask) {
3076 vpsrad(scratch, mask, 32, vector_len);
3077 mask = scratch;
3078 }
3079 if (dst == src1) {
3080 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3081 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3082 } else {
3083 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3084 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3085 }
3086 vpor(dst, dst, scratch, vector_len);
3087 } else {
3088 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3089 }
3090 }
3091
3092 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3093 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3094 // WARN: Allow dst == (src1|src2), mask == scratch
3095 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3096 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3097 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3098 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3099 if (blend_emulation && scratch_available && dst_available) {
3100 if (compute_mask) {
3101 vpxor(scratch, scratch, scratch, vector_len);
3102 vpcmpgtq(scratch, scratch, mask, vector_len);
3103 mask = scratch;
3104 }
3105 if (dst == src1) {
3106 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3107 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3108 } else {
3109 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3110 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3111 }
3112 vpor(dst, dst, scratch, vector_len);
3113 } else {
3114 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3115 }
3116 }
3117
3118 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3119 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3120 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3121 }
3122
3123 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3124 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3125 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3126 }
3127
3128 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3129 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3130 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3131 }
3132
3133 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3134 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3135 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3136 }
3137
3138 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3139 assert(rscratch != noreg || always_reachable(src), "missing");
3140
3141 if (reachable(src)) {
3142 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3143 } else {
3144 lea(rscratch, src);
3145 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3146 }
3147 }
3148
3149 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3150 int comparison, bool is_signed, int vector_len, Register rscratch) {
3151 assert(rscratch != noreg || always_reachable(src), "missing");
3152
3153 if (reachable(src)) {
3154 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3155 } else {
3156 lea(rscratch, src);
3157 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3158 }
3159 }
3160
3161 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3162 int comparison, bool is_signed, int vector_len, Register rscratch) {
3163 assert(rscratch != noreg || always_reachable(src), "missing");
3164
3165 if (reachable(src)) {
3166 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3167 } else {
3168 lea(rscratch, src);
3169 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3170 }
3171 }
3172
3173 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3174 int comparison, bool is_signed, int vector_len, Register rscratch) {
3175 assert(rscratch != noreg || always_reachable(src), "missing");
3176
3177 if (reachable(src)) {
3178 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3179 } else {
3180 lea(rscratch, src);
3181 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3182 }
3183 }
3184
3185 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3186 int comparison, bool is_signed, int vector_len, Register rscratch) {
3187 assert(rscratch != noreg || always_reachable(src), "missing");
3188
3189 if (reachable(src)) {
3190 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3191 } else {
3192 lea(rscratch, src);
3193 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3194 }
3195 }
3196
3197 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3198 if (width == Assembler::Q) {
3199 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3200 } else {
3201 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3202 }
3203 }
3204
3205 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3206 int eq_cond_enc = 0x29;
3207 int gt_cond_enc = 0x37;
3208 if (width != Assembler::Q) {
3209 eq_cond_enc = 0x74 + width;
3210 gt_cond_enc = 0x64 + width;
3211 }
3212 switch (cond) {
3213 case eq:
3214 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3215 break;
3216 case neq:
3217 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3218 vallones(xtmp, vector_len);
3219 vpxor(dst, xtmp, dst, vector_len);
3220 break;
3221 case le:
3222 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3223 vallones(xtmp, vector_len);
3224 vpxor(dst, xtmp, dst, vector_len);
3225 break;
3226 case nlt:
3227 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3228 vallones(xtmp, vector_len);
3229 vpxor(dst, xtmp, dst, vector_len);
3230 break;
3231 case lt:
3232 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3233 break;
3234 case nle:
3235 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3236 break;
3237 default:
3238 assert(false, "Should not reach here");
3239 }
3240 }
3241
3242 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3243 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3244 Assembler::vpmovzxbw(dst, src, vector_len);
3245 }
3246
3247 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3248 assert((src->encoding() < 16),"XMM register should be 0-15");
3249 Assembler::vpmovmskb(dst, src, vector_len);
3250 }
3251
3252 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3253 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3254 Assembler::vpmullw(dst, nds, src, vector_len);
3255 }
3256
3257 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3258 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3259 Assembler::vpmullw(dst, nds, src, vector_len);
3260 }
3261
3262 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3263 assert((UseAVX > 0), "AVX support is needed");
3264 assert(rscratch != noreg || always_reachable(src), "missing");
3265
3266 if (reachable(src)) {
3267 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3268 } else {
3269 lea(rscratch, src);
3270 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3271 }
3272 }
3273
3274 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3275 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3276 Assembler::vpsubb(dst, nds, src, vector_len);
3277 }
3278
3279 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3280 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3281 Assembler::vpsubb(dst, nds, src, vector_len);
3282 }
3283
3284 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3285 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3286 Assembler::vpsubw(dst, nds, src, vector_len);
3287 }
3288
3289 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3290 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3291 Assembler::vpsubw(dst, nds, src, vector_len);
3292 }
3293
3294 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3295 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3296 Assembler::vpsraw(dst, nds, shift, vector_len);
3297 }
3298
3299 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3300 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3301 Assembler::vpsraw(dst, nds, shift, vector_len);
3302 }
3303
3304 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3305 assert(UseAVX > 2,"");
3306 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3307 vector_len = 2;
3308 }
3309 Assembler::evpsraq(dst, nds, shift, vector_len);
3310 }
3311
3312 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3313 assert(UseAVX > 2,"");
3314 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3315 vector_len = 2;
3316 }
3317 Assembler::evpsraq(dst, nds, shift, vector_len);
3318 }
3319
3320 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3321 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3322 Assembler::vpsrlw(dst, nds, shift, vector_len);
3323 }
3324
3325 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3326 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3327 Assembler::vpsrlw(dst, nds, shift, vector_len);
3328 }
3329
3330 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3331 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3332 Assembler::vpsllw(dst, nds, shift, vector_len);
3333 }
3334
3335 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3336 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3337 Assembler::vpsllw(dst, nds, shift, vector_len);
3338 }
3339
3340 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3341 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3342 Assembler::vptest(dst, src);
3343 }
3344
3345 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3346 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3347 Assembler::punpcklbw(dst, src);
3348 }
3349
3350 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3351 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3352 Assembler::pshufd(dst, src, mode);
3353 }
3354
3355 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3356 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3357 Assembler::pshuflw(dst, src, mode);
3358 }
3359
3360 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3361 assert(rscratch != noreg || always_reachable(src), "missing");
3362
3363 if (reachable(src)) {
3364 vandpd(dst, nds, as_Address(src), vector_len);
3365 } else {
3366 lea(rscratch, src);
3367 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3368 }
3369 }
3370
3371 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3372 assert(rscratch != noreg || always_reachable(src), "missing");
3373
3374 if (reachable(src)) {
3375 vandps(dst, nds, as_Address(src), vector_len);
3376 } else {
3377 lea(rscratch, src);
3378 vandps(dst, nds, Address(rscratch, 0), vector_len);
3379 }
3380 }
3381
3382 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3383 bool merge, int vector_len, Register rscratch) {
3384 assert(rscratch != noreg || always_reachable(src), "missing");
3385
3386 if (reachable(src)) {
3387 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3388 } else {
3389 lea(rscratch, src);
3390 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3391 }
3392 }
3393
3394 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3395 assert(rscratch != noreg || always_reachable(src), "missing");
3396
3397 if (reachable(src)) {
3398 vdivsd(dst, nds, as_Address(src));
3399 } else {
3400 lea(rscratch, src);
3401 vdivsd(dst, nds, Address(rscratch, 0));
3402 }
3403 }
3404
3405 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3406 assert(rscratch != noreg || always_reachable(src), "missing");
3407
3408 if (reachable(src)) {
3409 vdivss(dst, nds, as_Address(src));
3410 } else {
3411 lea(rscratch, src);
3412 vdivss(dst, nds, Address(rscratch, 0));
3413 }
3414 }
3415
3416 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3417 assert(rscratch != noreg || always_reachable(src), "missing");
3418
3419 if (reachable(src)) {
3420 vmulsd(dst, nds, as_Address(src));
3421 } else {
3422 lea(rscratch, src);
3423 vmulsd(dst, nds, Address(rscratch, 0));
3424 }
3425 }
3426
3427 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3428 assert(rscratch != noreg || always_reachable(src), "missing");
3429
3430 if (reachable(src)) {
3431 vmulss(dst, nds, as_Address(src));
3432 } else {
3433 lea(rscratch, src);
3434 vmulss(dst, nds, Address(rscratch, 0));
3435 }
3436 }
3437
3438 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3439 assert(rscratch != noreg || always_reachable(src), "missing");
3440
3441 if (reachable(src)) {
3442 vsubsd(dst, nds, as_Address(src));
3443 } else {
3444 lea(rscratch, src);
3445 vsubsd(dst, nds, Address(rscratch, 0));
3446 }
3447 }
3448
3449 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3450 assert(rscratch != noreg || always_reachable(src), "missing");
3451
3452 if (reachable(src)) {
3453 vsubss(dst, nds, as_Address(src));
3454 } else {
3455 lea(rscratch, src);
3456 vsubss(dst, nds, Address(rscratch, 0));
3457 }
3458 }
3459
3460 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3461 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3462 assert(rscratch != noreg || always_reachable(src), "missing");
3463
3464 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3465 }
3466
3467 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3468 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3469 assert(rscratch != noreg || always_reachable(src), "missing");
3470
3471 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3472 }
3473
3474 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3475 assert(rscratch != noreg || always_reachable(src), "missing");
3476
3477 if (reachable(src)) {
3478 vxorpd(dst, nds, as_Address(src), vector_len);
3479 } else {
3480 lea(rscratch, src);
3481 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3482 }
3483 }
3484
3485 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3486 assert(rscratch != noreg || always_reachable(src), "missing");
3487
3488 if (reachable(src)) {
3489 vxorps(dst, nds, as_Address(src), vector_len);
3490 } else {
3491 lea(rscratch, src);
3492 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3493 }
3494 }
3495
3496 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3497 assert(rscratch != noreg || always_reachable(src), "missing");
3498
3499 if (UseAVX > 1 || (vector_len < 1)) {
3500 if (reachable(src)) {
3501 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3502 } else {
3503 lea(rscratch, src);
3504 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3505 }
3506 } else {
3507 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3508 }
3509 }
3510
3511 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3512 assert(rscratch != noreg || always_reachable(src), "missing");
3513
3514 if (reachable(src)) {
3515 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3516 } else {
3517 lea(rscratch, src);
3518 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3519 }
3520 }
3521
3522 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3523 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3524 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3525 // The inverted mask is sign-extended
3526 andptr(possibly_non_local, inverted_mask);
3527 }
3528
3529 void MacroAssembler::resolve_jobject(Register value,
3530 Register tmp) {
3531 Register thread = r15_thread;
3532 assert_different_registers(value, thread, tmp);
3533 Label done, tagged, weak_tagged;
3534 testptr(value, value);
3535 jcc(Assembler::zero, done); // Use null as-is.
3536 testptr(value, JNIHandles::tag_mask); // Test for tag.
3537 jcc(Assembler::notZero, tagged);
3538
3539 // Resolve local handle
3540 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp);
3541 verify_oop(value);
3542 jmp(done);
3543
3544 bind(tagged);
3545 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3546 jcc(Assembler::notZero, weak_tagged);
3547
3548 // Resolve global handle
3549 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3550 verify_oop(value);
3551 jmp(done);
3552
3553 bind(weak_tagged);
3554 // Resolve jweak.
3555 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3556 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp);
3557 verify_oop(value);
3558
3559 bind(done);
3560 }
3561
3562 void MacroAssembler::resolve_global_jobject(Register value,
3563 Register tmp) {
3564 Register thread = r15_thread;
3565 assert_different_registers(value, thread, tmp);
3566 Label done;
3567
3568 testptr(value, value);
3569 jcc(Assembler::zero, done); // Use null as-is.
3570
3571 #ifdef ASSERT
3572 {
3573 Label valid_global_tag;
3574 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
3575 jcc(Assembler::notZero, valid_global_tag);
3576 stop("non global jobject using resolve_global_jobject");
3577 bind(valid_global_tag);
3578 }
3579 #endif
3580
3581 // Resolve global handle
3582 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3583 verify_oop(value);
3584
3585 bind(done);
3586 }
3587
3588 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3589 subq(dst, imm32);
3590 }
3591
3592 // Force generation of a 4 byte immediate value even if it fits into 8bit
3593 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3594 subq_imm32(dst, imm32);
3595 }
3596
3597 void MacroAssembler::subptr(Register dst, Register src) {
3598 subq(dst, src);
3599 }
3600
3601 // C++ bool manipulation
3602 void MacroAssembler::testbool(Register dst) {
3603 if(sizeof(bool) == 1)
3604 testb(dst, 0xff);
3605 else if(sizeof(bool) == 2) {
3606 // testw implementation needed for two byte bools
3607 ShouldNotReachHere();
3608 } else if(sizeof(bool) == 4)
3609 testl(dst, dst);
3610 else
3611 // unsupported
3612 ShouldNotReachHere();
3613 }
3614
3615 void MacroAssembler::testptr(Register dst, Register src) {
3616 testq(dst, src);
3617 }
3618
3619 // Object / value buffer allocation...
3620 //
3621 // Kills klass and rsi on LP64
3622 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
3623 Register t1, Register t2,
3624 bool clear_fields, Label& alloc_failed)
3625 {
3626 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
3627 Register layout_size = t1;
3628 assert(new_obj == rax, "needs to be rax");
3629 assert_different_registers(klass, new_obj, t1, t2);
3630
3631 // get instance_size in InstanceKlass (scaled to a count of bytes)
3632 movl(layout_size, Address(klass, Klass::layout_helper_offset()));
3633 // test to see if it is malformed in some way
3634 testl(layout_size, Klass::_lh_instance_slow_path_bit);
3635 jcc(Assembler::notZero, slow_case_no_pop);
3636
3637 // Allocate the instance:
3638 // If TLAB is enabled:
3639 // Try to allocate in the TLAB.
3640 // If fails, go to the slow path.
3641 // Else If inline contiguous allocations are enabled:
3642 // Try to allocate in eden.
3643 // If fails due to heap end, go to slow path.
3644 //
3645 // If TLAB is enabled OR inline contiguous is enabled:
3646 // Initialize the allocation.
3647 // Exit.
3648 //
3649 // Go to slow path.
3650
3651 push(klass);
3652 if (UseTLAB) {
3653 tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case);
3654 if (ZeroTLAB || (!clear_fields)) {
3655 // the fields have been already cleared
3656 jmp(initialize_header);
3657 } else {
3658 // initialize both the header and fields
3659 jmp(initialize_object);
3660 }
3661 } else {
3662 jmp(slow_case);
3663 }
3664
3665 // If UseTLAB is true, the object is created above and there is an initialize need.
3666 // Otherwise, skip and go to the slow path.
3667 if (UseTLAB) {
3668 if (clear_fields) {
3669 // The object is initialized before the header. If the object size is
3670 // zero, go directly to the header initialization.
3671 bind(initialize_object);
3672 if (UseCompactObjectHeaders) {
3673 assert(is_aligned(oopDesc::base_offset_in_bytes(), BytesPerLong), "oop base offset must be 8-byte-aligned");
3674 decrement(layout_size, oopDesc::base_offset_in_bytes());
3675 } else {
3676 decrement(layout_size, sizeof(oopDesc));
3677 }
3678 jcc(Assembler::zero, initialize_header);
3679
3680 // Initialize topmost object field, divide size by 8, check if odd and
3681 // test if zero.
3682 Register zero = klass;
3683 xorl(zero, zero); // use zero reg to clear memory (shorter code)
3684 shrl(layout_size, LogBytesPerLong); // divide by 2*oopSize and set carry flag if odd
3685
3686 #ifdef ASSERT
3687 // make sure instance_size was multiple of 8
3688 Label L;
3689 // Ignore partial flag stall after shrl() since it is debug VM
3690 jcc(Assembler::carryClear, L);
3691 stop("object size is not multiple of 2 - adjust this code");
3692 bind(L);
3693 // must be > 0, no extra check needed here
3694 #endif
3695
3696 // initialize remaining object fields: instance_size was a multiple of 8
3697 {
3698 Label loop;
3699 bind(loop);
3700 int header_size_bytes = oopDesc::header_size() * HeapWordSize;
3701 assert(is_aligned(header_size_bytes, BytesPerLong), "oop header size must be 8-byte-aligned");
3702 movptr(Address(new_obj, layout_size, Address::times_8, header_size_bytes - 1*oopSize), zero);
3703 decrement(layout_size);
3704 jcc(Assembler::notZero, loop);
3705 }
3706 } // clear_fields
3707
3708 // initialize object header only.
3709 bind(initialize_header);
3710 if (UseCompactObjectHeaders || Arguments::is_valhalla_enabled()) {
3711 pop(klass);
3712 Register mark_word = t2;
3713 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
3714 movptr(Address(new_obj, oopDesc::mark_offset_in_bytes ()), mark_word);
3715 } else {
3716 movptr(Address(new_obj, oopDesc::mark_offset_in_bytes()),
3717 (intptr_t)markWord::prototype().value()); // header
3718 pop(klass); // get saved klass back in the register.
3719 }
3720 if (!UseCompactObjectHeaders) {
3721 xorl(rsi, rsi); // use zero reg to clear memory (shorter code)
3722 store_klass_gap(new_obj, rsi); // zero klass gap for compressed oops
3723 movptr(t2, klass); // preserve klass
3724 store_klass(new_obj, t2, rscratch1); // src klass reg is potentially compressed
3725 }
3726 jmp(done);
3727 }
3728
3729 bind(slow_case);
3730 pop(klass);
3731 bind(slow_case_no_pop);
3732 jmp(alloc_failed);
3733
3734 bind(done);
3735 }
3736
3737 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3738 void MacroAssembler::tlab_allocate(Register obj,
3739 Register var_size_in_bytes,
3740 int con_size_in_bytes,
3741 Register t1,
3742 Register t2,
3743 Label& slow_case) {
3744 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3745 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3746 }
3747
3748 RegSet MacroAssembler::call_clobbered_gp_registers() {
3749 RegSet regs;
3750 regs += RegSet::of(rax, rcx, rdx);
3751 #ifndef _WINDOWS
3752 regs += RegSet::of(rsi, rdi);
3753 #endif
3754 regs += RegSet::range(r8, r11);
3755 if (UseAPX) {
3756 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
3757 }
3758 return regs;
3759 }
3760
3761 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3762 int num_xmm_registers = XMMRegister::available_xmm_registers();
3763 #if defined(_WINDOWS)
3764 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3765 if (num_xmm_registers > 16) {
3766 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3767 }
3768 return result;
3769 #else
3770 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3771 #endif
3772 }
3773
3774 // C1 only ever uses the first double/float of the XMM register.
3775 static int xmm_save_size() { return sizeof(double); }
3776
3777 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3778 masm->movdbl(Address(rsp, offset), reg);
3779 }
3780
3781 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3782 masm->movdbl(reg, Address(rsp, offset));
3783 }
3784
3785 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
3786 bool save_fpu, int& gp_area_size, int& xmm_area_size) {
3787
3788 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
3789 StackAlignmentInBytes);
3790 xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
3791
3792 return gp_area_size + xmm_area_size;
3793 }
3794
3795 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3796 block_comment("push_call_clobbered_registers start");
3797 // Regular registers
3798 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3799
3800 int gp_area_size;
3801 int xmm_area_size;
3802 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3803 gp_area_size, xmm_area_size);
3804 subptr(rsp, total_save_size);
3805
3806 push_set(gp_registers_to_push, 0);
3807
3808 if (save_fpu) {
3809 push_set(call_clobbered_xmm_registers(), gp_area_size);
3810 }
3811
3812 block_comment("push_call_clobbered_registers end");
3813 }
3814
3815 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3816 block_comment("pop_call_clobbered_registers start");
3817
3818 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3819
3820 int gp_area_size;
3821 int xmm_area_size;
3822 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3823 gp_area_size, xmm_area_size);
3824
3825 if (restore_fpu) {
3826 pop_set(call_clobbered_xmm_registers(), gp_area_size);
3827 }
3828
3829 pop_set(gp_registers_to_pop, 0);
3830
3831 addptr(rsp, total_save_size);
3832
3833 vzeroupper();
3834
3835 block_comment("pop_call_clobbered_registers end");
3836 }
3837
3838 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3839 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3840 int spill_offset = offset;
3841
3842 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3843 save_xmm_register(this, spill_offset, *it);
3844 spill_offset += xmm_save_size();
3845 }
3846 }
3847
3848 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3849 int restore_size = set.size() * xmm_save_size();
3850 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3851
3852 int restore_offset = offset + restore_size - xmm_save_size();
3853
3854 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3855 restore_xmm_register(this, restore_offset, *it);
3856 restore_offset -= xmm_save_size();
3857 }
3858 }
3859
3860 void MacroAssembler::push_set(RegSet set, int offset) {
3861 int spill_offset;
3862 if (offset == -1) {
3863 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3864 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3865 subptr(rsp, aligned_size);
3866 spill_offset = 0;
3867 } else {
3868 spill_offset = offset;
3869 }
3870
3871 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3872 movptr(Address(rsp, spill_offset), *it);
3873 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3874 }
3875 }
3876
3877 void MacroAssembler::pop_set(RegSet set, int offset) {
3878
3879 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3880 int restore_size = set.size() * gp_reg_size;
3881 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3882
3883 int restore_offset;
3884 if (offset == -1) {
3885 restore_offset = restore_size - gp_reg_size;
3886 } else {
3887 restore_offset = offset + restore_size - gp_reg_size;
3888 }
3889 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3890 movptr(*it, Address(rsp, restore_offset));
3891 restore_offset -= gp_reg_size;
3892 }
3893
3894 if (offset == -1) {
3895 addptr(rsp, aligned_size);
3896 }
3897 }
3898
3899 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3900 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3901 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3902 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3903 Label done;
3904
3905 testptr(length_in_bytes, length_in_bytes);
3906 jcc(Assembler::zero, done);
3907
3908 // initialize topmost word, divide index by 2, check if odd and test if zero
3909 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3910 #ifdef ASSERT
3911 {
3912 Label L;
3913 testptr(length_in_bytes, BytesPerWord - 1);
3914 jcc(Assembler::zero, L);
3915 stop("length must be a multiple of BytesPerWord");
3916 bind(L);
3917 }
3918 #endif
3919 Register index = length_in_bytes;
3920 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3921 if (UseIncDec) {
3922 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3923 } else {
3924 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3925 shrptr(index, 1);
3926 }
3927
3928 // initialize remaining object fields: index is a multiple of 2 now
3929 {
3930 Label loop;
3931 bind(loop);
3932 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3933 decrement(index);
3934 jcc(Assembler::notZero, loop);
3935 }
3936
3937 bind(done);
3938 }
3939
3940 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
3941 movptr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
3942 #ifdef ASSERT
3943 {
3944 Label done;
3945 cmpptr(layout_info, 0);
3946 jcc(Assembler::notEqual, done);
3947 stop("inline_layout_info_array is null");
3948 bind(done);
3949 }
3950 #endif
3951
3952 InlineLayoutInfo array[2];
3953 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
3954 if (is_power_of_2(size)) {
3955 shll(index, log2i_exact(size)); // Scale index by power of 2
3956 } else {
3957 imull(index, index, size); // Scale the index to be the entry index * array_element_size
3958 }
3959 lea(layout_info, Address(layout_info, index, Address::times_1, Array<InlineLayoutInfo>::base_offset_in_bytes()));
3960 }
3961
3962 // Look up the method for a megamorphic invokeinterface call.
3963 // The target method is determined by <intf_klass, itable_index>.
3964 // The receiver klass is in recv_klass.
3965 // On success, the result will be in method_result, and execution falls through.
3966 // On failure, execution transfers to the given label.
3967 void MacroAssembler::lookup_interface_method(Register recv_klass,
3968 Register intf_klass,
3969 RegisterOrConstant itable_index,
3970 Register method_result,
3971 Register scan_temp,
3972 Label& L_no_such_interface,
3973 bool return_method) {
3974 assert_different_registers(recv_klass, intf_klass, scan_temp);
3975 assert_different_registers(method_result, intf_klass, scan_temp);
3976 assert(recv_klass != method_result || !return_method,
3977 "recv_klass can be destroyed when method isn't needed");
3978
3979 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3980 "caller must use same register for non-constant itable index as for method");
3981
3982 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3983 int vtable_base = in_bytes(Klass::vtable_start_offset());
3984 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3985 int scan_step = itableOffsetEntry::size() * wordSize;
3986 int vte_size = vtableEntry::size_in_bytes();
3987 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3988 assert(vte_size == wordSize, "else adjust times_vte_scale");
3989
3990 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3991
3992 // Could store the aligned, prescaled offset in the klass.
3993 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3994
3995 if (return_method) {
3996 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3997 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3998 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3999 }
4000
4001 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
4002 // if (scan->interface() == intf) {
4003 // result = (klass + scan->offset() + itable_index);
4004 // }
4005 // }
4006 Label search, found_method;
4007
4008 for (int peel = 1; peel >= 0; peel--) {
4009 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
4010 cmpptr(intf_klass, method_result);
4011
4012 if (peel) {
4013 jccb(Assembler::equal, found_method);
4014 } else {
4015 jccb(Assembler::notEqual, search);
4016 // (invert the test to fall through to found_method...)
4017 }
4018
4019 if (!peel) break;
4020
4021 bind(search);
4022
4023 // Check that the previous entry is non-null. A null entry means that
4024 // the receiver class doesn't implement the interface, and wasn't the
4025 // same as when the caller was compiled.
4026 testptr(method_result, method_result);
4027 jcc(Assembler::zero, L_no_such_interface);
4028 addptr(scan_temp, scan_step);
4029 }
4030
4031 bind(found_method);
4032
4033 if (return_method) {
4034 // Got a hit.
4035 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4036 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4037 }
4038 }
4039
4040 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4041 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4042 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4043 // The target method is determined by <holder_klass, itable_index>.
4044 // The receiver klass is in recv_klass.
4045 // On success, the result will be in method_result, and execution falls through.
4046 // On failure, execution transfers to the given label.
4047 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4048 Register holder_klass,
4049 Register resolved_klass,
4050 Register method_result,
4051 Register scan_temp,
4052 Register temp_reg2,
4053 Register receiver,
4054 int itable_index,
4055 Label& L_no_such_interface) {
4056 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4057 Register temp_itbl_klass = method_result;
4058 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4059
4060 int vtable_base = in_bytes(Klass::vtable_start_offset());
4061 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4062 int scan_step = itableOffsetEntry::size() * wordSize;
4063 int vte_size = vtableEntry::size_in_bytes();
4064 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4065 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4066 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4067 assert(vte_size == wordSize, "adjust times_vte_scale");
4068
4069 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4070
4071 // temp_itbl_klass = recv_klass.itable[0]
4072 // scan_temp = &recv_klass.itable[0] + step
4073 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4074 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4075 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4076 xorptr(temp_reg, temp_reg);
4077
4078 // Initial checks:
4079 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4080 // - if (itable[0] == 0), no such interface
4081 // - if (itable[0] == holder_klass), shortcut to "holder found"
4082 cmpptr(holder_klass, resolved_klass);
4083 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4084 testptr(temp_itbl_klass, temp_itbl_klass);
4085 jccb(Assembler::zero, L_no_such_interface);
4086 cmpptr(holder_klass, temp_itbl_klass);
4087 jccb(Assembler::equal, L_holder_found);
4088
4089 // Loop: Look for holder_klass record in itable
4090 // do {
4091 // tmp = itable[index];
4092 // index += step;
4093 // if (tmp == holder_klass) {
4094 // goto L_holder_found; // Found!
4095 // }
4096 // } while (tmp != 0);
4097 // goto L_no_such_interface // Not found.
4098 Label L_scan_holder;
4099 bind(L_scan_holder);
4100 movptr(temp_itbl_klass, Address(scan_temp, 0));
4101 addptr(scan_temp, scan_step);
4102 cmpptr(holder_klass, temp_itbl_klass);
4103 jccb(Assembler::equal, L_holder_found);
4104 testptr(temp_itbl_klass, temp_itbl_klass);
4105 jccb(Assembler::notZero, L_scan_holder);
4106
4107 jmpb(L_no_such_interface);
4108
4109 // Loop: Look for resolved_class record in itable
4110 // do {
4111 // tmp = itable[index];
4112 // index += step;
4113 // if (tmp == holder_klass) {
4114 // // Also check if we have met a holder klass
4115 // holder_tmp = itable[index-step-ioffset];
4116 // }
4117 // if (tmp == resolved_klass) {
4118 // goto L_resolved_found; // Found!
4119 // }
4120 // } while (tmp != 0);
4121 // goto L_no_such_interface // Not found.
4122 //
4123 Label L_loop_scan_resolved;
4124 bind(L_loop_scan_resolved);
4125 movptr(temp_itbl_klass, Address(scan_temp, 0));
4126 addptr(scan_temp, scan_step);
4127 bind(L_loop_scan_resolved_entry);
4128 cmpptr(holder_klass, temp_itbl_klass);
4129 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4130 cmpptr(resolved_klass, temp_itbl_klass);
4131 jccb(Assembler::equal, L_resolved_found);
4132 testptr(temp_itbl_klass, temp_itbl_klass);
4133 jccb(Assembler::notZero, L_loop_scan_resolved);
4134
4135 jmpb(L_no_such_interface);
4136
4137 Label L_ready;
4138
4139 // See if we already have a holder klass. If not, go and scan for it.
4140 bind(L_resolved_found);
4141 testptr(temp_reg, temp_reg);
4142 jccb(Assembler::zero, L_scan_holder);
4143 jmpb(L_ready);
4144
4145 bind(L_holder_found);
4146 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4147
4148 // Finally, temp_reg contains holder_klass vtable offset
4149 bind(L_ready);
4150 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4151 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4152 load_klass(scan_temp, receiver, noreg);
4153 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4154 } else {
4155 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4156 }
4157 }
4158
4159
4160 // virtual method calling
4161 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4162 RegisterOrConstant vtable_index,
4163 Register method_result) {
4164 const ByteSize base = Klass::vtable_start_offset();
4165 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4166 Address vtable_entry_addr(recv_klass,
4167 vtable_index, Address::times_ptr,
4168 base + vtableEntry::method_offset());
4169 movptr(method_result, vtable_entry_addr);
4170 }
4171
4172
4173 void MacroAssembler::check_klass_subtype(Register sub_klass,
4174 Register super_klass,
4175 Register temp_reg,
4176 Label& L_success) {
4177 Label L_failure;
4178 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4179 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4180 bind(L_failure);
4181 }
4182
4183
4184 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4185 Register super_klass,
4186 Register temp_reg,
4187 Label* L_success,
4188 Label* L_failure,
4189 Label* L_slow_path,
4190 RegisterOrConstant super_check_offset) {
4191 assert_different_registers(sub_klass, super_klass, temp_reg);
4192 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4193 if (super_check_offset.is_register()) {
4194 assert_different_registers(sub_klass, super_klass,
4195 super_check_offset.as_register());
4196 } else if (must_load_sco) {
4197 assert(temp_reg != noreg, "supply either a temp or a register offset");
4198 }
4199
4200 Label L_fallthrough;
4201 int label_nulls = 0;
4202 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4203 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4204 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4205 assert(label_nulls <= 1, "at most one null in the batch");
4206
4207 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4208 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4209 Address super_check_offset_addr(super_klass, sco_offset);
4210
4211 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4212 // range of a jccb. If this routine grows larger, reconsider at
4213 // least some of these.
4214 #define local_jcc(assembler_cond, label) \
4215 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4216 else jcc( assembler_cond, label) /*omit semi*/
4217
4218 // Hacked jmp, which may only be used just before L_fallthrough.
4219 #define final_jmp(label) \
4220 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4221 else jmp(label) /*omit semi*/
4222
4223 // If the pointers are equal, we are done (e.g., String[] elements).
4224 // This self-check enables sharing of secondary supertype arrays among
4225 // non-primary types such as array-of-interface. Otherwise, each such
4226 // type would need its own customized SSA.
4227 // We move this check to the front of the fast path because many
4228 // type checks are in fact trivially successful in this manner,
4229 // so we get a nicely predicted branch right at the start of the check.
4230 cmpptr(sub_klass, super_klass);
4231 local_jcc(Assembler::equal, *L_success);
4232
4233 // Check the supertype display:
4234 if (must_load_sco) {
4235 // Positive movl does right thing on LP64.
4236 movl(temp_reg, super_check_offset_addr);
4237 super_check_offset = RegisterOrConstant(temp_reg);
4238 }
4239 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4240 cmpptr(super_klass, super_check_addr); // load displayed supertype
4241
4242 // This check has worked decisively for primary supers.
4243 // Secondary supers are sought in the super_cache ('super_cache_addr').
4244 // (Secondary supers are interfaces and very deeply nested subtypes.)
4245 // This works in the same check above because of a tricky aliasing
4246 // between the super_cache and the primary super display elements.
4247 // (The 'super_check_addr' can address either, as the case requires.)
4248 // Note that the cache is updated below if it does not help us find
4249 // what we need immediately.
4250 // So if it was a primary super, we can just fail immediately.
4251 // Otherwise, it's the slow path for us (no success at this point).
4252
4253 if (super_check_offset.is_register()) {
4254 local_jcc(Assembler::equal, *L_success);
4255 cmpl(super_check_offset.as_register(), sc_offset);
4256 if (L_failure == &L_fallthrough) {
4257 local_jcc(Assembler::equal, *L_slow_path);
4258 } else {
4259 local_jcc(Assembler::notEqual, *L_failure);
4260 final_jmp(*L_slow_path);
4261 }
4262 } else if (super_check_offset.as_constant() == sc_offset) {
4263 // Need a slow path; fast failure is impossible.
4264 if (L_slow_path == &L_fallthrough) {
4265 local_jcc(Assembler::equal, *L_success);
4266 } else {
4267 local_jcc(Assembler::notEqual, *L_slow_path);
4268 final_jmp(*L_success);
4269 }
4270 } else {
4271 // No slow path; it's a fast decision.
4272 if (L_failure == &L_fallthrough) {
4273 local_jcc(Assembler::equal, *L_success);
4274 } else {
4275 local_jcc(Assembler::notEqual, *L_failure);
4276 final_jmp(*L_success);
4277 }
4278 }
4279
4280 bind(L_fallthrough);
4281
4282 #undef local_jcc
4283 #undef final_jmp
4284 }
4285
4286
4287 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4288 Register super_klass,
4289 Register temp_reg,
4290 Register temp2_reg,
4291 Label* L_success,
4292 Label* L_failure,
4293 bool set_cond_codes) {
4294 assert_different_registers(sub_klass, super_klass, temp_reg);
4295 if (temp2_reg != noreg)
4296 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4297 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4298
4299 Label L_fallthrough;
4300 int label_nulls = 0;
4301 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4302 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4303 assert(label_nulls <= 1, "at most one null in the batch");
4304
4305 // a couple of useful fields in sub_klass:
4306 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4307 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4308 Address secondary_supers_addr(sub_klass, ss_offset);
4309 Address super_cache_addr( sub_klass, sc_offset);
4310
4311 // Do a linear scan of the secondary super-klass chain.
4312 // This code is rarely used, so simplicity is a virtue here.
4313 // The repne_scan instruction uses fixed registers, which we must spill.
4314 // Don't worry too much about pre-existing connections with the input regs.
4315
4316 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4317 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4318
4319 // Get super_klass value into rax (even if it was in rdi or rcx).
4320 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4321 if (super_klass != rax) {
4322 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4323 mov(rax, super_klass);
4324 }
4325 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4326 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4327
4328 #ifndef PRODUCT
4329 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4330 ExternalAddress pst_counter_addr((address) pst_counter);
4331 lea(rcx, pst_counter_addr);
4332 incrementl(Address(rcx, 0));
4333 #endif //PRODUCT
4334
4335 // We will consult the secondary-super array.
4336 movptr(rdi, secondary_supers_addr);
4337 // Load the array length. (Positive movl does right thing on LP64.)
4338 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4339 // Skip to start of data.
4340 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4341
4342 // Scan RCX words at [RDI] for an occurrence of RAX.
4343 // Set NZ/Z based on last compare.
4344 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4345 // not change flags (only scas instruction which is repeated sets flags).
4346 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4347
4348 testptr(rax,rax); // Set Z = 0
4349 repne_scan();
4350
4351 // Unspill the temp. registers:
4352 if (pushed_rdi) pop(rdi);
4353 if (pushed_rcx) pop(rcx);
4354 if (pushed_rax) pop(rax);
4355
4356 if (set_cond_codes) {
4357 // Special hack for the AD files: rdi is guaranteed non-zero.
4358 assert(!pushed_rdi, "rdi must be left non-null");
4359 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4360 }
4361
4362 if (L_failure == &L_fallthrough)
4363 jccb(Assembler::notEqual, *L_failure);
4364 else jcc(Assembler::notEqual, *L_failure);
4365
4366 // Success. Cache the super we found and proceed in triumph.
4367 movptr(super_cache_addr, super_klass);
4368
4369 if (L_success != &L_fallthrough) {
4370 jmp(*L_success);
4371 }
4372
4373 #undef IS_A_TEMP
4374
4375 bind(L_fallthrough);
4376 }
4377
4378 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4379 Register super_klass,
4380 Register temp_reg,
4381 Register temp2_reg,
4382 Label* L_success,
4383 Label* L_failure,
4384 bool set_cond_codes) {
4385 assert(set_cond_codes == false, "must be false on 64-bit x86");
4386 check_klass_subtype_slow_path
4387 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4388 L_success, L_failure);
4389 }
4390
4391 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4392 Register super_klass,
4393 Register temp_reg,
4394 Register temp2_reg,
4395 Register temp3_reg,
4396 Register temp4_reg,
4397 Label* L_success,
4398 Label* L_failure) {
4399 if (UseSecondarySupersTable) {
4400 check_klass_subtype_slow_path_table
4401 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4402 L_success, L_failure);
4403 } else {
4404 check_klass_subtype_slow_path_linear
4405 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4406 }
4407 }
4408
4409 Register MacroAssembler::allocate_if_noreg(Register r,
4410 RegSetIterator<Register> &available_regs,
4411 RegSet ®s_to_push) {
4412 if (!r->is_valid()) {
4413 r = *available_regs++;
4414 regs_to_push += r;
4415 }
4416 return r;
4417 }
4418
4419 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4420 Register super_klass,
4421 Register temp_reg,
4422 Register temp2_reg,
4423 Register temp3_reg,
4424 Register result_reg,
4425 Label* L_success,
4426 Label* L_failure) {
4427 // NB! Callers may assume that, when temp2_reg is a valid register,
4428 // this code sets it to a nonzero value.
4429 bool temp2_reg_was_valid = temp2_reg->is_valid();
4430
4431 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4432
4433 Label L_fallthrough;
4434 int label_nulls = 0;
4435 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4436 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4437 assert(label_nulls <= 1, "at most one null in the batch");
4438
4439 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4440
4441 RegSetIterator<Register> available_regs
4442 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4443
4444 RegSet pushed_regs;
4445
4446 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4447 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4448 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4449 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4450 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4451
4452 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4453
4454 {
4455
4456 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4457 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4458 subptr(rsp, aligned_size);
4459 push_set(pushed_regs, 0);
4460
4461 lookup_secondary_supers_table_var(sub_klass,
4462 super_klass,
4463 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4464 cmpq(result_reg, 0);
4465
4466 // Unspill the temp. registers:
4467 pop_set(pushed_regs, 0);
4468 // Increment SP but do not clobber flags.
4469 lea(rsp, Address(rsp, aligned_size));
4470 }
4471
4472 if (temp2_reg_was_valid) {
4473 movq(temp2_reg, 1);
4474 }
4475
4476 jcc(Assembler::notEqual, *L_failure);
4477
4478 if (L_success != &L_fallthrough) {
4479 jmp(*L_success);
4480 }
4481
4482 bind(L_fallthrough);
4483 }
4484
4485 // population_count variant for running without the POPCNT
4486 // instruction, which was introduced with SSE4.2 in 2008.
4487 void MacroAssembler::population_count(Register dst, Register src,
4488 Register scratch1, Register scratch2) {
4489 assert_different_registers(src, scratch1, scratch2);
4490 if (UsePopCountInstruction) {
4491 Assembler::popcntq(dst, src);
4492 } else {
4493 assert_different_registers(src, scratch1, scratch2);
4494 assert_different_registers(dst, scratch1, scratch2);
4495 Label loop, done;
4496
4497 mov(scratch1, src);
4498 // dst = 0;
4499 // while(scratch1 != 0) {
4500 // dst++;
4501 // scratch1 &= (scratch1 - 1);
4502 // }
4503 xorl(dst, dst);
4504 testq(scratch1, scratch1);
4505 jccb(Assembler::equal, done);
4506 {
4507 bind(loop);
4508 incq(dst);
4509 movq(scratch2, scratch1);
4510 decq(scratch2);
4511 andq(scratch1, scratch2);
4512 jccb(Assembler::notEqual, loop);
4513 }
4514 bind(done);
4515 }
4516 #ifdef ASSERT
4517 mov64(scratch1, 0xCafeBabeDeadBeef);
4518 movq(scratch2, scratch1);
4519 #endif
4520 }
4521
4522 // Ensure that the inline code and the stub are using the same registers.
4523 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4524 do { \
4525 assert(r_super_klass == rax, "mismatch"); \
4526 assert(r_array_base == rbx, "mismatch"); \
4527 assert(r_array_length == rcx, "mismatch"); \
4528 assert(r_array_index == rdx, "mismatch"); \
4529 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4530 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4531 assert(result == rdi || result == noreg, "mismatch"); \
4532 } while(0)
4533
4534 // Versions of salq and rorq that don't need count to be in rcx
4535
4536 void MacroAssembler::salq(Register dest, Register count) {
4537 if (count == rcx) {
4538 Assembler::salq(dest);
4539 } else {
4540 assert_different_registers(rcx, dest);
4541 xchgq(rcx, count);
4542 Assembler::salq(dest);
4543 xchgq(rcx, count);
4544 }
4545 }
4546
4547 void MacroAssembler::rorq(Register dest, Register count) {
4548 if (count == rcx) {
4549 Assembler::rorq(dest);
4550 } else {
4551 assert_different_registers(rcx, dest);
4552 xchgq(rcx, count);
4553 Assembler::rorq(dest);
4554 xchgq(rcx, count);
4555 }
4556 }
4557
4558 // Return true: we succeeded in generating this code
4559 //
4560 // At runtime, return 0 in result if r_super_klass is a superclass of
4561 // r_sub_klass, otherwise return nonzero. Use this if you know the
4562 // super_klass_slot of the class you're looking for. This is always
4563 // the case for instanceof and checkcast.
4564 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4565 Register r_super_klass,
4566 Register temp1,
4567 Register temp2,
4568 Register temp3,
4569 Register temp4,
4570 Register result,
4571 u1 super_klass_slot) {
4572 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4573
4574 Label L_fallthrough, L_success, L_failure;
4575
4576 BLOCK_COMMENT("lookup_secondary_supers_table {");
4577
4578 const Register
4579 r_array_index = temp1,
4580 r_array_length = temp2,
4581 r_array_base = temp3,
4582 r_bitmap = temp4;
4583
4584 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4585
4586 xorq(result, result); // = 0
4587
4588 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4589 movq(r_array_index, r_bitmap);
4590
4591 // First check the bitmap to see if super_klass might be present. If
4592 // the bit is zero, we are certain that super_klass is not one of
4593 // the secondary supers.
4594 u1 bit = super_klass_slot;
4595 {
4596 // NB: If the count in a x86 shift instruction is 0, the flags are
4597 // not affected, so we do a testq instead.
4598 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4599 if (shift_count != 0) {
4600 salq(r_array_index, shift_count);
4601 } else {
4602 testq(r_array_index, r_array_index);
4603 }
4604 }
4605 // We test the MSB of r_array_index, i.e. its sign bit
4606 jcc(Assembler::positive, L_failure);
4607
4608 // Get the first array index that can contain super_klass into r_array_index.
4609 if (bit != 0) {
4610 population_count(r_array_index, r_array_index, temp2, temp3);
4611 } else {
4612 movl(r_array_index, 1);
4613 }
4614 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4615
4616 // We will consult the secondary-super array.
4617 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4618
4619 // We're asserting that the first word in an Array<Klass*> is the
4620 // length, and the second word is the first word of the data. If
4621 // that ever changes, r_array_base will have to be adjusted here.
4622 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4623 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4624
4625 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4626 jccb(Assembler::equal, L_success);
4627
4628 // Is there another entry to check? Consult the bitmap.
4629 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4630 jccb(Assembler::carryClear, L_failure);
4631
4632 // Linear probe. Rotate the bitmap so that the next bit to test is
4633 // in Bit 1.
4634 if (bit != 0) {
4635 rorq(r_bitmap, bit);
4636 }
4637
4638 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4639 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4640 // Kills: r_array_length.
4641 // Returns: result.
4642 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4643 // Result (0/1) is in rdi
4644 jmpb(L_fallthrough);
4645
4646 bind(L_failure);
4647 incq(result); // 0 => 1
4648
4649 bind(L_success);
4650 // result = 0;
4651
4652 bind(L_fallthrough);
4653 BLOCK_COMMENT("} lookup_secondary_supers_table");
4654
4655 if (VerifySecondarySupers) {
4656 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4657 temp1, temp2, temp3);
4658 }
4659 }
4660
4661 // At runtime, return 0 in result if r_super_klass is a superclass of
4662 // r_sub_klass, otherwise return nonzero. Use this version of
4663 // lookup_secondary_supers_table() if you don't know ahead of time
4664 // which superclass will be searched for. Used by interpreter and
4665 // runtime stubs. It is larger and has somewhat greater latency than
4666 // the version above, which takes a constant super_klass_slot.
4667 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
4668 Register r_super_klass,
4669 Register temp1,
4670 Register temp2,
4671 Register temp3,
4672 Register temp4,
4673 Register result) {
4674 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4675 assert_different_registers(r_sub_klass, r_super_klass, rcx);
4676 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
4677
4678 Label L_fallthrough, L_success, L_failure;
4679
4680 BLOCK_COMMENT("lookup_secondary_supers_table {");
4681
4682 RegSetIterator<Register> available_regs = (temps - rcx).begin();
4683
4684 // FIXME. Once we are sure that all paths reaching this point really
4685 // do pass rcx as one of our temps we can get rid of the following
4686 // workaround.
4687 assert(temps.contains(rcx), "fix this code");
4688
4689 // We prefer to have our shift count in rcx. If rcx is one of our
4690 // temps, use it for slot. If not, pick any of our temps.
4691 Register slot;
4692 if (!temps.contains(rcx)) {
4693 slot = *available_regs++;
4694 } else {
4695 slot = rcx;
4696 }
4697
4698 const Register r_array_index = *available_regs++;
4699 const Register r_bitmap = *available_regs++;
4700
4701 // The logic above guarantees this property, but we state it here.
4702 assert_different_registers(r_array_index, r_bitmap, rcx);
4703
4704 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4705 movq(r_array_index, r_bitmap);
4706
4707 // First check the bitmap to see if super_klass might be present. If
4708 // the bit is zero, we are certain that super_klass is not one of
4709 // the secondary supers.
4710 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4711 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
4712 salq(r_array_index, slot);
4713
4714 testq(r_array_index, r_array_index);
4715 // We test the MSB of r_array_index, i.e. its sign bit
4716 jcc(Assembler::positive, L_failure);
4717
4718 const Register r_array_base = *available_regs++;
4719
4720 // Get the first array index that can contain super_klass into r_array_index.
4721 // Note: Clobbers r_array_base and slot.
4722 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
4723
4724 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4725
4726 // We will consult the secondary-super array.
4727 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4728
4729 // We're asserting that the first word in an Array<Klass*> is the
4730 // length, and the second word is the first word of the data. If
4731 // that ever changes, r_array_base will have to be adjusted here.
4732 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4733 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4734
4735 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4736 jccb(Assembler::equal, L_success);
4737
4738 // Restore slot to its true value
4739 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4740
4741 // Linear probe. Rotate the bitmap so that the next bit to test is
4742 // in Bit 1.
4743 rorq(r_bitmap, slot);
4744
4745 // Is there another entry to check? Consult the bitmap.
4746 btq(r_bitmap, 1);
4747 jccb(Assembler::carryClear, L_failure);
4748
4749 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4750 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4751 // Kills: r_array_length.
4752 // Returns: result.
4753 lookup_secondary_supers_table_slow_path(r_super_klass,
4754 r_array_base,
4755 r_array_index,
4756 r_bitmap,
4757 /*temp1*/result,
4758 /*temp2*/slot,
4759 &L_success,
4760 nullptr);
4761
4762 bind(L_failure);
4763 movq(result, 1);
4764 jmpb(L_fallthrough);
4765
4766 bind(L_success);
4767 xorq(result, result); // = 0
4768
4769 bind(L_fallthrough);
4770 BLOCK_COMMENT("} lookup_secondary_supers_table");
4771
4772 if (VerifySecondarySupers) {
4773 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4774 temp1, temp2, temp3);
4775 }
4776 }
4777
4778 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4779 Label* L_success, Label* L_failure) {
4780 Label L_loop, L_fallthrough;
4781 {
4782 int label_nulls = 0;
4783 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4784 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4785 assert(label_nulls <= 1, "at most one null in the batch");
4786 }
4787 bind(L_loop);
4788 cmpq(value, Address(addr, count, Address::times_8));
4789 jcc(Assembler::equal, *L_success);
4790 addl(count, 1);
4791 cmpl(count, limit);
4792 jcc(Assembler::less, L_loop);
4793
4794 if (&L_fallthrough != L_failure) {
4795 jmp(*L_failure);
4796 }
4797 bind(L_fallthrough);
4798 }
4799
4800 // Called by code generated by check_klass_subtype_slow_path
4801 // above. This is called when there is a collision in the hashed
4802 // lookup in the secondary supers array.
4803 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4804 Register r_array_base,
4805 Register r_array_index,
4806 Register r_bitmap,
4807 Register temp1,
4808 Register temp2,
4809 Label* L_success,
4810 Label* L_failure) {
4811 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4812
4813 const Register
4814 r_array_length = temp1,
4815 r_sub_klass = noreg,
4816 result = noreg;
4817
4818 Label L_fallthrough;
4819 int label_nulls = 0;
4820 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4821 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4822 assert(label_nulls <= 1, "at most one null in the batch");
4823
4824 // Load the array length.
4825 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4826 // And adjust the array base to point to the data.
4827 // NB! Effectively increments current slot index by 1.
4828 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4829 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4830
4831 // Linear probe
4832 Label L_huge;
4833
4834 // The bitmap is full to bursting.
4835 // Implicit invariant: BITMAP_FULL implies (length > 0)
4836 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
4837 jcc(Assembler::greater, L_huge);
4838
4839 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4840 // current slot (at secondary_supers[r_array_index]) has not yet
4841 // been inspected, and r_array_index may be out of bounds if we
4842 // wrapped around the end of the array.
4843
4844 { // This is conventional linear probing, but instead of terminating
4845 // when a null entry is found in the table, we maintain a bitmap
4846 // in which a 0 indicates missing entries.
4847 // The check above guarantees there are 0s in the bitmap, so the loop
4848 // eventually terminates.
4849
4850 xorl(temp2, temp2); // = 0;
4851
4852 Label L_again;
4853 bind(L_again);
4854
4855 // Check for array wraparound.
4856 cmpl(r_array_index, r_array_length);
4857 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4858
4859 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4860 jcc(Assembler::equal, *L_success);
4861
4862 // If the next bit in bitmap is zero, we're done.
4863 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4864 jcc(Assembler::carryClear, *L_failure);
4865
4866 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4867 addl(r_array_index, 1);
4868
4869 jmp(L_again);
4870 }
4871
4872 { // Degenerate case: more than 64 secondary supers.
4873 // FIXME: We could do something smarter here, maybe a vectorized
4874 // comparison or a binary search, but is that worth any added
4875 // complexity?
4876 bind(L_huge);
4877 xorl(r_array_index, r_array_index); // = 0
4878 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4879 L_success,
4880 (&L_fallthrough != L_failure ? L_failure : nullptr));
4881
4882 bind(L_fallthrough);
4883 }
4884 }
4885
4886 struct VerifyHelperArguments {
4887 Klass* _super;
4888 Klass* _sub;
4889 intptr_t _linear_result;
4890 intptr_t _table_result;
4891 };
4892
4893 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
4894 Klass::on_secondary_supers_verification_failure(args->_super,
4895 args->_sub,
4896 args->_linear_result,
4897 args->_table_result,
4898 msg);
4899 }
4900
4901 // Make sure that the hashed lookup and a linear scan agree.
4902 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
4903 Register r_super_klass,
4904 Register result,
4905 Register temp1,
4906 Register temp2,
4907 Register temp3) {
4908 const Register
4909 r_array_index = temp1,
4910 r_array_length = temp2,
4911 r_array_base = temp3,
4912 r_bitmap = noreg;
4913
4914 BLOCK_COMMENT("verify_secondary_supers_table {");
4915
4916 Label L_success, L_failure, L_check, L_done;
4917
4918 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4919 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4920 // And adjust the array base to point to the data.
4921 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4922
4923 testl(r_array_length, r_array_length); // array_length == 0?
4924 jcc(Assembler::zero, L_failure);
4925
4926 movl(r_array_index, 0);
4927 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
4928 // fall through to L_failure
4929
4930 const Register linear_result = r_array_index; // reuse temp1
4931
4932 bind(L_failure); // not present
4933 movl(linear_result, 1);
4934 jmp(L_check);
4935
4936 bind(L_success); // present
4937 movl(linear_result, 0);
4938
4939 bind(L_check);
4940 cmpl(linear_result, result);
4941 jcc(Assembler::equal, L_done);
4942
4943 { // To avoid calling convention issues, build a record on the stack
4944 // and pass the pointer to that instead.
4945 push(result);
4946 push(linear_result);
4947 push(r_sub_klass);
4948 push(r_super_klass);
4949 movptr(c_rarg1, rsp);
4950 movptr(c_rarg0, (uintptr_t) "mismatch");
4951 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
4952 should_not_reach_here();
4953 }
4954 bind(L_done);
4955
4956 BLOCK_COMMENT("} verify_secondary_supers_table");
4957 }
4958
4959 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
4960
4961 void MacroAssembler::clinit_barrier(Register klass, Label* L_fast_path, Label* L_slow_path) {
4962 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
4963
4964 Label L_fallthrough;
4965 if (L_fast_path == nullptr) {
4966 L_fast_path = &L_fallthrough;
4967 } else if (L_slow_path == nullptr) {
4968 L_slow_path = &L_fallthrough;
4969 }
4970
4971 // Fast path check: class is fully initialized.
4972 // init_state needs acquire, but x86 is TSO, and so we are already good.
4973 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4974 jcc(Assembler::equal, *L_fast_path);
4975
4976 // Fast path check: current thread is initializer thread
4977 cmpptr(r15_thread, Address(klass, InstanceKlass::init_thread_offset()));
4978 if (L_slow_path == &L_fallthrough) {
4979 jcc(Assembler::equal, *L_fast_path);
4980 bind(*L_slow_path);
4981 } else if (L_fast_path == &L_fallthrough) {
4982 jcc(Assembler::notEqual, *L_slow_path);
4983 bind(*L_fast_path);
4984 } else {
4985 Unimplemented();
4986 }
4987 }
4988
4989 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4990 if (VM_Version::supports_cmov()) {
4991 cmovl(cc, dst, src);
4992 } else {
4993 Label L;
4994 jccb(negate_condition(cc), L);
4995 movl(dst, src);
4996 bind(L);
4997 }
4998 }
4999
5000 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5001 if (VM_Version::supports_cmov()) {
5002 cmovl(cc, dst, src);
5003 } else {
5004 Label L;
5005 jccb(negate_condition(cc), L);
5006 movl(dst, src);
5007 bind(L);
5008 }
5009 }
5010
5011 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5012 if (!VerifyOops || VerifyAdapterSharing) {
5013 // Below address of the code string confuses VerifyAdapterSharing
5014 // because it may differ between otherwise equivalent adapters.
5015 return;
5016 }
5017
5018 BLOCK_COMMENT("verify_oop {");
5019 push(rscratch1);
5020 push(rax); // save rax
5021 push(reg); // pass register argument
5022
5023 // Pass register number to verify_oop_subroutine
5024 const char* b = nullptr;
5025 {
5026 ResourceMark rm;
5027 stringStream ss;
5028 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5029 b = code_string(ss.as_string());
5030 }
5031 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5032 pushptr(buffer.addr(), rscratch1);
5033
5034 // call indirectly to solve generation ordering problem
5035 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5036 call(rax);
5037 // Caller pops the arguments (oop, message) and restores rax, r10
5038 BLOCK_COMMENT("} verify_oop");
5039 }
5040
5041 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5042 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5043 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5044 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5045 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5046 } else if (VM_Version::supports_avx()) {
5047 vpcmpeqd(dst, dst, dst, vector_len);
5048 } else {
5049 pcmpeqd(dst, dst);
5050 }
5051 }
5052
5053 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5054 int extra_slot_offset) {
5055 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5056 int stackElementSize = Interpreter::stackElementSize;
5057 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5058 #ifdef ASSERT
5059 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5060 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5061 #endif
5062 Register scale_reg = noreg;
5063 Address::ScaleFactor scale_factor = Address::no_scale;
5064 if (arg_slot.is_constant()) {
5065 offset += arg_slot.as_constant() * stackElementSize;
5066 } else {
5067 scale_reg = arg_slot.as_register();
5068 scale_factor = Address::times(stackElementSize);
5069 }
5070 offset += wordSize; // return PC is on stack
5071 return Address(rsp, scale_reg, scale_factor, offset);
5072 }
5073
5074 // Handle the receiver type profile update given the "recv" klass.
5075 //
5076 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
5077 // If there are no matching or claimable receiver entries in RD, updates
5078 // the polymorphic counter.
5079 //
5080 // This code expected to run by either the interpreter or JIT-ed code, without
5081 // extra synchronization. For safety, receiver cells are claimed atomically, which
5082 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
5083 // counter updates are not atomic.
5084 //
5085 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
5086 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
5087 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
5088 int poly_count_offset = in_bytes(CounterData::count_offset());
5089 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
5090 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
5091
5092 // Adjust for MDP offsets. Slots are pointer-sized, so is the global offset.
5093 assert(is_aligned(mdp_offset, BytesPerWord), "sanity");
5094 base_receiver_offset += mdp_offset;
5095 end_receiver_offset += mdp_offset;
5096 poly_count_offset += mdp_offset;
5097
5098 // Scale down to optimize encoding. Slots are pointer-sized.
5099 assert(is_aligned(base_receiver_offset, BytesPerWord), "sanity");
5100 assert(is_aligned(end_receiver_offset, BytesPerWord), "sanity");
5101 assert(is_aligned(poly_count_offset, BytesPerWord), "sanity");
5102 assert(is_aligned(receiver_step, BytesPerWord), "sanity");
5103 assert(is_aligned(receiver_to_count_step, BytesPerWord), "sanity");
5104 base_receiver_offset >>= LogBytesPerWord;
5105 end_receiver_offset >>= LogBytesPerWord;
5106 poly_count_offset >>= LogBytesPerWord;
5107 receiver_step >>= LogBytesPerWord;
5108 receiver_to_count_step >>= LogBytesPerWord;
5109
5110 #ifdef ASSERT
5111 // We are about to walk the MDO slots without asking for offsets.
5112 // Check that our math hits all the right spots.
5113 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
5114 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
5115 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
5116 int offset = base_receiver_offset + receiver_step*c;
5117 int count_offset = offset + receiver_to_count_step;
5118 assert((offset << LogBytesPerWord) == real_recv_offset, "receiver slot math");
5119 assert((count_offset << LogBytesPerWord) == real_count_offset, "receiver count math");
5120 }
5121 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
5122 assert(poly_count_offset << LogBytesPerWord == real_poly_count_offset, "poly counter math");
5123 #endif
5124
5125 // Corner case: no profile table. Increment poly counter and exit.
5126 if (ReceiverTypeData::row_limit() == 0) {
5127 addptr(Address(mdp, poly_count_offset, Address::times_ptr), DataLayout::counter_increment);
5128 return;
5129 }
5130
5131 Register offset = rscratch1;
5132
5133 Label L_loop_search_receiver, L_loop_search_empty;
5134 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
5135
5136 // The code here recognizes three major cases:
5137 // A. Fastest: receiver found in the table
5138 // B. Fast: no receiver in the table, and the table is full
5139 // C. Slow: no receiver in the table, free slots in the table
5140 //
5141 // The case A performance is most important, as perfectly-behaved code would end up
5142 // there, especially with larger TypeProfileWidth. The case B performance is
5143 // important as well, this is where bulk of code would land for normally megamorphic
5144 // cases. The case C performance is not essential, its job is to deal with installation
5145 // races, we optimize for code density instead. Case C needs to make sure that receiver
5146 // rows are only claimed once. This makes sure we never overwrite a row for another
5147 // receiver and never duplicate the receivers in the list, making profile type-accurate.
5148 //
5149 // It is very tempting to handle these cases in a single loop, and claim the first slot
5150 // without checking the rest of the table. But, profiling code should tolerate free slots
5151 // in the table, as class unloading can clear them. After such cleanup, the receiver
5152 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
5153 // to complete, before trying to install new slots. Splitting the code in several tight
5154 // loops also helpfully optimizes for cases A and B.
5155 //
5156 // This code is effectively:
5157 //
5158 // restart:
5159 // // Fastest: receiver is already installed
5160 // for (i = 0; i < receiver_count(); i++) {
5161 // if (receiver(i) == recv) goto found_recv(i);
5162 // }
5163 //
5164 // // Fast: no receiver, but profile is full
5165 // for (i = 0; i < receiver_count(); i++) {
5166 // if (receiver(i) == null) goto found_null(i);
5167 // }
5168 // goto polymorphic
5169 //
5170 // // Slow: try to install receiver
5171 // found_null(i):
5172 // CAS(&receiver(i), null, recv);
5173 // goto restart
5174 //
5175 // polymorphic:
5176 // count++;
5177 // return
5178 //
5179 // found_recv(i):
5180 // *receiver_count(i)++
5181 //
5182
5183 bind(L_restart);
5184
5185 // Fastest: receiver is already installed
5186 movptr(offset, base_receiver_offset);
5187 bind(L_loop_search_receiver);
5188 cmpptr(recv, Address(mdp, offset, Address::times_ptr));
5189 jccb(Assembler::equal, L_found_recv);
5190 addptr(offset, receiver_step);
5191 cmpptr(offset, end_receiver_offset);
5192 jccb(Assembler::notEqual, L_loop_search_receiver);
5193
5194 // Fast: no receiver, but profile is full
5195 movptr(offset, base_receiver_offset);
5196 bind(L_loop_search_empty);
5197 cmpptr(Address(mdp, offset, Address::times_ptr), NULL_WORD);
5198 jccb(Assembler::equal, L_found_empty);
5199 addptr(offset, receiver_step);
5200 cmpptr(offset, end_receiver_offset);
5201 jccb(Assembler::notEqual, L_loop_search_empty);
5202 jmpb(L_polymorphic);
5203
5204 // Slow: try to install receiver
5205 bind(L_found_empty);
5206
5207 // Atomically swing receiver slot: null -> recv.
5208 //
5209 // The update code uses CAS, which wants RAX register specifically, *and* it needs
5210 // other important registers untouched, as they form the address. Therefore, we need
5211 // to shift any important registers from RAX into some other spare register. If we
5212 // have a spare register, we are forced to save it on stack here.
5213
5214 Register spare_reg = noreg;
5215 Register shifted_mdp = mdp;
5216 Register shifted_recv = recv;
5217 if (recv == rax || mdp == rax) {
5218 spare_reg = (recv != rbx && mdp != rbx) ? rbx :
5219 (recv != rcx && mdp != rcx) ? rcx :
5220 rdx;
5221 assert_different_registers(mdp, recv, offset, spare_reg);
5222
5223 push(spare_reg);
5224 if (recv == rax) {
5225 movptr(spare_reg, recv);
5226 shifted_recv = spare_reg;
5227 } else {
5228 assert(mdp == rax, "Remaining case");
5229 movptr(spare_reg, mdp);
5230 shifted_mdp = spare_reg;
5231 }
5232 } else {
5233 push(rax);
5234 }
5235
5236 // None of the important registers are in RAX after this shuffle.
5237 assert_different_registers(rax, shifted_mdp, shifted_recv, offset);
5238
5239 xorptr(rax, rax);
5240 cmpxchgptr(shifted_recv, Address(shifted_mdp, offset, Address::times_ptr));
5241
5242 // Unshift registers.
5243 if (recv == rax || mdp == rax) {
5244 movptr(rax, spare_reg);
5245 pop(spare_reg);
5246 } else {
5247 pop(rax);
5248 }
5249
5250 // CAS success means the slot now has the receiver we want. CAS failure means
5251 // something had claimed the slot concurrently: it can be the same receiver we want,
5252 // or something else. Since this is a slow path, we can optimize for code density,
5253 // and just restart the search from the beginning.
5254 jmpb(L_restart);
5255
5256 // Counter updates:
5257
5258 // Increment polymorphic counter instead of receiver slot.
5259 bind(L_polymorphic);
5260 movptr(offset, poly_count_offset);
5261 jmpb(L_count_update);
5262
5263 // Found a receiver, convert its slot offset to corresponding count offset.
5264 bind(L_found_recv);
5265 addptr(offset, receiver_to_count_step);
5266
5267 bind(L_count_update);
5268 addptr(Address(mdp, offset, Address::times_ptr), DataLayout::counter_increment);
5269 }
5270
5271 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5272 if (!VerifyOops || VerifyAdapterSharing) {
5273 // Below address of the code string confuses VerifyAdapterSharing
5274 // because it may differ between otherwise equivalent adapters.
5275 return;
5276 }
5277
5278 push(rscratch1);
5279 push(rax); // save rax,
5280 // addr may contain rsp so we will have to adjust it based on the push
5281 // we just did (and on 64 bit we do two pushes)
5282 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5283 // stores rax into addr which is backwards of what was intended.
5284 if (addr.uses(rsp)) {
5285 lea(rax, addr);
5286 pushptr(Address(rax, 2 * BytesPerWord));
5287 } else {
5288 pushptr(addr);
5289 }
5290
5291 // Pass register number to verify_oop_subroutine
5292 const char* b = nullptr;
5293 {
5294 ResourceMark rm;
5295 stringStream ss;
5296 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5297 b = code_string(ss.as_string());
5298 }
5299 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5300 pushptr(buffer.addr(), rscratch1);
5301
5302 // call indirectly to solve generation ordering problem
5303 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5304 call(rax);
5305 // Caller pops the arguments (addr, message) and restores rax, r10.
5306 }
5307
5308 void MacroAssembler::verify_tlab() {
5309 #ifdef ASSERT
5310 if (UseTLAB && VerifyOops) {
5311 Label next, ok;
5312 Register t1 = rsi;
5313
5314 push(t1);
5315
5316 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5317 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
5318 jcc(Assembler::aboveEqual, next);
5319 STOP("assert(top >= start)");
5320 should_not_reach_here();
5321
5322 bind(next);
5323 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
5324 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5325 jcc(Assembler::aboveEqual, ok);
5326 STOP("assert(top <= end)");
5327 should_not_reach_here();
5328
5329 bind(ok);
5330 pop(t1);
5331 }
5332 #endif
5333 }
5334
5335 class ControlWord {
5336 public:
5337 int32_t _value;
5338
5339 int rounding_control() const { return (_value >> 10) & 3 ; }
5340 int precision_control() const { return (_value >> 8) & 3 ; }
5341 bool precision() const { return ((_value >> 5) & 1) != 0; }
5342 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5343 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5344 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5345 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5346 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5347
5348 void print() const {
5349 // rounding control
5350 const char* rc;
5351 switch (rounding_control()) {
5352 case 0: rc = "round near"; break;
5353 case 1: rc = "round down"; break;
5354 case 2: rc = "round up "; break;
5355 case 3: rc = "chop "; break;
5356 default:
5357 rc = nullptr; // silence compiler warnings
5358 fatal("Unknown rounding control: %d", rounding_control());
5359 };
5360 // precision control
5361 const char* pc;
5362 switch (precision_control()) {
5363 case 0: pc = "24 bits "; break;
5364 case 1: pc = "reserved"; break;
5365 case 2: pc = "53 bits "; break;
5366 case 3: pc = "64 bits "; break;
5367 default:
5368 pc = nullptr; // silence compiler warnings
5369 fatal("Unknown precision control: %d", precision_control());
5370 };
5371 // flags
5372 char f[9];
5373 f[0] = ' ';
5374 f[1] = ' ';
5375 f[2] = (precision ()) ? 'P' : 'p';
5376 f[3] = (underflow ()) ? 'U' : 'u';
5377 f[4] = (overflow ()) ? 'O' : 'o';
5378 f[5] = (zero_divide ()) ? 'Z' : 'z';
5379 f[6] = (denormalized()) ? 'D' : 'd';
5380 f[7] = (invalid ()) ? 'I' : 'i';
5381 f[8] = '\x0';
5382 // output
5383 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5384 }
5385
5386 };
5387
5388 class StatusWord {
5389 public:
5390 int32_t _value;
5391
5392 bool busy() const { return ((_value >> 15) & 1) != 0; }
5393 bool C3() const { return ((_value >> 14) & 1) != 0; }
5394 bool C2() const { return ((_value >> 10) & 1) != 0; }
5395 bool C1() const { return ((_value >> 9) & 1) != 0; }
5396 bool C0() const { return ((_value >> 8) & 1) != 0; }
5397 int top() const { return (_value >> 11) & 7 ; }
5398 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5399 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5400 bool precision() const { return ((_value >> 5) & 1) != 0; }
5401 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5402 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5403 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5404 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5405 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5406
5407 void print() const {
5408 // condition codes
5409 char c[5];
5410 c[0] = (C3()) ? '3' : '-';
5411 c[1] = (C2()) ? '2' : '-';
5412 c[2] = (C1()) ? '1' : '-';
5413 c[3] = (C0()) ? '0' : '-';
5414 c[4] = '\x0';
5415 // flags
5416 char f[9];
5417 f[0] = (error_status()) ? 'E' : '-';
5418 f[1] = (stack_fault ()) ? 'S' : '-';
5419 f[2] = (precision ()) ? 'P' : '-';
5420 f[3] = (underflow ()) ? 'U' : '-';
5421 f[4] = (overflow ()) ? 'O' : '-';
5422 f[5] = (zero_divide ()) ? 'Z' : '-';
5423 f[6] = (denormalized()) ? 'D' : '-';
5424 f[7] = (invalid ()) ? 'I' : '-';
5425 f[8] = '\x0';
5426 // output
5427 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5428 }
5429
5430 };
5431
5432 class TagWord {
5433 public:
5434 int32_t _value;
5435
5436 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5437
5438 void print() const {
5439 printf("%04x", _value & 0xFFFF);
5440 }
5441
5442 };
5443
5444 class FPU_Register {
5445 public:
5446 int32_t _m0;
5447 int32_t _m1;
5448 int16_t _ex;
5449
5450 bool is_indefinite() const {
5451 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5452 }
5453
5454 void print() const {
5455 char sign = (_ex < 0) ? '-' : '+';
5456 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5457 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5458 };
5459
5460 };
5461
5462 class FPU_State {
5463 public:
5464 enum {
5465 register_size = 10,
5466 number_of_registers = 8,
5467 register_mask = 7
5468 };
5469
5470 ControlWord _control_word;
5471 StatusWord _status_word;
5472 TagWord _tag_word;
5473 int32_t _error_offset;
5474 int32_t _error_selector;
5475 int32_t _data_offset;
5476 int32_t _data_selector;
5477 int8_t _register[register_size * number_of_registers];
5478
5479 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5480 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5481
5482 const char* tag_as_string(int tag) const {
5483 switch (tag) {
5484 case 0: return "valid";
5485 case 1: return "zero";
5486 case 2: return "special";
5487 case 3: return "empty";
5488 }
5489 ShouldNotReachHere();
5490 return nullptr;
5491 }
5492
5493 void print() const {
5494 // print computation registers
5495 { int t = _status_word.top();
5496 for (int i = 0; i < number_of_registers; i++) {
5497 int j = (i - t) & register_mask;
5498 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5499 st(j)->print();
5500 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5501 }
5502 }
5503 printf("\n");
5504 // print control registers
5505 printf("ctrl = "); _control_word.print(); printf("\n");
5506 printf("stat = "); _status_word .print(); printf("\n");
5507 printf("tags = "); _tag_word .print(); printf("\n");
5508 }
5509
5510 };
5511
5512 class Flag_Register {
5513 public:
5514 int32_t _value;
5515
5516 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5517 bool direction() const { return ((_value >> 10) & 1) != 0; }
5518 bool sign() const { return ((_value >> 7) & 1) != 0; }
5519 bool zero() const { return ((_value >> 6) & 1) != 0; }
5520 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5521 bool parity() const { return ((_value >> 2) & 1) != 0; }
5522 bool carry() const { return ((_value >> 0) & 1) != 0; }
5523
5524 void print() const {
5525 // flags
5526 char f[8];
5527 f[0] = (overflow ()) ? 'O' : '-';
5528 f[1] = (direction ()) ? 'D' : '-';
5529 f[2] = (sign ()) ? 'S' : '-';
5530 f[3] = (zero ()) ? 'Z' : '-';
5531 f[4] = (auxiliary_carry()) ? 'A' : '-';
5532 f[5] = (parity ()) ? 'P' : '-';
5533 f[6] = (carry ()) ? 'C' : '-';
5534 f[7] = '\x0';
5535 // output
5536 printf("%08x flags = %s", _value, f);
5537 }
5538
5539 };
5540
5541 class IU_Register {
5542 public:
5543 int32_t _value;
5544
5545 void print() const {
5546 printf("%08x %11d", _value, _value);
5547 }
5548
5549 };
5550
5551 class IU_State {
5552 public:
5553 Flag_Register _eflags;
5554 IU_Register _rdi;
5555 IU_Register _rsi;
5556 IU_Register _rbp;
5557 IU_Register _rsp;
5558 IU_Register _rbx;
5559 IU_Register _rdx;
5560 IU_Register _rcx;
5561 IU_Register _rax;
5562
5563 void print() const {
5564 // computation registers
5565 printf("rax, = "); _rax.print(); printf("\n");
5566 printf("rbx, = "); _rbx.print(); printf("\n");
5567 printf("rcx = "); _rcx.print(); printf("\n");
5568 printf("rdx = "); _rdx.print(); printf("\n");
5569 printf("rdi = "); _rdi.print(); printf("\n");
5570 printf("rsi = "); _rsi.print(); printf("\n");
5571 printf("rbp, = "); _rbp.print(); printf("\n");
5572 printf("rsp = "); _rsp.print(); printf("\n");
5573 printf("\n");
5574 // control registers
5575 printf("flgs = "); _eflags.print(); printf("\n");
5576 }
5577 };
5578
5579
5580 class CPU_State {
5581 public:
5582 FPU_State _fpu_state;
5583 IU_State _iu_state;
5584
5585 void print() const {
5586 printf("--------------------------------------------------\n");
5587 _iu_state .print();
5588 printf("\n");
5589 _fpu_state.print();
5590 printf("--------------------------------------------------\n");
5591 }
5592
5593 };
5594
5595
5596 static void _print_CPU_state(CPU_State* state) {
5597 state->print();
5598 };
5599
5600
5601 void MacroAssembler::print_CPU_state() {
5602 push_CPU_state();
5603 push(rsp); // pass CPU state
5604 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5605 addptr(rsp, wordSize); // discard argument
5606 pop_CPU_state();
5607 }
5608
5609 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5610 // Either restore the MXCSR register after returning from the JNI Call
5611 // or verify that it wasn't changed (with -Xcheck:jni flag).
5612 if (VM_Version::supports_sse()) {
5613 if (RestoreMXCSROnJNICalls) {
5614 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5615 } else if (CheckJNICalls) {
5616 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5617 }
5618 }
5619 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5620 vzeroupper();
5621 }
5622
5623 // ((OopHandle)result).resolve();
5624 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5625 assert_different_registers(result, tmp);
5626
5627 // Only 64 bit platforms support GCs that require a tmp register
5628 // Only IN_HEAP loads require a thread_tmp register
5629 // OopHandle::resolve is an indirection like jobject.
5630 access_load_at(T_OBJECT, IN_NATIVE,
5631 result, Address(result, 0), tmp);
5632 }
5633
5634 // ((WeakHandle)result).resolve();
5635 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5636 assert_different_registers(rresult, rtmp);
5637 Label resolved;
5638
5639 // A null weak handle resolves to null.
5640 cmpptr(rresult, 0);
5641 jcc(Assembler::equal, resolved);
5642
5643 // Only 64 bit platforms support GCs that require a tmp register
5644 // Only IN_HEAP loads require a thread_tmp register
5645 // WeakHandle::resolve is an indirection like jweak.
5646 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5647 rresult, Address(rresult, 0), rtmp);
5648 bind(resolved);
5649 }
5650
5651 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5652 // get mirror
5653 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5654 load_method_holder(mirror, method);
5655 movptr(mirror, Address(mirror, mirror_offset));
5656 resolve_oop_handle(mirror, tmp);
5657 }
5658
5659 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5660 load_method_holder(rresult, rmethod);
5661 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5662 }
5663
5664 void MacroAssembler::load_method_holder(Register holder, Register method) {
5665 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5666 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5667 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5668 }
5669
5670 void MacroAssembler::load_metadata(Register dst, Register src) {
5671 if (UseCompactObjectHeaders) {
5672 load_narrow_klass_compact(dst, src);
5673 } else {
5674 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5675 }
5676 }
5677
5678 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5679 assert(UseCompactObjectHeaders, "expect compact object headers");
5680 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5681 shrq(dst, markWord::klass_shift);
5682 }
5683
5684 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5685 assert_different_registers(src, tmp);
5686 assert_different_registers(dst, tmp);
5687
5688 if (UseCompactObjectHeaders) {
5689 load_narrow_klass_compact(dst, src);
5690 decode_klass_not_null(dst, tmp);
5691 } else {
5692 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5693 decode_klass_not_null(dst, tmp);
5694 }
5695 }
5696
5697 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
5698 load_klass(dst, src, tmp);
5699 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5700 }
5701
5702 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5703 assert(!UseCompactObjectHeaders, "not with compact headers");
5704 assert_different_registers(src, tmp);
5705 assert_different_registers(dst, tmp);
5706 encode_klass_not_null(src, tmp);
5707 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5708 }
5709
5710 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5711 if (UseCompactObjectHeaders) {
5712 assert(tmp != noreg, "need tmp");
5713 assert_different_registers(klass, obj, tmp);
5714 load_narrow_klass_compact(tmp, obj);
5715 cmpl(klass, tmp);
5716 } else {
5717 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5718 }
5719 }
5720
5721 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5722 if (UseCompactObjectHeaders) {
5723 assert(tmp2 != noreg, "need tmp2");
5724 assert_different_registers(obj1, obj2, tmp1, tmp2);
5725 load_narrow_klass_compact(tmp1, obj1);
5726 load_narrow_klass_compact(tmp2, obj2);
5727 cmpl(tmp1, tmp2);
5728 } else {
5729 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5730 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5731 }
5732 }
5733
5734 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5735 Register tmp1) {
5736 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5737 decorators = AccessInternal::decorator_fixup(decorators, type);
5738 bool as_raw = (decorators & AS_RAW) != 0;
5739 if (as_raw) {
5740 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1);
5741 } else {
5742 bs->load_at(this, decorators, type, dst, src, tmp1);
5743 }
5744 }
5745
5746 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5747 Register tmp1, Register tmp2, Register tmp3) {
5748 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5749 decorators = AccessInternal::decorator_fixup(decorators, type);
5750 bool as_raw = (decorators & AS_RAW) != 0;
5751 if (as_raw) {
5752 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5753 } else {
5754 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5755 }
5756 }
5757
5758 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5759 Register inline_layout_info) {
5760 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5761 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5762 }
5763
5764 void MacroAssembler::payload_offset(Register inline_klass, Register offset) {
5765 movptr(offset, Address(inline_klass, InlineKlass::adr_members_offset()));
5766 movl(offset, Address(offset, InlineKlass::payload_offset_offset()));
5767 }
5768
5769 void MacroAssembler::payload_addr(Register oop, Register data, Register inline_klass) {
5770 // ((address) (void*) o) + vk->payload_offset();
5771 Register offset = (data == oop) ? rscratch1 : data;
5772 payload_offset(inline_klass, offset);
5773 if (data == oop) {
5774 addptr(data, offset);
5775 } else {
5776 lea(data, Address(oop, offset));
5777 }
5778 }
5779
5780 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
5781 Register index, Register data) {
5782 assert(index != rcx, "index needs to shift by rcx");
5783 assert_different_registers(array, array_klass, index);
5784 assert_different_registers(rcx, array, index);
5785
5786 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
5787 movl(rcx, Address(array_klass, Klass::layout_helper_offset()));
5788
5789 // Klass::layout_helper_log2_element_size(lh)
5790 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
5791 shrl(rcx, Klass::_lh_log2_element_size_shift);
5792 andl(rcx, Klass::_lh_log2_element_size_mask);
5793 shlptr(index); // index << rcx
5794
5795 lea(data, Address(array, index, Address::times_1, arrayOopDesc::base_offset_in_bytes(T_FLAT_ELEMENT)));
5796 }
5797
5798 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5799 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1);
5800 }
5801
5802 // Doesn't do verification, generates fixed size code
5803 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5804 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1);
5805 }
5806
5807 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5808 Register tmp2, Register tmp3, DecoratorSet decorators) {
5809 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5810 }
5811
5812 // Used for storing nulls.
5813 void MacroAssembler::store_heap_oop_null(Address dst) {
5814 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5815 }
5816
5817 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5818 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5819 // Store to klass gap in destination
5820 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5821 }
5822
5823 #ifdef ASSERT
5824 void MacroAssembler::verify_heapbase(const char* msg) {
5825 assert (UseCompressedOops, "should be compressed");
5826 assert (Universe::heap() != nullptr, "java heap should be initialized");
5827 if (CheckCompressedOops) {
5828 Label ok;
5829 ExternalAddress src2(CompressedOops::base_addr());
5830 const bool is_src2_reachable = reachable(src2);
5831 if (!is_src2_reachable) {
5832 push(rscratch1); // cmpptr trashes rscratch1
5833 }
5834 cmpptr(r12_heapbase, src2, rscratch1);
5835 jcc(Assembler::equal, ok);
5836 STOP(msg);
5837 bind(ok);
5838 if (!is_src2_reachable) {
5839 pop(rscratch1);
5840 }
5841 }
5842 }
5843 #endif
5844
5845 // Algorithm must match oop.inline.hpp encode_heap_oop.
5846 void MacroAssembler::encode_heap_oop(Register r) {
5847 #ifdef ASSERT
5848 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5849 #endif
5850 verify_oop_msg(r, "broken oop in encode_heap_oop");
5851 if (CompressedOops::base() == nullptr) {
5852 if (CompressedOops::shift() != 0) {
5853 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5854 shrq(r, LogMinObjAlignmentInBytes);
5855 }
5856 return;
5857 }
5858 testq(r, r);
5859 cmovq(Assembler::equal, r, r12_heapbase);
5860 subq(r, r12_heapbase);
5861 shrq(r, LogMinObjAlignmentInBytes);
5862 }
5863
5864 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5865 #ifdef ASSERT
5866 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5867 if (CheckCompressedOops) {
5868 Label ok;
5869 testq(r, r);
5870 jcc(Assembler::notEqual, ok);
5871 STOP("null oop passed to encode_heap_oop_not_null");
5872 bind(ok);
5873 }
5874 #endif
5875 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5876 if (CompressedOops::base() != nullptr) {
5877 subq(r, r12_heapbase);
5878 }
5879 if (CompressedOops::shift() != 0) {
5880 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5881 shrq(r, LogMinObjAlignmentInBytes);
5882 }
5883 }
5884
5885 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5886 #ifdef ASSERT
5887 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5888 if (CheckCompressedOops) {
5889 Label ok;
5890 testq(src, src);
5891 jcc(Assembler::notEqual, ok);
5892 STOP("null oop passed to encode_heap_oop_not_null2");
5893 bind(ok);
5894 }
5895 #endif
5896 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5897 if (dst != src) {
5898 movq(dst, src);
5899 }
5900 if (CompressedOops::base() != nullptr) {
5901 subq(dst, r12_heapbase);
5902 }
5903 if (CompressedOops::shift() != 0) {
5904 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5905 shrq(dst, LogMinObjAlignmentInBytes);
5906 }
5907 }
5908
5909 void MacroAssembler::decode_heap_oop(Register r) {
5910 #ifdef ASSERT
5911 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5912 #endif
5913 if (CompressedOops::base() == nullptr) {
5914 if (CompressedOops::shift() != 0) {
5915 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5916 shlq(r, LogMinObjAlignmentInBytes);
5917 }
5918 } else {
5919 Label done;
5920 shlq(r, LogMinObjAlignmentInBytes);
5921 jccb(Assembler::equal, done);
5922 addq(r, r12_heapbase);
5923 bind(done);
5924 }
5925 verify_oop_msg(r, "broken oop in decode_heap_oop");
5926 }
5927
5928 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5929 // Note: it will change flags
5930 assert (UseCompressedOops, "should only be used for compressed headers");
5931 assert (Universe::heap() != nullptr, "java heap should be initialized");
5932 // Cannot assert, unverified entry point counts instructions (see .ad file)
5933 // vtableStubs also counts instructions in pd_code_size_limit.
5934 // Also do not verify_oop as this is called by verify_oop.
5935 if (CompressedOops::shift() != 0) {
5936 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5937 shlq(r, LogMinObjAlignmentInBytes);
5938 if (CompressedOops::base() != nullptr) {
5939 addq(r, r12_heapbase);
5940 }
5941 } else {
5942 assert (CompressedOops::base() == nullptr, "sanity");
5943 }
5944 }
5945
5946 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5947 // Note: it will change flags
5948 assert (UseCompressedOops, "should only be used for compressed headers");
5949 assert (Universe::heap() != nullptr, "java heap should be initialized");
5950 // Cannot assert, unverified entry point counts instructions (see .ad file)
5951 // vtableStubs also counts instructions in pd_code_size_limit.
5952 // Also do not verify_oop as this is called by verify_oop.
5953 if (CompressedOops::shift() != 0) {
5954 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5955 if (LogMinObjAlignmentInBytes == Address::times_8) {
5956 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5957 } else {
5958 if (dst != src) {
5959 movq(dst, src);
5960 }
5961 shlq(dst, LogMinObjAlignmentInBytes);
5962 if (CompressedOops::base() != nullptr) {
5963 addq(dst, r12_heapbase);
5964 }
5965 }
5966 } else {
5967 assert (CompressedOops::base() == nullptr, "sanity");
5968 if (dst != src) {
5969 movq(dst, src);
5970 }
5971 }
5972 }
5973
5974 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5975 BLOCK_COMMENT("encode_klass_not_null {");
5976 assert_different_registers(r, tmp);
5977 if (CompressedKlassPointers::base() != nullptr) {
5978 if (AOTCodeCache::is_on_for_dump()) {
5979 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5980 } else {
5981 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5982 }
5983 subq(r, tmp);
5984 }
5985 if (CompressedKlassPointers::shift() != 0) {
5986 shrq(r, CompressedKlassPointers::shift());
5987 }
5988 BLOCK_COMMENT("} encode_klass_not_null");
5989 }
5990
5991 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5992 BLOCK_COMMENT("encode_and_move_klass_not_null {");
5993 assert_different_registers(src, dst);
5994 if (CompressedKlassPointers::base() != nullptr) {
5995 movptr(dst, -(intptr_t)CompressedKlassPointers::base());
5996 addq(dst, src);
5997 } else {
5998 movptr(dst, src);
5999 }
6000 if (CompressedKlassPointers::shift() != 0) {
6001 shrq(dst, CompressedKlassPointers::shift());
6002 }
6003 BLOCK_COMMENT("} encode_and_move_klass_not_null");
6004 }
6005
6006 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
6007 BLOCK_COMMENT("decode_klass_not_null {");
6008 assert_different_registers(r, tmp);
6009 // Note: it will change flags
6010 // Cannot assert, unverified entry point counts instructions (see .ad file)
6011 // vtableStubs also counts instructions in pd_code_size_limit.
6012 // Also do not verify_oop as this is called by verify_oop.
6013 if (CompressedKlassPointers::shift() != 0) {
6014 shlq(r, CompressedKlassPointers::shift());
6015 }
6016 if (CompressedKlassPointers::base() != nullptr) {
6017 if (AOTCodeCache::is_on_for_dump()) {
6018 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
6019 } else {
6020 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
6021 }
6022 addq(r, tmp);
6023 }
6024 BLOCK_COMMENT("} decode_klass_not_null");
6025 }
6026
6027 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
6028 BLOCK_COMMENT("decode_and_move_klass_not_null {");
6029 assert_different_registers(src, dst);
6030 // Note: it will change flags
6031 // Cannot assert, unverified entry point counts instructions (see .ad file)
6032 // vtableStubs also counts instructions in pd_code_size_limit.
6033 // Also do not verify_oop as this is called by verify_oop.
6034
6035 if (CompressedKlassPointers::base() == nullptr &&
6036 CompressedKlassPointers::shift() == 0) {
6037 // The best case scenario is that there is no base or shift. Then it is already
6038 // a pointer that needs nothing but a register rename.
6039 movl(dst, src);
6040 } else {
6041 if (CompressedKlassPointers::shift() <= Address::times_8) {
6042 if (CompressedKlassPointers::base() != nullptr) {
6043 movptr(dst, (intptr_t)CompressedKlassPointers::base());
6044 } else {
6045 xorq(dst, dst);
6046 }
6047 if (CompressedKlassPointers::shift() != 0) {
6048 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
6049 leaq(dst, Address(dst, src, Address::times_8, 0));
6050 } else {
6051 addq(dst, src);
6052 }
6053 } else {
6054 if (CompressedKlassPointers::base() != nullptr) {
6055 const intptr_t base_right_shifted =
6056 (intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
6057 movptr(dst, base_right_shifted);
6058 } else {
6059 xorq(dst, dst);
6060 }
6061 addq(dst, src);
6062 shlq(dst, CompressedKlassPointers::shift());
6063 }
6064 }
6065 BLOCK_COMMENT("} decode_and_move_klass_not_null");
6066 }
6067
6068 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6069 assert (UseCompressedOops, "should only be used for compressed headers");
6070 assert (Universe::heap() != nullptr, "java heap should be initialized");
6071 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6072 int oop_index = oop_recorder()->find_index(obj);
6073 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6074 mov_narrow_oop(dst, oop_index, rspec);
6075 }
6076
6077 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6078 assert (UseCompressedOops, "should only be used for compressed headers");
6079 assert (Universe::heap() != nullptr, "java heap should be initialized");
6080 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6081 int oop_index = oop_recorder()->find_index(obj);
6082 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6083 mov_narrow_oop(dst, oop_index, rspec);
6084 }
6085
6086 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6087 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6088 int klass_index = oop_recorder()->find_index(k);
6089 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6090 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6091 }
6092
6093 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6094 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6095 int klass_index = oop_recorder()->find_index(k);
6096 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6097 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6098 }
6099
6100 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6101 assert (UseCompressedOops, "should only be used for compressed headers");
6102 assert (Universe::heap() != nullptr, "java heap should be initialized");
6103 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6104 int oop_index = oop_recorder()->find_index(obj);
6105 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6106 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6107 }
6108
6109 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6110 assert (UseCompressedOops, "should only be used for compressed headers");
6111 assert (Universe::heap() != nullptr, "java heap should be initialized");
6112 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6113 int oop_index = oop_recorder()->find_index(obj);
6114 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6115 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6116 }
6117
6118 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6119 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6120 int klass_index = oop_recorder()->find_index(k);
6121 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6122 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6123 }
6124
6125 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6126 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6127 int klass_index = oop_recorder()->find_index(k);
6128 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6129 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6130 }
6131
6132 void MacroAssembler::reinit_heapbase() {
6133 if (UseCompressedOops) {
6134 if (Universe::heap() != nullptr) {
6135 if (CompressedOops::base() == nullptr) {
6136 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6137 } else {
6138 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6139 }
6140 } else {
6141 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6142 }
6143 }
6144 }
6145
6146 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6147 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6148 // An inline type might be returned. If fields are in registers we
6149 // need to allocate an inline type instance and initialize it with
6150 // the value of the fields.
6151 Label skip;
6152 // We only need a new buffered inline type if a new one is not returned
6153 testptr(rax, 1);
6154 jcc(Assembler::zero, skip);
6155 int call_offset = -1;
6156
6157 #ifdef _LP64
6158 // The following code is similar to allocate_instance but has some slight differences,
6159 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6160 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
6161 Label slow_case;
6162 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6163 mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
6164 if (vk != nullptr) {
6165 // Called from C1, where the return type is statically known.
6166 movptr(rbx, (intptr_t)vk->get_InlineKlass());
6167 jint lh = vk->layout_helper();
6168 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6169 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6170 tlab_allocate(rax, noreg, lh, r13, r14, slow_case);
6171 } else {
6172 jmp(slow_case);
6173 }
6174 } else {
6175 // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
6176 mov(rbx, rax);
6177 andptr(rbx, -2);
6178 if (UseTLAB) {
6179 movl(r14, Address(rbx, Klass::layout_helper_offset()));
6180 testl(r14, Klass::_lh_instance_slow_path_bit);
6181 jcc(Assembler::notZero, slow_case);
6182 tlab_allocate(rax, r14, 0, r13, r14, slow_case);
6183 } else {
6184 jmp(slow_case);
6185 }
6186 }
6187 if (UseTLAB) {
6188 // 2. Initialize buffered inline instance header
6189 Register buffer_obj = rax;
6190 Register klass = rbx;
6191 if (UseCompactObjectHeaders) {
6192 Register mark_word = r13;
6193 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
6194 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), mark_word);
6195 } else {
6196 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
6197 xorl(r13, r13);
6198 store_klass_gap(buffer_obj, r13);
6199 if (vk == nullptr) {
6200 // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
6201 mov(r13, klass);
6202 }
6203 store_klass(buffer_obj, klass, rscratch1);
6204 klass = r13;
6205 }
6206 // 3. Initialize its fields with an inline class specific handler
6207 if (vk != nullptr) {
6208 call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6209 } else {
6210 movptr(rbx, Address(klass, InlineKlass::adr_members_offset()));
6211 movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
6212 call(rbx);
6213 }
6214 jmp(skip);
6215 }
6216 bind(slow_case);
6217 // We failed to allocate a new inline type, fall back to a runtime
6218 // call. Some oop field may be live in some registers but we can't
6219 // tell. That runtime call will take care of preserving them
6220 // across a GC if there's one.
6221 mov(rax, rscratch1);
6222 #endif
6223
6224 if (from_interpreter) {
6225 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6226 } else {
6227 call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6228 call_offset = offset();
6229 }
6230
6231 bind(skip);
6232 return call_offset;
6233 }
6234
6235 // Move a value between registers/stack slots and update the reg_state
6236 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6237 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6238 if (reg_state[to->value()] == reg_written) {
6239 return true; // Already written
6240 }
6241 if (from != to && bt != T_VOID) {
6242 if (reg_state[to->value()] == reg_readonly) {
6243 return false; // Not yet writable
6244 }
6245 if (from->is_reg()) {
6246 if (to->is_reg()) {
6247 if (from->is_XMMRegister()) {
6248 if (bt == T_DOUBLE) {
6249 movdbl(to->as_XMMRegister(), from->as_XMMRegister());
6250 } else {
6251 assert(bt == T_FLOAT, "must be float");
6252 movflt(to->as_XMMRegister(), from->as_XMMRegister());
6253 }
6254 } else {
6255 movq(to->as_Register(), from->as_Register());
6256 }
6257 } else {
6258 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6259 Address to_addr = Address(rsp, st_off);
6260 if (from->is_XMMRegister()) {
6261 if (bt == T_DOUBLE) {
6262 movdbl(to_addr, from->as_XMMRegister());
6263 } else {
6264 assert(bt == T_FLOAT, "must be float");
6265 movflt(to_addr, from->as_XMMRegister());
6266 }
6267 } else {
6268 movq(to_addr, from->as_Register());
6269 }
6270 }
6271 } else {
6272 Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
6273 if (to->is_reg()) {
6274 if (to->is_XMMRegister()) {
6275 if (bt == T_DOUBLE) {
6276 movdbl(to->as_XMMRegister(), from_addr);
6277 } else {
6278 assert(bt == T_FLOAT, "must be float");
6279 movflt(to->as_XMMRegister(), from_addr);
6280 }
6281 } else {
6282 movq(to->as_Register(), from_addr);
6283 }
6284 } else {
6285 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6286 movq(r13, from_addr);
6287 movq(Address(rsp, st_off), r13);
6288 }
6289 }
6290 }
6291 // Update register states
6292 reg_state[from->value()] = reg_writable;
6293 reg_state[to->value()] = reg_written;
6294 return true;
6295 }
6296
6297 // Calculate the extra stack space required for packing or unpacking inline
6298 // args and adjust the stack pointer (see MacroAssembler::remove_frame).
6299 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6300 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
6301 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6302 assert(sp_inc > 0, "sanity");
6303 // Two additional slots to account for return address
6304 sp_inc += 2 * VMRegImpl::stack_slot_size;
6305
6306 push(rbp);
6307 subptr(rsp, sp_inc);
6308 #ifdef ASSERT
6309 movl(Address(rsp, 0), badRegWordVal);
6310 movl(Address(rsp, VMRegImpl::stack_slot_size), badRegWordVal);
6311 #endif
6312 return sp_inc + wordSize; // account for rbp space
6313 }
6314
6315 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
6316 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6317 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6318 RegState reg_state[]) {
6319 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6320 assert(from->is_valid(), "source must be valid");
6321 bool progress = false;
6322 #ifdef ASSERT
6323 const int start_offset = offset();
6324 #endif
6325
6326 Label L_null, L_notNull;
6327 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6328 Register tmp1 = r10;
6329 Register tmp2 = r13;
6330 Register fromReg = noreg;
6331 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, true);
6332 bool done = true;
6333 bool mark_done = true;
6334 VMReg toReg;
6335 BasicType bt;
6336 // Check if argument requires a null check
6337 bool null_check = false;
6338 VMReg nullCheckReg;
6339 while (stream.next(nullCheckReg, bt)) {
6340 if (sig->at(stream.sig_index())._offset == -1) {
6341 null_check = true;
6342 break;
6343 }
6344 }
6345 stream.reset(sig_index, to_index);
6346 while (stream.next(toReg, bt)) {
6347 assert(toReg->is_valid(), "destination must be valid");
6348 int idx = (int)toReg->value();
6349 if (reg_state[idx] == reg_readonly) {
6350 if (idx != from->value()) {
6351 mark_done = false;
6352 }
6353 done = false;
6354 continue;
6355 } else if (reg_state[idx] == reg_written) {
6356 continue;
6357 }
6358 assert(reg_state[idx] == reg_writable, "must be writable");
6359 reg_state[idx] = reg_written;
6360 progress = true;
6361
6362 if (fromReg == noreg) {
6363 if (from->is_reg()) {
6364 fromReg = from->as_Register();
6365 } else {
6366 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6367 movq(tmp1, Address(rsp, st_off));
6368 fromReg = tmp1;
6369 }
6370 if (null_check) {
6371 // Nullable inline type argument, emit null check
6372 testptr(fromReg, fromReg);
6373 jcc(Assembler::zero, L_null);
6374 }
6375 }
6376 int off = sig->at(stream.sig_index())._offset;
6377 if (off == -1) {
6378 assert(null_check, "Missing null check at");
6379 if (toReg->is_stack()) {
6380 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6381 movq(Address(rsp, st_off), 1);
6382 } else {
6383 movq(toReg->as_Register(), 1);
6384 }
6385 continue;
6386 }
6387 if (sig->at(stream.sig_index())._vt_oop) {
6388 if (toReg->is_stack()) {
6389 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6390 movq(Address(rsp, st_off), fromReg);
6391 } else {
6392 movq(toReg->as_Register(), fromReg);
6393 }
6394 continue;
6395 }
6396 assert(off > 0, "offset in object should be positive");
6397 Address fromAddr = Address(fromReg, off);
6398 if (!toReg->is_XMMRegister()) {
6399 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
6400 if (is_reference_type(bt)) {
6401 load_heap_oop(dst, fromAddr);
6402 } else {
6403 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
6404 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
6405 }
6406 if (toReg->is_stack()) {
6407 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6408 movq(Address(rsp, st_off), dst);
6409 }
6410 } else if (bt == T_DOUBLE) {
6411 movdbl(toReg->as_XMMRegister(), fromAddr);
6412 } else {
6413 assert(bt == T_FLOAT, "must be float");
6414 movflt(toReg->as_XMMRegister(), fromAddr);
6415 }
6416 }
6417 if (progress && null_check) {
6418 if (done) {
6419 jmp(L_notNull);
6420 bind(L_null);
6421 // Set null marker to zero to signal that the argument is null.
6422 // Also set all fields to zero since the runtime requires a canonical
6423 // representation of a flat null.
6424 stream.reset(sig_index, to_index);
6425 while (stream.next(toReg, bt)) {
6426 if (toReg->is_stack()) {
6427 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6428 movq(Address(rsp, st_off), 0);
6429 } else if (toReg->is_XMMRegister()) {
6430 xorps(toReg->as_XMMRegister(), toReg->as_XMMRegister());
6431 } else {
6432 xorl(toReg->as_Register(), toReg->as_Register());
6433 }
6434 }
6435 bind(L_notNull);
6436 } else {
6437 bind(L_null);
6438 }
6439 }
6440
6441 sig_index = stream.sig_index();
6442 to_index = stream.regs_index();
6443
6444 if (mark_done && reg_state[from->value()] != reg_written) {
6445 // This is okay because no one else will write to that slot
6446 reg_state[from->value()] = reg_writable;
6447 }
6448 from_index--;
6449 assert(progress || (start_offset == offset()), "should not emit code");
6450 return done;
6451 }
6452
6453 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
6454 VMRegPair* from, int from_count, int& from_index, VMReg to,
6455 RegState reg_state[], Register val_array) {
6456 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
6457 assert(to->is_valid(), "destination must be valid");
6458
6459 if (reg_state[to->value()] == reg_written) {
6460 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6461 return true; // Already written
6462 }
6463
6464 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
6465 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
6466 Register val_obj_tmp = r11;
6467 Register from_reg_tmp = r14;
6468 Register tmp1 = r10;
6469 Register tmp2 = r13;
6470 Register tmp3 = rbx;
6471 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
6472
6473 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
6474
6475 if (reg_state[to->value()] == reg_readonly) {
6476 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
6477 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6478 return false; // Not yet writable
6479 }
6480 val_obj = val_obj_tmp;
6481 }
6482
6483 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
6484 VMReg fromReg;
6485 BasicType bt;
6486 Label L_null;
6487 while (stream.next(fromReg, bt)) {
6488 assert(fromReg->is_valid(), "source must be valid");
6489 reg_state[fromReg->value()] = reg_writable;
6490
6491 int off = sig->at(stream.sig_index())._offset;
6492 if (off == -1) {
6493 // Nullable inline type argument, emit null check
6494 Label L_notNull;
6495 if (fromReg->is_stack()) {
6496 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6497 testb(Address(rsp, ld_off), 1);
6498 } else {
6499 testb(fromReg->as_Register(), 1);
6500 }
6501 jcc(Assembler::notZero, L_notNull);
6502 movptr(val_obj, 0);
6503 jmp(L_null);
6504 bind(L_notNull);
6505 continue;
6506 }
6507 if (sig->at(stream.sig_index())._vt_oop) {
6508 // buffer argument: use if non null
6509 if (fromReg->is_stack()) {
6510 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6511 movptr(val_obj, Address(rsp, ld_off));
6512 } else {
6513 movptr(val_obj, fromReg->as_Register());
6514 }
6515 testptr(val_obj, val_obj);
6516 jcc(Assembler::notEqual, L_null);
6517 // otherwise get the buffer from the just allocated pool of buffers
6518 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
6519 load_heap_oop(val_obj, Address(val_array, index));
6520 continue;
6521 }
6522
6523 assert(off > 0, "offset in object should be positive");
6524 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
6525
6526 // Pack the scalarized field into the value object.
6527 Address dst(val_obj, off);
6528 if (!fromReg->is_XMMRegister()) {
6529 Register src;
6530 if (fromReg->is_stack()) {
6531 src = from_reg_tmp;
6532 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6533 load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
6534 } else {
6535 src = fromReg->as_Register();
6536 }
6537 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
6538 if (is_reference_type(bt)) {
6539 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep val_obj valid.
6540 mov(tmp3, val_obj);
6541 Address dst_with_tmp3(tmp3, off);
6542 store_heap_oop(dst_with_tmp3, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
6543 } else {
6544 store_sized_value(dst, src, size_in_bytes);
6545 }
6546 } else if (bt == T_DOUBLE) {
6547 movdbl(dst, fromReg->as_XMMRegister());
6548 } else {
6549 assert(bt == T_FLOAT, "must be float");
6550 movflt(dst, fromReg->as_XMMRegister());
6551 }
6552 }
6553 bind(L_null);
6554 sig_index = stream.sig_index();
6555 from_index = stream.regs_index();
6556
6557 assert(reg_state[to->value()] == reg_writable, "must have already been read");
6558 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6559 assert(success, "to register must be writeable");
6560 return true;
6561 }
6562
6563 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6564 return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
6565 }
6566
6567 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
6568 assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6569 if (needs_stack_repair) {
6570 // The method has a scalarized entry point (where fields of value object arguments
6571 // are passed through registers and stack), and a non-scalarized entry point (where
6572 // value object arguments are given as oops). The non-scalarized entry point will
6573 // first load each field of value object arguments and store them in registers and on
6574 // the stack in a way compatible with the scalarized entry point. To do so, some extra
6575 // stack space might be reserved (if argument registers are not enough). On leaving the
6576 // method, this space must be freed.
6577 //
6578 // In case we used the non-scalarized entry point the stack looks like this:
6579 //
6580 // | Arguments from caller |
6581 // |---------------------------| <-- caller's SP
6582 // | Return address #1 |
6583 // | Saved RBP #1 |
6584 // |---------------------------|
6585 // | Extension space for |
6586 // | inline arg (un)packing |
6587 // |---------------------------| <-- start of this method's frame
6588 // | Return address #2 |
6589 // | Saved RBP #2 |
6590 // |---------------------------| <-- RBP (with -XX:+PreserveFramePointer)
6591 // | sp_inc |
6592 // | method locals |
6593 // |---------------------------| <-- SP
6594 //
6595 // Space for the return pc and saved rbp is reserved twice. But only the #1 copies
6596 // contain the real values of return pc and saved rbp. The #2 copies are not reliable
6597 // and should not be used. They are mostly needed to add space between the extension
6598 // space and the locals, as there would be between the real arguments and the locals
6599 // if we don't need to do unpacking (from the scalarized entry point).
6600 //
6601 // When leaving, one must load RBP #1 into RBP, and use the copy #1 of the return address,
6602 // while keeping in mind that from the scalarized entry point, there will be only one
6603 // copy. Indeed, in the case we used the scalarized calling convention, the stack looks like this:
6604 //
6605 // | Arguments from caller |
6606 // |---------------------------| <-- caller's SP
6607 // | Return address |
6608 // | Saved RBP |
6609 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer)
6610 // | sp_inc |
6611 // | method locals |
6612 // |---------------------------| <-- SP
6613 //
6614 // The sp_inc stack slot holds the total size of the frame, including the extension
6615 // space and copies #2 of the return address and the saved RBP (but never the copies
6616 // #1 of the return address and saved RBP). That is how to find the copies #1 of the
6617 // return address and saved rbp. This size is expressed in bytes. Be careful when using
6618 // it from C++ in pointer arithmetic you might need to divide it by wordSize.
6619
6620 // The stack increment resides just below the saved rbp
6621 addq(rsp, Address(rsp, initial_framesize - wordSize));
6622 pop(rbp);
6623 } else {
6624 if (initial_framesize > 0) {
6625 addq(rsp, initial_framesize);
6626 }
6627 pop(rbp);
6628 }
6629 }
6630
6631 #if COMPILER2_OR_JVMCI
6632
6633 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6634 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
6635 // cnt - number of qwords (8-byte words).
6636 // base - start address, qword aligned.
6637 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6638 bool use64byteVector = (MaxVectorSize == 64) && (CopyAVX3Threshold == 0);
6639 if (use64byteVector) {
6640 evpbroadcastq(xtmp, val, AVX_512bit);
6641 } else if (MaxVectorSize >= 32) {
6642 movdq(xtmp, val);
6643 punpcklqdq(xtmp, xtmp);
6644 vinserti128_high(xtmp, xtmp);
6645 } else {
6646 movdq(xtmp, val);
6647 punpcklqdq(xtmp, xtmp);
6648 }
6649 jmp(L_zero_64_bytes);
6650
6651 BIND(L_loop);
6652 if (MaxVectorSize >= 32) {
6653 fill64(base, 0, xtmp, use64byteVector);
6654 } else {
6655 movdqu(Address(base, 0), xtmp);
6656 movdqu(Address(base, 16), xtmp);
6657 movdqu(Address(base, 32), xtmp);
6658 movdqu(Address(base, 48), xtmp);
6659 }
6660 addptr(base, 64);
6661
6662 BIND(L_zero_64_bytes);
6663 subptr(cnt, 8);
6664 jccb(Assembler::greaterEqual, L_loop);
6665
6666 // Copy trailing 64 bytes
6667 if (use64byteVector) {
6668 addptr(cnt, 8);
6669 jccb(Assembler::equal, L_end);
6670 fill64_masked(3, base, 0, xtmp, mask, cnt, val, true);
6671 jmp(L_end);
6672 } else {
6673 addptr(cnt, 4);
6674 jccb(Assembler::less, L_tail);
6675 if (MaxVectorSize >= 32) {
6676 vmovdqu(Address(base, 0), xtmp);
6677 } else {
6678 movdqu(Address(base, 0), xtmp);
6679 movdqu(Address(base, 16), xtmp);
6680 }
6681 }
6682 addptr(base, 32);
6683 subptr(cnt, 4);
6684
6685 BIND(L_tail);
6686 addptr(cnt, 4);
6687 jccb(Assembler::lessEqual, L_end);
6688 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6689 fill32_masked(3, base, 0, xtmp, mask, cnt, val);
6690 } else {
6691 decrement(cnt);
6692
6693 BIND(L_sloop);
6694 movq(Address(base, 0), xtmp);
6695 addptr(base, 8);
6696 decrement(cnt);
6697 jccb(Assembler::greaterEqual, L_sloop);
6698 }
6699 BIND(L_end);
6700 }
6701
6702 // Clearing constant sized memory using YMM/ZMM registers.
6703 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6704 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6705 bool use64byteVector = (MaxVectorSize > 32) && (CopyAVX3Threshold == 0);
6706
6707 int vector64_count = (cnt & (~0x7)) >> 3;
6708 cnt = cnt & 0x7;
6709 const int fill64_per_loop = 4;
6710 const int max_unrolled_fill64 = 8;
6711
6712 // 64 byte initialization loop.
6713 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6714 int start64 = 0;
6715 if (vector64_count > max_unrolled_fill64) {
6716 Label LOOP;
6717 Register index = rtmp;
6718
6719 start64 = vector64_count - (vector64_count % fill64_per_loop);
6720
6721 movl(index, 0);
6722 BIND(LOOP);
6723 for (int i = 0; i < fill64_per_loop; i++) {
6724 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6725 }
6726 addl(index, fill64_per_loop * 64);
6727 cmpl(index, start64 * 64);
6728 jccb(Assembler::less, LOOP);
6729 }
6730 for (int i = start64; i < vector64_count; i++) {
6731 fill64(base, i * 64, xtmp, use64byteVector);
6732 }
6733
6734 // Clear remaining 64 byte tail.
6735 int disp = vector64_count * 64;
6736 if (cnt) {
6737 switch (cnt) {
6738 case 1:
6739 movq(Address(base, disp), xtmp);
6740 break;
6741 case 2:
6742 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6743 break;
6744 case 3:
6745 movl(rtmp, 0x7);
6746 kmovwl(mask, rtmp);
6747 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6748 break;
6749 case 4:
6750 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6751 break;
6752 case 5:
6753 if (use64byteVector) {
6754 movl(rtmp, 0x1F);
6755 kmovwl(mask, rtmp);
6756 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6757 } else {
6758 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6759 movq(Address(base, disp + 32), xtmp);
6760 }
6761 break;
6762 case 6:
6763 if (use64byteVector) {
6764 movl(rtmp, 0x3F);
6765 kmovwl(mask, rtmp);
6766 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6767 } else {
6768 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6769 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6770 }
6771 break;
6772 case 7:
6773 if (use64byteVector) {
6774 movl(rtmp, 0x7F);
6775 kmovwl(mask, rtmp);
6776 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6777 } else {
6778 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6779 movl(rtmp, 0x7);
6780 kmovwl(mask, rtmp);
6781 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6782 }
6783 break;
6784 default:
6785 fatal("Unexpected length : %d\n",cnt);
6786 break;
6787 }
6788 }
6789 }
6790
6791 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
6792 bool is_large, bool word_copy_only, KRegister mask) {
6793 // cnt - number of qwords (8-byte words).
6794 // base - start address, qword aligned.
6795 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6796 assert(base==rdi, "base register must be edi for rep stos");
6797 assert(val==rax, "val register must be eax for rep stos");
6798 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6799 assert(InitArrayShortSize % BytesPerLong == 0,
6800 "InitArrayShortSize should be the multiple of BytesPerLong");
6801
6802 Label DONE;
6803
6804 if (!is_large) {
6805 Label LOOP, LONG;
6806 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6807 jccb(Assembler::greater, LONG);
6808
6809 decrement(cnt);
6810 jccb(Assembler::negative, DONE); // Zero length
6811
6812 // Use individual pointer-sized stores for small counts:
6813 BIND(LOOP);
6814 movptr(Address(base, cnt, Address::times_ptr), val);
6815 decrement(cnt);
6816 jccb(Assembler::greaterEqual, LOOP);
6817 jmpb(DONE);
6818
6819 BIND(LONG);
6820 }
6821
6822 // Use longer rep-prefixed ops for non-small counts:
6823 if (UseFastStosb && !word_copy_only) {
6824 shlptr(cnt, 3); // convert to number of bytes
6825 rep_stosb();
6826 } else if (UseXMMForObjInit) {
6827 xmm_clear_mem(base, cnt, val, xtmp, mask);
6828 } else {
6829 rep_stos();
6830 }
6831
6832 BIND(DONE);
6833 }
6834
6835 #endif //COMPILER2_OR_JVMCI
6836
6837
6838 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6839 Register to, Register value, Register count,
6840 Register rtmp, XMMRegister xtmp) {
6841 ShortBranchVerifier sbv(this);
6842 assert_different_registers(to, value, count, rtmp);
6843 Label L_exit;
6844 Label L_fill_2_bytes, L_fill_4_bytes;
6845
6846 #if defined(COMPILER2)
6847 if(MaxVectorSize >=32 &&
6848 VM_Version::supports_avx512vlbw() &&
6849 VM_Version::supports_bmi2()) {
6850 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6851 return;
6852 }
6853 #endif
6854
6855 int shift = -1;
6856 switch (t) {
6857 case T_BYTE:
6858 shift = 2;
6859 break;
6860 case T_SHORT:
6861 shift = 1;
6862 break;
6863 case T_INT:
6864 shift = 0;
6865 break;
6866 default: ShouldNotReachHere();
6867 }
6868
6869 if (t == T_BYTE) {
6870 andl(value, 0xff);
6871 movl(rtmp, value);
6872 shll(rtmp, 8);
6873 orl(value, rtmp);
6874 }
6875 if (t == T_SHORT) {
6876 andl(value, 0xffff);
6877 }
6878 if (t == T_BYTE || t == T_SHORT) {
6879 movl(rtmp, value);
6880 shll(rtmp, 16);
6881 orl(value, rtmp);
6882 }
6883
6884 cmpptr(count, 8 << shift); // Short arrays (< 32 bytes) fill by element
6885 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6886 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6887 Label L_skip_align2;
6888 // align source address at 4 bytes address boundary
6889 if (t == T_BYTE) {
6890 Label L_skip_align1;
6891 // One byte misalignment happens only for byte arrays
6892 testptr(to, 1);
6893 jccb(Assembler::zero, L_skip_align1);
6894 movb(Address(to, 0), value);
6895 increment(to);
6896 decrement(count);
6897 BIND(L_skip_align1);
6898 }
6899 // Two bytes misalignment happens only for byte and short (char) arrays
6900 testptr(to, 2);
6901 jccb(Assembler::zero, L_skip_align2);
6902 movw(Address(to, 0), value);
6903 addptr(to, 2);
6904 subptr(count, 1<<(shift-1));
6905 BIND(L_skip_align2);
6906 }
6907 {
6908 Label L_fill_32_bytes;
6909 if (!UseUnalignedLoadStores) {
6910 // align to 8 bytes, we know we are 4 byte aligned to start
6911 testptr(to, 4);
6912 jccb(Assembler::zero, L_fill_32_bytes);
6913 movl(Address(to, 0), value);
6914 addptr(to, 4);
6915 subptr(count, 1<<shift);
6916 }
6917 BIND(L_fill_32_bytes);
6918 {
6919 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6920 movdl(xtmp, value);
6921 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6922 Label L_check_fill_32_bytes;
6923 if (UseAVX > 2) {
6924 // Fill 64-byte chunks
6925 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6926
6927 // If number of bytes to fill < CopyAVX3Threshold, perform fill using AVX2
6928 cmpptr(count, CopyAVX3Threshold);
6929 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6930
6931 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6932
6933 subptr(count, 16 << shift);
6934 jcc(Assembler::less, L_check_fill_32_bytes);
6935 align(16);
6936
6937 BIND(L_fill_64_bytes_loop_avx3);
6938 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6939 addptr(to, 64);
6940 subptr(count, 16 << shift);
6941 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6942 jmpb(L_check_fill_32_bytes);
6943
6944 BIND(L_check_fill_64_bytes_avx2);
6945 }
6946 // Fill 64-byte chunks
6947 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6948
6949 subptr(count, 16 << shift);
6950 jcc(Assembler::less, L_check_fill_32_bytes);
6951
6952 // align data for 64-byte chunks
6953 Label L_fill_64_bytes_loop, L_align_64_bytes_loop;
6954 if (EnableX86ECoreOpts) {
6955 // align 'big' arrays to cache lines to minimize split_stores
6956 cmpptr(count, 96 << shift);
6957 jcc(Assembler::below, L_fill_64_bytes_loop);
6958
6959 // Find the bytes needed for alignment
6960 movptr(rtmp, to);
6961 andptr(rtmp, 0x1c);
6962 jcc(Assembler::zero, L_fill_64_bytes_loop);
6963 negptr(rtmp); // number of bytes to fill 32-rtmp. it filled by 2 mov by 32
6964 addptr(rtmp, 32);
6965 shrptr(rtmp, 2 - shift);// get number of elements from bytes
6966 subptr(count, rtmp); // adjust count by number of elements
6967
6968 align(16);
6969 BIND(L_align_64_bytes_loop);
6970 movdl(Address(to, 0), xtmp);
6971 addptr(to, 4);
6972 subptr(rtmp, 1 << shift);
6973 jcc(Assembler::greater, L_align_64_bytes_loop);
6974 }
6975
6976 align(16);
6977 BIND(L_fill_64_bytes_loop);
6978 vmovdqu(Address(to, 0), xtmp);
6979 vmovdqu(Address(to, 32), xtmp);
6980 addptr(to, 64);
6981 subptr(count, 16 << shift);
6982 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6983
6984 align(16);
6985 BIND(L_check_fill_32_bytes);
6986 addptr(count, 8 << shift);
6987 jccb(Assembler::less, L_check_fill_8_bytes);
6988 vmovdqu(Address(to, 0), xtmp);
6989 addptr(to, 32);
6990 subptr(count, 8 << shift);
6991
6992 BIND(L_check_fill_8_bytes);
6993 // clean upper bits of YMM registers
6994 movdl(xtmp, value);
6995 pshufd(xtmp, xtmp, 0);
6996 } else {
6997 // Fill 32-byte chunks
6998 pshufd(xtmp, xtmp, 0);
6999
7000 subptr(count, 8 << shift);
7001 jcc(Assembler::less, L_check_fill_8_bytes);
7002 align(16);
7003
7004 BIND(L_fill_32_bytes_loop);
7005
7006 if (UseUnalignedLoadStores) {
7007 movdqu(Address(to, 0), xtmp);
7008 movdqu(Address(to, 16), xtmp);
7009 } else {
7010 movq(Address(to, 0), xtmp);
7011 movq(Address(to, 8), xtmp);
7012 movq(Address(to, 16), xtmp);
7013 movq(Address(to, 24), xtmp);
7014 }
7015
7016 addptr(to, 32);
7017 subptr(count, 8 << shift);
7018 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
7019
7020 BIND(L_check_fill_8_bytes);
7021 }
7022 addptr(count, 8 << shift);
7023 jccb(Assembler::zero, L_exit);
7024 jmpb(L_fill_8_bytes);
7025
7026 //
7027 // length is too short, just fill qwords
7028 //
7029 align(16);
7030 BIND(L_fill_8_bytes_loop);
7031 movq(Address(to, 0), xtmp);
7032 addptr(to, 8);
7033 BIND(L_fill_8_bytes);
7034 subptr(count, 1 << (shift + 1));
7035 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
7036 }
7037 }
7038
7039 Label L_fill_4_bytes_loop;
7040 testl(count, 1 << shift);
7041 jccb(Assembler::zero, L_fill_2_bytes);
7042
7043 align(16);
7044 BIND(L_fill_4_bytes_loop);
7045 movl(Address(to, 0), value);
7046 addptr(to, 4);
7047
7048 BIND(L_fill_4_bytes);
7049 subptr(count, 1 << shift);
7050 jccb(Assembler::greaterEqual, L_fill_4_bytes_loop);
7051
7052 if (t == T_BYTE || t == T_SHORT) {
7053 Label L_fill_byte;
7054 BIND(L_fill_2_bytes);
7055 // fill trailing 2 bytes
7056 testl(count, 1<<(shift-1));
7057 jccb(Assembler::zero, L_fill_byte);
7058 movw(Address(to, 0), value);
7059 if (t == T_BYTE) {
7060 addptr(to, 2);
7061 BIND(L_fill_byte);
7062 // fill trailing byte
7063 testl(count, 1);
7064 jccb(Assembler::zero, L_exit);
7065 movb(Address(to, 0), value);
7066 } else {
7067 BIND(L_fill_byte);
7068 }
7069 } else {
7070 BIND(L_fill_2_bytes);
7071 }
7072 BIND(L_exit);
7073 }
7074
7075 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
7076 switch(type) {
7077 case T_BYTE:
7078 case T_BOOLEAN:
7079 evpbroadcastb(dst, src, vector_len);
7080 break;
7081 case T_SHORT:
7082 case T_CHAR:
7083 evpbroadcastw(dst, src, vector_len);
7084 break;
7085 case T_INT:
7086 case T_FLOAT:
7087 evpbroadcastd(dst, src, vector_len);
7088 break;
7089 case T_LONG:
7090 case T_DOUBLE:
7091 evpbroadcastq(dst, src, vector_len);
7092 break;
7093 default:
7094 fatal("Unhandled type : %s", type2name(type));
7095 break;
7096 }
7097 }
7098
7099 // Encode given char[]/byte[] to byte[] in ISO_8859_1 or ASCII
7100 //
7101 // @IntrinsicCandidate
7102 // int sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(
7103 // char[] sa, int sp, byte[] da, int dp, int len) {
7104 // int i = 0;
7105 // for (; i < len; i++) {
7106 // char c = sa[sp++];
7107 // if (c > '\u00FF')
7108 // break;
7109 // da[dp++] = (byte) c;
7110 // }
7111 // return i;
7112 // }
7113 //
7114 // @IntrinsicCandidate
7115 // int java.lang.StringCoding.encodeISOArray0(
7116 // byte[] sa, int sp, byte[] da, int dp, int len) {
7117 // int i = 0;
7118 // for (; i < len; i++) {
7119 // char c = StringUTF16.getChar(sa, sp++);
7120 // if (c > '\u00FF')
7121 // break;
7122 // da[dp++] = (byte) c;
7123 // }
7124 // return i;
7125 // }
7126 //
7127 // @IntrinsicCandidate
7128 // int java.lang.StringCoding.encodeAsciiArray0(
7129 // char[] sa, int sp, byte[] da, int dp, int len) {
7130 // int i = 0;
7131 // for (; i < len; i++) {
7132 // char c = sa[sp++];
7133 // if (c >= '\u0080')
7134 // break;
7135 // da[dp++] = (byte) c;
7136 // }
7137 // return i;
7138 // }
7139 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7140 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7141 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7142 Register tmp5, Register result, bool ascii) {
7143
7144 // rsi: src
7145 // rdi: dst
7146 // rdx: len
7147 // rcx: tmp5
7148 // rax: result
7149 ShortBranchVerifier sbv(this);
7150 assert_different_registers(src, dst, len, tmp5, result);
7151 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7152
7153 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
7154 int short_mask = ascii ? 0xff80 : 0xff00;
7155
7156 // set result
7157 xorl(result, result);
7158 // check for zero length
7159 testl(len, len);
7160 jcc(Assembler::zero, L_done);
7161
7162 movl(result, len);
7163
7164 // Setup pointers
7165 lea(src, Address(src, len, Address::times_2)); // char[]
7166 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7167 negptr(len);
7168
7169 if (UseSSE42Intrinsics || UseAVX >= 2) {
7170 Label L_copy_8_chars, L_copy_8_chars_exit;
7171 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7172
7173 if (UseAVX >= 2) {
7174 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7175 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7176 movdl(tmp1Reg, tmp5);
7177 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7178 jmp(L_chars_32_check);
7179
7180 bind(L_copy_32_chars);
7181 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7182 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7183 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7184 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7185 jccb(Assembler::notZero, L_copy_32_chars_exit);
7186 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7187 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7188 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7189
7190 bind(L_chars_32_check);
7191 addptr(len, 32);
7192 jcc(Assembler::lessEqual, L_copy_32_chars);
7193
7194 bind(L_copy_32_chars_exit);
7195 subptr(len, 16);
7196 jccb(Assembler::greater, L_copy_16_chars_exit);
7197
7198 } else if (UseSSE42Intrinsics) {
7199 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7200 movdl(tmp1Reg, tmp5);
7201 pshufd(tmp1Reg, tmp1Reg, 0);
7202 jmpb(L_chars_16_check);
7203 }
7204
7205 bind(L_copy_16_chars);
7206 if (UseAVX >= 2) {
7207 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7208 vptest(tmp2Reg, tmp1Reg);
7209 jcc(Assembler::notZero, L_copy_16_chars_exit);
7210 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7211 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7212 } else {
7213 if (UseAVX > 0) {
7214 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7215 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7216 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7217 } else {
7218 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7219 por(tmp2Reg, tmp3Reg);
7220 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7221 por(tmp2Reg, tmp4Reg);
7222 }
7223 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7224 jccb(Assembler::notZero, L_copy_16_chars_exit);
7225 packuswb(tmp3Reg, tmp4Reg);
7226 }
7227 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7228
7229 bind(L_chars_16_check);
7230 addptr(len, 16);
7231 jcc(Assembler::lessEqual, L_copy_16_chars);
7232
7233 bind(L_copy_16_chars_exit);
7234 if (UseAVX >= 2) {
7235 // clean upper bits of YMM registers
7236 vpxor(tmp2Reg, tmp2Reg);
7237 vpxor(tmp3Reg, tmp3Reg);
7238 vpxor(tmp4Reg, tmp4Reg);
7239 movdl(tmp1Reg, tmp5);
7240 pshufd(tmp1Reg, tmp1Reg, 0);
7241 }
7242 subptr(len, 8);
7243 jccb(Assembler::greater, L_copy_8_chars_exit);
7244
7245 bind(L_copy_8_chars);
7246 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7247 ptest(tmp3Reg, tmp1Reg);
7248 jccb(Assembler::notZero, L_copy_8_chars_exit);
7249 packuswb(tmp3Reg, tmp1Reg);
7250 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7251 addptr(len, 8);
7252 jccb(Assembler::lessEqual, L_copy_8_chars);
7253
7254 bind(L_copy_8_chars_exit);
7255 subptr(len, 8);
7256 jccb(Assembler::zero, L_done);
7257 }
7258
7259 bind(L_copy_1_char);
7260 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7261 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7262 jccb(Assembler::notZero, L_copy_1_char_exit);
7263 movb(Address(dst, len, Address::times_1, 0), tmp5);
7264 addptr(len, 1);
7265 jccb(Assembler::less, L_copy_1_char);
7266
7267 bind(L_copy_1_char_exit);
7268 addptr(result, len); // len is negative count of not processed elements
7269
7270 bind(L_done);
7271 }
7272
7273 /**
7274 * Helper for multiply_to_len().
7275 */
7276 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7277 addq(dest_lo, src1);
7278 adcq(dest_hi, 0);
7279 addq(dest_lo, src2);
7280 adcq(dest_hi, 0);
7281 }
7282
7283 /**
7284 * Multiply 64 bit by 64 bit first loop.
7285 */
7286 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7287 Register y, Register y_idx, Register z,
7288 Register carry, Register product,
7289 Register idx, Register kdx) {
7290 //
7291 // jlong carry, x[], y[], z[];
7292 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7293 // huge_128 product = y[idx] * x[xstart] + carry;
7294 // z[kdx] = (jlong)product;
7295 // carry = (jlong)(product >>> 64);
7296 // }
7297 // z[xstart] = carry;
7298 //
7299
7300 Label L_first_loop, L_first_loop_exit;
7301 Label L_one_x, L_one_y, L_multiply;
7302
7303 decrementl(xstart);
7304 jcc(Assembler::negative, L_one_x);
7305
7306 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7307 rorq(x_xstart, 32); // convert big-endian to little-endian
7308
7309 bind(L_first_loop);
7310 decrementl(idx);
7311 jcc(Assembler::negative, L_first_loop_exit);
7312 decrementl(idx);
7313 jcc(Assembler::negative, L_one_y);
7314 movq(y_idx, Address(y, idx, Address::times_4, 0));
7315 rorq(y_idx, 32); // convert big-endian to little-endian
7316 bind(L_multiply);
7317 movq(product, x_xstart);
7318 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7319 addq(product, carry);
7320 adcq(rdx, 0);
7321 subl(kdx, 2);
7322 movl(Address(z, kdx, Address::times_4, 4), product);
7323 shrq(product, 32);
7324 movl(Address(z, kdx, Address::times_4, 0), product);
7325 movq(carry, rdx);
7326 jmp(L_first_loop);
7327
7328 bind(L_one_y);
7329 movl(y_idx, Address(y, 0));
7330 jmp(L_multiply);
7331
7332 bind(L_one_x);
7333 movl(x_xstart, Address(x, 0));
7334 jmp(L_first_loop);
7335
7336 bind(L_first_loop_exit);
7337 }
7338
7339 /**
7340 * Multiply 64 bit by 64 bit and add 128 bit.
7341 */
7342 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7343 Register yz_idx, Register idx,
7344 Register carry, Register product, int offset) {
7345 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7346 // z[kdx] = (jlong)product;
7347
7348 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7349 rorq(yz_idx, 32); // convert big-endian to little-endian
7350 movq(product, x_xstart);
7351 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7352 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7353 rorq(yz_idx, 32); // convert big-endian to little-endian
7354
7355 add2_with_carry(rdx, product, carry, yz_idx);
7356
7357 movl(Address(z, idx, Address::times_4, offset+4), product);
7358 shrq(product, 32);
7359 movl(Address(z, idx, Address::times_4, offset), product);
7360
7361 }
7362
7363 /**
7364 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7365 */
7366 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7367 Register yz_idx, Register idx, Register jdx,
7368 Register carry, Register product,
7369 Register carry2) {
7370 // jlong carry, x[], y[], z[];
7371 // int kdx = ystart+1;
7372 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7373 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7374 // z[kdx+idx+1] = (jlong)product;
7375 // jlong carry2 = (jlong)(product >>> 64);
7376 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7377 // z[kdx+idx] = (jlong)product;
7378 // carry = (jlong)(product >>> 64);
7379 // }
7380 // idx += 2;
7381 // if (idx > 0) {
7382 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7383 // z[kdx+idx] = (jlong)product;
7384 // carry = (jlong)(product >>> 64);
7385 // }
7386 //
7387
7388 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7389
7390 movl(jdx, idx);
7391 andl(jdx, 0xFFFFFFFC);
7392 shrl(jdx, 2);
7393
7394 bind(L_third_loop);
7395 subl(jdx, 1);
7396 jcc(Assembler::negative, L_third_loop_exit);
7397 subl(idx, 4);
7398
7399 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7400 movq(carry2, rdx);
7401
7402 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7403 movq(carry, rdx);
7404 jmp(L_third_loop);
7405
7406 bind (L_third_loop_exit);
7407
7408 andl (idx, 0x3);
7409 jcc(Assembler::zero, L_post_third_loop_done);
7410
7411 Label L_check_1;
7412 subl(idx, 2);
7413 jcc(Assembler::negative, L_check_1);
7414
7415 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7416 movq(carry, rdx);
7417
7418 bind (L_check_1);
7419 addl (idx, 0x2);
7420 andl (idx, 0x1);
7421 subl(idx, 1);
7422 jcc(Assembler::negative, L_post_third_loop_done);
7423
7424 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7425 movq(product, x_xstart);
7426 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7427 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7428
7429 add2_with_carry(rdx, product, yz_idx, carry);
7430
7431 movl(Address(z, idx, Address::times_4, 0), product);
7432 shrq(product, 32);
7433
7434 shlq(rdx, 32);
7435 orq(product, rdx);
7436 movq(carry, product);
7437
7438 bind(L_post_third_loop_done);
7439 }
7440
7441 /**
7442 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7443 *
7444 */
7445 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7446 Register carry, Register carry2,
7447 Register idx, Register jdx,
7448 Register yz_idx1, Register yz_idx2,
7449 Register tmp, Register tmp3, Register tmp4) {
7450 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7451
7452 // jlong carry, x[], y[], z[];
7453 // int kdx = ystart+1;
7454 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7455 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7456 // jlong carry2 = (jlong)(tmp3 >>> 64);
7457 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7458 // carry = (jlong)(tmp4 >>> 64);
7459 // z[kdx+idx+1] = (jlong)tmp3;
7460 // z[kdx+idx] = (jlong)tmp4;
7461 // }
7462 // idx += 2;
7463 // if (idx > 0) {
7464 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7465 // z[kdx+idx] = (jlong)yz_idx1;
7466 // carry = (jlong)(yz_idx1 >>> 64);
7467 // }
7468 //
7469
7470 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7471
7472 movl(jdx, idx);
7473 andl(jdx, 0xFFFFFFFC);
7474 shrl(jdx, 2);
7475
7476 bind(L_third_loop);
7477 subl(jdx, 1);
7478 jcc(Assembler::negative, L_third_loop_exit);
7479 subl(idx, 4);
7480
7481 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7482 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7483 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7484 rorxq(yz_idx2, yz_idx2, 32);
7485
7486 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7487 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7488
7489 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7490 rorxq(yz_idx1, yz_idx1, 32);
7491 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7492 rorxq(yz_idx2, yz_idx2, 32);
7493
7494 if (VM_Version::supports_adx()) {
7495 adcxq(tmp3, carry);
7496 adoxq(tmp3, yz_idx1);
7497
7498 adcxq(tmp4, tmp);
7499 adoxq(tmp4, yz_idx2);
7500
7501 movl(carry, 0); // does not affect flags
7502 adcxq(carry2, carry);
7503 adoxq(carry2, carry);
7504 } else {
7505 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7506 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7507 }
7508 movq(carry, carry2);
7509
7510 movl(Address(z, idx, Address::times_4, 12), tmp3);
7511 shrq(tmp3, 32);
7512 movl(Address(z, idx, Address::times_4, 8), tmp3);
7513
7514 movl(Address(z, idx, Address::times_4, 4), tmp4);
7515 shrq(tmp4, 32);
7516 movl(Address(z, idx, Address::times_4, 0), tmp4);
7517
7518 jmp(L_third_loop);
7519
7520 bind (L_third_loop_exit);
7521
7522 andl (idx, 0x3);
7523 jcc(Assembler::zero, L_post_third_loop_done);
7524
7525 Label L_check_1;
7526 subl(idx, 2);
7527 jcc(Assembler::negative, L_check_1);
7528
7529 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7530 rorxq(yz_idx1, yz_idx1, 32);
7531 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7532 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7533 rorxq(yz_idx2, yz_idx2, 32);
7534
7535 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7536
7537 movl(Address(z, idx, Address::times_4, 4), tmp3);
7538 shrq(tmp3, 32);
7539 movl(Address(z, idx, Address::times_4, 0), tmp3);
7540 movq(carry, tmp4);
7541
7542 bind (L_check_1);
7543 addl (idx, 0x2);
7544 andl (idx, 0x1);
7545 subl(idx, 1);
7546 jcc(Assembler::negative, L_post_third_loop_done);
7547 movl(tmp4, Address(y, idx, Address::times_4, 0));
7548 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7549 movl(tmp4, Address(z, idx, Address::times_4, 0));
7550
7551 add2_with_carry(carry2, tmp3, tmp4, carry);
7552
7553 movl(Address(z, idx, Address::times_4, 0), tmp3);
7554 shrq(tmp3, 32);
7555
7556 shlq(carry2, 32);
7557 orq(tmp3, carry2);
7558 movq(carry, tmp3);
7559
7560 bind(L_post_third_loop_done);
7561 }
7562
7563 /**
7564 * Code for BigInteger::multiplyToLen() intrinsic.
7565 *
7566 * rdi: x
7567 * rax: xlen
7568 * rsi: y
7569 * rcx: ylen
7570 * r8: z
7571 * r11: tmp0
7572 * r12: tmp1
7573 * r13: tmp2
7574 * r14: tmp3
7575 * r15: tmp4
7576 * rbx: tmp5
7577 *
7578 */
7579 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7580 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7581 ShortBranchVerifier sbv(this);
7582 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7583
7584 push(tmp0);
7585 push(tmp1);
7586 push(tmp2);
7587 push(tmp3);
7588 push(tmp4);
7589 push(tmp5);
7590
7591 push(xlen);
7592
7593 const Register idx = tmp1;
7594 const Register kdx = tmp2;
7595 const Register xstart = tmp3;
7596
7597 const Register y_idx = tmp4;
7598 const Register carry = tmp5;
7599 const Register product = xlen;
7600 const Register x_xstart = tmp0;
7601
7602 // First Loop.
7603 //
7604 // final static long LONG_MASK = 0xffffffffL;
7605 // int xstart = xlen - 1;
7606 // int ystart = ylen - 1;
7607 // long carry = 0;
7608 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7609 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7610 // z[kdx] = (int)product;
7611 // carry = product >>> 32;
7612 // }
7613 // z[xstart] = (int)carry;
7614 //
7615
7616 movl(idx, ylen); // idx = ylen;
7617 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7618 xorq(carry, carry); // carry = 0;
7619
7620 Label L_done;
7621
7622 movl(xstart, xlen);
7623 decrementl(xstart);
7624 jcc(Assembler::negative, L_done);
7625
7626 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7627
7628 Label L_second_loop;
7629 testl(kdx, kdx);
7630 jcc(Assembler::zero, L_second_loop);
7631
7632 Label L_carry;
7633 subl(kdx, 1);
7634 jcc(Assembler::zero, L_carry);
7635
7636 movl(Address(z, kdx, Address::times_4, 0), carry);
7637 shrq(carry, 32);
7638 subl(kdx, 1);
7639
7640 bind(L_carry);
7641 movl(Address(z, kdx, Address::times_4, 0), carry);
7642
7643 // Second and third (nested) loops.
7644 //
7645 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7646 // carry = 0;
7647 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7648 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7649 // (z[k] & LONG_MASK) + carry;
7650 // z[k] = (int)product;
7651 // carry = product >>> 32;
7652 // }
7653 // z[i] = (int)carry;
7654 // }
7655 //
7656 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7657
7658 const Register jdx = tmp1;
7659
7660 bind(L_second_loop);
7661 xorl(carry, carry); // carry = 0;
7662 movl(jdx, ylen); // j = ystart+1
7663
7664 subl(xstart, 1); // i = xstart-1;
7665 jcc(Assembler::negative, L_done);
7666
7667 push (z);
7668
7669 Label L_last_x;
7670 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7671 subl(xstart, 1); // i = xstart-1;
7672 jcc(Assembler::negative, L_last_x);
7673
7674 if (UseBMI2Instructions) {
7675 movq(rdx, Address(x, xstart, Address::times_4, 0));
7676 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7677 } else {
7678 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7679 rorq(x_xstart, 32); // convert big-endian to little-endian
7680 }
7681
7682 Label L_third_loop_prologue;
7683 bind(L_third_loop_prologue);
7684
7685 push (x);
7686 push (xstart);
7687 push (ylen);
7688
7689
7690 if (UseBMI2Instructions) {
7691 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7692 } else { // !UseBMI2Instructions
7693 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7694 }
7695
7696 pop(ylen);
7697 pop(xlen);
7698 pop(x);
7699 pop(z);
7700
7701 movl(tmp3, xlen);
7702 addl(tmp3, 1);
7703 movl(Address(z, tmp3, Address::times_4, 0), carry);
7704 subl(tmp3, 1);
7705 jccb(Assembler::negative, L_done);
7706
7707 shrq(carry, 32);
7708 movl(Address(z, tmp3, Address::times_4, 0), carry);
7709 jmp(L_second_loop);
7710
7711 // Next infrequent code is moved outside loops.
7712 bind(L_last_x);
7713 if (UseBMI2Instructions) {
7714 movl(rdx, Address(x, 0));
7715 } else {
7716 movl(x_xstart, Address(x, 0));
7717 }
7718 jmp(L_third_loop_prologue);
7719
7720 bind(L_done);
7721
7722 pop(xlen);
7723
7724 pop(tmp5);
7725 pop(tmp4);
7726 pop(tmp3);
7727 pop(tmp2);
7728 pop(tmp1);
7729 pop(tmp0);
7730 }
7731
7732 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7733 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7734 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7735 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7736 Label VECTOR8_TAIL, VECTOR4_TAIL;
7737 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7738 Label SAME_TILL_END, DONE;
7739 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7740
7741 //scale is in rcx in both Win64 and Unix
7742 ShortBranchVerifier sbv(this);
7743
7744 shlq(length);
7745 xorq(result, result);
7746
7747 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7748 VM_Version::supports_avx512vlbw()) {
7749 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7750
7751 cmpq(length, 64);
7752 jcc(Assembler::less, VECTOR32_TAIL);
7753
7754 movq(tmp1, length);
7755 andq(tmp1, 0x3F); // tail count
7756 andq(length, ~(0x3F)); //vector count
7757
7758 bind(VECTOR64_LOOP);
7759 // AVX512 code to compare 64 byte vectors.
7760 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7761 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7762 kortestql(k7, k7);
7763 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7764 addq(result, 64);
7765 subq(length, 64);
7766 jccb(Assembler::notZero, VECTOR64_LOOP);
7767
7768 //bind(VECTOR64_TAIL);
7769 testq(tmp1, tmp1);
7770 jcc(Assembler::zero, SAME_TILL_END);
7771
7772 //bind(VECTOR64_TAIL);
7773 // AVX512 code to compare up to 63 byte vectors.
7774 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7775 shlxq(tmp2, tmp2, tmp1);
7776 notq(tmp2);
7777 kmovql(k3, tmp2);
7778
7779 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7780 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7781
7782 ktestql(k7, k3);
7783 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7784
7785 bind(VECTOR64_NOT_EQUAL);
7786 kmovql(tmp1, k7);
7787 notq(tmp1);
7788 tzcntq(tmp1, tmp1);
7789 addq(result, tmp1);
7790 shrq(result);
7791 jmp(DONE);
7792 bind(VECTOR32_TAIL);
7793 }
7794
7795 cmpq(length, 8);
7796 jcc(Assembler::equal, VECTOR8_LOOP);
7797 jcc(Assembler::less, VECTOR4_TAIL);
7798
7799 if (UseAVX >= 2) {
7800 Label VECTOR16_TAIL, VECTOR32_LOOP;
7801
7802 cmpq(length, 16);
7803 jcc(Assembler::equal, VECTOR16_LOOP);
7804 jcc(Assembler::less, VECTOR8_LOOP);
7805
7806 cmpq(length, 32);
7807 jccb(Assembler::less, VECTOR16_TAIL);
7808
7809 subq(length, 32);
7810 bind(VECTOR32_LOOP);
7811 vmovdqu(rymm0, Address(obja, result));
7812 vmovdqu(rymm1, Address(objb, result));
7813 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7814 vptest(rymm2, rymm2);
7815 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7816 addq(result, 32);
7817 subq(length, 32);
7818 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7819 addq(length, 32);
7820 jcc(Assembler::equal, SAME_TILL_END);
7821 //falling through if less than 32 bytes left //close the branch here.
7822
7823 bind(VECTOR16_TAIL);
7824 cmpq(length, 16);
7825 jccb(Assembler::less, VECTOR8_TAIL);
7826 bind(VECTOR16_LOOP);
7827 movdqu(rymm0, Address(obja, result));
7828 movdqu(rymm1, Address(objb, result));
7829 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7830 ptest(rymm2, rymm2);
7831 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7832 addq(result, 16);
7833 subq(length, 16);
7834 jcc(Assembler::equal, SAME_TILL_END);
7835 //falling through if less than 16 bytes left
7836 } else {//regular intrinsics
7837
7838 cmpq(length, 16);
7839 jccb(Assembler::less, VECTOR8_TAIL);
7840
7841 subq(length, 16);
7842 bind(VECTOR16_LOOP);
7843 movdqu(rymm0, Address(obja, result));
7844 movdqu(rymm1, Address(objb, result));
7845 pxor(rymm0, rymm1);
7846 ptest(rymm0, rymm0);
7847 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7848 addq(result, 16);
7849 subq(length, 16);
7850 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7851 addq(length, 16);
7852 jcc(Assembler::equal, SAME_TILL_END);
7853 //falling through if less than 16 bytes left
7854 }
7855
7856 bind(VECTOR8_TAIL);
7857 cmpq(length, 8);
7858 jccb(Assembler::less, VECTOR4_TAIL);
7859 bind(VECTOR8_LOOP);
7860 movq(tmp1, Address(obja, result));
7861 movq(tmp2, Address(objb, result));
7862 xorq(tmp1, tmp2);
7863 testq(tmp1, tmp1);
7864 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7865 addq(result, 8);
7866 subq(length, 8);
7867 jcc(Assembler::equal, SAME_TILL_END);
7868 //falling through if less than 8 bytes left
7869
7870 bind(VECTOR4_TAIL);
7871 cmpq(length, 4);
7872 jccb(Assembler::less, BYTES_TAIL);
7873 bind(VECTOR4_LOOP);
7874 movl(tmp1, Address(obja, result));
7875 xorl(tmp1, Address(objb, result));
7876 testl(tmp1, tmp1);
7877 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7878 addq(result, 4);
7879 subq(length, 4);
7880 jcc(Assembler::equal, SAME_TILL_END);
7881 //falling through if less than 4 bytes left
7882
7883 bind(BYTES_TAIL);
7884 bind(BYTES_LOOP);
7885 load_unsigned_byte(tmp1, Address(obja, result));
7886 load_unsigned_byte(tmp2, Address(objb, result));
7887 xorl(tmp1, tmp2);
7888 testl(tmp1, tmp1);
7889 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7890 decq(length);
7891 jcc(Assembler::zero, SAME_TILL_END);
7892 incq(result);
7893 load_unsigned_byte(tmp1, Address(obja, result));
7894 load_unsigned_byte(tmp2, Address(objb, result));
7895 xorl(tmp1, tmp2);
7896 testl(tmp1, tmp1);
7897 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7898 decq(length);
7899 jcc(Assembler::zero, SAME_TILL_END);
7900 incq(result);
7901 load_unsigned_byte(tmp1, Address(obja, result));
7902 load_unsigned_byte(tmp2, Address(objb, result));
7903 xorl(tmp1, tmp2);
7904 testl(tmp1, tmp1);
7905 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7906 jmp(SAME_TILL_END);
7907
7908 if (UseAVX >= 2) {
7909 bind(VECTOR32_NOT_EQUAL);
7910 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7911 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7912 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7913 vpmovmskb(tmp1, rymm0);
7914 bsfq(tmp1, tmp1);
7915 addq(result, tmp1);
7916 shrq(result);
7917 jmp(DONE);
7918 }
7919
7920 bind(VECTOR16_NOT_EQUAL);
7921 if (UseAVX >= 2) {
7922 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7923 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7924 pxor(rymm0, rymm2);
7925 } else {
7926 pcmpeqb(rymm2, rymm2);
7927 pxor(rymm0, rymm1);
7928 pcmpeqb(rymm0, rymm1);
7929 pxor(rymm0, rymm2);
7930 }
7931 pmovmskb(tmp1, rymm0);
7932 bsfq(tmp1, tmp1);
7933 addq(result, tmp1);
7934 shrq(result);
7935 jmpb(DONE);
7936
7937 bind(VECTOR8_NOT_EQUAL);
7938 bind(VECTOR4_NOT_EQUAL);
7939 bsfq(tmp1, tmp1);
7940 shrq(tmp1, 3);
7941 addq(result, tmp1);
7942 bind(BYTES_NOT_EQUAL);
7943 shrq(result);
7944 jmpb(DONE);
7945
7946 bind(SAME_TILL_END);
7947 mov64(result, -1);
7948
7949 bind(DONE);
7950 }
7951
7952 //Helper functions for square_to_len()
7953
7954 /**
7955 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7956 * Preserves x and z and modifies rest of the registers.
7957 */
7958 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7959 // Perform square and right shift by 1
7960 // Handle odd xlen case first, then for even xlen do the following
7961 // jlong carry = 0;
7962 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7963 // huge_128 product = x[j:j+1] * x[j:j+1];
7964 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7965 // z[i+2:i+3] = (jlong)(product >>> 1);
7966 // carry = (jlong)product;
7967 // }
7968
7969 xorq(tmp5, tmp5); // carry
7970 xorq(rdxReg, rdxReg);
7971 xorl(tmp1, tmp1); // index for x
7972 xorl(tmp4, tmp4); // index for z
7973
7974 Label L_first_loop, L_first_loop_exit;
7975
7976 testl(xlen, 1);
7977 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7978
7979 // Square and right shift by 1 the odd element using 32 bit multiply
7980 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7981 imulq(raxReg, raxReg);
7982 shrq(raxReg, 1);
7983 adcq(tmp5, 0);
7984 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7985 incrementl(tmp1);
7986 addl(tmp4, 2);
7987
7988 // Square and right shift by 1 the rest using 64 bit multiply
7989 bind(L_first_loop);
7990 cmpptr(tmp1, xlen);
7991 jccb(Assembler::equal, L_first_loop_exit);
7992
7993 // Square
7994 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7995 rorq(raxReg, 32); // convert big-endian to little-endian
7996 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7997
7998 // Right shift by 1 and save carry
7999 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
8000 rcrq(rdxReg, 1);
8001 rcrq(raxReg, 1);
8002 adcq(tmp5, 0);
8003
8004 // Store result in z
8005 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
8006 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
8007
8008 // Update indices for x and z
8009 addl(tmp1, 2);
8010 addl(tmp4, 4);
8011 jmp(L_first_loop);
8012
8013 bind(L_first_loop_exit);
8014 }
8015
8016
8017 /**
8018 * Perform the following multiply add operation using BMI2 instructions
8019 * carry:sum = sum + op1*op2 + carry
8020 * op2 should be in rdx
8021 * op2 is preserved, all other registers are modified
8022 */
8023 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
8024 // assert op2 is rdx
8025 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
8026 addq(sum, carry);
8027 adcq(tmp2, 0);
8028 addq(sum, op1);
8029 adcq(tmp2, 0);
8030 movq(carry, tmp2);
8031 }
8032
8033 /**
8034 * Perform the following multiply add operation:
8035 * carry:sum = sum + op1*op2 + carry
8036 * Preserves op1, op2 and modifies rest of registers
8037 */
8038 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
8039 // rdx:rax = op1 * op2
8040 movq(raxReg, op2);
8041 mulq(op1);
8042
8043 // rdx:rax = sum + carry + rdx:rax
8044 addq(sum, carry);
8045 adcq(rdxReg, 0);
8046 addq(sum, raxReg);
8047 adcq(rdxReg, 0);
8048
8049 // carry:sum = rdx:sum
8050 movq(carry, rdxReg);
8051 }
8052
8053 /**
8054 * Add 64 bit long carry into z[] with carry propagation.
8055 * Preserves z and carry register values and modifies rest of registers.
8056 *
8057 */
8058 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
8059 Label L_fourth_loop, L_fourth_loop_exit;
8060
8061 movl(tmp1, 1);
8062 subl(zlen, 2);
8063 addq(Address(z, zlen, Address::times_4, 0), carry);
8064
8065 bind(L_fourth_loop);
8066 jccb(Assembler::carryClear, L_fourth_loop_exit);
8067 subl(zlen, 2);
8068 jccb(Assembler::negative, L_fourth_loop_exit);
8069 addq(Address(z, zlen, Address::times_4, 0), tmp1);
8070 jmp(L_fourth_loop);
8071 bind(L_fourth_loop_exit);
8072 }
8073
8074 /**
8075 * Shift z[] left by 1 bit.
8076 * Preserves x, len, z and zlen registers and modifies rest of the registers.
8077 *
8078 */
8079 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
8080
8081 Label L_fifth_loop, L_fifth_loop_exit;
8082
8083 // Fifth loop
8084 // Perform primitiveLeftShift(z, zlen, 1)
8085
8086 const Register prev_carry = tmp1;
8087 const Register new_carry = tmp4;
8088 const Register value = tmp2;
8089 const Register zidx = tmp3;
8090
8091 // int zidx, carry;
8092 // long value;
8093 // carry = 0;
8094 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
8095 // (carry:value) = (z[i] << 1) | carry ;
8096 // z[i] = value;
8097 // }
8098
8099 movl(zidx, zlen);
8100 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
8101
8102 bind(L_fifth_loop);
8103 decl(zidx); // Use decl to preserve carry flag
8104 decl(zidx);
8105 jccb(Assembler::negative, L_fifth_loop_exit);
8106
8107 if (UseBMI2Instructions) {
8108 movq(value, Address(z, zidx, Address::times_4, 0));
8109 rclq(value, 1);
8110 rorxq(value, value, 32);
8111 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8112 }
8113 else {
8114 // clear new_carry
8115 xorl(new_carry, new_carry);
8116
8117 // Shift z[i] by 1, or in previous carry and save new carry
8118 movq(value, Address(z, zidx, Address::times_4, 0));
8119 shlq(value, 1);
8120 adcl(new_carry, 0);
8121
8122 orq(value, prev_carry);
8123 rorq(value, 0x20);
8124 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8125
8126 // Set previous carry = new carry
8127 movl(prev_carry, new_carry);
8128 }
8129 jmp(L_fifth_loop);
8130
8131 bind(L_fifth_loop_exit);
8132 }
8133
8134
8135 /**
8136 * Code for BigInteger::squareToLen() intrinsic
8137 *
8138 * rdi: x
8139 * rsi: len
8140 * r8: z
8141 * rcx: zlen
8142 * r12: tmp1
8143 * r13: tmp2
8144 * r14: tmp3
8145 * r15: tmp4
8146 * rbx: tmp5
8147 *
8148 */
8149 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8150
8151 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8152 push(tmp1);
8153 push(tmp2);
8154 push(tmp3);
8155 push(tmp4);
8156 push(tmp5);
8157
8158 // First loop
8159 // Store the squares, right shifted one bit (i.e., divided by 2).
8160 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8161
8162 // Add in off-diagonal sums.
8163 //
8164 // Second, third (nested) and fourth loops.
8165 // zlen +=2;
8166 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8167 // carry = 0;
8168 // long op2 = x[xidx:xidx+1];
8169 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8170 // k -= 2;
8171 // long op1 = x[j:j+1];
8172 // long sum = z[k:k+1];
8173 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8174 // z[k:k+1] = sum;
8175 // }
8176 // add_one_64(z, k, carry, tmp_regs);
8177 // }
8178
8179 const Register carry = tmp5;
8180 const Register sum = tmp3;
8181 const Register op1 = tmp4;
8182 Register op2 = tmp2;
8183
8184 push(zlen);
8185 push(len);
8186 addl(zlen,2);
8187 bind(L_second_loop);
8188 xorq(carry, carry);
8189 subl(zlen, 4);
8190 subl(len, 2);
8191 push(zlen);
8192 push(len);
8193 cmpl(len, 0);
8194 jccb(Assembler::lessEqual, L_second_loop_exit);
8195
8196 // Multiply an array by one 64 bit long.
8197 if (UseBMI2Instructions) {
8198 op2 = rdxReg;
8199 movq(op2, Address(x, len, Address::times_4, 0));
8200 rorxq(op2, op2, 32);
8201 }
8202 else {
8203 movq(op2, Address(x, len, Address::times_4, 0));
8204 rorq(op2, 32);
8205 }
8206
8207 bind(L_third_loop);
8208 decrementl(len);
8209 jccb(Assembler::negative, L_third_loop_exit);
8210 decrementl(len);
8211 jccb(Assembler::negative, L_last_x);
8212
8213 movq(op1, Address(x, len, Address::times_4, 0));
8214 rorq(op1, 32);
8215
8216 bind(L_multiply);
8217 subl(zlen, 2);
8218 movq(sum, Address(z, zlen, Address::times_4, 0));
8219
8220 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8221 if (UseBMI2Instructions) {
8222 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8223 }
8224 else {
8225 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8226 }
8227
8228 movq(Address(z, zlen, Address::times_4, 0), sum);
8229
8230 jmp(L_third_loop);
8231 bind(L_third_loop_exit);
8232
8233 // Fourth loop
8234 // Add 64 bit long carry into z with carry propagation.
8235 // Uses offsetted zlen.
8236 add_one_64(z, zlen, carry, tmp1);
8237
8238 pop(len);
8239 pop(zlen);
8240 jmp(L_second_loop);
8241
8242 // Next infrequent code is moved outside loops.
8243 bind(L_last_x);
8244 movl(op1, Address(x, 0));
8245 jmp(L_multiply);
8246
8247 bind(L_second_loop_exit);
8248 pop(len);
8249 pop(zlen);
8250 pop(len);
8251 pop(zlen);
8252
8253 // Fifth loop
8254 // Shift z left 1 bit.
8255 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8256
8257 // z[zlen-1] |= x[len-1] & 1;
8258 movl(tmp3, Address(x, len, Address::times_4, -4));
8259 andl(tmp3, 1);
8260 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8261
8262 pop(tmp5);
8263 pop(tmp4);
8264 pop(tmp3);
8265 pop(tmp2);
8266 pop(tmp1);
8267 }
8268
8269 /**
8270 * Helper function for mul_add()
8271 * Multiply the in[] by int k and add to out[] starting at offset offs using
8272 * 128 bit by 32 bit multiply and return the carry in tmp5.
8273 * Only quad int aligned length of in[] is operated on in this function.
8274 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8275 * This function preserves out, in and k registers.
8276 * len and offset point to the appropriate index in "in" & "out" correspondingly
8277 * tmp5 has the carry.
8278 * other registers are temporary and are modified.
8279 *
8280 */
8281 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8282 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8283 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8284
8285 Label L_first_loop, L_first_loop_exit;
8286
8287 movl(tmp1, len);
8288 shrl(tmp1, 2);
8289
8290 bind(L_first_loop);
8291 subl(tmp1, 1);
8292 jccb(Assembler::negative, L_first_loop_exit);
8293
8294 subl(len, 4);
8295 subl(offset, 4);
8296
8297 Register op2 = tmp2;
8298 const Register sum = tmp3;
8299 const Register op1 = tmp4;
8300 const Register carry = tmp5;
8301
8302 if (UseBMI2Instructions) {
8303 op2 = rdxReg;
8304 }
8305
8306 movq(op1, Address(in, len, Address::times_4, 8));
8307 rorq(op1, 32);
8308 movq(sum, Address(out, offset, Address::times_4, 8));
8309 rorq(sum, 32);
8310 if (UseBMI2Instructions) {
8311 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8312 }
8313 else {
8314 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8315 }
8316 // Store back in big endian from little endian
8317 rorq(sum, 0x20);
8318 movq(Address(out, offset, Address::times_4, 8), sum);
8319
8320 movq(op1, Address(in, len, Address::times_4, 0));
8321 rorq(op1, 32);
8322 movq(sum, Address(out, offset, Address::times_4, 0));
8323 rorq(sum, 32);
8324 if (UseBMI2Instructions) {
8325 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8326 }
8327 else {
8328 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8329 }
8330 // Store back in big endian from little endian
8331 rorq(sum, 0x20);
8332 movq(Address(out, offset, Address::times_4, 0), sum);
8333
8334 jmp(L_first_loop);
8335 bind(L_first_loop_exit);
8336 }
8337
8338 /**
8339 * Code for BigInteger::mulAdd() intrinsic
8340 *
8341 * rdi: out
8342 * rsi: in
8343 * r11: offs (out.length - offset)
8344 * rcx: len
8345 * r8: k
8346 * r12: tmp1
8347 * r13: tmp2
8348 * r14: tmp3
8349 * r15: tmp4
8350 * rbx: tmp5
8351 * Multiply the in[] by word k and add to out[], return the carry in rax
8352 */
8353 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8354 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8355 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8356
8357 Label L_carry, L_last_in, L_done;
8358
8359 // carry = 0;
8360 // for (int j=len-1; j >= 0; j--) {
8361 // long product = (in[j] & LONG_MASK) * kLong +
8362 // (out[offs] & LONG_MASK) + carry;
8363 // out[offs--] = (int)product;
8364 // carry = product >>> 32;
8365 // }
8366 //
8367 push(tmp1);
8368 push(tmp2);
8369 push(tmp3);
8370 push(tmp4);
8371 push(tmp5);
8372
8373 Register op2 = tmp2;
8374 const Register sum = tmp3;
8375 const Register op1 = tmp4;
8376 const Register carry = tmp5;
8377
8378 if (UseBMI2Instructions) {
8379 op2 = rdxReg;
8380 movl(op2, k);
8381 }
8382 else {
8383 movl(op2, k);
8384 }
8385
8386 xorq(carry, carry);
8387
8388 //First loop
8389
8390 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8391 //The carry is in tmp5
8392 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8393
8394 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8395 decrementl(len);
8396 jccb(Assembler::negative, L_carry);
8397 decrementl(len);
8398 jccb(Assembler::negative, L_last_in);
8399
8400 movq(op1, Address(in, len, Address::times_4, 0));
8401 rorq(op1, 32);
8402
8403 subl(offs, 2);
8404 movq(sum, Address(out, offs, Address::times_4, 0));
8405 rorq(sum, 32);
8406
8407 if (UseBMI2Instructions) {
8408 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8409 }
8410 else {
8411 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8412 }
8413
8414 // Store back in big endian from little endian
8415 rorq(sum, 0x20);
8416 movq(Address(out, offs, Address::times_4, 0), sum);
8417
8418 testl(len, len);
8419 jccb(Assembler::zero, L_carry);
8420
8421 //Multiply the last in[] entry, if any
8422 bind(L_last_in);
8423 movl(op1, Address(in, 0));
8424 movl(sum, Address(out, offs, Address::times_4, -4));
8425
8426 movl(raxReg, k);
8427 mull(op1); //tmp4 * eax -> edx:eax
8428 addl(sum, carry);
8429 adcl(rdxReg, 0);
8430 addl(sum, raxReg);
8431 adcl(rdxReg, 0);
8432 movl(carry, rdxReg);
8433
8434 movl(Address(out, offs, Address::times_4, -4), sum);
8435
8436 bind(L_carry);
8437 //return tmp5/carry as carry in rax
8438 movl(rax, carry);
8439
8440 bind(L_done);
8441 pop(tmp5);
8442 pop(tmp4);
8443 pop(tmp3);
8444 pop(tmp2);
8445 pop(tmp1);
8446 }
8447
8448 /**
8449 * Emits code to update CRC-32 with a byte value according to constants in table
8450 *
8451 * @param [in,out]crc Register containing the crc.
8452 * @param [in]val Register containing the byte to fold into the CRC.
8453 * @param [in]table Register containing the table of crc constants.
8454 *
8455 * uint32_t crc;
8456 * val = crc_table[(val ^ crc) & 0xFF];
8457 * crc = val ^ (crc >> 8);
8458 *
8459 */
8460 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8461 xorl(val, crc);
8462 andl(val, 0xFF);
8463 shrl(crc, 8); // unsigned shift
8464 xorl(crc, Address(table, val, Address::times_4, 0));
8465 }
8466
8467 /**
8468 * Fold 128-bit data chunk
8469 */
8470 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8471 if (UseAVX > 0) {
8472 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8473 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8474 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8475 pxor(xcrc, xtmp);
8476 } else {
8477 movdqa(xtmp, xcrc);
8478 pclmulhdq(xtmp, xK); // [123:64]
8479 pclmulldq(xcrc, xK); // [63:0]
8480 pxor(xcrc, xtmp);
8481 movdqu(xtmp, Address(buf, offset));
8482 pxor(xcrc, xtmp);
8483 }
8484 }
8485
8486 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8487 if (UseAVX > 0) {
8488 vpclmulhdq(xtmp, xK, xcrc);
8489 vpclmulldq(xcrc, xK, xcrc);
8490 pxor(xcrc, xbuf);
8491 pxor(xcrc, xtmp);
8492 } else {
8493 movdqa(xtmp, xcrc);
8494 pclmulhdq(xtmp, xK);
8495 pclmulldq(xcrc, xK);
8496 pxor(xcrc, xbuf);
8497 pxor(xcrc, xtmp);
8498 }
8499 }
8500
8501 /**
8502 * 8-bit folds to compute 32-bit CRC
8503 *
8504 * uint64_t xcrc;
8505 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8506 */
8507 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8508 movdl(tmp, xcrc);
8509 andl(tmp, 0xFF);
8510 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8511 psrldq(xcrc, 1); // unsigned shift one byte
8512 pxor(xcrc, xtmp);
8513 }
8514
8515 /**
8516 * uint32_t crc;
8517 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8518 */
8519 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8520 movl(tmp, crc);
8521 andl(tmp, 0xFF);
8522 shrl(crc, 8);
8523 xorl(crc, Address(table, tmp, Address::times_4, 0));
8524 }
8525
8526 /**
8527 * @param crc register containing existing CRC (32-bit)
8528 * @param buf register pointing to input byte buffer (byte*)
8529 * @param len register containing number of bytes
8530 * @param table register that will contain address of CRC table
8531 * @param tmp scratch register
8532 */
8533 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8534 assert_different_registers(crc, buf, len, table, tmp, rax);
8535
8536 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8537 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8538
8539 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8540 // context for the registers used, where all instructions below are using 128-bit mode
8541 // On EVEX without VL and BW, these instructions will all be AVX.
8542 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8543 notl(crc); // ~crc
8544 cmpl(len, 16);
8545 jcc(Assembler::less, L_tail);
8546
8547 // Align buffer to 16 bytes
8548 movl(tmp, buf);
8549 andl(tmp, 0xF);
8550 jccb(Assembler::zero, L_aligned);
8551 subl(tmp, 16);
8552 addl(len, tmp);
8553
8554 align(4);
8555 BIND(L_align_loop);
8556 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8557 update_byte_crc32(crc, rax, table);
8558 increment(buf);
8559 incrementl(tmp);
8560 jccb(Assembler::less, L_align_loop);
8561
8562 BIND(L_aligned);
8563 movl(tmp, len); // save
8564 shrl(len, 4);
8565 jcc(Assembler::zero, L_tail_restore);
8566
8567 // Fold crc into first bytes of vector
8568 movdqa(xmm1, Address(buf, 0));
8569 movdl(rax, xmm1);
8570 xorl(crc, rax);
8571 if (VM_Version::supports_sse4_1()) {
8572 pinsrd(xmm1, crc, 0);
8573 } else {
8574 pinsrw(xmm1, crc, 0);
8575 shrl(crc, 16);
8576 pinsrw(xmm1, crc, 1);
8577 }
8578 addptr(buf, 16);
8579 subl(len, 4); // len > 0
8580 jcc(Assembler::less, L_fold_tail);
8581
8582 movdqa(xmm2, Address(buf, 0));
8583 movdqa(xmm3, Address(buf, 16));
8584 movdqa(xmm4, Address(buf, 32));
8585 addptr(buf, 48);
8586 subl(len, 3);
8587 jcc(Assembler::lessEqual, L_fold_512b);
8588
8589 // Fold total 512 bits of polynomial on each iteration,
8590 // 128 bits per each of 4 parallel streams.
8591 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8592
8593 align32();
8594 BIND(L_fold_512b_loop);
8595 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8596 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8597 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8598 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8599 addptr(buf, 64);
8600 subl(len, 4);
8601 jcc(Assembler::greater, L_fold_512b_loop);
8602
8603 // Fold 512 bits to 128 bits.
8604 BIND(L_fold_512b);
8605 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8606 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8607 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8608 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8609
8610 // Fold the rest of 128 bits data chunks
8611 BIND(L_fold_tail);
8612 addl(len, 3);
8613 jccb(Assembler::lessEqual, L_fold_128b);
8614 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8615
8616 BIND(L_fold_tail_loop);
8617 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8618 addptr(buf, 16);
8619 decrementl(len);
8620 jccb(Assembler::greater, L_fold_tail_loop);
8621
8622 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8623 BIND(L_fold_128b);
8624 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8625 if (UseAVX > 0) {
8626 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8627 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8628 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8629 } else {
8630 movdqa(xmm2, xmm0);
8631 pclmulqdq(xmm2, xmm1, 0x1);
8632 movdqa(xmm3, xmm0);
8633 pand(xmm3, xmm2);
8634 pclmulqdq(xmm0, xmm3, 0x1);
8635 }
8636 psrldq(xmm1, 8);
8637 psrldq(xmm2, 4);
8638 pxor(xmm0, xmm1);
8639 pxor(xmm0, xmm2);
8640
8641 // 8 8-bit folds to compute 32-bit CRC.
8642 for (int j = 0; j < 4; j++) {
8643 fold_8bit_crc32(xmm0, table, xmm1, rax);
8644 }
8645 movdl(crc, xmm0); // mov 32 bits to general register
8646 for (int j = 0; j < 4; j++) {
8647 fold_8bit_crc32(crc, table, rax);
8648 }
8649
8650 BIND(L_tail_restore);
8651 movl(len, tmp); // restore
8652 BIND(L_tail);
8653 andl(len, 0xf);
8654 jccb(Assembler::zero, L_exit);
8655
8656 // Fold the rest of bytes
8657 align(4);
8658 BIND(L_tail_loop);
8659 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8660 update_byte_crc32(crc, rax, table);
8661 increment(buf);
8662 decrementl(len);
8663 jccb(Assembler::greater, L_tail_loop);
8664
8665 BIND(L_exit);
8666 notl(crc); // ~c
8667 }
8668
8669 // Helper function for AVX 512 CRC32
8670 // Fold 512-bit data chunks
8671 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8672 Register pos, int offset) {
8673 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8674 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8675 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8676 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8677 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8678 }
8679
8680 // Helper function for AVX 512 CRC32
8681 // Compute CRC32 for < 256B buffers
8682 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8683 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8684 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8685
8686 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8687 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8688 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8689
8690 // check if there is enough buffer to be able to fold 16B at a time
8691 cmpl(len, 32);
8692 jcc(Assembler::less, L_less_than_32);
8693
8694 // if there is, load the constants
8695 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8696 movdl(xmm0, crc); // get the initial crc value
8697 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8698 pxor(xmm7, xmm0);
8699
8700 // update the buffer pointer
8701 addl(pos, 16);
8702 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8703 subl(len, 32);
8704 jmp(L_16B_reduction_loop);
8705
8706 bind(L_less_than_32);
8707 //mov initial crc to the return value. this is necessary for zero - length buffers.
8708 movl(rax, crc);
8709 testl(len, len);
8710 jcc(Assembler::equal, L_cleanup);
8711
8712 movdl(xmm0, crc); //get the initial crc value
8713
8714 cmpl(len, 16);
8715 jcc(Assembler::equal, L_exact_16_left);
8716 jcc(Assembler::less, L_less_than_16_left);
8717
8718 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8719 pxor(xmm7, xmm0); //xor the initial crc value
8720 addl(pos, 16);
8721 subl(len, 16);
8722 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8723 jmp(L_get_last_two_xmms);
8724
8725 bind(L_less_than_16_left);
8726 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8727 pxor(xmm1, xmm1);
8728 movptr(tmp1, rsp);
8729 movdqu(Address(tmp1, 0 * 16), xmm1);
8730
8731 cmpl(len, 4);
8732 jcc(Assembler::less, L_only_less_than_4);
8733
8734 //backup the counter value
8735 movl(tmp2, len);
8736 cmpl(len, 8);
8737 jcc(Assembler::less, L_less_than_8_left);
8738
8739 //load 8 Bytes
8740 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8741 movq(Address(tmp1, 0 * 16), rax);
8742 addptr(tmp1, 8);
8743 subl(len, 8);
8744 addl(pos, 8);
8745
8746 bind(L_less_than_8_left);
8747 cmpl(len, 4);
8748 jcc(Assembler::less, L_less_than_4_left);
8749
8750 //load 4 Bytes
8751 movl(rax, Address(buf, pos, Address::times_1, 0));
8752 movl(Address(tmp1, 0 * 16), rax);
8753 addptr(tmp1, 4);
8754 subl(len, 4);
8755 addl(pos, 4);
8756
8757 bind(L_less_than_4_left);
8758 cmpl(len, 2);
8759 jcc(Assembler::less, L_less_than_2_left);
8760
8761 // load 2 Bytes
8762 movw(rax, Address(buf, pos, Address::times_1, 0));
8763 movl(Address(tmp1, 0 * 16), rax);
8764 addptr(tmp1, 2);
8765 subl(len, 2);
8766 addl(pos, 2);
8767
8768 bind(L_less_than_2_left);
8769 cmpl(len, 1);
8770 jcc(Assembler::less, L_zero_left);
8771
8772 // load 1 Byte
8773 movb(rax, Address(buf, pos, Address::times_1, 0));
8774 movb(Address(tmp1, 0 * 16), rax);
8775
8776 bind(L_zero_left);
8777 movdqu(xmm7, Address(rsp, 0));
8778 pxor(xmm7, xmm0); //xor the initial crc value
8779
8780 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8781 movdqu(xmm0, Address(rax, tmp2));
8782 pshufb(xmm7, xmm0);
8783 jmp(L_128_done);
8784
8785 bind(L_exact_16_left);
8786 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8787 pxor(xmm7, xmm0); //xor the initial crc value
8788 jmp(L_128_done);
8789
8790 bind(L_only_less_than_4);
8791 cmpl(len, 3);
8792 jcc(Assembler::less, L_only_less_than_3);
8793
8794 // load 3 Bytes
8795 movb(rax, Address(buf, pos, Address::times_1, 0));
8796 movb(Address(tmp1, 0), rax);
8797
8798 movb(rax, Address(buf, pos, Address::times_1, 1));
8799 movb(Address(tmp1, 1), rax);
8800
8801 movb(rax, Address(buf, pos, Address::times_1, 2));
8802 movb(Address(tmp1, 2), rax);
8803
8804 movdqu(xmm7, Address(rsp, 0));
8805 pxor(xmm7, xmm0); //xor the initial crc value
8806
8807 pslldq(xmm7, 0x5);
8808 jmp(L_barrett);
8809 bind(L_only_less_than_3);
8810 cmpl(len, 2);
8811 jcc(Assembler::less, L_only_less_than_2);
8812
8813 // load 2 Bytes
8814 movb(rax, Address(buf, pos, Address::times_1, 0));
8815 movb(Address(tmp1, 0), rax);
8816
8817 movb(rax, Address(buf, pos, Address::times_1, 1));
8818 movb(Address(tmp1, 1), rax);
8819
8820 movdqu(xmm7, Address(rsp, 0));
8821 pxor(xmm7, xmm0); //xor the initial crc value
8822
8823 pslldq(xmm7, 0x6);
8824 jmp(L_barrett);
8825
8826 bind(L_only_less_than_2);
8827 //load 1 Byte
8828 movb(rax, Address(buf, pos, Address::times_1, 0));
8829 movb(Address(tmp1, 0), rax);
8830
8831 movdqu(xmm7, Address(rsp, 0));
8832 pxor(xmm7, xmm0); //xor the initial crc value
8833
8834 pslldq(xmm7, 0x7);
8835 }
8836
8837 /**
8838 * Compute CRC32 using AVX512 instructions
8839 * param crc register containing existing CRC (32-bit)
8840 * param buf register pointing to input byte buffer (byte*)
8841 * param len register containing number of bytes
8842 * param table address of crc or crc32c table
8843 * param tmp1 scratch register
8844 * param tmp2 scratch register
8845 * return rax result register
8846 *
8847 * This routine is identical for crc32c with the exception of the precomputed constant
8848 * table which will be passed as the table argument. The calculation steps are
8849 * the same for both variants.
8850 */
8851 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8852 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8853
8854 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8855 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8856 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8857 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8858 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8859
8860 const Register pos = r12;
8861 push(r12);
8862 subptr(rsp, 16 * 2 + 8);
8863
8864 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8865 // context for the registers used, where all instructions below are using 128-bit mode
8866 // On EVEX without VL and BW, these instructions will all be AVX.
8867 movl(pos, 0);
8868
8869 // check if smaller than 256B
8870 cmpl(len, 256);
8871 jcc(Assembler::less, L_less_than_256);
8872
8873 // load the initial crc value
8874 movdl(xmm10, crc);
8875
8876 // receive the initial 64B data, xor the initial crc value
8877 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8878 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8879 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8880 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8881
8882 subl(len, 256);
8883 cmpl(len, 256);
8884 jcc(Assembler::less, L_fold_128_B_loop);
8885
8886 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8887 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8888 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8889 subl(len, 256);
8890
8891 bind(L_fold_256_B_loop);
8892 addl(pos, 256);
8893 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8894 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8895 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8896 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8897
8898 subl(len, 256);
8899 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8900
8901 // Fold 256 into 128
8902 addl(pos, 256);
8903 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8904 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8905 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8906
8907 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8908 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8909 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8910
8911 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8912 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8913
8914 addl(len, 128);
8915 jmp(L_fold_128_B_register);
8916
8917 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8918 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8919
8920 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8921 bind(L_fold_128_B_loop);
8922 addl(pos, 128);
8923 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8924 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8925
8926 subl(len, 128);
8927 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8928
8929 addl(pos, 128);
8930
8931 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8932 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8933 bind(L_fold_128_B_register);
8934 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8935 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8936 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8937 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8938 // save last that has no multiplicand
8939 vextracti64x2(xmm7, xmm4, 3);
8940
8941 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8942 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8943 // Needed later in reduction loop
8944 movdqu(xmm10, Address(table, 1 * 16));
8945 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8946 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8947
8948 // Swap 1,0,3,2 - 01 00 11 10
8949 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8950 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8951 vextracti128(xmm5, xmm8, 1);
8952 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8953
8954 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8955 // instead of a cmp instruction, we use the negative flag with the jl instruction
8956 addl(len, 128 - 16);
8957 jcc(Assembler::less, L_final_reduction_for_128);
8958
8959 bind(L_16B_reduction_loop);
8960 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8961 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8962 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8963 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8964 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8965 addl(pos, 16);
8966 subl(len, 16);
8967 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8968
8969 bind(L_final_reduction_for_128);
8970 addl(len, 16);
8971 jcc(Assembler::equal, L_128_done);
8972
8973 bind(L_get_last_two_xmms);
8974 movdqu(xmm2, xmm7);
8975 addl(pos, len);
8976 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8977 subl(pos, len);
8978
8979 // get rid of the extra data that was loaded before
8980 // load the shift constant
8981 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8982 movdqu(xmm0, Address(rax, len));
8983 addl(rax, len);
8984
8985 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8986 //Change mask to 512
8987 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8988 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8989
8990 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8991 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8992 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8993 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8994 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8995
8996 bind(L_128_done);
8997 // compute crc of a 128-bit value
8998 movdqu(xmm10, Address(table, 3 * 16));
8999 movdqu(xmm0, xmm7);
9000
9001 // 64b fold
9002 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
9003 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
9004 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
9005
9006 // 32b fold
9007 movdqu(xmm0, xmm7);
9008 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
9009 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
9010 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
9011 jmp(L_barrett);
9012
9013 bind(L_less_than_256);
9014 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
9015
9016 //barrett reduction
9017 bind(L_barrett);
9018 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
9019 movdqu(xmm1, xmm7);
9020 movdqu(xmm2, xmm7);
9021 movdqu(xmm10, Address(table, 4 * 16));
9022
9023 pclmulqdq(xmm7, xmm10, 0x0);
9024 pxor(xmm7, xmm2);
9025 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
9026 movdqu(xmm2, xmm7);
9027 pclmulqdq(xmm7, xmm10, 0x10);
9028 pxor(xmm7, xmm2);
9029 pxor(xmm7, xmm1);
9030 pextrd(crc, xmm7, 2);
9031
9032 bind(L_cleanup);
9033 addptr(rsp, 16 * 2 + 8);
9034 pop(r12);
9035 }
9036
9037 // S. Gueron / Information Processing Letters 112 (2012) 184
9038 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
9039 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
9040 // Output: the 64-bit carry-less product of B * CONST
9041 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
9042 Register tmp1, Register tmp2, Register tmp3) {
9043 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9044 if (n > 0) {
9045 addq(tmp3, n * 256 * 8);
9046 }
9047 // Q1 = TABLEExt[n][B & 0xFF];
9048 movl(tmp1, in);
9049 andl(tmp1, 0x000000FF);
9050 shll(tmp1, 3);
9051 addq(tmp1, tmp3);
9052 movq(tmp1, Address(tmp1, 0));
9053
9054 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9055 movl(tmp2, in);
9056 shrl(tmp2, 8);
9057 andl(tmp2, 0x000000FF);
9058 shll(tmp2, 3);
9059 addq(tmp2, tmp3);
9060 movq(tmp2, Address(tmp2, 0));
9061
9062 shlq(tmp2, 8);
9063 xorq(tmp1, tmp2);
9064
9065 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9066 movl(tmp2, in);
9067 shrl(tmp2, 16);
9068 andl(tmp2, 0x000000FF);
9069 shll(tmp2, 3);
9070 addq(tmp2, tmp3);
9071 movq(tmp2, Address(tmp2, 0));
9072
9073 shlq(tmp2, 16);
9074 xorq(tmp1, tmp2);
9075
9076 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9077 shrl(in, 24);
9078 andl(in, 0x000000FF);
9079 shll(in, 3);
9080 addq(in, tmp3);
9081 movq(in, Address(in, 0));
9082
9083 shlq(in, 24);
9084 xorq(in, tmp1);
9085 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9086 }
9087
9088 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9089 Register in_out,
9090 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9091 XMMRegister w_xtmp2,
9092 Register tmp1,
9093 Register n_tmp2, Register n_tmp3) {
9094 if (is_pclmulqdq_supported) {
9095 movdl(w_xtmp1, in_out); // modified blindly
9096
9097 movl(tmp1, const_or_pre_comp_const_index);
9098 movdl(w_xtmp2, tmp1);
9099 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9100
9101 movdq(in_out, w_xtmp1);
9102 } else {
9103 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
9104 }
9105 }
9106
9107 // Recombination Alternative 2: No bit-reflections
9108 // T1 = (CRC_A * U1) << 1
9109 // T2 = (CRC_B * U2) << 1
9110 // C1 = T1 >> 32
9111 // C2 = T2 >> 32
9112 // T1 = T1 & 0xFFFFFFFF
9113 // T2 = T2 & 0xFFFFFFFF
9114 // T1 = CRC32(0, T1)
9115 // T2 = CRC32(0, T2)
9116 // C1 = C1 ^ T1
9117 // C2 = C2 ^ T2
9118 // CRC = C1 ^ C2 ^ CRC_C
9119 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9120 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9121 Register tmp1, Register tmp2,
9122 Register n_tmp3) {
9123 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9124 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9125 shlq(in_out, 1);
9126 movl(tmp1, in_out);
9127 shrq(in_out, 32);
9128 xorl(tmp2, tmp2);
9129 crc32(tmp2, tmp1, 4);
9130 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9131 shlq(in1, 1);
9132 movl(tmp1, in1);
9133 shrq(in1, 32);
9134 xorl(tmp2, tmp2);
9135 crc32(tmp2, tmp1, 4);
9136 xorl(in1, tmp2);
9137 xorl(in_out, in1);
9138 xorl(in_out, in2);
9139 }
9140
9141 // Set N to predefined value
9142 // Subtract from a length of a buffer
9143 // execute in a loop:
9144 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9145 // for i = 1 to N do
9146 // CRC_A = CRC32(CRC_A, A[i])
9147 // CRC_B = CRC32(CRC_B, B[i])
9148 // CRC_C = CRC32(CRC_C, C[i])
9149 // end for
9150 // Recombine
9151 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9152 Register in_out1, Register in_out2, Register in_out3,
9153 Register tmp1, Register tmp2, Register tmp3,
9154 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9155 Register tmp4, Register tmp5,
9156 Register n_tmp6) {
9157 Label L_processPartitions;
9158 Label L_processPartition;
9159 Label L_exit;
9160
9161 bind(L_processPartitions);
9162 cmpl(in_out1, 3 * size);
9163 jcc(Assembler::less, L_exit);
9164 xorl(tmp1, tmp1);
9165 xorl(tmp2, tmp2);
9166 movq(tmp3, in_out2);
9167 addq(tmp3, size);
9168
9169 bind(L_processPartition);
9170 crc32(in_out3, Address(in_out2, 0), 8);
9171 crc32(tmp1, Address(in_out2, size), 8);
9172 crc32(tmp2, Address(in_out2, size * 2), 8);
9173 addq(in_out2, 8);
9174 cmpq(in_out2, tmp3);
9175 jcc(Assembler::less, L_processPartition);
9176 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9177 w_xtmp1, w_xtmp2, w_xtmp3,
9178 tmp4, tmp5,
9179 n_tmp6);
9180 addq(in_out2, 2 * size);
9181 subl(in_out1, 3 * size);
9182 jmp(L_processPartitions);
9183
9184 bind(L_exit);
9185 }
9186
9187 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9188 // Input: A buffer I of L bytes.
9189 // Output: the CRC32C value of the buffer.
9190 // Notations:
9191 // Write L = 24N + r, with N = floor (L/24).
9192 // r = L mod 24 (0 <= r < 24).
9193 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9194 // N quadwords, and R consists of r bytes.
9195 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9196 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9197 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9198 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9199 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9200 Register tmp1, Register tmp2, Register tmp3,
9201 Register tmp4, Register tmp5, Register tmp6,
9202 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9203 bool is_pclmulqdq_supported) {
9204 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9205 Label L_wordByWord;
9206 Label L_byteByByteProlog;
9207 Label L_byteByByte;
9208 Label L_exit;
9209
9210 if (is_pclmulqdq_supported ) {
9211 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9212 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9213
9214 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9215 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9216
9217 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9218 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9219 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9220 } else {
9221 const_or_pre_comp_const_index[0] = 1;
9222 const_or_pre_comp_const_index[1] = 0;
9223
9224 const_or_pre_comp_const_index[2] = 3;
9225 const_or_pre_comp_const_index[3] = 2;
9226
9227 const_or_pre_comp_const_index[4] = 5;
9228 const_or_pre_comp_const_index[5] = 4;
9229 }
9230 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9231 in2, in1, in_out,
9232 tmp1, tmp2, tmp3,
9233 w_xtmp1, w_xtmp2, w_xtmp3,
9234 tmp4, tmp5,
9235 tmp6);
9236 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9237 in2, in1, in_out,
9238 tmp1, tmp2, tmp3,
9239 w_xtmp1, w_xtmp2, w_xtmp3,
9240 tmp4, tmp5,
9241 tmp6);
9242 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9243 in2, in1, in_out,
9244 tmp1, tmp2, tmp3,
9245 w_xtmp1, w_xtmp2, w_xtmp3,
9246 tmp4, tmp5,
9247 tmp6);
9248 movl(tmp1, in2);
9249 andl(tmp1, 0x00000007);
9250 negl(tmp1);
9251 addl(tmp1, in2);
9252 addq(tmp1, in1);
9253
9254 cmpq(in1, tmp1);
9255 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9256 align(16);
9257 BIND(L_wordByWord);
9258 crc32(in_out, Address(in1, 0), 8);
9259 addq(in1, 8);
9260 cmpq(in1, tmp1);
9261 jcc(Assembler::less, L_wordByWord);
9262
9263 BIND(L_byteByByteProlog);
9264 andl(in2, 0x00000007);
9265 movl(tmp2, 1);
9266
9267 cmpl(tmp2, in2);
9268 jccb(Assembler::greater, L_exit);
9269 BIND(L_byteByByte);
9270 crc32(in_out, Address(in1, 0), 1);
9271 incq(in1);
9272 incl(tmp2);
9273 cmpl(tmp2, in2);
9274 jcc(Assembler::lessEqual, L_byteByByte);
9275
9276 BIND(L_exit);
9277 }
9278 #undef BIND
9279 #undef BLOCK_COMMENT
9280
9281 // Compress char[] array to byte[].
9282 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9283 // Return the array length if every element in array can be encoded,
9284 // otherwise, the index of first non-latin1 (> 0xff) character.
9285 // @IntrinsicCandidate
9286 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9287 // for (int i = 0; i < len; i++) {
9288 // char c = src[srcOff];
9289 // if (c > 0xff) {
9290 // return i; // return index of non-latin1 char
9291 // }
9292 // dst[dstOff] = (byte)c;
9293 // srcOff++;
9294 // dstOff++;
9295 // }
9296 // return len;
9297 // }
9298 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9299 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9300 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9301 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9302 Label copy_chars_loop, done, reset_sp, copy_tail;
9303
9304 // rsi: src
9305 // rdi: dst
9306 // rdx: len
9307 // rcx: tmp5
9308 // rax: result
9309
9310 // rsi holds start addr of source char[] to be compressed
9311 // rdi holds start addr of destination byte[]
9312 // rdx holds length
9313
9314 assert(len != result, "");
9315
9316 // save length for return
9317 movl(result, len);
9318
9319 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9320 VM_Version::supports_avx512vlbw() &&
9321 VM_Version::supports_bmi2()) {
9322
9323 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9324
9325 // alignment
9326 Label post_alignment;
9327
9328 // if length of the string is less than 32, handle it the old fashioned way
9329 testl(len, -32);
9330 jcc(Assembler::zero, below_threshold);
9331
9332 // First check whether a character is compressible ( <= 0xFF).
9333 // Create mask to test for Unicode chars inside zmm vector
9334 movl(tmp5, 0x00FF);
9335 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9336
9337 testl(len, -64);
9338 jccb(Assembler::zero, post_alignment);
9339
9340 movl(tmp5, dst);
9341 andl(tmp5, (32 - 1));
9342 negl(tmp5);
9343 andl(tmp5, (32 - 1));
9344
9345 // bail out when there is nothing to be done
9346 testl(tmp5, 0xFFFFFFFF);
9347 jccb(Assembler::zero, post_alignment);
9348
9349 // ~(~0 << len), where len is the # of remaining elements to process
9350 movl(len, 0xFFFFFFFF);
9351 shlxl(len, len, tmp5);
9352 notl(len);
9353 kmovdl(mask2, len);
9354 movl(len, result);
9355
9356 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9357 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9358 ktestd(mask1, mask2);
9359 jcc(Assembler::carryClear, copy_tail);
9360
9361 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9362
9363 addptr(src, tmp5);
9364 addptr(src, tmp5);
9365 addptr(dst, tmp5);
9366 subl(len, tmp5);
9367
9368 bind(post_alignment);
9369 // end of alignment
9370
9371 movl(tmp5, len);
9372 andl(tmp5, (32 - 1)); // tail count (in chars)
9373 andl(len, ~(32 - 1)); // vector count (in chars)
9374 jccb(Assembler::zero, copy_loop_tail);
9375
9376 lea(src, Address(src, len, Address::times_2));
9377 lea(dst, Address(dst, len, Address::times_1));
9378 negptr(len);
9379
9380 bind(copy_32_loop);
9381 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9382 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9383 kortestdl(mask1, mask1);
9384 jccb(Assembler::carryClear, reset_for_copy_tail);
9385
9386 // All elements in current processed chunk are valid candidates for
9387 // compression. Write a truncated byte elements to the memory.
9388 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9389 addptr(len, 32);
9390 jccb(Assembler::notZero, copy_32_loop);
9391
9392 bind(copy_loop_tail);
9393 // bail out when there is nothing to be done
9394 testl(tmp5, 0xFFFFFFFF);
9395 jcc(Assembler::zero, done);
9396
9397 movl(len, tmp5);
9398
9399 // ~(~0 << len), where len is the # of remaining elements to process
9400 movl(tmp5, 0xFFFFFFFF);
9401 shlxl(tmp5, tmp5, len);
9402 notl(tmp5);
9403
9404 kmovdl(mask2, tmp5);
9405
9406 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9407 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9408 ktestd(mask1, mask2);
9409 jcc(Assembler::carryClear, copy_tail);
9410
9411 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9412 jmp(done);
9413
9414 bind(reset_for_copy_tail);
9415 lea(src, Address(src, tmp5, Address::times_2));
9416 lea(dst, Address(dst, tmp5, Address::times_1));
9417 subptr(len, tmp5);
9418 jmp(copy_chars_loop);
9419
9420 bind(below_threshold);
9421 }
9422
9423 if (UseSSE42Intrinsics) {
9424 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9425
9426 // vectored compression
9427 testl(len, 0xfffffff8);
9428 jcc(Assembler::zero, copy_tail);
9429
9430 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9431 movdl(tmp1Reg, tmp5);
9432 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9433
9434 andl(len, 0xfffffff0);
9435 jccb(Assembler::zero, copy_16);
9436
9437 // compress 16 chars per iter
9438 pxor(tmp4Reg, tmp4Reg);
9439
9440 lea(src, Address(src, len, Address::times_2));
9441 lea(dst, Address(dst, len, Address::times_1));
9442 negptr(len);
9443
9444 bind(copy_32_loop);
9445 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9446 por(tmp4Reg, tmp2Reg);
9447 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9448 por(tmp4Reg, tmp3Reg);
9449 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9450 jccb(Assembler::notZero, reset_for_copy_tail);
9451 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9452 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9453 addptr(len, 16);
9454 jccb(Assembler::notZero, copy_32_loop);
9455
9456 // compress next vector of 8 chars (if any)
9457 bind(copy_16);
9458 // len = 0
9459 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9460 jccb(Assembler::zero, copy_tail_sse);
9461
9462 pxor(tmp3Reg, tmp3Reg);
9463
9464 movdqu(tmp2Reg, Address(src, 0));
9465 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9466 jccb(Assembler::notZero, reset_for_copy_tail);
9467 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9468 movq(Address(dst, 0), tmp2Reg);
9469 addptr(src, 16);
9470 addptr(dst, 8);
9471 jmpb(copy_tail_sse);
9472
9473 bind(reset_for_copy_tail);
9474 movl(tmp5, result);
9475 andl(tmp5, 0x0000000f);
9476 lea(src, Address(src, tmp5, Address::times_2));
9477 lea(dst, Address(dst, tmp5, Address::times_1));
9478 subptr(len, tmp5);
9479 jmpb(copy_chars_loop);
9480
9481 bind(copy_tail_sse);
9482 movl(len, result);
9483 andl(len, 0x00000007); // tail count (in chars)
9484 }
9485 // compress 1 char per iter
9486 bind(copy_tail);
9487 testl(len, len);
9488 jccb(Assembler::zero, done);
9489 lea(src, Address(src, len, Address::times_2));
9490 lea(dst, Address(dst, len, Address::times_1));
9491 negptr(len);
9492
9493 bind(copy_chars_loop);
9494 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9495 testl(tmp5, 0xff00); // check if Unicode char
9496 jccb(Assembler::notZero, reset_sp);
9497 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9498 increment(len);
9499 jccb(Assembler::notZero, copy_chars_loop);
9500
9501 // add len then return (len will be zero if compress succeeded, otherwise negative)
9502 bind(reset_sp);
9503 addl(result, len);
9504
9505 bind(done);
9506 }
9507
9508 // Inflate byte[] array to char[].
9509 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9510 // @IntrinsicCandidate
9511 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9512 // for (int i = 0; i < len; i++) {
9513 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9514 // }
9515 // }
9516 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9517 XMMRegister tmp1, Register tmp2, KRegister mask) {
9518 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9519 // rsi: src
9520 // rdi: dst
9521 // rdx: len
9522 // rcx: tmp2
9523
9524 // rsi holds start addr of source byte[] to be inflated
9525 // rdi holds start addr of destination char[]
9526 // rdx holds length
9527 assert_different_registers(src, dst, len, tmp2);
9528 movl(tmp2, len);
9529 if ((UseAVX > 2) && // AVX512
9530 VM_Version::supports_avx512vlbw() &&
9531 VM_Version::supports_bmi2()) {
9532
9533 Label copy_32_loop, copy_tail;
9534 Register tmp3_aliased = len;
9535
9536 // if length of the string is less than 16, handle it in an old fashioned way
9537 testl(len, -16);
9538 jcc(Assembler::zero, below_threshold);
9539
9540 testl(len, -1 * AVX3Threshold);
9541 jcc(Assembler::zero, avx3_threshold);
9542
9543 // In order to use only one arithmetic operation for the main loop we use
9544 // this pre-calculation
9545 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9546 andl(len, -32); // vector count
9547 jccb(Assembler::zero, copy_tail);
9548
9549 lea(src, Address(src, len, Address::times_1));
9550 lea(dst, Address(dst, len, Address::times_2));
9551 negptr(len);
9552
9553
9554 // inflate 32 chars per iter
9555 bind(copy_32_loop);
9556 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9557 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9558 addptr(len, 32);
9559 jcc(Assembler::notZero, copy_32_loop);
9560
9561 bind(copy_tail);
9562 // bail out when there is nothing to be done
9563 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9564 jcc(Assembler::zero, done);
9565
9566 // ~(~0 << length), where length is the # of remaining elements to process
9567 movl(tmp3_aliased, -1);
9568 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9569 notl(tmp3_aliased);
9570 kmovdl(mask, tmp3_aliased);
9571 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9572 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9573
9574 jmp(done);
9575 bind(avx3_threshold);
9576 }
9577 if (UseSSE42Intrinsics) {
9578 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9579
9580 if (UseAVX > 1) {
9581 andl(tmp2, (16 - 1));
9582 andl(len, -16);
9583 jccb(Assembler::zero, copy_new_tail);
9584 } else {
9585 andl(tmp2, 0x00000007); // tail count (in chars)
9586 andl(len, 0xfffffff8); // vector count (in chars)
9587 jccb(Assembler::zero, copy_tail);
9588 }
9589
9590 // vectored inflation
9591 lea(src, Address(src, len, Address::times_1));
9592 lea(dst, Address(dst, len, Address::times_2));
9593 negptr(len);
9594
9595 if (UseAVX > 1) {
9596 bind(copy_16_loop);
9597 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9598 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9599 addptr(len, 16);
9600 jcc(Assembler::notZero, copy_16_loop);
9601
9602 bind(below_threshold);
9603 bind(copy_new_tail);
9604 movl(len, tmp2);
9605 andl(tmp2, 0x00000007);
9606 andl(len, 0xFFFFFFF8);
9607 jccb(Assembler::zero, copy_tail);
9608
9609 pmovzxbw(tmp1, Address(src, 0));
9610 movdqu(Address(dst, 0), tmp1);
9611 addptr(src, 8);
9612 addptr(dst, 2 * 8);
9613
9614 jmp(copy_tail, true);
9615 }
9616
9617 // inflate 8 chars per iter
9618 bind(copy_8_loop);
9619 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9620 movdqu(Address(dst, len, Address::times_2), tmp1);
9621 addptr(len, 8);
9622 jcc(Assembler::notZero, copy_8_loop);
9623
9624 bind(copy_tail);
9625 movl(len, tmp2);
9626
9627 cmpl(len, 4);
9628 jccb(Assembler::less, copy_bytes);
9629
9630 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9631 pmovzxbw(tmp1, tmp1);
9632 movq(Address(dst, 0), tmp1);
9633 subptr(len, 4);
9634 addptr(src, 4);
9635 addptr(dst, 8);
9636
9637 bind(copy_bytes);
9638 } else {
9639 bind(below_threshold);
9640 }
9641
9642 testl(len, len);
9643 jccb(Assembler::zero, done);
9644 lea(src, Address(src, len, Address::times_1));
9645 lea(dst, Address(dst, len, Address::times_2));
9646 negptr(len);
9647
9648 // inflate 1 char per iter
9649 bind(copy_chars_loop);
9650 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9651 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9652 increment(len);
9653 jcc(Assembler::notZero, copy_chars_loop);
9654
9655 bind(done);
9656 }
9657
9658 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9659 switch(type) {
9660 case T_BYTE:
9661 case T_BOOLEAN:
9662 evmovdqub(dst, kmask, src, merge, vector_len);
9663 break;
9664 case T_CHAR:
9665 case T_SHORT:
9666 evmovdquw(dst, kmask, src, merge, vector_len);
9667 break;
9668 case T_INT:
9669 case T_FLOAT:
9670 evmovdqul(dst, kmask, src, merge, vector_len);
9671 break;
9672 case T_LONG:
9673 case T_DOUBLE:
9674 evmovdquq(dst, kmask, src, merge, vector_len);
9675 break;
9676 default:
9677 fatal("Unexpected type argument %s", type2name(type));
9678 break;
9679 }
9680 }
9681
9682
9683 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9684 switch(type) {
9685 case T_BYTE:
9686 case T_BOOLEAN:
9687 evmovdqub(dst, kmask, src, merge, vector_len);
9688 break;
9689 case T_CHAR:
9690 case T_SHORT:
9691 evmovdquw(dst, kmask, src, merge, vector_len);
9692 break;
9693 case T_INT:
9694 case T_FLOAT:
9695 evmovdqul(dst, kmask, src, merge, vector_len);
9696 break;
9697 case T_LONG:
9698 case T_DOUBLE:
9699 evmovdquq(dst, kmask, src, merge, vector_len);
9700 break;
9701 default:
9702 fatal("Unexpected type argument %s", type2name(type));
9703 break;
9704 }
9705 }
9706
9707 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9708 switch(type) {
9709 case T_BYTE:
9710 case T_BOOLEAN:
9711 evmovdqub(dst, kmask, src, merge, vector_len);
9712 break;
9713 case T_CHAR:
9714 case T_SHORT:
9715 evmovdquw(dst, kmask, src, merge, vector_len);
9716 break;
9717 case T_INT:
9718 case T_FLOAT:
9719 evmovdqul(dst, kmask, src, merge, vector_len);
9720 break;
9721 case T_LONG:
9722 case T_DOUBLE:
9723 evmovdquq(dst, kmask, src, merge, vector_len);
9724 break;
9725 default:
9726 fatal("Unexpected type argument %s", type2name(type));
9727 break;
9728 }
9729 }
9730
9731 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9732 switch(masklen) {
9733 case 2:
9734 knotbl(dst, src);
9735 movl(rtmp, 3);
9736 kmovbl(ktmp, rtmp);
9737 kandbl(dst, ktmp, dst);
9738 break;
9739 case 4:
9740 knotbl(dst, src);
9741 movl(rtmp, 15);
9742 kmovbl(ktmp, rtmp);
9743 kandbl(dst, ktmp, dst);
9744 break;
9745 case 8:
9746 knotbl(dst, src);
9747 break;
9748 case 16:
9749 knotwl(dst, src);
9750 break;
9751 case 32:
9752 knotdl(dst, src);
9753 break;
9754 case 64:
9755 knotql(dst, src);
9756 break;
9757 default:
9758 fatal("Unexpected vector length %d", masklen);
9759 break;
9760 }
9761 }
9762
9763 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9764 switch(type) {
9765 case T_BOOLEAN:
9766 case T_BYTE:
9767 kandbl(dst, src1, src2);
9768 break;
9769 case T_CHAR:
9770 case T_SHORT:
9771 kandwl(dst, src1, src2);
9772 break;
9773 case T_INT:
9774 case T_FLOAT:
9775 kanddl(dst, src1, src2);
9776 break;
9777 case T_LONG:
9778 case T_DOUBLE:
9779 kandql(dst, src1, src2);
9780 break;
9781 default:
9782 fatal("Unexpected type argument %s", type2name(type));
9783 break;
9784 }
9785 }
9786
9787 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9788 switch(type) {
9789 case T_BOOLEAN:
9790 case T_BYTE:
9791 korbl(dst, src1, src2);
9792 break;
9793 case T_CHAR:
9794 case T_SHORT:
9795 korwl(dst, src1, src2);
9796 break;
9797 case T_INT:
9798 case T_FLOAT:
9799 kordl(dst, src1, src2);
9800 break;
9801 case T_LONG:
9802 case T_DOUBLE:
9803 korql(dst, src1, src2);
9804 break;
9805 default:
9806 fatal("Unexpected type argument %s", type2name(type));
9807 break;
9808 }
9809 }
9810
9811 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9812 switch(type) {
9813 case T_BOOLEAN:
9814 case T_BYTE:
9815 kxorbl(dst, src1, src2);
9816 break;
9817 case T_CHAR:
9818 case T_SHORT:
9819 kxorwl(dst, src1, src2);
9820 break;
9821 case T_INT:
9822 case T_FLOAT:
9823 kxordl(dst, src1, src2);
9824 break;
9825 case T_LONG:
9826 case T_DOUBLE:
9827 kxorql(dst, src1, src2);
9828 break;
9829 default:
9830 fatal("Unexpected type argument %s", type2name(type));
9831 break;
9832 }
9833 }
9834
9835 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9836 switch(type) {
9837 case T_BOOLEAN:
9838 case T_BYTE:
9839 evpermb(dst, mask, nds, src, merge, vector_len); break;
9840 case T_CHAR:
9841 case T_SHORT:
9842 evpermw(dst, mask, nds, src, merge, vector_len); break;
9843 case T_INT:
9844 case T_FLOAT:
9845 evpermd(dst, mask, nds, src, merge, vector_len); break;
9846 case T_LONG:
9847 case T_DOUBLE:
9848 evpermq(dst, mask, nds, src, merge, vector_len); break;
9849 default:
9850 fatal("Unexpected type argument %s", type2name(type)); break;
9851 }
9852 }
9853
9854 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9855 switch(type) {
9856 case T_BOOLEAN:
9857 case T_BYTE:
9858 evpermb(dst, mask, nds, src, merge, vector_len); break;
9859 case T_CHAR:
9860 case T_SHORT:
9861 evpermw(dst, mask, nds, src, merge, vector_len); break;
9862 case T_INT:
9863 case T_FLOAT:
9864 evpermd(dst, mask, nds, src, merge, vector_len); break;
9865 case T_LONG:
9866 case T_DOUBLE:
9867 evpermq(dst, mask, nds, src, merge, vector_len); break;
9868 default:
9869 fatal("Unexpected type argument %s", type2name(type)); break;
9870 }
9871 }
9872
9873 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9874 switch(type) {
9875 case T_BYTE:
9876 evpminub(dst, mask, nds, src, merge, vector_len); break;
9877 case T_SHORT:
9878 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9879 case T_INT:
9880 evpminud(dst, mask, nds, src, merge, vector_len); break;
9881 case T_LONG:
9882 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9883 default:
9884 fatal("Unexpected type argument %s", type2name(type)); break;
9885 }
9886 }
9887
9888 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9889 switch(type) {
9890 case T_BYTE:
9891 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9892 case T_SHORT:
9893 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9894 case T_INT:
9895 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9896 case T_LONG:
9897 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9898 default:
9899 fatal("Unexpected type argument %s", type2name(type)); break;
9900 }
9901 }
9902
9903 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9904 switch(type) {
9905 case T_BYTE:
9906 evpminub(dst, mask, nds, src, merge, vector_len); break;
9907 case T_SHORT:
9908 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9909 case T_INT:
9910 evpminud(dst, mask, nds, src, merge, vector_len); break;
9911 case T_LONG:
9912 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9913 default:
9914 fatal("Unexpected type argument %s", type2name(type)); break;
9915 }
9916 }
9917
9918 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9919 switch(type) {
9920 case T_BYTE:
9921 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9922 case T_SHORT:
9923 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9924 case T_INT:
9925 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9926 case T_LONG:
9927 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9928 default:
9929 fatal("Unexpected type argument %s", type2name(type)); break;
9930 }
9931 }
9932
9933 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9934 switch(type) {
9935 case T_BYTE:
9936 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9937 case T_SHORT:
9938 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9939 case T_INT:
9940 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9941 case T_LONG:
9942 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9943 case T_FLOAT:
9944 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9945 case T_DOUBLE:
9946 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9947 default:
9948 fatal("Unexpected type argument %s", type2name(type)); break;
9949 }
9950 }
9951
9952 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9953 switch(type) {
9954 case T_BYTE:
9955 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9956 case T_SHORT:
9957 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9958 case T_INT:
9959 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9960 case T_LONG:
9961 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9962 case T_FLOAT:
9963 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9964 case T_DOUBLE:
9965 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9966 default:
9967 fatal("Unexpected type argument %s", type2name(type)); break;
9968 }
9969 }
9970
9971 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9972 switch(type) {
9973 case T_BYTE:
9974 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9975 case T_SHORT:
9976 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9977 case T_INT:
9978 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9979 case T_LONG:
9980 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9981 case T_FLOAT:
9982 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9983 case T_DOUBLE:
9984 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9985 default:
9986 fatal("Unexpected type argument %s", type2name(type)); break;
9987 }
9988 }
9989
9990 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9991 switch(type) {
9992 case T_BYTE:
9993 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9994 case T_SHORT:
9995 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9996 case T_INT:
9997 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9998 case T_LONG:
9999 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
10000 case T_FLOAT:
10001 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
10002 case T_DOUBLE:
10003 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
10004 default:
10005 fatal("Unexpected type argument %s", type2name(type)); break;
10006 }
10007 }
10008
10009 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10010 switch(type) {
10011 case T_INT:
10012 evpxord(dst, mask, nds, src, merge, vector_len); break;
10013 case T_LONG:
10014 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10015 default:
10016 fatal("Unexpected type argument %s", type2name(type)); break;
10017 }
10018 }
10019
10020 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10021 switch(type) {
10022 case T_INT:
10023 evpxord(dst, mask, nds, src, merge, vector_len); break;
10024 case T_LONG:
10025 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10026 default:
10027 fatal("Unexpected type argument %s", type2name(type)); break;
10028 }
10029 }
10030
10031 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10032 switch(type) {
10033 case T_INT:
10034 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10035 case T_LONG:
10036 evporq(dst, mask, nds, src, merge, vector_len); break;
10037 default:
10038 fatal("Unexpected type argument %s", type2name(type)); break;
10039 }
10040 }
10041
10042 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10043 switch(type) {
10044 case T_INT:
10045 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10046 case T_LONG:
10047 evporq(dst, mask, nds, src, merge, vector_len); break;
10048 default:
10049 fatal("Unexpected type argument %s", type2name(type)); break;
10050 }
10051 }
10052
10053 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10054 switch(type) {
10055 case T_INT:
10056 evpandd(dst, mask, nds, src, merge, vector_len); break;
10057 case T_LONG:
10058 evpandq(dst, mask, nds, src, merge, vector_len); break;
10059 default:
10060 fatal("Unexpected type argument %s", type2name(type)); break;
10061 }
10062 }
10063
10064 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10065 switch(type) {
10066 case T_INT:
10067 evpandd(dst, mask, nds, src, merge, vector_len); break;
10068 case T_LONG:
10069 evpandq(dst, mask, nds, src, merge, vector_len); break;
10070 default:
10071 fatal("Unexpected type argument %s", type2name(type)); break;
10072 }
10073 }
10074
10075 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
10076 switch(masklen) {
10077 case 8:
10078 kortestbl(src1, src2);
10079 break;
10080 case 16:
10081 kortestwl(src1, src2);
10082 break;
10083 case 32:
10084 kortestdl(src1, src2);
10085 break;
10086 case 64:
10087 kortestql(src1, src2);
10088 break;
10089 default:
10090 fatal("Unexpected mask length %d", masklen);
10091 break;
10092 }
10093 }
10094
10095
10096 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
10097 switch(masklen) {
10098 case 8:
10099 ktestbl(src1, src2);
10100 break;
10101 case 16:
10102 ktestwl(src1, src2);
10103 break;
10104 case 32:
10105 ktestdl(src1, src2);
10106 break;
10107 case 64:
10108 ktestql(src1, src2);
10109 break;
10110 default:
10111 fatal("Unexpected mask length %d", masklen);
10112 break;
10113 }
10114 }
10115
10116 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10117 switch(type) {
10118 case T_INT:
10119 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10120 case T_LONG:
10121 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10122 default:
10123 fatal("Unexpected type argument %s", type2name(type)); break;
10124 break;
10125 }
10126 }
10127
10128 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10129 switch(type) {
10130 case T_INT:
10131 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10132 case T_LONG:
10133 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10134 default:
10135 fatal("Unexpected type argument %s", type2name(type)); break;
10136 }
10137 }
10138
10139 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10140 switch(type) {
10141 case T_INT:
10142 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10143 case T_LONG:
10144 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10145 default:
10146 fatal("Unexpected type argument %s", type2name(type)); break;
10147 }
10148 }
10149
10150 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10151 switch(type) {
10152 case T_INT:
10153 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10154 case T_LONG:
10155 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10156 default:
10157 fatal("Unexpected type argument %s", type2name(type)); break;
10158 }
10159 }
10160
10161 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10162 assert(rscratch != noreg || always_reachable(src), "missing");
10163
10164 if (reachable(src)) {
10165 evpandq(dst, nds, as_Address(src), vector_len);
10166 } else {
10167 lea(rscratch, src);
10168 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10169 }
10170 }
10171
10172 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10173 assert(rscratch != noreg || always_reachable(src), "missing");
10174
10175 if (reachable(src)) {
10176 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10177 } else {
10178 lea(rscratch, src);
10179 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10180 }
10181 }
10182
10183 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10184 assert(rscratch != noreg || always_reachable(src), "missing");
10185
10186 if (reachable(src)) {
10187 evporq(dst, nds, as_Address(src), vector_len);
10188 } else {
10189 lea(rscratch, src);
10190 evporq(dst, nds, Address(rscratch, 0), vector_len);
10191 }
10192 }
10193
10194 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10195 assert(rscratch != noreg || always_reachable(src), "missing");
10196
10197 if (reachable(src)) {
10198 vpshufb(dst, nds, as_Address(src), vector_len);
10199 } else {
10200 lea(rscratch, src);
10201 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10202 }
10203 }
10204
10205 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10206 assert(rscratch != noreg || always_reachable(src), "missing");
10207
10208 if (reachable(src)) {
10209 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10210 } else {
10211 lea(rscratch, src);
10212 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10213 }
10214 }
10215
10216 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10217 assert(rscratch != noreg || always_reachable(src3), "missing");
10218
10219 if (reachable(src3)) {
10220 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10221 } else {
10222 lea(rscratch, src3);
10223 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10224 }
10225 }
10226
10227 #if COMPILER2_OR_JVMCI
10228
10229 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10230 Register length, Register temp, int vec_enc) {
10231 // Computing mask for predicated vector store.
10232 movptr(temp, -1);
10233 bzhiq(temp, temp, length);
10234 kmov(mask, temp);
10235 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10236 }
10237
10238 // Set memory operation for length "less than" 64 bytes.
10239 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10240 XMMRegister xmm, KRegister mask, Register length,
10241 Register temp, bool use64byteVector) {
10242 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10243 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10244 if (!use64byteVector) {
10245 fill32(dst, disp, xmm);
10246 subptr(length, 32 >> shift);
10247 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10248 } else {
10249 assert(MaxVectorSize == 64, "vector length != 64");
10250 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10251 }
10252 }
10253
10254
10255 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10256 XMMRegister xmm, KRegister mask, Register length,
10257 Register temp) {
10258 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10259 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10260 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10261 }
10262
10263
10264 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10265 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10266 vmovdqu(dst, xmm);
10267 }
10268
10269 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10270 fill32(Address(dst, disp), xmm);
10271 }
10272
10273 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10274 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10275 if (!use64byteVector) {
10276 fill32(dst, xmm);
10277 fill32(dst.plus_disp(32), xmm);
10278 } else {
10279 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10280 }
10281 }
10282
10283 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10284 fill64(Address(dst, disp), xmm, use64byteVector);
10285 }
10286
10287 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10288 Register count, Register rtmp, XMMRegister xtmp) {
10289 Label L_exit;
10290 Label L_fill_start;
10291 Label L_fill_64_bytes;
10292 Label L_fill_96_bytes;
10293 Label L_fill_128_bytes;
10294 Label L_fill_128_bytes_loop;
10295 Label L_fill_128_loop_header;
10296 Label L_fill_128_bytes_loop_header;
10297 Label L_fill_128_bytes_loop_pre_header;
10298 Label L_fill_zmm_sequence;
10299
10300 int shift = -1;
10301 switch(type) {
10302 case T_BYTE: shift = 0;
10303 break;
10304 case T_SHORT: shift = 1;
10305 break;
10306 case T_INT: shift = 2;
10307 break;
10308 /* Uncomment when LONG fill stubs are supported.
10309 case T_LONG: shift = 3;
10310 break;
10311 */
10312 default:
10313 fatal("Unhandled type: %s\n", type2name(type));
10314 }
10315
10316 if ((CopyAVX3Threshold != 0) || (MaxVectorSize == 32)) {
10317
10318 if (MaxVectorSize == 64) {
10319 cmpq(count, CopyAVX3Threshold >> shift);
10320 jcc(Assembler::greater, L_fill_zmm_sequence);
10321 }
10322
10323 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10324
10325 bind(L_fill_start);
10326
10327 cmpq(count, 32 >> shift);
10328 jccb(Assembler::greater, L_fill_64_bytes);
10329 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10330 jmp(L_exit);
10331
10332 bind(L_fill_64_bytes);
10333 cmpq(count, 64 >> shift);
10334 jccb(Assembler::greater, L_fill_96_bytes);
10335 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10336 jmp(L_exit);
10337
10338 bind(L_fill_96_bytes);
10339 cmpq(count, 96 >> shift);
10340 jccb(Assembler::greater, L_fill_128_bytes);
10341 fill64(to, 0, xtmp);
10342 subq(count, 64 >> shift);
10343 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10344 jmp(L_exit);
10345
10346 bind(L_fill_128_bytes);
10347 cmpq(count, 128 >> shift);
10348 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10349 fill64(to, 0, xtmp);
10350 fill32(to, 64, xtmp);
10351 subq(count, 96 >> shift);
10352 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10353 jmp(L_exit);
10354
10355 bind(L_fill_128_bytes_loop_pre_header);
10356 {
10357 mov(rtmp, to);
10358 andq(rtmp, 31);
10359 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10360 negq(rtmp);
10361 addq(rtmp, 32);
10362 mov64(r8, -1L);
10363 bzhiq(r8, r8, rtmp);
10364 kmovql(k2, r8);
10365 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10366 addq(to, rtmp);
10367 shrq(rtmp, shift);
10368 subq(count, rtmp);
10369 }
10370
10371 cmpq(count, 128 >> shift);
10372 jcc(Assembler::less, L_fill_start);
10373
10374 bind(L_fill_128_bytes_loop_header);
10375 subq(count, 128 >> shift);
10376
10377 align32();
10378 bind(L_fill_128_bytes_loop);
10379 fill64(to, 0, xtmp);
10380 fill64(to, 64, xtmp);
10381 addq(to, 128);
10382 subq(count, 128 >> shift);
10383 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10384
10385 addq(count, 128 >> shift);
10386 jcc(Assembler::zero, L_exit);
10387 jmp(L_fill_start);
10388 }
10389
10390 if (MaxVectorSize == 64) {
10391 // Sequence using 64 byte ZMM register.
10392 Label L_fill_128_bytes_zmm;
10393 Label L_fill_192_bytes_zmm;
10394 Label L_fill_192_bytes_loop_zmm;
10395 Label L_fill_192_bytes_loop_header_zmm;
10396 Label L_fill_192_bytes_loop_pre_header_zmm;
10397 Label L_fill_start_zmm_sequence;
10398
10399 bind(L_fill_zmm_sequence);
10400 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10401
10402 bind(L_fill_start_zmm_sequence);
10403 cmpq(count, 64 >> shift);
10404 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10405 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10406 jmp(L_exit);
10407
10408 bind(L_fill_128_bytes_zmm);
10409 cmpq(count, 128 >> shift);
10410 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10411 fill64(to, 0, xtmp, true);
10412 subq(count, 64 >> shift);
10413 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10414 jmp(L_exit);
10415
10416 bind(L_fill_192_bytes_zmm);
10417 cmpq(count, 192 >> shift);
10418 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10419 fill64(to, 0, xtmp, true);
10420 fill64(to, 64, xtmp, true);
10421 subq(count, 128 >> shift);
10422 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10423 jmp(L_exit);
10424
10425 bind(L_fill_192_bytes_loop_pre_header_zmm);
10426 {
10427 movq(rtmp, to);
10428 andq(rtmp, 63);
10429 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10430 negq(rtmp);
10431 addq(rtmp, 64);
10432 mov64(r8, -1L);
10433 bzhiq(r8, r8, rtmp);
10434 kmovql(k2, r8);
10435 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10436 addq(to, rtmp);
10437 shrq(rtmp, shift);
10438 subq(count, rtmp);
10439 }
10440
10441 cmpq(count, 192 >> shift);
10442 jcc(Assembler::less, L_fill_start_zmm_sequence);
10443
10444 bind(L_fill_192_bytes_loop_header_zmm);
10445 subq(count, 192 >> shift);
10446
10447 align32();
10448 bind(L_fill_192_bytes_loop_zmm);
10449 fill64(to, 0, xtmp, true);
10450 fill64(to, 64, xtmp, true);
10451 fill64(to, 128, xtmp, true);
10452 addq(to, 192);
10453 subq(count, 192 >> shift);
10454 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10455
10456 addq(count, 192 >> shift);
10457 jcc(Assembler::zero, L_exit);
10458 jmp(L_fill_start_zmm_sequence);
10459 }
10460 bind(L_exit);
10461 }
10462 #endif //COMPILER2_OR_JVMCI
10463
10464
10465 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10466 Label done;
10467 cvttss2sil(dst, src);
10468 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10469 cmpl(dst, 0x80000000); // float_sign_flip
10470 jccb(Assembler::notEqual, done);
10471 subptr(rsp, 8);
10472 movflt(Address(rsp, 0), src);
10473 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10474 pop(dst);
10475 bind(done);
10476 }
10477
10478 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10479 Label done;
10480 cvttsd2sil(dst, src);
10481 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10482 cmpl(dst, 0x80000000); // float_sign_flip
10483 jccb(Assembler::notEqual, done);
10484 subptr(rsp, 8);
10485 movdbl(Address(rsp, 0), src);
10486 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10487 pop(dst);
10488 bind(done);
10489 }
10490
10491 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10492 Label done;
10493 cvttss2siq(dst, src);
10494 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10495 jccb(Assembler::notEqual, done);
10496 subptr(rsp, 8);
10497 movflt(Address(rsp, 0), src);
10498 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10499 pop(dst);
10500 bind(done);
10501 }
10502
10503 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10504 // Following code is line by line assembly translation rounding algorithm.
10505 // Please refer to java.lang.Math.round(float) algorithm for details.
10506 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10507 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10508 const int32_t FloatConsts_EXP_BIAS = 127;
10509 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10510 const int32_t MINUS_32 = 0xFFFFFFE0;
10511 Label L_special_case, L_block1, L_exit;
10512 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10513 movdl(dst, src);
10514 andl(dst, rtmp);
10515 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10516 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10517 subl(rtmp, dst);
10518 movl(rcx, rtmp);
10519 movl(dst, MINUS_32);
10520 testl(rtmp, dst);
10521 jccb(Assembler::notEqual, L_special_case);
10522 movdl(dst, src);
10523 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10524 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10525 movdl(rtmp, src);
10526 testl(rtmp, rtmp);
10527 jccb(Assembler::greaterEqual, L_block1);
10528 negl(dst);
10529 bind(L_block1);
10530 sarl(dst);
10531 addl(dst, 0x1);
10532 sarl(dst, 0x1);
10533 jmp(L_exit);
10534 bind(L_special_case);
10535 convert_f2i(dst, src);
10536 bind(L_exit);
10537 }
10538
10539 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10540 // Following code is line by line assembly translation rounding algorithm.
10541 // Please refer to java.lang.Math.round(double) algorithm for details.
10542 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10543 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10544 const int64_t DoubleConsts_EXP_BIAS = 1023;
10545 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10546 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10547 Label L_special_case, L_block1, L_exit;
10548 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10549 movq(dst, src);
10550 andq(dst, rtmp);
10551 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10552 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10553 subq(rtmp, dst);
10554 movq(rcx, rtmp);
10555 mov64(dst, MINUS_64);
10556 testq(rtmp, dst);
10557 jccb(Assembler::notEqual, L_special_case);
10558 movq(dst, src);
10559 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10560 andq(dst, rtmp);
10561 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10562 orq(dst, rtmp);
10563 movq(rtmp, src);
10564 testq(rtmp, rtmp);
10565 jccb(Assembler::greaterEqual, L_block1);
10566 negq(dst);
10567 bind(L_block1);
10568 sarq(dst);
10569 addq(dst, 0x1);
10570 sarq(dst, 0x1);
10571 jmp(L_exit);
10572 bind(L_special_case);
10573 convert_d2l(dst, src);
10574 bind(L_exit);
10575 }
10576
10577 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10578 Label done;
10579 cvttsd2siq(dst, src);
10580 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10581 jccb(Assembler::notEqual, done);
10582 subptr(rsp, 8);
10583 movdbl(Address(rsp, 0), src);
10584 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10585 pop(dst);
10586 bind(done);
10587 }
10588
10589 void MacroAssembler::cache_wb(Address line)
10590 {
10591 // 64 bit cpus always support clflush
10592 assert(VM_Version::supports_clflush(), "clflush should be available");
10593 bool optimized = VM_Version::supports_clflushopt();
10594 bool no_evict = VM_Version::supports_clwb();
10595
10596 // prefer clwb (writeback without evict) otherwise
10597 // prefer clflushopt (potentially parallel writeback with evict)
10598 // otherwise fallback on clflush (serial writeback with evict)
10599
10600 if (optimized) {
10601 if (no_evict) {
10602 clwb(line);
10603 } else {
10604 clflushopt(line);
10605 }
10606 } else {
10607 // no need for fence when using CLFLUSH
10608 clflush(line);
10609 }
10610 }
10611
10612 void MacroAssembler::cache_wbsync(bool is_pre)
10613 {
10614 assert(VM_Version::supports_clflush(), "clflush should be available");
10615 bool optimized = VM_Version::supports_clflushopt();
10616 bool no_evict = VM_Version::supports_clwb();
10617
10618 // pick the correct implementation
10619
10620 if (!is_pre && (optimized || no_evict)) {
10621 // need an sfence for post flush when using clflushopt or clwb
10622 // otherwise no no need for any synchroniaztion
10623
10624 sfence();
10625 }
10626 }
10627
10628 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10629 switch (cond) {
10630 // Note some conditions are synonyms for others
10631 case Assembler::zero: return Assembler::notZero;
10632 case Assembler::notZero: return Assembler::zero;
10633 case Assembler::less: return Assembler::greaterEqual;
10634 case Assembler::lessEqual: return Assembler::greater;
10635 case Assembler::greater: return Assembler::lessEqual;
10636 case Assembler::greaterEqual: return Assembler::less;
10637 case Assembler::below: return Assembler::aboveEqual;
10638 case Assembler::belowEqual: return Assembler::above;
10639 case Assembler::above: return Assembler::belowEqual;
10640 case Assembler::aboveEqual: return Assembler::below;
10641 case Assembler::overflow: return Assembler::noOverflow;
10642 case Assembler::noOverflow: return Assembler::overflow;
10643 case Assembler::negative: return Assembler::positive;
10644 case Assembler::positive: return Assembler::negative;
10645 case Assembler::parity: return Assembler::noParity;
10646 case Assembler::noParity: return Assembler::parity;
10647 }
10648 ShouldNotReachHere(); return Assembler::overflow;
10649 }
10650
10651 // This is simply a call to Thread::current()
10652 void MacroAssembler::get_thread_slow(Register thread) {
10653 if (thread != rax) {
10654 push(rax);
10655 }
10656 push(rdi);
10657 push(rsi);
10658 push(rdx);
10659 push(rcx);
10660 push(r8);
10661 push(r9);
10662 push(r10);
10663 push(r11);
10664
10665 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10666
10667 pop(r11);
10668 pop(r10);
10669 pop(r9);
10670 pop(r8);
10671 pop(rcx);
10672 pop(rdx);
10673 pop(rsi);
10674 pop(rdi);
10675 if (thread != rax) {
10676 mov(thread, rax);
10677 pop(rax);
10678 }
10679 }
10680
10681 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10682 Label L_stack_ok;
10683 if (bias == 0) {
10684 testptr(sp, 2 * wordSize - 1);
10685 } else {
10686 // lea(tmp, Address(rsp, bias);
10687 mov(tmp, sp);
10688 addptr(tmp, bias);
10689 testptr(tmp, 2 * wordSize - 1);
10690 }
10691 jcc(Assembler::equal, L_stack_ok);
10692 block_comment(msg);
10693 stop(msg);
10694 bind(L_stack_ok);
10695 }
10696
10697 // Implements fast-locking.
10698 //
10699 // obj: the object to be locked
10700 // reg_rax: rax
10701 // thread: the thread which attempts to lock obj
10702 // tmp: a temporary register
10703 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow) {
10704 Register thread = r15_thread;
10705
10706 assert(reg_rax == rax, "");
10707 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10708
10709 Label push;
10710 const Register top = tmp;
10711
10712 // Preload the markWord. It is important that this is the first
10713 // instruction emitted as it is part of C1's null check semantics.
10714 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10715
10716 if (UseObjectMonitorTable) {
10717 // Clear cache in case fast locking succeeds or we need to take the slow-path.
10718 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10719 }
10720
10721 if (DiagnoseSyncOnValueBasedClasses != 0) {
10722 load_klass(tmp, obj, rscratch1);
10723 testb(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
10724 jcc(Assembler::notZero, slow);
10725 }
10726
10727 // Load top.
10728 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10729
10730 // Check if the lock-stack is full.
10731 cmpl(top, LockStack::end_offset());
10732 jcc(Assembler::greaterEqual, slow);
10733
10734 // Check for recursion.
10735 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10736 jcc(Assembler::equal, push);
10737
10738 // Check header for monitor (0b10).
10739 testptr(reg_rax, markWord::monitor_value);
10740 jcc(Assembler::notZero, slow);
10741
10742 // Try to lock. Transition lock bits 0b01 => 0b00
10743 movptr(tmp, reg_rax);
10744 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10745 orptr(reg_rax, markWord::unlocked_value);
10746 // Mask inline_type bit such that we go to the slow path if object is an inline type
10747 andptr(reg_rax, ~((int) markWord::inline_type_bit_in_place));
10748
10749 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10750 jcc(Assembler::notEqual, slow);
10751
10752 // Restore top, CAS clobbers register.
10753 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10754
10755 bind(push);
10756 // After successful lock, push object on lock-stack.
10757 movptr(Address(thread, top), obj);
10758 incrementl(top, oopSize);
10759 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10760 }
10761
10762 // Implements fast-unlocking.
10763 //
10764 // obj: the object to be unlocked
10765 // reg_rax: rax
10766 // thread: the thread
10767 // tmp: a temporary register
10768 void MacroAssembler::fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow) {
10769 Register thread = r15_thread;
10770
10771 assert(reg_rax == rax, "");
10772 assert_different_registers(obj, reg_rax, thread, tmp);
10773
10774 Label unlocked, push_and_slow;
10775 const Register top = tmp;
10776
10777 // Check if obj is top of lock-stack.
10778 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10779 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10780 jcc(Assembler::notEqual, slow);
10781
10782 // Pop lock-stack.
10783 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10784 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10785
10786 // Check if recursive.
10787 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10788 jcc(Assembler::equal, unlocked);
10789
10790 // Not recursive. Check header for monitor (0b10).
10791 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10792 testptr(reg_rax, markWord::monitor_value);
10793 jcc(Assembler::notZero, push_and_slow);
10794
10795 #ifdef ASSERT
10796 // Check header not unlocked (0b01).
10797 Label not_unlocked;
10798 testptr(reg_rax, markWord::unlocked_value);
10799 jcc(Assembler::zero, not_unlocked);
10800 stop("fast_unlock already unlocked");
10801 bind(not_unlocked);
10802 #endif
10803
10804 // Try to unlock. Transition lock bits 0b00 => 0b01
10805 movptr(tmp, reg_rax);
10806 orptr(tmp, markWord::unlocked_value);
10807 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10808 jcc(Assembler::equal, unlocked);
10809
10810 bind(push_and_slow);
10811 // Restore lock-stack and handle the unlock in runtime.
10812 #ifdef ASSERT
10813 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10814 movptr(Address(thread, top), obj);
10815 #endif
10816 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10817 jmp(slow);
10818
10819 bind(unlocked);
10820 }
10821
10822 // Saves legacy GPRs state on stack.
10823 void MacroAssembler::save_legacy_gprs() {
10824 subq(rsp, 16 * wordSize);
10825 movq(Address(rsp, 15 * wordSize), rax);
10826 movq(Address(rsp, 14 * wordSize), rcx);
10827 movq(Address(rsp, 13 * wordSize), rdx);
10828 movq(Address(rsp, 12 * wordSize), rbx);
10829 movq(Address(rsp, 10 * wordSize), rbp);
10830 movq(Address(rsp, 9 * wordSize), rsi);
10831 movq(Address(rsp, 8 * wordSize), rdi);
10832 movq(Address(rsp, 7 * wordSize), r8);
10833 movq(Address(rsp, 6 * wordSize), r9);
10834 movq(Address(rsp, 5 * wordSize), r10);
10835 movq(Address(rsp, 4 * wordSize), r11);
10836 movq(Address(rsp, 3 * wordSize), r12);
10837 movq(Address(rsp, 2 * wordSize), r13);
10838 movq(Address(rsp, wordSize), r14);
10839 movq(Address(rsp, 0), r15);
10840 }
10841
10842 // Resotres back legacy GPRs state from stack.
10843 void MacroAssembler::restore_legacy_gprs() {
10844 movq(r15, Address(rsp, 0));
10845 movq(r14, Address(rsp, wordSize));
10846 movq(r13, Address(rsp, 2 * wordSize));
10847 movq(r12, Address(rsp, 3 * wordSize));
10848 movq(r11, Address(rsp, 4 * wordSize));
10849 movq(r10, Address(rsp, 5 * wordSize));
10850 movq(r9, Address(rsp, 6 * wordSize));
10851 movq(r8, Address(rsp, 7 * wordSize));
10852 movq(rdi, Address(rsp, 8 * wordSize));
10853 movq(rsi, Address(rsp, 9 * wordSize));
10854 movq(rbp, Address(rsp, 10 * wordSize));
10855 movq(rbx, Address(rsp, 12 * wordSize));
10856 movq(rdx, Address(rsp, 13 * wordSize));
10857 movq(rcx, Address(rsp, 14 * wordSize));
10858 movq(rax, Address(rsp, 15 * wordSize));
10859 addq(rsp, 16 * wordSize);
10860 }
10861
10862 void MacroAssembler::load_aotrc_address(Register reg, address a) {
10863 #if INCLUDE_CDS
10864 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
10865 if (AOTCodeCache::is_on_for_dump()) {
10866 // all aotrc field addresses should be registered in the AOTCodeCache address table
10867 lea(reg, ExternalAddress(a));
10868 } else {
10869 mov64(reg, (uint64_t)a);
10870 }
10871 #else
10872 ShouldNotReachHere();
10873 #endif
10874 }
10875
10876 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10877 if (VM_Version::supports_apx_f()) {
10878 esetzucc(comparison, dst);
10879 } else {
10880 setb(comparison, dst);
10881 movzbl(dst, dst);
10882 }
10883 }