1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/aotCodeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "ci/ciInlineKlass.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "interpreter/interpreterRuntime.hpp"
40 #include "jvm.h"
41 #include "memory/resourceArea.hpp"
42 #include "memory/universe.hpp"
43 #include "oops/accessDecorators.hpp"
44 #include "oops/compressedKlass.inline.hpp"
45 #include "oops/compressedOops.inline.hpp"
46 #include "oops/klass.inline.hpp"
47 #include "oops/resolvedFieldEntry.hpp"
48 #include "prims/methodHandles.hpp"
49 #include "runtime/continuation.hpp"
50 #include "runtime/interfaceSupport.inline.hpp"
51 #include "runtime/javaThread.hpp"
52 #include "runtime/jniHandles.hpp"
53 #include "runtime/objectMonitor.hpp"
54 #include "runtime/os.hpp"
55 #include "runtime/safepoint.hpp"
56 #include "runtime/safepointMechanism.hpp"
57 #include "runtime/sharedRuntime.hpp"
58 #include "runtime/signature_cc.hpp"
59 #include "runtime/stubRoutines.hpp"
60 #include "utilities/checkedCast.hpp"
61 #include "utilities/macros.hpp"
62 #include "vmreg_x86.inline.hpp"
63 #ifdef COMPILER2
64 #include "opto/output.hpp"
65 #endif
66
67 #ifdef PRODUCT
68 #define BLOCK_COMMENT(str) /* nothing */
69 #define STOP(error) stop(error)
70 #else
71 #define BLOCK_COMMENT(str) block_comment(str)
72 #define STOP(error) block_comment(error); stop(error)
73 #endif
74
75 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
76
77 #ifdef ASSERT
78 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
79 #endif
80
81 static const Assembler::Condition reverse[] = {
82 Assembler::noOverflow /* overflow = 0x0 */ ,
83 Assembler::overflow /* noOverflow = 0x1 */ ,
84 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
85 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
86 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
87 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
88 Assembler::above /* belowEqual = 0x6 */ ,
89 Assembler::belowEqual /* above = 0x7 */ ,
90 Assembler::positive /* negative = 0x8 */ ,
91 Assembler::negative /* positive = 0x9 */ ,
92 Assembler::noParity /* parity = 0xa */ ,
93 Assembler::parity /* noParity = 0xb */ ,
94 Assembler::greaterEqual /* less = 0xc */ ,
95 Assembler::less /* greaterEqual = 0xd */ ,
96 Assembler::greater /* lessEqual = 0xe */ ,
97 Assembler::lessEqual /* greater = 0xf, */
98
99 };
100
101
102 // Implementation of MacroAssembler
103
104 Address MacroAssembler::as_Address(AddressLiteral adr) {
105 // amd64 always does this as a pc-rel
106 // we can be absolute or disp based on the instruction type
107 // jmp/call are displacements others are absolute
108 assert(!adr.is_lval(), "must be rval");
109 assert(reachable(adr), "must be");
110 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
111
112 }
113
114 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
115 AddressLiteral base = adr.base();
116 lea(rscratch, base);
117 Address index = adr.index();
118 assert(index._disp == 0, "must not have disp"); // maybe it can?
119 Address array(rscratch, index._index, index._scale, index._disp);
120 return array;
121 }
122
123 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
124 Label L, E;
125
126 #ifdef _WIN64
127 // Windows always allocates space for it's register args
128 assert(num_args <= 4, "only register arguments supported");
129 subq(rsp, frame::arg_reg_save_area_bytes);
130 #endif
131
132 // Align stack if necessary
133 testl(rsp, 15);
134 jcc(Assembler::zero, L);
135
136 subq(rsp, 8);
137 call(RuntimeAddress(entry_point));
138 addq(rsp, 8);
139 jmp(E);
140
141 bind(L);
142 call(RuntimeAddress(entry_point));
143
144 bind(E);
145
146 #ifdef _WIN64
147 // restore stack pointer
148 addq(rsp, frame::arg_reg_save_area_bytes);
149 #endif
150 }
151
152 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
153 assert(!src2.is_lval(), "should use cmpptr");
154 assert(rscratch != noreg || always_reachable(src2), "missing");
155
156 if (reachable(src2)) {
157 cmpq(src1, as_Address(src2));
158 } else {
159 lea(rscratch, src2);
160 Assembler::cmpq(src1, Address(rscratch, 0));
161 }
162 }
163
164 int MacroAssembler::corrected_idivq(Register reg) {
165 // Full implementation of Java ldiv and lrem; checks for special
166 // case as described in JVM spec., p.243 & p.271. The function
167 // returns the (pc) offset of the idivl instruction - may be needed
168 // for implicit exceptions.
169 //
170 // normal case special case
171 //
172 // input : rax: dividend min_long
173 // reg: divisor (may not be eax/edx) -1
174 //
175 // output: rax: quotient (= rax idiv reg) min_long
176 // rdx: remainder (= rax irem reg) 0
177 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
178 static const int64_t min_long = 0x8000000000000000;
179 Label normal_case, special_case;
180
181 // check for special case
182 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
183 jcc(Assembler::notEqual, normal_case);
184 xorl(rdx, rdx); // prepare rdx for possible special case (where
185 // remainder = 0)
186 cmpq(reg, -1);
187 jcc(Assembler::equal, special_case);
188
189 // handle normal case
190 bind(normal_case);
191 cdqq();
192 int idivq_offset = offset();
193 idivq(reg);
194
195 // normal and special case exit
196 bind(special_case);
197
198 return idivq_offset;
199 }
200
201 void MacroAssembler::decrementq(Register reg, int value) {
202 if (value == min_jint) { subq(reg, value); return; }
203 if (value < 0) { incrementq(reg, -value); return; }
204 if (value == 0) { ; return; }
205 if (value == 1 && UseIncDec) { decq(reg) ; return; }
206 /* else */ { subq(reg, value) ; return; }
207 }
208
209 void MacroAssembler::decrementq(Address dst, int value) {
210 if (value == min_jint) { subq(dst, value); return; }
211 if (value < 0) { incrementq(dst, -value); return; }
212 if (value == 0) { ; return; }
213 if (value == 1 && UseIncDec) { decq(dst) ; return; }
214 /* else */ { subq(dst, value) ; return; }
215 }
216
217 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
218 assert(rscratch != noreg || always_reachable(dst), "missing");
219
220 if (reachable(dst)) {
221 incrementq(as_Address(dst));
222 } else {
223 lea(rscratch, dst);
224 incrementq(Address(rscratch, 0));
225 }
226 }
227
228 void MacroAssembler::incrementq(Register reg, int value) {
229 if (value == min_jint) { addq(reg, value); return; }
230 if (value < 0) { decrementq(reg, -value); return; }
231 if (value == 0) { ; return; }
232 if (value == 1 && UseIncDec) { incq(reg) ; return; }
233 /* else */ { addq(reg, value) ; return; }
234 }
235
236 void MacroAssembler::incrementq(Address dst, int value) {
237 if (value == min_jint) { addq(dst, value); return; }
238 if (value < 0) { decrementq(dst, -value); return; }
239 if (value == 0) { ; return; }
240 if (value == 1 && UseIncDec) { incq(dst) ; return; }
241 /* else */ { addq(dst, value) ; return; }
242 }
243
244 // 32bit can do a case table jump in one instruction but we no longer allow the base
245 // to be installed in the Address class
246 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
247 lea(rscratch, entry.base());
248 Address dispatch = entry.index();
249 assert(dispatch._base == noreg, "must be");
250 dispatch._base = rscratch;
251 jmp(dispatch);
252 }
253
254 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
255 ShouldNotReachHere(); // 64bit doesn't use two regs
256 cmpq(x_lo, y_lo);
257 }
258
259 void MacroAssembler::lea(Register dst, AddressLiteral src) {
260 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
261 }
262
263 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
264 lea(rscratch, adr);
265 movptr(dst, rscratch);
266 }
267
268 void MacroAssembler::leave() {
269 // %%% is this really better? Why not on 32bit too?
270 emit_int8((unsigned char)0xC9); // LEAVE
271 }
272
273 void MacroAssembler::lneg(Register hi, Register lo) {
274 ShouldNotReachHere(); // 64bit doesn't use two regs
275 negq(lo);
276 }
277
278 void MacroAssembler::movoop(Register dst, jobject obj) {
279 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
280 }
281
282 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
283 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
284 movq(dst, rscratch);
285 }
286
287 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
288 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
289 }
290
291 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
292 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
293 movq(dst, rscratch);
294 }
295
296 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
297 if (src.is_lval()) {
298 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
299 } else {
300 if (reachable(src)) {
301 movq(dst, as_Address(src));
302 } else {
303 lea(dst, src);
304 movq(dst, Address(dst, 0));
305 }
306 }
307 }
308
309 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
310 movq(as_Address(dst, rscratch), src);
311 }
312
313 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
314 movq(dst, as_Address(src, dst /*rscratch*/));
315 }
316
317 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
318 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
319 if (is_simm32(src)) {
320 movptr(dst, checked_cast<int32_t>(src));
321 } else {
322 mov64(rscratch, src);
323 movq(dst, rscratch);
324 }
325 }
326
327 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
328 movoop(rscratch, obj);
329 push(rscratch);
330 }
331
332 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
333 mov_metadata(rscratch, obj);
334 push(rscratch);
335 }
336
337 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
338 lea(rscratch, src);
339 if (src.is_lval()) {
340 push(rscratch);
341 } else {
342 pushq(Address(rscratch, 0));
343 }
344 }
345
346 static void pass_arg0(MacroAssembler* masm, Register arg) {
347 if (c_rarg0 != arg ) {
348 masm->mov(c_rarg0, arg);
349 }
350 }
351
352 static void pass_arg1(MacroAssembler* masm, Register arg) {
353 if (c_rarg1 != arg ) {
354 masm->mov(c_rarg1, arg);
355 }
356 }
357
358 static void pass_arg2(MacroAssembler* masm, Register arg) {
359 if (c_rarg2 != arg ) {
360 masm->mov(c_rarg2, arg);
361 }
362 }
363
364 static void pass_arg3(MacroAssembler* masm, Register arg) {
365 if (c_rarg3 != arg ) {
366 masm->mov(c_rarg3, arg);
367 }
368 }
369
370 void MacroAssembler::stop(const char* msg) {
371 if (ShowMessageBoxOnError) {
372 address rip = pc();
373 pusha(); // get regs on stack
374 lea(c_rarg1, InternalAddress(rip));
375 movq(c_rarg2, rsp); // pass pointer to regs array
376 }
377 // Skip AOT caching C strings in scratch buffer.
378 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
379 lea(c_rarg0, ExternalAddress((address) str));
380 andq(rsp, -16); // align stack as required by ABI
381 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
382 hlt();
383 }
384
385 void MacroAssembler::warn(const char* msg) {
386 push(rbp);
387 movq(rbp, rsp);
388 andq(rsp, -16); // align stack as required by push_CPU_state and call
389 push_CPU_state(); // keeps alignment at 16 bytes
390
391 #ifdef _WIN64
392 // Windows always allocates space for its register args
393 subq(rsp, frame::arg_reg_save_area_bytes);
394 #endif
395 lea(c_rarg0, ExternalAddress((address) msg));
396 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
397
398 #ifdef _WIN64
399 // restore stack pointer
400 addq(rsp, frame::arg_reg_save_area_bytes);
401 #endif
402 pop_CPU_state();
403 mov(rsp, rbp);
404 pop(rbp);
405 }
406
407 void MacroAssembler::print_state() {
408 address rip = pc();
409 pusha(); // get regs on stack
410 push(rbp);
411 movq(rbp, rsp);
412 andq(rsp, -16); // align stack as required by push_CPU_state and call
413 push_CPU_state(); // keeps alignment at 16 bytes
414
415 lea(c_rarg0, InternalAddress(rip));
416 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
417 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
418
419 pop_CPU_state();
420 mov(rsp, rbp);
421 pop(rbp);
422 popa();
423 }
424
425 #ifndef PRODUCT
426 extern "C" void findpc(intptr_t x);
427 #endif
428
429 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
430 // In order to get locks to work, we need to fake a in_VM state
431 if (ShowMessageBoxOnError) {
432 JavaThread* thread = JavaThread::current();
433 JavaThreadState saved_state = thread->thread_state();
434 thread->set_thread_state(_thread_in_vm);
435 #ifndef PRODUCT
436 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
437 ttyLocker ttyl;
438 BytecodeCounter::print();
439 }
440 #endif
441 // To see where a verify_oop failed, get $ebx+40/X for this frame.
442 // XXX correct this offset for amd64
443 // This is the value of eip which points to where verify_oop will return.
444 if (os::message_box(msg, "Execution stopped, print registers?")) {
445 print_state64(pc, regs);
446 BREAKPOINT;
447 }
448 }
449 fatal("DEBUG MESSAGE: %s", msg);
450 }
451
452 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
453 ttyLocker ttyl;
454 DebuggingContext debugging{};
455 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
456 #ifndef PRODUCT
457 tty->cr();
458 findpc(pc);
459 tty->cr();
460 #endif
461 #define PRINT_REG(rax, value) \
462 { tty->print("%s = ", #rax); os::print_location(tty, value); }
463 PRINT_REG(rax, regs[15]);
464 PRINT_REG(rbx, regs[12]);
465 PRINT_REG(rcx, regs[14]);
466 PRINT_REG(rdx, regs[13]);
467 PRINT_REG(rdi, regs[8]);
468 PRINT_REG(rsi, regs[9]);
469 PRINT_REG(rbp, regs[10]);
470 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
471 PRINT_REG(rsp, (intptr_t)(®s[16]));
472 PRINT_REG(r8 , regs[7]);
473 PRINT_REG(r9 , regs[6]);
474 PRINT_REG(r10, regs[5]);
475 PRINT_REG(r11, regs[4]);
476 PRINT_REG(r12, regs[3]);
477 PRINT_REG(r13, regs[2]);
478 PRINT_REG(r14, regs[1]);
479 PRINT_REG(r15, regs[0]);
480 #undef PRINT_REG
481 // Print some words near the top of the stack.
482 int64_t* rsp = ®s[16];
483 int64_t* dump_sp = rsp;
484 for (int col1 = 0; col1 < 8; col1++) {
485 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
486 os::print_location(tty, *dump_sp++);
487 }
488 for (int row = 0; row < 25; row++) {
489 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
490 for (int col = 0; col < 4; col++) {
491 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
492 }
493 tty->cr();
494 }
495 // Print some instructions around pc:
496 Disassembler::decode((address)pc-64, (address)pc);
497 tty->print_cr("--------");
498 Disassembler::decode((address)pc, (address)pc+32);
499 }
500
501 // The java_calling_convention describes stack locations as ideal slots on
502 // a frame with no abi restrictions. Since we must observe abi restrictions
503 // (like the placement of the register window) the slots must be biased by
504 // the following value.
505 static int reg2offset_in(VMReg r) {
506 // Account for saved rbp and return address
507 // This should really be in_preserve_stack_slots
508 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
509 }
510
511 static int reg2offset_out(VMReg r) {
512 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
513 }
514
515 // A long move
516 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
517
518 // The calling conventions assures us that each VMregpair is either
519 // all really one physical register or adjacent stack slots.
520
521 if (src.is_single_phys_reg() ) {
522 if (dst.is_single_phys_reg()) {
523 if (dst.first() != src.first()) {
524 mov(dst.first()->as_Register(), src.first()->as_Register());
525 }
526 } else {
527 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
528 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
529 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
530 }
531 } else if (dst.is_single_phys_reg()) {
532 assert(src.is_single_reg(), "not a stack pair");
533 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
534 } else {
535 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
536 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
537 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
538 }
539 }
540
541 // A double move
542 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
543
544 // The calling conventions assures us that each VMregpair is either
545 // all really one physical register or adjacent stack slots.
546
547 if (src.is_single_phys_reg() ) {
548 if (dst.is_single_phys_reg()) {
549 // In theory these overlap but the ordering is such that this is likely a nop
550 if ( src.first() != dst.first()) {
551 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
552 }
553 } else {
554 assert(dst.is_single_reg(), "not a stack pair");
555 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
556 }
557 } else if (dst.is_single_phys_reg()) {
558 assert(src.is_single_reg(), "not a stack pair");
559 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
560 } else {
561 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
562 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
563 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
564 }
565 }
566
567
568 // A float arg may have to do float reg int reg conversion
569 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
570 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
571
572 // The calling conventions assures us that each VMregpair is either
573 // all really one physical register or adjacent stack slots.
574
575 if (src.first()->is_stack()) {
576 if (dst.first()->is_stack()) {
577 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
578 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
579 } else {
580 // stack to reg
581 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
582 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
583 }
584 } else if (dst.first()->is_stack()) {
585 // reg to stack
586 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
587 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
588 } else {
589 // reg to reg
590 // In theory these overlap but the ordering is such that this is likely a nop
591 if ( src.first() != dst.first()) {
592 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
593 }
594 }
595 }
596
597 // On 64 bit we will store integer like items to the stack as
598 // 64 bits items (x86_32/64 abi) even though java would only store
599 // 32bits for a parameter. On 32bit it will simply be 32 bits
600 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
601 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
602 if (src.first()->is_stack()) {
603 if (dst.first()->is_stack()) {
604 // stack to stack
605 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
606 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
607 } else {
608 // stack to reg
609 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
610 }
611 } else if (dst.first()->is_stack()) {
612 // reg to stack
613 // Do we really have to sign extend???
614 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
615 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
616 } else {
617 // Do we really have to sign extend???
618 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
619 if (dst.first() != src.first()) {
620 movq(dst.first()->as_Register(), src.first()->as_Register());
621 }
622 }
623 }
624
625 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
626 if (src.first()->is_stack()) {
627 if (dst.first()->is_stack()) {
628 // stack to stack
629 movq(rax, Address(rbp, reg2offset_in(src.first())));
630 movq(Address(rsp, reg2offset_out(dst.first())), rax);
631 } else {
632 // stack to reg
633 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
634 }
635 } else if (dst.first()->is_stack()) {
636 // reg to stack
637 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
638 } else {
639 if (dst.first() != src.first()) {
640 movq(dst.first()->as_Register(), src.first()->as_Register());
641 }
642 }
643 }
644
645 // An oop arg. Must pass a handle not the oop itself
646 void MacroAssembler::object_move(OopMap* map,
647 int oop_handle_offset,
648 int framesize_in_slots,
649 VMRegPair src,
650 VMRegPair dst,
651 bool is_receiver,
652 int* receiver_offset) {
653
654 // must pass a handle. First figure out the location we use as a handle
655
656 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
657
658 // See if oop is null if it is we need no handle
659
660 if (src.first()->is_stack()) {
661
662 // Oop is already on the stack as an argument
663 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
664 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
665 if (is_receiver) {
666 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
667 }
668
669 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
670 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
671 // conditionally move a null
672 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
673 } else {
674
675 // Oop is in a register we must store it to the space we reserve
676 // on the stack for oop_handles and pass a handle if oop is non-null
677
678 const Register rOop = src.first()->as_Register();
679 int oop_slot;
680 if (rOop == j_rarg0)
681 oop_slot = 0;
682 else if (rOop == j_rarg1)
683 oop_slot = 1;
684 else if (rOop == j_rarg2)
685 oop_slot = 2;
686 else if (rOop == j_rarg3)
687 oop_slot = 3;
688 else if (rOop == j_rarg4)
689 oop_slot = 4;
690 else {
691 assert(rOop == j_rarg5, "wrong register");
692 oop_slot = 5;
693 }
694
695 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
696 int offset = oop_slot*VMRegImpl::stack_slot_size;
697
698 map->set_oop(VMRegImpl::stack2reg(oop_slot));
699 // Store oop in handle area, may be null
700 movptr(Address(rsp, offset), rOop);
701 if (is_receiver) {
702 *receiver_offset = offset;
703 }
704
705 cmpptr(rOop, NULL_WORD);
706 lea(rHandle, Address(rsp, offset));
707 // conditionally move a null from the handle area where it was just stored
708 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
709 }
710
711 // If arg is on the stack then place it otherwise it is already in correct reg.
712 if (dst.first()->is_stack()) {
713 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
714 }
715 }
716
717 void MacroAssembler::addptr(Register dst, int32_t imm32) {
718 addq(dst, imm32);
719 }
720
721 void MacroAssembler::addptr(Register dst, Register src) {
722 addq(dst, src);
723 }
724
725 void MacroAssembler::addptr(Address dst, Register src) {
726 addq(dst, src);
727 }
728
729 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
730 assert(rscratch != noreg || always_reachable(src), "missing");
731
732 if (reachable(src)) {
733 Assembler::addsd(dst, as_Address(src));
734 } else {
735 lea(rscratch, src);
736 Assembler::addsd(dst, Address(rscratch, 0));
737 }
738 }
739
740 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
741 assert(rscratch != noreg || always_reachable(src), "missing");
742
743 if (reachable(src)) {
744 addss(dst, as_Address(src));
745 } else {
746 lea(rscratch, src);
747 addss(dst, Address(rscratch, 0));
748 }
749 }
750
751 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
752 assert(rscratch != noreg || always_reachable(src), "missing");
753
754 if (reachable(src)) {
755 Assembler::addpd(dst, as_Address(src));
756 } else {
757 lea(rscratch, src);
758 Assembler::addpd(dst, Address(rscratch, 0));
759 }
760 }
761
762 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
763 // Stub code is generated once and never copied.
764 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
765 void MacroAssembler::align64() {
766 align(64, (uint)(uintptr_t)pc());
767 }
768
769 void MacroAssembler::align32() {
770 align(32, (uint)(uintptr_t)pc());
771 }
772
773 void MacroAssembler::align(uint modulus) {
774 // 8273459: Ensure alignment is possible with current segment alignment
775 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
776 align(modulus, offset());
777 }
778
779 void MacroAssembler::align(uint modulus, uint target) {
780 if (target % modulus != 0) {
781 nop(modulus - (target % modulus));
782 }
783 }
784
785 void MacroAssembler::push_f(XMMRegister r) {
786 subptr(rsp, wordSize);
787 movflt(Address(rsp, 0), r);
788 }
789
790 void MacroAssembler::pop_f(XMMRegister r) {
791 movflt(r, Address(rsp, 0));
792 addptr(rsp, wordSize);
793 }
794
795 void MacroAssembler::push_d(XMMRegister r) {
796 subptr(rsp, 2 * wordSize);
797 movdbl(Address(rsp, 0), r);
798 }
799
800 void MacroAssembler::pop_d(XMMRegister r) {
801 movdbl(r, Address(rsp, 0));
802 addptr(rsp, 2 * Interpreter::stackElementSize);
803 }
804
805 void MacroAssembler::push_ppx(Register src) {
806 if (VM_Version::supports_apx_f()) {
807 pushp(src);
808 } else {
809 Assembler::push(src);
810 }
811 }
812
813 void MacroAssembler::pop_ppx(Register dst) {
814 if (VM_Version::supports_apx_f()) {
815 popp(dst);
816 } else {
817 Assembler::pop(dst);
818 }
819 }
820
821 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
822 // Used in sign-masking with aligned address.
823 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
824 assert(rscratch != noreg || always_reachable(src), "missing");
825
826 if (UseAVX > 2 &&
827 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
828 (dst->encoding() >= 16)) {
829 vpand(dst, dst, src, AVX_512bit, rscratch);
830 } else if (reachable(src)) {
831 Assembler::andpd(dst, as_Address(src));
832 } else {
833 lea(rscratch, src);
834 Assembler::andpd(dst, Address(rscratch, 0));
835 }
836 }
837
838 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
839 // Used in sign-masking with aligned address.
840 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
841 assert(rscratch != noreg || always_reachable(src), "missing");
842
843 if (reachable(src)) {
844 Assembler::andps(dst, as_Address(src));
845 } else {
846 lea(rscratch, src);
847 Assembler::andps(dst, Address(rscratch, 0));
848 }
849 }
850
851 void MacroAssembler::andptr(Register dst, int32_t imm32) {
852 andq(dst, imm32);
853 }
854
855 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
856 assert(rscratch != noreg || always_reachable(src), "missing");
857
858 if (reachable(src)) {
859 andq(dst, as_Address(src));
860 } else {
861 lea(rscratch, src);
862 andq(dst, Address(rscratch, 0));
863 }
864 }
865
866 void MacroAssembler::atomic_incl(Address counter_addr) {
867 lock();
868 incrementl(counter_addr);
869 }
870
871 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
872 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
873
874 if (reachable(counter_addr)) {
875 atomic_incl(as_Address(counter_addr));
876 } else {
877 lea(rscratch, counter_addr);
878 atomic_incl(Address(rscratch, 0));
879 }
880 }
881
882 void MacroAssembler::atomic_incq(Address counter_addr) {
883 lock();
884 incrementq(counter_addr);
885 }
886
887 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
888 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
889
890 if (reachable(counter_addr)) {
891 atomic_incq(as_Address(counter_addr));
892 } else {
893 lea(rscratch, counter_addr);
894 atomic_incq(Address(rscratch, 0));
895 }
896 }
897
898 // Writes to stack successive pages until offset reached to check for
899 // stack overflow + shadow pages. This clobbers tmp.
900 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
901 movptr(tmp, rsp);
902 // Bang stack for total size given plus shadow page size.
903 // Bang one page at a time because large size can bang beyond yellow and
904 // red zones.
905 Label loop;
906 bind(loop);
907 movl(Address(tmp, (-(int)os::vm_page_size())), size );
908 subptr(tmp, (int)os::vm_page_size());
909 subl(size, (int)os::vm_page_size());
910 jcc(Assembler::greater, loop);
911
912 // Bang down shadow pages too.
913 // At this point, (tmp-0) is the last address touched, so don't
914 // touch it again. (It was touched as (tmp-pagesize) but then tmp
915 // was post-decremented.) Skip this address by starting at i=1, and
916 // touch a few more pages below. N.B. It is important to touch all
917 // the way down including all pages in the shadow zone.
918 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
919 // this could be any sized move but this is can be a debugging crumb
920 // so the bigger the better.
921 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
922 }
923 }
924
925 void MacroAssembler::reserved_stack_check() {
926 // testing if reserved zone needs to be enabled
927 Label no_reserved_zone_enabling;
928
929 cmpptr(rsp, Address(r15_thread, JavaThread::reserved_stack_activation_offset()));
930 jcc(Assembler::below, no_reserved_zone_enabling);
931
932 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), r15_thread);
933 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
934 should_not_reach_here();
935
936 bind(no_reserved_zone_enabling);
937 }
938
939 void MacroAssembler::c2bool(Register x) {
940 // implements x == 0 ? 0 : 1
941 // note: must only look at least-significant byte of x
942 // since C-style booleans are stored in one byte
943 // only! (was bug)
944 andl(x, 0xFF);
945 setb(Assembler::notZero, x);
946 }
947
948 // Wouldn't need if AddressLiteral version had new name
949 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
950 Assembler::call(L, rtype);
951 }
952
953 void MacroAssembler::call(Register entry) {
954 Assembler::call(entry);
955 }
956
957 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
958 assert(rscratch != noreg || always_reachable(entry), "missing");
959
960 if (reachable(entry)) {
961 Assembler::call_literal(entry.target(), entry.rspec());
962 } else {
963 lea(rscratch, entry);
964 Assembler::call(rscratch);
965 }
966 }
967
968 void MacroAssembler::ic_call(address entry, jint method_index) {
969 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
970 // Needs full 64-bit immediate for later patching.
971 mov64(rax, (int64_t)Universe::non_oop_word());
972 call(AddressLiteral(entry, rh));
973 }
974
975 int MacroAssembler::ic_check_size() {
976 return UseCompactObjectHeaders ? 17 : 14;
977 }
978
979 int MacroAssembler::ic_check(int end_alignment) {
980 Register receiver = j_rarg0;
981 Register data = rax;
982 Register temp = rscratch1;
983
984 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
985 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
986 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
987 // before the inline cache check here, and not after
988 align(end_alignment, offset() + ic_check_size());
989
990 int uep_offset = offset();
991
992 if (UseCompactObjectHeaders) {
993 load_narrow_klass_compact(temp, receiver);
994 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
995 } else if (UseCompressedClassPointers) {
996 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
997 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
998 } else {
999 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1000 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1001 }
1002
1003 // if inline cache check fails, then jump to runtime routine
1004 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1005 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1006
1007 return uep_offset;
1008 }
1009
1010 void MacroAssembler::emit_static_call_stub() {
1011 // Static stub relocation also tags the Method* in the code-stream.
1012 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1013 // This is recognized as unresolved by relocs/nativeinst/ic code.
1014 jump(RuntimeAddress(pc()));
1015 }
1016
1017 // Implementation of call_VM versions
1018
1019 void MacroAssembler::call_VM(Register oop_result,
1020 address entry_point,
1021 bool check_exceptions) {
1022 Label C, E;
1023 call(C, relocInfo::none);
1024 jmp(E);
1025
1026 bind(C);
1027 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1028 ret(0);
1029
1030 bind(E);
1031 }
1032
1033 void MacroAssembler::call_VM(Register oop_result,
1034 address entry_point,
1035 Register arg_1,
1036 bool check_exceptions) {
1037 Label C, E;
1038 call(C, relocInfo::none);
1039 jmp(E);
1040
1041 bind(C);
1042 pass_arg1(this, arg_1);
1043 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1044 ret(0);
1045
1046 bind(E);
1047 }
1048
1049 void MacroAssembler::call_VM(Register oop_result,
1050 address entry_point,
1051 Register arg_1,
1052 Register arg_2,
1053 bool check_exceptions) {
1054 Label C, E;
1055 call(C, relocInfo::none);
1056 jmp(E);
1057
1058 bind(C);
1059
1060 assert_different_registers(arg_1, c_rarg2);
1061
1062 pass_arg2(this, arg_2);
1063 pass_arg1(this, arg_1);
1064 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1065 ret(0);
1066
1067 bind(E);
1068 }
1069
1070 void MacroAssembler::call_VM(Register oop_result,
1071 address entry_point,
1072 Register arg_1,
1073 Register arg_2,
1074 Register arg_3,
1075 bool check_exceptions) {
1076 Label C, E;
1077 call(C, relocInfo::none);
1078 jmp(E);
1079
1080 bind(C);
1081
1082 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1083 assert_different_registers(arg_2, c_rarg3);
1084 pass_arg3(this, arg_3);
1085 pass_arg2(this, arg_2);
1086 pass_arg1(this, arg_1);
1087 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1088 ret(0);
1089
1090 bind(E);
1091 }
1092
1093 void MacroAssembler::call_VM(Register oop_result,
1094 Register last_java_sp,
1095 address entry_point,
1096 int number_of_arguments,
1097 bool check_exceptions) {
1098 call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1099 }
1100
1101 void MacroAssembler::call_VM(Register oop_result,
1102 Register last_java_sp,
1103 address entry_point,
1104 Register arg_1,
1105 bool check_exceptions) {
1106 pass_arg1(this, arg_1);
1107 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1108 }
1109
1110 void MacroAssembler::call_VM(Register oop_result,
1111 Register last_java_sp,
1112 address entry_point,
1113 Register arg_1,
1114 Register arg_2,
1115 bool check_exceptions) {
1116
1117 assert_different_registers(arg_1, c_rarg2);
1118 pass_arg2(this, arg_2);
1119 pass_arg1(this, arg_1);
1120 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1121 }
1122
1123 void MacroAssembler::call_VM(Register oop_result,
1124 Register last_java_sp,
1125 address entry_point,
1126 Register arg_1,
1127 Register arg_2,
1128 Register arg_3,
1129 bool check_exceptions) {
1130 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1131 assert_different_registers(arg_2, c_rarg3);
1132 pass_arg3(this, arg_3);
1133 pass_arg2(this, arg_2);
1134 pass_arg1(this, arg_1);
1135 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1136 }
1137
1138 void MacroAssembler::super_call_VM(Register oop_result,
1139 Register last_java_sp,
1140 address entry_point,
1141 int number_of_arguments,
1142 bool check_exceptions) {
1143 MacroAssembler::call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1144 }
1145
1146 void MacroAssembler::super_call_VM(Register oop_result,
1147 Register last_java_sp,
1148 address entry_point,
1149 Register arg_1,
1150 bool check_exceptions) {
1151 pass_arg1(this, arg_1);
1152 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1153 }
1154
1155 void MacroAssembler::super_call_VM(Register oop_result,
1156 Register last_java_sp,
1157 address entry_point,
1158 Register arg_1,
1159 Register arg_2,
1160 bool check_exceptions) {
1161
1162 assert_different_registers(arg_1, c_rarg2);
1163 pass_arg2(this, arg_2);
1164 pass_arg1(this, arg_1);
1165 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1166 }
1167
1168 void MacroAssembler::super_call_VM(Register oop_result,
1169 Register last_java_sp,
1170 address entry_point,
1171 Register arg_1,
1172 Register arg_2,
1173 Register arg_3,
1174 bool check_exceptions) {
1175 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1176 assert_different_registers(arg_2, c_rarg3);
1177 pass_arg3(this, arg_3);
1178 pass_arg2(this, arg_2);
1179 pass_arg1(this, arg_1);
1180 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1181 }
1182
1183 void MacroAssembler::call_VM_base(Register oop_result,
1184 Register last_java_sp,
1185 address entry_point,
1186 int number_of_arguments,
1187 bool check_exceptions) {
1188 Register java_thread = r15_thread;
1189
1190 // determine last_java_sp register
1191 if (!last_java_sp->is_valid()) {
1192 last_java_sp = rsp;
1193 }
1194 // debugging support
1195 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1196 #ifdef ASSERT
1197 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1198 // r12 is the heapbase.
1199 if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
1200 #endif // ASSERT
1201
1202 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1203 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1204
1205 // push java thread (becomes first argument of C function)
1206
1207 mov(c_rarg0, r15_thread);
1208
1209 // set last Java frame before call
1210 assert(last_java_sp != rbp, "can't use ebp/rbp");
1211
1212 // Only interpreter should have to set fp
1213 set_last_Java_frame(last_java_sp, rbp, nullptr, rscratch1);
1214
1215 // do the call, remove parameters
1216 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1217
1218 #ifdef ASSERT
1219 // Check that thread register is not clobbered.
1220 guarantee(java_thread != rax, "change this code");
1221 push(rax);
1222 { Label L;
1223 get_thread_slow(rax);
1224 cmpptr(java_thread, rax);
1225 jcc(Assembler::equal, L);
1226 STOP("MacroAssembler::call_VM_base: java_thread not callee saved?");
1227 bind(L);
1228 }
1229 pop(rax);
1230 #endif
1231
1232 // reset last Java frame
1233 // Only interpreter should have to clear fp
1234 reset_last_Java_frame(true);
1235
1236 // C++ interp handles this in the interpreter
1237 check_and_handle_popframe();
1238 check_and_handle_earlyret();
1239
1240 if (check_exceptions) {
1241 // check for pending exceptions (java_thread is set upon return)
1242 cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
1243 // This used to conditionally jump to forward_exception however it is
1244 // possible if we relocate that the branch will not reach. So we must jump
1245 // around so we can always reach
1246
1247 Label ok;
1248 jcc(Assembler::equal, ok);
1249 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1250 bind(ok);
1251 }
1252
1253 // get oop result if there is one and reset the value in the thread
1254 if (oop_result->is_valid()) {
1255 get_vm_result_oop(oop_result);
1256 }
1257 }
1258
1259 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1260 // Calculate the value for last_Java_sp somewhat subtle.
1261 // call_VM does an intermediate call which places a return address on
1262 // the stack just under the stack pointer as the user finished with it.
1263 // This allows use to retrieve last_Java_pc from last_Java_sp[-1].
1264
1265 // We've pushed one address, correct last_Java_sp
1266 lea(rax, Address(rsp, wordSize));
1267
1268 call_VM_base(oop_result, rax, entry_point, number_of_arguments, check_exceptions);
1269 }
1270
1271 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1272 void MacroAssembler::call_VM_leaf0(address entry_point) {
1273 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1274 }
1275
1276 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1277 call_VM_leaf_base(entry_point, number_of_arguments);
1278 }
1279
1280 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1281 pass_arg0(this, arg_0);
1282 call_VM_leaf(entry_point, 1);
1283 }
1284
1285 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1286
1287 assert_different_registers(arg_0, c_rarg1);
1288 pass_arg1(this, arg_1);
1289 pass_arg0(this, arg_0);
1290 call_VM_leaf(entry_point, 2);
1291 }
1292
1293 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1294 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1295 assert_different_registers(arg_1, c_rarg2);
1296 pass_arg2(this, arg_2);
1297 pass_arg1(this, arg_1);
1298 pass_arg0(this, arg_0);
1299 call_VM_leaf(entry_point, 3);
1300 }
1301
1302 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1303 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1304 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1305 assert_different_registers(arg_2, c_rarg3);
1306 pass_arg3(this, arg_3);
1307 pass_arg2(this, arg_2);
1308 pass_arg1(this, arg_1);
1309 pass_arg0(this, arg_0);
1310 call_VM_leaf(entry_point, 3);
1311 }
1312
1313 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1314 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1315 }
1316
1317 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1318 pass_arg0(this, arg_0);
1319 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1320 }
1321
1322 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1323 assert_different_registers(arg_0, c_rarg1);
1324 pass_arg1(this, arg_1);
1325 pass_arg0(this, arg_0);
1326 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1327 }
1328
1329 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1330 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1331 assert_different_registers(arg_1, c_rarg2);
1332 pass_arg2(this, arg_2);
1333 pass_arg1(this, arg_1);
1334 pass_arg0(this, arg_0);
1335 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1336 }
1337
1338 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1339 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1340 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1341 assert_different_registers(arg_2, c_rarg3);
1342 pass_arg3(this, arg_3);
1343 pass_arg2(this, arg_2);
1344 pass_arg1(this, arg_1);
1345 pass_arg0(this, arg_0);
1346 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1347 }
1348
1349 void MacroAssembler::get_vm_result_oop(Register oop_result) {
1350 movptr(oop_result, Address(r15_thread, JavaThread::vm_result_oop_offset()));
1351 movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
1352 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1353 }
1354
1355 void MacroAssembler::get_vm_result_metadata(Register metadata_result) {
1356 movptr(metadata_result, Address(r15_thread, JavaThread::vm_result_metadata_offset()));
1357 movptr(Address(r15_thread, JavaThread::vm_result_metadata_offset()), NULL_WORD);
1358 }
1359
1360 void MacroAssembler::check_and_handle_earlyret() {
1361 }
1362
1363 void MacroAssembler::check_and_handle_popframe() {
1364 }
1365
1366 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1367 assert(rscratch != noreg || always_reachable(src1), "missing");
1368
1369 if (reachable(src1)) {
1370 cmpl(as_Address(src1), imm);
1371 } else {
1372 lea(rscratch, src1);
1373 cmpl(Address(rscratch, 0), imm);
1374 }
1375 }
1376
1377 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1378 assert(!src2.is_lval(), "use cmpptr");
1379 assert(rscratch != noreg || always_reachable(src2), "missing");
1380
1381 if (reachable(src2)) {
1382 cmpl(src1, as_Address(src2));
1383 } else {
1384 lea(rscratch, src2);
1385 cmpl(src1, Address(rscratch, 0));
1386 }
1387 }
1388
1389 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1390 Assembler::cmpl(src1, imm);
1391 }
1392
1393 void MacroAssembler::cmp32(Register src1, Address src2) {
1394 Assembler::cmpl(src1, src2);
1395 }
1396
1397 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1398 ucomisd(opr1, opr2);
1399
1400 Label L;
1401 if (unordered_is_less) {
1402 movl(dst, -1);
1403 jcc(Assembler::parity, L);
1404 jcc(Assembler::below , L);
1405 movl(dst, 0);
1406 jcc(Assembler::equal , L);
1407 increment(dst);
1408 } else { // unordered is greater
1409 movl(dst, 1);
1410 jcc(Assembler::parity, L);
1411 jcc(Assembler::above , L);
1412 movl(dst, 0);
1413 jcc(Assembler::equal , L);
1414 decrementl(dst);
1415 }
1416 bind(L);
1417 }
1418
1419 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1420 ucomiss(opr1, opr2);
1421
1422 Label L;
1423 if (unordered_is_less) {
1424 movl(dst, -1);
1425 jcc(Assembler::parity, L);
1426 jcc(Assembler::below , L);
1427 movl(dst, 0);
1428 jcc(Assembler::equal , L);
1429 increment(dst);
1430 } else { // unordered is greater
1431 movl(dst, 1);
1432 jcc(Assembler::parity, L);
1433 jcc(Assembler::above , L);
1434 movl(dst, 0);
1435 jcc(Assembler::equal , L);
1436 decrementl(dst);
1437 }
1438 bind(L);
1439 }
1440
1441
1442 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1443 assert(rscratch != noreg || always_reachable(src1), "missing");
1444
1445 if (reachable(src1)) {
1446 cmpb(as_Address(src1), imm);
1447 } else {
1448 lea(rscratch, src1);
1449 cmpb(Address(rscratch, 0), imm);
1450 }
1451 }
1452
1453 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1454 assert(rscratch != noreg || always_reachable(src2), "missing");
1455
1456 if (src2.is_lval()) {
1457 movptr(rscratch, src2);
1458 Assembler::cmpq(src1, rscratch);
1459 } else if (reachable(src2)) {
1460 cmpq(src1, as_Address(src2));
1461 } else {
1462 lea(rscratch, src2);
1463 Assembler::cmpq(src1, Address(rscratch, 0));
1464 }
1465 }
1466
1467 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1468 assert(src2.is_lval(), "not a mem-mem compare");
1469 // moves src2's literal address
1470 movptr(rscratch, src2);
1471 Assembler::cmpq(src1, rscratch);
1472 }
1473
1474 void MacroAssembler::cmpoop(Register src1, Register src2) {
1475 cmpptr(src1, src2);
1476 }
1477
1478 void MacroAssembler::cmpoop(Register src1, Address src2) {
1479 cmpptr(src1, src2);
1480 }
1481
1482 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1483 movoop(rscratch, src2);
1484 cmpptr(src1, rscratch);
1485 }
1486
1487 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1488 assert(rscratch != noreg || always_reachable(adr), "missing");
1489
1490 if (reachable(adr)) {
1491 lock();
1492 cmpxchgptr(reg, as_Address(adr));
1493 } else {
1494 lea(rscratch, adr);
1495 lock();
1496 cmpxchgptr(reg, Address(rscratch, 0));
1497 }
1498 }
1499
1500 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1501 cmpxchgq(reg, adr);
1502 }
1503
1504 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1505 assert(rscratch != noreg || always_reachable(src), "missing");
1506
1507 if (reachable(src)) {
1508 Assembler::comisd(dst, as_Address(src));
1509 } else {
1510 lea(rscratch, src);
1511 Assembler::comisd(dst, Address(rscratch, 0));
1512 }
1513 }
1514
1515 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1516 assert(rscratch != noreg || always_reachable(src), "missing");
1517
1518 if (reachable(src)) {
1519 Assembler::comiss(dst, as_Address(src));
1520 } else {
1521 lea(rscratch, src);
1522 Assembler::comiss(dst, Address(rscratch, 0));
1523 }
1524 }
1525
1526
1527 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1528 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1529
1530 Condition negated_cond = negate_condition(cond);
1531 Label L;
1532 jcc(negated_cond, L);
1533 pushf(); // Preserve flags
1534 atomic_incl(counter_addr, rscratch);
1535 popf();
1536 bind(L);
1537 }
1538
1539 int MacroAssembler::corrected_idivl(Register reg) {
1540 // Full implementation of Java idiv and irem; checks for
1541 // special case as described in JVM spec., p.243 & p.271.
1542 // The function returns the (pc) offset of the idivl
1543 // instruction - may be needed for implicit exceptions.
1544 //
1545 // normal case special case
1546 //
1547 // input : rax,: dividend min_int
1548 // reg: divisor (may not be rax,/rdx) -1
1549 //
1550 // output: rax,: quotient (= rax, idiv reg) min_int
1551 // rdx: remainder (= rax, irem reg) 0
1552 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1553 const int min_int = 0x80000000;
1554 Label normal_case, special_case;
1555
1556 // check for special case
1557 cmpl(rax, min_int);
1558 jcc(Assembler::notEqual, normal_case);
1559 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1560 cmpl(reg, -1);
1561 jcc(Assembler::equal, special_case);
1562
1563 // handle normal case
1564 bind(normal_case);
1565 cdql();
1566 int idivl_offset = offset();
1567 idivl(reg);
1568
1569 // normal and special case exit
1570 bind(special_case);
1571
1572 return idivl_offset;
1573 }
1574
1575
1576
1577 void MacroAssembler::decrementl(Register reg, int value) {
1578 if (value == min_jint) {subl(reg, value) ; return; }
1579 if (value < 0) { incrementl(reg, -value); return; }
1580 if (value == 0) { ; return; }
1581 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1582 /* else */ { subl(reg, value) ; return; }
1583 }
1584
1585 void MacroAssembler::decrementl(Address dst, int value) {
1586 if (value == min_jint) {subl(dst, value) ; return; }
1587 if (value < 0) { incrementl(dst, -value); return; }
1588 if (value == 0) { ; return; }
1589 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1590 /* else */ { subl(dst, value) ; return; }
1591 }
1592
1593 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1594 assert(shift_value > 0, "illegal shift value");
1595 Label _is_positive;
1596 testl (reg, reg);
1597 jcc (Assembler::positive, _is_positive);
1598 int offset = (1 << shift_value) - 1 ;
1599
1600 if (offset == 1) {
1601 incrementl(reg);
1602 } else {
1603 addl(reg, offset);
1604 }
1605
1606 bind (_is_positive);
1607 sarl(reg, shift_value);
1608 }
1609
1610 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1611 assert(rscratch != noreg || always_reachable(src), "missing");
1612
1613 if (reachable(src)) {
1614 Assembler::divsd(dst, as_Address(src));
1615 } else {
1616 lea(rscratch, src);
1617 Assembler::divsd(dst, Address(rscratch, 0));
1618 }
1619 }
1620
1621 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1622 assert(rscratch != noreg || always_reachable(src), "missing");
1623
1624 if (reachable(src)) {
1625 Assembler::divss(dst, as_Address(src));
1626 } else {
1627 lea(rscratch, src);
1628 Assembler::divss(dst, Address(rscratch, 0));
1629 }
1630 }
1631
1632 void MacroAssembler::enter() {
1633 push(rbp);
1634 mov(rbp, rsp);
1635 }
1636
1637 void MacroAssembler::post_call_nop() {
1638 if (!Continuations::enabled()) {
1639 return;
1640 }
1641 InstructionMark im(this);
1642 relocate(post_call_nop_Relocation::spec());
1643 InlineSkippedInstructionsCounter skipCounter(this);
1644 emit_int8((uint8_t)0x0f);
1645 emit_int8((uint8_t)0x1f);
1646 emit_int8((uint8_t)0x84);
1647 emit_int8((uint8_t)0x00);
1648 emit_int32(0x00);
1649 }
1650
1651 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1652 assert(rscratch != noreg || always_reachable(src), "missing");
1653 if (reachable(src)) {
1654 Assembler::mulpd(dst, as_Address(src));
1655 } else {
1656 lea(rscratch, src);
1657 Assembler::mulpd(dst, Address(rscratch, 0));
1658 }
1659 }
1660
1661 // dst = c = a * b + c
1662 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1663 Assembler::vfmadd231sd(c, a, b);
1664 if (dst != c) {
1665 movdbl(dst, c);
1666 }
1667 }
1668
1669 // dst = c = a * b + c
1670 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1671 Assembler::vfmadd231ss(c, a, b);
1672 if (dst != c) {
1673 movflt(dst, c);
1674 }
1675 }
1676
1677 // dst = c = a * b + c
1678 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1679 Assembler::vfmadd231pd(c, a, b, vector_len);
1680 if (dst != c) {
1681 vmovdqu(dst, c);
1682 }
1683 }
1684
1685 // dst = c = a * b + c
1686 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1687 Assembler::vfmadd231ps(c, a, b, vector_len);
1688 if (dst != c) {
1689 vmovdqu(dst, c);
1690 }
1691 }
1692
1693 // dst = c = a * b + c
1694 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1695 Assembler::vfmadd231pd(c, a, b, vector_len);
1696 if (dst != c) {
1697 vmovdqu(dst, c);
1698 }
1699 }
1700
1701 // dst = c = a * b + c
1702 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1703 Assembler::vfmadd231ps(c, a, b, vector_len);
1704 if (dst != c) {
1705 vmovdqu(dst, c);
1706 }
1707 }
1708
1709 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
1710 assert(rscratch != noreg || always_reachable(dst), "missing");
1711
1712 if (reachable(dst)) {
1713 incrementl(as_Address(dst));
1714 } else {
1715 lea(rscratch, dst);
1716 incrementl(Address(rscratch, 0));
1717 }
1718 }
1719
1720 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
1721 incrementl(as_Address(dst, rscratch));
1722 }
1723
1724 void MacroAssembler::incrementl(Register reg, int value) {
1725 if (value == min_jint) {addl(reg, value) ; return; }
1726 if (value < 0) { decrementl(reg, -value); return; }
1727 if (value == 0) { ; return; }
1728 if (value == 1 && UseIncDec) { incl(reg) ; return; }
1729 /* else */ { addl(reg, value) ; return; }
1730 }
1731
1732 void MacroAssembler::incrementl(Address dst, int value) {
1733 if (value == min_jint) {addl(dst, value) ; return; }
1734 if (value < 0) { decrementl(dst, -value); return; }
1735 if (value == 0) { ; return; }
1736 if (value == 1 && UseIncDec) { incl(dst) ; return; }
1737 /* else */ { addl(dst, value) ; return; }
1738 }
1739
1740 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
1741 assert(rscratch != noreg || always_reachable(dst), "missing");
1742 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
1743 if (reachable(dst)) {
1744 jmp_literal(dst.target(), dst.rspec());
1745 } else {
1746 lea(rscratch, dst);
1747 jmp(rscratch);
1748 }
1749 }
1750
1751 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
1752 assert(rscratch != noreg || always_reachable(dst), "missing");
1753 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
1754 if (reachable(dst)) {
1755 InstructionMark im(this);
1756 relocate(dst.reloc());
1757 const int short_size = 2;
1758 const int long_size = 6;
1759 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
1760 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
1761 // 0111 tttn #8-bit disp
1762 emit_int8(0x70 | cc);
1763 emit_int8((offs - short_size) & 0xFF);
1764 } else {
1765 // 0000 1111 1000 tttn #32-bit disp
1766 emit_int8(0x0F);
1767 emit_int8((unsigned char)(0x80 | cc));
1768 emit_int32(offs - long_size);
1769 }
1770 } else {
1771 #ifdef ASSERT
1772 warning("reversing conditional branch");
1773 #endif /* ASSERT */
1774 Label skip;
1775 jccb(reverse[cc], skip);
1776 lea(rscratch, dst);
1777 Assembler::jmp(rscratch);
1778 bind(skip);
1779 }
1780 }
1781
1782 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
1783 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
1784 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
1785
1786 stmxcsr(mxcsr_save);
1787 movl(tmp, mxcsr_save);
1788 if (EnableX86ECoreOpts) {
1789 // The mxcsr_std has status bits set for performance on ECore
1790 orl(tmp, 0x003f);
1791 } else {
1792 // Mask out status bits (only check control and mask bits)
1793 andl(tmp, 0xFFC0);
1794 }
1795 cmp32(tmp, mxcsr_std, rscratch);
1796 }
1797
1798 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
1799 assert(rscratch != noreg || always_reachable(src), "missing");
1800
1801 if (reachable(src)) {
1802 Assembler::ldmxcsr(as_Address(src));
1803 } else {
1804 lea(rscratch, src);
1805 Assembler::ldmxcsr(Address(rscratch, 0));
1806 }
1807 }
1808
1809 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1810 int off = offset();
1811 movsbl(dst, src); // movsxb
1812 return off;
1813 }
1814
1815 // Note: load_signed_short used to be called load_signed_word.
1816 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
1817 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
1818 // The term "word" in HotSpot means a 32- or 64-bit machine word.
1819 int MacroAssembler::load_signed_short(Register dst, Address src) {
1820 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
1821 // version but this is what 64bit has always done. This seems to imply
1822 // that users are only using 32bits worth.
1823 int off = offset();
1824 movswl(dst, src); // movsxw
1825 return off;
1826 }
1827
1828 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1829 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1830 // and "3.9 Partial Register Penalties", p. 22).
1831 int off = offset();
1832 movzbl(dst, src); // movzxb
1833 return off;
1834 }
1835
1836 // Note: load_unsigned_short used to be called load_unsigned_word.
1837 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1838 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1839 // and "3.9 Partial Register Penalties", p. 22).
1840 int off = offset();
1841 movzwl(dst, src); // movzxw
1842 return off;
1843 }
1844
1845 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1846 switch (size_in_bytes) {
1847 case 8: movq(dst, src); break;
1848 case 4: movl(dst, src); break;
1849 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1850 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1851 default: ShouldNotReachHere();
1852 }
1853 }
1854
1855 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1856 switch (size_in_bytes) {
1857 case 8: movq(dst, src); break;
1858 case 4: movl(dst, src); break;
1859 case 2: movw(dst, src); break;
1860 case 1: movb(dst, src); break;
1861 default: ShouldNotReachHere();
1862 }
1863 }
1864
1865 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
1866 assert(rscratch != noreg || always_reachable(dst), "missing");
1867
1868 if (reachable(dst)) {
1869 movl(as_Address(dst), src);
1870 } else {
1871 lea(rscratch, dst);
1872 movl(Address(rscratch, 0), src);
1873 }
1874 }
1875
1876 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
1877 if (reachable(src)) {
1878 movl(dst, as_Address(src));
1879 } else {
1880 lea(dst, src);
1881 movl(dst, Address(dst, 0));
1882 }
1883 }
1884
1885 // C++ bool manipulation
1886
1887 void MacroAssembler::movbool(Register dst, Address src) {
1888 if(sizeof(bool) == 1)
1889 movb(dst, src);
1890 else if(sizeof(bool) == 2)
1891 movw(dst, src);
1892 else if(sizeof(bool) == 4)
1893 movl(dst, src);
1894 else
1895 // unsupported
1896 ShouldNotReachHere();
1897 }
1898
1899 void MacroAssembler::movbool(Address dst, bool boolconst) {
1900 if(sizeof(bool) == 1)
1901 movb(dst, (int) boolconst);
1902 else if(sizeof(bool) == 2)
1903 movw(dst, (int) boolconst);
1904 else if(sizeof(bool) == 4)
1905 movl(dst, (int) boolconst);
1906 else
1907 // unsupported
1908 ShouldNotReachHere();
1909 }
1910
1911 void MacroAssembler::movbool(Address dst, Register src) {
1912 if(sizeof(bool) == 1)
1913 movb(dst, src);
1914 else if(sizeof(bool) == 2)
1915 movw(dst, src);
1916 else if(sizeof(bool) == 4)
1917 movl(dst, src);
1918 else
1919 // unsupported
1920 ShouldNotReachHere();
1921 }
1922
1923 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1924 assert(rscratch != noreg || always_reachable(src), "missing");
1925
1926 if (reachable(src)) {
1927 movdl(dst, as_Address(src));
1928 } else {
1929 lea(rscratch, src);
1930 movdl(dst, Address(rscratch, 0));
1931 }
1932 }
1933
1934 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
1935 assert(rscratch != noreg || always_reachable(src), "missing");
1936
1937 if (reachable(src)) {
1938 movq(dst, as_Address(src));
1939 } else {
1940 lea(rscratch, src);
1941 movq(dst, Address(rscratch, 0));
1942 }
1943 }
1944
1945 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1946 assert(rscratch != noreg || always_reachable(src), "missing");
1947
1948 if (reachable(src)) {
1949 if (UseXmmLoadAndClearUpper) {
1950 movsd (dst, as_Address(src));
1951 } else {
1952 movlpd(dst, as_Address(src));
1953 }
1954 } else {
1955 lea(rscratch, src);
1956 if (UseXmmLoadAndClearUpper) {
1957 movsd (dst, Address(rscratch, 0));
1958 } else {
1959 movlpd(dst, Address(rscratch, 0));
1960 }
1961 }
1962 }
1963
1964 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
1965 assert(rscratch != noreg || always_reachable(src), "missing");
1966
1967 if (reachable(src)) {
1968 movss(dst, as_Address(src));
1969 } else {
1970 lea(rscratch, src);
1971 movss(dst, Address(rscratch, 0));
1972 }
1973 }
1974
1975 void MacroAssembler::movptr(Register dst, Register src) {
1976 movq(dst, src);
1977 }
1978
1979 void MacroAssembler::movptr(Register dst, Address src) {
1980 movq(dst, src);
1981 }
1982
1983 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
1984 void MacroAssembler::movptr(Register dst, intptr_t src) {
1985 if (is_uimm32(src)) {
1986 movl(dst, checked_cast<uint32_t>(src));
1987 } else if (is_simm32(src)) {
1988 movq(dst, checked_cast<int32_t>(src));
1989 } else {
1990 mov64(dst, src);
1991 }
1992 }
1993
1994 void MacroAssembler::movptr(Address dst, Register src) {
1995 movq(dst, src);
1996 }
1997
1998 void MacroAssembler::movptr(Address dst, int32_t src) {
1999 movslq(dst, src);
2000 }
2001
2002 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2003 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2004 Assembler::movdqu(dst, src);
2005 }
2006
2007 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2008 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2009 Assembler::movdqu(dst, src);
2010 }
2011
2012 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2013 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2014 Assembler::movdqu(dst, src);
2015 }
2016
2017 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2018 assert(rscratch != noreg || always_reachable(src), "missing");
2019
2020 if (reachable(src)) {
2021 movdqu(dst, as_Address(src));
2022 } else {
2023 lea(rscratch, src);
2024 movdqu(dst, Address(rscratch, 0));
2025 }
2026 }
2027
2028 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2029 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2030 Assembler::vmovdqu(dst, src);
2031 }
2032
2033 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2034 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2035 Assembler::vmovdqu(dst, src);
2036 }
2037
2038 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2039 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2040 Assembler::vmovdqu(dst, src);
2041 }
2042
2043 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2044 assert(rscratch != noreg || always_reachable(src), "missing");
2045
2046 if (reachable(src)) {
2047 vmovdqu(dst, as_Address(src));
2048 }
2049 else {
2050 lea(rscratch, src);
2051 vmovdqu(dst, Address(rscratch, 0));
2052 }
2053 }
2054
2055 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2056 assert(rscratch != noreg || always_reachable(src), "missing");
2057
2058 if (vector_len == AVX_512bit) {
2059 evmovdquq(dst, src, AVX_512bit, rscratch);
2060 } else if (vector_len == AVX_256bit) {
2061 vmovdqu(dst, src, rscratch);
2062 } else {
2063 movdqu(dst, src, rscratch);
2064 }
2065 }
2066
2067 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2068 if (vector_len == AVX_512bit) {
2069 evmovdquq(dst, src, AVX_512bit);
2070 } else if (vector_len == AVX_256bit) {
2071 vmovdqu(dst, src);
2072 } else {
2073 movdqu(dst, src);
2074 }
2075 }
2076
2077 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2078 if (vector_len == AVX_512bit) {
2079 evmovdquq(dst, src, AVX_512bit);
2080 } else if (vector_len == AVX_256bit) {
2081 vmovdqu(dst, src);
2082 } else {
2083 movdqu(dst, src);
2084 }
2085 }
2086
2087 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2088 if (vector_len == AVX_512bit) {
2089 evmovdquq(dst, src, AVX_512bit);
2090 } else if (vector_len == AVX_256bit) {
2091 vmovdqu(dst, src);
2092 } else {
2093 movdqu(dst, src);
2094 }
2095 }
2096
2097 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2098 assert(rscratch != noreg || always_reachable(src), "missing");
2099
2100 if (reachable(src)) {
2101 vmovdqa(dst, as_Address(src));
2102 }
2103 else {
2104 lea(rscratch, src);
2105 vmovdqa(dst, Address(rscratch, 0));
2106 }
2107 }
2108
2109 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2110 assert(rscratch != noreg || always_reachable(src), "missing");
2111
2112 if (vector_len == AVX_512bit) {
2113 evmovdqaq(dst, src, AVX_512bit, rscratch);
2114 } else if (vector_len == AVX_256bit) {
2115 vmovdqa(dst, src, rscratch);
2116 } else {
2117 movdqa(dst, src, rscratch);
2118 }
2119 }
2120
2121 void MacroAssembler::kmov(KRegister dst, Address src) {
2122 if (VM_Version::supports_avx512bw()) {
2123 kmovql(dst, src);
2124 } else {
2125 assert(VM_Version::supports_evex(), "");
2126 kmovwl(dst, src);
2127 }
2128 }
2129
2130 void MacroAssembler::kmov(Address dst, KRegister src) {
2131 if (VM_Version::supports_avx512bw()) {
2132 kmovql(dst, src);
2133 } else {
2134 assert(VM_Version::supports_evex(), "");
2135 kmovwl(dst, src);
2136 }
2137 }
2138
2139 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2140 if (VM_Version::supports_avx512bw()) {
2141 kmovql(dst, src);
2142 } else {
2143 assert(VM_Version::supports_evex(), "");
2144 kmovwl(dst, src);
2145 }
2146 }
2147
2148 void MacroAssembler::kmov(Register dst, KRegister src) {
2149 if (VM_Version::supports_avx512bw()) {
2150 kmovql(dst, src);
2151 } else {
2152 assert(VM_Version::supports_evex(), "");
2153 kmovwl(dst, src);
2154 }
2155 }
2156
2157 void MacroAssembler::kmov(KRegister dst, Register src) {
2158 if (VM_Version::supports_avx512bw()) {
2159 kmovql(dst, src);
2160 } else {
2161 assert(VM_Version::supports_evex(), "");
2162 kmovwl(dst, src);
2163 }
2164 }
2165
2166 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2167 assert(rscratch != noreg || always_reachable(src), "missing");
2168
2169 if (reachable(src)) {
2170 kmovql(dst, as_Address(src));
2171 } else {
2172 lea(rscratch, src);
2173 kmovql(dst, Address(rscratch, 0));
2174 }
2175 }
2176
2177 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2178 assert(rscratch != noreg || always_reachable(src), "missing");
2179
2180 if (reachable(src)) {
2181 kmovwl(dst, as_Address(src));
2182 } else {
2183 lea(rscratch, src);
2184 kmovwl(dst, Address(rscratch, 0));
2185 }
2186 }
2187
2188 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2189 int vector_len, Register rscratch) {
2190 assert(rscratch != noreg || always_reachable(src), "missing");
2191
2192 if (reachable(src)) {
2193 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2194 } else {
2195 lea(rscratch, src);
2196 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2197 }
2198 }
2199
2200 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2201 int vector_len, Register rscratch) {
2202 assert(rscratch != noreg || always_reachable(src), "missing");
2203
2204 if (reachable(src)) {
2205 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2206 } else {
2207 lea(rscratch, src);
2208 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2209 }
2210 }
2211
2212 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2213 assert(rscratch != noreg || always_reachable(src), "missing");
2214
2215 if (reachable(src)) {
2216 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2217 } else {
2218 lea(rscratch, src);
2219 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2220 }
2221 }
2222
2223 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2224 assert(rscratch != noreg || always_reachable(src), "missing");
2225
2226 if (reachable(src)) {
2227 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2228 } else {
2229 lea(rscratch, src);
2230 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2231 }
2232 }
2233
2234 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2235 assert(rscratch != noreg || always_reachable(src), "missing");
2236
2237 if (reachable(src)) {
2238 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2239 } else {
2240 lea(rscratch, src);
2241 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2242 }
2243 }
2244
2245 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2246 assert(rscratch != noreg || always_reachable(src), "missing");
2247
2248 if (reachable(src)) {
2249 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2250 } else {
2251 lea(rscratch, src);
2252 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2253 }
2254 }
2255
2256 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2257 assert(rscratch != noreg || always_reachable(src), "missing");
2258
2259 if (reachable(src)) {
2260 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2261 } else {
2262 lea(rscratch, src);
2263 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2264 }
2265 }
2266
2267 void MacroAssembler::movapd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2268 assert(rscratch != noreg || always_reachable(src), "missing");
2269
2270 if (reachable(src)) {
2271 Assembler::movapd(dst, as_Address(src));
2272 } else {
2273 lea(rscratch, src);
2274 Assembler::movapd(dst, Address(rscratch, 0));
2275 }
2276 }
2277
2278 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2279 assert(rscratch != noreg || always_reachable(src), "missing");
2280
2281 if (reachable(src)) {
2282 Assembler::movdqa(dst, as_Address(src));
2283 } else {
2284 lea(rscratch, src);
2285 Assembler::movdqa(dst, Address(rscratch, 0));
2286 }
2287 }
2288
2289 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2290 assert(rscratch != noreg || always_reachable(src), "missing");
2291
2292 if (reachable(src)) {
2293 Assembler::movsd(dst, as_Address(src));
2294 } else {
2295 lea(rscratch, src);
2296 Assembler::movsd(dst, Address(rscratch, 0));
2297 }
2298 }
2299
2300 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2301 assert(rscratch != noreg || always_reachable(src), "missing");
2302
2303 if (reachable(src)) {
2304 Assembler::movss(dst, as_Address(src));
2305 } else {
2306 lea(rscratch, src);
2307 Assembler::movss(dst, Address(rscratch, 0));
2308 }
2309 }
2310
2311 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2312 assert(rscratch != noreg || always_reachable(src), "missing");
2313
2314 if (reachable(src)) {
2315 Assembler::movddup(dst, as_Address(src));
2316 } else {
2317 lea(rscratch, src);
2318 Assembler::movddup(dst, Address(rscratch, 0));
2319 }
2320 }
2321
2322 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2323 assert(rscratch != noreg || always_reachable(src), "missing");
2324
2325 if (reachable(src)) {
2326 Assembler::vmovddup(dst, as_Address(src), vector_len);
2327 } else {
2328 lea(rscratch, src);
2329 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2330 }
2331 }
2332
2333 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2334 assert(rscratch != noreg || always_reachable(src), "missing");
2335
2336 if (reachable(src)) {
2337 Assembler::mulsd(dst, as_Address(src));
2338 } else {
2339 lea(rscratch, src);
2340 Assembler::mulsd(dst, Address(rscratch, 0));
2341 }
2342 }
2343
2344 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2345 assert(rscratch != noreg || always_reachable(src), "missing");
2346
2347 if (reachable(src)) {
2348 Assembler::mulss(dst, as_Address(src));
2349 } else {
2350 lea(rscratch, src);
2351 Assembler::mulss(dst, Address(rscratch, 0));
2352 }
2353 }
2354
2355 void MacroAssembler::null_check(Register reg, int offset) {
2356 if (needs_explicit_null_check(offset)) {
2357 // provoke OS null exception if reg is null by
2358 // accessing M[reg] w/o changing any (non-CC) registers
2359 // NOTE: cmpl is plenty here to provoke a segv
2360 cmpptr(rax, Address(reg, 0));
2361 // Note: should probably use testl(rax, Address(reg, 0));
2362 // may be shorter code (however, this version of
2363 // testl needs to be implemented first)
2364 } else {
2365 // nothing to do, (later) access of M[reg + offset]
2366 // will provoke OS null exception if reg is null
2367 }
2368 }
2369
2370 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2371 andptr(markword, markWord::inline_type_mask_in_place);
2372 cmpptr(markword, markWord::inline_type_pattern);
2373 jcc(Assembler::equal, is_inline_type);
2374 }
2375
2376 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null) {
2377 if (can_be_null) {
2378 testptr(object, object);
2379 jcc(Assembler::zero, not_inline_type);
2380 }
2381 const int is_inline_type_mask = markWord::inline_type_pattern;
2382 movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2383 andptr(tmp, is_inline_type_mask);
2384 cmpptr(tmp, is_inline_type_mask);
2385 jcc(Assembler::notEqual, not_inline_type);
2386 }
2387
2388 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2389 movl(temp_reg, flags);
2390 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2391 jcc(Assembler::notEqual, is_null_free_inline_type);
2392 }
2393
2394 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2395 movl(temp_reg, flags);
2396 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2397 jcc(Assembler::equal, not_null_free_inline_type);
2398 }
2399
2400 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2401 movl(temp_reg, flags);
2402 testl(temp_reg, 1 << ResolvedFieldEntry::is_flat_shift);
2403 jcc(Assembler::notEqual, is_flat);
2404 }
2405
2406 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2407 movl(temp_reg, flags);
2408 testl(temp_reg, 1 << ResolvedFieldEntry::has_null_marker_shift);
2409 jcc(Assembler::notEqual, has_null_marker);
2410 }
2411
2412 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2413 Label test_mark_word;
2414 // load mark word
2415 movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2416 // check displaced
2417 testl(temp_reg, markWord::unlocked_value);
2418 jccb(Assembler::notZero, test_mark_word);
2419 // slow path use klass prototype
2420 push(rscratch1);
2421 load_prototype_header(temp_reg, oop, rscratch1);
2422 pop(rscratch1);
2423
2424 bind(test_mark_word);
2425 testl(temp_reg, test_bit);
2426 jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
2427 }
2428
2429 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg,
2430 Label& is_flat_array) {
2431 #ifdef _LP64
2432 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2433 #else
2434 load_klass(temp_reg, oop, noreg);
2435 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
2436 test_flat_array_layout(temp_reg, is_flat_array);
2437 #endif
2438 }
2439
2440 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2441 Label& is_non_flat_array) {
2442 #ifdef _LP64
2443 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2444 #else
2445 load_klass(temp_reg, oop, noreg);
2446 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
2447 test_non_flat_array_layout(temp_reg, is_non_flat_array);
2448 #endif
2449 }
2450
2451 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
2452 #ifdef _LP64
2453 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2454 #else
2455 Unimplemented();
2456 #endif
2457 }
2458
2459 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2460 #ifdef _LP64
2461 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2462 #else
2463 Unimplemented();
2464 #endif
2465 }
2466
2467 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2468 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2469 jcc(Assembler::notZero, is_flat_array);
2470 }
2471
2472 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
2473 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2474 jcc(Assembler::zero, is_non_flat_array);
2475 }
2476
2477 void MacroAssembler::os_breakpoint() {
2478 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2479 // (e.g., MSVC can't call ps() otherwise)
2480 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2481 }
2482
2483 void MacroAssembler::unimplemented(const char* what) {
2484 const char* buf = nullptr;
2485 {
2486 ResourceMark rm;
2487 stringStream ss;
2488 ss.print("unimplemented: %s", what);
2489 buf = code_string(ss.as_string());
2490 }
2491 stop(buf);
2492 }
2493
2494 #define XSTATE_BV 0x200
2495
2496 void MacroAssembler::pop_CPU_state() {
2497 pop_FPU_state();
2498 pop_IU_state();
2499 }
2500
2501 void MacroAssembler::pop_FPU_state() {
2502 fxrstor(Address(rsp, 0));
2503 addptr(rsp, FPUStateSizeInWords * wordSize);
2504 }
2505
2506 void MacroAssembler::pop_IU_state() {
2507 popa();
2508 addq(rsp, 8);
2509 popf();
2510 }
2511
2512 // Save Integer and Float state
2513 // Warning: Stack must be 16 byte aligned (64bit)
2514 void MacroAssembler::push_CPU_state() {
2515 push_IU_state();
2516 push_FPU_state();
2517 }
2518
2519 void MacroAssembler::push_FPU_state() {
2520 subptr(rsp, FPUStateSizeInWords * wordSize);
2521 fxsave(Address(rsp, 0));
2522 }
2523
2524 void MacroAssembler::push_IU_state() {
2525 // Push flags first because pusha kills them
2526 pushf();
2527 // Make sure rsp stays 16-byte aligned
2528 subq(rsp, 8);
2529 pusha();
2530 }
2531
2532 void MacroAssembler::push_cont_fastpath() {
2533 if (!Continuations::enabled()) return;
2534
2535 Label L_done;
2536 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2537 jccb(Assembler::belowEqual, L_done);
2538 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), rsp);
2539 bind(L_done);
2540 }
2541
2542 void MacroAssembler::pop_cont_fastpath() {
2543 if (!Continuations::enabled()) return;
2544
2545 Label L_done;
2546 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2547 jccb(Assembler::below, L_done);
2548 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), 0);
2549 bind(L_done);
2550 }
2551
2552 void MacroAssembler::inc_held_monitor_count() {
2553 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
2554 }
2555
2556 void MacroAssembler::dec_held_monitor_count() {
2557 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
2558 }
2559
2560 #ifdef ASSERT
2561 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2562 Label no_cont;
2563 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2564 testl(cont, cont);
2565 jcc(Assembler::zero, no_cont);
2566 stop(name);
2567 bind(no_cont);
2568 }
2569 #endif
2570
2571 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { // determine java_thread register
2572 // we must set sp to zero to clear frame
2573 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2574 // must clear fp, so that compiled frames are not confused; it is
2575 // possible that we need it only for debugging
2576 if (clear_fp) {
2577 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2578 }
2579 // Always clear the pc because it could have been set by make_walkable()
2580 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2581 vzeroupper();
2582 }
2583
2584 void MacroAssembler::round_to(Register reg, int modulus) {
2585 addptr(reg, modulus - 1);
2586 andptr(reg, -modulus);
2587 }
2588
2589 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod) {
2590 if (at_return) {
2591 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2592 // we may safely use rsp instead to perform the stack watermark check.
2593 cmpptr(in_nmethod ? rsp : rbp, Address(r15_thread, JavaThread::polling_word_offset()));
2594 jcc(Assembler::above, slow_path);
2595 return;
2596 }
2597 testb(Address(r15_thread, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2598 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2599 }
2600
2601 // Calls to C land
2602 //
2603 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2604 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2605 // has to be reset to 0. This is required to allow proper stack traversal.
2606 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2607 Register last_java_fp,
2608 address last_java_pc,
2609 Register rscratch) {
2610 vzeroupper();
2611 // determine last_java_sp register
2612 if (!last_java_sp->is_valid()) {
2613 last_java_sp = rsp;
2614 }
2615 // last_java_fp is optional
2616 if (last_java_fp->is_valid()) {
2617 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2618 }
2619 // last_java_pc is optional
2620 if (last_java_pc != nullptr) {
2621 Address java_pc(r15_thread,
2622 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
2623 lea(java_pc, InternalAddress(last_java_pc), rscratch);
2624 }
2625 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2626 }
2627
2628 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2629 Register last_java_fp,
2630 Label &L,
2631 Register scratch) {
2632 lea(scratch, L);
2633 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
2634 set_last_Java_frame(last_java_sp, last_java_fp, nullptr, scratch);
2635 }
2636
2637 void MacroAssembler::shlptr(Register dst, int imm8) {
2638 shlq(dst, imm8);
2639 }
2640
2641 void MacroAssembler::shrptr(Register dst, int imm8) {
2642 shrq(dst, imm8);
2643 }
2644
2645 void MacroAssembler::sign_extend_byte(Register reg) {
2646 movsbl(reg, reg); // movsxb
2647 }
2648
2649 void MacroAssembler::sign_extend_short(Register reg) {
2650 movswl(reg, reg); // movsxw
2651 }
2652
2653 void MacroAssembler::testl(Address dst, int32_t imm32) {
2654 if (imm32 >= 0 && is8bit(imm32)) {
2655 testb(dst, imm32);
2656 } else {
2657 Assembler::testl(dst, imm32);
2658 }
2659 }
2660
2661 void MacroAssembler::testl(Register dst, int32_t imm32) {
2662 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
2663 testb(dst, imm32);
2664 } else {
2665 Assembler::testl(dst, imm32);
2666 }
2667 }
2668
2669 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2670 assert(always_reachable(src), "Address should be reachable");
2671 testl(dst, as_Address(src));
2672 }
2673
2674 void MacroAssembler::testq(Address dst, int32_t imm32) {
2675 if (imm32 >= 0) {
2676 testl(dst, imm32);
2677 } else {
2678 Assembler::testq(dst, imm32);
2679 }
2680 }
2681
2682 void MacroAssembler::testq(Register dst, int32_t imm32) {
2683 if (imm32 >= 0) {
2684 testl(dst, imm32);
2685 } else {
2686 Assembler::testq(dst, imm32);
2687 }
2688 }
2689
2690 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2691 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2692 Assembler::pcmpeqb(dst, src);
2693 }
2694
2695 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2696 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2697 Assembler::pcmpeqw(dst, src);
2698 }
2699
2700 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2701 assert((dst->encoding() < 16),"XMM register should be 0-15");
2702 Assembler::pcmpestri(dst, src, imm8);
2703 }
2704
2705 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2706 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2707 Assembler::pcmpestri(dst, src, imm8);
2708 }
2709
2710 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2711 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2712 Assembler::pmovzxbw(dst, src);
2713 }
2714
2715 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2716 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2717 Assembler::pmovzxbw(dst, src);
2718 }
2719
2720 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2721 assert((src->encoding() < 16),"XMM register should be 0-15");
2722 Assembler::pmovmskb(dst, src);
2723 }
2724
2725 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2726 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2727 Assembler::ptest(dst, src);
2728 }
2729
2730 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2731 assert(rscratch != noreg || always_reachable(src), "missing");
2732
2733 if (reachable(src)) {
2734 Assembler::sqrtss(dst, as_Address(src));
2735 } else {
2736 lea(rscratch, src);
2737 Assembler::sqrtss(dst, Address(rscratch, 0));
2738 }
2739 }
2740
2741 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2742 assert(rscratch != noreg || always_reachable(src), "missing");
2743
2744 if (reachable(src)) {
2745 Assembler::subsd(dst, as_Address(src));
2746 } else {
2747 lea(rscratch, src);
2748 Assembler::subsd(dst, Address(rscratch, 0));
2749 }
2750 }
2751
2752 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
2753 assert(rscratch != noreg || always_reachable(src), "missing");
2754
2755 if (reachable(src)) {
2756 Assembler::roundsd(dst, as_Address(src), rmode);
2757 } else {
2758 lea(rscratch, src);
2759 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
2760 }
2761 }
2762
2763 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2764 assert(rscratch != noreg || always_reachable(src), "missing");
2765
2766 if (reachable(src)) {
2767 Assembler::subss(dst, as_Address(src));
2768 } else {
2769 lea(rscratch, src);
2770 Assembler::subss(dst, Address(rscratch, 0));
2771 }
2772 }
2773
2774 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2775 assert(rscratch != noreg || always_reachable(src), "missing");
2776
2777 if (reachable(src)) {
2778 Assembler::ucomisd(dst, as_Address(src));
2779 } else {
2780 lea(rscratch, src);
2781 Assembler::ucomisd(dst, Address(rscratch, 0));
2782 }
2783 }
2784
2785 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2786 assert(rscratch != noreg || always_reachable(src), "missing");
2787
2788 if (reachable(src)) {
2789 Assembler::ucomiss(dst, as_Address(src));
2790 } else {
2791 lea(rscratch, src);
2792 Assembler::ucomiss(dst, Address(rscratch, 0));
2793 }
2794 }
2795
2796 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2797 assert(rscratch != noreg || always_reachable(src), "missing");
2798
2799 // Used in sign-bit flipping with aligned address.
2800 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2801
2802 if (UseAVX > 2 &&
2803 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2804 (dst->encoding() >= 16)) {
2805 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2806 } else if (reachable(src)) {
2807 Assembler::xorpd(dst, as_Address(src));
2808 } else {
2809 lea(rscratch, src);
2810 Assembler::xorpd(dst, Address(rscratch, 0));
2811 }
2812 }
2813
2814 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
2815 if (UseAVX > 2 &&
2816 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2817 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2818 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2819 } else {
2820 Assembler::xorpd(dst, src);
2821 }
2822 }
2823
2824 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
2825 if (UseAVX > 2 &&
2826 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2827 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2828 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2829 } else {
2830 Assembler::xorps(dst, src);
2831 }
2832 }
2833
2834 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
2835 assert(rscratch != noreg || always_reachable(src), "missing");
2836
2837 // Used in sign-bit flipping with aligned address.
2838 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2839
2840 if (UseAVX > 2 &&
2841 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2842 (dst->encoding() >= 16)) {
2843 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2844 } else if (reachable(src)) {
2845 Assembler::xorps(dst, as_Address(src));
2846 } else {
2847 lea(rscratch, src);
2848 Assembler::xorps(dst, Address(rscratch, 0));
2849 }
2850 }
2851
2852 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
2853 assert(rscratch != noreg || always_reachable(src), "missing");
2854
2855 // Used in sign-bit flipping with aligned address.
2856 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
2857 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2858 if (reachable(src)) {
2859 Assembler::pshufb(dst, as_Address(src));
2860 } else {
2861 lea(rscratch, src);
2862 Assembler::pshufb(dst, Address(rscratch, 0));
2863 }
2864 }
2865
2866 // AVX 3-operands instructions
2867
2868 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2869 assert(rscratch != noreg || always_reachable(src), "missing");
2870
2871 if (reachable(src)) {
2872 vaddsd(dst, nds, as_Address(src));
2873 } else {
2874 lea(rscratch, src);
2875 vaddsd(dst, nds, Address(rscratch, 0));
2876 }
2877 }
2878
2879 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2880 assert(rscratch != noreg || always_reachable(src), "missing");
2881
2882 if (reachable(src)) {
2883 vaddss(dst, nds, as_Address(src));
2884 } else {
2885 lea(rscratch, src);
2886 vaddss(dst, nds, Address(rscratch, 0));
2887 }
2888 }
2889
2890 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2891 assert(UseAVX > 0, "requires some form of AVX");
2892 assert(rscratch != noreg || always_reachable(src), "missing");
2893
2894 if (reachable(src)) {
2895 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
2896 } else {
2897 lea(rscratch, src);
2898 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
2899 }
2900 }
2901
2902 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2903 assert(UseAVX > 0, "requires some form of AVX");
2904 assert(rscratch != noreg || always_reachable(src), "missing");
2905
2906 if (reachable(src)) {
2907 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
2908 } else {
2909 lea(rscratch, src);
2910 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
2911 }
2912 }
2913
2914 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2915 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2916 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2917
2918 vandps(dst, nds, negate_field, vector_len, rscratch);
2919 }
2920
2921 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2922 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2923 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2924
2925 vandpd(dst, nds, negate_field, vector_len, rscratch);
2926 }
2927
2928 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2929 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2930 Assembler::vpaddb(dst, nds, src, vector_len);
2931 }
2932
2933 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2934 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2935 Assembler::vpaddb(dst, nds, src, vector_len);
2936 }
2937
2938 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2939 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2940 Assembler::vpaddw(dst, nds, src, vector_len);
2941 }
2942
2943 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2944 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2945 Assembler::vpaddw(dst, nds, src, vector_len);
2946 }
2947
2948 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2949 assert(rscratch != noreg || always_reachable(src), "missing");
2950
2951 if (reachable(src)) {
2952 Assembler::vpand(dst, nds, as_Address(src), vector_len);
2953 } else {
2954 lea(rscratch, src);
2955 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
2956 }
2957 }
2958
2959 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2960 assert(rscratch != noreg || always_reachable(src), "missing");
2961
2962 if (reachable(src)) {
2963 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
2964 } else {
2965 lea(rscratch, src);
2966 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
2967 }
2968 }
2969
2970 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2971 assert(rscratch != noreg || always_reachable(src), "missing");
2972
2973 if (reachable(src)) {
2974 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
2975 } else {
2976 lea(rscratch, src);
2977 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
2978 }
2979 }
2980
2981 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2982 assert(rscratch != noreg || always_reachable(src), "missing");
2983
2984 if (reachable(src)) {
2985 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
2986 } else {
2987 lea(rscratch, src);
2988 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
2989 }
2990 }
2991
2992 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2993 assert(rscratch != noreg || always_reachable(src), "missing");
2994
2995 if (reachable(src)) {
2996 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
2997 } else {
2998 lea(rscratch, src);
2999 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3000 }
3001 }
3002
3003 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3004 assert(rscratch != noreg || always_reachable(src), "missing");
3005
3006 if (reachable(src)) {
3007 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3008 } else {
3009 lea(rscratch, src);
3010 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3011 }
3012 }
3013
3014 // Vector float blend
3015 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3016 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3017 // WARN: Allow dst == (src1|src2), mask == scratch
3018 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3019 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3020 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3021 if (blend_emulation && scratch_available && dst_available) {
3022 if (compute_mask) {
3023 vpsrad(scratch, mask, 32, vector_len);
3024 mask = scratch;
3025 }
3026 if (dst == src1) {
3027 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3028 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3029 } else {
3030 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3031 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3032 }
3033 vpor(dst, dst, scratch, vector_len);
3034 } else {
3035 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3036 }
3037 }
3038
3039 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3040 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3041 // WARN: Allow dst == (src1|src2), mask == scratch
3042 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3043 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3044 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3045 if (blend_emulation && scratch_available && dst_available) {
3046 if (compute_mask) {
3047 vpxor(scratch, scratch, scratch, vector_len);
3048 vpcmpgtq(scratch, scratch, mask, vector_len);
3049 mask = scratch;
3050 }
3051 if (dst == src1) {
3052 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3053 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3054 } else {
3055 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3056 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3057 }
3058 vpor(dst, dst, scratch, vector_len);
3059 } else {
3060 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3061 }
3062 }
3063
3064 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3065 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3066 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3067 }
3068
3069 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3070 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3071 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3072 }
3073
3074 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3075 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3076 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3077 }
3078
3079 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3080 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3081 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3082 }
3083
3084 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3085 assert(rscratch != noreg || always_reachable(src), "missing");
3086
3087 if (reachable(src)) {
3088 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3089 } else {
3090 lea(rscratch, src);
3091 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3092 }
3093 }
3094
3095 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3096 int comparison, bool is_signed, int vector_len, Register rscratch) {
3097 assert(rscratch != noreg || always_reachable(src), "missing");
3098
3099 if (reachable(src)) {
3100 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3101 } else {
3102 lea(rscratch, src);
3103 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3104 }
3105 }
3106
3107 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3108 int comparison, bool is_signed, int vector_len, Register rscratch) {
3109 assert(rscratch != noreg || always_reachable(src), "missing");
3110
3111 if (reachable(src)) {
3112 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3113 } else {
3114 lea(rscratch, src);
3115 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3116 }
3117 }
3118
3119 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3120 int comparison, bool is_signed, int vector_len, Register rscratch) {
3121 assert(rscratch != noreg || always_reachable(src), "missing");
3122
3123 if (reachable(src)) {
3124 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3125 } else {
3126 lea(rscratch, src);
3127 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3128 }
3129 }
3130
3131 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3132 int comparison, bool is_signed, int vector_len, Register rscratch) {
3133 assert(rscratch != noreg || always_reachable(src), "missing");
3134
3135 if (reachable(src)) {
3136 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3137 } else {
3138 lea(rscratch, src);
3139 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3140 }
3141 }
3142
3143 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3144 if (width == Assembler::Q) {
3145 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3146 } else {
3147 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3148 }
3149 }
3150
3151 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3152 int eq_cond_enc = 0x29;
3153 int gt_cond_enc = 0x37;
3154 if (width != Assembler::Q) {
3155 eq_cond_enc = 0x74 + width;
3156 gt_cond_enc = 0x64 + width;
3157 }
3158 switch (cond) {
3159 case eq:
3160 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3161 break;
3162 case neq:
3163 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3164 vallones(xtmp, vector_len);
3165 vpxor(dst, xtmp, dst, vector_len);
3166 break;
3167 case le:
3168 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3169 vallones(xtmp, vector_len);
3170 vpxor(dst, xtmp, dst, vector_len);
3171 break;
3172 case nlt:
3173 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3174 vallones(xtmp, vector_len);
3175 vpxor(dst, xtmp, dst, vector_len);
3176 break;
3177 case lt:
3178 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3179 break;
3180 case nle:
3181 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3182 break;
3183 default:
3184 assert(false, "Should not reach here");
3185 }
3186 }
3187
3188 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3189 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3190 Assembler::vpmovzxbw(dst, src, vector_len);
3191 }
3192
3193 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3194 assert((src->encoding() < 16),"XMM register should be 0-15");
3195 Assembler::vpmovmskb(dst, src, vector_len);
3196 }
3197
3198 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3199 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3200 Assembler::vpmullw(dst, nds, src, vector_len);
3201 }
3202
3203 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3204 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3205 Assembler::vpmullw(dst, nds, src, vector_len);
3206 }
3207
3208 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3209 assert((UseAVX > 0), "AVX support is needed");
3210 assert(rscratch != noreg || always_reachable(src), "missing");
3211
3212 if (reachable(src)) {
3213 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3214 } else {
3215 lea(rscratch, src);
3216 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3217 }
3218 }
3219
3220 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3221 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3222 Assembler::vpsubb(dst, nds, src, vector_len);
3223 }
3224
3225 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3226 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3227 Assembler::vpsubb(dst, nds, src, vector_len);
3228 }
3229
3230 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3231 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3232 Assembler::vpsubw(dst, nds, src, vector_len);
3233 }
3234
3235 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3236 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3237 Assembler::vpsubw(dst, nds, src, vector_len);
3238 }
3239
3240 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3241 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3242 Assembler::vpsraw(dst, nds, shift, vector_len);
3243 }
3244
3245 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3246 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3247 Assembler::vpsraw(dst, nds, shift, vector_len);
3248 }
3249
3250 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3251 assert(UseAVX > 2,"");
3252 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3253 vector_len = 2;
3254 }
3255 Assembler::evpsraq(dst, nds, shift, vector_len);
3256 }
3257
3258 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3259 assert(UseAVX > 2,"");
3260 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3261 vector_len = 2;
3262 }
3263 Assembler::evpsraq(dst, nds, shift, vector_len);
3264 }
3265
3266 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3267 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3268 Assembler::vpsrlw(dst, nds, shift, vector_len);
3269 }
3270
3271 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3272 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3273 Assembler::vpsrlw(dst, nds, shift, vector_len);
3274 }
3275
3276 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3277 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3278 Assembler::vpsllw(dst, nds, shift, vector_len);
3279 }
3280
3281 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3282 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3283 Assembler::vpsllw(dst, nds, shift, vector_len);
3284 }
3285
3286 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3287 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3288 Assembler::vptest(dst, src);
3289 }
3290
3291 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3292 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3293 Assembler::punpcklbw(dst, src);
3294 }
3295
3296 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3297 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3298 Assembler::pshufd(dst, src, mode);
3299 }
3300
3301 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3302 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3303 Assembler::pshuflw(dst, src, mode);
3304 }
3305
3306 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3307 assert(rscratch != noreg || always_reachable(src), "missing");
3308
3309 if (reachable(src)) {
3310 vandpd(dst, nds, as_Address(src), vector_len);
3311 } else {
3312 lea(rscratch, src);
3313 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3314 }
3315 }
3316
3317 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3318 assert(rscratch != noreg || always_reachable(src), "missing");
3319
3320 if (reachable(src)) {
3321 vandps(dst, nds, as_Address(src), vector_len);
3322 } else {
3323 lea(rscratch, src);
3324 vandps(dst, nds, Address(rscratch, 0), vector_len);
3325 }
3326 }
3327
3328 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3329 bool merge, int vector_len, Register rscratch) {
3330 assert(rscratch != noreg || always_reachable(src), "missing");
3331
3332 if (reachable(src)) {
3333 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3334 } else {
3335 lea(rscratch, src);
3336 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3337 }
3338 }
3339
3340 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3341 assert(rscratch != noreg || always_reachable(src), "missing");
3342
3343 if (reachable(src)) {
3344 vdivsd(dst, nds, as_Address(src));
3345 } else {
3346 lea(rscratch, src);
3347 vdivsd(dst, nds, Address(rscratch, 0));
3348 }
3349 }
3350
3351 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3352 assert(rscratch != noreg || always_reachable(src), "missing");
3353
3354 if (reachable(src)) {
3355 vdivss(dst, nds, as_Address(src));
3356 } else {
3357 lea(rscratch, src);
3358 vdivss(dst, nds, Address(rscratch, 0));
3359 }
3360 }
3361
3362 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3363 assert(rscratch != noreg || always_reachable(src), "missing");
3364
3365 if (reachable(src)) {
3366 vmulsd(dst, nds, as_Address(src));
3367 } else {
3368 lea(rscratch, src);
3369 vmulsd(dst, nds, Address(rscratch, 0));
3370 }
3371 }
3372
3373 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3374 assert(rscratch != noreg || always_reachable(src), "missing");
3375
3376 if (reachable(src)) {
3377 vmulss(dst, nds, as_Address(src));
3378 } else {
3379 lea(rscratch, src);
3380 vmulss(dst, nds, Address(rscratch, 0));
3381 }
3382 }
3383
3384 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3385 assert(rscratch != noreg || always_reachable(src), "missing");
3386
3387 if (reachable(src)) {
3388 vsubsd(dst, nds, as_Address(src));
3389 } else {
3390 lea(rscratch, src);
3391 vsubsd(dst, nds, Address(rscratch, 0));
3392 }
3393 }
3394
3395 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3396 assert(rscratch != noreg || always_reachable(src), "missing");
3397
3398 if (reachable(src)) {
3399 vsubss(dst, nds, as_Address(src));
3400 } else {
3401 lea(rscratch, src);
3402 vsubss(dst, nds, Address(rscratch, 0));
3403 }
3404 }
3405
3406 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3407 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3408 assert(rscratch != noreg || always_reachable(src), "missing");
3409
3410 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3411 }
3412
3413 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3414 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3415 assert(rscratch != noreg || always_reachable(src), "missing");
3416
3417 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3418 }
3419
3420 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3421 assert(rscratch != noreg || always_reachable(src), "missing");
3422
3423 if (reachable(src)) {
3424 vxorpd(dst, nds, as_Address(src), vector_len);
3425 } else {
3426 lea(rscratch, src);
3427 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3428 }
3429 }
3430
3431 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3432 assert(rscratch != noreg || always_reachable(src), "missing");
3433
3434 if (reachable(src)) {
3435 vxorps(dst, nds, as_Address(src), vector_len);
3436 } else {
3437 lea(rscratch, src);
3438 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3439 }
3440 }
3441
3442 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3443 assert(rscratch != noreg || always_reachable(src), "missing");
3444
3445 if (UseAVX > 1 || (vector_len < 1)) {
3446 if (reachable(src)) {
3447 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3448 } else {
3449 lea(rscratch, src);
3450 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3451 }
3452 } else {
3453 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3454 }
3455 }
3456
3457 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3458 assert(rscratch != noreg || always_reachable(src), "missing");
3459
3460 if (reachable(src)) {
3461 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3462 } else {
3463 lea(rscratch, src);
3464 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3465 }
3466 }
3467
3468 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3469 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3470 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3471 // The inverted mask is sign-extended
3472 andptr(possibly_non_local, inverted_mask);
3473 }
3474
3475 void MacroAssembler::resolve_jobject(Register value,
3476 Register tmp) {
3477 Register thread = r15_thread;
3478 assert_different_registers(value, thread, tmp);
3479 Label done, tagged, weak_tagged;
3480 testptr(value, value);
3481 jcc(Assembler::zero, done); // Use null as-is.
3482 testptr(value, JNIHandles::tag_mask); // Test for tag.
3483 jcc(Assembler::notZero, tagged);
3484
3485 // Resolve local handle
3486 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp);
3487 verify_oop(value);
3488 jmp(done);
3489
3490 bind(tagged);
3491 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3492 jcc(Assembler::notZero, weak_tagged);
3493
3494 // Resolve global handle
3495 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3496 verify_oop(value);
3497 jmp(done);
3498
3499 bind(weak_tagged);
3500 // Resolve jweak.
3501 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3502 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp);
3503 verify_oop(value);
3504
3505 bind(done);
3506 }
3507
3508 void MacroAssembler::resolve_global_jobject(Register value,
3509 Register tmp) {
3510 Register thread = r15_thread;
3511 assert_different_registers(value, thread, tmp);
3512 Label done;
3513
3514 testptr(value, value);
3515 jcc(Assembler::zero, done); // Use null as-is.
3516
3517 #ifdef ASSERT
3518 {
3519 Label valid_global_tag;
3520 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
3521 jcc(Assembler::notZero, valid_global_tag);
3522 stop("non global jobject using resolve_global_jobject");
3523 bind(valid_global_tag);
3524 }
3525 #endif
3526
3527 // Resolve global handle
3528 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3529 verify_oop(value);
3530
3531 bind(done);
3532 }
3533
3534 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3535 subq(dst, imm32);
3536 }
3537
3538 // Force generation of a 4 byte immediate value even if it fits into 8bit
3539 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3540 subq_imm32(dst, imm32);
3541 }
3542
3543 void MacroAssembler::subptr(Register dst, Register src) {
3544 subq(dst, src);
3545 }
3546
3547 // C++ bool manipulation
3548 void MacroAssembler::testbool(Register dst) {
3549 if(sizeof(bool) == 1)
3550 testb(dst, 0xff);
3551 else if(sizeof(bool) == 2) {
3552 // testw implementation needed for two byte bools
3553 ShouldNotReachHere();
3554 } else if(sizeof(bool) == 4)
3555 testl(dst, dst);
3556 else
3557 // unsupported
3558 ShouldNotReachHere();
3559 }
3560
3561 void MacroAssembler::testptr(Register dst, Register src) {
3562 testq(dst, src);
3563 }
3564
3565 // Object / value buffer allocation...
3566 //
3567 // Kills klass and rsi on LP64
3568 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
3569 Register t1, Register t2,
3570 bool clear_fields, Label& alloc_failed)
3571 {
3572 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
3573 Register layout_size = t1;
3574 assert(new_obj == rax, "needs to be rax");
3575 assert_different_registers(klass, new_obj, t1, t2);
3576
3577 // get instance_size in InstanceKlass (scaled to a count of bytes)
3578 movl(layout_size, Address(klass, Klass::layout_helper_offset()));
3579 // test to see if it is malformed in some way
3580 testl(layout_size, Klass::_lh_instance_slow_path_bit);
3581 jcc(Assembler::notZero, slow_case_no_pop);
3582
3583 // Allocate the instance:
3584 // If TLAB is enabled:
3585 // Try to allocate in the TLAB.
3586 // If fails, go to the slow path.
3587 // Else If inline contiguous allocations are enabled:
3588 // Try to allocate in eden.
3589 // If fails due to heap end, go to slow path.
3590 //
3591 // If TLAB is enabled OR inline contiguous is enabled:
3592 // Initialize the allocation.
3593 // Exit.
3594 //
3595 // Go to slow path.
3596
3597 push(klass);
3598 if (UseTLAB) {
3599 tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case);
3600 if (ZeroTLAB || (!clear_fields)) {
3601 // the fields have been already cleared
3602 jmp(initialize_header);
3603 } else {
3604 // initialize both the header and fields
3605 jmp(initialize_object);
3606 }
3607 } else {
3608 jmp(slow_case);
3609 }
3610
3611 // If UseTLAB is true, the object is created above and there is an initialize need.
3612 // Otherwise, skip and go to the slow path.
3613 if (UseTLAB) {
3614 if (clear_fields) {
3615 // The object is initialized before the header. If the object size is
3616 // zero, go directly to the header initialization.
3617 bind(initialize_object);
3618 if (UseCompactObjectHeaders) {
3619 assert(is_aligned(oopDesc::base_offset_in_bytes(), BytesPerLong), "oop base offset must be 8-byte-aligned");
3620 decrement(layout_size, oopDesc::base_offset_in_bytes());
3621 } else {
3622 decrement(layout_size, sizeof(oopDesc));
3623 }
3624 jcc(Assembler::zero, initialize_header);
3625
3626 // Initialize topmost object field, divide size by 8, check if odd and
3627 // test if zero.
3628 Register zero = klass;
3629 xorl(zero, zero); // use zero reg to clear memory (shorter code)
3630 shrl(layout_size, LogBytesPerLong); // divide by 2*oopSize and set carry flag if odd
3631
3632 #ifdef ASSERT
3633 // make sure instance_size was multiple of 8
3634 Label L;
3635 // Ignore partial flag stall after shrl() since it is debug VM
3636 jcc(Assembler::carryClear, L);
3637 stop("object size is not multiple of 2 - adjust this code");
3638 bind(L);
3639 // must be > 0, no extra check needed here
3640 #endif
3641
3642 // initialize remaining object fields: instance_size was a multiple of 8
3643 {
3644 Label loop;
3645 bind(loop);
3646 int header_size_bytes = oopDesc::header_size() * HeapWordSize;
3647 assert(is_aligned(header_size_bytes, BytesPerLong), "oop header size must be 8-byte-aligned");
3648 movptr(Address(new_obj, layout_size, Address::times_8, header_size_bytes - 1*oopSize), zero);
3649 decrement(layout_size);
3650 jcc(Assembler::notZero, loop);
3651 }
3652 } // clear_fields
3653
3654 // initialize object header only.
3655 bind(initialize_header);
3656 if (UseCompactObjectHeaders || EnableValhalla) {
3657 pop(klass);
3658 Register mark_word = t2;
3659 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
3660 movptr(Address(new_obj, oopDesc::mark_offset_in_bytes ()), mark_word);
3661 } else {
3662 movptr(Address(new_obj, oopDesc::mark_offset_in_bytes()),
3663 (intptr_t)markWord::prototype().value()); // header
3664 pop(klass); // get saved klass back in the register.
3665 }
3666 if (!UseCompactObjectHeaders) {
3667 xorl(rsi, rsi); // use zero reg to clear memory (shorter code)
3668 store_klass_gap(new_obj, rsi); // zero klass gap for compressed oops
3669 movptr(t2, klass); // preserve klass
3670 store_klass(new_obj, t2, rscratch1); // src klass reg is potentially compressed
3671 }
3672 jmp(done);
3673 }
3674
3675 bind(slow_case);
3676 pop(klass);
3677 bind(slow_case_no_pop);
3678 jmp(alloc_failed);
3679
3680 bind(done);
3681 }
3682
3683 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3684 void MacroAssembler::tlab_allocate(Register obj,
3685 Register var_size_in_bytes,
3686 int con_size_in_bytes,
3687 Register t1,
3688 Register t2,
3689 Label& slow_case) {
3690 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3691 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3692 }
3693
3694 RegSet MacroAssembler::call_clobbered_gp_registers() {
3695 RegSet regs;
3696 regs += RegSet::of(rax, rcx, rdx);
3697 #ifndef _WINDOWS
3698 regs += RegSet::of(rsi, rdi);
3699 #endif
3700 regs += RegSet::range(r8, r11);
3701 if (UseAPX) {
3702 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
3703 }
3704 return regs;
3705 }
3706
3707 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3708 int num_xmm_registers = XMMRegister::available_xmm_registers();
3709 #if defined(_WINDOWS)
3710 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3711 if (num_xmm_registers > 16) {
3712 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3713 }
3714 return result;
3715 #else
3716 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3717 #endif
3718 }
3719
3720 // C1 only ever uses the first double/float of the XMM register.
3721 static int xmm_save_size() { return sizeof(double); }
3722
3723 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3724 masm->movdbl(Address(rsp, offset), reg);
3725 }
3726
3727 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3728 masm->movdbl(reg, Address(rsp, offset));
3729 }
3730
3731 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
3732 bool save_fpu, int& gp_area_size, int& xmm_area_size) {
3733
3734 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
3735 StackAlignmentInBytes);
3736 xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
3737
3738 return gp_area_size + xmm_area_size;
3739 }
3740
3741 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3742 block_comment("push_call_clobbered_registers start");
3743 // Regular registers
3744 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3745
3746 int gp_area_size;
3747 int xmm_area_size;
3748 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3749 gp_area_size, xmm_area_size);
3750 subptr(rsp, total_save_size);
3751
3752 push_set(gp_registers_to_push, 0);
3753
3754 if (save_fpu) {
3755 push_set(call_clobbered_xmm_registers(), gp_area_size);
3756 }
3757
3758 block_comment("push_call_clobbered_registers end");
3759 }
3760
3761 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3762 block_comment("pop_call_clobbered_registers start");
3763
3764 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3765
3766 int gp_area_size;
3767 int xmm_area_size;
3768 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3769 gp_area_size, xmm_area_size);
3770
3771 if (restore_fpu) {
3772 pop_set(call_clobbered_xmm_registers(), gp_area_size);
3773 }
3774
3775 pop_set(gp_registers_to_pop, 0);
3776
3777 addptr(rsp, total_save_size);
3778
3779 vzeroupper();
3780
3781 block_comment("pop_call_clobbered_registers end");
3782 }
3783
3784 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3785 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3786 int spill_offset = offset;
3787
3788 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3789 save_xmm_register(this, spill_offset, *it);
3790 spill_offset += xmm_save_size();
3791 }
3792 }
3793
3794 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3795 int restore_size = set.size() * xmm_save_size();
3796 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3797
3798 int restore_offset = offset + restore_size - xmm_save_size();
3799
3800 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3801 restore_xmm_register(this, restore_offset, *it);
3802 restore_offset -= xmm_save_size();
3803 }
3804 }
3805
3806 void MacroAssembler::push_set(RegSet set, int offset) {
3807 int spill_offset;
3808 if (offset == -1) {
3809 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3810 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3811 subptr(rsp, aligned_size);
3812 spill_offset = 0;
3813 } else {
3814 spill_offset = offset;
3815 }
3816
3817 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3818 movptr(Address(rsp, spill_offset), *it);
3819 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3820 }
3821 }
3822
3823 void MacroAssembler::pop_set(RegSet set, int offset) {
3824
3825 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3826 int restore_size = set.size() * gp_reg_size;
3827 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3828
3829 int restore_offset;
3830 if (offset == -1) {
3831 restore_offset = restore_size - gp_reg_size;
3832 } else {
3833 restore_offset = offset + restore_size - gp_reg_size;
3834 }
3835 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3836 movptr(*it, Address(rsp, restore_offset));
3837 restore_offset -= gp_reg_size;
3838 }
3839
3840 if (offset == -1) {
3841 addptr(rsp, aligned_size);
3842 }
3843 }
3844
3845 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3846 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3847 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3848 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3849 Label done;
3850
3851 testptr(length_in_bytes, length_in_bytes);
3852 jcc(Assembler::zero, done);
3853
3854 // initialize topmost word, divide index by 2, check if odd and test if zero
3855 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3856 #ifdef ASSERT
3857 {
3858 Label L;
3859 testptr(length_in_bytes, BytesPerWord - 1);
3860 jcc(Assembler::zero, L);
3861 stop("length must be a multiple of BytesPerWord");
3862 bind(L);
3863 }
3864 #endif
3865 Register index = length_in_bytes;
3866 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3867 if (UseIncDec) {
3868 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3869 } else {
3870 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3871 shrptr(index, 1);
3872 }
3873
3874 // initialize remaining object fields: index is a multiple of 2 now
3875 {
3876 Label loop;
3877 bind(loop);
3878 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3879 decrement(index);
3880 jcc(Assembler::notZero, loop);
3881 }
3882
3883 bind(done);
3884 }
3885
3886 void MacroAssembler::get_inline_type_field_klass(Register holder_klass, Register index, Register inline_klass) {
3887 inline_layout_info(holder_klass, index, inline_klass);
3888 movptr(inline_klass, Address(inline_klass, InlineLayoutInfo::klass_offset()));
3889 }
3890
3891 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
3892 movptr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
3893 #ifdef ASSERT
3894 {
3895 Label done;
3896 cmpptr(layout_info, 0);
3897 jcc(Assembler::notEqual, done);
3898 stop("inline_layout_info_array is null");
3899 bind(done);
3900 }
3901 #endif
3902
3903 InlineLayoutInfo array[2];
3904 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
3905 if (is_power_of_2(size)) {
3906 shll(index, log2i_exact(size)); // Scale index by power of 2
3907 } else {
3908 imull(index, index, size); // Scale the index to be the entry index * array_element_size
3909 }
3910 lea(layout_info, Address(layout_info, index, Address::times_1, Array<InlineLayoutInfo>::base_offset_in_bytes()));
3911 }
3912
3913 // Look up the method for a megamorphic invokeinterface call.
3914 // The target method is determined by <intf_klass, itable_index>.
3915 // The receiver klass is in recv_klass.
3916 // On success, the result will be in method_result, and execution falls through.
3917 // On failure, execution transfers to the given label.
3918 void MacroAssembler::lookup_interface_method(Register recv_klass,
3919 Register intf_klass,
3920 RegisterOrConstant itable_index,
3921 Register method_result,
3922 Register scan_temp,
3923 Label& L_no_such_interface,
3924 bool return_method) {
3925 assert_different_registers(recv_klass, intf_klass, scan_temp);
3926 assert_different_registers(method_result, intf_klass, scan_temp);
3927 assert(recv_klass != method_result || !return_method,
3928 "recv_klass can be destroyed when method isn't needed");
3929
3930 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3931 "caller must use same register for non-constant itable index as for method");
3932
3933 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3934 int vtable_base = in_bytes(Klass::vtable_start_offset());
3935 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3936 int scan_step = itableOffsetEntry::size() * wordSize;
3937 int vte_size = vtableEntry::size_in_bytes();
3938 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3939 assert(vte_size == wordSize, "else adjust times_vte_scale");
3940
3941 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3942
3943 // Could store the aligned, prescaled offset in the klass.
3944 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3945
3946 if (return_method) {
3947 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3948 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3949 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3950 }
3951
3952 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
3953 // if (scan->interface() == intf) {
3954 // result = (klass + scan->offset() + itable_index);
3955 // }
3956 // }
3957 Label search, found_method;
3958
3959 for (int peel = 1; peel >= 0; peel--) {
3960 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
3961 cmpptr(intf_klass, method_result);
3962
3963 if (peel) {
3964 jccb(Assembler::equal, found_method);
3965 } else {
3966 jccb(Assembler::notEqual, search);
3967 // (invert the test to fall through to found_method...)
3968 }
3969
3970 if (!peel) break;
3971
3972 bind(search);
3973
3974 // Check that the previous entry is non-null. A null entry means that
3975 // the receiver class doesn't implement the interface, and wasn't the
3976 // same as when the caller was compiled.
3977 testptr(method_result, method_result);
3978 jcc(Assembler::zero, L_no_such_interface);
3979 addptr(scan_temp, scan_step);
3980 }
3981
3982 bind(found_method);
3983
3984 if (return_method) {
3985 // Got a hit.
3986 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
3987 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3988 }
3989 }
3990
3991 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
3992 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
3993 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
3994 // The target method is determined by <holder_klass, itable_index>.
3995 // The receiver klass is in recv_klass.
3996 // On success, the result will be in method_result, and execution falls through.
3997 // On failure, execution transfers to the given label.
3998 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
3999 Register holder_klass,
4000 Register resolved_klass,
4001 Register method_result,
4002 Register scan_temp,
4003 Register temp_reg2,
4004 Register receiver,
4005 int itable_index,
4006 Label& L_no_such_interface) {
4007 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4008 Register temp_itbl_klass = method_result;
4009 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4010
4011 int vtable_base = in_bytes(Klass::vtable_start_offset());
4012 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4013 int scan_step = itableOffsetEntry::size() * wordSize;
4014 int vte_size = vtableEntry::size_in_bytes();
4015 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4016 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4017 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4018 assert(vte_size == wordSize, "adjust times_vte_scale");
4019
4020 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4021
4022 // temp_itbl_klass = recv_klass.itable[0]
4023 // scan_temp = &recv_klass.itable[0] + step
4024 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4025 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4026 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4027 xorptr(temp_reg, temp_reg);
4028
4029 // Initial checks:
4030 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4031 // - if (itable[0] == 0), no such interface
4032 // - if (itable[0] == holder_klass), shortcut to "holder found"
4033 cmpptr(holder_klass, resolved_klass);
4034 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4035 testptr(temp_itbl_klass, temp_itbl_klass);
4036 jccb(Assembler::zero, L_no_such_interface);
4037 cmpptr(holder_klass, temp_itbl_klass);
4038 jccb(Assembler::equal, L_holder_found);
4039
4040 // Loop: Look for holder_klass record in itable
4041 // do {
4042 // tmp = itable[index];
4043 // index += step;
4044 // if (tmp == holder_klass) {
4045 // goto L_holder_found; // Found!
4046 // }
4047 // } while (tmp != 0);
4048 // goto L_no_such_interface // Not found.
4049 Label L_scan_holder;
4050 bind(L_scan_holder);
4051 movptr(temp_itbl_klass, Address(scan_temp, 0));
4052 addptr(scan_temp, scan_step);
4053 cmpptr(holder_klass, temp_itbl_klass);
4054 jccb(Assembler::equal, L_holder_found);
4055 testptr(temp_itbl_klass, temp_itbl_klass);
4056 jccb(Assembler::notZero, L_scan_holder);
4057
4058 jmpb(L_no_such_interface);
4059
4060 // Loop: Look for resolved_class record in itable
4061 // do {
4062 // tmp = itable[index];
4063 // index += step;
4064 // if (tmp == holder_klass) {
4065 // // Also check if we have met a holder klass
4066 // holder_tmp = itable[index-step-ioffset];
4067 // }
4068 // if (tmp == resolved_klass) {
4069 // goto L_resolved_found; // Found!
4070 // }
4071 // } while (tmp != 0);
4072 // goto L_no_such_interface // Not found.
4073 //
4074 Label L_loop_scan_resolved;
4075 bind(L_loop_scan_resolved);
4076 movptr(temp_itbl_klass, Address(scan_temp, 0));
4077 addptr(scan_temp, scan_step);
4078 bind(L_loop_scan_resolved_entry);
4079 cmpptr(holder_klass, temp_itbl_klass);
4080 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4081 cmpptr(resolved_klass, temp_itbl_klass);
4082 jccb(Assembler::equal, L_resolved_found);
4083 testptr(temp_itbl_klass, temp_itbl_klass);
4084 jccb(Assembler::notZero, L_loop_scan_resolved);
4085
4086 jmpb(L_no_such_interface);
4087
4088 Label L_ready;
4089
4090 // See if we already have a holder klass. If not, go and scan for it.
4091 bind(L_resolved_found);
4092 testptr(temp_reg, temp_reg);
4093 jccb(Assembler::zero, L_scan_holder);
4094 jmpb(L_ready);
4095
4096 bind(L_holder_found);
4097 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4098
4099 // Finally, temp_reg contains holder_klass vtable offset
4100 bind(L_ready);
4101 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4102 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4103 load_klass(scan_temp, receiver, noreg);
4104 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4105 } else {
4106 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4107 }
4108 }
4109
4110
4111 // virtual method calling
4112 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4113 RegisterOrConstant vtable_index,
4114 Register method_result) {
4115 const ByteSize base = Klass::vtable_start_offset();
4116 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4117 Address vtable_entry_addr(recv_klass,
4118 vtable_index, Address::times_ptr,
4119 base + vtableEntry::method_offset());
4120 movptr(method_result, vtable_entry_addr);
4121 }
4122
4123
4124 void MacroAssembler::check_klass_subtype(Register sub_klass,
4125 Register super_klass,
4126 Register temp_reg,
4127 Label& L_success) {
4128 Label L_failure;
4129 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4130 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4131 bind(L_failure);
4132 }
4133
4134
4135 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4136 Register super_klass,
4137 Register temp_reg,
4138 Label* L_success,
4139 Label* L_failure,
4140 Label* L_slow_path,
4141 RegisterOrConstant super_check_offset) {
4142 assert_different_registers(sub_klass, super_klass, temp_reg);
4143 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4144 if (super_check_offset.is_register()) {
4145 assert_different_registers(sub_klass, super_klass,
4146 super_check_offset.as_register());
4147 } else if (must_load_sco) {
4148 assert(temp_reg != noreg, "supply either a temp or a register offset");
4149 }
4150
4151 Label L_fallthrough;
4152 int label_nulls = 0;
4153 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4154 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4155 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4156 assert(label_nulls <= 1, "at most one null in the batch");
4157
4158 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4159 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4160 Address super_check_offset_addr(super_klass, sco_offset);
4161
4162 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4163 // range of a jccb. If this routine grows larger, reconsider at
4164 // least some of these.
4165 #define local_jcc(assembler_cond, label) \
4166 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4167 else jcc( assembler_cond, label) /*omit semi*/
4168
4169 // Hacked jmp, which may only be used just before L_fallthrough.
4170 #define final_jmp(label) \
4171 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4172 else jmp(label) /*omit semi*/
4173
4174 // If the pointers are equal, we are done (e.g., String[] elements).
4175 // This self-check enables sharing of secondary supertype arrays among
4176 // non-primary types such as array-of-interface. Otherwise, each such
4177 // type would need its own customized SSA.
4178 // We move this check to the front of the fast path because many
4179 // type checks are in fact trivially successful in this manner,
4180 // so we get a nicely predicted branch right at the start of the check.
4181 cmpptr(sub_klass, super_klass);
4182 local_jcc(Assembler::equal, *L_success);
4183
4184 // Check the supertype display:
4185 if (must_load_sco) {
4186 // Positive movl does right thing on LP64.
4187 movl(temp_reg, super_check_offset_addr);
4188 super_check_offset = RegisterOrConstant(temp_reg);
4189 }
4190 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4191 cmpptr(super_klass, super_check_addr); // load displayed supertype
4192
4193 // This check has worked decisively for primary supers.
4194 // Secondary supers are sought in the super_cache ('super_cache_addr').
4195 // (Secondary supers are interfaces and very deeply nested subtypes.)
4196 // This works in the same check above because of a tricky aliasing
4197 // between the super_cache and the primary super display elements.
4198 // (The 'super_check_addr' can address either, as the case requires.)
4199 // Note that the cache is updated below if it does not help us find
4200 // what we need immediately.
4201 // So if it was a primary super, we can just fail immediately.
4202 // Otherwise, it's the slow path for us (no success at this point).
4203
4204 if (super_check_offset.is_register()) {
4205 local_jcc(Assembler::equal, *L_success);
4206 cmpl(super_check_offset.as_register(), sc_offset);
4207 if (L_failure == &L_fallthrough) {
4208 local_jcc(Assembler::equal, *L_slow_path);
4209 } else {
4210 local_jcc(Assembler::notEqual, *L_failure);
4211 final_jmp(*L_slow_path);
4212 }
4213 } else if (super_check_offset.as_constant() == sc_offset) {
4214 // Need a slow path; fast failure is impossible.
4215 if (L_slow_path == &L_fallthrough) {
4216 local_jcc(Assembler::equal, *L_success);
4217 } else {
4218 local_jcc(Assembler::notEqual, *L_slow_path);
4219 final_jmp(*L_success);
4220 }
4221 } else {
4222 // No slow path; it's a fast decision.
4223 if (L_failure == &L_fallthrough) {
4224 local_jcc(Assembler::equal, *L_success);
4225 } else {
4226 local_jcc(Assembler::notEqual, *L_failure);
4227 final_jmp(*L_success);
4228 }
4229 }
4230
4231 bind(L_fallthrough);
4232
4233 #undef local_jcc
4234 #undef final_jmp
4235 }
4236
4237
4238 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4239 Register super_klass,
4240 Register temp_reg,
4241 Register temp2_reg,
4242 Label* L_success,
4243 Label* L_failure,
4244 bool set_cond_codes) {
4245 assert_different_registers(sub_klass, super_klass, temp_reg);
4246 if (temp2_reg != noreg)
4247 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4248 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4249
4250 Label L_fallthrough;
4251 int label_nulls = 0;
4252 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4253 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4254 assert(label_nulls <= 1, "at most one null in the batch");
4255
4256 // a couple of useful fields in sub_klass:
4257 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4258 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4259 Address secondary_supers_addr(sub_klass, ss_offset);
4260 Address super_cache_addr( sub_klass, sc_offset);
4261
4262 // Do a linear scan of the secondary super-klass chain.
4263 // This code is rarely used, so simplicity is a virtue here.
4264 // The repne_scan instruction uses fixed registers, which we must spill.
4265 // Don't worry too much about pre-existing connections with the input regs.
4266
4267 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4268 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4269
4270 // Get super_klass value into rax (even if it was in rdi or rcx).
4271 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4272 if (super_klass != rax) {
4273 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4274 mov(rax, super_klass);
4275 }
4276 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4277 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4278
4279 #ifndef PRODUCT
4280 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4281 ExternalAddress pst_counter_addr((address) pst_counter);
4282 lea(rcx, pst_counter_addr);
4283 incrementl(Address(rcx, 0));
4284 #endif //PRODUCT
4285
4286 // We will consult the secondary-super array.
4287 movptr(rdi, secondary_supers_addr);
4288 // Load the array length. (Positive movl does right thing on LP64.)
4289 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4290 // Skip to start of data.
4291 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4292
4293 // Scan RCX words at [RDI] for an occurrence of RAX.
4294 // Set NZ/Z based on last compare.
4295 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4296 // not change flags (only scas instruction which is repeated sets flags).
4297 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4298
4299 testptr(rax,rax); // Set Z = 0
4300 repne_scan();
4301
4302 // Unspill the temp. registers:
4303 if (pushed_rdi) pop(rdi);
4304 if (pushed_rcx) pop(rcx);
4305 if (pushed_rax) pop(rax);
4306
4307 if (set_cond_codes) {
4308 // Special hack for the AD files: rdi is guaranteed non-zero.
4309 assert(!pushed_rdi, "rdi must be left non-null");
4310 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4311 }
4312
4313 if (L_failure == &L_fallthrough)
4314 jccb(Assembler::notEqual, *L_failure);
4315 else jcc(Assembler::notEqual, *L_failure);
4316
4317 // Success. Cache the super we found and proceed in triumph.
4318 movptr(super_cache_addr, super_klass);
4319
4320 if (L_success != &L_fallthrough) {
4321 jmp(*L_success);
4322 }
4323
4324 #undef IS_A_TEMP
4325
4326 bind(L_fallthrough);
4327 }
4328
4329 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4330 Register super_klass,
4331 Register temp_reg,
4332 Register temp2_reg,
4333 Label* L_success,
4334 Label* L_failure,
4335 bool set_cond_codes) {
4336 assert(set_cond_codes == false, "must be false on 64-bit x86");
4337 check_klass_subtype_slow_path
4338 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4339 L_success, L_failure);
4340 }
4341
4342 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4343 Register super_klass,
4344 Register temp_reg,
4345 Register temp2_reg,
4346 Register temp3_reg,
4347 Register temp4_reg,
4348 Label* L_success,
4349 Label* L_failure) {
4350 if (UseSecondarySupersTable) {
4351 check_klass_subtype_slow_path_table
4352 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4353 L_success, L_failure);
4354 } else {
4355 check_klass_subtype_slow_path_linear
4356 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4357 }
4358 }
4359
4360 Register MacroAssembler::allocate_if_noreg(Register r,
4361 RegSetIterator<Register> &available_regs,
4362 RegSet ®s_to_push) {
4363 if (!r->is_valid()) {
4364 r = *available_regs++;
4365 regs_to_push += r;
4366 }
4367 return r;
4368 }
4369
4370 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4371 Register super_klass,
4372 Register temp_reg,
4373 Register temp2_reg,
4374 Register temp3_reg,
4375 Register result_reg,
4376 Label* L_success,
4377 Label* L_failure) {
4378 // NB! Callers may assume that, when temp2_reg is a valid register,
4379 // this code sets it to a nonzero value.
4380 bool temp2_reg_was_valid = temp2_reg->is_valid();
4381
4382 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4383
4384 Label L_fallthrough;
4385 int label_nulls = 0;
4386 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4387 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4388 assert(label_nulls <= 1, "at most one null in the batch");
4389
4390 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4391
4392 RegSetIterator<Register> available_regs
4393 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4394
4395 RegSet pushed_regs;
4396
4397 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4398 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4399 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4400 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4401 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4402
4403 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4404
4405 {
4406
4407 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4408 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4409 subptr(rsp, aligned_size);
4410 push_set(pushed_regs, 0);
4411
4412 lookup_secondary_supers_table_var(sub_klass,
4413 super_klass,
4414 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4415 cmpq(result_reg, 0);
4416
4417 // Unspill the temp. registers:
4418 pop_set(pushed_regs, 0);
4419 // Increment SP but do not clobber flags.
4420 lea(rsp, Address(rsp, aligned_size));
4421 }
4422
4423 if (temp2_reg_was_valid) {
4424 movq(temp2_reg, 1);
4425 }
4426
4427 jcc(Assembler::notEqual, *L_failure);
4428
4429 if (L_success != &L_fallthrough) {
4430 jmp(*L_success);
4431 }
4432
4433 bind(L_fallthrough);
4434 }
4435
4436 // population_count variant for running without the POPCNT
4437 // instruction, which was introduced with SSE4.2 in 2008.
4438 void MacroAssembler::population_count(Register dst, Register src,
4439 Register scratch1, Register scratch2) {
4440 assert_different_registers(src, scratch1, scratch2);
4441 if (UsePopCountInstruction) {
4442 Assembler::popcntq(dst, src);
4443 } else {
4444 assert_different_registers(src, scratch1, scratch2);
4445 assert_different_registers(dst, scratch1, scratch2);
4446 Label loop, done;
4447
4448 mov(scratch1, src);
4449 // dst = 0;
4450 // while(scratch1 != 0) {
4451 // dst++;
4452 // scratch1 &= (scratch1 - 1);
4453 // }
4454 xorl(dst, dst);
4455 testq(scratch1, scratch1);
4456 jccb(Assembler::equal, done);
4457 {
4458 bind(loop);
4459 incq(dst);
4460 movq(scratch2, scratch1);
4461 decq(scratch2);
4462 andq(scratch1, scratch2);
4463 jccb(Assembler::notEqual, loop);
4464 }
4465 bind(done);
4466 }
4467 #ifdef ASSERT
4468 mov64(scratch1, 0xCafeBabeDeadBeef);
4469 movq(scratch2, scratch1);
4470 #endif
4471 }
4472
4473 // Ensure that the inline code and the stub are using the same registers.
4474 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4475 do { \
4476 assert(r_super_klass == rax, "mismatch"); \
4477 assert(r_array_base == rbx, "mismatch"); \
4478 assert(r_array_length == rcx, "mismatch"); \
4479 assert(r_array_index == rdx, "mismatch"); \
4480 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4481 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4482 assert(result == rdi || result == noreg, "mismatch"); \
4483 } while(0)
4484
4485 // Versions of salq and rorq that don't need count to be in rcx
4486
4487 void MacroAssembler::salq(Register dest, Register count) {
4488 if (count == rcx) {
4489 Assembler::salq(dest);
4490 } else {
4491 assert_different_registers(rcx, dest);
4492 xchgq(rcx, count);
4493 Assembler::salq(dest);
4494 xchgq(rcx, count);
4495 }
4496 }
4497
4498 void MacroAssembler::rorq(Register dest, Register count) {
4499 if (count == rcx) {
4500 Assembler::rorq(dest);
4501 } else {
4502 assert_different_registers(rcx, dest);
4503 xchgq(rcx, count);
4504 Assembler::rorq(dest);
4505 xchgq(rcx, count);
4506 }
4507 }
4508
4509 // Return true: we succeeded in generating this code
4510 //
4511 // At runtime, return 0 in result if r_super_klass is a superclass of
4512 // r_sub_klass, otherwise return nonzero. Use this if you know the
4513 // super_klass_slot of the class you're looking for. This is always
4514 // the case for instanceof and checkcast.
4515 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4516 Register r_super_klass,
4517 Register temp1,
4518 Register temp2,
4519 Register temp3,
4520 Register temp4,
4521 Register result,
4522 u1 super_klass_slot) {
4523 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4524
4525 Label L_fallthrough, L_success, L_failure;
4526
4527 BLOCK_COMMENT("lookup_secondary_supers_table {");
4528
4529 const Register
4530 r_array_index = temp1,
4531 r_array_length = temp2,
4532 r_array_base = temp3,
4533 r_bitmap = temp4;
4534
4535 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4536
4537 xorq(result, result); // = 0
4538
4539 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4540 movq(r_array_index, r_bitmap);
4541
4542 // First check the bitmap to see if super_klass might be present. If
4543 // the bit is zero, we are certain that super_klass is not one of
4544 // the secondary supers.
4545 u1 bit = super_klass_slot;
4546 {
4547 // NB: If the count in a x86 shift instruction is 0, the flags are
4548 // not affected, so we do a testq instead.
4549 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4550 if (shift_count != 0) {
4551 salq(r_array_index, shift_count);
4552 } else {
4553 testq(r_array_index, r_array_index);
4554 }
4555 }
4556 // We test the MSB of r_array_index, i.e. its sign bit
4557 jcc(Assembler::positive, L_failure);
4558
4559 // Get the first array index that can contain super_klass into r_array_index.
4560 if (bit != 0) {
4561 population_count(r_array_index, r_array_index, temp2, temp3);
4562 } else {
4563 movl(r_array_index, 1);
4564 }
4565 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4566
4567 // We will consult the secondary-super array.
4568 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4569
4570 // We're asserting that the first word in an Array<Klass*> is the
4571 // length, and the second word is the first word of the data. If
4572 // that ever changes, r_array_base will have to be adjusted here.
4573 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4574 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4575
4576 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4577 jccb(Assembler::equal, L_success);
4578
4579 // Is there another entry to check? Consult the bitmap.
4580 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4581 jccb(Assembler::carryClear, L_failure);
4582
4583 // Linear probe. Rotate the bitmap so that the next bit to test is
4584 // in Bit 1.
4585 if (bit != 0) {
4586 rorq(r_bitmap, bit);
4587 }
4588
4589 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4590 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4591 // Kills: r_array_length.
4592 // Returns: result.
4593 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4594 // Result (0/1) is in rdi
4595 jmpb(L_fallthrough);
4596
4597 bind(L_failure);
4598 incq(result); // 0 => 1
4599
4600 bind(L_success);
4601 // result = 0;
4602
4603 bind(L_fallthrough);
4604 BLOCK_COMMENT("} lookup_secondary_supers_table");
4605
4606 if (VerifySecondarySupers) {
4607 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4608 temp1, temp2, temp3);
4609 }
4610 }
4611
4612 // At runtime, return 0 in result if r_super_klass is a superclass of
4613 // r_sub_klass, otherwise return nonzero. Use this version of
4614 // lookup_secondary_supers_table() if you don't know ahead of time
4615 // which superclass will be searched for. Used by interpreter and
4616 // runtime stubs. It is larger and has somewhat greater latency than
4617 // the version above, which takes a constant super_klass_slot.
4618 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
4619 Register r_super_klass,
4620 Register temp1,
4621 Register temp2,
4622 Register temp3,
4623 Register temp4,
4624 Register result) {
4625 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4626 assert_different_registers(r_sub_klass, r_super_klass, rcx);
4627 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
4628
4629 Label L_fallthrough, L_success, L_failure;
4630
4631 BLOCK_COMMENT("lookup_secondary_supers_table {");
4632
4633 RegSetIterator<Register> available_regs = (temps - rcx).begin();
4634
4635 // FIXME. Once we are sure that all paths reaching this point really
4636 // do pass rcx as one of our temps we can get rid of the following
4637 // workaround.
4638 assert(temps.contains(rcx), "fix this code");
4639
4640 // We prefer to have our shift count in rcx. If rcx is one of our
4641 // temps, use it for slot. If not, pick any of our temps.
4642 Register slot;
4643 if (!temps.contains(rcx)) {
4644 slot = *available_regs++;
4645 } else {
4646 slot = rcx;
4647 }
4648
4649 const Register r_array_index = *available_regs++;
4650 const Register r_bitmap = *available_regs++;
4651
4652 // The logic above guarantees this property, but we state it here.
4653 assert_different_registers(r_array_index, r_bitmap, rcx);
4654
4655 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4656 movq(r_array_index, r_bitmap);
4657
4658 // First check the bitmap to see if super_klass might be present. If
4659 // the bit is zero, we are certain that super_klass is not one of
4660 // the secondary supers.
4661 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4662 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
4663 salq(r_array_index, slot);
4664
4665 testq(r_array_index, r_array_index);
4666 // We test the MSB of r_array_index, i.e. its sign bit
4667 jcc(Assembler::positive, L_failure);
4668
4669 const Register r_array_base = *available_regs++;
4670
4671 // Get the first array index that can contain super_klass into r_array_index.
4672 // Note: Clobbers r_array_base and slot.
4673 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
4674
4675 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4676
4677 // We will consult the secondary-super array.
4678 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4679
4680 // We're asserting that the first word in an Array<Klass*> is the
4681 // length, and the second word is the first word of the data. If
4682 // that ever changes, r_array_base will have to be adjusted here.
4683 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4684 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4685
4686 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4687 jccb(Assembler::equal, L_success);
4688
4689 // Restore slot to its true value
4690 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4691
4692 // Linear probe. Rotate the bitmap so that the next bit to test is
4693 // in Bit 1.
4694 rorq(r_bitmap, slot);
4695
4696 // Is there another entry to check? Consult the bitmap.
4697 btq(r_bitmap, 1);
4698 jccb(Assembler::carryClear, L_failure);
4699
4700 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4701 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4702 // Kills: r_array_length.
4703 // Returns: result.
4704 lookup_secondary_supers_table_slow_path(r_super_klass,
4705 r_array_base,
4706 r_array_index,
4707 r_bitmap,
4708 /*temp1*/result,
4709 /*temp2*/slot,
4710 &L_success,
4711 nullptr);
4712
4713 bind(L_failure);
4714 movq(result, 1);
4715 jmpb(L_fallthrough);
4716
4717 bind(L_success);
4718 xorq(result, result); // = 0
4719
4720 bind(L_fallthrough);
4721 BLOCK_COMMENT("} lookup_secondary_supers_table");
4722
4723 if (VerifySecondarySupers) {
4724 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4725 temp1, temp2, temp3);
4726 }
4727 }
4728
4729 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4730 Label* L_success, Label* L_failure) {
4731 Label L_loop, L_fallthrough;
4732 {
4733 int label_nulls = 0;
4734 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4735 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4736 assert(label_nulls <= 1, "at most one null in the batch");
4737 }
4738 bind(L_loop);
4739 cmpq(value, Address(addr, count, Address::times_8));
4740 jcc(Assembler::equal, *L_success);
4741 addl(count, 1);
4742 cmpl(count, limit);
4743 jcc(Assembler::less, L_loop);
4744
4745 if (&L_fallthrough != L_failure) {
4746 jmp(*L_failure);
4747 }
4748 bind(L_fallthrough);
4749 }
4750
4751 // Called by code generated by check_klass_subtype_slow_path
4752 // above. This is called when there is a collision in the hashed
4753 // lookup in the secondary supers array.
4754 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4755 Register r_array_base,
4756 Register r_array_index,
4757 Register r_bitmap,
4758 Register temp1,
4759 Register temp2,
4760 Label* L_success,
4761 Label* L_failure) {
4762 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4763
4764 const Register
4765 r_array_length = temp1,
4766 r_sub_klass = noreg,
4767 result = noreg;
4768
4769 Label L_fallthrough;
4770 int label_nulls = 0;
4771 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4772 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4773 assert(label_nulls <= 1, "at most one null in the batch");
4774
4775 // Load the array length.
4776 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4777 // And adjust the array base to point to the data.
4778 // NB! Effectively increments current slot index by 1.
4779 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4780 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4781
4782 // Linear probe
4783 Label L_huge;
4784
4785 // The bitmap is full to bursting.
4786 // Implicit invariant: BITMAP_FULL implies (length > 0)
4787 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
4788 jcc(Assembler::greater, L_huge);
4789
4790 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4791 // current slot (at secondary_supers[r_array_index]) has not yet
4792 // been inspected, and r_array_index may be out of bounds if we
4793 // wrapped around the end of the array.
4794
4795 { // This is conventional linear probing, but instead of terminating
4796 // when a null entry is found in the table, we maintain a bitmap
4797 // in which a 0 indicates missing entries.
4798 // The check above guarantees there are 0s in the bitmap, so the loop
4799 // eventually terminates.
4800
4801 xorl(temp2, temp2); // = 0;
4802
4803 Label L_again;
4804 bind(L_again);
4805
4806 // Check for array wraparound.
4807 cmpl(r_array_index, r_array_length);
4808 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4809
4810 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4811 jcc(Assembler::equal, *L_success);
4812
4813 // If the next bit in bitmap is zero, we're done.
4814 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4815 jcc(Assembler::carryClear, *L_failure);
4816
4817 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4818 addl(r_array_index, 1);
4819
4820 jmp(L_again);
4821 }
4822
4823 { // Degenerate case: more than 64 secondary supers.
4824 // FIXME: We could do something smarter here, maybe a vectorized
4825 // comparison or a binary search, but is that worth any added
4826 // complexity?
4827 bind(L_huge);
4828 xorl(r_array_index, r_array_index); // = 0
4829 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4830 L_success,
4831 (&L_fallthrough != L_failure ? L_failure : nullptr));
4832
4833 bind(L_fallthrough);
4834 }
4835 }
4836
4837 struct VerifyHelperArguments {
4838 Klass* _super;
4839 Klass* _sub;
4840 intptr_t _linear_result;
4841 intptr_t _table_result;
4842 };
4843
4844 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
4845 Klass::on_secondary_supers_verification_failure(args->_super,
4846 args->_sub,
4847 args->_linear_result,
4848 args->_table_result,
4849 msg);
4850 }
4851
4852 // Make sure that the hashed lookup and a linear scan agree.
4853 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
4854 Register r_super_klass,
4855 Register result,
4856 Register temp1,
4857 Register temp2,
4858 Register temp3) {
4859 const Register
4860 r_array_index = temp1,
4861 r_array_length = temp2,
4862 r_array_base = temp3,
4863 r_bitmap = noreg;
4864
4865 BLOCK_COMMENT("verify_secondary_supers_table {");
4866
4867 Label L_success, L_failure, L_check, L_done;
4868
4869 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4870 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4871 // And adjust the array base to point to the data.
4872 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4873
4874 testl(r_array_length, r_array_length); // array_length == 0?
4875 jcc(Assembler::zero, L_failure);
4876
4877 movl(r_array_index, 0);
4878 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
4879 // fall through to L_failure
4880
4881 const Register linear_result = r_array_index; // reuse temp1
4882
4883 bind(L_failure); // not present
4884 movl(linear_result, 1);
4885 jmp(L_check);
4886
4887 bind(L_success); // present
4888 movl(linear_result, 0);
4889
4890 bind(L_check);
4891 cmpl(linear_result, result);
4892 jcc(Assembler::equal, L_done);
4893
4894 { // To avoid calling convention issues, build a record on the stack
4895 // and pass the pointer to that instead.
4896 push(result);
4897 push(linear_result);
4898 push(r_sub_klass);
4899 push(r_super_klass);
4900 movptr(c_rarg1, rsp);
4901 movptr(c_rarg0, (uintptr_t) "mismatch");
4902 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
4903 should_not_reach_here();
4904 }
4905 bind(L_done);
4906
4907 BLOCK_COMMENT("} verify_secondary_supers_table");
4908 }
4909
4910 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
4911
4912 void MacroAssembler::clinit_barrier(Register klass, Label* L_fast_path, Label* L_slow_path) {
4913 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
4914
4915 Label L_fallthrough;
4916 if (L_fast_path == nullptr) {
4917 L_fast_path = &L_fallthrough;
4918 } else if (L_slow_path == nullptr) {
4919 L_slow_path = &L_fallthrough;
4920 }
4921
4922 // Fast path check: class is fully initialized.
4923 // init_state needs acquire, but x86 is TSO, and so we are already good.
4924 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4925 jcc(Assembler::equal, *L_fast_path);
4926
4927 // Fast path check: current thread is initializer thread
4928 cmpptr(r15_thread, Address(klass, InstanceKlass::init_thread_offset()));
4929 if (L_slow_path == &L_fallthrough) {
4930 jcc(Assembler::equal, *L_fast_path);
4931 bind(*L_slow_path);
4932 } else if (L_fast_path == &L_fallthrough) {
4933 jcc(Assembler::notEqual, *L_slow_path);
4934 bind(*L_fast_path);
4935 } else {
4936 Unimplemented();
4937 }
4938 }
4939
4940 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4941 if (VM_Version::supports_cmov()) {
4942 cmovl(cc, dst, src);
4943 } else {
4944 Label L;
4945 jccb(negate_condition(cc), L);
4946 movl(dst, src);
4947 bind(L);
4948 }
4949 }
4950
4951 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4952 if (VM_Version::supports_cmov()) {
4953 cmovl(cc, dst, src);
4954 } else {
4955 Label L;
4956 jccb(negate_condition(cc), L);
4957 movl(dst, src);
4958 bind(L);
4959 }
4960 }
4961
4962 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4963 if (!VerifyOops || VerifyAdapterSharing) {
4964 // Below address of the code string confuses VerifyAdapterSharing
4965 // because it may differ between otherwise equivalent adapters.
4966 return;
4967 }
4968
4969 BLOCK_COMMENT("verify_oop {");
4970 push(rscratch1);
4971 push(rax); // save rax
4972 push(reg); // pass register argument
4973
4974 // Pass register number to verify_oop_subroutine
4975 const char* b = nullptr;
4976 {
4977 ResourceMark rm;
4978 stringStream ss;
4979 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4980 b = code_string(ss.as_string());
4981 }
4982 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
4983 pushptr(buffer.addr(), rscratch1);
4984
4985 // call indirectly to solve generation ordering problem
4986 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4987 call(rax);
4988 // Caller pops the arguments (oop, message) and restores rax, r10
4989 BLOCK_COMMENT("} verify_oop");
4990 }
4991
4992 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4993 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4994 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
4995 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
4996 vpternlogd(dst, 0xFF, dst, dst, vector_len);
4997 } else if (VM_Version::supports_avx()) {
4998 vpcmpeqd(dst, dst, dst, vector_len);
4999 } else {
5000 pcmpeqd(dst, dst);
5001 }
5002 }
5003
5004 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5005 int extra_slot_offset) {
5006 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5007 int stackElementSize = Interpreter::stackElementSize;
5008 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5009 #ifdef ASSERT
5010 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5011 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5012 #endif
5013 Register scale_reg = noreg;
5014 Address::ScaleFactor scale_factor = Address::no_scale;
5015 if (arg_slot.is_constant()) {
5016 offset += arg_slot.as_constant() * stackElementSize;
5017 } else {
5018 scale_reg = arg_slot.as_register();
5019 scale_factor = Address::times(stackElementSize);
5020 }
5021 offset += wordSize; // return PC is on stack
5022 return Address(rsp, scale_reg, scale_factor, offset);
5023 }
5024
5025 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5026 if (!VerifyOops || VerifyAdapterSharing) {
5027 // Below address of the code string confuses VerifyAdapterSharing
5028 // because it may differ between otherwise equivalent adapters.
5029 return;
5030 }
5031
5032 push(rscratch1);
5033 push(rax); // save rax,
5034 // addr may contain rsp so we will have to adjust it based on the push
5035 // we just did (and on 64 bit we do two pushes)
5036 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5037 // stores rax into addr which is backwards of what was intended.
5038 if (addr.uses(rsp)) {
5039 lea(rax, addr);
5040 pushptr(Address(rax, 2 * BytesPerWord));
5041 } else {
5042 pushptr(addr);
5043 }
5044
5045 // Pass register number to verify_oop_subroutine
5046 const char* b = nullptr;
5047 {
5048 ResourceMark rm;
5049 stringStream ss;
5050 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5051 b = code_string(ss.as_string());
5052 }
5053 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5054 pushptr(buffer.addr(), rscratch1);
5055
5056 // call indirectly to solve generation ordering problem
5057 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5058 call(rax);
5059 // Caller pops the arguments (addr, message) and restores rax, r10.
5060 }
5061
5062 void MacroAssembler::verify_tlab() {
5063 #ifdef ASSERT
5064 if (UseTLAB && VerifyOops) {
5065 Label next, ok;
5066 Register t1 = rsi;
5067
5068 push(t1);
5069
5070 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5071 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
5072 jcc(Assembler::aboveEqual, next);
5073 STOP("assert(top >= start)");
5074 should_not_reach_here();
5075
5076 bind(next);
5077 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
5078 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5079 jcc(Assembler::aboveEqual, ok);
5080 STOP("assert(top <= end)");
5081 should_not_reach_here();
5082
5083 bind(ok);
5084 pop(t1);
5085 }
5086 #endif
5087 }
5088
5089 class ControlWord {
5090 public:
5091 int32_t _value;
5092
5093 int rounding_control() const { return (_value >> 10) & 3 ; }
5094 int precision_control() const { return (_value >> 8) & 3 ; }
5095 bool precision() const { return ((_value >> 5) & 1) != 0; }
5096 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5097 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5098 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5099 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5100 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5101
5102 void print() const {
5103 // rounding control
5104 const char* rc;
5105 switch (rounding_control()) {
5106 case 0: rc = "round near"; break;
5107 case 1: rc = "round down"; break;
5108 case 2: rc = "round up "; break;
5109 case 3: rc = "chop "; break;
5110 default:
5111 rc = nullptr; // silence compiler warnings
5112 fatal("Unknown rounding control: %d", rounding_control());
5113 };
5114 // precision control
5115 const char* pc;
5116 switch (precision_control()) {
5117 case 0: pc = "24 bits "; break;
5118 case 1: pc = "reserved"; break;
5119 case 2: pc = "53 bits "; break;
5120 case 3: pc = "64 bits "; break;
5121 default:
5122 pc = nullptr; // silence compiler warnings
5123 fatal("Unknown precision control: %d", precision_control());
5124 };
5125 // flags
5126 char f[9];
5127 f[0] = ' ';
5128 f[1] = ' ';
5129 f[2] = (precision ()) ? 'P' : 'p';
5130 f[3] = (underflow ()) ? 'U' : 'u';
5131 f[4] = (overflow ()) ? 'O' : 'o';
5132 f[5] = (zero_divide ()) ? 'Z' : 'z';
5133 f[6] = (denormalized()) ? 'D' : 'd';
5134 f[7] = (invalid ()) ? 'I' : 'i';
5135 f[8] = '\x0';
5136 // output
5137 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5138 }
5139
5140 };
5141
5142 class StatusWord {
5143 public:
5144 int32_t _value;
5145
5146 bool busy() const { return ((_value >> 15) & 1) != 0; }
5147 bool C3() const { return ((_value >> 14) & 1) != 0; }
5148 bool C2() const { return ((_value >> 10) & 1) != 0; }
5149 bool C1() const { return ((_value >> 9) & 1) != 0; }
5150 bool C0() const { return ((_value >> 8) & 1) != 0; }
5151 int top() const { return (_value >> 11) & 7 ; }
5152 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5153 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5154 bool precision() const { return ((_value >> 5) & 1) != 0; }
5155 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5156 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5157 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5158 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5159 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5160
5161 void print() const {
5162 // condition codes
5163 char c[5];
5164 c[0] = (C3()) ? '3' : '-';
5165 c[1] = (C2()) ? '2' : '-';
5166 c[2] = (C1()) ? '1' : '-';
5167 c[3] = (C0()) ? '0' : '-';
5168 c[4] = '\x0';
5169 // flags
5170 char f[9];
5171 f[0] = (error_status()) ? 'E' : '-';
5172 f[1] = (stack_fault ()) ? 'S' : '-';
5173 f[2] = (precision ()) ? 'P' : '-';
5174 f[3] = (underflow ()) ? 'U' : '-';
5175 f[4] = (overflow ()) ? 'O' : '-';
5176 f[5] = (zero_divide ()) ? 'Z' : '-';
5177 f[6] = (denormalized()) ? 'D' : '-';
5178 f[7] = (invalid ()) ? 'I' : '-';
5179 f[8] = '\x0';
5180 // output
5181 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5182 }
5183
5184 };
5185
5186 class TagWord {
5187 public:
5188 int32_t _value;
5189
5190 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5191
5192 void print() const {
5193 printf("%04x", _value & 0xFFFF);
5194 }
5195
5196 };
5197
5198 class FPU_Register {
5199 public:
5200 int32_t _m0;
5201 int32_t _m1;
5202 int16_t _ex;
5203
5204 bool is_indefinite() const {
5205 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5206 }
5207
5208 void print() const {
5209 char sign = (_ex < 0) ? '-' : '+';
5210 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5211 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5212 };
5213
5214 };
5215
5216 class FPU_State {
5217 public:
5218 enum {
5219 register_size = 10,
5220 number_of_registers = 8,
5221 register_mask = 7
5222 };
5223
5224 ControlWord _control_word;
5225 StatusWord _status_word;
5226 TagWord _tag_word;
5227 int32_t _error_offset;
5228 int32_t _error_selector;
5229 int32_t _data_offset;
5230 int32_t _data_selector;
5231 int8_t _register[register_size * number_of_registers];
5232
5233 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5234 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5235
5236 const char* tag_as_string(int tag) const {
5237 switch (tag) {
5238 case 0: return "valid";
5239 case 1: return "zero";
5240 case 2: return "special";
5241 case 3: return "empty";
5242 }
5243 ShouldNotReachHere();
5244 return nullptr;
5245 }
5246
5247 void print() const {
5248 // print computation registers
5249 { int t = _status_word.top();
5250 for (int i = 0; i < number_of_registers; i++) {
5251 int j = (i - t) & register_mask;
5252 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5253 st(j)->print();
5254 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5255 }
5256 }
5257 printf("\n");
5258 // print control registers
5259 printf("ctrl = "); _control_word.print(); printf("\n");
5260 printf("stat = "); _status_word .print(); printf("\n");
5261 printf("tags = "); _tag_word .print(); printf("\n");
5262 }
5263
5264 };
5265
5266 class Flag_Register {
5267 public:
5268 int32_t _value;
5269
5270 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5271 bool direction() const { return ((_value >> 10) & 1) != 0; }
5272 bool sign() const { return ((_value >> 7) & 1) != 0; }
5273 bool zero() const { return ((_value >> 6) & 1) != 0; }
5274 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5275 bool parity() const { return ((_value >> 2) & 1) != 0; }
5276 bool carry() const { return ((_value >> 0) & 1) != 0; }
5277
5278 void print() const {
5279 // flags
5280 char f[8];
5281 f[0] = (overflow ()) ? 'O' : '-';
5282 f[1] = (direction ()) ? 'D' : '-';
5283 f[2] = (sign ()) ? 'S' : '-';
5284 f[3] = (zero ()) ? 'Z' : '-';
5285 f[4] = (auxiliary_carry()) ? 'A' : '-';
5286 f[5] = (parity ()) ? 'P' : '-';
5287 f[6] = (carry ()) ? 'C' : '-';
5288 f[7] = '\x0';
5289 // output
5290 printf("%08x flags = %s", _value, f);
5291 }
5292
5293 };
5294
5295 class IU_Register {
5296 public:
5297 int32_t _value;
5298
5299 void print() const {
5300 printf("%08x %11d", _value, _value);
5301 }
5302
5303 };
5304
5305 class IU_State {
5306 public:
5307 Flag_Register _eflags;
5308 IU_Register _rdi;
5309 IU_Register _rsi;
5310 IU_Register _rbp;
5311 IU_Register _rsp;
5312 IU_Register _rbx;
5313 IU_Register _rdx;
5314 IU_Register _rcx;
5315 IU_Register _rax;
5316
5317 void print() const {
5318 // computation registers
5319 printf("rax, = "); _rax.print(); printf("\n");
5320 printf("rbx, = "); _rbx.print(); printf("\n");
5321 printf("rcx = "); _rcx.print(); printf("\n");
5322 printf("rdx = "); _rdx.print(); printf("\n");
5323 printf("rdi = "); _rdi.print(); printf("\n");
5324 printf("rsi = "); _rsi.print(); printf("\n");
5325 printf("rbp, = "); _rbp.print(); printf("\n");
5326 printf("rsp = "); _rsp.print(); printf("\n");
5327 printf("\n");
5328 // control registers
5329 printf("flgs = "); _eflags.print(); printf("\n");
5330 }
5331 };
5332
5333
5334 class CPU_State {
5335 public:
5336 FPU_State _fpu_state;
5337 IU_State _iu_state;
5338
5339 void print() const {
5340 printf("--------------------------------------------------\n");
5341 _iu_state .print();
5342 printf("\n");
5343 _fpu_state.print();
5344 printf("--------------------------------------------------\n");
5345 }
5346
5347 };
5348
5349
5350 static void _print_CPU_state(CPU_State* state) {
5351 state->print();
5352 };
5353
5354
5355 void MacroAssembler::print_CPU_state() {
5356 push_CPU_state();
5357 push(rsp); // pass CPU state
5358 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5359 addptr(rsp, wordSize); // discard argument
5360 pop_CPU_state();
5361 }
5362
5363 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5364 // Either restore the MXCSR register after returning from the JNI Call
5365 // or verify that it wasn't changed (with -Xcheck:jni flag).
5366 if (VM_Version::supports_sse()) {
5367 if (RestoreMXCSROnJNICalls) {
5368 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5369 } else if (CheckJNICalls) {
5370 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5371 }
5372 }
5373 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5374 vzeroupper();
5375 }
5376
5377 // ((OopHandle)result).resolve();
5378 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5379 assert_different_registers(result, tmp);
5380
5381 // Only 64 bit platforms support GCs that require a tmp register
5382 // Only IN_HEAP loads require a thread_tmp register
5383 // OopHandle::resolve is an indirection like jobject.
5384 access_load_at(T_OBJECT, IN_NATIVE,
5385 result, Address(result, 0), tmp);
5386 }
5387
5388 // ((WeakHandle)result).resolve();
5389 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5390 assert_different_registers(rresult, rtmp);
5391 Label resolved;
5392
5393 // A null weak handle resolves to null.
5394 cmpptr(rresult, 0);
5395 jcc(Assembler::equal, resolved);
5396
5397 // Only 64 bit platforms support GCs that require a tmp register
5398 // Only IN_HEAP loads require a thread_tmp register
5399 // WeakHandle::resolve is an indirection like jweak.
5400 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5401 rresult, Address(rresult, 0), rtmp);
5402 bind(resolved);
5403 }
5404
5405 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5406 // get mirror
5407 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5408 load_method_holder(mirror, method);
5409 movptr(mirror, Address(mirror, mirror_offset));
5410 resolve_oop_handle(mirror, tmp);
5411 }
5412
5413 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5414 load_method_holder(rresult, rmethod);
5415 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5416 }
5417
5418 void MacroAssembler::load_method_holder(Register holder, Register method) {
5419 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5420 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5421 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5422 }
5423
5424 void MacroAssembler::load_metadata(Register dst, Register src) {
5425 if (UseCompactObjectHeaders) {
5426 load_narrow_klass_compact(dst, src);
5427 } else if (UseCompressedClassPointers) {
5428 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5429 } else {
5430 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5431 }
5432 }
5433
5434 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5435 assert(UseCompactObjectHeaders, "expect compact object headers");
5436 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5437 shrq(dst, markWord::klass_shift);
5438 }
5439
5440 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5441 assert_different_registers(src, tmp);
5442 assert_different_registers(dst, tmp);
5443
5444 if (UseCompactObjectHeaders) {
5445 load_narrow_klass_compact(dst, src);
5446 decode_klass_not_null(dst, tmp);
5447 } else if (UseCompressedClassPointers) {
5448 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5449 decode_klass_not_null(dst, tmp);
5450 } else {
5451 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5452 }
5453 }
5454
5455 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
5456 load_klass(dst, src, tmp);
5457 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5458 }
5459
5460 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5461 assert(!UseCompactObjectHeaders, "not with compact headers");
5462 assert_different_registers(src, tmp);
5463 assert_different_registers(dst, tmp);
5464 if (UseCompressedClassPointers) {
5465 encode_klass_not_null(src, tmp);
5466 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5467 } else {
5468 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5469 }
5470 }
5471
5472 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5473 if (UseCompactObjectHeaders) {
5474 assert(tmp != noreg, "need tmp");
5475 assert_different_registers(klass, obj, tmp);
5476 load_narrow_klass_compact(tmp, obj);
5477 cmpl(klass, tmp);
5478 } else if (UseCompressedClassPointers) {
5479 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5480 } else {
5481 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5482 }
5483 }
5484
5485 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5486 if (UseCompactObjectHeaders) {
5487 assert(tmp2 != noreg, "need tmp2");
5488 assert_different_registers(obj1, obj2, tmp1, tmp2);
5489 load_narrow_klass_compact(tmp1, obj1);
5490 load_narrow_klass_compact(tmp2, obj2);
5491 cmpl(tmp1, tmp2);
5492 } else if (UseCompressedClassPointers) {
5493 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5494 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5495 } else {
5496 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5497 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5498 }
5499 }
5500
5501 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5502 Register tmp1) {
5503 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5504 decorators = AccessInternal::decorator_fixup(decorators, type);
5505 bool as_raw = (decorators & AS_RAW) != 0;
5506 if (as_raw) {
5507 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1);
5508 } else {
5509 bs->load_at(this, decorators, type, dst, src, tmp1);
5510 }
5511 }
5512
5513 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5514 Register tmp1, Register tmp2, Register tmp3) {
5515 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5516 decorators = AccessInternal::decorator_fixup(decorators, type);
5517 bool as_raw = (decorators & AS_RAW) != 0;
5518 if (as_raw) {
5519 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5520 } else {
5521 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5522 }
5523 }
5524
5525 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5526 Register inline_layout_info) {
5527 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5528 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5529 }
5530
5531 void MacroAssembler::payload_offset(Register inline_klass, Register offset) {
5532 movptr(offset, Address(inline_klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
5533 movl(offset, Address(offset, InlineKlass::payload_offset_offset()));
5534 }
5535
5536 void MacroAssembler::payload_addr(Register oop, Register data, Register inline_klass) {
5537 // ((address) (void*) o) + vk->payload_offset();
5538 Register offset = (data == oop) ? rscratch1 : data;
5539 payload_offset(inline_klass, offset);
5540 if (data == oop) {
5541 addptr(data, offset);
5542 } else {
5543 lea(data, Address(oop, offset));
5544 }
5545 }
5546
5547 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
5548 Register index, Register data) {
5549 assert(index != rcx, "index needs to shift by rcx");
5550 assert_different_registers(array, array_klass, index);
5551 assert_different_registers(rcx, array, index);
5552
5553 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
5554 movl(rcx, Address(array_klass, Klass::layout_helper_offset()));
5555
5556 // Klass::layout_helper_log2_element_size(lh)
5557 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
5558 shrl(rcx, Klass::_lh_log2_element_size_shift);
5559 andl(rcx, Klass::_lh_log2_element_size_mask);
5560 shlptr(index); // index << rcx
5561
5562 lea(data, Address(array, index, Address::times_1, arrayOopDesc::base_offset_in_bytes(T_FLAT_ELEMENT)));
5563 }
5564
5565 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5566 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1);
5567 }
5568
5569 // Doesn't do verification, generates fixed size code
5570 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5571 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1);
5572 }
5573
5574 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5575 Register tmp2, Register tmp3, DecoratorSet decorators) {
5576 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5577 }
5578
5579 // Used for storing nulls.
5580 void MacroAssembler::store_heap_oop_null(Address dst) {
5581 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5582 }
5583
5584 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5585 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5586 if (UseCompressedClassPointers) {
5587 // Store to klass gap in destination
5588 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5589 }
5590 }
5591
5592 #ifdef ASSERT
5593 void MacroAssembler::verify_heapbase(const char* msg) {
5594 assert (UseCompressedOops, "should be compressed");
5595 assert (Universe::heap() != nullptr, "java heap should be initialized");
5596 if (CheckCompressedOops) {
5597 Label ok;
5598 ExternalAddress src2(CompressedOops::base_addr());
5599 const bool is_src2_reachable = reachable(src2);
5600 if (!is_src2_reachable) {
5601 push(rscratch1); // cmpptr trashes rscratch1
5602 }
5603 cmpptr(r12_heapbase, src2, rscratch1);
5604 jcc(Assembler::equal, ok);
5605 STOP(msg);
5606 bind(ok);
5607 if (!is_src2_reachable) {
5608 pop(rscratch1);
5609 }
5610 }
5611 }
5612 #endif
5613
5614 // Algorithm must match oop.inline.hpp encode_heap_oop.
5615 void MacroAssembler::encode_heap_oop(Register r) {
5616 #ifdef ASSERT
5617 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5618 #endif
5619 verify_oop_msg(r, "broken oop in encode_heap_oop");
5620 if (CompressedOops::base() == nullptr) {
5621 if (CompressedOops::shift() != 0) {
5622 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5623 shrq(r, LogMinObjAlignmentInBytes);
5624 }
5625 return;
5626 }
5627 testq(r, r);
5628 cmovq(Assembler::equal, r, r12_heapbase);
5629 subq(r, r12_heapbase);
5630 shrq(r, LogMinObjAlignmentInBytes);
5631 }
5632
5633 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5634 #ifdef ASSERT
5635 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5636 if (CheckCompressedOops) {
5637 Label ok;
5638 testq(r, r);
5639 jcc(Assembler::notEqual, ok);
5640 STOP("null oop passed to encode_heap_oop_not_null");
5641 bind(ok);
5642 }
5643 #endif
5644 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5645 if (CompressedOops::base() != nullptr) {
5646 subq(r, r12_heapbase);
5647 }
5648 if (CompressedOops::shift() != 0) {
5649 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5650 shrq(r, LogMinObjAlignmentInBytes);
5651 }
5652 }
5653
5654 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5655 #ifdef ASSERT
5656 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5657 if (CheckCompressedOops) {
5658 Label ok;
5659 testq(src, src);
5660 jcc(Assembler::notEqual, ok);
5661 STOP("null oop passed to encode_heap_oop_not_null2");
5662 bind(ok);
5663 }
5664 #endif
5665 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5666 if (dst != src) {
5667 movq(dst, src);
5668 }
5669 if (CompressedOops::base() != nullptr) {
5670 subq(dst, r12_heapbase);
5671 }
5672 if (CompressedOops::shift() != 0) {
5673 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5674 shrq(dst, LogMinObjAlignmentInBytes);
5675 }
5676 }
5677
5678 void MacroAssembler::decode_heap_oop(Register r) {
5679 #ifdef ASSERT
5680 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5681 #endif
5682 if (CompressedOops::base() == nullptr) {
5683 if (CompressedOops::shift() != 0) {
5684 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5685 shlq(r, LogMinObjAlignmentInBytes);
5686 }
5687 } else {
5688 Label done;
5689 shlq(r, LogMinObjAlignmentInBytes);
5690 jccb(Assembler::equal, done);
5691 addq(r, r12_heapbase);
5692 bind(done);
5693 }
5694 verify_oop_msg(r, "broken oop in decode_heap_oop");
5695 }
5696
5697 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5698 // Note: it will change flags
5699 assert (UseCompressedOops, "should only be used for compressed headers");
5700 assert (Universe::heap() != nullptr, "java heap should be initialized");
5701 // Cannot assert, unverified entry point counts instructions (see .ad file)
5702 // vtableStubs also counts instructions in pd_code_size_limit.
5703 // Also do not verify_oop as this is called by verify_oop.
5704 if (CompressedOops::shift() != 0) {
5705 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5706 shlq(r, LogMinObjAlignmentInBytes);
5707 if (CompressedOops::base() != nullptr) {
5708 addq(r, r12_heapbase);
5709 }
5710 } else {
5711 assert (CompressedOops::base() == nullptr, "sanity");
5712 }
5713 }
5714
5715 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5716 // Note: it will change flags
5717 assert (UseCompressedOops, "should only be used for compressed headers");
5718 assert (Universe::heap() != nullptr, "java heap should be initialized");
5719 // Cannot assert, unverified entry point counts instructions (see .ad file)
5720 // vtableStubs also counts instructions in pd_code_size_limit.
5721 // Also do not verify_oop as this is called by verify_oop.
5722 if (CompressedOops::shift() != 0) {
5723 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5724 if (LogMinObjAlignmentInBytes == Address::times_8) {
5725 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5726 } else {
5727 if (dst != src) {
5728 movq(dst, src);
5729 }
5730 shlq(dst, LogMinObjAlignmentInBytes);
5731 if (CompressedOops::base() != nullptr) {
5732 addq(dst, r12_heapbase);
5733 }
5734 }
5735 } else {
5736 assert (CompressedOops::base() == nullptr, "sanity");
5737 if (dst != src) {
5738 movq(dst, src);
5739 }
5740 }
5741 }
5742
5743 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5744 BLOCK_COMMENT("encode_klass_not_null {");
5745 assert_different_registers(r, tmp);
5746 if (CompressedKlassPointers::base() != nullptr) {
5747 if (AOTCodeCache::is_on_for_dump()) {
5748 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5749 } else {
5750 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5751 }
5752 subq(r, tmp);
5753 }
5754 if (CompressedKlassPointers::shift() != 0) {
5755 shrq(r, CompressedKlassPointers::shift());
5756 }
5757 BLOCK_COMMENT("} encode_klass_not_null");
5758 }
5759
5760 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5761 BLOCK_COMMENT("encode_and_move_klass_not_null {");
5762 assert_different_registers(src, dst);
5763 if (CompressedKlassPointers::base() != nullptr) {
5764 movptr(dst, -(intptr_t)CompressedKlassPointers::base());
5765 addq(dst, src);
5766 } else {
5767 movptr(dst, src);
5768 }
5769 if (CompressedKlassPointers::shift() != 0) {
5770 shrq(dst, CompressedKlassPointers::shift());
5771 }
5772 BLOCK_COMMENT("} encode_and_move_klass_not_null");
5773 }
5774
5775 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5776 BLOCK_COMMENT("decode_klass_not_null {");
5777 assert_different_registers(r, tmp);
5778 // Note: it will change flags
5779 assert(UseCompressedClassPointers, "should only be used for compressed headers");
5780 // Cannot assert, unverified entry point counts instructions (see .ad file)
5781 // vtableStubs also counts instructions in pd_code_size_limit.
5782 // Also do not verify_oop as this is called by verify_oop.
5783 if (CompressedKlassPointers::shift() != 0) {
5784 shlq(r, CompressedKlassPointers::shift());
5785 }
5786 if (CompressedKlassPointers::base() != nullptr) {
5787 if (AOTCodeCache::is_on_for_dump()) {
5788 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5789 } else {
5790 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5791 }
5792 addq(r, tmp);
5793 }
5794 BLOCK_COMMENT("} decode_klass_not_null");
5795 }
5796
5797 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5798 BLOCK_COMMENT("decode_and_move_klass_not_null {");
5799 assert_different_registers(src, dst);
5800 // Note: it will change flags
5801 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5802 // Cannot assert, unverified entry point counts instructions (see .ad file)
5803 // vtableStubs also counts instructions in pd_code_size_limit.
5804 // Also do not verify_oop as this is called by verify_oop.
5805
5806 if (CompressedKlassPointers::base() == nullptr &&
5807 CompressedKlassPointers::shift() == 0) {
5808 // The best case scenario is that there is no base or shift. Then it is already
5809 // a pointer that needs nothing but a register rename.
5810 movl(dst, src);
5811 } else {
5812 if (CompressedKlassPointers::shift() <= Address::times_8) {
5813 if (CompressedKlassPointers::base() != nullptr) {
5814 movptr(dst, (intptr_t)CompressedKlassPointers::base());
5815 } else {
5816 xorq(dst, dst);
5817 }
5818 if (CompressedKlassPointers::shift() != 0) {
5819 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
5820 leaq(dst, Address(dst, src, Address::times_8, 0));
5821 } else {
5822 addq(dst, src);
5823 }
5824 } else {
5825 if (CompressedKlassPointers::base() != nullptr) {
5826 const intptr_t base_right_shifted =
5827 (intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5828 movptr(dst, base_right_shifted);
5829 } else {
5830 xorq(dst, dst);
5831 }
5832 addq(dst, src);
5833 shlq(dst, CompressedKlassPointers::shift());
5834 }
5835 }
5836 BLOCK_COMMENT("} decode_and_move_klass_not_null");
5837 }
5838
5839 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5840 assert (UseCompressedOops, "should only be used for compressed headers");
5841 assert (Universe::heap() != nullptr, "java heap should be initialized");
5842 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5843 int oop_index = oop_recorder()->find_index(obj);
5844 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5845 mov_narrow_oop(dst, oop_index, rspec);
5846 }
5847
5848 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5849 assert (UseCompressedOops, "should only be used for compressed headers");
5850 assert (Universe::heap() != nullptr, "java heap should be initialized");
5851 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5852 int oop_index = oop_recorder()->find_index(obj);
5853 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5854 mov_narrow_oop(dst, oop_index, rspec);
5855 }
5856
5857 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5858 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5859 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5860 int klass_index = oop_recorder()->find_index(k);
5861 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5862 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5863 }
5864
5865 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5866 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5867 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5868 int klass_index = oop_recorder()->find_index(k);
5869 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5870 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5871 }
5872
5873 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5874 assert (UseCompressedOops, "should only be used for compressed headers");
5875 assert (Universe::heap() != nullptr, "java heap should be initialized");
5876 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5877 int oop_index = oop_recorder()->find_index(obj);
5878 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5879 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5880 }
5881
5882 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5883 assert (UseCompressedOops, "should only be used for compressed headers");
5884 assert (Universe::heap() != nullptr, "java heap should be initialized");
5885 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5886 int oop_index = oop_recorder()->find_index(obj);
5887 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5888 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5889 }
5890
5891 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5892 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5893 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5894 int klass_index = oop_recorder()->find_index(k);
5895 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5896 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5897 }
5898
5899 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5900 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5901 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5902 int klass_index = oop_recorder()->find_index(k);
5903 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5904 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5905 }
5906
5907 void MacroAssembler::reinit_heapbase() {
5908 if (UseCompressedOops) {
5909 if (Universe::heap() != nullptr) {
5910 if (CompressedOops::base() == nullptr) {
5911 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5912 } else {
5913 mov64(r12_heapbase, (int64_t)CompressedOops::base());
5914 }
5915 } else {
5916 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
5917 }
5918 }
5919 }
5920
5921 #if COMPILER2_OR_JVMCI
5922
5923 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
5924 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
5925 // cnt - number of qwords (8-byte words).
5926 // base - start address, qword aligned.
5927 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5928 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
5929 if (use64byteVector) {
5930 evpbroadcastq(xtmp, val, AVX_512bit);
5931 } else if (MaxVectorSize >= 32) {
5932 movdq(xtmp, val);
5933 punpcklqdq(xtmp, xtmp);
5934 vinserti128_high(xtmp, xtmp);
5935 } else {
5936 movdq(xtmp, val);
5937 punpcklqdq(xtmp, xtmp);
5938 }
5939 jmp(L_zero_64_bytes);
5940
5941 BIND(L_loop);
5942 if (MaxVectorSize >= 32) {
5943 fill64(base, 0, xtmp, use64byteVector);
5944 } else {
5945 movdqu(Address(base, 0), xtmp);
5946 movdqu(Address(base, 16), xtmp);
5947 movdqu(Address(base, 32), xtmp);
5948 movdqu(Address(base, 48), xtmp);
5949 }
5950 addptr(base, 64);
5951
5952 BIND(L_zero_64_bytes);
5953 subptr(cnt, 8);
5954 jccb(Assembler::greaterEqual, L_loop);
5955
5956 // Copy trailing 64 bytes
5957 if (use64byteVector) {
5958 addptr(cnt, 8);
5959 jccb(Assembler::equal, L_end);
5960 fill64_masked(3, base, 0, xtmp, mask, cnt, val, true);
5961 jmp(L_end);
5962 } else {
5963 addptr(cnt, 4);
5964 jccb(Assembler::less, L_tail);
5965 if (MaxVectorSize >= 32) {
5966 vmovdqu(Address(base, 0), xtmp);
5967 } else {
5968 movdqu(Address(base, 0), xtmp);
5969 movdqu(Address(base, 16), xtmp);
5970 }
5971 }
5972 addptr(base, 32);
5973 subptr(cnt, 4);
5974
5975 BIND(L_tail);
5976 addptr(cnt, 4);
5977 jccb(Assembler::lessEqual, L_end);
5978 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
5979 fill32_masked(3, base, 0, xtmp, mask, cnt, val);
5980 } else {
5981 decrement(cnt);
5982
5983 BIND(L_sloop);
5984 movq(Address(base, 0), xtmp);
5985 addptr(base, 8);
5986 decrement(cnt);
5987 jccb(Assembler::greaterEqual, L_sloop);
5988 }
5989 BIND(L_end);
5990 }
5991
5992 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
5993 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
5994 // An inline type might be returned. If fields are in registers we
5995 // need to allocate an inline type instance and initialize it with
5996 // the value of the fields.
5997 Label skip;
5998 // We only need a new buffered inline type if a new one is not returned
5999 testptr(rax, 1);
6000 jcc(Assembler::zero, skip);
6001 int call_offset = -1;
6002
6003 #ifdef _LP64
6004 // The following code is similar to allocate_instance but has some slight differences,
6005 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6006 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
6007 Label slow_case;
6008 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6009 mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
6010 if (vk != nullptr) {
6011 // Called from C1, where the return type is statically known.
6012 movptr(rbx, (intptr_t)vk->get_InlineKlass());
6013 jint lh = vk->layout_helper();
6014 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6015 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6016 tlab_allocate(rax, noreg, lh, r13, r14, slow_case);
6017 } else {
6018 jmp(slow_case);
6019 }
6020 } else {
6021 // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
6022 mov(rbx, rax);
6023 andptr(rbx, -2);
6024 if (UseTLAB) {
6025 movl(r14, Address(rbx, Klass::layout_helper_offset()));
6026 testl(r14, Klass::_lh_instance_slow_path_bit);
6027 jcc(Assembler::notZero, slow_case);
6028 tlab_allocate(rax, r14, 0, r13, r14, slow_case);
6029 } else {
6030 jmp(slow_case);
6031 }
6032 }
6033 if (UseTLAB) {
6034 // 2. Initialize buffered inline instance header
6035 Register buffer_obj = rax;
6036 Register klass = rbx;
6037 if (UseCompactObjectHeaders) {
6038 Register mark_word = r13;
6039 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
6040 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), mark_word);
6041 } else {
6042 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
6043 xorl(r13, r13);
6044 store_klass_gap(buffer_obj, r13);
6045 if (vk == nullptr) {
6046 // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
6047 mov(r13, klass);
6048 }
6049 store_klass(buffer_obj, klass, rscratch1);
6050 klass = r13;
6051 }
6052 // 3. Initialize its fields with an inline class specific handler
6053 if (vk != nullptr) {
6054 call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6055 } else {
6056 movptr(rbx, Address(klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
6057 movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
6058 call(rbx);
6059 }
6060 jmp(skip);
6061 }
6062 bind(slow_case);
6063 // We failed to allocate a new inline type, fall back to a runtime
6064 // call. Some oop field may be live in some registers but we can't
6065 // tell. That runtime call will take care of preserving them
6066 // across a GC if there's one.
6067 mov(rax, rscratch1);
6068 #endif
6069
6070 if (from_interpreter) {
6071 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6072 } else {
6073 call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6074 call_offset = offset();
6075 }
6076
6077 bind(skip);
6078 return call_offset;
6079 }
6080
6081 // Move a value between registers/stack slots and update the reg_state
6082 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6083 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6084 if (reg_state[to->value()] == reg_written) {
6085 return true; // Already written
6086 }
6087 if (from != to && bt != T_VOID) {
6088 if (reg_state[to->value()] == reg_readonly) {
6089 return false; // Not yet writable
6090 }
6091 if (from->is_reg()) {
6092 if (to->is_reg()) {
6093 if (from->is_XMMRegister()) {
6094 if (bt == T_DOUBLE) {
6095 movdbl(to->as_XMMRegister(), from->as_XMMRegister());
6096 } else {
6097 assert(bt == T_FLOAT, "must be float");
6098 movflt(to->as_XMMRegister(), from->as_XMMRegister());
6099 }
6100 } else {
6101 movq(to->as_Register(), from->as_Register());
6102 }
6103 } else {
6104 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6105 Address to_addr = Address(rsp, st_off);
6106 if (from->is_XMMRegister()) {
6107 if (bt == T_DOUBLE) {
6108 movdbl(to_addr, from->as_XMMRegister());
6109 } else {
6110 assert(bt == T_FLOAT, "must be float");
6111 movflt(to_addr, from->as_XMMRegister());
6112 }
6113 } else {
6114 movq(to_addr, from->as_Register());
6115 }
6116 }
6117 } else {
6118 Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
6119 if (to->is_reg()) {
6120 if (to->is_XMMRegister()) {
6121 if (bt == T_DOUBLE) {
6122 movdbl(to->as_XMMRegister(), from_addr);
6123 } else {
6124 assert(bt == T_FLOAT, "must be float");
6125 movflt(to->as_XMMRegister(), from_addr);
6126 }
6127 } else {
6128 movq(to->as_Register(), from_addr);
6129 }
6130 } else {
6131 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6132 movq(r13, from_addr);
6133 movq(Address(rsp, st_off), r13);
6134 }
6135 }
6136 }
6137 // Update register states
6138 reg_state[from->value()] = reg_writable;
6139 reg_state[to->value()] = reg_written;
6140 return true;
6141 }
6142
6143 // Calculate the extra stack space required for packing or unpacking inline
6144 // args and adjust the stack pointer
6145 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6146 // Two additional slots to account for return address
6147 int sp_inc = (args_on_stack + 2) * VMRegImpl::stack_slot_size;
6148 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6149 // Save the return address, adjust the stack (make sure it is properly
6150 // 16-byte aligned) and copy the return address to the new top of the stack.
6151 // The stack will be repaired on return (see MacroAssembler::remove_frame).
6152 assert(sp_inc > 0, "sanity");
6153 pop(r13);
6154 subptr(rsp, sp_inc);
6155 push(r13);
6156 return sp_inc;
6157 }
6158
6159 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
6160 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6161 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6162 RegState reg_state[]) {
6163 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6164 assert(from->is_valid(), "source must be valid");
6165 bool progress = false;
6166 #ifdef ASSERT
6167 const int start_offset = offset();
6168 #endif
6169
6170 Label L_null, L_notNull;
6171 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6172 Register tmp1 = r10;
6173 Register tmp2 = r13;
6174 Register fromReg = noreg;
6175 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
6176 bool done = true;
6177 bool mark_done = true;
6178 VMReg toReg;
6179 BasicType bt;
6180 // Check if argument requires a null check
6181 bool null_check = false;
6182 VMReg nullCheckReg;
6183 while (stream.next(nullCheckReg, bt)) {
6184 if (sig->at(stream.sig_index())._offset == -1) {
6185 null_check = true;
6186 break;
6187 }
6188 }
6189 stream.reset(sig_index, to_index);
6190 while (stream.next(toReg, bt)) {
6191 assert(toReg->is_valid(), "destination must be valid");
6192 int idx = (int)toReg->value();
6193 if (reg_state[idx] == reg_readonly) {
6194 if (idx != from->value()) {
6195 mark_done = false;
6196 }
6197 done = false;
6198 continue;
6199 } else if (reg_state[idx] == reg_written) {
6200 continue;
6201 }
6202 assert(reg_state[idx] == reg_writable, "must be writable");
6203 reg_state[idx] = reg_written;
6204 progress = true;
6205
6206 if (fromReg == noreg) {
6207 if (from->is_reg()) {
6208 fromReg = from->as_Register();
6209 } else {
6210 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6211 movq(tmp1, Address(rsp, st_off));
6212 fromReg = tmp1;
6213 }
6214 if (null_check) {
6215 // Nullable inline type argument, emit null check
6216 testptr(fromReg, fromReg);
6217 jcc(Assembler::zero, L_null);
6218 }
6219 }
6220 int off = sig->at(stream.sig_index())._offset;
6221 if (off == -1) {
6222 assert(null_check, "Missing null check at");
6223 if (toReg->is_stack()) {
6224 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6225 movq(Address(rsp, st_off), 1);
6226 } else {
6227 movq(toReg->as_Register(), 1);
6228 }
6229 continue;
6230 }
6231 assert(off > 0, "offset in object should be positive");
6232 Address fromAddr = Address(fromReg, off);
6233 if (!toReg->is_XMMRegister()) {
6234 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
6235 if (is_reference_type(bt)) {
6236 load_heap_oop(dst, fromAddr);
6237 } else {
6238 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
6239 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
6240 }
6241 if (toReg->is_stack()) {
6242 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6243 movq(Address(rsp, st_off), dst);
6244 }
6245 } else if (bt == T_DOUBLE) {
6246 movdbl(toReg->as_XMMRegister(), fromAddr);
6247 } else {
6248 assert(bt == T_FLOAT, "must be float");
6249 movflt(toReg->as_XMMRegister(), fromAddr);
6250 }
6251 }
6252 if (progress && null_check) {
6253 if (done) {
6254 jmp(L_notNull);
6255 bind(L_null);
6256 // Set null marker to zero to signal that the argument is null.
6257 // Also set all oop fields to zero to make the GC happy.
6258 stream.reset(sig_index, to_index);
6259 while (stream.next(toReg, bt)) {
6260 if (sig->at(stream.sig_index())._offset == -1 ||
6261 bt == T_OBJECT || bt == T_ARRAY) {
6262 if (toReg->is_stack()) {
6263 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6264 movq(Address(rsp, st_off), 0);
6265 } else {
6266 xorq(toReg->as_Register(), toReg->as_Register());
6267 }
6268 }
6269 }
6270 bind(L_notNull);
6271 } else {
6272 bind(L_null);
6273 }
6274 }
6275
6276 sig_index = stream.sig_index();
6277 to_index = stream.regs_index();
6278
6279 if (mark_done && reg_state[from->value()] != reg_written) {
6280 // This is okay because no one else will write to that slot
6281 reg_state[from->value()] = reg_writable;
6282 }
6283 from_index--;
6284 assert(progress || (start_offset == offset()), "should not emit code");
6285 return done;
6286 }
6287
6288 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
6289 VMRegPair* from, int from_count, int& from_index, VMReg to,
6290 RegState reg_state[], Register val_array) {
6291 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
6292 assert(to->is_valid(), "destination must be valid");
6293
6294 if (reg_state[to->value()] == reg_written) {
6295 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6296 return true; // Already written
6297 }
6298
6299 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
6300 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
6301 Register val_obj_tmp = r11;
6302 Register from_reg_tmp = r14;
6303 Register tmp1 = r10;
6304 Register tmp2 = r13;
6305 Register tmp3 = rbx;
6306 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
6307
6308 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
6309
6310 if (reg_state[to->value()] == reg_readonly) {
6311 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
6312 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6313 return false; // Not yet writable
6314 }
6315 val_obj = val_obj_tmp;
6316 }
6317
6318 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
6319 load_heap_oop(val_obj, Address(val_array, index));
6320
6321 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
6322 VMReg fromReg;
6323 BasicType bt;
6324 Label L_null;
6325 while (stream.next(fromReg, bt)) {
6326 assert(fromReg->is_valid(), "source must be valid");
6327 reg_state[fromReg->value()] = reg_writable;
6328
6329 int off = sig->at(stream.sig_index())._offset;
6330 if (off == -1) {
6331 // Nullable inline type argument, emit null check
6332 Label L_notNull;
6333 if (fromReg->is_stack()) {
6334 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6335 testb(Address(rsp, ld_off), 1);
6336 } else {
6337 testb(fromReg->as_Register(), 1);
6338 }
6339 jcc(Assembler::notZero, L_notNull);
6340 movptr(val_obj, 0);
6341 jmp(L_null);
6342 bind(L_notNull);
6343 continue;
6344 }
6345
6346 assert(off > 0, "offset in object should be positive");
6347 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
6348
6349 // Pack the scalarized field into the value object.
6350 Address dst(val_obj, off);
6351 if (!fromReg->is_XMMRegister()) {
6352 Register src;
6353 if (fromReg->is_stack()) {
6354 src = from_reg_tmp;
6355 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6356 load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
6357 } else {
6358 src = fromReg->as_Register();
6359 }
6360 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
6361 if (is_reference_type(bt)) {
6362 store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
6363 } else {
6364 store_sized_value(dst, src, size_in_bytes);
6365 }
6366 } else if (bt == T_DOUBLE) {
6367 movdbl(dst, fromReg->as_XMMRegister());
6368 } else {
6369 assert(bt == T_FLOAT, "must be float");
6370 movflt(dst, fromReg->as_XMMRegister());
6371 }
6372 }
6373 bind(L_null);
6374 sig_index = stream.sig_index();
6375 from_index = stream.regs_index();
6376
6377 assert(reg_state[to->value()] == reg_writable, "must have already been read");
6378 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6379 assert(success, "to register must be writeable");
6380 return true;
6381 }
6382
6383 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6384 return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
6385 }
6386
6387 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
6388 assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6389 if (needs_stack_repair) {
6390 // TODO 8284443 Add a comment drawing the frame like in Aarch64's version of MacroAssembler::remove_frame
6391 movq(rbp, Address(rsp, initial_framesize));
6392 // The stack increment resides just below the saved rbp
6393 addq(rsp, Address(rsp, initial_framesize - wordSize));
6394 } else {
6395 if (initial_framesize > 0) {
6396 addq(rsp, initial_framesize);
6397 }
6398 pop(rbp);
6399 }
6400 }
6401
6402 // Clearing constant sized memory using YMM/ZMM registers.
6403 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6404 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6405 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6406
6407 int vector64_count = (cnt & (~0x7)) >> 3;
6408 cnt = cnt & 0x7;
6409 const int fill64_per_loop = 4;
6410 const int max_unrolled_fill64 = 8;
6411
6412 // 64 byte initialization loop.
6413 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6414 int start64 = 0;
6415 if (vector64_count > max_unrolled_fill64) {
6416 Label LOOP;
6417 Register index = rtmp;
6418
6419 start64 = vector64_count - (vector64_count % fill64_per_loop);
6420
6421 movl(index, 0);
6422 BIND(LOOP);
6423 for (int i = 0; i < fill64_per_loop; i++) {
6424 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6425 }
6426 addl(index, fill64_per_loop * 64);
6427 cmpl(index, start64 * 64);
6428 jccb(Assembler::less, LOOP);
6429 }
6430 for (int i = start64; i < vector64_count; i++) {
6431 fill64(base, i * 64, xtmp, use64byteVector);
6432 }
6433
6434 // Clear remaining 64 byte tail.
6435 int disp = vector64_count * 64;
6436 if (cnt) {
6437 switch (cnt) {
6438 case 1:
6439 movq(Address(base, disp), xtmp);
6440 break;
6441 case 2:
6442 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6443 break;
6444 case 3:
6445 movl(rtmp, 0x7);
6446 kmovwl(mask, rtmp);
6447 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6448 break;
6449 case 4:
6450 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6451 break;
6452 case 5:
6453 if (use64byteVector) {
6454 movl(rtmp, 0x1F);
6455 kmovwl(mask, rtmp);
6456 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6457 } else {
6458 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6459 movq(Address(base, disp + 32), xtmp);
6460 }
6461 break;
6462 case 6:
6463 if (use64byteVector) {
6464 movl(rtmp, 0x3F);
6465 kmovwl(mask, rtmp);
6466 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6467 } else {
6468 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6469 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6470 }
6471 break;
6472 case 7:
6473 if (use64byteVector) {
6474 movl(rtmp, 0x7F);
6475 kmovwl(mask, rtmp);
6476 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6477 } else {
6478 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6479 movl(rtmp, 0x7);
6480 kmovwl(mask, rtmp);
6481 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6482 }
6483 break;
6484 default:
6485 fatal("Unexpected length : %d\n",cnt);
6486 break;
6487 }
6488 }
6489 }
6490
6491 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
6492 bool is_large, bool word_copy_only, KRegister mask) {
6493 // cnt - number of qwords (8-byte words).
6494 // base - start address, qword aligned.
6495 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6496 assert(base==rdi, "base register must be edi for rep stos");
6497 assert(val==rax, "val register must be eax for rep stos");
6498 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6499 assert(InitArrayShortSize % BytesPerLong == 0,
6500 "InitArrayShortSize should be the multiple of BytesPerLong");
6501
6502 Label DONE;
6503
6504 if (!is_large) {
6505 Label LOOP, LONG;
6506 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6507 jccb(Assembler::greater, LONG);
6508
6509 decrement(cnt);
6510 jccb(Assembler::negative, DONE); // Zero length
6511
6512 // Use individual pointer-sized stores for small counts:
6513 BIND(LOOP);
6514 movptr(Address(base, cnt, Address::times_ptr), val);
6515 decrement(cnt);
6516 jccb(Assembler::greaterEqual, LOOP);
6517 jmpb(DONE);
6518
6519 BIND(LONG);
6520 }
6521
6522 // Use longer rep-prefixed ops for non-small counts:
6523 if (UseFastStosb && !word_copy_only) {
6524 shlptr(cnt, 3); // convert to number of bytes
6525 rep_stosb();
6526 } else if (UseXMMForObjInit) {
6527 xmm_clear_mem(base, cnt, val, xtmp, mask);
6528 } else {
6529 rep_stos();
6530 }
6531
6532 BIND(DONE);
6533 }
6534
6535 #endif //COMPILER2_OR_JVMCI
6536
6537
6538 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6539 Register to, Register value, Register count,
6540 Register rtmp, XMMRegister xtmp) {
6541 ShortBranchVerifier sbv(this);
6542 assert_different_registers(to, value, count, rtmp);
6543 Label L_exit;
6544 Label L_fill_2_bytes, L_fill_4_bytes;
6545
6546 #if defined(COMPILER2)
6547 if(MaxVectorSize >=32 &&
6548 VM_Version::supports_avx512vlbw() &&
6549 VM_Version::supports_bmi2()) {
6550 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6551 return;
6552 }
6553 #endif
6554
6555 int shift = -1;
6556 switch (t) {
6557 case T_BYTE:
6558 shift = 2;
6559 break;
6560 case T_SHORT:
6561 shift = 1;
6562 break;
6563 case T_INT:
6564 shift = 0;
6565 break;
6566 default: ShouldNotReachHere();
6567 }
6568
6569 if (t == T_BYTE) {
6570 andl(value, 0xff);
6571 movl(rtmp, value);
6572 shll(rtmp, 8);
6573 orl(value, rtmp);
6574 }
6575 if (t == T_SHORT) {
6576 andl(value, 0xffff);
6577 }
6578 if (t == T_BYTE || t == T_SHORT) {
6579 movl(rtmp, value);
6580 shll(rtmp, 16);
6581 orl(value, rtmp);
6582 }
6583
6584 cmpptr(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6585 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6586 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6587 Label L_skip_align2;
6588 // align source address at 4 bytes address boundary
6589 if (t == T_BYTE) {
6590 Label L_skip_align1;
6591 // One byte misalignment happens only for byte arrays
6592 testptr(to, 1);
6593 jccb(Assembler::zero, L_skip_align1);
6594 movb(Address(to, 0), value);
6595 increment(to);
6596 decrement(count);
6597 BIND(L_skip_align1);
6598 }
6599 // Two bytes misalignment happens only for byte and short (char) arrays
6600 testptr(to, 2);
6601 jccb(Assembler::zero, L_skip_align2);
6602 movw(Address(to, 0), value);
6603 addptr(to, 2);
6604 subptr(count, 1<<(shift-1));
6605 BIND(L_skip_align2);
6606 }
6607 {
6608 Label L_fill_32_bytes;
6609 if (!UseUnalignedLoadStores) {
6610 // align to 8 bytes, we know we are 4 byte aligned to start
6611 testptr(to, 4);
6612 jccb(Assembler::zero, L_fill_32_bytes);
6613 movl(Address(to, 0), value);
6614 addptr(to, 4);
6615 subptr(count, 1<<shift);
6616 }
6617 BIND(L_fill_32_bytes);
6618 {
6619 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6620 movdl(xtmp, value);
6621 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6622 Label L_check_fill_32_bytes;
6623 if (UseAVX > 2) {
6624 // Fill 64-byte chunks
6625 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6626
6627 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6628 cmpptr(count, VM_Version::avx3_threshold());
6629 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6630
6631 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6632
6633 subptr(count, 16 << shift);
6634 jccb(Assembler::less, L_check_fill_32_bytes);
6635 align(16);
6636
6637 BIND(L_fill_64_bytes_loop_avx3);
6638 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6639 addptr(to, 64);
6640 subptr(count, 16 << shift);
6641 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6642 jmpb(L_check_fill_32_bytes);
6643
6644 BIND(L_check_fill_64_bytes_avx2);
6645 }
6646 // Fill 64-byte chunks
6647 Label L_fill_64_bytes_loop;
6648 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6649
6650 subptr(count, 16 << shift);
6651 jcc(Assembler::less, L_check_fill_32_bytes);
6652 align(16);
6653
6654 BIND(L_fill_64_bytes_loop);
6655 vmovdqu(Address(to, 0), xtmp);
6656 vmovdqu(Address(to, 32), xtmp);
6657 addptr(to, 64);
6658 subptr(count, 16 << shift);
6659 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6660
6661 BIND(L_check_fill_32_bytes);
6662 addptr(count, 8 << shift);
6663 jccb(Assembler::less, L_check_fill_8_bytes);
6664 vmovdqu(Address(to, 0), xtmp);
6665 addptr(to, 32);
6666 subptr(count, 8 << shift);
6667
6668 BIND(L_check_fill_8_bytes);
6669 // clean upper bits of YMM registers
6670 movdl(xtmp, value);
6671 pshufd(xtmp, xtmp, 0);
6672 } else {
6673 // Fill 32-byte chunks
6674 pshufd(xtmp, xtmp, 0);
6675
6676 subptr(count, 8 << shift);
6677 jcc(Assembler::less, L_check_fill_8_bytes);
6678 align(16);
6679
6680 BIND(L_fill_32_bytes_loop);
6681
6682 if (UseUnalignedLoadStores) {
6683 movdqu(Address(to, 0), xtmp);
6684 movdqu(Address(to, 16), xtmp);
6685 } else {
6686 movq(Address(to, 0), xtmp);
6687 movq(Address(to, 8), xtmp);
6688 movq(Address(to, 16), xtmp);
6689 movq(Address(to, 24), xtmp);
6690 }
6691
6692 addptr(to, 32);
6693 subptr(count, 8 << shift);
6694 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6695
6696 BIND(L_check_fill_8_bytes);
6697 }
6698 addptr(count, 8 << shift);
6699 jccb(Assembler::zero, L_exit);
6700 jmpb(L_fill_8_bytes);
6701
6702 //
6703 // length is too short, just fill qwords
6704 //
6705 BIND(L_fill_8_bytes_loop);
6706 movq(Address(to, 0), xtmp);
6707 addptr(to, 8);
6708 BIND(L_fill_8_bytes);
6709 subptr(count, 1 << (shift + 1));
6710 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6711 }
6712 }
6713 // fill trailing 4 bytes
6714 BIND(L_fill_4_bytes);
6715 testl(count, 1<<shift);
6716 jccb(Assembler::zero, L_fill_2_bytes);
6717 movl(Address(to, 0), value);
6718 if (t == T_BYTE || t == T_SHORT) {
6719 Label L_fill_byte;
6720 addptr(to, 4);
6721 BIND(L_fill_2_bytes);
6722 // fill trailing 2 bytes
6723 testl(count, 1<<(shift-1));
6724 jccb(Assembler::zero, L_fill_byte);
6725 movw(Address(to, 0), value);
6726 if (t == T_BYTE) {
6727 addptr(to, 2);
6728 BIND(L_fill_byte);
6729 // fill trailing byte
6730 testl(count, 1);
6731 jccb(Assembler::zero, L_exit);
6732 movb(Address(to, 0), value);
6733 } else {
6734 BIND(L_fill_byte);
6735 }
6736 } else {
6737 BIND(L_fill_2_bytes);
6738 }
6739 BIND(L_exit);
6740 }
6741
6742 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6743 switch(type) {
6744 case T_BYTE:
6745 case T_BOOLEAN:
6746 evpbroadcastb(dst, src, vector_len);
6747 break;
6748 case T_SHORT:
6749 case T_CHAR:
6750 evpbroadcastw(dst, src, vector_len);
6751 break;
6752 case T_INT:
6753 case T_FLOAT:
6754 evpbroadcastd(dst, src, vector_len);
6755 break;
6756 case T_LONG:
6757 case T_DOUBLE:
6758 evpbroadcastq(dst, src, vector_len);
6759 break;
6760 default:
6761 fatal("Unhandled type : %s", type2name(type));
6762 break;
6763 }
6764 }
6765
6766 // Encode given char[]/byte[] to byte[] in ISO_8859_1 or ASCII
6767 //
6768 // @IntrinsicCandidate
6769 // int sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(
6770 // char[] sa, int sp, byte[] da, int dp, int len) {
6771 // int i = 0;
6772 // for (; i < len; i++) {
6773 // char c = sa[sp++];
6774 // if (c > '\u00FF')
6775 // break;
6776 // da[dp++] = (byte) c;
6777 // }
6778 // return i;
6779 // }
6780 //
6781 // @IntrinsicCandidate
6782 // int java.lang.StringCoding.encodeISOArray0(
6783 // byte[] sa, int sp, byte[] da, int dp, int len) {
6784 // int i = 0;
6785 // for (; i < len; i++) {
6786 // char c = StringUTF16.getChar(sa, sp++);
6787 // if (c > '\u00FF')
6788 // break;
6789 // da[dp++] = (byte) c;
6790 // }
6791 // return i;
6792 // }
6793 //
6794 // @IntrinsicCandidate
6795 // int java.lang.StringCoding.encodeAsciiArray0(
6796 // char[] sa, int sp, byte[] da, int dp, int len) {
6797 // int i = 0;
6798 // for (; i < len; i++) {
6799 // char c = sa[sp++];
6800 // if (c >= '\u0080')
6801 // break;
6802 // da[dp++] = (byte) c;
6803 // }
6804 // return i;
6805 // }
6806 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6807 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6808 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6809 Register tmp5, Register result, bool ascii) {
6810
6811 // rsi: src
6812 // rdi: dst
6813 // rdx: len
6814 // rcx: tmp5
6815 // rax: result
6816 ShortBranchVerifier sbv(this);
6817 assert_different_registers(src, dst, len, tmp5, result);
6818 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6819
6820 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6821 int short_mask = ascii ? 0xff80 : 0xff00;
6822
6823 // set result
6824 xorl(result, result);
6825 // check for zero length
6826 testl(len, len);
6827 jcc(Assembler::zero, L_done);
6828
6829 movl(result, len);
6830
6831 // Setup pointers
6832 lea(src, Address(src, len, Address::times_2)); // char[]
6833 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6834 negptr(len);
6835
6836 if (UseSSE42Intrinsics || UseAVX >= 2) {
6837 Label L_copy_8_chars, L_copy_8_chars_exit;
6838 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6839
6840 if (UseAVX >= 2) {
6841 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6842 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6843 movdl(tmp1Reg, tmp5);
6844 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6845 jmp(L_chars_32_check);
6846
6847 bind(L_copy_32_chars);
6848 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6849 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6850 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6851 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6852 jccb(Assembler::notZero, L_copy_32_chars_exit);
6853 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6854 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6855 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6856
6857 bind(L_chars_32_check);
6858 addptr(len, 32);
6859 jcc(Assembler::lessEqual, L_copy_32_chars);
6860
6861 bind(L_copy_32_chars_exit);
6862 subptr(len, 16);
6863 jccb(Assembler::greater, L_copy_16_chars_exit);
6864
6865 } else if (UseSSE42Intrinsics) {
6866 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6867 movdl(tmp1Reg, tmp5);
6868 pshufd(tmp1Reg, tmp1Reg, 0);
6869 jmpb(L_chars_16_check);
6870 }
6871
6872 bind(L_copy_16_chars);
6873 if (UseAVX >= 2) {
6874 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6875 vptest(tmp2Reg, tmp1Reg);
6876 jcc(Assembler::notZero, L_copy_16_chars_exit);
6877 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6878 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6879 } else {
6880 if (UseAVX > 0) {
6881 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6882 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6883 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6884 } else {
6885 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6886 por(tmp2Reg, tmp3Reg);
6887 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6888 por(tmp2Reg, tmp4Reg);
6889 }
6890 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6891 jccb(Assembler::notZero, L_copy_16_chars_exit);
6892 packuswb(tmp3Reg, tmp4Reg);
6893 }
6894 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
6895
6896 bind(L_chars_16_check);
6897 addptr(len, 16);
6898 jcc(Assembler::lessEqual, L_copy_16_chars);
6899
6900 bind(L_copy_16_chars_exit);
6901 if (UseAVX >= 2) {
6902 // clean upper bits of YMM registers
6903 vpxor(tmp2Reg, tmp2Reg);
6904 vpxor(tmp3Reg, tmp3Reg);
6905 vpxor(tmp4Reg, tmp4Reg);
6906 movdl(tmp1Reg, tmp5);
6907 pshufd(tmp1Reg, tmp1Reg, 0);
6908 }
6909 subptr(len, 8);
6910 jccb(Assembler::greater, L_copy_8_chars_exit);
6911
6912 bind(L_copy_8_chars);
6913 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
6914 ptest(tmp3Reg, tmp1Reg);
6915 jccb(Assembler::notZero, L_copy_8_chars_exit);
6916 packuswb(tmp3Reg, tmp1Reg);
6917 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
6918 addptr(len, 8);
6919 jccb(Assembler::lessEqual, L_copy_8_chars);
6920
6921 bind(L_copy_8_chars_exit);
6922 subptr(len, 8);
6923 jccb(Assembler::zero, L_done);
6924 }
6925
6926 bind(L_copy_1_char);
6927 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
6928 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
6929 jccb(Assembler::notZero, L_copy_1_char_exit);
6930 movb(Address(dst, len, Address::times_1, 0), tmp5);
6931 addptr(len, 1);
6932 jccb(Assembler::less, L_copy_1_char);
6933
6934 bind(L_copy_1_char_exit);
6935 addptr(result, len); // len is negative count of not processed elements
6936
6937 bind(L_done);
6938 }
6939
6940 /**
6941 * Helper for multiply_to_len().
6942 */
6943 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
6944 addq(dest_lo, src1);
6945 adcq(dest_hi, 0);
6946 addq(dest_lo, src2);
6947 adcq(dest_hi, 0);
6948 }
6949
6950 /**
6951 * Multiply 64 bit by 64 bit first loop.
6952 */
6953 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
6954 Register y, Register y_idx, Register z,
6955 Register carry, Register product,
6956 Register idx, Register kdx) {
6957 //
6958 // jlong carry, x[], y[], z[];
6959 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6960 // huge_128 product = y[idx] * x[xstart] + carry;
6961 // z[kdx] = (jlong)product;
6962 // carry = (jlong)(product >>> 64);
6963 // }
6964 // z[xstart] = carry;
6965 //
6966
6967 Label L_first_loop, L_first_loop_exit;
6968 Label L_one_x, L_one_y, L_multiply;
6969
6970 decrementl(xstart);
6971 jcc(Assembler::negative, L_one_x);
6972
6973 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
6974 rorq(x_xstart, 32); // convert big-endian to little-endian
6975
6976 bind(L_first_loop);
6977 decrementl(idx);
6978 jcc(Assembler::negative, L_first_loop_exit);
6979 decrementl(idx);
6980 jcc(Assembler::negative, L_one_y);
6981 movq(y_idx, Address(y, idx, Address::times_4, 0));
6982 rorq(y_idx, 32); // convert big-endian to little-endian
6983 bind(L_multiply);
6984 movq(product, x_xstart);
6985 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
6986 addq(product, carry);
6987 adcq(rdx, 0);
6988 subl(kdx, 2);
6989 movl(Address(z, kdx, Address::times_4, 4), product);
6990 shrq(product, 32);
6991 movl(Address(z, kdx, Address::times_4, 0), product);
6992 movq(carry, rdx);
6993 jmp(L_first_loop);
6994
6995 bind(L_one_y);
6996 movl(y_idx, Address(y, 0));
6997 jmp(L_multiply);
6998
6999 bind(L_one_x);
7000 movl(x_xstart, Address(x, 0));
7001 jmp(L_first_loop);
7002
7003 bind(L_first_loop_exit);
7004 }
7005
7006 /**
7007 * Multiply 64 bit by 64 bit and add 128 bit.
7008 */
7009 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7010 Register yz_idx, Register idx,
7011 Register carry, Register product, int offset) {
7012 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7013 // z[kdx] = (jlong)product;
7014
7015 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7016 rorq(yz_idx, 32); // convert big-endian to little-endian
7017 movq(product, x_xstart);
7018 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7019 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7020 rorq(yz_idx, 32); // convert big-endian to little-endian
7021
7022 add2_with_carry(rdx, product, carry, yz_idx);
7023
7024 movl(Address(z, idx, Address::times_4, offset+4), product);
7025 shrq(product, 32);
7026 movl(Address(z, idx, Address::times_4, offset), product);
7027
7028 }
7029
7030 /**
7031 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7032 */
7033 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7034 Register yz_idx, Register idx, Register jdx,
7035 Register carry, Register product,
7036 Register carry2) {
7037 // jlong carry, x[], y[], z[];
7038 // int kdx = ystart+1;
7039 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7040 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7041 // z[kdx+idx+1] = (jlong)product;
7042 // jlong carry2 = (jlong)(product >>> 64);
7043 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7044 // z[kdx+idx] = (jlong)product;
7045 // carry = (jlong)(product >>> 64);
7046 // }
7047 // idx += 2;
7048 // if (idx > 0) {
7049 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7050 // z[kdx+idx] = (jlong)product;
7051 // carry = (jlong)(product >>> 64);
7052 // }
7053 //
7054
7055 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7056
7057 movl(jdx, idx);
7058 andl(jdx, 0xFFFFFFFC);
7059 shrl(jdx, 2);
7060
7061 bind(L_third_loop);
7062 subl(jdx, 1);
7063 jcc(Assembler::negative, L_third_loop_exit);
7064 subl(idx, 4);
7065
7066 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7067 movq(carry2, rdx);
7068
7069 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7070 movq(carry, rdx);
7071 jmp(L_third_loop);
7072
7073 bind (L_third_loop_exit);
7074
7075 andl (idx, 0x3);
7076 jcc(Assembler::zero, L_post_third_loop_done);
7077
7078 Label L_check_1;
7079 subl(idx, 2);
7080 jcc(Assembler::negative, L_check_1);
7081
7082 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7083 movq(carry, rdx);
7084
7085 bind (L_check_1);
7086 addl (idx, 0x2);
7087 andl (idx, 0x1);
7088 subl(idx, 1);
7089 jcc(Assembler::negative, L_post_third_loop_done);
7090
7091 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7092 movq(product, x_xstart);
7093 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7094 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7095
7096 add2_with_carry(rdx, product, yz_idx, carry);
7097
7098 movl(Address(z, idx, Address::times_4, 0), product);
7099 shrq(product, 32);
7100
7101 shlq(rdx, 32);
7102 orq(product, rdx);
7103 movq(carry, product);
7104
7105 bind(L_post_third_loop_done);
7106 }
7107
7108 /**
7109 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7110 *
7111 */
7112 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7113 Register carry, Register carry2,
7114 Register idx, Register jdx,
7115 Register yz_idx1, Register yz_idx2,
7116 Register tmp, Register tmp3, Register tmp4) {
7117 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7118
7119 // jlong carry, x[], y[], z[];
7120 // int kdx = ystart+1;
7121 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7122 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7123 // jlong carry2 = (jlong)(tmp3 >>> 64);
7124 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7125 // carry = (jlong)(tmp4 >>> 64);
7126 // z[kdx+idx+1] = (jlong)tmp3;
7127 // z[kdx+idx] = (jlong)tmp4;
7128 // }
7129 // idx += 2;
7130 // if (idx > 0) {
7131 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7132 // z[kdx+idx] = (jlong)yz_idx1;
7133 // carry = (jlong)(yz_idx1 >>> 64);
7134 // }
7135 //
7136
7137 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7138
7139 movl(jdx, idx);
7140 andl(jdx, 0xFFFFFFFC);
7141 shrl(jdx, 2);
7142
7143 bind(L_third_loop);
7144 subl(jdx, 1);
7145 jcc(Assembler::negative, L_third_loop_exit);
7146 subl(idx, 4);
7147
7148 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7149 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7150 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7151 rorxq(yz_idx2, yz_idx2, 32);
7152
7153 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7154 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7155
7156 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7157 rorxq(yz_idx1, yz_idx1, 32);
7158 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7159 rorxq(yz_idx2, yz_idx2, 32);
7160
7161 if (VM_Version::supports_adx()) {
7162 adcxq(tmp3, carry);
7163 adoxq(tmp3, yz_idx1);
7164
7165 adcxq(tmp4, tmp);
7166 adoxq(tmp4, yz_idx2);
7167
7168 movl(carry, 0); // does not affect flags
7169 adcxq(carry2, carry);
7170 adoxq(carry2, carry);
7171 } else {
7172 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7173 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7174 }
7175 movq(carry, carry2);
7176
7177 movl(Address(z, idx, Address::times_4, 12), tmp3);
7178 shrq(tmp3, 32);
7179 movl(Address(z, idx, Address::times_4, 8), tmp3);
7180
7181 movl(Address(z, idx, Address::times_4, 4), tmp4);
7182 shrq(tmp4, 32);
7183 movl(Address(z, idx, Address::times_4, 0), tmp4);
7184
7185 jmp(L_third_loop);
7186
7187 bind (L_third_loop_exit);
7188
7189 andl (idx, 0x3);
7190 jcc(Assembler::zero, L_post_third_loop_done);
7191
7192 Label L_check_1;
7193 subl(idx, 2);
7194 jcc(Assembler::negative, L_check_1);
7195
7196 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7197 rorxq(yz_idx1, yz_idx1, 32);
7198 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7199 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7200 rorxq(yz_idx2, yz_idx2, 32);
7201
7202 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7203
7204 movl(Address(z, idx, Address::times_4, 4), tmp3);
7205 shrq(tmp3, 32);
7206 movl(Address(z, idx, Address::times_4, 0), tmp3);
7207 movq(carry, tmp4);
7208
7209 bind (L_check_1);
7210 addl (idx, 0x2);
7211 andl (idx, 0x1);
7212 subl(idx, 1);
7213 jcc(Assembler::negative, L_post_third_loop_done);
7214 movl(tmp4, Address(y, idx, Address::times_4, 0));
7215 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7216 movl(tmp4, Address(z, idx, Address::times_4, 0));
7217
7218 add2_with_carry(carry2, tmp3, tmp4, carry);
7219
7220 movl(Address(z, idx, Address::times_4, 0), tmp3);
7221 shrq(tmp3, 32);
7222
7223 shlq(carry2, 32);
7224 orq(tmp3, carry2);
7225 movq(carry, tmp3);
7226
7227 bind(L_post_third_loop_done);
7228 }
7229
7230 /**
7231 * Code for BigInteger::multiplyToLen() intrinsic.
7232 *
7233 * rdi: x
7234 * rax: xlen
7235 * rsi: y
7236 * rcx: ylen
7237 * r8: z
7238 * r11: tmp0
7239 * r12: tmp1
7240 * r13: tmp2
7241 * r14: tmp3
7242 * r15: tmp4
7243 * rbx: tmp5
7244 *
7245 */
7246 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7247 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7248 ShortBranchVerifier sbv(this);
7249 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7250
7251 push(tmp0);
7252 push(tmp1);
7253 push(tmp2);
7254 push(tmp3);
7255 push(tmp4);
7256 push(tmp5);
7257
7258 push(xlen);
7259
7260 const Register idx = tmp1;
7261 const Register kdx = tmp2;
7262 const Register xstart = tmp3;
7263
7264 const Register y_idx = tmp4;
7265 const Register carry = tmp5;
7266 const Register product = xlen;
7267 const Register x_xstart = tmp0;
7268
7269 // First Loop.
7270 //
7271 // final static long LONG_MASK = 0xffffffffL;
7272 // int xstart = xlen - 1;
7273 // int ystart = ylen - 1;
7274 // long carry = 0;
7275 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7276 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7277 // z[kdx] = (int)product;
7278 // carry = product >>> 32;
7279 // }
7280 // z[xstart] = (int)carry;
7281 //
7282
7283 movl(idx, ylen); // idx = ylen;
7284 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7285 xorq(carry, carry); // carry = 0;
7286
7287 Label L_done;
7288
7289 movl(xstart, xlen);
7290 decrementl(xstart);
7291 jcc(Assembler::negative, L_done);
7292
7293 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7294
7295 Label L_second_loop;
7296 testl(kdx, kdx);
7297 jcc(Assembler::zero, L_second_loop);
7298
7299 Label L_carry;
7300 subl(kdx, 1);
7301 jcc(Assembler::zero, L_carry);
7302
7303 movl(Address(z, kdx, Address::times_4, 0), carry);
7304 shrq(carry, 32);
7305 subl(kdx, 1);
7306
7307 bind(L_carry);
7308 movl(Address(z, kdx, Address::times_4, 0), carry);
7309
7310 // Second and third (nested) loops.
7311 //
7312 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7313 // carry = 0;
7314 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7315 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7316 // (z[k] & LONG_MASK) + carry;
7317 // z[k] = (int)product;
7318 // carry = product >>> 32;
7319 // }
7320 // z[i] = (int)carry;
7321 // }
7322 //
7323 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7324
7325 const Register jdx = tmp1;
7326
7327 bind(L_second_loop);
7328 xorl(carry, carry); // carry = 0;
7329 movl(jdx, ylen); // j = ystart+1
7330
7331 subl(xstart, 1); // i = xstart-1;
7332 jcc(Assembler::negative, L_done);
7333
7334 push (z);
7335
7336 Label L_last_x;
7337 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7338 subl(xstart, 1); // i = xstart-1;
7339 jcc(Assembler::negative, L_last_x);
7340
7341 if (UseBMI2Instructions) {
7342 movq(rdx, Address(x, xstart, Address::times_4, 0));
7343 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7344 } else {
7345 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7346 rorq(x_xstart, 32); // convert big-endian to little-endian
7347 }
7348
7349 Label L_third_loop_prologue;
7350 bind(L_third_loop_prologue);
7351
7352 push (x);
7353 push (xstart);
7354 push (ylen);
7355
7356
7357 if (UseBMI2Instructions) {
7358 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7359 } else { // !UseBMI2Instructions
7360 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7361 }
7362
7363 pop(ylen);
7364 pop(xlen);
7365 pop(x);
7366 pop(z);
7367
7368 movl(tmp3, xlen);
7369 addl(tmp3, 1);
7370 movl(Address(z, tmp3, Address::times_4, 0), carry);
7371 subl(tmp3, 1);
7372 jccb(Assembler::negative, L_done);
7373
7374 shrq(carry, 32);
7375 movl(Address(z, tmp3, Address::times_4, 0), carry);
7376 jmp(L_second_loop);
7377
7378 // Next infrequent code is moved outside loops.
7379 bind(L_last_x);
7380 if (UseBMI2Instructions) {
7381 movl(rdx, Address(x, 0));
7382 } else {
7383 movl(x_xstart, Address(x, 0));
7384 }
7385 jmp(L_third_loop_prologue);
7386
7387 bind(L_done);
7388
7389 pop(xlen);
7390
7391 pop(tmp5);
7392 pop(tmp4);
7393 pop(tmp3);
7394 pop(tmp2);
7395 pop(tmp1);
7396 pop(tmp0);
7397 }
7398
7399 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7400 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7401 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7402 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7403 Label VECTOR8_TAIL, VECTOR4_TAIL;
7404 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7405 Label SAME_TILL_END, DONE;
7406 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7407
7408 //scale is in rcx in both Win64 and Unix
7409 ShortBranchVerifier sbv(this);
7410
7411 shlq(length);
7412 xorq(result, result);
7413
7414 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7415 VM_Version::supports_avx512vlbw()) {
7416 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7417
7418 cmpq(length, 64);
7419 jcc(Assembler::less, VECTOR32_TAIL);
7420
7421 movq(tmp1, length);
7422 andq(tmp1, 0x3F); // tail count
7423 andq(length, ~(0x3F)); //vector count
7424
7425 bind(VECTOR64_LOOP);
7426 // AVX512 code to compare 64 byte vectors.
7427 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7428 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7429 kortestql(k7, k7);
7430 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7431 addq(result, 64);
7432 subq(length, 64);
7433 jccb(Assembler::notZero, VECTOR64_LOOP);
7434
7435 //bind(VECTOR64_TAIL);
7436 testq(tmp1, tmp1);
7437 jcc(Assembler::zero, SAME_TILL_END);
7438
7439 //bind(VECTOR64_TAIL);
7440 // AVX512 code to compare up to 63 byte vectors.
7441 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7442 shlxq(tmp2, tmp2, tmp1);
7443 notq(tmp2);
7444 kmovql(k3, tmp2);
7445
7446 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7447 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7448
7449 ktestql(k7, k3);
7450 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7451
7452 bind(VECTOR64_NOT_EQUAL);
7453 kmovql(tmp1, k7);
7454 notq(tmp1);
7455 tzcntq(tmp1, tmp1);
7456 addq(result, tmp1);
7457 shrq(result);
7458 jmp(DONE);
7459 bind(VECTOR32_TAIL);
7460 }
7461
7462 cmpq(length, 8);
7463 jcc(Assembler::equal, VECTOR8_LOOP);
7464 jcc(Assembler::less, VECTOR4_TAIL);
7465
7466 if (UseAVX >= 2) {
7467 Label VECTOR16_TAIL, VECTOR32_LOOP;
7468
7469 cmpq(length, 16);
7470 jcc(Assembler::equal, VECTOR16_LOOP);
7471 jcc(Assembler::less, VECTOR8_LOOP);
7472
7473 cmpq(length, 32);
7474 jccb(Assembler::less, VECTOR16_TAIL);
7475
7476 subq(length, 32);
7477 bind(VECTOR32_LOOP);
7478 vmovdqu(rymm0, Address(obja, result));
7479 vmovdqu(rymm1, Address(objb, result));
7480 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7481 vptest(rymm2, rymm2);
7482 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7483 addq(result, 32);
7484 subq(length, 32);
7485 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7486 addq(length, 32);
7487 jcc(Assembler::equal, SAME_TILL_END);
7488 //falling through if less than 32 bytes left //close the branch here.
7489
7490 bind(VECTOR16_TAIL);
7491 cmpq(length, 16);
7492 jccb(Assembler::less, VECTOR8_TAIL);
7493 bind(VECTOR16_LOOP);
7494 movdqu(rymm0, Address(obja, result));
7495 movdqu(rymm1, Address(objb, result));
7496 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7497 ptest(rymm2, rymm2);
7498 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7499 addq(result, 16);
7500 subq(length, 16);
7501 jcc(Assembler::equal, SAME_TILL_END);
7502 //falling through if less than 16 bytes left
7503 } else {//regular intrinsics
7504
7505 cmpq(length, 16);
7506 jccb(Assembler::less, VECTOR8_TAIL);
7507
7508 subq(length, 16);
7509 bind(VECTOR16_LOOP);
7510 movdqu(rymm0, Address(obja, result));
7511 movdqu(rymm1, Address(objb, result));
7512 pxor(rymm0, rymm1);
7513 ptest(rymm0, rymm0);
7514 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7515 addq(result, 16);
7516 subq(length, 16);
7517 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7518 addq(length, 16);
7519 jcc(Assembler::equal, SAME_TILL_END);
7520 //falling through if less than 16 bytes left
7521 }
7522
7523 bind(VECTOR8_TAIL);
7524 cmpq(length, 8);
7525 jccb(Assembler::less, VECTOR4_TAIL);
7526 bind(VECTOR8_LOOP);
7527 movq(tmp1, Address(obja, result));
7528 movq(tmp2, Address(objb, result));
7529 xorq(tmp1, tmp2);
7530 testq(tmp1, tmp1);
7531 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7532 addq(result, 8);
7533 subq(length, 8);
7534 jcc(Assembler::equal, SAME_TILL_END);
7535 //falling through if less than 8 bytes left
7536
7537 bind(VECTOR4_TAIL);
7538 cmpq(length, 4);
7539 jccb(Assembler::less, BYTES_TAIL);
7540 bind(VECTOR4_LOOP);
7541 movl(tmp1, Address(obja, result));
7542 xorl(tmp1, Address(objb, result));
7543 testl(tmp1, tmp1);
7544 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7545 addq(result, 4);
7546 subq(length, 4);
7547 jcc(Assembler::equal, SAME_TILL_END);
7548 //falling through if less than 4 bytes left
7549
7550 bind(BYTES_TAIL);
7551 bind(BYTES_LOOP);
7552 load_unsigned_byte(tmp1, Address(obja, result));
7553 load_unsigned_byte(tmp2, Address(objb, result));
7554 xorl(tmp1, tmp2);
7555 testl(tmp1, tmp1);
7556 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7557 decq(length);
7558 jcc(Assembler::zero, SAME_TILL_END);
7559 incq(result);
7560 load_unsigned_byte(tmp1, Address(obja, result));
7561 load_unsigned_byte(tmp2, Address(objb, result));
7562 xorl(tmp1, tmp2);
7563 testl(tmp1, tmp1);
7564 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7565 decq(length);
7566 jcc(Assembler::zero, SAME_TILL_END);
7567 incq(result);
7568 load_unsigned_byte(tmp1, Address(obja, result));
7569 load_unsigned_byte(tmp2, Address(objb, result));
7570 xorl(tmp1, tmp2);
7571 testl(tmp1, tmp1);
7572 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7573 jmp(SAME_TILL_END);
7574
7575 if (UseAVX >= 2) {
7576 bind(VECTOR32_NOT_EQUAL);
7577 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7578 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7579 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7580 vpmovmskb(tmp1, rymm0);
7581 bsfq(tmp1, tmp1);
7582 addq(result, tmp1);
7583 shrq(result);
7584 jmp(DONE);
7585 }
7586
7587 bind(VECTOR16_NOT_EQUAL);
7588 if (UseAVX >= 2) {
7589 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7590 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7591 pxor(rymm0, rymm2);
7592 } else {
7593 pcmpeqb(rymm2, rymm2);
7594 pxor(rymm0, rymm1);
7595 pcmpeqb(rymm0, rymm1);
7596 pxor(rymm0, rymm2);
7597 }
7598 pmovmskb(tmp1, rymm0);
7599 bsfq(tmp1, tmp1);
7600 addq(result, tmp1);
7601 shrq(result);
7602 jmpb(DONE);
7603
7604 bind(VECTOR8_NOT_EQUAL);
7605 bind(VECTOR4_NOT_EQUAL);
7606 bsfq(tmp1, tmp1);
7607 shrq(tmp1, 3);
7608 addq(result, tmp1);
7609 bind(BYTES_NOT_EQUAL);
7610 shrq(result);
7611 jmpb(DONE);
7612
7613 bind(SAME_TILL_END);
7614 mov64(result, -1);
7615
7616 bind(DONE);
7617 }
7618
7619 //Helper functions for square_to_len()
7620
7621 /**
7622 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7623 * Preserves x and z and modifies rest of the registers.
7624 */
7625 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7626 // Perform square and right shift by 1
7627 // Handle odd xlen case first, then for even xlen do the following
7628 // jlong carry = 0;
7629 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7630 // huge_128 product = x[j:j+1] * x[j:j+1];
7631 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7632 // z[i+2:i+3] = (jlong)(product >>> 1);
7633 // carry = (jlong)product;
7634 // }
7635
7636 xorq(tmp5, tmp5); // carry
7637 xorq(rdxReg, rdxReg);
7638 xorl(tmp1, tmp1); // index for x
7639 xorl(tmp4, tmp4); // index for z
7640
7641 Label L_first_loop, L_first_loop_exit;
7642
7643 testl(xlen, 1);
7644 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7645
7646 // Square and right shift by 1 the odd element using 32 bit multiply
7647 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7648 imulq(raxReg, raxReg);
7649 shrq(raxReg, 1);
7650 adcq(tmp5, 0);
7651 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7652 incrementl(tmp1);
7653 addl(tmp4, 2);
7654
7655 // Square and right shift by 1 the rest using 64 bit multiply
7656 bind(L_first_loop);
7657 cmpptr(tmp1, xlen);
7658 jccb(Assembler::equal, L_first_loop_exit);
7659
7660 // Square
7661 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7662 rorq(raxReg, 32); // convert big-endian to little-endian
7663 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7664
7665 // Right shift by 1 and save carry
7666 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7667 rcrq(rdxReg, 1);
7668 rcrq(raxReg, 1);
7669 adcq(tmp5, 0);
7670
7671 // Store result in z
7672 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7673 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7674
7675 // Update indices for x and z
7676 addl(tmp1, 2);
7677 addl(tmp4, 4);
7678 jmp(L_first_loop);
7679
7680 bind(L_first_loop_exit);
7681 }
7682
7683
7684 /**
7685 * Perform the following multiply add operation using BMI2 instructions
7686 * carry:sum = sum + op1*op2 + carry
7687 * op2 should be in rdx
7688 * op2 is preserved, all other registers are modified
7689 */
7690 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7691 // assert op2 is rdx
7692 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7693 addq(sum, carry);
7694 adcq(tmp2, 0);
7695 addq(sum, op1);
7696 adcq(tmp2, 0);
7697 movq(carry, tmp2);
7698 }
7699
7700 /**
7701 * Perform the following multiply add operation:
7702 * carry:sum = sum + op1*op2 + carry
7703 * Preserves op1, op2 and modifies rest of registers
7704 */
7705 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7706 // rdx:rax = op1 * op2
7707 movq(raxReg, op2);
7708 mulq(op1);
7709
7710 // rdx:rax = sum + carry + rdx:rax
7711 addq(sum, carry);
7712 adcq(rdxReg, 0);
7713 addq(sum, raxReg);
7714 adcq(rdxReg, 0);
7715
7716 // carry:sum = rdx:sum
7717 movq(carry, rdxReg);
7718 }
7719
7720 /**
7721 * Add 64 bit long carry into z[] with carry propagation.
7722 * Preserves z and carry register values and modifies rest of registers.
7723 *
7724 */
7725 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7726 Label L_fourth_loop, L_fourth_loop_exit;
7727
7728 movl(tmp1, 1);
7729 subl(zlen, 2);
7730 addq(Address(z, zlen, Address::times_4, 0), carry);
7731
7732 bind(L_fourth_loop);
7733 jccb(Assembler::carryClear, L_fourth_loop_exit);
7734 subl(zlen, 2);
7735 jccb(Assembler::negative, L_fourth_loop_exit);
7736 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7737 jmp(L_fourth_loop);
7738 bind(L_fourth_loop_exit);
7739 }
7740
7741 /**
7742 * Shift z[] left by 1 bit.
7743 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7744 *
7745 */
7746 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7747
7748 Label L_fifth_loop, L_fifth_loop_exit;
7749
7750 // Fifth loop
7751 // Perform primitiveLeftShift(z, zlen, 1)
7752
7753 const Register prev_carry = tmp1;
7754 const Register new_carry = tmp4;
7755 const Register value = tmp2;
7756 const Register zidx = tmp3;
7757
7758 // int zidx, carry;
7759 // long value;
7760 // carry = 0;
7761 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7762 // (carry:value) = (z[i] << 1) | carry ;
7763 // z[i] = value;
7764 // }
7765
7766 movl(zidx, zlen);
7767 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7768
7769 bind(L_fifth_loop);
7770 decl(zidx); // Use decl to preserve carry flag
7771 decl(zidx);
7772 jccb(Assembler::negative, L_fifth_loop_exit);
7773
7774 if (UseBMI2Instructions) {
7775 movq(value, Address(z, zidx, Address::times_4, 0));
7776 rclq(value, 1);
7777 rorxq(value, value, 32);
7778 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7779 }
7780 else {
7781 // clear new_carry
7782 xorl(new_carry, new_carry);
7783
7784 // Shift z[i] by 1, or in previous carry and save new carry
7785 movq(value, Address(z, zidx, Address::times_4, 0));
7786 shlq(value, 1);
7787 adcl(new_carry, 0);
7788
7789 orq(value, prev_carry);
7790 rorq(value, 0x20);
7791 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7792
7793 // Set previous carry = new carry
7794 movl(prev_carry, new_carry);
7795 }
7796 jmp(L_fifth_loop);
7797
7798 bind(L_fifth_loop_exit);
7799 }
7800
7801
7802 /**
7803 * Code for BigInteger::squareToLen() intrinsic
7804 *
7805 * rdi: x
7806 * rsi: len
7807 * r8: z
7808 * rcx: zlen
7809 * r12: tmp1
7810 * r13: tmp2
7811 * r14: tmp3
7812 * r15: tmp4
7813 * rbx: tmp5
7814 *
7815 */
7816 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7817
7818 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7819 push(tmp1);
7820 push(tmp2);
7821 push(tmp3);
7822 push(tmp4);
7823 push(tmp5);
7824
7825 // First loop
7826 // Store the squares, right shifted one bit (i.e., divided by 2).
7827 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7828
7829 // Add in off-diagonal sums.
7830 //
7831 // Second, third (nested) and fourth loops.
7832 // zlen +=2;
7833 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7834 // carry = 0;
7835 // long op2 = x[xidx:xidx+1];
7836 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7837 // k -= 2;
7838 // long op1 = x[j:j+1];
7839 // long sum = z[k:k+1];
7840 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7841 // z[k:k+1] = sum;
7842 // }
7843 // add_one_64(z, k, carry, tmp_regs);
7844 // }
7845
7846 const Register carry = tmp5;
7847 const Register sum = tmp3;
7848 const Register op1 = tmp4;
7849 Register op2 = tmp2;
7850
7851 push(zlen);
7852 push(len);
7853 addl(zlen,2);
7854 bind(L_second_loop);
7855 xorq(carry, carry);
7856 subl(zlen, 4);
7857 subl(len, 2);
7858 push(zlen);
7859 push(len);
7860 cmpl(len, 0);
7861 jccb(Assembler::lessEqual, L_second_loop_exit);
7862
7863 // Multiply an array by one 64 bit long.
7864 if (UseBMI2Instructions) {
7865 op2 = rdxReg;
7866 movq(op2, Address(x, len, Address::times_4, 0));
7867 rorxq(op2, op2, 32);
7868 }
7869 else {
7870 movq(op2, Address(x, len, Address::times_4, 0));
7871 rorq(op2, 32);
7872 }
7873
7874 bind(L_third_loop);
7875 decrementl(len);
7876 jccb(Assembler::negative, L_third_loop_exit);
7877 decrementl(len);
7878 jccb(Assembler::negative, L_last_x);
7879
7880 movq(op1, Address(x, len, Address::times_4, 0));
7881 rorq(op1, 32);
7882
7883 bind(L_multiply);
7884 subl(zlen, 2);
7885 movq(sum, Address(z, zlen, Address::times_4, 0));
7886
7887 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
7888 if (UseBMI2Instructions) {
7889 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
7890 }
7891 else {
7892 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7893 }
7894
7895 movq(Address(z, zlen, Address::times_4, 0), sum);
7896
7897 jmp(L_third_loop);
7898 bind(L_third_loop_exit);
7899
7900 // Fourth loop
7901 // Add 64 bit long carry into z with carry propagation.
7902 // Uses offsetted zlen.
7903 add_one_64(z, zlen, carry, tmp1);
7904
7905 pop(len);
7906 pop(zlen);
7907 jmp(L_second_loop);
7908
7909 // Next infrequent code is moved outside loops.
7910 bind(L_last_x);
7911 movl(op1, Address(x, 0));
7912 jmp(L_multiply);
7913
7914 bind(L_second_loop_exit);
7915 pop(len);
7916 pop(zlen);
7917 pop(len);
7918 pop(zlen);
7919
7920 // Fifth loop
7921 // Shift z left 1 bit.
7922 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
7923
7924 // z[zlen-1] |= x[len-1] & 1;
7925 movl(tmp3, Address(x, len, Address::times_4, -4));
7926 andl(tmp3, 1);
7927 orl(Address(z, zlen, Address::times_4, -4), tmp3);
7928
7929 pop(tmp5);
7930 pop(tmp4);
7931 pop(tmp3);
7932 pop(tmp2);
7933 pop(tmp1);
7934 }
7935
7936 /**
7937 * Helper function for mul_add()
7938 * Multiply the in[] by int k and add to out[] starting at offset offs using
7939 * 128 bit by 32 bit multiply and return the carry in tmp5.
7940 * Only quad int aligned length of in[] is operated on in this function.
7941 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
7942 * This function preserves out, in and k registers.
7943 * len and offset point to the appropriate index in "in" & "out" correspondingly
7944 * tmp5 has the carry.
7945 * other registers are temporary and are modified.
7946 *
7947 */
7948 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
7949 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
7950 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7951
7952 Label L_first_loop, L_first_loop_exit;
7953
7954 movl(tmp1, len);
7955 shrl(tmp1, 2);
7956
7957 bind(L_first_loop);
7958 subl(tmp1, 1);
7959 jccb(Assembler::negative, L_first_loop_exit);
7960
7961 subl(len, 4);
7962 subl(offset, 4);
7963
7964 Register op2 = tmp2;
7965 const Register sum = tmp3;
7966 const Register op1 = tmp4;
7967 const Register carry = tmp5;
7968
7969 if (UseBMI2Instructions) {
7970 op2 = rdxReg;
7971 }
7972
7973 movq(op1, Address(in, len, Address::times_4, 8));
7974 rorq(op1, 32);
7975 movq(sum, Address(out, offset, Address::times_4, 8));
7976 rorq(sum, 32);
7977 if (UseBMI2Instructions) {
7978 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7979 }
7980 else {
7981 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7982 }
7983 // Store back in big endian from little endian
7984 rorq(sum, 0x20);
7985 movq(Address(out, offset, Address::times_4, 8), sum);
7986
7987 movq(op1, Address(in, len, Address::times_4, 0));
7988 rorq(op1, 32);
7989 movq(sum, Address(out, offset, Address::times_4, 0));
7990 rorq(sum, 32);
7991 if (UseBMI2Instructions) {
7992 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7993 }
7994 else {
7995 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7996 }
7997 // Store back in big endian from little endian
7998 rorq(sum, 0x20);
7999 movq(Address(out, offset, Address::times_4, 0), sum);
8000
8001 jmp(L_first_loop);
8002 bind(L_first_loop_exit);
8003 }
8004
8005 /**
8006 * Code for BigInteger::mulAdd() intrinsic
8007 *
8008 * rdi: out
8009 * rsi: in
8010 * r11: offs (out.length - offset)
8011 * rcx: len
8012 * r8: k
8013 * r12: tmp1
8014 * r13: tmp2
8015 * r14: tmp3
8016 * r15: tmp4
8017 * rbx: tmp5
8018 * Multiply the in[] by word k and add to out[], return the carry in rax
8019 */
8020 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8021 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8022 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8023
8024 Label L_carry, L_last_in, L_done;
8025
8026 // carry = 0;
8027 // for (int j=len-1; j >= 0; j--) {
8028 // long product = (in[j] & LONG_MASK) * kLong +
8029 // (out[offs] & LONG_MASK) + carry;
8030 // out[offs--] = (int)product;
8031 // carry = product >>> 32;
8032 // }
8033 //
8034 push(tmp1);
8035 push(tmp2);
8036 push(tmp3);
8037 push(tmp4);
8038 push(tmp5);
8039
8040 Register op2 = tmp2;
8041 const Register sum = tmp3;
8042 const Register op1 = tmp4;
8043 const Register carry = tmp5;
8044
8045 if (UseBMI2Instructions) {
8046 op2 = rdxReg;
8047 movl(op2, k);
8048 }
8049 else {
8050 movl(op2, k);
8051 }
8052
8053 xorq(carry, carry);
8054
8055 //First loop
8056
8057 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8058 //The carry is in tmp5
8059 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8060
8061 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8062 decrementl(len);
8063 jccb(Assembler::negative, L_carry);
8064 decrementl(len);
8065 jccb(Assembler::negative, L_last_in);
8066
8067 movq(op1, Address(in, len, Address::times_4, 0));
8068 rorq(op1, 32);
8069
8070 subl(offs, 2);
8071 movq(sum, Address(out, offs, Address::times_4, 0));
8072 rorq(sum, 32);
8073
8074 if (UseBMI2Instructions) {
8075 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8076 }
8077 else {
8078 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8079 }
8080
8081 // Store back in big endian from little endian
8082 rorq(sum, 0x20);
8083 movq(Address(out, offs, Address::times_4, 0), sum);
8084
8085 testl(len, len);
8086 jccb(Assembler::zero, L_carry);
8087
8088 //Multiply the last in[] entry, if any
8089 bind(L_last_in);
8090 movl(op1, Address(in, 0));
8091 movl(sum, Address(out, offs, Address::times_4, -4));
8092
8093 movl(raxReg, k);
8094 mull(op1); //tmp4 * eax -> edx:eax
8095 addl(sum, carry);
8096 adcl(rdxReg, 0);
8097 addl(sum, raxReg);
8098 adcl(rdxReg, 0);
8099 movl(carry, rdxReg);
8100
8101 movl(Address(out, offs, Address::times_4, -4), sum);
8102
8103 bind(L_carry);
8104 //return tmp5/carry as carry in rax
8105 movl(rax, carry);
8106
8107 bind(L_done);
8108 pop(tmp5);
8109 pop(tmp4);
8110 pop(tmp3);
8111 pop(tmp2);
8112 pop(tmp1);
8113 }
8114
8115 /**
8116 * Emits code to update CRC-32 with a byte value according to constants in table
8117 *
8118 * @param [in,out]crc Register containing the crc.
8119 * @param [in]val Register containing the byte to fold into the CRC.
8120 * @param [in]table Register containing the table of crc constants.
8121 *
8122 * uint32_t crc;
8123 * val = crc_table[(val ^ crc) & 0xFF];
8124 * crc = val ^ (crc >> 8);
8125 *
8126 */
8127 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8128 xorl(val, crc);
8129 andl(val, 0xFF);
8130 shrl(crc, 8); // unsigned shift
8131 xorl(crc, Address(table, val, Address::times_4, 0));
8132 }
8133
8134 /**
8135 * Fold 128-bit data chunk
8136 */
8137 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8138 if (UseAVX > 0) {
8139 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8140 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8141 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8142 pxor(xcrc, xtmp);
8143 } else {
8144 movdqa(xtmp, xcrc);
8145 pclmulhdq(xtmp, xK); // [123:64]
8146 pclmulldq(xcrc, xK); // [63:0]
8147 pxor(xcrc, xtmp);
8148 movdqu(xtmp, Address(buf, offset));
8149 pxor(xcrc, xtmp);
8150 }
8151 }
8152
8153 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8154 if (UseAVX > 0) {
8155 vpclmulhdq(xtmp, xK, xcrc);
8156 vpclmulldq(xcrc, xK, xcrc);
8157 pxor(xcrc, xbuf);
8158 pxor(xcrc, xtmp);
8159 } else {
8160 movdqa(xtmp, xcrc);
8161 pclmulhdq(xtmp, xK);
8162 pclmulldq(xcrc, xK);
8163 pxor(xcrc, xbuf);
8164 pxor(xcrc, xtmp);
8165 }
8166 }
8167
8168 /**
8169 * 8-bit folds to compute 32-bit CRC
8170 *
8171 * uint64_t xcrc;
8172 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8173 */
8174 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8175 movdl(tmp, xcrc);
8176 andl(tmp, 0xFF);
8177 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8178 psrldq(xcrc, 1); // unsigned shift one byte
8179 pxor(xcrc, xtmp);
8180 }
8181
8182 /**
8183 * uint32_t crc;
8184 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8185 */
8186 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8187 movl(tmp, crc);
8188 andl(tmp, 0xFF);
8189 shrl(crc, 8);
8190 xorl(crc, Address(table, tmp, Address::times_4, 0));
8191 }
8192
8193 /**
8194 * @param crc register containing existing CRC (32-bit)
8195 * @param buf register pointing to input byte buffer (byte*)
8196 * @param len register containing number of bytes
8197 * @param table register that will contain address of CRC table
8198 * @param tmp scratch register
8199 */
8200 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8201 assert_different_registers(crc, buf, len, table, tmp, rax);
8202
8203 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8204 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8205
8206 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8207 // context for the registers used, where all instructions below are using 128-bit mode
8208 // On EVEX without VL and BW, these instructions will all be AVX.
8209 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8210 notl(crc); // ~crc
8211 cmpl(len, 16);
8212 jcc(Assembler::less, L_tail);
8213
8214 // Align buffer to 16 bytes
8215 movl(tmp, buf);
8216 andl(tmp, 0xF);
8217 jccb(Assembler::zero, L_aligned);
8218 subl(tmp, 16);
8219 addl(len, tmp);
8220
8221 align(4);
8222 BIND(L_align_loop);
8223 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8224 update_byte_crc32(crc, rax, table);
8225 increment(buf);
8226 incrementl(tmp);
8227 jccb(Assembler::less, L_align_loop);
8228
8229 BIND(L_aligned);
8230 movl(tmp, len); // save
8231 shrl(len, 4);
8232 jcc(Assembler::zero, L_tail_restore);
8233
8234 // Fold crc into first bytes of vector
8235 movdqa(xmm1, Address(buf, 0));
8236 movdl(rax, xmm1);
8237 xorl(crc, rax);
8238 if (VM_Version::supports_sse4_1()) {
8239 pinsrd(xmm1, crc, 0);
8240 } else {
8241 pinsrw(xmm1, crc, 0);
8242 shrl(crc, 16);
8243 pinsrw(xmm1, crc, 1);
8244 }
8245 addptr(buf, 16);
8246 subl(len, 4); // len > 0
8247 jcc(Assembler::less, L_fold_tail);
8248
8249 movdqa(xmm2, Address(buf, 0));
8250 movdqa(xmm3, Address(buf, 16));
8251 movdqa(xmm4, Address(buf, 32));
8252 addptr(buf, 48);
8253 subl(len, 3);
8254 jcc(Assembler::lessEqual, L_fold_512b);
8255
8256 // Fold total 512 bits of polynomial on each iteration,
8257 // 128 bits per each of 4 parallel streams.
8258 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8259
8260 align32();
8261 BIND(L_fold_512b_loop);
8262 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8263 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8264 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8265 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8266 addptr(buf, 64);
8267 subl(len, 4);
8268 jcc(Assembler::greater, L_fold_512b_loop);
8269
8270 // Fold 512 bits to 128 bits.
8271 BIND(L_fold_512b);
8272 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8273 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8274 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8275 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8276
8277 // Fold the rest of 128 bits data chunks
8278 BIND(L_fold_tail);
8279 addl(len, 3);
8280 jccb(Assembler::lessEqual, L_fold_128b);
8281 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8282
8283 BIND(L_fold_tail_loop);
8284 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8285 addptr(buf, 16);
8286 decrementl(len);
8287 jccb(Assembler::greater, L_fold_tail_loop);
8288
8289 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8290 BIND(L_fold_128b);
8291 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8292 if (UseAVX > 0) {
8293 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8294 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8295 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8296 } else {
8297 movdqa(xmm2, xmm0);
8298 pclmulqdq(xmm2, xmm1, 0x1);
8299 movdqa(xmm3, xmm0);
8300 pand(xmm3, xmm2);
8301 pclmulqdq(xmm0, xmm3, 0x1);
8302 }
8303 psrldq(xmm1, 8);
8304 psrldq(xmm2, 4);
8305 pxor(xmm0, xmm1);
8306 pxor(xmm0, xmm2);
8307
8308 // 8 8-bit folds to compute 32-bit CRC.
8309 for (int j = 0; j < 4; j++) {
8310 fold_8bit_crc32(xmm0, table, xmm1, rax);
8311 }
8312 movdl(crc, xmm0); // mov 32 bits to general register
8313 for (int j = 0; j < 4; j++) {
8314 fold_8bit_crc32(crc, table, rax);
8315 }
8316
8317 BIND(L_tail_restore);
8318 movl(len, tmp); // restore
8319 BIND(L_tail);
8320 andl(len, 0xf);
8321 jccb(Assembler::zero, L_exit);
8322
8323 // Fold the rest of bytes
8324 align(4);
8325 BIND(L_tail_loop);
8326 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8327 update_byte_crc32(crc, rax, table);
8328 increment(buf);
8329 decrementl(len);
8330 jccb(Assembler::greater, L_tail_loop);
8331
8332 BIND(L_exit);
8333 notl(crc); // ~c
8334 }
8335
8336 // Helper function for AVX 512 CRC32
8337 // Fold 512-bit data chunks
8338 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8339 Register pos, int offset) {
8340 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8341 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8342 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8343 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8344 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8345 }
8346
8347 // Helper function for AVX 512 CRC32
8348 // Compute CRC32 for < 256B buffers
8349 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8350 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8351 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8352
8353 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8354 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8355 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8356
8357 // check if there is enough buffer to be able to fold 16B at a time
8358 cmpl(len, 32);
8359 jcc(Assembler::less, L_less_than_32);
8360
8361 // if there is, load the constants
8362 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8363 movdl(xmm0, crc); // get the initial crc value
8364 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8365 pxor(xmm7, xmm0);
8366
8367 // update the buffer pointer
8368 addl(pos, 16);
8369 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8370 subl(len, 32);
8371 jmp(L_16B_reduction_loop);
8372
8373 bind(L_less_than_32);
8374 //mov initial crc to the return value. this is necessary for zero - length buffers.
8375 movl(rax, crc);
8376 testl(len, len);
8377 jcc(Assembler::equal, L_cleanup);
8378
8379 movdl(xmm0, crc); //get the initial crc value
8380
8381 cmpl(len, 16);
8382 jcc(Assembler::equal, L_exact_16_left);
8383 jcc(Assembler::less, L_less_than_16_left);
8384
8385 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8386 pxor(xmm7, xmm0); //xor the initial crc value
8387 addl(pos, 16);
8388 subl(len, 16);
8389 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8390 jmp(L_get_last_two_xmms);
8391
8392 bind(L_less_than_16_left);
8393 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8394 pxor(xmm1, xmm1);
8395 movptr(tmp1, rsp);
8396 movdqu(Address(tmp1, 0 * 16), xmm1);
8397
8398 cmpl(len, 4);
8399 jcc(Assembler::less, L_only_less_than_4);
8400
8401 //backup the counter value
8402 movl(tmp2, len);
8403 cmpl(len, 8);
8404 jcc(Assembler::less, L_less_than_8_left);
8405
8406 //load 8 Bytes
8407 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8408 movq(Address(tmp1, 0 * 16), rax);
8409 addptr(tmp1, 8);
8410 subl(len, 8);
8411 addl(pos, 8);
8412
8413 bind(L_less_than_8_left);
8414 cmpl(len, 4);
8415 jcc(Assembler::less, L_less_than_4_left);
8416
8417 //load 4 Bytes
8418 movl(rax, Address(buf, pos, Address::times_1, 0));
8419 movl(Address(tmp1, 0 * 16), rax);
8420 addptr(tmp1, 4);
8421 subl(len, 4);
8422 addl(pos, 4);
8423
8424 bind(L_less_than_4_left);
8425 cmpl(len, 2);
8426 jcc(Assembler::less, L_less_than_2_left);
8427
8428 // load 2 Bytes
8429 movw(rax, Address(buf, pos, Address::times_1, 0));
8430 movl(Address(tmp1, 0 * 16), rax);
8431 addptr(tmp1, 2);
8432 subl(len, 2);
8433 addl(pos, 2);
8434
8435 bind(L_less_than_2_left);
8436 cmpl(len, 1);
8437 jcc(Assembler::less, L_zero_left);
8438
8439 // load 1 Byte
8440 movb(rax, Address(buf, pos, Address::times_1, 0));
8441 movb(Address(tmp1, 0 * 16), rax);
8442
8443 bind(L_zero_left);
8444 movdqu(xmm7, Address(rsp, 0));
8445 pxor(xmm7, xmm0); //xor the initial crc value
8446
8447 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8448 movdqu(xmm0, Address(rax, tmp2));
8449 pshufb(xmm7, xmm0);
8450 jmp(L_128_done);
8451
8452 bind(L_exact_16_left);
8453 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8454 pxor(xmm7, xmm0); //xor the initial crc value
8455 jmp(L_128_done);
8456
8457 bind(L_only_less_than_4);
8458 cmpl(len, 3);
8459 jcc(Assembler::less, L_only_less_than_3);
8460
8461 // load 3 Bytes
8462 movb(rax, Address(buf, pos, Address::times_1, 0));
8463 movb(Address(tmp1, 0), rax);
8464
8465 movb(rax, Address(buf, pos, Address::times_1, 1));
8466 movb(Address(tmp1, 1), rax);
8467
8468 movb(rax, Address(buf, pos, Address::times_1, 2));
8469 movb(Address(tmp1, 2), rax);
8470
8471 movdqu(xmm7, Address(rsp, 0));
8472 pxor(xmm7, xmm0); //xor the initial crc value
8473
8474 pslldq(xmm7, 0x5);
8475 jmp(L_barrett);
8476 bind(L_only_less_than_3);
8477 cmpl(len, 2);
8478 jcc(Assembler::less, L_only_less_than_2);
8479
8480 // load 2 Bytes
8481 movb(rax, Address(buf, pos, Address::times_1, 0));
8482 movb(Address(tmp1, 0), rax);
8483
8484 movb(rax, Address(buf, pos, Address::times_1, 1));
8485 movb(Address(tmp1, 1), rax);
8486
8487 movdqu(xmm7, Address(rsp, 0));
8488 pxor(xmm7, xmm0); //xor the initial crc value
8489
8490 pslldq(xmm7, 0x6);
8491 jmp(L_barrett);
8492
8493 bind(L_only_less_than_2);
8494 //load 1 Byte
8495 movb(rax, Address(buf, pos, Address::times_1, 0));
8496 movb(Address(tmp1, 0), rax);
8497
8498 movdqu(xmm7, Address(rsp, 0));
8499 pxor(xmm7, xmm0); //xor the initial crc value
8500
8501 pslldq(xmm7, 0x7);
8502 }
8503
8504 /**
8505 * Compute CRC32 using AVX512 instructions
8506 * param crc register containing existing CRC (32-bit)
8507 * param buf register pointing to input byte buffer (byte*)
8508 * param len register containing number of bytes
8509 * param table address of crc or crc32c table
8510 * param tmp1 scratch register
8511 * param tmp2 scratch register
8512 * return rax result register
8513 *
8514 * This routine is identical for crc32c with the exception of the precomputed constant
8515 * table which will be passed as the table argument. The calculation steps are
8516 * the same for both variants.
8517 */
8518 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8519 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8520
8521 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8522 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8523 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8524 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8525 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8526
8527 const Register pos = r12;
8528 push(r12);
8529 subptr(rsp, 16 * 2 + 8);
8530
8531 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8532 // context for the registers used, where all instructions below are using 128-bit mode
8533 // On EVEX without VL and BW, these instructions will all be AVX.
8534 movl(pos, 0);
8535
8536 // check if smaller than 256B
8537 cmpl(len, 256);
8538 jcc(Assembler::less, L_less_than_256);
8539
8540 // load the initial crc value
8541 movdl(xmm10, crc);
8542
8543 // receive the initial 64B data, xor the initial crc value
8544 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8545 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8546 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8547 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8548
8549 subl(len, 256);
8550 cmpl(len, 256);
8551 jcc(Assembler::less, L_fold_128_B_loop);
8552
8553 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8554 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8555 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8556 subl(len, 256);
8557
8558 bind(L_fold_256_B_loop);
8559 addl(pos, 256);
8560 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8561 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8562 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8563 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8564
8565 subl(len, 256);
8566 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8567
8568 // Fold 256 into 128
8569 addl(pos, 256);
8570 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8571 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8572 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8573
8574 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8575 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8576 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8577
8578 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8579 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8580
8581 addl(len, 128);
8582 jmp(L_fold_128_B_register);
8583
8584 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8585 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8586
8587 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8588 bind(L_fold_128_B_loop);
8589 addl(pos, 128);
8590 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8591 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8592
8593 subl(len, 128);
8594 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8595
8596 addl(pos, 128);
8597
8598 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8599 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8600 bind(L_fold_128_B_register);
8601 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8602 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8603 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8604 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8605 // save last that has no multiplicand
8606 vextracti64x2(xmm7, xmm4, 3);
8607
8608 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8609 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8610 // Needed later in reduction loop
8611 movdqu(xmm10, Address(table, 1 * 16));
8612 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8613 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8614
8615 // Swap 1,0,3,2 - 01 00 11 10
8616 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8617 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8618 vextracti128(xmm5, xmm8, 1);
8619 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8620
8621 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8622 // instead of a cmp instruction, we use the negative flag with the jl instruction
8623 addl(len, 128 - 16);
8624 jcc(Assembler::less, L_final_reduction_for_128);
8625
8626 bind(L_16B_reduction_loop);
8627 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8628 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8629 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8630 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8631 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8632 addl(pos, 16);
8633 subl(len, 16);
8634 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8635
8636 bind(L_final_reduction_for_128);
8637 addl(len, 16);
8638 jcc(Assembler::equal, L_128_done);
8639
8640 bind(L_get_last_two_xmms);
8641 movdqu(xmm2, xmm7);
8642 addl(pos, len);
8643 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8644 subl(pos, len);
8645
8646 // get rid of the extra data that was loaded before
8647 // load the shift constant
8648 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8649 movdqu(xmm0, Address(rax, len));
8650 addl(rax, len);
8651
8652 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8653 //Change mask to 512
8654 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8655 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8656
8657 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8658 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8659 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8660 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8661 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8662
8663 bind(L_128_done);
8664 // compute crc of a 128-bit value
8665 movdqu(xmm10, Address(table, 3 * 16));
8666 movdqu(xmm0, xmm7);
8667
8668 // 64b fold
8669 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8670 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8671 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8672
8673 // 32b fold
8674 movdqu(xmm0, xmm7);
8675 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8676 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8677 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8678 jmp(L_barrett);
8679
8680 bind(L_less_than_256);
8681 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8682
8683 //barrett reduction
8684 bind(L_barrett);
8685 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8686 movdqu(xmm1, xmm7);
8687 movdqu(xmm2, xmm7);
8688 movdqu(xmm10, Address(table, 4 * 16));
8689
8690 pclmulqdq(xmm7, xmm10, 0x0);
8691 pxor(xmm7, xmm2);
8692 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8693 movdqu(xmm2, xmm7);
8694 pclmulqdq(xmm7, xmm10, 0x10);
8695 pxor(xmm7, xmm2);
8696 pxor(xmm7, xmm1);
8697 pextrd(crc, xmm7, 2);
8698
8699 bind(L_cleanup);
8700 addptr(rsp, 16 * 2 + 8);
8701 pop(r12);
8702 }
8703
8704 // S. Gueron / Information Processing Letters 112 (2012) 184
8705 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8706 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8707 // Output: the 64-bit carry-less product of B * CONST
8708 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8709 Register tmp1, Register tmp2, Register tmp3) {
8710 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8711 if (n > 0) {
8712 addq(tmp3, n * 256 * 8);
8713 }
8714 // Q1 = TABLEExt[n][B & 0xFF];
8715 movl(tmp1, in);
8716 andl(tmp1, 0x000000FF);
8717 shll(tmp1, 3);
8718 addq(tmp1, tmp3);
8719 movq(tmp1, Address(tmp1, 0));
8720
8721 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8722 movl(tmp2, in);
8723 shrl(tmp2, 8);
8724 andl(tmp2, 0x000000FF);
8725 shll(tmp2, 3);
8726 addq(tmp2, tmp3);
8727 movq(tmp2, Address(tmp2, 0));
8728
8729 shlq(tmp2, 8);
8730 xorq(tmp1, tmp2);
8731
8732 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8733 movl(tmp2, in);
8734 shrl(tmp2, 16);
8735 andl(tmp2, 0x000000FF);
8736 shll(tmp2, 3);
8737 addq(tmp2, tmp3);
8738 movq(tmp2, Address(tmp2, 0));
8739
8740 shlq(tmp2, 16);
8741 xorq(tmp1, tmp2);
8742
8743 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8744 shrl(in, 24);
8745 andl(in, 0x000000FF);
8746 shll(in, 3);
8747 addq(in, tmp3);
8748 movq(in, Address(in, 0));
8749
8750 shlq(in, 24);
8751 xorq(in, tmp1);
8752 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8753 }
8754
8755 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8756 Register in_out,
8757 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8758 XMMRegister w_xtmp2,
8759 Register tmp1,
8760 Register n_tmp2, Register n_tmp3) {
8761 if (is_pclmulqdq_supported) {
8762 movdl(w_xtmp1, in_out); // modified blindly
8763
8764 movl(tmp1, const_or_pre_comp_const_index);
8765 movdl(w_xtmp2, tmp1);
8766 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8767
8768 movdq(in_out, w_xtmp1);
8769 } else {
8770 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8771 }
8772 }
8773
8774 // Recombination Alternative 2: No bit-reflections
8775 // T1 = (CRC_A * U1) << 1
8776 // T2 = (CRC_B * U2) << 1
8777 // C1 = T1 >> 32
8778 // C2 = T2 >> 32
8779 // T1 = T1 & 0xFFFFFFFF
8780 // T2 = T2 & 0xFFFFFFFF
8781 // T1 = CRC32(0, T1)
8782 // T2 = CRC32(0, T2)
8783 // C1 = C1 ^ T1
8784 // C2 = C2 ^ T2
8785 // CRC = C1 ^ C2 ^ CRC_C
8786 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8787 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8788 Register tmp1, Register tmp2,
8789 Register n_tmp3) {
8790 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8791 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8792 shlq(in_out, 1);
8793 movl(tmp1, in_out);
8794 shrq(in_out, 32);
8795 xorl(tmp2, tmp2);
8796 crc32(tmp2, tmp1, 4);
8797 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8798 shlq(in1, 1);
8799 movl(tmp1, in1);
8800 shrq(in1, 32);
8801 xorl(tmp2, tmp2);
8802 crc32(tmp2, tmp1, 4);
8803 xorl(in1, tmp2);
8804 xorl(in_out, in1);
8805 xorl(in_out, in2);
8806 }
8807
8808 // Set N to predefined value
8809 // Subtract from a length of a buffer
8810 // execute in a loop:
8811 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8812 // for i = 1 to N do
8813 // CRC_A = CRC32(CRC_A, A[i])
8814 // CRC_B = CRC32(CRC_B, B[i])
8815 // CRC_C = CRC32(CRC_C, C[i])
8816 // end for
8817 // Recombine
8818 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8819 Register in_out1, Register in_out2, Register in_out3,
8820 Register tmp1, Register tmp2, Register tmp3,
8821 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8822 Register tmp4, Register tmp5,
8823 Register n_tmp6) {
8824 Label L_processPartitions;
8825 Label L_processPartition;
8826 Label L_exit;
8827
8828 bind(L_processPartitions);
8829 cmpl(in_out1, 3 * size);
8830 jcc(Assembler::less, L_exit);
8831 xorl(tmp1, tmp1);
8832 xorl(tmp2, tmp2);
8833 movq(tmp3, in_out2);
8834 addq(tmp3, size);
8835
8836 bind(L_processPartition);
8837 crc32(in_out3, Address(in_out2, 0), 8);
8838 crc32(tmp1, Address(in_out2, size), 8);
8839 crc32(tmp2, Address(in_out2, size * 2), 8);
8840 addq(in_out2, 8);
8841 cmpq(in_out2, tmp3);
8842 jcc(Assembler::less, L_processPartition);
8843 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8844 w_xtmp1, w_xtmp2, w_xtmp3,
8845 tmp4, tmp5,
8846 n_tmp6);
8847 addq(in_out2, 2 * size);
8848 subl(in_out1, 3 * size);
8849 jmp(L_processPartitions);
8850
8851 bind(L_exit);
8852 }
8853
8854 // Algorithm 2: Pipelined usage of the CRC32 instruction.
8855 // Input: A buffer I of L bytes.
8856 // Output: the CRC32C value of the buffer.
8857 // Notations:
8858 // Write L = 24N + r, with N = floor (L/24).
8859 // r = L mod 24 (0 <= r < 24).
8860 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
8861 // N quadwords, and R consists of r bytes.
8862 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
8863 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
8864 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
8865 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
8866 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
8867 Register tmp1, Register tmp2, Register tmp3,
8868 Register tmp4, Register tmp5, Register tmp6,
8869 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8870 bool is_pclmulqdq_supported) {
8871 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
8872 Label L_wordByWord;
8873 Label L_byteByByteProlog;
8874 Label L_byteByByte;
8875 Label L_exit;
8876
8877 if (is_pclmulqdq_supported ) {
8878 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
8879 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
8880
8881 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
8882 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
8883
8884 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
8885 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
8886 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
8887 } else {
8888 const_or_pre_comp_const_index[0] = 1;
8889 const_or_pre_comp_const_index[1] = 0;
8890
8891 const_or_pre_comp_const_index[2] = 3;
8892 const_or_pre_comp_const_index[3] = 2;
8893
8894 const_or_pre_comp_const_index[4] = 5;
8895 const_or_pre_comp_const_index[5] = 4;
8896 }
8897 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8898 in2, in1, in_out,
8899 tmp1, tmp2, tmp3,
8900 w_xtmp1, w_xtmp2, w_xtmp3,
8901 tmp4, tmp5,
8902 tmp6);
8903 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8904 in2, in1, in_out,
8905 tmp1, tmp2, tmp3,
8906 w_xtmp1, w_xtmp2, w_xtmp3,
8907 tmp4, tmp5,
8908 tmp6);
8909 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8910 in2, in1, in_out,
8911 tmp1, tmp2, tmp3,
8912 w_xtmp1, w_xtmp2, w_xtmp3,
8913 tmp4, tmp5,
8914 tmp6);
8915 movl(tmp1, in2);
8916 andl(tmp1, 0x00000007);
8917 negl(tmp1);
8918 addl(tmp1, in2);
8919 addq(tmp1, in1);
8920
8921 cmpq(in1, tmp1);
8922 jccb(Assembler::greaterEqual, L_byteByByteProlog);
8923 align(16);
8924 BIND(L_wordByWord);
8925 crc32(in_out, Address(in1, 0), 8);
8926 addq(in1, 8);
8927 cmpq(in1, tmp1);
8928 jcc(Assembler::less, L_wordByWord);
8929
8930 BIND(L_byteByByteProlog);
8931 andl(in2, 0x00000007);
8932 movl(tmp2, 1);
8933
8934 cmpl(tmp2, in2);
8935 jccb(Assembler::greater, L_exit);
8936 BIND(L_byteByByte);
8937 crc32(in_out, Address(in1, 0), 1);
8938 incq(in1);
8939 incl(tmp2);
8940 cmpl(tmp2, in2);
8941 jcc(Assembler::lessEqual, L_byteByByte);
8942
8943 BIND(L_exit);
8944 }
8945 #undef BIND
8946 #undef BLOCK_COMMENT
8947
8948 // Compress char[] array to byte[].
8949 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
8950 // Return the array length if every element in array can be encoded,
8951 // otherwise, the index of first non-latin1 (> 0xff) character.
8952 // @IntrinsicCandidate
8953 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
8954 // for (int i = 0; i < len; i++) {
8955 // char c = src[srcOff];
8956 // if (c > 0xff) {
8957 // return i; // return index of non-latin1 char
8958 // }
8959 // dst[dstOff] = (byte)c;
8960 // srcOff++;
8961 // dstOff++;
8962 // }
8963 // return len;
8964 // }
8965 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
8966 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8967 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8968 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
8969 Label copy_chars_loop, done, reset_sp, copy_tail;
8970
8971 // rsi: src
8972 // rdi: dst
8973 // rdx: len
8974 // rcx: tmp5
8975 // rax: result
8976
8977 // rsi holds start addr of source char[] to be compressed
8978 // rdi holds start addr of destination byte[]
8979 // rdx holds length
8980
8981 assert(len != result, "");
8982
8983 // save length for return
8984 movl(result, len);
8985
8986 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
8987 VM_Version::supports_avx512vlbw() &&
8988 VM_Version::supports_bmi2()) {
8989
8990 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
8991
8992 // alignment
8993 Label post_alignment;
8994
8995 // if length of the string is less than 32, handle it the old fashioned way
8996 testl(len, -32);
8997 jcc(Assembler::zero, below_threshold);
8998
8999 // First check whether a character is compressible ( <= 0xFF).
9000 // Create mask to test for Unicode chars inside zmm vector
9001 movl(tmp5, 0x00FF);
9002 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9003
9004 testl(len, -64);
9005 jccb(Assembler::zero, post_alignment);
9006
9007 movl(tmp5, dst);
9008 andl(tmp5, (32 - 1));
9009 negl(tmp5);
9010 andl(tmp5, (32 - 1));
9011
9012 // bail out when there is nothing to be done
9013 testl(tmp5, 0xFFFFFFFF);
9014 jccb(Assembler::zero, post_alignment);
9015
9016 // ~(~0 << len), where len is the # of remaining elements to process
9017 movl(len, 0xFFFFFFFF);
9018 shlxl(len, len, tmp5);
9019 notl(len);
9020 kmovdl(mask2, len);
9021 movl(len, result);
9022
9023 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9024 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9025 ktestd(mask1, mask2);
9026 jcc(Assembler::carryClear, copy_tail);
9027
9028 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9029
9030 addptr(src, tmp5);
9031 addptr(src, tmp5);
9032 addptr(dst, tmp5);
9033 subl(len, tmp5);
9034
9035 bind(post_alignment);
9036 // end of alignment
9037
9038 movl(tmp5, len);
9039 andl(tmp5, (32 - 1)); // tail count (in chars)
9040 andl(len, ~(32 - 1)); // vector count (in chars)
9041 jccb(Assembler::zero, copy_loop_tail);
9042
9043 lea(src, Address(src, len, Address::times_2));
9044 lea(dst, Address(dst, len, Address::times_1));
9045 negptr(len);
9046
9047 bind(copy_32_loop);
9048 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9049 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9050 kortestdl(mask1, mask1);
9051 jccb(Assembler::carryClear, reset_for_copy_tail);
9052
9053 // All elements in current processed chunk are valid candidates for
9054 // compression. Write a truncated byte elements to the memory.
9055 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9056 addptr(len, 32);
9057 jccb(Assembler::notZero, copy_32_loop);
9058
9059 bind(copy_loop_tail);
9060 // bail out when there is nothing to be done
9061 testl(tmp5, 0xFFFFFFFF);
9062 jcc(Assembler::zero, done);
9063
9064 movl(len, tmp5);
9065
9066 // ~(~0 << len), where len is the # of remaining elements to process
9067 movl(tmp5, 0xFFFFFFFF);
9068 shlxl(tmp5, tmp5, len);
9069 notl(tmp5);
9070
9071 kmovdl(mask2, tmp5);
9072
9073 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9074 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9075 ktestd(mask1, mask2);
9076 jcc(Assembler::carryClear, copy_tail);
9077
9078 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9079 jmp(done);
9080
9081 bind(reset_for_copy_tail);
9082 lea(src, Address(src, tmp5, Address::times_2));
9083 lea(dst, Address(dst, tmp5, Address::times_1));
9084 subptr(len, tmp5);
9085 jmp(copy_chars_loop);
9086
9087 bind(below_threshold);
9088 }
9089
9090 if (UseSSE42Intrinsics) {
9091 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9092
9093 // vectored compression
9094 testl(len, 0xfffffff8);
9095 jcc(Assembler::zero, copy_tail);
9096
9097 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9098 movdl(tmp1Reg, tmp5);
9099 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9100
9101 andl(len, 0xfffffff0);
9102 jccb(Assembler::zero, copy_16);
9103
9104 // compress 16 chars per iter
9105 pxor(tmp4Reg, tmp4Reg);
9106
9107 lea(src, Address(src, len, Address::times_2));
9108 lea(dst, Address(dst, len, Address::times_1));
9109 negptr(len);
9110
9111 bind(copy_32_loop);
9112 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9113 por(tmp4Reg, tmp2Reg);
9114 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9115 por(tmp4Reg, tmp3Reg);
9116 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9117 jccb(Assembler::notZero, reset_for_copy_tail);
9118 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9119 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9120 addptr(len, 16);
9121 jccb(Assembler::notZero, copy_32_loop);
9122
9123 // compress next vector of 8 chars (if any)
9124 bind(copy_16);
9125 // len = 0
9126 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9127 jccb(Assembler::zero, copy_tail_sse);
9128
9129 pxor(tmp3Reg, tmp3Reg);
9130
9131 movdqu(tmp2Reg, Address(src, 0));
9132 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9133 jccb(Assembler::notZero, reset_for_copy_tail);
9134 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9135 movq(Address(dst, 0), tmp2Reg);
9136 addptr(src, 16);
9137 addptr(dst, 8);
9138 jmpb(copy_tail_sse);
9139
9140 bind(reset_for_copy_tail);
9141 movl(tmp5, result);
9142 andl(tmp5, 0x0000000f);
9143 lea(src, Address(src, tmp5, Address::times_2));
9144 lea(dst, Address(dst, tmp5, Address::times_1));
9145 subptr(len, tmp5);
9146 jmpb(copy_chars_loop);
9147
9148 bind(copy_tail_sse);
9149 movl(len, result);
9150 andl(len, 0x00000007); // tail count (in chars)
9151 }
9152 // compress 1 char per iter
9153 bind(copy_tail);
9154 testl(len, len);
9155 jccb(Assembler::zero, done);
9156 lea(src, Address(src, len, Address::times_2));
9157 lea(dst, Address(dst, len, Address::times_1));
9158 negptr(len);
9159
9160 bind(copy_chars_loop);
9161 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9162 testl(tmp5, 0xff00); // check if Unicode char
9163 jccb(Assembler::notZero, reset_sp);
9164 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9165 increment(len);
9166 jccb(Assembler::notZero, copy_chars_loop);
9167
9168 // add len then return (len will be zero if compress succeeded, otherwise negative)
9169 bind(reset_sp);
9170 addl(result, len);
9171
9172 bind(done);
9173 }
9174
9175 // Inflate byte[] array to char[].
9176 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9177 // @IntrinsicCandidate
9178 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9179 // for (int i = 0; i < len; i++) {
9180 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9181 // }
9182 // }
9183 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9184 XMMRegister tmp1, Register tmp2, KRegister mask) {
9185 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9186 // rsi: src
9187 // rdi: dst
9188 // rdx: len
9189 // rcx: tmp2
9190
9191 // rsi holds start addr of source byte[] to be inflated
9192 // rdi holds start addr of destination char[]
9193 // rdx holds length
9194 assert_different_registers(src, dst, len, tmp2);
9195 movl(tmp2, len);
9196 if ((UseAVX > 2) && // AVX512
9197 VM_Version::supports_avx512vlbw() &&
9198 VM_Version::supports_bmi2()) {
9199
9200 Label copy_32_loop, copy_tail;
9201 Register tmp3_aliased = len;
9202
9203 // if length of the string is less than 16, handle it in an old fashioned way
9204 testl(len, -16);
9205 jcc(Assembler::zero, below_threshold);
9206
9207 testl(len, -1 * AVX3Threshold);
9208 jcc(Assembler::zero, avx3_threshold);
9209
9210 // In order to use only one arithmetic operation for the main loop we use
9211 // this pre-calculation
9212 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9213 andl(len, -32); // vector count
9214 jccb(Assembler::zero, copy_tail);
9215
9216 lea(src, Address(src, len, Address::times_1));
9217 lea(dst, Address(dst, len, Address::times_2));
9218 negptr(len);
9219
9220
9221 // inflate 32 chars per iter
9222 bind(copy_32_loop);
9223 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9224 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9225 addptr(len, 32);
9226 jcc(Assembler::notZero, copy_32_loop);
9227
9228 bind(copy_tail);
9229 // bail out when there is nothing to be done
9230 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9231 jcc(Assembler::zero, done);
9232
9233 // ~(~0 << length), where length is the # of remaining elements to process
9234 movl(tmp3_aliased, -1);
9235 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9236 notl(tmp3_aliased);
9237 kmovdl(mask, tmp3_aliased);
9238 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9239 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9240
9241 jmp(done);
9242 bind(avx3_threshold);
9243 }
9244 if (UseSSE42Intrinsics) {
9245 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9246
9247 if (UseAVX > 1) {
9248 andl(tmp2, (16 - 1));
9249 andl(len, -16);
9250 jccb(Assembler::zero, copy_new_tail);
9251 } else {
9252 andl(tmp2, 0x00000007); // tail count (in chars)
9253 andl(len, 0xfffffff8); // vector count (in chars)
9254 jccb(Assembler::zero, copy_tail);
9255 }
9256
9257 // vectored inflation
9258 lea(src, Address(src, len, Address::times_1));
9259 lea(dst, Address(dst, len, Address::times_2));
9260 negptr(len);
9261
9262 if (UseAVX > 1) {
9263 bind(copy_16_loop);
9264 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9265 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9266 addptr(len, 16);
9267 jcc(Assembler::notZero, copy_16_loop);
9268
9269 bind(below_threshold);
9270 bind(copy_new_tail);
9271 movl(len, tmp2);
9272 andl(tmp2, 0x00000007);
9273 andl(len, 0xFFFFFFF8);
9274 jccb(Assembler::zero, copy_tail);
9275
9276 pmovzxbw(tmp1, Address(src, 0));
9277 movdqu(Address(dst, 0), tmp1);
9278 addptr(src, 8);
9279 addptr(dst, 2 * 8);
9280
9281 jmp(copy_tail, true);
9282 }
9283
9284 // inflate 8 chars per iter
9285 bind(copy_8_loop);
9286 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9287 movdqu(Address(dst, len, Address::times_2), tmp1);
9288 addptr(len, 8);
9289 jcc(Assembler::notZero, copy_8_loop);
9290
9291 bind(copy_tail);
9292 movl(len, tmp2);
9293
9294 cmpl(len, 4);
9295 jccb(Assembler::less, copy_bytes);
9296
9297 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9298 pmovzxbw(tmp1, tmp1);
9299 movq(Address(dst, 0), tmp1);
9300 subptr(len, 4);
9301 addptr(src, 4);
9302 addptr(dst, 8);
9303
9304 bind(copy_bytes);
9305 } else {
9306 bind(below_threshold);
9307 }
9308
9309 testl(len, len);
9310 jccb(Assembler::zero, done);
9311 lea(src, Address(src, len, Address::times_1));
9312 lea(dst, Address(dst, len, Address::times_2));
9313 negptr(len);
9314
9315 // inflate 1 char per iter
9316 bind(copy_chars_loop);
9317 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9318 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9319 increment(len);
9320 jcc(Assembler::notZero, copy_chars_loop);
9321
9322 bind(done);
9323 }
9324
9325 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9326 switch(type) {
9327 case T_BYTE:
9328 case T_BOOLEAN:
9329 evmovdqub(dst, kmask, src, merge, vector_len);
9330 break;
9331 case T_CHAR:
9332 case T_SHORT:
9333 evmovdquw(dst, kmask, src, merge, vector_len);
9334 break;
9335 case T_INT:
9336 case T_FLOAT:
9337 evmovdqul(dst, kmask, src, merge, vector_len);
9338 break;
9339 case T_LONG:
9340 case T_DOUBLE:
9341 evmovdquq(dst, kmask, src, merge, vector_len);
9342 break;
9343 default:
9344 fatal("Unexpected type argument %s", type2name(type));
9345 break;
9346 }
9347 }
9348
9349
9350 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9351 switch(type) {
9352 case T_BYTE:
9353 case T_BOOLEAN:
9354 evmovdqub(dst, kmask, src, merge, vector_len);
9355 break;
9356 case T_CHAR:
9357 case T_SHORT:
9358 evmovdquw(dst, kmask, src, merge, vector_len);
9359 break;
9360 case T_INT:
9361 case T_FLOAT:
9362 evmovdqul(dst, kmask, src, merge, vector_len);
9363 break;
9364 case T_LONG:
9365 case T_DOUBLE:
9366 evmovdquq(dst, kmask, src, merge, vector_len);
9367 break;
9368 default:
9369 fatal("Unexpected type argument %s", type2name(type));
9370 break;
9371 }
9372 }
9373
9374 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9375 switch(type) {
9376 case T_BYTE:
9377 case T_BOOLEAN:
9378 evmovdqub(dst, kmask, src, merge, vector_len);
9379 break;
9380 case T_CHAR:
9381 case T_SHORT:
9382 evmovdquw(dst, kmask, src, merge, vector_len);
9383 break;
9384 case T_INT:
9385 case T_FLOAT:
9386 evmovdqul(dst, kmask, src, merge, vector_len);
9387 break;
9388 case T_LONG:
9389 case T_DOUBLE:
9390 evmovdquq(dst, kmask, src, merge, vector_len);
9391 break;
9392 default:
9393 fatal("Unexpected type argument %s", type2name(type));
9394 break;
9395 }
9396 }
9397
9398 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9399 switch(masklen) {
9400 case 2:
9401 knotbl(dst, src);
9402 movl(rtmp, 3);
9403 kmovbl(ktmp, rtmp);
9404 kandbl(dst, ktmp, dst);
9405 break;
9406 case 4:
9407 knotbl(dst, src);
9408 movl(rtmp, 15);
9409 kmovbl(ktmp, rtmp);
9410 kandbl(dst, ktmp, dst);
9411 break;
9412 case 8:
9413 knotbl(dst, src);
9414 break;
9415 case 16:
9416 knotwl(dst, src);
9417 break;
9418 case 32:
9419 knotdl(dst, src);
9420 break;
9421 case 64:
9422 knotql(dst, src);
9423 break;
9424 default:
9425 fatal("Unexpected vector length %d", masklen);
9426 break;
9427 }
9428 }
9429
9430 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9431 switch(type) {
9432 case T_BOOLEAN:
9433 case T_BYTE:
9434 kandbl(dst, src1, src2);
9435 break;
9436 case T_CHAR:
9437 case T_SHORT:
9438 kandwl(dst, src1, src2);
9439 break;
9440 case T_INT:
9441 case T_FLOAT:
9442 kanddl(dst, src1, src2);
9443 break;
9444 case T_LONG:
9445 case T_DOUBLE:
9446 kandql(dst, src1, src2);
9447 break;
9448 default:
9449 fatal("Unexpected type argument %s", type2name(type));
9450 break;
9451 }
9452 }
9453
9454 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9455 switch(type) {
9456 case T_BOOLEAN:
9457 case T_BYTE:
9458 korbl(dst, src1, src2);
9459 break;
9460 case T_CHAR:
9461 case T_SHORT:
9462 korwl(dst, src1, src2);
9463 break;
9464 case T_INT:
9465 case T_FLOAT:
9466 kordl(dst, src1, src2);
9467 break;
9468 case T_LONG:
9469 case T_DOUBLE:
9470 korql(dst, src1, src2);
9471 break;
9472 default:
9473 fatal("Unexpected type argument %s", type2name(type));
9474 break;
9475 }
9476 }
9477
9478 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9479 switch(type) {
9480 case T_BOOLEAN:
9481 case T_BYTE:
9482 kxorbl(dst, src1, src2);
9483 break;
9484 case T_CHAR:
9485 case T_SHORT:
9486 kxorwl(dst, src1, src2);
9487 break;
9488 case T_INT:
9489 case T_FLOAT:
9490 kxordl(dst, src1, src2);
9491 break;
9492 case T_LONG:
9493 case T_DOUBLE:
9494 kxorql(dst, src1, src2);
9495 break;
9496 default:
9497 fatal("Unexpected type argument %s", type2name(type));
9498 break;
9499 }
9500 }
9501
9502 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9503 switch(type) {
9504 case T_BOOLEAN:
9505 case T_BYTE:
9506 evpermb(dst, mask, nds, src, merge, vector_len); break;
9507 case T_CHAR:
9508 case T_SHORT:
9509 evpermw(dst, mask, nds, src, merge, vector_len); break;
9510 case T_INT:
9511 case T_FLOAT:
9512 evpermd(dst, mask, nds, src, merge, vector_len); break;
9513 case T_LONG:
9514 case T_DOUBLE:
9515 evpermq(dst, mask, nds, src, merge, vector_len); break;
9516 default:
9517 fatal("Unexpected type argument %s", type2name(type)); break;
9518 }
9519 }
9520
9521 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9522 switch(type) {
9523 case T_BOOLEAN:
9524 case T_BYTE:
9525 evpermb(dst, mask, nds, src, merge, vector_len); break;
9526 case T_CHAR:
9527 case T_SHORT:
9528 evpermw(dst, mask, nds, src, merge, vector_len); break;
9529 case T_INT:
9530 case T_FLOAT:
9531 evpermd(dst, mask, nds, src, merge, vector_len); break;
9532 case T_LONG:
9533 case T_DOUBLE:
9534 evpermq(dst, mask, nds, src, merge, vector_len); break;
9535 default:
9536 fatal("Unexpected type argument %s", type2name(type)); break;
9537 }
9538 }
9539
9540 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9541 switch(type) {
9542 case T_BYTE:
9543 evpminub(dst, mask, nds, src, merge, vector_len); break;
9544 case T_SHORT:
9545 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9546 case T_INT:
9547 evpminud(dst, mask, nds, src, merge, vector_len); break;
9548 case T_LONG:
9549 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9550 default:
9551 fatal("Unexpected type argument %s", type2name(type)); break;
9552 }
9553 }
9554
9555 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9556 switch(type) {
9557 case T_BYTE:
9558 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9559 case T_SHORT:
9560 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9561 case T_INT:
9562 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9563 case T_LONG:
9564 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9565 default:
9566 fatal("Unexpected type argument %s", type2name(type)); break;
9567 }
9568 }
9569
9570 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9571 switch(type) {
9572 case T_BYTE:
9573 evpminub(dst, mask, nds, src, merge, vector_len); break;
9574 case T_SHORT:
9575 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9576 case T_INT:
9577 evpminud(dst, mask, nds, src, merge, vector_len); break;
9578 case T_LONG:
9579 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9580 default:
9581 fatal("Unexpected type argument %s", type2name(type)); break;
9582 }
9583 }
9584
9585 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9586 switch(type) {
9587 case T_BYTE:
9588 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9589 case T_SHORT:
9590 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9591 case T_INT:
9592 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9593 case T_LONG:
9594 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9595 default:
9596 fatal("Unexpected type argument %s", type2name(type)); break;
9597 }
9598 }
9599
9600 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9601 switch(type) {
9602 case T_BYTE:
9603 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9604 case T_SHORT:
9605 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9606 case T_INT:
9607 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9608 case T_LONG:
9609 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9610 case T_FLOAT:
9611 evminmaxps(dst, mask, nds, src, merge, AVX10_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9612 case T_DOUBLE:
9613 evminmaxpd(dst, mask, nds, src, merge, AVX10_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9614 default:
9615 fatal("Unexpected type argument %s", type2name(type)); break;
9616 }
9617 }
9618
9619 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9620 switch(type) {
9621 case T_BYTE:
9622 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9623 case T_SHORT:
9624 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9625 case T_INT:
9626 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9627 case T_LONG:
9628 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9629 case T_FLOAT:
9630 evminmaxps(dst, mask, nds, src, merge, AVX10_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9631 case T_DOUBLE:
9632 evminmaxpd(dst, mask, nds, src, merge, AVX10_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9633 default:
9634 fatal("Unexpected type argument %s", type2name(type)); break;
9635 }
9636 }
9637
9638 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9639 switch(type) {
9640 case T_BYTE:
9641 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9642 case T_SHORT:
9643 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9644 case T_INT:
9645 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9646 case T_LONG:
9647 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9648 case T_FLOAT:
9649 evminmaxps(dst, mask, nds, src, merge, AVX10_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9650 case T_DOUBLE:
9651 evminmaxpd(dst, mask, nds, src, merge, AVX10_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9652 default:
9653 fatal("Unexpected type argument %s", type2name(type)); break;
9654 }
9655 }
9656
9657 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9658 switch(type) {
9659 case T_BYTE:
9660 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9661 case T_SHORT:
9662 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9663 case T_INT:
9664 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9665 case T_LONG:
9666 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9667 case T_FLOAT:
9668 evminmaxps(dst, mask, nds, src, merge, AVX10_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9669 case T_DOUBLE:
9670 evminmaxps(dst, mask, nds, src, merge, AVX10_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9671 default:
9672 fatal("Unexpected type argument %s", type2name(type)); break;
9673 }
9674 }
9675
9676 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9677 switch(type) {
9678 case T_INT:
9679 evpxord(dst, mask, nds, src, merge, vector_len); break;
9680 case T_LONG:
9681 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9682 default:
9683 fatal("Unexpected type argument %s", type2name(type)); break;
9684 }
9685 }
9686
9687 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9688 switch(type) {
9689 case T_INT:
9690 evpxord(dst, mask, nds, src, merge, vector_len); break;
9691 case T_LONG:
9692 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9693 default:
9694 fatal("Unexpected type argument %s", type2name(type)); break;
9695 }
9696 }
9697
9698 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9699 switch(type) {
9700 case T_INT:
9701 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9702 case T_LONG:
9703 evporq(dst, mask, nds, src, merge, vector_len); break;
9704 default:
9705 fatal("Unexpected type argument %s", type2name(type)); break;
9706 }
9707 }
9708
9709 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9710 switch(type) {
9711 case T_INT:
9712 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9713 case T_LONG:
9714 evporq(dst, mask, nds, src, merge, vector_len); break;
9715 default:
9716 fatal("Unexpected type argument %s", type2name(type)); break;
9717 }
9718 }
9719
9720 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9721 switch(type) {
9722 case T_INT:
9723 evpandd(dst, mask, nds, src, merge, vector_len); break;
9724 case T_LONG:
9725 evpandq(dst, mask, nds, src, merge, vector_len); break;
9726 default:
9727 fatal("Unexpected type argument %s", type2name(type)); break;
9728 }
9729 }
9730
9731 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9732 switch(type) {
9733 case T_INT:
9734 evpandd(dst, mask, nds, src, merge, vector_len); break;
9735 case T_LONG:
9736 evpandq(dst, mask, nds, src, merge, vector_len); break;
9737 default:
9738 fatal("Unexpected type argument %s", type2name(type)); break;
9739 }
9740 }
9741
9742 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
9743 switch(masklen) {
9744 case 8:
9745 kortestbl(src1, src2);
9746 break;
9747 case 16:
9748 kortestwl(src1, src2);
9749 break;
9750 case 32:
9751 kortestdl(src1, src2);
9752 break;
9753 case 64:
9754 kortestql(src1, src2);
9755 break;
9756 default:
9757 fatal("Unexpected mask length %d", masklen);
9758 break;
9759 }
9760 }
9761
9762
9763 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
9764 switch(masklen) {
9765 case 8:
9766 ktestbl(src1, src2);
9767 break;
9768 case 16:
9769 ktestwl(src1, src2);
9770 break;
9771 case 32:
9772 ktestdl(src1, src2);
9773 break;
9774 case 64:
9775 ktestql(src1, src2);
9776 break;
9777 default:
9778 fatal("Unexpected mask length %d", masklen);
9779 break;
9780 }
9781 }
9782
9783 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9784 switch(type) {
9785 case T_INT:
9786 evprold(dst, mask, src, shift, merge, vlen_enc); break;
9787 case T_LONG:
9788 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
9789 default:
9790 fatal("Unexpected type argument %s", type2name(type)); break;
9791 break;
9792 }
9793 }
9794
9795 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9796 switch(type) {
9797 case T_INT:
9798 evprord(dst, mask, src, shift, merge, vlen_enc); break;
9799 case T_LONG:
9800 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
9801 default:
9802 fatal("Unexpected type argument %s", type2name(type)); break;
9803 }
9804 }
9805
9806 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9807 switch(type) {
9808 case T_INT:
9809 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
9810 case T_LONG:
9811 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
9812 default:
9813 fatal("Unexpected type argument %s", type2name(type)); break;
9814 }
9815 }
9816
9817 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9818 switch(type) {
9819 case T_INT:
9820 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
9821 case T_LONG:
9822 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
9823 default:
9824 fatal("Unexpected type argument %s", type2name(type)); break;
9825 }
9826 }
9827
9828 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9829 assert(rscratch != noreg || always_reachable(src), "missing");
9830
9831 if (reachable(src)) {
9832 evpandq(dst, nds, as_Address(src), vector_len);
9833 } else {
9834 lea(rscratch, src);
9835 evpandq(dst, nds, Address(rscratch, 0), vector_len);
9836 }
9837 }
9838
9839 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
9840 assert(rscratch != noreg || always_reachable(src), "missing");
9841
9842 if (reachable(src)) {
9843 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
9844 } else {
9845 lea(rscratch, src);
9846 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
9847 }
9848 }
9849
9850 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9851 assert(rscratch != noreg || always_reachable(src), "missing");
9852
9853 if (reachable(src)) {
9854 evporq(dst, nds, as_Address(src), vector_len);
9855 } else {
9856 lea(rscratch, src);
9857 evporq(dst, nds, Address(rscratch, 0), vector_len);
9858 }
9859 }
9860
9861 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9862 assert(rscratch != noreg || always_reachable(src), "missing");
9863
9864 if (reachable(src)) {
9865 vpshufb(dst, nds, as_Address(src), vector_len);
9866 } else {
9867 lea(rscratch, src);
9868 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
9869 }
9870 }
9871
9872 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9873 assert(rscratch != noreg || always_reachable(src), "missing");
9874
9875 if (reachable(src)) {
9876 Assembler::vpor(dst, nds, as_Address(src), vector_len);
9877 } else {
9878 lea(rscratch, src);
9879 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
9880 }
9881 }
9882
9883 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
9884 assert(rscratch != noreg || always_reachable(src3), "missing");
9885
9886 if (reachable(src3)) {
9887 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
9888 } else {
9889 lea(rscratch, src3);
9890 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
9891 }
9892 }
9893
9894 #if COMPILER2_OR_JVMCI
9895
9896 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
9897 Register length, Register temp, int vec_enc) {
9898 // Computing mask for predicated vector store.
9899 movptr(temp, -1);
9900 bzhiq(temp, temp, length);
9901 kmov(mask, temp);
9902 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
9903 }
9904
9905 // Set memory operation for length "less than" 64 bytes.
9906 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
9907 XMMRegister xmm, KRegister mask, Register length,
9908 Register temp, bool use64byteVector) {
9909 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9910 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9911 if (!use64byteVector) {
9912 fill32(dst, disp, xmm);
9913 subptr(length, 32 >> shift);
9914 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
9915 } else {
9916 assert(MaxVectorSize == 64, "vector length != 64");
9917 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
9918 }
9919 }
9920
9921
9922 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
9923 XMMRegister xmm, KRegister mask, Register length,
9924 Register temp) {
9925 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9926 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9927 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
9928 }
9929
9930
9931 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
9932 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9933 vmovdqu(dst, xmm);
9934 }
9935
9936 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
9937 fill32(Address(dst, disp), xmm);
9938 }
9939
9940 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
9941 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9942 if (!use64byteVector) {
9943 fill32(dst, xmm);
9944 fill32(dst.plus_disp(32), xmm);
9945 } else {
9946 evmovdquq(dst, xmm, Assembler::AVX_512bit);
9947 }
9948 }
9949
9950 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
9951 fill64(Address(dst, disp), xmm, use64byteVector);
9952 }
9953
9954 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
9955 Register count, Register rtmp, XMMRegister xtmp) {
9956 Label L_exit;
9957 Label L_fill_start;
9958 Label L_fill_64_bytes;
9959 Label L_fill_96_bytes;
9960 Label L_fill_128_bytes;
9961 Label L_fill_128_bytes_loop;
9962 Label L_fill_128_loop_header;
9963 Label L_fill_128_bytes_loop_header;
9964 Label L_fill_128_bytes_loop_pre_header;
9965 Label L_fill_zmm_sequence;
9966
9967 int shift = -1;
9968 int avx3threshold = VM_Version::avx3_threshold();
9969 switch(type) {
9970 case T_BYTE: shift = 0;
9971 break;
9972 case T_SHORT: shift = 1;
9973 break;
9974 case T_INT: shift = 2;
9975 break;
9976 /* Uncomment when LONG fill stubs are supported.
9977 case T_LONG: shift = 3;
9978 break;
9979 */
9980 default:
9981 fatal("Unhandled type: %s\n", type2name(type));
9982 }
9983
9984 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
9985
9986 if (MaxVectorSize == 64) {
9987 cmpq(count, avx3threshold >> shift);
9988 jcc(Assembler::greater, L_fill_zmm_sequence);
9989 }
9990
9991 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
9992
9993 bind(L_fill_start);
9994
9995 cmpq(count, 32 >> shift);
9996 jccb(Assembler::greater, L_fill_64_bytes);
9997 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
9998 jmp(L_exit);
9999
10000 bind(L_fill_64_bytes);
10001 cmpq(count, 64 >> shift);
10002 jccb(Assembler::greater, L_fill_96_bytes);
10003 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10004 jmp(L_exit);
10005
10006 bind(L_fill_96_bytes);
10007 cmpq(count, 96 >> shift);
10008 jccb(Assembler::greater, L_fill_128_bytes);
10009 fill64(to, 0, xtmp);
10010 subq(count, 64 >> shift);
10011 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10012 jmp(L_exit);
10013
10014 bind(L_fill_128_bytes);
10015 cmpq(count, 128 >> shift);
10016 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10017 fill64(to, 0, xtmp);
10018 fill32(to, 64, xtmp);
10019 subq(count, 96 >> shift);
10020 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10021 jmp(L_exit);
10022
10023 bind(L_fill_128_bytes_loop_pre_header);
10024 {
10025 mov(rtmp, to);
10026 andq(rtmp, 31);
10027 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10028 negq(rtmp);
10029 addq(rtmp, 32);
10030 mov64(r8, -1L);
10031 bzhiq(r8, r8, rtmp);
10032 kmovql(k2, r8);
10033 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10034 addq(to, rtmp);
10035 shrq(rtmp, shift);
10036 subq(count, rtmp);
10037 }
10038
10039 cmpq(count, 128 >> shift);
10040 jcc(Assembler::less, L_fill_start);
10041
10042 bind(L_fill_128_bytes_loop_header);
10043 subq(count, 128 >> shift);
10044
10045 align32();
10046 bind(L_fill_128_bytes_loop);
10047 fill64(to, 0, xtmp);
10048 fill64(to, 64, xtmp);
10049 addq(to, 128);
10050 subq(count, 128 >> shift);
10051 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10052
10053 addq(count, 128 >> shift);
10054 jcc(Assembler::zero, L_exit);
10055 jmp(L_fill_start);
10056 }
10057
10058 if (MaxVectorSize == 64) {
10059 // Sequence using 64 byte ZMM register.
10060 Label L_fill_128_bytes_zmm;
10061 Label L_fill_192_bytes_zmm;
10062 Label L_fill_192_bytes_loop_zmm;
10063 Label L_fill_192_bytes_loop_header_zmm;
10064 Label L_fill_192_bytes_loop_pre_header_zmm;
10065 Label L_fill_start_zmm_sequence;
10066
10067 bind(L_fill_zmm_sequence);
10068 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10069
10070 bind(L_fill_start_zmm_sequence);
10071 cmpq(count, 64 >> shift);
10072 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10073 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10074 jmp(L_exit);
10075
10076 bind(L_fill_128_bytes_zmm);
10077 cmpq(count, 128 >> shift);
10078 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10079 fill64(to, 0, xtmp, true);
10080 subq(count, 64 >> shift);
10081 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10082 jmp(L_exit);
10083
10084 bind(L_fill_192_bytes_zmm);
10085 cmpq(count, 192 >> shift);
10086 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10087 fill64(to, 0, xtmp, true);
10088 fill64(to, 64, xtmp, true);
10089 subq(count, 128 >> shift);
10090 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10091 jmp(L_exit);
10092
10093 bind(L_fill_192_bytes_loop_pre_header_zmm);
10094 {
10095 movq(rtmp, to);
10096 andq(rtmp, 63);
10097 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10098 negq(rtmp);
10099 addq(rtmp, 64);
10100 mov64(r8, -1L);
10101 bzhiq(r8, r8, rtmp);
10102 kmovql(k2, r8);
10103 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10104 addq(to, rtmp);
10105 shrq(rtmp, shift);
10106 subq(count, rtmp);
10107 }
10108
10109 cmpq(count, 192 >> shift);
10110 jcc(Assembler::less, L_fill_start_zmm_sequence);
10111
10112 bind(L_fill_192_bytes_loop_header_zmm);
10113 subq(count, 192 >> shift);
10114
10115 align32();
10116 bind(L_fill_192_bytes_loop_zmm);
10117 fill64(to, 0, xtmp, true);
10118 fill64(to, 64, xtmp, true);
10119 fill64(to, 128, xtmp, true);
10120 addq(to, 192);
10121 subq(count, 192 >> shift);
10122 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10123
10124 addq(count, 192 >> shift);
10125 jcc(Assembler::zero, L_exit);
10126 jmp(L_fill_start_zmm_sequence);
10127 }
10128 bind(L_exit);
10129 }
10130 #endif //COMPILER2_OR_JVMCI
10131
10132
10133 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10134 Label done;
10135 cvttss2sil(dst, src);
10136 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10137 cmpl(dst, 0x80000000); // float_sign_flip
10138 jccb(Assembler::notEqual, done);
10139 subptr(rsp, 8);
10140 movflt(Address(rsp, 0), src);
10141 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10142 pop(dst);
10143 bind(done);
10144 }
10145
10146 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10147 Label done;
10148 cvttsd2sil(dst, src);
10149 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10150 cmpl(dst, 0x80000000); // float_sign_flip
10151 jccb(Assembler::notEqual, done);
10152 subptr(rsp, 8);
10153 movdbl(Address(rsp, 0), src);
10154 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10155 pop(dst);
10156 bind(done);
10157 }
10158
10159 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10160 Label done;
10161 cvttss2siq(dst, src);
10162 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10163 jccb(Assembler::notEqual, done);
10164 subptr(rsp, 8);
10165 movflt(Address(rsp, 0), src);
10166 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10167 pop(dst);
10168 bind(done);
10169 }
10170
10171 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10172 // Following code is line by line assembly translation rounding algorithm.
10173 // Please refer to java.lang.Math.round(float) algorithm for details.
10174 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10175 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10176 const int32_t FloatConsts_EXP_BIAS = 127;
10177 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10178 const int32_t MINUS_32 = 0xFFFFFFE0;
10179 Label L_special_case, L_block1, L_exit;
10180 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10181 movdl(dst, src);
10182 andl(dst, rtmp);
10183 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10184 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10185 subl(rtmp, dst);
10186 movl(rcx, rtmp);
10187 movl(dst, MINUS_32);
10188 testl(rtmp, dst);
10189 jccb(Assembler::notEqual, L_special_case);
10190 movdl(dst, src);
10191 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10192 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10193 movdl(rtmp, src);
10194 testl(rtmp, rtmp);
10195 jccb(Assembler::greaterEqual, L_block1);
10196 negl(dst);
10197 bind(L_block1);
10198 sarl(dst);
10199 addl(dst, 0x1);
10200 sarl(dst, 0x1);
10201 jmp(L_exit);
10202 bind(L_special_case);
10203 convert_f2i(dst, src);
10204 bind(L_exit);
10205 }
10206
10207 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10208 // Following code is line by line assembly translation rounding algorithm.
10209 // Please refer to java.lang.Math.round(double) algorithm for details.
10210 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10211 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10212 const int64_t DoubleConsts_EXP_BIAS = 1023;
10213 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10214 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10215 Label L_special_case, L_block1, L_exit;
10216 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10217 movq(dst, src);
10218 andq(dst, rtmp);
10219 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10220 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10221 subq(rtmp, dst);
10222 movq(rcx, rtmp);
10223 mov64(dst, MINUS_64);
10224 testq(rtmp, dst);
10225 jccb(Assembler::notEqual, L_special_case);
10226 movq(dst, src);
10227 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10228 andq(dst, rtmp);
10229 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10230 orq(dst, rtmp);
10231 movq(rtmp, src);
10232 testq(rtmp, rtmp);
10233 jccb(Assembler::greaterEqual, L_block1);
10234 negq(dst);
10235 bind(L_block1);
10236 sarq(dst);
10237 addq(dst, 0x1);
10238 sarq(dst, 0x1);
10239 jmp(L_exit);
10240 bind(L_special_case);
10241 convert_d2l(dst, src);
10242 bind(L_exit);
10243 }
10244
10245 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10246 Label done;
10247 cvttsd2siq(dst, src);
10248 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10249 jccb(Assembler::notEqual, done);
10250 subptr(rsp, 8);
10251 movdbl(Address(rsp, 0), src);
10252 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10253 pop(dst);
10254 bind(done);
10255 }
10256
10257 void MacroAssembler::cache_wb(Address line)
10258 {
10259 // 64 bit cpus always support clflush
10260 assert(VM_Version::supports_clflush(), "clflush should be available");
10261 bool optimized = VM_Version::supports_clflushopt();
10262 bool no_evict = VM_Version::supports_clwb();
10263
10264 // prefer clwb (writeback without evict) otherwise
10265 // prefer clflushopt (potentially parallel writeback with evict)
10266 // otherwise fallback on clflush (serial writeback with evict)
10267
10268 if (optimized) {
10269 if (no_evict) {
10270 clwb(line);
10271 } else {
10272 clflushopt(line);
10273 }
10274 } else {
10275 // no need for fence when using CLFLUSH
10276 clflush(line);
10277 }
10278 }
10279
10280 void MacroAssembler::cache_wbsync(bool is_pre)
10281 {
10282 assert(VM_Version::supports_clflush(), "clflush should be available");
10283 bool optimized = VM_Version::supports_clflushopt();
10284 bool no_evict = VM_Version::supports_clwb();
10285
10286 // pick the correct implementation
10287
10288 if (!is_pre && (optimized || no_evict)) {
10289 // need an sfence for post flush when using clflushopt or clwb
10290 // otherwise no no need for any synchroniaztion
10291
10292 sfence();
10293 }
10294 }
10295
10296 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10297 switch (cond) {
10298 // Note some conditions are synonyms for others
10299 case Assembler::zero: return Assembler::notZero;
10300 case Assembler::notZero: return Assembler::zero;
10301 case Assembler::less: return Assembler::greaterEqual;
10302 case Assembler::lessEqual: return Assembler::greater;
10303 case Assembler::greater: return Assembler::lessEqual;
10304 case Assembler::greaterEqual: return Assembler::less;
10305 case Assembler::below: return Assembler::aboveEqual;
10306 case Assembler::belowEqual: return Assembler::above;
10307 case Assembler::above: return Assembler::belowEqual;
10308 case Assembler::aboveEqual: return Assembler::below;
10309 case Assembler::overflow: return Assembler::noOverflow;
10310 case Assembler::noOverflow: return Assembler::overflow;
10311 case Assembler::negative: return Assembler::positive;
10312 case Assembler::positive: return Assembler::negative;
10313 case Assembler::parity: return Assembler::noParity;
10314 case Assembler::noParity: return Assembler::parity;
10315 }
10316 ShouldNotReachHere(); return Assembler::overflow;
10317 }
10318
10319 // This is simply a call to Thread::current()
10320 void MacroAssembler::get_thread_slow(Register thread) {
10321 if (thread != rax) {
10322 push(rax);
10323 }
10324 push(rdi);
10325 push(rsi);
10326 push(rdx);
10327 push(rcx);
10328 push(r8);
10329 push(r9);
10330 push(r10);
10331 push(r11);
10332
10333 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10334
10335 pop(r11);
10336 pop(r10);
10337 pop(r9);
10338 pop(r8);
10339 pop(rcx);
10340 pop(rdx);
10341 pop(rsi);
10342 pop(rdi);
10343 if (thread != rax) {
10344 mov(thread, rax);
10345 pop(rax);
10346 }
10347 }
10348
10349 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10350 Label L_stack_ok;
10351 if (bias == 0) {
10352 testptr(sp, 2 * wordSize - 1);
10353 } else {
10354 // lea(tmp, Address(rsp, bias);
10355 mov(tmp, sp);
10356 addptr(tmp, bias);
10357 testptr(tmp, 2 * wordSize - 1);
10358 }
10359 jcc(Assembler::equal, L_stack_ok);
10360 block_comment(msg);
10361 stop(msg);
10362 bind(L_stack_ok);
10363 }
10364
10365 // Implements lightweight-locking.
10366 //
10367 // obj: the object to be locked
10368 // reg_rax: rax
10369 // thread: the thread which attempts to lock obj
10370 // tmp: a temporary register
10371 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow) {
10372 Register thread = r15_thread;
10373
10374 assert(reg_rax == rax, "");
10375 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10376
10377 Label push;
10378 const Register top = tmp;
10379
10380 // Preload the markWord. It is important that this is the first
10381 // instruction emitted as it is part of C1's null check semantics.
10382 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10383
10384 if (UseObjectMonitorTable) {
10385 // Clear cache in case fast locking succeeds or we need to take the slow-path.
10386 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10387 }
10388
10389 if (DiagnoseSyncOnValueBasedClasses != 0) {
10390 load_klass(tmp, obj, rscratch1);
10391 testb(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
10392 jcc(Assembler::notZero, slow);
10393 }
10394
10395 // Load top.
10396 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10397
10398 // Check if the lock-stack is full.
10399 cmpl(top, LockStack::end_offset());
10400 jcc(Assembler::greaterEqual, slow);
10401
10402 // Check for recursion.
10403 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10404 jcc(Assembler::equal, push);
10405
10406 // Check header for monitor (0b10).
10407 testptr(reg_rax, markWord::monitor_value);
10408 jcc(Assembler::notZero, slow);
10409
10410 // Try to lock. Transition lock bits 0b01 => 0b00
10411 movptr(tmp, reg_rax);
10412 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10413 orptr(reg_rax, markWord::unlocked_value);
10414 if (EnableValhalla) {
10415 // Mask inline_type bit such that we go to the slow path if object is an inline type
10416 andptr(reg_rax, ~((int) markWord::inline_type_bit_in_place));
10417 }
10418 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10419 jcc(Assembler::notEqual, slow);
10420
10421 // Restore top, CAS clobbers register.
10422 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10423
10424 bind(push);
10425 // After successful lock, push object on lock-stack.
10426 movptr(Address(thread, top), obj);
10427 incrementl(top, oopSize);
10428 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10429 }
10430
10431 // Implements lightweight-unlocking.
10432 //
10433 // obj: the object to be unlocked
10434 // reg_rax: rax
10435 // thread: the thread
10436 // tmp: a temporary register
10437 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register tmp, Label& slow) {
10438 Register thread = r15_thread;
10439
10440 assert(reg_rax == rax, "");
10441 assert_different_registers(obj, reg_rax, thread, tmp);
10442
10443 Label unlocked, push_and_slow;
10444 const Register top = tmp;
10445
10446 // Check if obj is top of lock-stack.
10447 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10448 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10449 jcc(Assembler::notEqual, slow);
10450
10451 // Pop lock-stack.
10452 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10453 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10454
10455 // Check if recursive.
10456 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10457 jcc(Assembler::equal, unlocked);
10458
10459 // Not recursive. Check header for monitor (0b10).
10460 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10461 testptr(reg_rax, markWord::monitor_value);
10462 jcc(Assembler::notZero, push_and_slow);
10463
10464 #ifdef ASSERT
10465 // Check header not unlocked (0b01).
10466 Label not_unlocked;
10467 testptr(reg_rax, markWord::unlocked_value);
10468 jcc(Assembler::zero, not_unlocked);
10469 stop("lightweight_unlock already unlocked");
10470 bind(not_unlocked);
10471 #endif
10472
10473 // Try to unlock. Transition lock bits 0b00 => 0b01
10474 movptr(tmp, reg_rax);
10475 orptr(tmp, markWord::unlocked_value);
10476 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10477 jcc(Assembler::equal, unlocked);
10478
10479 bind(push_and_slow);
10480 // Restore lock-stack and handle the unlock in runtime.
10481 #ifdef ASSERT
10482 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10483 movptr(Address(thread, top), obj);
10484 #endif
10485 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10486 jmp(slow);
10487
10488 bind(unlocked);
10489 }
10490
10491 // Saves legacy GPRs state on stack.
10492 void MacroAssembler::save_legacy_gprs() {
10493 subq(rsp, 16 * wordSize);
10494 movq(Address(rsp, 15 * wordSize), rax);
10495 movq(Address(rsp, 14 * wordSize), rcx);
10496 movq(Address(rsp, 13 * wordSize), rdx);
10497 movq(Address(rsp, 12 * wordSize), rbx);
10498 movq(Address(rsp, 10 * wordSize), rbp);
10499 movq(Address(rsp, 9 * wordSize), rsi);
10500 movq(Address(rsp, 8 * wordSize), rdi);
10501 movq(Address(rsp, 7 * wordSize), r8);
10502 movq(Address(rsp, 6 * wordSize), r9);
10503 movq(Address(rsp, 5 * wordSize), r10);
10504 movq(Address(rsp, 4 * wordSize), r11);
10505 movq(Address(rsp, 3 * wordSize), r12);
10506 movq(Address(rsp, 2 * wordSize), r13);
10507 movq(Address(rsp, wordSize), r14);
10508 movq(Address(rsp, 0), r15);
10509 }
10510
10511 // Resotres back legacy GPRs state from stack.
10512 void MacroAssembler::restore_legacy_gprs() {
10513 movq(r15, Address(rsp, 0));
10514 movq(r14, Address(rsp, wordSize));
10515 movq(r13, Address(rsp, 2 * wordSize));
10516 movq(r12, Address(rsp, 3 * wordSize));
10517 movq(r11, Address(rsp, 4 * wordSize));
10518 movq(r10, Address(rsp, 5 * wordSize));
10519 movq(r9, Address(rsp, 6 * wordSize));
10520 movq(r8, Address(rsp, 7 * wordSize));
10521 movq(rdi, Address(rsp, 8 * wordSize));
10522 movq(rsi, Address(rsp, 9 * wordSize));
10523 movq(rbp, Address(rsp, 10 * wordSize));
10524 movq(rbx, Address(rsp, 12 * wordSize));
10525 movq(rdx, Address(rsp, 13 * wordSize));
10526 movq(rcx, Address(rsp, 14 * wordSize));
10527 movq(rax, Address(rsp, 15 * wordSize));
10528 addq(rsp, 16 * wordSize);
10529 }
10530
10531 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10532 if (VM_Version::supports_apx_f()) {
10533 esetzucc(comparison, dst);
10534 } else {
10535 setb(comparison, dst);
10536 movzbl(dst, dst);
10537 }
10538 }