1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/aotCodeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "ci/ciInlineKlass.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "interpreter/interpreterRuntime.hpp"
40 #include "jvm.h"
41 #include "memory/resourceArea.hpp"
42 #include "memory/universe.hpp"
43 #include "oops/accessDecorators.hpp"
44 #include "oops/compressedKlass.inline.hpp"
45 #include "oops/compressedOops.inline.hpp"
46 #include "oops/klass.inline.hpp"
47 #include "oops/resolvedFieldEntry.hpp"
48 #include "prims/methodHandles.hpp"
49 #include "runtime/arguments.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/interfaceSupport.inline.hpp"
52 #include "runtime/javaThread.hpp"
53 #include "runtime/jniHandles.hpp"
54 #include "runtime/objectMonitor.hpp"
55 #include "runtime/os.hpp"
56 #include "runtime/safepoint.hpp"
57 #include "runtime/safepointMechanism.hpp"
58 #include "runtime/sharedRuntime.hpp"
59 #include "runtime/signature_cc.hpp"
60 #include "runtime/stubRoutines.hpp"
61 #include "utilities/checkedCast.hpp"
62 #include "utilities/globalDefinitions.hpp"
63 #include "utilities/macros.hpp"
64 #include "vmreg_x86.inline.hpp"
65 #ifdef COMPILER2
66 #include "opto/output.hpp"
67 #endif
68
69 #ifdef PRODUCT
70 #define BLOCK_COMMENT(str) /* nothing */
71 #define STOP(error) stop(error)
72 #else
73 #define BLOCK_COMMENT(str) block_comment(str)
74 #define STOP(error) block_comment(error); stop(error)
75 #endif
76
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
79 #ifdef ASSERT
80 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
81 #endif
82
83 static const Assembler::Condition reverse[] = {
84 Assembler::noOverflow /* overflow = 0x0 */ ,
85 Assembler::overflow /* noOverflow = 0x1 */ ,
86 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
87 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
88 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
89 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
90 Assembler::above /* belowEqual = 0x6 */ ,
91 Assembler::belowEqual /* above = 0x7 */ ,
92 Assembler::positive /* negative = 0x8 */ ,
93 Assembler::negative /* positive = 0x9 */ ,
94 Assembler::noParity /* parity = 0xa */ ,
95 Assembler::parity /* noParity = 0xb */ ,
96 Assembler::greaterEqual /* less = 0xc */ ,
97 Assembler::less /* greaterEqual = 0xd */ ,
98 Assembler::greater /* lessEqual = 0xe */ ,
99 Assembler::lessEqual /* greater = 0xf, */
100
101 };
102
103
104 // Implementation of MacroAssembler
105
106 Address MacroAssembler::as_Address(AddressLiteral adr) {
107 // amd64 always does this as a pc-rel
108 // we can be absolute or disp based on the instruction type
109 // jmp/call are displacements others are absolute
110 assert(!adr.is_lval(), "must be rval");
111 assert(reachable(adr), "must be");
112 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
113
114 }
115
116 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
117 AddressLiteral base = adr.base();
118 lea(rscratch, base);
119 Address index = adr.index();
120 assert(index._disp == 0, "must not have disp"); // maybe it can?
121 Address array(rscratch, index._index, index._scale, index._disp);
122 return array;
123 }
124
125 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
126 Label L, E;
127
128 #ifdef _WIN64
129 // Windows always allocates space for it's register args
130 assert(num_args <= 4, "only register arguments supported");
131 subq(rsp, frame::arg_reg_save_area_bytes);
132 #endif
133
134 // Align stack if necessary
135 testl(rsp, 15);
136 jcc(Assembler::zero, L);
137
138 subq(rsp, 8);
139 call(RuntimeAddress(entry_point));
140 addq(rsp, 8);
141 jmp(E);
142
143 bind(L);
144 call(RuntimeAddress(entry_point));
145
146 bind(E);
147
148 #ifdef _WIN64
149 // restore stack pointer
150 addq(rsp, frame::arg_reg_save_area_bytes);
151 #endif
152 }
153
154 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
155 assert(!src2.is_lval(), "should use cmpptr");
156 assert(rscratch != noreg || always_reachable(src2), "missing");
157
158 if (reachable(src2)) {
159 cmpq(src1, as_Address(src2));
160 } else {
161 lea(rscratch, src2);
162 Assembler::cmpq(src1, Address(rscratch, 0));
163 }
164 }
165
166 int MacroAssembler::corrected_idivq(Register reg) {
167 // Full implementation of Java ldiv and lrem; checks for special
168 // case as described in JVM spec., p.243 & p.271. The function
169 // returns the (pc) offset of the idivl instruction - may be needed
170 // for implicit exceptions.
171 //
172 // normal case special case
173 //
174 // input : rax: dividend min_long
175 // reg: divisor (may not be eax/edx) -1
176 //
177 // output: rax: quotient (= rax idiv reg) min_long
178 // rdx: remainder (= rax irem reg) 0
179 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
180 static const int64_t min_long = 0x8000000000000000;
181 Label normal_case, special_case;
182
183 // check for special case
184 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
185 jcc(Assembler::notEqual, normal_case);
186 xorl(rdx, rdx); // prepare rdx for possible special case (where
187 // remainder = 0)
188 cmpq(reg, -1);
189 jcc(Assembler::equal, special_case);
190
191 // handle normal case
192 bind(normal_case);
193 cdqq();
194 int idivq_offset = offset();
195 idivq(reg);
196
197 // normal and special case exit
198 bind(special_case);
199
200 return idivq_offset;
201 }
202
203 void MacroAssembler::decrementq(Register reg, int value) {
204 if (value == min_jint) { subq(reg, value); return; }
205 if (value < 0) { incrementq(reg, -value); return; }
206 if (value == 0) { ; return; }
207 if (value == 1 && UseIncDec) { decq(reg) ; return; }
208 /* else */ { subq(reg, value) ; return; }
209 }
210
211 void MacroAssembler::decrementq(Address dst, int value) {
212 if (value == min_jint) { subq(dst, value); return; }
213 if (value < 0) { incrementq(dst, -value); return; }
214 if (value == 0) { ; return; }
215 if (value == 1 && UseIncDec) { decq(dst) ; return; }
216 /* else */ { subq(dst, value) ; return; }
217 }
218
219 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
220 assert(rscratch != noreg || always_reachable(dst), "missing");
221
222 if (reachable(dst)) {
223 incrementq(as_Address(dst));
224 } else {
225 lea(rscratch, dst);
226 incrementq(Address(rscratch, 0));
227 }
228 }
229
230 void MacroAssembler::incrementq(Register reg, int value) {
231 if (value == min_jint) { addq(reg, value); return; }
232 if (value < 0) { decrementq(reg, -value); return; }
233 if (value == 0) { ; return; }
234 if (value == 1 && UseIncDec) { incq(reg) ; return; }
235 /* else */ { addq(reg, value) ; return; }
236 }
237
238 void MacroAssembler::incrementq(Address dst, int value) {
239 if (value == min_jint) { addq(dst, value); return; }
240 if (value < 0) { decrementq(dst, -value); return; }
241 if (value == 0) { ; return; }
242 if (value == 1 && UseIncDec) { incq(dst) ; return; }
243 /* else */ { addq(dst, value) ; return; }
244 }
245
246 // 32bit can do a case table jump in one instruction but we no longer allow the base
247 // to be installed in the Address class
248 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
249 lea(rscratch, entry.base());
250 Address dispatch = entry.index();
251 assert(dispatch._base == noreg, "must be");
252 dispatch._base = rscratch;
253 jmp(dispatch);
254 }
255
256 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
257 ShouldNotReachHere(); // 64bit doesn't use two regs
258 cmpq(x_lo, y_lo);
259 }
260
261 void MacroAssembler::lea(Register dst, AddressLiteral src) {
262 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
263 }
264
265 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
266 lea(rscratch, adr);
267 movptr(dst, rscratch);
268 }
269
270 void MacroAssembler::leave() {
271 // %%% is this really better? Why not on 32bit too?
272 emit_int8((unsigned char)0xC9); // LEAVE
273 }
274
275 void MacroAssembler::lneg(Register hi, Register lo) {
276 ShouldNotReachHere(); // 64bit doesn't use two regs
277 negq(lo);
278 }
279
280 void MacroAssembler::movoop(Register dst, jobject obj) {
281 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
282 }
283
284 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
285 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
286 movq(dst, rscratch);
287 }
288
289 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
290 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
291 }
292
293 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
294 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
295 movq(dst, rscratch);
296 }
297
298 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
299 if (src.is_lval()) {
300 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
301 } else {
302 if (reachable(src)) {
303 movq(dst, as_Address(src));
304 } else {
305 lea(dst, src);
306 movq(dst, Address(dst, 0));
307 }
308 }
309 }
310
311 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
312 movq(as_Address(dst, rscratch), src);
313 }
314
315 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
316 movq(dst, as_Address(src, dst /*rscratch*/));
317 }
318
319 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
320 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
321 if (is_simm32(src)) {
322 movptr(dst, checked_cast<int32_t>(src));
323 } else {
324 mov64(rscratch, src);
325 movq(dst, rscratch);
326 }
327 }
328
329 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
330 movoop(rscratch, obj);
331 push(rscratch);
332 }
333
334 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
335 mov_metadata(rscratch, obj);
336 push(rscratch);
337 }
338
339 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
340 lea(rscratch, src);
341 if (src.is_lval()) {
342 push(rscratch);
343 } else {
344 pushq(Address(rscratch, 0));
345 }
346 }
347
348 static void pass_arg0(MacroAssembler* masm, Register arg) {
349 if (c_rarg0 != arg ) {
350 masm->mov(c_rarg0, arg);
351 }
352 }
353
354 static void pass_arg1(MacroAssembler* masm, Register arg) {
355 if (c_rarg1 != arg ) {
356 masm->mov(c_rarg1, arg);
357 }
358 }
359
360 static void pass_arg2(MacroAssembler* masm, Register arg) {
361 if (c_rarg2 != arg ) {
362 masm->mov(c_rarg2, arg);
363 }
364 }
365
366 static void pass_arg3(MacroAssembler* masm, Register arg) {
367 if (c_rarg3 != arg ) {
368 masm->mov(c_rarg3, arg);
369 }
370 }
371
372 void MacroAssembler::stop(const char* msg) {
373 if (ShowMessageBoxOnError) {
374 address rip = pc();
375 pusha(); // get regs on stack
376 lea(c_rarg1, InternalAddress(rip));
377 movq(c_rarg2, rsp); // pass pointer to regs array
378 }
379 // Skip AOT caching C strings in scratch buffer.
380 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
381 lea(c_rarg0, ExternalAddress((address) str));
382 andq(rsp, -16); // align stack as required by ABI
383 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
384 hlt();
385 }
386
387 void MacroAssembler::warn(const char* msg) {
388 push(rbp);
389 movq(rbp, rsp);
390 andq(rsp, -16); // align stack as required by push_CPU_state and call
391 push_CPU_state(); // keeps alignment at 16 bytes
392
393 #ifdef _WIN64
394 // Windows always allocates space for its register args
395 subq(rsp, frame::arg_reg_save_area_bytes);
396 #endif
397 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
398 lea(c_rarg0, ExternalAddress((address) str));
399 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
400
401 #ifdef _WIN64
402 // restore stack pointer
403 addq(rsp, frame::arg_reg_save_area_bytes);
404 #endif
405 pop_CPU_state();
406 mov(rsp, rbp);
407 pop(rbp);
408 }
409
410 void MacroAssembler::print_state() {
411 address rip = pc();
412 pusha(); // get regs on stack
413 push(rbp);
414 movq(rbp, rsp);
415 andq(rsp, -16); // align stack as required by push_CPU_state and call
416 push_CPU_state(); // keeps alignment at 16 bytes
417
418 lea(c_rarg0, InternalAddress(rip));
419 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
420 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
421
422 pop_CPU_state();
423 mov(rsp, rbp);
424 pop(rbp);
425 popa();
426 }
427
428 #ifndef PRODUCT
429 extern "C" void findpc(intptr_t x);
430 #endif
431
432 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
433 // In order to get locks to work, we need to fake a in_VM state
434 if (ShowMessageBoxOnError) {
435 JavaThread* thread = JavaThread::current();
436 JavaThreadState saved_state = thread->thread_state();
437 thread->set_thread_state(_thread_in_vm);
438 #ifndef PRODUCT
439 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
440 ttyLocker ttyl;
441 BytecodeCounter::print();
442 }
443 #endif
444 // To see where a verify_oop failed, get $ebx+40/X for this frame.
445 // XXX correct this offset for amd64
446 // This is the value of eip which points to where verify_oop will return.
447 if (os::message_box(msg, "Execution stopped, print registers?")) {
448 print_state64(pc, regs);
449 BREAKPOINT;
450 }
451 }
452 fatal("DEBUG MESSAGE: %s", msg);
453 }
454
455 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
456 ttyLocker ttyl;
457 DebuggingContext debugging{};
458 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
459 #ifndef PRODUCT
460 tty->cr();
461 findpc(pc);
462 tty->cr();
463 #endif
464 #define PRINT_REG(rax, value) \
465 { tty->print("%s = ", #rax); os::print_location(tty, value); }
466 PRINT_REG(rax, regs[15]);
467 PRINT_REG(rbx, regs[12]);
468 PRINT_REG(rcx, regs[14]);
469 PRINT_REG(rdx, regs[13]);
470 PRINT_REG(rdi, regs[8]);
471 PRINT_REG(rsi, regs[9]);
472 PRINT_REG(rbp, regs[10]);
473 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
474 PRINT_REG(rsp, (intptr_t)(®s[16]));
475 PRINT_REG(r8 , regs[7]);
476 PRINT_REG(r9 , regs[6]);
477 PRINT_REG(r10, regs[5]);
478 PRINT_REG(r11, regs[4]);
479 PRINT_REG(r12, regs[3]);
480 PRINT_REG(r13, regs[2]);
481 PRINT_REG(r14, regs[1]);
482 PRINT_REG(r15, regs[0]);
483 #undef PRINT_REG
484 // Print some words near the top of the stack.
485 int64_t* rsp = ®s[16];
486 int64_t* dump_sp = rsp;
487 for (int col1 = 0; col1 < 8; col1++) {
488 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
489 os::print_location(tty, *dump_sp++);
490 }
491 for (int row = 0; row < 25; row++) {
492 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
493 for (int col = 0; col < 4; col++) {
494 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
495 }
496 tty->cr();
497 }
498 // Print some instructions around pc:
499 Disassembler::decode((address)pc-64, (address)pc);
500 tty->print_cr("--------");
501 Disassembler::decode((address)pc, (address)pc+32);
502 }
503
504 // The java_calling_convention describes stack locations as ideal slots on
505 // a frame with no abi restrictions. Since we must observe abi restrictions
506 // (like the placement of the register window) the slots must be biased by
507 // the following value.
508 static int reg2offset_in(VMReg r) {
509 // Account for saved rbp and return address
510 // This should really be in_preserve_stack_slots
511 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
512 }
513
514 static int reg2offset_out(VMReg r) {
515 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
516 }
517
518 // A long move
519 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
520
521 // The calling conventions assures us that each VMregpair is either
522 // all really one physical register or adjacent stack slots.
523
524 if (src.is_single_phys_reg() ) {
525 if (dst.is_single_phys_reg()) {
526 if (dst.first() != src.first()) {
527 mov(dst.first()->as_Register(), src.first()->as_Register());
528 }
529 } else {
530 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
531 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
532 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
533 }
534 } else if (dst.is_single_phys_reg()) {
535 assert(src.is_single_reg(), "not a stack pair");
536 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
537 } else {
538 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
539 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
540 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
541 }
542 }
543
544 // A double move
545 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
546
547 // The calling conventions assures us that each VMregpair is either
548 // all really one physical register or adjacent stack slots.
549
550 if (src.is_single_phys_reg() ) {
551 if (dst.is_single_phys_reg()) {
552 // In theory these overlap but the ordering is such that this is likely a nop
553 if ( src.first() != dst.first()) {
554 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
555 }
556 } else {
557 assert(dst.is_single_reg(), "not a stack pair");
558 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
559 }
560 } else if (dst.is_single_phys_reg()) {
561 assert(src.is_single_reg(), "not a stack pair");
562 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
563 } else {
564 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
565 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
566 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
567 }
568 }
569
570
571 // A float arg may have to do float reg int reg conversion
572 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
573 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
574
575 // The calling conventions assures us that each VMregpair is either
576 // all really one physical register or adjacent stack slots.
577
578 if (src.first()->is_stack()) {
579 if (dst.first()->is_stack()) {
580 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
581 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
582 } else {
583 // stack to reg
584 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
585 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
586 }
587 } else if (dst.first()->is_stack()) {
588 // reg to stack
589 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
590 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
591 } else {
592 // reg to reg
593 // In theory these overlap but the ordering is such that this is likely a nop
594 if ( src.first() != dst.first()) {
595 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
596 }
597 }
598 }
599
600 // On 64 bit we will store integer like items to the stack as
601 // 64 bits items (x86_32/64 abi) even though java would only store
602 // 32bits for a parameter. On 32bit it will simply be 32 bits
603 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
604 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
605 if (src.first()->is_stack()) {
606 if (dst.first()->is_stack()) {
607 // stack to stack
608 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
609 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
610 } else {
611 // stack to reg
612 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
613 }
614 } else if (dst.first()->is_stack()) {
615 // reg to stack
616 // Do we really have to sign extend???
617 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
618 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
619 } else {
620 // Do we really have to sign extend???
621 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
622 if (dst.first() != src.first()) {
623 movq(dst.first()->as_Register(), src.first()->as_Register());
624 }
625 }
626 }
627
628 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
629 if (src.first()->is_stack()) {
630 if (dst.first()->is_stack()) {
631 // stack to stack
632 movq(rax, Address(rbp, reg2offset_in(src.first())));
633 movq(Address(rsp, reg2offset_out(dst.first())), rax);
634 } else {
635 // stack to reg
636 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
637 }
638 } else if (dst.first()->is_stack()) {
639 // reg to stack
640 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
641 } else {
642 if (dst.first() != src.first()) {
643 movq(dst.first()->as_Register(), src.first()->as_Register());
644 }
645 }
646 }
647
648 // An oop arg. Must pass a handle not the oop itself
649 void MacroAssembler::object_move(OopMap* map,
650 int oop_handle_offset,
651 int framesize_in_slots,
652 VMRegPair src,
653 VMRegPair dst,
654 bool is_receiver,
655 int* receiver_offset) {
656
657 // must pass a handle. First figure out the location we use as a handle
658
659 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
660
661 // See if oop is null if it is we need no handle
662
663 if (src.first()->is_stack()) {
664
665 // Oop is already on the stack as an argument
666 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
667 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
668 if (is_receiver) {
669 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
670 }
671
672 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
673 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
674 // conditionally move a null
675 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
676 } else {
677
678 // Oop is in a register we must store it to the space we reserve
679 // on the stack for oop_handles and pass a handle if oop is non-null
680
681 const Register rOop = src.first()->as_Register();
682 int oop_slot;
683 if (rOop == j_rarg0)
684 oop_slot = 0;
685 else if (rOop == j_rarg1)
686 oop_slot = 1;
687 else if (rOop == j_rarg2)
688 oop_slot = 2;
689 else if (rOop == j_rarg3)
690 oop_slot = 3;
691 else if (rOop == j_rarg4)
692 oop_slot = 4;
693 else {
694 assert(rOop == j_rarg5, "wrong register");
695 oop_slot = 5;
696 }
697
698 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
699 int offset = oop_slot*VMRegImpl::stack_slot_size;
700
701 map->set_oop(VMRegImpl::stack2reg(oop_slot));
702 // Store oop in handle area, may be null
703 movptr(Address(rsp, offset), rOop);
704 if (is_receiver) {
705 *receiver_offset = offset;
706 }
707
708 cmpptr(rOop, NULL_WORD);
709 lea(rHandle, Address(rsp, offset));
710 // conditionally move a null from the handle area where it was just stored
711 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
712 }
713
714 // If arg is on the stack then place it otherwise it is already in correct reg.
715 if (dst.first()->is_stack()) {
716 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
717 }
718 }
719
720 void MacroAssembler::addptr(Register dst, int32_t imm32) {
721 addq(dst, imm32);
722 }
723
724 void MacroAssembler::addptr(Register dst, Register src) {
725 addq(dst, src);
726 }
727
728 void MacroAssembler::addptr(Address dst, Register src) {
729 addq(dst, src);
730 }
731
732 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
733 assert(rscratch != noreg || always_reachable(src), "missing");
734
735 if (reachable(src)) {
736 Assembler::addsd(dst, as_Address(src));
737 } else {
738 lea(rscratch, src);
739 Assembler::addsd(dst, Address(rscratch, 0));
740 }
741 }
742
743 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
744 assert(rscratch != noreg || always_reachable(src), "missing");
745
746 if (reachable(src)) {
747 addss(dst, as_Address(src));
748 } else {
749 lea(rscratch, src);
750 addss(dst, Address(rscratch, 0));
751 }
752 }
753
754 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
755 assert(rscratch != noreg || always_reachable(src), "missing");
756
757 if (reachable(src)) {
758 Assembler::addpd(dst, as_Address(src));
759 } else {
760 lea(rscratch, src);
761 Assembler::addpd(dst, Address(rscratch, 0));
762 }
763 }
764
765 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
766 // Stub code is generated once and never copied.
767 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
768 void MacroAssembler::align64() {
769 align(64, (uint)(uintptr_t)pc());
770 }
771
772 void MacroAssembler::align32() {
773 align(32, (uint)(uintptr_t)pc());
774 }
775
776 void MacroAssembler::align(uint modulus) {
777 // 8273459: Ensure alignment is possible with current segment alignment
778 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
779 align(modulus, offset());
780 }
781
782 void MacroAssembler::align(uint modulus, uint target) {
783 if (target % modulus != 0) {
784 nop(modulus - (target % modulus));
785 }
786 }
787
788 void MacroAssembler::push_f(XMMRegister r) {
789 subptr(rsp, wordSize);
790 movflt(Address(rsp, 0), r);
791 }
792
793 void MacroAssembler::pop_f(XMMRegister r) {
794 movflt(r, Address(rsp, 0));
795 addptr(rsp, wordSize);
796 }
797
798 void MacroAssembler::push_d(XMMRegister r) {
799 subptr(rsp, 2 * wordSize);
800 movdbl(Address(rsp, 0), r);
801 }
802
803 void MacroAssembler::pop_d(XMMRegister r) {
804 movdbl(r, Address(rsp, 0));
805 addptr(rsp, 2 * Interpreter::stackElementSize);
806 }
807
808 void MacroAssembler::push_ppx(Register src) {
809 if (VM_Version::supports_apx_f()) {
810 pushp(src);
811 } else {
812 Assembler::push(src);
813 }
814 }
815
816 void MacroAssembler::pop_ppx(Register dst) {
817 if (VM_Version::supports_apx_f()) {
818 popp(dst);
819 } else {
820 Assembler::pop(dst);
821 }
822 }
823
824 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
825 // Used in sign-masking with aligned address.
826 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
827 assert(rscratch != noreg || always_reachable(src), "missing");
828
829 if (UseAVX > 2 &&
830 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
831 (dst->encoding() >= 16)) {
832 vpand(dst, dst, src, AVX_512bit, rscratch);
833 } else if (reachable(src)) {
834 Assembler::andpd(dst, as_Address(src));
835 } else {
836 lea(rscratch, src);
837 Assembler::andpd(dst, Address(rscratch, 0));
838 }
839 }
840
841 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
842 // Used in sign-masking with aligned address.
843 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
844 assert(rscratch != noreg || always_reachable(src), "missing");
845
846 if (reachable(src)) {
847 Assembler::andps(dst, as_Address(src));
848 } else {
849 lea(rscratch, src);
850 Assembler::andps(dst, Address(rscratch, 0));
851 }
852 }
853
854 void MacroAssembler::andptr(Register dst, int32_t imm32) {
855 andq(dst, imm32);
856 }
857
858 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
859 assert(rscratch != noreg || always_reachable(src), "missing");
860
861 if (reachable(src)) {
862 andq(dst, as_Address(src));
863 } else {
864 lea(rscratch, src);
865 andq(dst, Address(rscratch, 0));
866 }
867 }
868
869 void MacroAssembler::atomic_incl(Address counter_addr) {
870 lock();
871 incrementl(counter_addr);
872 }
873
874 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
875 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
876
877 if (reachable(counter_addr)) {
878 atomic_incl(as_Address(counter_addr));
879 } else {
880 lea(rscratch, counter_addr);
881 atomic_incl(Address(rscratch, 0));
882 }
883 }
884
885 void MacroAssembler::atomic_incq(Address counter_addr) {
886 lock();
887 incrementq(counter_addr);
888 }
889
890 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
891 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
892
893 if (reachable(counter_addr)) {
894 atomic_incq(as_Address(counter_addr));
895 } else {
896 lea(rscratch, counter_addr);
897 atomic_incq(Address(rscratch, 0));
898 }
899 }
900
901 // Writes to stack successive pages until offset reached to check for
902 // stack overflow + shadow pages. This clobbers tmp.
903 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
904 movptr(tmp, rsp);
905 // Bang stack for total size given plus shadow page size.
906 // Bang one page at a time because large size can bang beyond yellow and
907 // red zones.
908 Label loop;
909 bind(loop);
910 movl(Address(tmp, (-(int)os::vm_page_size())), size );
911 subptr(tmp, (int)os::vm_page_size());
912 subl(size, (int)os::vm_page_size());
913 jcc(Assembler::greater, loop);
914
915 // Bang down shadow pages too.
916 // At this point, (tmp-0) is the last address touched, so don't
917 // touch it again. (It was touched as (tmp-pagesize) but then tmp
918 // was post-decremented.) Skip this address by starting at i=1, and
919 // touch a few more pages below. N.B. It is important to touch all
920 // the way down including all pages in the shadow zone.
921 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
922 // this could be any sized move but this is can be a debugging crumb
923 // so the bigger the better.
924 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
925 }
926 }
927
928 void MacroAssembler::reserved_stack_check() {
929 // testing if reserved zone needs to be enabled
930 Label no_reserved_zone_enabling;
931
932 cmpptr(rsp, Address(r15_thread, JavaThread::reserved_stack_activation_offset()));
933 jcc(Assembler::below, no_reserved_zone_enabling);
934
935 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), r15_thread);
936 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
937 should_not_reach_here();
938
939 bind(no_reserved_zone_enabling);
940 }
941
942 void MacroAssembler::c2bool(Register x) {
943 // implements x == 0 ? 0 : 1
944 // note: must only look at least-significant byte of x
945 // since C-style booleans are stored in one byte
946 // only! (was bug)
947 andl(x, 0xFF);
948 setb(Assembler::notZero, x);
949 }
950
951 // Wouldn't need if AddressLiteral version had new name
952 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
953 Assembler::call(L, rtype);
954 }
955
956 void MacroAssembler::call(Register entry) {
957 Assembler::call(entry);
958 }
959
960 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
961 assert(rscratch != noreg || always_reachable(entry), "missing");
962
963 if (reachable(entry)) {
964 Assembler::call_literal(entry.target(), entry.rspec());
965 } else {
966 lea(rscratch, entry);
967 Assembler::call(rscratch);
968 }
969 }
970
971 void MacroAssembler::ic_call(address entry, jint method_index) {
972 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
973 // Needs full 64-bit immediate for later patching.
974 Assembler::mov64(rax, (int64_t)Universe::non_oop_word());
975 call(AddressLiteral(entry, rh));
976 }
977
978 int MacroAssembler::ic_check_size() {
979 return UseCompactObjectHeaders ? 17 : 14;
980 }
981
982 int MacroAssembler::ic_check(int end_alignment) {
983 Register receiver = j_rarg0;
984 Register data = rax;
985 Register temp = rscratch1;
986
987 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
988 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
989 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
990 // before the inline cache check here, and not after
991 align(end_alignment, offset() + ic_check_size());
992
993 int uep_offset = offset();
994
995 if (UseCompactObjectHeaders) {
996 load_narrow_klass_compact(temp, receiver);
997 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
998 } else {
999 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1000 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1001 }
1002
1003 // if inline cache check fails, then jump to runtime routine
1004 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1005 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1006
1007 return uep_offset;
1008 }
1009
1010 void MacroAssembler::emit_static_call_stub() {
1011 // Static stub relocation also tags the Method* in the code-stream.
1012 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1013 // This is recognized as unresolved by relocs/nativeinst/ic code.
1014 jump(RuntimeAddress(pc()));
1015 }
1016
1017 // Implementation of call_VM versions
1018
1019 void MacroAssembler::call_VM(Register oop_result,
1020 address entry_point,
1021 bool check_exceptions) {
1022 Label C, E;
1023 call(C, relocInfo::none);
1024 jmp(E);
1025
1026 bind(C);
1027 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1028 ret(0);
1029
1030 bind(E);
1031 }
1032
1033 void MacroAssembler::call_VM(Register oop_result,
1034 address entry_point,
1035 Register arg_1,
1036 bool check_exceptions) {
1037 Label C, E;
1038 call(C, relocInfo::none);
1039 jmp(E);
1040
1041 bind(C);
1042 pass_arg1(this, arg_1);
1043 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1044 ret(0);
1045
1046 bind(E);
1047 }
1048
1049 void MacroAssembler::call_VM(Register oop_result,
1050 address entry_point,
1051 Register arg_1,
1052 Register arg_2,
1053 bool check_exceptions) {
1054 Label C, E;
1055 call(C, relocInfo::none);
1056 jmp(E);
1057
1058 bind(C);
1059
1060 assert_different_registers(arg_1, c_rarg2);
1061
1062 pass_arg2(this, arg_2);
1063 pass_arg1(this, arg_1);
1064 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1065 ret(0);
1066
1067 bind(E);
1068 }
1069
1070 void MacroAssembler::call_VM(Register oop_result,
1071 address entry_point,
1072 Register arg_1,
1073 Register arg_2,
1074 Register arg_3,
1075 bool check_exceptions) {
1076 Label C, E;
1077 call(C, relocInfo::none);
1078 jmp(E);
1079
1080 bind(C);
1081
1082 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1083 assert_different_registers(arg_2, c_rarg3);
1084 pass_arg3(this, arg_3);
1085 pass_arg2(this, arg_2);
1086 pass_arg1(this, arg_1);
1087 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1088 ret(0);
1089
1090 bind(E);
1091 }
1092
1093 void MacroAssembler::call_VM(Register oop_result,
1094 Register last_java_sp,
1095 address entry_point,
1096 int number_of_arguments,
1097 bool check_exceptions) {
1098 call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1099 }
1100
1101 void MacroAssembler::call_VM(Register oop_result,
1102 Register last_java_sp,
1103 address entry_point,
1104 Register arg_1,
1105 bool check_exceptions) {
1106 pass_arg1(this, arg_1);
1107 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1108 }
1109
1110 void MacroAssembler::call_VM(Register oop_result,
1111 Register last_java_sp,
1112 address entry_point,
1113 Register arg_1,
1114 Register arg_2,
1115 bool check_exceptions) {
1116
1117 assert_different_registers(arg_1, c_rarg2);
1118 pass_arg2(this, arg_2);
1119 pass_arg1(this, arg_1);
1120 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1121 }
1122
1123 void MacroAssembler::call_VM(Register oop_result,
1124 Register last_java_sp,
1125 address entry_point,
1126 Register arg_1,
1127 Register arg_2,
1128 Register arg_3,
1129 bool check_exceptions) {
1130 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1131 assert_different_registers(arg_2, c_rarg3);
1132 pass_arg3(this, arg_3);
1133 pass_arg2(this, arg_2);
1134 pass_arg1(this, arg_1);
1135 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1136 }
1137
1138 void MacroAssembler::super_call_VM(Register oop_result,
1139 Register last_java_sp,
1140 address entry_point,
1141 int number_of_arguments,
1142 bool check_exceptions) {
1143 MacroAssembler::call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1144 }
1145
1146 void MacroAssembler::super_call_VM(Register oop_result,
1147 Register last_java_sp,
1148 address entry_point,
1149 Register arg_1,
1150 bool check_exceptions) {
1151 pass_arg1(this, arg_1);
1152 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1153 }
1154
1155 void MacroAssembler::super_call_VM(Register oop_result,
1156 Register last_java_sp,
1157 address entry_point,
1158 Register arg_1,
1159 Register arg_2,
1160 bool check_exceptions) {
1161
1162 assert_different_registers(arg_1, c_rarg2);
1163 pass_arg2(this, arg_2);
1164 pass_arg1(this, arg_1);
1165 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1166 }
1167
1168 void MacroAssembler::super_call_VM(Register oop_result,
1169 Register last_java_sp,
1170 address entry_point,
1171 Register arg_1,
1172 Register arg_2,
1173 Register arg_3,
1174 bool check_exceptions) {
1175 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1176 assert_different_registers(arg_2, c_rarg3);
1177 pass_arg3(this, arg_3);
1178 pass_arg2(this, arg_2);
1179 pass_arg1(this, arg_1);
1180 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1181 }
1182
1183 void MacroAssembler::call_VM_base(Register oop_result,
1184 Register last_java_sp,
1185 address entry_point,
1186 int number_of_arguments,
1187 bool check_exceptions) {
1188 Register java_thread = r15_thread;
1189
1190 // determine last_java_sp register
1191 if (!last_java_sp->is_valid()) {
1192 last_java_sp = rsp;
1193 }
1194 // debugging support
1195 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1196 #ifdef ASSERT
1197 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1198 // r12 is the heapbase.
1199 if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
1200 #endif // ASSERT
1201
1202 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1203 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1204
1205 // push java thread (becomes first argument of C function)
1206
1207 mov(c_rarg0, r15_thread);
1208
1209 // set last Java frame before call
1210 assert(last_java_sp != rbp, "can't use ebp/rbp");
1211
1212 // Only interpreter should have to set fp
1213 set_last_Java_frame(last_java_sp, rbp, nullptr, rscratch1);
1214
1215 // do the call, remove parameters
1216 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1217
1218 #ifdef ASSERT
1219 // Check that thread register is not clobbered.
1220 guarantee(java_thread != rax, "change this code");
1221 push(rax);
1222 { Label L;
1223 get_thread_slow(rax);
1224 cmpptr(java_thread, rax);
1225 jcc(Assembler::equal, L);
1226 STOP("MacroAssembler::call_VM_base: java_thread not callee saved?");
1227 bind(L);
1228 }
1229 pop(rax);
1230 #endif
1231
1232 // reset last Java frame
1233 // Only interpreter should have to clear fp
1234 reset_last_Java_frame(true);
1235
1236 // C++ interp handles this in the interpreter
1237 check_and_handle_popframe();
1238 check_and_handle_earlyret();
1239
1240 if (check_exceptions) {
1241 // check for pending exceptions (java_thread is set upon return)
1242 cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
1243 // This used to conditionally jump to forward_exception however it is
1244 // possible if we relocate that the branch will not reach. So we must jump
1245 // around so we can always reach
1246
1247 Label ok;
1248 jcc(Assembler::equal, ok);
1249 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1250 bind(ok);
1251 }
1252
1253 // get oop result if there is one and reset the value in the thread
1254 if (oop_result->is_valid()) {
1255 get_vm_result_oop(oop_result);
1256 }
1257 }
1258
1259 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1260 // Calculate the value for last_Java_sp somewhat subtle.
1261 // call_VM does an intermediate call which places a return address on
1262 // the stack just under the stack pointer as the user finished with it.
1263 // This allows use to retrieve last_Java_pc from last_Java_sp[-1].
1264
1265 // We've pushed one address, correct last_Java_sp
1266 lea(rax, Address(rsp, wordSize));
1267
1268 call_VM_base(oop_result, rax, entry_point, number_of_arguments, check_exceptions);
1269 }
1270
1271 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1272 void MacroAssembler::call_VM_leaf0(address entry_point) {
1273 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1274 }
1275
1276 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1277 call_VM_leaf_base(entry_point, number_of_arguments);
1278 }
1279
1280 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1281 pass_arg0(this, arg_0);
1282 call_VM_leaf(entry_point, 1);
1283 }
1284
1285 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1286
1287 assert_different_registers(arg_0, c_rarg1);
1288 pass_arg1(this, arg_1);
1289 pass_arg0(this, arg_0);
1290 call_VM_leaf(entry_point, 2);
1291 }
1292
1293 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1294 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1295 assert_different_registers(arg_1, c_rarg2);
1296 pass_arg2(this, arg_2);
1297 pass_arg1(this, arg_1);
1298 pass_arg0(this, arg_0);
1299 call_VM_leaf(entry_point, 3);
1300 }
1301
1302 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1303 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1304 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1305 assert_different_registers(arg_2, c_rarg3);
1306 pass_arg3(this, arg_3);
1307 pass_arg2(this, arg_2);
1308 pass_arg1(this, arg_1);
1309 pass_arg0(this, arg_0);
1310 call_VM_leaf(entry_point, 3);
1311 }
1312
1313 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1314 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1315 }
1316
1317 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1318 pass_arg0(this, arg_0);
1319 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1320 }
1321
1322 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1323 assert_different_registers(arg_0, c_rarg1);
1324 pass_arg1(this, arg_1);
1325 pass_arg0(this, arg_0);
1326 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1327 }
1328
1329 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1330 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1331 assert_different_registers(arg_1, c_rarg2);
1332 pass_arg2(this, arg_2);
1333 pass_arg1(this, arg_1);
1334 pass_arg0(this, arg_0);
1335 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1336 }
1337
1338 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1339 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1340 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1341 assert_different_registers(arg_2, c_rarg3);
1342 pass_arg3(this, arg_3);
1343 pass_arg2(this, arg_2);
1344 pass_arg1(this, arg_1);
1345 pass_arg0(this, arg_0);
1346 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1347 }
1348
1349 void MacroAssembler::get_vm_result_oop(Register oop_result) {
1350 movptr(oop_result, Address(r15_thread, JavaThread::vm_result_oop_offset()));
1351 movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
1352 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1353 }
1354
1355 void MacroAssembler::get_vm_result_metadata(Register metadata_result) {
1356 movptr(metadata_result, Address(r15_thread, JavaThread::vm_result_metadata_offset()));
1357 movptr(Address(r15_thread, JavaThread::vm_result_metadata_offset()), NULL_WORD);
1358 }
1359
1360 void MacroAssembler::check_and_handle_earlyret() {
1361 }
1362
1363 void MacroAssembler::check_and_handle_popframe() {
1364 }
1365
1366 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1367 assert(rscratch != noreg || always_reachable(src1), "missing");
1368
1369 if (reachable(src1)) {
1370 cmpl(as_Address(src1), imm);
1371 } else {
1372 lea(rscratch, src1);
1373 cmpl(Address(rscratch, 0), imm);
1374 }
1375 }
1376
1377 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1378 assert(!src2.is_lval(), "use cmpptr");
1379 assert(rscratch != noreg || always_reachable(src2), "missing");
1380
1381 if (reachable(src2)) {
1382 cmpl(src1, as_Address(src2));
1383 } else {
1384 lea(rscratch, src2);
1385 cmpl(src1, Address(rscratch, 0));
1386 }
1387 }
1388
1389 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1390 Assembler::cmpl(src1, imm);
1391 }
1392
1393 void MacroAssembler::cmp32(Register src1, Address src2) {
1394 Assembler::cmpl(src1, src2);
1395 }
1396
1397 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1398 ucomisd(opr1, opr2);
1399
1400 Label L;
1401 if (unordered_is_less) {
1402 movl(dst, -1);
1403 jcc(Assembler::parity, L);
1404 jcc(Assembler::below , L);
1405 movl(dst, 0);
1406 jcc(Assembler::equal , L);
1407 increment(dst);
1408 } else { // unordered is greater
1409 movl(dst, 1);
1410 jcc(Assembler::parity, L);
1411 jcc(Assembler::above , L);
1412 movl(dst, 0);
1413 jcc(Assembler::equal , L);
1414 decrementl(dst);
1415 }
1416 bind(L);
1417 }
1418
1419 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1420 ucomiss(opr1, opr2);
1421
1422 Label L;
1423 if (unordered_is_less) {
1424 movl(dst, -1);
1425 jcc(Assembler::parity, L);
1426 jcc(Assembler::below , L);
1427 movl(dst, 0);
1428 jcc(Assembler::equal , L);
1429 increment(dst);
1430 } else { // unordered is greater
1431 movl(dst, 1);
1432 jcc(Assembler::parity, L);
1433 jcc(Assembler::above , L);
1434 movl(dst, 0);
1435 jcc(Assembler::equal , L);
1436 decrementl(dst);
1437 }
1438 bind(L);
1439 }
1440
1441
1442 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1443 assert(rscratch != noreg || always_reachable(src1), "missing");
1444
1445 if (reachable(src1)) {
1446 cmpb(as_Address(src1), imm);
1447 } else {
1448 lea(rscratch, src1);
1449 cmpb(Address(rscratch, 0), imm);
1450 }
1451 }
1452
1453 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1454 assert(rscratch != noreg || always_reachable(src2), "missing");
1455
1456 if (src2.is_lval()) {
1457 movptr(rscratch, src2);
1458 Assembler::cmpq(src1, rscratch);
1459 } else if (reachable(src2)) {
1460 cmpq(src1, as_Address(src2));
1461 } else {
1462 lea(rscratch, src2);
1463 Assembler::cmpq(src1, Address(rscratch, 0));
1464 }
1465 }
1466
1467 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1468 assert(src2.is_lval(), "not a mem-mem compare");
1469 // moves src2's literal address
1470 movptr(rscratch, src2);
1471 Assembler::cmpq(src1, rscratch);
1472 }
1473
1474 void MacroAssembler::cmpoop(Register src1, Register src2) {
1475 cmpptr(src1, src2);
1476 }
1477
1478 void MacroAssembler::cmpoop(Register src1, Address src2) {
1479 cmpptr(src1, src2);
1480 }
1481
1482 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1483 movoop(rscratch, src2);
1484 cmpptr(src1, rscratch);
1485 }
1486
1487 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1488 assert(rscratch != noreg || always_reachable(adr), "missing");
1489
1490 if (reachable(adr)) {
1491 lock();
1492 cmpxchgptr(reg, as_Address(adr));
1493 } else {
1494 lea(rscratch, adr);
1495 lock();
1496 cmpxchgptr(reg, Address(rscratch, 0));
1497 }
1498 }
1499
1500 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1501 cmpxchgq(reg, adr);
1502 }
1503
1504 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1505 assert(rscratch != noreg || always_reachable(src), "missing");
1506
1507 if (reachable(src)) {
1508 Assembler::comisd(dst, as_Address(src));
1509 } else {
1510 lea(rscratch, src);
1511 Assembler::comisd(dst, Address(rscratch, 0));
1512 }
1513 }
1514
1515 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1516 assert(rscratch != noreg || always_reachable(src), "missing");
1517
1518 if (reachable(src)) {
1519 Assembler::comiss(dst, as_Address(src));
1520 } else {
1521 lea(rscratch, src);
1522 Assembler::comiss(dst, Address(rscratch, 0));
1523 }
1524 }
1525
1526
1527 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1528 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1529
1530 Condition negated_cond = negate_condition(cond);
1531 Label L;
1532 jcc(negated_cond, L);
1533 pushf(); // Preserve flags
1534 atomic_incl(counter_addr, rscratch);
1535 popf();
1536 bind(L);
1537 }
1538
1539 int MacroAssembler::corrected_idivl(Register reg) {
1540 // Full implementation of Java idiv and irem; checks for
1541 // special case as described in JVM spec., p.243 & p.271.
1542 // The function returns the (pc) offset of the idivl
1543 // instruction - may be needed for implicit exceptions.
1544 //
1545 // normal case special case
1546 //
1547 // input : rax,: dividend min_int
1548 // reg: divisor (may not be rax,/rdx) -1
1549 //
1550 // output: rax,: quotient (= rax, idiv reg) min_int
1551 // rdx: remainder (= rax, irem reg) 0
1552 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1553 const int min_int = 0x80000000;
1554 Label normal_case, special_case;
1555
1556 // check for special case
1557 cmpl(rax, min_int);
1558 jcc(Assembler::notEqual, normal_case);
1559 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1560 cmpl(reg, -1);
1561 jcc(Assembler::equal, special_case);
1562
1563 // handle normal case
1564 bind(normal_case);
1565 cdql();
1566 int idivl_offset = offset();
1567 idivl(reg);
1568
1569 // normal and special case exit
1570 bind(special_case);
1571
1572 return idivl_offset;
1573 }
1574
1575
1576
1577 void MacroAssembler::decrementl(Register reg, int value) {
1578 if (value == min_jint) {subl(reg, value) ; return; }
1579 if (value < 0) { incrementl(reg, -value); return; }
1580 if (value == 0) { ; return; }
1581 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1582 /* else */ { subl(reg, value) ; return; }
1583 }
1584
1585 void MacroAssembler::decrementl(Address dst, int value) {
1586 if (value == min_jint) {subl(dst, value) ; return; }
1587 if (value < 0) { incrementl(dst, -value); return; }
1588 if (value == 0) { ; return; }
1589 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1590 /* else */ { subl(dst, value) ; return; }
1591 }
1592
1593 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1594 assert(shift_value > 0, "illegal shift value");
1595 Label _is_positive;
1596 testl (reg, reg);
1597 jcc (Assembler::positive, _is_positive);
1598 int offset = (1 << shift_value) - 1 ;
1599
1600 if (offset == 1) {
1601 incrementl(reg);
1602 } else {
1603 addl(reg, offset);
1604 }
1605
1606 bind (_is_positive);
1607 sarl(reg, shift_value);
1608 }
1609
1610 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1611 assert(rscratch != noreg || always_reachable(src), "missing");
1612
1613 if (reachable(src)) {
1614 Assembler::divsd(dst, as_Address(src));
1615 } else {
1616 lea(rscratch, src);
1617 Assembler::divsd(dst, Address(rscratch, 0));
1618 }
1619 }
1620
1621 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1622 assert(rscratch != noreg || always_reachable(src), "missing");
1623
1624 if (reachable(src)) {
1625 Assembler::divss(dst, as_Address(src));
1626 } else {
1627 lea(rscratch, src);
1628 Assembler::divss(dst, Address(rscratch, 0));
1629 }
1630 }
1631
1632 void MacroAssembler::enter() {
1633 push(rbp);
1634 mov(rbp, rsp);
1635 }
1636
1637 void MacroAssembler::post_call_nop() {
1638 if (!Continuations::enabled()) {
1639 return;
1640 }
1641 InstructionMark im(this);
1642 relocate(post_call_nop_Relocation::spec());
1643 InlineSkippedInstructionsCounter skipCounter(this);
1644 emit_int8((uint8_t)0x0f);
1645 emit_int8((uint8_t)0x1f);
1646 emit_int8((uint8_t)0x84);
1647 emit_int8((uint8_t)0x00);
1648 emit_int32(0x00);
1649 }
1650
1651 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1652 assert(rscratch != noreg || always_reachable(src), "missing");
1653 if (reachable(src)) {
1654 Assembler::mulpd(dst, as_Address(src));
1655 } else {
1656 lea(rscratch, src);
1657 Assembler::mulpd(dst, Address(rscratch, 0));
1658 }
1659 }
1660
1661 // dst = c = a * b + c
1662 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1663 Assembler::vfmadd231sd(c, a, b);
1664 if (dst != c) {
1665 movdbl(dst, c);
1666 }
1667 }
1668
1669 // dst = c = a * b + c
1670 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1671 Assembler::vfmadd231ss(c, a, b);
1672 if (dst != c) {
1673 movflt(dst, c);
1674 }
1675 }
1676
1677 // dst = c = a * b + c
1678 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1679 Assembler::vfmadd231pd(c, a, b, vector_len);
1680 if (dst != c) {
1681 vmovdqu(dst, c);
1682 }
1683 }
1684
1685 // dst = c = a * b + c
1686 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1687 Assembler::vfmadd231ps(c, a, b, vector_len);
1688 if (dst != c) {
1689 vmovdqu(dst, c);
1690 }
1691 }
1692
1693 // dst = c = a * b + c
1694 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1695 Assembler::vfmadd231pd(c, a, b, vector_len);
1696 if (dst != c) {
1697 vmovdqu(dst, c);
1698 }
1699 }
1700
1701 // dst = c = a * b + c
1702 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1703 Assembler::vfmadd231ps(c, a, b, vector_len);
1704 if (dst != c) {
1705 vmovdqu(dst, c);
1706 }
1707 }
1708
1709 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
1710 assert(rscratch != noreg || always_reachable(dst), "missing");
1711
1712 if (reachable(dst)) {
1713 incrementl(as_Address(dst));
1714 } else {
1715 lea(rscratch, dst);
1716 incrementl(Address(rscratch, 0));
1717 }
1718 }
1719
1720 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
1721 incrementl(as_Address(dst, rscratch));
1722 }
1723
1724 void MacroAssembler::incrementl(Register reg, int value) {
1725 if (value == min_jint) {addl(reg, value) ; return; }
1726 if (value < 0) { decrementl(reg, -value); return; }
1727 if (value == 0) { ; return; }
1728 if (value == 1 && UseIncDec) { incl(reg) ; return; }
1729 /* else */ { addl(reg, value) ; return; }
1730 }
1731
1732 void MacroAssembler::incrementl(Address dst, int value) {
1733 if (value == min_jint) {addl(dst, value) ; return; }
1734 if (value < 0) { decrementl(dst, -value); return; }
1735 if (value == 0) { ; return; }
1736 if (value == 1 && UseIncDec) { incl(dst) ; return; }
1737 /* else */ { addl(dst, value) ; return; }
1738 }
1739
1740 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
1741 assert(rscratch != noreg || always_reachable(dst), "missing");
1742 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
1743 if (reachable(dst)) {
1744 jmp_literal(dst.target(), dst.rspec());
1745 } else {
1746 lea(rscratch, dst);
1747 jmp(rscratch);
1748 }
1749 }
1750
1751 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
1752 assert(rscratch != noreg || always_reachable(dst), "missing");
1753 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
1754 if (reachable(dst)) {
1755 InstructionMark im(this);
1756 relocate(dst.reloc());
1757 const int short_size = 2;
1758 const int long_size = 6;
1759 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
1760 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
1761 // 0111 tttn #8-bit disp
1762 emit_int8(0x70 | cc);
1763 emit_int8((offs - short_size) & 0xFF);
1764 } else {
1765 // 0000 1111 1000 tttn #32-bit disp
1766 emit_int8(0x0F);
1767 emit_int8((unsigned char)(0x80 | cc));
1768 emit_int32(offs - long_size);
1769 }
1770 } else {
1771 #ifdef ASSERT
1772 warning("reversing conditional branch");
1773 #endif /* ASSERT */
1774 Label skip;
1775 jccb(reverse[cc], skip);
1776 lea(rscratch, dst);
1777 Assembler::jmp(rscratch);
1778 bind(skip);
1779 }
1780 }
1781
1782 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
1783 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
1784 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
1785
1786 stmxcsr(mxcsr_save);
1787 movl(tmp, mxcsr_save);
1788 if (EnableX86ECoreOpts) {
1789 // The mxcsr_std has status bits set for performance on ECore
1790 orl(tmp, 0x003f);
1791 } else {
1792 // Mask out status bits (only check control and mask bits)
1793 andl(tmp, 0xFFC0);
1794 }
1795 cmp32(tmp, mxcsr_std, rscratch);
1796 }
1797
1798 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
1799 assert(rscratch != noreg || always_reachable(src), "missing");
1800
1801 if (reachable(src)) {
1802 Assembler::ldmxcsr(as_Address(src));
1803 } else {
1804 lea(rscratch, src);
1805 Assembler::ldmxcsr(Address(rscratch, 0));
1806 }
1807 }
1808
1809 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1810 int off = offset();
1811 movsbl(dst, src); // movsxb
1812 return off;
1813 }
1814
1815 // Note: load_signed_short used to be called load_signed_word.
1816 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
1817 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
1818 // The term "word" in HotSpot means a 32- or 64-bit machine word.
1819 int MacroAssembler::load_signed_short(Register dst, Address src) {
1820 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
1821 // version but this is what 64bit has always done. This seems to imply
1822 // that users are only using 32bits worth.
1823 int off = offset();
1824 movswl(dst, src); // movsxw
1825 return off;
1826 }
1827
1828 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1829 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1830 // and "3.9 Partial Register Penalties", p. 22).
1831 int off = offset();
1832 movzbl(dst, src); // movzxb
1833 return off;
1834 }
1835
1836 // Note: load_unsigned_short used to be called load_unsigned_word.
1837 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1838 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1839 // and "3.9 Partial Register Penalties", p. 22).
1840 int off = offset();
1841 movzwl(dst, src); // movzxw
1842 return off;
1843 }
1844
1845 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1846 switch (size_in_bytes) {
1847 case 8: movq(dst, src); break;
1848 case 4: movl(dst, src); break;
1849 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1850 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1851 default: ShouldNotReachHere();
1852 }
1853 }
1854
1855 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1856 switch (size_in_bytes) {
1857 case 8: movq(dst, src); break;
1858 case 4: movl(dst, src); break;
1859 case 2: movw(dst, src); break;
1860 case 1: movb(dst, src); break;
1861 default: ShouldNotReachHere();
1862 }
1863 }
1864
1865 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
1866 assert(rscratch != noreg || always_reachable(dst), "missing");
1867
1868 if (reachable(dst)) {
1869 movl(as_Address(dst), src);
1870 } else {
1871 lea(rscratch, dst);
1872 movl(Address(rscratch, 0), src);
1873 }
1874 }
1875
1876 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
1877 if (reachable(src)) {
1878 movl(dst, as_Address(src));
1879 } else {
1880 lea(dst, src);
1881 movl(dst, Address(dst, 0));
1882 }
1883 }
1884
1885 // C++ bool manipulation
1886
1887 void MacroAssembler::movbool(Register dst, Address src) {
1888 if(sizeof(bool) == 1)
1889 movb(dst, src);
1890 else if(sizeof(bool) == 2)
1891 movw(dst, src);
1892 else if(sizeof(bool) == 4)
1893 movl(dst, src);
1894 else
1895 // unsupported
1896 ShouldNotReachHere();
1897 }
1898
1899 void MacroAssembler::movbool(Address dst, bool boolconst) {
1900 if(sizeof(bool) == 1)
1901 movb(dst, (int) boolconst);
1902 else if(sizeof(bool) == 2)
1903 movw(dst, (int) boolconst);
1904 else if(sizeof(bool) == 4)
1905 movl(dst, (int) boolconst);
1906 else
1907 // unsupported
1908 ShouldNotReachHere();
1909 }
1910
1911 void MacroAssembler::movbool(Address dst, Register src) {
1912 if(sizeof(bool) == 1)
1913 movb(dst, src);
1914 else if(sizeof(bool) == 2)
1915 movw(dst, src);
1916 else if(sizeof(bool) == 4)
1917 movl(dst, src);
1918 else
1919 // unsupported
1920 ShouldNotReachHere();
1921 }
1922
1923 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1924 assert(rscratch != noreg || always_reachable(src), "missing");
1925
1926 if (reachable(src)) {
1927 movdl(dst, as_Address(src));
1928 } else {
1929 lea(rscratch, src);
1930 movdl(dst, Address(rscratch, 0));
1931 }
1932 }
1933
1934 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
1935 assert(rscratch != noreg || always_reachable(src), "missing");
1936
1937 if (reachable(src)) {
1938 movq(dst, as_Address(src));
1939 } else {
1940 lea(rscratch, src);
1941 movq(dst, Address(rscratch, 0));
1942 }
1943 }
1944
1945 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1946 assert(rscratch != noreg || always_reachable(src), "missing");
1947
1948 if (reachable(src)) {
1949 if (UseXmmLoadAndClearUpper) {
1950 movsd (dst, as_Address(src));
1951 } else {
1952 movlpd(dst, as_Address(src));
1953 }
1954 } else {
1955 lea(rscratch, src);
1956 if (UseXmmLoadAndClearUpper) {
1957 movsd (dst, Address(rscratch, 0));
1958 } else {
1959 movlpd(dst, Address(rscratch, 0));
1960 }
1961 }
1962 }
1963
1964 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
1965 assert(rscratch != noreg || always_reachable(src), "missing");
1966
1967 if (reachable(src)) {
1968 movss(dst, as_Address(src));
1969 } else {
1970 lea(rscratch, src);
1971 movss(dst, Address(rscratch, 0));
1972 }
1973 }
1974
1975 void MacroAssembler::movhlf(XMMRegister dst, XMMRegister src, Register rscratch) {
1976 if (VM_Version::supports_avx10_2()) {
1977 evmovw(dst, src);
1978 } else {
1979 assert(rscratch != noreg, "missing");
1980 evmovw(rscratch, src);
1981 evmovw(dst, rscratch);
1982 }
1983 }
1984
1985 void MacroAssembler::mov64(Register dst, int64_t imm64) {
1986 if (is_uimm32(imm64)) {
1987 movl(dst, checked_cast<uint32_t>(imm64));
1988 } else if (is_simm32(imm64)) {
1989 movq(dst, checked_cast<int32_t>(imm64));
1990 } else {
1991 Assembler::mov64(dst, imm64);
1992 }
1993 }
1994
1995 void MacroAssembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) {
1996 Assembler::mov64(dst, imm64, rtype, format);
1997 }
1998
1999 void MacroAssembler::movptr(Register dst, Register src) {
2000 movq(dst, src);
2001 }
2002
2003 void MacroAssembler::movptr(Register dst, Address src) {
2004 movq(dst, src);
2005 }
2006
2007 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2008 void MacroAssembler::movptr(Register dst, intptr_t src) {
2009 mov64(dst, src);
2010 }
2011
2012 void MacroAssembler::movptr(Address dst, Register src) {
2013 movq(dst, src);
2014 }
2015
2016 void MacroAssembler::movptr(Address dst, int32_t src) {
2017 movslq(dst, src);
2018 }
2019
2020 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2021 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2022 Assembler::movdqu(dst, src);
2023 }
2024
2025 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2026 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2027 Assembler::movdqu(dst, src);
2028 }
2029
2030 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2031 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2032 Assembler::movdqu(dst, src);
2033 }
2034
2035 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2036 assert(rscratch != noreg || always_reachable(src), "missing");
2037
2038 if (reachable(src)) {
2039 movdqu(dst, as_Address(src));
2040 } else {
2041 lea(rscratch, src);
2042 movdqu(dst, Address(rscratch, 0));
2043 }
2044 }
2045
2046 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2047 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2048 Assembler::vmovdqu(dst, src);
2049 }
2050
2051 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2052 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2053 Assembler::vmovdqu(dst, src);
2054 }
2055
2056 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2057 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2058 Assembler::vmovdqu(dst, src);
2059 }
2060
2061 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2062 assert(rscratch != noreg || always_reachable(src), "missing");
2063
2064 if (reachable(src)) {
2065 vmovdqu(dst, as_Address(src));
2066 }
2067 else {
2068 lea(rscratch, src);
2069 vmovdqu(dst, Address(rscratch, 0));
2070 }
2071 }
2072
2073 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2074 assert(rscratch != noreg || always_reachable(src), "missing");
2075
2076 if (vector_len == AVX_512bit) {
2077 evmovdquq(dst, src, AVX_512bit, rscratch);
2078 } else if (vector_len == AVX_256bit) {
2079 vmovdqu(dst, src, rscratch);
2080 } else {
2081 movdqu(dst, src, rscratch);
2082 }
2083 }
2084
2085 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2086 if (vector_len == AVX_512bit) {
2087 evmovdquq(dst, src, AVX_512bit);
2088 } else if (vector_len == AVX_256bit) {
2089 vmovdqu(dst, src);
2090 } else {
2091 movdqu(dst, src);
2092 }
2093 }
2094
2095 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2096 if (vector_len == AVX_512bit) {
2097 evmovdquq(dst, src, AVX_512bit);
2098 } else if (vector_len == AVX_256bit) {
2099 vmovdqu(dst, src);
2100 } else {
2101 movdqu(dst, src);
2102 }
2103 }
2104
2105 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2106 if (vector_len == AVX_512bit) {
2107 evmovdquq(dst, src, AVX_512bit);
2108 } else if (vector_len == AVX_256bit) {
2109 vmovdqu(dst, src);
2110 } else {
2111 movdqu(dst, src);
2112 }
2113 }
2114
2115 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2116 assert(rscratch != noreg || always_reachable(src), "missing");
2117
2118 if (reachable(src)) {
2119 vmovdqa(dst, as_Address(src));
2120 }
2121 else {
2122 lea(rscratch, src);
2123 vmovdqa(dst, Address(rscratch, 0));
2124 }
2125 }
2126
2127 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2128 assert(rscratch != noreg || always_reachable(src), "missing");
2129
2130 if (vector_len == AVX_512bit) {
2131 evmovdqaq(dst, src, AVX_512bit, rscratch);
2132 } else if (vector_len == AVX_256bit) {
2133 vmovdqa(dst, src, rscratch);
2134 } else {
2135 movdqa(dst, src, rscratch);
2136 }
2137 }
2138
2139 void MacroAssembler::kmov(KRegister dst, Address src) {
2140 if (VM_Version::supports_avx512bw()) {
2141 kmovql(dst, src);
2142 } else {
2143 assert(VM_Version::supports_evex(), "");
2144 kmovwl(dst, src);
2145 }
2146 }
2147
2148 void MacroAssembler::kmov(Address dst, KRegister src) {
2149 if (VM_Version::supports_avx512bw()) {
2150 kmovql(dst, src);
2151 } else {
2152 assert(VM_Version::supports_evex(), "");
2153 kmovwl(dst, src);
2154 }
2155 }
2156
2157 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2158 if (VM_Version::supports_avx512bw()) {
2159 kmovql(dst, src);
2160 } else {
2161 assert(VM_Version::supports_evex(), "");
2162 kmovwl(dst, src);
2163 }
2164 }
2165
2166 void MacroAssembler::kmov(Register dst, KRegister src) {
2167 if (VM_Version::supports_avx512bw()) {
2168 kmovql(dst, src);
2169 } else {
2170 assert(VM_Version::supports_evex(), "");
2171 kmovwl(dst, src);
2172 }
2173 }
2174
2175 void MacroAssembler::kmov(KRegister dst, Register src) {
2176 if (VM_Version::supports_avx512bw()) {
2177 kmovql(dst, src);
2178 } else {
2179 assert(VM_Version::supports_evex(), "");
2180 kmovwl(dst, src);
2181 }
2182 }
2183
2184 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2185 assert(rscratch != noreg || always_reachable(src), "missing");
2186
2187 if (reachable(src)) {
2188 kmovql(dst, as_Address(src));
2189 } else {
2190 lea(rscratch, src);
2191 kmovql(dst, Address(rscratch, 0));
2192 }
2193 }
2194
2195 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2196 assert(rscratch != noreg || always_reachable(src), "missing");
2197
2198 if (reachable(src)) {
2199 kmovwl(dst, as_Address(src));
2200 } else {
2201 lea(rscratch, src);
2202 kmovwl(dst, Address(rscratch, 0));
2203 }
2204 }
2205
2206 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2207 int vector_len, Register rscratch) {
2208 assert(rscratch != noreg || always_reachable(src), "missing");
2209
2210 if (reachable(src)) {
2211 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2212 } else {
2213 lea(rscratch, src);
2214 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2215 }
2216 }
2217
2218 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2219 int vector_len, Register rscratch) {
2220 assert(rscratch != noreg || always_reachable(src), "missing");
2221
2222 if (reachable(src)) {
2223 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2224 } else {
2225 lea(rscratch, src);
2226 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2227 }
2228 }
2229
2230 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2231 assert(rscratch != noreg || always_reachable(src), "missing");
2232
2233 if (reachable(src)) {
2234 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2235 } else {
2236 lea(rscratch, src);
2237 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2238 }
2239 }
2240
2241 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2242 assert(rscratch != noreg || always_reachable(src), "missing");
2243
2244 if (reachable(src)) {
2245 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2246 } else {
2247 lea(rscratch, src);
2248 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2249 }
2250 }
2251
2252 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2253 assert(rscratch != noreg || always_reachable(src), "missing");
2254
2255 if (reachable(src)) {
2256 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2257 } else {
2258 lea(rscratch, src);
2259 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2260 }
2261 }
2262
2263 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2264 assert(rscratch != noreg || always_reachable(src), "missing");
2265
2266 if (reachable(src)) {
2267 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2268 } else {
2269 lea(rscratch, src);
2270 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2271 }
2272 }
2273
2274 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2275 assert(rscratch != noreg || always_reachable(src), "missing");
2276
2277 if (reachable(src)) {
2278 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2279 } else {
2280 lea(rscratch, src);
2281 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2282 }
2283 }
2284
2285 void MacroAssembler::movapd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2286 assert(rscratch != noreg || always_reachable(src), "missing");
2287
2288 if (reachable(src)) {
2289 Assembler::movapd(dst, as_Address(src));
2290 } else {
2291 lea(rscratch, src);
2292 Assembler::movapd(dst, Address(rscratch, 0));
2293 }
2294 }
2295
2296 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2297 assert(rscratch != noreg || always_reachable(src), "missing");
2298
2299 if (reachable(src)) {
2300 Assembler::movdqa(dst, as_Address(src));
2301 } else {
2302 lea(rscratch, src);
2303 Assembler::movdqa(dst, Address(rscratch, 0));
2304 }
2305 }
2306
2307 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2308 assert(rscratch != noreg || always_reachable(src), "missing");
2309
2310 if (reachable(src)) {
2311 Assembler::movsd(dst, as_Address(src));
2312 } else {
2313 lea(rscratch, src);
2314 Assembler::movsd(dst, Address(rscratch, 0));
2315 }
2316 }
2317
2318 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2319 assert(rscratch != noreg || always_reachable(src), "missing");
2320
2321 if (reachable(src)) {
2322 Assembler::movss(dst, as_Address(src));
2323 } else {
2324 lea(rscratch, src);
2325 Assembler::movss(dst, Address(rscratch, 0));
2326 }
2327 }
2328
2329 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2330 assert(rscratch != noreg || always_reachable(src), "missing");
2331
2332 if (reachable(src)) {
2333 Assembler::movddup(dst, as_Address(src));
2334 } else {
2335 lea(rscratch, src);
2336 Assembler::movddup(dst, Address(rscratch, 0));
2337 }
2338 }
2339
2340 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2341 assert(rscratch != noreg || always_reachable(src), "missing");
2342
2343 if (reachable(src)) {
2344 Assembler::vmovddup(dst, as_Address(src), vector_len);
2345 } else {
2346 lea(rscratch, src);
2347 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2348 }
2349 }
2350
2351 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2352 assert(rscratch != noreg || always_reachable(src), "missing");
2353
2354 if (reachable(src)) {
2355 Assembler::mulsd(dst, as_Address(src));
2356 } else {
2357 lea(rscratch, src);
2358 Assembler::mulsd(dst, Address(rscratch, 0));
2359 }
2360 }
2361
2362 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2363 assert(rscratch != noreg || always_reachable(src), "missing");
2364
2365 if (reachable(src)) {
2366 Assembler::mulss(dst, as_Address(src));
2367 } else {
2368 lea(rscratch, src);
2369 Assembler::mulss(dst, Address(rscratch, 0));
2370 }
2371 }
2372
2373 void MacroAssembler::null_check(Register reg, int offset) {
2374 if (needs_explicit_null_check(offset)) {
2375 // provoke OS null exception if reg is null by
2376 // accessing M[reg] w/o changing any (non-CC) registers
2377 // NOTE: cmpl is plenty here to provoke a segv
2378 cmpptr(rax, Address(reg, 0));
2379 // Note: should probably use testl(rax, Address(reg, 0));
2380 // may be shorter code (however, this version of
2381 // testl needs to be implemented first)
2382 } else {
2383 // nothing to do, (later) access of M[reg + offset]
2384 // will provoke OS null exception if reg is null
2385 }
2386 }
2387
2388 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2389 andptr(markword, markWord::inline_type_pattern_mask);
2390 cmpptr(markword, markWord::inline_type_pattern);
2391 jcc(Assembler::equal, is_inline_type);
2392 }
2393
2394 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null) {
2395 if (can_be_null) {
2396 testptr(object, object);
2397 jcc(Assembler::zero, not_inline_type);
2398 }
2399 const int is_inline_type_mask = markWord::inline_type_pattern;
2400 movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2401 andptr(tmp, is_inline_type_mask);
2402 cmpptr(tmp, is_inline_type_mask);
2403 jcc(Assembler::notEqual, not_inline_type);
2404 }
2405
2406 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2407 movl(temp_reg, flags);
2408 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2409 jcc(Assembler::notEqual, is_null_free_inline_type);
2410 }
2411
2412 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2413 movl(temp_reg, flags);
2414 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2415 jcc(Assembler::equal, not_null_free_inline_type);
2416 }
2417
2418 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2419 movl(temp_reg, flags);
2420 testl(temp_reg, 1 << ResolvedFieldEntry::is_flat_shift);
2421 jcc(Assembler::notEqual, is_flat);
2422 }
2423
2424 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2425 Label test_mark_word;
2426 // load mark word
2427 movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2428 // check displaced
2429 testl(temp_reg, markWord::unlocked_value);
2430 jccb(Assembler::notZero, test_mark_word);
2431 // slow path use klass prototype
2432 push(rscratch1);
2433 load_prototype_header(temp_reg, oop, rscratch1);
2434 pop(rscratch1);
2435
2436 bind(test_mark_word);
2437 testl(temp_reg, test_bit);
2438 jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
2439 }
2440
2441 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg,
2442 Label& is_flat_array) {
2443 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2444 }
2445
2446 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2447 Label& is_non_flat_array) {
2448 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2449 }
2450
2451 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
2452 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2453 }
2454
2455 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2456 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2457 }
2458
2459 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2460 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2461 jcc(Assembler::notZero, is_flat_array);
2462 }
2463
2464 void MacroAssembler::os_breakpoint() {
2465 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2466 // (e.g., MSVC can't call ps() otherwise)
2467 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2468 }
2469
2470 void MacroAssembler::unimplemented(const char* what) {
2471 const char* buf = nullptr;
2472 {
2473 ResourceMark rm;
2474 stringStream ss;
2475 ss.print("unimplemented: %s", what);
2476 buf = code_string(ss.as_string());
2477 }
2478 stop(buf);
2479 }
2480
2481 #define XSTATE_BV 0x200
2482
2483 void MacroAssembler::pop_CPU_state() {
2484 pop_FPU_state();
2485 pop_IU_state();
2486 }
2487
2488 void MacroAssembler::pop_FPU_state() {
2489 fxrstor(Address(rsp, 0));
2490 addptr(rsp, FPUStateSizeInWords * wordSize);
2491 }
2492
2493 void MacroAssembler::pop_IU_state() {
2494 popa();
2495 addq(rsp, 8);
2496 popf();
2497 }
2498
2499 // Save Integer and Float state
2500 // Warning: Stack must be 16 byte aligned (64bit)
2501 void MacroAssembler::push_CPU_state() {
2502 push_IU_state();
2503 push_FPU_state();
2504 }
2505
2506 void MacroAssembler::push_FPU_state() {
2507 subptr(rsp, FPUStateSizeInWords * wordSize);
2508 fxsave(Address(rsp, 0));
2509 }
2510
2511 void MacroAssembler::push_IU_state() {
2512 // Push flags first because pusha kills them
2513 pushf();
2514 // Make sure rsp stays 16-byte aligned
2515 subq(rsp, 8);
2516 pusha();
2517 }
2518
2519 void MacroAssembler::push_cont_fastpath() {
2520 if (!Continuations::enabled()) return;
2521
2522 Label L_done;
2523 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2524 jccb(Assembler::belowEqual, L_done);
2525 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), rsp);
2526 bind(L_done);
2527 }
2528
2529 void MacroAssembler::pop_cont_fastpath() {
2530 if (!Continuations::enabled()) return;
2531
2532 Label L_done;
2533 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2534 jccb(Assembler::below, L_done);
2535 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), 0);
2536 bind(L_done);
2537 }
2538
2539 #ifdef ASSERT
2540 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2541 Label no_cont;
2542 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2543 testl(cont, cont);
2544 jcc(Assembler::zero, no_cont);
2545 stop(name);
2546 bind(no_cont);
2547 }
2548 #endif
2549
2550 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { // determine java_thread register
2551 // we must set sp to zero to clear frame
2552 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2553 // must clear fp, so that compiled frames are not confused; it is
2554 // possible that we need it only for debugging
2555 if (clear_fp) {
2556 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2557 }
2558 // Always clear the pc because it could have been set by make_walkable()
2559 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2560 vzeroupper();
2561 }
2562
2563 void MacroAssembler::round_to(Register reg, int modulus) {
2564 addptr(reg, modulus - 1);
2565 andptr(reg, -modulus);
2566 }
2567
2568 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod) {
2569 if (at_return) {
2570 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2571 // we may safely use rsp instead to perform the stack watermark check.
2572 cmpptr(in_nmethod ? rsp : rbp, Address(r15_thread, JavaThread::polling_word_offset()));
2573 jcc(Assembler::above, slow_path);
2574 return;
2575 }
2576 testb(Address(r15_thread, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2577 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2578 }
2579
2580 // Calls to C land
2581 //
2582 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2583 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2584 // has to be reset to 0. This is required to allow proper stack traversal.
2585 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2586 Register last_java_fp,
2587 address last_java_pc,
2588 Register rscratch) {
2589 vzeroupper();
2590 // determine last_java_sp register
2591 if (!last_java_sp->is_valid()) {
2592 last_java_sp = rsp;
2593 }
2594 // last_java_fp is optional
2595 if (last_java_fp->is_valid()) {
2596 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2597 }
2598 // last_java_pc is optional
2599 if (last_java_pc != nullptr) {
2600 Address java_pc(r15_thread,
2601 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
2602 lea(java_pc, InternalAddress(last_java_pc), rscratch);
2603 }
2604 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2605 }
2606
2607 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2608 Register last_java_fp,
2609 Label &L,
2610 Register scratch) {
2611 lea(scratch, L);
2612 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
2613 set_last_Java_frame(last_java_sp, last_java_fp, nullptr, scratch);
2614 }
2615
2616 void MacroAssembler::shlptr(Register dst, int imm8) {
2617 shlq(dst, imm8);
2618 }
2619
2620 void MacroAssembler::shrptr(Register dst, int imm8) {
2621 shrq(dst, imm8);
2622 }
2623
2624 void MacroAssembler::sign_extend_byte(Register reg) {
2625 movsbl(reg, reg); // movsxb
2626 }
2627
2628 void MacroAssembler::sign_extend_short(Register reg) {
2629 movswl(reg, reg); // movsxw
2630 }
2631
2632 void MacroAssembler::narrow_subword_type(Register reg, BasicType bt) {
2633 assert(is_subword_type(bt), "required");
2634 switch (bt) {
2635 case T_BOOLEAN: andl(reg, 1); break;
2636 case T_BYTE: movsbl(reg, reg); break;
2637 case T_CHAR: movzwl(reg, reg); break;
2638 case T_SHORT: movswl(reg, reg); break;
2639 default: ShouldNotReachHere();
2640 }
2641 }
2642
2643 void MacroAssembler::testl(Address dst, int32_t imm32) {
2644 if (imm32 >= 0 && is8bit(imm32)) {
2645 testb(dst, imm32);
2646 } else {
2647 Assembler::testl(dst, imm32);
2648 }
2649 }
2650
2651 void MacroAssembler::testl(Register dst, int32_t imm32) {
2652 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
2653 testb(dst, imm32);
2654 } else {
2655 Assembler::testl(dst, imm32);
2656 }
2657 }
2658
2659 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2660 assert(always_reachable(src), "Address should be reachable");
2661 testl(dst, as_Address(src));
2662 }
2663
2664 void MacroAssembler::testq(Address dst, int32_t imm32) {
2665 if (imm32 >= 0) {
2666 testl(dst, imm32);
2667 } else {
2668 Assembler::testq(dst, imm32);
2669 }
2670 }
2671
2672 void MacroAssembler::testq(Register dst, int32_t imm32) {
2673 if (imm32 >= 0) {
2674 testl(dst, imm32);
2675 } else {
2676 Assembler::testq(dst, imm32);
2677 }
2678 }
2679
2680 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2681 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2682 Assembler::pcmpeqb(dst, src);
2683 }
2684
2685 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2686 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2687 Assembler::pcmpeqw(dst, src);
2688 }
2689
2690 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2691 assert((dst->encoding() < 16),"XMM register should be 0-15");
2692 Assembler::pcmpestri(dst, src, imm8);
2693 }
2694
2695 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2696 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2697 Assembler::pcmpestri(dst, src, imm8);
2698 }
2699
2700 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2701 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2702 Assembler::pmovzxbw(dst, src);
2703 }
2704
2705 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2706 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2707 Assembler::pmovzxbw(dst, src);
2708 }
2709
2710 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2711 assert((src->encoding() < 16),"XMM register should be 0-15");
2712 Assembler::pmovmskb(dst, src);
2713 }
2714
2715 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2716 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2717 Assembler::ptest(dst, src);
2718 }
2719
2720 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2721 assert(rscratch != noreg || always_reachable(src), "missing");
2722
2723 if (reachable(src)) {
2724 Assembler::sqrtss(dst, as_Address(src));
2725 } else {
2726 lea(rscratch, src);
2727 Assembler::sqrtss(dst, Address(rscratch, 0));
2728 }
2729 }
2730
2731 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2732 assert(rscratch != noreg || always_reachable(src), "missing");
2733
2734 if (reachable(src)) {
2735 Assembler::subsd(dst, as_Address(src));
2736 } else {
2737 lea(rscratch, src);
2738 Assembler::subsd(dst, Address(rscratch, 0));
2739 }
2740 }
2741
2742 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
2743 assert(rscratch != noreg || always_reachable(src), "missing");
2744
2745 if (reachable(src)) {
2746 Assembler::roundsd(dst, as_Address(src), rmode);
2747 } else {
2748 lea(rscratch, src);
2749 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
2750 }
2751 }
2752
2753 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2754 assert(rscratch != noreg || always_reachable(src), "missing");
2755
2756 if (reachable(src)) {
2757 Assembler::subss(dst, as_Address(src));
2758 } else {
2759 lea(rscratch, src);
2760 Assembler::subss(dst, Address(rscratch, 0));
2761 }
2762 }
2763
2764 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2765 assert(rscratch != noreg || always_reachable(src), "missing");
2766
2767 if (reachable(src)) {
2768 Assembler::ucomisd(dst, as_Address(src));
2769 } else {
2770 lea(rscratch, src);
2771 Assembler::ucomisd(dst, Address(rscratch, 0));
2772 }
2773 }
2774
2775 void MacroAssembler::evucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2776 assert(rscratch != noreg || always_reachable(src), "missing");
2777
2778 if (reachable(src)) {
2779 Assembler::evucomxsd(dst, as_Address(src));
2780 } else {
2781 lea(rscratch, src);
2782 Assembler::evucomxsd(dst, Address(rscratch, 0));
2783 }
2784 }
2785
2786 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2787 assert(rscratch != noreg || always_reachable(src), "missing");
2788
2789 if (reachable(src)) {
2790 Assembler::ucomiss(dst, as_Address(src));
2791 } else {
2792 lea(rscratch, src);
2793 Assembler::ucomiss(dst, Address(rscratch, 0));
2794 }
2795 }
2796
2797 void MacroAssembler::evucomxss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2798 assert(rscratch != noreg || always_reachable(src), "missing");
2799
2800 if (reachable(src)) {
2801 Assembler::evucomxss(dst, as_Address(src));
2802 } else {
2803 lea(rscratch, src);
2804 Assembler::evucomxss(dst, Address(rscratch, 0));
2805 }
2806 }
2807
2808 void MacroAssembler::evucomish(XMMRegister dst, AddressLiteral src, Register rscratch) {
2809 assert(rscratch != noreg || always_reachable(src), "missing");
2810
2811 if (reachable(src)) {
2812 Assembler::evucomish(dst, as_Address(src));
2813 } else {
2814 lea(rscratch, src);
2815 Assembler::evucomish(dst, Address(rscratch, 0));
2816 }
2817 }
2818
2819 void MacroAssembler::evucomxsh(XMMRegister dst, AddressLiteral src, Register rscratch) {
2820 assert(rscratch != noreg || always_reachable(src), "missing");
2821
2822 if (reachable(src)) {
2823 Assembler::evucomxsh(dst, as_Address(src));
2824 } else {
2825 lea(rscratch, src);
2826 Assembler::evucomxsh(dst, Address(rscratch, 0));
2827 }
2828 }
2829
2830 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2831 assert(rscratch != noreg || always_reachable(src), "missing");
2832
2833 // Used in sign-bit flipping with aligned address.
2834 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2835
2836 if (UseAVX > 2 &&
2837 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2838 (dst->encoding() >= 16)) {
2839 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2840 } else if (reachable(src)) {
2841 Assembler::xorpd(dst, as_Address(src));
2842 } else {
2843 lea(rscratch, src);
2844 Assembler::xorpd(dst, Address(rscratch, 0));
2845 }
2846 }
2847
2848 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
2849 if (UseAVX > 2 &&
2850 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2851 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2852 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2853 } else {
2854 Assembler::xorpd(dst, src);
2855 }
2856 }
2857
2858 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
2859 if (UseAVX > 2 &&
2860 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2861 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2862 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2863 } else {
2864 Assembler::xorps(dst, src);
2865 }
2866 }
2867
2868 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
2869 assert(rscratch != noreg || always_reachable(src), "missing");
2870
2871 // Used in sign-bit flipping with aligned address.
2872 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2873
2874 if (UseAVX > 2 &&
2875 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2876 (dst->encoding() >= 16)) {
2877 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2878 } else if (reachable(src)) {
2879 Assembler::xorps(dst, as_Address(src));
2880 } else {
2881 lea(rscratch, src);
2882 Assembler::xorps(dst, Address(rscratch, 0));
2883 }
2884 }
2885
2886 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
2887 assert(rscratch != noreg || always_reachable(src), "missing");
2888
2889 // Used in sign-bit flipping with aligned address.
2890 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
2891 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2892 if (reachable(src)) {
2893 Assembler::pshufb(dst, as_Address(src));
2894 } else {
2895 lea(rscratch, src);
2896 Assembler::pshufb(dst, Address(rscratch, 0));
2897 }
2898 }
2899
2900 // AVX 3-operands instructions
2901
2902 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2903 assert(rscratch != noreg || always_reachable(src), "missing");
2904
2905 if (reachable(src)) {
2906 vaddsd(dst, nds, as_Address(src));
2907 } else {
2908 lea(rscratch, src);
2909 vaddsd(dst, nds, Address(rscratch, 0));
2910 }
2911 }
2912
2913 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2914 assert(rscratch != noreg || always_reachable(src), "missing");
2915
2916 if (reachable(src)) {
2917 vaddss(dst, nds, as_Address(src));
2918 } else {
2919 lea(rscratch, src);
2920 vaddss(dst, nds, Address(rscratch, 0));
2921 }
2922 }
2923
2924 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2925 assert(UseAVX > 0, "requires some form of AVX");
2926 assert(rscratch != noreg || always_reachable(src), "missing");
2927
2928 if (reachable(src)) {
2929 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
2930 } else {
2931 lea(rscratch, src);
2932 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
2933 }
2934 }
2935
2936 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2937 assert(UseAVX > 0, "requires some form of AVX");
2938 assert(rscratch != noreg || always_reachable(src), "missing");
2939
2940 if (reachable(src)) {
2941 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
2942 } else {
2943 lea(rscratch, src);
2944 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
2945 }
2946 }
2947
2948 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2949 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2950 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2951
2952 vandps(dst, nds, negate_field, vector_len, rscratch);
2953 }
2954
2955 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2956 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2957 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2958
2959 vandpd(dst, nds, negate_field, vector_len, rscratch);
2960 }
2961
2962 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2963 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2964 Assembler::vpaddb(dst, nds, src, vector_len);
2965 }
2966
2967 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2968 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2969 Assembler::vpaddb(dst, nds, src, vector_len);
2970 }
2971
2972 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2973 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2974 Assembler::vpaddw(dst, nds, src, vector_len);
2975 }
2976
2977 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2978 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2979 Assembler::vpaddw(dst, nds, src, vector_len);
2980 }
2981
2982 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2983 assert(rscratch != noreg || always_reachable(src), "missing");
2984
2985 if (reachable(src)) {
2986 Assembler::vpand(dst, nds, as_Address(src), vector_len);
2987 } else {
2988 lea(rscratch, src);
2989 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
2990 }
2991 }
2992
2993 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2994 assert(rscratch != noreg || always_reachable(src), "missing");
2995
2996 if (reachable(src)) {
2997 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
2998 } else {
2999 lea(rscratch, src);
3000 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3001 }
3002 }
3003
3004 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3005 assert(rscratch != noreg || always_reachable(src), "missing");
3006
3007 if (reachable(src)) {
3008 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3009 } else {
3010 lea(rscratch, src);
3011 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3012 }
3013 }
3014
3015 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3016 assert(rscratch != noreg || always_reachable(src), "missing");
3017
3018 if (reachable(src)) {
3019 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3020 } else {
3021 lea(rscratch, src);
3022 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3023 }
3024 }
3025
3026 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3027 assert(rscratch != noreg || always_reachable(src), "missing");
3028
3029 if (reachable(src)) {
3030 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3031 } else {
3032 lea(rscratch, src);
3033 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3034 }
3035 }
3036
3037 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3038 assert(rscratch != noreg || always_reachable(src), "missing");
3039
3040 if (reachable(src)) {
3041 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3042 } else {
3043 lea(rscratch, src);
3044 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3045 }
3046 }
3047
3048 // Vector float blend
3049 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3050 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3051 // WARN: Allow dst == (src1|src2), mask == scratch
3052 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3053 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3054 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3055 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3056 if (blend_emulation && scratch_available && dst_available) {
3057 if (compute_mask) {
3058 vpsrad(scratch, mask, 32, vector_len);
3059 mask = scratch;
3060 }
3061 if (dst == src1) {
3062 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3063 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3064 } else {
3065 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3066 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3067 }
3068 vpor(dst, dst, scratch, vector_len);
3069 } else {
3070 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3071 }
3072 }
3073
3074 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3075 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3076 // WARN: Allow dst == (src1|src2), mask == scratch
3077 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
3078 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
3079 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3080 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3081 if (blend_emulation && scratch_available && dst_available) {
3082 if (compute_mask) {
3083 vpxor(scratch, scratch, scratch, vector_len);
3084 vpcmpgtq(scratch, scratch, mask, vector_len);
3085 mask = scratch;
3086 }
3087 if (dst == src1) {
3088 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3089 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3090 } else {
3091 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3092 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3093 }
3094 vpor(dst, dst, scratch, vector_len);
3095 } else {
3096 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3097 }
3098 }
3099
3100 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3101 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3102 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3103 }
3104
3105 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3106 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3107 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3108 }
3109
3110 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3111 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3112 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3113 }
3114
3115 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3116 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3117 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3118 }
3119
3120 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3121 assert(rscratch != noreg || always_reachable(src), "missing");
3122
3123 if (reachable(src)) {
3124 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3125 } else {
3126 lea(rscratch, src);
3127 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3128 }
3129 }
3130
3131 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3132 int comparison, bool is_signed, int vector_len, Register rscratch) {
3133 assert(rscratch != noreg || always_reachable(src), "missing");
3134
3135 if (reachable(src)) {
3136 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3137 } else {
3138 lea(rscratch, src);
3139 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3140 }
3141 }
3142
3143 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3144 int comparison, bool is_signed, int vector_len, Register rscratch) {
3145 assert(rscratch != noreg || always_reachable(src), "missing");
3146
3147 if (reachable(src)) {
3148 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3149 } else {
3150 lea(rscratch, src);
3151 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3152 }
3153 }
3154
3155 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3156 int comparison, bool is_signed, int vector_len, Register rscratch) {
3157 assert(rscratch != noreg || always_reachable(src), "missing");
3158
3159 if (reachable(src)) {
3160 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3161 } else {
3162 lea(rscratch, src);
3163 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3164 }
3165 }
3166
3167 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3168 int comparison, bool is_signed, int vector_len, Register rscratch) {
3169 assert(rscratch != noreg || always_reachable(src), "missing");
3170
3171 if (reachable(src)) {
3172 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3173 } else {
3174 lea(rscratch, src);
3175 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3176 }
3177 }
3178
3179 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3180 if (width == Assembler::Q) {
3181 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3182 } else {
3183 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3184 }
3185 }
3186
3187 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3188 int eq_cond_enc = 0x29;
3189 int gt_cond_enc = 0x37;
3190 if (width != Assembler::Q) {
3191 eq_cond_enc = 0x74 + width;
3192 gt_cond_enc = 0x64 + width;
3193 }
3194 switch (cond) {
3195 case eq:
3196 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3197 break;
3198 case neq:
3199 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3200 vallones(xtmp, vector_len);
3201 vpxor(dst, xtmp, dst, vector_len);
3202 break;
3203 case le:
3204 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3205 vallones(xtmp, vector_len);
3206 vpxor(dst, xtmp, dst, vector_len);
3207 break;
3208 case nlt:
3209 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3210 vallones(xtmp, vector_len);
3211 vpxor(dst, xtmp, dst, vector_len);
3212 break;
3213 case lt:
3214 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3215 break;
3216 case nle:
3217 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3218 break;
3219 default:
3220 assert(false, "Should not reach here");
3221 }
3222 }
3223
3224 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3225 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3226 Assembler::vpmovzxbw(dst, src, vector_len);
3227 }
3228
3229 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3230 assert((src->encoding() < 16),"XMM register should be 0-15");
3231 Assembler::vpmovmskb(dst, src, vector_len);
3232 }
3233
3234 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3235 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3236 Assembler::vpmullw(dst, nds, src, vector_len);
3237 }
3238
3239 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3240 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3241 Assembler::vpmullw(dst, nds, src, vector_len);
3242 }
3243
3244 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3245 assert((UseAVX > 0), "AVX support is needed");
3246 assert(rscratch != noreg || always_reachable(src), "missing");
3247
3248 if (reachable(src)) {
3249 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3250 } else {
3251 lea(rscratch, src);
3252 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3253 }
3254 }
3255
3256 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3257 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3258 Assembler::vpsubb(dst, nds, src, vector_len);
3259 }
3260
3261 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3262 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3263 Assembler::vpsubb(dst, nds, src, vector_len);
3264 }
3265
3266 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3267 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3268 Assembler::vpsubw(dst, nds, src, vector_len);
3269 }
3270
3271 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3272 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3273 Assembler::vpsubw(dst, nds, src, vector_len);
3274 }
3275
3276 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3277 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3278 Assembler::vpsraw(dst, nds, shift, vector_len);
3279 }
3280
3281 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3282 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3283 Assembler::vpsraw(dst, nds, shift, vector_len);
3284 }
3285
3286 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3287 assert(UseAVX > 2,"");
3288 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3289 vector_len = 2;
3290 }
3291 Assembler::evpsraq(dst, nds, shift, vector_len);
3292 }
3293
3294 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3295 assert(UseAVX > 2,"");
3296 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3297 vector_len = 2;
3298 }
3299 Assembler::evpsraq(dst, nds, shift, vector_len);
3300 }
3301
3302 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3303 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3304 Assembler::vpsrlw(dst, nds, shift, vector_len);
3305 }
3306
3307 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3308 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3309 Assembler::vpsrlw(dst, nds, shift, vector_len);
3310 }
3311
3312 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3313 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3314 Assembler::vpsllw(dst, nds, shift, vector_len);
3315 }
3316
3317 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3318 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3319 Assembler::vpsllw(dst, nds, shift, vector_len);
3320 }
3321
3322 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3323 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3324 Assembler::vptest(dst, src);
3325 }
3326
3327 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3328 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3329 Assembler::punpcklbw(dst, src);
3330 }
3331
3332 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3333 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3334 Assembler::pshufd(dst, src, mode);
3335 }
3336
3337 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3338 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3339 Assembler::pshuflw(dst, src, mode);
3340 }
3341
3342 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3343 assert(rscratch != noreg || always_reachable(src), "missing");
3344
3345 if (reachable(src)) {
3346 vandpd(dst, nds, as_Address(src), vector_len);
3347 } else {
3348 lea(rscratch, src);
3349 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3350 }
3351 }
3352
3353 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3354 assert(rscratch != noreg || always_reachable(src), "missing");
3355
3356 if (reachable(src)) {
3357 vandps(dst, nds, as_Address(src), vector_len);
3358 } else {
3359 lea(rscratch, src);
3360 vandps(dst, nds, Address(rscratch, 0), vector_len);
3361 }
3362 }
3363
3364 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3365 bool merge, int vector_len, Register rscratch) {
3366 assert(rscratch != noreg || always_reachable(src), "missing");
3367
3368 if (reachable(src)) {
3369 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3370 } else {
3371 lea(rscratch, src);
3372 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3373 }
3374 }
3375
3376 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3377 assert(rscratch != noreg || always_reachable(src), "missing");
3378
3379 if (reachable(src)) {
3380 vdivsd(dst, nds, as_Address(src));
3381 } else {
3382 lea(rscratch, src);
3383 vdivsd(dst, nds, Address(rscratch, 0));
3384 }
3385 }
3386
3387 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3388 assert(rscratch != noreg || always_reachable(src), "missing");
3389
3390 if (reachable(src)) {
3391 vdivss(dst, nds, as_Address(src));
3392 } else {
3393 lea(rscratch, src);
3394 vdivss(dst, nds, Address(rscratch, 0));
3395 }
3396 }
3397
3398 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3399 assert(rscratch != noreg || always_reachable(src), "missing");
3400
3401 if (reachable(src)) {
3402 vmulsd(dst, nds, as_Address(src));
3403 } else {
3404 lea(rscratch, src);
3405 vmulsd(dst, nds, Address(rscratch, 0));
3406 }
3407 }
3408
3409 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3410 assert(rscratch != noreg || always_reachable(src), "missing");
3411
3412 if (reachable(src)) {
3413 vmulss(dst, nds, as_Address(src));
3414 } else {
3415 lea(rscratch, src);
3416 vmulss(dst, nds, Address(rscratch, 0));
3417 }
3418 }
3419
3420 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3421 assert(rscratch != noreg || always_reachable(src), "missing");
3422
3423 if (reachable(src)) {
3424 vsubsd(dst, nds, as_Address(src));
3425 } else {
3426 lea(rscratch, src);
3427 vsubsd(dst, nds, Address(rscratch, 0));
3428 }
3429 }
3430
3431 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3432 assert(rscratch != noreg || always_reachable(src), "missing");
3433
3434 if (reachable(src)) {
3435 vsubss(dst, nds, as_Address(src));
3436 } else {
3437 lea(rscratch, src);
3438 vsubss(dst, nds, Address(rscratch, 0));
3439 }
3440 }
3441
3442 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3443 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3444 assert(rscratch != noreg || always_reachable(src), "missing");
3445
3446 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3447 }
3448
3449 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3450 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3451 assert(rscratch != noreg || always_reachable(src), "missing");
3452
3453 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3454 }
3455
3456 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3457 assert(rscratch != noreg || always_reachable(src), "missing");
3458
3459 if (reachable(src)) {
3460 vxorpd(dst, nds, as_Address(src), vector_len);
3461 } else {
3462 lea(rscratch, src);
3463 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3464 }
3465 }
3466
3467 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3468 assert(rscratch != noreg || always_reachable(src), "missing");
3469
3470 if (reachable(src)) {
3471 vxorps(dst, nds, as_Address(src), vector_len);
3472 } else {
3473 lea(rscratch, src);
3474 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3475 }
3476 }
3477
3478 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3479 assert(rscratch != noreg || always_reachable(src), "missing");
3480
3481 if (UseAVX > 1 || (vector_len < 1)) {
3482 if (reachable(src)) {
3483 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3484 } else {
3485 lea(rscratch, src);
3486 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3487 }
3488 } else {
3489 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3490 }
3491 }
3492
3493 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3494 assert(rscratch != noreg || always_reachable(src), "missing");
3495
3496 if (reachable(src)) {
3497 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3498 } else {
3499 lea(rscratch, src);
3500 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3501 }
3502 }
3503
3504 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3505 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3506 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3507 // The inverted mask is sign-extended
3508 andptr(possibly_non_local, inverted_mask);
3509 }
3510
3511 void MacroAssembler::resolve_jobject(Register value,
3512 Register tmp) {
3513 Register thread = r15_thread;
3514 assert_different_registers(value, thread, tmp);
3515 Label done, tagged, weak_tagged;
3516 testptr(value, value);
3517 jcc(Assembler::zero, done); // Use null as-is.
3518 testptr(value, JNIHandles::tag_mask); // Test for tag.
3519 jcc(Assembler::notZero, tagged);
3520
3521 // Resolve local handle
3522 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp);
3523 verify_oop(value);
3524 jmp(done);
3525
3526 bind(tagged);
3527 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3528 jcc(Assembler::notZero, weak_tagged);
3529
3530 // Resolve global handle
3531 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3532 verify_oop(value);
3533 jmp(done);
3534
3535 bind(weak_tagged);
3536 // Resolve jweak.
3537 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3538 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp);
3539 verify_oop(value);
3540
3541 bind(done);
3542 }
3543
3544 void MacroAssembler::resolve_global_jobject(Register value,
3545 Register tmp) {
3546 Register thread = r15_thread;
3547 assert_different_registers(value, thread, tmp);
3548 Label done;
3549
3550 testptr(value, value);
3551 jcc(Assembler::zero, done); // Use null as-is.
3552
3553 #ifdef ASSERT
3554 {
3555 Label valid_global_tag;
3556 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
3557 jcc(Assembler::notZero, valid_global_tag);
3558 stop("non global jobject using resolve_global_jobject");
3559 bind(valid_global_tag);
3560 }
3561 #endif
3562
3563 // Resolve global handle
3564 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3565 verify_oop(value);
3566
3567 bind(done);
3568 }
3569
3570 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3571 subq(dst, imm32);
3572 }
3573
3574 // Force generation of a 4 byte immediate value even if it fits into 8bit
3575 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3576 subq_imm32(dst, imm32);
3577 }
3578
3579 void MacroAssembler::subptr(Register dst, Register src) {
3580 subq(dst, src);
3581 }
3582
3583 // C++ bool manipulation
3584 void MacroAssembler::testbool(Register dst) {
3585 if(sizeof(bool) == 1)
3586 testb(dst, 0xff);
3587 else if(sizeof(bool) == 2) {
3588 // testw implementation needed for two byte bools
3589 ShouldNotReachHere();
3590 } else if(sizeof(bool) == 4)
3591 testl(dst, dst);
3592 else
3593 // unsupported
3594 ShouldNotReachHere();
3595 }
3596
3597 void MacroAssembler::testptr(Register dst, Register src) {
3598 testq(dst, src);
3599 }
3600
3601 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3602 void MacroAssembler::tlab_allocate(Register obj,
3603 Register var_size_in_bytes,
3604 int con_size_in_bytes,
3605 Register t1,
3606 Register t2,
3607 Label& slow_case) {
3608 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3609 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3610 }
3611
3612 RegSet MacroAssembler::call_clobbered_gp_registers() {
3613 RegSet regs;
3614 regs += RegSet::of(rax, rcx, rdx);
3615 #ifndef _WINDOWS
3616 regs += RegSet::of(rsi, rdi);
3617 #endif
3618 regs += RegSet::range(r8, r11);
3619 if (UseAPX) {
3620 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
3621 }
3622 return regs;
3623 }
3624
3625 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3626 int num_xmm_registers = XMMRegister::available_xmm_registers();
3627 #if defined(_WINDOWS)
3628 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3629 if (num_xmm_registers > 16) {
3630 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3631 }
3632 return result;
3633 #else
3634 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3635 #endif
3636 }
3637
3638 // C1 only ever uses the first double/float of the XMM register.
3639 static int xmm_save_size() { return sizeof(double); }
3640
3641 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3642 masm->movdbl(Address(rsp, offset), reg);
3643 }
3644
3645 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3646 masm->movdbl(reg, Address(rsp, offset));
3647 }
3648
3649 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
3650 bool save_fpu, int& gp_area_size, int& xmm_area_size) {
3651
3652 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
3653 StackAlignmentInBytes);
3654 xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
3655
3656 return gp_area_size + xmm_area_size;
3657 }
3658
3659 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3660 block_comment("push_call_clobbered_registers start");
3661 // Regular registers
3662 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3663
3664 int gp_area_size;
3665 int xmm_area_size;
3666 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3667 gp_area_size, xmm_area_size);
3668 subptr(rsp, total_save_size);
3669
3670 push_set(gp_registers_to_push, 0);
3671
3672 if (save_fpu) {
3673 push_set(call_clobbered_xmm_registers(), gp_area_size);
3674 }
3675
3676 block_comment("push_call_clobbered_registers end");
3677 }
3678
3679 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3680 block_comment("pop_call_clobbered_registers start");
3681
3682 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3683
3684 int gp_area_size;
3685 int xmm_area_size;
3686 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3687 gp_area_size, xmm_area_size);
3688
3689 if (restore_fpu) {
3690 pop_set(call_clobbered_xmm_registers(), gp_area_size);
3691 }
3692
3693 pop_set(gp_registers_to_pop, 0);
3694
3695 addptr(rsp, total_save_size);
3696
3697 vzeroupper();
3698
3699 block_comment("pop_call_clobbered_registers end");
3700 }
3701
3702 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3703 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3704 int spill_offset = offset;
3705
3706 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3707 save_xmm_register(this, spill_offset, *it);
3708 spill_offset += xmm_save_size();
3709 }
3710 }
3711
3712 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3713 int restore_size = set.size() * xmm_save_size();
3714 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3715
3716 int restore_offset = offset + restore_size - xmm_save_size();
3717
3718 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3719 restore_xmm_register(this, restore_offset, *it);
3720 restore_offset -= xmm_save_size();
3721 }
3722 }
3723
3724 void MacroAssembler::push_set(RegSet set, int offset) {
3725 int spill_offset;
3726 if (offset == -1) {
3727 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3728 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3729 subptr(rsp, aligned_size);
3730 spill_offset = 0;
3731 } else {
3732 spill_offset = offset;
3733 }
3734
3735 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3736 movptr(Address(rsp, spill_offset), *it);
3737 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3738 }
3739 }
3740
3741 void MacroAssembler::pop_set(RegSet set, int offset) {
3742
3743 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3744 int restore_size = set.size() * gp_reg_size;
3745 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3746
3747 int restore_offset;
3748 if (offset == -1) {
3749 restore_offset = restore_size - gp_reg_size;
3750 } else {
3751 restore_offset = offset + restore_size - gp_reg_size;
3752 }
3753 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3754 movptr(*it, Address(rsp, restore_offset));
3755 restore_offset -= gp_reg_size;
3756 }
3757
3758 if (offset == -1) {
3759 addptr(rsp, aligned_size);
3760 }
3761 }
3762
3763 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3764 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3765 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3766 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3767 Label done;
3768
3769 testptr(length_in_bytes, length_in_bytes);
3770 jcc(Assembler::zero, done);
3771
3772 // initialize topmost word, divide index by 2, check if odd and test if zero
3773 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3774 #ifdef ASSERT
3775 {
3776 Label L;
3777 testptr(length_in_bytes, BytesPerWord - 1);
3778 jcc(Assembler::zero, L);
3779 stop("length must be a multiple of BytesPerWord");
3780 bind(L);
3781 }
3782 #endif
3783 Register index = length_in_bytes;
3784 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3785 if (UseIncDec) {
3786 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3787 } else {
3788 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3789 shrptr(index, 1);
3790 }
3791
3792 // initialize remaining object fields: index is a multiple of 2 now
3793 {
3794 Label loop;
3795 bind(loop);
3796 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3797 decrement(index);
3798 jcc(Assembler::notZero, loop);
3799 }
3800
3801 bind(done);
3802 }
3803
3804 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
3805 movptr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
3806 #ifdef ASSERT
3807 {
3808 Label done;
3809 cmpptr(layout_info, 0);
3810 jcc(Assembler::notEqual, done);
3811 stop("inline_layout_info_array is null");
3812 bind(done);
3813 }
3814 #endif
3815
3816 InlineLayoutInfo array[2];
3817 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
3818 if (is_power_of_2(size)) {
3819 shll(index, log2i_exact(size)); // Scale index by power of 2
3820 } else {
3821 imull(index, index, size); // Scale the index to be the entry index * array_element_size
3822 }
3823 lea(layout_info, Address(layout_info, index, Address::times_1, Array<InlineLayoutInfo>::base_offset_in_bytes()));
3824 }
3825
3826 // Look up the method for a megamorphic invokeinterface call.
3827 // The target method is determined by <intf_klass, itable_index>.
3828 // The receiver klass is in recv_klass.
3829 // On success, the result will be in method_result, and execution falls through.
3830 // On failure, execution transfers to the given label.
3831 void MacroAssembler::lookup_interface_method(Register recv_klass,
3832 Register intf_klass,
3833 RegisterOrConstant itable_index,
3834 Register method_result,
3835 Register scan_temp,
3836 Label& L_no_such_interface,
3837 bool return_method) {
3838 assert_different_registers(recv_klass, intf_klass, scan_temp);
3839 assert_different_registers(method_result, intf_klass, scan_temp);
3840 assert(recv_klass != method_result || !return_method,
3841 "recv_klass can be destroyed when method isn't needed");
3842
3843 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3844 "caller must use same register for non-constant itable index as for method");
3845
3846 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3847 int vtable_base = in_bytes(Klass::vtable_start_offset());
3848 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3849 int scan_step = itableOffsetEntry::size() * wordSize;
3850 int vte_size = vtableEntry::size_in_bytes();
3851 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3852 assert(vte_size == wordSize, "else adjust times_vte_scale");
3853
3854 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3855
3856 // Could store the aligned, prescaled offset in the klass.
3857 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3858
3859 if (return_method) {
3860 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3861 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3862 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3863 }
3864
3865 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
3866 // if (scan->interface() == intf) {
3867 // result = (klass + scan->offset() + itable_index);
3868 // }
3869 // }
3870 Label search, found_method;
3871
3872 for (int peel = 1; peel >= 0; peel--) {
3873 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
3874 cmpptr(intf_klass, method_result);
3875
3876 if (peel) {
3877 jccb(Assembler::equal, found_method);
3878 } else {
3879 jccb(Assembler::notEqual, search);
3880 // (invert the test to fall through to found_method...)
3881 }
3882
3883 if (!peel) break;
3884
3885 bind(search);
3886
3887 // Check that the previous entry is non-null. A null entry means that
3888 // the receiver class doesn't implement the interface, and wasn't the
3889 // same as when the caller was compiled.
3890 testptr(method_result, method_result);
3891 jcc(Assembler::zero, L_no_such_interface);
3892 addptr(scan_temp, scan_step);
3893 }
3894
3895 bind(found_method);
3896
3897 if (return_method) {
3898 // Got a hit.
3899 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
3900 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3901 }
3902 }
3903
3904 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
3905 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
3906 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
3907 // The target method is determined by <holder_klass, itable_index>.
3908 // The receiver klass is in recv_klass.
3909 // On success, the result will be in method_result, and execution falls through.
3910 // On failure, execution transfers to the given label.
3911 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
3912 Register holder_klass,
3913 Register resolved_klass,
3914 Register method_result,
3915 Register scan_temp,
3916 Register temp_reg2,
3917 Register receiver,
3918 int itable_index,
3919 Label& L_no_such_interface) {
3920 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
3921 Register temp_itbl_klass = method_result;
3922 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
3923
3924 int vtable_base = in_bytes(Klass::vtable_start_offset());
3925 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3926 int scan_step = itableOffsetEntry::size() * wordSize;
3927 int vte_size = vtableEntry::size_in_bytes();
3928 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
3929 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
3930 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3931 assert(vte_size == wordSize, "adjust times_vte_scale");
3932
3933 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
3934
3935 // temp_itbl_klass = recv_klass.itable[0]
3936 // scan_temp = &recv_klass.itable[0] + step
3937 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3938 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
3939 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
3940 xorptr(temp_reg, temp_reg);
3941
3942 // Initial checks:
3943 // - if (holder_klass != resolved_klass), go to "scan for resolved"
3944 // - if (itable[0] == 0), no such interface
3945 // - if (itable[0] == holder_klass), shortcut to "holder found"
3946 cmpptr(holder_klass, resolved_klass);
3947 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
3948 testptr(temp_itbl_klass, temp_itbl_klass);
3949 jccb(Assembler::zero, L_no_such_interface);
3950 cmpptr(holder_klass, temp_itbl_klass);
3951 jccb(Assembler::equal, L_holder_found);
3952
3953 // Loop: Look for holder_klass record in itable
3954 // do {
3955 // tmp = itable[index];
3956 // index += step;
3957 // if (tmp == holder_klass) {
3958 // goto L_holder_found; // Found!
3959 // }
3960 // } while (tmp != 0);
3961 // goto L_no_such_interface // Not found.
3962 Label L_scan_holder;
3963 bind(L_scan_holder);
3964 movptr(temp_itbl_klass, Address(scan_temp, 0));
3965 addptr(scan_temp, scan_step);
3966 cmpptr(holder_klass, temp_itbl_klass);
3967 jccb(Assembler::equal, L_holder_found);
3968 testptr(temp_itbl_klass, temp_itbl_klass);
3969 jccb(Assembler::notZero, L_scan_holder);
3970
3971 jmpb(L_no_such_interface);
3972
3973 // Loop: Look for resolved_class record in itable
3974 // do {
3975 // tmp = itable[index];
3976 // index += step;
3977 // if (tmp == holder_klass) {
3978 // // Also check if we have met a holder klass
3979 // holder_tmp = itable[index-step-ioffset];
3980 // }
3981 // if (tmp == resolved_klass) {
3982 // goto L_resolved_found; // Found!
3983 // }
3984 // } while (tmp != 0);
3985 // goto L_no_such_interface // Not found.
3986 //
3987 Label L_loop_scan_resolved;
3988 bind(L_loop_scan_resolved);
3989 movptr(temp_itbl_klass, Address(scan_temp, 0));
3990 addptr(scan_temp, scan_step);
3991 bind(L_loop_scan_resolved_entry);
3992 cmpptr(holder_klass, temp_itbl_klass);
3993 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
3994 cmpptr(resolved_klass, temp_itbl_klass);
3995 jccb(Assembler::equal, L_resolved_found);
3996 testptr(temp_itbl_klass, temp_itbl_klass);
3997 jccb(Assembler::notZero, L_loop_scan_resolved);
3998
3999 jmpb(L_no_such_interface);
4000
4001 Label L_ready;
4002
4003 // See if we already have a holder klass. If not, go and scan for it.
4004 bind(L_resolved_found);
4005 testptr(temp_reg, temp_reg);
4006 jccb(Assembler::zero, L_scan_holder);
4007 jmpb(L_ready);
4008
4009 bind(L_holder_found);
4010 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4011
4012 // Finally, temp_reg contains holder_klass vtable offset
4013 bind(L_ready);
4014 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4015 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4016 load_klass(scan_temp, receiver, noreg);
4017 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4018 } else {
4019 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4020 }
4021 }
4022
4023
4024 // virtual method calling
4025 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4026 RegisterOrConstant vtable_index,
4027 Register method_result) {
4028 const ByteSize base = Klass::vtable_start_offset();
4029 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4030 Address vtable_entry_addr(recv_klass,
4031 vtable_index, Address::times_ptr,
4032 base + vtableEntry::method_offset());
4033 movptr(method_result, vtable_entry_addr);
4034 }
4035
4036
4037 void MacroAssembler::check_klass_subtype(Register sub_klass,
4038 Register super_klass,
4039 Register temp_reg,
4040 Label& L_success) {
4041 Label L_failure;
4042 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4043 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4044 bind(L_failure);
4045 }
4046
4047
4048 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4049 Register super_klass,
4050 Register temp_reg,
4051 Label* L_success,
4052 Label* L_failure,
4053 Label* L_slow_path,
4054 RegisterOrConstant super_check_offset) {
4055 assert_different_registers(sub_klass, super_klass, temp_reg);
4056 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4057 if (super_check_offset.is_register()) {
4058 assert_different_registers(sub_klass, super_klass,
4059 super_check_offset.as_register());
4060 } else if (must_load_sco) {
4061 assert(temp_reg != noreg, "supply either a temp or a register offset");
4062 }
4063
4064 Label L_fallthrough;
4065 int label_nulls = 0;
4066 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4067 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4068 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4069 assert(label_nulls <= 1, "at most one null in the batch");
4070
4071 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4072 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4073 Address super_check_offset_addr(super_klass, sco_offset);
4074
4075 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4076 // range of a jccb. If this routine grows larger, reconsider at
4077 // least some of these.
4078 #define local_jcc(assembler_cond, label) \
4079 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4080 else jcc( assembler_cond, label) /*omit semi*/
4081
4082 // Hacked jmp, which may only be used just before L_fallthrough.
4083 #define final_jmp(label) \
4084 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4085 else jmp(label) /*omit semi*/
4086
4087 // If the pointers are equal, we are done (e.g., String[] elements).
4088 // This self-check enables sharing of secondary supertype arrays among
4089 // non-primary types such as array-of-interface. Otherwise, each such
4090 // type would need its own customized SSA.
4091 // We move this check to the front of the fast path because many
4092 // type checks are in fact trivially successful in this manner,
4093 // so we get a nicely predicted branch right at the start of the check.
4094 cmpptr(sub_klass, super_klass);
4095 local_jcc(Assembler::equal, *L_success);
4096
4097 // Check the supertype display:
4098 if (must_load_sco) {
4099 // Positive movl does right thing on LP64.
4100 movl(temp_reg, super_check_offset_addr);
4101 super_check_offset = RegisterOrConstant(temp_reg);
4102 }
4103 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4104 cmpptr(super_klass, super_check_addr); // load displayed supertype
4105
4106 // This check has worked decisively for primary supers.
4107 // Secondary supers are sought in the super_cache ('super_cache_addr').
4108 // (Secondary supers are interfaces and very deeply nested subtypes.)
4109 // This works in the same check above because of a tricky aliasing
4110 // between the super_cache and the primary super display elements.
4111 // (The 'super_check_addr' can address either, as the case requires.)
4112 // Note that the cache is updated below if it does not help us find
4113 // what we need immediately.
4114 // So if it was a primary super, we can just fail immediately.
4115 // Otherwise, it's the slow path for us (no success at this point).
4116
4117 if (super_check_offset.is_register()) {
4118 local_jcc(Assembler::equal, *L_success);
4119 cmpl(super_check_offset.as_register(), sc_offset);
4120 if (L_failure == &L_fallthrough) {
4121 local_jcc(Assembler::equal, *L_slow_path);
4122 } else {
4123 local_jcc(Assembler::notEqual, *L_failure);
4124 final_jmp(*L_slow_path);
4125 }
4126 } else if (super_check_offset.as_constant() == sc_offset) {
4127 // Need a slow path; fast failure is impossible.
4128 if (L_slow_path == &L_fallthrough) {
4129 local_jcc(Assembler::equal, *L_success);
4130 } else {
4131 local_jcc(Assembler::notEqual, *L_slow_path);
4132 final_jmp(*L_success);
4133 }
4134 } else {
4135 // No slow path; it's a fast decision.
4136 if (L_failure == &L_fallthrough) {
4137 local_jcc(Assembler::equal, *L_success);
4138 } else {
4139 local_jcc(Assembler::notEqual, *L_failure);
4140 final_jmp(*L_success);
4141 }
4142 }
4143
4144 bind(L_fallthrough);
4145
4146 #undef local_jcc
4147 #undef final_jmp
4148 }
4149
4150
4151 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4152 Register super_klass,
4153 Register temp_reg,
4154 Register temp2_reg,
4155 Label* L_success,
4156 Label* L_failure,
4157 bool set_cond_codes) {
4158 assert_different_registers(sub_klass, super_klass, temp_reg);
4159 if (temp2_reg != noreg)
4160 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4161 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4162
4163 Label L_fallthrough;
4164 int label_nulls = 0;
4165 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4166 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4167 assert(label_nulls <= 1, "at most one null in the batch");
4168
4169 // a couple of useful fields in sub_klass:
4170 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4171 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4172 Address secondary_supers_addr(sub_klass, ss_offset);
4173 Address super_cache_addr( sub_klass, sc_offset);
4174
4175 // Do a linear scan of the secondary super-klass chain.
4176 // This code is rarely used, so simplicity is a virtue here.
4177 // The repne_scan instruction uses fixed registers, which we must spill.
4178 // Don't worry too much about pre-existing connections with the input regs.
4179
4180 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4181 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4182
4183 // Get super_klass value into rax (even if it was in rdi or rcx).
4184 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4185 if (super_klass != rax) {
4186 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4187 mov(rax, super_klass);
4188 }
4189 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4190 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4191
4192 #ifndef PRODUCT
4193 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4194 ExternalAddress pst_counter_addr((address) pst_counter);
4195 lea(rcx, pst_counter_addr);
4196 incrementl(Address(rcx, 0));
4197 #endif //PRODUCT
4198
4199 // We will consult the secondary-super array.
4200 movptr(rdi, secondary_supers_addr);
4201 // Load the array length. (Positive movl does right thing on LP64.)
4202 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4203 // Skip to start of data.
4204 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4205
4206 // Scan RCX words at [RDI] for an occurrence of RAX.
4207 // Set NZ/Z based on last compare.
4208 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4209 // not change flags (only scas instruction which is repeated sets flags).
4210 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4211
4212 testptr(rax,rax); // Set Z = 0
4213 repne_scan();
4214
4215 // Unspill the temp. registers:
4216 if (pushed_rdi) pop(rdi);
4217 if (pushed_rcx) pop(rcx);
4218 if (pushed_rax) pop(rax);
4219
4220 if (set_cond_codes) {
4221 // Special hack for the AD files: rdi is guaranteed non-zero.
4222 assert(!pushed_rdi, "rdi must be left non-null");
4223 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4224 }
4225
4226 if (L_failure == &L_fallthrough)
4227 jccb(Assembler::notEqual, *L_failure);
4228 else jcc(Assembler::notEqual, *L_failure);
4229
4230 // Success. Cache the super we found and proceed in triumph.
4231 movptr(super_cache_addr, super_klass);
4232
4233 if (L_success != &L_fallthrough) {
4234 jmp(*L_success);
4235 }
4236
4237 #undef IS_A_TEMP
4238
4239 bind(L_fallthrough);
4240 }
4241
4242 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4243 Register super_klass,
4244 Register temp_reg,
4245 Register temp2_reg,
4246 Label* L_success,
4247 Label* L_failure,
4248 bool set_cond_codes) {
4249 assert(set_cond_codes == false, "must be false on 64-bit x86");
4250 check_klass_subtype_slow_path
4251 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4252 L_success, L_failure);
4253 }
4254
4255 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4256 Register super_klass,
4257 Register temp_reg,
4258 Register temp2_reg,
4259 Register temp3_reg,
4260 Register temp4_reg,
4261 Label* L_success,
4262 Label* L_failure) {
4263 if (UseSecondarySupersTable) {
4264 check_klass_subtype_slow_path_table
4265 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4266 L_success, L_failure);
4267 } else {
4268 check_klass_subtype_slow_path_linear
4269 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4270 }
4271 }
4272
4273 Register MacroAssembler::allocate_if_noreg(Register r,
4274 RegSetIterator<Register> &available_regs,
4275 RegSet ®s_to_push) {
4276 if (!r->is_valid()) {
4277 r = *available_regs++;
4278 regs_to_push += r;
4279 }
4280 return r;
4281 }
4282
4283 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4284 Register super_klass,
4285 Register temp_reg,
4286 Register temp2_reg,
4287 Register temp3_reg,
4288 Register result_reg,
4289 Label* L_success,
4290 Label* L_failure) {
4291 // NB! Callers may assume that, when temp2_reg is a valid register,
4292 // this code sets it to a nonzero value.
4293 bool temp2_reg_was_valid = temp2_reg->is_valid();
4294
4295 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4296
4297 Label L_fallthrough;
4298 int label_nulls = 0;
4299 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4300 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4301 assert(label_nulls <= 1, "at most one null in the batch");
4302
4303 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4304
4305 RegSetIterator<Register> available_regs
4306 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4307
4308 RegSet pushed_regs;
4309
4310 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4311 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4312 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4313 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4314 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4315
4316 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4317
4318 {
4319
4320 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4321 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4322 subptr(rsp, aligned_size);
4323 push_set(pushed_regs, 0);
4324
4325 lookup_secondary_supers_table_var(sub_klass,
4326 super_klass,
4327 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4328 cmpq(result_reg, 0);
4329
4330 // Unspill the temp. registers:
4331 pop_set(pushed_regs, 0);
4332 // Increment SP but do not clobber flags.
4333 lea(rsp, Address(rsp, aligned_size));
4334 }
4335
4336 if (temp2_reg_was_valid) {
4337 movq(temp2_reg, 1);
4338 }
4339
4340 jcc(Assembler::notEqual, *L_failure);
4341
4342 if (L_success != &L_fallthrough) {
4343 jmp(*L_success);
4344 }
4345
4346 bind(L_fallthrough);
4347 }
4348
4349 // population_count variant for running without the POPCNT
4350 // instruction, which was introduced with SSE4.2 in 2008.
4351 void MacroAssembler::population_count(Register dst, Register src,
4352 Register scratch1, Register scratch2) {
4353 assert_different_registers(src, scratch1, scratch2);
4354 if (UsePopCountInstruction) {
4355 Assembler::popcntq(dst, src);
4356 } else {
4357 assert_different_registers(src, scratch1, scratch2);
4358 assert_different_registers(dst, scratch1, scratch2);
4359 Label loop, done;
4360
4361 mov(scratch1, src);
4362 // dst = 0;
4363 // while(scratch1 != 0) {
4364 // dst++;
4365 // scratch1 &= (scratch1 - 1);
4366 // }
4367 xorl(dst, dst);
4368 testq(scratch1, scratch1);
4369 jccb(Assembler::equal, done);
4370 {
4371 bind(loop);
4372 incq(dst);
4373 movq(scratch2, scratch1);
4374 decq(scratch2);
4375 andq(scratch1, scratch2);
4376 jccb(Assembler::notEqual, loop);
4377 }
4378 bind(done);
4379 }
4380 #ifdef ASSERT
4381 mov64(scratch1, 0xCafeBabeDeadBeef);
4382 movq(scratch2, scratch1);
4383 #endif
4384 }
4385
4386 // Ensure that the inline code and the stub are using the same registers.
4387 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4388 do { \
4389 assert(r_super_klass == rax, "mismatch"); \
4390 assert(r_array_base == rbx, "mismatch"); \
4391 assert(r_array_length == rcx, "mismatch"); \
4392 assert(r_array_index == rdx, "mismatch"); \
4393 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4394 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4395 assert(result == rdi || result == noreg, "mismatch"); \
4396 } while(0)
4397
4398 // Versions of salq and rorq that don't need count to be in rcx
4399
4400 void MacroAssembler::salq(Register dest, Register count) {
4401 if (count == rcx) {
4402 Assembler::salq(dest);
4403 } else {
4404 assert_different_registers(rcx, dest);
4405 xchgq(rcx, count);
4406 Assembler::salq(dest);
4407 xchgq(rcx, count);
4408 }
4409 }
4410
4411 void MacroAssembler::rorq(Register dest, Register count) {
4412 if (count == rcx) {
4413 Assembler::rorq(dest);
4414 } else {
4415 assert_different_registers(rcx, dest);
4416 xchgq(rcx, count);
4417 Assembler::rorq(dest);
4418 xchgq(rcx, count);
4419 }
4420 }
4421
4422 // Return true: we succeeded in generating this code
4423 //
4424 // At runtime, return 0 in result if r_super_klass is a superclass of
4425 // r_sub_klass, otherwise return nonzero. Use this if you know the
4426 // super_klass_slot of the class you're looking for. This is always
4427 // the case for instanceof and checkcast.
4428 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4429 Register r_super_klass,
4430 Register temp1,
4431 Register temp2,
4432 Register temp3,
4433 Register temp4,
4434 Register result,
4435 u1 super_klass_slot) {
4436 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4437
4438 Label L_fallthrough, L_success, L_failure;
4439
4440 BLOCK_COMMENT("lookup_secondary_supers_table {");
4441
4442 const Register
4443 r_array_index = temp1,
4444 r_array_length = temp2,
4445 r_array_base = temp3,
4446 r_bitmap = temp4;
4447
4448 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4449
4450 xorq(result, result); // = 0
4451
4452 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4453 movq(r_array_index, r_bitmap);
4454
4455 // First check the bitmap to see if super_klass might be present. If
4456 // the bit is zero, we are certain that super_klass is not one of
4457 // the secondary supers.
4458 u1 bit = super_klass_slot;
4459 {
4460 // NB: If the count in a x86 shift instruction is 0, the flags are
4461 // not affected, so we do a testq instead.
4462 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4463 if (shift_count != 0) {
4464 salq(r_array_index, shift_count);
4465 } else {
4466 testq(r_array_index, r_array_index);
4467 }
4468 }
4469 // We test the MSB of r_array_index, i.e. its sign bit
4470 jcc(Assembler::positive, L_failure);
4471
4472 // Get the first array index that can contain super_klass into r_array_index.
4473 if (bit != 0) {
4474 population_count(r_array_index, r_array_index, temp2, temp3);
4475 } else {
4476 movl(r_array_index, 1);
4477 }
4478 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4479
4480 // We will consult the secondary-super array.
4481 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4482
4483 // We're asserting that the first word in an Array<Klass*> is the
4484 // length, and the second word is the first word of the data. If
4485 // that ever changes, r_array_base will have to be adjusted here.
4486 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4487 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4488
4489 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4490 jccb(Assembler::equal, L_success);
4491
4492 // Is there another entry to check? Consult the bitmap.
4493 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4494 jccb(Assembler::carryClear, L_failure);
4495
4496 // Linear probe. Rotate the bitmap so that the next bit to test is
4497 // in Bit 1.
4498 if (bit != 0) {
4499 rorq(r_bitmap, bit);
4500 }
4501
4502 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4503 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4504 // Kills: r_array_length.
4505 // Returns: result.
4506 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4507 // Result (0/1) is in rdi
4508 jmpb(L_fallthrough);
4509
4510 bind(L_failure);
4511 incq(result); // 0 => 1
4512
4513 bind(L_success);
4514 // result = 0;
4515
4516 bind(L_fallthrough);
4517 BLOCK_COMMENT("} lookup_secondary_supers_table");
4518
4519 if (VerifySecondarySupers) {
4520 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4521 temp1, temp2, temp3);
4522 }
4523 }
4524
4525 // At runtime, return 0 in result if r_super_klass is a superclass of
4526 // r_sub_klass, otherwise return nonzero. Use this version of
4527 // lookup_secondary_supers_table() if you don't know ahead of time
4528 // which superclass will be searched for. Used by interpreter and
4529 // runtime stubs. It is larger and has somewhat greater latency than
4530 // the version above, which takes a constant super_klass_slot.
4531 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
4532 Register r_super_klass,
4533 Register temp1,
4534 Register temp2,
4535 Register temp3,
4536 Register temp4,
4537 Register result) {
4538 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4539 assert_different_registers(r_sub_klass, r_super_klass, rcx);
4540 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
4541
4542 Label L_fallthrough, L_success, L_failure;
4543
4544 BLOCK_COMMENT("lookup_secondary_supers_table {");
4545
4546 RegSetIterator<Register> available_regs = (temps - rcx).begin();
4547
4548 // FIXME. Once we are sure that all paths reaching this point really
4549 // do pass rcx as one of our temps we can get rid of the following
4550 // workaround.
4551 assert(temps.contains(rcx), "fix this code");
4552
4553 // We prefer to have our shift count in rcx. If rcx is one of our
4554 // temps, use it for slot. If not, pick any of our temps.
4555 Register slot;
4556 if (!temps.contains(rcx)) {
4557 slot = *available_regs++;
4558 } else {
4559 slot = rcx;
4560 }
4561
4562 const Register r_array_index = *available_regs++;
4563 const Register r_bitmap = *available_regs++;
4564
4565 // The logic above guarantees this property, but we state it here.
4566 assert_different_registers(r_array_index, r_bitmap, rcx);
4567
4568 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4569 movq(r_array_index, r_bitmap);
4570
4571 // First check the bitmap to see if super_klass might be present. If
4572 // the bit is zero, we are certain that super_klass is not one of
4573 // the secondary supers.
4574 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4575 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
4576 salq(r_array_index, slot);
4577
4578 testq(r_array_index, r_array_index);
4579 // We test the MSB of r_array_index, i.e. its sign bit
4580 jcc(Assembler::positive, L_failure);
4581
4582 const Register r_array_base = *available_regs++;
4583
4584 // Get the first array index that can contain super_klass into r_array_index.
4585 // Note: Clobbers r_array_base and slot.
4586 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
4587
4588 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4589
4590 // We will consult the secondary-super array.
4591 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4592
4593 // We're asserting that the first word in an Array<Klass*> is the
4594 // length, and the second word is the first word of the data. If
4595 // that ever changes, r_array_base will have to be adjusted here.
4596 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4597 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4598
4599 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4600 jccb(Assembler::equal, L_success);
4601
4602 // Restore slot to its true value
4603 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4604
4605 // Linear probe. Rotate the bitmap so that the next bit to test is
4606 // in Bit 1.
4607 rorq(r_bitmap, slot);
4608
4609 // Is there another entry to check? Consult the bitmap.
4610 btq(r_bitmap, 1);
4611 jccb(Assembler::carryClear, L_failure);
4612
4613 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4614 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4615 // Kills: r_array_length.
4616 // Returns: result.
4617 lookup_secondary_supers_table_slow_path(r_super_klass,
4618 r_array_base,
4619 r_array_index,
4620 r_bitmap,
4621 /*temp1*/result,
4622 /*temp2*/slot,
4623 &L_success,
4624 nullptr);
4625
4626 bind(L_failure);
4627 movq(result, 1);
4628 jmpb(L_fallthrough);
4629
4630 bind(L_success);
4631 xorq(result, result); // = 0
4632
4633 bind(L_fallthrough);
4634 BLOCK_COMMENT("} lookup_secondary_supers_table");
4635
4636 if (VerifySecondarySupers) {
4637 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4638 temp1, temp2, temp3);
4639 }
4640 }
4641
4642 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4643 Label* L_success, Label* L_failure) {
4644 Label L_loop, L_fallthrough;
4645 {
4646 int label_nulls = 0;
4647 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4648 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4649 assert(label_nulls <= 1, "at most one null in the batch");
4650 }
4651 bind(L_loop);
4652 cmpq(value, Address(addr, count, Address::times_8));
4653 jcc(Assembler::equal, *L_success);
4654 addl(count, 1);
4655 cmpl(count, limit);
4656 jcc(Assembler::less, L_loop);
4657
4658 if (&L_fallthrough != L_failure) {
4659 jmp(*L_failure);
4660 }
4661 bind(L_fallthrough);
4662 }
4663
4664 // Called by code generated by check_klass_subtype_slow_path
4665 // above. This is called when there is a collision in the hashed
4666 // lookup in the secondary supers array.
4667 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4668 Register r_array_base,
4669 Register r_array_index,
4670 Register r_bitmap,
4671 Register temp1,
4672 Register temp2,
4673 Label* L_success,
4674 Label* L_failure) {
4675 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4676
4677 const Register
4678 r_array_length = temp1,
4679 r_sub_klass = noreg,
4680 result = noreg;
4681
4682 Label L_fallthrough;
4683 int label_nulls = 0;
4684 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4685 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4686 assert(label_nulls <= 1, "at most one null in the batch");
4687
4688 // Load the array length.
4689 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4690 // And adjust the array base to point to the data.
4691 // NB! Effectively increments current slot index by 1.
4692 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4693 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4694
4695 // Linear probe
4696 Label L_huge;
4697
4698 // The bitmap is full to bursting.
4699 // Implicit invariant: BITMAP_FULL implies (length > 0)
4700 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
4701 jcc(Assembler::greater, L_huge);
4702
4703 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4704 // current slot (at secondary_supers[r_array_index]) has not yet
4705 // been inspected, and r_array_index may be out of bounds if we
4706 // wrapped around the end of the array.
4707
4708 { // This is conventional linear probing, but instead of terminating
4709 // when a null entry is found in the table, we maintain a bitmap
4710 // in which a 0 indicates missing entries.
4711 // The check above guarantees there are 0s in the bitmap, so the loop
4712 // eventually terminates.
4713
4714 xorl(temp2, temp2); // = 0;
4715
4716 Label L_again;
4717 bind(L_again);
4718
4719 // Check for array wraparound.
4720 cmpl(r_array_index, r_array_length);
4721 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4722
4723 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4724 jcc(Assembler::equal, *L_success);
4725
4726 // If the next bit in bitmap is zero, we're done.
4727 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4728 jcc(Assembler::carryClear, *L_failure);
4729
4730 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4731 addl(r_array_index, 1);
4732
4733 jmp(L_again);
4734 }
4735
4736 { // Degenerate case: more than 64 secondary supers.
4737 // FIXME: We could do something smarter here, maybe a vectorized
4738 // comparison or a binary search, but is that worth any added
4739 // complexity?
4740 bind(L_huge);
4741 xorl(r_array_index, r_array_index); // = 0
4742 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4743 L_success,
4744 (&L_fallthrough != L_failure ? L_failure : nullptr));
4745
4746 bind(L_fallthrough);
4747 }
4748 }
4749
4750 struct VerifyHelperArguments {
4751 Klass* _super;
4752 Klass* _sub;
4753 intptr_t _linear_result;
4754 intptr_t _table_result;
4755 };
4756
4757 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
4758 Klass::on_secondary_supers_verification_failure(args->_super,
4759 args->_sub,
4760 args->_linear_result,
4761 args->_table_result,
4762 msg);
4763 }
4764
4765 // Make sure that the hashed lookup and a linear scan agree.
4766 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
4767 Register r_super_klass,
4768 Register result,
4769 Register temp1,
4770 Register temp2,
4771 Register temp3) {
4772 const Register
4773 r_array_index = temp1,
4774 r_array_length = temp2,
4775 r_array_base = temp3,
4776 r_bitmap = noreg;
4777
4778 BLOCK_COMMENT("verify_secondary_supers_table {");
4779
4780 Label L_success, L_failure, L_check, L_done;
4781
4782 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4783 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4784 // And adjust the array base to point to the data.
4785 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4786
4787 testl(r_array_length, r_array_length); // array_length == 0?
4788 jcc(Assembler::zero, L_failure);
4789
4790 movl(r_array_index, 0);
4791 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
4792 // fall through to L_failure
4793
4794 const Register linear_result = r_array_index; // reuse temp1
4795
4796 bind(L_failure); // not present
4797 movl(linear_result, 1);
4798 jmp(L_check);
4799
4800 bind(L_success); // present
4801 movl(linear_result, 0);
4802
4803 bind(L_check);
4804 cmpl(linear_result, result);
4805 jcc(Assembler::equal, L_done);
4806
4807 { // To avoid calling convention issues, build a record on the stack
4808 // and pass the pointer to that instead.
4809 push(result);
4810 push(linear_result);
4811 push(r_sub_klass);
4812 push(r_super_klass);
4813 movptr(c_rarg1, rsp);
4814 movptr(c_rarg0, (uintptr_t) "mismatch");
4815 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
4816 should_not_reach_here();
4817 }
4818 bind(L_done);
4819
4820 BLOCK_COMMENT("} verify_secondary_supers_table");
4821 }
4822
4823 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
4824
4825 void MacroAssembler::clinit_barrier(Register klass, Label* L_fast_path, Label* L_slow_path) {
4826 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
4827
4828 Label L_fallthrough;
4829 if (L_fast_path == nullptr) {
4830 L_fast_path = &L_fallthrough;
4831 } else if (L_slow_path == nullptr) {
4832 L_slow_path = &L_fallthrough;
4833 }
4834
4835 // Fast path check: class is fully initialized.
4836 // init_state needs acquire, but x86 is TSO, and so we are already good.
4837 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4838 jcc(Assembler::equal, *L_fast_path);
4839
4840 // Fast path check: current thread is initializer thread
4841 cmpptr(r15_thread, Address(klass, InstanceKlass::init_thread_offset()));
4842 if (L_slow_path == &L_fallthrough) {
4843 jcc(Assembler::equal, *L_fast_path);
4844 bind(*L_slow_path);
4845 } else if (L_fast_path == &L_fallthrough) {
4846 jcc(Assembler::notEqual, *L_slow_path);
4847 bind(*L_fast_path);
4848 } else {
4849 Unimplemented();
4850 }
4851 }
4852
4853 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4854 if (VM_Version::supports_cmov()) {
4855 cmovl(cc, dst, src);
4856 } else {
4857 Label L;
4858 jccb(negate_condition(cc), L);
4859 movl(dst, src);
4860 bind(L);
4861 }
4862 }
4863
4864 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4865 if (VM_Version::supports_cmov()) {
4866 cmovl(cc, dst, src);
4867 } else {
4868 Label L;
4869 jccb(negate_condition(cc), L);
4870 movl(dst, src);
4871 bind(L);
4872 }
4873 }
4874
4875 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4876 if (!VerifyOops || VerifyAdapterSharing) {
4877 // Below address of the code string confuses VerifyAdapterSharing
4878 // because it may differ between otherwise equivalent adapters.
4879 return;
4880 }
4881
4882 BLOCK_COMMENT("verify_oop {");
4883 push(rscratch1);
4884 push(rax); // save rax
4885 push(reg); // pass register argument
4886
4887 // Pass register number to verify_oop_subroutine
4888 const char* b = nullptr;
4889 {
4890 ResourceMark rm;
4891 stringStream ss;
4892 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4893 b = code_string(ss.as_string());
4894 }
4895 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
4896 pushptr(buffer.addr(), rscratch1);
4897
4898 // call indirectly to solve generation ordering problem
4899 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4900 call(rax);
4901 // Caller pops the arguments (oop, message) and restores rax, r10
4902 BLOCK_COMMENT("} verify_oop");
4903 }
4904
4905 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4906 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4907 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
4908 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
4909 vpternlogd(dst, 0xFF, dst, dst, vector_len);
4910 } else if (VM_Version::supports_avx()) {
4911 vpcmpeqd(dst, dst, dst, vector_len);
4912 } else {
4913 pcmpeqd(dst, dst);
4914 }
4915 }
4916
4917 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4918 int extra_slot_offset) {
4919 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4920 int stackElementSize = Interpreter::stackElementSize;
4921 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4922 #ifdef ASSERT
4923 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4924 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4925 #endif
4926 Register scale_reg = noreg;
4927 Address::ScaleFactor scale_factor = Address::no_scale;
4928 if (arg_slot.is_constant()) {
4929 offset += arg_slot.as_constant() * stackElementSize;
4930 } else {
4931 scale_reg = arg_slot.as_register();
4932 scale_factor = Address::times(stackElementSize);
4933 }
4934 offset += wordSize; // return PC is on stack
4935 return Address(rsp, scale_reg, scale_factor, offset);
4936 }
4937
4938 // Handle the receiver type profile update given the "recv" klass.
4939 //
4940 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
4941 // If there are no matching or claimable receiver entries in RD, updates
4942 // the polymorphic counter.
4943 //
4944 // This code expected to run by either the interpreter or JIT-ed code, without
4945 // extra synchronization. For safety, receiver cells are claimed atomically, which
4946 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
4947 // counter updates are not atomic.
4948 //
4949 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
4950 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
4951 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
4952 int poly_count_offset = in_bytes(CounterData::count_offset());
4953 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
4954 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
4955
4956 // Adjust for MDP offsets. Slots are pointer-sized, so is the global offset.
4957 assert(is_aligned(mdp_offset, BytesPerWord), "sanity");
4958 base_receiver_offset += mdp_offset;
4959 end_receiver_offset += mdp_offset;
4960 poly_count_offset += mdp_offset;
4961
4962 // Scale down to optimize encoding. Slots are pointer-sized.
4963 assert(is_aligned(base_receiver_offset, BytesPerWord), "sanity");
4964 assert(is_aligned(end_receiver_offset, BytesPerWord), "sanity");
4965 assert(is_aligned(poly_count_offset, BytesPerWord), "sanity");
4966 assert(is_aligned(receiver_step, BytesPerWord), "sanity");
4967 assert(is_aligned(receiver_to_count_step, BytesPerWord), "sanity");
4968 base_receiver_offset >>= LogBytesPerWord;
4969 end_receiver_offset >>= LogBytesPerWord;
4970 poly_count_offset >>= LogBytesPerWord;
4971 receiver_step >>= LogBytesPerWord;
4972 receiver_to_count_step >>= LogBytesPerWord;
4973
4974 #ifdef ASSERT
4975 // We are about to walk the MDO slots without asking for offsets.
4976 // Check that our math hits all the right spots.
4977 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
4978 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
4979 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
4980 int offset = base_receiver_offset + receiver_step*c;
4981 int count_offset = offset + receiver_to_count_step;
4982 assert((offset << LogBytesPerWord) == real_recv_offset, "receiver slot math");
4983 assert((count_offset << LogBytesPerWord) == real_count_offset, "receiver count math");
4984 }
4985 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
4986 assert(poly_count_offset << LogBytesPerWord == real_poly_count_offset, "poly counter math");
4987 #endif
4988
4989 // Corner case: no profile table. Increment poly counter and exit.
4990 if (ReceiverTypeData::row_limit() == 0) {
4991 addptr(Address(mdp, poly_count_offset, Address::times_ptr), DataLayout::counter_increment);
4992 return;
4993 }
4994
4995 Register offset = rscratch1;
4996
4997 Label L_loop_search_receiver, L_loop_search_empty;
4998 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
4999
5000 // The code here recognizes three major cases:
5001 // A. Fastest: receiver found in the table
5002 // B. Fast: no receiver in the table, and the table is full
5003 // C. Slow: no receiver in the table, free slots in the table
5004 //
5005 // The case A performance is most important, as perfectly-behaved code would end up
5006 // there, especially with larger TypeProfileWidth. The case B performance is
5007 // important as well, this is where bulk of code would land for normally megamorphic
5008 // cases. The case C performance is not essential, its job is to deal with installation
5009 // races, we optimize for code density instead. Case C needs to make sure that receiver
5010 // rows are only claimed once. This makes sure we never overwrite a row for another
5011 // receiver and never duplicate the receivers in the list, making profile type-accurate.
5012 //
5013 // It is very tempting to handle these cases in a single loop, and claim the first slot
5014 // without checking the rest of the table. But, profiling code should tolerate free slots
5015 // in the table, as class unloading can clear them. After such cleanup, the receiver
5016 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
5017 // to complete, before trying to install new slots. Splitting the code in several tight
5018 // loops also helpfully optimizes for cases A and B.
5019 //
5020 // This code is effectively:
5021 //
5022 // restart:
5023 // // Fastest: receiver is already installed
5024 // for (i = 0; i < receiver_count(); i++) {
5025 // if (receiver(i) == recv) goto found_recv(i);
5026 // }
5027 //
5028 // // Fast: no receiver, but profile is full
5029 // for (i = 0; i < receiver_count(); i++) {
5030 // if (receiver(i) == null) goto found_null(i);
5031 // }
5032 // goto polymorphic
5033 //
5034 // // Slow: try to install receiver
5035 // found_null(i):
5036 // CAS(&receiver(i), null, recv);
5037 // goto restart
5038 //
5039 // polymorphic:
5040 // count++;
5041 // return
5042 //
5043 // found_recv(i):
5044 // *receiver_count(i)++
5045 //
5046
5047 bind(L_restart);
5048
5049 // Fastest: receiver is already installed
5050 movptr(offset, base_receiver_offset);
5051 bind(L_loop_search_receiver);
5052 cmpptr(recv, Address(mdp, offset, Address::times_ptr));
5053 jccb(Assembler::equal, L_found_recv);
5054 addptr(offset, receiver_step);
5055 cmpptr(offset, end_receiver_offset);
5056 jccb(Assembler::notEqual, L_loop_search_receiver);
5057
5058 // Fast: no receiver, but profile is full
5059 movptr(offset, base_receiver_offset);
5060 bind(L_loop_search_empty);
5061 cmpptr(Address(mdp, offset, Address::times_ptr), NULL_WORD);
5062 jccb(Assembler::equal, L_found_empty);
5063 addptr(offset, receiver_step);
5064 cmpptr(offset, end_receiver_offset);
5065 jccb(Assembler::notEqual, L_loop_search_empty);
5066 jmpb(L_polymorphic);
5067
5068 // Slow: try to install receiver
5069 bind(L_found_empty);
5070
5071 // Atomically swing receiver slot: null -> recv.
5072 //
5073 // The update code uses CAS, which wants RAX register specifically, *and* it needs
5074 // other important registers untouched, as they form the address. Therefore, we need
5075 // to shift any important registers from RAX into some other spare register. If we
5076 // have a spare register, we are forced to save it on stack here.
5077
5078 Register spare_reg = noreg;
5079 Register shifted_mdp = mdp;
5080 Register shifted_recv = recv;
5081 if (recv == rax || mdp == rax) {
5082 spare_reg = (recv != rbx && mdp != rbx) ? rbx :
5083 (recv != rcx && mdp != rcx) ? rcx :
5084 rdx;
5085 assert_different_registers(mdp, recv, offset, spare_reg);
5086
5087 push(spare_reg);
5088 if (recv == rax) {
5089 movptr(spare_reg, recv);
5090 shifted_recv = spare_reg;
5091 } else {
5092 assert(mdp == rax, "Remaining case");
5093 movptr(spare_reg, mdp);
5094 shifted_mdp = spare_reg;
5095 }
5096 } else {
5097 push(rax);
5098 }
5099
5100 // None of the important registers are in RAX after this shuffle.
5101 assert_different_registers(rax, shifted_mdp, shifted_recv, offset);
5102
5103 xorptr(rax, rax);
5104 cmpxchgptr(shifted_recv, Address(shifted_mdp, offset, Address::times_ptr));
5105
5106 // Unshift registers.
5107 if (recv == rax || mdp == rax) {
5108 movptr(rax, spare_reg);
5109 pop(spare_reg);
5110 } else {
5111 pop(rax);
5112 }
5113
5114 // CAS success means the slot now has the receiver we want. CAS failure means
5115 // something had claimed the slot concurrently: it can be the same receiver we want,
5116 // or something else. Since this is a slow path, we can optimize for code density,
5117 // and just restart the search from the beginning.
5118 jmpb(L_restart);
5119
5120 // Counter updates:
5121
5122 // Increment polymorphic counter instead of receiver slot.
5123 bind(L_polymorphic);
5124 movptr(offset, poly_count_offset);
5125 jmpb(L_count_update);
5126
5127 // Found a receiver, convert its slot offset to corresponding count offset.
5128 bind(L_found_recv);
5129 addptr(offset, receiver_to_count_step);
5130
5131 bind(L_count_update);
5132 addptr(Address(mdp, offset, Address::times_ptr), DataLayout::counter_increment);
5133 }
5134
5135 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5136 if (!VerifyOops || VerifyAdapterSharing) {
5137 // Below address of the code string confuses VerifyAdapterSharing
5138 // because it may differ between otherwise equivalent adapters.
5139 return;
5140 }
5141
5142 push(rscratch1);
5143 push(rax); // save rax,
5144 // addr may contain rsp so we will have to adjust it based on the push
5145 // we just did (and on 64 bit we do two pushes)
5146 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5147 // stores rax into addr which is backwards of what was intended.
5148 if (addr.uses(rsp)) {
5149 lea(rax, addr);
5150 pushptr(Address(rax, 2 * BytesPerWord));
5151 } else {
5152 pushptr(addr);
5153 }
5154
5155 // Pass register number to verify_oop_subroutine
5156 const char* b = nullptr;
5157 {
5158 ResourceMark rm;
5159 stringStream ss;
5160 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5161 b = code_string(ss.as_string());
5162 }
5163 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5164 pushptr(buffer.addr(), rscratch1);
5165
5166 // call indirectly to solve generation ordering problem
5167 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5168 call(rax);
5169 // Caller pops the arguments (addr, message) and restores rax, r10.
5170 }
5171
5172 void MacroAssembler::verify_tlab() {
5173 #ifdef ASSERT
5174 if (UseTLAB && VerifyOops) {
5175 Label next, ok;
5176 Register t1 = rsi;
5177
5178 push(t1);
5179
5180 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5181 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
5182 jcc(Assembler::aboveEqual, next);
5183 STOP("assert(top >= start)");
5184 should_not_reach_here();
5185
5186 bind(next);
5187 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
5188 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5189 jcc(Assembler::aboveEqual, ok);
5190 STOP("assert(top <= end)");
5191 should_not_reach_here();
5192
5193 bind(ok);
5194 pop(t1);
5195 }
5196 #endif
5197 }
5198
5199 class ControlWord {
5200 public:
5201 int32_t _value;
5202
5203 int rounding_control() const { return (_value >> 10) & 3 ; }
5204 int precision_control() const { return (_value >> 8) & 3 ; }
5205 bool precision() const { return ((_value >> 5) & 1) != 0; }
5206 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5207 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5208 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5209 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5210 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5211
5212 void print() const {
5213 // rounding control
5214 const char* rc;
5215 switch (rounding_control()) {
5216 case 0: rc = "round near"; break;
5217 case 1: rc = "round down"; break;
5218 case 2: rc = "round up "; break;
5219 case 3: rc = "chop "; break;
5220 default:
5221 rc = nullptr; // silence compiler warnings
5222 fatal("Unknown rounding control: %d", rounding_control());
5223 };
5224 // precision control
5225 const char* pc;
5226 switch (precision_control()) {
5227 case 0: pc = "24 bits "; break;
5228 case 1: pc = "reserved"; break;
5229 case 2: pc = "53 bits "; break;
5230 case 3: pc = "64 bits "; break;
5231 default:
5232 pc = nullptr; // silence compiler warnings
5233 fatal("Unknown precision control: %d", precision_control());
5234 };
5235 // flags
5236 char f[9];
5237 f[0] = ' ';
5238 f[1] = ' ';
5239 f[2] = (precision ()) ? 'P' : 'p';
5240 f[3] = (underflow ()) ? 'U' : 'u';
5241 f[4] = (overflow ()) ? 'O' : 'o';
5242 f[5] = (zero_divide ()) ? 'Z' : 'z';
5243 f[6] = (denormalized()) ? 'D' : 'd';
5244 f[7] = (invalid ()) ? 'I' : 'i';
5245 f[8] = '\x0';
5246 // output
5247 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5248 }
5249
5250 };
5251
5252 class StatusWord {
5253 public:
5254 int32_t _value;
5255
5256 bool busy() const { return ((_value >> 15) & 1) != 0; }
5257 bool C3() const { return ((_value >> 14) & 1) != 0; }
5258 bool C2() const { return ((_value >> 10) & 1) != 0; }
5259 bool C1() const { return ((_value >> 9) & 1) != 0; }
5260 bool C0() const { return ((_value >> 8) & 1) != 0; }
5261 int top() const { return (_value >> 11) & 7 ; }
5262 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5263 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5264 bool precision() const { return ((_value >> 5) & 1) != 0; }
5265 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5266 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5267 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5268 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5269 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5270
5271 void print() const {
5272 // condition codes
5273 char c[5];
5274 c[0] = (C3()) ? '3' : '-';
5275 c[1] = (C2()) ? '2' : '-';
5276 c[2] = (C1()) ? '1' : '-';
5277 c[3] = (C0()) ? '0' : '-';
5278 c[4] = '\x0';
5279 // flags
5280 char f[9];
5281 f[0] = (error_status()) ? 'E' : '-';
5282 f[1] = (stack_fault ()) ? 'S' : '-';
5283 f[2] = (precision ()) ? 'P' : '-';
5284 f[3] = (underflow ()) ? 'U' : '-';
5285 f[4] = (overflow ()) ? 'O' : '-';
5286 f[5] = (zero_divide ()) ? 'Z' : '-';
5287 f[6] = (denormalized()) ? 'D' : '-';
5288 f[7] = (invalid ()) ? 'I' : '-';
5289 f[8] = '\x0';
5290 // output
5291 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5292 }
5293
5294 };
5295
5296 class TagWord {
5297 public:
5298 int32_t _value;
5299
5300 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5301
5302 void print() const {
5303 printf("%04x", _value & 0xFFFF);
5304 }
5305
5306 };
5307
5308 class FPU_Register {
5309 public:
5310 int32_t _m0;
5311 int32_t _m1;
5312 int16_t _ex;
5313
5314 bool is_indefinite() const {
5315 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5316 }
5317
5318 void print() const {
5319 char sign = (_ex < 0) ? '-' : '+';
5320 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5321 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5322 };
5323
5324 };
5325
5326 class FPU_State {
5327 public:
5328 enum {
5329 register_size = 10,
5330 number_of_registers = 8,
5331 register_mask = 7
5332 };
5333
5334 ControlWord _control_word;
5335 StatusWord _status_word;
5336 TagWord _tag_word;
5337 int32_t _error_offset;
5338 int32_t _error_selector;
5339 int32_t _data_offset;
5340 int32_t _data_selector;
5341 int8_t _register[register_size * number_of_registers];
5342
5343 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5344 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5345
5346 const char* tag_as_string(int tag) const {
5347 switch (tag) {
5348 case 0: return "valid";
5349 case 1: return "zero";
5350 case 2: return "special";
5351 case 3: return "empty";
5352 }
5353 ShouldNotReachHere();
5354 return nullptr;
5355 }
5356
5357 void print() const {
5358 // print computation registers
5359 { int t = _status_word.top();
5360 for (int i = 0; i < number_of_registers; i++) {
5361 int j = (i - t) & register_mask;
5362 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5363 st(j)->print();
5364 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5365 }
5366 }
5367 printf("\n");
5368 // print control registers
5369 printf("ctrl = "); _control_word.print(); printf("\n");
5370 printf("stat = "); _status_word .print(); printf("\n");
5371 printf("tags = "); _tag_word .print(); printf("\n");
5372 }
5373
5374 };
5375
5376 class Flag_Register {
5377 public:
5378 int32_t _value;
5379
5380 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5381 bool direction() const { return ((_value >> 10) & 1) != 0; }
5382 bool sign() const { return ((_value >> 7) & 1) != 0; }
5383 bool zero() const { return ((_value >> 6) & 1) != 0; }
5384 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5385 bool parity() const { return ((_value >> 2) & 1) != 0; }
5386 bool carry() const { return ((_value >> 0) & 1) != 0; }
5387
5388 void print() const {
5389 // flags
5390 char f[8];
5391 f[0] = (overflow ()) ? 'O' : '-';
5392 f[1] = (direction ()) ? 'D' : '-';
5393 f[2] = (sign ()) ? 'S' : '-';
5394 f[3] = (zero ()) ? 'Z' : '-';
5395 f[4] = (auxiliary_carry()) ? 'A' : '-';
5396 f[5] = (parity ()) ? 'P' : '-';
5397 f[6] = (carry ()) ? 'C' : '-';
5398 f[7] = '\x0';
5399 // output
5400 printf("%08x flags = %s", _value, f);
5401 }
5402
5403 };
5404
5405 class IU_Register {
5406 public:
5407 int32_t _value;
5408
5409 void print() const {
5410 printf("%08x %11d", _value, _value);
5411 }
5412
5413 };
5414
5415 class IU_State {
5416 public:
5417 Flag_Register _eflags;
5418 IU_Register _rdi;
5419 IU_Register _rsi;
5420 IU_Register _rbp;
5421 IU_Register _rsp;
5422 IU_Register _rbx;
5423 IU_Register _rdx;
5424 IU_Register _rcx;
5425 IU_Register _rax;
5426
5427 void print() const {
5428 // computation registers
5429 printf("rax, = "); _rax.print(); printf("\n");
5430 printf("rbx, = "); _rbx.print(); printf("\n");
5431 printf("rcx = "); _rcx.print(); printf("\n");
5432 printf("rdx = "); _rdx.print(); printf("\n");
5433 printf("rdi = "); _rdi.print(); printf("\n");
5434 printf("rsi = "); _rsi.print(); printf("\n");
5435 printf("rbp, = "); _rbp.print(); printf("\n");
5436 printf("rsp = "); _rsp.print(); printf("\n");
5437 printf("\n");
5438 // control registers
5439 printf("flgs = "); _eflags.print(); printf("\n");
5440 }
5441 };
5442
5443
5444 class CPU_State {
5445 public:
5446 FPU_State _fpu_state;
5447 IU_State _iu_state;
5448
5449 void print() const {
5450 printf("--------------------------------------------------\n");
5451 _iu_state .print();
5452 printf("\n");
5453 _fpu_state.print();
5454 printf("--------------------------------------------------\n");
5455 }
5456
5457 };
5458
5459
5460 static void _print_CPU_state(CPU_State* state) {
5461 state->print();
5462 };
5463
5464
5465 void MacroAssembler::print_CPU_state() {
5466 push_CPU_state();
5467 push(rsp); // pass CPU state
5468 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5469 addptr(rsp, wordSize); // discard argument
5470 pop_CPU_state();
5471 }
5472
5473 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5474 // Either restore the MXCSR register after returning from the JNI Call
5475 // or verify that it wasn't changed (with -Xcheck:jni flag).
5476 if (RestoreMXCSROnJNICalls) {
5477 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5478 } else if (CheckJNICalls) {
5479 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5480 }
5481 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5482 vzeroupper();
5483 }
5484
5485 // ((OopHandle)result).resolve();
5486 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5487 assert_different_registers(result, tmp);
5488
5489 // Only 64 bit platforms support GCs that require a tmp register
5490 // Only IN_HEAP loads require a thread_tmp register
5491 // OopHandle::resolve is an indirection like jobject.
5492 access_load_at(T_OBJECT, IN_NATIVE,
5493 result, Address(result, 0), tmp);
5494 }
5495
5496 // ((WeakHandle)result).resolve();
5497 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5498 assert_different_registers(rresult, rtmp);
5499 Label resolved;
5500
5501 // A null weak handle resolves to null.
5502 cmpptr(rresult, 0);
5503 jcc(Assembler::equal, resolved);
5504
5505 // Only 64 bit platforms support GCs that require a tmp register
5506 // Only IN_HEAP loads require a thread_tmp register
5507 // WeakHandle::resolve is an indirection like jweak.
5508 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5509 rresult, Address(rresult, 0), rtmp);
5510 bind(resolved);
5511 }
5512
5513 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5514 // get mirror
5515 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5516 load_method_holder(mirror, method);
5517 movptr(mirror, Address(mirror, mirror_offset));
5518 resolve_oop_handle(mirror, tmp);
5519 }
5520
5521 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5522 load_method_holder(rresult, rmethod);
5523 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5524 }
5525
5526 void MacroAssembler::load_method_holder(Register holder, Register method) {
5527 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5528 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5529 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5530 }
5531
5532 void MacroAssembler::load_metadata(Register dst, Register src) {
5533 if (UseCompactObjectHeaders) {
5534 load_narrow_klass_compact(dst, src);
5535 } else {
5536 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5537 }
5538 }
5539
5540 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5541 assert(UseCompactObjectHeaders, "expect compact object headers");
5542 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5543 shrq(dst, markWord::klass_shift);
5544 }
5545
5546 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5547 assert_different_registers(src, tmp);
5548 assert_different_registers(dst, tmp);
5549
5550 if (UseCompactObjectHeaders) {
5551 load_narrow_klass_compact(dst, src);
5552 decode_klass_not_null(dst, tmp);
5553 } else {
5554 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5555 decode_klass_not_null(dst, tmp);
5556 }
5557 }
5558
5559 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
5560 load_klass(dst, src, tmp);
5561 movptr(dst, Address(dst, Klass::prototype_header_offset()));
5562 }
5563
5564 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5565 assert(!UseCompactObjectHeaders, "not with compact headers");
5566 assert_different_registers(src, tmp);
5567 assert_different_registers(dst, tmp);
5568 encode_klass_not_null(src, tmp);
5569 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5570 }
5571
5572 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5573 if (UseCompactObjectHeaders) {
5574 assert(tmp != noreg, "need tmp");
5575 assert_different_registers(klass, obj, tmp);
5576 load_narrow_klass_compact(tmp, obj);
5577 cmpl(klass, tmp);
5578 } else {
5579 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5580 }
5581 }
5582
5583 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5584 if (UseCompactObjectHeaders) {
5585 assert(tmp2 != noreg, "need tmp2");
5586 assert_different_registers(obj1, obj2, tmp1, tmp2);
5587 load_narrow_klass_compact(tmp1, obj1);
5588 load_narrow_klass_compact(tmp2, obj2);
5589 cmpl(tmp1, tmp2);
5590 } else {
5591 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5592 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5593 }
5594 }
5595
5596 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5597 Register tmp1) {
5598 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5599 decorators = AccessInternal::decorator_fixup(decorators, type);
5600 bool as_raw = (decorators & AS_RAW) != 0;
5601 if (as_raw) {
5602 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1);
5603 } else {
5604 bs->load_at(this, decorators, type, dst, src, tmp1);
5605 }
5606 }
5607
5608 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5609 Register tmp1, Register tmp2, Register tmp3) {
5610 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5611 decorators = AccessInternal::decorator_fixup(decorators, type);
5612 bool as_raw = (decorators & AS_RAW) != 0;
5613 if (as_raw) {
5614 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5615 } else {
5616 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5617 }
5618 }
5619
5620 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5621 Register inline_layout_info) {
5622 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5623 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5624 }
5625
5626 void MacroAssembler::payload_offset(Register inline_klass, Register offset) {
5627 movptr(offset, Address(inline_klass, InlineKlass::adr_members_offset()));
5628 movl(offset, Address(offset, InlineKlass::payload_offset_offset()));
5629 }
5630
5631 void MacroAssembler::payload_addr(Register oop, Register data, Register inline_klass) {
5632 // ((address) (void*) o) + vk->payload_offset();
5633 Register offset = (data == oop) ? rscratch1 : data;
5634 payload_offset(inline_klass, offset);
5635 if (data == oop) {
5636 addptr(data, offset);
5637 } else {
5638 lea(data, Address(oop, offset));
5639 }
5640 }
5641
5642 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5643 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1);
5644 }
5645
5646 // Doesn't do verification, generates fixed size code
5647 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5648 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1);
5649 }
5650
5651 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5652 Register tmp2, Register tmp3, DecoratorSet decorators) {
5653 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5654 }
5655
5656 // Used for storing nulls.
5657 void MacroAssembler::store_heap_oop_null(Address dst) {
5658 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5659 }
5660
5661 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5662 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5663 // Store to klass gap in destination
5664 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5665 }
5666
5667 #ifdef ASSERT
5668 void MacroAssembler::verify_heapbase(const char* msg) {
5669 assert (UseCompressedOops, "should be compressed");
5670 assert (Universe::heap() != nullptr, "java heap should be initialized");
5671 if (CheckCompressedOops) {
5672 Label ok;
5673 ExternalAddress src2(CompressedOops::base_addr());
5674 const bool is_src2_reachable = reachable(src2);
5675 if (!is_src2_reachable) {
5676 push(rscratch1); // cmpptr trashes rscratch1
5677 }
5678 cmpptr(r12_heapbase, src2, rscratch1);
5679 jcc(Assembler::equal, ok);
5680 STOP(msg);
5681 bind(ok);
5682 if (!is_src2_reachable) {
5683 pop(rscratch1);
5684 }
5685 }
5686 }
5687 #endif
5688
5689 // Algorithm must match oop.inline.hpp encode_heap_oop.
5690 void MacroAssembler::encode_heap_oop(Register r) {
5691 #ifdef ASSERT
5692 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5693 #endif
5694 verify_oop_msg(r, "broken oop in encode_heap_oop");
5695 if (CompressedOops::base() == nullptr) {
5696 if (CompressedOops::shift() != 0) {
5697 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5698 shrq(r, LogMinObjAlignmentInBytes);
5699 }
5700 return;
5701 }
5702 testq(r, r);
5703 cmovq(Assembler::equal, r, r12_heapbase);
5704 subq(r, r12_heapbase);
5705 shrq(r, LogMinObjAlignmentInBytes);
5706 }
5707
5708 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5709 #ifdef ASSERT
5710 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5711 if (CheckCompressedOops) {
5712 Label ok;
5713 testq(r, r);
5714 jcc(Assembler::notEqual, ok);
5715 STOP("null oop passed to encode_heap_oop_not_null");
5716 bind(ok);
5717 }
5718 #endif
5719 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5720 if (CompressedOops::base() != nullptr) {
5721 subq(r, r12_heapbase);
5722 }
5723 if (CompressedOops::shift() != 0) {
5724 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5725 shrq(r, LogMinObjAlignmentInBytes);
5726 }
5727 }
5728
5729 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5730 #ifdef ASSERT
5731 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5732 if (CheckCompressedOops) {
5733 Label ok;
5734 testq(src, src);
5735 jcc(Assembler::notEqual, ok);
5736 STOP("null oop passed to encode_heap_oop_not_null2");
5737 bind(ok);
5738 }
5739 #endif
5740 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5741 if (dst != src) {
5742 movq(dst, src);
5743 }
5744 if (CompressedOops::base() != nullptr) {
5745 subq(dst, r12_heapbase);
5746 }
5747 if (CompressedOops::shift() != 0) {
5748 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5749 shrq(dst, LogMinObjAlignmentInBytes);
5750 }
5751 }
5752
5753 void MacroAssembler::decode_heap_oop(Register r) {
5754 #ifdef ASSERT
5755 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5756 #endif
5757 if (CompressedOops::base() == nullptr) {
5758 if (CompressedOops::shift() != 0) {
5759 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5760 shlq(r, LogMinObjAlignmentInBytes);
5761 }
5762 } else {
5763 Label done;
5764 shlq(r, LogMinObjAlignmentInBytes);
5765 jccb(Assembler::equal, done);
5766 addq(r, r12_heapbase);
5767 bind(done);
5768 }
5769 verify_oop_msg(r, "broken oop in decode_heap_oop");
5770 }
5771
5772 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5773 // Note: it will change flags
5774 assert (UseCompressedOops, "should only be used for compressed headers");
5775 assert (Universe::heap() != nullptr, "java heap should be initialized");
5776 // Cannot assert, unverified entry point counts instructions (see .ad file)
5777 // vtableStubs also counts instructions in pd_code_size_limit.
5778 // Also do not verify_oop as this is called by verify_oop.
5779 if (CompressedOops::shift() != 0) {
5780 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5781 shlq(r, LogMinObjAlignmentInBytes);
5782 if (CompressedOops::base() != nullptr) {
5783 addq(r, r12_heapbase);
5784 }
5785 } else {
5786 assert (CompressedOops::base() == nullptr, "sanity");
5787 }
5788 }
5789
5790 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5791 // Note: it will change flags
5792 assert (UseCompressedOops, "should only be used for compressed headers");
5793 assert (Universe::heap() != nullptr, "java heap should be initialized");
5794 // Cannot assert, unverified entry point counts instructions (see .ad file)
5795 // vtableStubs also counts instructions in pd_code_size_limit.
5796 // Also do not verify_oop as this is called by verify_oop.
5797 if (CompressedOops::shift() != 0) {
5798 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5799 if (LogMinObjAlignmentInBytes == Address::times_8) {
5800 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5801 } else {
5802 if (dst != src) {
5803 movq(dst, src);
5804 }
5805 shlq(dst, LogMinObjAlignmentInBytes);
5806 if (CompressedOops::base() != nullptr) {
5807 addq(dst, r12_heapbase);
5808 }
5809 }
5810 } else {
5811 assert (CompressedOops::base() == nullptr, "sanity");
5812 if (dst != src) {
5813 movq(dst, src);
5814 }
5815 }
5816 }
5817
5818 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5819 BLOCK_COMMENT("encode_klass_not_null {");
5820 assert_different_registers(r, tmp);
5821 if (CompressedKlassPointers::base() != nullptr) {
5822 if (AOTCodeCache::is_on_for_dump()) {
5823 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5824 } else {
5825 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5826 }
5827 subq(r, tmp);
5828 }
5829 if (CompressedKlassPointers::shift() != 0) {
5830 shrq(r, CompressedKlassPointers::shift());
5831 }
5832 BLOCK_COMMENT("} encode_klass_not_null");
5833 }
5834
5835 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5836 BLOCK_COMMENT("encode_and_move_klass_not_null {");
5837 assert_different_registers(src, dst);
5838 if (CompressedKlassPointers::base() != nullptr) {
5839 if (AOTCodeCache::is_on_for_dump()) {
5840 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5841 negq(dst);
5842 } else {
5843 movptr(dst, -(intptr_t)CompressedKlassPointers::base());
5844 }
5845 addq(dst, src);
5846 } else {
5847 movptr(dst, src);
5848 }
5849 if (CompressedKlassPointers::shift() != 0) {
5850 shrq(dst, CompressedKlassPointers::shift());
5851 }
5852 BLOCK_COMMENT("} encode_and_move_klass_not_null");
5853 }
5854
5855 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5856 BLOCK_COMMENT("decode_klass_not_null {");
5857 assert_different_registers(r, tmp);
5858 // Note: it will change flags
5859 // Cannot assert, unverified entry point counts instructions (see .ad file)
5860 // vtableStubs also counts instructions in pd_code_size_limit.
5861 // Also do not verify_oop as this is called by verify_oop.
5862 if (CompressedKlassPointers::shift() != 0) {
5863 shlq(r, CompressedKlassPointers::shift());
5864 }
5865 if (CompressedKlassPointers::base() != nullptr) {
5866 if (AOTCodeCache::is_on_for_dump()) {
5867 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5868 } else {
5869 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5870 }
5871 addq(r, tmp);
5872 }
5873 BLOCK_COMMENT("} decode_klass_not_null");
5874 }
5875
5876 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5877 BLOCK_COMMENT("decode_and_move_klass_not_null {");
5878 assert_different_registers(src, dst);
5879 // Note: it will change flags
5880 // Cannot assert, unverified entry point counts instructions (see .ad file)
5881 // vtableStubs also counts instructions in pd_code_size_limit.
5882 // Also do not verify_oop as this is called by verify_oop.
5883
5884 if (CompressedKlassPointers::base() == nullptr &&
5885 CompressedKlassPointers::shift() == 0) {
5886 // The best case scenario is that there is no base or shift. Then it is already
5887 // a pointer that needs nothing but a register rename.
5888 movl(dst, src);
5889 } else {
5890 if (CompressedKlassPointers::shift() <= Address::times_8) {
5891 if (CompressedKlassPointers::base() != nullptr) {
5892 if (AOTCodeCache::is_on_for_dump()) {
5893 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5894 } else {
5895 movptr(dst, (intptr_t)CompressedKlassPointers::base());
5896 }
5897 } else {
5898 xorq(dst, dst);
5899 }
5900 if (CompressedKlassPointers::shift() != 0) {
5901 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
5902 leaq(dst, Address(dst, src, Address::times_8, 0));
5903 } else {
5904 addq(dst, src);
5905 }
5906 } else {
5907 if (CompressedKlassPointers::base() != nullptr) {
5908 if (AOTCodeCache::is_on_for_dump()) {
5909 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5910 shrq(dst, CompressedKlassPointers::shift());
5911 } else {
5912 const intptr_t base_right_shifted =
5913 (intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5914 movptr(dst, base_right_shifted);
5915 }
5916 } else {
5917 xorq(dst, dst);
5918 }
5919 addq(dst, src);
5920 shlq(dst, CompressedKlassPointers::shift());
5921 }
5922 }
5923 BLOCK_COMMENT("} decode_and_move_klass_not_null");
5924 }
5925
5926 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5927 assert (UseCompressedOops, "should only be used for compressed headers");
5928 assert (Universe::heap() != nullptr, "java heap should be initialized");
5929 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5930 int oop_index = oop_recorder()->find_index(obj);
5931 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5932 mov_narrow_oop(dst, oop_index, rspec);
5933 }
5934
5935 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5936 assert (UseCompressedOops, "should only be used for compressed headers");
5937 assert (Universe::heap() != nullptr, "java heap should be initialized");
5938 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5939 int oop_index = oop_recorder()->find_index(obj);
5940 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5941 mov_narrow_oop(dst, oop_index, rspec);
5942 }
5943
5944 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5945 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5946 int klass_index = oop_recorder()->find_index(k);
5947 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5948 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5949 }
5950
5951 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5952 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5953 int klass_index = oop_recorder()->find_index(k);
5954 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5955 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5956 }
5957
5958 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5959 assert (UseCompressedOops, "should only be used for compressed headers");
5960 assert (Universe::heap() != nullptr, "java heap should be initialized");
5961 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5962 int oop_index = oop_recorder()->find_index(obj);
5963 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5964 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5965 }
5966
5967 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5968 assert (UseCompressedOops, "should only be used for compressed headers");
5969 assert (Universe::heap() != nullptr, "java heap should be initialized");
5970 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5971 int oop_index = oop_recorder()->find_index(obj);
5972 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5973 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5974 }
5975
5976 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5977 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5978 int klass_index = oop_recorder()->find_index(k);
5979 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5980 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5981 }
5982
5983 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5984 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5985 int klass_index = oop_recorder()->find_index(k);
5986 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5987 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5988 }
5989
5990 void MacroAssembler::reinit_heapbase() {
5991 if (UseCompressedOops) {
5992 if (Universe::heap() != nullptr && !AOTCodeCache::is_on_for_dump()) {
5993 if (CompressedOops::base() == nullptr) {
5994 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5995 } else {
5996 mov64(r12_heapbase, (int64_t)CompressedOops::base());
5997 }
5998 } else {
5999 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6000 }
6001 }
6002 }
6003
6004 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6005 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6006 // An inline type might be returned. If fields are in registers we
6007 // need to allocate an inline type instance and initialize it with
6008 // the value of the fields.
6009 Label skip;
6010 // We only need a new buffered inline type if a new one is not returned
6011 testptr(rax, 1);
6012 jcc(Assembler::zero, skip);
6013 int call_offset = -1;
6014
6015 // The following code is similar to allocation code in TemplateTable::_new but has some slight differences,
6016 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6017 // allocating is not necessary if vk != nullptr, etc.
6018 Label slow_case;
6019 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6020 mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
6021 if (vk != nullptr) {
6022 // Called from C1, where the return type is statically known.
6023 movptr(rbx, (intptr_t)vk->get_InlineKlass());
6024 jint lh = vk->layout_helper();
6025 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6026 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6027 tlab_allocate(rax, noreg, lh, r13, r14, slow_case);
6028 } else {
6029 jmp(slow_case);
6030 }
6031 } else {
6032 // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
6033 mov(rbx, rax);
6034 andptr(rbx, -2);
6035 if (UseTLAB) {
6036 movl(r14, Address(rbx, Klass::layout_helper_offset()));
6037 testl(r14, Klass::_lh_instance_slow_path_bit);
6038 jcc(Assembler::notZero, slow_case);
6039 tlab_allocate(rax, r14, 0, r13, r14, slow_case);
6040 } else {
6041 jmp(slow_case);
6042 }
6043 }
6044 if (UseTLAB) {
6045 // 2. Initialize buffered inline instance header
6046 Register buffer_obj = rax;
6047 Register klass = rbx;
6048 if (UseCompactObjectHeaders) {
6049 Register mark_word = r13;
6050 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
6051 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), mark_word);
6052 } else {
6053 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
6054 xorl(r13, r13);
6055 store_klass_gap(buffer_obj, r13);
6056 if (vk == nullptr) {
6057 // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
6058 mov(r13, klass);
6059 }
6060 store_klass(buffer_obj, klass, rscratch1);
6061 klass = r13;
6062 }
6063 // 3. Initialize its fields with an inline class specific handler
6064 if (vk != nullptr) {
6065 call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6066 } else {
6067 movptr(rbx, Address(klass, InlineKlass::adr_members_offset()));
6068 movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
6069 call(rbx);
6070 }
6071 jmp(skip);
6072 }
6073 bind(slow_case);
6074 // We failed to allocate a new inline type, fall back to a runtime
6075 // call. Some oop field may be live in some registers but we can't
6076 // tell. That runtime call will take care of preserving them
6077 // across a GC if there's one.
6078 mov(rax, rscratch1);
6079
6080 if (from_interpreter) {
6081 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6082 } else {
6083 call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6084 call_offset = offset();
6085 }
6086
6087 bind(skip);
6088 return call_offset;
6089 }
6090
6091 // Move a value between registers/stack slots and update the reg_state
6092 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6093 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6094 if (reg_state[to->value()] == reg_written) {
6095 return true; // Already written
6096 }
6097 if (from != to && bt != T_VOID) {
6098 if (reg_state[to->value()] == reg_readonly) {
6099 return false; // Not yet writable
6100 }
6101 if (from->is_reg()) {
6102 if (to->is_reg()) {
6103 if (from->is_XMMRegister()) {
6104 if (bt == T_DOUBLE) {
6105 movdbl(to->as_XMMRegister(), from->as_XMMRegister());
6106 } else {
6107 assert(bt == T_FLOAT, "must be float");
6108 movflt(to->as_XMMRegister(), from->as_XMMRegister());
6109 }
6110 } else {
6111 movq(to->as_Register(), from->as_Register());
6112 }
6113 } else {
6114 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6115 Address to_addr = Address(rsp, st_off);
6116 if (from->is_XMMRegister()) {
6117 if (bt == T_DOUBLE) {
6118 movdbl(to_addr, from->as_XMMRegister());
6119 } else {
6120 assert(bt == T_FLOAT, "must be float");
6121 movflt(to_addr, from->as_XMMRegister());
6122 }
6123 } else {
6124 movq(to_addr, from->as_Register());
6125 }
6126 }
6127 } else {
6128 Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
6129 if (to->is_reg()) {
6130 if (to->is_XMMRegister()) {
6131 if (bt == T_DOUBLE) {
6132 movdbl(to->as_XMMRegister(), from_addr);
6133 } else {
6134 assert(bt == T_FLOAT, "must be float");
6135 movflt(to->as_XMMRegister(), from_addr);
6136 }
6137 } else {
6138 movq(to->as_Register(), from_addr);
6139 }
6140 } else {
6141 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6142 movq(r13, from_addr);
6143 movq(Address(rsp, st_off), r13);
6144 }
6145 }
6146 }
6147 // Update register states
6148 reg_state[from->value()] = reg_writable;
6149 reg_state[to->value()] = reg_written;
6150 return true;
6151 }
6152
6153 // Calculate the extra stack space required for packing or unpacking inline
6154 // args and adjust the stack pointer (see MacroAssembler::remove_frame).
6155 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6156 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
6157 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6158 assert(sp_inc > 0, "sanity");
6159 // Two additional slots to account for return address
6160 sp_inc += 2 * VMRegImpl::stack_slot_size;
6161
6162 push(rbp);
6163 subptr(rsp, sp_inc);
6164 #ifdef ASSERT
6165 movl(Address(rsp, 0), badRegWordVal);
6166 movl(Address(rsp, VMRegImpl::stack_slot_size), badRegWordVal);
6167 #endif
6168 return sp_inc + wordSize; // account for rbp space
6169 }
6170
6171 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
6172 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6173 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6174 RegState reg_state[]) {
6175 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6176 assert(from->is_valid(), "source must be valid");
6177 bool progress = false;
6178 #ifdef ASSERT
6179 const int start_offset = offset();
6180 #endif
6181
6182 Label L_null, L_notNull;
6183 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6184 Register tmp1 = r10;
6185 Register tmp2 = r13;
6186 Register fromReg = noreg;
6187 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, true);
6188 bool done = true;
6189 bool mark_done = true;
6190 VMReg toReg;
6191 BasicType bt;
6192 // Check if argument requires a null check
6193 bool null_check = false;
6194 VMReg nullCheckReg;
6195 while (stream.next(nullCheckReg, bt)) {
6196 if (sig->at(stream.sig_index())._offset == -1) {
6197 null_check = true;
6198 break;
6199 }
6200 }
6201 stream.reset(sig_index, to_index);
6202 while (stream.next(toReg, bt)) {
6203 assert(toReg->is_valid(), "destination must be valid");
6204 int idx = (int)toReg->value();
6205 if (reg_state[idx] == reg_readonly) {
6206 if (idx != from->value()) {
6207 mark_done = false;
6208 }
6209 done = false;
6210 continue;
6211 } else if (reg_state[idx] == reg_written) {
6212 continue;
6213 }
6214 assert(reg_state[idx] == reg_writable, "must be writable");
6215 reg_state[idx] = reg_written;
6216 progress = true;
6217
6218 if (fromReg == noreg) {
6219 if (from->is_reg()) {
6220 fromReg = from->as_Register();
6221 } else {
6222 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6223 movq(tmp1, Address(rsp, st_off));
6224 fromReg = tmp1;
6225 }
6226 if (null_check) {
6227 // Nullable inline type argument, emit null check
6228 testptr(fromReg, fromReg);
6229 jcc(Assembler::zero, L_null);
6230 }
6231 }
6232 int off = sig->at(stream.sig_index())._offset;
6233 if (off == -1) {
6234 assert(null_check, "Missing null check at");
6235 if (toReg->is_stack()) {
6236 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6237 movq(Address(rsp, st_off), 1);
6238 } else {
6239 movq(toReg->as_Register(), 1);
6240 }
6241 continue;
6242 }
6243 if (sig->at(stream.sig_index())._vt_oop) {
6244 if (toReg->is_stack()) {
6245 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6246 movq(Address(rsp, st_off), fromReg);
6247 } else {
6248 movq(toReg->as_Register(), fromReg);
6249 }
6250 continue;
6251 }
6252 assert(off > 0, "offset in object should be positive");
6253 Address fromAddr = Address(fromReg, off);
6254 if (!toReg->is_XMMRegister()) {
6255 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
6256 if (is_reference_type(bt)) {
6257 load_heap_oop(dst, fromAddr);
6258 } else {
6259 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
6260 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
6261 }
6262 if (toReg->is_stack()) {
6263 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6264 movq(Address(rsp, st_off), dst);
6265 }
6266 } else if (bt == T_DOUBLE) {
6267 movdbl(toReg->as_XMMRegister(), fromAddr);
6268 } else {
6269 assert(bt == T_FLOAT, "must be float");
6270 movflt(toReg->as_XMMRegister(), fromAddr);
6271 }
6272 }
6273 if (progress && null_check) {
6274 if (done) {
6275 jmp(L_notNull);
6276 bind(L_null);
6277 // Set null marker to zero to signal that the argument is null.
6278 // Also set all fields to zero since the runtime requires a canonical
6279 // representation of a flat null.
6280 stream.reset(sig_index, to_index);
6281 while (stream.next(toReg, bt)) {
6282 if (toReg->is_stack()) {
6283 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6284 movq(Address(rsp, st_off), 0);
6285 } else if (toReg->is_XMMRegister()) {
6286 xorps(toReg->as_XMMRegister(), toReg->as_XMMRegister());
6287 } else {
6288 xorl(toReg->as_Register(), toReg->as_Register());
6289 }
6290 }
6291 bind(L_notNull);
6292 } else {
6293 bind(L_null);
6294 }
6295 }
6296
6297 sig_index = stream.sig_index();
6298 to_index = stream.regs_index();
6299
6300 if (mark_done && reg_state[from->value()] != reg_written) {
6301 // This is okay because no one else will write to that slot
6302 reg_state[from->value()] = reg_writable;
6303 }
6304 from_index--;
6305 assert(progress || (start_offset == offset()), "should not emit code");
6306 return done;
6307 }
6308
6309 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
6310 VMRegPair* from, int from_count, int& from_index, VMReg to,
6311 RegState reg_state[], Register val_array) {
6312 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
6313 assert(to->is_valid(), "destination must be valid");
6314
6315 if (reg_state[to->value()] == reg_written) {
6316 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6317 return true; // Already written
6318 }
6319
6320 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
6321 Register val_obj_tmp = r11;
6322 Register from_reg_tmp = r14;
6323 Register tmp1 = r10;
6324 Register tmp2 = r13;
6325 Register tmp3 = rbx;
6326 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
6327
6328 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
6329
6330 if (reg_state[to->value()] == reg_readonly) {
6331 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
6332 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6333 return false; // Not yet writable
6334 }
6335 val_obj = val_obj_tmp;
6336 }
6337
6338 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
6339 VMReg fromReg;
6340 BasicType bt;
6341 Label L_null;
6342 while (stream.next(fromReg, bt)) {
6343 assert(fromReg->is_valid(), "source must be valid");
6344 reg_state[fromReg->value()] = reg_writable;
6345
6346 int off = sig->at(stream.sig_index())._offset;
6347 if (off == -1) {
6348 // Nullable inline type argument, emit null check
6349 Label L_notNull;
6350 if (fromReg->is_stack()) {
6351 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6352 testb(Address(rsp, ld_off), 1);
6353 } else {
6354 testb(fromReg->as_Register(), 1);
6355 }
6356 jcc(Assembler::notZero, L_notNull);
6357 movptr(val_obj, 0);
6358 jmp(L_null);
6359 bind(L_notNull);
6360 continue;
6361 }
6362 if (sig->at(stream.sig_index())._vt_oop) {
6363 // buffer argument: use if non null
6364 if (fromReg->is_stack()) {
6365 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6366 movptr(val_obj, Address(rsp, ld_off));
6367 } else {
6368 movptr(val_obj, fromReg->as_Register());
6369 }
6370 testptr(val_obj, val_obj);
6371 jcc(Assembler::notEqual, L_null);
6372 // otherwise get the buffer from the just allocated pool of buffers
6373 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
6374 load_heap_oop(val_obj, Address(val_array, index));
6375 continue;
6376 }
6377
6378 assert(off > 0, "offset in object should be positive");
6379 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
6380
6381 // Pack the scalarized field into the value object.
6382 Address dst(val_obj, off);
6383 if (!fromReg->is_XMMRegister()) {
6384 Register src;
6385 if (fromReg->is_stack()) {
6386 src = from_reg_tmp;
6387 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6388 load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
6389 } else {
6390 src = fromReg->as_Register();
6391 }
6392 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
6393 if (is_reference_type(bt)) {
6394 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep val_obj valid.
6395 mov(tmp3, val_obj);
6396 Address dst_with_tmp3(tmp3, off);
6397 store_heap_oop(dst_with_tmp3, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
6398 } else {
6399 store_sized_value(dst, src, size_in_bytes);
6400 }
6401 } else if (bt == T_DOUBLE) {
6402 movdbl(dst, fromReg->as_XMMRegister());
6403 } else {
6404 assert(bt == T_FLOAT, "must be float");
6405 movflt(dst, fromReg->as_XMMRegister());
6406 }
6407 }
6408 bind(L_null);
6409 sig_index = stream.sig_index();
6410 from_index = stream.regs_index();
6411
6412 assert(reg_state[to->value()] == reg_writable, "must have already been read");
6413 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6414 assert(success, "to register must be writeable");
6415 return true;
6416 }
6417
6418 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6419 return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
6420 }
6421
6422 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
6423 assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6424 if (needs_stack_repair) {
6425 // The method has a scalarized entry point (where fields of value object arguments
6426 // are passed through registers and stack), and a non-scalarized entry point (where
6427 // value object arguments are given as oops). The non-scalarized entry point will
6428 // first load each field of value object arguments and store them in registers and on
6429 // the stack in a way compatible with the scalarized entry point. To do so, some extra
6430 // stack space might be reserved (if argument registers are not enough). On leaving the
6431 // method, this space must be freed.
6432 //
6433 // In case we used the non-scalarized entry point the stack looks like this:
6434 //
6435 // | Arguments from caller |
6436 // |---------------------------| <-- caller's SP
6437 // | Return address #1 |
6438 // | Saved RBP #1 |
6439 // |---------------------------|
6440 // | Extension space for |
6441 // | inline arg (un)packing |
6442 // |---------------------------| <-- start of this method's frame
6443 // | Return address #2 |
6444 // | Saved RBP #2 |
6445 // |---------------------------| <-- RBP (with -XX:+PreserveFramePointer)
6446 // | sp_inc |
6447 // | method locals |
6448 // |---------------------------| <-- SP
6449 //
6450 // Space for the return pc and saved rbp is reserved twice. But only the #1 copies
6451 // contain the real values of return pc and saved rbp. The #2 copies are not reliable
6452 // and should not be used. They are mostly needed to add space between the extension
6453 // space and the locals, as there would be between the real arguments and the locals
6454 // if we don't need to do unpacking (from the scalarized entry point).
6455 //
6456 // When leaving, one must load RBP #1 into RBP, and use the copy #1 of the return address,
6457 // while keeping in mind that from the scalarized entry point, there will be only one
6458 // copy. Indeed, in the case we used the scalarized calling convention, the stack looks like this:
6459 //
6460 // | Arguments from caller |
6461 // |---------------------------| <-- caller's SP
6462 // | Return address |
6463 // | Saved RBP |
6464 // |---------------------------| <-- FP (with -XX:+PreserveFramePointer)
6465 // | sp_inc |
6466 // | method locals |
6467 // |---------------------------| <-- SP
6468 //
6469 // The sp_inc stack slot holds the total size of the frame, including the extension
6470 // space and copies #2 of the return address and the saved RBP (but never the copies
6471 // #1 of the return address and saved RBP). That is how to find the copies #1 of the
6472 // return address and saved rbp. This size is expressed in bytes. Be careful when using
6473 // it from C++ in pointer arithmetic you might need to divide it by wordSize.
6474
6475 // The stack increment resides just below the saved rbp
6476 addq(rsp, Address(rsp, initial_framesize - wordSize));
6477 pop(rbp);
6478 } else {
6479 if (initial_framesize > 0) {
6480 addq(rsp, initial_framesize);
6481 }
6482 pop(rbp);
6483 }
6484 }
6485
6486 #if COMPILER2_OR_JVMCI
6487
6488 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6489 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
6490 // cnt - number of qwords (8-byte words).
6491 // base - start address, qword aligned.
6492 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6493 bool use64byteVector = (MaxVectorSize == 64) && (CopyAVX3Threshold == 0);
6494 if (use64byteVector) {
6495 evpbroadcastq(xtmp, val, AVX_512bit);
6496 } else if (MaxVectorSize >= 32) {
6497 movdq(xtmp, val);
6498 punpcklqdq(xtmp, xtmp);
6499 vinserti128_high(xtmp, xtmp);
6500 } else {
6501 movdq(xtmp, val);
6502 punpcklqdq(xtmp, xtmp);
6503 }
6504 jmp(L_zero_64_bytes);
6505
6506 BIND(L_loop);
6507 if (MaxVectorSize >= 32) {
6508 fill64(base, 0, xtmp, use64byteVector);
6509 } else {
6510 movdqu(Address(base, 0), xtmp);
6511 movdqu(Address(base, 16), xtmp);
6512 movdqu(Address(base, 32), xtmp);
6513 movdqu(Address(base, 48), xtmp);
6514 }
6515 addptr(base, 64);
6516
6517 BIND(L_zero_64_bytes);
6518 subptr(cnt, 8);
6519 jccb(Assembler::greaterEqual, L_loop);
6520
6521 // Copy trailing 64 bytes
6522 if (use64byteVector) {
6523 addptr(cnt, 8);
6524 jccb(Assembler::equal, L_end);
6525 fill64_masked(3, base, 0, xtmp, mask, cnt, val, true);
6526 jmp(L_end);
6527 } else {
6528 addptr(cnt, 4);
6529 jccb(Assembler::less, L_tail);
6530 if (MaxVectorSize >= 32) {
6531 vmovdqu(Address(base, 0), xtmp);
6532 } else {
6533 movdqu(Address(base, 0), xtmp);
6534 movdqu(Address(base, 16), xtmp);
6535 }
6536 }
6537 addptr(base, 32);
6538 subptr(cnt, 4);
6539
6540 BIND(L_tail);
6541 addptr(cnt, 4);
6542 jccb(Assembler::lessEqual, L_end);
6543 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6544 fill32_masked(3, base, 0, xtmp, mask, cnt, val);
6545 } else {
6546 decrement(cnt);
6547
6548 BIND(L_sloop);
6549 movq(Address(base, 0), xtmp);
6550 addptr(base, 8);
6551 decrement(cnt);
6552 jccb(Assembler::greaterEqual, L_sloop);
6553 }
6554 BIND(L_end);
6555 }
6556
6557 // Clearing constant sized memory using YMM/ZMM registers.
6558 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6559 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6560 bool use64byteVector = (MaxVectorSize > 32) && (CopyAVX3Threshold == 0);
6561
6562 int vector64_count = (cnt & (~0x7)) >> 3;
6563 cnt = cnt & 0x7;
6564 const int fill64_per_loop = 4;
6565 const int max_unrolled_fill64 = 8;
6566
6567 // 64 byte initialization loop.
6568 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6569 int start64 = 0;
6570 if (vector64_count > max_unrolled_fill64) {
6571 Label LOOP;
6572 Register index = rtmp;
6573
6574 start64 = vector64_count - (vector64_count % fill64_per_loop);
6575
6576 movl(index, 0);
6577 BIND(LOOP);
6578 for (int i = 0; i < fill64_per_loop; i++) {
6579 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6580 }
6581 addl(index, fill64_per_loop * 64);
6582 cmpl(index, start64 * 64);
6583 jccb(Assembler::less, LOOP);
6584 }
6585 for (int i = start64; i < vector64_count; i++) {
6586 fill64(base, i * 64, xtmp, use64byteVector);
6587 }
6588
6589 // Clear remaining 64 byte tail.
6590 int disp = vector64_count * 64;
6591 if (cnt) {
6592 switch (cnt) {
6593 case 1:
6594 movq(Address(base, disp), xtmp);
6595 break;
6596 case 2:
6597 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6598 break;
6599 case 3:
6600 movl(rtmp, 0x7);
6601 kmovwl(mask, rtmp);
6602 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6603 break;
6604 case 4:
6605 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6606 break;
6607 case 5:
6608 if (use64byteVector) {
6609 movl(rtmp, 0x1F);
6610 kmovwl(mask, rtmp);
6611 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6612 } else {
6613 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6614 movq(Address(base, disp + 32), xtmp);
6615 }
6616 break;
6617 case 6:
6618 if (use64byteVector) {
6619 movl(rtmp, 0x3F);
6620 kmovwl(mask, rtmp);
6621 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6622 } else {
6623 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6624 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6625 }
6626 break;
6627 case 7:
6628 if (use64byteVector) {
6629 movl(rtmp, 0x7F);
6630 kmovwl(mask, rtmp);
6631 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6632 } else {
6633 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6634 movl(rtmp, 0x7);
6635 kmovwl(mask, rtmp);
6636 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6637 }
6638 break;
6639 default:
6640 fatal("Unexpected length : %d\n",cnt);
6641 break;
6642 }
6643 }
6644 }
6645
6646 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
6647 bool is_large, bool word_copy_only, KRegister mask) {
6648 // cnt - number of qwords (8-byte words).
6649 // base - start address, qword aligned.
6650 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6651 assert(base==rdi, "base register must be edi for rep stos");
6652 assert(val==rax, "val register must be eax for rep stos");
6653 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6654 assert(InitArrayShortSize % BytesPerLong == 0,
6655 "InitArrayShortSize should be the multiple of BytesPerLong");
6656
6657 Label DONE;
6658
6659 if (!is_large) {
6660 Label LOOP, LONG;
6661 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6662 jccb(Assembler::greater, LONG);
6663
6664 decrement(cnt);
6665 jccb(Assembler::negative, DONE); // Zero length
6666
6667 // Use individual pointer-sized stores for small counts:
6668 BIND(LOOP);
6669 movptr(Address(base, cnt, Address::times_ptr), val);
6670 decrement(cnt);
6671 jccb(Assembler::greaterEqual, LOOP);
6672 jmpb(DONE);
6673
6674 BIND(LONG);
6675 }
6676
6677 // Use longer rep-prefixed ops for non-small counts:
6678 if (UseFastStosb && !word_copy_only) {
6679 shlptr(cnt, 3); // convert to number of bytes
6680 rep_stosb();
6681 } else if (UseXMMForObjInit) {
6682 xmm_clear_mem(base, cnt, val, xtmp, mask);
6683 } else {
6684 rep_stos();
6685 }
6686
6687 BIND(DONE);
6688 }
6689
6690 #endif //COMPILER2_OR_JVMCI
6691
6692
6693 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6694 Register to, Register value, Register count,
6695 Register rtmp, XMMRegister xtmp) {
6696 ShortBranchVerifier sbv(this);
6697 assert_different_registers(to, value, count, rtmp);
6698 Label L_exit;
6699 Label L_fill_2_bytes, L_fill_4_bytes;
6700
6701 #if defined(COMPILER2)
6702 if(MaxVectorSize >=32 &&
6703 VM_Version::supports_avx512vlbw() &&
6704 VM_Version::supports_bmi2()) {
6705 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6706 return;
6707 }
6708 #endif
6709
6710 int shift = -1;
6711 switch (t) {
6712 case T_BYTE:
6713 shift = 2;
6714 break;
6715 case T_SHORT:
6716 shift = 1;
6717 break;
6718 case T_INT:
6719 shift = 0;
6720 break;
6721 default: ShouldNotReachHere();
6722 }
6723
6724 if (t == T_BYTE) {
6725 andl(value, 0xff);
6726 movl(rtmp, value);
6727 shll(rtmp, 8);
6728 orl(value, rtmp);
6729 }
6730 if (t == T_SHORT) {
6731 andl(value, 0xffff);
6732 }
6733 if (t == T_BYTE || t == T_SHORT) {
6734 movl(rtmp, value);
6735 shll(rtmp, 16);
6736 orl(value, rtmp);
6737 }
6738
6739 cmpptr(count, 8 << shift); // Short arrays (< 32 bytes) fill by element
6740 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6741 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6742 Label L_skip_align2;
6743 // align source address at 4 bytes address boundary
6744 if (t == T_BYTE) {
6745 Label L_skip_align1;
6746 // One byte misalignment happens only for byte arrays
6747 testptr(to, 1);
6748 jccb(Assembler::zero, L_skip_align1);
6749 movb(Address(to, 0), value);
6750 increment(to);
6751 decrement(count);
6752 BIND(L_skip_align1);
6753 }
6754 // Two bytes misalignment happens only for byte and short (char) arrays
6755 testptr(to, 2);
6756 jccb(Assembler::zero, L_skip_align2);
6757 movw(Address(to, 0), value);
6758 addptr(to, 2);
6759 subptr(count, 1<<(shift-1));
6760 BIND(L_skip_align2);
6761 }
6762 {
6763 Label L_fill_32_bytes;
6764 if (!UseUnalignedLoadStores) {
6765 // align to 8 bytes, we know we are 4 byte aligned to start
6766 testptr(to, 4);
6767 jccb(Assembler::zero, L_fill_32_bytes);
6768 movl(Address(to, 0), value);
6769 addptr(to, 4);
6770 subptr(count, 1<<shift);
6771 }
6772 BIND(L_fill_32_bytes);
6773 {
6774 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6775 movdl(xtmp, value);
6776 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6777 Label L_check_fill_32_bytes;
6778 if (UseAVX > 2) {
6779 // Fill 64-byte chunks
6780 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6781
6782 // If number of bytes to fill < CopyAVX3Threshold, perform fill using AVX2
6783 cmpptr(count, CopyAVX3Threshold);
6784 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6785
6786 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6787
6788 subptr(count, 16 << shift);
6789 jcc(Assembler::less, L_check_fill_32_bytes);
6790 align(16);
6791
6792 BIND(L_fill_64_bytes_loop_avx3);
6793 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6794 addptr(to, 64);
6795 subptr(count, 16 << shift);
6796 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6797 jmpb(L_check_fill_32_bytes);
6798
6799 BIND(L_check_fill_64_bytes_avx2);
6800 }
6801 // Fill 64-byte chunks
6802 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6803
6804 subptr(count, 16 << shift);
6805 jcc(Assembler::less, L_check_fill_32_bytes);
6806
6807 // align data for 64-byte chunks
6808 Label L_fill_64_bytes_loop, L_align_64_bytes_loop;
6809 if (EnableX86ECoreOpts) {
6810 // align 'big' arrays to cache lines to minimize split_stores
6811 cmpptr(count, 96 << shift);
6812 jcc(Assembler::below, L_fill_64_bytes_loop);
6813
6814 // Find the bytes needed for alignment
6815 movptr(rtmp, to);
6816 andptr(rtmp, 0x1c);
6817 jcc(Assembler::zero, L_fill_64_bytes_loop);
6818 negptr(rtmp); // number of bytes to fill 32-rtmp. it filled by 2 mov by 32
6819 addptr(rtmp, 32);
6820 shrptr(rtmp, 2 - shift);// get number of elements from bytes
6821 subptr(count, rtmp); // adjust count by number of elements
6822
6823 align(16);
6824 BIND(L_align_64_bytes_loop);
6825 movdl(Address(to, 0), xtmp);
6826 addptr(to, 4);
6827 subptr(rtmp, 1 << shift);
6828 jcc(Assembler::greater, L_align_64_bytes_loop);
6829 }
6830
6831 align(16);
6832 BIND(L_fill_64_bytes_loop);
6833 vmovdqu(Address(to, 0), xtmp);
6834 vmovdqu(Address(to, 32), xtmp);
6835 addptr(to, 64);
6836 subptr(count, 16 << shift);
6837 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6838
6839 align(16);
6840 BIND(L_check_fill_32_bytes);
6841 addptr(count, 8 << shift);
6842 jccb(Assembler::less, L_check_fill_8_bytes);
6843 vmovdqu(Address(to, 0), xtmp);
6844 addptr(to, 32);
6845 subptr(count, 8 << shift);
6846
6847 BIND(L_check_fill_8_bytes);
6848 // clean upper bits of YMM registers
6849 movdl(xtmp, value);
6850 pshufd(xtmp, xtmp, 0);
6851 } else {
6852 // Fill 32-byte chunks
6853 pshufd(xtmp, xtmp, 0);
6854
6855 subptr(count, 8 << shift);
6856 jcc(Assembler::less, L_check_fill_8_bytes);
6857 align(16);
6858
6859 BIND(L_fill_32_bytes_loop);
6860
6861 if (UseUnalignedLoadStores) {
6862 movdqu(Address(to, 0), xtmp);
6863 movdqu(Address(to, 16), xtmp);
6864 } else {
6865 movq(Address(to, 0), xtmp);
6866 movq(Address(to, 8), xtmp);
6867 movq(Address(to, 16), xtmp);
6868 movq(Address(to, 24), xtmp);
6869 }
6870
6871 addptr(to, 32);
6872 subptr(count, 8 << shift);
6873 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6874
6875 BIND(L_check_fill_8_bytes);
6876 }
6877 addptr(count, 8 << shift);
6878 jccb(Assembler::zero, L_exit);
6879 jmpb(L_fill_8_bytes);
6880
6881 //
6882 // length is too short, just fill qwords
6883 //
6884 align(16);
6885 BIND(L_fill_8_bytes_loop);
6886 movq(Address(to, 0), xtmp);
6887 addptr(to, 8);
6888 BIND(L_fill_8_bytes);
6889 subptr(count, 1 << (shift + 1));
6890 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6891 }
6892 }
6893
6894 Label L_fill_4_bytes_loop;
6895 testl(count, 1 << shift);
6896 jccb(Assembler::zero, L_fill_2_bytes);
6897
6898 align(16);
6899 BIND(L_fill_4_bytes_loop);
6900 movl(Address(to, 0), value);
6901 addptr(to, 4);
6902
6903 BIND(L_fill_4_bytes);
6904 subptr(count, 1 << shift);
6905 jccb(Assembler::greaterEqual, L_fill_4_bytes_loop);
6906
6907 if (t == T_BYTE || t == T_SHORT) {
6908 Label L_fill_byte;
6909 BIND(L_fill_2_bytes);
6910 // fill trailing 2 bytes
6911 testl(count, 1<<(shift-1));
6912 jccb(Assembler::zero, L_fill_byte);
6913 movw(Address(to, 0), value);
6914 if (t == T_BYTE) {
6915 addptr(to, 2);
6916 BIND(L_fill_byte);
6917 // fill trailing byte
6918 testl(count, 1);
6919 jccb(Assembler::zero, L_exit);
6920 movb(Address(to, 0), value);
6921 } else {
6922 BIND(L_fill_byte);
6923 }
6924 } else {
6925 BIND(L_fill_2_bytes);
6926 }
6927 BIND(L_exit);
6928 }
6929
6930 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6931 switch(type) {
6932 case T_BYTE:
6933 case T_BOOLEAN:
6934 evpbroadcastb(dst, src, vector_len);
6935 break;
6936 case T_SHORT:
6937 case T_CHAR:
6938 evpbroadcastw(dst, src, vector_len);
6939 break;
6940 case T_INT:
6941 case T_FLOAT:
6942 evpbroadcastd(dst, src, vector_len);
6943 break;
6944 case T_LONG:
6945 case T_DOUBLE:
6946 evpbroadcastq(dst, src, vector_len);
6947 break;
6948 default:
6949 fatal("Unhandled type : %s", type2name(type));
6950 break;
6951 }
6952 }
6953
6954 // Encode given char[]/byte[] to byte[] in ISO_8859_1 or ASCII
6955 //
6956 // @IntrinsicCandidate
6957 // int sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(
6958 // char[] sa, int sp, byte[] da, int dp, int len) {
6959 // int i = 0;
6960 // for (; i < len; i++) {
6961 // char c = sa[sp++];
6962 // if (c > '\u00FF')
6963 // break;
6964 // da[dp++] = (byte) c;
6965 // }
6966 // return i;
6967 // }
6968 //
6969 // @IntrinsicCandidate
6970 // int java.lang.StringCoding.encodeISOArray0(
6971 // byte[] sa, int sp, byte[] da, int dp, int len) {
6972 // int i = 0;
6973 // for (; i < len; i++) {
6974 // char c = StringUTF16.getChar(sa, sp++);
6975 // if (c > '\u00FF')
6976 // break;
6977 // da[dp++] = (byte) c;
6978 // }
6979 // return i;
6980 // }
6981 //
6982 // @IntrinsicCandidate
6983 // int java.lang.StringCoding.encodeAsciiArray0(
6984 // char[] sa, int sp, byte[] da, int dp, int len) {
6985 // int i = 0;
6986 // for (; i < len; i++) {
6987 // char c = sa[sp++];
6988 // if (c >= '\u0080')
6989 // break;
6990 // da[dp++] = (byte) c;
6991 // }
6992 // return i;
6993 // }
6994 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6995 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6996 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6997 Register tmp5, Register result, bool ascii) {
6998
6999 // rsi: src
7000 // rdi: dst
7001 // rdx: len
7002 // rcx: tmp5
7003 // rax: result
7004 ShortBranchVerifier sbv(this);
7005 assert_different_registers(src, dst, len, tmp5, result);
7006 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7007
7008 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
7009 int short_mask = ascii ? 0xff80 : 0xff00;
7010
7011 // set result
7012 xorl(result, result);
7013 // check for zero length
7014 testl(len, len);
7015 jcc(Assembler::zero, L_done);
7016
7017 movl(result, len);
7018
7019 // Setup pointers
7020 lea(src, Address(src, len, Address::times_2)); // char[]
7021 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7022 negptr(len);
7023
7024 if (UseSSE42Intrinsics || UseAVX >= 2) {
7025 Label L_copy_8_chars, L_copy_8_chars_exit;
7026 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7027
7028 if (UseAVX >= 2) {
7029 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7030 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7031 movdl(tmp1Reg, tmp5);
7032 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7033 jmp(L_chars_32_check);
7034
7035 bind(L_copy_32_chars);
7036 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7037 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7038 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7039 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7040 jccb(Assembler::notZero, L_copy_32_chars_exit);
7041 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7042 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7043 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7044
7045 bind(L_chars_32_check);
7046 addptr(len, 32);
7047 jcc(Assembler::lessEqual, L_copy_32_chars);
7048
7049 bind(L_copy_32_chars_exit);
7050 subptr(len, 16);
7051 jccb(Assembler::greater, L_copy_16_chars_exit);
7052
7053 } else if (UseSSE42Intrinsics) {
7054 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7055 movdl(tmp1Reg, tmp5);
7056 pshufd(tmp1Reg, tmp1Reg, 0);
7057 jmpb(L_chars_16_check);
7058 }
7059
7060 bind(L_copy_16_chars);
7061 if (UseAVX >= 2) {
7062 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7063 vptest(tmp2Reg, tmp1Reg);
7064 jcc(Assembler::notZero, L_copy_16_chars_exit);
7065 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7066 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7067 } else {
7068 if (UseAVX > 0) {
7069 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7070 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7071 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7072 } else {
7073 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7074 por(tmp2Reg, tmp3Reg);
7075 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7076 por(tmp2Reg, tmp4Reg);
7077 }
7078 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7079 jccb(Assembler::notZero, L_copy_16_chars_exit);
7080 packuswb(tmp3Reg, tmp4Reg);
7081 }
7082 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7083
7084 bind(L_chars_16_check);
7085 addptr(len, 16);
7086 jcc(Assembler::lessEqual, L_copy_16_chars);
7087
7088 bind(L_copy_16_chars_exit);
7089 if (UseAVX >= 2) {
7090 // clean upper bits of YMM registers
7091 vpxor(tmp2Reg, tmp2Reg);
7092 vpxor(tmp3Reg, tmp3Reg);
7093 vpxor(tmp4Reg, tmp4Reg);
7094 movdl(tmp1Reg, tmp5);
7095 pshufd(tmp1Reg, tmp1Reg, 0);
7096 }
7097 subptr(len, 8);
7098 jccb(Assembler::greater, L_copy_8_chars_exit);
7099
7100 bind(L_copy_8_chars);
7101 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7102 ptest(tmp3Reg, tmp1Reg);
7103 jccb(Assembler::notZero, L_copy_8_chars_exit);
7104 packuswb(tmp3Reg, tmp1Reg);
7105 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7106 addptr(len, 8);
7107 jccb(Assembler::lessEqual, L_copy_8_chars);
7108
7109 bind(L_copy_8_chars_exit);
7110 subptr(len, 8);
7111 jccb(Assembler::zero, L_done);
7112 }
7113
7114 bind(L_copy_1_char);
7115 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7116 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7117 jccb(Assembler::notZero, L_copy_1_char_exit);
7118 movb(Address(dst, len, Address::times_1, 0), tmp5);
7119 addptr(len, 1);
7120 jccb(Assembler::less, L_copy_1_char);
7121
7122 bind(L_copy_1_char_exit);
7123 addptr(result, len); // len is negative count of not processed elements
7124
7125 bind(L_done);
7126 }
7127
7128 /**
7129 * Helper for multiply_to_len().
7130 */
7131 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7132 addq(dest_lo, src1);
7133 adcq(dest_hi, 0);
7134 addq(dest_lo, src2);
7135 adcq(dest_hi, 0);
7136 }
7137
7138 /**
7139 * Multiply 64 bit by 64 bit first loop.
7140 */
7141 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7142 Register y, Register y_idx, Register z,
7143 Register carry, Register product,
7144 Register idx, Register kdx) {
7145 //
7146 // jlong carry, x[], y[], z[];
7147 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7148 // huge_128 product = y[idx] * x[xstart] + carry;
7149 // z[kdx] = (jlong)product;
7150 // carry = (jlong)(product >>> 64);
7151 // }
7152 // z[xstart] = carry;
7153 //
7154
7155 Label L_first_loop, L_first_loop_exit;
7156 Label L_one_x, L_one_y, L_multiply;
7157
7158 decrementl(xstart);
7159 jcc(Assembler::negative, L_one_x);
7160
7161 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7162 rorq(x_xstart, 32); // convert big-endian to little-endian
7163
7164 bind(L_first_loop);
7165 decrementl(idx);
7166 jcc(Assembler::negative, L_first_loop_exit);
7167 decrementl(idx);
7168 jcc(Assembler::negative, L_one_y);
7169 movq(y_idx, Address(y, idx, Address::times_4, 0));
7170 rorq(y_idx, 32); // convert big-endian to little-endian
7171 bind(L_multiply);
7172 movq(product, x_xstart);
7173 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7174 addq(product, carry);
7175 adcq(rdx, 0);
7176 subl(kdx, 2);
7177 movl(Address(z, kdx, Address::times_4, 4), product);
7178 shrq(product, 32);
7179 movl(Address(z, kdx, Address::times_4, 0), product);
7180 movq(carry, rdx);
7181 jmp(L_first_loop);
7182
7183 bind(L_one_y);
7184 movl(y_idx, Address(y, 0));
7185 jmp(L_multiply);
7186
7187 bind(L_one_x);
7188 movl(x_xstart, Address(x, 0));
7189 jmp(L_first_loop);
7190
7191 bind(L_first_loop_exit);
7192 }
7193
7194 /**
7195 * Multiply 64 bit by 64 bit and add 128 bit.
7196 */
7197 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7198 Register yz_idx, Register idx,
7199 Register carry, Register product, int offset) {
7200 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7201 // z[kdx] = (jlong)product;
7202
7203 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7204 rorq(yz_idx, 32); // convert big-endian to little-endian
7205 movq(product, x_xstart);
7206 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7207 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7208 rorq(yz_idx, 32); // convert big-endian to little-endian
7209
7210 add2_with_carry(rdx, product, carry, yz_idx);
7211
7212 movl(Address(z, idx, Address::times_4, offset+4), product);
7213 shrq(product, 32);
7214 movl(Address(z, idx, Address::times_4, offset), product);
7215
7216 }
7217
7218 /**
7219 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7220 */
7221 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7222 Register yz_idx, Register idx, Register jdx,
7223 Register carry, Register product,
7224 Register carry2) {
7225 // jlong carry, x[], y[], z[];
7226 // int kdx = ystart+1;
7227 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7228 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7229 // z[kdx+idx+1] = (jlong)product;
7230 // jlong carry2 = (jlong)(product >>> 64);
7231 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7232 // z[kdx+idx] = (jlong)product;
7233 // carry = (jlong)(product >>> 64);
7234 // }
7235 // idx += 2;
7236 // if (idx > 0) {
7237 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7238 // z[kdx+idx] = (jlong)product;
7239 // carry = (jlong)(product >>> 64);
7240 // }
7241 //
7242
7243 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7244
7245 movl(jdx, idx);
7246 andl(jdx, 0xFFFFFFFC);
7247 shrl(jdx, 2);
7248
7249 bind(L_third_loop);
7250 subl(jdx, 1);
7251 jcc(Assembler::negative, L_third_loop_exit);
7252 subl(idx, 4);
7253
7254 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7255 movq(carry2, rdx);
7256
7257 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7258 movq(carry, rdx);
7259 jmp(L_third_loop);
7260
7261 bind (L_third_loop_exit);
7262
7263 andl (idx, 0x3);
7264 jcc(Assembler::zero, L_post_third_loop_done);
7265
7266 Label L_check_1;
7267 subl(idx, 2);
7268 jcc(Assembler::negative, L_check_1);
7269
7270 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7271 movq(carry, rdx);
7272
7273 bind (L_check_1);
7274 addl (idx, 0x2);
7275 andl (idx, 0x1);
7276 subl(idx, 1);
7277 jcc(Assembler::negative, L_post_third_loop_done);
7278
7279 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7280 movq(product, x_xstart);
7281 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7282 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7283
7284 add2_with_carry(rdx, product, yz_idx, carry);
7285
7286 movl(Address(z, idx, Address::times_4, 0), product);
7287 shrq(product, 32);
7288
7289 shlq(rdx, 32);
7290 orq(product, rdx);
7291 movq(carry, product);
7292
7293 bind(L_post_third_loop_done);
7294 }
7295
7296 /**
7297 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7298 *
7299 */
7300 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7301 Register carry, Register carry2,
7302 Register idx, Register jdx,
7303 Register yz_idx1, Register yz_idx2,
7304 Register tmp, Register tmp3, Register tmp4) {
7305 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7306
7307 // jlong carry, x[], y[], z[];
7308 // int kdx = ystart+1;
7309 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7310 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7311 // jlong carry2 = (jlong)(tmp3 >>> 64);
7312 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7313 // carry = (jlong)(tmp4 >>> 64);
7314 // z[kdx+idx+1] = (jlong)tmp3;
7315 // z[kdx+idx] = (jlong)tmp4;
7316 // }
7317 // idx += 2;
7318 // if (idx > 0) {
7319 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7320 // z[kdx+idx] = (jlong)yz_idx1;
7321 // carry = (jlong)(yz_idx1 >>> 64);
7322 // }
7323 //
7324
7325 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7326
7327 movl(jdx, idx);
7328 andl(jdx, 0xFFFFFFFC);
7329 shrl(jdx, 2);
7330
7331 bind(L_third_loop);
7332 subl(jdx, 1);
7333 jcc(Assembler::negative, L_third_loop_exit);
7334 subl(idx, 4);
7335
7336 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7337 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7338 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7339 rorxq(yz_idx2, yz_idx2, 32);
7340
7341 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7342 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7343
7344 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7345 rorxq(yz_idx1, yz_idx1, 32);
7346 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7347 rorxq(yz_idx2, yz_idx2, 32);
7348
7349 if (VM_Version::supports_adx()) {
7350 adcxq(tmp3, carry);
7351 adoxq(tmp3, yz_idx1);
7352
7353 adcxq(tmp4, tmp);
7354 adoxq(tmp4, yz_idx2);
7355
7356 movl(carry, 0); // does not affect flags
7357 adcxq(carry2, carry);
7358 adoxq(carry2, carry);
7359 } else {
7360 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7361 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7362 }
7363 movq(carry, carry2);
7364
7365 movl(Address(z, idx, Address::times_4, 12), tmp3);
7366 shrq(tmp3, 32);
7367 movl(Address(z, idx, Address::times_4, 8), tmp3);
7368
7369 movl(Address(z, idx, Address::times_4, 4), tmp4);
7370 shrq(tmp4, 32);
7371 movl(Address(z, idx, Address::times_4, 0), tmp4);
7372
7373 jmp(L_third_loop);
7374
7375 bind (L_third_loop_exit);
7376
7377 andl (idx, 0x3);
7378 jcc(Assembler::zero, L_post_third_loop_done);
7379
7380 Label L_check_1;
7381 subl(idx, 2);
7382 jcc(Assembler::negative, L_check_1);
7383
7384 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7385 rorxq(yz_idx1, yz_idx1, 32);
7386 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7387 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7388 rorxq(yz_idx2, yz_idx2, 32);
7389
7390 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7391
7392 movl(Address(z, idx, Address::times_4, 4), tmp3);
7393 shrq(tmp3, 32);
7394 movl(Address(z, idx, Address::times_4, 0), tmp3);
7395 movq(carry, tmp4);
7396
7397 bind (L_check_1);
7398 addl (idx, 0x2);
7399 andl (idx, 0x1);
7400 subl(idx, 1);
7401 jcc(Assembler::negative, L_post_third_loop_done);
7402 movl(tmp4, Address(y, idx, Address::times_4, 0));
7403 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7404 movl(tmp4, Address(z, idx, Address::times_4, 0));
7405
7406 add2_with_carry(carry2, tmp3, tmp4, carry);
7407
7408 movl(Address(z, idx, Address::times_4, 0), tmp3);
7409 shrq(tmp3, 32);
7410
7411 shlq(carry2, 32);
7412 orq(tmp3, carry2);
7413 movq(carry, tmp3);
7414
7415 bind(L_post_third_loop_done);
7416 }
7417
7418 /**
7419 * Code for BigInteger::multiplyToLen() intrinsic.
7420 *
7421 * rdi: x
7422 * rax: xlen
7423 * rsi: y
7424 * rcx: ylen
7425 * r8: z
7426 * r11: tmp0
7427 * r12: tmp1
7428 * r13: tmp2
7429 * r14: tmp3
7430 * r15: tmp4
7431 * rbx: tmp5
7432 *
7433 */
7434 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7435 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7436 ShortBranchVerifier sbv(this);
7437 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7438
7439 push(tmp0);
7440 push(tmp1);
7441 push(tmp2);
7442 push(tmp3);
7443 push(tmp4);
7444 push(tmp5);
7445
7446 push(xlen);
7447
7448 const Register idx = tmp1;
7449 const Register kdx = tmp2;
7450 const Register xstart = tmp3;
7451
7452 const Register y_idx = tmp4;
7453 const Register carry = tmp5;
7454 const Register product = xlen;
7455 const Register x_xstart = tmp0;
7456
7457 // First Loop.
7458 //
7459 // final static long LONG_MASK = 0xffffffffL;
7460 // int xstart = xlen - 1;
7461 // int ystart = ylen - 1;
7462 // long carry = 0;
7463 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7464 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7465 // z[kdx] = (int)product;
7466 // carry = product >>> 32;
7467 // }
7468 // z[xstart] = (int)carry;
7469 //
7470
7471 movl(idx, ylen); // idx = ylen;
7472 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7473 xorq(carry, carry); // carry = 0;
7474
7475 Label L_done;
7476
7477 movl(xstart, xlen);
7478 decrementl(xstart);
7479 jcc(Assembler::negative, L_done);
7480
7481 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7482
7483 Label L_second_loop;
7484 testl(kdx, kdx);
7485 jcc(Assembler::zero, L_second_loop);
7486
7487 Label L_carry;
7488 subl(kdx, 1);
7489 jcc(Assembler::zero, L_carry);
7490
7491 movl(Address(z, kdx, Address::times_4, 0), carry);
7492 shrq(carry, 32);
7493 subl(kdx, 1);
7494
7495 bind(L_carry);
7496 movl(Address(z, kdx, Address::times_4, 0), carry);
7497
7498 // Second and third (nested) loops.
7499 //
7500 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7501 // carry = 0;
7502 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7503 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7504 // (z[k] & LONG_MASK) + carry;
7505 // z[k] = (int)product;
7506 // carry = product >>> 32;
7507 // }
7508 // z[i] = (int)carry;
7509 // }
7510 //
7511 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7512
7513 const Register jdx = tmp1;
7514
7515 bind(L_second_loop);
7516 xorl(carry, carry); // carry = 0;
7517 movl(jdx, ylen); // j = ystart+1
7518
7519 subl(xstart, 1); // i = xstart-1;
7520 jcc(Assembler::negative, L_done);
7521
7522 push (z);
7523
7524 Label L_last_x;
7525 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7526 subl(xstart, 1); // i = xstart-1;
7527 jcc(Assembler::negative, L_last_x);
7528
7529 if (UseBMI2Instructions) {
7530 movq(rdx, Address(x, xstart, Address::times_4, 0));
7531 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7532 } else {
7533 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7534 rorq(x_xstart, 32); // convert big-endian to little-endian
7535 }
7536
7537 Label L_third_loop_prologue;
7538 bind(L_third_loop_prologue);
7539
7540 push (x);
7541 push (xstart);
7542 push (ylen);
7543
7544
7545 if (UseBMI2Instructions) {
7546 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7547 } else { // !UseBMI2Instructions
7548 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7549 }
7550
7551 pop(ylen);
7552 pop(xlen);
7553 pop(x);
7554 pop(z);
7555
7556 movl(tmp3, xlen);
7557 addl(tmp3, 1);
7558 movl(Address(z, tmp3, Address::times_4, 0), carry);
7559 subl(tmp3, 1);
7560 jccb(Assembler::negative, L_done);
7561
7562 shrq(carry, 32);
7563 movl(Address(z, tmp3, Address::times_4, 0), carry);
7564 jmp(L_second_loop);
7565
7566 // Next infrequent code is moved outside loops.
7567 bind(L_last_x);
7568 if (UseBMI2Instructions) {
7569 movl(rdx, Address(x, 0));
7570 } else {
7571 movl(x_xstart, Address(x, 0));
7572 }
7573 jmp(L_third_loop_prologue);
7574
7575 bind(L_done);
7576
7577 pop(xlen);
7578
7579 pop(tmp5);
7580 pop(tmp4);
7581 pop(tmp3);
7582 pop(tmp2);
7583 pop(tmp1);
7584 pop(tmp0);
7585 }
7586
7587 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7588 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7589 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7590 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7591 Label VECTOR8_TAIL, VECTOR4_TAIL;
7592 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7593 Label SAME_TILL_END, DONE;
7594 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7595
7596 //scale is in rcx in both Win64 and Unix
7597 ShortBranchVerifier sbv(this);
7598
7599 shlq(length);
7600 xorq(result, result);
7601
7602 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7603 VM_Version::supports_avx512vlbw() && UseCountTrailingZerosInstruction) {
7604 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7605
7606 cmpq(length, 64);
7607 jcc(Assembler::less, VECTOR32_TAIL);
7608
7609 movq(tmp1, length);
7610 andq(tmp1, 0x3F); // tail count
7611 andq(length, ~(0x3F)); //vector count
7612
7613 bind(VECTOR64_LOOP);
7614 // AVX512 code to compare 64 byte vectors.
7615 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7616 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7617 kortestql(k7, k7);
7618 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7619 addq(result, 64);
7620 subq(length, 64);
7621 jccb(Assembler::notZero, VECTOR64_LOOP);
7622
7623 //bind(VECTOR64_TAIL);
7624 testq(tmp1, tmp1);
7625 jcc(Assembler::zero, SAME_TILL_END);
7626
7627 //bind(VECTOR64_TAIL);
7628 // AVX512 code to compare up to 63 byte vectors.
7629 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7630 shlxq(tmp2, tmp2, tmp1);
7631 notq(tmp2);
7632 kmovql(k3, tmp2);
7633
7634 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7635 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7636
7637 ktestql(k7, k3);
7638 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7639
7640 bind(VECTOR64_NOT_EQUAL);
7641 kmovql(tmp1, k7);
7642 notq(tmp1);
7643 tzcntq(tmp1, tmp1);
7644 addq(result, tmp1);
7645 shrq(result);
7646 jmp(DONE);
7647 bind(VECTOR32_TAIL);
7648 }
7649
7650 cmpq(length, 8);
7651 jcc(Assembler::equal, VECTOR8_LOOP);
7652 jcc(Assembler::less, VECTOR4_TAIL);
7653
7654 if (UseAVX >= 2) {
7655 Label VECTOR16_TAIL, VECTOR32_LOOP;
7656
7657 cmpq(length, 16);
7658 jcc(Assembler::equal, VECTOR16_LOOP);
7659 jcc(Assembler::less, VECTOR8_LOOP);
7660
7661 cmpq(length, 32);
7662 jccb(Assembler::less, VECTOR16_TAIL);
7663
7664 subq(length, 32);
7665 bind(VECTOR32_LOOP);
7666 vmovdqu(rymm0, Address(obja, result));
7667 vmovdqu(rymm1, Address(objb, result));
7668 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7669 vptest(rymm2, rymm2);
7670 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7671 addq(result, 32);
7672 subq(length, 32);
7673 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7674 addq(length, 32);
7675 jcc(Assembler::equal, SAME_TILL_END);
7676 //falling through if less than 32 bytes left //close the branch here.
7677
7678 bind(VECTOR16_TAIL);
7679 cmpq(length, 16);
7680 jccb(Assembler::less, VECTOR8_TAIL);
7681 bind(VECTOR16_LOOP);
7682 movdqu(rymm0, Address(obja, result));
7683 movdqu(rymm1, Address(objb, result));
7684 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7685 ptest(rymm2, rymm2);
7686 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7687 addq(result, 16);
7688 subq(length, 16);
7689 jcc(Assembler::equal, SAME_TILL_END);
7690 //falling through if less than 16 bytes left
7691 } else {//regular intrinsics
7692
7693 cmpq(length, 16);
7694 jccb(Assembler::less, VECTOR8_TAIL);
7695
7696 subq(length, 16);
7697 bind(VECTOR16_LOOP);
7698 movdqu(rymm0, Address(obja, result));
7699 movdqu(rymm1, Address(objb, result));
7700 pxor(rymm0, rymm1);
7701 ptest(rymm0, rymm0);
7702 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7703 addq(result, 16);
7704 subq(length, 16);
7705 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7706 addq(length, 16);
7707 jcc(Assembler::equal, SAME_TILL_END);
7708 //falling through if less than 16 bytes left
7709 }
7710
7711 bind(VECTOR8_TAIL);
7712 cmpq(length, 8);
7713 jccb(Assembler::less, VECTOR4_TAIL);
7714 bind(VECTOR8_LOOP);
7715 movq(tmp1, Address(obja, result));
7716 movq(tmp2, Address(objb, result));
7717 xorq(tmp1, tmp2);
7718 testq(tmp1, tmp1);
7719 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7720 addq(result, 8);
7721 subq(length, 8);
7722 jcc(Assembler::equal, SAME_TILL_END);
7723 //falling through if less than 8 bytes left
7724
7725 bind(VECTOR4_TAIL);
7726 cmpq(length, 4);
7727 jccb(Assembler::less, BYTES_TAIL);
7728 bind(VECTOR4_LOOP);
7729 movl(tmp1, Address(obja, result));
7730 xorl(tmp1, Address(objb, result));
7731 testl(tmp1, tmp1);
7732 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7733 addq(result, 4);
7734 subq(length, 4);
7735 jcc(Assembler::equal, SAME_TILL_END);
7736 //falling through if less than 4 bytes left
7737
7738 bind(BYTES_TAIL);
7739 bind(BYTES_LOOP);
7740 load_unsigned_byte(tmp1, Address(obja, result));
7741 load_unsigned_byte(tmp2, Address(objb, result));
7742 xorl(tmp1, tmp2);
7743 testl(tmp1, tmp1);
7744 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7745 decq(length);
7746 jcc(Assembler::zero, SAME_TILL_END);
7747 incq(result);
7748 load_unsigned_byte(tmp1, Address(obja, result));
7749 load_unsigned_byte(tmp2, Address(objb, result));
7750 xorl(tmp1, tmp2);
7751 testl(tmp1, tmp1);
7752 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7753 decq(length);
7754 jcc(Assembler::zero, SAME_TILL_END);
7755 incq(result);
7756 load_unsigned_byte(tmp1, Address(obja, result));
7757 load_unsigned_byte(tmp2, Address(objb, result));
7758 xorl(tmp1, tmp2);
7759 testl(tmp1, tmp1);
7760 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7761 jmp(SAME_TILL_END);
7762
7763 if (UseAVX >= 2) {
7764 bind(VECTOR32_NOT_EQUAL);
7765 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7766 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7767 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7768 vpmovmskb(tmp1, rymm0);
7769 bsfq(tmp1, tmp1);
7770 addq(result, tmp1);
7771 shrq(result);
7772 jmp(DONE);
7773 }
7774
7775 bind(VECTOR16_NOT_EQUAL);
7776 if (UseAVX >= 2) {
7777 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7778 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7779 pxor(rymm0, rymm2);
7780 } else {
7781 pcmpeqb(rymm2, rymm2);
7782 pxor(rymm0, rymm1);
7783 pcmpeqb(rymm0, rymm1);
7784 pxor(rymm0, rymm2);
7785 }
7786 pmovmskb(tmp1, rymm0);
7787 bsfq(tmp1, tmp1);
7788 addq(result, tmp1);
7789 shrq(result);
7790 jmpb(DONE);
7791
7792 bind(VECTOR8_NOT_EQUAL);
7793 bind(VECTOR4_NOT_EQUAL);
7794 bsfq(tmp1, tmp1);
7795 shrq(tmp1, 3);
7796 addq(result, tmp1);
7797 bind(BYTES_NOT_EQUAL);
7798 shrq(result);
7799 jmpb(DONE);
7800
7801 bind(SAME_TILL_END);
7802 mov64(result, -1);
7803
7804 bind(DONE);
7805 }
7806
7807 //Helper functions for square_to_len()
7808
7809 /**
7810 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7811 * Preserves x and z and modifies rest of the registers.
7812 */
7813 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7814 // Perform square and right shift by 1
7815 // Handle odd xlen case first, then for even xlen do the following
7816 // jlong carry = 0;
7817 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7818 // huge_128 product = x[j:j+1] * x[j:j+1];
7819 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7820 // z[i+2:i+3] = (jlong)(product >>> 1);
7821 // carry = (jlong)product;
7822 // }
7823
7824 xorq(tmp5, tmp5); // carry
7825 xorq(rdxReg, rdxReg);
7826 xorl(tmp1, tmp1); // index for x
7827 xorl(tmp4, tmp4); // index for z
7828
7829 Label L_first_loop, L_first_loop_exit;
7830
7831 testl(xlen, 1);
7832 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7833
7834 // Square and right shift by 1 the odd element using 32 bit multiply
7835 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7836 imulq(raxReg, raxReg);
7837 shrq(raxReg, 1);
7838 adcq(tmp5, 0);
7839 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7840 incrementl(tmp1);
7841 addl(tmp4, 2);
7842
7843 // Square and right shift by 1 the rest using 64 bit multiply
7844 bind(L_first_loop);
7845 cmpptr(tmp1, xlen);
7846 jccb(Assembler::equal, L_first_loop_exit);
7847
7848 // Square
7849 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7850 rorq(raxReg, 32); // convert big-endian to little-endian
7851 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7852
7853 // Right shift by 1 and save carry
7854 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7855 rcrq(rdxReg, 1);
7856 rcrq(raxReg, 1);
7857 adcq(tmp5, 0);
7858
7859 // Store result in z
7860 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7861 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7862
7863 // Update indices for x and z
7864 addl(tmp1, 2);
7865 addl(tmp4, 4);
7866 jmp(L_first_loop);
7867
7868 bind(L_first_loop_exit);
7869 }
7870
7871
7872 /**
7873 * Perform the following multiply add operation using BMI2 instructions
7874 * carry:sum = sum + op1*op2 + carry
7875 * op2 should be in rdx
7876 * op2 is preserved, all other registers are modified
7877 */
7878 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7879 // assert op2 is rdx
7880 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7881 addq(sum, carry);
7882 adcq(tmp2, 0);
7883 addq(sum, op1);
7884 adcq(tmp2, 0);
7885 movq(carry, tmp2);
7886 }
7887
7888 /**
7889 * Perform the following multiply add operation:
7890 * carry:sum = sum + op1*op2 + carry
7891 * Preserves op1, op2 and modifies rest of registers
7892 */
7893 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7894 // rdx:rax = op1 * op2
7895 movq(raxReg, op2);
7896 mulq(op1);
7897
7898 // rdx:rax = sum + carry + rdx:rax
7899 addq(sum, carry);
7900 adcq(rdxReg, 0);
7901 addq(sum, raxReg);
7902 adcq(rdxReg, 0);
7903
7904 // carry:sum = rdx:sum
7905 movq(carry, rdxReg);
7906 }
7907
7908 /**
7909 * Add 64 bit long carry into z[] with carry propagation.
7910 * Preserves z and carry register values and modifies rest of registers.
7911 *
7912 */
7913 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7914 Label L_fourth_loop, L_fourth_loop_exit;
7915
7916 movl(tmp1, 1);
7917 subl(zlen, 2);
7918 addq(Address(z, zlen, Address::times_4, 0), carry);
7919
7920 bind(L_fourth_loop);
7921 jccb(Assembler::carryClear, L_fourth_loop_exit);
7922 subl(zlen, 2);
7923 jccb(Assembler::negative, L_fourth_loop_exit);
7924 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7925 jmp(L_fourth_loop);
7926 bind(L_fourth_loop_exit);
7927 }
7928
7929 /**
7930 * Shift z[] left by 1 bit.
7931 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7932 *
7933 */
7934 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7935
7936 Label L_fifth_loop, L_fifth_loop_exit;
7937
7938 // Fifth loop
7939 // Perform primitiveLeftShift(z, zlen, 1)
7940
7941 const Register prev_carry = tmp1;
7942 const Register new_carry = tmp4;
7943 const Register value = tmp2;
7944 const Register zidx = tmp3;
7945
7946 // int zidx, carry;
7947 // long value;
7948 // carry = 0;
7949 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7950 // (carry:value) = (z[i] << 1) | carry ;
7951 // z[i] = value;
7952 // }
7953
7954 movl(zidx, zlen);
7955 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7956
7957 bind(L_fifth_loop);
7958 decl(zidx); // Use decl to preserve carry flag
7959 decl(zidx);
7960 jccb(Assembler::negative, L_fifth_loop_exit);
7961
7962 if (UseBMI2Instructions) {
7963 movq(value, Address(z, zidx, Address::times_4, 0));
7964 rclq(value, 1);
7965 rorxq(value, value, 32);
7966 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7967 }
7968 else {
7969 // clear new_carry
7970 xorl(new_carry, new_carry);
7971
7972 // Shift z[i] by 1, or in previous carry and save new carry
7973 movq(value, Address(z, zidx, Address::times_4, 0));
7974 shlq(value, 1);
7975 adcl(new_carry, 0);
7976
7977 orq(value, prev_carry);
7978 rorq(value, 0x20);
7979 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7980
7981 // Set previous carry = new carry
7982 movl(prev_carry, new_carry);
7983 }
7984 jmp(L_fifth_loop);
7985
7986 bind(L_fifth_loop_exit);
7987 }
7988
7989
7990 /**
7991 * Code for BigInteger::squareToLen() intrinsic
7992 *
7993 * rdi: x
7994 * rsi: len
7995 * r8: z
7996 * rcx: zlen
7997 * r12: tmp1
7998 * r13: tmp2
7999 * r14: tmp3
8000 * r15: tmp4
8001 * rbx: tmp5
8002 *
8003 */
8004 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8005
8006 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8007 push(tmp1);
8008 push(tmp2);
8009 push(tmp3);
8010 push(tmp4);
8011 push(tmp5);
8012
8013 // First loop
8014 // Store the squares, right shifted one bit (i.e., divided by 2).
8015 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8016
8017 // Add in off-diagonal sums.
8018 //
8019 // Second, third (nested) and fourth loops.
8020 // zlen +=2;
8021 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8022 // carry = 0;
8023 // long op2 = x[xidx:xidx+1];
8024 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8025 // k -= 2;
8026 // long op1 = x[j:j+1];
8027 // long sum = z[k:k+1];
8028 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8029 // z[k:k+1] = sum;
8030 // }
8031 // add_one_64(z, k, carry, tmp_regs);
8032 // }
8033
8034 const Register carry = tmp5;
8035 const Register sum = tmp3;
8036 const Register op1 = tmp4;
8037 Register op2 = tmp2;
8038
8039 push(zlen);
8040 push(len);
8041 addl(zlen,2);
8042 bind(L_second_loop);
8043 xorq(carry, carry);
8044 subl(zlen, 4);
8045 subl(len, 2);
8046 push(zlen);
8047 push(len);
8048 cmpl(len, 0);
8049 jccb(Assembler::lessEqual, L_second_loop_exit);
8050
8051 // Multiply an array by one 64 bit long.
8052 if (UseBMI2Instructions) {
8053 op2 = rdxReg;
8054 movq(op2, Address(x, len, Address::times_4, 0));
8055 rorxq(op2, op2, 32);
8056 }
8057 else {
8058 movq(op2, Address(x, len, Address::times_4, 0));
8059 rorq(op2, 32);
8060 }
8061
8062 bind(L_third_loop);
8063 decrementl(len);
8064 jccb(Assembler::negative, L_third_loop_exit);
8065 decrementl(len);
8066 jccb(Assembler::negative, L_last_x);
8067
8068 movq(op1, Address(x, len, Address::times_4, 0));
8069 rorq(op1, 32);
8070
8071 bind(L_multiply);
8072 subl(zlen, 2);
8073 movq(sum, Address(z, zlen, Address::times_4, 0));
8074
8075 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8076 if (UseBMI2Instructions) {
8077 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8078 }
8079 else {
8080 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8081 }
8082
8083 movq(Address(z, zlen, Address::times_4, 0), sum);
8084
8085 jmp(L_third_loop);
8086 bind(L_third_loop_exit);
8087
8088 // Fourth loop
8089 // Add 64 bit long carry into z with carry propagation.
8090 // Uses offsetted zlen.
8091 add_one_64(z, zlen, carry, tmp1);
8092
8093 pop(len);
8094 pop(zlen);
8095 jmp(L_second_loop);
8096
8097 // Next infrequent code is moved outside loops.
8098 bind(L_last_x);
8099 movl(op1, Address(x, 0));
8100 jmp(L_multiply);
8101
8102 bind(L_second_loop_exit);
8103 pop(len);
8104 pop(zlen);
8105 pop(len);
8106 pop(zlen);
8107
8108 // Fifth loop
8109 // Shift z left 1 bit.
8110 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8111
8112 // z[zlen-1] |= x[len-1] & 1;
8113 movl(tmp3, Address(x, len, Address::times_4, -4));
8114 andl(tmp3, 1);
8115 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8116
8117 pop(tmp5);
8118 pop(tmp4);
8119 pop(tmp3);
8120 pop(tmp2);
8121 pop(tmp1);
8122 }
8123
8124 /**
8125 * Helper function for mul_add()
8126 * Multiply the in[] by int k and add to out[] starting at offset offs using
8127 * 128 bit by 32 bit multiply and return the carry in tmp5.
8128 * Only quad int aligned length of in[] is operated on in this function.
8129 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8130 * This function preserves out, in and k registers.
8131 * len and offset point to the appropriate index in "in" & "out" correspondingly
8132 * tmp5 has the carry.
8133 * other registers are temporary and are modified.
8134 *
8135 */
8136 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8137 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8138 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8139
8140 Label L_first_loop, L_first_loop_exit;
8141
8142 movl(tmp1, len);
8143 shrl(tmp1, 2);
8144
8145 bind(L_first_loop);
8146 subl(tmp1, 1);
8147 jccb(Assembler::negative, L_first_loop_exit);
8148
8149 subl(len, 4);
8150 subl(offset, 4);
8151
8152 Register op2 = tmp2;
8153 const Register sum = tmp3;
8154 const Register op1 = tmp4;
8155 const Register carry = tmp5;
8156
8157 if (UseBMI2Instructions) {
8158 op2 = rdxReg;
8159 }
8160
8161 movq(op1, Address(in, len, Address::times_4, 8));
8162 rorq(op1, 32);
8163 movq(sum, Address(out, offset, Address::times_4, 8));
8164 rorq(sum, 32);
8165 if (UseBMI2Instructions) {
8166 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8167 }
8168 else {
8169 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8170 }
8171 // Store back in big endian from little endian
8172 rorq(sum, 0x20);
8173 movq(Address(out, offset, Address::times_4, 8), sum);
8174
8175 movq(op1, Address(in, len, Address::times_4, 0));
8176 rorq(op1, 32);
8177 movq(sum, Address(out, offset, Address::times_4, 0));
8178 rorq(sum, 32);
8179 if (UseBMI2Instructions) {
8180 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8181 }
8182 else {
8183 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8184 }
8185 // Store back in big endian from little endian
8186 rorq(sum, 0x20);
8187 movq(Address(out, offset, Address::times_4, 0), sum);
8188
8189 jmp(L_first_loop);
8190 bind(L_first_loop_exit);
8191 }
8192
8193 /**
8194 * Code for BigInteger::mulAdd() intrinsic
8195 *
8196 * rdi: out
8197 * rsi: in
8198 * r11: offs (out.length - offset)
8199 * rcx: len
8200 * r8: k
8201 * r12: tmp1
8202 * r13: tmp2
8203 * r14: tmp3
8204 * r15: tmp4
8205 * rbx: tmp5
8206 * Multiply the in[] by word k and add to out[], return the carry in rax
8207 */
8208 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8209 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8210 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8211
8212 Label L_carry, L_last_in, L_done;
8213
8214 // carry = 0;
8215 // for (int j=len-1; j >= 0; j--) {
8216 // long product = (in[j] & LONG_MASK) * kLong +
8217 // (out[offs] & LONG_MASK) + carry;
8218 // out[offs--] = (int)product;
8219 // carry = product >>> 32;
8220 // }
8221 //
8222 push(tmp1);
8223 push(tmp2);
8224 push(tmp3);
8225 push(tmp4);
8226 push(tmp5);
8227
8228 Register op2 = tmp2;
8229 const Register sum = tmp3;
8230 const Register op1 = tmp4;
8231 const Register carry = tmp5;
8232
8233 if (UseBMI2Instructions) {
8234 op2 = rdxReg;
8235 movl(op2, k);
8236 }
8237 else {
8238 movl(op2, k);
8239 }
8240
8241 xorq(carry, carry);
8242
8243 //First loop
8244
8245 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8246 //The carry is in tmp5
8247 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8248
8249 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8250 decrementl(len);
8251 jccb(Assembler::negative, L_carry);
8252 decrementl(len);
8253 jccb(Assembler::negative, L_last_in);
8254
8255 movq(op1, Address(in, len, Address::times_4, 0));
8256 rorq(op1, 32);
8257
8258 subl(offs, 2);
8259 movq(sum, Address(out, offs, Address::times_4, 0));
8260 rorq(sum, 32);
8261
8262 if (UseBMI2Instructions) {
8263 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8264 }
8265 else {
8266 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8267 }
8268
8269 // Store back in big endian from little endian
8270 rorq(sum, 0x20);
8271 movq(Address(out, offs, Address::times_4, 0), sum);
8272
8273 testl(len, len);
8274 jccb(Assembler::zero, L_carry);
8275
8276 //Multiply the last in[] entry, if any
8277 bind(L_last_in);
8278 movl(op1, Address(in, 0));
8279 movl(sum, Address(out, offs, Address::times_4, -4));
8280
8281 movl(raxReg, k);
8282 mull(op1); //tmp4 * eax -> edx:eax
8283 addl(sum, carry);
8284 adcl(rdxReg, 0);
8285 addl(sum, raxReg);
8286 adcl(rdxReg, 0);
8287 movl(carry, rdxReg);
8288
8289 movl(Address(out, offs, Address::times_4, -4), sum);
8290
8291 bind(L_carry);
8292 //return tmp5/carry as carry in rax
8293 movl(rax, carry);
8294
8295 bind(L_done);
8296 pop(tmp5);
8297 pop(tmp4);
8298 pop(tmp3);
8299 pop(tmp2);
8300 pop(tmp1);
8301 }
8302
8303 /**
8304 * Emits code to update CRC-32 with a byte value according to constants in table
8305 *
8306 * @param [in,out]crc Register containing the crc.
8307 * @param [in]val Register containing the byte to fold into the CRC.
8308 * @param [in]table Register containing the table of crc constants.
8309 *
8310 * uint32_t crc;
8311 * val = crc_table[(val ^ crc) & 0xFF];
8312 * crc = val ^ (crc >> 8);
8313 *
8314 */
8315 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8316 xorl(val, crc);
8317 andl(val, 0xFF);
8318 shrl(crc, 8); // unsigned shift
8319 xorl(crc, Address(table, val, Address::times_4, 0));
8320 }
8321
8322 /**
8323 * Fold 128-bit data chunk
8324 */
8325 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8326 if (UseAVX > 0) {
8327 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8328 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8329 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8330 pxor(xcrc, xtmp);
8331 } else {
8332 movdqa(xtmp, xcrc);
8333 pclmulhdq(xtmp, xK); // [123:64]
8334 pclmulldq(xcrc, xK); // [63:0]
8335 pxor(xcrc, xtmp);
8336 movdqu(xtmp, Address(buf, offset));
8337 pxor(xcrc, xtmp);
8338 }
8339 }
8340
8341 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8342 if (UseAVX > 0) {
8343 vpclmulhdq(xtmp, xK, xcrc);
8344 vpclmulldq(xcrc, xK, xcrc);
8345 pxor(xcrc, xbuf);
8346 pxor(xcrc, xtmp);
8347 } else {
8348 movdqa(xtmp, xcrc);
8349 pclmulhdq(xtmp, xK);
8350 pclmulldq(xcrc, xK);
8351 pxor(xcrc, xbuf);
8352 pxor(xcrc, xtmp);
8353 }
8354 }
8355
8356 /**
8357 * 8-bit folds to compute 32-bit CRC
8358 *
8359 * uint64_t xcrc;
8360 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8361 */
8362 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8363 movdl(tmp, xcrc);
8364 andl(tmp, 0xFF);
8365 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8366 psrldq(xcrc, 1); // unsigned shift one byte
8367 pxor(xcrc, xtmp);
8368 }
8369
8370 /**
8371 * uint32_t crc;
8372 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8373 */
8374 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8375 movl(tmp, crc);
8376 andl(tmp, 0xFF);
8377 shrl(crc, 8);
8378 xorl(crc, Address(table, tmp, Address::times_4, 0));
8379 }
8380
8381 /**
8382 * @param crc register containing existing CRC (32-bit)
8383 * @param buf register pointing to input byte buffer (byte*)
8384 * @param len register containing number of bytes
8385 * @param table register that will contain address of CRC table
8386 * @param tmp scratch register
8387 */
8388 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8389 assert_different_registers(crc, buf, len, table, tmp, rax);
8390
8391 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8392 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8393
8394 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8395 // context for the registers used, where all instructions below are using 128-bit mode
8396 // On EVEX without VL and BW, these instructions will all be AVX.
8397 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8398 notl(crc); // ~crc
8399 cmpl(len, 16);
8400 jcc(Assembler::less, L_tail);
8401
8402 // Align buffer to 16 bytes
8403 movl(tmp, buf);
8404 andl(tmp, 0xF);
8405 jccb(Assembler::zero, L_aligned);
8406 subl(tmp, 16);
8407 addl(len, tmp);
8408
8409 align(4);
8410 BIND(L_align_loop);
8411 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8412 update_byte_crc32(crc, rax, table);
8413 increment(buf);
8414 incrementl(tmp);
8415 jccb(Assembler::less, L_align_loop);
8416
8417 BIND(L_aligned);
8418 movl(tmp, len); // save
8419 shrl(len, 4);
8420 jcc(Assembler::zero, L_tail_restore);
8421
8422 // Fold crc into first bytes of vector
8423 movdqa(xmm1, Address(buf, 0));
8424 movdl(rax, xmm1);
8425 xorl(crc, rax);
8426 if (VM_Version::supports_sse4_1()) {
8427 pinsrd(xmm1, crc, 0);
8428 } else {
8429 pinsrw(xmm1, crc, 0);
8430 shrl(crc, 16);
8431 pinsrw(xmm1, crc, 1);
8432 }
8433 addptr(buf, 16);
8434 subl(len, 4); // len > 0
8435 jcc(Assembler::less, L_fold_tail);
8436
8437 movdqa(xmm2, Address(buf, 0));
8438 movdqa(xmm3, Address(buf, 16));
8439 movdqa(xmm4, Address(buf, 32));
8440 addptr(buf, 48);
8441 subl(len, 3);
8442 jcc(Assembler::lessEqual, L_fold_512b);
8443
8444 // Fold total 512 bits of polynomial on each iteration,
8445 // 128 bits per each of 4 parallel streams.
8446 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8447
8448 align32();
8449 BIND(L_fold_512b_loop);
8450 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8451 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8452 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8453 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8454 addptr(buf, 64);
8455 subl(len, 4);
8456 jcc(Assembler::greater, L_fold_512b_loop);
8457
8458 // Fold 512 bits to 128 bits.
8459 BIND(L_fold_512b);
8460 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8461 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8462 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8463 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8464
8465 // Fold the rest of 128 bits data chunks
8466 BIND(L_fold_tail);
8467 addl(len, 3);
8468 jccb(Assembler::lessEqual, L_fold_128b);
8469 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8470
8471 BIND(L_fold_tail_loop);
8472 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8473 addptr(buf, 16);
8474 decrementl(len);
8475 jccb(Assembler::greater, L_fold_tail_loop);
8476
8477 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8478 BIND(L_fold_128b);
8479 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8480 if (UseAVX > 0) {
8481 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8482 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8483 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8484 } else {
8485 movdqa(xmm2, xmm0);
8486 pclmulqdq(xmm2, xmm1, 0x1);
8487 movdqa(xmm3, xmm0);
8488 pand(xmm3, xmm2);
8489 pclmulqdq(xmm0, xmm3, 0x1);
8490 }
8491 psrldq(xmm1, 8);
8492 psrldq(xmm2, 4);
8493 pxor(xmm0, xmm1);
8494 pxor(xmm0, xmm2);
8495
8496 // 8 8-bit folds to compute 32-bit CRC.
8497 for (int j = 0; j < 4; j++) {
8498 fold_8bit_crc32(xmm0, table, xmm1, rax);
8499 }
8500 movdl(crc, xmm0); // mov 32 bits to general register
8501 for (int j = 0; j < 4; j++) {
8502 fold_8bit_crc32(crc, table, rax);
8503 }
8504
8505 BIND(L_tail_restore);
8506 movl(len, tmp); // restore
8507 BIND(L_tail);
8508 andl(len, 0xf);
8509 jccb(Assembler::zero, L_exit);
8510
8511 // Fold the rest of bytes
8512 align(4);
8513 BIND(L_tail_loop);
8514 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8515 update_byte_crc32(crc, rax, table);
8516 increment(buf);
8517 decrementl(len);
8518 jccb(Assembler::greater, L_tail_loop);
8519
8520 BIND(L_exit);
8521 notl(crc); // ~c
8522 }
8523
8524 // Helper function for AVX 512 CRC32
8525 // Fold 512-bit data chunks
8526 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8527 Register pos, int offset) {
8528 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8529 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8530 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8531 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8532 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8533 }
8534
8535 // Helper function for AVX 512 CRC32
8536 // Compute CRC32 for < 256B buffers
8537 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8538 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8539 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8540
8541 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8542 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8543 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8544
8545 // check if there is enough buffer to be able to fold 16B at a time
8546 cmpl(len, 32);
8547 jcc(Assembler::less, L_less_than_32);
8548
8549 // if there is, load the constants
8550 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8551 movdl(xmm0, crc); // get the initial crc value
8552 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8553 pxor(xmm7, xmm0);
8554
8555 // update the buffer pointer
8556 addl(pos, 16);
8557 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8558 subl(len, 32);
8559 jmp(L_16B_reduction_loop);
8560
8561 bind(L_less_than_32);
8562 //mov initial crc to the return value. this is necessary for zero - length buffers.
8563 movl(rax, crc);
8564 testl(len, len);
8565 jcc(Assembler::equal, L_cleanup);
8566
8567 movdl(xmm0, crc); //get the initial crc value
8568
8569 cmpl(len, 16);
8570 jcc(Assembler::equal, L_exact_16_left);
8571 jcc(Assembler::less, L_less_than_16_left);
8572
8573 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8574 pxor(xmm7, xmm0); //xor the initial crc value
8575 addl(pos, 16);
8576 subl(len, 16);
8577 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8578 jmp(L_get_last_two_xmms);
8579
8580 bind(L_less_than_16_left);
8581 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8582 pxor(xmm1, xmm1);
8583 movptr(tmp1, rsp);
8584 movdqu(Address(tmp1, 0 * 16), xmm1);
8585
8586 cmpl(len, 4);
8587 jcc(Assembler::less, L_only_less_than_4);
8588
8589 //backup the counter value
8590 movl(tmp2, len);
8591 cmpl(len, 8);
8592 jcc(Assembler::less, L_less_than_8_left);
8593
8594 //load 8 Bytes
8595 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8596 movq(Address(tmp1, 0 * 16), rax);
8597 addptr(tmp1, 8);
8598 subl(len, 8);
8599 addl(pos, 8);
8600
8601 bind(L_less_than_8_left);
8602 cmpl(len, 4);
8603 jcc(Assembler::less, L_less_than_4_left);
8604
8605 //load 4 Bytes
8606 movl(rax, Address(buf, pos, Address::times_1, 0));
8607 movl(Address(tmp1, 0 * 16), rax);
8608 addptr(tmp1, 4);
8609 subl(len, 4);
8610 addl(pos, 4);
8611
8612 bind(L_less_than_4_left);
8613 cmpl(len, 2);
8614 jcc(Assembler::less, L_less_than_2_left);
8615
8616 // load 2 Bytes
8617 movw(rax, Address(buf, pos, Address::times_1, 0));
8618 movl(Address(tmp1, 0 * 16), rax);
8619 addptr(tmp1, 2);
8620 subl(len, 2);
8621 addl(pos, 2);
8622
8623 bind(L_less_than_2_left);
8624 cmpl(len, 1);
8625 jcc(Assembler::less, L_zero_left);
8626
8627 // load 1 Byte
8628 movb(rax, Address(buf, pos, Address::times_1, 0));
8629 movb(Address(tmp1, 0 * 16), rax);
8630
8631 bind(L_zero_left);
8632 movdqu(xmm7, Address(rsp, 0));
8633 pxor(xmm7, xmm0); //xor the initial crc value
8634
8635 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8636 movdqu(xmm0, Address(rax, tmp2));
8637 pshufb(xmm7, xmm0);
8638 jmp(L_128_done);
8639
8640 bind(L_exact_16_left);
8641 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8642 pxor(xmm7, xmm0); //xor the initial crc value
8643 jmp(L_128_done);
8644
8645 bind(L_only_less_than_4);
8646 cmpl(len, 3);
8647 jcc(Assembler::less, L_only_less_than_3);
8648
8649 // load 3 Bytes
8650 movb(rax, Address(buf, pos, Address::times_1, 0));
8651 movb(Address(tmp1, 0), rax);
8652
8653 movb(rax, Address(buf, pos, Address::times_1, 1));
8654 movb(Address(tmp1, 1), rax);
8655
8656 movb(rax, Address(buf, pos, Address::times_1, 2));
8657 movb(Address(tmp1, 2), rax);
8658
8659 movdqu(xmm7, Address(rsp, 0));
8660 pxor(xmm7, xmm0); //xor the initial crc value
8661
8662 pslldq(xmm7, 0x5);
8663 jmp(L_barrett);
8664 bind(L_only_less_than_3);
8665 cmpl(len, 2);
8666 jcc(Assembler::less, L_only_less_than_2);
8667
8668 // load 2 Bytes
8669 movb(rax, Address(buf, pos, Address::times_1, 0));
8670 movb(Address(tmp1, 0), rax);
8671
8672 movb(rax, Address(buf, pos, Address::times_1, 1));
8673 movb(Address(tmp1, 1), rax);
8674
8675 movdqu(xmm7, Address(rsp, 0));
8676 pxor(xmm7, xmm0); //xor the initial crc value
8677
8678 pslldq(xmm7, 0x6);
8679 jmp(L_barrett);
8680
8681 bind(L_only_less_than_2);
8682 //load 1 Byte
8683 movb(rax, Address(buf, pos, Address::times_1, 0));
8684 movb(Address(tmp1, 0), rax);
8685
8686 movdqu(xmm7, Address(rsp, 0));
8687 pxor(xmm7, xmm0); //xor the initial crc value
8688
8689 pslldq(xmm7, 0x7);
8690 }
8691
8692 /**
8693 * Compute CRC32 using AVX512 instructions
8694 * param crc register containing existing CRC (32-bit)
8695 * param buf register pointing to input byte buffer (byte*)
8696 * param len register containing number of bytes
8697 * param table address of crc or crc32c table
8698 * param tmp1 scratch register
8699 * param tmp2 scratch register
8700 * return rax result register
8701 *
8702 * This routine is identical for crc32c with the exception of the precomputed constant
8703 * table which will be passed as the table argument. The calculation steps are
8704 * the same for both variants.
8705 */
8706 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8707 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8708
8709 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8710 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8711 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8712 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8713 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8714
8715 const Register pos = r12;
8716 push(r12);
8717 subptr(rsp, 16 * 2 + 8);
8718
8719 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8720 // context for the registers used, where all instructions below are using 128-bit mode
8721 // On EVEX without VL and BW, these instructions will all be AVX.
8722 movl(pos, 0);
8723
8724 // check if smaller than 256B
8725 cmpl(len, 256);
8726 jcc(Assembler::less, L_less_than_256);
8727
8728 // load the initial crc value
8729 movdl(xmm10, crc);
8730
8731 // receive the initial 64B data, xor the initial crc value
8732 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8733 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8734 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8735 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8736
8737 subl(len, 256);
8738 cmpl(len, 256);
8739 jcc(Assembler::less, L_fold_128_B_loop);
8740
8741 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8742 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8743 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8744 subl(len, 256);
8745
8746 bind(L_fold_256_B_loop);
8747 addl(pos, 256);
8748 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8749 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8750 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8751 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8752
8753 subl(len, 256);
8754 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8755
8756 // Fold 256 into 128
8757 addl(pos, 256);
8758 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8759 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8760 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8761
8762 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8763 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8764 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8765
8766 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8767 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8768
8769 addl(len, 128);
8770 jmp(L_fold_128_B_register);
8771
8772 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8773 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8774
8775 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8776 bind(L_fold_128_B_loop);
8777 addl(pos, 128);
8778 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8779 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8780
8781 subl(len, 128);
8782 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8783
8784 addl(pos, 128);
8785
8786 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8787 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8788 bind(L_fold_128_B_register);
8789 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8790 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8791 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8792 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8793 // save last that has no multiplicand
8794 vextracti64x2(xmm7, xmm4, 3);
8795
8796 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8797 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8798 // Needed later in reduction loop
8799 movdqu(xmm10, Address(table, 1 * 16));
8800 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8801 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8802
8803 // Swap 1,0,3,2 - 01 00 11 10
8804 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8805 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8806 vextracti128(xmm5, xmm8, 1);
8807 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8808
8809 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8810 // instead of a cmp instruction, we use the negative flag with the jl instruction
8811 addl(len, 128 - 16);
8812 jcc(Assembler::less, L_final_reduction_for_128);
8813
8814 bind(L_16B_reduction_loop);
8815 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8816 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8817 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8818 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8819 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8820 addl(pos, 16);
8821 subl(len, 16);
8822 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8823
8824 bind(L_final_reduction_for_128);
8825 addl(len, 16);
8826 jcc(Assembler::equal, L_128_done);
8827
8828 bind(L_get_last_two_xmms);
8829 movdqu(xmm2, xmm7);
8830 addl(pos, len);
8831 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8832 subl(pos, len);
8833
8834 // get rid of the extra data that was loaded before
8835 // load the shift constant
8836 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8837 movdqu(xmm0, Address(rax, len));
8838 addl(rax, len);
8839
8840 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8841 //Change mask to 512
8842 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8843 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8844
8845 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8846 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8847 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8848 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8849 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8850
8851 bind(L_128_done);
8852 // compute crc of a 128-bit value
8853 movdqu(xmm10, Address(table, 3 * 16));
8854 movdqu(xmm0, xmm7);
8855
8856 // 64b fold
8857 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8858 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8859 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8860
8861 // 32b fold
8862 movdqu(xmm0, xmm7);
8863 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8864 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8865 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8866 jmp(L_barrett);
8867
8868 bind(L_less_than_256);
8869 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8870
8871 //barrett reduction
8872 bind(L_barrett);
8873 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8874 movdqu(xmm1, xmm7);
8875 movdqu(xmm2, xmm7);
8876 movdqu(xmm10, Address(table, 4 * 16));
8877
8878 pclmulqdq(xmm7, xmm10, 0x0);
8879 pxor(xmm7, xmm2);
8880 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8881 movdqu(xmm2, xmm7);
8882 pclmulqdq(xmm7, xmm10, 0x10);
8883 pxor(xmm7, xmm2);
8884 pxor(xmm7, xmm1);
8885 pextrd(crc, xmm7, 2);
8886
8887 bind(L_cleanup);
8888 addptr(rsp, 16 * 2 + 8);
8889 pop(r12);
8890 }
8891
8892 // S. Gueron / Information Processing Letters 112 (2012) 184
8893 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8894 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8895 // Output: the 64-bit carry-less product of B * CONST
8896 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8897 Register tmp1, Register tmp2, Register tmp3) {
8898 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8899 if (n > 0) {
8900 addq(tmp3, n * 256 * 8);
8901 }
8902 // Q1 = TABLEExt[n][B & 0xFF];
8903 movl(tmp1, in);
8904 andl(tmp1, 0x000000FF);
8905 shll(tmp1, 3);
8906 addq(tmp1, tmp3);
8907 movq(tmp1, Address(tmp1, 0));
8908
8909 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8910 movl(tmp2, in);
8911 shrl(tmp2, 8);
8912 andl(tmp2, 0x000000FF);
8913 shll(tmp2, 3);
8914 addq(tmp2, tmp3);
8915 movq(tmp2, Address(tmp2, 0));
8916
8917 shlq(tmp2, 8);
8918 xorq(tmp1, tmp2);
8919
8920 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8921 movl(tmp2, in);
8922 shrl(tmp2, 16);
8923 andl(tmp2, 0x000000FF);
8924 shll(tmp2, 3);
8925 addq(tmp2, tmp3);
8926 movq(tmp2, Address(tmp2, 0));
8927
8928 shlq(tmp2, 16);
8929 xorq(tmp1, tmp2);
8930
8931 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8932 shrl(in, 24);
8933 andl(in, 0x000000FF);
8934 shll(in, 3);
8935 addq(in, tmp3);
8936 movq(in, Address(in, 0));
8937
8938 shlq(in, 24);
8939 xorq(in, tmp1);
8940 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8941 }
8942
8943 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8944 Register in_out,
8945 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8946 XMMRegister w_xtmp2,
8947 Register tmp1,
8948 Register n_tmp2, Register n_tmp3) {
8949 if (is_pclmulqdq_supported) {
8950 movdl(w_xtmp1, in_out); // modified blindly
8951
8952 movl(tmp1, const_or_pre_comp_const_index);
8953 movdl(w_xtmp2, tmp1);
8954 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8955
8956 movdq(in_out, w_xtmp1);
8957 } else {
8958 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8959 }
8960 }
8961
8962 // Recombination Alternative 2: No bit-reflections
8963 // T1 = (CRC_A * U1) << 1
8964 // T2 = (CRC_B * U2) << 1
8965 // C1 = T1 >> 32
8966 // C2 = T2 >> 32
8967 // T1 = T1 & 0xFFFFFFFF
8968 // T2 = T2 & 0xFFFFFFFF
8969 // T1 = CRC32(0, T1)
8970 // T2 = CRC32(0, T2)
8971 // C1 = C1 ^ T1
8972 // C2 = C2 ^ T2
8973 // CRC = C1 ^ C2 ^ CRC_C
8974 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8975 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8976 Register tmp1, Register tmp2,
8977 Register n_tmp3) {
8978 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8979 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8980 shlq(in_out, 1);
8981 movl(tmp1, in_out);
8982 shrq(in_out, 32);
8983 xorl(tmp2, tmp2);
8984 crc32(tmp2, tmp1, 4);
8985 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8986 shlq(in1, 1);
8987 movl(tmp1, in1);
8988 shrq(in1, 32);
8989 xorl(tmp2, tmp2);
8990 crc32(tmp2, tmp1, 4);
8991 xorl(in1, tmp2);
8992 xorl(in_out, in1);
8993 xorl(in_out, in2);
8994 }
8995
8996 // Set N to predefined value
8997 // Subtract from a length of a buffer
8998 // execute in a loop:
8999 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9000 // for i = 1 to N do
9001 // CRC_A = CRC32(CRC_A, A[i])
9002 // CRC_B = CRC32(CRC_B, B[i])
9003 // CRC_C = CRC32(CRC_C, C[i])
9004 // end for
9005 // Recombine
9006 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9007 Register in_out1, Register in_out2, Register in_out3,
9008 Register tmp1, Register tmp2, Register tmp3,
9009 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9010 Register tmp4, Register tmp5,
9011 Register n_tmp6) {
9012 Label L_processPartitions;
9013 Label L_processPartition;
9014 Label L_exit;
9015
9016 bind(L_processPartitions);
9017 cmpl(in_out1, 3 * size);
9018 jcc(Assembler::less, L_exit);
9019 xorl(tmp1, tmp1);
9020 xorl(tmp2, tmp2);
9021 movq(tmp3, in_out2);
9022 addq(tmp3, size);
9023
9024 bind(L_processPartition);
9025 crc32(in_out3, Address(in_out2, 0), 8);
9026 crc32(tmp1, Address(in_out2, size), 8);
9027 crc32(tmp2, Address(in_out2, size * 2), 8);
9028 addq(in_out2, 8);
9029 cmpq(in_out2, tmp3);
9030 jcc(Assembler::less, L_processPartition);
9031 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9032 w_xtmp1, w_xtmp2, w_xtmp3,
9033 tmp4, tmp5,
9034 n_tmp6);
9035 addq(in_out2, 2 * size);
9036 subl(in_out1, 3 * size);
9037 jmp(L_processPartitions);
9038
9039 bind(L_exit);
9040 }
9041
9042 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9043 // Input: A buffer I of L bytes.
9044 // Output: the CRC32C value of the buffer.
9045 // Notations:
9046 // Write L = 24N + r, with N = floor (L/24).
9047 // r = L mod 24 (0 <= r < 24).
9048 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9049 // N quadwords, and R consists of r bytes.
9050 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9051 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9052 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9053 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9054 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9055 Register tmp1, Register tmp2, Register tmp3,
9056 Register tmp4, Register tmp5, Register tmp6,
9057 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9058 bool is_pclmulqdq_supported) {
9059 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9060 Label L_wordByWord;
9061 Label L_byteByByteProlog;
9062 Label L_byteByByte;
9063 Label L_exit;
9064
9065 if (is_pclmulqdq_supported ) {
9066 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9067 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9068
9069 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9070 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9071
9072 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9073 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9074 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9075 } else {
9076 const_or_pre_comp_const_index[0] = 1;
9077 const_or_pre_comp_const_index[1] = 0;
9078
9079 const_or_pre_comp_const_index[2] = 3;
9080 const_or_pre_comp_const_index[3] = 2;
9081
9082 const_or_pre_comp_const_index[4] = 5;
9083 const_or_pre_comp_const_index[5] = 4;
9084 }
9085 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9086 in2, in1, in_out,
9087 tmp1, tmp2, tmp3,
9088 w_xtmp1, w_xtmp2, w_xtmp3,
9089 tmp4, tmp5,
9090 tmp6);
9091 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9092 in2, in1, in_out,
9093 tmp1, tmp2, tmp3,
9094 w_xtmp1, w_xtmp2, w_xtmp3,
9095 tmp4, tmp5,
9096 tmp6);
9097 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9098 in2, in1, in_out,
9099 tmp1, tmp2, tmp3,
9100 w_xtmp1, w_xtmp2, w_xtmp3,
9101 tmp4, tmp5,
9102 tmp6);
9103 movl(tmp1, in2);
9104 andl(tmp1, 0x00000007);
9105 negl(tmp1);
9106 addl(tmp1, in2);
9107 addq(tmp1, in1);
9108
9109 cmpq(in1, tmp1);
9110 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9111 align(16);
9112 BIND(L_wordByWord);
9113 crc32(in_out, Address(in1, 0), 8);
9114 addq(in1, 8);
9115 cmpq(in1, tmp1);
9116 jcc(Assembler::less, L_wordByWord);
9117
9118 BIND(L_byteByByteProlog);
9119 andl(in2, 0x00000007);
9120 movl(tmp2, 1);
9121
9122 cmpl(tmp2, in2);
9123 jccb(Assembler::greater, L_exit);
9124 BIND(L_byteByByte);
9125 crc32(in_out, Address(in1, 0), 1);
9126 incq(in1);
9127 incl(tmp2);
9128 cmpl(tmp2, in2);
9129 jcc(Assembler::lessEqual, L_byteByByte);
9130
9131 BIND(L_exit);
9132 }
9133 #undef BIND
9134 #undef BLOCK_COMMENT
9135
9136 // Compress char[] array to byte[].
9137 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9138 // Return the array length if every element in array can be encoded,
9139 // otherwise, the index of first non-latin1 (> 0xff) character.
9140 // @IntrinsicCandidate
9141 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9142 // for (int i = 0; i < len; i++) {
9143 // char c = src[srcOff];
9144 // if (c > 0xff) {
9145 // return i; // return index of non-latin1 char
9146 // }
9147 // dst[dstOff] = (byte)c;
9148 // srcOff++;
9149 // dstOff++;
9150 // }
9151 // return len;
9152 // }
9153 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9154 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9155 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9156 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9157 Label copy_chars_loop, done, reset_sp, copy_tail;
9158
9159 // rsi: src
9160 // rdi: dst
9161 // rdx: len
9162 // rcx: tmp5
9163 // rax: result
9164
9165 // rsi holds start addr of source char[] to be compressed
9166 // rdi holds start addr of destination byte[]
9167 // rdx holds length
9168
9169 assert(len != result, "");
9170
9171 // save length for return
9172 movl(result, len);
9173
9174 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9175 VM_Version::supports_avx512vlbw() &&
9176 VM_Version::supports_bmi2()) {
9177
9178 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9179
9180 // alignment
9181 Label post_alignment;
9182
9183 // if length of the string is less than 32, handle it the old fashioned way
9184 testl(len, -32);
9185 jcc(Assembler::zero, below_threshold);
9186
9187 // First check whether a character is compressible ( <= 0xFF).
9188 // Create mask to test for Unicode chars inside zmm vector
9189 movl(tmp5, 0x00FF);
9190 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9191
9192 testl(len, -64);
9193 jccb(Assembler::zero, post_alignment);
9194
9195 movl(tmp5, dst);
9196 andl(tmp5, (32 - 1));
9197 negl(tmp5);
9198 andl(tmp5, (32 - 1));
9199
9200 // bail out when there is nothing to be done
9201 testl(tmp5, 0xFFFFFFFF);
9202 jccb(Assembler::zero, post_alignment);
9203
9204 // ~(~0 << len), where len is the # of remaining elements to process
9205 movl(len, 0xFFFFFFFF);
9206 shlxl(len, len, tmp5);
9207 notl(len);
9208 kmovdl(mask2, len);
9209 movl(len, result);
9210
9211 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9212 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9213 ktestd(mask1, mask2);
9214 jcc(Assembler::carryClear, copy_tail);
9215
9216 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9217
9218 addptr(src, tmp5);
9219 addptr(src, tmp5);
9220 addptr(dst, tmp5);
9221 subl(len, tmp5);
9222
9223 bind(post_alignment);
9224 // end of alignment
9225
9226 movl(tmp5, len);
9227 andl(tmp5, (32 - 1)); // tail count (in chars)
9228 andl(len, ~(32 - 1)); // vector count (in chars)
9229 jccb(Assembler::zero, copy_loop_tail);
9230
9231 lea(src, Address(src, len, Address::times_2));
9232 lea(dst, Address(dst, len, Address::times_1));
9233 negptr(len);
9234
9235 bind(copy_32_loop);
9236 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9237 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9238 kortestdl(mask1, mask1);
9239 jccb(Assembler::carryClear, reset_for_copy_tail);
9240
9241 // All elements in current processed chunk are valid candidates for
9242 // compression. Write a truncated byte elements to the memory.
9243 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9244 addptr(len, 32);
9245 jccb(Assembler::notZero, copy_32_loop);
9246
9247 bind(copy_loop_tail);
9248 // bail out when there is nothing to be done
9249 testl(tmp5, 0xFFFFFFFF);
9250 jcc(Assembler::zero, done);
9251
9252 movl(len, tmp5);
9253
9254 // ~(~0 << len), where len is the # of remaining elements to process
9255 movl(tmp5, 0xFFFFFFFF);
9256 shlxl(tmp5, tmp5, len);
9257 notl(tmp5);
9258
9259 kmovdl(mask2, tmp5);
9260
9261 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9262 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9263 ktestd(mask1, mask2);
9264 jcc(Assembler::carryClear, copy_tail);
9265
9266 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9267 jmp(done);
9268
9269 bind(reset_for_copy_tail);
9270 lea(src, Address(src, tmp5, Address::times_2));
9271 lea(dst, Address(dst, tmp5, Address::times_1));
9272 subptr(len, tmp5);
9273 jmp(copy_chars_loop);
9274
9275 bind(below_threshold);
9276 }
9277
9278 if (UseSSE42Intrinsics) {
9279 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9280
9281 // vectored compression
9282 testl(len, 0xfffffff8);
9283 jcc(Assembler::zero, copy_tail);
9284
9285 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9286 movdl(tmp1Reg, tmp5);
9287 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9288
9289 andl(len, 0xfffffff0);
9290 jccb(Assembler::zero, copy_16);
9291
9292 // compress 16 chars per iter
9293 pxor(tmp4Reg, tmp4Reg);
9294
9295 lea(src, Address(src, len, Address::times_2));
9296 lea(dst, Address(dst, len, Address::times_1));
9297 negptr(len);
9298
9299 bind(copy_32_loop);
9300 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9301 por(tmp4Reg, tmp2Reg);
9302 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9303 por(tmp4Reg, tmp3Reg);
9304 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9305 jccb(Assembler::notZero, reset_for_copy_tail);
9306 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9307 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9308 addptr(len, 16);
9309 jccb(Assembler::notZero, copy_32_loop);
9310
9311 // compress next vector of 8 chars (if any)
9312 bind(copy_16);
9313 // len = 0
9314 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9315 jccb(Assembler::zero, copy_tail_sse);
9316
9317 pxor(tmp3Reg, tmp3Reg);
9318
9319 movdqu(tmp2Reg, Address(src, 0));
9320 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9321 jccb(Assembler::notZero, reset_for_copy_tail);
9322 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9323 movq(Address(dst, 0), tmp2Reg);
9324 addptr(src, 16);
9325 addptr(dst, 8);
9326 jmpb(copy_tail_sse);
9327
9328 bind(reset_for_copy_tail);
9329 movl(tmp5, result);
9330 andl(tmp5, 0x0000000f);
9331 lea(src, Address(src, tmp5, Address::times_2));
9332 lea(dst, Address(dst, tmp5, Address::times_1));
9333 subptr(len, tmp5);
9334 jmpb(copy_chars_loop);
9335
9336 bind(copy_tail_sse);
9337 movl(len, result);
9338 andl(len, 0x00000007); // tail count (in chars)
9339 }
9340 // compress 1 char per iter
9341 bind(copy_tail);
9342 testl(len, len);
9343 jccb(Assembler::zero, done);
9344 lea(src, Address(src, len, Address::times_2));
9345 lea(dst, Address(dst, len, Address::times_1));
9346 negptr(len);
9347
9348 bind(copy_chars_loop);
9349 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9350 testl(tmp5, 0xff00); // check if Unicode char
9351 jccb(Assembler::notZero, reset_sp);
9352 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9353 increment(len);
9354 jccb(Assembler::notZero, copy_chars_loop);
9355
9356 // add len then return (len will be zero if compress succeeded, otherwise negative)
9357 bind(reset_sp);
9358 addl(result, len);
9359
9360 bind(done);
9361 }
9362
9363 // Inflate byte[] array to char[].
9364 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9365 // @IntrinsicCandidate
9366 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9367 // for (int i = 0; i < len; i++) {
9368 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9369 // }
9370 // }
9371 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9372 XMMRegister tmp1, Register tmp2, KRegister mask) {
9373 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9374 // rsi: src
9375 // rdi: dst
9376 // rdx: len
9377 // rcx: tmp2
9378
9379 // rsi holds start addr of source byte[] to be inflated
9380 // rdi holds start addr of destination char[]
9381 // rdx holds length
9382 assert_different_registers(src, dst, len, tmp2);
9383 movl(tmp2, len);
9384 if ((UseAVX > 2) && // AVX512
9385 VM_Version::supports_avx512vlbw() &&
9386 VM_Version::supports_bmi2()) {
9387
9388 Label copy_32_loop, copy_tail;
9389 Register tmp3_aliased = len;
9390
9391 // if length of the string is less than 16, handle it in an old fashioned way
9392 testl(len, -16);
9393 jcc(Assembler::zero, below_threshold);
9394
9395 testl(len, -1 * AVX3Threshold);
9396 jcc(Assembler::zero, avx3_threshold);
9397
9398 // In order to use only one arithmetic operation for the main loop we use
9399 // this pre-calculation
9400 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9401 andl(len, -32); // vector count
9402 jccb(Assembler::zero, copy_tail);
9403
9404 lea(src, Address(src, len, Address::times_1));
9405 lea(dst, Address(dst, len, Address::times_2));
9406 negptr(len);
9407
9408
9409 // inflate 32 chars per iter
9410 bind(copy_32_loop);
9411 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9412 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9413 addptr(len, 32);
9414 jcc(Assembler::notZero, copy_32_loop);
9415
9416 bind(copy_tail);
9417 // bail out when there is nothing to be done
9418 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9419 jcc(Assembler::zero, done);
9420
9421 // ~(~0 << length), where length is the # of remaining elements to process
9422 movl(tmp3_aliased, -1);
9423 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9424 notl(tmp3_aliased);
9425 kmovdl(mask, tmp3_aliased);
9426 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9427 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9428
9429 jmp(done);
9430 bind(avx3_threshold);
9431 }
9432 if (UseSSE42Intrinsics) {
9433 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9434
9435 if (UseAVX > 1) {
9436 andl(tmp2, (16 - 1));
9437 andl(len, -16);
9438 jccb(Assembler::zero, copy_new_tail);
9439 } else {
9440 andl(tmp2, 0x00000007); // tail count (in chars)
9441 andl(len, 0xfffffff8); // vector count (in chars)
9442 jccb(Assembler::zero, copy_tail);
9443 }
9444
9445 // vectored inflation
9446 lea(src, Address(src, len, Address::times_1));
9447 lea(dst, Address(dst, len, Address::times_2));
9448 negptr(len);
9449
9450 if (UseAVX > 1) {
9451 bind(copy_16_loop);
9452 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9453 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9454 addptr(len, 16);
9455 jcc(Assembler::notZero, copy_16_loop);
9456
9457 bind(below_threshold);
9458 bind(copy_new_tail);
9459 movl(len, tmp2);
9460 andl(tmp2, 0x00000007);
9461 andl(len, 0xFFFFFFF8);
9462 jccb(Assembler::zero, copy_tail);
9463
9464 pmovzxbw(tmp1, Address(src, 0));
9465 movdqu(Address(dst, 0), tmp1);
9466 addptr(src, 8);
9467 addptr(dst, 2 * 8);
9468
9469 jmp(copy_tail, true);
9470 }
9471
9472 // inflate 8 chars per iter
9473 bind(copy_8_loop);
9474 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9475 movdqu(Address(dst, len, Address::times_2), tmp1);
9476 addptr(len, 8);
9477 jcc(Assembler::notZero, copy_8_loop);
9478
9479 bind(copy_tail);
9480 movl(len, tmp2);
9481
9482 cmpl(len, 4);
9483 jccb(Assembler::less, copy_bytes);
9484
9485 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9486 pmovzxbw(tmp1, tmp1);
9487 movq(Address(dst, 0), tmp1);
9488 subptr(len, 4);
9489 addptr(src, 4);
9490 addptr(dst, 8);
9491
9492 bind(copy_bytes);
9493 } else {
9494 bind(below_threshold);
9495 }
9496
9497 testl(len, len);
9498 jccb(Assembler::zero, done);
9499 lea(src, Address(src, len, Address::times_1));
9500 lea(dst, Address(dst, len, Address::times_2));
9501 negptr(len);
9502
9503 // inflate 1 char per iter
9504 bind(copy_chars_loop);
9505 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9506 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9507 increment(len);
9508 jcc(Assembler::notZero, copy_chars_loop);
9509
9510 bind(done);
9511 }
9512
9513 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9514 switch(type) {
9515 case T_BYTE:
9516 case T_BOOLEAN:
9517 evmovdqub(dst, kmask, src, merge, vector_len);
9518 break;
9519 case T_CHAR:
9520 case T_SHORT:
9521 evmovdquw(dst, kmask, src, merge, vector_len);
9522 break;
9523 case T_INT:
9524 case T_FLOAT:
9525 evmovdqul(dst, kmask, src, merge, vector_len);
9526 break;
9527 case T_LONG:
9528 case T_DOUBLE:
9529 evmovdquq(dst, kmask, src, merge, vector_len);
9530 break;
9531 default:
9532 fatal("Unexpected type argument %s", type2name(type));
9533 break;
9534 }
9535 }
9536
9537
9538 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9539 switch(type) {
9540 case T_BYTE:
9541 case T_BOOLEAN:
9542 evmovdqub(dst, kmask, src, merge, vector_len);
9543 break;
9544 case T_CHAR:
9545 case T_SHORT:
9546 evmovdquw(dst, kmask, src, merge, vector_len);
9547 break;
9548 case T_INT:
9549 case T_FLOAT:
9550 evmovdqul(dst, kmask, src, merge, vector_len);
9551 break;
9552 case T_LONG:
9553 case T_DOUBLE:
9554 evmovdquq(dst, kmask, src, merge, vector_len);
9555 break;
9556 default:
9557 fatal("Unexpected type argument %s", type2name(type));
9558 break;
9559 }
9560 }
9561
9562 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9563 switch(type) {
9564 case T_BYTE:
9565 case T_BOOLEAN:
9566 evmovdqub(dst, kmask, src, merge, vector_len);
9567 break;
9568 case T_CHAR:
9569 case T_SHORT:
9570 evmovdquw(dst, kmask, src, merge, vector_len);
9571 break;
9572 case T_INT:
9573 case T_FLOAT:
9574 evmovdqul(dst, kmask, src, merge, vector_len);
9575 break;
9576 case T_LONG:
9577 case T_DOUBLE:
9578 evmovdquq(dst, kmask, src, merge, vector_len);
9579 break;
9580 default:
9581 fatal("Unexpected type argument %s", type2name(type));
9582 break;
9583 }
9584 }
9585
9586 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9587 switch(masklen) {
9588 case 2:
9589 knotbl(dst, src);
9590 movl(rtmp, 3);
9591 kmovbl(ktmp, rtmp);
9592 kandbl(dst, ktmp, dst);
9593 break;
9594 case 4:
9595 knotbl(dst, src);
9596 movl(rtmp, 15);
9597 kmovbl(ktmp, rtmp);
9598 kandbl(dst, ktmp, dst);
9599 break;
9600 case 8:
9601 knotbl(dst, src);
9602 break;
9603 case 16:
9604 knotwl(dst, src);
9605 break;
9606 case 32:
9607 knotdl(dst, src);
9608 break;
9609 case 64:
9610 knotql(dst, src);
9611 break;
9612 default:
9613 fatal("Unexpected vector length %d", masklen);
9614 break;
9615 }
9616 }
9617
9618 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9619 switch(type) {
9620 case T_BOOLEAN:
9621 case T_BYTE:
9622 kandbl(dst, src1, src2);
9623 break;
9624 case T_CHAR:
9625 case T_SHORT:
9626 kandwl(dst, src1, src2);
9627 break;
9628 case T_INT:
9629 case T_FLOAT:
9630 kanddl(dst, src1, src2);
9631 break;
9632 case T_LONG:
9633 case T_DOUBLE:
9634 kandql(dst, src1, src2);
9635 break;
9636 default:
9637 fatal("Unexpected type argument %s", type2name(type));
9638 break;
9639 }
9640 }
9641
9642 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9643 switch(type) {
9644 case T_BOOLEAN:
9645 case T_BYTE:
9646 korbl(dst, src1, src2);
9647 break;
9648 case T_CHAR:
9649 case T_SHORT:
9650 korwl(dst, src1, src2);
9651 break;
9652 case T_INT:
9653 case T_FLOAT:
9654 kordl(dst, src1, src2);
9655 break;
9656 case T_LONG:
9657 case T_DOUBLE:
9658 korql(dst, src1, src2);
9659 break;
9660 default:
9661 fatal("Unexpected type argument %s", type2name(type));
9662 break;
9663 }
9664 }
9665
9666 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9667 switch(type) {
9668 case T_BOOLEAN:
9669 case T_BYTE:
9670 kxorbl(dst, src1, src2);
9671 break;
9672 case T_CHAR:
9673 case T_SHORT:
9674 kxorwl(dst, src1, src2);
9675 break;
9676 case T_INT:
9677 case T_FLOAT:
9678 kxordl(dst, src1, src2);
9679 break;
9680 case T_LONG:
9681 case T_DOUBLE:
9682 kxorql(dst, src1, src2);
9683 break;
9684 default:
9685 fatal("Unexpected type argument %s", type2name(type));
9686 break;
9687 }
9688 }
9689
9690 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9691 switch(type) {
9692 case T_BOOLEAN:
9693 case T_BYTE:
9694 evpermb(dst, mask, nds, src, merge, vector_len); break;
9695 case T_CHAR:
9696 case T_SHORT:
9697 evpermw(dst, mask, nds, src, merge, vector_len); break;
9698 case T_INT:
9699 case T_FLOAT:
9700 evpermd(dst, mask, nds, src, merge, vector_len); break;
9701 case T_LONG:
9702 case T_DOUBLE:
9703 evpermq(dst, mask, nds, src, merge, vector_len); break;
9704 default:
9705 fatal("Unexpected type argument %s", type2name(type)); break;
9706 }
9707 }
9708
9709 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9710 switch(type) {
9711 case T_BOOLEAN:
9712 case T_BYTE:
9713 evpermb(dst, mask, nds, src, merge, vector_len); break;
9714 case T_CHAR:
9715 case T_SHORT:
9716 evpermw(dst, mask, nds, src, merge, vector_len); break;
9717 case T_INT:
9718 case T_FLOAT:
9719 evpermd(dst, mask, nds, src, merge, vector_len); break;
9720 case T_LONG:
9721 case T_DOUBLE:
9722 evpermq(dst, mask, nds, src, merge, vector_len); break;
9723 default:
9724 fatal("Unexpected type argument %s", type2name(type)); break;
9725 }
9726 }
9727
9728 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9729 switch(type) {
9730 case T_BYTE:
9731 evpminub(dst, mask, nds, src, merge, vector_len); break;
9732 case T_SHORT:
9733 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9734 case T_INT:
9735 evpminud(dst, mask, nds, src, merge, vector_len); break;
9736 case T_LONG:
9737 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9738 default:
9739 fatal("Unexpected type argument %s", type2name(type)); break;
9740 }
9741 }
9742
9743 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9744 switch(type) {
9745 case T_BYTE:
9746 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9747 case T_SHORT:
9748 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9749 case T_INT:
9750 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9751 case T_LONG:
9752 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9753 default:
9754 fatal("Unexpected type argument %s", type2name(type)); break;
9755 }
9756 }
9757
9758 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9759 switch(type) {
9760 case T_BYTE:
9761 evpminub(dst, mask, nds, src, merge, vector_len); break;
9762 case T_SHORT:
9763 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9764 case T_INT:
9765 evpminud(dst, mask, nds, src, merge, vector_len); break;
9766 case T_LONG:
9767 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9768 default:
9769 fatal("Unexpected type argument %s", type2name(type)); break;
9770 }
9771 }
9772
9773 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9774 switch(type) {
9775 case T_BYTE:
9776 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9777 case T_SHORT:
9778 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9779 case T_INT:
9780 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9781 case T_LONG:
9782 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9783 default:
9784 fatal("Unexpected type argument %s", type2name(type)); break;
9785 }
9786 }
9787
9788 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9789 switch(type) {
9790 case T_BYTE:
9791 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9792 case T_SHORT:
9793 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9794 case T_INT:
9795 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9796 case T_LONG:
9797 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9798 case T_FLOAT:
9799 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9800 case T_DOUBLE:
9801 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9802 default:
9803 fatal("Unexpected type argument %s", type2name(type)); break;
9804 }
9805 }
9806
9807 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9808 switch(type) {
9809 case T_BYTE:
9810 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9811 case T_SHORT:
9812 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9813 case T_INT:
9814 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9815 case T_LONG:
9816 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9817 case T_FLOAT:
9818 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9819 case T_DOUBLE:
9820 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9821 default:
9822 fatal("Unexpected type argument %s", type2name(type)); break;
9823 }
9824 }
9825
9826 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9827 switch(type) {
9828 case T_BYTE:
9829 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9830 case T_SHORT:
9831 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9832 case T_INT:
9833 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9834 case T_LONG:
9835 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9836 case T_FLOAT:
9837 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9838 case T_DOUBLE:
9839 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9840 default:
9841 fatal("Unexpected type argument %s", type2name(type)); break;
9842 }
9843 }
9844
9845 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9846 switch(type) {
9847 case T_BYTE:
9848 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9849 case T_SHORT:
9850 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9851 case T_INT:
9852 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9853 case T_LONG:
9854 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9855 case T_FLOAT:
9856 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9857 case T_DOUBLE:
9858 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9859 default:
9860 fatal("Unexpected type argument %s", type2name(type)); break;
9861 }
9862 }
9863
9864 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9865 switch(type) {
9866 case T_INT:
9867 evpxord(dst, mask, nds, src, merge, vector_len); break;
9868 case T_LONG:
9869 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9870 default:
9871 fatal("Unexpected type argument %s", type2name(type)); break;
9872 }
9873 }
9874
9875 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9876 switch(type) {
9877 case T_INT:
9878 evpxord(dst, mask, nds, src, merge, vector_len); break;
9879 case T_LONG:
9880 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9881 default:
9882 fatal("Unexpected type argument %s", type2name(type)); break;
9883 }
9884 }
9885
9886 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9887 switch(type) {
9888 case T_INT:
9889 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9890 case T_LONG:
9891 evporq(dst, mask, nds, src, merge, vector_len); break;
9892 default:
9893 fatal("Unexpected type argument %s", type2name(type)); break;
9894 }
9895 }
9896
9897 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9898 switch(type) {
9899 case T_INT:
9900 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9901 case T_LONG:
9902 evporq(dst, mask, nds, src, merge, vector_len); break;
9903 default:
9904 fatal("Unexpected type argument %s", type2name(type)); break;
9905 }
9906 }
9907
9908 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9909 switch(type) {
9910 case T_INT:
9911 evpandd(dst, mask, nds, src, merge, vector_len); break;
9912 case T_LONG:
9913 evpandq(dst, mask, nds, src, merge, vector_len); break;
9914 default:
9915 fatal("Unexpected type argument %s", type2name(type)); break;
9916 }
9917 }
9918
9919 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9920 switch(type) {
9921 case T_INT:
9922 evpandd(dst, mask, nds, src, merge, vector_len); break;
9923 case T_LONG:
9924 evpandq(dst, mask, nds, src, merge, vector_len); break;
9925 default:
9926 fatal("Unexpected type argument %s", type2name(type)); break;
9927 }
9928 }
9929
9930 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
9931 switch(masklen) {
9932 case 8:
9933 kortestbl(src1, src2);
9934 break;
9935 case 16:
9936 kortestwl(src1, src2);
9937 break;
9938 case 32:
9939 kortestdl(src1, src2);
9940 break;
9941 case 64:
9942 kortestql(src1, src2);
9943 break;
9944 default:
9945 fatal("Unexpected mask length %d", masklen);
9946 break;
9947 }
9948 }
9949
9950
9951 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
9952 switch(masklen) {
9953 case 8:
9954 ktestbl(src1, src2);
9955 break;
9956 case 16:
9957 ktestwl(src1, src2);
9958 break;
9959 case 32:
9960 ktestdl(src1, src2);
9961 break;
9962 case 64:
9963 ktestql(src1, src2);
9964 break;
9965 default:
9966 fatal("Unexpected mask length %d", masklen);
9967 break;
9968 }
9969 }
9970
9971 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9972 switch(type) {
9973 case T_INT:
9974 evprold(dst, mask, src, shift, merge, vlen_enc); break;
9975 case T_LONG:
9976 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
9977 default:
9978 fatal("Unexpected type argument %s", type2name(type)); break;
9979 break;
9980 }
9981 }
9982
9983 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9984 switch(type) {
9985 case T_INT:
9986 evprord(dst, mask, src, shift, merge, vlen_enc); break;
9987 case T_LONG:
9988 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
9989 default:
9990 fatal("Unexpected type argument %s", type2name(type)); break;
9991 }
9992 }
9993
9994 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9995 switch(type) {
9996 case T_INT:
9997 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
9998 case T_LONG:
9999 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10000 default:
10001 fatal("Unexpected type argument %s", type2name(type)); break;
10002 }
10003 }
10004
10005 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10006 switch(type) {
10007 case T_INT:
10008 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10009 case T_LONG:
10010 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10011 default:
10012 fatal("Unexpected type argument %s", type2name(type)); break;
10013 }
10014 }
10015
10016 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10017 assert(rscratch != noreg || always_reachable(src), "missing");
10018
10019 if (reachable(src)) {
10020 evpandq(dst, nds, as_Address(src), vector_len);
10021 } else {
10022 lea(rscratch, src);
10023 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10024 }
10025 }
10026
10027 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10028 assert(rscratch != noreg || always_reachable(src), "missing");
10029
10030 if (reachable(src)) {
10031 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10032 } else {
10033 lea(rscratch, src);
10034 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10035 }
10036 }
10037
10038 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10039 assert(rscratch != noreg || always_reachable(src), "missing");
10040
10041 if (reachable(src)) {
10042 evporq(dst, nds, as_Address(src), vector_len);
10043 } else {
10044 lea(rscratch, src);
10045 evporq(dst, nds, Address(rscratch, 0), vector_len);
10046 }
10047 }
10048
10049 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10050 assert(rscratch != noreg || always_reachable(src), "missing");
10051
10052 if (reachable(src)) {
10053 vpshufb(dst, nds, as_Address(src), vector_len);
10054 } else {
10055 lea(rscratch, src);
10056 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10057 }
10058 }
10059
10060 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10061 assert(rscratch != noreg || always_reachable(src), "missing");
10062
10063 if (reachable(src)) {
10064 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10065 } else {
10066 lea(rscratch, src);
10067 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10068 }
10069 }
10070
10071 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10072 assert(rscratch != noreg || always_reachable(src3), "missing");
10073
10074 if (reachable(src3)) {
10075 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10076 } else {
10077 lea(rscratch, src3);
10078 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10079 }
10080 }
10081
10082 #if COMPILER2_OR_JVMCI
10083
10084 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10085 Register length, Register temp, int vec_enc) {
10086 // Computing mask for predicated vector store.
10087 movptr(temp, -1);
10088 bzhiq(temp, temp, length);
10089 kmov(mask, temp);
10090 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10091 }
10092
10093 // Set memory operation for length "less than" 64 bytes.
10094 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10095 XMMRegister xmm, KRegister mask, Register length,
10096 Register temp, bool use64byteVector) {
10097 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10098 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10099 if (!use64byteVector) {
10100 fill32(dst, disp, xmm);
10101 subptr(length, 32 >> shift);
10102 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10103 } else {
10104 assert(MaxVectorSize == 64, "vector length != 64");
10105 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10106 }
10107 }
10108
10109
10110 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10111 XMMRegister xmm, KRegister mask, Register length,
10112 Register temp) {
10113 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10114 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10115 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10116 }
10117
10118
10119 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10120 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10121 vmovdqu(dst, xmm);
10122 }
10123
10124 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10125 fill32(Address(dst, disp), xmm);
10126 }
10127
10128 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10129 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10130 if (!use64byteVector) {
10131 fill32(dst, xmm);
10132 fill32(dst.plus_disp(32), xmm);
10133 } else {
10134 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10135 }
10136 }
10137
10138 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10139 fill64(Address(dst, disp), xmm, use64byteVector);
10140 }
10141
10142 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10143 Register count, Register rtmp, XMMRegister xtmp) {
10144 Label L_exit;
10145 Label L_fill_start;
10146 Label L_fill_64_bytes;
10147 Label L_fill_96_bytes;
10148 Label L_fill_128_bytes;
10149 Label L_fill_128_bytes_loop;
10150 Label L_fill_128_loop_header;
10151 Label L_fill_128_bytes_loop_header;
10152 Label L_fill_128_bytes_loop_pre_header;
10153 Label L_fill_zmm_sequence;
10154
10155 int shift = -1;
10156 switch(type) {
10157 case T_BYTE: shift = 0;
10158 break;
10159 case T_SHORT: shift = 1;
10160 break;
10161 case T_INT: shift = 2;
10162 break;
10163 /* Uncomment when LONG fill stubs are supported.
10164 case T_LONG: shift = 3;
10165 break;
10166 */
10167 default:
10168 fatal("Unhandled type: %s\n", type2name(type));
10169 }
10170
10171 if ((CopyAVX3Threshold != 0) || (MaxVectorSize == 32)) {
10172
10173 if (MaxVectorSize == 64) {
10174 cmpq(count, CopyAVX3Threshold >> shift);
10175 jcc(Assembler::greater, L_fill_zmm_sequence);
10176 }
10177
10178 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10179
10180 bind(L_fill_start);
10181
10182 cmpq(count, 32 >> shift);
10183 jccb(Assembler::greater, L_fill_64_bytes);
10184 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10185 jmp(L_exit);
10186
10187 bind(L_fill_64_bytes);
10188 cmpq(count, 64 >> shift);
10189 jccb(Assembler::greater, L_fill_96_bytes);
10190 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10191 jmp(L_exit);
10192
10193 bind(L_fill_96_bytes);
10194 cmpq(count, 96 >> shift);
10195 jccb(Assembler::greater, L_fill_128_bytes);
10196 fill64(to, 0, xtmp);
10197 subq(count, 64 >> shift);
10198 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10199 jmp(L_exit);
10200
10201 bind(L_fill_128_bytes);
10202 cmpq(count, 128 >> shift);
10203 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10204 fill64(to, 0, xtmp);
10205 fill32(to, 64, xtmp);
10206 subq(count, 96 >> shift);
10207 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10208 jmp(L_exit);
10209
10210 bind(L_fill_128_bytes_loop_pre_header);
10211 {
10212 mov(rtmp, to);
10213 andq(rtmp, 31);
10214 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10215 negq(rtmp);
10216 addq(rtmp, 32);
10217 mov64(r8, -1L);
10218 bzhiq(r8, r8, rtmp);
10219 kmovql(k2, r8);
10220 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10221 addq(to, rtmp);
10222 shrq(rtmp, shift);
10223 subq(count, rtmp);
10224 }
10225
10226 cmpq(count, 128 >> shift);
10227 jcc(Assembler::less, L_fill_start);
10228
10229 bind(L_fill_128_bytes_loop_header);
10230 subq(count, 128 >> shift);
10231
10232 align32();
10233 bind(L_fill_128_bytes_loop);
10234 fill64(to, 0, xtmp);
10235 fill64(to, 64, xtmp);
10236 addq(to, 128);
10237 subq(count, 128 >> shift);
10238 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10239
10240 addq(count, 128 >> shift);
10241 jcc(Assembler::zero, L_exit);
10242 jmp(L_fill_start);
10243 }
10244
10245 if (MaxVectorSize == 64) {
10246 // Sequence using 64 byte ZMM register.
10247 Label L_fill_128_bytes_zmm;
10248 Label L_fill_192_bytes_zmm;
10249 Label L_fill_192_bytes_loop_zmm;
10250 Label L_fill_192_bytes_loop_header_zmm;
10251 Label L_fill_192_bytes_loop_pre_header_zmm;
10252 Label L_fill_start_zmm_sequence;
10253
10254 bind(L_fill_zmm_sequence);
10255 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10256
10257 bind(L_fill_start_zmm_sequence);
10258 cmpq(count, 64 >> shift);
10259 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10260 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10261 jmp(L_exit);
10262
10263 bind(L_fill_128_bytes_zmm);
10264 cmpq(count, 128 >> shift);
10265 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10266 fill64(to, 0, xtmp, true);
10267 subq(count, 64 >> shift);
10268 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10269 jmp(L_exit);
10270
10271 bind(L_fill_192_bytes_zmm);
10272 cmpq(count, 192 >> shift);
10273 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10274 fill64(to, 0, xtmp, true);
10275 fill64(to, 64, xtmp, true);
10276 subq(count, 128 >> shift);
10277 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10278 jmp(L_exit);
10279
10280 bind(L_fill_192_bytes_loop_pre_header_zmm);
10281 {
10282 movq(rtmp, to);
10283 andq(rtmp, 63);
10284 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10285 negq(rtmp);
10286 addq(rtmp, 64);
10287 mov64(r8, -1L);
10288 bzhiq(r8, r8, rtmp);
10289 kmovql(k2, r8);
10290 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10291 addq(to, rtmp);
10292 shrq(rtmp, shift);
10293 subq(count, rtmp);
10294 }
10295
10296 cmpq(count, 192 >> shift);
10297 jcc(Assembler::less, L_fill_start_zmm_sequence);
10298
10299 bind(L_fill_192_bytes_loop_header_zmm);
10300 subq(count, 192 >> shift);
10301
10302 align32();
10303 bind(L_fill_192_bytes_loop_zmm);
10304 fill64(to, 0, xtmp, true);
10305 fill64(to, 64, xtmp, true);
10306 fill64(to, 128, xtmp, true);
10307 addq(to, 192);
10308 subq(count, 192 >> shift);
10309 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10310
10311 addq(count, 192 >> shift);
10312 jcc(Assembler::zero, L_exit);
10313 jmp(L_fill_start_zmm_sequence);
10314 }
10315 bind(L_exit);
10316 }
10317 #endif //COMPILER2_OR_JVMCI
10318
10319
10320 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10321 Label done;
10322 cvttss2sil(dst, src);
10323 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10324 cmpl(dst, 0x80000000); // float_sign_flip
10325 jccb(Assembler::notEqual, done);
10326 subptr(rsp, 8);
10327 movflt(Address(rsp, 0), src);
10328 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10329 pop(dst);
10330 bind(done);
10331 }
10332
10333 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10334 Label done;
10335 cvttsd2sil(dst, src);
10336 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10337 cmpl(dst, 0x80000000); // float_sign_flip
10338 jccb(Assembler::notEqual, done);
10339 subptr(rsp, 8);
10340 movdbl(Address(rsp, 0), src);
10341 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10342 pop(dst);
10343 bind(done);
10344 }
10345
10346 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10347 Label done;
10348 cvttss2siq(dst, src);
10349 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10350 jccb(Assembler::notEqual, done);
10351 subptr(rsp, 8);
10352 movflt(Address(rsp, 0), src);
10353 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10354 pop(dst);
10355 bind(done);
10356 }
10357
10358 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10359 // Following code is line by line assembly translation rounding algorithm.
10360 // Please refer to java.lang.Math.round(float) algorithm for details.
10361 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10362 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10363 const int32_t FloatConsts_EXP_BIAS = 127;
10364 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10365 const int32_t MINUS_32 = 0xFFFFFFE0;
10366 Label L_special_case, L_block1, L_exit;
10367 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10368 movdl(dst, src);
10369 andl(dst, rtmp);
10370 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10371 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10372 subl(rtmp, dst);
10373 movl(rcx, rtmp);
10374 movl(dst, MINUS_32);
10375 testl(rtmp, dst);
10376 jccb(Assembler::notEqual, L_special_case);
10377 movdl(dst, src);
10378 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10379 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10380 movdl(rtmp, src);
10381 testl(rtmp, rtmp);
10382 jccb(Assembler::greaterEqual, L_block1);
10383 negl(dst);
10384 bind(L_block1);
10385 sarl(dst);
10386 addl(dst, 0x1);
10387 sarl(dst, 0x1);
10388 jmp(L_exit);
10389 bind(L_special_case);
10390 convert_f2i(dst, src);
10391 bind(L_exit);
10392 }
10393
10394 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10395 // Following code is line by line assembly translation rounding algorithm.
10396 // Please refer to java.lang.Math.round(double) algorithm for details.
10397 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10398 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10399 const int64_t DoubleConsts_EXP_BIAS = 1023;
10400 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10401 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10402 Label L_special_case, L_block1, L_exit;
10403 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10404 movq(dst, src);
10405 andq(dst, rtmp);
10406 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10407 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10408 subq(rtmp, dst);
10409 movq(rcx, rtmp);
10410 mov64(dst, MINUS_64);
10411 testq(rtmp, dst);
10412 jccb(Assembler::notEqual, L_special_case);
10413 movq(dst, src);
10414 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10415 andq(dst, rtmp);
10416 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10417 orq(dst, rtmp);
10418 movq(rtmp, src);
10419 testq(rtmp, rtmp);
10420 jccb(Assembler::greaterEqual, L_block1);
10421 negq(dst);
10422 bind(L_block1);
10423 sarq(dst);
10424 addq(dst, 0x1);
10425 sarq(dst, 0x1);
10426 jmp(L_exit);
10427 bind(L_special_case);
10428 convert_d2l(dst, src);
10429 bind(L_exit);
10430 }
10431
10432 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10433 Label done;
10434 cvttsd2siq(dst, src);
10435 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10436 jccb(Assembler::notEqual, done);
10437 subptr(rsp, 8);
10438 movdbl(Address(rsp, 0), src);
10439 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10440 pop(dst);
10441 bind(done);
10442 }
10443
10444 void MacroAssembler::cache_wb(Address line)
10445 {
10446 // 64 bit cpus always support clflush
10447 bool optimized = VM_Version::supports_clflushopt();
10448 bool no_evict = VM_Version::supports_clwb();
10449
10450 // prefer clwb (writeback without evict) otherwise
10451 // prefer clflushopt (potentially parallel writeback with evict)
10452 // otherwise fallback on clflush (serial writeback with evict)
10453
10454 if (optimized) {
10455 if (no_evict) {
10456 clwb(line);
10457 } else {
10458 clflushopt(line);
10459 }
10460 } else {
10461 // no need for fence when using CLFLUSH
10462 clflush(line);
10463 }
10464 }
10465
10466 void MacroAssembler::cache_wbsync(bool is_pre)
10467 {
10468 bool optimized = VM_Version::supports_clflushopt();
10469 bool no_evict = VM_Version::supports_clwb();
10470
10471 // pick the correct implementation
10472
10473 if (!is_pre && (optimized || no_evict)) {
10474 // need an sfence for post flush when using clflushopt or clwb
10475 // otherwise no no need for any synchroniaztion
10476
10477 sfence();
10478 }
10479 }
10480
10481 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10482 switch (cond) {
10483 // Note some conditions are synonyms for others
10484 case Assembler::zero: return Assembler::notZero;
10485 case Assembler::notZero: return Assembler::zero;
10486 case Assembler::less: return Assembler::greaterEqual;
10487 case Assembler::lessEqual: return Assembler::greater;
10488 case Assembler::greater: return Assembler::lessEqual;
10489 case Assembler::greaterEqual: return Assembler::less;
10490 case Assembler::below: return Assembler::aboveEqual;
10491 case Assembler::belowEqual: return Assembler::above;
10492 case Assembler::above: return Assembler::belowEqual;
10493 case Assembler::aboveEqual: return Assembler::below;
10494 case Assembler::overflow: return Assembler::noOverflow;
10495 case Assembler::noOverflow: return Assembler::overflow;
10496 case Assembler::negative: return Assembler::positive;
10497 case Assembler::positive: return Assembler::negative;
10498 case Assembler::parity: return Assembler::noParity;
10499 case Assembler::noParity: return Assembler::parity;
10500 }
10501 ShouldNotReachHere(); return Assembler::overflow;
10502 }
10503
10504 // This is simply a call to Thread::current()
10505 void MacroAssembler::get_thread_slow(Register thread) {
10506 if (thread != rax) {
10507 push(rax);
10508 }
10509 push(rdi);
10510 push(rsi);
10511 push(rdx);
10512 push(rcx);
10513 push(r8);
10514 push(r9);
10515 push(r10);
10516 push(r11);
10517
10518 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10519
10520 pop(r11);
10521 pop(r10);
10522 pop(r9);
10523 pop(r8);
10524 pop(rcx);
10525 pop(rdx);
10526 pop(rsi);
10527 pop(rdi);
10528 if (thread != rax) {
10529 mov(thread, rax);
10530 pop(rax);
10531 }
10532 }
10533
10534 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10535 Label L_stack_ok;
10536 if (bias == 0) {
10537 testptr(sp, 2 * wordSize - 1);
10538 } else {
10539 // lea(tmp, Address(rsp, bias);
10540 mov(tmp, sp);
10541 addptr(tmp, bias);
10542 testptr(tmp, 2 * wordSize - 1);
10543 }
10544 jcc(Assembler::equal, L_stack_ok);
10545 block_comment(msg);
10546 stop(msg);
10547 bind(L_stack_ok);
10548 }
10549
10550 // Implements fast-locking.
10551 //
10552 // obj: the object to be locked
10553 // reg_rax: rax
10554 // thread: the thread which attempts to lock obj
10555 // tmp: a temporary register
10556 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow) {
10557 Register thread = r15_thread;
10558
10559 assert(reg_rax == rax, "");
10560 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10561
10562 Label push;
10563 const Register top = tmp;
10564
10565 // Preload the markWord. It is important that this is the first
10566 // instruction emitted as it is part of C1's null check semantics.
10567 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10568
10569 if (UseObjectMonitorTable) {
10570 // Clear cache in case fast locking succeeds or we need to take the slow-path.
10571 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10572 }
10573
10574 if (DiagnoseSyncOnValueBasedClasses != 0) {
10575 load_klass(tmp, obj, rscratch1);
10576 testb(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
10577 jcc(Assembler::notZero, slow);
10578 }
10579
10580 // Load top.
10581 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10582
10583 // Check if the lock-stack is full.
10584 cmpl(top, LockStack::end_offset());
10585 jcc(Assembler::greaterEqual, slow);
10586
10587 // Check for recursion.
10588 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10589 jcc(Assembler::equal, push);
10590
10591 // Check header for monitor (0b10).
10592 testptr(reg_rax, markWord::monitor_value);
10593 jcc(Assembler::notZero, slow);
10594
10595 // Try to lock. Transition lock bits 0b01 => 0b00
10596 movptr(tmp, reg_rax);
10597 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10598 orptr(reg_rax, markWord::unlocked_value);
10599 // Mask inline_type bit such that we go to the slow path if object is an inline type
10600 andptr(reg_rax, ~((int) markWord::inline_type_bit_in_place));
10601
10602 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10603 jcc(Assembler::notEqual, slow);
10604
10605 // Restore top, CAS clobbers register.
10606 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10607
10608 bind(push);
10609 // After successful lock, push object on lock-stack.
10610 movptr(Address(thread, top), obj);
10611 incrementl(top, oopSize);
10612 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10613 }
10614
10615 // Implements fast-unlocking.
10616 //
10617 // obj: the object to be unlocked
10618 // reg_rax: rax
10619 // thread: the thread
10620 // tmp: a temporary register
10621 void MacroAssembler::fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow) {
10622 Register thread = r15_thread;
10623
10624 assert(reg_rax == rax, "");
10625 assert_different_registers(obj, reg_rax, thread, tmp);
10626
10627 Label unlocked, push_and_slow;
10628 const Register top = tmp;
10629
10630 // Check if obj is top of lock-stack.
10631 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10632 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10633 jcc(Assembler::notEqual, slow);
10634
10635 // Pop lock-stack.
10636 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10637 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10638
10639 // Check if recursive.
10640 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10641 jcc(Assembler::equal, unlocked);
10642
10643 // Not recursive. Check header for monitor (0b10).
10644 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10645 testptr(reg_rax, markWord::monitor_value);
10646 jcc(Assembler::notZero, push_and_slow);
10647
10648 #ifdef ASSERT
10649 // Check header not unlocked (0b01).
10650 Label not_unlocked;
10651 testptr(reg_rax, markWord::unlocked_value);
10652 jcc(Assembler::zero, not_unlocked);
10653 stop("fast_unlock already unlocked");
10654 bind(not_unlocked);
10655 #endif
10656
10657 // Try to unlock. Transition lock bits 0b00 => 0b01
10658 movptr(tmp, reg_rax);
10659 orptr(tmp, markWord::unlocked_value);
10660 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10661 jcc(Assembler::equal, unlocked);
10662
10663 bind(push_and_slow);
10664 // Restore lock-stack and handle the unlock in runtime.
10665 #ifdef ASSERT
10666 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10667 movptr(Address(thread, top), obj);
10668 #endif
10669 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10670 jmp(slow);
10671
10672 bind(unlocked);
10673 }
10674
10675 // Saves legacy GPRs state on stack.
10676 void MacroAssembler::save_legacy_gprs() {
10677 subq(rsp, 16 * wordSize);
10678 movq(Address(rsp, 15 * wordSize), rax);
10679 movq(Address(rsp, 14 * wordSize), rcx);
10680 movq(Address(rsp, 13 * wordSize), rdx);
10681 movq(Address(rsp, 12 * wordSize), rbx);
10682 movq(Address(rsp, 10 * wordSize), rbp);
10683 movq(Address(rsp, 9 * wordSize), rsi);
10684 movq(Address(rsp, 8 * wordSize), rdi);
10685 movq(Address(rsp, 7 * wordSize), r8);
10686 movq(Address(rsp, 6 * wordSize), r9);
10687 movq(Address(rsp, 5 * wordSize), r10);
10688 movq(Address(rsp, 4 * wordSize), r11);
10689 movq(Address(rsp, 3 * wordSize), r12);
10690 movq(Address(rsp, 2 * wordSize), r13);
10691 movq(Address(rsp, wordSize), r14);
10692 movq(Address(rsp, 0), r15);
10693 }
10694
10695 // Resotres back legacy GPRs state from stack.
10696 void MacroAssembler::restore_legacy_gprs() {
10697 movq(r15, Address(rsp, 0));
10698 movq(r14, Address(rsp, wordSize));
10699 movq(r13, Address(rsp, 2 * wordSize));
10700 movq(r12, Address(rsp, 3 * wordSize));
10701 movq(r11, Address(rsp, 4 * wordSize));
10702 movq(r10, Address(rsp, 5 * wordSize));
10703 movq(r9, Address(rsp, 6 * wordSize));
10704 movq(r8, Address(rsp, 7 * wordSize));
10705 movq(rdi, Address(rsp, 8 * wordSize));
10706 movq(rsi, Address(rsp, 9 * wordSize));
10707 movq(rbp, Address(rsp, 10 * wordSize));
10708 movq(rbx, Address(rsp, 12 * wordSize));
10709 movq(rdx, Address(rsp, 13 * wordSize));
10710 movq(rcx, Address(rsp, 14 * wordSize));
10711 movq(rax, Address(rsp, 15 * wordSize));
10712 addq(rsp, 16 * wordSize);
10713 }
10714
10715 void MacroAssembler::load_aotrc_address(Register reg, address a) {
10716 #if INCLUDE_CDS
10717 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
10718 if (AOTCodeCache::is_on_for_dump()) {
10719 // all aotrc field addresses should be registered in the AOTCodeCache address table
10720 lea(reg, ExternalAddress(a));
10721 } else {
10722 mov64(reg, (uint64_t)a);
10723 }
10724 #else
10725 ShouldNotReachHere();
10726 #endif
10727 }
10728
10729 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10730 if (VM_Version::supports_apx_f()) {
10731 esetzucc(comparison, dst);
10732 } else {
10733 setb(comparison, dst);
10734 movzbl(dst, dst);
10735 }
10736 }