1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/aotCodeCache.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "crc32c.h"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/barrierSetAssembler.hpp"
34 #include "gc/shared/collectedHeap.inline.hpp"
35 #include "gc/shared/tlab_globals.hpp"
36 #include "interpreter/bytecodeHistogram.hpp"
37 #include "interpreter/interpreter.hpp"
38 #include "interpreter/interpreterRuntime.hpp"
39 #include "jvm.h"
40 #include "memory/resourceArea.hpp"
41 #include "memory/universe.hpp"
42 #include "oops/accessDecorators.hpp"
43 #include "oops/compressedKlass.inline.hpp"
44 #include "oops/compressedOops.inline.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "prims/methodHandles.hpp"
47 #include "runtime/continuation.hpp"
48 #include "runtime/interfaceSupport.inline.hpp"
49 #include "runtime/javaThread.hpp"
50 #include "runtime/jniHandles.hpp"
51 #include "runtime/objectMonitor.hpp"
52 #include "runtime/os.hpp"
53 #include "runtime/safepoint.hpp"
54 #include "runtime/safepointMechanism.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/checkedCast.hpp"
58 #include "utilities/macros.hpp"
59
60 #ifdef PRODUCT
61 #define BLOCK_COMMENT(str) /* nothing */
62 #define STOP(error) stop(error)
63 #else
64 #define BLOCK_COMMENT(str) block_comment(str)
65 #define STOP(error) block_comment(error); stop(error)
66 #endif
67
68 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
69
70 #ifdef ASSERT
71 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
72 #endif
73
74 static const Assembler::Condition reverse[] = {
75 Assembler::noOverflow /* overflow = 0x0 */ ,
76 Assembler::overflow /* noOverflow = 0x1 */ ,
77 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
78 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
79 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
80 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
81 Assembler::above /* belowEqual = 0x6 */ ,
82 Assembler::belowEqual /* above = 0x7 */ ,
83 Assembler::positive /* negative = 0x8 */ ,
84 Assembler::negative /* positive = 0x9 */ ,
85 Assembler::noParity /* parity = 0xa */ ,
86 Assembler::parity /* noParity = 0xb */ ,
87 Assembler::greaterEqual /* less = 0xc */ ,
88 Assembler::less /* greaterEqual = 0xd */ ,
89 Assembler::greater /* lessEqual = 0xe */ ,
90 Assembler::lessEqual /* greater = 0xf, */
91
92 };
93
94
95 // Implementation of MacroAssembler
96
97 Address MacroAssembler::as_Address(AddressLiteral adr) {
98 // amd64 always does this as a pc-rel
99 // we can be absolute or disp based on the instruction type
100 // jmp/call are displacements others are absolute
101 assert(!adr.is_lval(), "must be rval");
102 assert(reachable(adr), "must be");
103 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
104
105 }
106
107 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
108 AddressLiteral base = adr.base();
109 lea(rscratch, base);
110 Address index = adr.index();
111 assert(index._disp == 0, "must not have disp"); // maybe it can?
112 Address array(rscratch, index._index, index._scale, index._disp);
113 return array;
114 }
115
116 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
117 Label L, E;
118
119 #ifdef _WIN64
120 // Windows always allocates space for it's register args
121 assert(num_args <= 4, "only register arguments supported");
122 subq(rsp, frame::arg_reg_save_area_bytes);
123 #endif
124
125 // Align stack if necessary
126 testl(rsp, 15);
127 jcc(Assembler::zero, L);
128
129 subq(rsp, 8);
130 call(RuntimeAddress(entry_point));
131 addq(rsp, 8);
132 jmp(E);
133
134 bind(L);
135 call(RuntimeAddress(entry_point));
136
137 bind(E);
138
139 #ifdef _WIN64
140 // restore stack pointer
141 addq(rsp, frame::arg_reg_save_area_bytes);
142 #endif
143 }
144
145 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
146 assert(!src2.is_lval(), "should use cmpptr");
147 assert(rscratch != noreg || always_reachable(src2), "missing");
148
149 if (reachable(src2)) {
150 cmpq(src1, as_Address(src2));
151 } else {
152 lea(rscratch, src2);
153 Assembler::cmpq(src1, Address(rscratch, 0));
154 }
155 }
156
157 int MacroAssembler::corrected_idivq(Register reg) {
158 // Full implementation of Java ldiv and lrem; checks for special
159 // case as described in JVM spec., p.243 & p.271. The function
160 // returns the (pc) offset of the idivl instruction - may be needed
161 // for implicit exceptions.
162 //
163 // normal case special case
164 //
165 // input : rax: dividend min_long
166 // reg: divisor (may not be eax/edx) -1
167 //
168 // output: rax: quotient (= rax idiv reg) min_long
169 // rdx: remainder (= rax irem reg) 0
170 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
171 static const int64_t min_long = 0x8000000000000000;
172 Label normal_case, special_case;
173
174 // check for special case
175 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
176 jcc(Assembler::notEqual, normal_case);
177 xorl(rdx, rdx); // prepare rdx for possible special case (where
178 // remainder = 0)
179 cmpq(reg, -1);
180 jcc(Assembler::equal, special_case);
181
182 // handle normal case
183 bind(normal_case);
184 cdqq();
185 int idivq_offset = offset();
186 idivq(reg);
187
188 // normal and special case exit
189 bind(special_case);
190
191 return idivq_offset;
192 }
193
194 void MacroAssembler::decrementq(Register reg, int value) {
195 if (value == min_jint) { subq(reg, value); return; }
196 if (value < 0) { incrementq(reg, -value); return; }
197 if (value == 0) { ; return; }
198 if (value == 1 && UseIncDec) { decq(reg) ; return; }
199 /* else */ { subq(reg, value) ; return; }
200 }
201
202 void MacroAssembler::decrementq(Address dst, int value) {
203 if (value == min_jint) { subq(dst, value); return; }
204 if (value < 0) { incrementq(dst, -value); return; }
205 if (value == 0) { ; return; }
206 if (value == 1 && UseIncDec) { decq(dst) ; return; }
207 /* else */ { subq(dst, value) ; return; }
208 }
209
210 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
211 assert(rscratch != noreg || always_reachable(dst), "missing");
212
213 if (reachable(dst)) {
214 incrementq(as_Address(dst));
215 } else {
216 lea(rscratch, dst);
217 incrementq(Address(rscratch, 0));
218 }
219 }
220
221 void MacroAssembler::incrementq(Register reg, int value) {
222 if (value == min_jint) { addq(reg, value); return; }
223 if (value < 0) { decrementq(reg, -value); return; }
224 if (value == 0) { ; return; }
225 if (value == 1 && UseIncDec) { incq(reg) ; return; }
226 /* else */ { addq(reg, value) ; return; }
227 }
228
229 void MacroAssembler::incrementq(Address dst, int value) {
230 if (value == min_jint) { addq(dst, value); return; }
231 if (value < 0) { decrementq(dst, -value); return; }
232 if (value == 0) { ; return; }
233 if (value == 1 && UseIncDec) { incq(dst) ; return; }
234 /* else */ { addq(dst, value) ; return; }
235 }
236
237 // 32bit can do a case table jump in one instruction but we no longer allow the base
238 // to be installed in the Address class
239 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
240 lea(rscratch, entry.base());
241 Address dispatch = entry.index();
242 assert(dispatch._base == noreg, "must be");
243 dispatch._base = rscratch;
244 jmp(dispatch);
245 }
246
247 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
248 ShouldNotReachHere(); // 64bit doesn't use two regs
249 cmpq(x_lo, y_lo);
250 }
251
252 void MacroAssembler::lea(Register dst, AddressLiteral src) {
253 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
254 }
255
256 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
257 lea(rscratch, adr);
258 movptr(dst, rscratch);
259 }
260
261 void MacroAssembler::leave() {
262 // %%% is this really better? Why not on 32bit too?
263 emit_int8((unsigned char)0xC9); // LEAVE
264 }
265
266 void MacroAssembler::lneg(Register hi, Register lo) {
267 ShouldNotReachHere(); // 64bit doesn't use two regs
268 negq(lo);
269 }
270
271 void MacroAssembler::movoop(Register dst, jobject obj) {
272 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
273 }
274
275 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
276 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
277 movq(dst, rscratch);
278 }
279
280 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
281 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
282 }
283
284 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
285 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
286 movq(dst, rscratch);
287 }
288
289 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
290 if (src.is_lval()) {
291 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
292 } else {
293 if (reachable(src)) {
294 movq(dst, as_Address(src));
295 } else {
296 lea(dst, src);
297 movq(dst, Address(dst, 0));
298 }
299 }
300 }
301
302 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
303 movq(as_Address(dst, rscratch), src);
304 }
305
306 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
307 movq(dst, as_Address(src, dst /*rscratch*/));
308 }
309
310 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
311 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
312 if (is_simm32(src)) {
313 movptr(dst, checked_cast<int32_t>(src));
314 } else {
315 mov64(rscratch, src);
316 movq(dst, rscratch);
317 }
318 }
319
320 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
321 movoop(rscratch, obj);
322 push(rscratch);
323 }
324
325 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
326 mov_metadata(rscratch, obj);
327 push(rscratch);
328 }
329
330 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
331 lea(rscratch, src);
332 if (src.is_lval()) {
333 push(rscratch);
334 } else {
335 pushq(Address(rscratch, 0));
336 }
337 }
338
339 static void pass_arg0(MacroAssembler* masm, Register arg) {
340 if (c_rarg0 != arg ) {
341 masm->mov(c_rarg0, arg);
342 }
343 }
344
345 static void pass_arg1(MacroAssembler* masm, Register arg) {
346 if (c_rarg1 != arg ) {
347 masm->mov(c_rarg1, arg);
348 }
349 }
350
351 static void pass_arg2(MacroAssembler* masm, Register arg) {
352 if (c_rarg2 != arg ) {
353 masm->mov(c_rarg2, arg);
354 }
355 }
356
357 static void pass_arg3(MacroAssembler* masm, Register arg) {
358 if (c_rarg3 != arg ) {
359 masm->mov(c_rarg3, arg);
360 }
361 }
362
363 void MacroAssembler::stop(const char* msg) {
364 if (ShowMessageBoxOnError) {
365 address rip = pc();
366 pusha(); // get regs on stack
367 lea(c_rarg1, InternalAddress(rip));
368 movq(c_rarg2, rsp); // pass pointer to regs array
369 }
370 // Skip AOT caching C strings in scratch buffer.
371 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
372 lea(c_rarg0, ExternalAddress((address) str));
373 andq(rsp, -16); // align stack as required by ABI
374 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
375 hlt();
376 }
377
378 void MacroAssembler::warn(const char* msg) {
379 push(rbp);
380 movq(rbp, rsp);
381 andq(rsp, -16); // align stack as required by push_CPU_state and call
382 push_CPU_state(); // keeps alignment at 16 bytes
383
384 #ifdef _WIN64
385 // Windows always allocates space for its register args
386 subq(rsp, frame::arg_reg_save_area_bytes);
387 #endif
388 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
389 lea(c_rarg0, ExternalAddress((address) str));
390 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
391
392 #ifdef _WIN64
393 // restore stack pointer
394 addq(rsp, frame::arg_reg_save_area_bytes);
395 #endif
396 pop_CPU_state();
397 mov(rsp, rbp);
398 pop(rbp);
399 }
400
401 void MacroAssembler::print_state() {
402 address rip = pc();
403 pusha(); // get regs on stack
404 push(rbp);
405 movq(rbp, rsp);
406 andq(rsp, -16); // align stack as required by push_CPU_state and call
407 push_CPU_state(); // keeps alignment at 16 bytes
408
409 lea(c_rarg0, InternalAddress(rip));
410 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
411 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
412
413 pop_CPU_state();
414 mov(rsp, rbp);
415 pop(rbp);
416 popa();
417 }
418
419 #ifndef PRODUCT
420 extern "C" void findpc(intptr_t x);
421 #endif
422
423 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
424 // In order to get locks to work, we need to fake a in_VM state
425 if (ShowMessageBoxOnError) {
426 JavaThread* thread = JavaThread::current();
427 JavaThreadState saved_state = thread->thread_state();
428 thread->set_thread_state(_thread_in_vm);
429 #ifndef PRODUCT
430 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
431 ttyLocker ttyl;
432 BytecodeCounter::print();
433 }
434 #endif
435 // To see where a verify_oop failed, get $ebx+40/X for this frame.
436 // XXX correct this offset for amd64
437 // This is the value of eip which points to where verify_oop will return.
438 if (os::message_box(msg, "Execution stopped, print registers?")) {
439 print_state64(pc, regs);
440 BREAKPOINT;
441 }
442 }
443 fatal("DEBUG MESSAGE: %s", msg);
444 }
445
446 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
447 ttyLocker ttyl;
448 DebuggingContext debugging{};
449 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
450 #ifndef PRODUCT
451 tty->cr();
452 findpc(pc);
453 tty->cr();
454 #endif
455 #define PRINT_REG(rax, value) \
456 { tty->print("%s = ", #rax); os::print_location(tty, value); }
457 PRINT_REG(rax, regs[15]);
458 PRINT_REG(rbx, regs[12]);
459 PRINT_REG(rcx, regs[14]);
460 PRINT_REG(rdx, regs[13]);
461 PRINT_REG(rdi, regs[8]);
462 PRINT_REG(rsi, regs[9]);
463 PRINT_REG(rbp, regs[10]);
464 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
465 PRINT_REG(rsp, (intptr_t)(®s[16]));
466 PRINT_REG(r8 , regs[7]);
467 PRINT_REG(r9 , regs[6]);
468 PRINT_REG(r10, regs[5]);
469 PRINT_REG(r11, regs[4]);
470 PRINT_REG(r12, regs[3]);
471 PRINT_REG(r13, regs[2]);
472 PRINT_REG(r14, regs[1]);
473 PRINT_REG(r15, regs[0]);
474 #undef PRINT_REG
475 // Print some words near the top of the stack.
476 int64_t* rsp = ®s[16];
477 int64_t* dump_sp = rsp;
478 for (int col1 = 0; col1 < 8; col1++) {
479 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
480 os::print_location(tty, *dump_sp++);
481 }
482 for (int row = 0; row < 25; row++) {
483 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
484 for (int col = 0; col < 4; col++) {
485 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
486 }
487 tty->cr();
488 }
489 // Print some instructions around pc:
490 Disassembler::decode((address)pc-64, (address)pc);
491 tty->print_cr("--------");
492 Disassembler::decode((address)pc, (address)pc+32);
493 }
494
495 // The java_calling_convention describes stack locations as ideal slots on
496 // a frame with no abi restrictions. Since we must observe abi restrictions
497 // (like the placement of the register window) the slots must be biased by
498 // the following value.
499 static int reg2offset_in(VMReg r) {
500 // Account for saved rbp and return address
501 // This should really be in_preserve_stack_slots
502 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
503 }
504
505 static int reg2offset_out(VMReg r) {
506 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
507 }
508
509 // A long move
510 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
511
512 // The calling conventions assures us that each VMregpair is either
513 // all really one physical register or adjacent stack slots.
514
515 if (src.is_single_phys_reg() ) {
516 if (dst.is_single_phys_reg()) {
517 if (dst.first() != src.first()) {
518 mov(dst.first()->as_Register(), src.first()->as_Register());
519 }
520 } else {
521 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
522 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
523 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
524 }
525 } else if (dst.is_single_phys_reg()) {
526 assert(src.is_single_reg(), "not a stack pair");
527 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
528 } else {
529 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
530 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
531 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
532 }
533 }
534
535 // A double move
536 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
537
538 // The calling conventions assures us that each VMregpair is either
539 // all really one physical register or adjacent stack slots.
540
541 if (src.is_single_phys_reg() ) {
542 if (dst.is_single_phys_reg()) {
543 // In theory these overlap but the ordering is such that this is likely a nop
544 if ( src.first() != dst.first()) {
545 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
546 }
547 } else {
548 assert(dst.is_single_reg(), "not a stack pair");
549 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
550 }
551 } else if (dst.is_single_phys_reg()) {
552 assert(src.is_single_reg(), "not a stack pair");
553 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
554 } else {
555 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
556 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
557 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
558 }
559 }
560
561
562 // A float arg may have to do float reg int reg conversion
563 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
564 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
565
566 // The calling conventions assures us that each VMregpair is either
567 // all really one physical register or adjacent stack slots.
568
569 if (src.first()->is_stack()) {
570 if (dst.first()->is_stack()) {
571 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
572 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
573 } else {
574 // stack to reg
575 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
576 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
577 }
578 } else if (dst.first()->is_stack()) {
579 // reg to stack
580 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
581 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
582 } else {
583 // reg to reg
584 // In theory these overlap but the ordering is such that this is likely a nop
585 if ( src.first() != dst.first()) {
586 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
587 }
588 }
589 }
590
591 // On 64 bit we will store integer like items to the stack as
592 // 64 bits items (x86_32/64 abi) even though java would only store
593 // 32bits for a parameter. On 32bit it will simply be 32 bits
594 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
595 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
596 if (src.first()->is_stack()) {
597 if (dst.first()->is_stack()) {
598 // stack to stack
599 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
600 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
601 } else {
602 // stack to reg
603 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
604 }
605 } else if (dst.first()->is_stack()) {
606 // reg to stack
607 // Do we really have to sign extend???
608 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
609 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
610 } else {
611 // Do we really have to sign extend???
612 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
613 if (dst.first() != src.first()) {
614 movq(dst.first()->as_Register(), src.first()->as_Register());
615 }
616 }
617 }
618
619 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
620 if (src.first()->is_stack()) {
621 if (dst.first()->is_stack()) {
622 // stack to stack
623 movq(rax, Address(rbp, reg2offset_in(src.first())));
624 movq(Address(rsp, reg2offset_out(dst.first())), rax);
625 } else {
626 // stack to reg
627 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
628 }
629 } else if (dst.first()->is_stack()) {
630 // reg to stack
631 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
632 } else {
633 if (dst.first() != src.first()) {
634 movq(dst.first()->as_Register(), src.first()->as_Register());
635 }
636 }
637 }
638
639 // An oop arg. Must pass a handle not the oop itself
640 void MacroAssembler::object_move(OopMap* map,
641 int oop_handle_offset,
642 int framesize_in_slots,
643 VMRegPair src,
644 VMRegPair dst,
645 bool is_receiver,
646 int* receiver_offset) {
647
648 // must pass a handle. First figure out the location we use as a handle
649
650 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
651
652 // See if oop is null if it is we need no handle
653
654 if (src.first()->is_stack()) {
655
656 // Oop is already on the stack as an argument
657 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
658 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
659 if (is_receiver) {
660 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
661 }
662
663 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
664 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
665 // conditionally move a null
666 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
667 } else {
668
669 // Oop is in a register we must store it to the space we reserve
670 // on the stack for oop_handles and pass a handle if oop is non-null
671
672 const Register rOop = src.first()->as_Register();
673 int oop_slot;
674 if (rOop == j_rarg0)
675 oop_slot = 0;
676 else if (rOop == j_rarg1)
677 oop_slot = 1;
678 else if (rOop == j_rarg2)
679 oop_slot = 2;
680 else if (rOop == j_rarg3)
681 oop_slot = 3;
682 else if (rOop == j_rarg4)
683 oop_slot = 4;
684 else {
685 assert(rOop == j_rarg5, "wrong register");
686 oop_slot = 5;
687 }
688
689 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
690 int offset = oop_slot*VMRegImpl::stack_slot_size;
691
692 map->set_oop(VMRegImpl::stack2reg(oop_slot));
693 // Store oop in handle area, may be null
694 movptr(Address(rsp, offset), rOop);
695 if (is_receiver) {
696 *receiver_offset = offset;
697 }
698
699 cmpptr(rOop, NULL_WORD);
700 lea(rHandle, Address(rsp, offset));
701 // conditionally move a null from the handle area where it was just stored
702 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
703 }
704
705 // If arg is on the stack then place it otherwise it is already in correct reg.
706 if (dst.first()->is_stack()) {
707 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
708 }
709 }
710
711 void MacroAssembler::addptr(Register dst, int32_t imm32) {
712 addq(dst, imm32);
713 }
714
715 void MacroAssembler::addptr(Register dst, Register src) {
716 addq(dst, src);
717 }
718
719 void MacroAssembler::addptr(Address dst, Register src) {
720 addq(dst, src);
721 }
722
723 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
724 assert(rscratch != noreg || always_reachable(src), "missing");
725
726 if (reachable(src)) {
727 Assembler::addsd(dst, as_Address(src));
728 } else {
729 lea(rscratch, src);
730 Assembler::addsd(dst, Address(rscratch, 0));
731 }
732 }
733
734 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
735 assert(rscratch != noreg || always_reachable(src), "missing");
736
737 if (reachable(src)) {
738 addss(dst, as_Address(src));
739 } else {
740 lea(rscratch, src);
741 addss(dst, Address(rscratch, 0));
742 }
743 }
744
745 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
746 assert(rscratch != noreg || always_reachable(src), "missing");
747
748 if (reachable(src)) {
749 Assembler::addpd(dst, as_Address(src));
750 } else {
751 lea(rscratch, src);
752 Assembler::addpd(dst, Address(rscratch, 0));
753 }
754 }
755
756 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
757 // Stub code is generated once and never copied.
758 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
759 void MacroAssembler::align64() {
760 align(64, (uint)(uintptr_t)pc());
761 }
762
763 void MacroAssembler::align32() {
764 align(32, (uint)(uintptr_t)pc());
765 }
766
767 void MacroAssembler::align(uint modulus) {
768 // 8273459: Ensure alignment is possible with current segment alignment
769 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
770 align(modulus, offset());
771 }
772
773 void MacroAssembler::align(uint modulus, uint target) {
774 if (target % modulus != 0) {
775 nop(modulus - (target % modulus));
776 }
777 }
778
779 void MacroAssembler::push_f(XMMRegister r) {
780 subptr(rsp, wordSize);
781 movflt(Address(rsp, 0), r);
782 }
783
784 void MacroAssembler::pop_f(XMMRegister r) {
785 movflt(r, Address(rsp, 0));
786 addptr(rsp, wordSize);
787 }
788
789 void MacroAssembler::push_d(XMMRegister r) {
790 subptr(rsp, 2 * wordSize);
791 movdbl(Address(rsp, 0), r);
792 }
793
794 void MacroAssembler::pop_d(XMMRegister r) {
795 movdbl(r, Address(rsp, 0));
796 addptr(rsp, 2 * Interpreter::stackElementSize);
797 }
798
799 void MacroAssembler::push_ppx(Register src) {
800 if (VM_Version::supports_apx_f()) {
801 pushp(src);
802 } else {
803 Assembler::push(src);
804 }
805 }
806
807 void MacroAssembler::pop_ppx(Register dst) {
808 if (VM_Version::supports_apx_f()) {
809 popp(dst);
810 } else {
811 Assembler::pop(dst);
812 }
813 }
814
815 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
816 // Used in sign-masking with aligned address.
817 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
818 assert(rscratch != noreg || always_reachable(src), "missing");
819
820 if (UseAVX > 2 &&
821 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
822 (dst->encoding() >= 16)) {
823 vpand(dst, dst, src, AVX_512bit, rscratch);
824 } else if (reachable(src)) {
825 Assembler::andpd(dst, as_Address(src));
826 } else {
827 lea(rscratch, src);
828 Assembler::andpd(dst, Address(rscratch, 0));
829 }
830 }
831
832 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
833 // Used in sign-masking with aligned address.
834 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
835 assert(rscratch != noreg || always_reachable(src), "missing");
836
837 if (reachable(src)) {
838 Assembler::andps(dst, as_Address(src));
839 } else {
840 lea(rscratch, src);
841 Assembler::andps(dst, Address(rscratch, 0));
842 }
843 }
844
845 void MacroAssembler::andptr(Register dst, int32_t imm32) {
846 andq(dst, imm32);
847 }
848
849 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
850 assert(rscratch != noreg || always_reachable(src), "missing");
851
852 if (reachable(src)) {
853 andq(dst, as_Address(src));
854 } else {
855 lea(rscratch, src);
856 andq(dst, Address(rscratch, 0));
857 }
858 }
859
860 void MacroAssembler::atomic_incl(Address counter_addr) {
861 lock();
862 incrementl(counter_addr);
863 }
864
865 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
866 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
867
868 if (reachable(counter_addr)) {
869 atomic_incl(as_Address(counter_addr));
870 } else {
871 lea(rscratch, counter_addr);
872 atomic_incl(Address(rscratch, 0));
873 }
874 }
875
876 void MacroAssembler::atomic_incq(Address counter_addr) {
877 lock();
878 incrementq(counter_addr);
879 }
880
881 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
882 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
883
884 if (reachable(counter_addr)) {
885 atomic_incq(as_Address(counter_addr));
886 } else {
887 lea(rscratch, counter_addr);
888 atomic_incq(Address(rscratch, 0));
889 }
890 }
891
892 // Writes to stack successive pages until offset reached to check for
893 // stack overflow + shadow pages. This clobbers tmp.
894 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
895 movptr(tmp, rsp);
896 // Bang stack for total size given plus shadow page size.
897 // Bang one page at a time because large size can bang beyond yellow and
898 // red zones.
899 Label loop;
900 bind(loop);
901 movl(Address(tmp, (-(int)os::vm_page_size())), size );
902 subptr(tmp, (int)os::vm_page_size());
903 subl(size, (int)os::vm_page_size());
904 jcc(Assembler::greater, loop);
905
906 // Bang down shadow pages too.
907 // At this point, (tmp-0) is the last address touched, so don't
908 // touch it again. (It was touched as (tmp-pagesize) but then tmp
909 // was post-decremented.) Skip this address by starting at i=1, and
910 // touch a few more pages below. N.B. It is important to touch all
911 // the way down including all pages in the shadow zone.
912 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
913 // this could be any sized move but this is can be a debugging crumb
914 // so the bigger the better.
915 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
916 }
917 }
918
919 void MacroAssembler::reserved_stack_check() {
920 // testing if reserved zone needs to be enabled
921 Label no_reserved_zone_enabling;
922
923 cmpptr(rsp, Address(r15_thread, JavaThread::reserved_stack_activation_offset()));
924 jcc(Assembler::below, no_reserved_zone_enabling);
925
926 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), r15_thread);
927 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
928 should_not_reach_here();
929
930 bind(no_reserved_zone_enabling);
931 }
932
933 void MacroAssembler::c2bool(Register x) {
934 // implements x == 0 ? 0 : 1
935 // note: must only look at least-significant byte of x
936 // since C-style booleans are stored in one byte
937 // only! (was bug)
938 andl(x, 0xFF);
939 setb(Assembler::notZero, x);
940 }
941
942 // Wouldn't need if AddressLiteral version had new name
943 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
944 Assembler::call(L, rtype);
945 }
946
947 void MacroAssembler::call(Register entry) {
948 Assembler::call(entry);
949 }
950
951 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
952 assert(rscratch != noreg || always_reachable(entry), "missing");
953
954 if (reachable(entry)) {
955 Assembler::call_literal(entry.target(), entry.rspec());
956 } else {
957 lea(rscratch, entry);
958 Assembler::call(rscratch);
959 }
960 }
961
962 void MacroAssembler::ic_call(address entry, jint method_index) {
963 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
964 // Needs full 64-bit immediate for later patching.
965 Assembler::mov64(rax, (int64_t)Universe::non_oop_word());
966 call(AddressLiteral(entry, rh));
967 }
968
969 int MacroAssembler::ic_check_size() {
970 return UseCompactObjectHeaders ? 17 : 14;
971 }
972
973 int MacroAssembler::ic_check(int end_alignment) {
974 Register receiver = j_rarg0;
975 Register data = rax;
976 Register temp = rscratch1;
977
978 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
979 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
980 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
981 // before the inline cache check here, and not after
982 align(end_alignment, offset() + ic_check_size());
983
984 int uep_offset = offset();
985
986 if (UseCompactObjectHeaders) {
987 load_narrow_klass_compact(temp, receiver);
988 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
989 } else {
990 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
991 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
992 }
993
994 // if inline cache check fails, then jump to runtime routine
995 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
996 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
997
998 return uep_offset;
999 }
1000
1001 void MacroAssembler::emit_static_call_stub() {
1002 // Static stub relocation also tags the Method* in the code-stream.
1003 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1004 // This is recognized as unresolved by relocs/nativeinst/ic code.
1005 jump(RuntimeAddress(pc()));
1006 }
1007
1008 // Implementation of call_VM versions
1009
1010 void MacroAssembler::call_VM(Register oop_result,
1011 address entry_point,
1012 bool check_exceptions) {
1013 Label C, E;
1014 call(C, relocInfo::none);
1015 jmp(E);
1016
1017 bind(C);
1018 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1019 ret(0);
1020
1021 bind(E);
1022 }
1023
1024 void MacroAssembler::call_VM(Register oop_result,
1025 address entry_point,
1026 Register arg_1,
1027 bool check_exceptions) {
1028 Label C, E;
1029 call(C, relocInfo::none);
1030 jmp(E);
1031
1032 bind(C);
1033 pass_arg1(this, arg_1);
1034 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1035 ret(0);
1036
1037 bind(E);
1038 }
1039
1040 void MacroAssembler::call_VM(Register oop_result,
1041 address entry_point,
1042 Register arg_1,
1043 Register arg_2,
1044 bool check_exceptions) {
1045 Label C, E;
1046 call(C, relocInfo::none);
1047 jmp(E);
1048
1049 bind(C);
1050
1051 assert_different_registers(arg_1, c_rarg2);
1052
1053 pass_arg2(this, arg_2);
1054 pass_arg1(this, arg_1);
1055 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1056 ret(0);
1057
1058 bind(E);
1059 }
1060
1061 void MacroAssembler::call_VM(Register oop_result,
1062 address entry_point,
1063 Register arg_1,
1064 Register arg_2,
1065 Register arg_3,
1066 bool check_exceptions) {
1067 Label C, E;
1068 call(C, relocInfo::none);
1069 jmp(E);
1070
1071 bind(C);
1072
1073 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1074 assert_different_registers(arg_2, c_rarg3);
1075 pass_arg3(this, arg_3);
1076 pass_arg2(this, arg_2);
1077 pass_arg1(this, arg_1);
1078 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1079 ret(0);
1080
1081 bind(E);
1082 }
1083
1084 void MacroAssembler::call_VM(Register oop_result,
1085 Register last_java_sp,
1086 address entry_point,
1087 int number_of_arguments,
1088 bool check_exceptions) {
1089 call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1090 }
1091
1092 void MacroAssembler::call_VM(Register oop_result,
1093 Register last_java_sp,
1094 address entry_point,
1095 Register arg_1,
1096 bool check_exceptions) {
1097 pass_arg1(this, arg_1);
1098 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1099 }
1100
1101 void MacroAssembler::call_VM(Register oop_result,
1102 Register last_java_sp,
1103 address entry_point,
1104 Register arg_1,
1105 Register arg_2,
1106 bool check_exceptions) {
1107
1108 assert_different_registers(arg_1, c_rarg2);
1109 pass_arg2(this, arg_2);
1110 pass_arg1(this, arg_1);
1111 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1112 }
1113
1114 void MacroAssembler::call_VM(Register oop_result,
1115 Register last_java_sp,
1116 address entry_point,
1117 Register arg_1,
1118 Register arg_2,
1119 Register arg_3,
1120 bool check_exceptions) {
1121 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1122 assert_different_registers(arg_2, c_rarg3);
1123 pass_arg3(this, arg_3);
1124 pass_arg2(this, arg_2);
1125 pass_arg1(this, arg_1);
1126 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1127 }
1128
1129 void MacroAssembler::super_call_VM(Register oop_result,
1130 Register last_java_sp,
1131 address entry_point,
1132 int number_of_arguments,
1133 bool check_exceptions) {
1134 MacroAssembler::call_VM_base(oop_result, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1135 }
1136
1137 void MacroAssembler::super_call_VM(Register oop_result,
1138 Register last_java_sp,
1139 address entry_point,
1140 Register arg_1,
1141 bool check_exceptions) {
1142 pass_arg1(this, arg_1);
1143 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1144 }
1145
1146 void MacroAssembler::super_call_VM(Register oop_result,
1147 Register last_java_sp,
1148 address entry_point,
1149 Register arg_1,
1150 Register arg_2,
1151 bool check_exceptions) {
1152
1153 assert_different_registers(arg_1, c_rarg2);
1154 pass_arg2(this, arg_2);
1155 pass_arg1(this, arg_1);
1156 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1157 }
1158
1159 void MacroAssembler::super_call_VM(Register oop_result,
1160 Register last_java_sp,
1161 address entry_point,
1162 Register arg_1,
1163 Register arg_2,
1164 Register arg_3,
1165 bool check_exceptions) {
1166 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1167 assert_different_registers(arg_2, c_rarg3);
1168 pass_arg3(this, arg_3);
1169 pass_arg2(this, arg_2);
1170 pass_arg1(this, arg_1);
1171 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1172 }
1173
1174 void MacroAssembler::call_VM_base(Register oop_result,
1175 Register last_java_sp,
1176 address entry_point,
1177 int number_of_arguments,
1178 bool check_exceptions) {
1179 Register java_thread = r15_thread;
1180
1181 // determine last_java_sp register
1182 if (!last_java_sp->is_valid()) {
1183 last_java_sp = rsp;
1184 }
1185 // debugging support
1186 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1187 #ifdef ASSERT
1188 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1189 // r12 is the heapbase.
1190 if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
1191 #endif // ASSERT
1192
1193 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1194 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1195
1196 // push java thread (becomes first argument of C function)
1197
1198 mov(c_rarg0, r15_thread);
1199
1200 // set last Java frame before call
1201 assert(last_java_sp != rbp, "can't use ebp/rbp");
1202
1203 // Only interpreter should have to set fp
1204 set_last_Java_frame(last_java_sp, rbp, nullptr, rscratch1);
1205
1206 // do the call, remove parameters
1207 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1208
1209 #ifdef ASSERT
1210 // Check that thread register is not clobbered.
1211 guarantee(java_thread != rax, "change this code");
1212 push(rax);
1213 { Label L;
1214 get_thread_slow(rax);
1215 cmpptr(java_thread, rax);
1216 jcc(Assembler::equal, L);
1217 STOP("MacroAssembler::call_VM_base: java_thread not callee saved?");
1218 bind(L);
1219 }
1220 pop(rax);
1221 #endif
1222
1223 // reset last Java frame
1224 // Only interpreter should have to clear fp
1225 reset_last_Java_frame(true);
1226
1227 // C++ interp handles this in the interpreter
1228 check_and_handle_popframe();
1229 check_and_handle_earlyret();
1230
1231 if (check_exceptions) {
1232 // check for pending exceptions (java_thread is set upon return)
1233 cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
1234 // This used to conditionally jump to forward_exception however it is
1235 // possible if we relocate that the branch will not reach. So we must jump
1236 // around so we can always reach
1237
1238 Label ok;
1239 jcc(Assembler::equal, ok);
1240 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1241 bind(ok);
1242 }
1243
1244 // get oop result if there is one and reset the value in the thread
1245 if (oop_result->is_valid()) {
1246 get_vm_result_oop(oop_result);
1247 }
1248 }
1249
1250 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1251 // Calculate the value for last_Java_sp somewhat subtle.
1252 // call_VM does an intermediate call which places a return address on
1253 // the stack just under the stack pointer as the user finished with it.
1254 // This allows use to retrieve last_Java_pc from last_Java_sp[-1].
1255
1256 // We've pushed one address, correct last_Java_sp
1257 lea(rax, Address(rsp, wordSize));
1258
1259 call_VM_base(oop_result, rax, entry_point, number_of_arguments, check_exceptions);
1260 }
1261
1262 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1263 void MacroAssembler::call_VM_leaf0(address entry_point) {
1264 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1265 }
1266
1267 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1268 call_VM_leaf_base(entry_point, number_of_arguments);
1269 }
1270
1271 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1272 pass_arg0(this, arg_0);
1273 call_VM_leaf(entry_point, 1);
1274 }
1275
1276 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1277
1278 assert_different_registers(arg_0, c_rarg1);
1279 pass_arg1(this, arg_1);
1280 pass_arg0(this, arg_0);
1281 call_VM_leaf(entry_point, 2);
1282 }
1283
1284 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1285 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1286 assert_different_registers(arg_1, c_rarg2);
1287 pass_arg2(this, arg_2);
1288 pass_arg1(this, arg_1);
1289 pass_arg0(this, arg_0);
1290 call_VM_leaf(entry_point, 3);
1291 }
1292
1293 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1294 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1295 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1296 assert_different_registers(arg_2, c_rarg3);
1297 pass_arg3(this, arg_3);
1298 pass_arg2(this, arg_2);
1299 pass_arg1(this, arg_1);
1300 pass_arg0(this, arg_0);
1301 call_VM_leaf(entry_point, 3);
1302 }
1303
1304 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1305 pass_arg0(this, arg_0);
1306 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1307 }
1308
1309 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1310 assert_different_registers(arg_0, c_rarg1);
1311 pass_arg1(this, arg_1);
1312 pass_arg0(this, arg_0);
1313 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1314 }
1315
1316 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1317 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1318 assert_different_registers(arg_1, c_rarg2);
1319 pass_arg2(this, arg_2);
1320 pass_arg1(this, arg_1);
1321 pass_arg0(this, arg_0);
1322 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1323 }
1324
1325 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1326 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
1327 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1328 assert_different_registers(arg_2, c_rarg3);
1329 pass_arg3(this, arg_3);
1330 pass_arg2(this, arg_2);
1331 pass_arg1(this, arg_1);
1332 pass_arg0(this, arg_0);
1333 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1334 }
1335
1336 void MacroAssembler::get_vm_result_oop(Register oop_result) {
1337 movptr(oop_result, Address(r15_thread, JavaThread::vm_result_oop_offset()));
1338 movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
1339 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1340 }
1341
1342 void MacroAssembler::get_vm_result_metadata(Register metadata_result) {
1343 movptr(metadata_result, Address(r15_thread, JavaThread::vm_result_metadata_offset()));
1344 movptr(Address(r15_thread, JavaThread::vm_result_metadata_offset()), NULL_WORD);
1345 }
1346
1347 void MacroAssembler::check_and_handle_earlyret() {
1348 }
1349
1350 void MacroAssembler::check_and_handle_popframe() {
1351 }
1352
1353 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1354 assert(rscratch != noreg || always_reachable(src1), "missing");
1355
1356 if (reachable(src1)) {
1357 cmpl(as_Address(src1), imm);
1358 } else {
1359 lea(rscratch, src1);
1360 cmpl(Address(rscratch, 0), imm);
1361 }
1362 }
1363
1364 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1365 assert(!src2.is_lval(), "use cmpptr");
1366 assert(rscratch != noreg || always_reachable(src2), "missing");
1367
1368 if (reachable(src2)) {
1369 cmpl(src1, as_Address(src2));
1370 } else {
1371 lea(rscratch, src2);
1372 cmpl(src1, Address(rscratch, 0));
1373 }
1374 }
1375
1376 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1377 Assembler::cmpl(src1, imm);
1378 }
1379
1380 void MacroAssembler::cmp32(Register src1, Address src2) {
1381 Assembler::cmpl(src1, src2);
1382 }
1383
1384 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1385 ucomisd(opr1, opr2);
1386
1387 Label L;
1388 if (unordered_is_less) {
1389 movl(dst, -1);
1390 jcc(Assembler::parity, L);
1391 jcc(Assembler::below , L);
1392 movl(dst, 0);
1393 jcc(Assembler::equal , L);
1394 increment(dst);
1395 } else { // unordered is greater
1396 movl(dst, 1);
1397 jcc(Assembler::parity, L);
1398 jcc(Assembler::above , L);
1399 movl(dst, 0);
1400 jcc(Assembler::equal , L);
1401 decrementl(dst);
1402 }
1403 bind(L);
1404 }
1405
1406 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1407 ucomiss(opr1, opr2);
1408
1409 Label L;
1410 if (unordered_is_less) {
1411 movl(dst, -1);
1412 jcc(Assembler::parity, L);
1413 jcc(Assembler::below , L);
1414 movl(dst, 0);
1415 jcc(Assembler::equal , L);
1416 increment(dst);
1417 } else { // unordered is greater
1418 movl(dst, 1);
1419 jcc(Assembler::parity, L);
1420 jcc(Assembler::above , L);
1421 movl(dst, 0);
1422 jcc(Assembler::equal , L);
1423 decrementl(dst);
1424 }
1425 bind(L);
1426 }
1427
1428
1429 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1430 assert(rscratch != noreg || always_reachable(src1), "missing");
1431
1432 if (reachable(src1)) {
1433 cmpb(as_Address(src1), imm);
1434 } else {
1435 lea(rscratch, src1);
1436 cmpb(Address(rscratch, 0), imm);
1437 }
1438 }
1439
1440 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1441 assert(rscratch != noreg || always_reachable(src2), "missing");
1442
1443 if (src2.is_lval()) {
1444 movptr(rscratch, src2);
1445 Assembler::cmpq(src1, rscratch);
1446 } else if (reachable(src2)) {
1447 cmpq(src1, as_Address(src2));
1448 } else {
1449 lea(rscratch, src2);
1450 Assembler::cmpq(src1, Address(rscratch, 0));
1451 }
1452 }
1453
1454 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1455 assert(src2.is_lval(), "not a mem-mem compare");
1456 // moves src2's literal address
1457 movptr(rscratch, src2);
1458 Assembler::cmpq(src1, rscratch);
1459 }
1460
1461 void MacroAssembler::cmpoop(Register src1, Register src2) {
1462 cmpptr(src1, src2);
1463 }
1464
1465 void MacroAssembler::cmpoop(Register src1, Address src2) {
1466 cmpptr(src1, src2);
1467 }
1468
1469 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1470 movoop(rscratch, src2);
1471 cmpptr(src1, rscratch);
1472 }
1473
1474 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1475 assert(rscratch != noreg || always_reachable(adr), "missing");
1476
1477 if (reachable(adr)) {
1478 lock();
1479 cmpxchgptr(reg, as_Address(adr));
1480 } else {
1481 lea(rscratch, adr);
1482 lock();
1483 cmpxchgptr(reg, Address(rscratch, 0));
1484 }
1485 }
1486
1487 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1488 cmpxchgq(reg, adr);
1489 }
1490
1491 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1492 assert(rscratch != noreg || always_reachable(src), "missing");
1493
1494 if (reachable(src)) {
1495 Assembler::comisd(dst, as_Address(src));
1496 } else {
1497 lea(rscratch, src);
1498 Assembler::comisd(dst, Address(rscratch, 0));
1499 }
1500 }
1501
1502 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1503 assert(rscratch != noreg || always_reachable(src), "missing");
1504
1505 if (reachable(src)) {
1506 Assembler::comiss(dst, as_Address(src));
1507 } else {
1508 lea(rscratch, src);
1509 Assembler::comiss(dst, Address(rscratch, 0));
1510 }
1511 }
1512
1513
1514 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1515 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1516
1517 Condition negated_cond = negate_condition(cond);
1518 Label L;
1519 jcc(negated_cond, L);
1520 pushf(); // Preserve flags
1521 atomic_incl(counter_addr, rscratch);
1522 popf();
1523 bind(L);
1524 }
1525
1526 int MacroAssembler::corrected_idivl(Register reg) {
1527 // Full implementation of Java idiv and irem; checks for
1528 // special case as described in JVM spec., p.243 & p.271.
1529 // The function returns the (pc) offset of the idivl
1530 // instruction - may be needed for implicit exceptions.
1531 //
1532 // normal case special case
1533 //
1534 // input : rax,: dividend min_int
1535 // reg: divisor (may not be rax,/rdx) -1
1536 //
1537 // output: rax,: quotient (= rax, idiv reg) min_int
1538 // rdx: remainder (= rax, irem reg) 0
1539 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1540 const int min_int = 0x80000000;
1541 Label normal_case, special_case;
1542
1543 // check for special case
1544 cmpl(rax, min_int);
1545 jcc(Assembler::notEqual, normal_case);
1546 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1547 cmpl(reg, -1);
1548 jcc(Assembler::equal, special_case);
1549
1550 // handle normal case
1551 bind(normal_case);
1552 cdql();
1553 int idivl_offset = offset();
1554 idivl(reg);
1555
1556 // normal and special case exit
1557 bind(special_case);
1558
1559 return idivl_offset;
1560 }
1561
1562
1563
1564 void MacroAssembler::decrementl(Register reg, int value) {
1565 if (value == min_jint) {subl(reg, value) ; return; }
1566 if (value < 0) { incrementl(reg, -value); return; }
1567 if (value == 0) { ; return; }
1568 if (value == 1 && UseIncDec) { decl(reg) ; return; }
1569 /* else */ { subl(reg, value) ; return; }
1570 }
1571
1572 void MacroAssembler::decrementl(Address dst, int value) {
1573 if (value == min_jint) {subl(dst, value) ; return; }
1574 if (value < 0) { incrementl(dst, -value); return; }
1575 if (value == 0) { ; return; }
1576 if (value == 1 && UseIncDec) { decl(dst) ; return; }
1577 /* else */ { subl(dst, value) ; return; }
1578 }
1579
1580 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1581 assert(shift_value > 0, "illegal shift value");
1582 Label _is_positive;
1583 testl (reg, reg);
1584 jcc (Assembler::positive, _is_positive);
1585 int offset = (1 << shift_value) - 1 ;
1586
1587 if (offset == 1) {
1588 incrementl(reg);
1589 } else {
1590 addl(reg, offset);
1591 }
1592
1593 bind (_is_positive);
1594 sarl(reg, shift_value);
1595 }
1596
1597 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1598 assert(rscratch != noreg || always_reachable(src), "missing");
1599
1600 if (reachable(src)) {
1601 Assembler::divsd(dst, as_Address(src));
1602 } else {
1603 lea(rscratch, src);
1604 Assembler::divsd(dst, Address(rscratch, 0));
1605 }
1606 }
1607
1608 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1609 assert(rscratch != noreg || always_reachable(src), "missing");
1610
1611 if (reachable(src)) {
1612 Assembler::divss(dst, as_Address(src));
1613 } else {
1614 lea(rscratch, src);
1615 Assembler::divss(dst, Address(rscratch, 0));
1616 }
1617 }
1618
1619 void MacroAssembler::enter() {
1620 push(rbp);
1621 mov(rbp, rsp);
1622 }
1623
1624 void MacroAssembler::post_call_nop() {
1625 if (!Continuations::enabled()) {
1626 return;
1627 }
1628 InstructionMark im(this);
1629 relocate(post_call_nop_Relocation::spec());
1630 InlineSkippedInstructionsCounter skipCounter(this);
1631 emit_int8((uint8_t)0x0f);
1632 emit_int8((uint8_t)0x1f);
1633 emit_int8((uint8_t)0x84);
1634 emit_int8((uint8_t)0x00);
1635 emit_int32(0x00);
1636 }
1637
1638 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1639 assert(rscratch != noreg || always_reachable(src), "missing");
1640 if (reachable(src)) {
1641 Assembler::mulpd(dst, as_Address(src));
1642 } else {
1643 lea(rscratch, src);
1644 Assembler::mulpd(dst, Address(rscratch, 0));
1645 }
1646 }
1647
1648 // dst = c = a * b + c
1649 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1650 Assembler::vfmadd231sd(c, a, b);
1651 if (dst != c) {
1652 movdbl(dst, c);
1653 }
1654 }
1655
1656 // dst = c = a * b + c
1657 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
1658 Assembler::vfmadd231ss(c, a, b);
1659 if (dst != c) {
1660 movflt(dst, c);
1661 }
1662 }
1663
1664 // dst = c = a * b + c
1665 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1666 Assembler::vfmadd231pd(c, a, b, vector_len);
1667 if (dst != c) {
1668 vmovdqu(dst, c);
1669 }
1670 }
1671
1672 // dst = c = a * b + c
1673 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
1674 Assembler::vfmadd231ps(c, a, b, vector_len);
1675 if (dst != c) {
1676 vmovdqu(dst, c);
1677 }
1678 }
1679
1680 // dst = c = a * b + c
1681 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1682 Assembler::vfmadd231pd(c, a, b, vector_len);
1683 if (dst != c) {
1684 vmovdqu(dst, c);
1685 }
1686 }
1687
1688 // dst = c = a * b + c
1689 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
1690 Assembler::vfmadd231ps(c, a, b, vector_len);
1691 if (dst != c) {
1692 vmovdqu(dst, c);
1693 }
1694 }
1695
1696 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
1697 assert(rscratch != noreg || always_reachable(dst), "missing");
1698
1699 if (reachable(dst)) {
1700 incrementl(as_Address(dst));
1701 } else {
1702 lea(rscratch, dst);
1703 incrementl(Address(rscratch, 0));
1704 }
1705 }
1706
1707 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
1708 incrementl(as_Address(dst, rscratch));
1709 }
1710
1711 void MacroAssembler::incrementl(Register reg, int value) {
1712 if (value == min_jint) {addl(reg, value) ; return; }
1713 if (value < 0) { decrementl(reg, -value); return; }
1714 if (value == 0) { ; return; }
1715 if (value == 1 && UseIncDec) { incl(reg) ; return; }
1716 /* else */ { addl(reg, value) ; return; }
1717 }
1718
1719 void MacroAssembler::incrementl(Address dst, int value) {
1720 if (value == min_jint) {addl(dst, value) ; return; }
1721 if (value < 0) { decrementl(dst, -value); return; }
1722 if (value == 0) { ; return; }
1723 if (value == 1 && UseIncDec) { incl(dst) ; return; }
1724 /* else */ { addl(dst, value) ; return; }
1725 }
1726
1727 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
1728 assert(rscratch != noreg || always_reachable(dst), "missing");
1729 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
1730 if (reachable(dst)) {
1731 jmp_literal(dst.target(), dst.rspec());
1732 } else {
1733 lea(rscratch, dst);
1734 jmp(rscratch);
1735 }
1736 }
1737
1738 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
1739 assert(rscratch != noreg || always_reachable(dst), "missing");
1740 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
1741 if (reachable(dst)) {
1742 InstructionMark im(this);
1743 relocate(dst.reloc());
1744 const int short_size = 2;
1745 const int long_size = 6;
1746 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
1747 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
1748 // 0111 tttn #8-bit disp
1749 emit_int8(0x70 | cc);
1750 emit_int8((offs - short_size) & 0xFF);
1751 } else {
1752 // 0000 1111 1000 tttn #32-bit disp
1753 emit_int8(0x0F);
1754 emit_int8((unsigned char)(0x80 | cc));
1755 emit_int32(offs - long_size);
1756 }
1757 } else {
1758 #ifdef ASSERT
1759 warning("reversing conditional branch");
1760 #endif /* ASSERT */
1761 Label skip;
1762 jccb(reverse[cc], skip);
1763 lea(rscratch, dst);
1764 Assembler::jmp(rscratch);
1765 bind(skip);
1766 }
1767 }
1768
1769 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
1770 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
1771 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
1772
1773 stmxcsr(mxcsr_save);
1774 movl(tmp, mxcsr_save);
1775 if (EnableX86ECoreOpts) {
1776 // The mxcsr_std has status bits set for performance on ECore
1777 orl(tmp, 0x003f);
1778 } else {
1779 // Mask out status bits (only check control and mask bits)
1780 andl(tmp, 0xFFC0);
1781 }
1782 cmp32(tmp, mxcsr_std, rscratch);
1783 }
1784
1785 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
1786 assert(rscratch != noreg || always_reachable(src), "missing");
1787
1788 if (reachable(src)) {
1789 Assembler::ldmxcsr(as_Address(src));
1790 } else {
1791 lea(rscratch, src);
1792 Assembler::ldmxcsr(Address(rscratch, 0));
1793 }
1794 }
1795
1796 int MacroAssembler::load_signed_byte(Register dst, Address src) {
1797 int off = offset();
1798 movsbl(dst, src); // movsxb
1799 return off;
1800 }
1801
1802 // Note: load_signed_short used to be called load_signed_word.
1803 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
1804 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
1805 // The term "word" in HotSpot means a 32- or 64-bit machine word.
1806 int MacroAssembler::load_signed_short(Register dst, Address src) {
1807 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
1808 // version but this is what 64bit has always done. This seems to imply
1809 // that users are only using 32bits worth.
1810 int off = offset();
1811 movswl(dst, src); // movsxw
1812 return off;
1813 }
1814
1815 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
1816 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1817 // and "3.9 Partial Register Penalties", p. 22).
1818 int off = offset();
1819 movzbl(dst, src); // movzxb
1820 return off;
1821 }
1822
1823 // Note: load_unsigned_short used to be called load_unsigned_word.
1824 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
1825 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
1826 // and "3.9 Partial Register Penalties", p. 22).
1827 int off = offset();
1828 movzwl(dst, src); // movzxw
1829 return off;
1830 }
1831
1832 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
1833 switch (size_in_bytes) {
1834 case 8: movq(dst, src); break;
1835 case 4: movl(dst, src); break;
1836 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
1837 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
1838 default: ShouldNotReachHere();
1839 }
1840 }
1841
1842 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
1843 switch (size_in_bytes) {
1844 case 8: movq(dst, src); break;
1845 case 4: movl(dst, src); break;
1846 case 2: movw(dst, src); break;
1847 case 1: movb(dst, src); break;
1848 default: ShouldNotReachHere();
1849 }
1850 }
1851
1852 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
1853 assert(rscratch != noreg || always_reachable(dst), "missing");
1854
1855 if (reachable(dst)) {
1856 movl(as_Address(dst), src);
1857 } else {
1858 lea(rscratch, dst);
1859 movl(Address(rscratch, 0), src);
1860 }
1861 }
1862
1863 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
1864 if (reachable(src)) {
1865 movl(dst, as_Address(src));
1866 } else {
1867 lea(dst, src);
1868 movl(dst, Address(dst, 0));
1869 }
1870 }
1871
1872 // C++ bool manipulation
1873
1874 void MacroAssembler::movbool(Register dst, Address src) {
1875 if(sizeof(bool) == 1)
1876 movb(dst, src);
1877 else if(sizeof(bool) == 2)
1878 movw(dst, src);
1879 else if(sizeof(bool) == 4)
1880 movl(dst, src);
1881 else
1882 // unsupported
1883 ShouldNotReachHere();
1884 }
1885
1886 void MacroAssembler::movbool(Address dst, bool boolconst) {
1887 if(sizeof(bool) == 1)
1888 movb(dst, (int) boolconst);
1889 else if(sizeof(bool) == 2)
1890 movw(dst, (int) boolconst);
1891 else if(sizeof(bool) == 4)
1892 movl(dst, (int) boolconst);
1893 else
1894 // unsupported
1895 ShouldNotReachHere();
1896 }
1897
1898 void MacroAssembler::movbool(Address dst, Register src) {
1899 if(sizeof(bool) == 1)
1900 movb(dst, src);
1901 else if(sizeof(bool) == 2)
1902 movw(dst, src);
1903 else if(sizeof(bool) == 4)
1904 movl(dst, src);
1905 else
1906 // unsupported
1907 ShouldNotReachHere();
1908 }
1909
1910 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1911 assert(rscratch != noreg || always_reachable(src), "missing");
1912
1913 if (reachable(src)) {
1914 movdl(dst, as_Address(src));
1915 } else {
1916 lea(rscratch, src);
1917 movdl(dst, Address(rscratch, 0));
1918 }
1919 }
1920
1921 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
1922 assert(rscratch != noreg || always_reachable(src), "missing");
1923
1924 if (reachable(src)) {
1925 movq(dst, as_Address(src));
1926 } else {
1927 lea(rscratch, src);
1928 movq(dst, Address(rscratch, 0));
1929 }
1930 }
1931
1932 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
1933 assert(rscratch != noreg || always_reachable(src), "missing");
1934
1935 if (reachable(src)) {
1936 if (UseXmmLoadAndClearUpper) {
1937 movsd (dst, as_Address(src));
1938 } else {
1939 movlpd(dst, as_Address(src));
1940 }
1941 } else {
1942 lea(rscratch, src);
1943 if (UseXmmLoadAndClearUpper) {
1944 movsd (dst, Address(rscratch, 0));
1945 } else {
1946 movlpd(dst, Address(rscratch, 0));
1947 }
1948 }
1949 }
1950
1951 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
1952 assert(rscratch != noreg || always_reachable(src), "missing");
1953
1954 if (reachable(src)) {
1955 movss(dst, as_Address(src));
1956 } else {
1957 lea(rscratch, src);
1958 movss(dst, Address(rscratch, 0));
1959 }
1960 }
1961
1962 void MacroAssembler::movhlf(XMMRegister dst, XMMRegister src, Register rscratch) {
1963 if (VM_Version::supports_avx10_2()) {
1964 evmovw(dst, src);
1965 } else {
1966 assert(rscratch != noreg, "missing");
1967 evmovw(rscratch, src);
1968 evmovw(dst, rscratch);
1969 }
1970 }
1971
1972 void MacroAssembler::mov64(Register dst, int64_t imm64) {
1973 if (is_uimm32(imm64)) {
1974 movl(dst, checked_cast<uint32_t>(imm64));
1975 } else if (is_simm32(imm64)) {
1976 movq(dst, checked_cast<int32_t>(imm64));
1977 } else {
1978 Assembler::mov64(dst, imm64);
1979 }
1980 }
1981
1982 void MacroAssembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) {
1983 Assembler::mov64(dst, imm64, rtype, format);
1984 }
1985
1986 void MacroAssembler::movptr(Register dst, Register src) {
1987 movq(dst, src);
1988 }
1989
1990 void MacroAssembler::movptr(Register dst, Address src) {
1991 movq(dst, src);
1992 }
1993
1994 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
1995 void MacroAssembler::movptr(Register dst, intptr_t src) {
1996 mov64(dst, src);
1997 }
1998
1999 void MacroAssembler::movptr(Address dst, Register src) {
2000 movq(dst, src);
2001 }
2002
2003 void MacroAssembler::movptr(Address dst, int32_t src) {
2004 movslq(dst, src);
2005 }
2006
2007 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2008 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2009 Assembler::movdqu(dst, src);
2010 }
2011
2012 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2013 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2014 Assembler::movdqu(dst, src);
2015 }
2016
2017 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2018 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2019 Assembler::movdqu(dst, src);
2020 }
2021
2022 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2023 assert(rscratch != noreg || always_reachable(src), "missing");
2024
2025 if (reachable(src)) {
2026 movdqu(dst, as_Address(src));
2027 } else {
2028 lea(rscratch, src);
2029 movdqu(dst, Address(rscratch, 0));
2030 }
2031 }
2032
2033 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2034 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2035 Assembler::vmovdqu(dst, src);
2036 }
2037
2038 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2039 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2040 Assembler::vmovdqu(dst, src);
2041 }
2042
2043 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2044 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2045 Assembler::vmovdqu(dst, src);
2046 }
2047
2048 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2049 assert(rscratch != noreg || always_reachable(src), "missing");
2050
2051 if (reachable(src)) {
2052 vmovdqu(dst, as_Address(src));
2053 }
2054 else {
2055 lea(rscratch, src);
2056 vmovdqu(dst, Address(rscratch, 0));
2057 }
2058 }
2059
2060 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2061 assert(rscratch != noreg || always_reachable(src), "missing");
2062
2063 if (vector_len == AVX_512bit) {
2064 evmovdquq(dst, src, AVX_512bit, rscratch);
2065 } else if (vector_len == AVX_256bit) {
2066 vmovdqu(dst, src, rscratch);
2067 } else {
2068 movdqu(dst, src, rscratch);
2069 }
2070 }
2071
2072 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2073 if (vector_len == AVX_512bit) {
2074 evmovdquq(dst, src, AVX_512bit);
2075 } else if (vector_len == AVX_256bit) {
2076 vmovdqu(dst, src);
2077 } else {
2078 movdqu(dst, src);
2079 }
2080 }
2081
2082 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2083 if (vector_len == AVX_512bit) {
2084 evmovdquq(dst, src, AVX_512bit);
2085 } else if (vector_len == AVX_256bit) {
2086 vmovdqu(dst, src);
2087 } else {
2088 movdqu(dst, src);
2089 }
2090 }
2091
2092 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2093 if (vector_len == AVX_512bit) {
2094 evmovdquq(dst, src, AVX_512bit);
2095 } else if (vector_len == AVX_256bit) {
2096 vmovdqu(dst, src);
2097 } else {
2098 movdqu(dst, src);
2099 }
2100 }
2101
2102 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2103 assert(rscratch != noreg || always_reachable(src), "missing");
2104
2105 if (reachable(src)) {
2106 vmovdqa(dst, as_Address(src));
2107 }
2108 else {
2109 lea(rscratch, src);
2110 vmovdqa(dst, Address(rscratch, 0));
2111 }
2112 }
2113
2114 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2115 assert(rscratch != noreg || always_reachable(src), "missing");
2116
2117 if (vector_len == AVX_512bit) {
2118 evmovdqaq(dst, src, AVX_512bit, rscratch);
2119 } else if (vector_len == AVX_256bit) {
2120 vmovdqa(dst, src, rscratch);
2121 } else {
2122 movdqa(dst, src, rscratch);
2123 }
2124 }
2125
2126 void MacroAssembler::kmov(KRegister dst, Address src) {
2127 if (VM_Version::supports_avx512bw()) {
2128 kmovql(dst, src);
2129 } else {
2130 assert(VM_Version::supports_evex(), "");
2131 kmovwl(dst, src);
2132 }
2133 }
2134
2135 void MacroAssembler::kmov(Address dst, KRegister src) {
2136 if (VM_Version::supports_avx512bw()) {
2137 kmovql(dst, src);
2138 } else {
2139 assert(VM_Version::supports_evex(), "");
2140 kmovwl(dst, src);
2141 }
2142 }
2143
2144 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2145 if (VM_Version::supports_avx512bw()) {
2146 kmovql(dst, src);
2147 } else {
2148 assert(VM_Version::supports_evex(), "");
2149 kmovwl(dst, src);
2150 }
2151 }
2152
2153 void MacroAssembler::kmov(Register dst, KRegister src) {
2154 if (VM_Version::supports_avx512bw()) {
2155 kmovql(dst, src);
2156 } else {
2157 assert(VM_Version::supports_evex(), "");
2158 kmovwl(dst, src);
2159 }
2160 }
2161
2162 void MacroAssembler::kmov(KRegister dst, Register src) {
2163 if (VM_Version::supports_avx512bw()) {
2164 kmovql(dst, src);
2165 } else {
2166 assert(VM_Version::supports_evex(), "");
2167 kmovwl(dst, src);
2168 }
2169 }
2170
2171 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2172 assert(rscratch != noreg || always_reachable(src), "missing");
2173
2174 if (reachable(src)) {
2175 kmovql(dst, as_Address(src));
2176 } else {
2177 lea(rscratch, src);
2178 kmovql(dst, Address(rscratch, 0));
2179 }
2180 }
2181
2182 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2183 assert(rscratch != noreg || always_reachable(src), "missing");
2184
2185 if (reachable(src)) {
2186 kmovwl(dst, as_Address(src));
2187 } else {
2188 lea(rscratch, src);
2189 kmovwl(dst, Address(rscratch, 0));
2190 }
2191 }
2192
2193 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2194 int vector_len, Register rscratch) {
2195 assert(rscratch != noreg || always_reachable(src), "missing");
2196
2197 if (reachable(src)) {
2198 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2199 } else {
2200 lea(rscratch, src);
2201 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2202 }
2203 }
2204
2205 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2206 int vector_len, Register rscratch) {
2207 assert(rscratch != noreg || always_reachable(src), "missing");
2208
2209 if (reachable(src)) {
2210 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2211 } else {
2212 lea(rscratch, src);
2213 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2214 }
2215 }
2216
2217 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2218 assert(rscratch != noreg || always_reachable(src), "missing");
2219
2220 if (reachable(src)) {
2221 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2222 } else {
2223 lea(rscratch, src);
2224 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2225 }
2226 }
2227
2228 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2229 assert(rscratch != noreg || always_reachable(src), "missing");
2230
2231 if (reachable(src)) {
2232 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2233 } else {
2234 lea(rscratch, src);
2235 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2236 }
2237 }
2238
2239 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2240 assert(rscratch != noreg || always_reachable(src), "missing");
2241
2242 if (reachable(src)) {
2243 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2244 } else {
2245 lea(rscratch, src);
2246 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2247 }
2248 }
2249
2250 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2251 assert(rscratch != noreg || always_reachable(src), "missing");
2252
2253 if (reachable(src)) {
2254 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2255 } else {
2256 lea(rscratch, src);
2257 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2258 }
2259 }
2260
2261 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2262 assert(rscratch != noreg || always_reachable(src), "missing");
2263
2264 if (reachable(src)) {
2265 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2266 } else {
2267 lea(rscratch, src);
2268 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2269 }
2270 }
2271
2272 void MacroAssembler::movapd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2273 assert(rscratch != noreg || always_reachable(src), "missing");
2274
2275 if (reachable(src)) {
2276 Assembler::movapd(dst, as_Address(src));
2277 } else {
2278 lea(rscratch, src);
2279 Assembler::movapd(dst, Address(rscratch, 0));
2280 }
2281 }
2282
2283 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2284 assert(rscratch != noreg || always_reachable(src), "missing");
2285
2286 if (reachable(src)) {
2287 Assembler::movdqa(dst, as_Address(src));
2288 } else {
2289 lea(rscratch, src);
2290 Assembler::movdqa(dst, Address(rscratch, 0));
2291 }
2292 }
2293
2294 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2295 assert(rscratch != noreg || always_reachable(src), "missing");
2296
2297 if (reachable(src)) {
2298 Assembler::movsd(dst, as_Address(src));
2299 } else {
2300 lea(rscratch, src);
2301 Assembler::movsd(dst, Address(rscratch, 0));
2302 }
2303 }
2304
2305 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2306 assert(rscratch != noreg || always_reachable(src), "missing");
2307
2308 if (reachable(src)) {
2309 Assembler::movss(dst, as_Address(src));
2310 } else {
2311 lea(rscratch, src);
2312 Assembler::movss(dst, Address(rscratch, 0));
2313 }
2314 }
2315
2316 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2317 assert(rscratch != noreg || always_reachable(src), "missing");
2318
2319 if (reachable(src)) {
2320 Assembler::movddup(dst, as_Address(src));
2321 } else {
2322 lea(rscratch, src);
2323 Assembler::movddup(dst, Address(rscratch, 0));
2324 }
2325 }
2326
2327 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2328 assert(rscratch != noreg || always_reachable(src), "missing");
2329
2330 if (reachable(src)) {
2331 Assembler::vmovddup(dst, as_Address(src), vector_len);
2332 } else {
2333 lea(rscratch, src);
2334 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2335 }
2336 }
2337
2338 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2339 assert(rscratch != noreg || always_reachable(src), "missing");
2340
2341 if (reachable(src)) {
2342 Assembler::mulsd(dst, as_Address(src));
2343 } else {
2344 lea(rscratch, src);
2345 Assembler::mulsd(dst, Address(rscratch, 0));
2346 }
2347 }
2348
2349 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2350 assert(rscratch != noreg || always_reachable(src), "missing");
2351
2352 if (reachable(src)) {
2353 Assembler::mulss(dst, as_Address(src));
2354 } else {
2355 lea(rscratch, src);
2356 Assembler::mulss(dst, Address(rscratch, 0));
2357 }
2358 }
2359
2360 void MacroAssembler::null_check(Register reg, int offset) {
2361 if (needs_explicit_null_check(offset)) {
2362 // provoke OS null exception if reg is null by
2363 // accessing M[reg] w/o changing any (non-CC) registers
2364 // NOTE: cmpl is plenty here to provoke a segv
2365 cmpptr(rax, Address(reg, 0));
2366 // Note: should probably use testl(rax, Address(reg, 0));
2367 // may be shorter code (however, this version of
2368 // testl needs to be implemented first)
2369 } else {
2370 // nothing to do, (later) access of M[reg + offset]
2371 // will provoke OS null exception if reg is null
2372 }
2373 }
2374
2375 void MacroAssembler::os_breakpoint() {
2376 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2377 // (e.g., MSVC can't call ps() otherwise)
2378 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2379 }
2380
2381 void MacroAssembler::unimplemented(const char* what) {
2382 const char* buf = nullptr;
2383 {
2384 ResourceMark rm;
2385 stringStream ss;
2386 ss.print("unimplemented: %s", what);
2387 buf = code_string(ss.as_string());
2388 }
2389 stop(buf);
2390 }
2391
2392 #define XSTATE_BV 0x200
2393
2394 void MacroAssembler::pop_CPU_state() {
2395 pop_FPU_state();
2396 pop_IU_state();
2397 }
2398
2399 void MacroAssembler::pop_FPU_state() {
2400 fxrstor(Address(rsp, 0));
2401 addptr(rsp, FPUStateSizeInWords * wordSize);
2402 }
2403
2404 void MacroAssembler::pop_IU_state() {
2405 popa();
2406 addq(rsp, 8);
2407 popf();
2408 }
2409
2410 // Save Integer and Float state
2411 // Warning: Stack must be 16 byte aligned (64bit)
2412 void MacroAssembler::push_CPU_state() {
2413 push_IU_state();
2414 push_FPU_state();
2415 }
2416
2417 void MacroAssembler::push_FPU_state() {
2418 subptr(rsp, FPUStateSizeInWords * wordSize);
2419 fxsave(Address(rsp, 0));
2420 }
2421
2422 void MacroAssembler::push_IU_state() {
2423 // Push flags first because pusha kills them
2424 pushf();
2425 // Make sure rsp stays 16-byte aligned
2426 subq(rsp, 8);
2427 pusha();
2428 }
2429
2430 void MacroAssembler::push_cont_fastpath() {
2431 if (!Continuations::enabled()) return;
2432
2433 Label L_done;
2434 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2435 jccb(Assembler::belowEqual, L_done);
2436 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), rsp);
2437 bind(L_done);
2438 }
2439
2440 void MacroAssembler::pop_cont_fastpath() {
2441 if (!Continuations::enabled()) return;
2442
2443 Label L_done;
2444 cmpptr(rsp, Address(r15_thread, JavaThread::cont_fastpath_offset()));
2445 jccb(Assembler::below, L_done);
2446 movptr(Address(r15_thread, JavaThread::cont_fastpath_offset()), 0);
2447 bind(L_done);
2448 }
2449
2450 #ifdef ASSERT
2451 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2452 Label no_cont;
2453 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2454 testl(cont, cont);
2455 jcc(Assembler::zero, no_cont);
2456 stop(name);
2457 bind(no_cont);
2458 }
2459 #endif
2460
2461 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { // determine java_thread register
2462 // we must set sp to zero to clear frame
2463 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2464 // must clear fp, so that compiled frames are not confused; it is
2465 // possible that we need it only for debugging
2466 if (clear_fp) {
2467 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2468 }
2469 // Always clear the pc because it could have been set by make_walkable()
2470 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2471 vzeroupper();
2472 }
2473
2474 void MacroAssembler::round_to(Register reg, int modulus) {
2475 addptr(reg, modulus - 1);
2476 andptr(reg, -modulus);
2477 }
2478
2479 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod) {
2480 if (at_return) {
2481 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2482 // we may safely use rsp instead to perform the stack watermark check.
2483 cmpptr(in_nmethod ? rsp : rbp, Address(r15_thread, JavaThread::polling_word_offset()));
2484 jcc(Assembler::above, slow_path);
2485 return;
2486 }
2487 testb(Address(r15_thread, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2488 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2489 }
2490
2491 // Calls to C land
2492 //
2493 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2494 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2495 // has to be reset to 0. This is required to allow proper stack traversal.
2496 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2497 Register last_java_fp,
2498 address last_java_pc,
2499 Register rscratch) {
2500 vzeroupper();
2501 // determine last_java_sp register
2502 if (!last_java_sp->is_valid()) {
2503 last_java_sp = rsp;
2504 }
2505 // last_java_fp is optional
2506 if (last_java_fp->is_valid()) {
2507 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2508 }
2509 // last_java_pc is optional
2510 if (last_java_pc != nullptr) {
2511 Address java_pc(r15_thread,
2512 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
2513 lea(java_pc, InternalAddress(last_java_pc), rscratch);
2514 }
2515 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2516 }
2517
2518 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
2519 Register last_java_fp,
2520 Label &L,
2521 Register scratch) {
2522 lea(scratch, L);
2523 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
2524 set_last_Java_frame(last_java_sp, last_java_fp, nullptr, scratch);
2525 }
2526
2527 void MacroAssembler::shlptr(Register dst, int imm8) {
2528 shlq(dst, imm8);
2529 }
2530
2531 void MacroAssembler::shrptr(Register dst, int imm8) {
2532 shrq(dst, imm8);
2533 }
2534
2535 void MacroAssembler::sign_extend_byte(Register reg) {
2536 movsbl(reg, reg); // movsxb
2537 }
2538
2539 void MacroAssembler::sign_extend_short(Register reg) {
2540 movswl(reg, reg); // movsxw
2541 }
2542
2543 void MacroAssembler::testl(Address dst, int32_t imm32) {
2544 if (imm32 >= 0 && is8bit(imm32)) {
2545 testb(dst, imm32);
2546 } else {
2547 Assembler::testl(dst, imm32);
2548 }
2549 }
2550
2551 void MacroAssembler::testl(Register dst, int32_t imm32) {
2552 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
2553 testb(dst, imm32);
2554 } else {
2555 Assembler::testl(dst, imm32);
2556 }
2557 }
2558
2559 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2560 assert(always_reachable(src), "Address should be reachable");
2561 testl(dst, as_Address(src));
2562 }
2563
2564 void MacroAssembler::testq(Address dst, int32_t imm32) {
2565 if (imm32 >= 0) {
2566 testl(dst, imm32);
2567 } else {
2568 Assembler::testq(dst, imm32);
2569 }
2570 }
2571
2572 void MacroAssembler::testq(Register dst, int32_t imm32) {
2573 if (imm32 >= 0) {
2574 testl(dst, imm32);
2575 } else {
2576 Assembler::testq(dst, imm32);
2577 }
2578 }
2579
2580 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2581 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2582 Assembler::pcmpeqb(dst, src);
2583 }
2584
2585 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2586 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2587 Assembler::pcmpeqw(dst, src);
2588 }
2589
2590 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2591 assert((dst->encoding() < 16),"XMM register should be 0-15");
2592 Assembler::pcmpestri(dst, src, imm8);
2593 }
2594
2595 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2596 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2597 Assembler::pcmpestri(dst, src, imm8);
2598 }
2599
2600 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2601 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2602 Assembler::pmovzxbw(dst, src);
2603 }
2604
2605 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2606 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2607 Assembler::pmovzxbw(dst, src);
2608 }
2609
2610 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2611 assert((src->encoding() < 16),"XMM register should be 0-15");
2612 Assembler::pmovmskb(dst, src);
2613 }
2614
2615 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2616 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2617 Assembler::ptest(dst, src);
2618 }
2619
2620 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2621 assert(rscratch != noreg || always_reachable(src), "missing");
2622
2623 if (reachable(src)) {
2624 Assembler::sqrtss(dst, as_Address(src));
2625 } else {
2626 lea(rscratch, src);
2627 Assembler::sqrtss(dst, Address(rscratch, 0));
2628 }
2629 }
2630
2631 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2632 assert(rscratch != noreg || always_reachable(src), "missing");
2633
2634 if (reachable(src)) {
2635 Assembler::subsd(dst, as_Address(src));
2636 } else {
2637 lea(rscratch, src);
2638 Assembler::subsd(dst, Address(rscratch, 0));
2639 }
2640 }
2641
2642 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
2643 assert(rscratch != noreg || always_reachable(src), "missing");
2644
2645 if (reachable(src)) {
2646 Assembler::roundsd(dst, as_Address(src), rmode);
2647 } else {
2648 lea(rscratch, src);
2649 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
2650 }
2651 }
2652
2653 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2654 assert(rscratch != noreg || always_reachable(src), "missing");
2655
2656 if (reachable(src)) {
2657 Assembler::subss(dst, as_Address(src));
2658 } else {
2659 lea(rscratch, src);
2660 Assembler::subss(dst, Address(rscratch, 0));
2661 }
2662 }
2663
2664 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2665 assert(rscratch != noreg || always_reachable(src), "missing");
2666
2667 if (reachable(src)) {
2668 Assembler::ucomisd(dst, as_Address(src));
2669 } else {
2670 lea(rscratch, src);
2671 Assembler::ucomisd(dst, Address(rscratch, 0));
2672 }
2673 }
2674
2675 void MacroAssembler::evucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2676 assert(rscratch != noreg || always_reachable(src), "missing");
2677
2678 if (reachable(src)) {
2679 Assembler::evucomxsd(dst, as_Address(src));
2680 } else {
2681 lea(rscratch, src);
2682 Assembler::evucomxsd(dst, Address(rscratch, 0));
2683 }
2684 }
2685
2686 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2687 assert(rscratch != noreg || always_reachable(src), "missing");
2688
2689 if (reachable(src)) {
2690 Assembler::ucomiss(dst, as_Address(src));
2691 } else {
2692 lea(rscratch, src);
2693 Assembler::ucomiss(dst, Address(rscratch, 0));
2694 }
2695 }
2696
2697 void MacroAssembler::evucomxss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2698 assert(rscratch != noreg || always_reachable(src), "missing");
2699
2700 if (reachable(src)) {
2701 Assembler::evucomxss(dst, as_Address(src));
2702 } else {
2703 lea(rscratch, src);
2704 Assembler::evucomxss(dst, Address(rscratch, 0));
2705 }
2706 }
2707
2708 void MacroAssembler::evucomish(XMMRegister dst, AddressLiteral src, Register rscratch) {
2709 assert(rscratch != noreg || always_reachable(src), "missing");
2710
2711 if (reachable(src)) {
2712 Assembler::evucomish(dst, as_Address(src));
2713 } else {
2714 lea(rscratch, src);
2715 Assembler::evucomish(dst, Address(rscratch, 0));
2716 }
2717 }
2718
2719 void MacroAssembler::evucomxsh(XMMRegister dst, AddressLiteral src, Register rscratch) {
2720 assert(rscratch != noreg || always_reachable(src), "missing");
2721
2722 if (reachable(src)) {
2723 Assembler::evucomxsh(dst, as_Address(src));
2724 } else {
2725 lea(rscratch, src);
2726 Assembler::evucomxsh(dst, Address(rscratch, 0));
2727 }
2728 }
2729
2730 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2731 assert(rscratch != noreg || always_reachable(src), "missing");
2732
2733 // Used in sign-bit flipping with aligned address.
2734 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2735
2736 if (UseAVX > 2 &&
2737 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2738 (dst->encoding() >= 16)) {
2739 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2740 } else if (reachable(src)) {
2741 Assembler::xorpd(dst, as_Address(src));
2742 } else {
2743 lea(rscratch, src);
2744 Assembler::xorpd(dst, Address(rscratch, 0));
2745 }
2746 }
2747
2748 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
2749 if (UseAVX > 2 &&
2750 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2751 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2752 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2753 } else {
2754 Assembler::xorpd(dst, src);
2755 }
2756 }
2757
2758 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
2759 if (UseAVX > 2 &&
2760 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2761 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
2762 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
2763 } else {
2764 Assembler::xorps(dst, src);
2765 }
2766 }
2767
2768 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
2769 assert(rscratch != noreg || always_reachable(src), "missing");
2770
2771 // Used in sign-bit flipping with aligned address.
2772 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
2773
2774 if (UseAVX > 2 &&
2775 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
2776 (dst->encoding() >= 16)) {
2777 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
2778 } else if (reachable(src)) {
2779 Assembler::xorps(dst, as_Address(src));
2780 } else {
2781 lea(rscratch, src);
2782 Assembler::xorps(dst, Address(rscratch, 0));
2783 }
2784 }
2785
2786 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
2787 assert(rscratch != noreg || always_reachable(src), "missing");
2788
2789 // Used in sign-bit flipping with aligned address.
2790 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
2791 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
2792 if (reachable(src)) {
2793 Assembler::pshufb(dst, as_Address(src));
2794 } else {
2795 lea(rscratch, src);
2796 Assembler::pshufb(dst, Address(rscratch, 0));
2797 }
2798 }
2799
2800 // AVX 3-operands instructions
2801
2802 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2803 assert(rscratch != noreg || always_reachable(src), "missing");
2804
2805 if (reachable(src)) {
2806 vaddsd(dst, nds, as_Address(src));
2807 } else {
2808 lea(rscratch, src);
2809 vaddsd(dst, nds, Address(rscratch, 0));
2810 }
2811 }
2812
2813 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
2814 assert(rscratch != noreg || always_reachable(src), "missing");
2815
2816 if (reachable(src)) {
2817 vaddss(dst, nds, as_Address(src));
2818 } else {
2819 lea(rscratch, src);
2820 vaddss(dst, nds, Address(rscratch, 0));
2821 }
2822 }
2823
2824 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2825 assert(UseAVX > 0, "requires some form of AVX");
2826 assert(rscratch != noreg || always_reachable(src), "missing");
2827
2828 if (reachable(src)) {
2829 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
2830 } else {
2831 lea(rscratch, src);
2832 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
2833 }
2834 }
2835
2836 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2837 assert(UseAVX > 0, "requires some form of AVX");
2838 assert(rscratch != noreg || always_reachable(src), "missing");
2839
2840 if (reachable(src)) {
2841 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
2842 } else {
2843 lea(rscratch, src);
2844 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
2845 }
2846 }
2847
2848 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2849 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2850 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2851
2852 vandps(dst, nds, negate_field, vector_len, rscratch);
2853 }
2854
2855 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
2856 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
2857 assert(rscratch != noreg || always_reachable(negate_field), "missing");
2858
2859 vandpd(dst, nds, negate_field, vector_len, rscratch);
2860 }
2861
2862 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2863 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2864 Assembler::vpaddb(dst, nds, src, vector_len);
2865 }
2866
2867 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2868 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2869 Assembler::vpaddb(dst, nds, src, vector_len);
2870 }
2871
2872 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2873 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2874 Assembler::vpaddw(dst, nds, src, vector_len);
2875 }
2876
2877 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
2878 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2879 Assembler::vpaddw(dst, nds, src, vector_len);
2880 }
2881
2882 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
2883 assert(rscratch != noreg || always_reachable(src), "missing");
2884
2885 if (reachable(src)) {
2886 Assembler::vpand(dst, nds, as_Address(src), vector_len);
2887 } else {
2888 lea(rscratch, src);
2889 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
2890 }
2891 }
2892
2893 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2894 assert(rscratch != noreg || always_reachable(src), "missing");
2895
2896 if (reachable(src)) {
2897 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
2898 } else {
2899 lea(rscratch, src);
2900 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
2901 }
2902 }
2903
2904 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2905 assert(rscratch != noreg || always_reachable(src), "missing");
2906
2907 if (reachable(src)) {
2908 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
2909 } else {
2910 lea(rscratch, src);
2911 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
2912 }
2913 }
2914
2915 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2916 assert(rscratch != noreg || always_reachable(src), "missing");
2917
2918 if (reachable(src)) {
2919 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
2920 } else {
2921 lea(rscratch, src);
2922 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
2923 }
2924 }
2925
2926 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2927 assert(rscratch != noreg || always_reachable(src), "missing");
2928
2929 if (reachable(src)) {
2930 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
2931 } else {
2932 lea(rscratch, src);
2933 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
2934 }
2935 }
2936
2937 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2938 assert(rscratch != noreg || always_reachable(src), "missing");
2939
2940 if (reachable(src)) {
2941 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
2942 } else {
2943 lea(rscratch, src);
2944 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
2945 }
2946 }
2947
2948 // Vector float blend
2949 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
2950 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
2951 // WARN: Allow dst == (src1|src2), mask == scratch
2952 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
2953 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
2954 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
2955 bool dst_available = dst != mask && (dst != src1 || dst != src2);
2956 if (blend_emulation && scratch_available && dst_available) {
2957 if (compute_mask) {
2958 vpsrad(scratch, mask, 32, vector_len);
2959 mask = scratch;
2960 }
2961 if (dst == src1) {
2962 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
2963 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
2964 } else {
2965 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
2966 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
2967 }
2968 vpor(dst, dst, scratch, vector_len);
2969 } else {
2970 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
2971 }
2972 }
2973
2974 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
2975 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
2976 // WARN: Allow dst == (src1|src2), mask == scratch
2977 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1 &&
2978 !(VM_Version::is_intel_darkmont() && (dst == src1)); // partially fixed on Darkmont
2979 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
2980 bool dst_available = dst != mask && (dst != src1 || dst != src2);
2981 if (blend_emulation && scratch_available && dst_available) {
2982 if (compute_mask) {
2983 vpxor(scratch, scratch, scratch, vector_len);
2984 vpcmpgtq(scratch, scratch, mask, vector_len);
2985 mask = scratch;
2986 }
2987 if (dst == src1) {
2988 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
2989 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
2990 } else {
2991 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
2992 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
2993 }
2994 vpor(dst, dst, scratch, vector_len);
2995 } else {
2996 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
2997 }
2998 }
2999
3000 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3001 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3002 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3003 }
3004
3005 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3006 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3007 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3008 }
3009
3010 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3011 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3012 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3013 }
3014
3015 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3016 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3017 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3018 }
3019
3020 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3021 assert(rscratch != noreg || always_reachable(src), "missing");
3022
3023 if (reachable(src)) {
3024 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3025 } else {
3026 lea(rscratch, src);
3027 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3028 }
3029 }
3030
3031 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3032 int comparison, bool is_signed, int vector_len, Register rscratch) {
3033 assert(rscratch != noreg || always_reachable(src), "missing");
3034
3035 if (reachable(src)) {
3036 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3037 } else {
3038 lea(rscratch, src);
3039 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3040 }
3041 }
3042
3043 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3044 int comparison, bool is_signed, int vector_len, Register rscratch) {
3045 assert(rscratch != noreg || always_reachable(src), "missing");
3046
3047 if (reachable(src)) {
3048 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3049 } else {
3050 lea(rscratch, src);
3051 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3052 }
3053 }
3054
3055 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3056 int comparison, bool is_signed, int vector_len, Register rscratch) {
3057 assert(rscratch != noreg || always_reachable(src), "missing");
3058
3059 if (reachable(src)) {
3060 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3061 } else {
3062 lea(rscratch, src);
3063 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3064 }
3065 }
3066
3067 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3068 int comparison, bool is_signed, int vector_len, Register rscratch) {
3069 assert(rscratch != noreg || always_reachable(src), "missing");
3070
3071 if (reachable(src)) {
3072 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3073 } else {
3074 lea(rscratch, src);
3075 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3076 }
3077 }
3078
3079 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3080 if (width == Assembler::Q) {
3081 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3082 } else {
3083 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3084 }
3085 }
3086
3087 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3088 int eq_cond_enc = 0x29;
3089 int gt_cond_enc = 0x37;
3090 if (width != Assembler::Q) {
3091 eq_cond_enc = 0x74 + width;
3092 gt_cond_enc = 0x64 + width;
3093 }
3094 switch (cond) {
3095 case eq:
3096 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3097 break;
3098 case neq:
3099 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3100 vallones(xtmp, vector_len);
3101 vpxor(dst, xtmp, dst, vector_len);
3102 break;
3103 case le:
3104 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3105 vallones(xtmp, vector_len);
3106 vpxor(dst, xtmp, dst, vector_len);
3107 break;
3108 case nlt:
3109 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3110 vallones(xtmp, vector_len);
3111 vpxor(dst, xtmp, dst, vector_len);
3112 break;
3113 case lt:
3114 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3115 break;
3116 case nle:
3117 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3118 break;
3119 default:
3120 assert(false, "Should not reach here");
3121 }
3122 }
3123
3124 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3125 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3126 Assembler::vpmovzxbw(dst, src, vector_len);
3127 }
3128
3129 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3130 assert((src->encoding() < 16),"XMM register should be 0-15");
3131 Assembler::vpmovmskb(dst, src, vector_len);
3132 }
3133
3134 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3135 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3136 Assembler::vpmullw(dst, nds, src, vector_len);
3137 }
3138
3139 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3140 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3141 Assembler::vpmullw(dst, nds, src, vector_len);
3142 }
3143
3144 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3145 assert((UseAVX > 0), "AVX support is needed");
3146 assert(rscratch != noreg || always_reachable(src), "missing");
3147
3148 if (reachable(src)) {
3149 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3150 } else {
3151 lea(rscratch, src);
3152 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3153 }
3154 }
3155
3156 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3157 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3158 Assembler::vpsubb(dst, nds, src, vector_len);
3159 }
3160
3161 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3162 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3163 Assembler::vpsubb(dst, nds, src, vector_len);
3164 }
3165
3166 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3167 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3168 Assembler::vpsubw(dst, nds, src, vector_len);
3169 }
3170
3171 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3172 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3173 Assembler::vpsubw(dst, nds, src, vector_len);
3174 }
3175
3176 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3177 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3178 Assembler::vpsraw(dst, nds, shift, vector_len);
3179 }
3180
3181 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3182 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3183 Assembler::vpsraw(dst, nds, shift, vector_len);
3184 }
3185
3186 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3187 assert(UseAVX > 2,"");
3188 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3189 vector_len = 2;
3190 }
3191 Assembler::evpsraq(dst, nds, shift, vector_len);
3192 }
3193
3194 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3195 assert(UseAVX > 2,"");
3196 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3197 vector_len = 2;
3198 }
3199 Assembler::evpsraq(dst, nds, shift, vector_len);
3200 }
3201
3202 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3203 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3204 Assembler::vpsrlw(dst, nds, shift, vector_len);
3205 }
3206
3207 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3208 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3209 Assembler::vpsrlw(dst, nds, shift, vector_len);
3210 }
3211
3212 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3213 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3214 Assembler::vpsllw(dst, nds, shift, vector_len);
3215 }
3216
3217 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3218 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3219 Assembler::vpsllw(dst, nds, shift, vector_len);
3220 }
3221
3222 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3223 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3224 Assembler::vptest(dst, src);
3225 }
3226
3227 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3228 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3229 Assembler::punpcklbw(dst, src);
3230 }
3231
3232 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3233 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3234 Assembler::pshufd(dst, src, mode);
3235 }
3236
3237 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3238 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3239 Assembler::pshuflw(dst, src, mode);
3240 }
3241
3242 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3243 assert(rscratch != noreg || always_reachable(src), "missing");
3244
3245 if (reachable(src)) {
3246 vandpd(dst, nds, as_Address(src), vector_len);
3247 } else {
3248 lea(rscratch, src);
3249 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3250 }
3251 }
3252
3253 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3254 assert(rscratch != noreg || always_reachable(src), "missing");
3255
3256 if (reachable(src)) {
3257 vandps(dst, nds, as_Address(src), vector_len);
3258 } else {
3259 lea(rscratch, src);
3260 vandps(dst, nds, Address(rscratch, 0), vector_len);
3261 }
3262 }
3263
3264 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3265 bool merge, int vector_len, Register rscratch) {
3266 assert(rscratch != noreg || always_reachable(src), "missing");
3267
3268 if (reachable(src)) {
3269 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3270 } else {
3271 lea(rscratch, src);
3272 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3273 }
3274 }
3275
3276 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3277 assert(rscratch != noreg || always_reachable(src), "missing");
3278
3279 if (reachable(src)) {
3280 vdivsd(dst, nds, as_Address(src));
3281 } else {
3282 lea(rscratch, src);
3283 vdivsd(dst, nds, Address(rscratch, 0));
3284 }
3285 }
3286
3287 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3288 assert(rscratch != noreg || always_reachable(src), "missing");
3289
3290 if (reachable(src)) {
3291 vdivss(dst, nds, as_Address(src));
3292 } else {
3293 lea(rscratch, src);
3294 vdivss(dst, nds, Address(rscratch, 0));
3295 }
3296 }
3297
3298 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3299 assert(rscratch != noreg || always_reachable(src), "missing");
3300
3301 if (reachable(src)) {
3302 vmulsd(dst, nds, as_Address(src));
3303 } else {
3304 lea(rscratch, src);
3305 vmulsd(dst, nds, Address(rscratch, 0));
3306 }
3307 }
3308
3309 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3310 assert(rscratch != noreg || always_reachable(src), "missing");
3311
3312 if (reachable(src)) {
3313 vmulss(dst, nds, as_Address(src));
3314 } else {
3315 lea(rscratch, src);
3316 vmulss(dst, nds, Address(rscratch, 0));
3317 }
3318 }
3319
3320 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3321 assert(rscratch != noreg || always_reachable(src), "missing");
3322
3323 if (reachable(src)) {
3324 vsubsd(dst, nds, as_Address(src));
3325 } else {
3326 lea(rscratch, src);
3327 vsubsd(dst, nds, Address(rscratch, 0));
3328 }
3329 }
3330
3331 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3332 assert(rscratch != noreg || always_reachable(src), "missing");
3333
3334 if (reachable(src)) {
3335 vsubss(dst, nds, as_Address(src));
3336 } else {
3337 lea(rscratch, src);
3338 vsubss(dst, nds, Address(rscratch, 0));
3339 }
3340 }
3341
3342 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3343 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3344 assert(rscratch != noreg || always_reachable(src), "missing");
3345
3346 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3347 }
3348
3349 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3350 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3351 assert(rscratch != noreg || always_reachable(src), "missing");
3352
3353 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3354 }
3355
3356 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3357 assert(rscratch != noreg || always_reachable(src), "missing");
3358
3359 if (reachable(src)) {
3360 vxorpd(dst, nds, as_Address(src), vector_len);
3361 } else {
3362 lea(rscratch, src);
3363 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3364 }
3365 }
3366
3367 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3368 assert(rscratch != noreg || always_reachable(src), "missing");
3369
3370 if (reachable(src)) {
3371 vxorps(dst, nds, as_Address(src), vector_len);
3372 } else {
3373 lea(rscratch, src);
3374 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3375 }
3376 }
3377
3378 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3379 assert(rscratch != noreg || always_reachable(src), "missing");
3380
3381 if (UseAVX > 1 || (vector_len < 1)) {
3382 if (reachable(src)) {
3383 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3384 } else {
3385 lea(rscratch, src);
3386 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3387 }
3388 } else {
3389 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3390 }
3391 }
3392
3393 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3394 assert(rscratch != noreg || always_reachable(src), "missing");
3395
3396 if (reachable(src)) {
3397 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3398 } else {
3399 lea(rscratch, src);
3400 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3401 }
3402 }
3403
3404 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3405 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3406 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3407 // The inverted mask is sign-extended
3408 andptr(possibly_non_local, inverted_mask);
3409 }
3410
3411 void MacroAssembler::resolve_jobject(Register value,
3412 Register tmp) {
3413 Register thread = r15_thread;
3414 assert_different_registers(value, thread, tmp);
3415 Label done, tagged, weak_tagged;
3416 testptr(value, value);
3417 jcc(Assembler::zero, done); // Use null as-is.
3418 testptr(value, JNIHandles::tag_mask); // Test for tag.
3419 jcc(Assembler::notZero, tagged);
3420
3421 // Resolve local handle
3422 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp);
3423 verify_oop(value);
3424 jmp(done);
3425
3426 bind(tagged);
3427 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
3428 jcc(Assembler::notZero, weak_tagged);
3429
3430 // Resolve global handle
3431 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3432 verify_oop(value);
3433 jmp(done);
3434
3435 bind(weak_tagged);
3436 // Resolve jweak.
3437 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3438 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp);
3439 verify_oop(value);
3440
3441 bind(done);
3442 }
3443
3444 void MacroAssembler::resolve_global_jobject(Register value,
3445 Register tmp) {
3446 Register thread = r15_thread;
3447 assert_different_registers(value, thread, tmp);
3448 Label done;
3449
3450 testptr(value, value);
3451 jcc(Assembler::zero, done); // Use null as-is.
3452
3453 #ifdef ASSERT
3454 {
3455 Label valid_global_tag;
3456 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
3457 jcc(Assembler::notZero, valid_global_tag);
3458 stop("non global jobject using resolve_global_jobject");
3459 bind(valid_global_tag);
3460 }
3461 #endif
3462
3463 // Resolve global handle
3464 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp);
3465 verify_oop(value);
3466
3467 bind(done);
3468 }
3469
3470 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3471 subq(dst, imm32);
3472 }
3473
3474 // Force generation of a 4 byte immediate value even if it fits into 8bit
3475 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3476 subq_imm32(dst, imm32);
3477 }
3478
3479 void MacroAssembler::subptr(Register dst, Register src) {
3480 subq(dst, src);
3481 }
3482
3483 // C++ bool manipulation
3484 void MacroAssembler::testbool(Register dst) {
3485 if(sizeof(bool) == 1)
3486 testb(dst, 0xff);
3487 else if(sizeof(bool) == 2) {
3488 // testw implementation needed for two byte bools
3489 ShouldNotReachHere();
3490 } else if(sizeof(bool) == 4)
3491 testl(dst, dst);
3492 else
3493 // unsupported
3494 ShouldNotReachHere();
3495 }
3496
3497 void MacroAssembler::testptr(Register dst, Register src) {
3498 testq(dst, src);
3499 }
3500
3501 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3502 void MacroAssembler::tlab_allocate(Register obj,
3503 Register var_size_in_bytes,
3504 int con_size_in_bytes,
3505 Register t1,
3506 Register t2,
3507 Label& slow_case) {
3508 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3509 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3510 }
3511
3512 RegSet MacroAssembler::call_clobbered_gp_registers() {
3513 RegSet regs;
3514 regs += RegSet::of(rax, rcx, rdx);
3515 #ifndef _WINDOWS
3516 regs += RegSet::of(rsi, rdi);
3517 #endif
3518 regs += RegSet::range(r8, r11);
3519 if (UseAPX) {
3520 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
3521 }
3522 return regs;
3523 }
3524
3525 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3526 int num_xmm_registers = XMMRegister::available_xmm_registers();
3527 #if defined(_WINDOWS)
3528 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3529 if (num_xmm_registers > 16) {
3530 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3531 }
3532 return result;
3533 #else
3534 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3535 #endif
3536 }
3537
3538 // C1 only ever uses the first double/float of the XMM register.
3539 static int xmm_save_size() { return sizeof(double); }
3540
3541 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3542 masm->movdbl(Address(rsp, offset), reg);
3543 }
3544
3545 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3546 masm->movdbl(reg, Address(rsp, offset));
3547 }
3548
3549 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
3550 bool save_fpu, int& gp_area_size, int& xmm_area_size) {
3551
3552 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
3553 StackAlignmentInBytes);
3554 xmm_area_size = save_fpu ? xmm_registers.size() * xmm_save_size() : 0;
3555
3556 return gp_area_size + xmm_area_size;
3557 }
3558
3559 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3560 block_comment("push_call_clobbered_registers start");
3561 // Regular registers
3562 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3563
3564 int gp_area_size;
3565 int xmm_area_size;
3566 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3567 gp_area_size, xmm_area_size);
3568 subptr(rsp, total_save_size);
3569
3570 push_set(gp_registers_to_push, 0);
3571
3572 if (save_fpu) {
3573 push_set(call_clobbered_xmm_registers(), gp_area_size);
3574 }
3575
3576 block_comment("push_call_clobbered_registers end");
3577 }
3578
3579 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3580 block_comment("pop_call_clobbered_registers start");
3581
3582 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3583
3584 int gp_area_size;
3585 int xmm_area_size;
3586 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3587 gp_area_size, xmm_area_size);
3588
3589 if (restore_fpu) {
3590 pop_set(call_clobbered_xmm_registers(), gp_area_size);
3591 }
3592
3593 pop_set(gp_registers_to_pop, 0);
3594
3595 addptr(rsp, total_save_size);
3596
3597 vzeroupper();
3598
3599 block_comment("pop_call_clobbered_registers end");
3600 }
3601
3602 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3603 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3604 int spill_offset = offset;
3605
3606 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3607 save_xmm_register(this, spill_offset, *it);
3608 spill_offset += xmm_save_size();
3609 }
3610 }
3611
3612 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3613 int restore_size = set.size() * xmm_save_size();
3614 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3615
3616 int restore_offset = offset + restore_size - xmm_save_size();
3617
3618 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3619 restore_xmm_register(this, restore_offset, *it);
3620 restore_offset -= xmm_save_size();
3621 }
3622 }
3623
3624 void MacroAssembler::push_set(RegSet set, int offset) {
3625 int spill_offset;
3626 if (offset == -1) {
3627 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3628 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3629 subptr(rsp, aligned_size);
3630 spill_offset = 0;
3631 } else {
3632 spill_offset = offset;
3633 }
3634
3635 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3636 movptr(Address(rsp, spill_offset), *it);
3637 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3638 }
3639 }
3640
3641 void MacroAssembler::pop_set(RegSet set, int offset) {
3642
3643 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
3644 int restore_size = set.size() * gp_reg_size;
3645 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3646
3647 int restore_offset;
3648 if (offset == -1) {
3649 restore_offset = restore_size - gp_reg_size;
3650 } else {
3651 restore_offset = offset + restore_size - gp_reg_size;
3652 }
3653 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3654 movptr(*it, Address(rsp, restore_offset));
3655 restore_offset -= gp_reg_size;
3656 }
3657
3658 if (offset == -1) {
3659 addptr(rsp, aligned_size);
3660 }
3661 }
3662
3663 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3664 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3665 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3666 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3667 Label done;
3668
3669 testptr(length_in_bytes, length_in_bytes);
3670 jcc(Assembler::zero, done);
3671
3672 // initialize topmost word, divide index by 2, check if odd and test if zero
3673 // note: for the remaining code to work, index must be a multiple of BytesPerWord
3674 #ifdef ASSERT
3675 {
3676 Label L;
3677 testptr(length_in_bytes, BytesPerWord - 1);
3678 jcc(Assembler::zero, L);
3679 stop("length must be a multiple of BytesPerWord");
3680 bind(L);
3681 }
3682 #endif
3683 Register index = length_in_bytes;
3684 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
3685 if (UseIncDec) {
3686 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
3687 } else {
3688 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
3689 shrptr(index, 1);
3690 }
3691
3692 // initialize remaining object fields: index is a multiple of 2 now
3693 {
3694 Label loop;
3695 bind(loop);
3696 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3697 decrement(index);
3698 jcc(Assembler::notZero, loop);
3699 }
3700
3701 bind(done);
3702 }
3703
3704 // Look up the method for a megamorphic invokeinterface call.
3705 // The target method is determined by <intf_klass, itable_index>.
3706 // The receiver klass is in recv_klass.
3707 // On success, the result will be in method_result, and execution falls through.
3708 // On failure, execution transfers to the given label.
3709 void MacroAssembler::lookup_interface_method(Register recv_klass,
3710 Register intf_klass,
3711 RegisterOrConstant itable_index,
3712 Register method_result,
3713 Register scan_temp,
3714 Label& L_no_such_interface,
3715 bool return_method) {
3716 assert_different_registers(recv_klass, intf_klass, scan_temp);
3717 assert_different_registers(method_result, intf_klass, scan_temp);
3718 assert(recv_klass != method_result || !return_method,
3719 "recv_klass can be destroyed when method isn't needed");
3720
3721 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3722 "caller must use same register for non-constant itable index as for method");
3723
3724 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3725 int vtable_base = in_bytes(Klass::vtable_start_offset());
3726 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3727 int scan_step = itableOffsetEntry::size() * wordSize;
3728 int vte_size = vtableEntry::size_in_bytes();
3729 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3730 assert(vte_size == wordSize, "else adjust times_vte_scale");
3731
3732 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3733
3734 // Could store the aligned, prescaled offset in the klass.
3735 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3736
3737 if (return_method) {
3738 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3739 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3740 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3741 }
3742
3743 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
3744 // if (scan->interface() == intf) {
3745 // result = (klass + scan->offset() + itable_index);
3746 // }
3747 // }
3748 Label search, found_method;
3749
3750 for (int peel = 1; peel >= 0; peel--) {
3751 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
3752 cmpptr(intf_klass, method_result);
3753
3754 if (peel) {
3755 jccb(Assembler::equal, found_method);
3756 } else {
3757 jccb(Assembler::notEqual, search);
3758 // (invert the test to fall through to found_method...)
3759 }
3760
3761 if (!peel) break;
3762
3763 bind(search);
3764
3765 // Check that the previous entry is non-null. A null entry means that
3766 // the receiver class doesn't implement the interface, and wasn't the
3767 // same as when the caller was compiled.
3768 testptr(method_result, method_result);
3769 jcc(Assembler::zero, L_no_such_interface);
3770 addptr(scan_temp, scan_step);
3771 }
3772
3773 bind(found_method);
3774
3775 if (return_method) {
3776 // Got a hit.
3777 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
3778 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3779 }
3780 }
3781
3782 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
3783 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
3784 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
3785 // The target method is determined by <holder_klass, itable_index>.
3786 // The receiver klass is in recv_klass.
3787 // On success, the result will be in method_result, and execution falls through.
3788 // On failure, execution transfers to the given label.
3789 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
3790 Register holder_klass,
3791 Register resolved_klass,
3792 Register method_result,
3793 Register scan_temp,
3794 Register temp_reg2,
3795 Register receiver,
3796 int itable_index,
3797 Label& L_no_such_interface) {
3798 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
3799 Register temp_itbl_klass = method_result;
3800 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
3801
3802 int vtable_base = in_bytes(Klass::vtable_start_offset());
3803 int itentry_off = in_bytes(itableMethodEntry::method_offset());
3804 int scan_step = itableOffsetEntry::size() * wordSize;
3805 int vte_size = vtableEntry::size_in_bytes();
3806 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
3807 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
3808 Address::ScaleFactor times_vte_scale = Address::times_ptr;
3809 assert(vte_size == wordSize, "adjust times_vte_scale");
3810
3811 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
3812
3813 // temp_itbl_klass = recv_klass.itable[0]
3814 // scan_temp = &recv_klass.itable[0] + step
3815 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3816 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
3817 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
3818 xorptr(temp_reg, temp_reg);
3819
3820 // Initial checks:
3821 // - if (holder_klass != resolved_klass), go to "scan for resolved"
3822 // - if (itable[0] == 0), no such interface
3823 // - if (itable[0] == holder_klass), shortcut to "holder found"
3824 cmpptr(holder_klass, resolved_klass);
3825 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
3826 testptr(temp_itbl_klass, temp_itbl_klass);
3827 jccb(Assembler::zero, L_no_such_interface);
3828 cmpptr(holder_klass, temp_itbl_klass);
3829 jccb(Assembler::equal, L_holder_found);
3830
3831 // Loop: Look for holder_klass record in itable
3832 // do {
3833 // tmp = itable[index];
3834 // index += step;
3835 // if (tmp == holder_klass) {
3836 // goto L_holder_found; // Found!
3837 // }
3838 // } while (tmp != 0);
3839 // goto L_no_such_interface // Not found.
3840 Label L_scan_holder;
3841 bind(L_scan_holder);
3842 movptr(temp_itbl_klass, Address(scan_temp, 0));
3843 addptr(scan_temp, scan_step);
3844 cmpptr(holder_klass, temp_itbl_klass);
3845 jccb(Assembler::equal, L_holder_found);
3846 testptr(temp_itbl_klass, temp_itbl_klass);
3847 jccb(Assembler::notZero, L_scan_holder);
3848
3849 jmpb(L_no_such_interface);
3850
3851 // Loop: Look for resolved_class record in itable
3852 // do {
3853 // tmp = itable[index];
3854 // index += step;
3855 // if (tmp == holder_klass) {
3856 // // Also check if we have met a holder klass
3857 // holder_tmp = itable[index-step-ioffset];
3858 // }
3859 // if (tmp == resolved_klass) {
3860 // goto L_resolved_found; // Found!
3861 // }
3862 // } while (tmp != 0);
3863 // goto L_no_such_interface // Not found.
3864 //
3865 Label L_loop_scan_resolved;
3866 bind(L_loop_scan_resolved);
3867 movptr(temp_itbl_klass, Address(scan_temp, 0));
3868 addptr(scan_temp, scan_step);
3869 bind(L_loop_scan_resolved_entry);
3870 cmpptr(holder_klass, temp_itbl_klass);
3871 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
3872 cmpptr(resolved_klass, temp_itbl_klass);
3873 jccb(Assembler::equal, L_resolved_found);
3874 testptr(temp_itbl_klass, temp_itbl_klass);
3875 jccb(Assembler::notZero, L_loop_scan_resolved);
3876
3877 jmpb(L_no_such_interface);
3878
3879 Label L_ready;
3880
3881 // See if we already have a holder klass. If not, go and scan for it.
3882 bind(L_resolved_found);
3883 testptr(temp_reg, temp_reg);
3884 jccb(Assembler::zero, L_scan_holder);
3885 jmpb(L_ready);
3886
3887 bind(L_holder_found);
3888 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
3889
3890 // Finally, temp_reg contains holder_klass vtable offset
3891 bind(L_ready);
3892 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3893 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
3894 load_klass(scan_temp, receiver, noreg);
3895 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
3896 } else {
3897 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
3898 }
3899 }
3900
3901
3902 // virtual method calling
3903 void MacroAssembler::lookup_virtual_method(Register recv_klass,
3904 RegisterOrConstant vtable_index,
3905 Register method_result) {
3906 const ByteSize base = Klass::vtable_start_offset();
3907 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
3908 Address vtable_entry_addr(recv_klass,
3909 vtable_index, Address::times_ptr,
3910 base + vtableEntry::method_offset());
3911 movptr(method_result, vtable_entry_addr);
3912 }
3913
3914
3915 void MacroAssembler::check_klass_subtype(Register sub_klass,
3916 Register super_klass,
3917 Register temp_reg,
3918 Label& L_success) {
3919 Label L_failure;
3920 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
3921 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
3922 bind(L_failure);
3923 }
3924
3925
3926 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3927 Register super_klass,
3928 Register temp_reg,
3929 Label* L_success,
3930 Label* L_failure,
3931 Label* L_slow_path,
3932 RegisterOrConstant super_check_offset) {
3933 assert_different_registers(sub_klass, super_klass, temp_reg);
3934 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3935 if (super_check_offset.is_register()) {
3936 assert_different_registers(sub_klass, super_klass,
3937 super_check_offset.as_register());
3938 } else if (must_load_sco) {
3939 assert(temp_reg != noreg, "supply either a temp or a register offset");
3940 }
3941
3942 Label L_fallthrough;
3943 int label_nulls = 0;
3944 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
3945 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
3946 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
3947 assert(label_nulls <= 1, "at most one null in the batch");
3948
3949 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3950 int sco_offset = in_bytes(Klass::super_check_offset_offset());
3951 Address super_check_offset_addr(super_klass, sco_offset);
3952
3953 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
3954 // range of a jccb. If this routine grows larger, reconsider at
3955 // least some of these.
3956 #define local_jcc(assembler_cond, label) \
3957 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
3958 else jcc( assembler_cond, label) /*omit semi*/
3959
3960 // Hacked jmp, which may only be used just before L_fallthrough.
3961 #define final_jmp(label) \
3962 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
3963 else jmp(label) /*omit semi*/
3964
3965 // If the pointers are equal, we are done (e.g., String[] elements).
3966 // This self-check enables sharing of secondary supertype arrays among
3967 // non-primary types such as array-of-interface. Otherwise, each such
3968 // type would need its own customized SSA.
3969 // We move this check to the front of the fast path because many
3970 // type checks are in fact trivially successful in this manner,
3971 // so we get a nicely predicted branch right at the start of the check.
3972 cmpptr(sub_klass, super_klass);
3973 local_jcc(Assembler::equal, *L_success);
3974
3975 // Check the supertype display:
3976 if (must_load_sco) {
3977 // Positive movl does right thing on LP64.
3978 movl(temp_reg, super_check_offset_addr);
3979 super_check_offset = RegisterOrConstant(temp_reg);
3980 }
3981 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
3982 cmpptr(super_klass, super_check_addr); // load displayed supertype
3983
3984 // This check has worked decisively for primary supers.
3985 // Secondary supers are sought in the super_cache ('super_cache_addr').
3986 // (Secondary supers are interfaces and very deeply nested subtypes.)
3987 // This works in the same check above because of a tricky aliasing
3988 // between the super_cache and the primary super display elements.
3989 // (The 'super_check_addr' can address either, as the case requires.)
3990 // Note that the cache is updated below if it does not help us find
3991 // what we need immediately.
3992 // So if it was a primary super, we can just fail immediately.
3993 // Otherwise, it's the slow path for us (no success at this point).
3994
3995 if (super_check_offset.is_register()) {
3996 local_jcc(Assembler::equal, *L_success);
3997 cmpl(super_check_offset.as_register(), sc_offset);
3998 if (L_failure == &L_fallthrough) {
3999 local_jcc(Assembler::equal, *L_slow_path);
4000 } else {
4001 local_jcc(Assembler::notEqual, *L_failure);
4002 final_jmp(*L_slow_path);
4003 }
4004 } else if (super_check_offset.as_constant() == sc_offset) {
4005 // Need a slow path; fast failure is impossible.
4006 if (L_slow_path == &L_fallthrough) {
4007 local_jcc(Assembler::equal, *L_success);
4008 } else {
4009 local_jcc(Assembler::notEqual, *L_slow_path);
4010 final_jmp(*L_success);
4011 }
4012 } else {
4013 // No slow path; it's a fast decision.
4014 if (L_failure == &L_fallthrough) {
4015 local_jcc(Assembler::equal, *L_success);
4016 } else {
4017 local_jcc(Assembler::notEqual, *L_failure);
4018 final_jmp(*L_success);
4019 }
4020 }
4021
4022 bind(L_fallthrough);
4023
4024 #undef local_jcc
4025 #undef final_jmp
4026 }
4027
4028
4029 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4030 Register super_klass,
4031 Register temp_reg,
4032 Register temp2_reg,
4033 Label* L_success,
4034 Label* L_failure,
4035 bool set_cond_codes) {
4036 assert_different_registers(sub_klass, super_klass, temp_reg);
4037 if (temp2_reg != noreg)
4038 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4039 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4040
4041 Label L_fallthrough;
4042 int label_nulls = 0;
4043 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4044 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4045 assert(label_nulls <= 1, "at most one null in the batch");
4046
4047 // a couple of useful fields in sub_klass:
4048 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4049 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4050 Address secondary_supers_addr(sub_klass, ss_offset);
4051 Address super_cache_addr( sub_klass, sc_offset);
4052
4053 // Do a linear scan of the secondary super-klass chain.
4054 // This code is rarely used, so simplicity is a virtue here.
4055 // The repne_scan instruction uses fixed registers, which we must spill.
4056 // Don't worry too much about pre-existing connections with the input regs.
4057
4058 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4059 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4060
4061 // Get super_klass value into rax (even if it was in rdi or rcx).
4062 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4063 if (super_klass != rax) {
4064 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4065 mov(rax, super_klass);
4066 }
4067 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4068 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4069
4070 #ifndef PRODUCT
4071 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4072 ExternalAddress pst_counter_addr((address) pst_counter);
4073 lea(rcx, pst_counter_addr);
4074 incrementl(Address(rcx, 0));
4075 #endif //PRODUCT
4076
4077 // We will consult the secondary-super array.
4078 movptr(rdi, secondary_supers_addr);
4079 // Load the array length. (Positive movl does right thing on LP64.)
4080 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4081 // Skip to start of data.
4082 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4083
4084 // Scan RCX words at [RDI] for an occurrence of RAX.
4085 // Set NZ/Z based on last compare.
4086 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4087 // not change flags (only scas instruction which is repeated sets flags).
4088 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4089
4090 testptr(rax,rax); // Set Z = 0
4091 repne_scan();
4092
4093 // Unspill the temp. registers:
4094 if (pushed_rdi) pop(rdi);
4095 if (pushed_rcx) pop(rcx);
4096 if (pushed_rax) pop(rax);
4097
4098 if (set_cond_codes) {
4099 // Special hack for the AD files: rdi is guaranteed non-zero.
4100 assert(!pushed_rdi, "rdi must be left non-null");
4101 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4102 }
4103
4104 if (L_failure == &L_fallthrough)
4105 jccb(Assembler::notEqual, *L_failure);
4106 else jcc(Assembler::notEqual, *L_failure);
4107
4108 // Success. Cache the super we found and proceed in triumph.
4109 movptr(super_cache_addr, super_klass);
4110
4111 if (L_success != &L_fallthrough) {
4112 jmp(*L_success);
4113 }
4114
4115 #undef IS_A_TEMP
4116
4117 bind(L_fallthrough);
4118 }
4119
4120 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4121 Register super_klass,
4122 Register temp_reg,
4123 Register temp2_reg,
4124 Label* L_success,
4125 Label* L_failure,
4126 bool set_cond_codes) {
4127 assert(set_cond_codes == false, "must be false on 64-bit x86");
4128 check_klass_subtype_slow_path
4129 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4130 L_success, L_failure);
4131 }
4132
4133 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4134 Register super_klass,
4135 Register temp_reg,
4136 Register temp2_reg,
4137 Register temp3_reg,
4138 Register temp4_reg,
4139 Label* L_success,
4140 Label* L_failure) {
4141 if (UseSecondarySupersTable) {
4142 check_klass_subtype_slow_path_table
4143 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4144 L_success, L_failure);
4145 } else {
4146 check_klass_subtype_slow_path_linear
4147 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4148 }
4149 }
4150
4151 Register MacroAssembler::allocate_if_noreg(Register r,
4152 RegSetIterator<Register> &available_regs,
4153 RegSet ®s_to_push) {
4154 if (!r->is_valid()) {
4155 r = *available_regs++;
4156 regs_to_push += r;
4157 }
4158 return r;
4159 }
4160
4161 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4162 Register super_klass,
4163 Register temp_reg,
4164 Register temp2_reg,
4165 Register temp3_reg,
4166 Register result_reg,
4167 Label* L_success,
4168 Label* L_failure) {
4169 // NB! Callers may assume that, when temp2_reg is a valid register,
4170 // this code sets it to a nonzero value.
4171 bool temp2_reg_was_valid = temp2_reg->is_valid();
4172
4173 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4174
4175 Label L_fallthrough;
4176 int label_nulls = 0;
4177 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4178 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4179 assert(label_nulls <= 1, "at most one null in the batch");
4180
4181 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4182
4183 RegSetIterator<Register> available_regs
4184 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4185
4186 RegSet pushed_regs;
4187
4188 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4189 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4190 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4191 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4192 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4193
4194 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4195
4196 {
4197
4198 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4199 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4200 subptr(rsp, aligned_size);
4201 push_set(pushed_regs, 0);
4202
4203 lookup_secondary_supers_table_var(sub_klass,
4204 super_klass,
4205 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4206 cmpq(result_reg, 0);
4207
4208 // Unspill the temp. registers:
4209 pop_set(pushed_regs, 0);
4210 // Increment SP but do not clobber flags.
4211 lea(rsp, Address(rsp, aligned_size));
4212 }
4213
4214 if (temp2_reg_was_valid) {
4215 movq(temp2_reg, 1);
4216 }
4217
4218 jcc(Assembler::notEqual, *L_failure);
4219
4220 if (L_success != &L_fallthrough) {
4221 jmp(*L_success);
4222 }
4223
4224 bind(L_fallthrough);
4225 }
4226
4227 // population_count variant for running without the POPCNT
4228 // instruction, which was introduced with SSE4.2 in 2008.
4229 void MacroAssembler::population_count(Register dst, Register src,
4230 Register scratch1, Register scratch2) {
4231 assert_different_registers(src, scratch1, scratch2);
4232 if (UsePopCountInstruction) {
4233 Assembler::popcntq(dst, src);
4234 } else {
4235 assert_different_registers(src, scratch1, scratch2);
4236 assert_different_registers(dst, scratch1, scratch2);
4237 Label loop, done;
4238
4239 mov(scratch1, src);
4240 // dst = 0;
4241 // while(scratch1 != 0) {
4242 // dst++;
4243 // scratch1 &= (scratch1 - 1);
4244 // }
4245 xorl(dst, dst);
4246 testq(scratch1, scratch1);
4247 jccb(Assembler::equal, done);
4248 {
4249 bind(loop);
4250 incq(dst);
4251 movq(scratch2, scratch1);
4252 decq(scratch2);
4253 andq(scratch1, scratch2);
4254 jccb(Assembler::notEqual, loop);
4255 }
4256 bind(done);
4257 }
4258 #ifdef ASSERT
4259 mov64(scratch1, 0xCafeBabeDeadBeef);
4260 movq(scratch2, scratch1);
4261 #endif
4262 }
4263
4264 // Ensure that the inline code and the stub are using the same registers.
4265 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4266 do { \
4267 assert(r_super_klass == rax, "mismatch"); \
4268 assert(r_array_base == rbx, "mismatch"); \
4269 assert(r_array_length == rcx, "mismatch"); \
4270 assert(r_array_index == rdx, "mismatch"); \
4271 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4272 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4273 assert(result == rdi || result == noreg, "mismatch"); \
4274 } while(0)
4275
4276 // Versions of salq and rorq that don't need count to be in rcx
4277
4278 void MacroAssembler::salq(Register dest, Register count) {
4279 if (count == rcx) {
4280 Assembler::salq(dest);
4281 } else {
4282 assert_different_registers(rcx, dest);
4283 xchgq(rcx, count);
4284 Assembler::salq(dest);
4285 xchgq(rcx, count);
4286 }
4287 }
4288
4289 void MacroAssembler::rorq(Register dest, Register count) {
4290 if (count == rcx) {
4291 Assembler::rorq(dest);
4292 } else {
4293 assert_different_registers(rcx, dest);
4294 xchgq(rcx, count);
4295 Assembler::rorq(dest);
4296 xchgq(rcx, count);
4297 }
4298 }
4299
4300 // Return true: we succeeded in generating this code
4301 //
4302 // At runtime, return 0 in result if r_super_klass is a superclass of
4303 // r_sub_klass, otherwise return nonzero. Use this if you know the
4304 // super_klass_slot of the class you're looking for. This is always
4305 // the case for instanceof and checkcast.
4306 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
4307 Register r_super_klass,
4308 Register temp1,
4309 Register temp2,
4310 Register temp3,
4311 Register temp4,
4312 Register result,
4313 u1 super_klass_slot) {
4314 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4315
4316 Label L_fallthrough, L_success, L_failure;
4317
4318 BLOCK_COMMENT("lookup_secondary_supers_table {");
4319
4320 const Register
4321 r_array_index = temp1,
4322 r_array_length = temp2,
4323 r_array_base = temp3,
4324 r_bitmap = temp4;
4325
4326 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4327
4328 xorq(result, result); // = 0
4329
4330 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4331 movq(r_array_index, r_bitmap);
4332
4333 // First check the bitmap to see if super_klass might be present. If
4334 // the bit is zero, we are certain that super_klass is not one of
4335 // the secondary supers.
4336 u1 bit = super_klass_slot;
4337 {
4338 // NB: If the count in a x86 shift instruction is 0, the flags are
4339 // not affected, so we do a testq instead.
4340 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4341 if (shift_count != 0) {
4342 salq(r_array_index, shift_count);
4343 } else {
4344 testq(r_array_index, r_array_index);
4345 }
4346 }
4347 // We test the MSB of r_array_index, i.e. its sign bit
4348 jcc(Assembler::positive, L_failure);
4349
4350 // Get the first array index that can contain super_klass into r_array_index.
4351 if (bit != 0) {
4352 population_count(r_array_index, r_array_index, temp2, temp3);
4353 } else {
4354 movl(r_array_index, 1);
4355 }
4356 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4357
4358 // We will consult the secondary-super array.
4359 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4360
4361 // We're asserting that the first word in an Array<Klass*> is the
4362 // length, and the second word is the first word of the data. If
4363 // that ever changes, r_array_base will have to be adjusted here.
4364 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4365 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4366
4367 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4368 jccb(Assembler::equal, L_success);
4369
4370 // Is there another entry to check? Consult the bitmap.
4371 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4372 jccb(Assembler::carryClear, L_failure);
4373
4374 // Linear probe. Rotate the bitmap so that the next bit to test is
4375 // in Bit 1.
4376 if (bit != 0) {
4377 rorq(r_bitmap, bit);
4378 }
4379
4380 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4381 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4382 // Kills: r_array_length.
4383 // Returns: result.
4384 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4385 // Result (0/1) is in rdi
4386 jmpb(L_fallthrough);
4387
4388 bind(L_failure);
4389 incq(result); // 0 => 1
4390
4391 bind(L_success);
4392 // result = 0;
4393
4394 bind(L_fallthrough);
4395 BLOCK_COMMENT("} lookup_secondary_supers_table");
4396
4397 if (VerifySecondarySupers) {
4398 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4399 temp1, temp2, temp3);
4400 }
4401 }
4402
4403 // At runtime, return 0 in result if r_super_klass is a superclass of
4404 // r_sub_klass, otherwise return nonzero. Use this version of
4405 // lookup_secondary_supers_table() if you don't know ahead of time
4406 // which superclass will be searched for. Used by interpreter and
4407 // runtime stubs. It is larger and has somewhat greater latency than
4408 // the version above, which takes a constant super_klass_slot.
4409 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
4410 Register r_super_klass,
4411 Register temp1,
4412 Register temp2,
4413 Register temp3,
4414 Register temp4,
4415 Register result) {
4416 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4417 assert_different_registers(r_sub_klass, r_super_klass, rcx);
4418 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
4419
4420 Label L_fallthrough, L_success, L_failure;
4421
4422 BLOCK_COMMENT("lookup_secondary_supers_table {");
4423
4424 RegSetIterator<Register> available_regs = (temps - rcx).begin();
4425
4426 // FIXME. Once we are sure that all paths reaching this point really
4427 // do pass rcx as one of our temps we can get rid of the following
4428 // workaround.
4429 assert(temps.contains(rcx), "fix this code");
4430
4431 // We prefer to have our shift count in rcx. If rcx is one of our
4432 // temps, use it for slot. If not, pick any of our temps.
4433 Register slot;
4434 if (!temps.contains(rcx)) {
4435 slot = *available_regs++;
4436 } else {
4437 slot = rcx;
4438 }
4439
4440 const Register r_array_index = *available_regs++;
4441 const Register r_bitmap = *available_regs++;
4442
4443 // The logic above guarantees this property, but we state it here.
4444 assert_different_registers(r_array_index, r_bitmap, rcx);
4445
4446 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
4447 movq(r_array_index, r_bitmap);
4448
4449 // First check the bitmap to see if super_klass might be present. If
4450 // the bit is zero, we are certain that super_klass is not one of
4451 // the secondary supers.
4452 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4453 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
4454 salq(r_array_index, slot);
4455
4456 testq(r_array_index, r_array_index);
4457 // We test the MSB of r_array_index, i.e. its sign bit
4458 jcc(Assembler::positive, L_failure);
4459
4460 const Register r_array_base = *available_regs++;
4461
4462 // Get the first array index that can contain super_klass into r_array_index.
4463 // Note: Clobbers r_array_base and slot.
4464 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
4465
4466 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4467
4468 // We will consult the secondary-super array.
4469 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4470
4471 // We're asserting that the first word in an Array<Klass*> is the
4472 // length, and the second word is the first word of the data. If
4473 // that ever changes, r_array_base will have to be adjusted here.
4474 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4475 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4476
4477 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4478 jccb(Assembler::equal, L_success);
4479
4480 // Restore slot to its true value
4481 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
4482
4483 // Linear probe. Rotate the bitmap so that the next bit to test is
4484 // in Bit 1.
4485 rorq(r_bitmap, slot);
4486
4487 // Is there another entry to check? Consult the bitmap.
4488 btq(r_bitmap, 1);
4489 jccb(Assembler::carryClear, L_failure);
4490
4491 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4492 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4493 // Kills: r_array_length.
4494 // Returns: result.
4495 lookup_secondary_supers_table_slow_path(r_super_klass,
4496 r_array_base,
4497 r_array_index,
4498 r_bitmap,
4499 /*temp1*/result,
4500 /*temp2*/slot,
4501 &L_success,
4502 nullptr);
4503
4504 bind(L_failure);
4505 movq(result, 1);
4506 jmpb(L_fallthrough);
4507
4508 bind(L_success);
4509 xorq(result, result); // = 0
4510
4511 bind(L_fallthrough);
4512 BLOCK_COMMENT("} lookup_secondary_supers_table");
4513
4514 if (VerifySecondarySupers) {
4515 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4516 temp1, temp2, temp3);
4517 }
4518 }
4519
4520 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4521 Label* L_success, Label* L_failure) {
4522 Label L_loop, L_fallthrough;
4523 {
4524 int label_nulls = 0;
4525 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4526 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4527 assert(label_nulls <= 1, "at most one null in the batch");
4528 }
4529 bind(L_loop);
4530 cmpq(value, Address(addr, count, Address::times_8));
4531 jcc(Assembler::equal, *L_success);
4532 addl(count, 1);
4533 cmpl(count, limit);
4534 jcc(Assembler::less, L_loop);
4535
4536 if (&L_fallthrough != L_failure) {
4537 jmp(*L_failure);
4538 }
4539 bind(L_fallthrough);
4540 }
4541
4542 // Called by code generated by check_klass_subtype_slow_path
4543 // above. This is called when there is a collision in the hashed
4544 // lookup in the secondary supers array.
4545 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4546 Register r_array_base,
4547 Register r_array_index,
4548 Register r_bitmap,
4549 Register temp1,
4550 Register temp2,
4551 Label* L_success,
4552 Label* L_failure) {
4553 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4554
4555 const Register
4556 r_array_length = temp1,
4557 r_sub_klass = noreg,
4558 result = noreg;
4559
4560 Label L_fallthrough;
4561 int label_nulls = 0;
4562 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4563 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4564 assert(label_nulls <= 1, "at most one null in the batch");
4565
4566 // Load the array length.
4567 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4568 // And adjust the array base to point to the data.
4569 // NB! Effectively increments current slot index by 1.
4570 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4571 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4572
4573 // Linear probe
4574 Label L_huge;
4575
4576 // The bitmap is full to bursting.
4577 // Implicit invariant: BITMAP_FULL implies (length > 0)
4578 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
4579 jcc(Assembler::greater, L_huge);
4580
4581 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4582 // current slot (at secondary_supers[r_array_index]) has not yet
4583 // been inspected, and r_array_index may be out of bounds if we
4584 // wrapped around the end of the array.
4585
4586 { // This is conventional linear probing, but instead of terminating
4587 // when a null entry is found in the table, we maintain a bitmap
4588 // in which a 0 indicates missing entries.
4589 // The check above guarantees there are 0s in the bitmap, so the loop
4590 // eventually terminates.
4591
4592 xorl(temp2, temp2); // = 0;
4593
4594 Label L_again;
4595 bind(L_again);
4596
4597 // Check for array wraparound.
4598 cmpl(r_array_index, r_array_length);
4599 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4600
4601 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4602 jcc(Assembler::equal, *L_success);
4603
4604 // If the next bit in bitmap is zero, we're done.
4605 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4606 jcc(Assembler::carryClear, *L_failure);
4607
4608 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4609 addl(r_array_index, 1);
4610
4611 jmp(L_again);
4612 }
4613
4614 { // Degenerate case: more than 64 secondary supers.
4615 // FIXME: We could do something smarter here, maybe a vectorized
4616 // comparison or a binary search, but is that worth any added
4617 // complexity?
4618 bind(L_huge);
4619 xorl(r_array_index, r_array_index); // = 0
4620 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4621 L_success,
4622 (&L_fallthrough != L_failure ? L_failure : nullptr));
4623
4624 bind(L_fallthrough);
4625 }
4626 }
4627
4628 struct VerifyHelperArguments {
4629 Klass* _super;
4630 Klass* _sub;
4631 intptr_t _linear_result;
4632 intptr_t _table_result;
4633 };
4634
4635 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
4636 Klass::on_secondary_supers_verification_failure(args->_super,
4637 args->_sub,
4638 args->_linear_result,
4639 args->_table_result,
4640 msg);
4641 }
4642
4643 // Make sure that the hashed lookup and a linear scan agree.
4644 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
4645 Register r_super_klass,
4646 Register result,
4647 Register temp1,
4648 Register temp2,
4649 Register temp3) {
4650 const Register
4651 r_array_index = temp1,
4652 r_array_length = temp2,
4653 r_array_base = temp3,
4654 r_bitmap = noreg;
4655
4656 BLOCK_COMMENT("verify_secondary_supers_table {");
4657
4658 Label L_success, L_failure, L_check, L_done;
4659
4660 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4661 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4662 // And adjust the array base to point to the data.
4663 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4664
4665 testl(r_array_length, r_array_length); // array_length == 0?
4666 jcc(Assembler::zero, L_failure);
4667
4668 movl(r_array_index, 0);
4669 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
4670 // fall through to L_failure
4671
4672 const Register linear_result = r_array_index; // reuse temp1
4673
4674 bind(L_failure); // not present
4675 movl(linear_result, 1);
4676 jmp(L_check);
4677
4678 bind(L_success); // present
4679 movl(linear_result, 0);
4680
4681 bind(L_check);
4682 cmpl(linear_result, result);
4683 jcc(Assembler::equal, L_done);
4684
4685 { // To avoid calling convention issues, build a record on the stack
4686 // and pass the pointer to that instead.
4687 push(result);
4688 push(linear_result);
4689 push(r_sub_klass);
4690 push(r_super_klass);
4691 movptr(c_rarg1, rsp);
4692 movptr(c_rarg0, (uintptr_t) "mismatch");
4693 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
4694 should_not_reach_here();
4695 }
4696 bind(L_done);
4697
4698 BLOCK_COMMENT("} verify_secondary_supers_table");
4699 }
4700
4701 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
4702
4703 void MacroAssembler::clinit_barrier(Register klass, Label* L_fast_path, Label* L_slow_path) {
4704 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
4705
4706 Label L_fallthrough;
4707 if (L_fast_path == nullptr) {
4708 L_fast_path = &L_fallthrough;
4709 } else if (L_slow_path == nullptr) {
4710 L_slow_path = &L_fallthrough;
4711 }
4712
4713 // Fast path check: class is fully initialized.
4714 // init_state needs acquire, but x86 is TSO, and so we are already good.
4715 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4716 jcc(Assembler::equal, *L_fast_path);
4717
4718 // Fast path check: current thread is initializer thread
4719 cmpptr(r15_thread, Address(klass, InstanceKlass::init_thread_offset()));
4720 if (L_slow_path == &L_fallthrough) {
4721 jcc(Assembler::equal, *L_fast_path);
4722 bind(*L_slow_path);
4723 } else if (L_fast_path == &L_fallthrough) {
4724 jcc(Assembler::notEqual, *L_slow_path);
4725 bind(*L_fast_path);
4726 } else {
4727 Unimplemented();
4728 }
4729 }
4730
4731 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4732 if (VM_Version::supports_cmov()) {
4733 cmovl(cc, dst, src);
4734 } else {
4735 Label L;
4736 jccb(negate_condition(cc), L);
4737 movl(dst, src);
4738 bind(L);
4739 }
4740 }
4741
4742 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4743 if (VM_Version::supports_cmov()) {
4744 cmovl(cc, dst, src);
4745 } else {
4746 Label L;
4747 jccb(negate_condition(cc), L);
4748 movl(dst, src);
4749 bind(L);
4750 }
4751 }
4752
4753 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4754 if (!VerifyOops) return;
4755
4756 BLOCK_COMMENT("verify_oop {");
4757 push(rscratch1);
4758 push(rax); // save rax
4759 push(reg); // pass register argument
4760
4761 // Pass register number to verify_oop_subroutine
4762 const char* b = nullptr;
4763 {
4764 ResourceMark rm;
4765 stringStream ss;
4766 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4767 b = code_string(ss.as_string());
4768 }
4769 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
4770 pushptr(buffer.addr(), rscratch1);
4771
4772 // call indirectly to solve generation ordering problem
4773 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4774 call(rax);
4775 // Caller pops the arguments (oop, message) and restores rax, r10
4776 BLOCK_COMMENT("} verify_oop");
4777 }
4778
4779 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4780 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4781 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
4782 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
4783 vpternlogd(dst, 0xFF, dst, dst, vector_len);
4784 } else if (VM_Version::supports_avx()) {
4785 vpcmpeqd(dst, dst, dst, vector_len);
4786 } else {
4787 pcmpeqd(dst, dst);
4788 }
4789 }
4790
4791 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4792 int extra_slot_offset) {
4793 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4794 int stackElementSize = Interpreter::stackElementSize;
4795 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4796 #ifdef ASSERT
4797 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4798 assert(offset1 - offset == stackElementSize, "correct arithmetic");
4799 #endif
4800 Register scale_reg = noreg;
4801 Address::ScaleFactor scale_factor = Address::no_scale;
4802 if (arg_slot.is_constant()) {
4803 offset += arg_slot.as_constant() * stackElementSize;
4804 } else {
4805 scale_reg = arg_slot.as_register();
4806 scale_factor = Address::times(stackElementSize);
4807 }
4808 offset += wordSize; // return PC is on stack
4809 return Address(rsp, scale_reg, scale_factor, offset);
4810 }
4811
4812 // Handle the receiver type profile update given the "recv" klass.
4813 //
4814 // Normally updates the ReceiverData (RD) that starts at "mdp" + "mdp_offset".
4815 // If there are no matching or claimable receiver entries in RD, updates
4816 // the polymorphic counter.
4817 //
4818 // This code expected to run by either the interpreter or JIT-ed code, without
4819 // extra synchronization. For safety, receiver cells are claimed atomically, which
4820 // avoids grossly misrepresenting the profiles under concurrent updates. For speed,
4821 // counter updates are not atomic.
4822 //
4823 void MacroAssembler::profile_receiver_type(Register recv, Register mdp, int mdp_offset) {
4824 int base_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(0));
4825 int end_receiver_offset = in_bytes(ReceiverTypeData::receiver_offset(ReceiverTypeData::row_limit()));
4826 int poly_count_offset = in_bytes(CounterData::count_offset());
4827 int receiver_step = in_bytes(ReceiverTypeData::receiver_offset(1)) - base_receiver_offset;
4828 int receiver_to_count_step = in_bytes(ReceiverTypeData::receiver_count_offset(0)) - base_receiver_offset;
4829
4830 // Adjust for MDP offsets. Slots are pointer-sized, so is the global offset.
4831 assert(is_aligned(mdp_offset, BytesPerWord), "sanity");
4832 base_receiver_offset += mdp_offset;
4833 end_receiver_offset += mdp_offset;
4834 poly_count_offset += mdp_offset;
4835
4836 // Scale down to optimize encoding. Slots are pointer-sized.
4837 assert(is_aligned(base_receiver_offset, BytesPerWord), "sanity");
4838 assert(is_aligned(end_receiver_offset, BytesPerWord), "sanity");
4839 assert(is_aligned(poly_count_offset, BytesPerWord), "sanity");
4840 assert(is_aligned(receiver_step, BytesPerWord), "sanity");
4841 assert(is_aligned(receiver_to_count_step, BytesPerWord), "sanity");
4842 base_receiver_offset >>= LogBytesPerWord;
4843 end_receiver_offset >>= LogBytesPerWord;
4844 poly_count_offset >>= LogBytesPerWord;
4845 receiver_step >>= LogBytesPerWord;
4846 receiver_to_count_step >>= LogBytesPerWord;
4847
4848 #ifdef ASSERT
4849 // We are about to walk the MDO slots without asking for offsets.
4850 // Check that our math hits all the right spots.
4851 for (uint c = 0; c < ReceiverTypeData::row_limit(); c++) {
4852 int real_recv_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_offset(c));
4853 int real_count_offset = mdp_offset + in_bytes(ReceiverTypeData::receiver_count_offset(c));
4854 int offset = base_receiver_offset + receiver_step*c;
4855 int count_offset = offset + receiver_to_count_step;
4856 assert((offset << LogBytesPerWord) == real_recv_offset, "receiver slot math");
4857 assert((count_offset << LogBytesPerWord) == real_count_offset, "receiver count math");
4858 }
4859 int real_poly_count_offset = mdp_offset + in_bytes(CounterData::count_offset());
4860 assert(poly_count_offset << LogBytesPerWord == real_poly_count_offset, "poly counter math");
4861 #endif
4862
4863 // Corner case: no profile table. Increment poly counter and exit.
4864 if (ReceiverTypeData::row_limit() == 0) {
4865 addptr(Address(mdp, poly_count_offset, Address::times_ptr), DataLayout::counter_increment);
4866 return;
4867 }
4868
4869 Register offset = rscratch1;
4870
4871 Label L_loop_search_receiver, L_loop_search_empty;
4872 Label L_restart, L_found_recv, L_found_empty, L_polymorphic, L_count_update;
4873
4874 // The code here recognizes three major cases:
4875 // A. Fastest: receiver found in the table
4876 // B. Fast: no receiver in the table, and the table is full
4877 // C. Slow: no receiver in the table, free slots in the table
4878 //
4879 // The case A performance is most important, as perfectly-behaved code would end up
4880 // there, especially with larger TypeProfileWidth. The case B performance is
4881 // important as well, this is where bulk of code would land for normally megamorphic
4882 // cases. The case C performance is not essential, its job is to deal with installation
4883 // races, we optimize for code density instead. Case C needs to make sure that receiver
4884 // rows are only claimed once. This makes sure we never overwrite a row for another
4885 // receiver and never duplicate the receivers in the list, making profile type-accurate.
4886 //
4887 // It is very tempting to handle these cases in a single loop, and claim the first slot
4888 // without checking the rest of the table. But, profiling code should tolerate free slots
4889 // in the table, as class unloading can clear them. After such cleanup, the receiver
4890 // we need might be _after_ the free slot. Therefore, we need to let at least full scan
4891 // to complete, before trying to install new slots. Splitting the code in several tight
4892 // loops also helpfully optimizes for cases A and B.
4893 //
4894 // This code is effectively:
4895 //
4896 // restart:
4897 // // Fastest: receiver is already installed
4898 // for (i = 0; i < receiver_count(); i++) {
4899 // if (receiver(i) == recv) goto found_recv(i);
4900 // }
4901 //
4902 // // Fast: no receiver, but profile is full
4903 // for (i = 0; i < receiver_count(); i++) {
4904 // if (receiver(i) == null) goto found_null(i);
4905 // }
4906 // goto polymorphic
4907 //
4908 // // Slow: try to install receiver
4909 // found_null(i):
4910 // CAS(&receiver(i), null, recv);
4911 // goto restart
4912 //
4913 // polymorphic:
4914 // count++;
4915 // return
4916 //
4917 // found_recv(i):
4918 // *receiver_count(i)++
4919 //
4920
4921 bind(L_restart);
4922
4923 // Fastest: receiver is already installed
4924 movptr(offset, base_receiver_offset);
4925 bind(L_loop_search_receiver);
4926 cmpptr(recv, Address(mdp, offset, Address::times_ptr));
4927 jccb(Assembler::equal, L_found_recv);
4928 addptr(offset, receiver_step);
4929 cmpptr(offset, end_receiver_offset);
4930 jccb(Assembler::notEqual, L_loop_search_receiver);
4931
4932 // Fast: no receiver, but profile is full
4933 movptr(offset, base_receiver_offset);
4934 bind(L_loop_search_empty);
4935 cmpptr(Address(mdp, offset, Address::times_ptr), NULL_WORD);
4936 jccb(Assembler::equal, L_found_empty);
4937 addptr(offset, receiver_step);
4938 cmpptr(offset, end_receiver_offset);
4939 jccb(Assembler::notEqual, L_loop_search_empty);
4940 jmpb(L_polymorphic);
4941
4942 // Slow: try to install receiver
4943 bind(L_found_empty);
4944
4945 // Atomically swing receiver slot: null -> recv.
4946 //
4947 // The update code uses CAS, which wants RAX register specifically, *and* it needs
4948 // other important registers untouched, as they form the address. Therefore, we need
4949 // to shift any important registers from RAX into some other spare register. If we
4950 // have a spare register, we are forced to save it on stack here.
4951
4952 Register spare_reg = noreg;
4953 Register shifted_mdp = mdp;
4954 Register shifted_recv = recv;
4955 if (recv == rax || mdp == rax) {
4956 spare_reg = (recv != rbx && mdp != rbx) ? rbx :
4957 (recv != rcx && mdp != rcx) ? rcx :
4958 rdx;
4959 assert_different_registers(mdp, recv, offset, spare_reg);
4960
4961 push(spare_reg);
4962 if (recv == rax) {
4963 movptr(spare_reg, recv);
4964 shifted_recv = spare_reg;
4965 } else {
4966 assert(mdp == rax, "Remaining case");
4967 movptr(spare_reg, mdp);
4968 shifted_mdp = spare_reg;
4969 }
4970 } else {
4971 push(rax);
4972 }
4973
4974 // None of the important registers are in RAX after this shuffle.
4975 assert_different_registers(rax, shifted_mdp, shifted_recv, offset);
4976
4977 xorptr(rax, rax);
4978 cmpxchgptr(shifted_recv, Address(shifted_mdp, offset, Address::times_ptr));
4979
4980 // Unshift registers.
4981 if (recv == rax || mdp == rax) {
4982 movptr(rax, spare_reg);
4983 pop(spare_reg);
4984 } else {
4985 pop(rax);
4986 }
4987
4988 // CAS success means the slot now has the receiver we want. CAS failure means
4989 // something had claimed the slot concurrently: it can be the same receiver we want,
4990 // or something else. Since this is a slow path, we can optimize for code density,
4991 // and just restart the search from the beginning.
4992 jmpb(L_restart);
4993
4994 // Counter updates:
4995
4996 // Increment polymorphic counter instead of receiver slot.
4997 bind(L_polymorphic);
4998 movptr(offset, poly_count_offset);
4999 jmpb(L_count_update);
5000
5001 // Found a receiver, convert its slot offset to corresponding count offset.
5002 bind(L_found_recv);
5003 addptr(offset, receiver_to_count_step);
5004
5005 bind(L_count_update);
5006 addptr(Address(mdp, offset, Address::times_ptr), DataLayout::counter_increment);
5007 }
5008
5009 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5010 if (!VerifyOops) return;
5011
5012 push(rscratch1);
5013 push(rax); // save rax,
5014 // addr may contain rsp so we will have to adjust it based on the push
5015 // we just did (and on 64 bit we do two pushes)
5016 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5017 // stores rax into addr which is backwards of what was intended.
5018 if (addr.uses(rsp)) {
5019 lea(rax, addr);
5020 pushptr(Address(rax, 2 * BytesPerWord));
5021 } else {
5022 pushptr(addr);
5023 }
5024
5025 // Pass register number to verify_oop_subroutine
5026 const char* b = nullptr;
5027 {
5028 ResourceMark rm;
5029 stringStream ss;
5030 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5031 b = code_string(ss.as_string());
5032 }
5033 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5034 pushptr(buffer.addr(), rscratch1);
5035
5036 // call indirectly to solve generation ordering problem
5037 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5038 call(rax);
5039 // Caller pops the arguments (addr, message) and restores rax, r10.
5040 }
5041
5042 void MacroAssembler::verify_tlab() {
5043 #ifdef ASSERT
5044 if (UseTLAB && VerifyOops) {
5045 Label next, ok;
5046 Register t1 = rsi;
5047
5048 push(t1);
5049
5050 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5051 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_start_offset())));
5052 jcc(Assembler::aboveEqual, next);
5053 STOP("assert(top >= start)");
5054 should_not_reach_here();
5055
5056 bind(next);
5057 movptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_end_offset())));
5058 cmpptr(t1, Address(r15_thread, in_bytes(JavaThread::tlab_top_offset())));
5059 jcc(Assembler::aboveEqual, ok);
5060 STOP("assert(top <= end)");
5061 should_not_reach_here();
5062
5063 bind(ok);
5064 pop(t1);
5065 }
5066 #endif
5067 }
5068
5069 class ControlWord {
5070 public:
5071 int32_t _value;
5072
5073 int rounding_control() const { return (_value >> 10) & 3 ; }
5074 int precision_control() const { return (_value >> 8) & 3 ; }
5075 bool precision() const { return ((_value >> 5) & 1) != 0; }
5076 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5077 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5078 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5079 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5080 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5081
5082 void print() const {
5083 // rounding control
5084 const char* rc;
5085 switch (rounding_control()) {
5086 case 0: rc = "round near"; break;
5087 case 1: rc = "round down"; break;
5088 case 2: rc = "round up "; break;
5089 case 3: rc = "chop "; break;
5090 default:
5091 rc = nullptr; // silence compiler warnings
5092 fatal("Unknown rounding control: %d", rounding_control());
5093 };
5094 // precision control
5095 const char* pc;
5096 switch (precision_control()) {
5097 case 0: pc = "24 bits "; break;
5098 case 1: pc = "reserved"; break;
5099 case 2: pc = "53 bits "; break;
5100 case 3: pc = "64 bits "; break;
5101 default:
5102 pc = nullptr; // silence compiler warnings
5103 fatal("Unknown precision control: %d", precision_control());
5104 };
5105 // flags
5106 char f[9];
5107 f[0] = ' ';
5108 f[1] = ' ';
5109 f[2] = (precision ()) ? 'P' : 'p';
5110 f[3] = (underflow ()) ? 'U' : 'u';
5111 f[4] = (overflow ()) ? 'O' : 'o';
5112 f[5] = (zero_divide ()) ? 'Z' : 'z';
5113 f[6] = (denormalized()) ? 'D' : 'd';
5114 f[7] = (invalid ()) ? 'I' : 'i';
5115 f[8] = '\x0';
5116 // output
5117 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5118 }
5119
5120 };
5121
5122 class StatusWord {
5123 public:
5124 int32_t _value;
5125
5126 bool busy() const { return ((_value >> 15) & 1) != 0; }
5127 bool C3() const { return ((_value >> 14) & 1) != 0; }
5128 bool C2() const { return ((_value >> 10) & 1) != 0; }
5129 bool C1() const { return ((_value >> 9) & 1) != 0; }
5130 bool C0() const { return ((_value >> 8) & 1) != 0; }
5131 int top() const { return (_value >> 11) & 7 ; }
5132 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5133 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5134 bool precision() const { return ((_value >> 5) & 1) != 0; }
5135 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5136 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5137 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5138 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5139 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5140
5141 void print() const {
5142 // condition codes
5143 char c[5];
5144 c[0] = (C3()) ? '3' : '-';
5145 c[1] = (C2()) ? '2' : '-';
5146 c[2] = (C1()) ? '1' : '-';
5147 c[3] = (C0()) ? '0' : '-';
5148 c[4] = '\x0';
5149 // flags
5150 char f[9];
5151 f[0] = (error_status()) ? 'E' : '-';
5152 f[1] = (stack_fault ()) ? 'S' : '-';
5153 f[2] = (precision ()) ? 'P' : '-';
5154 f[3] = (underflow ()) ? 'U' : '-';
5155 f[4] = (overflow ()) ? 'O' : '-';
5156 f[5] = (zero_divide ()) ? 'Z' : '-';
5157 f[6] = (denormalized()) ? 'D' : '-';
5158 f[7] = (invalid ()) ? 'I' : '-';
5159 f[8] = '\x0';
5160 // output
5161 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5162 }
5163
5164 };
5165
5166 class TagWord {
5167 public:
5168 int32_t _value;
5169
5170 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5171
5172 void print() const {
5173 printf("%04x", _value & 0xFFFF);
5174 }
5175
5176 };
5177
5178 class FPU_Register {
5179 public:
5180 int32_t _m0;
5181 int32_t _m1;
5182 int16_t _ex;
5183
5184 bool is_indefinite() const {
5185 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5186 }
5187
5188 void print() const {
5189 char sign = (_ex < 0) ? '-' : '+';
5190 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5191 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5192 };
5193
5194 };
5195
5196 class FPU_State {
5197 public:
5198 enum {
5199 register_size = 10,
5200 number_of_registers = 8,
5201 register_mask = 7
5202 };
5203
5204 ControlWord _control_word;
5205 StatusWord _status_word;
5206 TagWord _tag_word;
5207 int32_t _error_offset;
5208 int32_t _error_selector;
5209 int32_t _data_offset;
5210 int32_t _data_selector;
5211 int8_t _register[register_size * number_of_registers];
5212
5213 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5214 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5215
5216 const char* tag_as_string(int tag) const {
5217 switch (tag) {
5218 case 0: return "valid";
5219 case 1: return "zero";
5220 case 2: return "special";
5221 case 3: return "empty";
5222 }
5223 ShouldNotReachHere();
5224 return nullptr;
5225 }
5226
5227 void print() const {
5228 // print computation registers
5229 { int t = _status_word.top();
5230 for (int i = 0; i < number_of_registers; i++) {
5231 int j = (i - t) & register_mask;
5232 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5233 st(j)->print();
5234 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5235 }
5236 }
5237 printf("\n");
5238 // print control registers
5239 printf("ctrl = "); _control_word.print(); printf("\n");
5240 printf("stat = "); _status_word .print(); printf("\n");
5241 printf("tags = "); _tag_word .print(); printf("\n");
5242 }
5243
5244 };
5245
5246 class Flag_Register {
5247 public:
5248 int32_t _value;
5249
5250 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5251 bool direction() const { return ((_value >> 10) & 1) != 0; }
5252 bool sign() const { return ((_value >> 7) & 1) != 0; }
5253 bool zero() const { return ((_value >> 6) & 1) != 0; }
5254 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5255 bool parity() const { return ((_value >> 2) & 1) != 0; }
5256 bool carry() const { return ((_value >> 0) & 1) != 0; }
5257
5258 void print() const {
5259 // flags
5260 char f[8];
5261 f[0] = (overflow ()) ? 'O' : '-';
5262 f[1] = (direction ()) ? 'D' : '-';
5263 f[2] = (sign ()) ? 'S' : '-';
5264 f[3] = (zero ()) ? 'Z' : '-';
5265 f[4] = (auxiliary_carry()) ? 'A' : '-';
5266 f[5] = (parity ()) ? 'P' : '-';
5267 f[6] = (carry ()) ? 'C' : '-';
5268 f[7] = '\x0';
5269 // output
5270 printf("%08x flags = %s", _value, f);
5271 }
5272
5273 };
5274
5275 class IU_Register {
5276 public:
5277 int32_t _value;
5278
5279 void print() const {
5280 printf("%08x %11d", _value, _value);
5281 }
5282
5283 };
5284
5285 class IU_State {
5286 public:
5287 Flag_Register _eflags;
5288 IU_Register _rdi;
5289 IU_Register _rsi;
5290 IU_Register _rbp;
5291 IU_Register _rsp;
5292 IU_Register _rbx;
5293 IU_Register _rdx;
5294 IU_Register _rcx;
5295 IU_Register _rax;
5296
5297 void print() const {
5298 // computation registers
5299 printf("rax, = "); _rax.print(); printf("\n");
5300 printf("rbx, = "); _rbx.print(); printf("\n");
5301 printf("rcx = "); _rcx.print(); printf("\n");
5302 printf("rdx = "); _rdx.print(); printf("\n");
5303 printf("rdi = "); _rdi.print(); printf("\n");
5304 printf("rsi = "); _rsi.print(); printf("\n");
5305 printf("rbp, = "); _rbp.print(); printf("\n");
5306 printf("rsp = "); _rsp.print(); printf("\n");
5307 printf("\n");
5308 // control registers
5309 printf("flgs = "); _eflags.print(); printf("\n");
5310 }
5311 };
5312
5313
5314 class CPU_State {
5315 public:
5316 FPU_State _fpu_state;
5317 IU_State _iu_state;
5318
5319 void print() const {
5320 printf("--------------------------------------------------\n");
5321 _iu_state .print();
5322 printf("\n");
5323 _fpu_state.print();
5324 printf("--------------------------------------------------\n");
5325 }
5326
5327 };
5328
5329
5330 static void _print_CPU_state(CPU_State* state) {
5331 state->print();
5332 };
5333
5334
5335 void MacroAssembler::print_CPU_state() {
5336 push_CPU_state();
5337 push(rsp); // pass CPU state
5338 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5339 addptr(rsp, wordSize); // discard argument
5340 pop_CPU_state();
5341 }
5342
5343 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5344 // Either restore the MXCSR register after returning from the JNI Call
5345 // or verify that it wasn't changed (with -Xcheck:jni flag).
5346 if (VM_Version::supports_sse()) {
5347 if (RestoreMXCSROnJNICalls) {
5348 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5349 } else if (CheckJNICalls) {
5350 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5351 }
5352 }
5353 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5354 vzeroupper();
5355 }
5356
5357 // ((OopHandle)result).resolve();
5358 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5359 assert_different_registers(result, tmp);
5360
5361 // Only 64 bit platforms support GCs that require a tmp register
5362 // Only IN_HEAP loads require a thread_tmp register
5363 // OopHandle::resolve is an indirection like jobject.
5364 access_load_at(T_OBJECT, IN_NATIVE,
5365 result, Address(result, 0), tmp);
5366 }
5367
5368 // ((WeakHandle)result).resolve();
5369 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5370 assert_different_registers(rresult, rtmp);
5371 Label resolved;
5372
5373 // A null weak handle resolves to null.
5374 cmpptr(rresult, 0);
5375 jcc(Assembler::equal, resolved);
5376
5377 // Only 64 bit platforms support GCs that require a tmp register
5378 // Only IN_HEAP loads require a thread_tmp register
5379 // WeakHandle::resolve is an indirection like jweak.
5380 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5381 rresult, Address(rresult, 0), rtmp);
5382 bind(resolved);
5383 }
5384
5385 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5386 // get mirror
5387 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5388 load_method_holder(mirror, method);
5389 movptr(mirror, Address(mirror, mirror_offset));
5390 resolve_oop_handle(mirror, tmp);
5391 }
5392
5393 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5394 load_method_holder(rresult, rmethod);
5395 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5396 }
5397
5398 void MacroAssembler::load_method_holder(Register holder, Register method) {
5399 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5400 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5401 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5402 }
5403
5404 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5405 assert(UseCompactObjectHeaders, "expect compact object headers");
5406 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5407 shrq(dst, markWord::klass_shift);
5408 }
5409
5410 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5411 assert_different_registers(src, tmp);
5412 assert_different_registers(dst, tmp);
5413
5414 if (UseCompactObjectHeaders) {
5415 load_narrow_klass_compact(dst, src);
5416 decode_klass_not_null(dst, tmp);
5417 } else {
5418 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5419 decode_klass_not_null(dst, tmp);
5420 }
5421 }
5422
5423 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5424 assert(!UseCompactObjectHeaders, "not with compact headers");
5425 assert_different_registers(src, tmp);
5426 assert_different_registers(dst, tmp);
5427 encode_klass_not_null(src, tmp);
5428 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5429 }
5430
5431 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5432 if (UseCompactObjectHeaders) {
5433 assert(tmp != noreg, "need tmp");
5434 assert_different_registers(klass, obj, tmp);
5435 load_narrow_klass_compact(tmp, obj);
5436 cmpl(klass, tmp);
5437 } else {
5438 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5439 }
5440 }
5441
5442 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5443 if (UseCompactObjectHeaders) {
5444 assert(tmp2 != noreg, "need tmp2");
5445 assert_different_registers(obj1, obj2, tmp1, tmp2);
5446 load_narrow_klass_compact(tmp1, obj1);
5447 load_narrow_klass_compact(tmp2, obj2);
5448 cmpl(tmp1, tmp2);
5449 } else {
5450 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5451 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
5452 }
5453 }
5454
5455 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5456 Register tmp1) {
5457 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5458 decorators = AccessInternal::decorator_fixup(decorators, type);
5459 bool as_raw = (decorators & AS_RAW) != 0;
5460 if (as_raw) {
5461 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1);
5462 } else {
5463 bs->load_at(this, decorators, type, dst, src, tmp1);
5464 }
5465 }
5466
5467 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5468 Register tmp1, Register tmp2, Register tmp3) {
5469 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5470 decorators = AccessInternal::decorator_fixup(decorators, type);
5471 bool as_raw = (decorators & AS_RAW) != 0;
5472 if (as_raw) {
5473 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5474 } else {
5475 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5476 }
5477 }
5478
5479 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5480 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1);
5481 }
5482
5483 // Doesn't do verification, generates fixed size code
5484 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, DecoratorSet decorators) {
5485 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1);
5486 }
5487
5488 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5489 Register tmp2, Register tmp3, DecoratorSet decorators) {
5490 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5491 }
5492
5493 // Used for storing nulls.
5494 void MacroAssembler::store_heap_oop_null(Address dst) {
5495 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5496 }
5497
5498 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5499 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5500 // Store to klass gap in destination
5501 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5502 }
5503
5504 #ifdef ASSERT
5505 void MacroAssembler::verify_heapbase(const char* msg) {
5506 assert (UseCompressedOops, "should be compressed");
5507 assert (Universe::heap() != nullptr, "java heap should be initialized");
5508 if (CheckCompressedOops) {
5509 Label ok;
5510 ExternalAddress src2(CompressedOops::base_addr());
5511 const bool is_src2_reachable = reachable(src2);
5512 if (!is_src2_reachable) {
5513 push(rscratch1); // cmpptr trashes rscratch1
5514 }
5515 cmpptr(r12_heapbase, src2, rscratch1);
5516 jcc(Assembler::equal, ok);
5517 STOP(msg);
5518 bind(ok);
5519 if (!is_src2_reachable) {
5520 pop(rscratch1);
5521 }
5522 }
5523 }
5524 #endif
5525
5526 // Algorithm must match oop.inline.hpp encode_heap_oop.
5527 void MacroAssembler::encode_heap_oop(Register r) {
5528 #ifdef ASSERT
5529 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5530 #endif
5531 verify_oop_msg(r, "broken oop in encode_heap_oop");
5532 if (CompressedOops::base() == nullptr) {
5533 if (CompressedOops::shift() != 0) {
5534 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5535 shrq(r, LogMinObjAlignmentInBytes);
5536 }
5537 return;
5538 }
5539 testq(r, r);
5540 cmovq(Assembler::equal, r, r12_heapbase);
5541 subq(r, r12_heapbase);
5542 shrq(r, LogMinObjAlignmentInBytes);
5543 }
5544
5545 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5546 #ifdef ASSERT
5547 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5548 if (CheckCompressedOops) {
5549 Label ok;
5550 testq(r, r);
5551 jcc(Assembler::notEqual, ok);
5552 STOP("null oop passed to encode_heap_oop_not_null");
5553 bind(ok);
5554 }
5555 #endif
5556 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5557 if (CompressedOops::base() != nullptr) {
5558 subq(r, r12_heapbase);
5559 }
5560 if (CompressedOops::shift() != 0) {
5561 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5562 shrq(r, LogMinObjAlignmentInBytes);
5563 }
5564 }
5565
5566 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5567 #ifdef ASSERT
5568 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5569 if (CheckCompressedOops) {
5570 Label ok;
5571 testq(src, src);
5572 jcc(Assembler::notEqual, ok);
5573 STOP("null oop passed to encode_heap_oop_not_null2");
5574 bind(ok);
5575 }
5576 #endif
5577 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5578 if (dst != src) {
5579 movq(dst, src);
5580 }
5581 if (CompressedOops::base() != nullptr) {
5582 subq(dst, r12_heapbase);
5583 }
5584 if (CompressedOops::shift() != 0) {
5585 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5586 shrq(dst, LogMinObjAlignmentInBytes);
5587 }
5588 }
5589
5590 void MacroAssembler::decode_heap_oop(Register r) {
5591 #ifdef ASSERT
5592 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5593 #endif
5594 if (CompressedOops::base() == nullptr) {
5595 if (CompressedOops::shift() != 0) {
5596 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5597 shlq(r, LogMinObjAlignmentInBytes);
5598 }
5599 } else {
5600 Label done;
5601 shlq(r, LogMinObjAlignmentInBytes);
5602 jccb(Assembler::equal, done);
5603 addq(r, r12_heapbase);
5604 bind(done);
5605 }
5606 verify_oop_msg(r, "broken oop in decode_heap_oop");
5607 }
5608
5609 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5610 // Note: it will change flags
5611 assert (UseCompressedOops, "should only be used for compressed headers");
5612 assert (Universe::heap() != nullptr, "java heap should be initialized");
5613 // Cannot assert, unverified entry point counts instructions (see .ad file)
5614 // vtableStubs also counts instructions in pd_code_size_limit.
5615 // Also do not verify_oop as this is called by verify_oop.
5616 if (CompressedOops::shift() != 0) {
5617 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5618 shlq(r, LogMinObjAlignmentInBytes);
5619 if (CompressedOops::base() != nullptr) {
5620 addq(r, r12_heapbase);
5621 }
5622 } else {
5623 assert (CompressedOops::base() == nullptr, "sanity");
5624 }
5625 }
5626
5627 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5628 // Note: it will change flags
5629 assert (UseCompressedOops, "should only be used for compressed headers");
5630 assert (Universe::heap() != nullptr, "java heap should be initialized");
5631 // Cannot assert, unverified entry point counts instructions (see .ad file)
5632 // vtableStubs also counts instructions in pd_code_size_limit.
5633 // Also do not verify_oop as this is called by verify_oop.
5634 if (CompressedOops::shift() != 0) {
5635 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5636 if (LogMinObjAlignmentInBytes == Address::times_8) {
5637 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5638 } else {
5639 if (dst != src) {
5640 movq(dst, src);
5641 }
5642 shlq(dst, LogMinObjAlignmentInBytes);
5643 if (CompressedOops::base() != nullptr) {
5644 addq(dst, r12_heapbase);
5645 }
5646 }
5647 } else {
5648 assert (CompressedOops::base() == nullptr, "sanity");
5649 if (dst != src) {
5650 movq(dst, src);
5651 }
5652 }
5653 }
5654
5655 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5656 BLOCK_COMMENT("encode_klass_not_null {");
5657 assert_different_registers(r, tmp);
5658 if (CompressedKlassPointers::base() != nullptr) {
5659 if (AOTCodeCache::is_on_for_dump()) {
5660 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5661 } else {
5662 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5663 }
5664 subq(r, tmp);
5665 }
5666 if (CompressedKlassPointers::shift() != 0) {
5667 shrq(r, CompressedKlassPointers::shift());
5668 }
5669 BLOCK_COMMENT("} encode_klass_not_null");
5670 }
5671
5672 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5673 BLOCK_COMMENT("encode_and_move_klass_not_null {");
5674 assert_different_registers(src, dst);
5675 if (CompressedKlassPointers::base() != nullptr) {
5676 if (AOTCodeCache::is_on_for_dump()) {
5677 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5678 negq(dst);
5679 } else {
5680 movptr(dst, -(intptr_t)CompressedKlassPointers::base());
5681 }
5682 addq(dst, src);
5683 } else {
5684 movptr(dst, src);
5685 }
5686 if (CompressedKlassPointers::shift() != 0) {
5687 shrq(dst, CompressedKlassPointers::shift());
5688 }
5689 BLOCK_COMMENT("} encode_and_move_klass_not_null");
5690 }
5691
5692 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5693 BLOCK_COMMENT("decode_klass_not_null {");
5694 assert_different_registers(r, tmp);
5695 // Note: it will change flags
5696 // Cannot assert, unverified entry point counts instructions (see .ad file)
5697 // vtableStubs also counts instructions in pd_code_size_limit.
5698 // Also do not verify_oop as this is called by verify_oop.
5699 if (CompressedKlassPointers::shift() != 0) {
5700 shlq(r, CompressedKlassPointers::shift());
5701 }
5702 if (CompressedKlassPointers::base() != nullptr) {
5703 if (AOTCodeCache::is_on_for_dump()) {
5704 movptr(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5705 } else {
5706 movptr(tmp, (intptr_t)CompressedKlassPointers::base());
5707 }
5708 addq(r, tmp);
5709 }
5710 BLOCK_COMMENT("} decode_klass_not_null");
5711 }
5712
5713 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5714 BLOCK_COMMENT("decode_and_move_klass_not_null {");
5715 assert_different_registers(src, dst);
5716 // Note: it will change flags
5717 // Cannot assert, unverified entry point counts instructions (see .ad file)
5718 // vtableStubs also counts instructions in pd_code_size_limit.
5719 // Also do not verify_oop as this is called by verify_oop.
5720
5721 if (CompressedKlassPointers::base() == nullptr &&
5722 CompressedKlassPointers::shift() == 0) {
5723 // The best case scenario is that there is no base or shift. Then it is already
5724 // a pointer that needs nothing but a register rename.
5725 movl(dst, src);
5726 } else {
5727 if (CompressedKlassPointers::shift() <= Address::times_8) {
5728 if (CompressedKlassPointers::base() != nullptr) {
5729 if (AOTCodeCache::is_on_for_dump()) {
5730 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5731 } else {
5732 movptr(dst, (intptr_t)CompressedKlassPointers::base());
5733 }
5734 } else {
5735 xorq(dst, dst);
5736 }
5737 if (CompressedKlassPointers::shift() != 0) {
5738 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
5739 leaq(dst, Address(dst, src, Address::times_8, 0));
5740 } else {
5741 addq(dst, src);
5742 }
5743 } else {
5744 if (CompressedKlassPointers::base() != nullptr) {
5745 if (AOTCodeCache::is_on_for_dump()) {
5746 movptr(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5747 shrq(dst, CompressedKlassPointers::shift());
5748 } else {
5749 const intptr_t base_right_shifted =
5750 (intptr_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5751 movptr(dst, base_right_shifted);
5752 }
5753 } else {
5754 xorq(dst, dst);
5755 }
5756 addq(dst, src);
5757 shlq(dst, CompressedKlassPointers::shift());
5758 }
5759 }
5760 BLOCK_COMMENT("} decode_and_move_klass_not_null");
5761 }
5762
5763 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5764 assert (UseCompressedOops, "should only be used for compressed headers");
5765 assert (Universe::heap() != nullptr, "java heap should be initialized");
5766 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5767 int oop_index = oop_recorder()->find_index(obj);
5768 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5769 mov_narrow_oop(dst, oop_index, rspec);
5770 }
5771
5772 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5773 assert (UseCompressedOops, "should only be used for compressed headers");
5774 assert (Universe::heap() != nullptr, "java heap should be initialized");
5775 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5776 int oop_index = oop_recorder()->find_index(obj);
5777 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5778 mov_narrow_oop(dst, oop_index, rspec);
5779 }
5780
5781 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5782 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5783 int klass_index = oop_recorder()->find_index(k);
5784 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5785 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5786 }
5787
5788 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5789 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5790 int klass_index = oop_recorder()->find_index(k);
5791 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5792 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5793 }
5794
5795 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5796 assert (UseCompressedOops, "should only be used for compressed headers");
5797 assert (Universe::heap() != nullptr, "java heap should be initialized");
5798 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5799 int oop_index = oop_recorder()->find_index(obj);
5800 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5801 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5802 }
5803
5804 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5805 assert (UseCompressedOops, "should only be used for compressed headers");
5806 assert (Universe::heap() != nullptr, "java heap should be initialized");
5807 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5808 int oop_index = oop_recorder()->find_index(obj);
5809 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5810 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5811 }
5812
5813 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5814 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5815 int klass_index = oop_recorder()->find_index(k);
5816 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5817 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5818 }
5819
5820 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5821 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5822 int klass_index = oop_recorder()->find_index(k);
5823 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5824 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5825 }
5826
5827 void MacroAssembler::reinit_heapbase() {
5828 if (UseCompressedOops) {
5829 if (Universe::heap() != nullptr && !AOTCodeCache::is_on_for_dump()) {
5830 if (CompressedOops::base() == nullptr) {
5831 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5832 } else {
5833 mov64(r12_heapbase, (int64_t)CompressedOops::base());
5834 }
5835 } else {
5836 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
5837 }
5838 }
5839 }
5840
5841 #if COMPILER2_OR_JVMCI
5842
5843 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
5844 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5845 // cnt - number of qwords (8-byte words).
5846 // base - start address, qword aligned.
5847 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5848 bool use64byteVector = (MaxVectorSize == 64) && (CopyAVX3Threshold == 0);
5849 if (use64byteVector) {
5850 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
5851 } else if (MaxVectorSize >= 32) {
5852 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5853 } else {
5854 pxor(xtmp, xtmp);
5855 }
5856 jmp(L_zero_64_bytes);
5857
5858 BIND(L_loop);
5859 if (MaxVectorSize >= 32) {
5860 fill64(base, 0, xtmp, use64byteVector);
5861 } else {
5862 movdqu(Address(base, 0), xtmp);
5863 movdqu(Address(base, 16), xtmp);
5864 movdqu(Address(base, 32), xtmp);
5865 movdqu(Address(base, 48), xtmp);
5866 }
5867 addptr(base, 64);
5868
5869 BIND(L_zero_64_bytes);
5870 subptr(cnt, 8);
5871 jccb(Assembler::greaterEqual, L_loop);
5872
5873 // Copy trailing 64 bytes
5874 if (use64byteVector) {
5875 addptr(cnt, 8);
5876 jccb(Assembler::equal, L_end);
5877 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
5878 jmp(L_end);
5879 } else {
5880 addptr(cnt, 4);
5881 jccb(Assembler::less, L_tail);
5882 if (MaxVectorSize >= 32) {
5883 vmovdqu(Address(base, 0), xtmp);
5884 } else {
5885 movdqu(Address(base, 0), xtmp);
5886 movdqu(Address(base, 16), xtmp);
5887 }
5888 }
5889 addptr(base, 32);
5890 subptr(cnt, 4);
5891
5892 BIND(L_tail);
5893 addptr(cnt, 4);
5894 jccb(Assembler::lessEqual, L_end);
5895 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
5896 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
5897 } else {
5898 decrement(cnt);
5899
5900 BIND(L_sloop);
5901 movq(Address(base, 0), xtmp);
5902 addptr(base, 8);
5903 decrement(cnt);
5904 jccb(Assembler::greaterEqual, L_sloop);
5905 }
5906 BIND(L_end);
5907 }
5908
5909 // Clearing constant sized memory using YMM/ZMM registers.
5910 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5911 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
5912 bool use64byteVector = (MaxVectorSize > 32) && (CopyAVX3Threshold == 0);
5913
5914 int vector64_count = (cnt & (~0x7)) >> 3;
5915 cnt = cnt & 0x7;
5916 const int fill64_per_loop = 4;
5917 const int max_unrolled_fill64 = 8;
5918
5919 // 64 byte initialization loop.
5920 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
5921 int start64 = 0;
5922 if (vector64_count > max_unrolled_fill64) {
5923 Label LOOP;
5924 Register index = rtmp;
5925
5926 start64 = vector64_count - (vector64_count % fill64_per_loop);
5927
5928 movl(index, 0);
5929 BIND(LOOP);
5930 for (int i = 0; i < fill64_per_loop; i++) {
5931 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
5932 }
5933 addl(index, fill64_per_loop * 64);
5934 cmpl(index, start64 * 64);
5935 jccb(Assembler::less, LOOP);
5936 }
5937 for (int i = start64; i < vector64_count; i++) {
5938 fill64(base, i * 64, xtmp, use64byteVector);
5939 }
5940
5941 // Clear remaining 64 byte tail.
5942 int disp = vector64_count * 64;
5943 if (cnt) {
5944 switch (cnt) {
5945 case 1:
5946 movq(Address(base, disp), xtmp);
5947 break;
5948 case 2:
5949 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
5950 break;
5951 case 3:
5952 movl(rtmp, 0x7);
5953 kmovwl(mask, rtmp);
5954 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
5955 break;
5956 case 4:
5957 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5958 break;
5959 case 5:
5960 if (use64byteVector) {
5961 movl(rtmp, 0x1F);
5962 kmovwl(mask, rtmp);
5963 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
5964 } else {
5965 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5966 movq(Address(base, disp + 32), xtmp);
5967 }
5968 break;
5969 case 6:
5970 if (use64byteVector) {
5971 movl(rtmp, 0x3F);
5972 kmovwl(mask, rtmp);
5973 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
5974 } else {
5975 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5976 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
5977 }
5978 break;
5979 case 7:
5980 if (use64byteVector) {
5981 movl(rtmp, 0x7F);
5982 kmovwl(mask, rtmp);
5983 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
5984 } else {
5985 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
5986 movl(rtmp, 0x7);
5987 kmovwl(mask, rtmp);
5988 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
5989 }
5990 break;
5991 default:
5992 fatal("Unexpected length : %d\n",cnt);
5993 break;
5994 }
5995 }
5996 }
5997
5998 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
5999 bool is_large, KRegister mask) {
6000 // cnt - number of qwords (8-byte words).
6001 // base - start address, qword aligned.
6002 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6003 assert(base==rdi, "base register must be edi for rep stos");
6004 assert(tmp==rax, "tmp register must be eax for rep stos");
6005 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6006 assert(InitArrayShortSize % BytesPerLong == 0,
6007 "InitArrayShortSize should be the multiple of BytesPerLong");
6008
6009 Label DONE;
6010 if (!is_large || !UseXMMForObjInit) {
6011 xorptr(tmp, tmp);
6012 }
6013
6014 if (!is_large) {
6015 Label LOOP, LONG;
6016 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6017 jccb(Assembler::greater, LONG);
6018
6019 decrement(cnt);
6020 jccb(Assembler::negative, DONE); // Zero length
6021
6022 // Use individual pointer-sized stores for small counts:
6023 BIND(LOOP);
6024 movptr(Address(base, cnt, Address::times_ptr), tmp);
6025 decrement(cnt);
6026 jccb(Assembler::greaterEqual, LOOP);
6027 jmpb(DONE);
6028
6029 BIND(LONG);
6030 }
6031
6032 // Use longer rep-prefixed ops for non-small counts:
6033 if (UseFastStosb) {
6034 shlptr(cnt, 3); // convert to number of bytes
6035 rep_stosb();
6036 } else if (UseXMMForObjInit) {
6037 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6038 } else {
6039 rep_stos();
6040 }
6041
6042 BIND(DONE);
6043 }
6044
6045 #endif //COMPILER2_OR_JVMCI
6046
6047
6048 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6049 Register to, Register value, Register count,
6050 Register rtmp, XMMRegister xtmp) {
6051 ShortBranchVerifier sbv(this);
6052 assert_different_registers(to, value, count, rtmp);
6053 Label L_exit;
6054 Label L_fill_2_bytes, L_fill_4_bytes;
6055
6056 #if defined(COMPILER2)
6057 if(MaxVectorSize >=32 &&
6058 VM_Version::supports_avx512vlbw() &&
6059 VM_Version::supports_bmi2()) {
6060 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6061 return;
6062 }
6063 #endif
6064
6065 int shift = -1;
6066 switch (t) {
6067 case T_BYTE:
6068 shift = 2;
6069 break;
6070 case T_SHORT:
6071 shift = 1;
6072 break;
6073 case T_INT:
6074 shift = 0;
6075 break;
6076 default: ShouldNotReachHere();
6077 }
6078
6079 if (t == T_BYTE) {
6080 andl(value, 0xff);
6081 movl(rtmp, value);
6082 shll(rtmp, 8);
6083 orl(value, rtmp);
6084 }
6085 if (t == T_SHORT) {
6086 andl(value, 0xffff);
6087 }
6088 if (t == T_BYTE || t == T_SHORT) {
6089 movl(rtmp, value);
6090 shll(rtmp, 16);
6091 orl(value, rtmp);
6092 }
6093
6094 cmpptr(count, 8 << shift); // Short arrays (< 32 bytes) fill by element
6095 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6096 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6097 Label L_skip_align2;
6098 // align source address at 4 bytes address boundary
6099 if (t == T_BYTE) {
6100 Label L_skip_align1;
6101 // One byte misalignment happens only for byte arrays
6102 testptr(to, 1);
6103 jccb(Assembler::zero, L_skip_align1);
6104 movb(Address(to, 0), value);
6105 increment(to);
6106 decrement(count);
6107 BIND(L_skip_align1);
6108 }
6109 // Two bytes misalignment happens only for byte and short (char) arrays
6110 testptr(to, 2);
6111 jccb(Assembler::zero, L_skip_align2);
6112 movw(Address(to, 0), value);
6113 addptr(to, 2);
6114 subptr(count, 1<<(shift-1));
6115 BIND(L_skip_align2);
6116 }
6117 {
6118 Label L_fill_32_bytes;
6119 if (!UseUnalignedLoadStores) {
6120 // align to 8 bytes, we know we are 4 byte aligned to start
6121 testptr(to, 4);
6122 jccb(Assembler::zero, L_fill_32_bytes);
6123 movl(Address(to, 0), value);
6124 addptr(to, 4);
6125 subptr(count, 1<<shift);
6126 }
6127 BIND(L_fill_32_bytes);
6128 {
6129 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6130 movdl(xtmp, value);
6131 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6132 Label L_check_fill_32_bytes;
6133 if (UseAVX > 2) {
6134 // Fill 64-byte chunks
6135 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6136
6137 // If number of bytes to fill < CopyAVX3Threshold, perform fill using AVX2
6138 cmpptr(count, CopyAVX3Threshold);
6139 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6140
6141 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6142
6143 subptr(count, 16 << shift);
6144 jcc(Assembler::less, L_check_fill_32_bytes);
6145 align(16);
6146
6147 BIND(L_fill_64_bytes_loop_avx3);
6148 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6149 addptr(to, 64);
6150 subptr(count, 16 << shift);
6151 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6152 jmpb(L_check_fill_32_bytes);
6153
6154 BIND(L_check_fill_64_bytes_avx2);
6155 }
6156 // Fill 64-byte chunks
6157 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6158
6159 subptr(count, 16 << shift);
6160 jcc(Assembler::less, L_check_fill_32_bytes);
6161
6162 // align data for 64-byte chunks
6163 Label L_fill_64_bytes_loop, L_align_64_bytes_loop;
6164 if (EnableX86ECoreOpts) {
6165 // align 'big' arrays to cache lines to minimize split_stores
6166 cmpptr(count, 96 << shift);
6167 jcc(Assembler::below, L_fill_64_bytes_loop);
6168
6169 // Find the bytes needed for alignment
6170 movptr(rtmp, to);
6171 andptr(rtmp, 0x1c);
6172 jcc(Assembler::zero, L_fill_64_bytes_loop);
6173 negptr(rtmp); // number of bytes to fill 32-rtmp. it filled by 2 mov by 32
6174 addptr(rtmp, 32);
6175 shrptr(rtmp, 2 - shift);// get number of elements from bytes
6176 subptr(count, rtmp); // adjust count by number of elements
6177
6178 align(16);
6179 BIND(L_align_64_bytes_loop);
6180 movdl(Address(to, 0), xtmp);
6181 addptr(to, 4);
6182 subptr(rtmp, 1 << shift);
6183 jcc(Assembler::greater, L_align_64_bytes_loop);
6184 }
6185
6186 align(16);
6187 BIND(L_fill_64_bytes_loop);
6188 vmovdqu(Address(to, 0), xtmp);
6189 vmovdqu(Address(to, 32), xtmp);
6190 addptr(to, 64);
6191 subptr(count, 16 << shift);
6192 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6193
6194 align(16);
6195 BIND(L_check_fill_32_bytes);
6196 addptr(count, 8 << shift);
6197 jccb(Assembler::less, L_check_fill_8_bytes);
6198 vmovdqu(Address(to, 0), xtmp);
6199 addptr(to, 32);
6200 subptr(count, 8 << shift);
6201
6202 BIND(L_check_fill_8_bytes);
6203 // clean upper bits of YMM registers
6204 movdl(xtmp, value);
6205 pshufd(xtmp, xtmp, 0);
6206 } else {
6207 // Fill 32-byte chunks
6208 pshufd(xtmp, xtmp, 0);
6209
6210 subptr(count, 8 << shift);
6211 jcc(Assembler::less, L_check_fill_8_bytes);
6212 align(16);
6213
6214 BIND(L_fill_32_bytes_loop);
6215
6216 if (UseUnalignedLoadStores) {
6217 movdqu(Address(to, 0), xtmp);
6218 movdqu(Address(to, 16), xtmp);
6219 } else {
6220 movq(Address(to, 0), xtmp);
6221 movq(Address(to, 8), xtmp);
6222 movq(Address(to, 16), xtmp);
6223 movq(Address(to, 24), xtmp);
6224 }
6225
6226 addptr(to, 32);
6227 subptr(count, 8 << shift);
6228 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6229
6230 BIND(L_check_fill_8_bytes);
6231 }
6232 addptr(count, 8 << shift);
6233 jccb(Assembler::zero, L_exit);
6234 jmpb(L_fill_8_bytes);
6235
6236 //
6237 // length is too short, just fill qwords
6238 //
6239 align(16);
6240 BIND(L_fill_8_bytes_loop);
6241 movq(Address(to, 0), xtmp);
6242 addptr(to, 8);
6243 BIND(L_fill_8_bytes);
6244 subptr(count, 1 << (shift + 1));
6245 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6246 }
6247 }
6248
6249 Label L_fill_4_bytes_loop;
6250 testl(count, 1 << shift);
6251 jccb(Assembler::zero, L_fill_2_bytes);
6252
6253 align(16);
6254 BIND(L_fill_4_bytes_loop);
6255 movl(Address(to, 0), value);
6256 addptr(to, 4);
6257
6258 BIND(L_fill_4_bytes);
6259 subptr(count, 1 << shift);
6260 jccb(Assembler::greaterEqual, L_fill_4_bytes_loop);
6261
6262 if (t == T_BYTE || t == T_SHORT) {
6263 Label L_fill_byte;
6264 BIND(L_fill_2_bytes);
6265 // fill trailing 2 bytes
6266 testl(count, 1<<(shift-1));
6267 jccb(Assembler::zero, L_fill_byte);
6268 movw(Address(to, 0), value);
6269 if (t == T_BYTE) {
6270 addptr(to, 2);
6271 BIND(L_fill_byte);
6272 // fill trailing byte
6273 testl(count, 1);
6274 jccb(Assembler::zero, L_exit);
6275 movb(Address(to, 0), value);
6276 } else {
6277 BIND(L_fill_byte);
6278 }
6279 } else {
6280 BIND(L_fill_2_bytes);
6281 }
6282 BIND(L_exit);
6283 }
6284
6285 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6286 switch(type) {
6287 case T_BYTE:
6288 case T_BOOLEAN:
6289 evpbroadcastb(dst, src, vector_len);
6290 break;
6291 case T_SHORT:
6292 case T_CHAR:
6293 evpbroadcastw(dst, src, vector_len);
6294 break;
6295 case T_INT:
6296 case T_FLOAT:
6297 evpbroadcastd(dst, src, vector_len);
6298 break;
6299 case T_LONG:
6300 case T_DOUBLE:
6301 evpbroadcastq(dst, src, vector_len);
6302 break;
6303 default:
6304 fatal("Unhandled type : %s", type2name(type));
6305 break;
6306 }
6307 }
6308
6309 // Encode given char[]/byte[] to byte[] in ISO_8859_1 or ASCII
6310 //
6311 // @IntrinsicCandidate
6312 // int sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(
6313 // char[] sa, int sp, byte[] da, int dp, int len) {
6314 // int i = 0;
6315 // for (; i < len; i++) {
6316 // char c = sa[sp++];
6317 // if (c > '\u00FF')
6318 // break;
6319 // da[dp++] = (byte) c;
6320 // }
6321 // return i;
6322 // }
6323 //
6324 // @IntrinsicCandidate
6325 // int java.lang.StringCoding.encodeISOArray0(
6326 // byte[] sa, int sp, byte[] da, int dp, int len) {
6327 // int i = 0;
6328 // for (; i < len; i++) {
6329 // char c = StringUTF16.getChar(sa, sp++);
6330 // if (c > '\u00FF')
6331 // break;
6332 // da[dp++] = (byte) c;
6333 // }
6334 // return i;
6335 // }
6336 //
6337 // @IntrinsicCandidate
6338 // int java.lang.StringCoding.encodeAsciiArray0(
6339 // char[] sa, int sp, byte[] da, int dp, int len) {
6340 // int i = 0;
6341 // for (; i < len; i++) {
6342 // char c = sa[sp++];
6343 // if (c >= '\u0080')
6344 // break;
6345 // da[dp++] = (byte) c;
6346 // }
6347 // return i;
6348 // }
6349 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6350 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6351 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6352 Register tmp5, Register result, bool ascii) {
6353
6354 // rsi: src
6355 // rdi: dst
6356 // rdx: len
6357 // rcx: tmp5
6358 // rax: result
6359 ShortBranchVerifier sbv(this);
6360 assert_different_registers(src, dst, len, tmp5, result);
6361 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6362
6363 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6364 int short_mask = ascii ? 0xff80 : 0xff00;
6365
6366 // set result
6367 xorl(result, result);
6368 // check for zero length
6369 testl(len, len);
6370 jcc(Assembler::zero, L_done);
6371
6372 movl(result, len);
6373
6374 // Setup pointers
6375 lea(src, Address(src, len, Address::times_2)); // char[]
6376 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6377 negptr(len);
6378
6379 if (UseSSE42Intrinsics || UseAVX >= 2) {
6380 Label L_copy_8_chars, L_copy_8_chars_exit;
6381 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6382
6383 if (UseAVX >= 2) {
6384 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6385 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6386 movdl(tmp1Reg, tmp5);
6387 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6388 jmp(L_chars_32_check);
6389
6390 bind(L_copy_32_chars);
6391 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6392 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6393 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6394 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6395 jccb(Assembler::notZero, L_copy_32_chars_exit);
6396 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6397 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6398 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6399
6400 bind(L_chars_32_check);
6401 addptr(len, 32);
6402 jcc(Assembler::lessEqual, L_copy_32_chars);
6403
6404 bind(L_copy_32_chars_exit);
6405 subptr(len, 16);
6406 jccb(Assembler::greater, L_copy_16_chars_exit);
6407
6408 } else if (UseSSE42Intrinsics) {
6409 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6410 movdl(tmp1Reg, tmp5);
6411 pshufd(tmp1Reg, tmp1Reg, 0);
6412 jmpb(L_chars_16_check);
6413 }
6414
6415 bind(L_copy_16_chars);
6416 if (UseAVX >= 2) {
6417 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6418 vptest(tmp2Reg, tmp1Reg);
6419 jcc(Assembler::notZero, L_copy_16_chars_exit);
6420 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6421 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6422 } else {
6423 if (UseAVX > 0) {
6424 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6425 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6426 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6427 } else {
6428 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6429 por(tmp2Reg, tmp3Reg);
6430 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6431 por(tmp2Reg, tmp4Reg);
6432 }
6433 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6434 jccb(Assembler::notZero, L_copy_16_chars_exit);
6435 packuswb(tmp3Reg, tmp4Reg);
6436 }
6437 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
6438
6439 bind(L_chars_16_check);
6440 addptr(len, 16);
6441 jcc(Assembler::lessEqual, L_copy_16_chars);
6442
6443 bind(L_copy_16_chars_exit);
6444 if (UseAVX >= 2) {
6445 // clean upper bits of YMM registers
6446 vpxor(tmp2Reg, tmp2Reg);
6447 vpxor(tmp3Reg, tmp3Reg);
6448 vpxor(tmp4Reg, tmp4Reg);
6449 movdl(tmp1Reg, tmp5);
6450 pshufd(tmp1Reg, tmp1Reg, 0);
6451 }
6452 subptr(len, 8);
6453 jccb(Assembler::greater, L_copy_8_chars_exit);
6454
6455 bind(L_copy_8_chars);
6456 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
6457 ptest(tmp3Reg, tmp1Reg);
6458 jccb(Assembler::notZero, L_copy_8_chars_exit);
6459 packuswb(tmp3Reg, tmp1Reg);
6460 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
6461 addptr(len, 8);
6462 jccb(Assembler::lessEqual, L_copy_8_chars);
6463
6464 bind(L_copy_8_chars_exit);
6465 subptr(len, 8);
6466 jccb(Assembler::zero, L_done);
6467 }
6468
6469 bind(L_copy_1_char);
6470 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
6471 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
6472 jccb(Assembler::notZero, L_copy_1_char_exit);
6473 movb(Address(dst, len, Address::times_1, 0), tmp5);
6474 addptr(len, 1);
6475 jccb(Assembler::less, L_copy_1_char);
6476
6477 bind(L_copy_1_char_exit);
6478 addptr(result, len); // len is negative count of not processed elements
6479
6480 bind(L_done);
6481 }
6482
6483 /**
6484 * Helper for multiply_to_len().
6485 */
6486 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
6487 addq(dest_lo, src1);
6488 adcq(dest_hi, 0);
6489 addq(dest_lo, src2);
6490 adcq(dest_hi, 0);
6491 }
6492
6493 /**
6494 * Multiply 64 bit by 64 bit first loop.
6495 */
6496 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
6497 Register y, Register y_idx, Register z,
6498 Register carry, Register product,
6499 Register idx, Register kdx) {
6500 //
6501 // jlong carry, x[], y[], z[];
6502 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6503 // huge_128 product = y[idx] * x[xstart] + carry;
6504 // z[kdx] = (jlong)product;
6505 // carry = (jlong)(product >>> 64);
6506 // }
6507 // z[xstart] = carry;
6508 //
6509
6510 Label L_first_loop, L_first_loop_exit;
6511 Label L_one_x, L_one_y, L_multiply;
6512
6513 decrementl(xstart);
6514 jcc(Assembler::negative, L_one_x);
6515
6516 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
6517 rorq(x_xstart, 32); // convert big-endian to little-endian
6518
6519 bind(L_first_loop);
6520 decrementl(idx);
6521 jcc(Assembler::negative, L_first_loop_exit);
6522 decrementl(idx);
6523 jcc(Assembler::negative, L_one_y);
6524 movq(y_idx, Address(y, idx, Address::times_4, 0));
6525 rorq(y_idx, 32); // convert big-endian to little-endian
6526 bind(L_multiply);
6527 movq(product, x_xstart);
6528 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
6529 addq(product, carry);
6530 adcq(rdx, 0);
6531 subl(kdx, 2);
6532 movl(Address(z, kdx, Address::times_4, 4), product);
6533 shrq(product, 32);
6534 movl(Address(z, kdx, Address::times_4, 0), product);
6535 movq(carry, rdx);
6536 jmp(L_first_loop);
6537
6538 bind(L_one_y);
6539 movl(y_idx, Address(y, 0));
6540 jmp(L_multiply);
6541
6542 bind(L_one_x);
6543 movl(x_xstart, Address(x, 0));
6544 jmp(L_first_loop);
6545
6546 bind(L_first_loop_exit);
6547 }
6548
6549 /**
6550 * Multiply 64 bit by 64 bit and add 128 bit.
6551 */
6552 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
6553 Register yz_idx, Register idx,
6554 Register carry, Register product, int offset) {
6555 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
6556 // z[kdx] = (jlong)product;
6557
6558 movq(yz_idx, Address(y, idx, Address::times_4, offset));
6559 rorq(yz_idx, 32); // convert big-endian to little-endian
6560 movq(product, x_xstart);
6561 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6562 movq(yz_idx, Address(z, idx, Address::times_4, offset));
6563 rorq(yz_idx, 32); // convert big-endian to little-endian
6564
6565 add2_with_carry(rdx, product, carry, yz_idx);
6566
6567 movl(Address(z, idx, Address::times_4, offset+4), product);
6568 shrq(product, 32);
6569 movl(Address(z, idx, Address::times_4, offset), product);
6570
6571 }
6572
6573 /**
6574 * Multiply 128 bit by 128 bit. Unrolled inner loop.
6575 */
6576 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
6577 Register yz_idx, Register idx, Register jdx,
6578 Register carry, Register product,
6579 Register carry2) {
6580 // jlong carry, x[], y[], z[];
6581 // int kdx = ystart+1;
6582 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6583 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
6584 // z[kdx+idx+1] = (jlong)product;
6585 // jlong carry2 = (jlong)(product >>> 64);
6586 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
6587 // z[kdx+idx] = (jlong)product;
6588 // carry = (jlong)(product >>> 64);
6589 // }
6590 // idx += 2;
6591 // if (idx > 0) {
6592 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
6593 // z[kdx+idx] = (jlong)product;
6594 // carry = (jlong)(product >>> 64);
6595 // }
6596 //
6597
6598 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6599
6600 movl(jdx, idx);
6601 andl(jdx, 0xFFFFFFFC);
6602 shrl(jdx, 2);
6603
6604 bind(L_third_loop);
6605 subl(jdx, 1);
6606 jcc(Assembler::negative, L_third_loop_exit);
6607 subl(idx, 4);
6608
6609 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
6610 movq(carry2, rdx);
6611
6612 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
6613 movq(carry, rdx);
6614 jmp(L_third_loop);
6615
6616 bind (L_third_loop_exit);
6617
6618 andl (idx, 0x3);
6619 jcc(Assembler::zero, L_post_third_loop_done);
6620
6621 Label L_check_1;
6622 subl(idx, 2);
6623 jcc(Assembler::negative, L_check_1);
6624
6625 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
6626 movq(carry, rdx);
6627
6628 bind (L_check_1);
6629 addl (idx, 0x2);
6630 andl (idx, 0x1);
6631 subl(idx, 1);
6632 jcc(Assembler::negative, L_post_third_loop_done);
6633
6634 movl(yz_idx, Address(y, idx, Address::times_4, 0));
6635 movq(product, x_xstart);
6636 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6637 movl(yz_idx, Address(z, idx, Address::times_4, 0));
6638
6639 add2_with_carry(rdx, product, yz_idx, carry);
6640
6641 movl(Address(z, idx, Address::times_4, 0), product);
6642 shrq(product, 32);
6643
6644 shlq(rdx, 32);
6645 orq(product, rdx);
6646 movq(carry, product);
6647
6648 bind(L_post_third_loop_done);
6649 }
6650
6651 /**
6652 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
6653 *
6654 */
6655 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
6656 Register carry, Register carry2,
6657 Register idx, Register jdx,
6658 Register yz_idx1, Register yz_idx2,
6659 Register tmp, Register tmp3, Register tmp4) {
6660 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
6661
6662 // jlong carry, x[], y[], z[];
6663 // int kdx = ystart+1;
6664 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6665 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
6666 // jlong carry2 = (jlong)(tmp3 >>> 64);
6667 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
6668 // carry = (jlong)(tmp4 >>> 64);
6669 // z[kdx+idx+1] = (jlong)tmp3;
6670 // z[kdx+idx] = (jlong)tmp4;
6671 // }
6672 // idx += 2;
6673 // if (idx > 0) {
6674 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
6675 // z[kdx+idx] = (jlong)yz_idx1;
6676 // carry = (jlong)(yz_idx1 >>> 64);
6677 // }
6678 //
6679
6680 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6681
6682 movl(jdx, idx);
6683 andl(jdx, 0xFFFFFFFC);
6684 shrl(jdx, 2);
6685
6686 bind(L_third_loop);
6687 subl(jdx, 1);
6688 jcc(Assembler::negative, L_third_loop_exit);
6689 subl(idx, 4);
6690
6691 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
6692 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
6693 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
6694 rorxq(yz_idx2, yz_idx2, 32);
6695
6696 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
6697 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
6698
6699 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
6700 rorxq(yz_idx1, yz_idx1, 32);
6701 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
6702 rorxq(yz_idx2, yz_idx2, 32);
6703
6704 if (VM_Version::supports_adx()) {
6705 adcxq(tmp3, carry);
6706 adoxq(tmp3, yz_idx1);
6707
6708 adcxq(tmp4, tmp);
6709 adoxq(tmp4, yz_idx2);
6710
6711 movl(carry, 0); // does not affect flags
6712 adcxq(carry2, carry);
6713 adoxq(carry2, carry);
6714 } else {
6715 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
6716 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
6717 }
6718 movq(carry, carry2);
6719
6720 movl(Address(z, idx, Address::times_4, 12), tmp3);
6721 shrq(tmp3, 32);
6722 movl(Address(z, idx, Address::times_4, 8), tmp3);
6723
6724 movl(Address(z, idx, Address::times_4, 4), tmp4);
6725 shrq(tmp4, 32);
6726 movl(Address(z, idx, Address::times_4, 0), tmp4);
6727
6728 jmp(L_third_loop);
6729
6730 bind (L_third_loop_exit);
6731
6732 andl (idx, 0x3);
6733 jcc(Assembler::zero, L_post_third_loop_done);
6734
6735 Label L_check_1;
6736 subl(idx, 2);
6737 jcc(Assembler::negative, L_check_1);
6738
6739 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
6740 rorxq(yz_idx1, yz_idx1, 32);
6741 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
6742 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
6743 rorxq(yz_idx2, yz_idx2, 32);
6744
6745 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
6746
6747 movl(Address(z, idx, Address::times_4, 4), tmp3);
6748 shrq(tmp3, 32);
6749 movl(Address(z, idx, Address::times_4, 0), tmp3);
6750 movq(carry, tmp4);
6751
6752 bind (L_check_1);
6753 addl (idx, 0x2);
6754 andl (idx, 0x1);
6755 subl(idx, 1);
6756 jcc(Assembler::negative, L_post_third_loop_done);
6757 movl(tmp4, Address(y, idx, Address::times_4, 0));
6758 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
6759 movl(tmp4, Address(z, idx, Address::times_4, 0));
6760
6761 add2_with_carry(carry2, tmp3, tmp4, carry);
6762
6763 movl(Address(z, idx, Address::times_4, 0), tmp3);
6764 shrq(tmp3, 32);
6765
6766 shlq(carry2, 32);
6767 orq(tmp3, carry2);
6768 movq(carry, tmp3);
6769
6770 bind(L_post_third_loop_done);
6771 }
6772
6773 /**
6774 * Code for BigInteger::multiplyToLen() intrinsic.
6775 *
6776 * rdi: x
6777 * rax: xlen
6778 * rsi: y
6779 * rcx: ylen
6780 * r8: z
6781 * r11: tmp0
6782 * r12: tmp1
6783 * r13: tmp2
6784 * r14: tmp3
6785 * r15: tmp4
6786 * rbx: tmp5
6787 *
6788 */
6789 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
6790 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
6791 ShortBranchVerifier sbv(this);
6792 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
6793
6794 push(tmp0);
6795 push(tmp1);
6796 push(tmp2);
6797 push(tmp3);
6798 push(tmp4);
6799 push(tmp5);
6800
6801 push(xlen);
6802
6803 const Register idx = tmp1;
6804 const Register kdx = tmp2;
6805 const Register xstart = tmp3;
6806
6807 const Register y_idx = tmp4;
6808 const Register carry = tmp5;
6809 const Register product = xlen;
6810 const Register x_xstart = tmp0;
6811
6812 // First Loop.
6813 //
6814 // final static long LONG_MASK = 0xffffffffL;
6815 // int xstart = xlen - 1;
6816 // int ystart = ylen - 1;
6817 // long carry = 0;
6818 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6819 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
6820 // z[kdx] = (int)product;
6821 // carry = product >>> 32;
6822 // }
6823 // z[xstart] = (int)carry;
6824 //
6825
6826 movl(idx, ylen); // idx = ylen;
6827 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
6828 xorq(carry, carry); // carry = 0;
6829
6830 Label L_done;
6831
6832 movl(xstart, xlen);
6833 decrementl(xstart);
6834 jcc(Assembler::negative, L_done);
6835
6836 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
6837
6838 Label L_second_loop;
6839 testl(kdx, kdx);
6840 jcc(Assembler::zero, L_second_loop);
6841
6842 Label L_carry;
6843 subl(kdx, 1);
6844 jcc(Assembler::zero, L_carry);
6845
6846 movl(Address(z, kdx, Address::times_4, 0), carry);
6847 shrq(carry, 32);
6848 subl(kdx, 1);
6849
6850 bind(L_carry);
6851 movl(Address(z, kdx, Address::times_4, 0), carry);
6852
6853 // Second and third (nested) loops.
6854 //
6855 // for (int i = xstart-1; i >= 0; i--) { // Second loop
6856 // carry = 0;
6857 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
6858 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
6859 // (z[k] & LONG_MASK) + carry;
6860 // z[k] = (int)product;
6861 // carry = product >>> 32;
6862 // }
6863 // z[i] = (int)carry;
6864 // }
6865 //
6866 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
6867
6868 const Register jdx = tmp1;
6869
6870 bind(L_second_loop);
6871 xorl(carry, carry); // carry = 0;
6872 movl(jdx, ylen); // j = ystart+1
6873
6874 subl(xstart, 1); // i = xstart-1;
6875 jcc(Assembler::negative, L_done);
6876
6877 push (z);
6878
6879 Label L_last_x;
6880 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
6881 subl(xstart, 1); // i = xstart-1;
6882 jcc(Assembler::negative, L_last_x);
6883
6884 if (UseBMI2Instructions) {
6885 movq(rdx, Address(x, xstart, Address::times_4, 0));
6886 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
6887 } else {
6888 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
6889 rorq(x_xstart, 32); // convert big-endian to little-endian
6890 }
6891
6892 Label L_third_loop_prologue;
6893 bind(L_third_loop_prologue);
6894
6895 push (x);
6896 push (xstart);
6897 push (ylen);
6898
6899
6900 if (UseBMI2Instructions) {
6901 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
6902 } else { // !UseBMI2Instructions
6903 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
6904 }
6905
6906 pop(ylen);
6907 pop(xlen);
6908 pop(x);
6909 pop(z);
6910
6911 movl(tmp3, xlen);
6912 addl(tmp3, 1);
6913 movl(Address(z, tmp3, Address::times_4, 0), carry);
6914 subl(tmp3, 1);
6915 jccb(Assembler::negative, L_done);
6916
6917 shrq(carry, 32);
6918 movl(Address(z, tmp3, Address::times_4, 0), carry);
6919 jmp(L_second_loop);
6920
6921 // Next infrequent code is moved outside loops.
6922 bind(L_last_x);
6923 if (UseBMI2Instructions) {
6924 movl(rdx, Address(x, 0));
6925 } else {
6926 movl(x_xstart, Address(x, 0));
6927 }
6928 jmp(L_third_loop_prologue);
6929
6930 bind(L_done);
6931
6932 pop(xlen);
6933
6934 pop(tmp5);
6935 pop(tmp4);
6936 pop(tmp3);
6937 pop(tmp2);
6938 pop(tmp1);
6939 pop(tmp0);
6940 }
6941
6942 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
6943 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
6944 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
6945 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
6946 Label VECTOR8_TAIL, VECTOR4_TAIL;
6947 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
6948 Label SAME_TILL_END, DONE;
6949 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
6950
6951 //scale is in rcx in both Win64 and Unix
6952 ShortBranchVerifier sbv(this);
6953
6954 shlq(length);
6955 xorq(result, result);
6956
6957 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
6958 VM_Version::supports_avx512vlbw()) {
6959 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
6960
6961 cmpq(length, 64);
6962 jcc(Assembler::less, VECTOR32_TAIL);
6963
6964 movq(tmp1, length);
6965 andq(tmp1, 0x3F); // tail count
6966 andq(length, ~(0x3F)); //vector count
6967
6968 bind(VECTOR64_LOOP);
6969 // AVX512 code to compare 64 byte vectors.
6970 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
6971 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
6972 kortestql(k7, k7);
6973 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
6974 addq(result, 64);
6975 subq(length, 64);
6976 jccb(Assembler::notZero, VECTOR64_LOOP);
6977
6978 //bind(VECTOR64_TAIL);
6979 testq(tmp1, tmp1);
6980 jcc(Assembler::zero, SAME_TILL_END);
6981
6982 //bind(VECTOR64_TAIL);
6983 // AVX512 code to compare up to 63 byte vectors.
6984 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
6985 shlxq(tmp2, tmp2, tmp1);
6986 notq(tmp2);
6987 kmovql(k3, tmp2);
6988
6989 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
6990 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
6991
6992 ktestql(k7, k3);
6993 jcc(Assembler::below, SAME_TILL_END); // not mismatch
6994
6995 bind(VECTOR64_NOT_EQUAL);
6996 kmovql(tmp1, k7);
6997 notq(tmp1);
6998 tzcntq(tmp1, tmp1);
6999 addq(result, tmp1);
7000 shrq(result);
7001 jmp(DONE);
7002 bind(VECTOR32_TAIL);
7003 }
7004
7005 cmpq(length, 8);
7006 jcc(Assembler::equal, VECTOR8_LOOP);
7007 jcc(Assembler::less, VECTOR4_TAIL);
7008
7009 if (UseAVX >= 2) {
7010 Label VECTOR16_TAIL, VECTOR32_LOOP;
7011
7012 cmpq(length, 16);
7013 jcc(Assembler::equal, VECTOR16_LOOP);
7014 jcc(Assembler::less, VECTOR8_LOOP);
7015
7016 cmpq(length, 32);
7017 jccb(Assembler::less, VECTOR16_TAIL);
7018
7019 subq(length, 32);
7020 bind(VECTOR32_LOOP);
7021 vmovdqu(rymm0, Address(obja, result));
7022 vmovdqu(rymm1, Address(objb, result));
7023 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7024 vptest(rymm2, rymm2);
7025 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7026 addq(result, 32);
7027 subq(length, 32);
7028 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7029 addq(length, 32);
7030 jcc(Assembler::equal, SAME_TILL_END);
7031 //falling through if less than 32 bytes left //close the branch here.
7032
7033 bind(VECTOR16_TAIL);
7034 cmpq(length, 16);
7035 jccb(Assembler::less, VECTOR8_TAIL);
7036 bind(VECTOR16_LOOP);
7037 movdqu(rymm0, Address(obja, result));
7038 movdqu(rymm1, Address(objb, result));
7039 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7040 ptest(rymm2, rymm2);
7041 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7042 addq(result, 16);
7043 subq(length, 16);
7044 jcc(Assembler::equal, SAME_TILL_END);
7045 //falling through if less than 16 bytes left
7046 } else {//regular intrinsics
7047
7048 cmpq(length, 16);
7049 jccb(Assembler::less, VECTOR8_TAIL);
7050
7051 subq(length, 16);
7052 bind(VECTOR16_LOOP);
7053 movdqu(rymm0, Address(obja, result));
7054 movdqu(rymm1, Address(objb, result));
7055 pxor(rymm0, rymm1);
7056 ptest(rymm0, rymm0);
7057 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7058 addq(result, 16);
7059 subq(length, 16);
7060 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7061 addq(length, 16);
7062 jcc(Assembler::equal, SAME_TILL_END);
7063 //falling through if less than 16 bytes left
7064 }
7065
7066 bind(VECTOR8_TAIL);
7067 cmpq(length, 8);
7068 jccb(Assembler::less, VECTOR4_TAIL);
7069 bind(VECTOR8_LOOP);
7070 movq(tmp1, Address(obja, result));
7071 movq(tmp2, Address(objb, result));
7072 xorq(tmp1, tmp2);
7073 testq(tmp1, tmp1);
7074 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7075 addq(result, 8);
7076 subq(length, 8);
7077 jcc(Assembler::equal, SAME_TILL_END);
7078 //falling through if less than 8 bytes left
7079
7080 bind(VECTOR4_TAIL);
7081 cmpq(length, 4);
7082 jccb(Assembler::less, BYTES_TAIL);
7083 bind(VECTOR4_LOOP);
7084 movl(tmp1, Address(obja, result));
7085 xorl(tmp1, Address(objb, result));
7086 testl(tmp1, tmp1);
7087 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7088 addq(result, 4);
7089 subq(length, 4);
7090 jcc(Assembler::equal, SAME_TILL_END);
7091 //falling through if less than 4 bytes left
7092
7093 bind(BYTES_TAIL);
7094 bind(BYTES_LOOP);
7095 load_unsigned_byte(tmp1, Address(obja, result));
7096 load_unsigned_byte(tmp2, Address(objb, result));
7097 xorl(tmp1, tmp2);
7098 testl(tmp1, tmp1);
7099 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7100 decq(length);
7101 jcc(Assembler::zero, SAME_TILL_END);
7102 incq(result);
7103 load_unsigned_byte(tmp1, Address(obja, result));
7104 load_unsigned_byte(tmp2, Address(objb, result));
7105 xorl(tmp1, tmp2);
7106 testl(tmp1, tmp1);
7107 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7108 decq(length);
7109 jcc(Assembler::zero, SAME_TILL_END);
7110 incq(result);
7111 load_unsigned_byte(tmp1, Address(obja, result));
7112 load_unsigned_byte(tmp2, Address(objb, result));
7113 xorl(tmp1, tmp2);
7114 testl(tmp1, tmp1);
7115 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7116 jmp(SAME_TILL_END);
7117
7118 if (UseAVX >= 2) {
7119 bind(VECTOR32_NOT_EQUAL);
7120 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7121 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7122 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7123 vpmovmskb(tmp1, rymm0);
7124 bsfq(tmp1, tmp1);
7125 addq(result, tmp1);
7126 shrq(result);
7127 jmp(DONE);
7128 }
7129
7130 bind(VECTOR16_NOT_EQUAL);
7131 if (UseAVX >= 2) {
7132 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7133 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7134 pxor(rymm0, rymm2);
7135 } else {
7136 pcmpeqb(rymm2, rymm2);
7137 pxor(rymm0, rymm1);
7138 pcmpeqb(rymm0, rymm1);
7139 pxor(rymm0, rymm2);
7140 }
7141 pmovmskb(tmp1, rymm0);
7142 bsfq(tmp1, tmp1);
7143 addq(result, tmp1);
7144 shrq(result);
7145 jmpb(DONE);
7146
7147 bind(VECTOR8_NOT_EQUAL);
7148 bind(VECTOR4_NOT_EQUAL);
7149 bsfq(tmp1, tmp1);
7150 shrq(tmp1, 3);
7151 addq(result, tmp1);
7152 bind(BYTES_NOT_EQUAL);
7153 shrq(result);
7154 jmpb(DONE);
7155
7156 bind(SAME_TILL_END);
7157 mov64(result, -1);
7158
7159 bind(DONE);
7160 }
7161
7162 //Helper functions for square_to_len()
7163
7164 /**
7165 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7166 * Preserves x and z and modifies rest of the registers.
7167 */
7168 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7169 // Perform square and right shift by 1
7170 // Handle odd xlen case first, then for even xlen do the following
7171 // jlong carry = 0;
7172 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7173 // huge_128 product = x[j:j+1] * x[j:j+1];
7174 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7175 // z[i+2:i+3] = (jlong)(product >>> 1);
7176 // carry = (jlong)product;
7177 // }
7178
7179 xorq(tmp5, tmp5); // carry
7180 xorq(rdxReg, rdxReg);
7181 xorl(tmp1, tmp1); // index for x
7182 xorl(tmp4, tmp4); // index for z
7183
7184 Label L_first_loop, L_first_loop_exit;
7185
7186 testl(xlen, 1);
7187 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7188
7189 // Square and right shift by 1 the odd element using 32 bit multiply
7190 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7191 imulq(raxReg, raxReg);
7192 shrq(raxReg, 1);
7193 adcq(tmp5, 0);
7194 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7195 incrementl(tmp1);
7196 addl(tmp4, 2);
7197
7198 // Square and right shift by 1 the rest using 64 bit multiply
7199 bind(L_first_loop);
7200 cmpptr(tmp1, xlen);
7201 jccb(Assembler::equal, L_first_loop_exit);
7202
7203 // Square
7204 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7205 rorq(raxReg, 32); // convert big-endian to little-endian
7206 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7207
7208 // Right shift by 1 and save carry
7209 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7210 rcrq(rdxReg, 1);
7211 rcrq(raxReg, 1);
7212 adcq(tmp5, 0);
7213
7214 // Store result in z
7215 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7216 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7217
7218 // Update indices for x and z
7219 addl(tmp1, 2);
7220 addl(tmp4, 4);
7221 jmp(L_first_loop);
7222
7223 bind(L_first_loop_exit);
7224 }
7225
7226
7227 /**
7228 * Perform the following multiply add operation using BMI2 instructions
7229 * carry:sum = sum + op1*op2 + carry
7230 * op2 should be in rdx
7231 * op2 is preserved, all other registers are modified
7232 */
7233 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7234 // assert op2 is rdx
7235 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7236 addq(sum, carry);
7237 adcq(tmp2, 0);
7238 addq(sum, op1);
7239 adcq(tmp2, 0);
7240 movq(carry, tmp2);
7241 }
7242
7243 /**
7244 * Perform the following multiply add operation:
7245 * carry:sum = sum + op1*op2 + carry
7246 * Preserves op1, op2 and modifies rest of registers
7247 */
7248 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7249 // rdx:rax = op1 * op2
7250 movq(raxReg, op2);
7251 mulq(op1);
7252
7253 // rdx:rax = sum + carry + rdx:rax
7254 addq(sum, carry);
7255 adcq(rdxReg, 0);
7256 addq(sum, raxReg);
7257 adcq(rdxReg, 0);
7258
7259 // carry:sum = rdx:sum
7260 movq(carry, rdxReg);
7261 }
7262
7263 /**
7264 * Add 64 bit long carry into z[] with carry propagation.
7265 * Preserves z and carry register values and modifies rest of registers.
7266 *
7267 */
7268 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7269 Label L_fourth_loop, L_fourth_loop_exit;
7270
7271 movl(tmp1, 1);
7272 subl(zlen, 2);
7273 addq(Address(z, zlen, Address::times_4, 0), carry);
7274
7275 bind(L_fourth_loop);
7276 jccb(Assembler::carryClear, L_fourth_loop_exit);
7277 subl(zlen, 2);
7278 jccb(Assembler::negative, L_fourth_loop_exit);
7279 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7280 jmp(L_fourth_loop);
7281 bind(L_fourth_loop_exit);
7282 }
7283
7284 /**
7285 * Shift z[] left by 1 bit.
7286 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7287 *
7288 */
7289 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7290
7291 Label L_fifth_loop, L_fifth_loop_exit;
7292
7293 // Fifth loop
7294 // Perform primitiveLeftShift(z, zlen, 1)
7295
7296 const Register prev_carry = tmp1;
7297 const Register new_carry = tmp4;
7298 const Register value = tmp2;
7299 const Register zidx = tmp3;
7300
7301 // int zidx, carry;
7302 // long value;
7303 // carry = 0;
7304 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7305 // (carry:value) = (z[i] << 1) | carry ;
7306 // z[i] = value;
7307 // }
7308
7309 movl(zidx, zlen);
7310 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7311
7312 bind(L_fifth_loop);
7313 decl(zidx); // Use decl to preserve carry flag
7314 decl(zidx);
7315 jccb(Assembler::negative, L_fifth_loop_exit);
7316
7317 if (UseBMI2Instructions) {
7318 movq(value, Address(z, zidx, Address::times_4, 0));
7319 rclq(value, 1);
7320 rorxq(value, value, 32);
7321 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7322 }
7323 else {
7324 // clear new_carry
7325 xorl(new_carry, new_carry);
7326
7327 // Shift z[i] by 1, or in previous carry and save new carry
7328 movq(value, Address(z, zidx, Address::times_4, 0));
7329 shlq(value, 1);
7330 adcl(new_carry, 0);
7331
7332 orq(value, prev_carry);
7333 rorq(value, 0x20);
7334 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7335
7336 // Set previous carry = new carry
7337 movl(prev_carry, new_carry);
7338 }
7339 jmp(L_fifth_loop);
7340
7341 bind(L_fifth_loop_exit);
7342 }
7343
7344
7345 /**
7346 * Code for BigInteger::squareToLen() intrinsic
7347 *
7348 * rdi: x
7349 * rsi: len
7350 * r8: z
7351 * rcx: zlen
7352 * r12: tmp1
7353 * r13: tmp2
7354 * r14: tmp3
7355 * r15: tmp4
7356 * rbx: tmp5
7357 *
7358 */
7359 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7360
7361 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7362 push(tmp1);
7363 push(tmp2);
7364 push(tmp3);
7365 push(tmp4);
7366 push(tmp5);
7367
7368 // First loop
7369 // Store the squares, right shifted one bit (i.e., divided by 2).
7370 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7371
7372 // Add in off-diagonal sums.
7373 //
7374 // Second, third (nested) and fourth loops.
7375 // zlen +=2;
7376 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7377 // carry = 0;
7378 // long op2 = x[xidx:xidx+1];
7379 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7380 // k -= 2;
7381 // long op1 = x[j:j+1];
7382 // long sum = z[k:k+1];
7383 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7384 // z[k:k+1] = sum;
7385 // }
7386 // add_one_64(z, k, carry, tmp_regs);
7387 // }
7388
7389 const Register carry = tmp5;
7390 const Register sum = tmp3;
7391 const Register op1 = tmp4;
7392 Register op2 = tmp2;
7393
7394 push(zlen);
7395 push(len);
7396 addl(zlen,2);
7397 bind(L_second_loop);
7398 xorq(carry, carry);
7399 subl(zlen, 4);
7400 subl(len, 2);
7401 push(zlen);
7402 push(len);
7403 cmpl(len, 0);
7404 jccb(Assembler::lessEqual, L_second_loop_exit);
7405
7406 // Multiply an array by one 64 bit long.
7407 if (UseBMI2Instructions) {
7408 op2 = rdxReg;
7409 movq(op2, Address(x, len, Address::times_4, 0));
7410 rorxq(op2, op2, 32);
7411 }
7412 else {
7413 movq(op2, Address(x, len, Address::times_4, 0));
7414 rorq(op2, 32);
7415 }
7416
7417 bind(L_third_loop);
7418 decrementl(len);
7419 jccb(Assembler::negative, L_third_loop_exit);
7420 decrementl(len);
7421 jccb(Assembler::negative, L_last_x);
7422
7423 movq(op1, Address(x, len, Address::times_4, 0));
7424 rorq(op1, 32);
7425
7426 bind(L_multiply);
7427 subl(zlen, 2);
7428 movq(sum, Address(z, zlen, Address::times_4, 0));
7429
7430 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
7431 if (UseBMI2Instructions) {
7432 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
7433 }
7434 else {
7435 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7436 }
7437
7438 movq(Address(z, zlen, Address::times_4, 0), sum);
7439
7440 jmp(L_third_loop);
7441 bind(L_third_loop_exit);
7442
7443 // Fourth loop
7444 // Add 64 bit long carry into z with carry propagation.
7445 // Uses offsetted zlen.
7446 add_one_64(z, zlen, carry, tmp1);
7447
7448 pop(len);
7449 pop(zlen);
7450 jmp(L_second_loop);
7451
7452 // Next infrequent code is moved outside loops.
7453 bind(L_last_x);
7454 movl(op1, Address(x, 0));
7455 jmp(L_multiply);
7456
7457 bind(L_second_loop_exit);
7458 pop(len);
7459 pop(zlen);
7460 pop(len);
7461 pop(zlen);
7462
7463 // Fifth loop
7464 // Shift z left 1 bit.
7465 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
7466
7467 // z[zlen-1] |= x[len-1] & 1;
7468 movl(tmp3, Address(x, len, Address::times_4, -4));
7469 andl(tmp3, 1);
7470 orl(Address(z, zlen, Address::times_4, -4), tmp3);
7471
7472 pop(tmp5);
7473 pop(tmp4);
7474 pop(tmp3);
7475 pop(tmp2);
7476 pop(tmp1);
7477 }
7478
7479 /**
7480 * Helper function for mul_add()
7481 * Multiply the in[] by int k and add to out[] starting at offset offs using
7482 * 128 bit by 32 bit multiply and return the carry in tmp5.
7483 * Only quad int aligned length of in[] is operated on in this function.
7484 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
7485 * This function preserves out, in and k registers.
7486 * len and offset point to the appropriate index in "in" & "out" correspondingly
7487 * tmp5 has the carry.
7488 * other registers are temporary and are modified.
7489 *
7490 */
7491 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
7492 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
7493 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7494
7495 Label L_first_loop, L_first_loop_exit;
7496
7497 movl(tmp1, len);
7498 shrl(tmp1, 2);
7499
7500 bind(L_first_loop);
7501 subl(tmp1, 1);
7502 jccb(Assembler::negative, L_first_loop_exit);
7503
7504 subl(len, 4);
7505 subl(offset, 4);
7506
7507 Register op2 = tmp2;
7508 const Register sum = tmp3;
7509 const Register op1 = tmp4;
7510 const Register carry = tmp5;
7511
7512 if (UseBMI2Instructions) {
7513 op2 = rdxReg;
7514 }
7515
7516 movq(op1, Address(in, len, Address::times_4, 8));
7517 rorq(op1, 32);
7518 movq(sum, Address(out, offset, Address::times_4, 8));
7519 rorq(sum, 32);
7520 if (UseBMI2Instructions) {
7521 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7522 }
7523 else {
7524 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7525 }
7526 // Store back in big endian from little endian
7527 rorq(sum, 0x20);
7528 movq(Address(out, offset, Address::times_4, 8), sum);
7529
7530 movq(op1, Address(in, len, Address::times_4, 0));
7531 rorq(op1, 32);
7532 movq(sum, Address(out, offset, Address::times_4, 0));
7533 rorq(sum, 32);
7534 if (UseBMI2Instructions) {
7535 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7536 }
7537 else {
7538 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7539 }
7540 // Store back in big endian from little endian
7541 rorq(sum, 0x20);
7542 movq(Address(out, offset, Address::times_4, 0), sum);
7543
7544 jmp(L_first_loop);
7545 bind(L_first_loop_exit);
7546 }
7547
7548 /**
7549 * Code for BigInteger::mulAdd() intrinsic
7550 *
7551 * rdi: out
7552 * rsi: in
7553 * r11: offs (out.length - offset)
7554 * rcx: len
7555 * r8: k
7556 * r12: tmp1
7557 * r13: tmp2
7558 * r14: tmp3
7559 * r15: tmp4
7560 * rbx: tmp5
7561 * Multiply the in[] by word k and add to out[], return the carry in rax
7562 */
7563 void MacroAssembler::mul_add(Register out, Register in, Register offs,
7564 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
7565 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7566
7567 Label L_carry, L_last_in, L_done;
7568
7569 // carry = 0;
7570 // for (int j=len-1; j >= 0; j--) {
7571 // long product = (in[j] & LONG_MASK) * kLong +
7572 // (out[offs] & LONG_MASK) + carry;
7573 // out[offs--] = (int)product;
7574 // carry = product >>> 32;
7575 // }
7576 //
7577 push(tmp1);
7578 push(tmp2);
7579 push(tmp3);
7580 push(tmp4);
7581 push(tmp5);
7582
7583 Register op2 = tmp2;
7584 const Register sum = tmp3;
7585 const Register op1 = tmp4;
7586 const Register carry = tmp5;
7587
7588 if (UseBMI2Instructions) {
7589 op2 = rdxReg;
7590 movl(op2, k);
7591 }
7592 else {
7593 movl(op2, k);
7594 }
7595
7596 xorq(carry, carry);
7597
7598 //First loop
7599
7600 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
7601 //The carry is in tmp5
7602 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
7603
7604 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
7605 decrementl(len);
7606 jccb(Assembler::negative, L_carry);
7607 decrementl(len);
7608 jccb(Assembler::negative, L_last_in);
7609
7610 movq(op1, Address(in, len, Address::times_4, 0));
7611 rorq(op1, 32);
7612
7613 subl(offs, 2);
7614 movq(sum, Address(out, offs, Address::times_4, 0));
7615 rorq(sum, 32);
7616
7617 if (UseBMI2Instructions) {
7618 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7619 }
7620 else {
7621 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7622 }
7623
7624 // Store back in big endian from little endian
7625 rorq(sum, 0x20);
7626 movq(Address(out, offs, Address::times_4, 0), sum);
7627
7628 testl(len, len);
7629 jccb(Assembler::zero, L_carry);
7630
7631 //Multiply the last in[] entry, if any
7632 bind(L_last_in);
7633 movl(op1, Address(in, 0));
7634 movl(sum, Address(out, offs, Address::times_4, -4));
7635
7636 movl(raxReg, k);
7637 mull(op1); //tmp4 * eax -> edx:eax
7638 addl(sum, carry);
7639 adcl(rdxReg, 0);
7640 addl(sum, raxReg);
7641 adcl(rdxReg, 0);
7642 movl(carry, rdxReg);
7643
7644 movl(Address(out, offs, Address::times_4, -4), sum);
7645
7646 bind(L_carry);
7647 //return tmp5/carry as carry in rax
7648 movl(rax, carry);
7649
7650 bind(L_done);
7651 pop(tmp5);
7652 pop(tmp4);
7653 pop(tmp3);
7654 pop(tmp2);
7655 pop(tmp1);
7656 }
7657
7658 /**
7659 * Emits code to update CRC-32 with a byte value according to constants in table
7660 *
7661 * @param [in,out]crc Register containing the crc.
7662 * @param [in]val Register containing the byte to fold into the CRC.
7663 * @param [in]table Register containing the table of crc constants.
7664 *
7665 * uint32_t crc;
7666 * val = crc_table[(val ^ crc) & 0xFF];
7667 * crc = val ^ (crc >> 8);
7668 *
7669 */
7670 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7671 xorl(val, crc);
7672 andl(val, 0xFF);
7673 shrl(crc, 8); // unsigned shift
7674 xorl(crc, Address(table, val, Address::times_4, 0));
7675 }
7676
7677 /**
7678 * Fold 128-bit data chunk
7679 */
7680 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7681 if (UseAVX > 0) {
7682 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7683 vpclmulldq(xcrc, xK, xcrc); // [63:0]
7684 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
7685 pxor(xcrc, xtmp);
7686 } else {
7687 movdqa(xtmp, xcrc);
7688 pclmulhdq(xtmp, xK); // [123:64]
7689 pclmulldq(xcrc, xK); // [63:0]
7690 pxor(xcrc, xtmp);
7691 movdqu(xtmp, Address(buf, offset));
7692 pxor(xcrc, xtmp);
7693 }
7694 }
7695
7696 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7697 if (UseAVX > 0) {
7698 vpclmulhdq(xtmp, xK, xcrc);
7699 vpclmulldq(xcrc, xK, xcrc);
7700 pxor(xcrc, xbuf);
7701 pxor(xcrc, xtmp);
7702 } else {
7703 movdqa(xtmp, xcrc);
7704 pclmulhdq(xtmp, xK);
7705 pclmulldq(xcrc, xK);
7706 pxor(xcrc, xbuf);
7707 pxor(xcrc, xtmp);
7708 }
7709 }
7710
7711 /**
7712 * 8-bit folds to compute 32-bit CRC
7713 *
7714 * uint64_t xcrc;
7715 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7716 */
7717 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7718 movdl(tmp, xcrc);
7719 andl(tmp, 0xFF);
7720 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7721 psrldq(xcrc, 1); // unsigned shift one byte
7722 pxor(xcrc, xtmp);
7723 }
7724
7725 /**
7726 * uint32_t crc;
7727 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7728 */
7729 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7730 movl(tmp, crc);
7731 andl(tmp, 0xFF);
7732 shrl(crc, 8);
7733 xorl(crc, Address(table, tmp, Address::times_4, 0));
7734 }
7735
7736 /**
7737 * @param crc register containing existing CRC (32-bit)
7738 * @param buf register pointing to input byte buffer (byte*)
7739 * @param len register containing number of bytes
7740 * @param table register that will contain address of CRC table
7741 * @param tmp scratch register
7742 */
7743 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7744 assert_different_registers(crc, buf, len, table, tmp, rax);
7745
7746 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7747 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7748
7749 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7750 // context for the registers used, where all instructions below are using 128-bit mode
7751 // On EVEX without VL and BW, these instructions will all be AVX.
7752 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7753 notl(crc); // ~crc
7754 cmpl(len, 16);
7755 jcc(Assembler::less, L_tail);
7756
7757 // Align buffer to 16 bytes
7758 movl(tmp, buf);
7759 andl(tmp, 0xF);
7760 jccb(Assembler::zero, L_aligned);
7761 subl(tmp, 16);
7762 addl(len, tmp);
7763
7764 align(4);
7765 BIND(L_align_loop);
7766 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7767 update_byte_crc32(crc, rax, table);
7768 increment(buf);
7769 incrementl(tmp);
7770 jccb(Assembler::less, L_align_loop);
7771
7772 BIND(L_aligned);
7773 movl(tmp, len); // save
7774 shrl(len, 4);
7775 jcc(Assembler::zero, L_tail_restore);
7776
7777 // Fold crc into first bytes of vector
7778 movdqa(xmm1, Address(buf, 0));
7779 movdl(rax, xmm1);
7780 xorl(crc, rax);
7781 if (VM_Version::supports_sse4_1()) {
7782 pinsrd(xmm1, crc, 0);
7783 } else {
7784 pinsrw(xmm1, crc, 0);
7785 shrl(crc, 16);
7786 pinsrw(xmm1, crc, 1);
7787 }
7788 addptr(buf, 16);
7789 subl(len, 4); // len > 0
7790 jcc(Assembler::less, L_fold_tail);
7791
7792 movdqa(xmm2, Address(buf, 0));
7793 movdqa(xmm3, Address(buf, 16));
7794 movdqa(xmm4, Address(buf, 32));
7795 addptr(buf, 48);
7796 subl(len, 3);
7797 jcc(Assembler::lessEqual, L_fold_512b);
7798
7799 // Fold total 512 bits of polynomial on each iteration,
7800 // 128 bits per each of 4 parallel streams.
7801 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
7802
7803 align32();
7804 BIND(L_fold_512b_loop);
7805 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7806 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7807 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7808 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7809 addptr(buf, 64);
7810 subl(len, 4);
7811 jcc(Assembler::greater, L_fold_512b_loop);
7812
7813 // Fold 512 bits to 128 bits.
7814 BIND(L_fold_512b);
7815 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
7816 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7817 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7818 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7819
7820 // Fold the rest of 128 bits data chunks
7821 BIND(L_fold_tail);
7822 addl(len, 3);
7823 jccb(Assembler::lessEqual, L_fold_128b);
7824 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
7825
7826 BIND(L_fold_tail_loop);
7827 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
7828 addptr(buf, 16);
7829 decrementl(len);
7830 jccb(Assembler::greater, L_fold_tail_loop);
7831
7832 // Fold 128 bits in xmm1 down into 32 bits in crc register.
7833 BIND(L_fold_128b);
7834 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
7835 if (UseAVX > 0) {
7836 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7837 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
7838 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7839 } else {
7840 movdqa(xmm2, xmm0);
7841 pclmulqdq(xmm2, xmm1, 0x1);
7842 movdqa(xmm3, xmm0);
7843 pand(xmm3, xmm2);
7844 pclmulqdq(xmm0, xmm3, 0x1);
7845 }
7846 psrldq(xmm1, 8);
7847 psrldq(xmm2, 4);
7848 pxor(xmm0, xmm1);
7849 pxor(xmm0, xmm2);
7850
7851 // 8 8-bit folds to compute 32-bit CRC.
7852 for (int j = 0; j < 4; j++) {
7853 fold_8bit_crc32(xmm0, table, xmm1, rax);
7854 }
7855 movdl(crc, xmm0); // mov 32 bits to general register
7856 for (int j = 0; j < 4; j++) {
7857 fold_8bit_crc32(crc, table, rax);
7858 }
7859
7860 BIND(L_tail_restore);
7861 movl(len, tmp); // restore
7862 BIND(L_tail);
7863 andl(len, 0xf);
7864 jccb(Assembler::zero, L_exit);
7865
7866 // Fold the rest of bytes
7867 align(4);
7868 BIND(L_tail_loop);
7869 movsbl(rax, Address(buf, 0)); // load byte with sign extension
7870 update_byte_crc32(crc, rax, table);
7871 increment(buf);
7872 decrementl(len);
7873 jccb(Assembler::greater, L_tail_loop);
7874
7875 BIND(L_exit);
7876 notl(crc); // ~c
7877 }
7878
7879 // Helper function for AVX 512 CRC32
7880 // Fold 512-bit data chunks
7881 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
7882 Register pos, int offset) {
7883 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
7884 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
7885 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
7886 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
7887 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
7888 }
7889
7890 // Helper function for AVX 512 CRC32
7891 // Compute CRC32 for < 256B buffers
7892 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
7893 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
7894 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
7895
7896 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
7897 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
7898 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
7899
7900 // check if there is enough buffer to be able to fold 16B at a time
7901 cmpl(len, 32);
7902 jcc(Assembler::less, L_less_than_32);
7903
7904 // if there is, load the constants
7905 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
7906 movdl(xmm0, crc); // get the initial crc value
7907 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7908 pxor(xmm7, xmm0);
7909
7910 // update the buffer pointer
7911 addl(pos, 16);
7912 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
7913 subl(len, 32);
7914 jmp(L_16B_reduction_loop);
7915
7916 bind(L_less_than_32);
7917 //mov initial crc to the return value. this is necessary for zero - length buffers.
7918 movl(rax, crc);
7919 testl(len, len);
7920 jcc(Assembler::equal, L_cleanup);
7921
7922 movdl(xmm0, crc); //get the initial crc value
7923
7924 cmpl(len, 16);
7925 jcc(Assembler::equal, L_exact_16_left);
7926 jcc(Assembler::less, L_less_than_16_left);
7927
7928 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7929 pxor(xmm7, xmm0); //xor the initial crc value
7930 addl(pos, 16);
7931 subl(len, 16);
7932 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
7933 jmp(L_get_last_two_xmms);
7934
7935 bind(L_less_than_16_left);
7936 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
7937 pxor(xmm1, xmm1);
7938 movptr(tmp1, rsp);
7939 movdqu(Address(tmp1, 0 * 16), xmm1);
7940
7941 cmpl(len, 4);
7942 jcc(Assembler::less, L_only_less_than_4);
7943
7944 //backup the counter value
7945 movl(tmp2, len);
7946 cmpl(len, 8);
7947 jcc(Assembler::less, L_less_than_8_left);
7948
7949 //load 8 Bytes
7950 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
7951 movq(Address(tmp1, 0 * 16), rax);
7952 addptr(tmp1, 8);
7953 subl(len, 8);
7954 addl(pos, 8);
7955
7956 bind(L_less_than_8_left);
7957 cmpl(len, 4);
7958 jcc(Assembler::less, L_less_than_4_left);
7959
7960 //load 4 Bytes
7961 movl(rax, Address(buf, pos, Address::times_1, 0));
7962 movl(Address(tmp1, 0 * 16), rax);
7963 addptr(tmp1, 4);
7964 subl(len, 4);
7965 addl(pos, 4);
7966
7967 bind(L_less_than_4_left);
7968 cmpl(len, 2);
7969 jcc(Assembler::less, L_less_than_2_left);
7970
7971 // load 2 Bytes
7972 movw(rax, Address(buf, pos, Address::times_1, 0));
7973 movl(Address(tmp1, 0 * 16), rax);
7974 addptr(tmp1, 2);
7975 subl(len, 2);
7976 addl(pos, 2);
7977
7978 bind(L_less_than_2_left);
7979 cmpl(len, 1);
7980 jcc(Assembler::less, L_zero_left);
7981
7982 // load 1 Byte
7983 movb(rax, Address(buf, pos, Address::times_1, 0));
7984 movb(Address(tmp1, 0 * 16), rax);
7985
7986 bind(L_zero_left);
7987 movdqu(xmm7, Address(rsp, 0));
7988 pxor(xmm7, xmm0); //xor the initial crc value
7989
7990 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7991 movdqu(xmm0, Address(rax, tmp2));
7992 pshufb(xmm7, xmm0);
7993 jmp(L_128_done);
7994
7995 bind(L_exact_16_left);
7996 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
7997 pxor(xmm7, xmm0); //xor the initial crc value
7998 jmp(L_128_done);
7999
8000 bind(L_only_less_than_4);
8001 cmpl(len, 3);
8002 jcc(Assembler::less, L_only_less_than_3);
8003
8004 // load 3 Bytes
8005 movb(rax, Address(buf, pos, Address::times_1, 0));
8006 movb(Address(tmp1, 0), rax);
8007
8008 movb(rax, Address(buf, pos, Address::times_1, 1));
8009 movb(Address(tmp1, 1), rax);
8010
8011 movb(rax, Address(buf, pos, Address::times_1, 2));
8012 movb(Address(tmp1, 2), rax);
8013
8014 movdqu(xmm7, Address(rsp, 0));
8015 pxor(xmm7, xmm0); //xor the initial crc value
8016
8017 pslldq(xmm7, 0x5);
8018 jmp(L_barrett);
8019 bind(L_only_less_than_3);
8020 cmpl(len, 2);
8021 jcc(Assembler::less, L_only_less_than_2);
8022
8023 // load 2 Bytes
8024 movb(rax, Address(buf, pos, Address::times_1, 0));
8025 movb(Address(tmp1, 0), rax);
8026
8027 movb(rax, Address(buf, pos, Address::times_1, 1));
8028 movb(Address(tmp1, 1), rax);
8029
8030 movdqu(xmm7, Address(rsp, 0));
8031 pxor(xmm7, xmm0); //xor the initial crc value
8032
8033 pslldq(xmm7, 0x6);
8034 jmp(L_barrett);
8035
8036 bind(L_only_less_than_2);
8037 //load 1 Byte
8038 movb(rax, Address(buf, pos, Address::times_1, 0));
8039 movb(Address(tmp1, 0), rax);
8040
8041 movdqu(xmm7, Address(rsp, 0));
8042 pxor(xmm7, xmm0); //xor the initial crc value
8043
8044 pslldq(xmm7, 0x7);
8045 }
8046
8047 /**
8048 * Compute CRC32 using AVX512 instructions
8049 * param crc register containing existing CRC (32-bit)
8050 * param buf register pointing to input byte buffer (byte*)
8051 * param len register containing number of bytes
8052 * param table address of crc or crc32c table
8053 * param tmp1 scratch register
8054 * param tmp2 scratch register
8055 * return rax result register
8056 *
8057 * This routine is identical for crc32c with the exception of the precomputed constant
8058 * table which will be passed as the table argument. The calculation steps are
8059 * the same for both variants.
8060 */
8061 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8062 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8063
8064 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8065 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8066 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8067 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8068 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8069
8070 const Register pos = r12;
8071 push(r12);
8072 subptr(rsp, 16 * 2 + 8);
8073
8074 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8075 // context for the registers used, where all instructions below are using 128-bit mode
8076 // On EVEX without VL and BW, these instructions will all be AVX.
8077 movl(pos, 0);
8078
8079 // check if smaller than 256B
8080 cmpl(len, 256);
8081 jcc(Assembler::less, L_less_than_256);
8082
8083 // load the initial crc value
8084 movdl(xmm10, crc);
8085
8086 // receive the initial 64B data, xor the initial crc value
8087 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8088 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8089 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8090 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8091
8092 subl(len, 256);
8093 cmpl(len, 256);
8094 jcc(Assembler::less, L_fold_128_B_loop);
8095
8096 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8097 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8098 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8099 subl(len, 256);
8100
8101 bind(L_fold_256_B_loop);
8102 addl(pos, 256);
8103 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8104 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8105 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8106 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8107
8108 subl(len, 256);
8109 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8110
8111 // Fold 256 into 128
8112 addl(pos, 256);
8113 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8114 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8115 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8116
8117 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8118 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8119 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8120
8121 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8122 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8123
8124 addl(len, 128);
8125 jmp(L_fold_128_B_register);
8126
8127 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8128 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8129
8130 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8131 bind(L_fold_128_B_loop);
8132 addl(pos, 128);
8133 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8134 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8135
8136 subl(len, 128);
8137 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8138
8139 addl(pos, 128);
8140
8141 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8142 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8143 bind(L_fold_128_B_register);
8144 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8145 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8146 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8147 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8148 // save last that has no multiplicand
8149 vextracti64x2(xmm7, xmm4, 3);
8150
8151 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8152 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8153 // Needed later in reduction loop
8154 movdqu(xmm10, Address(table, 1 * 16));
8155 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8156 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8157
8158 // Swap 1,0,3,2 - 01 00 11 10
8159 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8160 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8161 vextracti128(xmm5, xmm8, 1);
8162 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8163
8164 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8165 // instead of a cmp instruction, we use the negative flag with the jl instruction
8166 addl(len, 128 - 16);
8167 jcc(Assembler::less, L_final_reduction_for_128);
8168
8169 bind(L_16B_reduction_loop);
8170 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8171 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8172 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8173 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8174 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8175 addl(pos, 16);
8176 subl(len, 16);
8177 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8178
8179 bind(L_final_reduction_for_128);
8180 addl(len, 16);
8181 jcc(Assembler::equal, L_128_done);
8182
8183 bind(L_get_last_two_xmms);
8184 movdqu(xmm2, xmm7);
8185 addl(pos, len);
8186 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8187 subl(pos, len);
8188
8189 // get rid of the extra data that was loaded before
8190 // load the shift constant
8191 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8192 movdqu(xmm0, Address(rax, len));
8193 addl(rax, len);
8194
8195 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8196 //Change mask to 512
8197 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8198 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8199
8200 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8201 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8202 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8203 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8204 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8205
8206 bind(L_128_done);
8207 // compute crc of a 128-bit value
8208 movdqu(xmm10, Address(table, 3 * 16));
8209 movdqu(xmm0, xmm7);
8210
8211 // 64b fold
8212 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8213 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8214 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8215
8216 // 32b fold
8217 movdqu(xmm0, xmm7);
8218 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8219 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8220 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8221 jmp(L_barrett);
8222
8223 bind(L_less_than_256);
8224 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8225
8226 //barrett reduction
8227 bind(L_barrett);
8228 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8229 movdqu(xmm1, xmm7);
8230 movdqu(xmm2, xmm7);
8231 movdqu(xmm10, Address(table, 4 * 16));
8232
8233 pclmulqdq(xmm7, xmm10, 0x0);
8234 pxor(xmm7, xmm2);
8235 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8236 movdqu(xmm2, xmm7);
8237 pclmulqdq(xmm7, xmm10, 0x10);
8238 pxor(xmm7, xmm2);
8239 pxor(xmm7, xmm1);
8240 pextrd(crc, xmm7, 2);
8241
8242 bind(L_cleanup);
8243 addptr(rsp, 16 * 2 + 8);
8244 pop(r12);
8245 }
8246
8247 // S. Gueron / Information Processing Letters 112 (2012) 184
8248 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8249 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8250 // Output: the 64-bit carry-less product of B * CONST
8251 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8252 Register tmp1, Register tmp2, Register tmp3) {
8253 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8254 if (n > 0) {
8255 addq(tmp3, n * 256 * 8);
8256 }
8257 // Q1 = TABLEExt[n][B & 0xFF];
8258 movl(tmp1, in);
8259 andl(tmp1, 0x000000FF);
8260 shll(tmp1, 3);
8261 addq(tmp1, tmp3);
8262 movq(tmp1, Address(tmp1, 0));
8263
8264 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8265 movl(tmp2, in);
8266 shrl(tmp2, 8);
8267 andl(tmp2, 0x000000FF);
8268 shll(tmp2, 3);
8269 addq(tmp2, tmp3);
8270 movq(tmp2, Address(tmp2, 0));
8271
8272 shlq(tmp2, 8);
8273 xorq(tmp1, tmp2);
8274
8275 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8276 movl(tmp2, in);
8277 shrl(tmp2, 16);
8278 andl(tmp2, 0x000000FF);
8279 shll(tmp2, 3);
8280 addq(tmp2, tmp3);
8281 movq(tmp2, Address(tmp2, 0));
8282
8283 shlq(tmp2, 16);
8284 xorq(tmp1, tmp2);
8285
8286 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8287 shrl(in, 24);
8288 andl(in, 0x000000FF);
8289 shll(in, 3);
8290 addq(in, tmp3);
8291 movq(in, Address(in, 0));
8292
8293 shlq(in, 24);
8294 xorq(in, tmp1);
8295 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8296 }
8297
8298 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8299 Register in_out,
8300 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8301 XMMRegister w_xtmp2,
8302 Register tmp1,
8303 Register n_tmp2, Register n_tmp3) {
8304 if (is_pclmulqdq_supported) {
8305 movdl(w_xtmp1, in_out); // modified blindly
8306
8307 movl(tmp1, const_or_pre_comp_const_index);
8308 movdl(w_xtmp2, tmp1);
8309 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8310
8311 movdq(in_out, w_xtmp1);
8312 } else {
8313 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8314 }
8315 }
8316
8317 // Recombination Alternative 2: No bit-reflections
8318 // T1 = (CRC_A * U1) << 1
8319 // T2 = (CRC_B * U2) << 1
8320 // C1 = T1 >> 32
8321 // C2 = T2 >> 32
8322 // T1 = T1 & 0xFFFFFFFF
8323 // T2 = T2 & 0xFFFFFFFF
8324 // T1 = CRC32(0, T1)
8325 // T2 = CRC32(0, T2)
8326 // C1 = C1 ^ T1
8327 // C2 = C2 ^ T2
8328 // CRC = C1 ^ C2 ^ CRC_C
8329 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8330 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8331 Register tmp1, Register tmp2,
8332 Register n_tmp3) {
8333 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8334 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8335 shlq(in_out, 1);
8336 movl(tmp1, in_out);
8337 shrq(in_out, 32);
8338 xorl(tmp2, tmp2);
8339 crc32(tmp2, tmp1, 4);
8340 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8341 shlq(in1, 1);
8342 movl(tmp1, in1);
8343 shrq(in1, 32);
8344 xorl(tmp2, tmp2);
8345 crc32(tmp2, tmp1, 4);
8346 xorl(in1, tmp2);
8347 xorl(in_out, in1);
8348 xorl(in_out, in2);
8349 }
8350
8351 // Set N to predefined value
8352 // Subtract from a length of a buffer
8353 // execute in a loop:
8354 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8355 // for i = 1 to N do
8356 // CRC_A = CRC32(CRC_A, A[i])
8357 // CRC_B = CRC32(CRC_B, B[i])
8358 // CRC_C = CRC32(CRC_C, C[i])
8359 // end for
8360 // Recombine
8361 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8362 Register in_out1, Register in_out2, Register in_out3,
8363 Register tmp1, Register tmp2, Register tmp3,
8364 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8365 Register tmp4, Register tmp5,
8366 Register n_tmp6) {
8367 Label L_processPartitions;
8368 Label L_processPartition;
8369 Label L_exit;
8370
8371 bind(L_processPartitions);
8372 cmpl(in_out1, 3 * size);
8373 jcc(Assembler::less, L_exit);
8374 xorl(tmp1, tmp1);
8375 xorl(tmp2, tmp2);
8376 movq(tmp3, in_out2);
8377 addq(tmp3, size);
8378
8379 bind(L_processPartition);
8380 crc32(in_out3, Address(in_out2, 0), 8);
8381 crc32(tmp1, Address(in_out2, size), 8);
8382 crc32(tmp2, Address(in_out2, size * 2), 8);
8383 addq(in_out2, 8);
8384 cmpq(in_out2, tmp3);
8385 jcc(Assembler::less, L_processPartition);
8386 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8387 w_xtmp1, w_xtmp2, w_xtmp3,
8388 tmp4, tmp5,
8389 n_tmp6);
8390 addq(in_out2, 2 * size);
8391 subl(in_out1, 3 * size);
8392 jmp(L_processPartitions);
8393
8394 bind(L_exit);
8395 }
8396
8397 // Algorithm 2: Pipelined usage of the CRC32 instruction.
8398 // Input: A buffer I of L bytes.
8399 // Output: the CRC32C value of the buffer.
8400 // Notations:
8401 // Write L = 24N + r, with N = floor (L/24).
8402 // r = L mod 24 (0 <= r < 24).
8403 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
8404 // N quadwords, and R consists of r bytes.
8405 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
8406 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
8407 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
8408 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
8409 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
8410 Register tmp1, Register tmp2, Register tmp3,
8411 Register tmp4, Register tmp5, Register tmp6,
8412 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8413 bool is_pclmulqdq_supported) {
8414 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
8415 Label L_wordByWord;
8416 Label L_byteByByteProlog;
8417 Label L_byteByByte;
8418 Label L_exit;
8419
8420 if (is_pclmulqdq_supported ) {
8421 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
8422 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
8423
8424 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
8425 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
8426
8427 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
8428 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
8429 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
8430 } else {
8431 const_or_pre_comp_const_index[0] = 1;
8432 const_or_pre_comp_const_index[1] = 0;
8433
8434 const_or_pre_comp_const_index[2] = 3;
8435 const_or_pre_comp_const_index[3] = 2;
8436
8437 const_or_pre_comp_const_index[4] = 5;
8438 const_or_pre_comp_const_index[5] = 4;
8439 }
8440 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8441 in2, in1, in_out,
8442 tmp1, tmp2, tmp3,
8443 w_xtmp1, w_xtmp2, w_xtmp3,
8444 tmp4, tmp5,
8445 tmp6);
8446 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8447 in2, in1, in_out,
8448 tmp1, tmp2, tmp3,
8449 w_xtmp1, w_xtmp2, w_xtmp3,
8450 tmp4, tmp5,
8451 tmp6);
8452 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8453 in2, in1, in_out,
8454 tmp1, tmp2, tmp3,
8455 w_xtmp1, w_xtmp2, w_xtmp3,
8456 tmp4, tmp5,
8457 tmp6);
8458 movl(tmp1, in2);
8459 andl(tmp1, 0x00000007);
8460 negl(tmp1);
8461 addl(tmp1, in2);
8462 addq(tmp1, in1);
8463
8464 cmpq(in1, tmp1);
8465 jccb(Assembler::greaterEqual, L_byteByByteProlog);
8466 align(16);
8467 BIND(L_wordByWord);
8468 crc32(in_out, Address(in1, 0), 8);
8469 addq(in1, 8);
8470 cmpq(in1, tmp1);
8471 jcc(Assembler::less, L_wordByWord);
8472
8473 BIND(L_byteByByteProlog);
8474 andl(in2, 0x00000007);
8475 movl(tmp2, 1);
8476
8477 cmpl(tmp2, in2);
8478 jccb(Assembler::greater, L_exit);
8479 BIND(L_byteByByte);
8480 crc32(in_out, Address(in1, 0), 1);
8481 incq(in1);
8482 incl(tmp2);
8483 cmpl(tmp2, in2);
8484 jcc(Assembler::lessEqual, L_byteByByte);
8485
8486 BIND(L_exit);
8487 }
8488 #undef BIND
8489 #undef BLOCK_COMMENT
8490
8491 // Compress char[] array to byte[].
8492 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
8493 // Return the array length if every element in array can be encoded,
8494 // otherwise, the index of first non-latin1 (> 0xff) character.
8495 // @IntrinsicCandidate
8496 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
8497 // for (int i = 0; i < len; i++) {
8498 // char c = src[srcOff];
8499 // if (c > 0xff) {
8500 // return i; // return index of non-latin1 char
8501 // }
8502 // dst[dstOff] = (byte)c;
8503 // srcOff++;
8504 // dstOff++;
8505 // }
8506 // return len;
8507 // }
8508 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
8509 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8510 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8511 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
8512 Label copy_chars_loop, done, reset_sp, copy_tail;
8513
8514 // rsi: src
8515 // rdi: dst
8516 // rdx: len
8517 // rcx: tmp5
8518 // rax: result
8519
8520 // rsi holds start addr of source char[] to be compressed
8521 // rdi holds start addr of destination byte[]
8522 // rdx holds length
8523
8524 assert(len != result, "");
8525
8526 // save length for return
8527 movl(result, len);
8528
8529 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
8530 VM_Version::supports_avx512vlbw() &&
8531 VM_Version::supports_bmi2()) {
8532
8533 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
8534
8535 // alignment
8536 Label post_alignment;
8537
8538 // if length of the string is less than 32, handle it the old fashioned way
8539 testl(len, -32);
8540 jcc(Assembler::zero, below_threshold);
8541
8542 // First check whether a character is compressible ( <= 0xFF).
8543 // Create mask to test for Unicode chars inside zmm vector
8544 movl(tmp5, 0x00FF);
8545 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
8546
8547 testl(len, -64);
8548 jccb(Assembler::zero, post_alignment);
8549
8550 movl(tmp5, dst);
8551 andl(tmp5, (32 - 1));
8552 negl(tmp5);
8553 andl(tmp5, (32 - 1));
8554
8555 // bail out when there is nothing to be done
8556 testl(tmp5, 0xFFFFFFFF);
8557 jccb(Assembler::zero, post_alignment);
8558
8559 // ~(~0 << len), where len is the # of remaining elements to process
8560 movl(len, 0xFFFFFFFF);
8561 shlxl(len, len, tmp5);
8562 notl(len);
8563 kmovdl(mask2, len);
8564 movl(len, result);
8565
8566 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8567 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8568 ktestd(mask1, mask2);
8569 jcc(Assembler::carryClear, copy_tail);
8570
8571 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8572
8573 addptr(src, tmp5);
8574 addptr(src, tmp5);
8575 addptr(dst, tmp5);
8576 subl(len, tmp5);
8577
8578 bind(post_alignment);
8579 // end of alignment
8580
8581 movl(tmp5, len);
8582 andl(tmp5, (32 - 1)); // tail count (in chars)
8583 andl(len, ~(32 - 1)); // vector count (in chars)
8584 jccb(Assembler::zero, copy_loop_tail);
8585
8586 lea(src, Address(src, len, Address::times_2));
8587 lea(dst, Address(dst, len, Address::times_1));
8588 negptr(len);
8589
8590 bind(copy_32_loop);
8591 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
8592 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
8593 kortestdl(mask1, mask1);
8594 jccb(Assembler::carryClear, reset_for_copy_tail);
8595
8596 // All elements in current processed chunk are valid candidates for
8597 // compression. Write a truncated byte elements to the memory.
8598 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
8599 addptr(len, 32);
8600 jccb(Assembler::notZero, copy_32_loop);
8601
8602 bind(copy_loop_tail);
8603 // bail out when there is nothing to be done
8604 testl(tmp5, 0xFFFFFFFF);
8605 jcc(Assembler::zero, done);
8606
8607 movl(len, tmp5);
8608
8609 // ~(~0 << len), where len is the # of remaining elements to process
8610 movl(tmp5, 0xFFFFFFFF);
8611 shlxl(tmp5, tmp5, len);
8612 notl(tmp5);
8613
8614 kmovdl(mask2, tmp5);
8615
8616 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8617 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8618 ktestd(mask1, mask2);
8619 jcc(Assembler::carryClear, copy_tail);
8620
8621 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8622 jmp(done);
8623
8624 bind(reset_for_copy_tail);
8625 lea(src, Address(src, tmp5, Address::times_2));
8626 lea(dst, Address(dst, tmp5, Address::times_1));
8627 subptr(len, tmp5);
8628 jmp(copy_chars_loop);
8629
8630 bind(below_threshold);
8631 }
8632
8633 if (UseSSE42Intrinsics) {
8634 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
8635
8636 // vectored compression
8637 testl(len, 0xfffffff8);
8638 jcc(Assembler::zero, copy_tail);
8639
8640 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
8641 movdl(tmp1Reg, tmp5);
8642 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
8643
8644 andl(len, 0xfffffff0);
8645 jccb(Assembler::zero, copy_16);
8646
8647 // compress 16 chars per iter
8648 pxor(tmp4Reg, tmp4Reg);
8649
8650 lea(src, Address(src, len, Address::times_2));
8651 lea(dst, Address(dst, len, Address::times_1));
8652 negptr(len);
8653
8654 bind(copy_32_loop);
8655 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
8656 por(tmp4Reg, tmp2Reg);
8657 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
8658 por(tmp4Reg, tmp3Reg);
8659 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
8660 jccb(Assembler::notZero, reset_for_copy_tail);
8661 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
8662 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
8663 addptr(len, 16);
8664 jccb(Assembler::notZero, copy_32_loop);
8665
8666 // compress next vector of 8 chars (if any)
8667 bind(copy_16);
8668 // len = 0
8669 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
8670 jccb(Assembler::zero, copy_tail_sse);
8671
8672 pxor(tmp3Reg, tmp3Reg);
8673
8674 movdqu(tmp2Reg, Address(src, 0));
8675 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
8676 jccb(Assembler::notZero, reset_for_copy_tail);
8677 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
8678 movq(Address(dst, 0), tmp2Reg);
8679 addptr(src, 16);
8680 addptr(dst, 8);
8681 jmpb(copy_tail_sse);
8682
8683 bind(reset_for_copy_tail);
8684 movl(tmp5, result);
8685 andl(tmp5, 0x0000000f);
8686 lea(src, Address(src, tmp5, Address::times_2));
8687 lea(dst, Address(dst, tmp5, Address::times_1));
8688 subptr(len, tmp5);
8689 jmpb(copy_chars_loop);
8690
8691 bind(copy_tail_sse);
8692 movl(len, result);
8693 andl(len, 0x00000007); // tail count (in chars)
8694 }
8695 // compress 1 char per iter
8696 bind(copy_tail);
8697 testl(len, len);
8698 jccb(Assembler::zero, done);
8699 lea(src, Address(src, len, Address::times_2));
8700 lea(dst, Address(dst, len, Address::times_1));
8701 negptr(len);
8702
8703 bind(copy_chars_loop);
8704 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
8705 testl(tmp5, 0xff00); // check if Unicode char
8706 jccb(Assembler::notZero, reset_sp);
8707 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
8708 increment(len);
8709 jccb(Assembler::notZero, copy_chars_loop);
8710
8711 // add len then return (len will be zero if compress succeeded, otherwise negative)
8712 bind(reset_sp);
8713 addl(result, len);
8714
8715 bind(done);
8716 }
8717
8718 // Inflate byte[] array to char[].
8719 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
8720 // @IntrinsicCandidate
8721 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
8722 // for (int i = 0; i < len; i++) {
8723 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
8724 // }
8725 // }
8726 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
8727 XMMRegister tmp1, Register tmp2, KRegister mask) {
8728 Label copy_chars_loop, done, below_threshold, avx3_threshold;
8729 // rsi: src
8730 // rdi: dst
8731 // rdx: len
8732 // rcx: tmp2
8733
8734 // rsi holds start addr of source byte[] to be inflated
8735 // rdi holds start addr of destination char[]
8736 // rdx holds length
8737 assert_different_registers(src, dst, len, tmp2);
8738 movl(tmp2, len);
8739 if ((UseAVX > 2) && // AVX512
8740 VM_Version::supports_avx512vlbw() &&
8741 VM_Version::supports_bmi2()) {
8742
8743 Label copy_32_loop, copy_tail;
8744 Register tmp3_aliased = len;
8745
8746 // if length of the string is less than 16, handle it in an old fashioned way
8747 testl(len, -16);
8748 jcc(Assembler::zero, below_threshold);
8749
8750 testl(len, -1 * AVX3Threshold);
8751 jcc(Assembler::zero, avx3_threshold);
8752
8753 // In order to use only one arithmetic operation for the main loop we use
8754 // this pre-calculation
8755 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
8756 andl(len, -32); // vector count
8757 jccb(Assembler::zero, copy_tail);
8758
8759 lea(src, Address(src, len, Address::times_1));
8760 lea(dst, Address(dst, len, Address::times_2));
8761 negptr(len);
8762
8763
8764 // inflate 32 chars per iter
8765 bind(copy_32_loop);
8766 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
8767 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
8768 addptr(len, 32);
8769 jcc(Assembler::notZero, copy_32_loop);
8770
8771 bind(copy_tail);
8772 // bail out when there is nothing to be done
8773 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
8774 jcc(Assembler::zero, done);
8775
8776 // ~(~0 << length), where length is the # of remaining elements to process
8777 movl(tmp3_aliased, -1);
8778 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
8779 notl(tmp3_aliased);
8780 kmovdl(mask, tmp3_aliased);
8781 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
8782 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
8783
8784 jmp(done);
8785 bind(avx3_threshold);
8786 }
8787 if (UseSSE42Intrinsics) {
8788 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
8789
8790 if (UseAVX > 1) {
8791 andl(tmp2, (16 - 1));
8792 andl(len, -16);
8793 jccb(Assembler::zero, copy_new_tail);
8794 } else {
8795 andl(tmp2, 0x00000007); // tail count (in chars)
8796 andl(len, 0xfffffff8); // vector count (in chars)
8797 jccb(Assembler::zero, copy_tail);
8798 }
8799
8800 // vectored inflation
8801 lea(src, Address(src, len, Address::times_1));
8802 lea(dst, Address(dst, len, Address::times_2));
8803 negptr(len);
8804
8805 if (UseAVX > 1) {
8806 bind(copy_16_loop);
8807 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
8808 vmovdqu(Address(dst, len, Address::times_2), tmp1);
8809 addptr(len, 16);
8810 jcc(Assembler::notZero, copy_16_loop);
8811
8812 bind(below_threshold);
8813 bind(copy_new_tail);
8814 movl(len, tmp2);
8815 andl(tmp2, 0x00000007);
8816 andl(len, 0xFFFFFFF8);
8817 jccb(Assembler::zero, copy_tail);
8818
8819 pmovzxbw(tmp1, Address(src, 0));
8820 movdqu(Address(dst, 0), tmp1);
8821 addptr(src, 8);
8822 addptr(dst, 2 * 8);
8823
8824 jmp(copy_tail, true);
8825 }
8826
8827 // inflate 8 chars per iter
8828 bind(copy_8_loop);
8829 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
8830 movdqu(Address(dst, len, Address::times_2), tmp1);
8831 addptr(len, 8);
8832 jcc(Assembler::notZero, copy_8_loop);
8833
8834 bind(copy_tail);
8835 movl(len, tmp2);
8836
8837 cmpl(len, 4);
8838 jccb(Assembler::less, copy_bytes);
8839
8840 movdl(tmp1, Address(src, 0)); // load 4 byte chars
8841 pmovzxbw(tmp1, tmp1);
8842 movq(Address(dst, 0), tmp1);
8843 subptr(len, 4);
8844 addptr(src, 4);
8845 addptr(dst, 8);
8846
8847 bind(copy_bytes);
8848 } else {
8849 bind(below_threshold);
8850 }
8851
8852 testl(len, len);
8853 jccb(Assembler::zero, done);
8854 lea(src, Address(src, len, Address::times_1));
8855 lea(dst, Address(dst, len, Address::times_2));
8856 negptr(len);
8857
8858 // inflate 1 char per iter
8859 bind(copy_chars_loop);
8860 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
8861 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
8862 increment(len);
8863 jcc(Assembler::notZero, copy_chars_loop);
8864
8865 bind(done);
8866 }
8867
8868 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
8869 switch(type) {
8870 case T_BYTE:
8871 case T_BOOLEAN:
8872 evmovdqub(dst, kmask, src, merge, vector_len);
8873 break;
8874 case T_CHAR:
8875 case T_SHORT:
8876 evmovdquw(dst, kmask, src, merge, vector_len);
8877 break;
8878 case T_INT:
8879 case T_FLOAT:
8880 evmovdqul(dst, kmask, src, merge, vector_len);
8881 break;
8882 case T_LONG:
8883 case T_DOUBLE:
8884 evmovdquq(dst, kmask, src, merge, vector_len);
8885 break;
8886 default:
8887 fatal("Unexpected type argument %s", type2name(type));
8888 break;
8889 }
8890 }
8891
8892
8893 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
8894 switch(type) {
8895 case T_BYTE:
8896 case T_BOOLEAN:
8897 evmovdqub(dst, kmask, src, merge, vector_len);
8898 break;
8899 case T_CHAR:
8900 case T_SHORT:
8901 evmovdquw(dst, kmask, src, merge, vector_len);
8902 break;
8903 case T_INT:
8904 case T_FLOAT:
8905 evmovdqul(dst, kmask, src, merge, vector_len);
8906 break;
8907 case T_LONG:
8908 case T_DOUBLE:
8909 evmovdquq(dst, kmask, src, merge, vector_len);
8910 break;
8911 default:
8912 fatal("Unexpected type argument %s", type2name(type));
8913 break;
8914 }
8915 }
8916
8917 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
8918 switch(type) {
8919 case T_BYTE:
8920 case T_BOOLEAN:
8921 evmovdqub(dst, kmask, src, merge, vector_len);
8922 break;
8923 case T_CHAR:
8924 case T_SHORT:
8925 evmovdquw(dst, kmask, src, merge, vector_len);
8926 break;
8927 case T_INT:
8928 case T_FLOAT:
8929 evmovdqul(dst, kmask, src, merge, vector_len);
8930 break;
8931 case T_LONG:
8932 case T_DOUBLE:
8933 evmovdquq(dst, kmask, src, merge, vector_len);
8934 break;
8935 default:
8936 fatal("Unexpected type argument %s", type2name(type));
8937 break;
8938 }
8939 }
8940
8941 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
8942 switch(masklen) {
8943 case 2:
8944 knotbl(dst, src);
8945 movl(rtmp, 3);
8946 kmovbl(ktmp, rtmp);
8947 kandbl(dst, ktmp, dst);
8948 break;
8949 case 4:
8950 knotbl(dst, src);
8951 movl(rtmp, 15);
8952 kmovbl(ktmp, rtmp);
8953 kandbl(dst, ktmp, dst);
8954 break;
8955 case 8:
8956 knotbl(dst, src);
8957 break;
8958 case 16:
8959 knotwl(dst, src);
8960 break;
8961 case 32:
8962 knotdl(dst, src);
8963 break;
8964 case 64:
8965 knotql(dst, src);
8966 break;
8967 default:
8968 fatal("Unexpected vector length %d", masklen);
8969 break;
8970 }
8971 }
8972
8973 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8974 switch(type) {
8975 case T_BOOLEAN:
8976 case T_BYTE:
8977 kandbl(dst, src1, src2);
8978 break;
8979 case T_CHAR:
8980 case T_SHORT:
8981 kandwl(dst, src1, src2);
8982 break;
8983 case T_INT:
8984 case T_FLOAT:
8985 kanddl(dst, src1, src2);
8986 break;
8987 case T_LONG:
8988 case T_DOUBLE:
8989 kandql(dst, src1, src2);
8990 break;
8991 default:
8992 fatal("Unexpected type argument %s", type2name(type));
8993 break;
8994 }
8995 }
8996
8997 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8998 switch(type) {
8999 case T_BOOLEAN:
9000 case T_BYTE:
9001 korbl(dst, src1, src2);
9002 break;
9003 case T_CHAR:
9004 case T_SHORT:
9005 korwl(dst, src1, src2);
9006 break;
9007 case T_INT:
9008 case T_FLOAT:
9009 kordl(dst, src1, src2);
9010 break;
9011 case T_LONG:
9012 case T_DOUBLE:
9013 korql(dst, src1, src2);
9014 break;
9015 default:
9016 fatal("Unexpected type argument %s", type2name(type));
9017 break;
9018 }
9019 }
9020
9021 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9022 switch(type) {
9023 case T_BOOLEAN:
9024 case T_BYTE:
9025 kxorbl(dst, src1, src2);
9026 break;
9027 case T_CHAR:
9028 case T_SHORT:
9029 kxorwl(dst, src1, src2);
9030 break;
9031 case T_INT:
9032 case T_FLOAT:
9033 kxordl(dst, src1, src2);
9034 break;
9035 case T_LONG:
9036 case T_DOUBLE:
9037 kxorql(dst, src1, src2);
9038 break;
9039 default:
9040 fatal("Unexpected type argument %s", type2name(type));
9041 break;
9042 }
9043 }
9044
9045 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9046 switch(type) {
9047 case T_BOOLEAN:
9048 case T_BYTE:
9049 evpermb(dst, mask, nds, src, merge, vector_len); break;
9050 case T_CHAR:
9051 case T_SHORT:
9052 evpermw(dst, mask, nds, src, merge, vector_len); break;
9053 case T_INT:
9054 case T_FLOAT:
9055 evpermd(dst, mask, nds, src, merge, vector_len); break;
9056 case T_LONG:
9057 case T_DOUBLE:
9058 evpermq(dst, mask, nds, src, merge, vector_len); break;
9059 default:
9060 fatal("Unexpected type argument %s", type2name(type)); break;
9061 }
9062 }
9063
9064 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9065 switch(type) {
9066 case T_BOOLEAN:
9067 case T_BYTE:
9068 evpermb(dst, mask, nds, src, merge, vector_len); break;
9069 case T_CHAR:
9070 case T_SHORT:
9071 evpermw(dst, mask, nds, src, merge, vector_len); break;
9072 case T_INT:
9073 case T_FLOAT:
9074 evpermd(dst, mask, nds, src, merge, vector_len); break;
9075 case T_LONG:
9076 case T_DOUBLE:
9077 evpermq(dst, mask, nds, src, merge, vector_len); break;
9078 default:
9079 fatal("Unexpected type argument %s", type2name(type)); break;
9080 }
9081 }
9082
9083 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9084 switch(type) {
9085 case T_BYTE:
9086 evpminub(dst, mask, nds, src, merge, vector_len); break;
9087 case T_SHORT:
9088 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9089 case T_INT:
9090 evpminud(dst, mask, nds, src, merge, vector_len); break;
9091 case T_LONG:
9092 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9093 default:
9094 fatal("Unexpected type argument %s", type2name(type)); break;
9095 }
9096 }
9097
9098 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9099 switch(type) {
9100 case T_BYTE:
9101 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9102 case T_SHORT:
9103 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9104 case T_INT:
9105 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9106 case T_LONG:
9107 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9108 default:
9109 fatal("Unexpected type argument %s", type2name(type)); break;
9110 }
9111 }
9112
9113 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9114 switch(type) {
9115 case T_BYTE:
9116 evpminub(dst, mask, nds, src, merge, vector_len); break;
9117 case T_SHORT:
9118 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9119 case T_INT:
9120 evpminud(dst, mask, nds, src, merge, vector_len); break;
9121 case T_LONG:
9122 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9123 default:
9124 fatal("Unexpected type argument %s", type2name(type)); break;
9125 }
9126 }
9127
9128 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9129 switch(type) {
9130 case T_BYTE:
9131 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9132 case T_SHORT:
9133 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
9134 case T_INT:
9135 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
9136 case T_LONG:
9137 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
9138 default:
9139 fatal("Unexpected type argument %s", type2name(type)); break;
9140 }
9141 }
9142
9143 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9144 switch(type) {
9145 case T_BYTE:
9146 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9147 case T_SHORT:
9148 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9149 case T_INT:
9150 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9151 case T_LONG:
9152 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9153 case T_FLOAT:
9154 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9155 case T_DOUBLE:
9156 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9157 default:
9158 fatal("Unexpected type argument %s", type2name(type)); break;
9159 }
9160 }
9161
9162 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9163 switch(type) {
9164 case T_BYTE:
9165 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9166 case T_SHORT:
9167 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9168 case T_INT:
9169 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9170 case T_LONG:
9171 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9172 case T_FLOAT:
9173 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9174 case T_DOUBLE:
9175 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9176 default:
9177 fatal("Unexpected type argument %s", type2name(type)); break;
9178 }
9179 }
9180
9181 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9182 switch(type) {
9183 case T_BYTE:
9184 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9185 case T_SHORT:
9186 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9187 case T_INT:
9188 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9189 case T_LONG:
9190 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9191 case T_FLOAT:
9192 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9193 case T_DOUBLE:
9194 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MIN_COMPARE_SIGN, vector_len); break;
9195 default:
9196 fatal("Unexpected type argument %s", type2name(type)); break;
9197 }
9198 }
9199
9200 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9201 switch(type) {
9202 case T_BYTE:
9203 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9204 case T_SHORT:
9205 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9206 case T_INT:
9207 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9208 case T_LONG:
9209 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9210 case T_FLOAT:
9211 evminmaxps(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9212 case T_DOUBLE:
9213 evminmaxpd(dst, mask, nds, src, merge, AVX10_2_MINMAX_MAX_COMPARE_SIGN, vector_len); break;
9214 default:
9215 fatal("Unexpected type argument %s", type2name(type)); break;
9216 }
9217 }
9218
9219 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9220 switch(type) {
9221 case T_INT:
9222 evpxord(dst, mask, nds, src, merge, vector_len); break;
9223 case T_LONG:
9224 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9225 default:
9226 fatal("Unexpected type argument %s", type2name(type)); break;
9227 }
9228 }
9229
9230 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9231 switch(type) {
9232 case T_INT:
9233 evpxord(dst, mask, nds, src, merge, vector_len); break;
9234 case T_LONG:
9235 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9236 default:
9237 fatal("Unexpected type argument %s", type2name(type)); break;
9238 }
9239 }
9240
9241 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9242 switch(type) {
9243 case T_INT:
9244 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9245 case T_LONG:
9246 evporq(dst, mask, nds, src, merge, vector_len); break;
9247 default:
9248 fatal("Unexpected type argument %s", type2name(type)); break;
9249 }
9250 }
9251
9252 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9253 switch(type) {
9254 case T_INT:
9255 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9256 case T_LONG:
9257 evporq(dst, mask, nds, src, merge, vector_len); break;
9258 default:
9259 fatal("Unexpected type argument %s", type2name(type)); break;
9260 }
9261 }
9262
9263 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9264 switch(type) {
9265 case T_INT:
9266 evpandd(dst, mask, nds, src, merge, vector_len); break;
9267 case T_LONG:
9268 evpandq(dst, mask, nds, src, merge, vector_len); break;
9269 default:
9270 fatal("Unexpected type argument %s", type2name(type)); break;
9271 }
9272 }
9273
9274 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9275 switch(type) {
9276 case T_INT:
9277 evpandd(dst, mask, nds, src, merge, vector_len); break;
9278 case T_LONG:
9279 evpandq(dst, mask, nds, src, merge, vector_len); break;
9280 default:
9281 fatal("Unexpected type argument %s", type2name(type)); break;
9282 }
9283 }
9284
9285 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
9286 switch(masklen) {
9287 case 8:
9288 kortestbl(src1, src2);
9289 break;
9290 case 16:
9291 kortestwl(src1, src2);
9292 break;
9293 case 32:
9294 kortestdl(src1, src2);
9295 break;
9296 case 64:
9297 kortestql(src1, src2);
9298 break;
9299 default:
9300 fatal("Unexpected mask length %d", masklen);
9301 break;
9302 }
9303 }
9304
9305
9306 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
9307 switch(masklen) {
9308 case 8:
9309 ktestbl(src1, src2);
9310 break;
9311 case 16:
9312 ktestwl(src1, src2);
9313 break;
9314 case 32:
9315 ktestdl(src1, src2);
9316 break;
9317 case 64:
9318 ktestql(src1, src2);
9319 break;
9320 default:
9321 fatal("Unexpected mask length %d", masklen);
9322 break;
9323 }
9324 }
9325
9326 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9327 switch(type) {
9328 case T_INT:
9329 evprold(dst, mask, src, shift, merge, vlen_enc); break;
9330 case T_LONG:
9331 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
9332 default:
9333 fatal("Unexpected type argument %s", type2name(type)); break;
9334 break;
9335 }
9336 }
9337
9338 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9339 switch(type) {
9340 case T_INT:
9341 evprord(dst, mask, src, shift, merge, vlen_enc); break;
9342 case T_LONG:
9343 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
9344 default:
9345 fatal("Unexpected type argument %s", type2name(type)); break;
9346 }
9347 }
9348
9349 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9350 switch(type) {
9351 case T_INT:
9352 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
9353 case T_LONG:
9354 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
9355 default:
9356 fatal("Unexpected type argument %s", type2name(type)); break;
9357 }
9358 }
9359
9360 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9361 switch(type) {
9362 case T_INT:
9363 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
9364 case T_LONG:
9365 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
9366 default:
9367 fatal("Unexpected type argument %s", type2name(type)); break;
9368 }
9369 }
9370
9371 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9372 assert(rscratch != noreg || always_reachable(src), "missing");
9373
9374 if (reachable(src)) {
9375 evpandq(dst, nds, as_Address(src), vector_len);
9376 } else {
9377 lea(rscratch, src);
9378 evpandq(dst, nds, Address(rscratch, 0), vector_len);
9379 }
9380 }
9381
9382 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
9383 assert(rscratch != noreg || always_reachable(src), "missing");
9384
9385 if (reachable(src)) {
9386 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
9387 } else {
9388 lea(rscratch, src);
9389 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
9390 }
9391 }
9392
9393 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9394 assert(rscratch != noreg || always_reachable(src), "missing");
9395
9396 if (reachable(src)) {
9397 evporq(dst, nds, as_Address(src), vector_len);
9398 } else {
9399 lea(rscratch, src);
9400 evporq(dst, nds, Address(rscratch, 0), vector_len);
9401 }
9402 }
9403
9404 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9405 assert(rscratch != noreg || always_reachable(src), "missing");
9406
9407 if (reachable(src)) {
9408 vpshufb(dst, nds, as_Address(src), vector_len);
9409 } else {
9410 lea(rscratch, src);
9411 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
9412 }
9413 }
9414
9415 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9416 assert(rscratch != noreg || always_reachable(src), "missing");
9417
9418 if (reachable(src)) {
9419 Assembler::vpor(dst, nds, as_Address(src), vector_len);
9420 } else {
9421 lea(rscratch, src);
9422 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
9423 }
9424 }
9425
9426 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
9427 assert(rscratch != noreg || always_reachable(src3), "missing");
9428
9429 if (reachable(src3)) {
9430 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
9431 } else {
9432 lea(rscratch, src3);
9433 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
9434 }
9435 }
9436
9437 #if COMPILER2_OR_JVMCI
9438
9439 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
9440 Register length, Register temp, int vec_enc) {
9441 // Computing mask for predicated vector store.
9442 movptr(temp, -1);
9443 bzhiq(temp, temp, length);
9444 kmov(mask, temp);
9445 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
9446 }
9447
9448 // Set memory operation for length "less than" 64 bytes.
9449 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
9450 XMMRegister xmm, KRegister mask, Register length,
9451 Register temp, bool use64byteVector) {
9452 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9453 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9454 if (!use64byteVector) {
9455 fill32(dst, disp, xmm);
9456 subptr(length, 32 >> shift);
9457 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
9458 } else {
9459 assert(MaxVectorSize == 64, "vector length != 64");
9460 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
9461 }
9462 }
9463
9464
9465 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
9466 XMMRegister xmm, KRegister mask, Register length,
9467 Register temp) {
9468 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9469 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9470 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
9471 }
9472
9473
9474 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
9475 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9476 vmovdqu(dst, xmm);
9477 }
9478
9479 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
9480 fill32(Address(dst, disp), xmm);
9481 }
9482
9483 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
9484 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9485 if (!use64byteVector) {
9486 fill32(dst, xmm);
9487 fill32(dst.plus_disp(32), xmm);
9488 } else {
9489 evmovdquq(dst, xmm, Assembler::AVX_512bit);
9490 }
9491 }
9492
9493 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
9494 fill64(Address(dst, disp), xmm, use64byteVector);
9495 }
9496
9497 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
9498 Register count, Register rtmp, XMMRegister xtmp) {
9499 Label L_exit;
9500 Label L_fill_start;
9501 Label L_fill_64_bytes;
9502 Label L_fill_96_bytes;
9503 Label L_fill_128_bytes;
9504 Label L_fill_128_bytes_loop;
9505 Label L_fill_128_loop_header;
9506 Label L_fill_128_bytes_loop_header;
9507 Label L_fill_128_bytes_loop_pre_header;
9508 Label L_fill_zmm_sequence;
9509
9510 int shift = -1;
9511 switch(type) {
9512 case T_BYTE: shift = 0;
9513 break;
9514 case T_SHORT: shift = 1;
9515 break;
9516 case T_INT: shift = 2;
9517 break;
9518 /* Uncomment when LONG fill stubs are supported.
9519 case T_LONG: shift = 3;
9520 break;
9521 */
9522 default:
9523 fatal("Unhandled type: %s\n", type2name(type));
9524 }
9525
9526 if ((CopyAVX3Threshold != 0) || (MaxVectorSize == 32)) {
9527
9528 if (MaxVectorSize == 64) {
9529 cmpq(count, CopyAVX3Threshold >> shift);
9530 jcc(Assembler::greater, L_fill_zmm_sequence);
9531 }
9532
9533 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
9534
9535 bind(L_fill_start);
9536
9537 cmpq(count, 32 >> shift);
9538 jccb(Assembler::greater, L_fill_64_bytes);
9539 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
9540 jmp(L_exit);
9541
9542 bind(L_fill_64_bytes);
9543 cmpq(count, 64 >> shift);
9544 jccb(Assembler::greater, L_fill_96_bytes);
9545 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
9546 jmp(L_exit);
9547
9548 bind(L_fill_96_bytes);
9549 cmpq(count, 96 >> shift);
9550 jccb(Assembler::greater, L_fill_128_bytes);
9551 fill64(to, 0, xtmp);
9552 subq(count, 64 >> shift);
9553 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
9554 jmp(L_exit);
9555
9556 bind(L_fill_128_bytes);
9557 cmpq(count, 128 >> shift);
9558 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
9559 fill64(to, 0, xtmp);
9560 fill32(to, 64, xtmp);
9561 subq(count, 96 >> shift);
9562 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
9563 jmp(L_exit);
9564
9565 bind(L_fill_128_bytes_loop_pre_header);
9566 {
9567 mov(rtmp, to);
9568 andq(rtmp, 31);
9569 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
9570 negq(rtmp);
9571 addq(rtmp, 32);
9572 mov64(r8, -1L);
9573 bzhiq(r8, r8, rtmp);
9574 kmovql(k2, r8);
9575 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
9576 addq(to, rtmp);
9577 shrq(rtmp, shift);
9578 subq(count, rtmp);
9579 }
9580
9581 cmpq(count, 128 >> shift);
9582 jcc(Assembler::less, L_fill_start);
9583
9584 bind(L_fill_128_bytes_loop_header);
9585 subq(count, 128 >> shift);
9586
9587 align32();
9588 bind(L_fill_128_bytes_loop);
9589 fill64(to, 0, xtmp);
9590 fill64(to, 64, xtmp);
9591 addq(to, 128);
9592 subq(count, 128 >> shift);
9593 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
9594
9595 addq(count, 128 >> shift);
9596 jcc(Assembler::zero, L_exit);
9597 jmp(L_fill_start);
9598 }
9599
9600 if (MaxVectorSize == 64) {
9601 // Sequence using 64 byte ZMM register.
9602 Label L_fill_128_bytes_zmm;
9603 Label L_fill_192_bytes_zmm;
9604 Label L_fill_192_bytes_loop_zmm;
9605 Label L_fill_192_bytes_loop_header_zmm;
9606 Label L_fill_192_bytes_loop_pre_header_zmm;
9607 Label L_fill_start_zmm_sequence;
9608
9609 bind(L_fill_zmm_sequence);
9610 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
9611
9612 bind(L_fill_start_zmm_sequence);
9613 cmpq(count, 64 >> shift);
9614 jccb(Assembler::greater, L_fill_128_bytes_zmm);
9615 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
9616 jmp(L_exit);
9617
9618 bind(L_fill_128_bytes_zmm);
9619 cmpq(count, 128 >> shift);
9620 jccb(Assembler::greater, L_fill_192_bytes_zmm);
9621 fill64(to, 0, xtmp, true);
9622 subq(count, 64 >> shift);
9623 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
9624 jmp(L_exit);
9625
9626 bind(L_fill_192_bytes_zmm);
9627 cmpq(count, 192 >> shift);
9628 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
9629 fill64(to, 0, xtmp, true);
9630 fill64(to, 64, xtmp, true);
9631 subq(count, 128 >> shift);
9632 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
9633 jmp(L_exit);
9634
9635 bind(L_fill_192_bytes_loop_pre_header_zmm);
9636 {
9637 movq(rtmp, to);
9638 andq(rtmp, 63);
9639 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
9640 negq(rtmp);
9641 addq(rtmp, 64);
9642 mov64(r8, -1L);
9643 bzhiq(r8, r8, rtmp);
9644 kmovql(k2, r8);
9645 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
9646 addq(to, rtmp);
9647 shrq(rtmp, shift);
9648 subq(count, rtmp);
9649 }
9650
9651 cmpq(count, 192 >> shift);
9652 jcc(Assembler::less, L_fill_start_zmm_sequence);
9653
9654 bind(L_fill_192_bytes_loop_header_zmm);
9655 subq(count, 192 >> shift);
9656
9657 align32();
9658 bind(L_fill_192_bytes_loop_zmm);
9659 fill64(to, 0, xtmp, true);
9660 fill64(to, 64, xtmp, true);
9661 fill64(to, 128, xtmp, true);
9662 addq(to, 192);
9663 subq(count, 192 >> shift);
9664 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
9665
9666 addq(count, 192 >> shift);
9667 jcc(Assembler::zero, L_exit);
9668 jmp(L_fill_start_zmm_sequence);
9669 }
9670 bind(L_exit);
9671 }
9672 #endif //COMPILER2_OR_JVMCI
9673
9674
9675 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
9676 Label done;
9677 cvttss2sil(dst, src);
9678 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9679 cmpl(dst, 0x80000000); // float_sign_flip
9680 jccb(Assembler::notEqual, done);
9681 subptr(rsp, 8);
9682 movflt(Address(rsp, 0), src);
9683 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9684 pop(dst);
9685 bind(done);
9686 }
9687
9688 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
9689 Label done;
9690 cvttsd2sil(dst, src);
9691 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9692 cmpl(dst, 0x80000000); // float_sign_flip
9693 jccb(Assembler::notEqual, done);
9694 subptr(rsp, 8);
9695 movdbl(Address(rsp, 0), src);
9696 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9697 pop(dst);
9698 bind(done);
9699 }
9700
9701 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
9702 Label done;
9703 cvttss2siq(dst, src);
9704 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9705 jccb(Assembler::notEqual, done);
9706 subptr(rsp, 8);
9707 movflt(Address(rsp, 0), src);
9708 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9709 pop(dst);
9710 bind(done);
9711 }
9712
9713 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
9714 // Following code is line by line assembly translation rounding algorithm.
9715 // Please refer to java.lang.Math.round(float) algorithm for details.
9716 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
9717 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
9718 const int32_t FloatConsts_EXP_BIAS = 127;
9719 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
9720 const int32_t MINUS_32 = 0xFFFFFFE0;
9721 Label L_special_case, L_block1, L_exit;
9722 movl(rtmp, FloatConsts_EXP_BIT_MASK);
9723 movdl(dst, src);
9724 andl(dst, rtmp);
9725 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
9726 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
9727 subl(rtmp, dst);
9728 movl(rcx, rtmp);
9729 movl(dst, MINUS_32);
9730 testl(rtmp, dst);
9731 jccb(Assembler::notEqual, L_special_case);
9732 movdl(dst, src);
9733 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
9734 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
9735 movdl(rtmp, src);
9736 testl(rtmp, rtmp);
9737 jccb(Assembler::greaterEqual, L_block1);
9738 negl(dst);
9739 bind(L_block1);
9740 sarl(dst);
9741 addl(dst, 0x1);
9742 sarl(dst, 0x1);
9743 jmp(L_exit);
9744 bind(L_special_case);
9745 convert_f2i(dst, src);
9746 bind(L_exit);
9747 }
9748
9749 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
9750 // Following code is line by line assembly translation rounding algorithm.
9751 // Please refer to java.lang.Math.round(double) algorithm for details.
9752 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
9753 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
9754 const int64_t DoubleConsts_EXP_BIAS = 1023;
9755 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
9756 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
9757 Label L_special_case, L_block1, L_exit;
9758 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
9759 movq(dst, src);
9760 andq(dst, rtmp);
9761 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
9762 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
9763 subq(rtmp, dst);
9764 movq(rcx, rtmp);
9765 mov64(dst, MINUS_64);
9766 testq(rtmp, dst);
9767 jccb(Assembler::notEqual, L_special_case);
9768 movq(dst, src);
9769 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
9770 andq(dst, rtmp);
9771 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
9772 orq(dst, rtmp);
9773 movq(rtmp, src);
9774 testq(rtmp, rtmp);
9775 jccb(Assembler::greaterEqual, L_block1);
9776 negq(dst);
9777 bind(L_block1);
9778 sarq(dst);
9779 addq(dst, 0x1);
9780 sarq(dst, 0x1);
9781 jmp(L_exit);
9782 bind(L_special_case);
9783 convert_d2l(dst, src);
9784 bind(L_exit);
9785 }
9786
9787 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
9788 Label done;
9789 cvttsd2siq(dst, src);
9790 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9791 jccb(Assembler::notEqual, done);
9792 subptr(rsp, 8);
9793 movdbl(Address(rsp, 0), src);
9794 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
9795 pop(dst);
9796 bind(done);
9797 }
9798
9799 void MacroAssembler::cache_wb(Address line)
9800 {
9801 // 64 bit cpus always support clflush
9802 assert(VM_Version::supports_clflush(), "clflush should be available");
9803 bool optimized = VM_Version::supports_clflushopt();
9804 bool no_evict = VM_Version::supports_clwb();
9805
9806 // prefer clwb (writeback without evict) otherwise
9807 // prefer clflushopt (potentially parallel writeback with evict)
9808 // otherwise fallback on clflush (serial writeback with evict)
9809
9810 if (optimized) {
9811 if (no_evict) {
9812 clwb(line);
9813 } else {
9814 clflushopt(line);
9815 }
9816 } else {
9817 // no need for fence when using CLFLUSH
9818 clflush(line);
9819 }
9820 }
9821
9822 void MacroAssembler::cache_wbsync(bool is_pre)
9823 {
9824 assert(VM_Version::supports_clflush(), "clflush should be available");
9825 bool optimized = VM_Version::supports_clflushopt();
9826 bool no_evict = VM_Version::supports_clwb();
9827
9828 // pick the correct implementation
9829
9830 if (!is_pre && (optimized || no_evict)) {
9831 // need an sfence for post flush when using clflushopt or clwb
9832 // otherwise no no need for any synchroniaztion
9833
9834 sfence();
9835 }
9836 }
9837
9838 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9839 switch (cond) {
9840 // Note some conditions are synonyms for others
9841 case Assembler::zero: return Assembler::notZero;
9842 case Assembler::notZero: return Assembler::zero;
9843 case Assembler::less: return Assembler::greaterEqual;
9844 case Assembler::lessEqual: return Assembler::greater;
9845 case Assembler::greater: return Assembler::lessEqual;
9846 case Assembler::greaterEqual: return Assembler::less;
9847 case Assembler::below: return Assembler::aboveEqual;
9848 case Assembler::belowEqual: return Assembler::above;
9849 case Assembler::above: return Assembler::belowEqual;
9850 case Assembler::aboveEqual: return Assembler::below;
9851 case Assembler::overflow: return Assembler::noOverflow;
9852 case Assembler::noOverflow: return Assembler::overflow;
9853 case Assembler::negative: return Assembler::positive;
9854 case Assembler::positive: return Assembler::negative;
9855 case Assembler::parity: return Assembler::noParity;
9856 case Assembler::noParity: return Assembler::parity;
9857 }
9858 ShouldNotReachHere(); return Assembler::overflow;
9859 }
9860
9861 // This is simply a call to Thread::current()
9862 void MacroAssembler::get_thread_slow(Register thread) {
9863 if (thread != rax) {
9864 push(rax);
9865 }
9866 push(rdi);
9867 push(rsi);
9868 push(rdx);
9869 push(rcx);
9870 push(r8);
9871 push(r9);
9872 push(r10);
9873 push(r11);
9874
9875 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9876
9877 pop(r11);
9878 pop(r10);
9879 pop(r9);
9880 pop(r8);
9881 pop(rcx);
9882 pop(rdx);
9883 pop(rsi);
9884 pop(rdi);
9885 if (thread != rax) {
9886 mov(thread, rax);
9887 pop(rax);
9888 }
9889 }
9890
9891 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
9892 Label L_stack_ok;
9893 if (bias == 0) {
9894 testptr(sp, 2 * wordSize - 1);
9895 } else {
9896 // lea(tmp, Address(rsp, bias);
9897 mov(tmp, sp);
9898 addptr(tmp, bias);
9899 testptr(tmp, 2 * wordSize - 1);
9900 }
9901 jcc(Assembler::equal, L_stack_ok);
9902 block_comment(msg);
9903 stop(msg);
9904 bind(L_stack_ok);
9905 }
9906
9907 // Implements fast-locking.
9908 //
9909 // obj: the object to be locked
9910 // reg_rax: rax
9911 // thread: the thread which attempts to lock obj
9912 // tmp: a temporary register
9913 void MacroAssembler::fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow) {
9914 Register thread = r15_thread;
9915
9916 assert(reg_rax == rax, "");
9917 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
9918
9919 Label push;
9920 const Register top = tmp;
9921
9922 // Preload the markWord. It is important that this is the first
9923 // instruction emitted as it is part of C1's null check semantics.
9924 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
9925
9926 if (UseObjectMonitorTable) {
9927 // Clear cache in case fast locking succeeds or we need to take the slow-path.
9928 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
9929 }
9930
9931 if (DiagnoseSyncOnValueBasedClasses != 0) {
9932 load_klass(tmp, obj, rscratch1);
9933 testb(Address(tmp, Klass::misc_flags_offset()), KlassFlags::_misc_is_value_based_class);
9934 jcc(Assembler::notZero, slow);
9935 }
9936
9937 // Load top.
9938 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9939
9940 // Check if the lock-stack is full.
9941 cmpl(top, LockStack::end_offset());
9942 jcc(Assembler::greaterEqual, slow);
9943
9944 // Check for recursion.
9945 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
9946 jcc(Assembler::equal, push);
9947
9948 // Check header for monitor (0b10).
9949 testptr(reg_rax, markWord::monitor_value);
9950 jcc(Assembler::notZero, slow);
9951
9952 // Try to lock. Transition lock bits 0b01 => 0b00
9953 movptr(tmp, reg_rax);
9954 andptr(tmp, ~(int32_t)markWord::unlocked_value);
9955 orptr(reg_rax, markWord::unlocked_value);
9956 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
9957 jcc(Assembler::notEqual, slow);
9958
9959 // Restore top, CAS clobbers register.
9960 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9961
9962 bind(push);
9963 // After successful lock, push object on lock-stack.
9964 movptr(Address(thread, top), obj);
9965 incrementl(top, oopSize);
9966 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
9967 }
9968
9969 // Implements fast-unlocking.
9970 //
9971 // obj: the object to be unlocked
9972 // reg_rax: rax
9973 // thread: the thread
9974 // tmp: a temporary register
9975 void MacroAssembler::fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow) {
9976 Register thread = r15_thread;
9977
9978 assert(reg_rax == rax, "");
9979 assert_different_registers(obj, reg_rax, thread, tmp);
9980
9981 Label unlocked, push_and_slow;
9982 const Register top = tmp;
9983
9984 // Check if obj is top of lock-stack.
9985 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
9986 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
9987 jcc(Assembler::notEqual, slow);
9988
9989 // Pop lock-stack.
9990 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
9991 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
9992
9993 // Check if recursive.
9994 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
9995 jcc(Assembler::equal, unlocked);
9996
9997 // Not recursive. Check header for monitor (0b10).
9998 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
9999 testptr(reg_rax, markWord::monitor_value);
10000 jcc(Assembler::notZero, push_and_slow);
10001
10002 #ifdef ASSERT
10003 // Check header not unlocked (0b01).
10004 Label not_unlocked;
10005 testptr(reg_rax, markWord::unlocked_value);
10006 jcc(Assembler::zero, not_unlocked);
10007 stop("fast_unlock already unlocked");
10008 bind(not_unlocked);
10009 #endif
10010
10011 // Try to unlock. Transition lock bits 0b00 => 0b01
10012 movptr(tmp, reg_rax);
10013 orptr(tmp, markWord::unlocked_value);
10014 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10015 jcc(Assembler::equal, unlocked);
10016
10017 bind(push_and_slow);
10018 // Restore lock-stack and handle the unlock in runtime.
10019 #ifdef ASSERT
10020 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10021 movptr(Address(thread, top), obj);
10022 #endif
10023 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10024 jmp(slow);
10025
10026 bind(unlocked);
10027 }
10028
10029 // Saves legacy GPRs state on stack.
10030 void MacroAssembler::save_legacy_gprs() {
10031 subq(rsp, 16 * wordSize);
10032 movq(Address(rsp, 15 * wordSize), rax);
10033 movq(Address(rsp, 14 * wordSize), rcx);
10034 movq(Address(rsp, 13 * wordSize), rdx);
10035 movq(Address(rsp, 12 * wordSize), rbx);
10036 movq(Address(rsp, 10 * wordSize), rbp);
10037 movq(Address(rsp, 9 * wordSize), rsi);
10038 movq(Address(rsp, 8 * wordSize), rdi);
10039 movq(Address(rsp, 7 * wordSize), r8);
10040 movq(Address(rsp, 6 * wordSize), r9);
10041 movq(Address(rsp, 5 * wordSize), r10);
10042 movq(Address(rsp, 4 * wordSize), r11);
10043 movq(Address(rsp, 3 * wordSize), r12);
10044 movq(Address(rsp, 2 * wordSize), r13);
10045 movq(Address(rsp, wordSize), r14);
10046 movq(Address(rsp, 0), r15);
10047 }
10048
10049 // Resotres back legacy GPRs state from stack.
10050 void MacroAssembler::restore_legacy_gprs() {
10051 movq(r15, Address(rsp, 0));
10052 movq(r14, Address(rsp, wordSize));
10053 movq(r13, Address(rsp, 2 * wordSize));
10054 movq(r12, Address(rsp, 3 * wordSize));
10055 movq(r11, Address(rsp, 4 * wordSize));
10056 movq(r10, Address(rsp, 5 * wordSize));
10057 movq(r9, Address(rsp, 6 * wordSize));
10058 movq(r8, Address(rsp, 7 * wordSize));
10059 movq(rdi, Address(rsp, 8 * wordSize));
10060 movq(rsi, Address(rsp, 9 * wordSize));
10061 movq(rbp, Address(rsp, 10 * wordSize));
10062 movq(rbx, Address(rsp, 12 * wordSize));
10063 movq(rdx, Address(rsp, 13 * wordSize));
10064 movq(rcx, Address(rsp, 14 * wordSize));
10065 movq(rax, Address(rsp, 15 * wordSize));
10066 addq(rsp, 16 * wordSize);
10067 }
10068
10069 void MacroAssembler::load_aotrc_address(Register reg, address a) {
10070 #if INCLUDE_CDS
10071 assert(AOTRuntimeConstants::contains(a), "address out of range for data area");
10072 if (AOTCodeCache::is_on_for_dump()) {
10073 // all aotrc field addresses should be registered in the AOTCodeCache address table
10074 lea(reg, ExternalAddress(a));
10075 } else {
10076 mov64(reg, (uint64_t)a);
10077 }
10078 #else
10079 ShouldNotReachHere();
10080 #endif
10081 }
10082
10083 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10084 if (VM_Version::supports_apx_f()) {
10085 esetzucc(comparison, dst);
10086 } else {
10087 setb(comparison, dst);
10088 movzbl(dst, dst);
10089 }
10090 }
--- EOF ---