1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "asm/register.hpp"
30 #include "code/vmreg.inline.hpp"
31 #include "compiler/oopMap.hpp"
32 #include "utilities/macros.hpp"
33 #include "runtime/vm_version.hpp"
34 #include "utilities/checkedCast.hpp"
35
36 // MacroAssembler extends Assembler by frequently used macros.
37 //
38 // Instructions for which a 'better' code sequence exists depending
39 // on arguments should also go in here.
40
41 class MacroAssembler: public Assembler {
42 friend class LIR_Assembler;
43 friend class Runtime1; // as_Address()
44
45 public:
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments // the number of arguments to pop after the call
55 );
56
57 protected:
58 // This is the base routine called by the different versions of call_VM. The interpreter
59 // may customize this version by overriding it for its purposes (e.g., to save/restore
60 // additional registers when doing a VM call).
61 //
62 // call_VM_base returns the register which contains the thread upon return.
63 // If no last_java_sp is specified (noreg) than rsp will be used instead.
64 virtual void call_VM_base( // returns the register containing the thread upon return
65 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
66 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
67 address entry_point, // the entry point
68 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
69 bool check_exceptions // whether to check for pending exceptions after return
70 );
71
72 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
73
74 public:
75 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
76
77 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
78 // The implementation is only non-empty for the InterpreterMacroAssembler,
79 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
80 virtual void check_and_handle_popframe();
81 virtual void check_and_handle_earlyret();
82
83 Address as_Address(AddressLiteral adr);
84 Address as_Address(ArrayAddress adr, Register rscratch);
85
86 // Support for null-checks
87 //
88 // Generates code that causes a null OS exception if the content of reg is null.
89 // If the accessed location is M[reg + offset] and the offset is known, provide the
90 // offset. No explicit code generation is needed if the offset is within a certain
91 // range (0 <= offset <= page_size).
92
93 void null_check(Register reg, int offset = -1);
94 static bool needs_explicit_null_check(intptr_t offset);
95 static bool uses_implicit_null_check(void* address);
96
97 // Required platform-specific helpers for Label::patch_instructions.
98 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
99 void pd_patch_instruction(address branch, address target, const char* file, int line) {
100 unsigned char op = branch[0];
101 assert(op == 0xE8 /* call */ ||
102 op == 0xE9 /* jmp */ ||
103 op == 0xEB /* short jmp */ ||
104 (op & 0xF0) == 0x70 /* short jcc */ ||
105 (op == 0x0F && (branch[1] & 0xF0) == 0x80) /* jcc */ ||
106 (op == 0xC7 && branch[1] == 0xF8) /* xbegin */ ||
107 (op == 0x8D) /* lea */,
108 "Invalid opcode at patch point");
109
110 if (op == 0xEB || (op & 0xF0) == 0x70) {
111 // short offset operators (jmp and jcc)
112 char* disp = (char*) &branch[1];
113 int imm8 = checked_cast<int>(target - (address) &disp[1]);
114 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
115 file == nullptr ? "<null>" : file, line);
116 *disp = (char)imm8;
117 } else {
118 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7 || op == 0x8D) ? 2 : 1];
119 int imm32 = checked_cast<int>(target - (address) &disp[1]);
120 *disp = imm32;
121 }
122 }
123
124 // The following 4 methods return the offset of the appropriate move instruction
125
126 // Support for fast byte/short loading with zero extension (depending on particular CPU)
127 int load_unsigned_byte(Register dst, Address src);
128 int load_unsigned_short(Register dst, Address src);
129
130 // Support for fast byte/short loading with sign extension (depending on particular CPU)
131 int load_signed_byte(Register dst, Address src);
132 int load_signed_short(Register dst, Address src);
133
134 // Support for sign-extension (hi:lo = extend_sign(lo))
135 void extend_sign(Register hi, Register lo);
136
137 // Load and store values by size and signed-ness
138 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
139 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
140
141 // Support for inc/dec with optimal instruction selection depending on value
142
143 void increment(Register reg, int value = 1) { incrementq(reg, value); }
144 void decrement(Register reg, int value = 1) { decrementq(reg, value); }
145 void increment(Address dst, int value = 1) { incrementq(dst, value); }
146 void decrement(Address dst, int value = 1) { decrementq(dst, value); }
147
148 void decrementl(Address dst, int value = 1);
149 void decrementl(Register reg, int value = 1);
150
151 void decrementq(Register reg, int value = 1);
152 void decrementq(Address dst, int value = 1);
153
154 void incrementl(Address dst, int value = 1);
155 void incrementl(Register reg, int value = 1);
156
157 void incrementq(Register reg, int value = 1);
158 void incrementq(Address dst, int value = 1);
159
160 void incrementl(AddressLiteral dst, Register rscratch = noreg);
161 void incrementl(ArrayAddress dst, Register rscratch);
162
163 void incrementq(AddressLiteral dst, Register rscratch = noreg);
164
165 void movhlf(XMMRegister dst, XMMRegister src, Register rscratch = noreg);
166
167 // Support optimal SSE move instructions.
168 void movflt(XMMRegister dst, XMMRegister src) {
169 if (dst-> encoding() == src->encoding()) return;
170 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
171 else { movss (dst, src); return; }
172 }
173 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
174 void movflt(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
175 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
176
177 // Move with zero extension
178 void movfltz(XMMRegister dst, XMMRegister src) { movss(dst, src); }
179
180 void movdbl(XMMRegister dst, XMMRegister src) {
181 if (dst-> encoding() == src->encoding()) return;
182 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
183 else { movsd (dst, src); return; }
184 }
185
186 void movdbl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
187
188 void movdbl(XMMRegister dst, Address src) {
189 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
190 else { movlpd(dst, src); return; }
191 }
192 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
193
194 void flt_to_flt16(Register dst, XMMRegister src, XMMRegister tmp) {
195 // Use separate tmp XMM register because caller may
196 // requires src XMM register to be unchanged (as in x86.ad).
197 vcvtps2ph(tmp, src, 0x04, Assembler::AVX_128bit);
198 movdl(dst, tmp);
199 movswl(dst, dst);
200 }
201
202 void flt16_to_flt(XMMRegister dst, Register src) {
203 movdl(dst, src);
204 vcvtph2ps(dst, dst, Assembler::AVX_128bit);
205 }
206
207 // Alignment
208 void align32();
209 void align64();
210 void align(uint modulus);
211 void align(uint modulus, uint target);
212
213 void post_call_nop();
214
215 // Stack frame creation/removal
216 void enter();
217 void leave();
218
219 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information).
220 // The pointer will be loaded into the thread register. This is a slow version that does native call.
221 // Normally, JavaThread pointer is available in r15_thread, use that where possible.
222 void get_thread_slow(Register thread);
223
224 // Support for argument shuffling
225
226 // bias in bytes
227 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
228 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
229 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
230 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
231 void move_ptr(VMRegPair src, VMRegPair dst);
232 void object_move(OopMap* map,
233 int oop_handle_offset,
234 int framesize_in_slots,
235 VMRegPair src,
236 VMRegPair dst,
237 bool is_receiver,
238 int* receiver_offset);
239
240 // Support for VM calls
241 //
242 // It is imperative that all calls into the VM are handled via the call_VM macros.
243 // They make sure that the stack linkage is setup correctly. call_VM's correspond
244 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
245
246
247 void call_VM(Register oop_result,
248 address entry_point,
249 bool check_exceptions = true);
250 void call_VM(Register oop_result,
251 address entry_point,
252 Register arg_1,
253 bool check_exceptions = true);
254 void call_VM(Register oop_result,
255 address entry_point,
256 Register arg_1, Register arg_2,
257 bool check_exceptions = true);
258 void call_VM(Register oop_result,
259 address entry_point,
260 Register arg_1, Register arg_2, Register arg_3,
261 bool check_exceptions = true);
262
263 // Overloadings with last_Java_sp
264 void call_VM(Register oop_result,
265 Register last_java_sp,
266 address entry_point,
267 int number_of_arguments = 0,
268 bool check_exceptions = true);
269 void call_VM(Register oop_result,
270 Register last_java_sp,
271 address entry_point,
272 Register arg_1, bool
273 check_exceptions = true);
274 void call_VM(Register oop_result,
275 Register last_java_sp,
276 address entry_point,
277 Register arg_1, Register arg_2,
278 bool check_exceptions = true);
279 void call_VM(Register oop_result,
280 Register last_java_sp,
281 address entry_point,
282 Register arg_1, Register arg_2, Register arg_3,
283 bool check_exceptions = true);
284
285 void get_vm_result_oop(Register oop_result);
286 void get_vm_result_metadata(Register metadata_result);
287
288 // These always tightly bind to MacroAssembler::call_VM_base
289 // bypassing the virtual implementation
290 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
291 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
292 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
293 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
294 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
295
296 void call_VM_leaf0(address entry_point);
297 void call_VM_leaf(address entry_point,
298 int number_of_arguments = 0);
299 void call_VM_leaf(address entry_point,
300 Register arg_1);
301 void call_VM_leaf(address entry_point,
302 Register arg_1, Register arg_2);
303 void call_VM_leaf(address entry_point,
304 Register arg_1, Register arg_2, Register arg_3);
305
306 void call_VM_leaf(address entry_point,
307 Register arg_1, Register arg_2, Register arg_3, Register arg_4);
308
309 // These always tightly bind to MacroAssembler::call_VM_leaf_base
310 // bypassing the virtual implementation
311 void super_call_VM_leaf(address entry_point);
312 void super_call_VM_leaf(address entry_point, Register arg_1);
313 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
314 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
315 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
316
317 void set_last_Java_frame(Register last_java_sp,
318 Register last_java_fp,
319 address last_java_pc,
320 Register rscratch);
321
322 void set_last_Java_frame(Register last_java_sp,
323 Register last_java_fp,
324 Label &last_java_pc,
325 Register scratch);
326
327 void reset_last_Java_frame(bool clear_fp);
328
329 // jobjects
330 void clear_jobject_tag(Register possibly_non_local);
331 void resolve_jobject(Register value, Register tmp);
332 void resolve_global_jobject(Register value, Register tmp);
333
334 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
335 void c2bool(Register x);
336
337 // C++ bool manipulation
338
339 void movbool(Register dst, Address src);
340 void movbool(Address dst, bool boolconst);
341 void movbool(Address dst, Register src);
342 void testbool(Register dst);
343
344 void resolve_oop_handle(Register result, Register tmp);
345 void resolve_weak_handle(Register result, Register tmp);
346 void load_mirror(Register mirror, Register method, Register tmp);
347 void load_method_holder_cld(Register rresult, Register rmethod);
348
349 void load_method_holder(Register holder, Register method);
350
351 // oop manipulations
352 void load_narrow_klass_compact(Register dst, Register src);
353 void load_klass(Register dst, Register src, Register tmp);
354 void store_klass(Register dst, Register src, Register tmp);
355
356 // Compares the narrow Klass pointer of an object to a given narrow Klass.
357 void cmp_klass(Register klass, Register obj, Register tmp);
358
359 // Compares the Klass pointer of two objects obj1 and obj2. Result is in the condition flags.
360 // Uses tmp1 and tmp2 as temporary registers.
361 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
362
363 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
364 Register tmp1);
365 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
366 Register tmp1, Register tmp2, Register tmp3);
367
368 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg, DecoratorSet decorators = 0);
369 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg, DecoratorSet decorators = 0);
370 void store_heap_oop(Address dst, Register val, Register tmp1 = noreg,
371 Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
372
373 // Used for storing null. All other oop constants should be
374 // stored using routines that take a jobject.
375 void store_heap_oop_null(Address dst);
376
377 void store_klass_gap(Register dst, Register src);
378
379 // This dummy is to prevent a call to store_heap_oop from
380 // converting a zero (like null) into a Register by giving
381 // the compiler two choices it can't resolve
382
383 void store_heap_oop(Address dst, void* dummy);
384
385 void encode_heap_oop(Register r);
386 void decode_heap_oop(Register r);
387 void encode_heap_oop_not_null(Register r);
388 void decode_heap_oop_not_null(Register r);
389 void encode_heap_oop_not_null(Register dst, Register src);
390 void decode_heap_oop_not_null(Register dst, Register src);
391
392 void set_narrow_oop(Register dst, jobject obj);
393 void set_narrow_oop(Address dst, jobject obj);
394 void cmp_narrow_oop(Register dst, jobject obj);
395 void cmp_narrow_oop(Address dst, jobject obj);
396
397 void encode_klass_not_null(Register r, Register tmp);
398 void decode_klass_not_null(Register r, Register tmp);
399 void encode_and_move_klass_not_null(Register dst, Register src);
400 void decode_and_move_klass_not_null(Register dst, Register src);
401 void set_narrow_klass(Register dst, Klass* k);
402 void set_narrow_klass(Address dst, Klass* k);
403 void cmp_narrow_klass(Register dst, Klass* k);
404 void cmp_narrow_klass(Address dst, Klass* k);
405
406 // if heap base register is used - reinit it with the correct value
407 void reinit_heapbase();
408
409 DEBUG_ONLY(void verify_heapbase(const char* msg);)
410
411 // Int division/remainder for Java
412 // (as idivl, but checks for special case as described in JVM spec.)
413 // returns idivl instruction offset for implicit exception handling
414 int corrected_idivl(Register reg);
415
416 // Long division/remainder for Java
417 // (as idivq, but checks for special case as described in JVM spec.)
418 // returns idivq instruction offset for implicit exception handling
419 int corrected_idivq(Register reg);
420
421 void int3();
422
423 // Long operation macros for a 32bit cpu
424 // Long negation for Java
425 void lneg(Register hi, Register lo);
426
427 // Long multiplication for Java
428 // (destroys contents of eax, ebx, ecx and edx)
429 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
430
431 // Long shifts for Java
432 // (semantics as described in JVM spec.)
433 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
434 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
435
436 // Long compare for Java
437 // (semantics as described in JVM spec.)
438 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
439
440
441 // misc
442
443 // Sign extension
444 void sign_extend_short(Register reg);
445 void sign_extend_byte(Register reg);
446
447 // Division by power of 2, rounding towards 0
448 void division_with_shift(Register reg, int shift_value);
449
450 // dst = c = a * b + c
451 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
452 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
453
454 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
455 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
456 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
457 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
458
459
460 // same as fcmp2int, but using SSE2
461 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
462 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
463
464 void push_IU_state();
465 void pop_IU_state();
466
467 void push_FPU_state();
468 void pop_FPU_state();
469
470 void push_CPU_state();
471 void pop_CPU_state();
472
473 void push_cont_fastpath();
474 void pop_cont_fastpath();
475
476 DEBUG_ONLY(void stop_if_in_cont(Register cont_reg, const char* name);)
477
478 // Round up to a power of two
479 void round_to(Register reg, int modulus);
480
481 private:
482 // General purpose and XMM registers potentially clobbered by native code; there
483 // is no need for FPU or AVX opmask related methods because C1/interpreter
484 // - we save/restore FPU state as a whole always
485 // - do not care about AVX-512 opmask
486 static RegSet call_clobbered_gp_registers();
487 static XMMRegSet call_clobbered_xmm_registers();
488
489 void push_set(XMMRegSet set, int offset);
490 void pop_set(XMMRegSet set, int offset);
491
492 public:
493 void push_set(RegSet set, int offset = -1);
494 void pop_set(RegSet set, int offset = -1);
495
496 // Push and pop everything that might be clobbered by a native
497 // runtime call.
498 // Only save the lower 64 bits of each vector register.
499 // Additional registers can be excluded in a passed RegSet.
500 void push_call_clobbered_registers_except(RegSet exclude, bool save_fpu = true);
501 void pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu = true);
502
503 void push_call_clobbered_registers(bool save_fpu = true) {
504 push_call_clobbered_registers_except(RegSet(), save_fpu);
505 }
506 void pop_call_clobbered_registers(bool restore_fpu = true) {
507 pop_call_clobbered_registers_except(RegSet(), restore_fpu);
508 }
509
510 // allocation
511 void tlab_allocate(
512 Register obj, // result: pointer to object after successful allocation
513 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
514 int con_size_in_bytes, // object size in bytes if known at compile time
515 Register t1, // temp register
516 Register t2, // temp register
517 Label& slow_case // continuation point if fast allocation fails
518 );
519 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
520
521 void population_count(Register dst, Register src, Register scratch1, Register scratch2);
522
523 // interface method calling
524 void lookup_interface_method(Register recv_klass,
525 Register intf_klass,
526 RegisterOrConstant itable_index,
527 Register method_result,
528 Register scan_temp,
529 Label& no_such_interface,
530 bool return_method = true);
531
532 void lookup_interface_method_stub(Register recv_klass,
533 Register holder_klass,
534 Register resolved_klass,
535 Register method_result,
536 Register scan_temp,
537 Register temp_reg2,
538 Register receiver,
539 int itable_index,
540 Label& L_no_such_interface);
541
542 // virtual method calling
543 void lookup_virtual_method(Register recv_klass,
544 RegisterOrConstant vtable_index,
545 Register method_result);
546
547 // Test sub_klass against super_klass, with fast and slow paths.
548
549 // The fast path produces a tri-state answer: yes / no / maybe-slow.
550 // One of the three labels can be null, meaning take the fall-through.
551 // If super_check_offset is -1, the value is loaded up from super_klass.
552 // No registers are killed, except temp_reg.
553 void check_klass_subtype_fast_path(Register sub_klass,
554 Register super_klass,
555 Register temp_reg,
556 Label* L_success,
557 Label* L_failure,
558 Label* L_slow_path,
559 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
560
561 // The rest of the type check; must be wired to a corresponding fast path.
562 // It does not repeat the fast path logic, so don't use it standalone.
563 // The temp_reg and temp2_reg can be noreg, if no temps are available.
564 // Updates the sub's secondary super cache as necessary.
565 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
566 void check_klass_subtype_slow_path(Register sub_klass,
567 Register super_klass,
568 Register temp_reg,
569 Register temp2_reg,
570 Label* L_success,
571 Label* L_failure,
572 bool set_cond_codes = false);
573
574 // The 64-bit version, which may do a hashed subclass lookup.
575 void check_klass_subtype_slow_path(Register sub_klass,
576 Register super_klass,
577 Register temp_reg,
578 Register temp2_reg,
579 Register temp3_reg,
580 Register temp4_reg,
581 Label* L_success,
582 Label* L_failure);
583
584 // Three parts of a hashed subclass lookup: a simple linear search,
585 // a table lookup, and a fallback that does linear probing in the
586 // event of a hash collision.
587 void check_klass_subtype_slow_path_linear(Register sub_klass,
588 Register super_klass,
589 Register temp_reg,
590 Register temp2_reg,
591 Label* L_success,
592 Label* L_failure,
593 bool set_cond_codes = false);
594 void check_klass_subtype_slow_path_table(Register sub_klass,
595 Register super_klass,
596 Register temp_reg,
597 Register temp2_reg,
598 Register temp3_reg,
599 Register result_reg,
600 Label* L_success,
601 Label* L_failure);
602 void hashed_check_klass_subtype_slow_path(Register sub_klass,
603 Register super_klass,
604 Register temp_reg,
605 Label* L_success,
606 Label* L_failure);
607
608 // As above, but with a constant super_klass.
609 // The result is in Register result, not the condition codes.
610 void lookup_secondary_supers_table_const(Register sub_klass,
611 Register super_klass,
612 Register temp1,
613 Register temp2,
614 Register temp3,
615 Register temp4,
616 Register result,
617 u1 super_klass_slot);
618
619 using Assembler::salq;
620 void salq(Register dest, Register count);
621 using Assembler::rorq;
622 void rorq(Register dest, Register count);
623 void lookup_secondary_supers_table_var(Register sub_klass,
624 Register super_klass,
625 Register temp1,
626 Register temp2,
627 Register temp3,
628 Register temp4,
629 Register result);
630
631 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
632 Register r_array_base,
633 Register r_array_index,
634 Register r_bitmap,
635 Register temp1,
636 Register temp2,
637 Label* L_success,
638 Label* L_failure = nullptr);
639
640 void verify_secondary_supers_table(Register r_sub_klass,
641 Register r_super_klass,
642 Register expected,
643 Register temp1,
644 Register temp2,
645 Register temp3);
646
647 void repne_scanq(Register addr, Register value, Register count, Register limit,
648 Label* L_success,
649 Label* L_failure = nullptr);
650
651 // If r is valid, return r.
652 // If r is invalid, remove a register r2 from available_regs, add r2
653 // to regs_to_push, then return r2.
654 Register allocate_if_noreg(const Register r,
655 RegSetIterator<Register> &available_regs,
656 RegSet ®s_to_push);
657
658 // Simplified, combined version, good for typical uses.
659 // Falls through on failure.
660 void check_klass_subtype(Register sub_klass,
661 Register super_klass,
662 Register temp_reg,
663 Label& L_success);
664
665 void clinit_barrier(Register klass,
666 Label* L_fast_path = nullptr,
667 Label* L_slow_path = nullptr);
668
669 // method handles (JSR 292)
670 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
671
672 void profile_receiver_type(Register recv, Register mdp, int mdp_offset);
673
674 // Debugging
675
676 // only if +VerifyOops
677 void _verify_oop(Register reg, const char* s, const char* file, int line);
678 void _verify_oop_addr(Address addr, const char* s, const char* file, int line);
679
680 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
681 if (VerifyOops) {
682 _verify_oop(reg, s, file, line);
683 }
684 }
685 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
686 if (VerifyOops) {
687 _verify_oop_addr(reg, s, file, line);
688 }
689 }
690
691 // TODO: verify method and klass metadata (compare against vptr?)
692 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
693 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
694
695 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
696 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
697 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
698 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
699 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
700
701 // Verify or restore cpu control state after JNI call
702 void restore_cpu_control_state_after_jni(Register rscratch);
703
704 // prints msg, dumps registers and stops execution
705 void stop(const char* msg);
706
707 // prints msg and continues
708 void warn(const char* msg);
709
710 // dumps registers and other state
711 void print_state();
712
713 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
714 static void debug64(char* msg, int64_t pc, int64_t regs[]);
715 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
716 static void print_state64(int64_t pc, int64_t regs[]);
717
718 void os_breakpoint();
719
720 void untested() { stop("untested"); }
721
722 void unimplemented(const char* what = "");
723
724 void should_not_reach_here() { stop("should not reach here"); }
725
726 void print_CPU_state();
727
728 // Stack overflow checking
729 void bang_stack_with_offset(int offset) {
730 // stack grows down, caller passes positive offset
731 assert(offset > 0, "must bang with negative offset");
732 movl(Address(rsp, (-offset)), rax);
733 }
734
735 // Writes to stack successive pages until offset reached to check for
736 // stack overflow + shadow pages. Also, clobbers tmp
737 void bang_stack_size(Register size, Register tmp);
738
739 // Check for reserved stack access in method being exited (for JIT)
740 void reserved_stack_check();
741
742 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod);
743
744 void verify_tlab();
745
746 static Condition negate_condition(Condition cond);
747
748 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
749 // operands. In general the names are modified to avoid hiding the instruction in Assembler
750 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
751 // here in MacroAssembler. The major exception to this rule is call
752
753 // Arithmetics
754
755
756 void addptr(Address dst, int32_t src) { addq(dst, src); }
757 void addptr(Address dst, Register src);
758
759 void addptr(Register dst, Address src) { addq(dst, src); }
760 void addptr(Register dst, int32_t src);
761 void addptr(Register dst, Register src);
762 void addptr(Register dst, RegisterOrConstant src) {
763 if (src.is_constant()) addptr(dst, checked_cast<int>(src.as_constant()));
764 else addptr(dst, src.as_register());
765 }
766
767 void andptr(Register dst, int32_t src);
768 void andptr(Register src1, Register src2) { andq(src1, src2); }
769
770 using Assembler::andq;
771 void andq(Register dst, AddressLiteral src, Register rscratch = noreg);
772
773 void cmp8(AddressLiteral src1, int imm, Register rscratch = noreg);
774
775 // renamed to drag out the casting of address to int32_t/intptr_t
776 void cmp32(Register src1, int32_t imm);
777
778 void cmp32(AddressLiteral src1, int32_t imm, Register rscratch = noreg);
779 // compare reg - mem, or reg - &mem
780 void cmp32(Register src1, AddressLiteral src2, Register rscratch = noreg);
781
782 void cmp32(Register src1, Address src2);
783
784 void cmpoop(Register src1, Register src2);
785 void cmpoop(Register src1, Address src2);
786 void cmpoop(Register dst, jobject obj, Register rscratch);
787
788 // NOTE src2 must be the lval. This is NOT an mem-mem compare
789 void cmpptr(Address src1, AddressLiteral src2, Register rscratch);
790
791 void cmpptr(Register src1, AddressLiteral src2, Register rscratch = noreg);
792
793 void cmpptr(Register src1, Register src2) { cmpq(src1, src2); }
794 void cmpptr(Register src1, Address src2) { cmpq(src1, src2); }
795
796 void cmpptr(Register src1, int32_t src2) { cmpq(src1, src2); }
797 void cmpptr(Address src1, int32_t src2) { cmpq(src1, src2); }
798
799 // cmp64 to avoild hiding cmpq
800 void cmp64(Register src1, AddressLiteral src, Register rscratch = noreg);
801
802 void cmpxchgptr(Register reg, Address adr);
803
804 void locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch = noreg);
805
806 void imulptr(Register dst, Register src) { imulq(dst, src); }
807 void imulptr(Register dst, Register src, int imm32) { imulq(dst, src, imm32); }
808
809
810 void negptr(Register dst) { negq(dst); }
811
812 void notptr(Register dst) { notq(dst); }
813
814 void shlptr(Register dst, int32_t shift);
815 void shlptr(Register dst) { shlq(dst); }
816
817 void shrptr(Register dst, int32_t shift);
818 void shrptr(Register dst) { shrq(dst); }
819
820 void sarptr(Register dst) { sarq(dst); }
821 void sarptr(Register dst, int32_t src) { sarq(dst, src); }
822
823 void subptr(Address dst, int32_t src) { subq(dst, src); }
824
825 void subptr(Register dst, Address src) { subq(dst, src); }
826 void subptr(Register dst, int32_t src);
827 // Force generation of a 4 byte immediate value even if it fits into 8bit
828 void subptr_imm32(Register dst, int32_t src);
829 void subptr(Register dst, Register src);
830 void subptr(Register dst, RegisterOrConstant src) {
831 if (src.is_constant()) subptr(dst, (int) src.as_constant());
832 else subptr(dst, src.as_register());
833 }
834
835 void sbbptr(Address dst, int32_t src) { sbbq(dst, src); }
836 void sbbptr(Register dst, int32_t src) { sbbq(dst, src); }
837
838 void xchgptr(Register src1, Register src2) { xchgq(src1, src2); }
839 void xchgptr(Register src1, Address src2) { xchgq(src1, src2); }
840
841 void xaddptr(Address src1, Register src2) { xaddq(src1, src2); }
842
843
844
845 // Helper functions for statistics gathering.
846 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
847 void cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch = noreg);
848 // Unconditional atomic increment.
849 void atomic_incl(Address counter_addr);
850 void atomic_incl(AddressLiteral counter_addr, Register rscratch = noreg);
851 void atomic_incq(Address counter_addr);
852 void atomic_incq(AddressLiteral counter_addr, Register rscratch = noreg);
853 void atomic_incptr(AddressLiteral counter_addr, Register rscratch = noreg) { atomic_incq(counter_addr, rscratch); }
854 void atomic_incptr(Address counter_addr) { atomic_incq(counter_addr); }
855
856 using Assembler::lea;
857 void lea(Register dst, AddressLiteral adr);
858 void lea(Address dst, AddressLiteral adr, Register rscratch);
859
860 void leal32(Register dst, Address src) { leal(dst, src); }
861
862 // Import other testl() methods from the parent class or else
863 // they will be hidden by the following overriding declaration.
864 using Assembler::testl;
865 void testl(Address dst, int32_t imm32);
866 void testl(Register dst, int32_t imm32);
867 void testl(Register dst, AddressLiteral src); // requires reachable address
868 using Assembler::testq;
869 void testq(Address dst, int32_t imm32);
870 void testq(Register dst, int32_t imm32);
871
872 void orptr(Register dst, Address src) { orq(dst, src); }
873 void orptr(Register dst, Register src) { orq(dst, src); }
874 void orptr(Register dst, int32_t src) { orq(dst, src); }
875 void orptr(Address dst, int32_t imm32) { orq(dst, imm32); }
876
877 void testptr(Register src, int32_t imm32) { testq(src, imm32); }
878 void testptr(Register src1, Address src2) { testq(src1, src2); }
879 void testptr(Address src, int32_t imm32) { testq(src, imm32); }
880 void testptr(Register src1, Register src2);
881
882 void xorptr(Register dst, Register src) { xorq(dst, src); }
883 void xorptr(Register dst, Address src) { xorq(dst, src); }
884
885 // Calls
886
887 void call(Label& L, relocInfo::relocType rtype);
888 void call(Register entry);
889 void call(Address addr) { Assembler::call(addr); }
890
891 // NOTE: this call transfers to the effective address of entry NOT
892 // the address contained by entry. This is because this is more natural
893 // for jumps/calls.
894 void call(AddressLiteral entry, Register rscratch = rax);
895
896 // Emit the CompiledIC call idiom
897 void ic_call(address entry, jint method_index = 0);
898 static int ic_check_size();
899 int ic_check(int end_alignment);
900
901 void emit_static_call_stub();
902
903 // Jumps
904
905 // NOTE: these jumps transfer to the effective address of dst NOT
906 // the address contained by dst. This is because this is more natural
907 // for jumps/calls.
908 void jump(AddressLiteral dst, Register rscratch = noreg);
909
910 void jump_cc(Condition cc, AddressLiteral dst, Register rscratch = noreg);
911
912 // 32bit can do a case table jump in one instruction but we no longer allow the base
913 // to be installed in the Address class. This jump will transfer to the address
914 // contained in the location described by entry (not the address of entry)
915 void jump(ArrayAddress entry, Register rscratch);
916
917 // Adding more natural conditional jump instructions
918 void ALWAYSINLINE jo(Label& L, bool maybe_short = true) { jcc(Assembler::overflow, L, maybe_short); }
919 void ALWAYSINLINE jno(Label& L, bool maybe_short = true) { jcc(Assembler::noOverflow, L, maybe_short); }
920 void ALWAYSINLINE js(Label& L, bool maybe_short = true) { jcc(Assembler::negative, L, maybe_short); }
921 void ALWAYSINLINE jns(Label& L, bool maybe_short = true) { jcc(Assembler::positive, L, maybe_short); }
922 void ALWAYSINLINE je(Label& L, bool maybe_short = true) { jcc(Assembler::equal, L, maybe_short); }
923 void ALWAYSINLINE jz(Label& L, bool maybe_short = true) { jcc(Assembler::zero, L, maybe_short); }
924 void ALWAYSINLINE jne(Label& L, bool maybe_short = true) { jcc(Assembler::notEqual, L, maybe_short); }
925 void ALWAYSINLINE jnz(Label& L, bool maybe_short = true) { jcc(Assembler::notZero, L, maybe_short); }
926 void ALWAYSINLINE jb(Label& L, bool maybe_short = true) { jcc(Assembler::below, L, maybe_short); }
927 void ALWAYSINLINE jnae(Label& L, bool maybe_short = true) { jcc(Assembler::below, L, maybe_short); }
928 void ALWAYSINLINE jc(Label& L, bool maybe_short = true) { jcc(Assembler::carrySet, L, maybe_short); }
929 void ALWAYSINLINE jnb(Label& L, bool maybe_short = true) { jcc(Assembler::aboveEqual, L, maybe_short); }
930 void ALWAYSINLINE jae(Label& L, bool maybe_short = true) { jcc(Assembler::aboveEqual, L, maybe_short); }
931 void ALWAYSINLINE jnc(Label& L, bool maybe_short = true) { jcc(Assembler::carryClear, L, maybe_short); }
932 void ALWAYSINLINE jbe(Label& L, bool maybe_short = true) { jcc(Assembler::belowEqual, L, maybe_short); }
933 void ALWAYSINLINE jna(Label& L, bool maybe_short = true) { jcc(Assembler::belowEqual, L, maybe_short); }
934 void ALWAYSINLINE ja(Label& L, bool maybe_short = true) { jcc(Assembler::above, L, maybe_short); }
935 void ALWAYSINLINE jnbe(Label& L, bool maybe_short = true) { jcc(Assembler::above, L, maybe_short); }
936 void ALWAYSINLINE jl(Label& L, bool maybe_short = true) { jcc(Assembler::less, L, maybe_short); }
937 void ALWAYSINLINE jnge(Label& L, bool maybe_short = true) { jcc(Assembler::less, L, maybe_short); }
938 void ALWAYSINLINE jge(Label& L, bool maybe_short = true) { jcc(Assembler::greaterEqual, L, maybe_short); }
939 void ALWAYSINLINE jnl(Label& L, bool maybe_short = true) { jcc(Assembler::greaterEqual, L, maybe_short); }
940 void ALWAYSINLINE jle(Label& L, bool maybe_short = true) { jcc(Assembler::lessEqual, L, maybe_short); }
941 void ALWAYSINLINE jng(Label& L, bool maybe_short = true) { jcc(Assembler::lessEqual, L, maybe_short); }
942 void ALWAYSINLINE jg(Label& L, bool maybe_short = true) { jcc(Assembler::greater, L, maybe_short); }
943 void ALWAYSINLINE jnle(Label& L, bool maybe_short = true) { jcc(Assembler::greater, L, maybe_short); }
944 void ALWAYSINLINE jp(Label& L, bool maybe_short = true) { jcc(Assembler::parity, L, maybe_short); }
945 void ALWAYSINLINE jpe(Label& L, bool maybe_short = true) { jcc(Assembler::parity, L, maybe_short); }
946 void ALWAYSINLINE jnp(Label& L, bool maybe_short = true) { jcc(Assembler::noParity, L, maybe_short); }
947 void ALWAYSINLINE jpo(Label& L, bool maybe_short = true) { jcc(Assembler::noParity, L, maybe_short); }
948 // * No condition for this * void ALWAYSINLINE jcxz(Label& L, bool maybe_short = true) { jcc(Assembler::cxz, L, maybe_short); }
949 // * No condition for this * void ALWAYSINLINE jecxz(Label& L, bool maybe_short = true) { jcc(Assembler::cxz, L, maybe_short); }
950
951 // Short versions of the above
952 void ALWAYSINLINE jo_b(Label& L) { jccb(Assembler::overflow, L); }
953 void ALWAYSINLINE jno_b(Label& L) { jccb(Assembler::noOverflow, L); }
954 void ALWAYSINLINE js_b(Label& L) { jccb(Assembler::negative, L); }
955 void ALWAYSINLINE jns_b(Label& L) { jccb(Assembler::positive, L); }
956 void ALWAYSINLINE je_b(Label& L) { jccb(Assembler::equal, L); }
957 void ALWAYSINLINE jz_b(Label& L) { jccb(Assembler::zero, L); }
958 void ALWAYSINLINE jne_b(Label& L) { jccb(Assembler::notEqual, L); }
959 void ALWAYSINLINE jnz_b(Label& L) { jccb(Assembler::notZero, L); }
960 void ALWAYSINLINE jb_b(Label& L) { jccb(Assembler::below, L); }
961 void ALWAYSINLINE jnae_b(Label& L) { jccb(Assembler::below, L); }
962 void ALWAYSINLINE jc_b(Label& L) { jccb(Assembler::carrySet, L); }
963 void ALWAYSINLINE jnb_b(Label& L) { jccb(Assembler::aboveEqual, L); }
964 void ALWAYSINLINE jae_b(Label& L) { jccb(Assembler::aboveEqual, L); }
965 void ALWAYSINLINE jnc_b(Label& L) { jccb(Assembler::carryClear, L); }
966 void ALWAYSINLINE jbe_b(Label& L) { jccb(Assembler::belowEqual, L); }
967 void ALWAYSINLINE jna_b(Label& L) { jccb(Assembler::belowEqual, L); }
968 void ALWAYSINLINE ja_b(Label& L) { jccb(Assembler::above, L); }
969 void ALWAYSINLINE jnbe_b(Label& L) { jccb(Assembler::above, L); }
970 void ALWAYSINLINE jl_b(Label& L) { jccb(Assembler::less, L); }
971 void ALWAYSINLINE jnge_b(Label& L) { jccb(Assembler::less, L); }
972 void ALWAYSINLINE jge_b(Label& L) { jccb(Assembler::greaterEqual, L); }
973 void ALWAYSINLINE jnl_b(Label& L) { jccb(Assembler::greaterEqual, L); }
974 void ALWAYSINLINE jle_b(Label& L) { jccb(Assembler::lessEqual, L); }
975 void ALWAYSINLINE jng_b(Label& L) { jccb(Assembler::lessEqual, L); }
976 void ALWAYSINLINE jg_b(Label& L) { jccb(Assembler::greater, L); }
977 void ALWAYSINLINE jnle_b(Label& L) { jccb(Assembler::greater, L); }
978 void ALWAYSINLINE jp_b(Label& L) { jccb(Assembler::parity, L); }
979 void ALWAYSINLINE jpe_b(Label& L) { jccb(Assembler::parity, L); }
980 void ALWAYSINLINE jnp_b(Label& L) { jccb(Assembler::noParity, L); }
981 void ALWAYSINLINE jpo_b(Label& L) { jccb(Assembler::noParity, L); }
982 // * No condition for this * void ALWAYSINLINE jcxz_b(Label& L) { jccb(Assembler::cxz, L); }
983 // * No condition for this * void ALWAYSINLINE jecxz_b(Label& L) { jccb(Assembler::cxz, L); }
984
985 // Floating
986
987 void push_f(XMMRegister r);
988 void pop_f(XMMRegister r);
989 void push_d(XMMRegister r);
990 void pop_d(XMMRegister r);
991
992 void push_ppx(Register src);
993 void pop_ppx(Register dst);
994
995 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
996 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
997 void andpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
998
999 void andnpd(XMMRegister dst, XMMRegister src) { Assembler::andnpd(dst, src); }
1000
1001 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
1002 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
1003 void andps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1004
1005 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
1006 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
1007 void comiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1008
1009 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
1010 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
1011 void comisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1012
1013 void orpd(XMMRegister dst, XMMRegister src) { Assembler::orpd(dst, src); }
1014
1015 void cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch = noreg);
1016 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
1017 void ldmxcsr(AddressLiteral src, Register rscratch = noreg);
1018
1019 private:
1020 void sha256_AVX2_one_round_compute(
1021 Register reg_old_h,
1022 Register reg_a,
1023 Register reg_b,
1024 Register reg_c,
1025 Register reg_d,
1026 Register reg_e,
1027 Register reg_f,
1028 Register reg_g,
1029 Register reg_h,
1030 int iter);
1031 void sha256_AVX2_four_rounds_compute_first(int start);
1032 void sha256_AVX2_four_rounds_compute_last(int start);
1033 void sha256_AVX2_one_round_and_sched(
1034 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
1035 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
1036 XMMRegister xmm_2, /* ymm6 */
1037 XMMRegister xmm_3, /* ymm7 */
1038 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
1039 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
1040 Register reg_c, /* edi */
1041 Register reg_d, /* esi */
1042 Register reg_e, /* r8d */
1043 Register reg_f, /* r9d */
1044 Register reg_g, /* r10d */
1045 Register reg_h, /* r11d */
1046 int iter);
1047
1048 void addm(int disp, Register r1, Register r2);
1049
1050 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
1051 Register e, Register f, Register g, Register h, int iteration);
1052
1053 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1054 Register a, Register b, Register c, Register d, Register e, Register f,
1055 Register g, Register h, int iteration);
1056
1057 void addmq(int disp, Register r1, Register r2);
1058 public:
1059 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1060 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1061 Register buf, Register state, Register ofs, Register limit, Register rsp,
1062 bool multi_block, XMMRegister shuf_mask);
1063 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1064 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1065 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
1066 XMMRegister shuf_mask);
1067 void sha512_update_ni_x1(Register arg_hash, Register arg_msg, Register ofs, Register limit, bool multi_block);
1068
1069 void fast_md5(Register buf, Address state, Address ofs, Address limit,
1070 bool multi_block);
1071
1072 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1073 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1074 Register buf, Register state, Register ofs, Register limit, Register rsp,
1075 bool multi_block);
1076
1077 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1078 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1079 Register buf, Register state, Register ofs, Register limit, Register rsp,
1080 bool multi_block, XMMRegister shuf_mask);
1081
1082 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1083 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1084 Register rax, Register rcx, Register rdx, Register tmp);
1085
1086 private:
1087
1088 // these are private because users should be doing movflt/movdbl
1089
1090 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1091 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1092 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1093 void movss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1094
1095 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1096 void movlpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1097
1098 public:
1099
1100 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1101 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1102 void addsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1103
1104 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1105 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1106 void addss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1107
1108 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1109 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1110 void addpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1111
1112 using Assembler::vbroadcasti128;
1113 void vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1114
1115 using Assembler::vbroadcastsd;
1116 void vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1117
1118 using Assembler::vbroadcastss;
1119 void vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1120
1121 // Vector float blend
1122 void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg);
1123 void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg);
1124
1125 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1126 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1127 void divsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1128
1129 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1130 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1131 void divss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1132
1133 // Move Unaligned Double Quadword
1134 void movdqu(Address dst, XMMRegister src);
1135 void movdqu(XMMRegister dst, XMMRegister src);
1136 void movdqu(XMMRegister dst, Address src);
1137 void movdqu(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1138
1139 void kmovwl(Register dst, KRegister src) { Assembler::kmovwl(dst, src); }
1140 void kmovwl(Address dst, KRegister src) { Assembler::kmovwl(dst, src); }
1141 void kmovwl(KRegister dst, KRegister src) { Assembler::kmovwl(dst, src); }
1142 void kmovwl(KRegister dst, Register src) { Assembler::kmovwl(dst, src); }
1143 void kmovwl(KRegister dst, Address src) { Assembler::kmovwl(dst, src); }
1144 void kmovwl(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1145
1146 void kmovql(KRegister dst, KRegister src) { Assembler::kmovql(dst, src); }
1147 void kmovql(KRegister dst, Register src) { Assembler::kmovql(dst, src); }
1148 void kmovql(Register dst, KRegister src) { Assembler::kmovql(dst, src); }
1149 void kmovql(KRegister dst, Address src) { Assembler::kmovql(dst, src); }
1150 void kmovql(Address dst, KRegister src) { Assembler::kmovql(dst, src); }
1151 void kmovql(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1152
1153 // Safe move operation, lowers down to 16bit moves for targets supporting
1154 // AVX512F feature and 64bit moves for targets supporting AVX512BW feature.
1155 void kmov(Address dst, KRegister src);
1156 void kmov(KRegister dst, Address src);
1157 void kmov(KRegister dst, KRegister src);
1158 void kmov(Register dst, KRegister src);
1159 void kmov(KRegister dst, Register src);
1160
1161 using Assembler::movddup;
1162 void movddup(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1163
1164 using Assembler::vmovddup;
1165 void vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1166
1167 // AVX Unaligned forms
1168 void vmovdqu(Address dst, XMMRegister src);
1169 void vmovdqu(XMMRegister dst, Address src);
1170 void vmovdqu(XMMRegister dst, XMMRegister src);
1171 void vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1172 void vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1173 void vmovdqu(XMMRegister dst, XMMRegister src, int vector_len);
1174 void vmovdqu(XMMRegister dst, Address src, int vector_len);
1175 void vmovdqu(Address dst, XMMRegister src, int vector_len);
1176
1177 // AVX Aligned forms
1178 using Assembler::vmovdqa;
1179 void vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1180 void vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1181
1182 // AVX512 Unaligned
1183 void evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len);
1184 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len);
1185 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len);
1186
1187 void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1188 void evmovdqub(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1189
1190 void evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1191 if (dst->encoding() != src->encoding() || mask != k0) {
1192 Assembler::evmovdqub(dst, mask, src, merge, vector_len);
1193 }
1194 }
1195 void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1196 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1197 void evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1198
1199 void evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1200 void evmovdquw(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1201 void evmovdquw(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1202
1203 void evmovdquw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1204 if (dst->encoding() != src->encoding() || mask != k0) {
1205 Assembler::evmovdquw(dst, mask, src, merge, vector_len);
1206 }
1207 }
1208 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1209 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1210 void evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1211
1212 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
1213 if (dst->encoding() != src->encoding()) {
1214 Assembler::evmovdqul(dst, src, vector_len);
1215 }
1216 }
1217 void evmovdqul(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1218 void evmovdqul(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1219
1220 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1221 if (dst->encoding() != src->encoding() || mask != k0) {
1222 Assembler::evmovdqul(dst, mask, src, merge, vector_len);
1223 }
1224 }
1225 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1226 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1227 void evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1228
1229 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
1230 if (dst->encoding() != src->encoding()) {
1231 Assembler::evmovdquq(dst, src, vector_len);
1232 }
1233 }
1234 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1235 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1236 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1237 void evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1238
1239 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1240 if (dst->encoding() != src->encoding() || mask != k0) {
1241 Assembler::evmovdquq(dst, mask, src, merge, vector_len);
1242 }
1243 }
1244 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1245 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1246 void evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1247 void evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1248
1249 using Assembler::movapd;
1250 void movapd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1251
1252 // Move Aligned Double Quadword
1253 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1254 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1255 void movdqa(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1256
1257 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1258 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1259 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1260 void movsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1261
1262 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1263 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1264 void mulpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1265
1266 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1267 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1268 void mulsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1269
1270 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1271 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1272 void mulss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1273
1274 // Carry-Less Multiplication Quadword
1275 void pclmulldq(XMMRegister dst, XMMRegister src) {
1276 // 0x00 - multiply lower 64 bits [0:63]
1277 Assembler::pclmulqdq(dst, src, 0x00);
1278 }
1279 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1280 // 0x11 - multiply upper 64 bits [64:127]
1281 Assembler::pclmulqdq(dst, src, 0x11);
1282 }
1283
1284 void pcmpeqb(XMMRegister dst, XMMRegister src);
1285 void pcmpeqw(XMMRegister dst, XMMRegister src);
1286
1287 void pcmpestri(XMMRegister dst, Address src, int imm8);
1288 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1289
1290 void pmovzxbw(XMMRegister dst, XMMRegister src);
1291 void pmovzxbw(XMMRegister dst, Address src);
1292
1293 void pmovmskb(Register dst, XMMRegister src);
1294
1295 void ptest(XMMRegister dst, XMMRegister src);
1296
1297 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1298 void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1299 void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch = noreg);
1300
1301 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1302 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1303 void sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1304
1305 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1306 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1307 void subsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1308
1309 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1310 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1311 void subss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1312
1313 void evucomish(XMMRegister dst, XMMRegister src) { Assembler::evucomish(dst, src); }
1314 void evucomish(XMMRegister dst, Address src) { Assembler::evucomish(dst, src); }
1315 void evucomish(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1316
1317 void evucomxsh(XMMRegister dst, XMMRegister src) { Assembler::evucomxsh(dst, src); }
1318 void evucomxsh(XMMRegister dst, Address src) { Assembler::evucomxsh(dst, src); }
1319 void evucomxsh(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1320
1321 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1322 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1323 void ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1324
1325 void evucomxss(XMMRegister dst, XMMRegister src) { Assembler::evucomxss(dst, src); }
1326 void evucomxss(XMMRegister dst, Address src) { Assembler::evucomxss(dst, src); }
1327 void evucomxss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1328
1329 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1330 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1331 void ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1332
1333 void evucomxsd(XMMRegister dst, XMMRegister src) { Assembler::evucomxsd(dst, src); }
1334 void evucomxsd(XMMRegister dst, Address src) { Assembler::evucomxsd(dst, src); }
1335 void evucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1336
1337 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1338 void xorpd(XMMRegister dst, XMMRegister src);
1339 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1340 void xorpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1341
1342 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1343 void xorps(XMMRegister dst, XMMRegister src);
1344 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1345 void xorps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1346
1347 // Shuffle Bytes
1348 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1349 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1350 void pshufb(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1351 // AVX 3-operands instructions
1352
1353 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1354 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1355 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1356
1357 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1358 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1359 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1360
1361 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1362 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1363
1364 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1365 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1366 void vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1367
1368 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1369 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1370
1371 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1372 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1373 void vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1374
1375 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1376 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1377 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1378
1379 using Assembler::vpbroadcastd;
1380 void vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1381
1382 using Assembler::vpbroadcastq;
1383 void vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1384
1385 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1386 void vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len);
1387
1388 void vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1389 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1390 using Assembler::evpcmpeqd;
1391 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1392
1393 // Vector compares
1394 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1395 Assembler::evpcmpd(kdst, mask, nds, src, comparison, is_signed, vector_len);
1396 }
1397 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1398
1399 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1400 Assembler::evpcmpq(kdst, mask, nds, src, comparison, is_signed, vector_len);
1401 }
1402 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1403
1404 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1405 Assembler::evpcmpb(kdst, mask, nds, src, comparison, is_signed, vector_len);
1406 }
1407 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1408
1409 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1410 Assembler::evpcmpw(kdst, mask, nds, src, comparison, is_signed, vector_len);
1411 }
1412 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1413
1414 void evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len);
1415
1416 // Emit comparison instruction for the specified comparison predicate.
1417 void vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len);
1418 void vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len);
1419
1420 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1421 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1422
1423 void vpmovmskb(Register dst, XMMRegister src, int vector_len = Assembler::AVX_256bit);
1424
1425 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1426 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1427
1428 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1429 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1430 void vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1431
1432 void vpmuldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpmuldq(dst, nds, src, vector_len); }
1433
1434 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1435 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1436
1437 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1438 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1439
1440 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1441 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1442
1443 void evpsrad(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1444 void evpsrad(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1445
1446 void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1447 void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1448
1449 using Assembler::evpsllw;
1450 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1451 if (!is_varshift) {
1452 Assembler::evpsllw(dst, mask, nds, src, merge, vector_len);
1453 } else {
1454 Assembler::evpsllvw(dst, mask, nds, src, merge, vector_len);
1455 }
1456 }
1457 void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1458 if (!is_varshift) {
1459 Assembler::evpslld(dst, mask, nds, src, merge, vector_len);
1460 } else {
1461 Assembler::evpsllvd(dst, mask, nds, src, merge, vector_len);
1462 }
1463 }
1464 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1465 if (!is_varshift) {
1466 Assembler::evpsllq(dst, mask, nds, src, merge, vector_len);
1467 } else {
1468 Assembler::evpsllvq(dst, mask, nds, src, merge, vector_len);
1469 }
1470 }
1471 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1472 if (!is_varshift) {
1473 Assembler::evpsrlw(dst, mask, nds, src, merge, vector_len);
1474 } else {
1475 Assembler::evpsrlvw(dst, mask, nds, src, merge, vector_len);
1476 }
1477 }
1478 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1479 if (!is_varshift) {
1480 Assembler::evpsrld(dst, mask, nds, src, merge, vector_len);
1481 } else {
1482 Assembler::evpsrlvd(dst, mask, nds, src, merge, vector_len);
1483 }
1484 }
1485
1486 using Assembler::evpsrlq;
1487 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1488 if (!is_varshift) {
1489 Assembler::evpsrlq(dst, mask, nds, src, merge, vector_len);
1490 } else {
1491 Assembler::evpsrlvq(dst, mask, nds, src, merge, vector_len);
1492 }
1493 }
1494 using Assembler::evpsraw;
1495 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1496 if (!is_varshift) {
1497 Assembler::evpsraw(dst, mask, nds, src, merge, vector_len);
1498 } else {
1499 Assembler::evpsravw(dst, mask, nds, src, merge, vector_len);
1500 }
1501 }
1502 using Assembler::evpsrad;
1503 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1504 if (!is_varshift) {
1505 Assembler::evpsrad(dst, mask, nds, src, merge, vector_len);
1506 } else {
1507 Assembler::evpsravd(dst, mask, nds, src, merge, vector_len);
1508 }
1509 }
1510 using Assembler::evpsraq;
1511 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1512 if (!is_varshift) {
1513 Assembler::evpsraq(dst, mask, nds, src, merge, vector_len);
1514 } else {
1515 Assembler::evpsravq(dst, mask, nds, src, merge, vector_len);
1516 }
1517 }
1518
1519 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1520 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1521 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1522 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1523
1524 void evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1525 void evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1526 void evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1527 void evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1528
1529 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1530 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1531
1532 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1533 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1534
1535 void vptest(XMMRegister dst, XMMRegister src);
1536 void vptest(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vptest(dst, src, vector_len); }
1537
1538 void punpcklbw(XMMRegister dst, XMMRegister src);
1539 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1540
1541 void pshufd(XMMRegister dst, Address src, int mode);
1542 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1543
1544 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1545 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1546
1547 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1548 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1549 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1550
1551 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1552 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1553 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1554
1555 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1556
1557 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1558 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1559 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1560
1561 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1562 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1563 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1564
1565 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1566 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1567 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1568
1569 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1570 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1571 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1572
1573 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1574 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1575 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1576
1577 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1578 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1579 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1580
1581 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1582 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1583
1584 // AVX Vector instructions
1585
1586 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1587 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1588 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1589
1590 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1591 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1592 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1593
1594 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1595 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1596 Assembler::vpxor(dst, nds, src, vector_len);
1597 else
1598 Assembler::vxorpd(dst, nds, src, vector_len);
1599 }
1600 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1601 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1602 Assembler::vpxor(dst, nds, src, vector_len);
1603 else
1604 Assembler::vxorpd(dst, nds, src, vector_len);
1605 }
1606 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1607
1608 // Simple version for AVX2 256bit vectors
1609 void vpxor(XMMRegister dst, XMMRegister src) {
1610 assert(UseAVX >= 2, "Should be at least AVX2");
1611 Assembler::vpxor(dst, dst, src, AVX_256bit);
1612 }
1613 void vpxor(XMMRegister dst, Address src) {
1614 assert(UseAVX >= 2, "Should be at least AVX2");
1615 Assembler::vpxor(dst, dst, src, AVX_256bit);
1616 }
1617
1618 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpermd(dst, nds, src, vector_len); }
1619 void vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1620
1621 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1622 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1623 Assembler::vinserti32x4(dst, nds, src, imm8);
1624 } else if (UseAVX > 1) {
1625 // vinserti128 is available only in AVX2
1626 Assembler::vinserti128(dst, nds, src, imm8);
1627 } else {
1628 Assembler::vinsertf128(dst, nds, src, imm8);
1629 }
1630 }
1631
1632 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1633 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1634 Assembler::vinserti32x4(dst, nds, src, imm8);
1635 } else if (UseAVX > 1) {
1636 // vinserti128 is available only in AVX2
1637 Assembler::vinserti128(dst, nds, src, imm8);
1638 } else {
1639 Assembler::vinsertf128(dst, nds, src, imm8);
1640 }
1641 }
1642
1643 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1644 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1645 Assembler::vextracti32x4(dst, src, imm8);
1646 } else if (UseAVX > 1) {
1647 // vextracti128 is available only in AVX2
1648 Assembler::vextracti128(dst, src, imm8);
1649 } else {
1650 Assembler::vextractf128(dst, src, imm8);
1651 }
1652 }
1653
1654 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1655 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1656 Assembler::vextracti32x4(dst, src, imm8);
1657 } else if (UseAVX > 1) {
1658 // vextracti128 is available only in AVX2
1659 Assembler::vextracti128(dst, src, imm8);
1660 } else {
1661 Assembler::vextractf128(dst, src, imm8);
1662 }
1663 }
1664
1665 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1666 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1667 vinserti128(dst, dst, src, 1);
1668 }
1669 void vinserti128_high(XMMRegister dst, Address src) {
1670 vinserti128(dst, dst, src, 1);
1671 }
1672 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1673 vextracti128(dst, src, 1);
1674 }
1675 void vextracti128_high(Address dst, XMMRegister src) {
1676 vextracti128(dst, src, 1);
1677 }
1678
1679 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1680 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1681 Assembler::vinsertf32x4(dst, dst, src, 1);
1682 } else {
1683 Assembler::vinsertf128(dst, dst, src, 1);
1684 }
1685 }
1686
1687 void vinsertf128_high(XMMRegister dst, Address src) {
1688 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1689 Assembler::vinsertf32x4(dst, dst, src, 1);
1690 } else {
1691 Assembler::vinsertf128(dst, dst, src, 1);
1692 }
1693 }
1694
1695 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1696 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1697 Assembler::vextractf32x4(dst, src, 1);
1698 } else {
1699 Assembler::vextractf128(dst, src, 1);
1700 }
1701 }
1702
1703 void vextractf128_high(Address dst, XMMRegister src) {
1704 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1705 Assembler::vextractf32x4(dst, src, 1);
1706 } else {
1707 Assembler::vextractf128(dst, src, 1);
1708 }
1709 }
1710
1711 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1712 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1713 Assembler::vinserti64x4(dst, dst, src, 1);
1714 }
1715 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1716 Assembler::vinsertf64x4(dst, dst, src, 1);
1717 }
1718 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1719 Assembler::vextracti64x4(dst, src, 1);
1720 }
1721 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1722 Assembler::vextractf64x4(dst, src, 1);
1723 }
1724 void vextractf64x4_high(Address dst, XMMRegister src) {
1725 Assembler::vextractf64x4(dst, src, 1);
1726 }
1727 void vinsertf64x4_high(XMMRegister dst, Address src) {
1728 Assembler::vinsertf64x4(dst, dst, src, 1);
1729 }
1730
1731 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1732 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1733 vinserti128(dst, dst, src, 0);
1734 }
1735 void vinserti128_low(XMMRegister dst, Address src) {
1736 vinserti128(dst, dst, src, 0);
1737 }
1738 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1739 vextracti128(dst, src, 0);
1740 }
1741 void vextracti128_low(Address dst, XMMRegister src) {
1742 vextracti128(dst, src, 0);
1743 }
1744
1745 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1746 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1747 Assembler::vinsertf32x4(dst, dst, src, 0);
1748 } else {
1749 Assembler::vinsertf128(dst, dst, src, 0);
1750 }
1751 }
1752
1753 void vinsertf128_low(XMMRegister dst, Address src) {
1754 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1755 Assembler::vinsertf32x4(dst, dst, src, 0);
1756 } else {
1757 Assembler::vinsertf128(dst, dst, src, 0);
1758 }
1759 }
1760
1761 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1762 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1763 Assembler::vextractf32x4(dst, src, 0);
1764 } else {
1765 Assembler::vextractf128(dst, src, 0);
1766 }
1767 }
1768
1769 void vextractf128_low(Address dst, XMMRegister src) {
1770 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1771 Assembler::vextractf32x4(dst, src, 0);
1772 } else {
1773 Assembler::vextractf128(dst, src, 0);
1774 }
1775 }
1776
1777 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1778 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1779 Assembler::vinserti64x4(dst, dst, src, 0);
1780 }
1781 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1782 Assembler::vinsertf64x4(dst, dst, src, 0);
1783 }
1784 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1785 Assembler::vextracti64x4(dst, src, 0);
1786 }
1787 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1788 Assembler::vextractf64x4(dst, src, 0);
1789 }
1790 void vextractf64x4_low(Address dst, XMMRegister src) {
1791 Assembler::vextractf64x4(dst, src, 0);
1792 }
1793 void vinsertf64x4_low(XMMRegister dst, Address src) {
1794 Assembler::vinsertf64x4(dst, dst, src, 0);
1795 }
1796
1797 // Carry-Less Multiplication Quadword
1798 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1799 // 0x00 - multiply lower 64 bits [0:63]
1800 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1801 }
1802 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1803 // 0x11 - multiply upper 64 bits [64:127]
1804 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1805 }
1806 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1807 // 0x10 - multiply nds[0:63] and src[64:127]
1808 Assembler::vpclmulqdq(dst, nds, src, 0x10);
1809 }
1810 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1811 //0x01 - multiply nds[64:127] and src[0:63]
1812 Assembler::vpclmulqdq(dst, nds, src, 0x01);
1813 }
1814
1815 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1816 // 0x00 - multiply lower 64 bits [0:63]
1817 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1818 }
1819 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1820 // 0x11 - multiply upper 64 bits [64:127]
1821 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1822 }
1823
1824 // AVX-512 mask operations.
1825 void kand(BasicType etype, KRegister dst, KRegister src1, KRegister src2);
1826 void kor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1827 void knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp = knoreg, Register rtmp = noreg);
1828 void kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1829 void kortest(uint masklen, KRegister src1, KRegister src2);
1830 void ktest(uint masklen, KRegister src1, KRegister src2);
1831
1832 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1833 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1834
1835 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1836 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1837
1838 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1839 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1840
1841 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1842 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1843
1844 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1845 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1846 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1847 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1848
1849 using Assembler::evpandq;
1850 void evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1851
1852 using Assembler::evpaddq;
1853 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1854
1855 using Assembler::evporq;
1856 void evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1857
1858 using Assembler::vpshufb;
1859 void vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1860
1861 using Assembler::vpor;
1862 void vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1863
1864 using Assembler::vpternlogq;
1865 void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch = noreg);
1866
1867 void cmov32( Condition cc, Register dst, Address src);
1868 void cmov32( Condition cc, Register dst, Register src);
1869
1870 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1871
1872 void cmovptr(Condition cc, Register dst, Address src) { cmovq(cc, dst, src); }
1873 void cmovptr(Condition cc, Register dst, Register src) { cmovq(cc, dst, src); }
1874
1875 void movoop(Register dst, jobject obj);
1876 void movoop(Address dst, jobject obj, Register rscratch);
1877
1878 void mov_metadata(Register dst, Metadata* obj);
1879 void mov_metadata(Address dst, Metadata* obj, Register rscratch);
1880
1881 void mov64(Register dst, int64_t imm64);
1882 void mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format);
1883
1884 void movptr(Register dst, Register src);
1885 void movptr(Register dst, Address src);
1886 void movptr(Register dst, AddressLiteral src);
1887 void movptr(Register dst, ArrayAddress src);
1888 void movptr(Register dst, intptr_t src);
1889 void movptr(Address dst, Register src);
1890 void movptr(Address dst, int32_t imm);
1891 void movptr(Address dst, intptr_t src, Register rscratch);
1892 void movptr(ArrayAddress dst, Register src, Register rscratch);
1893
1894 void movptr(Register dst, RegisterOrConstant src) {
1895 if (src.is_constant()) movptr(dst, src.as_constant());
1896 else movptr(dst, src.as_register());
1897 }
1898
1899
1900 // to avoid hiding movl
1901 void mov32(Register dst, AddressLiteral src);
1902 void mov32(AddressLiteral dst, Register src, Register rscratch = noreg);
1903
1904 // Import other mov() methods from the parent class or else
1905 // they will be hidden by the following overriding declaration.
1906 using Assembler::movdl;
1907 void movdl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1908
1909 using Assembler::movq;
1910 void movq(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1911
1912 // Can push value or effective address
1913 void pushptr(AddressLiteral src, Register rscratch);
1914
1915 void pushptr(Address src) { pushq(src); }
1916 void popptr(Address src) { popq(src); }
1917
1918 void pushoop(jobject obj, Register rscratch);
1919 void pushklass(Metadata* obj, Register rscratch);
1920
1921 // sign extend as need a l to ptr sized element
1922 void movl2ptr(Register dst, Address src) { movslq(dst, src); }
1923 void movl2ptr(Register dst, Register src) { movslq(dst, src); }
1924
1925
1926 public:
1927 // clear memory of size 'cnt' qwords, starting at 'base';
1928 // if 'is_large' is set, do not try to produce short loop
1929 void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large, KRegister mask=knoreg);
1930
1931 // clear memory initialization sequence for constant size;
1932 void clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1933
1934 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1935 void xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1936
1937 // Fill primitive arrays
1938 void generate_fill(BasicType t, bool aligned,
1939 Register to, Register value, Register count,
1940 Register rtmp, XMMRegister xtmp);
1941
1942 void encode_iso_array(Register src, Register dst, Register len,
1943 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1944 XMMRegister tmp4, Register tmp5, Register result, bool ascii);
1945
1946 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1947 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1948 Register y, Register y_idx, Register z,
1949 Register carry, Register product,
1950 Register idx, Register kdx);
1951 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1952 Register yz_idx, Register idx,
1953 Register carry, Register product, int offset);
1954 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1955 Register carry, Register carry2,
1956 Register idx, Register jdx,
1957 Register yz_idx1, Register yz_idx2,
1958 Register tmp, Register tmp3, Register tmp4);
1959 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1960 Register yz_idx, Register idx, Register jdx,
1961 Register carry, Register product,
1962 Register carry2);
1963 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
1964 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1965 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1966 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1967 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1968 Register tmp2);
1969 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1970 Register rdxReg, Register raxReg);
1971 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1972 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1973 Register tmp3, Register tmp4);
1974 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1975 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1976
1977 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1978 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1979 Register raxReg);
1980 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1981 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1982 Register raxReg);
1983 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1984 Register result, Register tmp1, Register tmp2,
1985 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1986
1987 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1988 void update_byte_crc32(Register crc, Register val, Register table);
1989 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1990
1991 void kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2);
1992 void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
1993 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
1994 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup);
1995
1996 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1997 // Note on a naming convention:
1998 // Prefix w = register only used on a Westmere+ architecture
1999 // Prefix n = register only used on a Nehalem architecture
2000 void crc32c_ipl_alg4(Register in_out, uint32_t n,
2001 Register tmp1, Register tmp2, Register tmp3);
2002 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
2003 Register in_out,
2004 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
2005 XMMRegister w_xtmp2,
2006 Register tmp1,
2007 Register n_tmp2, Register n_tmp3);
2008 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
2009 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2010 Register tmp1, Register tmp2,
2011 Register n_tmp3);
2012 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
2013 Register in_out1, Register in_out2, Register in_out3,
2014 Register tmp1, Register tmp2, Register tmp3,
2015 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2016 Register tmp4, Register tmp5,
2017 Register n_tmp6);
2018 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
2019 Register tmp1, Register tmp2, Register tmp3,
2020 Register tmp4, Register tmp5, Register tmp6,
2021 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2022 bool is_pclmulqdq_supported);
2023 // Fold 128-bit data chunk
2024 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
2025 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
2026 // Fold 512-bit data chunk
2027 void fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, Register pos, int offset);
2028 // Fold 8-bit data
2029 void fold_8bit_crc32(Register crc, Register table, Register tmp);
2030 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
2031
2032 // Compress char[] array to byte[].
2033 void char_array_compress(Register src, Register dst, Register len,
2034 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
2035 XMMRegister tmp4, Register tmp5, Register result,
2036 KRegister mask1 = knoreg, KRegister mask2 = knoreg);
2037
2038 // Inflate byte[] array to char[].
2039 void byte_array_inflate(Register src, Register dst, Register len,
2040 XMMRegister tmp1, Register tmp2, KRegister mask = knoreg);
2041
2042 void fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
2043 Register length, Register temp, int vec_enc);
2044
2045 void fill64_masked(uint shift, Register dst, int disp,
2046 XMMRegister xmm, KRegister mask, Register length,
2047 Register temp, bool use64byteVector = false);
2048
2049 void fill32_masked(uint shift, Register dst, int disp,
2050 XMMRegister xmm, KRegister mask, Register length,
2051 Register temp);
2052
2053 void fill32(Address dst, XMMRegister xmm);
2054
2055 void fill32(Register dst, int disp, XMMRegister xmm);
2056
2057 void fill64(Address dst, XMMRegister xmm, bool use64byteVector = false);
2058
2059 void fill64(Register dst, int dis, XMMRegister xmm, bool use64byteVector = false);
2060
2061 void convert_f2i(Register dst, XMMRegister src);
2062 void convert_d2i(Register dst, XMMRegister src);
2063 void convert_f2l(Register dst, XMMRegister src);
2064 void convert_d2l(Register dst, XMMRegister src);
2065 void round_double(Register dst, XMMRegister src, Register rtmp, Register rcx);
2066 void round_float(Register dst, XMMRegister src, Register rtmp, Register rcx);
2067
2068 void cache_wb(Address line);
2069 void cache_wbsync(bool is_pre);
2070
2071 #ifdef COMPILER2_OR_JVMCI
2072 void generate_fill_avx3(BasicType type, Register to, Register value,
2073 Register count, Register rtmp, XMMRegister xtmp);
2074 #endif // COMPILER2_OR_JVMCI
2075
2076 void vallones(XMMRegister dst, int vector_len);
2077
2078 void check_stack_alignment(Register sp, const char* msg, unsigned bias = 0, Register tmp = noreg);
2079
2080 void fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow);
2081 void fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow);
2082
2083 void save_legacy_gprs();
2084 void restore_legacy_gprs();
2085 void load_aotrc_address(Register reg, address a);
2086 void setcc(Assembler::Condition comparison, Register dst);
2087 };
2088
2089 #endif // CPU_X86_MACROASSEMBLER_X86_HPP