1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "asm/register.hpp"
30 #include "code/vmreg.inline.hpp"
31 #include "compiler/oopMap.hpp"
32 #include "utilities/macros.hpp"
33 #include "runtime/vm_version.hpp"
34 #include "utilities/checkedCast.hpp"
35
36 // MacroAssembler extends Assembler by frequently used macros.
37 //
38 // Instructions for which a 'better' code sequence exists depending
39 // on arguments should also go in here.
40
41 class MacroAssembler: public Assembler {
42 friend class LIR_Assembler;
43 friend class Runtime1; // as_Address()
44
45 public:
46 // Support for VM calls
47 //
48 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
49 // may customize this version by overriding it for its purposes (e.g., to save/restore
50 // additional registers when doing a VM call).
51
52 virtual void call_VM_leaf_base(
53 address entry_point, // the entry point
54 int number_of_arguments // the number of arguments to pop after the call
55 );
56
57 protected:
58 // This is the base routine called by the different versions of call_VM. The interpreter
59 // may customize this version by overriding it for its purposes (e.g., to save/restore
60 // additional registers when doing a VM call).
61 //
62 // call_VM_base returns the register which contains the thread upon return.
63 // If no last_java_sp is specified (noreg) than rsp will be used instead.
64 virtual void call_VM_base( // returns the register containing the thread upon return
65 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
66 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
67 address entry_point, // the entry point
68 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
69 bool check_exceptions // whether to check for pending exceptions after return
70 );
71
72 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
73
74 public:
75 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
76
77 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
78 // The implementation is only non-empty for the InterpreterMacroAssembler,
79 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
80 virtual void check_and_handle_popframe();
81 virtual void check_and_handle_earlyret();
82
83 Address as_Address(AddressLiteral adr);
84 Address as_Address(ArrayAddress adr, Register rscratch);
85
86 // Support for null-checks
87 //
88 // Generates code that causes a null OS exception if the content of reg is null.
89 // If the accessed location is M[reg + offset] and the offset is known, provide the
90 // offset. No explicit code generation is needed if the offset is within a certain
91 // range (0 <= offset <= page_size).
92
93 void null_check(Register reg, int offset = -1);
94 static bool needs_explicit_null_check(intptr_t offset);
95 static bool uses_implicit_null_check(void* address);
96
97 // Required platform-specific helpers for Label::patch_instructions.
98 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
99 void pd_patch_instruction(address branch, address target, const char* file, int line) {
100 unsigned char op = branch[0];
101 assert(op == 0xE8 /* call */ ||
102 op == 0xE9 /* jmp */ ||
103 op == 0xEB /* short jmp */ ||
104 (op & 0xF0) == 0x70 /* short jcc */ ||
105 (op == 0x0F && (branch[1] & 0xF0) == 0x80) /* jcc */ ||
106 (op == 0xC7 && branch[1] == 0xF8) /* xbegin */ ||
107 (op == 0x8D) /* lea */,
108 "Invalid opcode at patch point");
109
110 if (op == 0xEB || (op & 0xF0) == 0x70) {
111 // short offset operators (jmp and jcc)
112 char* disp = (char*) &branch[1];
113 int imm8 = checked_cast<int>(target - (address) &disp[1]);
114 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
115 file == nullptr ? "<null>" : file, line);
116 *disp = (char)imm8;
117 } else {
118 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7 || op == 0x8D) ? 2 : 1];
119 int imm32 = checked_cast<int>(target - (address) &disp[1]);
120 *disp = imm32;
121 }
122 }
123
124 // The following 4 methods return the offset of the appropriate move instruction
125
126 // Support for fast byte/short loading with zero extension (depending on particular CPU)
127 int load_unsigned_byte(Register dst, Address src);
128 int load_unsigned_short(Register dst, Address src);
129
130 // Support for fast byte/short loading with sign extension (depending on particular CPU)
131 int load_signed_byte(Register dst, Address src);
132 int load_signed_short(Register dst, Address src);
133
134 // Support for sign-extension (hi:lo = extend_sign(lo))
135 void extend_sign(Register hi, Register lo);
136
137 // Load and store values by size and signed-ness
138 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
139 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
140
141 // Support for inc/dec with optimal instruction selection depending on value
142
143 void increment(Register reg, int value = 1) { incrementq(reg, value); }
144 void decrement(Register reg, int value = 1) { decrementq(reg, value); }
145 void increment(Address dst, int value = 1) { incrementq(dst, value); }
146 void decrement(Address dst, int value = 1) { decrementq(dst, value); }
147
148 void decrementl(Address dst, int value = 1);
149 void decrementl(Register reg, int value = 1);
150
151 void decrementq(Register reg, int value = 1);
152 void decrementq(Address dst, int value = 1);
153
154 void incrementl(Address dst, int value = 1);
155 void incrementl(Register reg, int value = 1);
156
157 void incrementq(Register reg, int value = 1);
158 void incrementq(Address dst, int value = 1);
159
160 void incrementl(AddressLiteral dst, Register rscratch = noreg);
161 void incrementl(ArrayAddress dst, Register rscratch);
162
163 void incrementq(AddressLiteral dst, Register rscratch = noreg);
164
165 void movhlf(XMMRegister dst, XMMRegister src, Register rscratch = noreg);
166
167 // Support optimal SSE move instructions.
168 void movflt(XMMRegister dst, XMMRegister src) {
169 if (dst-> encoding() == src->encoding()) return;
170 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
171 else { movss (dst, src); return; }
172 }
173 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
174 void movflt(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
175 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
176
177 // Move with zero extension
178 void movfltz(XMMRegister dst, XMMRegister src) { movss(dst, src); }
179
180 void movdbl(XMMRegister dst, XMMRegister src) {
181 if (dst-> encoding() == src->encoding()) return;
182 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
183 else { movsd (dst, src); return; }
184 }
185
186 void movdbl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
187
188 void movdbl(XMMRegister dst, Address src) {
189 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
190 else { movlpd(dst, src); return; }
191 }
192 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
193
194 void flt_to_flt16(Register dst, XMMRegister src, XMMRegister tmp) {
195 // Use separate tmp XMM register because caller may
196 // requires src XMM register to be unchanged (as in x86.ad).
197 vcvtps2ph(tmp, src, 0x04, Assembler::AVX_128bit);
198 movdl(dst, tmp);
199 movswl(dst, dst);
200 }
201
202 void flt16_to_flt(XMMRegister dst, Register src) {
203 movdl(dst, src);
204 vcvtph2ps(dst, dst, Assembler::AVX_128bit);
205 }
206
207 // Alignment
208 void align32();
209 void align64();
210 void align(uint modulus);
211 void align(uint modulus, uint target);
212
213 void post_call_nop();
214
215 // Stack frame creation/removal
216 void enter();
217 void leave();
218
219 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information).
220 // The pointer will be loaded into the thread register. This is a slow version that does native call.
221 // Normally, JavaThread pointer is available in r15_thread, use that where possible.
222 void get_thread_slow(Register thread);
223
224 // Support for argument shuffling
225
226 // bias in bytes
227 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
228 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
229 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
230 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
231 void move_ptr(VMRegPair src, VMRegPair dst);
232 void object_move(OopMap* map,
233 int oop_handle_offset,
234 int framesize_in_slots,
235 VMRegPair src,
236 VMRegPair dst,
237 bool is_receiver,
238 int* receiver_offset);
239
240 // Support for VM calls
241 //
242 // It is imperative that all calls into the VM are handled via the call_VM macros.
243 // They make sure that the stack linkage is setup correctly. call_VM's correspond
244 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
245
246
247 void call_VM(Register oop_result,
248 address entry_point,
249 bool check_exceptions = true);
250 void call_VM(Register oop_result,
251 address entry_point,
252 Register arg_1,
253 bool check_exceptions = true);
254 void call_VM(Register oop_result,
255 address entry_point,
256 Register arg_1, Register arg_2,
257 bool check_exceptions = true);
258 void call_VM(Register oop_result,
259 address entry_point,
260 Register arg_1, Register arg_2, Register arg_3,
261 bool check_exceptions = true);
262
263 // Overloadings with last_Java_sp
264 void call_VM(Register oop_result,
265 Register last_java_sp,
266 address entry_point,
267 int number_of_arguments = 0,
268 bool check_exceptions = true);
269 void call_VM(Register oop_result,
270 Register last_java_sp,
271 address entry_point,
272 Register arg_1, bool
273 check_exceptions = true);
274 void call_VM(Register oop_result,
275 Register last_java_sp,
276 address entry_point,
277 Register arg_1, Register arg_2,
278 bool check_exceptions = true);
279 void call_VM(Register oop_result,
280 Register last_java_sp,
281 address entry_point,
282 Register arg_1, Register arg_2, Register arg_3,
283 bool check_exceptions = true);
284
285 void get_vm_result_oop(Register oop_result);
286 void get_vm_result_metadata(Register metadata_result);
287
288 // These always tightly bind to MacroAssembler::call_VM_base
289 // bypassing the virtual implementation
290 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
291 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
292 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
293 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
294 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
295
296 void call_VM_leaf0(address entry_point);
297 void call_VM_leaf(address entry_point,
298 int number_of_arguments = 0);
299 void call_VM_leaf(address entry_point,
300 Register arg_1);
301 void call_VM_leaf(address entry_point,
302 Register arg_1, Register arg_2);
303 void call_VM_leaf(address entry_point,
304 Register arg_1, Register arg_2, Register arg_3);
305
306 void call_VM_leaf(address entry_point,
307 Register arg_1, Register arg_2, Register arg_3, Register arg_4);
308
309 // These always tightly bind to MacroAssembler::call_VM_leaf_base
310 // bypassing the virtual implementation
311 void super_call_VM_leaf(address entry_point);
312 void super_call_VM_leaf(address entry_point, Register arg_1);
313 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
314 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
315 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
316
317 void set_last_Java_frame(Register last_java_sp,
318 Register last_java_fp,
319 address last_java_pc,
320 Register rscratch);
321
322 void set_last_Java_frame(Register last_java_sp,
323 Register last_java_fp,
324 Label &last_java_pc,
325 Register scratch);
326
327 void reset_last_Java_frame(bool clear_fp);
328
329 // jobjects
330 void clear_jobject_tag(Register possibly_non_local);
331 void resolve_jobject(Register value, Register tmp);
332 void resolve_global_jobject(Register value, Register tmp);
333
334 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
335 void c2bool(Register x);
336
337 // C++ bool manipulation
338
339 void movbool(Register dst, Address src);
340 void movbool(Address dst, bool boolconst);
341 void movbool(Address dst, Register src);
342 void testbool(Register dst);
343
344 void resolve_oop_handle(Register result, Register tmp);
345 void resolve_weak_handle(Register result, Register tmp);
346 void load_mirror(Register mirror, Register method, Register tmp);
347 void load_method_holder_cld(Register rresult, Register rmethod);
348
349 void load_method_holder(Register holder, Register method);
350
351 // oop manipulations
352 void load_narrow_klass_compact(Register dst, Register src);
353 void load_narrow_klass(Register dst, Register src);
354 void load_klass(Register dst, Register src, Register tmp);
355 void store_klass(Register dst, Register src, Register tmp);
356
357 // Compares the narrow Klass pointer of an object to a given narrow Klass.
358 void cmp_klass(Register klass, Register obj, Register tmp);
359
360 // Compares the Klass pointer of two objects obj1 and obj2. Result is in the condition flags.
361 // Uses tmp1 and tmp2 as temporary registers.
362 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
363
364 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
365 Register tmp1);
366 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
367 Register tmp1, Register tmp2, Register tmp3);
368
369 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg, DecoratorSet decorators = 0);
370 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg, DecoratorSet decorators = 0);
371 void store_heap_oop(Address dst, Register val, Register tmp1 = noreg,
372 Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
373
374 // Used for storing null. All other oop constants should be
375 // stored using routines that take a jobject.
376 void store_heap_oop_null(Address dst);
377
378 void store_klass_gap(Register dst, Register src);
379
380 // This dummy is to prevent a call to store_heap_oop from
381 // converting a zero (like null) into a Register by giving
382 // the compiler two choices it can't resolve
383
384 void store_heap_oop(Address dst, void* dummy);
385
386 void encode_heap_oop(Register r);
387 void decode_heap_oop(Register r);
388 void encode_heap_oop_not_null(Register r);
389 void decode_heap_oop_not_null(Register r);
390 void encode_heap_oop_not_null(Register dst, Register src);
391 void decode_heap_oop_not_null(Register dst, Register src);
392
393 void set_narrow_oop(Register dst, jobject obj);
394 void set_narrow_oop(Address dst, jobject obj);
395 void cmp_narrow_oop(Register dst, jobject obj);
396 void cmp_narrow_oop(Address dst, jobject obj);
397
398 void encode_klass_not_null(Register r, Register tmp);
399 void decode_klass_not_null(Register r, Register tmp);
400 void encode_and_move_klass_not_null(Register dst, Register src);
401 void decode_and_move_klass_not_null(Register dst, Register src);
402 void set_narrow_klass(Register dst, Klass* k);
403 void set_narrow_klass(Address dst, Klass* k);
404 void cmp_narrow_klass(Register dst, Klass* k);
405 void cmp_narrow_klass(Address dst, Klass* k);
406
407 // if heap base register is used - reinit it with the correct value
408 void reinit_heapbase();
409
410 DEBUG_ONLY(void verify_heapbase(const char* msg);)
411
412 // Int division/remainder for Java
413 // (as idivl, but checks for special case as described in JVM spec.)
414 // returns idivl instruction offset for implicit exception handling
415 int corrected_idivl(Register reg);
416
417 // Long division/remainder for Java
418 // (as idivq, but checks for special case as described in JVM spec.)
419 // returns idivq instruction offset for implicit exception handling
420 int corrected_idivq(Register reg);
421
422 void int3();
423
424 // Long operation macros for a 32bit cpu
425 // Long negation for Java
426 void lneg(Register hi, Register lo);
427
428 // Long multiplication for Java
429 // (destroys contents of eax, ebx, ecx and edx)
430 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
431
432 // Long shifts for Java
433 // (semantics as described in JVM spec.)
434 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
435 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
436
437 // Long compare for Java
438 // (semantics as described in JVM spec.)
439 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
440
441
442 // misc
443
444 // Sign extension
445 void sign_extend_short(Register reg);
446 void sign_extend_byte(Register reg);
447
448 // Clean up a subword typed value to the representation in compliance with JVMS ยง2.3
449 void narrow_subword_type(Register reg, BasicType bt);
450
451 // Division by power of 2, rounding towards 0
452 void division_with_shift(Register reg, int shift_value);
453
454 // dst = c = a * b + c
455 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
456 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
457
458 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
459 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
460 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
461 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
462
463
464 // same as fcmp2int, but using SSE2
465 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
466 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
467
468 void push_IU_state();
469 void pop_IU_state();
470
471 void push_FPU_state();
472 void pop_FPU_state();
473
474 void push_CPU_state();
475 void pop_CPU_state();
476
477 void push_cont_fastpath();
478 void pop_cont_fastpath();
479
480 DEBUG_ONLY(void stop_if_in_cont(Register cont_reg, const char* name);)
481
482 // Round up to a power of two
483 void round_to(Register reg, int modulus);
484
485 private:
486 // General purpose and XMM registers potentially clobbered by native code; there
487 // is no need for FPU or AVX opmask related methods because C1/interpreter
488 // - we save/restore FPU state as a whole always
489 // - do not care about AVX-512 opmask
490 static RegSet call_clobbered_gp_registers();
491 static XMMRegSet call_clobbered_xmm_registers();
492
493 void push_set(XMMRegSet set, int offset);
494 void pop_set(XMMRegSet set, int offset);
495
496 public:
497 void push_set(RegSet set, int offset = -1);
498 void pop_set(RegSet set, int offset = -1);
499
500 // Push and pop everything that might be clobbered by a native
501 // runtime call.
502 // Only save the lower 64 bits of each vector register.
503 // Additional registers can be excluded in a passed RegSet.
504 void push_call_clobbered_registers_except(RegSet exclude, bool save_fpu = true);
505 void pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu = true);
506
507 void push_call_clobbered_registers(bool save_fpu = true) {
508 push_call_clobbered_registers_except(RegSet(), save_fpu);
509 }
510 void pop_call_clobbered_registers(bool restore_fpu = true) {
511 pop_call_clobbered_registers_except(RegSet(), restore_fpu);
512 }
513
514 // allocation
515 void tlab_allocate(
516 Register obj, // result: pointer to object after successful allocation
517 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
518 int con_size_in_bytes, // object size in bytes if known at compile time
519 Register t1, // temp register
520 Register t2, // temp register
521 Label& slow_case // continuation point if fast allocation fails
522 );
523 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
524
525 void population_count(Register dst, Register src, Register scratch1, Register scratch2);
526
527 // interface method calling
528 void lookup_interface_method(Register recv_klass,
529 Register intf_klass,
530 RegisterOrConstant itable_index,
531 Register method_result,
532 Register scan_temp,
533 Label& no_such_interface,
534 bool return_method = true);
535
536 void lookup_interface_method_stub(Register recv_klass,
537 Register holder_klass,
538 Register resolved_klass,
539 Register method_result,
540 Register scan_temp,
541 Register temp_reg2,
542 Register receiver,
543 int itable_index,
544 Label& L_no_such_interface);
545
546 // virtual method calling
547 void lookup_virtual_method(Register recv_klass,
548 RegisterOrConstant vtable_index,
549 Register method_result);
550
551 // Test sub_klass against super_klass, with fast and slow paths.
552
553 // The fast path produces a tri-state answer: yes / no / maybe-slow.
554 // One of the three labels can be null, meaning take the fall-through.
555 // If super_check_offset is -1, the value is loaded up from super_klass.
556 // No registers are killed, except temp_reg.
557 void check_klass_subtype_fast_path(Register sub_klass,
558 Register super_klass,
559 Register temp_reg,
560 Label* L_success,
561 Label* L_failure,
562 Label* L_slow_path,
563 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
564
565 // The rest of the type check; must be wired to a corresponding fast path.
566 // It does not repeat the fast path logic, so don't use it standalone.
567 // The temp_reg and temp2_reg can be noreg, if no temps are available.
568 // Updates the sub's secondary super cache as necessary.
569 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
570 void check_klass_subtype_slow_path(Register sub_klass,
571 Register super_klass,
572 Register temp_reg,
573 Register temp2_reg,
574 Label* L_success,
575 Label* L_failure,
576 bool set_cond_codes = false);
577
578 // The 64-bit version, which may do a hashed subclass lookup.
579 void check_klass_subtype_slow_path(Register sub_klass,
580 Register super_klass,
581 Register temp_reg,
582 Register temp2_reg,
583 Register temp3_reg,
584 Register temp4_reg,
585 Label* L_success,
586 Label* L_failure);
587
588 // Three parts of a hashed subclass lookup: a simple linear search,
589 // a table lookup, and a fallback that does linear probing in the
590 // event of a hash collision.
591 void check_klass_subtype_slow_path_linear(Register sub_klass,
592 Register super_klass,
593 Register temp_reg,
594 Register temp2_reg,
595 Label* L_success,
596 Label* L_failure,
597 bool set_cond_codes = false);
598 void check_klass_subtype_slow_path_table(Register sub_klass,
599 Register super_klass,
600 Register temp_reg,
601 Register temp2_reg,
602 Register temp3_reg,
603 Register result_reg,
604 Label* L_success,
605 Label* L_failure);
606 void hashed_check_klass_subtype_slow_path(Register sub_klass,
607 Register super_klass,
608 Register temp_reg,
609 Label* L_success,
610 Label* L_failure);
611
612 // As above, but with a constant super_klass.
613 // The result is in Register result, not the condition codes.
614 void lookup_secondary_supers_table_const(Register sub_klass,
615 Register super_klass,
616 Register temp1,
617 Register temp2,
618 Register temp3,
619 Register temp4,
620 Register result,
621 u1 super_klass_slot);
622
623 using Assembler::salq;
624 void salq(Register dest, Register count);
625 using Assembler::rorq;
626 void rorq(Register dest, Register count);
627 void lookup_secondary_supers_table_var(Register sub_klass,
628 Register super_klass,
629 Register temp1,
630 Register temp2,
631 Register temp3,
632 Register temp4,
633 Register result);
634
635 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
636 Register r_array_base,
637 Register r_array_index,
638 Register r_bitmap,
639 Register temp1,
640 Register temp2,
641 Label* L_success,
642 Label* L_failure = nullptr);
643
644 void verify_secondary_supers_table(Register r_sub_klass,
645 Register r_super_klass,
646 Register expected,
647 Register temp1,
648 Register temp2,
649 Register temp3);
650
651 void repne_scanq(Register addr, Register value, Register count, Register limit,
652 Label* L_success,
653 Label* L_failure = nullptr);
654
655 // If r is valid, return r.
656 // If r is invalid, remove a register r2 from available_regs, add r2
657 // to regs_to_push, then return r2.
658 Register allocate_if_noreg(const Register r,
659 RegSetIterator<Register> &available_regs,
660 RegSet ®s_to_push);
661
662 // Simplified, combined version, good for typical uses.
663 // Falls through on failure.
664 void check_klass_subtype(Register sub_klass,
665 Register super_klass,
666 Register temp_reg,
667 Label& L_success);
668
669 void clinit_barrier(Register klass,
670 Label* L_fast_path = nullptr,
671 Label* L_slow_path = nullptr);
672
673 // method handles (JSR 292)
674 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
675
676 void profile_receiver_type(Register recv, Register mdp, int mdp_offset);
677
678 // Debugging
679
680 // only if +VerifyOops
681 void _verify_oop(Register reg, const char* s, const char* file, int line);
682 void _verify_oop_addr(Address addr, const char* s, const char* file, int line);
683
684 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
685 if (VerifyOops) {
686 _verify_oop(reg, s, file, line);
687 }
688 }
689 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
690 if (VerifyOops) {
691 _verify_oop_addr(reg, s, file, line);
692 }
693 }
694
695 // TODO: verify method and klass metadata (compare against vptr?)
696 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
697 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
698
699 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
700 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
701 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
702 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
703 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
704
705 // Verify or restore cpu control state after JNI call
706 void restore_cpu_control_state_after_jni(Register rscratch);
707
708 // prints msg, dumps registers and stops execution
709 void stop(const char* msg);
710
711 // prints msg and continues
712 void warn(const char* msg);
713
714 // dumps registers and other state
715 void print_state();
716
717 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
718 static void debug64(char* msg, int64_t pc, int64_t regs[]);
719 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
720 static void print_state64(int64_t pc, int64_t regs[]);
721
722 void os_breakpoint();
723
724 void untested() { stop("untested"); }
725
726 void unimplemented(const char* what = "");
727
728 void should_not_reach_here() { stop("should not reach here"); }
729
730 void print_CPU_state();
731
732 // Stack overflow checking
733 void bang_stack_with_offset(int offset) {
734 // stack grows down, caller passes positive offset
735 assert(offset > 0, "must bang with negative offset");
736 movl(Address(rsp, (-offset)), rax);
737 }
738
739 // Writes to stack successive pages until offset reached to check for
740 // stack overflow + shadow pages. Also, clobbers tmp
741 void bang_stack_size(Register size, Register tmp);
742
743 // Check for reserved stack access in method being exited (for JIT)
744 void reserved_stack_check();
745
746 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod);
747
748 void verify_tlab();
749
750 static Condition negate_condition(Condition cond);
751
752 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
753 // operands. In general the names are modified to avoid hiding the instruction in Assembler
754 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
755 // here in MacroAssembler. The major exception to this rule is call
756
757 // Arithmetics
758
759
760 void addptr(Address dst, int32_t src) { addq(dst, src); }
761 void addptr(Address dst, Register src);
762
763 void addptr(Register dst, Address src) { addq(dst, src); }
764 void addptr(Register dst, int32_t src);
765 void addptr(Register dst, Register src);
766 void addptr(Register dst, RegisterOrConstant src) {
767 if (src.is_constant()) addptr(dst, checked_cast<int>(src.as_constant()));
768 else addptr(dst, src.as_register());
769 }
770
771 void andptr(Register dst, int32_t src);
772 void andptr(Register src1, Register src2) { andq(src1, src2); }
773
774 using Assembler::andq;
775 void andq(Register dst, AddressLiteral src, Register rscratch = noreg);
776
777 void cmp8(AddressLiteral src1, int imm, Register rscratch = noreg);
778
779 // renamed to drag out the casting of address to int32_t/intptr_t
780 void cmp32(Register src1, int32_t imm);
781
782 void cmp32(AddressLiteral src1, int32_t imm, Register rscratch = noreg);
783 // compare reg - mem, or reg - &mem
784 void cmp32(Register src1, AddressLiteral src2, Register rscratch = noreg);
785
786 void cmp32(Register src1, Address src2);
787
788 void cmpoop(Register src1, Register src2);
789 void cmpoop(Register src1, Address src2);
790 void cmpoop(Register dst, jobject obj, Register rscratch);
791
792 // NOTE src2 must be the lval. This is NOT an mem-mem compare
793 void cmpptr(Address src1, AddressLiteral src2, Register rscratch);
794
795 void cmpptr(Register src1, AddressLiteral src2, Register rscratch = noreg);
796
797 void cmpptr(Register src1, Register src2) { cmpq(src1, src2); }
798 void cmpptr(Register src1, Address src2) { cmpq(src1, src2); }
799
800 void cmpptr(Register src1, int32_t src2) { cmpq(src1, src2); }
801 void cmpptr(Address src1, int32_t src2) { cmpq(src1, src2); }
802
803 // cmp64 to avoild hiding cmpq
804 void cmp64(Register src1, AddressLiteral src, Register rscratch = noreg);
805
806 void cmpxchgptr(Register reg, Address adr);
807
808 void locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch = noreg);
809
810 void imulptr(Register dst, Register src) { imulq(dst, src); }
811 void imulptr(Register dst, Register src, int imm32) { imulq(dst, src, imm32); }
812
813
814 void negptr(Register dst) { negq(dst); }
815
816 void notptr(Register dst) { notq(dst); }
817
818 void shlptr(Register dst, int32_t shift);
819 void shlptr(Register dst) { shlq(dst); }
820
821 void shrptr(Register dst, int32_t shift);
822 void shrptr(Register dst) { shrq(dst); }
823
824 void sarptr(Register dst) { sarq(dst); }
825 void sarptr(Register dst, int32_t src) { sarq(dst, src); }
826
827 void subptr(Address dst, int32_t src) { subq(dst, src); }
828
829 void subptr(Register dst, Address src) { subq(dst, src); }
830 void subptr(Register dst, int32_t src);
831 // Force generation of a 4 byte immediate value even if it fits into 8bit
832 void subptr_imm32(Register dst, int32_t src);
833 void subptr(Register dst, Register src);
834 void subptr(Register dst, RegisterOrConstant src) {
835 if (src.is_constant()) subptr(dst, (int) src.as_constant());
836 else subptr(dst, src.as_register());
837 }
838
839 void sbbptr(Address dst, int32_t src) { sbbq(dst, src); }
840 void sbbptr(Register dst, int32_t src) { sbbq(dst, src); }
841
842 void xchgptr(Register src1, Register src2) { xchgq(src1, src2); }
843 void xchgptr(Register src1, Address src2) { xchgq(src1, src2); }
844
845 void xaddptr(Address src1, Register src2) { xaddq(src1, src2); }
846
847
848
849 // Helper functions for statistics gathering.
850 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
851 void cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch = noreg);
852 // Unconditional atomic increment.
853 void atomic_incl(Address counter_addr);
854 void atomic_incl(AddressLiteral counter_addr, Register rscratch = noreg);
855 void atomic_incq(Address counter_addr);
856 void atomic_incq(AddressLiteral counter_addr, Register rscratch = noreg);
857 void atomic_incptr(AddressLiteral counter_addr, Register rscratch = noreg) { atomic_incq(counter_addr, rscratch); }
858 void atomic_incptr(Address counter_addr) { atomic_incq(counter_addr); }
859
860 using Assembler::lea;
861 void lea(Register dst, AddressLiteral adr);
862 void lea(Address dst, AddressLiteral adr, Register rscratch);
863
864 void leal32(Register dst, Address src) { leal(dst, src); }
865
866 // Import other testl() methods from the parent class or else
867 // they will be hidden by the following overriding declaration.
868 using Assembler::testl;
869 void testl(Address dst, int32_t imm32);
870 void testl(Register dst, int32_t imm32);
871 void testl(Register dst, AddressLiteral src); // requires reachable address
872 using Assembler::testq;
873 void testq(Address dst, int32_t imm32);
874 void testq(Register dst, int32_t imm32);
875
876 void orptr(Register dst, Address src) { orq(dst, src); }
877 void orptr(Register dst, Register src) { orq(dst, src); }
878 void orptr(Register dst, int32_t src) { orq(dst, src); }
879 void orptr(Address dst, int32_t imm32) { orq(dst, imm32); }
880
881 void testptr(Register src, int32_t imm32) { testq(src, imm32); }
882 void testptr(Register src1, Address src2) { testq(src1, src2); }
883 void testptr(Address src, int32_t imm32) { testq(src, imm32); }
884 void testptr(Register src1, Register src2);
885
886 void xorptr(Register dst, Register src) { xorq(dst, src); }
887 void xorptr(Register dst, Address src) { xorq(dst, src); }
888
889 // Calls
890
891 void call(Label& L, relocInfo::relocType rtype);
892 void call(Register entry);
893 void call(Address addr) { Assembler::call(addr); }
894
895 // NOTE: this call transfers to the effective address of entry NOT
896 // the address contained by entry. This is because this is more natural
897 // for jumps/calls.
898 void call(AddressLiteral entry, Register rscratch = rax);
899
900 // Emit the CompiledIC call idiom
901 void ic_call(address entry, jint method_index = 0);
902 static int ic_check_size();
903 int ic_check(int end_alignment);
904
905 void emit_static_call_stub();
906
907 // Jumps
908
909 // NOTE: these jumps transfer to the effective address of dst NOT
910 // the address contained by dst. This is because this is more natural
911 // for jumps/calls.
912 void jump(AddressLiteral dst, Register rscratch = noreg);
913
914 void jump_cc(Condition cc, AddressLiteral dst, Register rscratch = noreg);
915
916 // 32bit can do a case table jump in one instruction but we no longer allow the base
917 // to be installed in the Address class. This jump will transfer to the address
918 // contained in the location described by entry (not the address of entry)
919 void jump(ArrayAddress entry, Register rscratch);
920
921 // Adding more natural conditional jump instructions
922 void ALWAYSINLINE jo(Label& L, bool maybe_short = true) { jcc(Assembler::overflow, L, maybe_short); }
923 void ALWAYSINLINE jno(Label& L, bool maybe_short = true) { jcc(Assembler::noOverflow, L, maybe_short); }
924 void ALWAYSINLINE js(Label& L, bool maybe_short = true) { jcc(Assembler::negative, L, maybe_short); }
925 void ALWAYSINLINE jns(Label& L, bool maybe_short = true) { jcc(Assembler::positive, L, maybe_short); }
926 void ALWAYSINLINE je(Label& L, bool maybe_short = true) { jcc(Assembler::equal, L, maybe_short); }
927 void ALWAYSINLINE jz(Label& L, bool maybe_short = true) { jcc(Assembler::zero, L, maybe_short); }
928 void ALWAYSINLINE jne(Label& L, bool maybe_short = true) { jcc(Assembler::notEqual, L, maybe_short); }
929 void ALWAYSINLINE jnz(Label& L, bool maybe_short = true) { jcc(Assembler::notZero, L, maybe_short); }
930 void ALWAYSINLINE jb(Label& L, bool maybe_short = true) { jcc(Assembler::below, L, maybe_short); }
931 void ALWAYSINLINE jnae(Label& L, bool maybe_short = true) { jcc(Assembler::below, L, maybe_short); }
932 void ALWAYSINLINE jc(Label& L, bool maybe_short = true) { jcc(Assembler::carrySet, L, maybe_short); }
933 void ALWAYSINLINE jnb(Label& L, bool maybe_short = true) { jcc(Assembler::aboveEqual, L, maybe_short); }
934 void ALWAYSINLINE jae(Label& L, bool maybe_short = true) { jcc(Assembler::aboveEqual, L, maybe_short); }
935 void ALWAYSINLINE jnc(Label& L, bool maybe_short = true) { jcc(Assembler::carryClear, L, maybe_short); }
936 void ALWAYSINLINE jbe(Label& L, bool maybe_short = true) { jcc(Assembler::belowEqual, L, maybe_short); }
937 void ALWAYSINLINE jna(Label& L, bool maybe_short = true) { jcc(Assembler::belowEqual, L, maybe_short); }
938 void ALWAYSINLINE ja(Label& L, bool maybe_short = true) { jcc(Assembler::above, L, maybe_short); }
939 void ALWAYSINLINE jnbe(Label& L, bool maybe_short = true) { jcc(Assembler::above, L, maybe_short); }
940 void ALWAYSINLINE jl(Label& L, bool maybe_short = true) { jcc(Assembler::less, L, maybe_short); }
941 void ALWAYSINLINE jnge(Label& L, bool maybe_short = true) { jcc(Assembler::less, L, maybe_short); }
942 void ALWAYSINLINE jge(Label& L, bool maybe_short = true) { jcc(Assembler::greaterEqual, L, maybe_short); }
943 void ALWAYSINLINE jnl(Label& L, bool maybe_short = true) { jcc(Assembler::greaterEqual, L, maybe_short); }
944 void ALWAYSINLINE jle(Label& L, bool maybe_short = true) { jcc(Assembler::lessEqual, L, maybe_short); }
945 void ALWAYSINLINE jng(Label& L, bool maybe_short = true) { jcc(Assembler::lessEqual, L, maybe_short); }
946 void ALWAYSINLINE jg(Label& L, bool maybe_short = true) { jcc(Assembler::greater, L, maybe_short); }
947 void ALWAYSINLINE jnle(Label& L, bool maybe_short = true) { jcc(Assembler::greater, L, maybe_short); }
948 void ALWAYSINLINE jp(Label& L, bool maybe_short = true) { jcc(Assembler::parity, L, maybe_short); }
949 void ALWAYSINLINE jpe(Label& L, bool maybe_short = true) { jcc(Assembler::parity, L, maybe_short); }
950 void ALWAYSINLINE jnp(Label& L, bool maybe_short = true) { jcc(Assembler::noParity, L, maybe_short); }
951 void ALWAYSINLINE jpo(Label& L, bool maybe_short = true) { jcc(Assembler::noParity, L, maybe_short); }
952 // * No condition for this * void ALWAYSINLINE jcxz(Label& L, bool maybe_short = true) { jcc(Assembler::cxz, L, maybe_short); }
953 // * No condition for this * void ALWAYSINLINE jecxz(Label& L, bool maybe_short = true) { jcc(Assembler::cxz, L, maybe_short); }
954
955 // Short versions of the above
956 void ALWAYSINLINE jo_b(Label& L) { jccb(Assembler::overflow, L); }
957 void ALWAYSINLINE jno_b(Label& L) { jccb(Assembler::noOverflow, L); }
958 void ALWAYSINLINE js_b(Label& L) { jccb(Assembler::negative, L); }
959 void ALWAYSINLINE jns_b(Label& L) { jccb(Assembler::positive, L); }
960 void ALWAYSINLINE je_b(Label& L) { jccb(Assembler::equal, L); }
961 void ALWAYSINLINE jz_b(Label& L) { jccb(Assembler::zero, L); }
962 void ALWAYSINLINE jne_b(Label& L) { jccb(Assembler::notEqual, L); }
963 void ALWAYSINLINE jnz_b(Label& L) { jccb(Assembler::notZero, L); }
964 void ALWAYSINLINE jb_b(Label& L) { jccb(Assembler::below, L); }
965 void ALWAYSINLINE jnae_b(Label& L) { jccb(Assembler::below, L); }
966 void ALWAYSINLINE jc_b(Label& L) { jccb(Assembler::carrySet, L); }
967 void ALWAYSINLINE jnb_b(Label& L) { jccb(Assembler::aboveEqual, L); }
968 void ALWAYSINLINE jae_b(Label& L) { jccb(Assembler::aboveEqual, L); }
969 void ALWAYSINLINE jnc_b(Label& L) { jccb(Assembler::carryClear, L); }
970 void ALWAYSINLINE jbe_b(Label& L) { jccb(Assembler::belowEqual, L); }
971 void ALWAYSINLINE jna_b(Label& L) { jccb(Assembler::belowEqual, L); }
972 void ALWAYSINLINE ja_b(Label& L) { jccb(Assembler::above, L); }
973 void ALWAYSINLINE jnbe_b(Label& L) { jccb(Assembler::above, L); }
974 void ALWAYSINLINE jl_b(Label& L) { jccb(Assembler::less, L); }
975 void ALWAYSINLINE jnge_b(Label& L) { jccb(Assembler::less, L); }
976 void ALWAYSINLINE jge_b(Label& L) { jccb(Assembler::greaterEqual, L); }
977 void ALWAYSINLINE jnl_b(Label& L) { jccb(Assembler::greaterEqual, L); }
978 void ALWAYSINLINE jle_b(Label& L) { jccb(Assembler::lessEqual, L); }
979 void ALWAYSINLINE jng_b(Label& L) { jccb(Assembler::lessEqual, L); }
980 void ALWAYSINLINE jg_b(Label& L) { jccb(Assembler::greater, L); }
981 void ALWAYSINLINE jnle_b(Label& L) { jccb(Assembler::greater, L); }
982 void ALWAYSINLINE jp_b(Label& L) { jccb(Assembler::parity, L); }
983 void ALWAYSINLINE jpe_b(Label& L) { jccb(Assembler::parity, L); }
984 void ALWAYSINLINE jnp_b(Label& L) { jccb(Assembler::noParity, L); }
985 void ALWAYSINLINE jpo_b(Label& L) { jccb(Assembler::noParity, L); }
986 // * No condition for this * void ALWAYSINLINE jcxz_b(Label& L) { jccb(Assembler::cxz, L); }
987 // * No condition for this * void ALWAYSINLINE jecxz_b(Label& L) { jccb(Assembler::cxz, L); }
988
989 // Floating
990
991 void push_f(XMMRegister r);
992 void pop_f(XMMRegister r);
993 void push_d(XMMRegister r);
994 void pop_d(XMMRegister r);
995
996 void push_ppx(Register src);
997 void pop_ppx(Register dst);
998
999 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
1000 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
1001 void andpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1002
1003 void andnpd(XMMRegister dst, XMMRegister src) { Assembler::andnpd(dst, src); }
1004
1005 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
1006 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
1007 void andps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1008
1009 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
1010 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
1011 void comiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1012
1013 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
1014 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
1015 void comisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1016
1017 void orpd(XMMRegister dst, XMMRegister src) { Assembler::orpd(dst, src); }
1018
1019 void cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch = noreg);
1020 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
1021 void ldmxcsr(AddressLiteral src, Register rscratch = noreg);
1022
1023 private:
1024 void sha256_AVX2_one_round_compute(
1025 Register reg_old_h,
1026 Register reg_a,
1027 Register reg_b,
1028 Register reg_c,
1029 Register reg_d,
1030 Register reg_e,
1031 Register reg_f,
1032 Register reg_g,
1033 Register reg_h,
1034 int iter);
1035 void sha256_AVX2_four_rounds_compute_first(int start);
1036 void sha256_AVX2_four_rounds_compute_last(int start);
1037 void sha256_AVX2_one_round_and_sched(
1038 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
1039 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
1040 XMMRegister xmm_2, /* ymm6 */
1041 XMMRegister xmm_3, /* ymm7 */
1042 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
1043 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
1044 Register reg_c, /* edi */
1045 Register reg_d, /* esi */
1046 Register reg_e, /* r8d */
1047 Register reg_f, /* r9d */
1048 Register reg_g, /* r10d */
1049 Register reg_h, /* r11d */
1050 int iter);
1051
1052 void addm(int disp, Register r1, Register r2);
1053
1054 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
1055 Register e, Register f, Register g, Register h, int iteration);
1056
1057 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1058 Register a, Register b, Register c, Register d, Register e, Register f,
1059 Register g, Register h, int iteration);
1060
1061 void addmq(int disp, Register r1, Register r2);
1062 public:
1063 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1064 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1065 Register buf, Register state, Register ofs, Register limit, Register rsp,
1066 bool multi_block, XMMRegister shuf_mask);
1067 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1068 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1069 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
1070 XMMRegister shuf_mask);
1071 void sha512_update_ni_x1(Register arg_hash, Register arg_msg, Register ofs, Register limit, bool multi_block);
1072
1073 void fast_md5(Register buf, Address state, Address ofs, Address limit,
1074 bool multi_block);
1075
1076 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1077 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1078 Register buf, Register state, Register ofs, Register limit, Register rsp,
1079 bool multi_block);
1080
1081 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1082 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1083 Register buf, Register state, Register ofs, Register limit, Register rsp,
1084 bool multi_block, XMMRegister shuf_mask);
1085
1086 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1087 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1088 Register rax, Register rcx, Register rdx, Register tmp);
1089
1090 private:
1091
1092 // these are private because users should be doing movflt/movdbl
1093
1094 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1095 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1096 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1097 void movss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1098
1099 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1100 void movlpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1101
1102 public:
1103
1104 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1105 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1106 void addsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1107
1108 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1109 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1110 void addss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1111
1112 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1113 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1114 void addpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1115
1116 using Assembler::vbroadcasti128;
1117 void vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1118
1119 using Assembler::vbroadcastsd;
1120 void vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1121
1122 using Assembler::vbroadcastss;
1123 void vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1124
1125 // Vector float blend
1126 void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg);
1127 void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg);
1128
1129 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1130 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1131 void divsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1132
1133 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1134 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1135 void divss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1136
1137 // Move Unaligned Double Quadword
1138 void movdqu(Address dst, XMMRegister src);
1139 void movdqu(XMMRegister dst, XMMRegister src);
1140 void movdqu(XMMRegister dst, Address src);
1141 void movdqu(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1142
1143 void kmovwl(Register dst, KRegister src) { Assembler::kmovwl(dst, src); }
1144 void kmovwl(Address dst, KRegister src) { Assembler::kmovwl(dst, src); }
1145 void kmovwl(KRegister dst, KRegister src) { Assembler::kmovwl(dst, src); }
1146 void kmovwl(KRegister dst, Register src) { Assembler::kmovwl(dst, src); }
1147 void kmovwl(KRegister dst, Address src) { Assembler::kmovwl(dst, src); }
1148 void kmovwl(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1149
1150 void kmovql(KRegister dst, KRegister src) { Assembler::kmovql(dst, src); }
1151 void kmovql(KRegister dst, Register src) { Assembler::kmovql(dst, src); }
1152 void kmovql(Register dst, KRegister src) { Assembler::kmovql(dst, src); }
1153 void kmovql(KRegister dst, Address src) { Assembler::kmovql(dst, src); }
1154 void kmovql(Address dst, KRegister src) { Assembler::kmovql(dst, src); }
1155 void kmovql(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1156
1157 // Safe move operation, lowers down to 16bit moves for targets supporting
1158 // AVX512F feature and 64bit moves for targets supporting AVX512BW feature.
1159 void kmov(Address dst, KRegister src);
1160 void kmov(KRegister dst, Address src);
1161 void kmov(KRegister dst, KRegister src);
1162 void kmov(Register dst, KRegister src);
1163 void kmov(KRegister dst, Register src);
1164
1165 using Assembler::movddup;
1166 void movddup(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1167
1168 using Assembler::vmovddup;
1169 void vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1170
1171 // AVX Unaligned forms
1172 void vmovdqu(Address dst, XMMRegister src);
1173 void vmovdqu(XMMRegister dst, Address src);
1174 void vmovdqu(XMMRegister dst, XMMRegister src);
1175 void vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1176 void vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1177 void vmovdqu(XMMRegister dst, XMMRegister src, int vector_len);
1178 void vmovdqu(XMMRegister dst, Address src, int vector_len);
1179 void vmovdqu(Address dst, XMMRegister src, int vector_len);
1180
1181 // AVX Aligned forms
1182 using Assembler::vmovdqa;
1183 void vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1184 void vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1185 void vmovdqa(XMMRegister dst, Address src, int vector_len);
1186 void vmovdqa(Address dst, XMMRegister src, int vector_len);
1187
1188 // AVX512 Unaligned
1189 void evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len);
1190 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len);
1191 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len);
1192
1193 void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1194 void evmovdqub(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1195
1196 void evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1197 if (dst->encoding() != src->encoding() || mask != k0) {
1198 Assembler::evmovdqub(dst, mask, src, merge, vector_len);
1199 }
1200 }
1201 void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1202 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1203 void evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1204
1205 void evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1206 void evmovdquw(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1207 void evmovdquw(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1208
1209 void evmovdquw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1210 if (dst->encoding() != src->encoding() || mask != k0) {
1211 Assembler::evmovdquw(dst, mask, src, merge, vector_len);
1212 }
1213 }
1214 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1215 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1216 void evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1217
1218 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
1219 if (dst->encoding() != src->encoding()) {
1220 Assembler::evmovdqul(dst, src, vector_len);
1221 }
1222 }
1223 void evmovdqul(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1224 void evmovdqul(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1225
1226 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1227 if (dst->encoding() != src->encoding() || mask != k0) {
1228 Assembler::evmovdqul(dst, mask, src, merge, vector_len);
1229 }
1230 }
1231 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1232 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1233 void evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1234
1235 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
1236 if (dst->encoding() != src->encoding()) {
1237 Assembler::evmovdquq(dst, src, vector_len);
1238 }
1239 }
1240 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1241 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1242 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1243 void evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1244
1245 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1246 if (dst->encoding() != src->encoding() || mask != k0) {
1247 Assembler::evmovdquq(dst, mask, src, merge, vector_len);
1248 }
1249 }
1250 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1251 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1252 void evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1253 void evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1254
1255 using Assembler::movapd;
1256 void movapd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1257
1258 // Move Aligned Double Quadword
1259 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1260 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1261 void movdqa(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1262
1263 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1264 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1265 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1266 void movsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1267
1268 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1269 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1270 void mulpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1271
1272 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1273 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1274 void mulsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1275
1276 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1277 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1278 void mulss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1279
1280 // Carry-Less Multiplication Quadword
1281 void pclmulldq(XMMRegister dst, XMMRegister src) {
1282 // 0x00 - multiply lower 64 bits [0:63]
1283 Assembler::pclmulqdq(dst, src, 0x00);
1284 }
1285 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1286 // 0x11 - multiply upper 64 bits [64:127]
1287 Assembler::pclmulqdq(dst, src, 0x11);
1288 }
1289
1290 void pcmpeqb(XMMRegister dst, XMMRegister src);
1291 void pcmpeqw(XMMRegister dst, XMMRegister src);
1292
1293 void pcmpestri(XMMRegister dst, Address src, int imm8);
1294 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1295
1296 void pmovzxbw(XMMRegister dst, XMMRegister src);
1297 void pmovzxbw(XMMRegister dst, Address src);
1298
1299 void pmovmskb(Register dst, XMMRegister src);
1300
1301 void ptest(XMMRegister dst, XMMRegister src);
1302
1303 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1304 void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1305 void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch = noreg);
1306
1307 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1308 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1309 void sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1310
1311 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1312 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1313 void subsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1314
1315 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1316 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1317 void subss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1318
1319 void evucomish(XMMRegister dst, XMMRegister src) { Assembler::evucomish(dst, src); }
1320 void evucomish(XMMRegister dst, Address src) { Assembler::evucomish(dst, src); }
1321 void evucomish(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1322
1323 void evucomxsh(XMMRegister dst, XMMRegister src) { Assembler::evucomxsh(dst, src); }
1324 void evucomxsh(XMMRegister dst, Address src) { Assembler::evucomxsh(dst, src); }
1325 void evucomxsh(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1326
1327 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1328 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1329 void ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1330
1331 void evucomxss(XMMRegister dst, XMMRegister src) { Assembler::evucomxss(dst, src); }
1332 void evucomxss(XMMRegister dst, Address src) { Assembler::evucomxss(dst, src); }
1333 void evucomxss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1334
1335 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1336 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1337 void ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1338
1339 void evucomxsd(XMMRegister dst, XMMRegister src) { Assembler::evucomxsd(dst, src); }
1340 void evucomxsd(XMMRegister dst, Address src) { Assembler::evucomxsd(dst, src); }
1341 void evucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1342
1343 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1344 void xorpd(XMMRegister dst, XMMRegister src);
1345 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1346 void xorpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1347
1348 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1349 void xorps(XMMRegister dst, XMMRegister src);
1350 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1351 void xorps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1352
1353 // Shuffle Bytes
1354 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1355 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1356 void pshufb(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1357 // AVX 3-operands instructions
1358
1359 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1360 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1361 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1362
1363 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1364 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1365 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1366
1367 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1368 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1369
1370 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1371 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1372 void vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1373
1374 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1375 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1376
1377 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1378 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1379 void vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1380
1381 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1382 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1383 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1384
1385 using Assembler::vpbroadcastd;
1386 void vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1387
1388 using Assembler::vpbroadcastq;
1389 void vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1390
1391 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1392 void vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len);
1393
1394 void vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1395 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1396 using Assembler::evpcmpeqd;
1397 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1398
1399 // Vector compares
1400 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1401 Assembler::evpcmpd(kdst, mask, nds, src, comparison, is_signed, vector_len);
1402 }
1403 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1404
1405 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1406 Assembler::evpcmpq(kdst, mask, nds, src, comparison, is_signed, vector_len);
1407 }
1408 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1409
1410 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1411 Assembler::evpcmpb(kdst, mask, nds, src, comparison, is_signed, vector_len);
1412 }
1413 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1414
1415 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1416 Assembler::evpcmpw(kdst, mask, nds, src, comparison, is_signed, vector_len);
1417 }
1418 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1419
1420 void evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len);
1421
1422 // Emit comparison instruction for the specified comparison predicate.
1423 void vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len);
1424 void vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len);
1425
1426 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1427 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1428
1429 void vpmovmskb(Register dst, XMMRegister src, int vector_len = Assembler::AVX_256bit);
1430
1431 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1432 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1433
1434 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1435 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1436 void vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1437
1438 void vpmuldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpmuldq(dst, nds, src, vector_len); }
1439
1440 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1441 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1442
1443 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1444 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1445
1446 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1447 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1448
1449 void evpsrad(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1450 void evpsrad(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1451
1452 void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1453 void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1454
1455 using Assembler::evpsllw;
1456 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1457 if (!is_varshift) {
1458 Assembler::evpsllw(dst, mask, nds, src, merge, vector_len);
1459 } else {
1460 Assembler::evpsllvw(dst, mask, nds, src, merge, vector_len);
1461 }
1462 }
1463 void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1464 if (!is_varshift) {
1465 Assembler::evpslld(dst, mask, nds, src, merge, vector_len);
1466 } else {
1467 Assembler::evpsllvd(dst, mask, nds, src, merge, vector_len);
1468 }
1469 }
1470 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1471 if (!is_varshift) {
1472 Assembler::evpsllq(dst, mask, nds, src, merge, vector_len);
1473 } else {
1474 Assembler::evpsllvq(dst, mask, nds, src, merge, vector_len);
1475 }
1476 }
1477 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1478 if (!is_varshift) {
1479 Assembler::evpsrlw(dst, mask, nds, src, merge, vector_len);
1480 } else {
1481 Assembler::evpsrlvw(dst, mask, nds, src, merge, vector_len);
1482 }
1483 }
1484 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1485 if (!is_varshift) {
1486 Assembler::evpsrld(dst, mask, nds, src, merge, vector_len);
1487 } else {
1488 Assembler::evpsrlvd(dst, mask, nds, src, merge, vector_len);
1489 }
1490 }
1491
1492 using Assembler::evpsrlq;
1493 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1494 if (!is_varshift) {
1495 Assembler::evpsrlq(dst, mask, nds, src, merge, vector_len);
1496 } else {
1497 Assembler::evpsrlvq(dst, mask, nds, src, merge, vector_len);
1498 }
1499 }
1500 using Assembler::evpsraw;
1501 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1502 if (!is_varshift) {
1503 Assembler::evpsraw(dst, mask, nds, src, merge, vector_len);
1504 } else {
1505 Assembler::evpsravw(dst, mask, nds, src, merge, vector_len);
1506 }
1507 }
1508 using Assembler::evpsrad;
1509 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1510 if (!is_varshift) {
1511 Assembler::evpsrad(dst, mask, nds, src, merge, vector_len);
1512 } else {
1513 Assembler::evpsravd(dst, mask, nds, src, merge, vector_len);
1514 }
1515 }
1516 using Assembler::evpsraq;
1517 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1518 if (!is_varshift) {
1519 Assembler::evpsraq(dst, mask, nds, src, merge, vector_len);
1520 } else {
1521 Assembler::evpsravq(dst, mask, nds, src, merge, vector_len);
1522 }
1523 }
1524
1525 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1526 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1527 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1528 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1529
1530 void evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1531 void evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1532 void evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1533 void evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1534
1535 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1536 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1537
1538 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1539 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1540
1541 void vptest(XMMRegister dst, XMMRegister src);
1542 void vptest(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vptest(dst, src, vector_len); }
1543
1544 void punpcklbw(XMMRegister dst, XMMRegister src);
1545 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1546
1547 void pshufd(XMMRegister dst, Address src, int mode);
1548 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1549
1550 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1551 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1552
1553 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1554 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1555 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1556
1557 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1558 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1559 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1560
1561 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1562
1563 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1564 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1565 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1566
1567 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1568 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1569 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1570
1571 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1572 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1573 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1574
1575 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1576 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1577 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1578
1579 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1580 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1581 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1582
1583 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1584 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1585 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1586
1587 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1588 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1589
1590 // AVX Vector instructions
1591
1592 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1593 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1594 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1595
1596 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1597 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1598 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1599
1600 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1601 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1602 Assembler::vpxor(dst, nds, src, vector_len);
1603 else
1604 Assembler::vxorpd(dst, nds, src, vector_len);
1605 }
1606 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1607 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1608 Assembler::vpxor(dst, nds, src, vector_len);
1609 else
1610 Assembler::vxorpd(dst, nds, src, vector_len);
1611 }
1612 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1613
1614 // Simple version for AVX2 256bit vectors
1615 void vpxor(XMMRegister dst, XMMRegister src) {
1616 assert(UseAVX >= 2, "Should be at least AVX2");
1617 Assembler::vpxor(dst, dst, src, AVX_256bit);
1618 }
1619 void vpxor(XMMRegister dst, Address src) {
1620 assert(UseAVX >= 2, "Should be at least AVX2");
1621 Assembler::vpxor(dst, dst, src, AVX_256bit);
1622 }
1623
1624 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpermd(dst, nds, src, vector_len); }
1625 void vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1626
1627 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1628 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1629 Assembler::vinserti32x4(dst, nds, src, imm8);
1630 } else if (UseAVX > 1) {
1631 // vinserti128 is available only in AVX2
1632 Assembler::vinserti128(dst, nds, src, imm8);
1633 } else {
1634 Assembler::vinsertf128(dst, nds, src, imm8);
1635 }
1636 }
1637
1638 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1639 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1640 Assembler::vinserti32x4(dst, nds, src, imm8);
1641 } else if (UseAVX > 1) {
1642 // vinserti128 is available only in AVX2
1643 Assembler::vinserti128(dst, nds, src, imm8);
1644 } else {
1645 Assembler::vinsertf128(dst, nds, src, imm8);
1646 }
1647 }
1648
1649 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1650 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1651 Assembler::vextracti32x4(dst, src, imm8);
1652 } else if (UseAVX > 1) {
1653 // vextracti128 is available only in AVX2
1654 Assembler::vextracti128(dst, src, imm8);
1655 } else {
1656 Assembler::vextractf128(dst, src, imm8);
1657 }
1658 }
1659
1660 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1661 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1662 Assembler::vextracti32x4(dst, src, imm8);
1663 } else if (UseAVX > 1) {
1664 // vextracti128 is available only in AVX2
1665 Assembler::vextracti128(dst, src, imm8);
1666 } else {
1667 Assembler::vextractf128(dst, src, imm8);
1668 }
1669 }
1670
1671 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1672 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1673 vinserti128(dst, dst, src, 1);
1674 }
1675 void vinserti128_high(XMMRegister dst, Address src) {
1676 vinserti128(dst, dst, src, 1);
1677 }
1678 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1679 vextracti128(dst, src, 1);
1680 }
1681 void vextracti128_high(Address dst, XMMRegister src) {
1682 vextracti128(dst, src, 1);
1683 }
1684
1685 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1686 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1687 Assembler::vinsertf32x4(dst, dst, src, 1);
1688 } else {
1689 Assembler::vinsertf128(dst, dst, src, 1);
1690 }
1691 }
1692
1693 void vinsertf128_high(XMMRegister dst, Address src) {
1694 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1695 Assembler::vinsertf32x4(dst, dst, src, 1);
1696 } else {
1697 Assembler::vinsertf128(dst, dst, src, 1);
1698 }
1699 }
1700
1701 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1702 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1703 Assembler::vextractf32x4(dst, src, 1);
1704 } else {
1705 Assembler::vextractf128(dst, src, 1);
1706 }
1707 }
1708
1709 void vextractf128_high(Address dst, XMMRegister src) {
1710 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1711 Assembler::vextractf32x4(dst, src, 1);
1712 } else {
1713 Assembler::vextractf128(dst, src, 1);
1714 }
1715 }
1716
1717 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1718 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1719 Assembler::vinserti64x4(dst, dst, src, 1);
1720 }
1721 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1722 Assembler::vinsertf64x4(dst, dst, src, 1);
1723 }
1724 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1725 Assembler::vextracti64x4(dst, src, 1);
1726 }
1727 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1728 Assembler::vextractf64x4(dst, src, 1);
1729 }
1730 void vextractf64x4_high(Address dst, XMMRegister src) {
1731 Assembler::vextractf64x4(dst, src, 1);
1732 }
1733 void vinsertf64x4_high(XMMRegister dst, Address src) {
1734 Assembler::vinsertf64x4(dst, dst, src, 1);
1735 }
1736
1737 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1738 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1739 vinserti128(dst, dst, src, 0);
1740 }
1741 void vinserti128_low(XMMRegister dst, Address src) {
1742 vinserti128(dst, dst, src, 0);
1743 }
1744 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1745 vextracti128(dst, src, 0);
1746 }
1747 void vextracti128_low(Address dst, XMMRegister src) {
1748 vextracti128(dst, src, 0);
1749 }
1750
1751 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1752 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1753 Assembler::vinsertf32x4(dst, dst, src, 0);
1754 } else {
1755 Assembler::vinsertf128(dst, dst, src, 0);
1756 }
1757 }
1758
1759 void vinsertf128_low(XMMRegister dst, Address src) {
1760 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1761 Assembler::vinsertf32x4(dst, dst, src, 0);
1762 } else {
1763 Assembler::vinsertf128(dst, dst, src, 0);
1764 }
1765 }
1766
1767 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1768 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1769 Assembler::vextractf32x4(dst, src, 0);
1770 } else {
1771 Assembler::vextractf128(dst, src, 0);
1772 }
1773 }
1774
1775 void vextractf128_low(Address dst, XMMRegister src) {
1776 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1777 Assembler::vextractf32x4(dst, src, 0);
1778 } else {
1779 Assembler::vextractf128(dst, src, 0);
1780 }
1781 }
1782
1783 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1784 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1785 Assembler::vinserti64x4(dst, dst, src, 0);
1786 }
1787 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1788 Assembler::vinsertf64x4(dst, dst, src, 0);
1789 }
1790 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1791 Assembler::vextracti64x4(dst, src, 0);
1792 }
1793 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1794 Assembler::vextractf64x4(dst, src, 0);
1795 }
1796 void vextractf64x4_low(Address dst, XMMRegister src) {
1797 Assembler::vextractf64x4(dst, src, 0);
1798 }
1799 void vinsertf64x4_low(XMMRegister dst, Address src) {
1800 Assembler::vinsertf64x4(dst, dst, src, 0);
1801 }
1802
1803 // Carry-Less Multiplication Quadword
1804 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1805 // 0x00 - multiply lower 64 bits [0:63]
1806 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1807 }
1808 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1809 // 0x11 - multiply upper 64 bits [64:127]
1810 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1811 }
1812 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1813 // 0x10 - multiply nds[0:63] and src[64:127]
1814 Assembler::vpclmulqdq(dst, nds, src, 0x10);
1815 }
1816 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1817 //0x01 - multiply nds[64:127] and src[0:63]
1818 Assembler::vpclmulqdq(dst, nds, src, 0x01);
1819 }
1820
1821 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1822 // 0x00 - multiply lower 64 bits [0:63]
1823 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1824 }
1825 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1826 // 0x11 - multiply upper 64 bits [64:127]
1827 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1828 }
1829
1830 // AVX-512 mask operations.
1831 void kand(BasicType etype, KRegister dst, KRegister src1, KRegister src2);
1832 void kor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1833 void knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp = knoreg, Register rtmp = noreg);
1834 void kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1835 void kortest(uint masklen, KRegister src1, KRegister src2);
1836 void ktest(uint masklen, KRegister src1, KRegister src2);
1837
1838 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1839 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1840
1841 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1842 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1843
1844 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1845 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1846
1847 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1848 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1849
1850 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1851 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1852 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1853 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1854
1855 using Assembler::evpandq;
1856 void evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1857
1858 using Assembler::evpaddq;
1859 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1860
1861 using Assembler::evporq;
1862 void evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1863
1864 using Assembler::vpshufb;
1865 void vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1866
1867 using Assembler::vpor;
1868 void vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1869
1870 using Assembler::vpternlogq;
1871 void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch = noreg);
1872
1873 void cmov32( Condition cc, Register dst, Address src);
1874 void cmov32( Condition cc, Register dst, Register src);
1875
1876 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1877
1878 void cmovptr(Condition cc, Register dst, Address src) { cmovq(cc, dst, src); }
1879 void cmovptr(Condition cc, Register dst, Register src) { cmovq(cc, dst, src); }
1880
1881 void movoop(Register dst, jobject obj);
1882 void movoop(Address dst, jobject obj, Register rscratch);
1883
1884 void mov_metadata(Register dst, Metadata* obj);
1885 void mov_metadata(Address dst, Metadata* obj, Register rscratch);
1886
1887 void mov64(Register dst, int64_t imm64);
1888 void mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format);
1889
1890 void movptr(Register dst, Register src);
1891 void movptr(Register dst, Address src);
1892 void movptr(Register dst, AddressLiteral src);
1893 void movptr(Register dst, ArrayAddress src);
1894 void movptr(Register dst, intptr_t src);
1895 void movptr(Address dst, Register src);
1896 void movptr(Address dst, int32_t imm);
1897 void movptr(Address dst, intptr_t src, Register rscratch);
1898 void movptr(ArrayAddress dst, Register src, Register rscratch);
1899
1900 void movptr(Register dst, RegisterOrConstant src) {
1901 if (src.is_constant()) movptr(dst, src.as_constant());
1902 else movptr(dst, src.as_register());
1903 }
1904
1905
1906 // to avoid hiding movl
1907 void mov32(Register dst, AddressLiteral src);
1908 void mov32(AddressLiteral dst, Register src, Register rscratch = noreg);
1909
1910 // Import other mov() methods from the parent class or else
1911 // they will be hidden by the following overriding declaration.
1912 using Assembler::movdl;
1913 void movdl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1914
1915 using Assembler::movq;
1916 void movq(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1917
1918 // Can push value or effective address
1919 void pushptr(AddressLiteral src, Register rscratch);
1920
1921 void pushptr(Address src) { pushq(src); }
1922 void popptr(Address src) { popq(src); }
1923
1924 void pushoop(jobject obj, Register rscratch);
1925 void pushklass(Metadata* obj, Register rscratch);
1926
1927 // sign extend as need a l to ptr sized element
1928 void movl2ptr(Register dst, Address src) { movslq(dst, src); }
1929 void movl2ptr(Register dst, Register src) { movslq(dst, src); }
1930
1931
1932 public:
1933 // clear memory of size 'cnt' qwords, starting at 'base';
1934 // if 'is_large' is set, do not try to produce short loop
1935 void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large, KRegister mask=knoreg);
1936
1937 // clear memory initialization sequence for constant size;
1938 void clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1939
1940 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1941 void xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1942
1943 // Fill primitive arrays
1944 void generate_fill(BasicType t, bool aligned,
1945 Register to, Register value, Register count,
1946 Register rtmp, XMMRegister xtmp);
1947
1948 void encode_iso_array(Register src, Register dst, Register len,
1949 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1950 XMMRegister tmp4, Register tmp5, Register result, bool ascii);
1951
1952 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1953 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1954 Register y, Register y_idx, Register z,
1955 Register carry, Register product,
1956 Register idx, Register kdx);
1957 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1958 Register yz_idx, Register idx,
1959 Register carry, Register product, int offset);
1960 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1961 Register carry, Register carry2,
1962 Register idx, Register jdx,
1963 Register yz_idx1, Register yz_idx2,
1964 Register tmp, Register tmp3, Register tmp4);
1965 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1966 Register yz_idx, Register idx, Register jdx,
1967 Register carry, Register product,
1968 Register carry2);
1969 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
1970 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1971 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1972 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1973 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1974 Register tmp2);
1975 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1976 Register rdxReg, Register raxReg);
1977 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1978 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1979 Register tmp3, Register tmp4);
1980 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1981 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1982
1983 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1984 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1985 Register raxReg);
1986 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1987 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1988 Register raxReg);
1989 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1990 Register result, Register tmp1, Register tmp2,
1991 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1992
1993 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1994 void update_byte_crc32(Register crc, Register val, Register table);
1995 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1996
1997 void kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2);
1998 void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
1999 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
2000 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup);
2001
2002 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
2003 // Note on a naming convention:
2004 // Prefix w = register only used on a Westmere+ architecture
2005 // Prefix n = register only used on a Nehalem architecture
2006 void crc32c_ipl_alg4(Register in_out, uint32_t n,
2007 Register tmp1, Register tmp2, Register tmp3);
2008 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
2009 Register in_out,
2010 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
2011 XMMRegister w_xtmp2,
2012 Register tmp1,
2013 Register n_tmp2, Register n_tmp3);
2014 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
2015 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2016 Register tmp1, Register tmp2,
2017 Register n_tmp3);
2018 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
2019 Register in_out1, Register in_out2, Register in_out3,
2020 Register tmp1, Register tmp2, Register tmp3,
2021 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2022 Register tmp4, Register tmp5,
2023 Register n_tmp6);
2024 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
2025 Register tmp1, Register tmp2, Register tmp3,
2026 Register tmp4, Register tmp5, Register tmp6,
2027 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2028 bool is_pclmulqdq_supported);
2029 // Fold 128-bit data chunk
2030 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
2031 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
2032 // Fold 512-bit data chunk
2033 void fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, Register pos, int offset);
2034 // Fold 8-bit data
2035 void fold_8bit_crc32(Register crc, Register table, Register tmp);
2036 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
2037
2038 // Compress char[] array to byte[].
2039 void char_array_compress(Register src, Register dst, Register len,
2040 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
2041 XMMRegister tmp4, Register tmp5, Register result,
2042 KRegister mask1 = knoreg, KRegister mask2 = knoreg);
2043
2044 // Inflate byte[] array to char[].
2045 void byte_array_inflate(Register src, Register dst, Register len,
2046 XMMRegister tmp1, Register tmp2, KRegister mask = knoreg);
2047
2048 void fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
2049 Register length, Register temp, int vec_enc);
2050
2051 void fill64_masked(uint shift, Register dst, int disp,
2052 XMMRegister xmm, KRegister mask, Register length,
2053 Register temp, bool use64byteVector = false);
2054
2055 void fill32_masked(uint shift, Register dst, int disp,
2056 XMMRegister xmm, KRegister mask, Register length,
2057 Register temp);
2058
2059 void fill32(Address dst, XMMRegister xmm);
2060
2061 void fill32(Register dst, int disp, XMMRegister xmm);
2062
2063 void fill64(Address dst, XMMRegister xmm, bool use64byteVector = false);
2064
2065 void fill64(Register dst, int dis, XMMRegister xmm, bool use64byteVector = false);
2066
2067 void convert_f2i(Register dst, XMMRegister src);
2068 void convert_d2i(Register dst, XMMRegister src);
2069 void convert_f2l(Register dst, XMMRegister src);
2070 void convert_d2l(Register dst, XMMRegister src);
2071 void round_double(Register dst, XMMRegister src, Register rtmp, Register rcx);
2072 void round_float(Register dst, XMMRegister src, Register rtmp, Register rcx);
2073
2074 void cache_wb(Address line);
2075 void cache_wbsync(bool is_pre);
2076
2077 #ifdef COMPILER2
2078 void generate_fill_avx3(BasicType type, Register to, Register value,
2079 Register count, Register rtmp, XMMRegister xtmp);
2080 #endif // COMPILER2
2081
2082 void vallones(XMMRegister dst, int vector_len);
2083
2084 void check_stack_alignment(Register sp, const char* msg, unsigned bias = 0, Register tmp = noreg);
2085
2086 void fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow);
2087 void fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow);
2088
2089 void save_legacy_gprs();
2090 void restore_legacy_gprs();
2091 void load_aotrc_address(Register reg, address a);
2092 void setcc(Assembler::Condition comparison, Register dst);
2093 };
2094
2095 #endif // CPU_X86_MACROASSEMBLER_X86_HPP