1 /*
2 * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "code/vmreg.inline.hpp"
30 #include "compiler/oopMap.hpp"
31 #include "utilities/macros.hpp"
32 #include "runtime/rtmLocking.hpp"
33 #include "runtime/signature.hpp"
34 #include "runtime/vm_version.hpp"
35
36 class ciInlineKlass;
37
38 // MacroAssembler extends Assembler by frequently used macros.
39 //
40 // Instructions for which a 'better' code sequence exists depending
41 // on arguments should also go in here.
42
43 class MacroAssembler: public Assembler {
44 friend class LIR_Assembler;
45 friend class Runtime1; // as_Address()
46
47 public:
48 // Support for VM calls
49 //
50 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
51 // may customize this version by overriding it for its purposes (e.g., to save/restore
52 // additional registers when doing a VM call).
53
54 virtual void call_VM_leaf_base(
55 address entry_point, // the entry point
56 int number_of_arguments // the number of arguments to pop after the call
57 );
58
59 protected:
60 // This is the base routine called by the different versions of call_VM. The interpreter
61 // may customize this version by overriding it for its purposes (e.g., to save/restore
62 // additional registers when doing a VM call).
63 //
64 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
65 // returns the register which contains the thread upon return. If a thread register has been
66 // specified, the return value will correspond to that register. If no last_java_sp is specified
67 // (noreg) than rsp will be used instead.
68 virtual void call_VM_base( // returns the register containing the thread upon return
69 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
70 Register java_thread, // the thread if computed before ; use noreg otherwise
71 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
72 address entry_point, // the entry point
73 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
74 bool check_exceptions // whether to check for pending exceptions after return
75 );
76
77 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
78
79 // helpers for FPU flag access
80 // tmp is a temporary register, if none is available use noreg
81 void save_rax (Register tmp);
82 void restore_rax(Register tmp);
83
84 public:
85 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
86
87 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
88 // The implementation is only non-empty for the InterpreterMacroAssembler,
89 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
90 virtual void check_and_handle_popframe(Register java_thread);
91 virtual void check_and_handle_earlyret(Register java_thread);
92
93 Address as_Address(AddressLiteral adr);
94 Address as_Address(ArrayAddress adr);
95
96 // Support for NULL-checks
97 //
98 // Generates code that causes a NULL OS exception if the content of reg is NULL.
99 // If the accessed location is M[reg + offset] and the offset is known, provide the
100 // offset. No explicit code generation is needed if the offset is within a certain
101 // range (0 <= offset <= page_size).
102
103 void null_check(Register reg, int offset = -1);
104 static bool needs_explicit_null_check(intptr_t offset);
105 static bool uses_implicit_null_check(void* address);
106
107 // markWord tests, kills markWord reg
108 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
109
110 // inlineKlass queries, kills temp_reg
111 void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type);
112 void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type);
113 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type);
114
115 // Get the default value oop for the given InlineKlass
116 void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj);
117 // The empty value oop, for the given InlineKlass ("empty" as in no instance fields)
118 // get_default_value_oop with extra assertion for empty inline klass
119 void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj);
120
121 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
122 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
123 void test_field_is_inlined(Register flags, Register temp_reg, Label& is_inlined);
124
125 // Check oops for special arrays, i.e. flattened and/or null-free
126 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
127 void test_flattened_array_oop(Register oop, Register temp_reg, Label&is_flattened_array);
128 void test_non_flattened_array_oop(Register oop, Register temp_reg, Label&is_non_flattened_array);
129 void test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array);
130 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
131
132 // Check array klass layout helper for flatten or null-free arrays...
133 void test_flattened_array_layout(Register lh, Label& is_flattened_array);
134 void test_non_flattened_array_layout(Register lh, Label& is_non_flattened_array);
135 void test_null_free_array_layout(Register lh, Label& is_null_free_array);
136 void test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array);
137
138 // Required platform-specific helpers for Label::patch_instructions.
139 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
140 void pd_patch_instruction(address branch, address target, const char* file, int line) {
141 unsigned char op = branch[0];
142 assert(op == 0xE8 /* call */ ||
143 op == 0xE9 /* jmp */ ||
144 op == 0xEB /* short jmp */ ||
145 (op & 0xF0) == 0x70 /* short jcc */ ||
146 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
147 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
148 "Invalid opcode at patch point");
149
150 if (op == 0xEB || (op & 0xF0) == 0x70) {
151 // short offset operators (jmp and jcc)
152 char* disp = (char*) &branch[1];
153 int imm8 = target - (address) &disp[1];
154 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
155 file == NULL ? "<NULL>" : file, line);
156 *disp = imm8;
157 } else {
158 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
159 int imm32 = target - (address) &disp[1];
160 *disp = imm32;
161 }
162 }
163
164 // The following 4 methods return the offset of the appropriate move instruction
165
166 // Support for fast byte/short loading with zero extension (depending on particular CPU)
167 int load_unsigned_byte(Register dst, Address src);
168 int load_unsigned_short(Register dst, Address src);
169
170 // Support for fast byte/short loading with sign extension (depending on particular CPU)
171 int load_signed_byte(Register dst, Address src);
172 int load_signed_short(Register dst, Address src);
173
174 // Support for sign-extension (hi:lo = extend_sign(lo))
175 void extend_sign(Register hi, Register lo);
176
177 // Load and store values by size and signed-ness
178 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
179 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
180
181 // Support for inc/dec with optimal instruction selection depending on value
182
183 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
184 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
185
186 void decrementl(Address dst, int value = 1);
187 void decrementl(Register reg, int value = 1);
188
189 void decrementq(Register reg, int value = 1);
190 void decrementq(Address dst, int value = 1);
191
192 void incrementl(Address dst, int value = 1);
193 void incrementl(Register reg, int value = 1);
194
195 void incrementq(Register reg, int value = 1);
196 void incrementq(Address dst, int value = 1);
197
198 // Support optimal SSE move instructions.
199 void movflt(XMMRegister dst, XMMRegister src) {
200 if (dst-> encoding() == src->encoding()) return;
201 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
202 else { movss (dst, src); return; }
203 }
204 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
205 void movflt(XMMRegister dst, AddressLiteral src);
206 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
207
208 // Move with zero extension
209 void movfltz(XMMRegister dst, XMMRegister src) { movss(dst, src); }
210
211 void movdbl(XMMRegister dst, XMMRegister src) {
212 if (dst-> encoding() == src->encoding()) return;
213 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
214 else { movsd (dst, src); return; }
215 }
216
217 void movdbl(XMMRegister dst, AddressLiteral src);
218
219 void movdbl(XMMRegister dst, Address src) {
220 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
221 else { movlpd(dst, src); return; }
222 }
223 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
224
225 void incrementl(AddressLiteral dst);
226 void incrementl(ArrayAddress dst);
227
228 void incrementq(AddressLiteral dst);
229
230 // Alignment
231 void align32();
232 void align64();
233 void align(int modulus);
234 void align(int modulus, int target);
235
236 // A 5 byte nop that is safe for patching (see patch_verified_entry)
237 void fat_nop();
238
239 // Stack frame creation/removal
240 void enter();
241 void leave();
242
243 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
244 // The pointer will be loaded into the thread register.
245 void get_thread(Register thread);
246
247 #ifdef _LP64
248 // Support for argument shuffling
249
250 void move32_64(VMRegPair src, VMRegPair dst);
251 void long_move(VMRegPair src, VMRegPair dst);
252 void float_move(VMRegPair src, VMRegPair dst);
253 void double_move(VMRegPair src, VMRegPair dst);
254 void move_ptr(VMRegPair src, VMRegPair dst);
255 void object_move(OopMap* map,
256 int oop_handle_offset,
257 int framesize_in_slots,
258 VMRegPair src,
259 VMRegPair dst,
260 bool is_receiver,
261 int* receiver_offset);
262 #endif // _LP64
263
264 // Support for VM calls
265 //
266 // It is imperative that all calls into the VM are handled via the call_VM macros.
267 // They make sure that the stack linkage is setup correctly. call_VM's correspond
268 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
269
270
271 void call_VM(Register oop_result,
272 address entry_point,
273 bool check_exceptions = true);
274 void call_VM(Register oop_result,
275 address entry_point,
276 Register arg_1,
277 bool check_exceptions = true);
278 void call_VM(Register oop_result,
279 address entry_point,
280 Register arg_1, Register arg_2,
281 bool check_exceptions = true);
282 void call_VM(Register oop_result,
283 address entry_point,
284 Register arg_1, Register arg_2, Register arg_3,
285 bool check_exceptions = true);
286
287 // Overloadings with last_Java_sp
288 void call_VM(Register oop_result,
289 Register last_java_sp,
290 address entry_point,
291 int number_of_arguments = 0,
292 bool check_exceptions = true);
293 void call_VM(Register oop_result,
294 Register last_java_sp,
295 address entry_point,
296 Register arg_1, bool
297 check_exceptions = true);
298 void call_VM(Register oop_result,
299 Register last_java_sp,
300 address entry_point,
301 Register arg_1, Register arg_2,
302 bool check_exceptions = true);
303 void call_VM(Register oop_result,
304 Register last_java_sp,
305 address entry_point,
306 Register arg_1, Register arg_2, Register arg_3,
307 bool check_exceptions = true);
308
309 void get_vm_result (Register oop_result, Register thread);
310 void get_vm_result_2(Register metadata_result, Register thread);
311
312 // These always tightly bind to MacroAssembler::call_VM_base
313 // bypassing the virtual implementation
314 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
315 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
316 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
317 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
318 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
319
320 void call_VM_leaf0(address entry_point);
321 void call_VM_leaf(address entry_point,
322 int number_of_arguments = 0);
323 void call_VM_leaf(address entry_point,
324 Register arg_1);
325 void call_VM_leaf(address entry_point,
326 Register arg_1, Register arg_2);
327 void call_VM_leaf(address entry_point,
328 Register arg_1, Register arg_2, Register arg_3);
329
330 // These always tightly bind to MacroAssembler::call_VM_leaf_base
331 // bypassing the virtual implementation
332 void super_call_VM_leaf(address entry_point);
333 void super_call_VM_leaf(address entry_point, Register arg_1);
334 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
335 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
336 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
337
338 // last Java Frame (fills frame anchor)
339 void set_last_Java_frame(Register thread,
340 Register last_java_sp,
341 Register last_java_fp,
342 address last_java_pc);
343
344 // thread in the default location (r15_thread on 64bit)
345 void set_last_Java_frame(Register last_java_sp,
346 Register last_java_fp,
347 address last_java_pc);
348
349 void reset_last_Java_frame(Register thread, bool clear_fp);
350
351 // thread in the default location (r15_thread on 64bit)
352 void reset_last_Java_frame(bool clear_fp);
353
354 // jobjects
355 void clear_jweak_tag(Register possibly_jweak);
356 void resolve_jobject(Register value, Register thread, Register tmp);
357
358 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
359 void c2bool(Register x);
360
361 // C++ bool manipulation
362
363 void movbool(Register dst, Address src);
364 void movbool(Address dst, bool boolconst);
365 void movbool(Address dst, Register src);
366 void testbool(Register dst);
367
368 void resolve_oop_handle(Register result, Register tmp = rscratch2);
369 void resolve_weak_handle(Register result, Register tmp);
370 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
371 void load_method_holder_cld(Register rresult, Register rmethod);
372
373 void load_method_holder(Register holder, Register method);
374
375 // oop manipulations
376 void load_metadata(Register dst, Register src);
377 void load_klass(Register dst, Register src, Register tmp);
378 void store_klass(Register dst, Register src, Register tmp);
379
380 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
381 Register tmp1, Register thread_tmp);
382 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
383 Register tmp1, Register tmp2, Register tmp3 = noreg);
384
385 void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass);
386
387 // inline type data payload offsets...
388 void first_field_offset(Register inline_klass, Register offset);
389 void data_for_oop(Register oop, Register data, Register inline_klass);
390 // get data payload ptr a flat value array at index, kills rcx and index
391 void data_for_value_array_index(Register array, Register array_klass,
392 Register index, Register data);
393
394
395 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
396 Register thread_tmp = noreg, DecoratorSet decorators = 0);
397 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
398 Register thread_tmp = noreg, DecoratorSet decorators = 0);
399 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
400 Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
401
402 // Used for storing NULL. All other oop constants should be
403 // stored using routines that take a jobject.
404 void store_heap_oop_null(Address dst);
405
406 void load_prototype_header(Register dst, Register src, Register tmp);
407
408 #ifdef _LP64
409 void store_klass_gap(Register dst, Register src);
410
411 // This dummy is to prevent a call to store_heap_oop from
412 // converting a zero (like NULL) into a Register by giving
413 // the compiler two choices it can't resolve
414
415 void store_heap_oop(Address dst, void* dummy);
416
417 void encode_heap_oop(Register r);
418 void decode_heap_oop(Register r);
419 void encode_heap_oop_not_null(Register r);
420 void decode_heap_oop_not_null(Register r);
421 void encode_heap_oop_not_null(Register dst, Register src);
422 void decode_heap_oop_not_null(Register dst, Register src);
423
424 void set_narrow_oop(Register dst, jobject obj);
425 void set_narrow_oop(Address dst, jobject obj);
426 void cmp_narrow_oop(Register dst, jobject obj);
427 void cmp_narrow_oop(Address dst, jobject obj);
428
429 void encode_klass_not_null(Register r, Register tmp);
430 void decode_klass_not_null(Register r, Register tmp);
431 void encode_and_move_klass_not_null(Register dst, Register src);
432 void decode_and_move_klass_not_null(Register dst, Register src);
433 void set_narrow_klass(Register dst, Klass* k);
434 void set_narrow_klass(Address dst, Klass* k);
435 void cmp_narrow_klass(Register dst, Klass* k);
436 void cmp_narrow_klass(Address dst, Klass* k);
437
438 // if heap base register is used - reinit it with the correct value
439 void reinit_heapbase();
440
441 DEBUG_ONLY(void verify_heapbase(const char* msg);)
442
443 #endif // _LP64
444
445 // Int division/remainder for Java
446 // (as idivl, but checks for special case as described in JVM spec.)
447 // returns idivl instruction offset for implicit exception handling
448 int corrected_idivl(Register reg);
449
450 // Long division/remainder for Java
451 // (as idivq, but checks for special case as described in JVM spec.)
452 // returns idivq instruction offset for implicit exception handling
453 int corrected_idivq(Register reg);
454
455 void int3();
456
457 // Long operation macros for a 32bit cpu
458 // Long negation for Java
459 void lneg(Register hi, Register lo);
460
461 // Long multiplication for Java
462 // (destroys contents of eax, ebx, ecx and edx)
463 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
464
465 // Long shifts for Java
466 // (semantics as described in JVM spec.)
467 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
468 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
469
470 // Long compare for Java
471 // (semantics as described in JVM spec.)
472 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
473
474
475 // misc
476
477 // Sign extension
478 void sign_extend_short(Register reg);
479 void sign_extend_byte(Register reg);
480
481 // Division by power of 2, rounding towards 0
482 void division_with_shift(Register reg, int shift_value);
483
484 #ifndef _LP64
485 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
486 //
487 // CF (corresponds to C0) if x < y
488 // PF (corresponds to C2) if unordered
489 // ZF (corresponds to C3) if x = y
490 //
491 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
492 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
493 void fcmp(Register tmp);
494 // Variant of the above which allows y to be further down the stack
495 // and which only pops x and y if specified. If pop_right is
496 // specified then pop_left must also be specified.
497 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
498
499 // Floating-point comparison for Java
500 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
501 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
502 // (semantics as described in JVM spec.)
503 void fcmp2int(Register dst, bool unordered_is_less);
504 // Variant of the above which allows y to be further down the stack
505 // and which only pops x and y if specified. If pop_right is
506 // specified then pop_left must also be specified.
507 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
508
509 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
510 // tmp is a temporary register, if none is available use noreg
511 void fremr(Register tmp);
512
513 // only if +VerifyFPU
514 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
515 #endif // !LP64
516
517 // dst = c = a * b + c
518 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
519 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
520
521 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
522 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
523 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
524 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
525
526
527 // same as fcmp2int, but using SSE2
528 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
529 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
530
531 // branch to L if FPU flag C2 is set/not set
532 // tmp is a temporary register, if none is available use noreg
533 void jC2 (Register tmp, Label& L);
534 void jnC2(Register tmp, Label& L);
535
536 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
537 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
538 void load_float(Address src);
539
540 // Store float value to 'address'. If UseSSE >= 1, the value is stored
541 // from register xmm0. Otherwise, the value is stored from the FPU stack.
542 void store_float(Address dst);
543
544 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
545 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
546 void load_double(Address src);
547
548 // Store double value to 'address'. If UseSSE >= 2, the value is stored
549 // from register xmm0. Otherwise, the value is stored from the FPU stack.
550 void store_double(Address dst);
551
552 #ifndef _LP64
553 // Pop ST (ffree & fincstp combined)
554 void fpop();
555
556 void empty_FPU_stack();
557 #endif // !_LP64
558
559 void push_IU_state();
560 void pop_IU_state();
561
562 void push_FPU_state();
563 void pop_FPU_state();
564
565 void push_CPU_state();
566 void pop_CPU_state();
567
568 // Round up to a power of two
569 void round_to(Register reg, int modulus);
570
571 // Callee saved registers handling
572 void push_callee_saved_registers();
573 void pop_callee_saved_registers();
574
575 // allocation
576
577 // Object / value buffer allocation...
578 // Allocate instance of klass, assumes klass initialized by caller
579 // new_obj prefers to be rax
580 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
581 void allocate_instance(Register klass, Register new_obj,
582 Register t1, Register t2,
583 bool clear_fields, Label& alloc_failed);
584
585 void eden_allocate(
586 Register thread, // Current thread
587 Register obj, // result: pointer to object after successful allocation
588 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
589 int con_size_in_bytes, // object size in bytes if known at compile time
590 Register t1, // temp register
591 Label& slow_case // continuation point if fast allocation fails
592 );
593 void tlab_allocate(
594 Register thread, // Current thread
595 Register obj, // result: pointer to object after successful allocation
596 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
597 int con_size_in_bytes, // object size in bytes if known at compile time
598 Register t1, // temp register
599 Register t2, // temp register
600 Label& slow_case // continuation point if fast allocation fails
601 );
602 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
603
604 // For field "index" within "klass", return inline_klass ...
605 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
606
607 // interface method calling
608 void lookup_interface_method(Register recv_klass,
609 Register intf_klass,
610 RegisterOrConstant itable_index,
611 Register method_result,
612 Register scan_temp,
613 Label& no_such_interface,
614 bool return_method = true);
615
616 // virtual method calling
617 void lookup_virtual_method(Register recv_klass,
618 RegisterOrConstant vtable_index,
619 Register method_result);
620
621 // Test sub_klass against super_klass, with fast and slow paths.
622
623 // The fast path produces a tri-state answer: yes / no / maybe-slow.
624 // One of the three labels can be NULL, meaning take the fall-through.
625 // If super_check_offset is -1, the value is loaded up from super_klass.
626 // No registers are killed, except temp_reg.
627 void check_klass_subtype_fast_path(Register sub_klass,
628 Register super_klass,
629 Register temp_reg,
630 Label* L_success,
631 Label* L_failure,
632 Label* L_slow_path,
633 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
634
635 // The rest of the type check; must be wired to a corresponding fast path.
636 // It does not repeat the fast path logic, so don't use it standalone.
637 // The temp_reg and temp2_reg can be noreg, if no temps are available.
638 // Updates the sub's secondary super cache as necessary.
639 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
640 void check_klass_subtype_slow_path(Register sub_klass,
641 Register super_klass,
642 Register temp_reg,
643 Register temp2_reg,
644 Label* L_success,
645 Label* L_failure,
646 bool set_cond_codes = false);
647
648 // Simplified, combined version, good for typical uses.
649 // Falls through on failure.
650 void check_klass_subtype(Register sub_klass,
651 Register super_klass,
652 Register temp_reg,
653 Label& L_success);
654
655 void clinit_barrier(Register klass,
656 Register thread,
657 Label* L_fast_path = NULL,
658 Label* L_slow_path = NULL);
659
660 // method handles (JSR 292)
661 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
662
663 // Debugging
664
665 // only if +VerifyOops
666 void _verify_oop(Register reg, const char* s, const char* file, int line);
667 void _verify_oop_addr(Address addr, const char* s, const char* file, int line);
668
669 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
670 if (VerifyOops) {
671 _verify_oop(reg, s, file, line);
672 }
673 }
674 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
675 if (VerifyOops) {
676 _verify_oop_addr(reg, s, file, line);
677 }
678 }
679
680 // TODO: verify method and klass metadata (compare against vptr?)
681 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
682 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
683
684 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
685 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
686 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
687 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
688 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
689
690 // Verify or restore cpu control state after JNI call
691 void restore_cpu_control_state_after_jni();
692
693 // prints msg, dumps registers and stops execution
694 void stop(const char* msg);
695
696 // prints msg and continues
697 void warn(const char* msg);
698
699 // dumps registers and other state
700 void print_state();
701
702 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
703 static void debug64(char* msg, int64_t pc, int64_t regs[]);
704 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
705 static void print_state64(int64_t pc, int64_t regs[]);
706
707 void os_breakpoint();
708
709 void untested() { stop("untested"); }
710
711 void unimplemented(const char* what = "");
712
713 void should_not_reach_here() { stop("should not reach here"); }
714
715 void print_CPU_state();
716
717 // Stack overflow checking
718 void bang_stack_with_offset(int offset) {
719 // stack grows down, caller passes positive offset
720 assert(offset > 0, "must bang with negative offset");
721 movl(Address(rsp, (-offset)), rax);
722 }
723
724 // Writes to stack successive pages until offset reached to check for
725 // stack overflow + shadow pages. Also, clobbers tmp
726 void bang_stack_size(Register size, Register tmp);
727
728 // Check for reserved stack access in method being exited (for JIT)
729 void reserved_stack_check();
730
731 void safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod);
732
733 void verify_tlab();
734
735 Condition negate_condition(Condition cond);
736
737 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
738 // operands. In general the names are modified to avoid hiding the instruction in Assembler
739 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
740 // here in MacroAssembler. The major exception to this rule is call
741
742 // Arithmetics
743
744
745 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
746 void addptr(Address dst, Register src);
747
748 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
749 void addptr(Register dst, int32_t src);
750 void addptr(Register dst, Register src);
751 void addptr(Register dst, RegisterOrConstant src) {
752 if (src.is_constant()) addptr(dst, (int) src.as_constant());
753 else addptr(dst, src.as_register());
754 }
755
756 void andptr(Register dst, int32_t src);
757 void andptr(Register dst, Register src) { LP64_ONLY(andq(dst, src)) NOT_LP64(andl(dst, src)) ; }
758 void andptr(Register dst, Address src) { LP64_ONLY(andq(dst, src)) NOT_LP64(andl(dst, src)) ; }
759
760 void cmp8(AddressLiteral src1, int imm);
761
762 // renamed to drag out the casting of address to int32_t/intptr_t
763 void cmp32(Register src1, int32_t imm);
764
765 void cmp32(AddressLiteral src1, int32_t imm);
766 // compare reg - mem, or reg - &mem
767 void cmp32(Register src1, AddressLiteral src2);
768
769 void cmp32(Register src1, Address src2);
770
771 #ifndef _LP64
772 void cmpklass(Address dst, Metadata* obj);
773 void cmpklass(Register dst, Metadata* obj);
774 void cmpoop(Address dst, jobject obj);
775 #endif // _LP64
776
777 void cmpoop(Register src1, Register src2);
778 void cmpoop(Register src1, Address src2);
779 void cmpoop(Register dst, jobject obj);
780
781 // NOTE src2 must be the lval. This is NOT an mem-mem compare
782 void cmpptr(Address src1, AddressLiteral src2);
783
784 void cmpptr(Register src1, AddressLiteral src2);
785
786 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
787 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
788 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
789
790 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
791 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
792
793 // cmp64 to avoild hiding cmpq
794 void cmp64(Register src1, AddressLiteral src);
795
796 void cmpxchgptr(Register reg, Address adr);
797
798 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
799
800
801 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
802 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
803
804
805 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
806
807 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
808
809 void shlptr(Register dst, int32_t shift);
810 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
811
812 void shrptr(Register dst, int32_t shift);
813 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
814
815 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
816 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
817
818 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
819
820 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
821 void subptr(Register dst, int32_t src);
822 // Force generation of a 4 byte immediate value even if it fits into 8bit
823 void subptr_imm32(Register dst, int32_t src);
824 void subptr(Register dst, Register src);
825 void subptr(Register dst, RegisterOrConstant src) {
826 if (src.is_constant()) subptr(dst, (int) src.as_constant());
827 else subptr(dst, src.as_register());
828 }
829
830 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
831 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
832
833 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
834 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
835
836 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
837
838
839
840 // Helper functions for statistics gathering.
841 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
842 void cond_inc32(Condition cond, AddressLiteral counter_addr);
843 // Unconditional atomic increment.
844 void atomic_incl(Address counter_addr);
845 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
846 #ifdef _LP64
847 void atomic_incq(Address counter_addr);
848 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
849 #endif
850 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
851 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
852
853 void lea(Register dst, AddressLiteral adr);
854 void lea(Address dst, AddressLiteral adr);
855 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
856
857 void leal32(Register dst, Address src) { leal(dst, src); }
858
859 // Import other testl() methods from the parent class or else
860 // they will be hidden by the following overriding declaration.
861 using Assembler::testl;
862 void testl(Register dst, AddressLiteral src);
863
864 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
865 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
866 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
867 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
868
869 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
870 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
871 void testptr(Register src1, Register src2);
872
873 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
874 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
875
876 // Calls
877
878 void call(Label& L, relocInfo::relocType rtype);
879 void call(Register entry);
880 void call(Address addr) { Assembler::call(addr); }
881
882 // NOTE: this call transfers to the effective address of entry NOT
883 // the address contained by entry. This is because this is more natural
884 // for jumps/calls.
885 void call(AddressLiteral entry);
886
887 // Emit the CompiledIC call idiom
888 void ic_call(address entry, jint method_index = 0);
889
890 // Jumps
891
892 // NOTE: these jumps tranfer to the effective address of dst NOT
893 // the address contained by dst. This is because this is more natural
894 // for jumps/calls.
895 void jump(AddressLiteral dst);
896 void jump_cc(Condition cc, AddressLiteral dst);
897
898 // 32bit can do a case table jump in one instruction but we no longer allow the base
899 // to be installed in the Address class. This jump will tranfers to the address
900 // contained in the location described by entry (not the address of entry)
901 void jump(ArrayAddress entry);
902
903 // Floating
904
905 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
906 void andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
907 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
908
909 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
910 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
911 void andps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
912
913 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
914 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
915 void comiss(XMMRegister dst, AddressLiteral src);
916
917 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
918 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
919 void comisd(XMMRegister dst, AddressLiteral src);
920
921 #ifndef _LP64
922 void fadd_s(Address src) { Assembler::fadd_s(src); }
923 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
924
925 void fldcw(Address src) { Assembler::fldcw(src); }
926 void fldcw(AddressLiteral src);
927
928 void fld_s(int index) { Assembler::fld_s(index); }
929 void fld_s(Address src) { Assembler::fld_s(src); }
930 void fld_s(AddressLiteral src);
931
932 void fld_d(Address src) { Assembler::fld_d(src); }
933 void fld_d(AddressLiteral src);
934
935 void fmul_s(Address src) { Assembler::fmul_s(src); }
936 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
937 #endif // _LP64
938
939 void fld_x(Address src) { Assembler::fld_x(src); }
940 void fld_x(AddressLiteral src);
941
942 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
943 void ldmxcsr(AddressLiteral src);
944
945 #ifdef _LP64
946 private:
947 void sha256_AVX2_one_round_compute(
948 Register reg_old_h,
949 Register reg_a,
950 Register reg_b,
951 Register reg_c,
952 Register reg_d,
953 Register reg_e,
954 Register reg_f,
955 Register reg_g,
956 Register reg_h,
957 int iter);
958 void sha256_AVX2_four_rounds_compute_first(int start);
959 void sha256_AVX2_four_rounds_compute_last(int start);
960 void sha256_AVX2_one_round_and_sched(
961 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
962 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
963 XMMRegister xmm_2, /* ymm6 */
964 XMMRegister xmm_3, /* ymm7 */
965 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
966 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
967 Register reg_c, /* edi */
968 Register reg_d, /* esi */
969 Register reg_e, /* r8d */
970 Register reg_f, /* r9d */
971 Register reg_g, /* r10d */
972 Register reg_h, /* r11d */
973 int iter);
974
975 void addm(int disp, Register r1, Register r2);
976 void gfmul(XMMRegister tmp0, XMMRegister t);
977 void schoolbookAAD(int i, Register subkeyH, XMMRegister data, XMMRegister tmp0,
978 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3);
979 void generateHtbl_one_block(Register htbl);
980 void generateHtbl_eight_blocks(Register htbl);
981 public:
982 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
983 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
984 Register buf, Register state, Register ofs, Register limit, Register rsp,
985 bool multi_block, XMMRegister shuf_mask);
986 void avx_ghash(Register state, Register htbl, Register data, Register blocks);
987 #endif
988
989 #ifdef _LP64
990 private:
991 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
992 Register e, Register f, Register g, Register h, int iteration);
993
994 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
995 Register a, Register b, Register c, Register d, Register e, Register f,
996 Register g, Register h, int iteration);
997
998 void addmq(int disp, Register r1, Register r2);
999 public:
1000 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1001 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1002 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
1003 XMMRegister shuf_mask);
1004 private:
1005 void roundEnc(XMMRegister key, int rnum);
1006 void lastroundEnc(XMMRegister key, int rnum);
1007 void roundDec(XMMRegister key, int rnum);
1008 void lastroundDec(XMMRegister key, int rnum);
1009 void ev_load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask);
1010 void gfmul_avx512(XMMRegister ghash, XMMRegister hkey);
1011 void generateHtbl_48_block_zmm(Register htbl, Register avx512_subkeyHtbl);
1012 void ghash16_encrypt16_parallel(Register key, Register subkeyHtbl, XMMRegister ctr_blockx,
1013 XMMRegister aad_hashx, Register in, Register out, Register data, Register pos, bool reduction,
1014 XMMRegister addmask, bool no_ghash_input, Register rounds, Register ghash_pos,
1015 bool final_reduction, int index, XMMRegister counter_inc_mask);
1016 public:
1017 void aesecb_encrypt(Register source_addr, Register dest_addr, Register key, Register len);
1018 void aesecb_decrypt(Register source_addr, Register dest_addr, Register key, Register len);
1019 void aesctr_encrypt(Register src_addr, Register dest_addr, Register key, Register counter,
1020 Register len_reg, Register used, Register used_addr, Register saved_encCounter_start);
1021 void aesgcm_encrypt(Register in, Register len, Register ct, Register out, Register key,
1022 Register state, Register subkeyHtbl, Register avx512_subkeyHtbl, Register counter);
1023
1024 #endif
1025
1026 void fast_md5(Register buf, Address state, Address ofs, Address limit,
1027 bool multi_block);
1028
1029 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1030 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1031 Register buf, Register state, Register ofs, Register limit, Register rsp,
1032 bool multi_block);
1033
1034 #ifdef _LP64
1035 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1036 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1037 Register buf, Register state, Register ofs, Register limit, Register rsp,
1038 bool multi_block, XMMRegister shuf_mask);
1039 #else
1040 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1041 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1042 Register buf, Register state, Register ofs, Register limit, Register rsp,
1043 bool multi_block);
1044 #endif
1045
1046 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1047 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1048 Register rax, Register rcx, Register rdx, Register tmp);
1049
1050 #ifdef _LP64
1051 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1052 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1053 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1054
1055 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1056 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1057 Register rax, Register rcx, Register rdx, Register r11);
1058
1059 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1060 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1061 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1062
1063 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1064 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1065 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1066 Register tmp3, Register tmp4);
1067
1068 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1069 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1070 Register rax, Register rcx, Register rdx, Register tmp1,
1071 Register tmp2, Register tmp3, Register tmp4);
1072 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1073 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1074 Register rax, Register rcx, Register rdx, Register tmp1,
1075 Register tmp2, Register tmp3, Register tmp4);
1076 #else
1077 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1078 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1079 Register rax, Register rcx, Register rdx, Register tmp1);
1080
1081 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1082 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1083 Register rax, Register rcx, Register rdx, Register tmp);
1084
1085 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1086 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1087 Register rdx, Register tmp);
1088
1089 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1090 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1091 Register rax, Register rbx, Register rdx);
1092
1093 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1094 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1095 Register rax, Register rcx, Register rdx, Register tmp);
1096
1097 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1098 Register edx, Register ebx, Register esi, Register edi,
1099 Register ebp, Register esp);
1100
1101 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1102 Register esi, Register edi, Register ebp, Register esp);
1103
1104 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1105 Register edx, Register ebx, Register esi, Register edi,
1106 Register ebp, Register esp);
1107
1108 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1109 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1110 Register rax, Register rcx, Register rdx, Register tmp);
1111 #endif
1112
1113 private:
1114
1115 // these are private because users should be doing movflt/movdbl
1116
1117 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1118 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1119 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1120 void movss(XMMRegister dst, AddressLiteral src);
1121
1122 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1123 void movlpd(XMMRegister dst, AddressLiteral src);
1124
1125 public:
1126
1127 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1128 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1129 void addsd(XMMRegister dst, AddressLiteral src);
1130
1131 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1132 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1133 void addss(XMMRegister dst, AddressLiteral src);
1134
1135 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1136 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1137 void addpd(XMMRegister dst, AddressLiteral src);
1138
1139 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1140 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1141 void divsd(XMMRegister dst, AddressLiteral src);
1142
1143 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1144 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1145 void divss(XMMRegister dst, AddressLiteral src);
1146
1147 // Move Unaligned Double Quadword
1148 void movdqu(Address dst, XMMRegister src);
1149 void movdqu(XMMRegister dst, Address src);
1150 void movdqu(XMMRegister dst, XMMRegister src);
1151 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1152
1153 void kmovwl(KRegister dst, Register src) { Assembler::kmovwl(dst, src); }
1154 void kmovwl(Register dst, KRegister src) { Assembler::kmovwl(dst, src); }
1155 void kmovwl(KRegister dst, Address src) { Assembler::kmovwl(dst, src); }
1156 void kmovwl(KRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1157 void kmovwl(Address dst, KRegister src) { Assembler::kmovwl(dst, src); }
1158 void kmovwl(KRegister dst, KRegister src) { Assembler::kmovwl(dst, src); }
1159
1160 void kmovql(KRegister dst, KRegister src) { Assembler::kmovql(dst, src); }
1161 void kmovql(KRegister dst, Register src) { Assembler::kmovql(dst, src); }
1162 void kmovql(Register dst, KRegister src) { Assembler::kmovql(dst, src); }
1163 void kmovql(KRegister dst, Address src) { Assembler::kmovql(dst, src); }
1164 void kmovql(Address dst, KRegister src) { Assembler::kmovql(dst, src); }
1165 void kmovql(KRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1166
1167 // Safe move operation, lowers down to 16bit moves for targets supporting
1168 // AVX512F feature and 64bit moves for targets supporting AVX512BW feature.
1169 void kmov(Address dst, KRegister src);
1170 void kmov(KRegister dst, Address src);
1171 void kmov(KRegister dst, KRegister src);
1172 void kmov(Register dst, KRegister src);
1173 void kmov(KRegister dst, Register src);
1174
1175 // AVX Unaligned forms
1176 void vmovdqu(Address dst, XMMRegister src);
1177 void vmovdqu(XMMRegister dst, Address src);
1178 void vmovdqu(XMMRegister dst, XMMRegister src);
1179 void vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1180
1181 // AVX512 Unaligned
1182 void evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, int vector_len);
1183 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, int vector_len);
1184
1185 void evmovdqub(Address dst, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, src, merge, vector_len); }
1186 void evmovdqub(XMMRegister dst, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, src, merge, vector_len); }
1187 void evmovdqub(XMMRegister dst, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, src, merge, vector_len); }
1188 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1189 void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1190 void evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1191
1192 void evmovdquw(Address dst, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, src, merge, vector_len); }
1193 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1194 void evmovdquw(XMMRegister dst, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, src, merge, vector_len); }
1195 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1196 void evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1197
1198 void evmovdqul(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1199 void evmovdqul(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1200 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
1201 if (dst->encoding() == src->encoding()) return;
1202 Assembler::evmovdqul(dst, src, vector_len);
1203 }
1204 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1205 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1206 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1207 if (dst->encoding() == src->encoding() && mask == k0) return;
1208 Assembler::evmovdqul(dst, mask, src, merge, vector_len);
1209 }
1210 void evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1211
1212 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1213 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1214 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1215 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
1216 if (dst->encoding() == src->encoding()) return;
1217 Assembler::evmovdquq(dst, src, vector_len);
1218 }
1219 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1220 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1221 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1222 if (dst->encoding() == src->encoding() && mask == k0) return;
1223 Assembler::evmovdquq(dst, mask, src, merge, vector_len);
1224 }
1225 void evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1226
1227 // Move Aligned Double Quadword
1228 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1229 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1230 void movdqa(XMMRegister dst, AddressLiteral src);
1231
1232 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1233 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1234 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1235 void movsd(XMMRegister dst, AddressLiteral src);
1236
1237 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1238 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1239 void mulpd(XMMRegister dst, AddressLiteral src);
1240
1241 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1242 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1243 void mulsd(XMMRegister dst, AddressLiteral src);
1244
1245 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1246 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1247 void mulss(XMMRegister dst, AddressLiteral src);
1248
1249 // Carry-Less Multiplication Quadword
1250 void pclmulldq(XMMRegister dst, XMMRegister src) {
1251 // 0x00 - multiply lower 64 bits [0:63]
1252 Assembler::pclmulqdq(dst, src, 0x00);
1253 }
1254 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1255 // 0x11 - multiply upper 64 bits [64:127]
1256 Assembler::pclmulqdq(dst, src, 0x11);
1257 }
1258
1259 void pcmpeqb(XMMRegister dst, XMMRegister src);
1260 void pcmpeqw(XMMRegister dst, XMMRegister src);
1261
1262 void pcmpestri(XMMRegister dst, Address src, int imm8);
1263 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1264
1265 void pmovzxbw(XMMRegister dst, XMMRegister src);
1266 void pmovzxbw(XMMRegister dst, Address src);
1267
1268 void pmovmskb(Register dst, XMMRegister src);
1269
1270 void ptest(XMMRegister dst, XMMRegister src);
1271
1272 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1273 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1274 void sqrtsd(XMMRegister dst, AddressLiteral src);
1275
1276 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1277 void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1278 void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg);
1279
1280 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1281 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1282 void sqrtss(XMMRegister dst, AddressLiteral src);
1283
1284 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1285 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1286 void subsd(XMMRegister dst, AddressLiteral src);
1287
1288 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1289 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1290 void subss(XMMRegister dst, AddressLiteral src);
1291
1292 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1293 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1294 void ucomiss(XMMRegister dst, AddressLiteral src);
1295
1296 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1297 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1298 void ucomisd(XMMRegister dst, AddressLiteral src);
1299
1300 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1301 void xorpd(XMMRegister dst, XMMRegister src);
1302 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1303 void xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1304
1305 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1306 void xorps(XMMRegister dst, XMMRegister src);
1307 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1308 void xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1309
1310 // Shuffle Bytes
1311 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1312 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1313 void pshufb(XMMRegister dst, AddressLiteral src);
1314 // AVX 3-operands instructions
1315
1316 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1317 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1318 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1319
1320 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1321 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1322 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1323
1324 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1325 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1326
1327 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1328 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1329 void vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch);
1330
1331 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1332 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1333
1334 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1335 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1336 void vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch);
1337
1338 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1339 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1340 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1341
1342 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1343 void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1344
1345 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1346
1347 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1348 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg);
1349
1350 // Vector compares
1351 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1352 int comparison, bool is_signed, int vector_len) { Assembler::evpcmpd(kdst, mask, nds, src, comparison, is_signed, vector_len); }
1353 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1354 int comparison, bool is_signed, int vector_len, Register scratch_reg);
1355 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1356 int comparison, bool is_signed, int vector_len) { Assembler::evpcmpq(kdst, mask, nds, src, comparison, is_signed, vector_len); }
1357 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1358 int comparison, bool is_signed, int vector_len, Register scratch_reg);
1359 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1360 int comparison, bool is_signed, int vector_len) { Assembler::evpcmpb(kdst, mask, nds, src, comparison, is_signed, vector_len); }
1361 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1362 int comparison, bool is_signed, int vector_len, Register scratch_reg);
1363 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1364 int comparison, bool is_signed, int vector_len) { Assembler::evpcmpw(kdst, mask, nds, src, comparison, is_signed, vector_len); }
1365 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1366 int comparison, bool is_signed, int vector_len, Register scratch_reg);
1367
1368
1369 // Emit comparison instruction for the specified comparison predicate.
1370 void vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, ComparisonPredicate cond, Width width, int vector_len, Register scratch_reg);
1371 void vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len);
1372
1373 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1374 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1375
1376 void vpmovmskb(Register dst, XMMRegister src, int vector_len = Assembler::AVX_256bit);
1377
1378 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1379 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1380 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1381 Assembler::vpmulld(dst, nds, src, vector_len);
1382 };
1383 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1384 Assembler::vpmulld(dst, nds, src, vector_len);
1385 }
1386 void vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg);
1387
1388 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1389 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1390
1391 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1392 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1393
1394 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1395 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1396
1397 void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1398 void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1399
1400 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1401 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1402
1403 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1404 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1405
1406 void vptest(XMMRegister dst, XMMRegister src);
1407 void vptest(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vptest(dst, src, vector_len); }
1408
1409 void punpcklbw(XMMRegister dst, XMMRegister src);
1410 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1411
1412 void pshufd(XMMRegister dst, Address src, int mode);
1413 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1414
1415 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1416 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1417
1418 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1419 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1420 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1421
1422 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1423 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1424 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1425
1426 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1427
1428 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1429 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1430 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1431
1432 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1433 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1434 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1435
1436 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1437 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1438 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1439
1440 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1441 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1442 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1443
1444 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1445 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1446 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1447
1448 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1449 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1450 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1451
1452 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1453 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1454
1455 // AVX Vector instructions
1456
1457 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1458 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1459 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1460
1461 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1462 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1463 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1464
1465 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1466 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1467 Assembler::vpxor(dst, nds, src, vector_len);
1468 else
1469 Assembler::vxorpd(dst, nds, src, vector_len);
1470 }
1471 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1472 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1473 Assembler::vpxor(dst, nds, src, vector_len);
1474 else
1475 Assembler::vxorpd(dst, nds, src, vector_len);
1476 }
1477 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1478
1479 // Simple version for AVX2 256bit vectors
1480 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1481 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1482
1483 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpermd(dst, nds, src, vector_len); }
1484 void vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg);
1485
1486 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1487 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1488 Assembler::vinserti32x4(dst, nds, src, imm8);
1489 } else if (UseAVX > 1) {
1490 // vinserti128 is available only in AVX2
1491 Assembler::vinserti128(dst, nds, src, imm8);
1492 } else {
1493 Assembler::vinsertf128(dst, nds, src, imm8);
1494 }
1495 }
1496
1497 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1498 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1499 Assembler::vinserti32x4(dst, nds, src, imm8);
1500 } else if (UseAVX > 1) {
1501 // vinserti128 is available only in AVX2
1502 Assembler::vinserti128(dst, nds, src, imm8);
1503 } else {
1504 Assembler::vinsertf128(dst, nds, src, imm8);
1505 }
1506 }
1507
1508 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1509 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1510 Assembler::vextracti32x4(dst, src, imm8);
1511 } else if (UseAVX > 1) {
1512 // vextracti128 is available only in AVX2
1513 Assembler::vextracti128(dst, src, imm8);
1514 } else {
1515 Assembler::vextractf128(dst, src, imm8);
1516 }
1517 }
1518
1519 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1520 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1521 Assembler::vextracti32x4(dst, src, imm8);
1522 } else if (UseAVX > 1) {
1523 // vextracti128 is available only in AVX2
1524 Assembler::vextracti128(dst, src, imm8);
1525 } else {
1526 Assembler::vextractf128(dst, src, imm8);
1527 }
1528 }
1529
1530 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1531 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1532 vinserti128(dst, dst, src, 1);
1533 }
1534 void vinserti128_high(XMMRegister dst, Address src) {
1535 vinserti128(dst, dst, src, 1);
1536 }
1537 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1538 vextracti128(dst, src, 1);
1539 }
1540 void vextracti128_high(Address dst, XMMRegister src) {
1541 vextracti128(dst, src, 1);
1542 }
1543
1544 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1545 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1546 Assembler::vinsertf32x4(dst, dst, src, 1);
1547 } else {
1548 Assembler::vinsertf128(dst, dst, src, 1);
1549 }
1550 }
1551
1552 void vinsertf128_high(XMMRegister dst, Address src) {
1553 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1554 Assembler::vinsertf32x4(dst, dst, src, 1);
1555 } else {
1556 Assembler::vinsertf128(dst, dst, src, 1);
1557 }
1558 }
1559
1560 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1561 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1562 Assembler::vextractf32x4(dst, src, 1);
1563 } else {
1564 Assembler::vextractf128(dst, src, 1);
1565 }
1566 }
1567
1568 void vextractf128_high(Address dst, XMMRegister src) {
1569 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1570 Assembler::vextractf32x4(dst, src, 1);
1571 } else {
1572 Assembler::vextractf128(dst, src, 1);
1573 }
1574 }
1575
1576 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1577 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1578 Assembler::vinserti64x4(dst, dst, src, 1);
1579 }
1580 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1581 Assembler::vinsertf64x4(dst, dst, src, 1);
1582 }
1583 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1584 Assembler::vextracti64x4(dst, src, 1);
1585 }
1586 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1587 Assembler::vextractf64x4(dst, src, 1);
1588 }
1589 void vextractf64x4_high(Address dst, XMMRegister src) {
1590 Assembler::vextractf64x4(dst, src, 1);
1591 }
1592 void vinsertf64x4_high(XMMRegister dst, Address src) {
1593 Assembler::vinsertf64x4(dst, dst, src, 1);
1594 }
1595
1596 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1597 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1598 vinserti128(dst, dst, src, 0);
1599 }
1600 void vinserti128_low(XMMRegister dst, Address src) {
1601 vinserti128(dst, dst, src, 0);
1602 }
1603 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1604 vextracti128(dst, src, 0);
1605 }
1606 void vextracti128_low(Address dst, XMMRegister src) {
1607 vextracti128(dst, src, 0);
1608 }
1609
1610 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1611 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1612 Assembler::vinsertf32x4(dst, dst, src, 0);
1613 } else {
1614 Assembler::vinsertf128(dst, dst, src, 0);
1615 }
1616 }
1617
1618 void vinsertf128_low(XMMRegister dst, Address src) {
1619 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1620 Assembler::vinsertf32x4(dst, dst, src, 0);
1621 } else {
1622 Assembler::vinsertf128(dst, dst, src, 0);
1623 }
1624 }
1625
1626 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1627 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1628 Assembler::vextractf32x4(dst, src, 0);
1629 } else {
1630 Assembler::vextractf128(dst, src, 0);
1631 }
1632 }
1633
1634 void vextractf128_low(Address dst, XMMRegister src) {
1635 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1636 Assembler::vextractf32x4(dst, src, 0);
1637 } else {
1638 Assembler::vextractf128(dst, src, 0);
1639 }
1640 }
1641
1642 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1643 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1644 Assembler::vinserti64x4(dst, dst, src, 0);
1645 }
1646 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1647 Assembler::vinsertf64x4(dst, dst, src, 0);
1648 }
1649 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1650 Assembler::vextracti64x4(dst, src, 0);
1651 }
1652 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1653 Assembler::vextractf64x4(dst, src, 0);
1654 }
1655 void vextractf64x4_low(Address dst, XMMRegister src) {
1656 Assembler::vextractf64x4(dst, src, 0);
1657 }
1658 void vinsertf64x4_low(XMMRegister dst, Address src) {
1659 Assembler::vinsertf64x4(dst, dst, src, 0);
1660 }
1661
1662 // Carry-Less Multiplication Quadword
1663 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1664 // 0x00 - multiply lower 64 bits [0:63]
1665 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1666 }
1667 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1668 // 0x11 - multiply upper 64 bits [64:127]
1669 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1670 }
1671 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1672 // 0x10 - multiply nds[0:63] and src[64:127]
1673 Assembler::vpclmulqdq(dst, nds, src, 0x10);
1674 }
1675 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1676 //0x01 - multiply nds[64:127] and src[0:63]
1677 Assembler::vpclmulqdq(dst, nds, src, 0x01);
1678 }
1679
1680 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1681 // 0x00 - multiply lower 64 bits [0:63]
1682 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1683 }
1684 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1685 // 0x11 - multiply upper 64 bits [64:127]
1686 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1687 }
1688
1689 // Data
1690
1691 void cmov32( Condition cc, Register dst, Address src);
1692 void cmov32( Condition cc, Register dst, Register src);
1693
1694 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1695
1696 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1697 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1698
1699 void movoop(Register dst, jobject obj);
1700 void movoop(Address dst, jobject obj);
1701
1702 void mov_metadata(Register dst, Metadata* obj);
1703 void mov_metadata(Address dst, Metadata* obj);
1704
1705 void movptr(ArrayAddress dst, Register src);
1706 // can this do an lea?
1707 void movptr(Register dst, ArrayAddress src);
1708
1709 void movptr(Register dst, Address src);
1710
1711 #ifdef _LP64
1712 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1713 #else
1714 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1715 #endif
1716
1717 void movptr(Register dst, intptr_t src);
1718 void movptr(Register dst, Register src);
1719 void movptr(Address dst, intptr_t src);
1720
1721 void movptr(Address dst, Register src);
1722
1723 void movptr(Register dst, RegisterOrConstant src) {
1724 if (src.is_constant()) movptr(dst, src.as_constant());
1725 else movptr(dst, src.as_register());
1726 }
1727
1728 #ifdef _LP64
1729 // Generally the next two are only used for moving NULL
1730 // Although there are situations in initializing the mark word where
1731 // they could be used. They are dangerous.
1732
1733 // They only exist on LP64 so that int32_t and intptr_t are not the same
1734 // and we have ambiguous declarations.
1735
1736 void movptr(Address dst, int32_t imm32);
1737 void movptr(Register dst, int32_t imm32);
1738 #endif // _LP64
1739
1740 // to avoid hiding movl
1741 void mov32(AddressLiteral dst, Register src);
1742 void mov32(Register dst, AddressLiteral src);
1743
1744 // to avoid hiding movb
1745 void movbyte(ArrayAddress dst, int src);
1746
1747 // Import other mov() methods from the parent class or else
1748 // they will be hidden by the following overriding declaration.
1749 using Assembler::movdl;
1750 using Assembler::movq;
1751 void movdl(XMMRegister dst, AddressLiteral src);
1752 void movq(XMMRegister dst, AddressLiteral src);
1753
1754 // Can push value or effective address
1755 void pushptr(AddressLiteral src);
1756
1757 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1758 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1759
1760 void pushoop(jobject obj);
1761 void pushklass(Metadata* obj);
1762
1763 // sign extend as need a l to ptr sized element
1764 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1765 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1766
1767
1768 public:
1769 // C2 compiled method's prolog code.
1770 void verified_entry(Compile* C, int sp_inc = 0);
1771
1772 // Inline type specific methods
1773 #include "asm/macroAssembler_common.hpp"
1774
1775 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1776 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1777 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1778 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1779 RegState reg_state[]);
1780 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1781 VMRegPair* from, int from_count, int& from_index, VMReg to,
1782 RegState reg_state[], Register val_array);
1783 int extend_stack_for_inline_args(int args_on_stack);
1784 void remove_frame(int initial_framesize, bool needs_stack_repair);
1785 VMReg spill_reg_for(VMReg reg);
1786
1787 // clear memory of size 'cnt' qwords, starting at 'base';
1788 // if 'is_large' is set, do not try to produce short loop
1789 void clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only, KRegister mask=knoreg);
1790
1791 // clear memory initialization sequence for constant size;
1792 void clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1793
1794 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1795 void xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1796
1797 // Fill primitive arrays
1798 void generate_fill(BasicType t, bool aligned,
1799 Register to, Register value, Register count,
1800 Register rtmp, XMMRegister xtmp);
1801
1802 void encode_iso_array(Register src, Register dst, Register len,
1803 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1804 XMMRegister tmp4, Register tmp5, Register result, bool ascii);
1805
1806 #ifdef _LP64
1807 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1808 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1809 Register y, Register y_idx, Register z,
1810 Register carry, Register product,
1811 Register idx, Register kdx);
1812 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1813 Register yz_idx, Register idx,
1814 Register carry, Register product, int offset);
1815 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1816 Register carry, Register carry2,
1817 Register idx, Register jdx,
1818 Register yz_idx1, Register yz_idx2,
1819 Register tmp, Register tmp3, Register tmp4);
1820 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1821 Register yz_idx, Register idx, Register jdx,
1822 Register carry, Register product,
1823 Register carry2);
1824 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1825 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1826 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1827 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1828 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1829 Register tmp2);
1830 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1831 Register rdxReg, Register raxReg);
1832 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1833 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1834 Register tmp3, Register tmp4);
1835 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1836 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1837
1838 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1839 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1840 Register raxReg);
1841 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1842 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1843 Register raxReg);
1844 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1845 Register result, Register tmp1, Register tmp2,
1846 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1847 #endif
1848
1849 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1850 void update_byte_crc32(Register crc, Register val, Register table);
1851 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1852
1853
1854 #ifdef _LP64
1855 void kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2);
1856 void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
1857 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
1858 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup);
1859 void updateBytesAdler32(Register adler32, Register buf, Register length, XMMRegister shuf0, XMMRegister shuf1, ExternalAddress scale);
1860 #endif // _LP64
1861
1862 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1863 // Note on a naming convention:
1864 // Prefix w = register only used on a Westmere+ architecture
1865 // Prefix n = register only used on a Nehalem architecture
1866 #ifdef _LP64
1867 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1868 Register tmp1, Register tmp2, Register tmp3);
1869 #else
1870 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1871 Register tmp1, Register tmp2, Register tmp3,
1872 XMMRegister xtmp1, XMMRegister xtmp2);
1873 #endif
1874 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1875 Register in_out,
1876 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1877 XMMRegister w_xtmp2,
1878 Register tmp1,
1879 Register n_tmp2, Register n_tmp3);
1880 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1881 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1882 Register tmp1, Register tmp2,
1883 Register n_tmp3);
1884 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1885 Register in_out1, Register in_out2, Register in_out3,
1886 Register tmp1, Register tmp2, Register tmp3,
1887 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1888 Register tmp4, Register tmp5,
1889 Register n_tmp6);
1890 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1891 Register tmp1, Register tmp2, Register tmp3,
1892 Register tmp4, Register tmp5, Register tmp6,
1893 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1894 bool is_pclmulqdq_supported);
1895 // Fold 128-bit data chunk
1896 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1897 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1898 #ifdef _LP64
1899 // Fold 512-bit data chunk
1900 void fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, Register pos, int offset);
1901 #endif // _LP64
1902 // Fold 8-bit data
1903 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1904 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1905
1906 // Compress char[] array to byte[].
1907 void char_array_compress(Register src, Register dst, Register len,
1908 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1909 XMMRegister tmp4, Register tmp5, Register result,
1910 KRegister mask1 = knoreg, KRegister mask2 = knoreg);
1911
1912 // Inflate byte[] array to char[].
1913 void byte_array_inflate(Register src, Register dst, Register len,
1914 XMMRegister tmp1, Register tmp2, KRegister mask = knoreg);
1915
1916 void fill64_masked_avx(uint shift, Register dst, int disp,
1917 XMMRegister xmm, KRegister mask, Register length,
1918 Register temp, bool use64byteVector = false);
1919
1920 void fill32_masked_avx(uint shift, Register dst, int disp,
1921 XMMRegister xmm, KRegister mask, Register length,
1922 Register temp);
1923
1924 void fill32_avx(Register dst, int disp, XMMRegister xmm);
1925
1926 void fill64_avx(Register dst, int dis, XMMRegister xmm, bool use64byteVector = false);
1927
1928 #ifdef _LP64
1929 void convert_f2i(Register dst, XMMRegister src);
1930 void convert_d2i(Register dst, XMMRegister src);
1931 void convert_f2l(Register dst, XMMRegister src);
1932 void convert_d2l(Register dst, XMMRegister src);
1933
1934 void cache_wb(Address line);
1935 void cache_wbsync(bool is_pre);
1936
1937 #if COMPILER2_OR_JVMCI
1938 void arraycopy_avx3_special_cases(XMMRegister xmm, KRegister mask, Register from,
1939 Register to, Register count, int shift,
1940 Register index, Register temp,
1941 bool use64byteVector, Label& L_entry, Label& L_exit);
1942
1943 void arraycopy_avx3_special_cases_conjoint(XMMRegister xmm, KRegister mask, Register from,
1944 Register to, Register start_index, Register end_index,
1945 Register count, int shift, Register temp,
1946 bool use64byteVector, Label& L_entry, Label& L_exit);
1947
1948 void copy64_masked_avx(Register dst, Register src, XMMRegister xmm,
1949 KRegister mask, Register length, Register index,
1950 Register temp, int shift = Address::times_1, int offset = 0,
1951 bool use64byteVector = false);
1952
1953 void copy32_masked_avx(Register dst, Register src, XMMRegister xmm,
1954 KRegister mask, Register length, Register index,
1955 Register temp, int shift = Address::times_1, int offset = 0);
1956
1957 void copy32_avx(Register dst, Register src, Register index, XMMRegister xmm,
1958 int shift = Address::times_1, int offset = 0);
1959
1960 void copy64_avx(Register dst, Register src, Register index, XMMRegister xmm,
1961 bool conjoint, int shift = Address::times_1, int offset = 0,
1962 bool use64byteVector = false);
1963 #endif // COMPILER2_OR_JVMCI
1964
1965 #endif // _LP64
1966
1967 void vallones(XMMRegister dst, int vector_len);
1968 };
1969
1970 /**
1971 * class SkipIfEqual:
1972 *
1973 * Instantiating this class will result in assembly code being output that will
1974 * jump around any code emitted between the creation of the instance and it's
1975 * automatic destruction at the end of a scope block, depending on the value of
1976 * the flag passed to the constructor, which will be checked at run-time.
1977 */
1978 class SkipIfEqual {
1979 private:
1980 MacroAssembler* _masm;
1981 Label _label;
1982
1983 public:
1984 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1985 ~SkipIfEqual();
1986 };
1987
1988 #endif // CPU_X86_MACROASSEMBLER_X86_HPP