1 /*
2 * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "asm/register.hpp"
30 #include "code/vmreg.inline.hpp"
31 #include "compiler/oopMap.hpp"
32 #include "utilities/macros.hpp"
33 #include "runtime/signature.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/checkedCast.hpp"
36
37 class ciInlineKlass;
38
39 // MacroAssembler extends Assembler by frequently used macros.
40 //
41 // Instructions for which a 'better' code sequence exists depending
42 // on arguments should also go in here.
43
44 class MacroAssembler: public Assembler {
45 friend class LIR_Assembler;
46 friend class Runtime1; // as_Address()
47
48 public:
49 // Support for VM calls
50 //
51 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
52 // may customize this version by overriding it for its purposes (e.g., to save/restore
53 // additional registers when doing a VM call).
54
55 virtual void call_VM_leaf_base(
56 address entry_point, // the entry point
57 int number_of_arguments // the number of arguments to pop after the call
58 );
59
60 protected:
61 // This is the base routine called by the different versions of call_VM. The interpreter
62 // may customize this version by overriding it for its purposes (e.g., to save/restore
63 // additional registers when doing a VM call).
64 //
65 // call_VM_base returns the register which contains the thread upon return.
66 // If no last_java_sp is specified (noreg) than rsp will be used instead.
67 virtual void call_VM_base( // returns the register containing the thread upon return
68 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
69 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
70 address entry_point, // the entry point
71 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
72 bool check_exceptions // whether to check for pending exceptions after return
73 );
74
75 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
76
77 public:
78 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
79
80 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
81 // The implementation is only non-empty for the InterpreterMacroAssembler,
82 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
83 virtual void check_and_handle_popframe();
84 virtual void check_and_handle_earlyret();
85
86 Address as_Address(AddressLiteral adr);
87 Address as_Address(ArrayAddress adr, Register rscratch);
88
89 // Support for null-checks
90 //
91 // Generates code that causes a null OS exception if the content of reg is null.
92 // If the accessed location is M[reg + offset] and the offset is known, provide the
93 // offset. No explicit code generation is needed if the offset is within a certain
94 // range (0 <= offset <= page_size).
95
96 void null_check(Register reg, int offset = -1);
97 static bool needs_explicit_null_check(intptr_t offset);
98 static bool uses_implicit_null_check(void* address);
99
100 // markWord tests, kills markWord reg
101 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
102
103 // inlineKlass queries, kills temp_reg
104 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
105
106 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
107 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
108 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
109
110 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
111 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
112 void test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array);
113 void test_non_flat_array_oop(Register oop, Register temp_reg, Label& is_non_flat_array);
114 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
115 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label& is_non_null_free_array);
116
117 // Check array klass layout helper for flat or null-free arrays...
118 void test_flat_array_layout(Register lh, Label& is_flat_array);
119
120 // Required platform-specific helpers for Label::patch_instructions.
121 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
122 void pd_patch_instruction(address branch, address target, const char* file, int line) {
123 unsigned char op = branch[0];
124 assert(op == 0xE8 /* call */ ||
125 op == 0xE9 /* jmp */ ||
126 op == 0xEB /* short jmp */ ||
127 (op & 0xF0) == 0x70 /* short jcc */ ||
128 (op == 0x0F && (branch[1] & 0xF0) == 0x80) /* jcc */ ||
129 (op == 0xC7 && branch[1] == 0xF8) /* xbegin */ ||
130 (op == 0x8D) /* lea */,
131 "Invalid opcode at patch point");
132
133 if (op == 0xEB || (op & 0xF0) == 0x70) {
134 // short offset operators (jmp and jcc)
135 char* disp = (char*) &branch[1];
136 int imm8 = checked_cast<int>(target - (address) &disp[1]);
137 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
138 file == nullptr ? "<null>" : file, line);
139 *disp = (char)imm8;
140 } else {
141 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7 || op == 0x8D) ? 2 : 1];
142 int imm32 = checked_cast<int>(target - (address) &disp[1]);
143 *disp = imm32;
144 }
145 }
146
147 // The following 4 methods return the offset of the appropriate move instruction
148
149 // Support for fast byte/short loading with zero extension (depending on particular CPU)
150 int load_unsigned_byte(Register dst, Address src);
151 int load_unsigned_short(Register dst, Address src);
152
153 // Support for fast byte/short loading with sign extension (depending on particular CPU)
154 int load_signed_byte(Register dst, Address src);
155 int load_signed_short(Register dst, Address src);
156
157 // Support for sign-extension (hi:lo = extend_sign(lo))
158 void extend_sign(Register hi, Register lo);
159
160 // Load and store values by size and signed-ness
161 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
162 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
163
164 // Support for inc/dec with optimal instruction selection depending on value
165
166 void increment(Register reg, int value = 1) { incrementq(reg, value); }
167 void decrement(Register reg, int value = 1) { decrementq(reg, value); }
168 void increment(Address dst, int value = 1) { incrementq(dst, value); }
169 void decrement(Address dst, int value = 1) { decrementq(dst, value); }
170
171 void decrementl(Address dst, int value = 1);
172 void decrementl(Register reg, int value = 1);
173
174 void decrementq(Register reg, int value = 1);
175 void decrementq(Address dst, int value = 1);
176
177 void incrementl(Address dst, int value = 1);
178 void incrementl(Register reg, int value = 1);
179
180 void incrementq(Register reg, int value = 1);
181 void incrementq(Address dst, int value = 1);
182
183 void incrementl(AddressLiteral dst, Register rscratch = noreg);
184 void incrementl(ArrayAddress dst, Register rscratch);
185
186 void incrementq(AddressLiteral dst, Register rscratch = noreg);
187
188 void movhlf(XMMRegister dst, XMMRegister src, Register rscratch = noreg);
189
190 // Support optimal SSE move instructions.
191 void movflt(XMMRegister dst, XMMRegister src) {
192 if (dst-> encoding() == src->encoding()) return;
193 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
194 else { movss (dst, src); return; }
195 }
196 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
197 void movflt(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
198 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
199
200 // Move with zero extension
201 void movfltz(XMMRegister dst, XMMRegister src) { movss(dst, src); }
202
203 void movdbl(XMMRegister dst, XMMRegister src) {
204 if (dst-> encoding() == src->encoding()) return;
205 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
206 else { movsd (dst, src); return; }
207 }
208
209 void movdbl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
210
211 void movdbl(XMMRegister dst, Address src) {
212 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
213 else { movlpd(dst, src); return; }
214 }
215 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
216
217 void flt_to_flt16(Register dst, XMMRegister src, XMMRegister tmp) {
218 // Use separate tmp XMM register because caller may
219 // requires src XMM register to be unchanged (as in x86.ad).
220 vcvtps2ph(tmp, src, 0x04, Assembler::AVX_128bit);
221 movdl(dst, tmp);
222 movswl(dst, dst);
223 }
224
225 void flt16_to_flt(XMMRegister dst, Register src) {
226 movdl(dst, src);
227 vcvtph2ps(dst, dst, Assembler::AVX_128bit);
228 }
229
230 // Alignment
231 void align32();
232 void align64();
233 void align(uint modulus);
234 void align(uint modulus, uint target);
235
236 void post_call_nop();
237
238 // Stack frame creation/removal
239 void enter();
240 void leave();
241
242 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information).
243 // The pointer will be loaded into the thread register. This is a slow version that does native call.
244 // Normally, JavaThread pointer is available in r15_thread, use that where possible.
245 void get_thread_slow(Register thread);
246
247 // Support for argument shuffling
248
249 // bias in bytes
250 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
251 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
252 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
253 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
254 void move_ptr(VMRegPair src, VMRegPair dst);
255 void object_move(OopMap* map,
256 int oop_handle_offset,
257 int framesize_in_slots,
258 VMRegPair src,
259 VMRegPair dst,
260 bool is_receiver,
261 int* receiver_offset);
262
263 // Support for VM calls
264 //
265 // It is imperative that all calls into the VM are handled via the call_VM macros.
266 // They make sure that the stack linkage is setup correctly. call_VM's correspond
267 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
268
269
270 void call_VM(Register oop_result,
271 address entry_point,
272 bool check_exceptions = true);
273 void call_VM(Register oop_result,
274 address entry_point,
275 Register arg_1,
276 bool check_exceptions = true);
277 void call_VM(Register oop_result,
278 address entry_point,
279 Register arg_1, Register arg_2,
280 bool check_exceptions = true);
281 void call_VM(Register oop_result,
282 address entry_point,
283 Register arg_1, Register arg_2, Register arg_3,
284 bool check_exceptions = true);
285
286 // Overloadings with last_Java_sp
287 void call_VM(Register oop_result,
288 Register last_java_sp,
289 address entry_point,
290 int number_of_arguments = 0,
291 bool check_exceptions = true);
292 void call_VM(Register oop_result,
293 Register last_java_sp,
294 address entry_point,
295 Register arg_1, bool
296 check_exceptions = true);
297 void call_VM(Register oop_result,
298 Register last_java_sp,
299 address entry_point,
300 Register arg_1, Register arg_2,
301 bool check_exceptions = true);
302 void call_VM(Register oop_result,
303 Register last_java_sp,
304 address entry_point,
305 Register arg_1, Register arg_2, Register arg_3,
306 bool check_exceptions = true);
307
308 void get_vm_result_oop(Register oop_result);
309 void get_vm_result_metadata(Register metadata_result);
310
311 // These always tightly bind to MacroAssembler::call_VM_base
312 // bypassing the virtual implementation
313 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
314 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
315 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
316 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
317 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
318
319 void call_VM_leaf0(address entry_point);
320 void call_VM_leaf(address entry_point,
321 int number_of_arguments = 0);
322 void call_VM_leaf(address entry_point,
323 Register arg_1);
324 void call_VM_leaf(address entry_point,
325 Register arg_1, Register arg_2);
326 void call_VM_leaf(address entry_point,
327 Register arg_1, Register arg_2, Register arg_3);
328
329 void call_VM_leaf(address entry_point,
330 Register arg_1, Register arg_2, Register arg_3, Register arg_4);
331
332 // These always tightly bind to MacroAssembler::call_VM_leaf_base
333 // bypassing the virtual implementation
334 void super_call_VM_leaf(address entry_point);
335 void super_call_VM_leaf(address entry_point, Register arg_1);
336 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
337 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
338 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
339
340 void set_last_Java_frame(Register last_java_sp,
341 Register last_java_fp,
342 address last_java_pc,
343 Register rscratch);
344
345 void set_last_Java_frame(Register last_java_sp,
346 Register last_java_fp,
347 Label &last_java_pc,
348 Register scratch);
349
350 void reset_last_Java_frame(bool clear_fp);
351
352 // jobjects
353 void clear_jobject_tag(Register possibly_non_local);
354 void resolve_jobject(Register value, Register tmp);
355 void resolve_global_jobject(Register value, Register tmp);
356
357 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
358 void c2bool(Register x);
359
360 // C++ bool manipulation
361
362 void movbool(Register dst, Address src);
363 void movbool(Address dst, bool boolconst);
364 void movbool(Address dst, Register src);
365 void testbool(Register dst);
366
367 void resolve_oop_handle(Register result, Register tmp);
368 void resolve_weak_handle(Register result, Register tmp);
369 void load_mirror(Register mirror, Register method, Register tmp);
370 void load_method_holder_cld(Register rresult, Register rmethod);
371
372 void load_method_holder(Register holder, Register method);
373
374 // oop manipulations
375
376 // Load oopDesc._metadata without decode (useful for direct Klass* compare from oops)
377 void load_metadata(Register dst, Register src);
378 void load_narrow_klass_compact(Register dst, Register src);
379 void load_narrow_klass(Register dst, Register src);
380 void load_klass(Register dst, Register src, Register tmp);
381 void store_klass(Register dst, Register src, Register tmp);
382
383 // Compares the narrow Klass pointer of an object to a given narrow Klass.
384 void cmp_klass(Register klass, Register obj, Register tmp);
385
386 // Compares the Klass pointer of two objects obj1 and obj2. Result is in the condition flags.
387 // Uses tmp1 and tmp2 as temporary registers.
388 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
389
390 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
391 Register tmp1);
392 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
393 Register tmp1, Register tmp2, Register tmp3);
394
395 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
396
397 // inline type data payload offsets...
398 void payload_offset(Register inline_klass, Register offset);
399 void payload_addr(Register oop, Register data, Register inline_klass);
400
401 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg, DecoratorSet decorators = 0);
402 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg, DecoratorSet decorators = 0);
403 void store_heap_oop(Address dst, Register val, Register tmp1 = noreg,
404 Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
405
406 // Used for storing null. All other oop constants should be
407 // stored using routines that take a jobject.
408 void store_heap_oop_null(Address dst);
409
410 void load_prototype_header(Register dst, Register src, Register tmp);
411
412 void store_klass_gap(Register dst, Register src);
413
414 // This dummy is to prevent a call to store_heap_oop from
415 // converting a zero (like null) into a Register by giving
416 // the compiler two choices it can't resolve
417
418 void store_heap_oop(Address dst, void* dummy);
419
420 void encode_heap_oop(Register r);
421 void decode_heap_oop(Register r);
422 void encode_heap_oop_not_null(Register r);
423 void decode_heap_oop_not_null(Register r);
424 void encode_heap_oop_not_null(Register dst, Register src);
425 void decode_heap_oop_not_null(Register dst, Register src);
426
427 void set_narrow_oop(Register dst, jobject obj);
428 void set_narrow_oop(Address dst, jobject obj);
429 void cmp_narrow_oop(Register dst, jobject obj);
430 void cmp_narrow_oop(Address dst, jobject obj);
431
432 void encode_klass_not_null(Register r, Register tmp);
433 void decode_klass_not_null(Register r, Register tmp);
434 void encode_and_move_klass_not_null(Register dst, Register src);
435 void decode_and_move_klass_not_null(Register dst, Register src);
436 void set_narrow_klass(Register dst, Klass* k);
437 void set_narrow_klass(Address dst, Klass* k);
438 void cmp_narrow_klass(Register dst, Klass* k);
439 void cmp_narrow_klass(Address dst, Klass* k);
440
441 // if heap base register is used - reinit it with the correct value
442 void reinit_heapbase();
443
444 DEBUG_ONLY(void verify_heapbase(const char* msg);)
445
446 // Int division/remainder for Java
447 // (as idivl, but checks for special case as described in JVM spec.)
448 // returns idivl instruction offset for implicit exception handling
449 int corrected_idivl(Register reg);
450
451 // Long division/remainder for Java
452 // (as idivq, but checks for special case as described in JVM spec.)
453 // returns idivq instruction offset for implicit exception handling
454 int corrected_idivq(Register reg);
455
456 void int3();
457
458 // Long operation macros for a 32bit cpu
459 // Long negation for Java
460 void lneg(Register hi, Register lo);
461
462 // Long multiplication for Java
463 // (destroys contents of eax, ebx, ecx and edx)
464 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
465
466 // Long shifts for Java
467 // (semantics as described in JVM spec.)
468 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
469 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
470
471 // Long compare for Java
472 // (semantics as described in JVM spec.)
473 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
474
475
476 // misc
477
478 // Sign extension
479 void sign_extend_short(Register reg);
480 void sign_extend_byte(Register reg);
481
482 // Clean up a subword typed value to the representation in compliance with JVMS ยง2.3
483 void narrow_subword_type(Register reg, BasicType bt);
484
485 // Division by power of 2, rounding towards 0
486 void division_with_shift(Register reg, int shift_value);
487
488 // dst = c = a * b + c
489 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
490 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
491
492 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
493 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
494 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
495 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
496
497
498 // same as fcmp2int, but using SSE2
499 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
500 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
501
502 void push_IU_state();
503 void pop_IU_state();
504
505 void push_FPU_state();
506 void pop_FPU_state();
507
508 void push_CPU_state();
509 void pop_CPU_state();
510
511 void push_cont_fastpath();
512 void pop_cont_fastpath();
513
514 DEBUG_ONLY(void stop_if_in_cont(Register cont_reg, const char* name);)
515
516 // Round up to a power of two
517 void round_to(Register reg, int modulus);
518
519 private:
520 // General purpose and XMM registers potentially clobbered by native code; there
521 // is no need for FPU or AVX opmask related methods because C1/interpreter
522 // - we save/restore FPU state as a whole always
523 // - do not care about AVX-512 opmask
524 static RegSet call_clobbered_gp_registers();
525 static XMMRegSet call_clobbered_xmm_registers();
526
527 void push_set(XMMRegSet set, int offset);
528 void pop_set(XMMRegSet set, int offset);
529
530 public:
531 void push_set(RegSet set, int offset = -1);
532 void pop_set(RegSet set, int offset = -1);
533
534 // Push and pop everything that might be clobbered by a native
535 // runtime call.
536 // Only save the lower 64 bits of each vector register.
537 // Additional registers can be excluded in a passed RegSet.
538 void push_call_clobbered_registers_except(RegSet exclude, bool save_fpu = true);
539 void pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu = true);
540
541 void push_call_clobbered_registers(bool save_fpu = true) {
542 push_call_clobbered_registers_except(RegSet(), save_fpu);
543 }
544 void pop_call_clobbered_registers(bool restore_fpu = true) {
545 pop_call_clobbered_registers_except(RegSet(), restore_fpu);
546 }
547
548 // allocation
549 void tlab_allocate(
550 Register obj, // result: pointer to object after successful allocation
551 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
552 int con_size_in_bytes, // object size in bytes if known at compile time
553 Register t1, // temp register
554 Register t2, // temp register
555 Label& slow_case // continuation point if fast allocation fails
556 );
557 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
558
559 void inline_layout_info(Register klass, Register index, Register layout_info);
560
561 void population_count(Register dst, Register src, Register scratch1, Register scratch2);
562
563 // interface method calling
564 void lookup_interface_method(Register recv_klass,
565 Register intf_klass,
566 RegisterOrConstant itable_index,
567 Register method_result,
568 Register scan_temp,
569 Label& no_such_interface,
570 bool return_method = true);
571
572 void lookup_interface_method_stub(Register recv_klass,
573 Register holder_klass,
574 Register resolved_klass,
575 Register method_result,
576 Register scan_temp,
577 Register temp_reg2,
578 Register receiver,
579 int itable_index,
580 Label& L_no_such_interface);
581
582 // virtual method calling
583 void lookup_virtual_method(Register recv_klass,
584 RegisterOrConstant vtable_index,
585 Register method_result);
586
587 // Test sub_klass against super_klass, with fast and slow paths.
588
589 // The fast path produces a tri-state answer: yes / no / maybe-slow.
590 // One of the three labels can be null, meaning take the fall-through.
591 // If super_check_offset is -1, the value is loaded up from super_klass.
592 // No registers are killed, except temp_reg.
593 void check_klass_subtype_fast_path(Register sub_klass,
594 Register super_klass,
595 Register temp_reg,
596 Label* L_success,
597 Label* L_failure,
598 Label* L_slow_path,
599 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
600
601 // The rest of the type check; must be wired to a corresponding fast path.
602 // It does not repeat the fast path logic, so don't use it standalone.
603 // The temp_reg and temp2_reg can be noreg, if no temps are available.
604 // Updates the sub's secondary super cache as necessary.
605 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
606 void check_klass_subtype_slow_path(Register sub_klass,
607 Register super_klass,
608 Register temp_reg,
609 Register temp2_reg,
610 Label* L_success,
611 Label* L_failure,
612 bool set_cond_codes = false);
613
614 // The 64-bit version, which may do a hashed subclass lookup.
615 void check_klass_subtype_slow_path(Register sub_klass,
616 Register super_klass,
617 Register temp_reg,
618 Register temp2_reg,
619 Register temp3_reg,
620 Register temp4_reg,
621 Label* L_success,
622 Label* L_failure);
623
624 // Three parts of a hashed subclass lookup: a simple linear search,
625 // a table lookup, and a fallback that does linear probing in the
626 // event of a hash collision.
627 void check_klass_subtype_slow_path_linear(Register sub_klass,
628 Register super_klass,
629 Register temp_reg,
630 Register temp2_reg,
631 Label* L_success,
632 Label* L_failure,
633 bool set_cond_codes = false);
634 void check_klass_subtype_slow_path_table(Register sub_klass,
635 Register super_klass,
636 Register temp_reg,
637 Register temp2_reg,
638 Register temp3_reg,
639 Register result_reg,
640 Label* L_success,
641 Label* L_failure);
642 void hashed_check_klass_subtype_slow_path(Register sub_klass,
643 Register super_klass,
644 Register temp_reg,
645 Label* L_success,
646 Label* L_failure);
647
648 // As above, but with a constant super_klass.
649 // The result is in Register result, not the condition codes.
650 void lookup_secondary_supers_table_const(Register sub_klass,
651 Register super_klass,
652 Register temp1,
653 Register temp2,
654 Register temp3,
655 Register temp4,
656 Register result,
657 u1 super_klass_slot);
658
659 using Assembler::salq;
660 void salq(Register dest, Register count);
661 using Assembler::rorq;
662 void rorq(Register dest, Register count);
663 void lookup_secondary_supers_table_var(Register sub_klass,
664 Register super_klass,
665 Register temp1,
666 Register temp2,
667 Register temp3,
668 Register temp4,
669 Register result);
670
671 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
672 Register r_array_base,
673 Register r_array_index,
674 Register r_bitmap,
675 Register temp1,
676 Register temp2,
677 Label* L_success,
678 Label* L_failure = nullptr);
679
680 void verify_secondary_supers_table(Register r_sub_klass,
681 Register r_super_klass,
682 Register expected,
683 Register temp1,
684 Register temp2,
685 Register temp3);
686
687 void repne_scanq(Register addr, Register value, Register count, Register limit,
688 Label* L_success,
689 Label* L_failure = nullptr);
690
691 // If r is valid, return r.
692 // If r is invalid, remove a register r2 from available_regs, add r2
693 // to regs_to_push, then return r2.
694 Register allocate_if_noreg(const Register r,
695 RegSetIterator<Register> &available_regs,
696 RegSet ®s_to_push);
697
698 // Simplified, combined version, good for typical uses.
699 // Falls through on failure.
700 void check_klass_subtype(Register sub_klass,
701 Register super_klass,
702 Register temp_reg,
703 Label& L_success);
704
705 void clinit_barrier(Register klass,
706 Label* L_fast_path = nullptr,
707 Label* L_slow_path = nullptr);
708
709 // method handles (JSR 292)
710 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
711
712 void profile_receiver_type(Register recv, Register mdp, int mdp_offset);
713
714 // Debugging
715
716 // only if +VerifyOops
717 void _verify_oop(Register reg, const char* s, const char* file, int line);
718 void _verify_oop_addr(Address addr, const char* s, const char* file, int line);
719
720 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
721 if (VerifyOops) {
722 _verify_oop(reg, s, file, line);
723 }
724 }
725 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
726 if (VerifyOops) {
727 _verify_oop_addr(reg, s, file, line);
728 }
729 }
730
731 // TODO: verify method and klass metadata (compare against vptr?)
732 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
733 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
734
735 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
736 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
737 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
738 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
739 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
740
741 // Verify or restore cpu control state after JNI call
742 void restore_cpu_control_state_after_jni(Register rscratch);
743
744 // prints msg, dumps registers and stops execution
745 void stop(const char* msg);
746
747 // prints msg and continues
748 void warn(const char* msg);
749
750 // dumps registers and other state
751 void print_state();
752
753 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
754 static void debug64(char* msg, int64_t pc, int64_t regs[]);
755 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
756 static void print_state64(int64_t pc, int64_t regs[]);
757
758 void os_breakpoint();
759
760 void untested() { stop("untested"); }
761
762 void unimplemented(const char* what = "");
763
764 void should_not_reach_here() { stop("should not reach here"); }
765
766 void print_CPU_state();
767
768 // Stack overflow checking
769 void bang_stack_with_offset(int offset) {
770 // stack grows down, caller passes positive offset
771 assert(offset > 0, "must bang with negative offset");
772 movl(Address(rsp, (-offset)), rax);
773 }
774
775 // Writes to stack successive pages until offset reached to check for
776 // stack overflow + shadow pages. Also, clobbers tmp
777 void bang_stack_size(Register size, Register tmp);
778
779 // Check for reserved stack access in method being exited (for JIT)
780 void reserved_stack_check();
781
782 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod);
783
784 void verify_tlab();
785
786 static Condition negate_condition(Condition cond);
787
788 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
789 // operands. In general the names are modified to avoid hiding the instruction in Assembler
790 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
791 // here in MacroAssembler. The major exception to this rule is call
792
793 // Arithmetics
794
795
796 void addptr(Address dst, int32_t src) { addq(dst, src); }
797 void addptr(Address dst, Register src);
798
799 void addptr(Register dst, Address src) { addq(dst, src); }
800 void addptr(Register dst, int32_t src);
801 void addptr(Register dst, Register src);
802 void addptr(Register dst, RegisterOrConstant src) {
803 if (src.is_constant()) addptr(dst, checked_cast<int>(src.as_constant()));
804 else addptr(dst, src.as_register());
805 }
806
807 void andptr(Register dst, int32_t src);
808 void andptr(Register src1, Register src2) { andq(src1, src2); }
809 void andptr(Register dst, Address src) { andq(dst, src); }
810
811 using Assembler::andq;
812 void andq(Register dst, AddressLiteral src, Register rscratch = noreg);
813
814 void cmp8(AddressLiteral src1, int imm, Register rscratch = noreg);
815
816 // renamed to drag out the casting of address to int32_t/intptr_t
817 void cmp32(Register src1, int32_t imm);
818
819 void cmp32(AddressLiteral src1, int32_t imm, Register rscratch = noreg);
820 // compare reg - mem, or reg - &mem
821 void cmp32(Register src1, AddressLiteral src2, Register rscratch = noreg);
822
823 void cmp32(Register src1, Address src2);
824
825 void cmpoop(Register src1, Register src2);
826 void cmpoop(Register src1, Address src2);
827 void cmpoop(Register dst, jobject obj, Register rscratch);
828
829 // NOTE src2 must be the lval. This is NOT an mem-mem compare
830 void cmpptr(Address src1, AddressLiteral src2, Register rscratch);
831
832 void cmpptr(Register src1, AddressLiteral src2, Register rscratch = noreg);
833
834 void cmpptr(Register src1, Register src2) { cmpq(src1, src2); }
835 void cmpptr(Register src1, Address src2) { cmpq(src1, src2); }
836
837 void cmpptr(Register src1, int32_t src2) { cmpq(src1, src2); }
838 void cmpptr(Address src1, int32_t src2) { cmpq(src1, src2); }
839
840 // cmp64 to avoild hiding cmpq
841 void cmp64(Register src1, AddressLiteral src, Register rscratch = noreg);
842
843 void cmpxchgptr(Register reg, Address adr);
844
845 void locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch = noreg);
846
847 void imulptr(Register dst, Register src) { imulq(dst, src); }
848 void imulptr(Register dst, Register src, int imm32) { imulq(dst, src, imm32); }
849
850
851 void negptr(Register dst) { negq(dst); }
852
853 void notptr(Register dst) { notq(dst); }
854
855 void shlptr(Register dst, int32_t shift);
856 void shlptr(Register dst) { shlq(dst); }
857
858 void shrptr(Register dst, int32_t shift);
859 void shrptr(Register dst) { shrq(dst); }
860
861 void sarptr(Register dst) { sarq(dst); }
862 void sarptr(Register dst, int32_t src) { sarq(dst, src); }
863
864 void subptr(Address dst, int32_t src) { subq(dst, src); }
865
866 void subptr(Register dst, Address src) { subq(dst, src); }
867 void subptr(Register dst, int32_t src);
868 // Force generation of a 4 byte immediate value even if it fits into 8bit
869 void subptr_imm32(Register dst, int32_t src);
870 void subptr(Register dst, Register src);
871 void subptr(Register dst, RegisterOrConstant src) {
872 if (src.is_constant()) subptr(dst, (int) src.as_constant());
873 else subptr(dst, src.as_register());
874 }
875
876 void sbbptr(Address dst, int32_t src) { sbbq(dst, src); }
877 void sbbptr(Register dst, int32_t src) { sbbq(dst, src); }
878
879 void xchgptr(Register src1, Register src2) { xchgq(src1, src2); }
880 void xchgptr(Register src1, Address src2) { xchgq(src1, src2); }
881
882 void xaddptr(Address src1, Register src2) { xaddq(src1, src2); }
883
884
885
886 // Helper functions for statistics gathering.
887 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
888 void cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch = noreg);
889 // Unconditional atomic increment.
890 void atomic_incl(Address counter_addr);
891 void atomic_incl(AddressLiteral counter_addr, Register rscratch = noreg);
892 void atomic_incq(Address counter_addr);
893 void atomic_incq(AddressLiteral counter_addr, Register rscratch = noreg);
894 void atomic_incptr(AddressLiteral counter_addr, Register rscratch = noreg) { atomic_incq(counter_addr, rscratch); }
895 void atomic_incptr(Address counter_addr) { atomic_incq(counter_addr); }
896
897 using Assembler::lea;
898 void lea(Register dst, AddressLiteral adr);
899 void lea(Address dst, AddressLiteral adr, Register rscratch);
900
901 void leal32(Register dst, Address src) { leal(dst, src); }
902
903 // Import other testl() methods from the parent class or else
904 // they will be hidden by the following overriding declaration.
905 using Assembler::testl;
906 void testl(Address dst, int32_t imm32);
907 void testl(Register dst, int32_t imm32);
908 void testl(Register dst, AddressLiteral src); // requires reachable address
909 using Assembler::testq;
910 void testq(Address dst, int32_t imm32);
911 void testq(Register dst, int32_t imm32);
912
913 void orptr(Register dst, Address src) { orq(dst, src); }
914 void orptr(Register dst, Register src) { orq(dst, src); }
915 void orptr(Register dst, int32_t src) { orq(dst, src); }
916 void orptr(Address dst, int32_t imm32) { orq(dst, imm32); }
917
918 void testptr(Register src, int32_t imm32) { testq(src, imm32); }
919 void testptr(Register src1, Address src2) { testq(src1, src2); }
920 void testptr(Address src, int32_t imm32) { testq(src, imm32); }
921 void testptr(Register src1, Register src2);
922
923 void xorptr(Register dst, Register src) { xorq(dst, src); }
924 void xorptr(Register dst, Address src) { xorq(dst, src); }
925
926 // Calls
927
928 void call(Label& L, relocInfo::relocType rtype);
929 void call(Register entry);
930 void call(Address addr) { Assembler::call(addr); }
931
932 // NOTE: this call transfers to the effective address of entry NOT
933 // the address contained by entry. This is because this is more natural
934 // for jumps/calls.
935 void call(AddressLiteral entry, Register rscratch = rax);
936
937 // Emit the CompiledIC call idiom
938 void ic_call(address entry, jint method_index = 0);
939 static int ic_check_size();
940 int ic_check(int end_alignment);
941
942 void emit_static_call_stub();
943
944 // Jumps
945
946 // NOTE: these jumps transfer to the effective address of dst NOT
947 // the address contained by dst. This is because this is more natural
948 // for jumps/calls.
949 void jump(AddressLiteral dst, Register rscratch = noreg);
950
951 void jump_cc(Condition cc, AddressLiteral dst, Register rscratch = noreg);
952
953 // 32bit can do a case table jump in one instruction but we no longer allow the base
954 // to be installed in the Address class. This jump will transfer to the address
955 // contained in the location described by entry (not the address of entry)
956 void jump(ArrayAddress entry, Register rscratch);
957
958 // Adding more natural conditional jump instructions
959 void ALWAYSINLINE jo(Label& L, bool maybe_short = true) { jcc(Assembler::overflow, L, maybe_short); }
960 void ALWAYSINLINE jno(Label& L, bool maybe_short = true) { jcc(Assembler::noOverflow, L, maybe_short); }
961 void ALWAYSINLINE js(Label& L, bool maybe_short = true) { jcc(Assembler::negative, L, maybe_short); }
962 void ALWAYSINLINE jns(Label& L, bool maybe_short = true) { jcc(Assembler::positive, L, maybe_short); }
963 void ALWAYSINLINE je(Label& L, bool maybe_short = true) { jcc(Assembler::equal, L, maybe_short); }
964 void ALWAYSINLINE jz(Label& L, bool maybe_short = true) { jcc(Assembler::zero, L, maybe_short); }
965 void ALWAYSINLINE jne(Label& L, bool maybe_short = true) { jcc(Assembler::notEqual, L, maybe_short); }
966 void ALWAYSINLINE jnz(Label& L, bool maybe_short = true) { jcc(Assembler::notZero, L, maybe_short); }
967 void ALWAYSINLINE jb(Label& L, bool maybe_short = true) { jcc(Assembler::below, L, maybe_short); }
968 void ALWAYSINLINE jnae(Label& L, bool maybe_short = true) { jcc(Assembler::below, L, maybe_short); }
969 void ALWAYSINLINE jc(Label& L, bool maybe_short = true) { jcc(Assembler::carrySet, L, maybe_short); }
970 void ALWAYSINLINE jnb(Label& L, bool maybe_short = true) { jcc(Assembler::aboveEqual, L, maybe_short); }
971 void ALWAYSINLINE jae(Label& L, bool maybe_short = true) { jcc(Assembler::aboveEqual, L, maybe_short); }
972 void ALWAYSINLINE jnc(Label& L, bool maybe_short = true) { jcc(Assembler::carryClear, L, maybe_short); }
973 void ALWAYSINLINE jbe(Label& L, bool maybe_short = true) { jcc(Assembler::belowEqual, L, maybe_short); }
974 void ALWAYSINLINE jna(Label& L, bool maybe_short = true) { jcc(Assembler::belowEqual, L, maybe_short); }
975 void ALWAYSINLINE ja(Label& L, bool maybe_short = true) { jcc(Assembler::above, L, maybe_short); }
976 void ALWAYSINLINE jnbe(Label& L, bool maybe_short = true) { jcc(Assembler::above, L, maybe_short); }
977 void ALWAYSINLINE jl(Label& L, bool maybe_short = true) { jcc(Assembler::less, L, maybe_short); }
978 void ALWAYSINLINE jnge(Label& L, bool maybe_short = true) { jcc(Assembler::less, L, maybe_short); }
979 void ALWAYSINLINE jge(Label& L, bool maybe_short = true) { jcc(Assembler::greaterEqual, L, maybe_short); }
980 void ALWAYSINLINE jnl(Label& L, bool maybe_short = true) { jcc(Assembler::greaterEqual, L, maybe_short); }
981 void ALWAYSINLINE jle(Label& L, bool maybe_short = true) { jcc(Assembler::lessEqual, L, maybe_short); }
982 void ALWAYSINLINE jng(Label& L, bool maybe_short = true) { jcc(Assembler::lessEqual, L, maybe_short); }
983 void ALWAYSINLINE jg(Label& L, bool maybe_short = true) { jcc(Assembler::greater, L, maybe_short); }
984 void ALWAYSINLINE jnle(Label& L, bool maybe_short = true) { jcc(Assembler::greater, L, maybe_short); }
985 void ALWAYSINLINE jp(Label& L, bool maybe_short = true) { jcc(Assembler::parity, L, maybe_short); }
986 void ALWAYSINLINE jpe(Label& L, bool maybe_short = true) { jcc(Assembler::parity, L, maybe_short); }
987 void ALWAYSINLINE jnp(Label& L, bool maybe_short = true) { jcc(Assembler::noParity, L, maybe_short); }
988 void ALWAYSINLINE jpo(Label& L, bool maybe_short = true) { jcc(Assembler::noParity, L, maybe_short); }
989 // * No condition for this * void ALWAYSINLINE jcxz(Label& L, bool maybe_short = true) { jcc(Assembler::cxz, L, maybe_short); }
990 // * No condition for this * void ALWAYSINLINE jecxz(Label& L, bool maybe_short = true) { jcc(Assembler::cxz, L, maybe_short); }
991
992 // Short versions of the above
993 void ALWAYSINLINE jo_b(Label& L) { jccb(Assembler::overflow, L); }
994 void ALWAYSINLINE jno_b(Label& L) { jccb(Assembler::noOverflow, L); }
995 void ALWAYSINLINE js_b(Label& L) { jccb(Assembler::negative, L); }
996 void ALWAYSINLINE jns_b(Label& L) { jccb(Assembler::positive, L); }
997 void ALWAYSINLINE je_b(Label& L) { jccb(Assembler::equal, L); }
998 void ALWAYSINLINE jz_b(Label& L) { jccb(Assembler::zero, L); }
999 void ALWAYSINLINE jne_b(Label& L) { jccb(Assembler::notEqual, L); }
1000 void ALWAYSINLINE jnz_b(Label& L) { jccb(Assembler::notZero, L); }
1001 void ALWAYSINLINE jb_b(Label& L) { jccb(Assembler::below, L); }
1002 void ALWAYSINLINE jnae_b(Label& L) { jccb(Assembler::below, L); }
1003 void ALWAYSINLINE jc_b(Label& L) { jccb(Assembler::carrySet, L); }
1004 void ALWAYSINLINE jnb_b(Label& L) { jccb(Assembler::aboveEqual, L); }
1005 void ALWAYSINLINE jae_b(Label& L) { jccb(Assembler::aboveEqual, L); }
1006 void ALWAYSINLINE jnc_b(Label& L) { jccb(Assembler::carryClear, L); }
1007 void ALWAYSINLINE jbe_b(Label& L) { jccb(Assembler::belowEqual, L); }
1008 void ALWAYSINLINE jna_b(Label& L) { jccb(Assembler::belowEqual, L); }
1009 void ALWAYSINLINE ja_b(Label& L) { jccb(Assembler::above, L); }
1010 void ALWAYSINLINE jnbe_b(Label& L) { jccb(Assembler::above, L); }
1011 void ALWAYSINLINE jl_b(Label& L) { jccb(Assembler::less, L); }
1012 void ALWAYSINLINE jnge_b(Label& L) { jccb(Assembler::less, L); }
1013 void ALWAYSINLINE jge_b(Label& L) { jccb(Assembler::greaterEqual, L); }
1014 void ALWAYSINLINE jnl_b(Label& L) { jccb(Assembler::greaterEqual, L); }
1015 void ALWAYSINLINE jle_b(Label& L) { jccb(Assembler::lessEqual, L); }
1016 void ALWAYSINLINE jng_b(Label& L) { jccb(Assembler::lessEqual, L); }
1017 void ALWAYSINLINE jg_b(Label& L) { jccb(Assembler::greater, L); }
1018 void ALWAYSINLINE jnle_b(Label& L) { jccb(Assembler::greater, L); }
1019 void ALWAYSINLINE jp_b(Label& L) { jccb(Assembler::parity, L); }
1020 void ALWAYSINLINE jpe_b(Label& L) { jccb(Assembler::parity, L); }
1021 void ALWAYSINLINE jnp_b(Label& L) { jccb(Assembler::noParity, L); }
1022 void ALWAYSINLINE jpo_b(Label& L) { jccb(Assembler::noParity, L); }
1023 // * No condition for this * void ALWAYSINLINE jcxz_b(Label& L) { jccb(Assembler::cxz, L); }
1024 // * No condition for this * void ALWAYSINLINE jecxz_b(Label& L) { jccb(Assembler::cxz, L); }
1025
1026 // Floating
1027
1028 void push_f(XMMRegister r);
1029 void pop_f(XMMRegister r);
1030 void push_d(XMMRegister r);
1031 void pop_d(XMMRegister r);
1032
1033 void push_ppx(Register src);
1034 void pop_ppx(Register dst);
1035
1036 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
1037 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
1038 void andpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1039
1040 void andnpd(XMMRegister dst, XMMRegister src) { Assembler::andnpd(dst, src); }
1041
1042 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
1043 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
1044 void andps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1045
1046 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
1047 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
1048 void comiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1049
1050 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
1051 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
1052 void comisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1053
1054 void orpd(XMMRegister dst, XMMRegister src) { Assembler::orpd(dst, src); }
1055
1056 void cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch = noreg);
1057 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
1058 void ldmxcsr(AddressLiteral src, Register rscratch = noreg);
1059
1060 private:
1061 void sha256_AVX2_one_round_compute(
1062 Register reg_old_h,
1063 Register reg_a,
1064 Register reg_b,
1065 Register reg_c,
1066 Register reg_d,
1067 Register reg_e,
1068 Register reg_f,
1069 Register reg_g,
1070 Register reg_h,
1071 int iter);
1072 void sha256_AVX2_four_rounds_compute_first(int start);
1073 void sha256_AVX2_four_rounds_compute_last(int start);
1074 void sha256_AVX2_one_round_and_sched(
1075 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
1076 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
1077 XMMRegister xmm_2, /* ymm6 */
1078 XMMRegister xmm_3, /* ymm7 */
1079 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
1080 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
1081 Register reg_c, /* edi */
1082 Register reg_d, /* esi */
1083 Register reg_e, /* r8d */
1084 Register reg_f, /* r9d */
1085 Register reg_g, /* r10d */
1086 Register reg_h, /* r11d */
1087 int iter);
1088
1089 void addm(int disp, Register r1, Register r2);
1090
1091 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
1092 Register e, Register f, Register g, Register h, int iteration);
1093
1094 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1095 Register a, Register b, Register c, Register d, Register e, Register f,
1096 Register g, Register h, int iteration);
1097
1098 void addmq(int disp, Register r1, Register r2);
1099 public:
1100 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1101 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1102 Register buf, Register state, Register ofs, Register limit, Register rsp,
1103 bool multi_block, XMMRegister shuf_mask);
1104 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1105 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1106 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
1107 XMMRegister shuf_mask);
1108 void sha512_update_ni_x1(Register arg_hash, Register arg_msg, Register ofs, Register limit, bool multi_block);
1109
1110 void fast_md5(Register buf, Address state, Address ofs, Address limit,
1111 bool multi_block);
1112
1113 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1114 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1115 Register buf, Register state, Register ofs, Register limit, Register rsp,
1116 bool multi_block);
1117
1118 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1119 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1120 Register buf, Register state, Register ofs, Register limit, Register rsp,
1121 bool multi_block, XMMRegister shuf_mask);
1122
1123 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1124 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1125 Register rax, Register rcx, Register rdx, Register tmp);
1126
1127 private:
1128
1129 // these are private because users should be doing movflt/movdbl
1130
1131 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1132 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1133 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1134 void movss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1135
1136 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1137 void movlpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1138
1139 public:
1140
1141 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1142 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1143 void addsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1144
1145 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1146 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1147 void addss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1148
1149 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1150 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1151 void addpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1152
1153 using Assembler::vbroadcasti128;
1154 void vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1155
1156 using Assembler::vbroadcastsd;
1157 void vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1158
1159 using Assembler::vbroadcastss;
1160 void vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1161
1162 // Vector float blend
1163 void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg);
1164 void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg);
1165
1166 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1167 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1168 void divsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1169
1170 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1171 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1172 void divss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1173
1174 // Move Unaligned Double Quadword
1175 void movdqu(Address dst, XMMRegister src);
1176 void movdqu(XMMRegister dst, XMMRegister src);
1177 void movdqu(XMMRegister dst, Address src);
1178 void movdqu(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1179
1180 void kmovwl(Register dst, KRegister src) { Assembler::kmovwl(dst, src); }
1181 void kmovwl(Address dst, KRegister src) { Assembler::kmovwl(dst, src); }
1182 void kmovwl(KRegister dst, KRegister src) { Assembler::kmovwl(dst, src); }
1183 void kmovwl(KRegister dst, Register src) { Assembler::kmovwl(dst, src); }
1184 void kmovwl(KRegister dst, Address src) { Assembler::kmovwl(dst, src); }
1185 void kmovwl(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1186
1187 void kmovql(KRegister dst, KRegister src) { Assembler::kmovql(dst, src); }
1188 void kmovql(KRegister dst, Register src) { Assembler::kmovql(dst, src); }
1189 void kmovql(Register dst, KRegister src) { Assembler::kmovql(dst, src); }
1190 void kmovql(KRegister dst, Address src) { Assembler::kmovql(dst, src); }
1191 void kmovql(Address dst, KRegister src) { Assembler::kmovql(dst, src); }
1192 void kmovql(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1193
1194 // Safe move operation, lowers down to 16bit moves for targets supporting
1195 // AVX512F feature and 64bit moves for targets supporting AVX512BW feature.
1196 void kmov(Address dst, KRegister src);
1197 void kmov(KRegister dst, Address src);
1198 void kmov(KRegister dst, KRegister src);
1199 void kmov(Register dst, KRegister src);
1200 void kmov(KRegister dst, Register src);
1201
1202 using Assembler::movddup;
1203 void movddup(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1204
1205 using Assembler::vmovddup;
1206 void vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1207
1208 // AVX Unaligned forms
1209 void vmovdqu(Address dst, XMMRegister src);
1210 void vmovdqu(XMMRegister dst, Address src);
1211 void vmovdqu(XMMRegister dst, XMMRegister src);
1212 void vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1213 void vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1214 void vmovdqu(XMMRegister dst, XMMRegister src, int vector_len);
1215 void vmovdqu(XMMRegister dst, Address src, int vector_len);
1216 void vmovdqu(Address dst, XMMRegister src, int vector_len);
1217
1218 // AVX Aligned forms
1219 using Assembler::vmovdqa;
1220 void vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1221 void vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1222 void vmovdqa(XMMRegister dst, Address src, int vector_len);
1223 void vmovdqa(Address dst, XMMRegister src, int vector_len);
1224
1225 // AVX512 Unaligned
1226 void evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len);
1227 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len);
1228 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len);
1229
1230 void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1231 void evmovdqub(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1232
1233 void evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1234 if (dst->encoding() != src->encoding() || mask != k0) {
1235 Assembler::evmovdqub(dst, mask, src, merge, vector_len);
1236 }
1237 }
1238 void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1239 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1240 void evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1241
1242 void evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1243 void evmovdquw(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1244 void evmovdquw(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1245
1246 void evmovdquw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1247 if (dst->encoding() != src->encoding() || mask != k0) {
1248 Assembler::evmovdquw(dst, mask, src, merge, vector_len);
1249 }
1250 }
1251 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1252 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1253 void evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1254
1255 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
1256 if (dst->encoding() != src->encoding()) {
1257 Assembler::evmovdqul(dst, src, vector_len);
1258 }
1259 }
1260 void evmovdqul(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1261 void evmovdqul(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1262
1263 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1264 if (dst->encoding() != src->encoding() || mask != k0) {
1265 Assembler::evmovdqul(dst, mask, src, merge, vector_len);
1266 }
1267 }
1268 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1269 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1270 void evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1271
1272 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
1273 if (dst->encoding() != src->encoding()) {
1274 Assembler::evmovdquq(dst, src, vector_len);
1275 }
1276 }
1277 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1278 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1279 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1280 void evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1281
1282 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1283 if (dst->encoding() != src->encoding() || mask != k0) {
1284 Assembler::evmovdquq(dst, mask, src, merge, vector_len);
1285 }
1286 }
1287 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1288 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1289 void evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1290 void evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1291
1292 using Assembler::movapd;
1293 void movapd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1294
1295 // Move Aligned Double Quadword
1296 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1297 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1298 void movdqa(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1299
1300 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1301 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1302 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1303 void movsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1304
1305 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1306 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1307 void mulpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1308
1309 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1310 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1311 void mulsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1312
1313 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1314 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1315 void mulss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1316
1317 // Carry-Less Multiplication Quadword
1318 void pclmulldq(XMMRegister dst, XMMRegister src) {
1319 // 0x00 - multiply lower 64 bits [0:63]
1320 Assembler::pclmulqdq(dst, src, 0x00);
1321 }
1322 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1323 // 0x11 - multiply upper 64 bits [64:127]
1324 Assembler::pclmulqdq(dst, src, 0x11);
1325 }
1326
1327 void pcmpeqb(XMMRegister dst, XMMRegister src);
1328 void pcmpeqw(XMMRegister dst, XMMRegister src);
1329
1330 void pcmpestri(XMMRegister dst, Address src, int imm8);
1331 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1332
1333 void pmovzxbw(XMMRegister dst, XMMRegister src);
1334 void pmovzxbw(XMMRegister dst, Address src);
1335
1336 void pmovmskb(Register dst, XMMRegister src);
1337
1338 void ptest(XMMRegister dst, XMMRegister src);
1339
1340 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1341 void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1342 void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch = noreg);
1343
1344 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1345 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1346 void sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1347
1348 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1349 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1350 void subsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1351
1352 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1353 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1354 void subss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1355
1356 void evucomish(XMMRegister dst, XMMRegister src) { Assembler::evucomish(dst, src); }
1357 void evucomish(XMMRegister dst, Address src) { Assembler::evucomish(dst, src); }
1358 void evucomish(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1359
1360 void evucomxsh(XMMRegister dst, XMMRegister src) { Assembler::evucomxsh(dst, src); }
1361 void evucomxsh(XMMRegister dst, Address src) { Assembler::evucomxsh(dst, src); }
1362 void evucomxsh(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1363
1364 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1365 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1366 void ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1367
1368 void evucomxss(XMMRegister dst, XMMRegister src) { Assembler::evucomxss(dst, src); }
1369 void evucomxss(XMMRegister dst, Address src) { Assembler::evucomxss(dst, src); }
1370 void evucomxss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1371
1372 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1373 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1374 void ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1375
1376 void evucomxsd(XMMRegister dst, XMMRegister src) { Assembler::evucomxsd(dst, src); }
1377 void evucomxsd(XMMRegister dst, Address src) { Assembler::evucomxsd(dst, src); }
1378 void evucomxsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1379
1380 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1381 void xorpd(XMMRegister dst, XMMRegister src);
1382 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1383 void xorpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1384
1385 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1386 void xorps(XMMRegister dst, XMMRegister src);
1387 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1388 void xorps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1389
1390 // Shuffle Bytes
1391 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1392 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1393 void pshufb(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1394 // AVX 3-operands instructions
1395
1396 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1397 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1398 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1399
1400 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1401 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1402 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1403
1404 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1405 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1406
1407 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1408 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1409 void vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1410
1411 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1412 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1413
1414 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1415 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1416 void vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1417
1418 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1419 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1420 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1421
1422 using Assembler::vpbroadcastd;
1423 void vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1424
1425 using Assembler::vpbroadcastq;
1426 void vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1427
1428 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1429 void vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len);
1430
1431 void vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1432 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1433 using Assembler::evpcmpeqd;
1434 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1435
1436 // Vector compares
1437 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1438 Assembler::evpcmpd(kdst, mask, nds, src, comparison, is_signed, vector_len);
1439 }
1440 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1441
1442 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1443 Assembler::evpcmpq(kdst, mask, nds, src, comparison, is_signed, vector_len);
1444 }
1445 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1446
1447 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1448 Assembler::evpcmpb(kdst, mask, nds, src, comparison, is_signed, vector_len);
1449 }
1450 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1451
1452 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1453 Assembler::evpcmpw(kdst, mask, nds, src, comparison, is_signed, vector_len);
1454 }
1455 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1456
1457 void evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len);
1458
1459 // Emit comparison instruction for the specified comparison predicate.
1460 void vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len);
1461 void vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len);
1462
1463 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1464 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1465
1466 void vpmovmskb(Register dst, XMMRegister src, int vector_len = Assembler::AVX_256bit);
1467
1468 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1469 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1470
1471 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1472 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1473 void vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1474
1475 void vpmuldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpmuldq(dst, nds, src, vector_len); }
1476
1477 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1478 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1479
1480 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1481 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1482
1483 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1484 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1485
1486 void evpsrad(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1487 void evpsrad(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1488
1489 void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1490 void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1491
1492 using Assembler::evpsllw;
1493 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1494 if (!is_varshift) {
1495 Assembler::evpsllw(dst, mask, nds, src, merge, vector_len);
1496 } else {
1497 Assembler::evpsllvw(dst, mask, nds, src, merge, vector_len);
1498 }
1499 }
1500 void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1501 if (!is_varshift) {
1502 Assembler::evpslld(dst, mask, nds, src, merge, vector_len);
1503 } else {
1504 Assembler::evpsllvd(dst, mask, nds, src, merge, vector_len);
1505 }
1506 }
1507 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1508 if (!is_varshift) {
1509 Assembler::evpsllq(dst, mask, nds, src, merge, vector_len);
1510 } else {
1511 Assembler::evpsllvq(dst, mask, nds, src, merge, vector_len);
1512 }
1513 }
1514 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1515 if (!is_varshift) {
1516 Assembler::evpsrlw(dst, mask, nds, src, merge, vector_len);
1517 } else {
1518 Assembler::evpsrlvw(dst, mask, nds, src, merge, vector_len);
1519 }
1520 }
1521 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1522 if (!is_varshift) {
1523 Assembler::evpsrld(dst, mask, nds, src, merge, vector_len);
1524 } else {
1525 Assembler::evpsrlvd(dst, mask, nds, src, merge, vector_len);
1526 }
1527 }
1528
1529 using Assembler::evpsrlq;
1530 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1531 if (!is_varshift) {
1532 Assembler::evpsrlq(dst, mask, nds, src, merge, vector_len);
1533 } else {
1534 Assembler::evpsrlvq(dst, mask, nds, src, merge, vector_len);
1535 }
1536 }
1537 using Assembler::evpsraw;
1538 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1539 if (!is_varshift) {
1540 Assembler::evpsraw(dst, mask, nds, src, merge, vector_len);
1541 } else {
1542 Assembler::evpsravw(dst, mask, nds, src, merge, vector_len);
1543 }
1544 }
1545 using Assembler::evpsrad;
1546 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1547 if (!is_varshift) {
1548 Assembler::evpsrad(dst, mask, nds, src, merge, vector_len);
1549 } else {
1550 Assembler::evpsravd(dst, mask, nds, src, merge, vector_len);
1551 }
1552 }
1553 using Assembler::evpsraq;
1554 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1555 if (!is_varshift) {
1556 Assembler::evpsraq(dst, mask, nds, src, merge, vector_len);
1557 } else {
1558 Assembler::evpsravq(dst, mask, nds, src, merge, vector_len);
1559 }
1560 }
1561
1562 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1563 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1564 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1565 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1566
1567 void evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1568 void evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1569 void evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1570 void evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1571
1572 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1573 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1574
1575 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1576 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1577
1578 void vptest(XMMRegister dst, XMMRegister src);
1579 void vptest(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vptest(dst, src, vector_len); }
1580
1581 void punpcklbw(XMMRegister dst, XMMRegister src);
1582 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1583
1584 void pshufd(XMMRegister dst, Address src, int mode);
1585 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1586
1587 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1588 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1589
1590 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1591 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1592 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1593
1594 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1595 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1596 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1597
1598 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1599
1600 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1601 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1602 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1603
1604 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1605 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1606 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1607
1608 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1609 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1610 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1611
1612 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1613 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1614 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1615
1616 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1617 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1618 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1619
1620 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1621 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1622 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1623
1624 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1625 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1626
1627 // AVX Vector instructions
1628
1629 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1630 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1631 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1632
1633 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1634 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1635 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1636
1637 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1638 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1639 Assembler::vpxor(dst, nds, src, vector_len);
1640 else
1641 Assembler::vxorpd(dst, nds, src, vector_len);
1642 }
1643 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1644 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1645 Assembler::vpxor(dst, nds, src, vector_len);
1646 else
1647 Assembler::vxorpd(dst, nds, src, vector_len);
1648 }
1649 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1650
1651 // Simple version for AVX2 256bit vectors
1652 void vpxor(XMMRegister dst, XMMRegister src) {
1653 assert(UseAVX >= 2, "Should be at least AVX2");
1654 Assembler::vpxor(dst, dst, src, AVX_256bit);
1655 }
1656 void vpxor(XMMRegister dst, Address src) {
1657 assert(UseAVX >= 2, "Should be at least AVX2");
1658 Assembler::vpxor(dst, dst, src, AVX_256bit);
1659 }
1660
1661 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpermd(dst, nds, src, vector_len); }
1662 void vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1663
1664 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1665 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1666 Assembler::vinserti32x4(dst, nds, src, imm8);
1667 } else if (UseAVX > 1) {
1668 // vinserti128 is available only in AVX2
1669 Assembler::vinserti128(dst, nds, src, imm8);
1670 } else {
1671 Assembler::vinsertf128(dst, nds, src, imm8);
1672 }
1673 }
1674
1675 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1676 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1677 Assembler::vinserti32x4(dst, nds, src, imm8);
1678 } else if (UseAVX > 1) {
1679 // vinserti128 is available only in AVX2
1680 Assembler::vinserti128(dst, nds, src, imm8);
1681 } else {
1682 Assembler::vinsertf128(dst, nds, src, imm8);
1683 }
1684 }
1685
1686 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1687 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1688 Assembler::vextracti32x4(dst, src, imm8);
1689 } else if (UseAVX > 1) {
1690 // vextracti128 is available only in AVX2
1691 Assembler::vextracti128(dst, src, imm8);
1692 } else {
1693 Assembler::vextractf128(dst, src, imm8);
1694 }
1695 }
1696
1697 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1698 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1699 Assembler::vextracti32x4(dst, src, imm8);
1700 } else if (UseAVX > 1) {
1701 // vextracti128 is available only in AVX2
1702 Assembler::vextracti128(dst, src, imm8);
1703 } else {
1704 Assembler::vextractf128(dst, src, imm8);
1705 }
1706 }
1707
1708 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1709 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1710 vinserti128(dst, dst, src, 1);
1711 }
1712 void vinserti128_high(XMMRegister dst, Address src) {
1713 vinserti128(dst, dst, src, 1);
1714 }
1715 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1716 vextracti128(dst, src, 1);
1717 }
1718 void vextracti128_high(Address dst, XMMRegister src) {
1719 vextracti128(dst, src, 1);
1720 }
1721
1722 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1723 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1724 Assembler::vinsertf32x4(dst, dst, src, 1);
1725 } else {
1726 Assembler::vinsertf128(dst, dst, src, 1);
1727 }
1728 }
1729
1730 void vinsertf128_high(XMMRegister dst, Address src) {
1731 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1732 Assembler::vinsertf32x4(dst, dst, src, 1);
1733 } else {
1734 Assembler::vinsertf128(dst, dst, src, 1);
1735 }
1736 }
1737
1738 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1739 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1740 Assembler::vextractf32x4(dst, src, 1);
1741 } else {
1742 Assembler::vextractf128(dst, src, 1);
1743 }
1744 }
1745
1746 void vextractf128_high(Address dst, XMMRegister src) {
1747 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1748 Assembler::vextractf32x4(dst, src, 1);
1749 } else {
1750 Assembler::vextractf128(dst, src, 1);
1751 }
1752 }
1753
1754 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1755 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1756 Assembler::vinserti64x4(dst, dst, src, 1);
1757 }
1758 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1759 Assembler::vinsertf64x4(dst, dst, src, 1);
1760 }
1761 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1762 Assembler::vextracti64x4(dst, src, 1);
1763 }
1764 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1765 Assembler::vextractf64x4(dst, src, 1);
1766 }
1767 void vextractf64x4_high(Address dst, XMMRegister src) {
1768 Assembler::vextractf64x4(dst, src, 1);
1769 }
1770 void vinsertf64x4_high(XMMRegister dst, Address src) {
1771 Assembler::vinsertf64x4(dst, dst, src, 1);
1772 }
1773
1774 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1775 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1776 vinserti128(dst, dst, src, 0);
1777 }
1778 void vinserti128_low(XMMRegister dst, Address src) {
1779 vinserti128(dst, dst, src, 0);
1780 }
1781 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1782 vextracti128(dst, src, 0);
1783 }
1784 void vextracti128_low(Address dst, XMMRegister src) {
1785 vextracti128(dst, src, 0);
1786 }
1787
1788 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1789 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1790 Assembler::vinsertf32x4(dst, dst, src, 0);
1791 } else {
1792 Assembler::vinsertf128(dst, dst, src, 0);
1793 }
1794 }
1795
1796 void vinsertf128_low(XMMRegister dst, Address src) {
1797 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1798 Assembler::vinsertf32x4(dst, dst, src, 0);
1799 } else {
1800 Assembler::vinsertf128(dst, dst, src, 0);
1801 }
1802 }
1803
1804 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1805 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1806 Assembler::vextractf32x4(dst, src, 0);
1807 } else {
1808 Assembler::vextractf128(dst, src, 0);
1809 }
1810 }
1811
1812 void vextractf128_low(Address dst, XMMRegister src) {
1813 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1814 Assembler::vextractf32x4(dst, src, 0);
1815 } else {
1816 Assembler::vextractf128(dst, src, 0);
1817 }
1818 }
1819
1820 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1821 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1822 Assembler::vinserti64x4(dst, dst, src, 0);
1823 }
1824 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1825 Assembler::vinsertf64x4(dst, dst, src, 0);
1826 }
1827 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1828 Assembler::vextracti64x4(dst, src, 0);
1829 }
1830 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1831 Assembler::vextractf64x4(dst, src, 0);
1832 }
1833 void vextractf64x4_low(Address dst, XMMRegister src) {
1834 Assembler::vextractf64x4(dst, src, 0);
1835 }
1836 void vinsertf64x4_low(XMMRegister dst, Address src) {
1837 Assembler::vinsertf64x4(dst, dst, src, 0);
1838 }
1839
1840 // Carry-Less Multiplication Quadword
1841 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1842 // 0x00 - multiply lower 64 bits [0:63]
1843 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1844 }
1845 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1846 // 0x11 - multiply upper 64 bits [64:127]
1847 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1848 }
1849 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1850 // 0x10 - multiply nds[0:63] and src[64:127]
1851 Assembler::vpclmulqdq(dst, nds, src, 0x10);
1852 }
1853 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1854 //0x01 - multiply nds[64:127] and src[0:63]
1855 Assembler::vpclmulqdq(dst, nds, src, 0x01);
1856 }
1857
1858 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1859 // 0x00 - multiply lower 64 bits [0:63]
1860 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1861 }
1862 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1863 // 0x11 - multiply upper 64 bits [64:127]
1864 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1865 }
1866
1867 // AVX-512 mask operations.
1868 void kand(BasicType etype, KRegister dst, KRegister src1, KRegister src2);
1869 void kor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1870 void knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp = knoreg, Register rtmp = noreg);
1871 void kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1872 void kortest(uint masklen, KRegister src1, KRegister src2);
1873 void ktest(uint masklen, KRegister src1, KRegister src2);
1874
1875 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1876 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1877
1878 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1879 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1880
1881 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1882 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1883
1884 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1885 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1886
1887 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1888 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1889 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1890 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1891
1892 using Assembler::evpandq;
1893 void evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1894
1895 using Assembler::evpaddq;
1896 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1897
1898 using Assembler::evporq;
1899 void evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1900
1901 using Assembler::vpshufb;
1902 void vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1903
1904 using Assembler::vpor;
1905 void vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1906
1907 using Assembler::vpternlogq;
1908 void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch = noreg);
1909
1910 void cmov32( Condition cc, Register dst, Address src);
1911 void cmov32( Condition cc, Register dst, Register src);
1912
1913 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1914
1915 void cmovptr(Condition cc, Register dst, Address src) { cmovq(cc, dst, src); }
1916 void cmovptr(Condition cc, Register dst, Register src) { cmovq(cc, dst, src); }
1917
1918 void movoop(Register dst, jobject obj);
1919 void movoop(Address dst, jobject obj, Register rscratch);
1920
1921 void mov_metadata(Register dst, Metadata* obj);
1922 void mov_metadata(Address dst, Metadata* obj, Register rscratch);
1923
1924 void mov64(Register dst, int64_t imm64);
1925 void mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format);
1926
1927 void movptr(Register dst, Register src);
1928 void movptr(Register dst, Address src);
1929 void movptr(Register dst, AddressLiteral src);
1930 void movptr(Register dst, ArrayAddress src);
1931 void movptr(Register dst, intptr_t src);
1932 void movptr(Address dst, Register src);
1933 void movptr(Address dst, int32_t imm);
1934 void movptr(Address dst, intptr_t src, Register rscratch);
1935 void movptr(ArrayAddress dst, Register src, Register rscratch);
1936
1937 void movptr(Register dst, RegisterOrConstant src) {
1938 if (src.is_constant()) movptr(dst, src.as_constant());
1939 else movptr(dst, src.as_register());
1940 }
1941
1942
1943 // to avoid hiding movl
1944 void mov32(Register dst, AddressLiteral src);
1945 void mov32(AddressLiteral dst, Register src, Register rscratch = noreg);
1946
1947 // Import other mov() methods from the parent class or else
1948 // they will be hidden by the following overriding declaration.
1949 using Assembler::movdl;
1950 void movdl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1951
1952 using Assembler::movq;
1953 void movq(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1954
1955 // Can push value or effective address
1956 void pushptr(AddressLiteral src, Register rscratch);
1957
1958 void pushptr(Address src) { pushq(src); }
1959 void popptr(Address src) { popq(src); }
1960
1961 void pushoop(jobject obj, Register rscratch);
1962 void pushklass(Metadata* obj, Register rscratch);
1963
1964 // sign extend as need a l to ptr sized element
1965 void movl2ptr(Register dst, Address src) { movslq(dst, src); }
1966 void movl2ptr(Register dst, Register src) { movslq(dst, src); }
1967
1968
1969 public:
1970 // Inline type specific methods
1971 #include "asm/macroAssembler_common.hpp"
1972
1973 // clear memory of size 'cnt' qwords, starting at 'base';
1974 // if 'is_large' is set, do not try to produce short loop
1975 void clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only, KRegister mask=knoreg);
1976
1977 // clear memory initialization sequence for constant size;
1978 void clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1979
1980 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1981 void xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1982
1983 // Fill primitive arrays
1984 void generate_fill(BasicType t, bool aligned,
1985 Register to, Register value, Register count,
1986 Register rtmp, XMMRegister xtmp);
1987
1988 void encode_iso_array(Register src, Register dst, Register len,
1989 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1990 XMMRegister tmp4, Register tmp5, Register result, bool ascii);
1991
1992 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1993 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1994 Register y, Register y_idx, Register z,
1995 Register carry, Register product,
1996 Register idx, Register kdx);
1997 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1998 Register yz_idx, Register idx,
1999 Register carry, Register product, int offset);
2000 void multiply_128_x_128_bmi2_loop(Register y, Register z,
2001 Register carry, Register carry2,
2002 Register idx, Register jdx,
2003 Register yz_idx1, Register yz_idx2,
2004 Register tmp, Register tmp3, Register tmp4);
2005 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
2006 Register yz_idx, Register idx, Register jdx,
2007 Register carry, Register product,
2008 Register carry2);
2009 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
2010 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
2011 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
2012 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
2013 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
2014 Register tmp2);
2015 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
2016 Register rdxReg, Register raxReg);
2017 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
2018 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
2019 Register tmp3, Register tmp4);
2020 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
2021 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
2022
2023 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
2024 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
2025 Register raxReg);
2026 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
2027 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
2028 Register raxReg);
2029 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
2030 Register result, Register tmp1, Register tmp2,
2031 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
2032
2033 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
2034 void update_byte_crc32(Register crc, Register val, Register table);
2035 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
2036
2037 void kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2);
2038 void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
2039 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
2040 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup);
2041
2042 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
2043 // Note on a naming convention:
2044 // Prefix w = register only used on a Westmere+ architecture
2045 // Prefix n = register only used on a Nehalem architecture
2046 void crc32c_ipl_alg4(Register in_out, uint32_t n,
2047 Register tmp1, Register tmp2, Register tmp3);
2048 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
2049 Register in_out,
2050 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
2051 XMMRegister w_xtmp2,
2052 Register tmp1,
2053 Register n_tmp2, Register n_tmp3);
2054 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
2055 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2056 Register tmp1, Register tmp2,
2057 Register n_tmp3);
2058 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
2059 Register in_out1, Register in_out2, Register in_out3,
2060 Register tmp1, Register tmp2, Register tmp3,
2061 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2062 Register tmp4, Register tmp5,
2063 Register n_tmp6);
2064 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
2065 Register tmp1, Register tmp2, Register tmp3,
2066 Register tmp4, Register tmp5, Register tmp6,
2067 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2068 bool is_pclmulqdq_supported);
2069 // Fold 128-bit data chunk
2070 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
2071 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
2072 // Fold 512-bit data chunk
2073 void fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, Register pos, int offset);
2074 // Fold 8-bit data
2075 void fold_8bit_crc32(Register crc, Register table, Register tmp);
2076 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
2077
2078 // Compress char[] array to byte[].
2079 void char_array_compress(Register src, Register dst, Register len,
2080 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
2081 XMMRegister tmp4, Register tmp5, Register result,
2082 KRegister mask1 = knoreg, KRegister mask2 = knoreg);
2083
2084 // Inflate byte[] array to char[].
2085 void byte_array_inflate(Register src, Register dst, Register len,
2086 XMMRegister tmp1, Register tmp2, KRegister mask = knoreg);
2087
2088 void fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
2089 Register length, Register temp, int vec_enc);
2090
2091 void fill64_masked(uint shift, Register dst, int disp,
2092 XMMRegister xmm, KRegister mask, Register length,
2093 Register temp, bool use64byteVector = false);
2094
2095 void fill32_masked(uint shift, Register dst, int disp,
2096 XMMRegister xmm, KRegister mask, Register length,
2097 Register temp);
2098
2099 void fill32(Address dst, XMMRegister xmm);
2100
2101 void fill32(Register dst, int disp, XMMRegister xmm);
2102
2103 void fill64(Address dst, XMMRegister xmm, bool use64byteVector = false);
2104
2105 void fill64(Register dst, int dis, XMMRegister xmm, bool use64byteVector = false);
2106
2107 void convert_f2i(Register dst, XMMRegister src);
2108 void convert_d2i(Register dst, XMMRegister src);
2109 void convert_f2l(Register dst, XMMRegister src);
2110 void convert_d2l(Register dst, XMMRegister src);
2111 void round_double(Register dst, XMMRegister src, Register rtmp, Register rcx);
2112 void round_float(Register dst, XMMRegister src, Register rtmp, Register rcx);
2113
2114 void cache_wb(Address line);
2115 void cache_wbsync(bool is_pre);
2116
2117 #ifdef COMPILER2
2118 void generate_fill_avx3(BasicType type, Register to, Register value,
2119 Register count, Register rtmp, XMMRegister xtmp);
2120 #endif // COMPILER2
2121
2122 void vallones(XMMRegister dst, int vector_len);
2123
2124 void check_stack_alignment(Register sp, const char* msg, unsigned bias = 0, Register tmp = noreg);
2125
2126 void fast_lock(Register basic_lock, Register obj, Register reg_rax, Register tmp, Label& slow);
2127 void fast_unlock(Register obj, Register reg_rax, Register tmp, Label& slow);
2128
2129 void save_legacy_gprs();
2130 void restore_legacy_gprs();
2131 void load_aotrc_address(Register reg, address a);
2132 void setcc(Assembler::Condition comparison, Register dst);
2133 };
2134
2135 #endif // CPU_X86_MACROASSEMBLER_X86_HPP