1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "asm/register.hpp"
30 #include "code/vmreg.inline.hpp"
31 #include "compiler/oopMap.hpp"
32 #include "utilities/macros.hpp"
33 #include "runtime/signature.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/checkedCast.hpp"
36
37 class ciInlineKlass;
38
39 // MacroAssembler extends Assembler by frequently used macros.
40 //
41 // Instructions for which a 'better' code sequence exists depending
42 // on arguments should also go in here.
43
44 class MacroAssembler: public Assembler {
45 friend class LIR_Assembler;
46 friend class Runtime1; // as_Address()
47
48 public:
49 // Support for VM calls
50 //
51 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
52 // may customize this version by overriding it for its purposes (e.g., to save/restore
53 // additional registers when doing a VM call).
54
55 virtual void call_VM_leaf_base(
56 address entry_point, // the entry point
57 int number_of_arguments // the number of arguments to pop after the call
58 );
59
60 protected:
61 // This is the base routine called by the different versions of call_VM. The interpreter
62 // may customize this version by overriding it for its purposes (e.g., to save/restore
63 // additional registers when doing a VM call).
64 //
65 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
66 // returns the register which contains the thread upon return. If a thread register has been
67 // specified, the return value will correspond to that register. If no last_java_sp is specified
68 // (noreg) than rsp will be used instead.
69 virtual void call_VM_base( // returns the register containing the thread upon return
70 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
71 Register java_thread, // the thread if computed before ; use noreg otherwise
72 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
73 address entry_point, // the entry point
74 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
75 bool check_exceptions // whether to check for pending exceptions after return
76 );
77
78 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
79
80 // helpers for FPU flag access
81 // tmp is a temporary register, if none is available use noreg
82 void save_rax (Register tmp);
83 void restore_rax(Register tmp);
84
85 public:
86 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
87
88 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
89 // The implementation is only non-empty for the InterpreterMacroAssembler,
90 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
91 virtual void check_and_handle_popframe(Register java_thread);
92 virtual void check_and_handle_earlyret(Register java_thread);
93
94 Address as_Address(AddressLiteral adr);
95 Address as_Address(ArrayAddress adr, Register rscratch);
96
97 // Support for null-checks
98 //
99 // Generates code that causes a null OS exception if the content of reg is null.
100 // If the accessed location is M[reg + offset] and the offset is known, provide the
101 // offset. No explicit code generation is needed if the offset is within a certain
102 // range (0 <= offset <= page_size).
103
104 void null_check(Register reg, int offset = -1);
105 static bool needs_explicit_null_check(intptr_t offset);
106 static bool uses_implicit_null_check(void* address);
107
108 // markWord tests, kills markWord reg
109 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
110
111 // inlineKlass queries, kills temp_reg
112 void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type);
113 void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type);
114 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type);
115
116 // Get the default value oop for the given InlineKlass
117 void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj);
118 // The empty value oop, for the given InlineKlass ("empty" as in no instance fields)
119 // get_default_value_oop with extra assertion for empty inline klass
120 void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj);
121
122 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
123 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
124 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
125 void test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker);
126
127 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
128 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
129 void test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array);
130 void test_non_flat_array_oop(Register oop, Register temp_reg, Label& is_non_flat_array);
131 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
132 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label& is_non_null_free_array);
133
134 // Check array klass layout helper for flat or null-free arrays...
135 void test_flat_array_layout(Register lh, Label& is_flat_array);
136 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array);
137
138 // Required platform-specific helpers for Label::patch_instructions.
139 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
140 void pd_patch_instruction(address branch, address target, const char* file, int line) {
141 unsigned char op = branch[0];
142 assert(op == 0xE8 /* call */ ||
143 op == 0xE9 /* jmp */ ||
144 op == 0xEB /* short jmp */ ||
145 (op & 0xF0) == 0x70 /* short jcc */ ||
146 (op == 0x0F && (branch[1] & 0xF0) == 0x80) /* jcc */ ||
147 (op == 0xC7 && branch[1] == 0xF8) /* xbegin */,
148 "Invalid opcode at patch point");
149
150 if (op == 0xEB || (op & 0xF0) == 0x70) {
151 // short offset operators (jmp and jcc)
152 char* disp = (char*) &branch[1];
153 int imm8 = checked_cast<int>(target - (address) &disp[1]);
154 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
155 file == nullptr ? "<null>" : file, line);
156 *disp = (char)imm8;
157 } else {
158 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
159 int imm32 = checked_cast<int>(target - (address) &disp[1]);
160 *disp = imm32;
161 }
162 }
163
164 // The following 4 methods return the offset of the appropriate move instruction
165
166 // Support for fast byte/short loading with zero extension (depending on particular CPU)
167 int load_unsigned_byte(Register dst, Address src);
168 int load_unsigned_short(Register dst, Address src);
169
170 // Support for fast byte/short loading with sign extension (depending on particular CPU)
171 int load_signed_byte(Register dst, Address src);
172 int load_signed_short(Register dst, Address src);
173
174 // Support for sign-extension (hi:lo = extend_sign(lo))
175 void extend_sign(Register hi, Register lo);
176
177 // Load and store values by size and signed-ness
178 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
179 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
180
181 // Support for inc/dec with optimal instruction selection depending on value
182
183 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
184 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
185 void increment(Address dst, int value = 1) { LP64_ONLY(incrementq(dst, value)) NOT_LP64(incrementl(dst, value)) ; }
186 void decrement(Address dst, int value = 1) { LP64_ONLY(decrementq(dst, value)) NOT_LP64(decrementl(dst, value)) ; }
187
188 void decrementl(Address dst, int value = 1);
189 void decrementl(Register reg, int value = 1);
190
191 void decrementq(Register reg, int value = 1);
192 void decrementq(Address dst, int value = 1);
193
194 void incrementl(Address dst, int value = 1);
195 void incrementl(Register reg, int value = 1);
196
197 void incrementq(Register reg, int value = 1);
198 void incrementq(Address dst, int value = 1);
199
200 void incrementl(AddressLiteral dst, Register rscratch = noreg);
201 void incrementl(ArrayAddress dst, Register rscratch);
202
203 void incrementq(AddressLiteral dst, Register rscratch = noreg);
204
205 // Support optimal SSE move instructions.
206 void movflt(XMMRegister dst, XMMRegister src) {
207 if (dst-> encoding() == src->encoding()) return;
208 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
209 else { movss (dst, src); return; }
210 }
211 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
212 void movflt(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
213 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
214
215 // Move with zero extension
216 void movfltz(XMMRegister dst, XMMRegister src) { movss(dst, src); }
217
218 void movdbl(XMMRegister dst, XMMRegister src) {
219 if (dst-> encoding() == src->encoding()) return;
220 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
221 else { movsd (dst, src); return; }
222 }
223
224 void movdbl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
225
226 void movdbl(XMMRegister dst, Address src) {
227 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
228 else { movlpd(dst, src); return; }
229 }
230 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
231
232 void flt_to_flt16(Register dst, XMMRegister src, XMMRegister tmp) {
233 // Use separate tmp XMM register because caller may
234 // requires src XMM register to be unchanged (as in x86.ad).
235 vcvtps2ph(tmp, src, 0x04, Assembler::AVX_128bit);
236 movdl(dst, tmp);
237 movswl(dst, dst);
238 }
239
240 void flt16_to_flt(XMMRegister dst, Register src) {
241 movdl(dst, src);
242 vcvtph2ps(dst, dst, Assembler::AVX_128bit);
243 }
244
245 // Alignment
246 void align32();
247 void align64();
248 void align(uint modulus);
249 void align(uint modulus, uint target);
250
251 void post_call_nop();
252 // A 5 byte nop that is safe for patching (see patch_verified_entry)
253 void fat_nop();
254
255 // Stack frame creation/removal
256 void enter();
257 void leave();
258
259 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
260 // The pointer will be loaded into the thread register.
261 void get_thread(Register thread);
262
263 #ifdef _LP64
264 // Support for argument shuffling
265
266 // bias in bytes
267 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
268 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
269 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
270 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
271 void move_ptr(VMRegPair src, VMRegPair dst);
272 void object_move(OopMap* map,
273 int oop_handle_offset,
274 int framesize_in_slots,
275 VMRegPair src,
276 VMRegPair dst,
277 bool is_receiver,
278 int* receiver_offset);
279 #endif // _LP64
280
281 // Support for VM calls
282 //
283 // It is imperative that all calls into the VM are handled via the call_VM macros.
284 // They make sure that the stack linkage is setup correctly. call_VM's correspond
285 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
286
287
288 void call_VM(Register oop_result,
289 address entry_point,
290 bool check_exceptions = true);
291 void call_VM(Register oop_result,
292 address entry_point,
293 Register arg_1,
294 bool check_exceptions = true);
295 void call_VM(Register oop_result,
296 address entry_point,
297 Register arg_1, Register arg_2,
298 bool check_exceptions = true);
299 void call_VM(Register oop_result,
300 address entry_point,
301 Register arg_1, Register arg_2, Register arg_3,
302 bool check_exceptions = true);
303
304 // Overloadings with last_Java_sp
305 void call_VM(Register oop_result,
306 Register last_java_sp,
307 address entry_point,
308 int number_of_arguments = 0,
309 bool check_exceptions = true);
310 void call_VM(Register oop_result,
311 Register last_java_sp,
312 address entry_point,
313 Register arg_1, bool
314 check_exceptions = true);
315 void call_VM(Register oop_result,
316 Register last_java_sp,
317 address entry_point,
318 Register arg_1, Register arg_2,
319 bool check_exceptions = true);
320 void call_VM(Register oop_result,
321 Register last_java_sp,
322 address entry_point,
323 Register arg_1, Register arg_2, Register arg_3,
324 bool check_exceptions = true);
325
326 void get_vm_result (Register oop_result, Register thread);
327 void get_vm_result_2(Register metadata_result, Register thread);
328
329 // These always tightly bind to MacroAssembler::call_VM_base
330 // bypassing the virtual implementation
331 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
332 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
333 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
334 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
335 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
336
337 void call_VM_leaf0(address entry_point);
338 void call_VM_leaf(address entry_point,
339 int number_of_arguments = 0);
340 void call_VM_leaf(address entry_point,
341 Register arg_1);
342 void call_VM_leaf(address entry_point,
343 Register arg_1, Register arg_2);
344 void call_VM_leaf(address entry_point,
345 Register arg_1, Register arg_2, Register arg_3);
346
347 void call_VM_leaf(address entry_point,
348 Register arg_1, Register arg_2, Register arg_3, Register arg_4);
349
350 // These always tightly bind to MacroAssembler::call_VM_leaf_base
351 // bypassing the virtual implementation
352 void super_call_VM_leaf(address entry_point);
353 void super_call_VM_leaf(address entry_point, Register arg_1);
354 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
355 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
356 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
357
358 // last Java Frame (fills frame anchor)
359 void set_last_Java_frame(Register thread,
360 Register last_java_sp,
361 Register last_java_fp,
362 address last_java_pc,
363 Register rscratch);
364
365 // thread in the default location (r15_thread on 64bit)
366 void set_last_Java_frame(Register last_java_sp,
367 Register last_java_fp,
368 address last_java_pc,
369 Register rscratch);
370
371 void reset_last_Java_frame(Register thread, bool clear_fp);
372
373 // thread in the default location (r15_thread on 64bit)
374 void reset_last_Java_frame(bool clear_fp);
375
376 // jobjects
377 void clear_jobject_tag(Register possibly_non_local);
378 void resolve_jobject(Register value, Register thread, Register tmp);
379 void resolve_global_jobject(Register value, Register thread, Register tmp);
380
381 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
382 void c2bool(Register x);
383
384 // C++ bool manipulation
385
386 void movbool(Register dst, Address src);
387 void movbool(Address dst, bool boolconst);
388 void movbool(Address dst, Register src);
389 void testbool(Register dst);
390
391 void resolve_oop_handle(Register result, Register tmp);
392 void resolve_weak_handle(Register result, Register tmp);
393 void load_mirror(Register mirror, Register method, Register tmp);
394 void load_method_holder_cld(Register rresult, Register rmethod);
395
396 void load_method_holder(Register holder, Register method);
397
398 // oop manipulations
399 void load_metadata(Register dst, Register src);
400 void load_klass(Register dst, Register src, Register tmp);
401 void store_klass(Register dst, Register src, Register tmp);
402
403 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
404 Register tmp1, Register thread_tmp);
405 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
406 Register tmp1, Register tmp2, Register tmp3);
407
408 void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass);
409 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
410 // We probably need the following for arrays: TODO FIXME
411 // void flat_element_copy(DecoratorSet decorators, Register src, Register dst, Register array);
412
413 // inline type data payload offsets...
414 void first_field_offset(Register inline_klass, Register offset);
415 void data_for_oop(Register oop, Register data, Register inline_klass);
416 // get data payload ptr a flat value array at index, kills rcx and index
417 void data_for_value_array_index(Register array, Register array_klass,
418 Register index, Register data);
419
420 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
421 Register thread_tmp = noreg, DecoratorSet decorators = 0);
422 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
423 Register thread_tmp = noreg, DecoratorSet decorators = 0);
424 void store_heap_oop(Address dst, Register val, Register tmp1 = noreg,
425 Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
426
427 // Used for storing null. All other oop constants should be
428 // stored using routines that take a jobject.
429 void store_heap_oop_null(Address dst);
430
431 void load_prototype_header(Register dst, Register src, Register tmp);
432
433 #ifdef _LP64
434 void store_klass_gap(Register dst, Register src);
435
436 // This dummy is to prevent a call to store_heap_oop from
437 // converting a zero (like null) into a Register by giving
438 // the compiler two choices it can't resolve
439
440 void store_heap_oop(Address dst, void* dummy);
441
442 void encode_heap_oop(Register r);
443 void decode_heap_oop(Register r);
444 void encode_heap_oop_not_null(Register r);
445 void decode_heap_oop_not_null(Register r);
446 void encode_heap_oop_not_null(Register dst, Register src);
447 void decode_heap_oop_not_null(Register dst, Register src);
448
449 void set_narrow_oop(Register dst, jobject obj);
450 void set_narrow_oop(Address dst, jobject obj);
451 void cmp_narrow_oop(Register dst, jobject obj);
452 void cmp_narrow_oop(Address dst, jobject obj);
453
454 void encode_klass_not_null(Register r, Register tmp);
455 void decode_klass_not_null(Register r, Register tmp);
456 void encode_and_move_klass_not_null(Register dst, Register src);
457 void decode_and_move_klass_not_null(Register dst, Register src);
458 void set_narrow_klass(Register dst, Klass* k);
459 void set_narrow_klass(Address dst, Klass* k);
460 void cmp_narrow_klass(Register dst, Klass* k);
461 void cmp_narrow_klass(Address dst, Klass* k);
462
463 // if heap base register is used - reinit it with the correct value
464 void reinit_heapbase();
465
466 DEBUG_ONLY(void verify_heapbase(const char* msg);)
467
468 #endif // _LP64
469
470 // Int division/remainder for Java
471 // (as idivl, but checks for special case as described in JVM spec.)
472 // returns idivl instruction offset for implicit exception handling
473 int corrected_idivl(Register reg);
474
475 // Long division/remainder for Java
476 // (as idivq, but checks for special case as described in JVM spec.)
477 // returns idivq instruction offset for implicit exception handling
478 int corrected_idivq(Register reg);
479
480 void int3();
481
482 // Long operation macros for a 32bit cpu
483 // Long negation for Java
484 void lneg(Register hi, Register lo);
485
486 // Long multiplication for Java
487 // (destroys contents of eax, ebx, ecx and edx)
488 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
489
490 // Long shifts for Java
491 // (semantics as described in JVM spec.)
492 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
493 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
494
495 // Long compare for Java
496 // (semantics as described in JVM spec.)
497 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
498
499
500 // misc
501
502 // Sign extension
503 void sign_extend_short(Register reg);
504 void sign_extend_byte(Register reg);
505
506 // Division by power of 2, rounding towards 0
507 void division_with_shift(Register reg, int shift_value);
508
509 #ifndef _LP64
510 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
511 //
512 // CF (corresponds to C0) if x < y
513 // PF (corresponds to C2) if unordered
514 // ZF (corresponds to C3) if x = y
515 //
516 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
517 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
518 void fcmp(Register tmp);
519 // Variant of the above which allows y to be further down the stack
520 // and which only pops x and y if specified. If pop_right is
521 // specified then pop_left must also be specified.
522 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
523
524 // Floating-point comparison for Java
525 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
526 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
527 // (semantics as described in JVM spec.)
528 void fcmp2int(Register dst, bool unordered_is_less);
529 // Variant of the above which allows y to be further down the stack
530 // and which only pops x and y if specified. If pop_right is
531 // specified then pop_left must also be specified.
532 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
533
534 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
535 // tmp is a temporary register, if none is available use noreg
536 void fremr(Register tmp);
537
538 // only if +VerifyFPU
539 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
540 #endif // !LP64
541
542 // dst = c = a * b + c
543 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
544 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
545
546 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
547 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
548 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
549 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
550
551
552 // same as fcmp2int, but using SSE2
553 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
554 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
555
556 // branch to L if FPU flag C2 is set/not set
557 // tmp is a temporary register, if none is available use noreg
558 void jC2 (Register tmp, Label& L);
559 void jnC2(Register tmp, Label& L);
560
561 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
562 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
563 void load_float(Address src);
564
565 // Store float value to 'address'. If UseSSE >= 1, the value is stored
566 // from register xmm0. Otherwise, the value is stored from the FPU stack.
567 void store_float(Address dst);
568
569 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
570 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
571 void load_double(Address src);
572
573 // Store double value to 'address'. If UseSSE >= 2, the value is stored
574 // from register xmm0. Otherwise, the value is stored from the FPU stack.
575 void store_double(Address dst);
576
577 #ifndef _LP64
578 // Pop ST (ffree & fincstp combined)
579 void fpop();
580
581 void empty_FPU_stack();
582 #endif // !_LP64
583
584 void push_IU_state();
585 void pop_IU_state();
586
587 void push_FPU_state();
588 void pop_FPU_state();
589
590 void push_CPU_state();
591 void pop_CPU_state();
592
593 void push_cont_fastpath();
594 void pop_cont_fastpath();
595
596 void inc_held_monitor_count();
597 void dec_held_monitor_count();
598
599 DEBUG_ONLY(void stop_if_in_cont(Register cont_reg, const char* name);)
600
601 // Round up to a power of two
602 void round_to(Register reg, int modulus);
603
604 private:
605 // General purpose and XMM registers potentially clobbered by native code; there
606 // is no need for FPU or AVX opmask related methods because C1/interpreter
607 // - we save/restore FPU state as a whole always
608 // - do not care about AVX-512 opmask
609 static RegSet call_clobbered_gp_registers();
610 static XMMRegSet call_clobbered_xmm_registers();
611
612 void push_set(XMMRegSet set, int offset);
613 void pop_set(XMMRegSet set, int offset);
614
615 public:
616 void push_set(RegSet set, int offset = -1);
617 void pop_set(RegSet set, int offset = -1);
618
619 // Push and pop everything that might be clobbered by a native
620 // runtime call.
621 // Only save the lower 64 bits of each vector register.
622 // Additional registers can be excluded in a passed RegSet.
623 void push_call_clobbered_registers_except(RegSet exclude, bool save_fpu = true);
624 void pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu = true);
625
626 void push_call_clobbered_registers(bool save_fpu = true) {
627 push_call_clobbered_registers_except(RegSet(), save_fpu);
628 }
629 void pop_call_clobbered_registers(bool restore_fpu = true) {
630 pop_call_clobbered_registers_except(RegSet(), restore_fpu);
631 }
632
633 // allocation
634
635 // Object / value buffer allocation...
636 // Allocate instance of klass, assumes klass initialized by caller
637 // new_obj prefers to be rax
638 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
639 void allocate_instance(Register klass, Register new_obj,
640 Register t1, Register t2,
641 bool clear_fields, Label& alloc_failed);
642
643 void tlab_allocate(
644 Register thread, // Current thread
645 Register obj, // result: pointer to object after successful allocation
646 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
647 int con_size_in_bytes, // object size in bytes if known at compile time
648 Register t1, // temp register
649 Register t2, // temp register
650 Label& slow_case // continuation point if fast allocation fails
651 );
652 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
653
654 // For field "index" within "klass", return inline_klass ...
655 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
656
657 void inline_layout_info(Register klass, Register index, Register layout_info);
658
659 void population_count(Register dst, Register src, Register scratch1, Register scratch2);
660
661 // interface method calling
662 void lookup_interface_method(Register recv_klass,
663 Register intf_klass,
664 RegisterOrConstant itable_index,
665 Register method_result,
666 Register scan_temp,
667 Label& no_such_interface,
668 bool return_method = true);
669
670 void lookup_interface_method_stub(Register recv_klass,
671 Register holder_klass,
672 Register resolved_klass,
673 Register method_result,
674 Register scan_temp,
675 Register temp_reg2,
676 Register receiver,
677 int itable_index,
678 Label& L_no_such_interface);
679
680 // virtual method calling
681 void lookup_virtual_method(Register recv_klass,
682 RegisterOrConstant vtable_index,
683 Register method_result);
684
685 // Test sub_klass against super_klass, with fast and slow paths.
686
687 // The fast path produces a tri-state answer: yes / no / maybe-slow.
688 // One of the three labels can be null, meaning take the fall-through.
689 // If super_check_offset is -1, the value is loaded up from super_klass.
690 // No registers are killed, except temp_reg.
691 void check_klass_subtype_fast_path(Register sub_klass,
692 Register super_klass,
693 Register temp_reg,
694 Label* L_success,
695 Label* L_failure,
696 Label* L_slow_path,
697 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
698
699 // The rest of the type check; must be wired to a corresponding fast path.
700 // It does not repeat the fast path logic, so don't use it standalone.
701 // The temp_reg and temp2_reg can be noreg, if no temps are available.
702 // Updates the sub's secondary super cache as necessary.
703 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
704 void check_klass_subtype_slow_path(Register sub_klass,
705 Register super_klass,
706 Register temp_reg,
707 Register temp2_reg,
708 Label* L_success,
709 Label* L_failure,
710 bool set_cond_codes = false);
711
712 #ifdef _LP64
713 // The 64-bit version, which may do a hashed subclass lookup.
714 void check_klass_subtype_slow_path(Register sub_klass,
715 Register super_klass,
716 Register temp_reg,
717 Register temp2_reg,
718 Register temp3_reg,
719 Register temp4_reg,
720 Label* L_success,
721 Label* L_failure);
722 #endif
723
724 // Three parts of a hashed subclass lookup: a simple linear search,
725 // a table lookup, and a fallback that does linear probing in the
726 // event of a hash collision.
727 void check_klass_subtype_slow_path_linear(Register sub_klass,
728 Register super_klass,
729 Register temp_reg,
730 Register temp2_reg,
731 Label* L_success,
732 Label* L_failure,
733 bool set_cond_codes = false);
734 void check_klass_subtype_slow_path_table(Register sub_klass,
735 Register super_klass,
736 Register temp_reg,
737 Register temp2_reg,
738 Register temp3_reg,
739 Register result_reg,
740 Label* L_success,
741 Label* L_failure);
742 void hashed_check_klass_subtype_slow_path(Register sub_klass,
743 Register super_klass,
744 Register temp_reg,
745 Label* L_success,
746 Label* L_failure);
747
748 // As above, but with a constant super_klass.
749 // The result is in Register result, not the condition codes.
750 void lookup_secondary_supers_table_const(Register sub_klass,
751 Register super_klass,
752 Register temp1,
753 Register temp2,
754 Register temp3,
755 Register temp4,
756 Register result,
757 u1 super_klass_slot);
758
759 #ifdef _LP64
760 using Assembler::salq;
761 void salq(Register dest, Register count);
762 using Assembler::rorq;
763 void rorq(Register dest, Register count);
764 void lookup_secondary_supers_table_var(Register sub_klass,
765 Register super_klass,
766 Register temp1,
767 Register temp2,
768 Register temp3,
769 Register temp4,
770 Register result);
771
772 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
773 Register r_array_base,
774 Register r_array_index,
775 Register r_bitmap,
776 Register temp1,
777 Register temp2,
778 Label* L_success,
779 Label* L_failure = nullptr);
780
781 void verify_secondary_supers_table(Register r_sub_klass,
782 Register r_super_klass,
783 Register expected,
784 Register temp1,
785 Register temp2,
786 Register temp3);
787 #endif
788
789 void repne_scanq(Register addr, Register value, Register count, Register limit,
790 Label* L_success,
791 Label* L_failure = nullptr);
792
793 // If r is valid, return r.
794 // If r is invalid, remove a register r2 from available_regs, add r2
795 // to regs_to_push, then return r2.
796 Register allocate_if_noreg(const Register r,
797 RegSetIterator<Register> &available_regs,
798 RegSet ®s_to_push);
799
800 // Simplified, combined version, good for typical uses.
801 // Falls through on failure.
802 void check_klass_subtype(Register sub_klass,
803 Register super_klass,
804 Register temp_reg,
805 Label& L_success);
806
807 void clinit_barrier(Register klass,
808 Register thread,
809 Label* L_fast_path = nullptr,
810 Label* L_slow_path = nullptr);
811
812 // method handles (JSR 292)
813 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
814
815 // Debugging
816
817 // only if +VerifyOops
818 void _verify_oop(Register reg, const char* s, const char* file, int line);
819 void _verify_oop_addr(Address addr, const char* s, const char* file, int line);
820
821 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
822 if (VerifyOops) {
823 _verify_oop(reg, s, file, line);
824 }
825 }
826 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
827 if (VerifyOops) {
828 _verify_oop_addr(reg, s, file, line);
829 }
830 }
831
832 // TODO: verify method and klass metadata (compare against vptr?)
833 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
834 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
835
836 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
837 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
838 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
839 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
840 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
841
842 // Verify or restore cpu control state after JNI call
843 void restore_cpu_control_state_after_jni(Register rscratch);
844
845 // prints msg, dumps registers and stops execution
846 void stop(const char* msg);
847
848 // prints msg and continues
849 void warn(const char* msg);
850
851 // dumps registers and other state
852 void print_state();
853
854 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
855 static void debug64(char* msg, int64_t pc, int64_t regs[]);
856 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
857 static void print_state64(int64_t pc, int64_t regs[]);
858
859 void os_breakpoint();
860
861 void untested() { stop("untested"); }
862
863 void unimplemented(const char* what = "");
864
865 void should_not_reach_here() { stop("should not reach here"); }
866
867 void print_CPU_state();
868
869 // Stack overflow checking
870 void bang_stack_with_offset(int offset) {
871 // stack grows down, caller passes positive offset
872 assert(offset > 0, "must bang with negative offset");
873 movl(Address(rsp, (-offset)), rax);
874 }
875
876 // Writes to stack successive pages until offset reached to check for
877 // stack overflow + shadow pages. Also, clobbers tmp
878 void bang_stack_size(Register size, Register tmp);
879
880 // Check for reserved stack access in method being exited (for JIT)
881 void reserved_stack_check();
882
883 void safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod);
884
885 void verify_tlab();
886
887 static Condition negate_condition(Condition cond);
888
889 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
890 // operands. In general the names are modified to avoid hiding the instruction in Assembler
891 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
892 // here in MacroAssembler. The major exception to this rule is call
893
894 // Arithmetics
895
896
897 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
898 void addptr(Address dst, Register src);
899
900 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
901 void addptr(Register dst, int32_t src);
902 void addptr(Register dst, Register src);
903 void addptr(Register dst, RegisterOrConstant src) {
904 if (src.is_constant()) addptr(dst, checked_cast<int>(src.as_constant()));
905 else addptr(dst, src.as_register());
906 }
907
908 void andptr(Register dst, int32_t src);
909 void andptr(Register dst, Register src) { LP64_ONLY(andq(dst, src)) NOT_LP64(andl(dst, src)) ; }
910 void andptr(Register dst, Address src) { LP64_ONLY(andq(dst, src)) NOT_LP64(andl(dst, src)) ; }
911
912 #ifdef _LP64
913 using Assembler::andq;
914 void andq(Register dst, AddressLiteral src, Register rscratch = noreg);
915 #endif
916
917 void cmp8(AddressLiteral src1, int imm, Register rscratch = noreg);
918
919 // renamed to drag out the casting of address to int32_t/intptr_t
920 void cmp32(Register src1, int32_t imm);
921
922 void cmp32(AddressLiteral src1, int32_t imm, Register rscratch = noreg);
923 // compare reg - mem, or reg - &mem
924 void cmp32(Register src1, AddressLiteral src2, Register rscratch = noreg);
925
926 void cmp32(Register src1, Address src2);
927
928 #ifndef _LP64
929 void cmpklass(Address dst, Metadata* obj);
930 void cmpklass(Register dst, Metadata* obj);
931 void cmpoop(Address dst, jobject obj);
932 #endif // _LP64
933
934 void cmpoop(Register src1, Register src2);
935 void cmpoop(Register src1, Address src2);
936 void cmpoop(Register dst, jobject obj, Register rscratch);
937
938 // NOTE src2 must be the lval. This is NOT an mem-mem compare
939 void cmpptr(Address src1, AddressLiteral src2, Register rscratch);
940
941 void cmpptr(Register src1, AddressLiteral src2, Register rscratch = noreg);
942
943 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
944 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
945 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
946
947 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
948 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
949
950 // cmp64 to avoild hiding cmpq
951 void cmp64(Register src1, AddressLiteral src, Register rscratch = noreg);
952
953 void cmpxchgptr(Register reg, Address adr);
954
955 void locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch = noreg);
956
957 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
958 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
959
960
961 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
962
963 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
964
965 void shlptr(Register dst, int32_t shift);
966 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
967
968 void shrptr(Register dst, int32_t shift);
969 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
970
971 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
972 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
973
974 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
975
976 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
977 void subptr(Register dst, int32_t src);
978 // Force generation of a 4 byte immediate value even if it fits into 8bit
979 void subptr_imm32(Register dst, int32_t src);
980 void subptr(Register dst, Register src);
981 void subptr(Register dst, RegisterOrConstant src) {
982 if (src.is_constant()) subptr(dst, (int) src.as_constant());
983 else subptr(dst, src.as_register());
984 }
985
986 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
987 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
988
989 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
990 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
991
992 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
993
994
995
996 // Helper functions for statistics gathering.
997 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
998 void cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch = noreg);
999 // Unconditional atomic increment.
1000 void atomic_incl(Address counter_addr);
1001 void atomic_incl(AddressLiteral counter_addr, Register rscratch = noreg);
1002 #ifdef _LP64
1003 void atomic_incq(Address counter_addr);
1004 void atomic_incq(AddressLiteral counter_addr, Register rscratch = noreg);
1005 #endif
1006 void atomic_incptr(AddressLiteral counter_addr, Register rscratch = noreg) { LP64_ONLY(atomic_incq(counter_addr, rscratch)) NOT_LP64(atomic_incl(counter_addr, rscratch)) ; }
1007 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
1008
1009 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
1010 void lea(Register dst, AddressLiteral adr);
1011 void lea(Address dst, AddressLiteral adr, Register rscratch);
1012
1013 void leal32(Register dst, Address src) { leal(dst, src); }
1014
1015 // Import other testl() methods from the parent class or else
1016 // they will be hidden by the following overriding declaration.
1017 using Assembler::testl;
1018 void testl(Address dst, int32_t imm32);
1019 void testl(Register dst, int32_t imm32);
1020 void testl(Register dst, AddressLiteral src); // requires reachable address
1021 using Assembler::testq;
1022 void testq(Address dst, int32_t imm32);
1023 void testq(Register dst, int32_t imm32);
1024
1025 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
1026 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
1027 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
1028 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
1029
1030 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
1031 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
1032 void testptr(Address src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
1033 void testptr(Register src1, Register src2);
1034
1035 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
1036 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
1037
1038 // Calls
1039
1040 void call(Label& L, relocInfo::relocType rtype);
1041 void call(Register entry);
1042 void call(Address addr) { Assembler::call(addr); }
1043
1044 // NOTE: this call transfers to the effective address of entry NOT
1045 // the address contained by entry. This is because this is more natural
1046 // for jumps/calls.
1047 void call(AddressLiteral entry, Register rscratch = rax);
1048
1049 // Emit the CompiledIC call idiom
1050 void ic_call(address entry, jint method_index = 0);
1051 static int ic_check_size();
1052 int ic_check(int end_alignment);
1053
1054 void emit_static_call_stub();
1055
1056 // Jumps
1057
1058 // NOTE: these jumps transfer to the effective address of dst NOT
1059 // the address contained by dst. This is because this is more natural
1060 // for jumps/calls.
1061 void jump(AddressLiteral dst, Register rscratch = noreg);
1062
1063 void jump_cc(Condition cc, AddressLiteral dst, Register rscratch = noreg);
1064
1065 // 32bit can do a case table jump in one instruction but we no longer allow the base
1066 // to be installed in the Address class. This jump will transfer to the address
1067 // contained in the location described by entry (not the address of entry)
1068 void jump(ArrayAddress entry, Register rscratch);
1069
1070 // Adding more natural conditional jump instructions
1071 void ALWAYSINLINE jo(Label& L, bool maybe_short = true) { jcc(Assembler::overflow, L, maybe_short); }
1072 void ALWAYSINLINE jno(Label& L, bool maybe_short = true) { jcc(Assembler::noOverflow, L, maybe_short); }
1073 void ALWAYSINLINE js(Label& L, bool maybe_short = true) { jcc(Assembler::negative, L, maybe_short); }
1074 void ALWAYSINLINE jns(Label& L, bool maybe_short = true) { jcc(Assembler::positive, L, maybe_short); }
1075 void ALWAYSINLINE je(Label& L, bool maybe_short = true) { jcc(Assembler::equal, L, maybe_short); }
1076 void ALWAYSINLINE jz(Label& L, bool maybe_short = true) { jcc(Assembler::zero, L, maybe_short); }
1077 void ALWAYSINLINE jne(Label& L, bool maybe_short = true) { jcc(Assembler::notEqual, L, maybe_short); }
1078 void ALWAYSINLINE jnz(Label& L, bool maybe_short = true) { jcc(Assembler::notZero, L, maybe_short); }
1079 void ALWAYSINLINE jb(Label& L, bool maybe_short = true) { jcc(Assembler::below, L, maybe_short); }
1080 void ALWAYSINLINE jnae(Label& L, bool maybe_short = true) { jcc(Assembler::below, L, maybe_short); }
1081 void ALWAYSINLINE jc(Label& L, bool maybe_short = true) { jcc(Assembler::carrySet, L, maybe_short); }
1082 void ALWAYSINLINE jnb(Label& L, bool maybe_short = true) { jcc(Assembler::aboveEqual, L, maybe_short); }
1083 void ALWAYSINLINE jae(Label& L, bool maybe_short = true) { jcc(Assembler::aboveEqual, L, maybe_short); }
1084 void ALWAYSINLINE jnc(Label& L, bool maybe_short = true) { jcc(Assembler::carryClear, L, maybe_short); }
1085 void ALWAYSINLINE jbe(Label& L, bool maybe_short = true) { jcc(Assembler::belowEqual, L, maybe_short); }
1086 void ALWAYSINLINE jna(Label& L, bool maybe_short = true) { jcc(Assembler::belowEqual, L, maybe_short); }
1087 void ALWAYSINLINE ja(Label& L, bool maybe_short = true) { jcc(Assembler::above, L, maybe_short); }
1088 void ALWAYSINLINE jnbe(Label& L, bool maybe_short = true) { jcc(Assembler::above, L, maybe_short); }
1089 void ALWAYSINLINE jl(Label& L, bool maybe_short = true) { jcc(Assembler::less, L, maybe_short); }
1090 void ALWAYSINLINE jnge(Label& L, bool maybe_short = true) { jcc(Assembler::less, L, maybe_short); }
1091 void ALWAYSINLINE jge(Label& L, bool maybe_short = true) { jcc(Assembler::greaterEqual, L, maybe_short); }
1092 void ALWAYSINLINE jnl(Label& L, bool maybe_short = true) { jcc(Assembler::greaterEqual, L, maybe_short); }
1093 void ALWAYSINLINE jle(Label& L, bool maybe_short = true) { jcc(Assembler::lessEqual, L, maybe_short); }
1094 void ALWAYSINLINE jng(Label& L, bool maybe_short = true) { jcc(Assembler::lessEqual, L, maybe_short); }
1095 void ALWAYSINLINE jg(Label& L, bool maybe_short = true) { jcc(Assembler::greater, L, maybe_short); }
1096 void ALWAYSINLINE jnle(Label& L, bool maybe_short = true) { jcc(Assembler::greater, L, maybe_short); }
1097 void ALWAYSINLINE jp(Label& L, bool maybe_short = true) { jcc(Assembler::parity, L, maybe_short); }
1098 void ALWAYSINLINE jpe(Label& L, bool maybe_short = true) { jcc(Assembler::parity, L, maybe_short); }
1099 void ALWAYSINLINE jnp(Label& L, bool maybe_short = true) { jcc(Assembler::noParity, L, maybe_short); }
1100 void ALWAYSINLINE jpo(Label& L, bool maybe_short = true) { jcc(Assembler::noParity, L, maybe_short); }
1101 // * No condition for this * void ALWAYSINLINE jcxz(Label& L, bool maybe_short = true) { jcc(Assembler::cxz, L, maybe_short); }
1102 // * No condition for this * void ALWAYSINLINE jecxz(Label& L, bool maybe_short = true) { jcc(Assembler::cxz, L, maybe_short); }
1103
1104 // Short versions of the above
1105 void ALWAYSINLINE jo_b(Label& L) { jccb(Assembler::overflow, L); }
1106 void ALWAYSINLINE jno_b(Label& L) { jccb(Assembler::noOverflow, L); }
1107 void ALWAYSINLINE js_b(Label& L) { jccb(Assembler::negative, L); }
1108 void ALWAYSINLINE jns_b(Label& L) { jccb(Assembler::positive, L); }
1109 void ALWAYSINLINE je_b(Label& L) { jccb(Assembler::equal, L); }
1110 void ALWAYSINLINE jz_b(Label& L) { jccb(Assembler::zero, L); }
1111 void ALWAYSINLINE jne_b(Label& L) { jccb(Assembler::notEqual, L); }
1112 void ALWAYSINLINE jnz_b(Label& L) { jccb(Assembler::notZero, L); }
1113 void ALWAYSINLINE jb_b(Label& L) { jccb(Assembler::below, L); }
1114 void ALWAYSINLINE jnae_b(Label& L) { jccb(Assembler::below, L); }
1115 void ALWAYSINLINE jc_b(Label& L) { jccb(Assembler::carrySet, L); }
1116 void ALWAYSINLINE jnb_b(Label& L) { jccb(Assembler::aboveEqual, L); }
1117 void ALWAYSINLINE jae_b(Label& L) { jccb(Assembler::aboveEqual, L); }
1118 void ALWAYSINLINE jnc_b(Label& L) { jccb(Assembler::carryClear, L); }
1119 void ALWAYSINLINE jbe_b(Label& L) { jccb(Assembler::belowEqual, L); }
1120 void ALWAYSINLINE jna_b(Label& L) { jccb(Assembler::belowEqual, L); }
1121 void ALWAYSINLINE ja_b(Label& L) { jccb(Assembler::above, L); }
1122 void ALWAYSINLINE jnbe_b(Label& L) { jccb(Assembler::above, L); }
1123 void ALWAYSINLINE jl_b(Label& L) { jccb(Assembler::less, L); }
1124 void ALWAYSINLINE jnge_b(Label& L) { jccb(Assembler::less, L); }
1125 void ALWAYSINLINE jge_b(Label& L) { jccb(Assembler::greaterEqual, L); }
1126 void ALWAYSINLINE jnl_b(Label& L) { jccb(Assembler::greaterEqual, L); }
1127 void ALWAYSINLINE jle_b(Label& L) { jccb(Assembler::lessEqual, L); }
1128 void ALWAYSINLINE jng_b(Label& L) { jccb(Assembler::lessEqual, L); }
1129 void ALWAYSINLINE jg_b(Label& L) { jccb(Assembler::greater, L); }
1130 void ALWAYSINLINE jnle_b(Label& L) { jccb(Assembler::greater, L); }
1131 void ALWAYSINLINE jp_b(Label& L) { jccb(Assembler::parity, L); }
1132 void ALWAYSINLINE jpe_b(Label& L) { jccb(Assembler::parity, L); }
1133 void ALWAYSINLINE jnp_b(Label& L) { jccb(Assembler::noParity, L); }
1134 void ALWAYSINLINE jpo_b(Label& L) { jccb(Assembler::noParity, L); }
1135 // * No condition for this * void ALWAYSINLINE jcxz_b(Label& L) { jccb(Assembler::cxz, L); }
1136 // * No condition for this * void ALWAYSINLINE jecxz_b(Label& L) { jccb(Assembler::cxz, L); }
1137
1138 // Floating
1139
1140 void push_f(XMMRegister r);
1141 void pop_f(XMMRegister r);
1142 void push_d(XMMRegister r);
1143 void pop_d(XMMRegister r);
1144
1145 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
1146 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
1147 void andpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1148
1149 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
1150 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
1151 void andps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1152
1153 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
1154 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
1155 void comiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1156
1157 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
1158 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
1159 void comisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1160
1161 #ifndef _LP64
1162 void fadd_s(Address src) { Assembler::fadd_s(src); }
1163 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
1164
1165 void fldcw(Address src) { Assembler::fldcw(src); }
1166 void fldcw(AddressLiteral src);
1167
1168 void fld_s(int index) { Assembler::fld_s(index); }
1169 void fld_s(Address src) { Assembler::fld_s(src); }
1170 void fld_s(AddressLiteral src);
1171
1172 void fld_d(Address src) { Assembler::fld_d(src); }
1173 void fld_d(AddressLiteral src);
1174
1175 void fld_x(Address src) { Assembler::fld_x(src); }
1176 void fld_x(AddressLiteral src) { Assembler::fld_x(as_Address(src)); }
1177
1178 void fmul_s(Address src) { Assembler::fmul_s(src); }
1179 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
1180 #endif // !_LP64
1181
1182 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
1183 void ldmxcsr(AddressLiteral src, Register rscratch = noreg);
1184
1185 #ifdef _LP64
1186 private:
1187 void sha256_AVX2_one_round_compute(
1188 Register reg_old_h,
1189 Register reg_a,
1190 Register reg_b,
1191 Register reg_c,
1192 Register reg_d,
1193 Register reg_e,
1194 Register reg_f,
1195 Register reg_g,
1196 Register reg_h,
1197 int iter);
1198 void sha256_AVX2_four_rounds_compute_first(int start);
1199 void sha256_AVX2_four_rounds_compute_last(int start);
1200 void sha256_AVX2_one_round_and_sched(
1201 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
1202 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
1203 XMMRegister xmm_2, /* ymm6 */
1204 XMMRegister xmm_3, /* ymm7 */
1205 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
1206 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
1207 Register reg_c, /* edi */
1208 Register reg_d, /* esi */
1209 Register reg_e, /* r8d */
1210 Register reg_f, /* r9d */
1211 Register reg_g, /* r10d */
1212 Register reg_h, /* r11d */
1213 int iter);
1214
1215 void addm(int disp, Register r1, Register r2);
1216
1217 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
1218 Register e, Register f, Register g, Register h, int iteration);
1219
1220 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1221 Register a, Register b, Register c, Register d, Register e, Register f,
1222 Register g, Register h, int iteration);
1223
1224 void addmq(int disp, Register r1, Register r2);
1225 public:
1226 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1227 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1228 Register buf, Register state, Register ofs, Register limit, Register rsp,
1229 bool multi_block, XMMRegister shuf_mask);
1230 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1231 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1232 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
1233 XMMRegister shuf_mask);
1234 void sha512_update_ni_x1(Register arg_hash, Register arg_msg, Register ofs, Register limit, bool multi_block);
1235 #endif // _LP64
1236
1237 void fast_md5(Register buf, Address state, Address ofs, Address limit,
1238 bool multi_block);
1239
1240 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1241 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1242 Register buf, Register state, Register ofs, Register limit, Register rsp,
1243 bool multi_block);
1244
1245 #ifdef _LP64
1246 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1247 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1248 Register buf, Register state, Register ofs, Register limit, Register rsp,
1249 bool multi_block, XMMRegister shuf_mask);
1250 #else
1251 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1252 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1253 Register buf, Register state, Register ofs, Register limit, Register rsp,
1254 bool multi_block);
1255 #endif
1256
1257 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1258 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1259 Register rax, Register rcx, Register rdx, Register tmp);
1260
1261 #ifndef _LP64
1262 private:
1263 // Initialized in macroAssembler_x86_constants.cpp
1264 static address ONES;
1265 static address L_2IL0FLOATPACKET_0;
1266 static address PI4_INV;
1267 static address PI4X3;
1268 static address PI4X4;
1269
1270 public:
1271 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1272 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1273 Register rax, Register rcx, Register rdx, Register tmp1);
1274
1275 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1276 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1277 Register rax, Register rcx, Register rdx, Register tmp);
1278
1279 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1280 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1281 Register rdx, Register tmp);
1282
1283 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1284 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1285 Register rax, Register rbx, Register rdx);
1286
1287 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1288 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1289 Register rax, Register rcx, Register rdx, Register tmp);
1290
1291 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1292 Register edx, Register ebx, Register esi, Register edi,
1293 Register ebp, Register esp);
1294
1295 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1296 Register esi, Register edi, Register ebp, Register esp);
1297
1298 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1299 Register edx, Register ebx, Register esi, Register edi,
1300 Register ebp, Register esp);
1301
1302 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1303 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1304 Register rax, Register rcx, Register rdx, Register tmp);
1305 #endif // !_LP64
1306
1307 private:
1308
1309 // these are private because users should be doing movflt/movdbl
1310
1311 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1312 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1313 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1314 void movss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1315
1316 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1317 void movlpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1318
1319 public:
1320
1321 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1322 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1323 void addsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1324
1325 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1326 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1327 void addss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1328
1329 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1330 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1331 void addpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1332
1333 using Assembler::vbroadcasti128;
1334 void vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1335
1336 using Assembler::vbroadcastsd;
1337 void vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1338
1339 using Assembler::vbroadcastss;
1340 void vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1341
1342 // Vector float blend
1343 void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg);
1344 void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg);
1345
1346 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1347 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1348 void divsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1349
1350 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1351 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1352 void divss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1353
1354 // Move Unaligned Double Quadword
1355 void movdqu(Address dst, XMMRegister src);
1356 void movdqu(XMMRegister dst, XMMRegister src);
1357 void movdqu(XMMRegister dst, Address src);
1358 void movdqu(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1359
1360 void kmovwl(Register dst, KRegister src) { Assembler::kmovwl(dst, src); }
1361 void kmovwl(Address dst, KRegister src) { Assembler::kmovwl(dst, src); }
1362 void kmovwl(KRegister dst, KRegister src) { Assembler::kmovwl(dst, src); }
1363 void kmovwl(KRegister dst, Register src) { Assembler::kmovwl(dst, src); }
1364 void kmovwl(KRegister dst, Address src) { Assembler::kmovwl(dst, src); }
1365 void kmovwl(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1366
1367 void kmovql(KRegister dst, KRegister src) { Assembler::kmovql(dst, src); }
1368 void kmovql(KRegister dst, Register src) { Assembler::kmovql(dst, src); }
1369 void kmovql(Register dst, KRegister src) { Assembler::kmovql(dst, src); }
1370 void kmovql(KRegister dst, Address src) { Assembler::kmovql(dst, src); }
1371 void kmovql(Address dst, KRegister src) { Assembler::kmovql(dst, src); }
1372 void kmovql(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1373
1374 // Safe move operation, lowers down to 16bit moves for targets supporting
1375 // AVX512F feature and 64bit moves for targets supporting AVX512BW feature.
1376 void kmov(Address dst, KRegister src);
1377 void kmov(KRegister dst, Address src);
1378 void kmov(KRegister dst, KRegister src);
1379 void kmov(Register dst, KRegister src);
1380 void kmov(KRegister dst, Register src);
1381
1382 using Assembler::movddup;
1383 void movddup(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1384
1385 using Assembler::vmovddup;
1386 void vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1387
1388 // AVX Unaligned forms
1389 void vmovdqu(Address dst, XMMRegister src);
1390 void vmovdqu(XMMRegister dst, Address src);
1391 void vmovdqu(XMMRegister dst, XMMRegister src);
1392 void vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1393 void vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1394
1395 // AVX512 Unaligned
1396 void evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len);
1397 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len);
1398 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len);
1399
1400 void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1401 void evmovdqub(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1402
1403 void evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1404 if (dst->encoding() != src->encoding() || mask != k0) {
1405 Assembler::evmovdqub(dst, mask, src, merge, vector_len);
1406 }
1407 }
1408 void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1409 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1410 void evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1411
1412 void evmovdquw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1413 void evmovdquw(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1414 void evmovdquw(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1415
1416 void evmovdquw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1417 if (dst->encoding() != src->encoding() || mask != k0) {
1418 Assembler::evmovdquw(dst, mask, src, merge, vector_len);
1419 }
1420 }
1421 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1422 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1423 void evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1424
1425 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
1426 if (dst->encoding() != src->encoding()) {
1427 Assembler::evmovdqul(dst, src, vector_len);
1428 }
1429 }
1430 void evmovdqul(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1431 void evmovdqul(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1432
1433 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1434 if (dst->encoding() != src->encoding() || mask != k0) {
1435 Assembler::evmovdqul(dst, mask, src, merge, vector_len);
1436 }
1437 }
1438 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1439 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1440 void evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1441
1442 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
1443 if (dst->encoding() != src->encoding()) {
1444 Assembler::evmovdquq(dst, src, vector_len);
1445 }
1446 }
1447 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1448 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1449 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1450
1451 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1452 if (dst->encoding() != src->encoding() || mask != k0) {
1453 Assembler::evmovdquq(dst, mask, src, merge, vector_len);
1454 }
1455 }
1456 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1457 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1458 void evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1459
1460 // Move Aligned Double Quadword
1461 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1462 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1463 void movdqa(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1464
1465 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1466 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1467 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1468 void movsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1469
1470 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1471 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1472 void mulpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1473
1474 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1475 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1476 void mulsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1477
1478 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1479 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1480 void mulss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1481
1482 // Carry-Less Multiplication Quadword
1483 void pclmulldq(XMMRegister dst, XMMRegister src) {
1484 // 0x00 - multiply lower 64 bits [0:63]
1485 Assembler::pclmulqdq(dst, src, 0x00);
1486 }
1487 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1488 // 0x11 - multiply upper 64 bits [64:127]
1489 Assembler::pclmulqdq(dst, src, 0x11);
1490 }
1491
1492 void pcmpeqb(XMMRegister dst, XMMRegister src);
1493 void pcmpeqw(XMMRegister dst, XMMRegister src);
1494
1495 void pcmpestri(XMMRegister dst, Address src, int imm8);
1496 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1497
1498 void pmovzxbw(XMMRegister dst, XMMRegister src);
1499 void pmovzxbw(XMMRegister dst, Address src);
1500
1501 void pmovmskb(Register dst, XMMRegister src);
1502
1503 void ptest(XMMRegister dst, XMMRegister src);
1504
1505 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1506 void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1507 void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch = noreg);
1508
1509 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1510 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1511 void sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1512
1513 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1514 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1515 void subsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1516
1517 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1518 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1519 void subss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1520
1521 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1522 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1523 void ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1524
1525 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1526 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1527 void ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1528
1529 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1530 void xorpd(XMMRegister dst, XMMRegister src);
1531 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1532 void xorpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1533
1534 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1535 void xorps(XMMRegister dst, XMMRegister src);
1536 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1537 void xorps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1538
1539 // Shuffle Bytes
1540 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1541 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1542 void pshufb(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1543 // AVX 3-operands instructions
1544
1545 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1546 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1547 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1548
1549 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1550 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1551 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1552
1553 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1554 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1555
1556 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1557 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1558 void vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1559
1560 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1561 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1562
1563 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1564 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1565 void vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1566
1567 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1568 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1569 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1570
1571 using Assembler::vpbroadcastd;
1572 void vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1573
1574 using Assembler::vpbroadcastq;
1575 void vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1576
1577 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1578 void vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len);
1579
1580 void vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1581 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1582 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1583
1584 // Vector compares
1585 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1586 Assembler::evpcmpd(kdst, mask, nds, src, comparison, is_signed, vector_len);
1587 }
1588 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1589
1590 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1591 Assembler::evpcmpq(kdst, mask, nds, src, comparison, is_signed, vector_len);
1592 }
1593 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1594
1595 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1596 Assembler::evpcmpb(kdst, mask, nds, src, comparison, is_signed, vector_len);
1597 }
1598 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1599
1600 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int comparison, bool is_signed, int vector_len) {
1601 Assembler::evpcmpw(kdst, mask, nds, src, comparison, is_signed, vector_len);
1602 }
1603 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1604
1605 void evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len);
1606
1607 // Emit comparison instruction for the specified comparison predicate.
1608 void vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len);
1609 void vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len);
1610
1611 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1612 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1613
1614 void vpmovmskb(Register dst, XMMRegister src, int vector_len = Assembler::AVX_256bit);
1615
1616 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1617 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1618
1619 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1620 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1621 void vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1622
1623 void vpmuldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpmuldq(dst, nds, src, vector_len); }
1624
1625 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1626 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1627
1628 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1629 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1630
1631 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1632 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1633
1634 void evpsrad(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1635 void evpsrad(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1636
1637 void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1638 void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1639
1640 using Assembler::evpsllw;
1641 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1642 if (!is_varshift) {
1643 Assembler::evpsllw(dst, mask, nds, src, merge, vector_len);
1644 } else {
1645 Assembler::evpsllvw(dst, mask, nds, src, merge, vector_len);
1646 }
1647 }
1648 void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1649 if (!is_varshift) {
1650 Assembler::evpslld(dst, mask, nds, src, merge, vector_len);
1651 } else {
1652 Assembler::evpsllvd(dst, mask, nds, src, merge, vector_len);
1653 }
1654 }
1655 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1656 if (!is_varshift) {
1657 Assembler::evpsllq(dst, mask, nds, src, merge, vector_len);
1658 } else {
1659 Assembler::evpsllvq(dst, mask, nds, src, merge, vector_len);
1660 }
1661 }
1662 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1663 if (!is_varshift) {
1664 Assembler::evpsrlw(dst, mask, nds, src, merge, vector_len);
1665 } else {
1666 Assembler::evpsrlvw(dst, mask, nds, src, merge, vector_len);
1667 }
1668 }
1669 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1670 if (!is_varshift) {
1671 Assembler::evpsrld(dst, mask, nds, src, merge, vector_len);
1672 } else {
1673 Assembler::evpsrlvd(dst, mask, nds, src, merge, vector_len);
1674 }
1675 }
1676
1677 using Assembler::evpsrlq;
1678 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1679 if (!is_varshift) {
1680 Assembler::evpsrlq(dst, mask, nds, src, merge, vector_len);
1681 } else {
1682 Assembler::evpsrlvq(dst, mask, nds, src, merge, vector_len);
1683 }
1684 }
1685 using Assembler::evpsraw;
1686 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1687 if (!is_varshift) {
1688 Assembler::evpsraw(dst, mask, nds, src, merge, vector_len);
1689 } else {
1690 Assembler::evpsravw(dst, mask, nds, src, merge, vector_len);
1691 }
1692 }
1693 using Assembler::evpsrad;
1694 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1695 if (!is_varshift) {
1696 Assembler::evpsrad(dst, mask, nds, src, merge, vector_len);
1697 } else {
1698 Assembler::evpsravd(dst, mask, nds, src, merge, vector_len);
1699 }
1700 }
1701 using Assembler::evpsraq;
1702 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1703 if (!is_varshift) {
1704 Assembler::evpsraq(dst, mask, nds, src, merge, vector_len);
1705 } else {
1706 Assembler::evpsravq(dst, mask, nds, src, merge, vector_len);
1707 }
1708 }
1709
1710 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1711 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1712 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1713 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1714
1715 void evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1716 void evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1717 void evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1718 void evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1719
1720 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1721 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1722
1723 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1724 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1725
1726 void vptest(XMMRegister dst, XMMRegister src);
1727 void vptest(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vptest(dst, src, vector_len); }
1728
1729 void punpcklbw(XMMRegister dst, XMMRegister src);
1730 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1731
1732 void pshufd(XMMRegister dst, Address src, int mode);
1733 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1734
1735 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1736 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1737
1738 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1739 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1740 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1741
1742 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1743 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1744 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1745
1746 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1747
1748 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1749 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1750 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1751
1752 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1753 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1754 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1755
1756 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1757 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1758 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1759
1760 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1761 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1762 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1763
1764 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1765 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1766 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1767
1768 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1769 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1770 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1771
1772 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1773 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1774
1775 // AVX Vector instructions
1776
1777 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1778 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1779 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1780
1781 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1782 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1783 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1784
1785 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1786 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1787 Assembler::vpxor(dst, nds, src, vector_len);
1788 else
1789 Assembler::vxorpd(dst, nds, src, vector_len);
1790 }
1791 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1792 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1793 Assembler::vpxor(dst, nds, src, vector_len);
1794 else
1795 Assembler::vxorpd(dst, nds, src, vector_len);
1796 }
1797 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1798
1799 // Simple version for AVX2 256bit vectors
1800 void vpxor(XMMRegister dst, XMMRegister src) {
1801 assert(UseAVX >= 2, "Should be at least AVX2");
1802 Assembler::vpxor(dst, dst, src, AVX_256bit);
1803 }
1804 void vpxor(XMMRegister dst, Address src) {
1805 assert(UseAVX >= 2, "Should be at least AVX2");
1806 Assembler::vpxor(dst, dst, src, AVX_256bit);
1807 }
1808
1809 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpermd(dst, nds, src, vector_len); }
1810 void vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1811
1812 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1813 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1814 Assembler::vinserti32x4(dst, nds, src, imm8);
1815 } else if (UseAVX > 1) {
1816 // vinserti128 is available only in AVX2
1817 Assembler::vinserti128(dst, nds, src, imm8);
1818 } else {
1819 Assembler::vinsertf128(dst, nds, src, imm8);
1820 }
1821 }
1822
1823 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1824 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1825 Assembler::vinserti32x4(dst, nds, src, imm8);
1826 } else if (UseAVX > 1) {
1827 // vinserti128 is available only in AVX2
1828 Assembler::vinserti128(dst, nds, src, imm8);
1829 } else {
1830 Assembler::vinsertf128(dst, nds, src, imm8);
1831 }
1832 }
1833
1834 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1835 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1836 Assembler::vextracti32x4(dst, src, imm8);
1837 } else if (UseAVX > 1) {
1838 // vextracti128 is available only in AVX2
1839 Assembler::vextracti128(dst, src, imm8);
1840 } else {
1841 Assembler::vextractf128(dst, src, imm8);
1842 }
1843 }
1844
1845 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1846 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1847 Assembler::vextracti32x4(dst, src, imm8);
1848 } else if (UseAVX > 1) {
1849 // vextracti128 is available only in AVX2
1850 Assembler::vextracti128(dst, src, imm8);
1851 } else {
1852 Assembler::vextractf128(dst, src, imm8);
1853 }
1854 }
1855
1856 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1857 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1858 vinserti128(dst, dst, src, 1);
1859 }
1860 void vinserti128_high(XMMRegister dst, Address src) {
1861 vinserti128(dst, dst, src, 1);
1862 }
1863 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1864 vextracti128(dst, src, 1);
1865 }
1866 void vextracti128_high(Address dst, XMMRegister src) {
1867 vextracti128(dst, src, 1);
1868 }
1869
1870 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1871 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1872 Assembler::vinsertf32x4(dst, dst, src, 1);
1873 } else {
1874 Assembler::vinsertf128(dst, dst, src, 1);
1875 }
1876 }
1877
1878 void vinsertf128_high(XMMRegister dst, Address src) {
1879 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1880 Assembler::vinsertf32x4(dst, dst, src, 1);
1881 } else {
1882 Assembler::vinsertf128(dst, dst, src, 1);
1883 }
1884 }
1885
1886 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1887 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1888 Assembler::vextractf32x4(dst, src, 1);
1889 } else {
1890 Assembler::vextractf128(dst, src, 1);
1891 }
1892 }
1893
1894 void vextractf128_high(Address dst, XMMRegister src) {
1895 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1896 Assembler::vextractf32x4(dst, src, 1);
1897 } else {
1898 Assembler::vextractf128(dst, src, 1);
1899 }
1900 }
1901
1902 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1903 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1904 Assembler::vinserti64x4(dst, dst, src, 1);
1905 }
1906 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1907 Assembler::vinsertf64x4(dst, dst, src, 1);
1908 }
1909 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1910 Assembler::vextracti64x4(dst, src, 1);
1911 }
1912 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1913 Assembler::vextractf64x4(dst, src, 1);
1914 }
1915 void vextractf64x4_high(Address dst, XMMRegister src) {
1916 Assembler::vextractf64x4(dst, src, 1);
1917 }
1918 void vinsertf64x4_high(XMMRegister dst, Address src) {
1919 Assembler::vinsertf64x4(dst, dst, src, 1);
1920 }
1921
1922 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1923 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1924 vinserti128(dst, dst, src, 0);
1925 }
1926 void vinserti128_low(XMMRegister dst, Address src) {
1927 vinserti128(dst, dst, src, 0);
1928 }
1929 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1930 vextracti128(dst, src, 0);
1931 }
1932 void vextracti128_low(Address dst, XMMRegister src) {
1933 vextracti128(dst, src, 0);
1934 }
1935
1936 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1937 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1938 Assembler::vinsertf32x4(dst, dst, src, 0);
1939 } else {
1940 Assembler::vinsertf128(dst, dst, src, 0);
1941 }
1942 }
1943
1944 void vinsertf128_low(XMMRegister dst, Address src) {
1945 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1946 Assembler::vinsertf32x4(dst, dst, src, 0);
1947 } else {
1948 Assembler::vinsertf128(dst, dst, src, 0);
1949 }
1950 }
1951
1952 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1953 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1954 Assembler::vextractf32x4(dst, src, 0);
1955 } else {
1956 Assembler::vextractf128(dst, src, 0);
1957 }
1958 }
1959
1960 void vextractf128_low(Address dst, XMMRegister src) {
1961 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1962 Assembler::vextractf32x4(dst, src, 0);
1963 } else {
1964 Assembler::vextractf128(dst, src, 0);
1965 }
1966 }
1967
1968 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1969 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1970 Assembler::vinserti64x4(dst, dst, src, 0);
1971 }
1972 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1973 Assembler::vinsertf64x4(dst, dst, src, 0);
1974 }
1975 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1976 Assembler::vextracti64x4(dst, src, 0);
1977 }
1978 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1979 Assembler::vextractf64x4(dst, src, 0);
1980 }
1981 void vextractf64x4_low(Address dst, XMMRegister src) {
1982 Assembler::vextractf64x4(dst, src, 0);
1983 }
1984 void vinsertf64x4_low(XMMRegister dst, Address src) {
1985 Assembler::vinsertf64x4(dst, dst, src, 0);
1986 }
1987
1988 // Carry-Less Multiplication Quadword
1989 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1990 // 0x00 - multiply lower 64 bits [0:63]
1991 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1992 }
1993 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1994 // 0x11 - multiply upper 64 bits [64:127]
1995 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1996 }
1997 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1998 // 0x10 - multiply nds[0:63] and src[64:127]
1999 Assembler::vpclmulqdq(dst, nds, src, 0x10);
2000 }
2001 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
2002 //0x01 - multiply nds[64:127] and src[0:63]
2003 Assembler::vpclmulqdq(dst, nds, src, 0x01);
2004 }
2005
2006 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2007 // 0x00 - multiply lower 64 bits [0:63]
2008 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
2009 }
2010 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
2011 // 0x11 - multiply upper 64 bits [64:127]
2012 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
2013 }
2014
2015 // AVX-512 mask operations.
2016 void kand(BasicType etype, KRegister dst, KRegister src1, KRegister src2);
2017 void kor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
2018 void knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp = knoreg, Register rtmp = noreg);
2019 void kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
2020 void kortest(uint masklen, KRegister src1, KRegister src2);
2021 void ktest(uint masklen, KRegister src1, KRegister src2);
2022
2023 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2024 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2025
2026 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2027 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2028
2029 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2030 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2031
2032 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2033 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2034
2035 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
2036 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
2037 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
2038 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
2039
2040 using Assembler::evpandq;
2041 void evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
2042
2043 using Assembler::evpaddq;
2044 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
2045
2046 using Assembler::evporq;
2047 void evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
2048
2049 using Assembler::vpshufb;
2050 void vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
2051
2052 using Assembler::vpor;
2053 void vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
2054
2055 using Assembler::vpternlogq;
2056 void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch = noreg);
2057
2058 void cmov32( Condition cc, Register dst, Address src);
2059 void cmov32( Condition cc, Register dst, Register src);
2060
2061 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
2062
2063 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2064 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
2065
2066 void movoop(Register dst, jobject obj);
2067 void movoop(Address dst, jobject obj, Register rscratch);
2068
2069 void mov_metadata(Register dst, Metadata* obj);
2070 void mov_metadata(Address dst, Metadata* obj, Register rscratch);
2071
2072 void movptr(Register dst, Register src);
2073 void movptr(Register dst, Address src);
2074 void movptr(Register dst, AddressLiteral src);
2075 void movptr(Register dst, ArrayAddress src);
2076 void movptr(Register dst, intptr_t src);
2077 void movptr(Address dst, Register src);
2078 void movptr(Address dst, int32_t imm);
2079 void movptr(Address dst, intptr_t src, Register rscratch);
2080 void movptr(ArrayAddress dst, Register src, Register rscratch);
2081
2082 void movptr(Register dst, RegisterOrConstant src) {
2083 if (src.is_constant()) movptr(dst, src.as_constant());
2084 else movptr(dst, src.as_register());
2085 }
2086
2087
2088 // to avoid hiding movl
2089 void mov32(Register dst, AddressLiteral src);
2090 void mov32(AddressLiteral dst, Register src, Register rscratch = noreg);
2091
2092 // Import other mov() methods from the parent class or else
2093 // they will be hidden by the following overriding declaration.
2094 using Assembler::movdl;
2095 void movdl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
2096
2097 using Assembler::movq;
2098 void movq(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
2099
2100 // Can push value or effective address
2101 void pushptr(AddressLiteral src, Register rscratch);
2102
2103 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
2104 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
2105
2106 void pushoop(jobject obj, Register rscratch);
2107 void pushklass(Metadata* obj, Register rscratch);
2108
2109 // sign extend as need a l to ptr sized element
2110 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
2111 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
2112
2113
2114 public:
2115 // Inline type specific methods
2116 #include "asm/macroAssembler_common.hpp"
2117
2118 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
2119 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
2120 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
2121 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
2122 RegState reg_state[]);
2123 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
2124 VMRegPair* from, int from_count, int& from_index, VMReg to,
2125 RegState reg_state[], Register val_array);
2126 int extend_stack_for_inline_args(int args_on_stack);
2127 void remove_frame(int initial_framesize, bool needs_stack_repair);
2128 VMReg spill_reg_for(VMReg reg);
2129
2130 // clear memory of size 'cnt' qwords, starting at 'base';
2131 // if 'is_large' is set, do not try to produce short loop
2132 void clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, bool is_large, bool word_copy_only, KRegister mask=knoreg);
2133
2134 // clear memory initialization sequence for constant size;
2135 void clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
2136
2137 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
2138 void xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
2139
2140 // Fill primitive arrays
2141 void generate_fill(BasicType t, bool aligned,
2142 Register to, Register value, Register count,
2143 Register rtmp, XMMRegister xtmp);
2144
2145 void encode_iso_array(Register src, Register dst, Register len,
2146 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
2147 XMMRegister tmp4, Register tmp5, Register result, bool ascii);
2148
2149 #ifdef _LP64
2150 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
2151 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
2152 Register y, Register y_idx, Register z,
2153 Register carry, Register product,
2154 Register idx, Register kdx);
2155 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
2156 Register yz_idx, Register idx,
2157 Register carry, Register product, int offset);
2158 void multiply_128_x_128_bmi2_loop(Register y, Register z,
2159 Register carry, Register carry2,
2160 Register idx, Register jdx,
2161 Register yz_idx1, Register yz_idx2,
2162 Register tmp, Register tmp3, Register tmp4);
2163 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
2164 Register yz_idx, Register idx, Register jdx,
2165 Register carry, Register product,
2166 Register carry2);
2167 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
2168 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
2169 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
2170 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
2171 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
2172 Register tmp2);
2173 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
2174 Register rdxReg, Register raxReg);
2175 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
2176 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
2177 Register tmp3, Register tmp4);
2178 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
2179 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
2180
2181 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
2182 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
2183 Register raxReg);
2184 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
2185 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
2186 Register raxReg);
2187 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
2188 Register result, Register tmp1, Register tmp2,
2189 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
2190 #endif
2191
2192 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
2193 void update_byte_crc32(Register crc, Register val, Register table);
2194 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
2195
2196
2197 #ifdef _LP64
2198 void kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2);
2199 void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
2200 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
2201 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup);
2202 #endif // _LP64
2203
2204 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
2205 // Note on a naming convention:
2206 // Prefix w = register only used on a Westmere+ architecture
2207 // Prefix n = register only used on a Nehalem architecture
2208 #ifdef _LP64
2209 void crc32c_ipl_alg4(Register in_out, uint32_t n,
2210 Register tmp1, Register tmp2, Register tmp3);
2211 #else
2212 void crc32c_ipl_alg4(Register in_out, uint32_t n,
2213 Register tmp1, Register tmp2, Register tmp3,
2214 XMMRegister xtmp1, XMMRegister xtmp2);
2215 #endif
2216 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
2217 Register in_out,
2218 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
2219 XMMRegister w_xtmp2,
2220 Register tmp1,
2221 Register n_tmp2, Register n_tmp3);
2222 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
2223 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2224 Register tmp1, Register tmp2,
2225 Register n_tmp3);
2226 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
2227 Register in_out1, Register in_out2, Register in_out3,
2228 Register tmp1, Register tmp2, Register tmp3,
2229 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2230 Register tmp4, Register tmp5,
2231 Register n_tmp6);
2232 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
2233 Register tmp1, Register tmp2, Register tmp3,
2234 Register tmp4, Register tmp5, Register tmp6,
2235 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
2236 bool is_pclmulqdq_supported);
2237 // Fold 128-bit data chunk
2238 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
2239 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
2240 #ifdef _LP64
2241 // Fold 512-bit data chunk
2242 void fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, Register pos, int offset);
2243 #endif // _LP64
2244 // Fold 8-bit data
2245 void fold_8bit_crc32(Register crc, Register table, Register tmp);
2246 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
2247
2248 // Compress char[] array to byte[].
2249 void char_array_compress(Register src, Register dst, Register len,
2250 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
2251 XMMRegister tmp4, Register tmp5, Register result,
2252 KRegister mask1 = knoreg, KRegister mask2 = knoreg);
2253
2254 // Inflate byte[] array to char[].
2255 void byte_array_inflate(Register src, Register dst, Register len,
2256 XMMRegister tmp1, Register tmp2, KRegister mask = knoreg);
2257
2258 void fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
2259 Register length, Register temp, int vec_enc);
2260
2261 void fill64_masked(uint shift, Register dst, int disp,
2262 XMMRegister xmm, KRegister mask, Register length,
2263 Register temp, bool use64byteVector = false);
2264
2265 void fill32_masked(uint shift, Register dst, int disp,
2266 XMMRegister xmm, KRegister mask, Register length,
2267 Register temp);
2268
2269 void fill32(Address dst, XMMRegister xmm);
2270
2271 void fill32(Register dst, int disp, XMMRegister xmm);
2272
2273 void fill64(Address dst, XMMRegister xmm, bool use64byteVector = false);
2274
2275 void fill64(Register dst, int dis, XMMRegister xmm, bool use64byteVector = false);
2276
2277 #ifdef _LP64
2278 void convert_f2i(Register dst, XMMRegister src);
2279 void convert_d2i(Register dst, XMMRegister src);
2280 void convert_f2l(Register dst, XMMRegister src);
2281 void convert_d2l(Register dst, XMMRegister src);
2282 void round_double(Register dst, XMMRegister src, Register rtmp, Register rcx);
2283 void round_float(Register dst, XMMRegister src, Register rtmp, Register rcx);
2284
2285 void cache_wb(Address line);
2286 void cache_wbsync(bool is_pre);
2287
2288 #ifdef COMPILER2_OR_JVMCI
2289 void generate_fill_avx3(BasicType type, Register to, Register value,
2290 Register count, Register rtmp, XMMRegister xtmp);
2291 #endif // COMPILER2_OR_JVMCI
2292 #endif // _LP64
2293
2294 void vallones(XMMRegister dst, int vector_len);
2295
2296 void check_stack_alignment(Register sp, const char* msg, unsigned bias = 0, Register tmp = noreg);
2297
2298 void lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register thread, Register tmp, Label& slow);
2299 void lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow);
2300
2301 #ifdef _LP64
2302 void save_legacy_gprs();
2303 void restore_legacy_gprs();
2304 void setcc(Assembler::Condition comparison, Register dst);
2305 #endif
2306 };
2307
2308 #endif // CPU_X86_MACROASSEMBLER_X86_HPP