10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef _WINDOWS
26 #include "alloca.h"
27 #endif
28 #include "asm/macroAssembler.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/compiledIC.hpp"
32 #include "code/debugInfoRec.hpp"
33 #include "code/nativeInst.hpp"
34 #include "code/vtableStubs.hpp"
35 #include "compiler/oopMap.hpp"
36 #include "gc/shared/collectedHeap.hpp"
37 #include "gc/shared/gcLocker.hpp"
38 #include "gc/shared/barrierSet.hpp"
39 #include "gc/shared/barrierSetAssembler.hpp"
40 #include "interpreter/interpreter.hpp"
41 #include "logging/log.hpp"
42 #include "memory/resourceArea.hpp"
43 #include "memory/universe.hpp"
44 #include "oops/klass.inline.hpp"
45 #include "oops/method.inline.hpp"
46 #include "prims/methodHandles.hpp"
47 #include "runtime/continuation.hpp"
48 #include "runtime/continuationEntry.inline.hpp"
49 #include "runtime/globals.hpp"
617 break;
618 case T_DOUBLE:
619 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
620 if (fp_args < Argument::n_float_register_parameters_j) {
621 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
622 } else {
623 stk_args = align_up(stk_args, 2);
624 regs[i].set2(VMRegImpl::stack2reg(stk_args));
625 stk_args += 2;
626 }
627 break;
628 default:
629 ShouldNotReachHere();
630 break;
631 }
632 }
633
634 return stk_args;
635 }
636
637 // Patch the callers callsite with entry to compiled code if it exists.
638 static void patch_callers_callsite(MacroAssembler *masm) {
639 Label L;
640 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
641 __ jcc(Assembler::equal, L);
642
643 // Save the current stack pointer
644 __ mov(r13, rsp);
645 // Schedule the branch target address early.
646 // Call into the VM to patch the caller, then jump to compiled callee
647 // rax isn't live so capture return address while we easily can
648 __ movptr(rax, Address(rsp, 0));
649
650 // align stack so push_CPU_state doesn't fault
651 __ andptr(rsp, -(StackAlignmentInBytes));
652 __ push_CPU_state();
653 __ vzeroupper();
654 // VM needs caller's callsite
655 // VM needs target method
656 // This needs to be a long call since we will relocate this adapter to
659 // Allocate argument register save area
660 if (frame::arg_reg_save_area_bytes != 0) {
661 __ subptr(rsp, frame::arg_reg_save_area_bytes);
662 }
663 __ mov(c_rarg0, rbx);
664 __ mov(c_rarg1, rax);
665 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
666
667 // De-allocate argument register save area
668 if (frame::arg_reg_save_area_bytes != 0) {
669 __ addptr(rsp, frame::arg_reg_save_area_bytes);
670 }
671
672 __ vzeroupper();
673 __ pop_CPU_state();
674 // restore sp
675 __ mov(rsp, r13);
676 __ bind(L);
677 }
678
679 static void gen_c2i_adapter(MacroAssembler *masm,
680 int total_args_passed,
681 int comp_args_on_stack,
682 const BasicType *sig_bt,
683 const VMRegPair *regs,
684 Label& skip_fixup) {
685 // Before we get into the guts of the C2I adapter, see if we should be here
686 // at all. We've come from compiled code and are attempting to jump to the
687 // interpreter, which means the caller made a static call to get here
688 // (vcalls always get a compiled target if there is one). Check for a
689 // compiled target. If there is one, we need to patch the caller's call.
690 patch_callers_callsite(masm);
691
692 __ bind(skip_fixup);
693
694 // Since all args are passed on the stack, total_args_passed *
695 // Interpreter::stackElementSize is the space we need.
696
697 assert(total_args_passed >= 0, "total_args_passed is %d", total_args_passed);
698
699 int extraspace = (total_args_passed * Interpreter::stackElementSize);
700
701 // stack is aligned, keep it that way
702 // This is not currently needed or enforced by the interpreter, but
703 // we might as well conform to the ABI.
704 extraspace = align_up(extraspace, 2*wordSize);
705
706 // set senderSP value
707 __ lea(r13, Address(rsp, wordSize));
708
709 #ifdef ASSERT
710 __ check_stack_alignment(r13, "sender stack not aligned");
711 #endif
712 if (extraspace > 0) {
713 // Pop the return address
714 __ pop(rax);
715
716 __ subptr(rsp, extraspace);
717
718 // Push the return address
719 __ push(rax);
720
721 // Account for the return address location since we store it first rather
722 // than hold it in a register across all the shuffling
723 extraspace += wordSize;
724 }
725
726 #ifdef ASSERT
727 __ check_stack_alignment(rsp, "callee stack not aligned", wordSize, rax);
728 #endif
729
730 // Now write the args into the outgoing interpreter space
731 for (int i = 0; i < total_args_passed; i++) {
732 if (sig_bt[i] == T_VOID) {
733 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
734 continue;
735 }
736
737 // offset to start parameters
738 int st_off = (total_args_passed - i) * Interpreter::stackElementSize;
739 int next_off = st_off - Interpreter::stackElementSize;
740
741 // Say 4 args:
742 // i st_off
743 // 0 32 T_LONG
744 // 1 24 T_VOID
745 // 2 16 T_OBJECT
746 // 3 8 T_BOOL
747 // - 0 return address
748 //
749 // However to make thing extra confusing. Because we can fit a long/double in
750 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
751 // leaves one slot empty and only stores to a single slot. In this case the
752 // slot that is occupied is the T_VOID slot. See I said it was confusing.
753
754 VMReg r_1 = regs[i].first();
755 VMReg r_2 = regs[i].second();
756 if (!r_1->is_valid()) {
757 assert(!r_2->is_valid(), "");
758 continue;
759 }
760 if (r_1->is_stack()) {
761 // memory to memory use rax
762 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
763 if (!r_2->is_valid()) {
764 // sign extend??
765 __ movl(rax, Address(rsp, ld_off));
766 __ movptr(Address(rsp, st_off), rax);
767
768 } else {
769
770 __ movq(rax, Address(rsp, ld_off));
771
772 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
773 // T_DOUBLE and T_LONG use two slots in the interpreter
774 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
775 // ld_off == LSW, ld_off+wordSize == MSW
776 // st_off == MSW, next_off == LSW
777 __ movq(Address(rsp, next_off), rax);
778 #ifdef ASSERT
779 // Overwrite the unused slot with known junk
780 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
781 __ movptr(Address(rsp, st_off), rax);
782 #endif /* ASSERT */
783 } else {
784 __ movq(Address(rsp, st_off), rax);
785 }
786 }
787 } else if (r_1->is_Register()) {
788 Register r = r_1->as_Register();
789 if (!r_2->is_valid()) {
790 // must be only an int (or less ) so move only 32bits to slot
791 // why not sign extend??
792 __ movl(Address(rsp, st_off), r);
793 } else {
794 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
795 // T_DOUBLE and T_LONG use two slots in the interpreter
796 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
797 // long/double in gpr
798 #ifdef ASSERT
799 // Overwrite the unused slot with known junk
800 __ mov64(rax, CONST64(0xdeadffffdeadaaab));
801 __ movptr(Address(rsp, st_off), rax);
802 #endif /* ASSERT */
803 __ movq(Address(rsp, next_off), r);
804 } else {
805 __ movptr(Address(rsp, st_off), r);
806 }
807 }
808 } else {
809 assert(r_1->is_XMMRegister(), "");
810 if (!r_2->is_valid()) {
811 // only a float use just part of the slot
812 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
813 } else {
814 #ifdef ASSERT
815 // Overwrite the unused slot with known junk
816 __ mov64(rax, CONST64(0xdeadffffdeadaaac));
817 __ movptr(Address(rsp, st_off), rax);
818 #endif /* ASSERT */
819 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
820 }
821 }
822 }
823
824 // Schedule the branch target address early.
825 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
826 __ jmp(rcx);
827 }
828
829 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
830 int total_args_passed,
831 int comp_args_on_stack,
832 const BasicType *sig_bt,
833 const VMRegPair *regs) {
834
835 // Note: r13 contains the senderSP on entry. We must preserve it since
836 // we may do a i2c -> c2i transition if we lose a race where compiled
837 // code goes non-entrant while we get args ready.
838 // In addition we use r13 to locate all the interpreter args as
839 // we must align the stack to 16 bytes on an i2c entry else we
840 // lose alignment we expect in all compiled code and register
841 // save code can segv when fxsave instructions find improperly
842 // aligned stack pointer.
843
844 // Adapters can be frameless because they do not require the caller
845 // to perform additional cleanup work, such as correcting the stack pointer.
846 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
847 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
848 // even if a callee has modified the stack pointer.
849 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
850 // routinely repairs its caller's stack pointer (from sender_sp, which is set
851 // up via the senderSP register).
852 // In other words, if *either* the caller or callee is interpreted, we can
868 // Convert 4-byte c2 stack slots to words.
869 int comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
870
871 if (comp_args_on_stack) {
872 __ subptr(rsp, comp_words_on_stack * wordSize);
873 }
874
875 // Ensure compiled code always sees stack at proper alignment
876 __ andptr(rsp, -16);
877
878 // push the return address and misalign the stack that youngest frame always sees
879 // as far as the placement of the call instruction
880 __ push(rax);
881
882 // Put saved SP in another register
883 const Register saved_sp = rax;
884 __ movptr(saved_sp, r11);
885
886 // Will jump to the compiled code just as if compiled code was doing it.
887 // Pre-load the register-jump target early, to schedule it better.
888 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset())));
889
890 #if INCLUDE_JVMCI
891 if (EnableJVMCI) {
892 // check if this call should be routed towards a specific entry point
893 __ cmpptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
894 Label no_alternative_target;
895 __ jcc(Assembler::equal, no_alternative_target);
896 __ movptr(r11, Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
897 __ movptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
898 __ bind(no_alternative_target);
899 }
900 #endif // INCLUDE_JVMCI
901
902 // Now generate the shuffle code. Pick up all register args and move the
903 // rest through the floating point stack top.
904 for (int i = 0; i < total_args_passed; i++) {
905 if (sig_bt[i] == T_VOID) {
906 // Longs and doubles are passed in native word order, but misaligned
907 // in the 32-bit build.
908 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
909 continue;
910 }
911
912 // Pick up 0, 1 or 2 words from SP+offset.
913
914 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
915 "scrambled load targets?");
916 // Load in argument order going down.
917 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
918 // Point to interpreter value (vs. tag)
919 int next_off = ld_off - Interpreter::stackElementSize;
920 //
921 //
922 //
923 VMReg r_1 = regs[i].first();
924 VMReg r_2 = regs[i].second();
925 if (!r_1->is_valid()) {
926 assert(!r_2->is_valid(), "");
927 continue;
928 }
930 // Convert stack slot to an SP offset (+ wordSize to account for return address )
931 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
932
933 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
934 // and if we end up going thru a c2i because of a miss a reasonable value of r13
935 // will be generated.
936 if (!r_2->is_valid()) {
937 // sign extend???
938 __ movl(r13, Address(saved_sp, ld_off));
939 __ movptr(Address(rsp, st_off), r13);
940 } else {
941 //
942 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
943 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
944 // So we must adjust where to pick up the data to match the interpreter.
945 //
946 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
947 // are accessed as negative so LSW is at LOW address
948
949 // ld_off is MSW so get LSW
950 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
951 next_off : ld_off;
952 __ movq(r13, Address(saved_sp, offset));
953 // st_off is LSW (i.e. reg.first())
954 __ movq(Address(rsp, st_off), r13);
955 }
956 } else if (r_1->is_Register()) { // Register argument
957 Register r = r_1->as_Register();
958 assert(r != rax, "must be different");
959 if (r_2->is_valid()) {
960 //
961 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
962 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
963 // So we must adjust where to pick up the data to match the interpreter.
964
965 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
966 next_off : ld_off;
967
968 // this can be a misaligned move
969 __ movq(r, Address(saved_sp, offset));
970 } else {
971 // sign extend and use a full word?
972 __ movl(r, Address(saved_sp, ld_off));
973 }
974 } else {
975 if (!r_2->is_valid()) {
976 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
977 } else {
978 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
979 }
980 }
981 }
982
983 __ push_cont_fastpath(); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
984
985 // 6243940 We might end up in handle_wrong_method if
986 // the callee is deoptimized as we race thru here. If that
987 // happens we don't want to take a safepoint because the
988 // caller frame will look interpreted and arguments are now
989 // "compiled" so it is much better to make this transition
990 // invisible to the stack walking code. Unfortunately if
991 // we try and find the callee by normal means a safepoint
992 // is possible. So we stash the desired callee in the thread
993 // and the vm will find there should this case occur.
994
995 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
996
997 // put Method* where a c2i would expect should we end up there
998 // only needed because eof c2 resolve stubs return Method* as a result in
999 // rax
1000 __ mov(rax, rbx);
1001 __ jmp(r11);
1002 }
1003
1004 // ---------------------------------------------------------------
1005 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
1006 int total_args_passed,
1007 int comp_args_on_stack,
1008 const BasicType *sig_bt,
1009 const VMRegPair *regs,
1010 address entry_address[AdapterBlob::ENTRY_COUNT]) {
1011 entry_address[AdapterBlob::I2C] = __ pc();
1012
1013 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
1014
1015 // -------------------------------------------------------------------------
1016 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls
1017 // to the interpreter. The args start out packed in the compiled layout. They
1018 // need to be unpacked into the interpreter layout. This will almost always
1019 // require some stack space. We grow the current (compiled) stack, then repack
1020 // the args. We finally end in a jump to the generic interpreter entry point.
1021 // On exit from the interpreter, the interpreter will restore our SP (lest the
1022 // compiled code, which relies solely on SP and not RBP, get sick).
1023
1024 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
1025 Label skip_fixup;
1026
1027 Register data = rax;
1028 Register receiver = j_rarg0;
1029 Register temp = rbx;
1030
1031 {
1032 __ ic_check(1 /* end_alignment */);
1033 __ movptr(rbx, Address(data, CompiledICData::speculated_method_offset()));
1034 // Method might have been compiled since the call site was patched to
1035 // interpreted if that is the case treat it as a miss so we can get
1036 // the call site corrected.
1037 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
1038 __ jcc(Assembler::equal, skip_fixup);
1039 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1040 }
1041
1042 entry_address[AdapterBlob::C2I] = __ pc();
1043
1044 // Class initialization barrier for static methods
1045 entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
1046 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
1047 Label L_skip_barrier;
1048 Register method = rbx;
1049
1050 // Bypass the barrier for non-static methods
1051 Register flags = rscratch1;
1052 __ load_unsigned_short(flags, Address(method, Method::access_flags_offset()));
1053 __ testl(flags, JVM_ACC_STATIC);
1054 __ jcc(Assembler::zero, L_skip_barrier); // non-static
1055
1056 Register klass = rscratch1;
1057 __ load_method_holder(klass, method);
1058 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
1059
1060 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
1061
1062 __ bind(L_skip_barrier);
1063 entry_address[AdapterBlob::C2I_No_Clinit_Check] = __ pc();
1064
1065 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1066 bs->c2i_entry_barrier(masm);
1067
1068 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
1069 return;
1070 }
1071
1072 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1073 VMRegPair *regs,
1074 int total_args_passed) {
1075
1076 // We return the amount of VMRegImpl stack slots we need to reserve for all
1077 // the arguments NOT counting out_preserve_stack_slots.
1078
1079 // NOTE: These arrays will have to change when c1 is ported
1080 #ifdef _WIN64
1081 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1082 c_rarg0, c_rarg1, c_rarg2, c_rarg3
1083 };
1084 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
1085 c_farg0, c_farg1, c_farg2, c_farg3
1086 };
1087 #else
1088 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1089 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
3492 julong *scratch = (julong *)alloca(total_allocation);
3493
3494 // Local scratch arrays
3495 julong
3496 *a = scratch + 0 * longwords,
3497 *n = scratch + 1 * longwords,
3498 *m = scratch + 2 * longwords;
3499
3500 reverse_words((julong *)a_ints, a, longwords);
3501 reverse_words((julong *)n_ints, n, longwords);
3502
3503 if (len >= MONTGOMERY_SQUARING_THRESHOLD) {
3504 ::montgomery_square(a, n, m, (julong)inv, longwords);
3505 } else {
3506 ::montgomery_multiply(a, a, n, m, (julong)inv, longwords);
3507 }
3508
3509 reverse_words(m, (julong *)m_ints, longwords);
3510 }
3511
3512 #if INCLUDE_JFR
3513
3514 // For c2: c_rarg0 is junk, call to runtime to write a checkpoint.
3515 // It returns a jobject handle to the event writer.
3516 // The handle is dereferenced and the return value is the event writer oop.
3517 RuntimeStub* SharedRuntime::generate_jfr_write_checkpoint() {
3518 enum layout {
3519 rbp_off,
3520 rbpH_off,
3521 return_off,
3522 return_off2,
3523 framesize // inclusive of return address
3524 };
3525
3526 const char* name = SharedRuntime::stub_name(StubId::shared_jfr_write_checkpoint_id);
3527 CodeBuffer code(name, 1024, 64);
3528 MacroAssembler* masm = new MacroAssembler(&code);
3529 address start = __ pc();
3530
3531 __ enter();
|
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef _WINDOWS
26 #include "alloca.h"
27 #endif
28 #include "asm/macroAssembler.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "classfile/symbolTable.hpp"
31 #include "code/aotCodeCache.hpp"
32 #include "code/compiledIC.hpp"
33 #include "code/debugInfoRec.hpp"
34 #include "code/nativeInst.hpp"
35 #include "code/vtableStubs.hpp"
36 #include "compiler/oopMap.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/gcLocker.hpp"
39 #include "gc/shared/barrierSet.hpp"
40 #include "gc/shared/barrierSetAssembler.hpp"
41 #include "interpreter/interpreter.hpp"
42 #include "logging/log.hpp"
43 #include "memory/resourceArea.hpp"
44 #include "memory/universe.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "oops/method.inline.hpp"
47 #include "prims/methodHandles.hpp"
48 #include "runtime/continuation.hpp"
49 #include "runtime/continuationEntry.inline.hpp"
50 #include "runtime/globals.hpp"
618 break;
619 case T_DOUBLE:
620 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
621 if (fp_args < Argument::n_float_register_parameters_j) {
622 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
623 } else {
624 stk_args = align_up(stk_args, 2);
625 regs[i].set2(VMRegImpl::stack2reg(stk_args));
626 stk_args += 2;
627 }
628 break;
629 default:
630 ShouldNotReachHere();
631 break;
632 }
633 }
634
635 return stk_args;
636 }
637
638 // Same as java_calling_convention() but for multiple return
639 // values. There's no way to store them on the stack so if we don't
640 // have enough registers, multiple values can't be returned.
641 const uint SharedRuntime::java_return_convention_max_int = Argument::n_int_register_parameters_j+1;
642 const uint SharedRuntime::java_return_convention_max_float = Argument::n_float_register_parameters_j;
643 int SharedRuntime::java_return_convention(const BasicType *sig_bt,
644 VMRegPair *regs,
645 int total_args_passed) {
646 // Create the mapping between argument positions and
647 // registers.
648 static const Register INT_ArgReg[java_return_convention_max_int] = {
649 rax, j_rarg5, j_rarg4, j_rarg3, j_rarg2, j_rarg1, j_rarg0
650 };
651 static const XMMRegister FP_ArgReg[java_return_convention_max_float] = {
652 j_farg0, j_farg1, j_farg2, j_farg3,
653 j_farg4, j_farg5, j_farg6, j_farg7
654 };
655
656
657 uint int_args = 0;
658 uint fp_args = 0;
659
660 for (int i = 0; i < total_args_passed; i++) {
661 switch (sig_bt[i]) {
662 case T_BOOLEAN:
663 case T_CHAR:
664 case T_BYTE:
665 case T_SHORT:
666 case T_INT:
667 if (int_args < Argument::n_int_register_parameters_j+1) {
668 regs[i].set1(INT_ArgReg[int_args]->as_VMReg());
669 int_args++;
670 } else {
671 return -1;
672 }
673 break;
674 case T_VOID:
675 // halves of T_LONG or T_DOUBLE
676 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
677 regs[i].set_bad();
678 break;
679 case T_LONG:
680 assert(sig_bt[i + 1] == T_VOID, "expecting half");
681 // fall through
682 case T_OBJECT:
683 case T_ARRAY:
684 case T_ADDRESS:
685 case T_METADATA:
686 if (int_args < Argument::n_int_register_parameters_j+1) {
687 regs[i].set2(INT_ArgReg[int_args]->as_VMReg());
688 int_args++;
689 } else {
690 return -1;
691 }
692 break;
693 case T_FLOAT:
694 if (fp_args < Argument::n_float_register_parameters_j) {
695 regs[i].set1(FP_ArgReg[fp_args]->as_VMReg());
696 fp_args++;
697 } else {
698 return -1;
699 }
700 break;
701 case T_DOUBLE:
702 assert(sig_bt[i + 1] == T_VOID, "expecting half");
703 if (fp_args < Argument::n_float_register_parameters_j) {
704 regs[i].set2(FP_ArgReg[fp_args]->as_VMReg());
705 fp_args++;
706 } else {
707 return -1;
708 }
709 break;
710 default:
711 ShouldNotReachHere();
712 break;
713 }
714 }
715
716 return int_args + fp_args;
717 }
718
719 // Patch the callers callsite with entry to compiled code if it exists.
720 static void patch_callers_callsite(MacroAssembler *masm) {
721 Label L;
722 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
723 __ jcc(Assembler::equal, L);
724
725 // Save the current stack pointer
726 __ mov(r13, rsp);
727 // Schedule the branch target address early.
728 // Call into the VM to patch the caller, then jump to compiled callee
729 // rax isn't live so capture return address while we easily can
730 __ movptr(rax, Address(rsp, 0));
731
732 // align stack so push_CPU_state doesn't fault
733 __ andptr(rsp, -(StackAlignmentInBytes));
734 __ push_CPU_state();
735 __ vzeroupper();
736 // VM needs caller's callsite
737 // VM needs target method
738 // This needs to be a long call since we will relocate this adapter to
741 // Allocate argument register save area
742 if (frame::arg_reg_save_area_bytes != 0) {
743 __ subptr(rsp, frame::arg_reg_save_area_bytes);
744 }
745 __ mov(c_rarg0, rbx);
746 __ mov(c_rarg1, rax);
747 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
748
749 // De-allocate argument register save area
750 if (frame::arg_reg_save_area_bytes != 0) {
751 __ addptr(rsp, frame::arg_reg_save_area_bytes);
752 }
753
754 __ vzeroupper();
755 __ pop_CPU_state();
756 // restore sp
757 __ mov(rsp, r13);
758 __ bind(L);
759 }
760
761 // For each inline type argument, sig includes the list of fields of
762 // the inline type. This utility function computes the number of
763 // arguments for the call if inline types are passed by reference (the
764 // calling convention the interpreter expects).
765 static int compute_total_args_passed_int(const GrowableArray<SigEntry>* sig_extended) {
766 int total_args_passed = 0;
767 if (InlineTypePassFieldsAsArgs) {
768 for (int i = 0; i < sig_extended->length(); i++) {
769 BasicType bt = sig_extended->at(i)._bt;
770 if (bt == T_METADATA) {
771 // In sig_extended, an inline type argument starts with:
772 // T_METADATA, followed by the types of the fields of the
773 // inline type and T_VOID to mark the end of the value
774 // type. Inline types are flattened so, for instance, in the
775 // case of an inline type with an int field and an inline type
776 // field that itself has 2 fields, an int and a long:
777 // T_METADATA T_INT T_METADATA T_INT T_LONG T_VOID (second
778 // slot for the T_LONG) T_VOID (inner inline type) T_VOID
779 // (outer inline type)
780 total_args_passed++;
781 int vt = 1;
782 do {
783 i++;
784 BasicType bt = sig_extended->at(i)._bt;
785 BasicType prev_bt = sig_extended->at(i-1)._bt;
786 if (bt == T_METADATA) {
787 vt++;
788 } else if (bt == T_VOID &&
789 prev_bt != T_LONG &&
790 prev_bt != T_DOUBLE) {
791 vt--;
792 }
793 } while (vt != 0);
794 } else {
795 total_args_passed++;
796 }
797 }
798 } else {
799 total_args_passed = sig_extended->length();
800 }
801 return total_args_passed;
802 }
803
804
805 static void gen_c2i_adapter_helper(MacroAssembler* masm,
806 BasicType bt,
807 BasicType prev_bt,
808 size_t size_in_bytes,
809 const VMRegPair& reg_pair,
810 const Address& to,
811 int extraspace,
812 bool is_oop) {
813 if (bt == T_VOID) {
814 assert(prev_bt == T_LONG || prev_bt == T_DOUBLE, "missing half");
815 return;
816 }
817
818 // Say 4 args:
819 // i st_off
820 // 0 32 T_LONG
821 // 1 24 T_VOID
822 // 2 16 T_OBJECT
823 // 3 8 T_BOOL
824 // - 0 return address
825 //
826 // However to make thing extra confusing. Because we can fit a long/double in
827 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
828 // leaves one slot empty and only stores to a single slot. In this case the
829 // slot that is occupied is the T_VOID slot. See I said it was confusing.
830
831 bool wide = (size_in_bytes == wordSize);
832 VMReg r_1 = reg_pair.first();
833 VMReg r_2 = reg_pair.second();
834 assert(r_2->is_valid() == wide, "invalid size");
835 if (!r_1->is_valid()) {
836 assert(!r_2->is_valid(), "must be invalid");
837 return;
838 }
839
840 if (!r_1->is_XMMRegister()) {
841 Register val = rax;
842 if (r_1->is_stack()) {
843 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
844 __ load_sized_value(val, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
845 } else {
846 val = r_1->as_Register();
847 }
848 assert_different_registers(to.base(), val, rscratch1);
849 if (is_oop) {
850 __ push(r13);
851 __ push(rbx);
852 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep it valid.
853 __ push(to.base());
854 __ store_heap_oop(to, val, rscratch1, r13, rbx, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
855 __ pop(to.base());
856 __ pop(rbx);
857 __ pop(r13);
858 } else {
859 __ store_sized_value(to, val, size_in_bytes);
860 }
861 } else {
862 if (wide) {
863 __ movdbl(to, r_1->as_XMMRegister());
864 } else {
865 __ movflt(to, r_1->as_XMMRegister());
866 }
867 }
868 }
869
870 static void gen_c2i_adapter(MacroAssembler *masm,
871 const GrowableArray<SigEntry>* sig_extended,
872 const VMRegPair *regs,
873 bool requires_clinit_barrier,
874 address& c2i_no_clinit_check_entry,
875 Label& skip_fixup,
876 address start,
877 OopMapSet* oop_maps,
878 int& frame_complete,
879 int& frame_size_in_words,
880 bool alloc_inline_receiver) {
881 if (requires_clinit_barrier) {
882 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
883 Label L_skip_barrier;
884 Register method = rbx;
885
886 { // Bypass the barrier for non-static methods
887 Register flags = rscratch1;
888 __ load_unsigned_short(flags, Address(method, Method::access_flags_offset()));
889 __ testl(flags, JVM_ACC_STATIC);
890 __ jcc(Assembler::zero, L_skip_barrier); // non-static
891 }
892
893 Register klass = rscratch1;
894 __ load_method_holder(klass, method);
895 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
896
897 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
898
899 __ bind(L_skip_barrier);
900 c2i_no_clinit_check_entry = __ pc();
901 }
902
903 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
904 bs->c2i_entry_barrier(masm);
905
906 // Before we get into the guts of the C2I adapter, see if we should be here
907 // at all. We've come from compiled code and are attempting to jump to the
908 // interpreter, which means the caller made a static call to get here
909 // (vcalls always get a compiled target if there is one). Check for a
910 // compiled target. If there is one, we need to patch the caller's call.
911 patch_callers_callsite(masm);
912
913 __ bind(skip_fixup);
914
915 if (InlineTypePassFieldsAsArgs) {
916 // Is there an inline type argument?
917 bool has_inline_argument = false;
918 for (int i = 0; i < sig_extended->length() && !has_inline_argument; i++) {
919 has_inline_argument = (sig_extended->at(i)._bt == T_METADATA);
920 }
921 if (has_inline_argument) {
922 // There is at least an inline type argument: we're coming from
923 // compiled code so we have no buffers to back the inline types.
924 // Allocate the buffers here with a runtime call.
925 OopMap* map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, /*save_wide_vectors*/ false);
926
927 frame_complete = __ offset();
928
929 __ set_last_Java_frame(noreg, noreg, nullptr, rscratch1);
930
931 __ mov(c_rarg0, r15_thread);
932 __ mov(c_rarg1, rbx);
933 __ mov64(c_rarg2, (int64_t)alloc_inline_receiver);
934 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::allocate_inline_types)));
935
936 oop_maps->add_gc_map((int)(__ pc() - start), map);
937 __ reset_last_Java_frame(false);
938
939 RegisterSaver::restore_live_registers(masm);
940
941 Label no_exception;
942 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
943 __ jcc(Assembler::equal, no_exception);
944
945 __ movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
946 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
947 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
948
949 __ bind(no_exception);
950
951 // We get an array of objects from the runtime call
952 __ get_vm_result_oop(rscratch2); // Use rscratch2 (r11) as temporary because rscratch1 (r10) is trashed by movptr()
953 __ get_vm_result_metadata(rbx); // TODO: required to keep the callee Method live?
954 }
955 }
956
957 // Since all args are passed on the stack, total_args_passed *
958 // Interpreter::stackElementSize is the space we need.
959 int total_args_passed = compute_total_args_passed_int(sig_extended);
960 assert(total_args_passed >= 0, "total_args_passed is %d", total_args_passed);
961
962 int extraspace = (total_args_passed * Interpreter::stackElementSize);
963
964 // stack is aligned, keep it that way
965 // This is not currently needed or enforced by the interpreter, but
966 // we might as well conform to the ABI.
967 extraspace = align_up(extraspace, 2*wordSize);
968
969 // set senderSP value
970 __ lea(r13, Address(rsp, wordSize));
971
972 #ifdef ASSERT
973 __ check_stack_alignment(r13, "sender stack not aligned");
974 #endif
975 if (extraspace > 0) {
976 // Pop the return address
977 __ pop(rax);
978
979 __ subptr(rsp, extraspace);
980
981 // Push the return address
982 __ push(rax);
983
984 // Account for the return address location since we store it first rather
985 // than hold it in a register across all the shuffling
986 extraspace += wordSize;
987 }
988
989 #ifdef ASSERT
990 __ check_stack_alignment(rsp, "callee stack not aligned", wordSize, rax);
991 #endif
992
993 // Now write the args into the outgoing interpreter space
994
995 // next_arg_comp is the next argument from the compiler point of
996 // view (inline type fields are passed in registers/on the stack). In
997 // sig_extended, an inline type argument starts with: T_METADATA,
998 // followed by the types of the fields of the inline type and T_VOID
999 // to mark the end of the inline type. ignored counts the number of
1000 // T_METADATA/T_VOID. next_vt_arg is the next inline type argument:
1001 // used to get the buffer for that argument from the pool of buffers
1002 // we allocated above and want to pass to the
1003 // interpreter. next_arg_int is the next argument from the
1004 // interpreter point of view (inline types are passed by reference).
1005 for (int next_arg_comp = 0, ignored = 0, next_vt_arg = 0, next_arg_int = 0;
1006 next_arg_comp < sig_extended->length(); next_arg_comp++) {
1007 assert(ignored <= next_arg_comp, "shouldn't skip over more slots than there are arguments");
1008 assert(next_arg_int <= total_args_passed, "more arguments for the interpreter than expected?");
1009 BasicType bt = sig_extended->at(next_arg_comp)._bt;
1010 int st_off = (total_args_passed - next_arg_int) * Interpreter::stackElementSize;
1011 if (!InlineTypePassFieldsAsArgs || bt != T_METADATA) {
1012 int next_off = st_off - Interpreter::stackElementSize;
1013 const int offset = (bt == T_LONG || bt == T_DOUBLE) ? next_off : st_off;
1014 const VMRegPair reg_pair = regs[next_arg_comp-ignored];
1015 size_t size_in_bytes = reg_pair.second()->is_valid() ? 8 : 4;
1016 gen_c2i_adapter_helper(masm, bt, next_arg_comp > 0 ? sig_extended->at(next_arg_comp-1)._bt : T_ILLEGAL,
1017 size_in_bytes, reg_pair, Address(rsp, offset), extraspace, false);
1018 next_arg_int++;
1019 #ifdef ASSERT
1020 if (bt == T_LONG || bt == T_DOUBLE) {
1021 // Overwrite the unused slot with known junk
1022 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
1023 __ movptr(Address(rsp, st_off), rax);
1024 }
1025 #endif /* ASSERT */
1026 } else {
1027 ignored++;
1028 // get the buffer from the just allocated pool of buffers
1029 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + next_vt_arg * type2aelembytes(T_OBJECT);
1030 __ load_heap_oop(r14, Address(rscratch2, index));
1031 next_vt_arg++; next_arg_int++;
1032 int vt = 1;
1033 // write fields we get from compiled code in registers/stack
1034 // slots to the buffer: we know we are done with that inline type
1035 // argument when we hit the T_VOID that acts as an end of inline
1036 // type delimiter for this inline type. Inline types are flattened
1037 // so we might encounter embedded inline types. Each entry in
1038 // sig_extended contains a field offset in the buffer.
1039 Label L_null;
1040 do {
1041 next_arg_comp++;
1042 BasicType bt = sig_extended->at(next_arg_comp)._bt;
1043 BasicType prev_bt = sig_extended->at(next_arg_comp-1)._bt;
1044 if (bt == T_METADATA) {
1045 vt++;
1046 ignored++;
1047 } else if (bt == T_VOID &&
1048 prev_bt != T_LONG &&
1049 prev_bt != T_DOUBLE) {
1050 vt--;
1051 ignored++;
1052 } else {
1053 int off = sig_extended->at(next_arg_comp)._offset;
1054 if (off == -1) {
1055 // Nullable inline type argument, emit null check
1056 VMReg reg = regs[next_arg_comp-ignored].first();
1057 Label L_notNull;
1058 if (reg->is_stack()) {
1059 int ld_off = reg->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
1060 __ testb(Address(rsp, ld_off), 1);
1061 } else {
1062 __ testb(reg->as_Register(), 1);
1063 }
1064 __ jcc(Assembler::notZero, L_notNull);
1065 __ movptr(Address(rsp, st_off), 0);
1066 __ jmp(L_null);
1067 __ bind(L_notNull);
1068 continue;
1069 }
1070 assert(off > 0, "offset in object should be positive");
1071 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
1072 bool is_oop = is_reference_type(bt);
1073 gen_c2i_adapter_helper(masm, bt, next_arg_comp > 0 ? sig_extended->at(next_arg_comp-1)._bt : T_ILLEGAL,
1074 size_in_bytes, regs[next_arg_comp-ignored], Address(r14, off), extraspace, is_oop);
1075 }
1076 } while (vt != 0);
1077 // pass the buffer to the interpreter
1078 __ movptr(Address(rsp, st_off), r14);
1079 __ bind(L_null);
1080 }
1081 }
1082
1083 // Schedule the branch target address early.
1084 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
1085 __ jmp(rcx);
1086 }
1087
1088 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
1089 int comp_args_on_stack,
1090 const GrowableArray<SigEntry>* sig,
1091 const VMRegPair *regs) {
1092
1093 // Note: r13 contains the senderSP on entry. We must preserve it since
1094 // we may do a i2c -> c2i transition if we lose a race where compiled
1095 // code goes non-entrant while we get args ready.
1096 // In addition we use r13 to locate all the interpreter args as
1097 // we must align the stack to 16 bytes on an i2c entry else we
1098 // lose alignment we expect in all compiled code and register
1099 // save code can segv when fxsave instructions find improperly
1100 // aligned stack pointer.
1101
1102 // Adapters can be frameless because they do not require the caller
1103 // to perform additional cleanup work, such as correcting the stack pointer.
1104 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
1105 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
1106 // even if a callee has modified the stack pointer.
1107 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
1108 // routinely repairs its caller's stack pointer (from sender_sp, which is set
1109 // up via the senderSP register).
1110 // In other words, if *either* the caller or callee is interpreted, we can
1126 // Convert 4-byte c2 stack slots to words.
1127 int comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
1128
1129 if (comp_args_on_stack) {
1130 __ subptr(rsp, comp_words_on_stack * wordSize);
1131 }
1132
1133 // Ensure compiled code always sees stack at proper alignment
1134 __ andptr(rsp, -16);
1135
1136 // push the return address and misalign the stack that youngest frame always sees
1137 // as far as the placement of the call instruction
1138 __ push(rax);
1139
1140 // Put saved SP in another register
1141 const Register saved_sp = rax;
1142 __ movptr(saved_sp, r11);
1143
1144 // Will jump to the compiled code just as if compiled code was doing it.
1145 // Pre-load the register-jump target early, to schedule it better.
1146 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_inline_offset())));
1147
1148 #if INCLUDE_JVMCI
1149 if (EnableJVMCI) {
1150 // check if this call should be routed towards a specific entry point
1151 __ cmpptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
1152 Label no_alternative_target;
1153 __ jcc(Assembler::equal, no_alternative_target);
1154 __ movptr(r11, Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
1155 __ movptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
1156 __ bind(no_alternative_target);
1157 }
1158 #endif // INCLUDE_JVMCI
1159
1160 int total_args_passed = sig->length();
1161
1162 // Now generate the shuffle code. Pick up all register args and move the
1163 // rest through the floating point stack top.
1164 for (int i = 0; i < total_args_passed; i++) {
1165 BasicType bt = sig->at(i)._bt;
1166 if (bt == T_VOID) {
1167 // Longs and doubles are passed in native word order, but misaligned
1168 // in the 32-bit build.
1169 BasicType prev_bt = (i > 0) ? sig->at(i-1)._bt : T_ILLEGAL;
1170 assert(i > 0 && (prev_bt == T_LONG || prev_bt == T_DOUBLE), "missing half");
1171 continue;
1172 }
1173
1174 // Pick up 0, 1 or 2 words from SP+offset.
1175
1176 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
1177 "scrambled load targets?");
1178 // Load in argument order going down.
1179 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
1180 // Point to interpreter value (vs. tag)
1181 int next_off = ld_off - Interpreter::stackElementSize;
1182 //
1183 //
1184 //
1185 VMReg r_1 = regs[i].first();
1186 VMReg r_2 = regs[i].second();
1187 if (!r_1->is_valid()) {
1188 assert(!r_2->is_valid(), "");
1189 continue;
1190 }
1192 // Convert stack slot to an SP offset (+ wordSize to account for return address )
1193 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
1194
1195 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
1196 // and if we end up going thru a c2i because of a miss a reasonable value of r13
1197 // will be generated.
1198 if (!r_2->is_valid()) {
1199 // sign extend???
1200 __ movl(r13, Address(saved_sp, ld_off));
1201 __ movptr(Address(rsp, st_off), r13);
1202 } else {
1203 //
1204 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
1205 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
1206 // So we must adjust where to pick up the data to match the interpreter.
1207 //
1208 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
1209 // are accessed as negative so LSW is at LOW address
1210
1211 // ld_off is MSW so get LSW
1212 const int offset = (bt==T_LONG||bt==T_DOUBLE)?
1213 next_off : ld_off;
1214 __ movq(r13, Address(saved_sp, offset));
1215 // st_off is LSW (i.e. reg.first())
1216 __ movq(Address(rsp, st_off), r13);
1217 }
1218 } else if (r_1->is_Register()) { // Register argument
1219 Register r = r_1->as_Register();
1220 assert(r != rax, "must be different");
1221 if (r_2->is_valid()) {
1222 //
1223 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
1224 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
1225 // So we must adjust where to pick up the data to match the interpreter.
1226
1227 const int offset = (bt==T_LONG||bt==T_DOUBLE)?
1228 next_off : ld_off;
1229
1230 // this can be a misaligned move
1231 __ movq(r, Address(saved_sp, offset));
1232 } else {
1233 // sign extend and use a full word?
1234 __ movl(r, Address(saved_sp, ld_off));
1235 }
1236 } else {
1237 if (!r_2->is_valid()) {
1238 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
1239 } else {
1240 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
1241 }
1242 }
1243 }
1244
1245 __ push_cont_fastpath(); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
1246
1247 // 6243940 We might end up in handle_wrong_method if
1248 // the callee is deoptimized as we race thru here. If that
1249 // happens we don't want to take a safepoint because the
1250 // caller frame will look interpreted and arguments are now
1251 // "compiled" so it is much better to make this transition
1252 // invisible to the stack walking code. Unfortunately if
1253 // we try and find the callee by normal means a safepoint
1254 // is possible. So we stash the desired callee in the thread
1255 // and the vm will find there should this case occur.
1256
1257 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
1258
1259 // put Method* where a c2i would expect should we end up there
1260 // only needed because of c2 resolve stubs return Method* as a result in
1261 // rax
1262 __ mov(rax, rbx);
1263 __ jmp(r11);
1264 }
1265
1266 static void gen_inline_cache_check(MacroAssembler *masm, Label& skip_fixup) {
1267 Register data = rax;
1268 __ ic_check(1 /* end_alignment */);
1269 __ movptr(rbx, Address(data, CompiledICData::speculated_method_offset()));
1270
1271 // Method might have been compiled since the call site was patched to
1272 // interpreted if that is the case treat it as a miss so we can get
1273 // the call site corrected.
1274 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
1275 __ jcc(Assembler::equal, skip_fixup);
1276 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1277 }
1278
1279 // ---------------------------------------------------------------
1280 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler* masm,
1281 int comp_args_on_stack,
1282 const GrowableArray<SigEntry>* sig,
1283 const VMRegPair* regs,
1284 const GrowableArray<SigEntry>* sig_cc,
1285 const VMRegPair* regs_cc,
1286 const GrowableArray<SigEntry>* sig_cc_ro,
1287 const VMRegPair* regs_cc_ro,
1288 address entry_address[AdapterBlob::ENTRY_COUNT],
1289 AdapterBlob*& new_adapter,
1290 bool allocate_code_blob) {
1291 entry_address[AdapterBlob::I2C] = __ pc();
1292 gen_i2c_adapter(masm, comp_args_on_stack, sig, regs);
1293
1294 // -------------------------------------------------------------------------
1295 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls
1296 // to the interpreter. The args start out packed in the compiled layout. They
1297 // need to be unpacked into the interpreter layout. This will almost always
1298 // require some stack space. We grow the current (compiled) stack, then repack
1299 // the args. We finally end in a jump to the generic interpreter entry point.
1300 // On exit from the interpreter, the interpreter will restore our SP (lest the
1301 // compiled code, which relies solely on SP and not RBP, get sick).
1302
1303 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
1304 entry_address[AdapterBlob::C2I_Unverified_Inline] = __ pc();
1305 Label skip_fixup;
1306
1307 gen_inline_cache_check(masm, skip_fixup);
1308
1309 OopMapSet* oop_maps = new OopMapSet();
1310 int frame_complete = CodeOffsets::frame_never_safe;
1311 int frame_size_in_words = 0;
1312
1313 // Scalarized c2i adapter with non-scalarized receiver (i.e., don't pack receiver)
1314 entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
1315 entry_address[AdapterBlob::C2I_Inline_RO] = __ pc();
1316 if (regs_cc != regs_cc_ro) {
1317 // No class init barrier needed because method is guaranteed to be non-static
1318 gen_c2i_adapter(masm, sig_cc_ro, regs_cc_ro, /* requires_clinit_barrier = */ false, entry_address[AdapterBlob::C2I_No_Clinit_Check],
1319 skip_fixup, entry_address[AdapterBlob::I2C], oop_maps, frame_complete, frame_size_in_words, /* alloc_inline_receiver = */ false);
1320 skip_fixup.reset();
1321 }
1322
1323 // Scalarized c2i adapter
1324 entry_address[AdapterBlob::C2I] = __ pc();
1325 entry_address[AdapterBlob::C2I_Inline] = __ pc();
1326 gen_c2i_adapter(masm, sig_cc, regs_cc, /* requires_clinit_barrier = */ true, entry_address[AdapterBlob::C2I_No_Clinit_Check],
1327 skip_fixup, entry_address[AdapterBlob::I2C], oop_maps, frame_complete, frame_size_in_words, /* alloc_inline_receiver = */ true);
1328
1329 // Non-scalarized c2i adapter
1330 if (regs != regs_cc) {
1331 entry_address[AdapterBlob::C2I_Unverified_Inline] = __ pc();
1332 Label inline_entry_skip_fixup;
1333 gen_inline_cache_check(masm, inline_entry_skip_fixup);
1334
1335 entry_address[AdapterBlob::C2I_Inline] = __ pc();
1336 gen_c2i_adapter(masm, sig, regs, /* requires_clinit_barrier = */ true, entry_address[AdapterBlob::C2I_No_Clinit_Check],
1337 inline_entry_skip_fixup, entry_address[AdapterBlob::I2C], oop_maps, frame_complete, frame_size_in_words, /* alloc_inline_receiver = */ false);
1338 }
1339
1340 // The c2i adapters might safepoint and trigger a GC. The caller must make sure that
1341 // the GC knows about the location of oop argument locations passed to the c2i adapter.
1342 if (allocate_code_blob) {
1343 bool caller_must_gc_arguments = (regs != regs_cc);
1344 int entry_offset[AdapterHandlerEntry::ENTRIES_COUNT];
1345 assert(AdapterHandlerEntry::ENTRIES_COUNT == 7, "sanity");
1346 AdapterHandlerLibrary::address_to_offset(entry_address, entry_offset);
1347 new_adapter = AdapterBlob::create(masm->code(), entry_offset, frame_complete, frame_size_in_words, oop_maps, caller_must_gc_arguments);
1348 }
1349 }
1350
1351 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1352 VMRegPair *regs,
1353 int total_args_passed) {
1354
1355 // We return the amount of VMRegImpl stack slots we need to reserve for all
1356 // the arguments NOT counting out_preserve_stack_slots.
1357
1358 // NOTE: These arrays will have to change when c1 is ported
1359 #ifdef _WIN64
1360 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1361 c_rarg0, c_rarg1, c_rarg2, c_rarg3
1362 };
1363 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
1364 c_farg0, c_farg1, c_farg2, c_farg3
1365 };
1366 #else
1367 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1368 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
3771 julong *scratch = (julong *)alloca(total_allocation);
3772
3773 // Local scratch arrays
3774 julong
3775 *a = scratch + 0 * longwords,
3776 *n = scratch + 1 * longwords,
3777 *m = scratch + 2 * longwords;
3778
3779 reverse_words((julong *)a_ints, a, longwords);
3780 reverse_words((julong *)n_ints, n, longwords);
3781
3782 if (len >= MONTGOMERY_SQUARING_THRESHOLD) {
3783 ::montgomery_square(a, n, m, (julong)inv, longwords);
3784 } else {
3785 ::montgomery_multiply(a, a, n, m, (julong)inv, longwords);
3786 }
3787
3788 reverse_words(m, (julong *)m_ints, longwords);
3789 }
3790
3791 BufferedInlineTypeBlob* SharedRuntime::generate_buffered_inline_type_adapter(const InlineKlass* vk) {
3792 BufferBlob* buf = BufferBlob::create("inline types pack/unpack", 16 * K);
3793 if (buf == nullptr) {
3794 return nullptr;
3795 }
3796 CodeBuffer buffer(buf);
3797 short buffer_locs[20];
3798 buffer.insts()->initialize_shared_locs((relocInfo*)buffer_locs,
3799 sizeof(buffer_locs)/sizeof(relocInfo));
3800
3801 MacroAssembler* masm = new MacroAssembler(&buffer);
3802
3803 const Array<SigEntry>* sig_vk = vk->extended_sig();
3804 const Array<VMRegPair>* regs = vk->return_regs();
3805
3806 int pack_fields_jobject_off = __ offset();
3807 // Resolve pre-allocated buffer from JNI handle.
3808 // We cannot do this in generate_call_stub() because it requires GC code to be initialized.
3809 __ movptr(rax, Address(r13, 0));
3810 __ resolve_jobject(rax /* value */,
3811 r12 /* tmp */);
3812 __ movptr(Address(r13, 0), rax);
3813
3814 int pack_fields_off = __ offset();
3815
3816 int j = 1;
3817 for (int i = 0; i < sig_vk->length(); i++) {
3818 BasicType bt = sig_vk->at(i)._bt;
3819 if (bt == T_METADATA) {
3820 continue;
3821 }
3822 if (bt == T_VOID) {
3823 if (sig_vk->at(i-1)._bt == T_LONG ||
3824 sig_vk->at(i-1)._bt == T_DOUBLE) {
3825 j++;
3826 }
3827 continue;
3828 }
3829 int off = sig_vk->at(i)._offset;
3830 assert(off > 0, "offset in object should be positive");
3831 VMRegPair pair = regs->at(j);
3832 VMReg r_1 = pair.first();
3833 Address to(rax, off);
3834 if (bt == T_FLOAT) {
3835 __ movflt(to, r_1->as_XMMRegister());
3836 } else if (bt == T_DOUBLE) {
3837 __ movdbl(to, r_1->as_XMMRegister());
3838 } else {
3839 Register val = r_1->as_Register();
3840 assert_different_registers(to.base(), val, r14, r13, rbx, rscratch1);
3841 if (is_reference_type(bt)) {
3842 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep rax valid.
3843 __ mov(rbx, rax);
3844 Address to_with_rbx(rbx, off);
3845 __ store_heap_oop(to_with_rbx, val, r14, r13, rbx, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
3846 } else {
3847 __ store_sized_value(to, r_1->as_Register(), type2aelembytes(bt));
3848 }
3849 }
3850 j++;
3851 }
3852 assert(j == regs->length(), "missed a field?");
3853 if (vk->supports_nullable_layouts()) {
3854 // Set the null marker
3855 __ movb(Address(rax, vk->null_marker_offset()), 1);
3856 }
3857 __ ret(0);
3858
3859 int unpack_fields_off = __ offset();
3860
3861 Label skip;
3862 Label not_null;
3863 __ testptr(rax, rax);
3864 __ jcc(Assembler::notZero, not_null);
3865
3866 // Return value is null. Zero all registers because the runtime requires a canonical
3867 // representation of a flat null.
3868 j = 1;
3869 for (int i = 0; i < sig_vk->length(); i++) {
3870 BasicType bt = sig_vk->at(i)._bt;
3871 if (bt == T_METADATA) {
3872 continue;
3873 }
3874 if (bt == T_VOID) {
3875 if (sig_vk->at(i-1)._bt == T_LONG ||
3876 sig_vk->at(i-1)._bt == T_DOUBLE) {
3877 j++;
3878 }
3879 continue;
3880 }
3881
3882 VMRegPair pair = regs->at(j);
3883 VMReg r_1 = pair.first();
3884 if (r_1->is_XMMRegister()) {
3885 __ xorps(r_1->as_XMMRegister(), r_1->as_XMMRegister());
3886 } else {
3887 __ xorl(r_1->as_Register(), r_1->as_Register());
3888 }
3889 j++;
3890 }
3891 __ jmp(skip);
3892 __ bind(not_null);
3893
3894 j = 1;
3895 for (int i = 0; i < sig_vk->length(); i++) {
3896 BasicType bt = sig_vk->at(i)._bt;
3897 if (bt == T_METADATA) {
3898 continue;
3899 }
3900 if (bt == T_VOID) {
3901 if (sig_vk->at(i-1)._bt == T_LONG ||
3902 sig_vk->at(i-1)._bt == T_DOUBLE) {
3903 j++;
3904 }
3905 continue;
3906 }
3907 int off = sig_vk->at(i)._offset;
3908 assert(off > 0, "offset in object should be positive");
3909 VMRegPair pair = regs->at(j);
3910 VMReg r_1 = pair.first();
3911 VMReg r_2 = pair.second();
3912 Address from(rax, off);
3913 if (bt == T_FLOAT) {
3914 __ movflt(r_1->as_XMMRegister(), from);
3915 } else if (bt == T_DOUBLE) {
3916 __ movdbl(r_1->as_XMMRegister(), from);
3917 } else if (bt == T_OBJECT || bt == T_ARRAY) {
3918 assert_different_registers(rax, r_1->as_Register());
3919 __ load_heap_oop(r_1->as_Register(), from);
3920 } else {
3921 assert(is_java_primitive(bt), "unexpected basic type");
3922 assert_different_registers(rax, r_1->as_Register());
3923 size_t size_in_bytes = type2aelembytes(bt);
3924 __ load_sized_value(r_1->as_Register(), from, size_in_bytes, bt != T_CHAR && bt != T_BOOLEAN);
3925 }
3926 j++;
3927 }
3928 assert(j == regs->length(), "missed a field?");
3929
3930 __ bind(skip);
3931 __ ret(0);
3932
3933 __ flush();
3934
3935 return BufferedInlineTypeBlob::create(&buffer, pack_fields_off, pack_fields_jobject_off, unpack_fields_off);
3936 }
3937
3938 #if INCLUDE_JFR
3939
3940 // For c2: c_rarg0 is junk, call to runtime to write a checkpoint.
3941 // It returns a jobject handle to the event writer.
3942 // The handle is dereferenced and the return value is the event writer oop.
3943 RuntimeStub* SharedRuntime::generate_jfr_write_checkpoint() {
3944 enum layout {
3945 rbp_off,
3946 rbpH_off,
3947 return_off,
3948 return_off2,
3949 framesize // inclusive of return address
3950 };
3951
3952 const char* name = SharedRuntime::stub_name(StubId::shared_jfr_write_checkpoint_id);
3953 CodeBuffer code(name, 1024, 64);
3954 MacroAssembler* masm = new MacroAssembler(&code);
3955 address start = __ pc();
3956
3957 __ enter();
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