10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef _WINDOWS
26 #include "alloca.h"
27 #endif
28 #include "asm/macroAssembler.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/compiledIC.hpp"
32 #include "code/debugInfoRec.hpp"
33 #include "code/nativeInst.hpp"
34 #include "code/vtableStubs.hpp"
35 #include "compiler/oopMap.hpp"
36 #include "gc/shared/collectedHeap.hpp"
37 #include "gc/shared/gcLocker.hpp"
38 #include "gc/shared/barrierSet.hpp"
39 #include "gc/shared/barrierSetAssembler.hpp"
40 #include "interpreter/interpreter.hpp"
41 #include "logging/log.hpp"
42 #include "memory/resourceArea.hpp"
43 #include "memory/universe.hpp"
44 #include "oops/klass.inline.hpp"
45 #include "oops/method.inline.hpp"
46 #include "prims/methodHandles.hpp"
47 #include "runtime/continuation.hpp"
48 #include "runtime/continuationEntry.inline.hpp"
49 #include "runtime/globals.hpp"
614 break;
615 case T_DOUBLE:
616 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
617 if (fp_args < Argument::n_float_register_parameters_j) {
618 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
619 } else {
620 stk_args = align_up(stk_args, 2);
621 regs[i].set2(VMRegImpl::stack2reg(stk_args));
622 stk_args += 2;
623 }
624 break;
625 default:
626 ShouldNotReachHere();
627 break;
628 }
629 }
630
631 return stk_args;
632 }
633
634 // Patch the callers callsite with entry to compiled code if it exists.
635 static void patch_callers_callsite(MacroAssembler *masm) {
636 Label L;
637 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
638 __ jcc(Assembler::equal, L);
639
640 // Save the current stack pointer
641 __ mov(r13, rsp);
642 // Schedule the branch target address early.
643 // Call into the VM to patch the caller, then jump to compiled callee
644 // rax isn't live so capture return address while we easily can
645 __ movptr(rax, Address(rsp, 0));
646
647 // align stack so push_CPU_state doesn't fault
648 __ andptr(rsp, -(StackAlignmentInBytes));
649 __ push_CPU_state();
650 __ vzeroupper();
651 // VM needs caller's callsite
652 // VM needs target method
653 // This needs to be a long call since we will relocate this adapter to
656 // Allocate argument register save area
657 if (frame::arg_reg_save_area_bytes != 0) {
658 __ subptr(rsp, frame::arg_reg_save_area_bytes);
659 }
660 __ mov(c_rarg0, rbx);
661 __ mov(c_rarg1, rax);
662 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
663
664 // De-allocate argument register save area
665 if (frame::arg_reg_save_area_bytes != 0) {
666 __ addptr(rsp, frame::arg_reg_save_area_bytes);
667 }
668
669 __ vzeroupper();
670 __ pop_CPU_state();
671 // restore sp
672 __ mov(rsp, r13);
673 __ bind(L);
674 }
675
676 static void gen_c2i_adapter(MacroAssembler *masm,
677 int total_args_passed,
678 int comp_args_on_stack,
679 const BasicType *sig_bt,
680 const VMRegPair *regs,
681 Label& skip_fixup) {
682 // Before we get into the guts of the C2I adapter, see if we should be here
683 // at all. We've come from compiled code and are attempting to jump to the
684 // interpreter, which means the caller made a static call to get here
685 // (vcalls always get a compiled target if there is one). Check for a
686 // compiled target. If there is one, we need to patch the caller's call.
687 patch_callers_callsite(masm);
688
689 __ bind(skip_fixup);
690
691 // Since all args are passed on the stack, total_args_passed *
692 // Interpreter::stackElementSize is the space we need.
693
694 assert(total_args_passed >= 0, "total_args_passed is %d", total_args_passed);
695
696 int extraspace = (total_args_passed * Interpreter::stackElementSize);
697
698 // stack is aligned, keep it that way
699 // This is not currently needed or enforced by the interpreter, but
700 // we might as well conform to the ABI.
701 extraspace = align_up(extraspace, 2*wordSize);
702
703 // set senderSP value
704 __ lea(r13, Address(rsp, wordSize));
705
706 #ifdef ASSERT
707 __ check_stack_alignment(r13, "sender stack not aligned");
708 #endif
709 if (extraspace > 0) {
710 // Pop the return address
711 __ pop(rax);
712
713 __ subptr(rsp, extraspace);
714
715 // Push the return address
716 __ push(rax);
717
718 // Account for the return address location since we store it first rather
719 // than hold it in a register across all the shuffling
720 extraspace += wordSize;
721 }
722
723 #ifdef ASSERT
724 __ check_stack_alignment(rsp, "callee stack not aligned", wordSize, rax);
725 #endif
726
727 // Now write the args into the outgoing interpreter space
728 for (int i = 0; i < total_args_passed; i++) {
729 if (sig_bt[i] == T_VOID) {
730 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
731 continue;
732 }
733
734 // offset to start parameters
735 int st_off = (total_args_passed - i) * Interpreter::stackElementSize;
736 int next_off = st_off - Interpreter::stackElementSize;
737
738 // Say 4 args:
739 // i st_off
740 // 0 32 T_LONG
741 // 1 24 T_VOID
742 // 2 16 T_OBJECT
743 // 3 8 T_BOOL
744 // - 0 return address
745 //
746 // However to make thing extra confusing. Because we can fit a long/double in
747 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
748 // leaves one slot empty and only stores to a single slot. In this case the
749 // slot that is occupied is the T_VOID slot. See I said it was confusing.
750
751 VMReg r_1 = regs[i].first();
752 VMReg r_2 = regs[i].second();
753 if (!r_1->is_valid()) {
754 assert(!r_2->is_valid(), "");
755 continue;
756 }
757 if (r_1->is_stack()) {
758 // memory to memory use rax
759 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
760 if (!r_2->is_valid()) {
761 // sign extend??
762 __ movl(rax, Address(rsp, ld_off));
763 __ movptr(Address(rsp, st_off), rax);
764
765 } else {
766
767 __ movq(rax, Address(rsp, ld_off));
768
769 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
770 // T_DOUBLE and T_LONG use two slots in the interpreter
771 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
772 // ld_off == LSW, ld_off+wordSize == MSW
773 // st_off == MSW, next_off == LSW
774 __ movq(Address(rsp, next_off), rax);
775 #ifdef ASSERT
776 // Overwrite the unused slot with known junk
777 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
778 __ movptr(Address(rsp, st_off), rax);
779 #endif /* ASSERT */
780 } else {
781 __ movq(Address(rsp, st_off), rax);
782 }
783 }
784 } else if (r_1->is_Register()) {
785 Register r = r_1->as_Register();
786 if (!r_2->is_valid()) {
787 // must be only an int (or less ) so move only 32bits to slot
788 // why not sign extend??
789 __ movl(Address(rsp, st_off), r);
790 } else {
791 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
792 // T_DOUBLE and T_LONG use two slots in the interpreter
793 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
794 // long/double in gpr
795 #ifdef ASSERT
796 // Overwrite the unused slot with known junk
797 __ mov64(rax, CONST64(0xdeadffffdeadaaab));
798 __ movptr(Address(rsp, st_off), rax);
799 #endif /* ASSERT */
800 __ movq(Address(rsp, next_off), r);
801 } else {
802 __ movptr(Address(rsp, st_off), r);
803 }
804 }
805 } else {
806 assert(r_1->is_XMMRegister(), "");
807 if (!r_2->is_valid()) {
808 // only a float use just part of the slot
809 __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
810 } else {
811 #ifdef ASSERT
812 // Overwrite the unused slot with known junk
813 __ mov64(rax, CONST64(0xdeadffffdeadaaac));
814 __ movptr(Address(rsp, st_off), rax);
815 #endif /* ASSERT */
816 __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
817 }
818 }
819 }
820
821 // Schedule the branch target address early.
822 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
823 __ jmp(rcx);
824 }
825
826 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
827 int total_args_passed,
828 int comp_args_on_stack,
829 const BasicType *sig_bt,
830 const VMRegPair *regs) {
831
832 // Note: r13 contains the senderSP on entry. We must preserve it since
833 // we may do a i2c -> c2i transition if we lose a race where compiled
834 // code goes non-entrant while we get args ready.
835 // In addition we use r13 to locate all the interpreter args as
836 // we must align the stack to 16 bytes on an i2c entry else we
837 // lose alignment we expect in all compiled code and register
838 // save code can segv when fxsave instructions find improperly
839 // aligned stack pointer.
840
841 // Adapters can be frameless because they do not require the caller
842 // to perform additional cleanup work, such as correcting the stack pointer.
843 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
844 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
845 // even if a callee has modified the stack pointer.
846 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
847 // routinely repairs its caller's stack pointer (from sender_sp, which is set
848 // up via the senderSP register).
849 // In other words, if *either* the caller or callee is interpreted, we can
865 // Convert 4-byte c2 stack slots to words.
866 int comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
867
868 if (comp_args_on_stack) {
869 __ subptr(rsp, comp_words_on_stack * wordSize);
870 }
871
872 // Ensure compiled code always sees stack at proper alignment
873 __ andptr(rsp, -16);
874
875 // push the return address and misalign the stack that youngest frame always sees
876 // as far as the placement of the call instruction
877 __ push(rax);
878
879 // Put saved SP in another register
880 const Register saved_sp = rax;
881 __ movptr(saved_sp, r11);
882
883 // Will jump to the compiled code just as if compiled code was doing it.
884 // Pre-load the register-jump target early, to schedule it better.
885 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset())));
886
887 // Now generate the shuffle code. Pick up all register args and move the
888 // rest through the floating point stack top.
889 for (int i = 0; i < total_args_passed; i++) {
890 if (sig_bt[i] == T_VOID) {
891 // Longs and doubles are passed in native word order, but misaligned
892 // in the 32-bit build.
893 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
894 continue;
895 }
896
897 // Pick up 0, 1 or 2 words from SP+offset.
898
899 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
900 "scrambled load targets?");
901 // Load in argument order going down.
902 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
903 // Point to interpreter value (vs. tag)
904 int next_off = ld_off - Interpreter::stackElementSize;
905 //
906 //
907 //
908 VMReg r_1 = regs[i].first();
909 VMReg r_2 = regs[i].second();
910 if (!r_1->is_valid()) {
911 assert(!r_2->is_valid(), "");
912 continue;
913 }
915 // Convert stack slot to an SP offset (+ wordSize to account for return address )
916 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
917
918 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
919 // and if we end up going thru a c2i because of a miss a reasonable value of r13
920 // will be generated.
921 if (!r_2->is_valid()) {
922 // sign extend???
923 __ movl(r13, Address(saved_sp, ld_off));
924 __ movptr(Address(rsp, st_off), r13);
925 } else {
926 //
927 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
928 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
929 // So we must adjust where to pick up the data to match the interpreter.
930 //
931 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
932 // are accessed as negative so LSW is at LOW address
933
934 // ld_off is MSW so get LSW
935 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
936 next_off : ld_off;
937 __ movq(r13, Address(saved_sp, offset));
938 // st_off is LSW (i.e. reg.first())
939 __ movq(Address(rsp, st_off), r13);
940 }
941 } else if (r_1->is_Register()) { // Register argument
942 Register r = r_1->as_Register();
943 assert(r != rax, "must be different");
944 if (r_2->is_valid()) {
945 //
946 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
947 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
948 // So we must adjust where to pick up the data to match the interpreter.
949
950 const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
951 next_off : ld_off;
952
953 // this can be a misaligned move
954 __ movq(r, Address(saved_sp, offset));
955 } else {
956 // sign extend and use a full word?
957 __ movl(r, Address(saved_sp, ld_off));
958 }
959 } else {
960 if (!r_2->is_valid()) {
961 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
962 } else {
963 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
964 }
965 }
966 }
967
968 __ push_cont_fastpath(); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
969
970 // 6243940 We might end up in handle_wrong_method if
971 // the callee is deoptimized as we race thru here. If that
972 // happens we don't want to take a safepoint because the
973 // caller frame will look interpreted and arguments are now
974 // "compiled" so it is much better to make this transition
975 // invisible to the stack walking code. Unfortunately if
976 // we try and find the callee by normal means a safepoint
977 // is possible. So we stash the desired callee in the thread
978 // and the vm will find there should this case occur.
979
980 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
981
982 // put Method* where a c2i would expect should we end up there
983 // only needed because eof c2 resolve stubs return Method* as a result in
984 // rax
985 __ mov(rax, rbx);
986 __ jmp(r11);
987 }
988
989 // ---------------------------------------------------------------
990 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
991 int total_args_passed,
992 int comp_args_on_stack,
993 const BasicType *sig_bt,
994 const VMRegPair *regs,
995 address entry_address[AdapterBlob::ENTRY_COUNT]) {
996 entry_address[AdapterBlob::I2C] = __ pc();
997
998 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
999
1000 // -------------------------------------------------------------------------
1001 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls
1002 // to the interpreter. The args start out packed in the compiled layout. They
1003 // need to be unpacked into the interpreter layout. This will almost always
1004 // require some stack space. We grow the current (compiled) stack, then repack
1005 // the args. We finally end in a jump to the generic interpreter entry point.
1006 // On exit from the interpreter, the interpreter will restore our SP (lest the
1007 // compiled code, which relies solely on SP and not RBP, get sick).
1008
1009 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
1010 Label skip_fixup;
1011
1012 Register data = rax;
1013 Register receiver = j_rarg0;
1014 Register temp = rbx;
1015
1016 {
1017 __ ic_check(1 /* end_alignment */);
1018 __ movptr(rbx, Address(data, CompiledICData::speculated_method_offset()));
1019 // Method might have been compiled since the call site was patched to
1020 // interpreted if that is the case treat it as a miss so we can get
1021 // the call site corrected.
1022 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
1023 __ jcc(Assembler::equal, skip_fixup);
1024 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1025 }
1026
1027 entry_address[AdapterBlob::C2I] = __ pc();
1028
1029 // Class initialization barrier for static methods
1030 entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
1031 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
1032 Label L_skip_barrier;
1033 Register method = rbx;
1034
1035 // Bypass the barrier for non-static methods
1036 Register flags = rscratch1;
1037 __ load_unsigned_short(flags, Address(method, Method::access_flags_offset()));
1038 __ testl(flags, JVM_ACC_STATIC);
1039 __ jcc(Assembler::zero, L_skip_barrier); // non-static
1040
1041 Register klass = rscratch1;
1042 __ load_method_holder(klass, method);
1043 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
1044
1045 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
1046
1047 __ bind(L_skip_barrier);
1048 entry_address[AdapterBlob::C2I_No_Clinit_Check] = __ pc();
1049
1050 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1051 bs->c2i_entry_barrier(masm);
1052
1053 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
1054 return;
1055 }
1056
1057 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1058 VMRegPair *regs,
1059 int total_args_passed) {
1060
1061 // We return the amount of VMRegImpl stack slots we need to reserve for all
1062 // the arguments NOT counting out_preserve_stack_slots.
1063
1064 // NOTE: These arrays will have to change when c1 is ported
1065 #ifdef _WIN64
1066 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1067 c_rarg0, c_rarg1, c_rarg2, c_rarg3
1068 };
1069 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
1070 c_farg0, c_farg1, c_farg2, c_farg3
1071 };
1072 #else
1073 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1074 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
3420 julong *scratch = (julong *)alloca(total_allocation);
3421
3422 // Local scratch arrays
3423 julong
3424 *a = scratch + 0 * longwords,
3425 *n = scratch + 1 * longwords,
3426 *m = scratch + 2 * longwords;
3427
3428 reverse_words((julong *)a_ints, a, longwords);
3429 reverse_words((julong *)n_ints, n, longwords);
3430
3431 if (len >= MONTGOMERY_SQUARING_THRESHOLD) {
3432 ::montgomery_square(a, n, m, (julong)inv, longwords);
3433 } else {
3434 ::montgomery_multiply(a, a, n, m, (julong)inv, longwords);
3435 }
3436
3437 reverse_words(m, (julong *)m_ints, longwords);
3438 }
3439
3440 #if INCLUDE_JFR
3441
3442 // For c2: c_rarg0 is junk, call to runtime to write a checkpoint.
3443 // It returns a jobject handle to the event writer.
3444 // The handle is dereferenced and the return value is the event writer oop.
3445 RuntimeStub* SharedRuntime::generate_jfr_write_checkpoint() {
3446 enum layout {
3447 rbp_off,
3448 rbpH_off,
3449 return_off,
3450 return_off2,
3451 framesize // inclusive of return address
3452 };
3453
3454 const char* name = SharedRuntime::stub_name(StubId::shared_jfr_write_checkpoint_id);
3455 CodeBuffer code(name, 1024, 64);
3456 MacroAssembler* masm = new MacroAssembler(&code);
3457 address start = __ pc();
3458
3459 __ enter();
|
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef _WINDOWS
26 #include "alloca.h"
27 #endif
28 #include "asm/macroAssembler.hpp"
29 #include "asm/macroAssembler.inline.hpp"
30 #include "classfile/symbolTable.hpp"
31 #include "code/aotCodeCache.hpp"
32 #include "code/compiledIC.hpp"
33 #include "code/debugInfoRec.hpp"
34 #include "code/nativeInst.hpp"
35 #include "code/vtableStubs.hpp"
36 #include "compiler/oopMap.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/gcLocker.hpp"
39 #include "gc/shared/barrierSet.hpp"
40 #include "gc/shared/barrierSetAssembler.hpp"
41 #include "interpreter/interpreter.hpp"
42 #include "logging/log.hpp"
43 #include "memory/resourceArea.hpp"
44 #include "memory/universe.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "oops/method.inline.hpp"
47 #include "prims/methodHandles.hpp"
48 #include "runtime/continuation.hpp"
49 #include "runtime/continuationEntry.inline.hpp"
50 #include "runtime/globals.hpp"
615 break;
616 case T_DOUBLE:
617 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
618 if (fp_args < Argument::n_float_register_parameters_j) {
619 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
620 } else {
621 stk_args = align_up(stk_args, 2);
622 regs[i].set2(VMRegImpl::stack2reg(stk_args));
623 stk_args += 2;
624 }
625 break;
626 default:
627 ShouldNotReachHere();
628 break;
629 }
630 }
631
632 return stk_args;
633 }
634
635 // Same as java_calling_convention() but for multiple return
636 // values. There's no way to store them on the stack so if we don't
637 // have enough registers, multiple values can't be returned.
638 const uint SharedRuntime::java_return_convention_max_int = Argument::n_int_register_parameters_j+1;
639 const uint SharedRuntime::java_return_convention_max_float = Argument::n_float_register_parameters_j;
640 int SharedRuntime::java_return_convention(const BasicType *sig_bt,
641 VMRegPair *regs,
642 int total_args_passed) {
643 // Create the mapping between argument positions and
644 // registers.
645 static const Register INT_ArgReg[java_return_convention_max_int] = {
646 rax, j_rarg5, j_rarg4, j_rarg3, j_rarg2, j_rarg1, j_rarg0
647 };
648 static const XMMRegister FP_ArgReg[java_return_convention_max_float] = {
649 j_farg0, j_farg1, j_farg2, j_farg3,
650 j_farg4, j_farg5, j_farg6, j_farg7
651 };
652
653
654 uint int_args = 0;
655 uint fp_args = 0;
656
657 for (int i = 0; i < total_args_passed; i++) {
658 switch (sig_bt[i]) {
659 case T_BOOLEAN:
660 case T_CHAR:
661 case T_BYTE:
662 case T_SHORT:
663 case T_INT:
664 if (int_args < Argument::n_int_register_parameters_j+1) {
665 regs[i].set1(INT_ArgReg[int_args]->as_VMReg());
666 int_args++;
667 } else {
668 return -1;
669 }
670 break;
671 case T_VOID:
672 // halves of T_LONG or T_DOUBLE
673 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
674 regs[i].set_bad();
675 break;
676 case T_LONG:
677 assert(sig_bt[i + 1] == T_VOID, "expecting half");
678 // fall through
679 case T_OBJECT:
680 case T_ARRAY:
681 case T_ADDRESS:
682 case T_METADATA:
683 if (int_args < Argument::n_int_register_parameters_j+1) {
684 regs[i].set2(INT_ArgReg[int_args]->as_VMReg());
685 int_args++;
686 } else {
687 return -1;
688 }
689 break;
690 case T_FLOAT:
691 if (fp_args < Argument::n_float_register_parameters_j) {
692 regs[i].set1(FP_ArgReg[fp_args]->as_VMReg());
693 fp_args++;
694 } else {
695 return -1;
696 }
697 break;
698 case T_DOUBLE:
699 assert(sig_bt[i + 1] == T_VOID, "expecting half");
700 if (fp_args < Argument::n_float_register_parameters_j) {
701 regs[i].set2(FP_ArgReg[fp_args]->as_VMReg());
702 fp_args++;
703 } else {
704 return -1;
705 }
706 break;
707 default:
708 ShouldNotReachHere();
709 break;
710 }
711 }
712
713 return int_args + fp_args;
714 }
715
716 // Patch the callers callsite with entry to compiled code if it exists.
717 static void patch_callers_callsite(MacroAssembler *masm) {
718 Label L;
719 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
720 __ jcc(Assembler::equal, L);
721
722 // Save the current stack pointer
723 __ mov(r13, rsp);
724 // Schedule the branch target address early.
725 // Call into the VM to patch the caller, then jump to compiled callee
726 // rax isn't live so capture return address while we easily can
727 __ movptr(rax, Address(rsp, 0));
728
729 // align stack so push_CPU_state doesn't fault
730 __ andptr(rsp, -(StackAlignmentInBytes));
731 __ push_CPU_state();
732 __ vzeroupper();
733 // VM needs caller's callsite
734 // VM needs target method
735 // This needs to be a long call since we will relocate this adapter to
738 // Allocate argument register save area
739 if (frame::arg_reg_save_area_bytes != 0) {
740 __ subptr(rsp, frame::arg_reg_save_area_bytes);
741 }
742 __ mov(c_rarg0, rbx);
743 __ mov(c_rarg1, rax);
744 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
745
746 // De-allocate argument register save area
747 if (frame::arg_reg_save_area_bytes != 0) {
748 __ addptr(rsp, frame::arg_reg_save_area_bytes);
749 }
750
751 __ vzeroupper();
752 __ pop_CPU_state();
753 // restore sp
754 __ mov(rsp, r13);
755 __ bind(L);
756 }
757
758 // For each inline type argument, sig includes the list of fields of
759 // the inline type. This utility function computes the number of
760 // arguments for the call if inline types are passed by reference (the
761 // calling convention the interpreter expects).
762 static int compute_total_args_passed_int(const GrowableArray<SigEntry>* sig_extended) {
763 int total_args_passed = 0;
764 if (InlineTypePassFieldsAsArgs) {
765 for (int i = 0; i < sig_extended->length(); i++) {
766 BasicType bt = sig_extended->at(i)._bt;
767 if (bt == T_METADATA) {
768 // In sig_extended, an inline type argument starts with:
769 // T_METADATA, followed by the types of the fields of the
770 // inline type and T_VOID to mark the end of the value
771 // type. Inline types are flattened so, for instance, in the
772 // case of an inline type with an int field and an inline type
773 // field that itself has 2 fields, an int and a long:
774 // T_METADATA T_INT T_METADATA T_INT T_LONG T_VOID (second
775 // slot for the T_LONG) T_VOID (inner inline type) T_VOID
776 // (outer inline type)
777 total_args_passed++;
778 int vt = 1;
779 do {
780 i++;
781 BasicType bt = sig_extended->at(i)._bt;
782 BasicType prev_bt = sig_extended->at(i-1)._bt;
783 if (bt == T_METADATA) {
784 vt++;
785 } else if (bt == T_VOID &&
786 prev_bt != T_LONG &&
787 prev_bt != T_DOUBLE) {
788 vt--;
789 }
790 } while (vt != 0);
791 } else {
792 total_args_passed++;
793 }
794 }
795 } else {
796 total_args_passed = sig_extended->length();
797 }
798 return total_args_passed;
799 }
800
801
802 static void gen_c2i_adapter_helper(MacroAssembler* masm,
803 BasicType bt,
804 BasicType prev_bt,
805 size_t size_in_bytes,
806 const VMRegPair& reg_pair,
807 const Address& to,
808 int extraspace,
809 bool is_oop) {
810 if (bt == T_VOID) {
811 assert(prev_bt == T_LONG || prev_bt == T_DOUBLE, "missing half");
812 return;
813 }
814
815 // Say 4 args:
816 // i st_off
817 // 0 32 T_LONG
818 // 1 24 T_VOID
819 // 2 16 T_OBJECT
820 // 3 8 T_BOOL
821 // - 0 return address
822 //
823 // However to make thing extra confusing. Because we can fit a long/double in
824 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
825 // leaves one slot empty and only stores to a single slot. In this case the
826 // slot that is occupied is the T_VOID slot. See I said it was confusing.
827
828 bool wide = (size_in_bytes == wordSize);
829 VMReg r_1 = reg_pair.first();
830 VMReg r_2 = reg_pair.second();
831 assert(r_2->is_valid() == wide, "invalid size");
832 if (!r_1->is_valid()) {
833 assert(!r_2->is_valid(), "must be invalid");
834 return;
835 }
836
837 if (!r_1->is_XMMRegister()) {
838 Register val = rax;
839 if (r_1->is_stack()) {
840 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
841 __ load_sized_value(val, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
842 } else {
843 val = r_1->as_Register();
844 }
845 assert_different_registers(to.base(), val, rscratch1);
846 if (is_oop) {
847 __ push(r13);
848 __ push(rbx);
849 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep it valid.
850 __ push(to.base());
851 __ store_heap_oop(to, val, rscratch1, r13, rbx, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
852 __ pop(to.base());
853 __ pop(rbx);
854 __ pop(r13);
855 } else {
856 __ store_sized_value(to, val, size_in_bytes);
857 }
858 } else {
859 if (wide) {
860 __ movdbl(to, r_1->as_XMMRegister());
861 } else {
862 __ movflt(to, r_1->as_XMMRegister());
863 }
864 }
865 }
866
867 static void gen_c2i_adapter(MacroAssembler *masm,
868 const GrowableArray<SigEntry>* sig_extended,
869 const VMRegPair *regs,
870 bool requires_clinit_barrier,
871 address& c2i_no_clinit_check_entry,
872 Label& skip_fixup,
873 address start,
874 OopMapSet* oop_maps,
875 int& frame_complete,
876 int& frame_size_in_words,
877 bool alloc_inline_receiver) {
878 if (requires_clinit_barrier) {
879 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
880 Label L_skip_barrier;
881 Register method = rbx;
882
883 { // Bypass the barrier for non-static methods
884 Register flags = rscratch1;
885 __ load_unsigned_short(flags, Address(method, Method::access_flags_offset()));
886 __ testl(flags, JVM_ACC_STATIC);
887 __ jcc(Assembler::zero, L_skip_barrier); // non-static
888 }
889
890 Register klass = rscratch1;
891 __ load_method_holder(klass, method);
892 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
893
894 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
895
896 __ bind(L_skip_barrier);
897 c2i_no_clinit_check_entry = __ pc();
898 }
899
900 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
901 bs->c2i_entry_barrier(masm);
902
903 // Before we get into the guts of the C2I adapter, see if we should be here
904 // at all. We've come from compiled code and are attempting to jump to the
905 // interpreter, which means the caller made a static call to get here
906 // (vcalls always get a compiled target if there is one). Check for a
907 // compiled target. If there is one, we need to patch the caller's call.
908 patch_callers_callsite(masm);
909
910 __ bind(skip_fixup);
911
912 if (InlineTypePassFieldsAsArgs) {
913 // Is there an inline type argument?
914 bool has_inline_argument = false;
915 for (int i = 0; i < sig_extended->length() && !has_inline_argument; i++) {
916 has_inline_argument = (sig_extended->at(i)._bt == T_METADATA);
917 }
918 if (has_inline_argument) {
919 // There is at least a value type argument: we're coming from
920 // compiled code so we may not have buffers to back the value
921 // objects. Allocate the buffers here with a runtime call for
922 // the value arguments that needs a buffer.
923 OopMap* map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, /*save_wide_vectors*/ false);
924
925 frame_complete = __ offset();
926
927 __ set_last_Java_frame(noreg, noreg, nullptr, rscratch1);
928
929 __ mov(c_rarg0, r15_thread);
930 __ mov(c_rarg1, rbx);
931 __ mov64(c_rarg2, (int64_t)alloc_inline_receiver);
932 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::allocate_inline_types)));
933
934 oop_maps->add_gc_map((int)(__ pc() - start), map);
935 __ reset_last_Java_frame(false);
936
937 RegisterSaver::restore_live_registers(masm);
938
939 Label no_exception;
940 __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
941 __ jcc(Assembler::equal, no_exception);
942
943 __ movptr(Address(r15_thread, JavaThread::vm_result_oop_offset()), NULL_WORD);
944 __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
945 __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
946
947 __ bind(no_exception);
948
949 // We get an array of objects from the runtime call
950 __ get_vm_result_oop(rscratch2); // Use rscratch2 (r11) as temporary because rscratch1 (r10) is trashed by movptr()
951 }
952 }
953
954 // Since all args are passed on the stack, total_args_passed *
955 // Interpreter::stackElementSize is the space we need.
956 int total_args_passed = compute_total_args_passed_int(sig_extended);
957 assert(total_args_passed >= 0, "total_args_passed is %d", total_args_passed);
958
959 int extraspace = (total_args_passed * Interpreter::stackElementSize);
960
961 // stack is aligned, keep it that way
962 // This is not currently needed or enforced by the interpreter, but
963 // we might as well conform to the ABI.
964 extraspace = align_up(extraspace, 2*wordSize);
965
966 // set senderSP value
967 __ lea(r13, Address(rsp, wordSize));
968
969 #ifdef ASSERT
970 __ check_stack_alignment(r13, "sender stack not aligned");
971 #endif
972 if (extraspace > 0) {
973 // Pop the return address
974 __ pop(rax);
975
976 __ subptr(rsp, extraspace);
977
978 // Push the return address
979 __ push(rax);
980
981 // Account for the return address location since we store it first rather
982 // than hold it in a register across all the shuffling
983 extraspace += wordSize;
984 }
985
986 #ifdef ASSERT
987 __ check_stack_alignment(rsp, "callee stack not aligned", wordSize, rax);
988 #endif
989
990 // Now write the args into the outgoing interpreter space
991
992 // next_arg_comp is the next argument from the compiler point of
993 // view (inline type fields are passed in registers/on the stack). In
994 // sig_extended, an inline type argument starts with: T_METADATA,
995 // followed by the types of the fields of the inline type and T_VOID
996 // to mark the end of the inline type. ignored counts the number of
997 // T_METADATA/T_VOID. next_vt_arg is the next inline type argument:
998 // used to get the buffer for that argument from the pool of buffers
999 // we allocated above and want to pass to the
1000 // interpreter. next_arg_int is the next argument from the
1001 // interpreter point of view (inline types are passed by reference).
1002 for (int next_arg_comp = 0, ignored = 0, next_vt_arg = 0, next_arg_int = 0;
1003 next_arg_comp < sig_extended->length(); next_arg_comp++) {
1004 assert(ignored <= next_arg_comp, "shouldn't skip over more slots than there are arguments");
1005 assert(next_arg_int <= total_args_passed, "more arguments for the interpreter than expected?");
1006 BasicType bt = sig_extended->at(next_arg_comp)._bt;
1007 int st_off = (total_args_passed - next_arg_int) * Interpreter::stackElementSize;
1008 if (!InlineTypePassFieldsAsArgs || bt != T_METADATA) {
1009 int next_off = st_off - Interpreter::stackElementSize;
1010 const int offset = (bt == T_LONG || bt == T_DOUBLE) ? next_off : st_off;
1011 const VMRegPair reg_pair = regs[next_arg_comp-ignored];
1012 size_t size_in_bytes = reg_pair.second()->is_valid() ? 8 : 4;
1013 gen_c2i_adapter_helper(masm, bt, next_arg_comp > 0 ? sig_extended->at(next_arg_comp-1)._bt : T_ILLEGAL,
1014 size_in_bytes, reg_pair, Address(rsp, offset), extraspace, false);
1015 next_arg_int++;
1016 #ifdef ASSERT
1017 if (bt == T_LONG || bt == T_DOUBLE) {
1018 // Overwrite the unused slot with known junk
1019 __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
1020 __ movptr(Address(rsp, st_off), rax);
1021 }
1022 #endif /* ASSERT */
1023 } else {
1024 ignored++;
1025 next_arg_int++;
1026 int vt = 1;
1027 // write fields we get from compiled code in registers/stack
1028 // slots to the buffer: we know we are done with that inline type
1029 // argument when we hit the T_VOID that acts as an end of inline
1030 // type delimiter for this inline type. Inline types are flattened
1031 // so we might encounter embedded inline types. Each entry in
1032 // sig_extended contains a field offset in the buffer.
1033 Label L_null;
1034 Label not_null_buffer;
1035 do {
1036 next_arg_comp++;
1037 BasicType bt = sig_extended->at(next_arg_comp)._bt;
1038 BasicType prev_bt = sig_extended->at(next_arg_comp-1)._bt;
1039 if (bt == T_METADATA) {
1040 vt++;
1041 ignored++;
1042 } else if (bt == T_VOID &&
1043 prev_bt != T_LONG &&
1044 prev_bt != T_DOUBLE) {
1045 vt--;
1046 ignored++;
1047 } else if (sig_extended->at(next_arg_comp)._vt_oop) {
1048 // buffer argument: use if non null
1049 VMReg buffer = regs[next_arg_comp-ignored].first();
1050 if (buffer->is_stack()) {
1051 int ld_off = buffer->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
1052 __ movptr(r14, Address(rsp, ld_off));
1053 } else {
1054 __ movptr(r14, buffer->as_Register());
1055 }
1056 __ testptr(r14, r14);
1057 __ jcc(Assembler::notEqual, not_null_buffer);
1058 // otherwise get the buffer from the just allocated pool of buffers
1059 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + next_vt_arg * type2aelembytes(T_OBJECT);
1060 __ load_heap_oop(r14, Address(rscratch2, index));
1061 next_vt_arg++;
1062 } else {
1063 int off = sig_extended->at(next_arg_comp)._offset;
1064 if (off == -1) {
1065 // Nullable inline type argument, emit null check
1066 VMReg reg = regs[next_arg_comp-ignored].first();
1067 Label L_notNull;
1068 if (reg->is_stack()) {
1069 int ld_off = reg->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
1070 __ testb(Address(rsp, ld_off), 1);
1071 } else {
1072 __ testb(reg->as_Register(), 1);
1073 }
1074 __ jcc(Assembler::notZero, L_notNull);
1075 __ movptr(Address(rsp, st_off), 0);
1076 __ jmp(L_null);
1077 __ bind(L_notNull);
1078 continue;
1079 }
1080 assert(off > 0, "offset in object should be positive");
1081 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
1082 bool is_oop = is_reference_type(bt);
1083 gen_c2i_adapter_helper(masm, bt, next_arg_comp > 0 ? sig_extended->at(next_arg_comp-1)._bt : T_ILLEGAL,
1084 size_in_bytes, regs[next_arg_comp-ignored], Address(r14, off), extraspace, is_oop);
1085 }
1086 } while (vt != 0);
1087 // pass the buffer to the interpreter
1088 __ bind(not_null_buffer);
1089 __ movptr(Address(rsp, st_off), r14);
1090 __ bind(L_null);
1091 }
1092 }
1093
1094 // Schedule the branch target address early.
1095 __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
1096 __ jmp(rcx);
1097 }
1098
1099 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
1100 int comp_args_on_stack,
1101 const GrowableArray<SigEntry>* sig,
1102 const VMRegPair *regs) {
1103
1104 // Note: r13 contains the senderSP on entry. We must preserve it since
1105 // we may do a i2c -> c2i transition if we lose a race where compiled
1106 // code goes non-entrant while we get args ready.
1107 // In addition we use r13 to locate all the interpreter args as
1108 // we must align the stack to 16 bytes on an i2c entry else we
1109 // lose alignment we expect in all compiled code and register
1110 // save code can segv when fxsave instructions find improperly
1111 // aligned stack pointer.
1112
1113 // Adapters can be frameless because they do not require the caller
1114 // to perform additional cleanup work, such as correcting the stack pointer.
1115 // An i2c adapter is frameless because the *caller* frame, which is interpreted,
1116 // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
1117 // even if a callee has modified the stack pointer.
1118 // A c2i adapter is frameless because the *callee* frame, which is interpreted,
1119 // routinely repairs its caller's stack pointer (from sender_sp, which is set
1120 // up via the senderSP register).
1121 // In other words, if *either* the caller or callee is interpreted, we can
1137 // Convert 4-byte c2 stack slots to words.
1138 int comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
1139
1140 if (comp_args_on_stack) {
1141 __ subptr(rsp, comp_words_on_stack * wordSize);
1142 }
1143
1144 // Ensure compiled code always sees stack at proper alignment
1145 __ andptr(rsp, -16);
1146
1147 // push the return address and misalign the stack that youngest frame always sees
1148 // as far as the placement of the call instruction
1149 __ push(rax);
1150
1151 // Put saved SP in another register
1152 const Register saved_sp = rax;
1153 __ movptr(saved_sp, r11);
1154
1155 // Will jump to the compiled code just as if compiled code was doing it.
1156 // Pre-load the register-jump target early, to schedule it better.
1157 __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_inline_offset())));
1158
1159 int total_args_passed = sig->length();
1160
1161 // Now generate the shuffle code. Pick up all register args and move the
1162 // rest through the floating point stack top.
1163 for (int i = 0; i < total_args_passed; i++) {
1164 BasicType bt = sig->at(i)._bt;
1165 if (bt == T_VOID) {
1166 // Longs and doubles are passed in native word order, but misaligned
1167 // in the 32-bit build.
1168 BasicType prev_bt = (i > 0) ? sig->at(i-1)._bt : T_ILLEGAL;
1169 assert(i > 0 && (prev_bt == T_LONG || prev_bt == T_DOUBLE), "missing half");
1170 continue;
1171 }
1172
1173 // Pick up 0, 1 or 2 words from SP+offset.
1174
1175 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
1176 "scrambled load targets?");
1177 // Load in argument order going down.
1178 int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
1179 // Point to interpreter value (vs. tag)
1180 int next_off = ld_off - Interpreter::stackElementSize;
1181 //
1182 //
1183 //
1184 VMReg r_1 = regs[i].first();
1185 VMReg r_2 = regs[i].second();
1186 if (!r_1->is_valid()) {
1187 assert(!r_2->is_valid(), "");
1188 continue;
1189 }
1191 // Convert stack slot to an SP offset (+ wordSize to account for return address )
1192 int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
1193
1194 // We can use r13 as a temp here because compiled code doesn't need r13 as an input
1195 // and if we end up going thru a c2i because of a miss a reasonable value of r13
1196 // will be generated.
1197 if (!r_2->is_valid()) {
1198 // sign extend???
1199 __ movl(r13, Address(saved_sp, ld_off));
1200 __ movptr(Address(rsp, st_off), r13);
1201 } else {
1202 //
1203 // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
1204 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
1205 // So we must adjust where to pick up the data to match the interpreter.
1206 //
1207 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
1208 // are accessed as negative so LSW is at LOW address
1209
1210 // ld_off is MSW so get LSW
1211 const int offset = (bt==T_LONG||bt==T_DOUBLE)?
1212 next_off : ld_off;
1213 __ movq(r13, Address(saved_sp, offset));
1214 // st_off is LSW (i.e. reg.first())
1215 __ movq(Address(rsp, st_off), r13);
1216 }
1217 } else if (r_1->is_Register()) { // Register argument
1218 Register r = r_1->as_Register();
1219 assert(r != rax, "must be different");
1220 if (r_2->is_valid()) {
1221 //
1222 // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
1223 // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
1224 // So we must adjust where to pick up the data to match the interpreter.
1225
1226 const int offset = (bt==T_LONG||bt==T_DOUBLE)?
1227 next_off : ld_off;
1228
1229 // this can be a misaligned move
1230 __ movq(r, Address(saved_sp, offset));
1231 } else {
1232 // sign extend and use a full word?
1233 __ movl(r, Address(saved_sp, ld_off));
1234 }
1235 } else {
1236 if (!r_2->is_valid()) {
1237 __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
1238 } else {
1239 __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
1240 }
1241 }
1242 }
1243
1244 __ push_cont_fastpath(); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
1245
1246 // 6243940 We might end up in handle_wrong_method if
1247 // the callee is deoptimized as we race thru here. If that
1248 // happens we don't want to take a safepoint because the
1249 // caller frame will look interpreted and arguments are now
1250 // "compiled" so it is much better to make this transition
1251 // invisible to the stack walking code. Unfortunately if
1252 // we try and find the callee by normal means a safepoint
1253 // is possible. So we stash the desired callee in the thread
1254 // and the vm will find there should this case occur.
1255
1256 __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
1257
1258 // put Method* where a c2i would expect should we end up there
1259 // only needed because of c2 resolve stubs return Method* as a result in
1260 // rax
1261 __ mov(rax, rbx);
1262 __ jmp(r11);
1263 }
1264
1265 static void gen_inline_cache_check(MacroAssembler *masm, Label& skip_fixup) {
1266 Register data = rax;
1267 __ ic_check(1 /* end_alignment */);
1268 __ movptr(rbx, Address(data, CompiledICData::speculated_method_offset()));
1269
1270 // Method might have been compiled since the call site was patched to
1271 // interpreted if that is the case treat it as a miss so we can get
1272 // the call site corrected.
1273 __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
1274 __ jcc(Assembler::equal, skip_fixup);
1275 __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1276 }
1277
1278 // ---------------------------------------------------------------
1279 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler* masm,
1280 int comp_args_on_stack,
1281 const GrowableArray<SigEntry>* sig,
1282 const VMRegPair* regs,
1283 const GrowableArray<SigEntry>* sig_cc,
1284 const VMRegPair* regs_cc,
1285 const GrowableArray<SigEntry>* sig_cc_ro,
1286 const VMRegPair* regs_cc_ro,
1287 address entry_address[AdapterBlob::ENTRY_COUNT],
1288 AdapterBlob*& new_adapter,
1289 bool allocate_code_blob) {
1290 entry_address[AdapterBlob::I2C] = __ pc();
1291 gen_i2c_adapter(masm, comp_args_on_stack, sig, regs);
1292
1293 // -------------------------------------------------------------------------
1294 // Generate a C2I adapter. On entry we know rbx holds the Method* during calls
1295 // to the interpreter. The args start out packed in the compiled layout. They
1296 // need to be unpacked into the interpreter layout. This will almost always
1297 // require some stack space. We grow the current (compiled) stack, then repack
1298 // the args. We finally end in a jump to the generic interpreter entry point.
1299 // On exit from the interpreter, the interpreter will restore our SP (lest the
1300 // compiled code, which relies solely on SP and not RBP, get sick).
1301
1302 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
1303 entry_address[AdapterBlob::C2I_Unverified_Inline] = __ pc();
1304 Label skip_fixup;
1305
1306 gen_inline_cache_check(masm, skip_fixup);
1307
1308 OopMapSet* oop_maps = new OopMapSet();
1309 int frame_complete = CodeOffsets::frame_never_safe;
1310 int frame_size_in_words = 0;
1311
1312 // Scalarized c2i adapter with non-scalarized receiver (i.e., don't pack receiver)
1313 entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
1314 entry_address[AdapterBlob::C2I_Inline_RO] = __ pc();
1315 if (regs_cc != regs_cc_ro) {
1316 // No class init barrier needed because method is guaranteed to be non-static
1317 gen_c2i_adapter(masm, sig_cc_ro, regs_cc_ro, /* requires_clinit_barrier = */ false, entry_address[AdapterBlob::C2I_No_Clinit_Check],
1318 skip_fixup, entry_address[AdapterBlob::I2C], oop_maps, frame_complete, frame_size_in_words, /* alloc_inline_receiver = */ false);
1319 skip_fixup.reset();
1320 }
1321
1322 // Scalarized c2i adapter
1323 entry_address[AdapterBlob::C2I] = __ pc();
1324 entry_address[AdapterBlob::C2I_Inline] = __ pc();
1325 gen_c2i_adapter(masm, sig_cc, regs_cc, /* requires_clinit_barrier = */ true, entry_address[AdapterBlob::C2I_No_Clinit_Check],
1326 skip_fixup, entry_address[AdapterBlob::I2C], oop_maps, frame_complete, frame_size_in_words, /* alloc_inline_receiver = */ true);
1327
1328 // Non-scalarized c2i adapter
1329 if (regs != regs_cc) {
1330 entry_address[AdapterBlob::C2I_Unverified_Inline] = __ pc();
1331 Label inline_entry_skip_fixup;
1332 gen_inline_cache_check(masm, inline_entry_skip_fixup);
1333
1334 entry_address[AdapterBlob::C2I_Inline] = __ pc();
1335 gen_c2i_adapter(masm, sig, regs, /* requires_clinit_barrier = */ true, entry_address[AdapterBlob::C2I_No_Clinit_Check],
1336 inline_entry_skip_fixup, entry_address[AdapterBlob::I2C], oop_maps, frame_complete, frame_size_in_words, /* alloc_inline_receiver = */ false);
1337 }
1338
1339 // The c2i adapters might safepoint and trigger a GC. The caller must make sure that
1340 // the GC knows about the location of oop argument locations passed to the c2i adapter.
1341 if (allocate_code_blob) {
1342 bool caller_must_gc_arguments = (regs != regs_cc);
1343 int entry_offset[AdapterHandlerEntry::ENTRIES_COUNT];
1344 assert(AdapterHandlerEntry::ENTRIES_COUNT == 7, "sanity");
1345 AdapterHandlerLibrary::address_to_offset(entry_address, entry_offset);
1346 new_adapter = AdapterBlob::create(masm->code(), entry_offset, frame_complete, frame_size_in_words, oop_maps, caller_must_gc_arguments);
1347 }
1348 }
1349
1350 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1351 VMRegPair *regs,
1352 int total_args_passed) {
1353
1354 // We return the amount of VMRegImpl stack slots we need to reserve for all
1355 // the arguments NOT counting out_preserve_stack_slots.
1356
1357 // NOTE: These arrays will have to change when c1 is ported
1358 #ifdef _WIN64
1359 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1360 c_rarg0, c_rarg1, c_rarg2, c_rarg3
1361 };
1362 static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
1363 c_farg0, c_farg1, c_farg2, c_farg3
1364 };
1365 #else
1366 static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1367 c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5
3713 julong *scratch = (julong *)alloca(total_allocation);
3714
3715 // Local scratch arrays
3716 julong
3717 *a = scratch + 0 * longwords,
3718 *n = scratch + 1 * longwords,
3719 *m = scratch + 2 * longwords;
3720
3721 reverse_words((julong *)a_ints, a, longwords);
3722 reverse_words((julong *)n_ints, n, longwords);
3723
3724 if (len >= MONTGOMERY_SQUARING_THRESHOLD) {
3725 ::montgomery_square(a, n, m, (julong)inv, longwords);
3726 } else {
3727 ::montgomery_multiply(a, a, n, m, (julong)inv, longwords);
3728 }
3729
3730 reverse_words(m, (julong *)m_ints, longwords);
3731 }
3732
3733 BufferedInlineTypeBlob* SharedRuntime::generate_buffered_inline_type_adapter(const InlineKlass* vk) {
3734 BufferBlob* buf = BufferBlob::create("inline types pack/unpack", 16 * K);
3735 if (buf == nullptr) {
3736 return nullptr;
3737 }
3738 CodeBuffer buffer(buf);
3739 short buffer_locs[20];
3740 buffer.insts()->initialize_shared_locs((relocInfo*)buffer_locs,
3741 sizeof(buffer_locs)/sizeof(relocInfo));
3742
3743 MacroAssembler* masm = new MacroAssembler(&buffer);
3744
3745 const Array<SigEntry>* sig_vk = vk->extended_sig();
3746 const Array<VMRegPair>* regs = vk->return_regs();
3747
3748 int pack_fields_jobject_off = __ offset();
3749 // Resolve pre-allocated buffer from JNI handle.
3750 // We cannot do this in generate_call_stub() because it requires GC code to be initialized.
3751 __ movptr(rax, Address(r13, 0));
3752 __ resolve_jobject(rax /* value */,
3753 r12 /* tmp */);
3754 __ movptr(Address(r13, 0), rax);
3755
3756 int pack_fields_off = __ offset();
3757
3758 int j = 1;
3759 for (int i = 0; i < sig_vk->length(); i++) {
3760 BasicType bt = sig_vk->at(i)._bt;
3761 if (bt == T_METADATA) {
3762 continue;
3763 }
3764 if (bt == T_VOID) {
3765 if (sig_vk->at(i-1)._bt == T_LONG ||
3766 sig_vk->at(i-1)._bt == T_DOUBLE) {
3767 j++;
3768 }
3769 continue;
3770 }
3771 int off = sig_vk->at(i)._offset;
3772 assert(off > 0, "offset in object should be positive");
3773 VMRegPair pair = regs->at(j);
3774 VMReg r_1 = pair.first();
3775 Address to(rax, off);
3776 if (bt == T_FLOAT) {
3777 __ movflt(to, r_1->as_XMMRegister());
3778 } else if (bt == T_DOUBLE) {
3779 __ movdbl(to, r_1->as_XMMRegister());
3780 } else {
3781 Register val = r_1->as_Register();
3782 assert_different_registers(to.base(), val, r14, r13, rbx, rscratch1);
3783 if (is_reference_type(bt)) {
3784 // store_heap_oop transitively calls oop_store_at which corrupts to.base(). We need to keep rax valid.
3785 __ mov(rbx, rax);
3786 Address to_with_rbx(rbx, off);
3787 __ store_heap_oop(to_with_rbx, val, r14, r13, rbx, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
3788 } else {
3789 __ store_sized_value(to, r_1->as_Register(), type2aelembytes(bt));
3790 }
3791 }
3792 j++;
3793 }
3794 assert(j == regs->length(), "missed a field?");
3795 if (vk->supports_nullable_layouts()) {
3796 // Set the null marker
3797 __ movb(Address(rax, vk->null_marker_offset()), 1);
3798 }
3799 __ ret(0);
3800
3801 int unpack_fields_off = __ offset();
3802
3803 Label skip;
3804 Label not_null;
3805 __ testptr(rax, rax);
3806 __ jcc(Assembler::notZero, not_null);
3807
3808 // Return value is null. Zero all registers because the runtime requires a canonical
3809 // representation of a flat null.
3810 j = 1;
3811 for (int i = 0; i < sig_vk->length(); i++) {
3812 BasicType bt = sig_vk->at(i)._bt;
3813 if (bt == T_METADATA) {
3814 continue;
3815 }
3816 if (bt == T_VOID) {
3817 if (sig_vk->at(i-1)._bt == T_LONG ||
3818 sig_vk->at(i-1)._bt == T_DOUBLE) {
3819 j++;
3820 }
3821 continue;
3822 }
3823
3824 VMRegPair pair = regs->at(j);
3825 VMReg r_1 = pair.first();
3826 if (r_1->is_XMMRegister()) {
3827 __ xorps(r_1->as_XMMRegister(), r_1->as_XMMRegister());
3828 } else {
3829 __ xorl(r_1->as_Register(), r_1->as_Register());
3830 }
3831 j++;
3832 }
3833 __ jmp(skip);
3834 __ bind(not_null);
3835
3836 j = 1;
3837 for (int i = 0; i < sig_vk->length(); i++) {
3838 BasicType bt = sig_vk->at(i)._bt;
3839 if (bt == T_METADATA) {
3840 continue;
3841 }
3842 if (bt == T_VOID) {
3843 if (sig_vk->at(i-1)._bt == T_LONG ||
3844 sig_vk->at(i-1)._bt == T_DOUBLE) {
3845 j++;
3846 }
3847 continue;
3848 }
3849 int off = sig_vk->at(i)._offset;
3850 assert(off > 0, "offset in object should be positive");
3851 VMRegPair pair = regs->at(j);
3852 VMReg r_1 = pair.first();
3853 VMReg r_2 = pair.second();
3854 Address from(rax, off);
3855 if (bt == T_FLOAT) {
3856 __ movflt(r_1->as_XMMRegister(), from);
3857 } else if (bt == T_DOUBLE) {
3858 __ movdbl(r_1->as_XMMRegister(), from);
3859 } else if (bt == T_OBJECT || bt == T_ARRAY) {
3860 assert_different_registers(rax, r_1->as_Register());
3861 __ load_heap_oop(r_1->as_Register(), from);
3862 } else {
3863 assert(is_java_primitive(bt), "unexpected basic type");
3864 assert_different_registers(rax, r_1->as_Register());
3865 size_t size_in_bytes = type2aelembytes(bt);
3866 __ load_sized_value(r_1->as_Register(), from, size_in_bytes, bt != T_CHAR && bt != T_BOOLEAN);
3867 }
3868 j++;
3869 }
3870 assert(j == regs->length(), "missed a field?");
3871
3872 __ bind(skip);
3873 __ ret(0);
3874
3875 __ flush();
3876
3877 return BufferedInlineTypeBlob::create(&buffer, pack_fields_off, pack_fields_jobject_off, unpack_fields_off);
3878 }
3879
3880 #if INCLUDE_JFR
3881
3882 // For c2: c_rarg0 is junk, call to runtime to write a checkpoint.
3883 // It returns a jobject handle to the event writer.
3884 // The handle is dereferenced and the return value is the event writer oop.
3885 RuntimeStub* SharedRuntime::generate_jfr_write_checkpoint() {
3886 enum layout {
3887 rbp_off,
3888 rbpH_off,
3889 return_off,
3890 return_off2,
3891 framesize // inclusive of return address
3892 };
3893
3894 const char* name = SharedRuntime::stub_name(StubId::shared_jfr_write_checkpoint_id);
3895 CodeBuffer code(name, 1024, 64);
3896 MacroAssembler* masm = new MacroAssembler(&code);
3897 address start = __ pc();
3898
3899 __ enter();
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