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src/hotspot/cpu/x86/sharedRuntime_x86_64.cpp

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  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #ifndef _WINDOWS
  27 #include "alloca.h"
  28 #endif
  29 #include "asm/macroAssembler.hpp"
  30 #include "asm/macroAssembler.inline.hpp"

  31 #include "code/compiledIC.hpp"
  32 #include "code/debugInfoRec.hpp"
  33 #include "code/icBuffer.hpp"
  34 #include "code/nativeInst.hpp"
  35 #include "code/vtableStubs.hpp"
  36 #include "compiler/oopMap.hpp"
  37 #include "gc/shared/collectedHeap.hpp"
  38 #include "gc/shared/gcLocker.hpp"
  39 #include "gc/shared/barrierSet.hpp"
  40 #include "gc/shared/barrierSetAssembler.hpp"
  41 #include "interpreter/interpreter.hpp"
  42 #include "logging/log.hpp"
  43 #include "memory/resourceArea.hpp"
  44 #include "memory/universe.hpp"
  45 #include "oops/compiledICHolder.hpp"
  46 #include "oops/klass.inline.hpp"
  47 #include "oops/method.inline.hpp"
  48 #include "prims/methodHandles.hpp"
  49 #include "runtime/continuation.hpp"
  50 #include "runtime/continuationEntry.inline.hpp"

 508     case T_SHORT:
 509     case T_INT:
 510       if (int_args < Argument::n_int_register_parameters_j) {
 511         regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
 512       } else {
 513         regs[i].set1(VMRegImpl::stack2reg(stk_args));
 514         stk_args += 2;
 515       }
 516       break;
 517     case T_VOID:
 518       // halves of T_LONG or T_DOUBLE
 519       assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
 520       regs[i].set_bad();
 521       break;
 522     case T_LONG:
 523       assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
 524       // fall through
 525     case T_OBJECT:
 526     case T_ARRAY:
 527     case T_ADDRESS:

 528       if (int_args < Argument::n_int_register_parameters_j) {
 529         regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
 530       } else {
 531         regs[i].set2(VMRegImpl::stack2reg(stk_args));
 532         stk_args += 2;
 533       }
 534       break;
 535     case T_FLOAT:
 536       if (fp_args < Argument::n_float_register_parameters_j) {
 537         regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
 538       } else {
 539         regs[i].set1(VMRegImpl::stack2reg(stk_args));
 540         stk_args += 2;
 541       }
 542       break;
 543     case T_DOUBLE:
 544       assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
 545       if (fp_args < Argument::n_float_register_parameters_j) {
 546         regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
 547       } else {
 548         regs[i].set2(VMRegImpl::stack2reg(stk_args));
 549         stk_args += 2;
 550       }
 551       break;
 552     default:
 553       ShouldNotReachHere();
 554       break;
 555     }
 556   }
 557 
 558   return align_up(stk_args, 2);
 559 }
 560 


















































































 561 // Patch the callers callsite with entry to compiled code if it exists.
 562 static void patch_callers_callsite(MacroAssembler *masm) {
 563   Label L;
 564   __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
 565   __ jcc(Assembler::equal, L);
 566 
 567   // Save the current stack pointer
 568   __ mov(r13, rsp);
 569   // Schedule the branch target address early.
 570   // Call into the VM to patch the caller, then jump to compiled callee
 571   // rax isn't live so capture return address while we easily can
 572   __ movptr(rax, Address(rsp, 0));
 573 
 574   // align stack so push_CPU_state doesn't fault
 575   __ andptr(rsp, -(StackAlignmentInBytes));
 576   __ push_CPU_state();
 577   __ vzeroupper();
 578   // VM needs caller's callsite
 579   // VM needs target method
 580   // This needs to be a long call since we will relocate this adapter to

 583   // Allocate argument register save area
 584   if (frame::arg_reg_save_area_bytes != 0) {
 585     __ subptr(rsp, frame::arg_reg_save_area_bytes);
 586   }
 587   __ mov(c_rarg0, rbx);
 588   __ mov(c_rarg1, rax);
 589   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
 590 
 591   // De-allocate argument register save area
 592   if (frame::arg_reg_save_area_bytes != 0) {
 593     __ addptr(rsp, frame::arg_reg_save_area_bytes);
 594   }
 595 
 596   __ vzeroupper();
 597   __ pop_CPU_state();
 598   // restore sp
 599   __ mov(rsp, r13);
 600   __ bind(L);
 601 }
 602 










































































































 603 
 604 static void gen_c2i_adapter(MacroAssembler *masm,
 605                             int total_args_passed,
 606                             int comp_args_on_stack,
 607                             const BasicType *sig_bt,
 608                             const VMRegPair *regs,
 609                             Label& skip_fixup) {































 610   // Before we get into the guts of the C2I adapter, see if we should be here
 611   // at all.  We've come from compiled code and are attempting to jump to the
 612   // interpreter, which means the caller made a static call to get here
 613   // (vcalls always get a compiled target if there is one).  Check for a
 614   // compiled target.  If there is one, we need to patch the caller's call.
 615   patch_callers_callsite(masm);
 616 
 617   __ bind(skip_fixup);
 618 










































 619   // Since all args are passed on the stack, total_args_passed *
 620   // Interpreter::stackElementSize is the space we need.
 621 
 622   assert(total_args_passed >= 0, "total_args_passed is %d", total_args_passed);
 623 
 624   int extraspace = (total_args_passed * Interpreter::stackElementSize);
 625 
 626   // stack is aligned, keep it that way
 627   // This is not currently needed or enforced by the interpreter, but
 628   // we might as well conform to the ABI.
 629   extraspace = align_up(extraspace, 2*wordSize);
 630 
 631   // set senderSP value
 632   __ lea(r13, Address(rsp, wordSize));
 633 
 634 #ifdef ASSERT
 635   __ check_stack_alignment(r13, "sender stack not aligned");
 636 #endif
 637   if (extraspace > 0) {
 638     // Pop the return address
 639     __ pop(rax);
 640 
 641     __ subptr(rsp, extraspace);
 642 
 643     // Push the return address
 644     __ push(rax);
 645 
 646     // Account for the return address location since we store it first rather
 647     // than hold it in a register across all the shuffling
 648     extraspace += wordSize;
 649   }
 650 
 651 #ifdef ASSERT
 652   __ check_stack_alignment(rsp, "callee stack not aligned", wordSize, rax);
 653 #endif
 654 
 655   // Now write the args into the outgoing interpreter space
 656   for (int i = 0; i < total_args_passed; i++) {
 657     if (sig_bt[i] == T_VOID) {
 658       assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
 659       continue;
 660     }
 661 
 662     // offset to start parameters
 663     int st_off   = (total_args_passed - i) * Interpreter::stackElementSize;
 664     int next_off = st_off - Interpreter::stackElementSize;
 665 
 666     // Say 4 args:
 667     // i   st_off
 668     // 0   32 T_LONG
 669     // 1   24 T_VOID
 670     // 2   16 T_OBJECT
 671     // 3    8 T_BOOL
 672     // -    0 return address
 673     //
 674     // However to make thing extra confusing. Because we can fit a long/double in
 675     // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
 676     // leaves one slot empty and only stores to a single slot. In this case the
 677     // slot that is occupied is the T_VOID slot. See I said it was confusing.
 678 
 679     VMReg r_1 = regs[i].first();
 680     VMReg r_2 = regs[i].second();
 681     if (!r_1->is_valid()) {
 682       assert(!r_2->is_valid(), "");
 683       continue;
 684     }
 685     if (r_1->is_stack()) {
 686       // memory to memory use rax
 687       int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
 688       if (!r_2->is_valid()) {
 689         // sign extend??
 690         __ movl(rax, Address(rsp, ld_off));
 691         __ movptr(Address(rsp, st_off), rax);
 692 
 693       } else {
 694 
 695         __ movq(rax, Address(rsp, ld_off));
 696 
 697         // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
 698         // T_DOUBLE and T_LONG use two slots in the interpreter
 699         if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
 700           // ld_off == LSW, ld_off+wordSize == MSW
 701           // st_off == MSW, next_off == LSW
 702           __ movq(Address(rsp, next_off), rax);
 703 #ifdef ASSERT
 704           // Overwrite the unused slot with known junk
 705           __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
 706           __ movptr(Address(rsp, st_off), rax);
 707 #endif /* ASSERT */
 708         } else {
 709           __ movq(Address(rsp, st_off), rax);
 710         }
 711       }
 712     } else if (r_1->is_Register()) {
 713       Register r = r_1->as_Register();
 714       if (!r_2->is_valid()) {
 715         // must be only an int (or less ) so move only 32bits to slot
 716         // why not sign extend??
 717         __ movl(Address(rsp, st_off), r);
 718       } else {
 719         // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
 720         // T_DOUBLE and T_LONG use two slots in the interpreter
 721         if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
 722           // long/double in gpr
 723 #ifdef ASSERT
 724           // Overwrite the unused slot with known junk
 725           __ mov64(rax, CONST64(0xdeadffffdeadaaab));
 726           __ movptr(Address(rsp, st_off), rax);
 727 #endif /* ASSERT */
 728           __ movq(Address(rsp, next_off), r);

























 729         } else {
 730           __ movptr(Address(rsp, st_off), r);





















 731         }
 732       }
 733     } else {
 734       assert(r_1->is_XMMRegister(), "");
 735       if (!r_2->is_valid()) {
 736         // only a float use just part of the slot
 737         __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
 738       } else {
 739 #ifdef ASSERT
 740         // Overwrite the unused slot with known junk
 741         __ mov64(rax, CONST64(0xdeadffffdeadaaac));
 742         __ movptr(Address(rsp, st_off), rax);
 743 #endif /* ASSERT */
 744         __ movdbl(Address(rsp, next_off), r_1->as_XMMRegister());
 745       }
 746     }
 747   }
 748 
 749   // Schedule the branch target address early.
 750   __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
 751   __ jmp(rcx);
 752 }
 753 
 754 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg,
 755                         address code_start, address code_end,
 756                         Label& L_ok) {
 757   Label L_fail;
 758   __ lea(temp_reg, ExternalAddress(code_start));
 759   __ cmpptr(pc_reg, temp_reg);
 760   __ jcc(Assembler::belowEqual, L_fail);
 761   __ lea(temp_reg, ExternalAddress(code_end));
 762   __ cmpptr(pc_reg, temp_reg);
 763   __ jcc(Assembler::below, L_ok);
 764   __ bind(L_fail);
 765 }
 766 
 767 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
 768                                     int total_args_passed,
 769                                     int comp_args_on_stack,
 770                                     const BasicType *sig_bt,
 771                                     const VMRegPair *regs) {
 772 
 773   // Note: r13 contains the senderSP on entry. We must preserve it since
 774   // we may do a i2c -> c2i transition if we lose a race where compiled
 775   // code goes non-entrant while we get args ready.
 776   // In addition we use r13 to locate all the interpreter args as
 777   // we must align the stack to 16 bytes on an i2c entry else we
 778   // lose alignment we expect in all compiled code and register
 779   // save code can segv when fxsave instructions find improperly
 780   // aligned stack pointer.
 781 
 782   // Adapters can be frameless because they do not require the caller
 783   // to perform additional cleanup work, such as correcting the stack pointer.
 784   // An i2c adapter is frameless because the *caller* frame, which is interpreted,
 785   // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
 786   // even if a callee has modified the stack pointer.
 787   // A c2i adapter is frameless because the *callee* frame, which is interpreted,
 788   // routinely repairs its caller's stack pointer (from sender_sp, which is set
 789   // up via the senderSP register).
 790   // In other words, if *either* the caller or callee is interpreted, we can

 841   // Convert 4-byte c2 stack slots to words.
 842   int comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
 843 
 844   if (comp_args_on_stack) {
 845     __ subptr(rsp, comp_words_on_stack * wordSize);
 846   }
 847 
 848   // Ensure compiled code always sees stack at proper alignment
 849   __ andptr(rsp, -16);
 850 
 851   // push the return address and misalign the stack that youngest frame always sees
 852   // as far as the placement of the call instruction
 853   __ push(rax);
 854 
 855   // Put saved SP in another register
 856   const Register saved_sp = rax;
 857   __ movptr(saved_sp, r11);
 858 
 859   // Will jump to the compiled code just as if compiled code was doing it.
 860   // Pre-load the register-jump target early, to schedule it better.
 861   __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_offset())));
 862 
 863 #if INCLUDE_JVMCI
 864   if (EnableJVMCI) {
 865     // check if this call should be routed towards a specific entry point
 866     __ cmpptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
 867     Label no_alternative_target;
 868     __ jcc(Assembler::equal, no_alternative_target);
 869     __ movptr(r11, Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
 870     __ movptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
 871     __ bind(no_alternative_target);
 872   }
 873 #endif // INCLUDE_JVMCI
 874 


 875   // Now generate the shuffle code.  Pick up all register args and move the
 876   // rest through the floating point stack top.
 877   for (int i = 0; i < total_args_passed; i++) {
 878     if (sig_bt[i] == T_VOID) {

 879       // Longs and doubles are passed in native word order, but misaligned
 880       // in the 32-bit build.
 881       assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");

 882       continue;
 883     }
 884 
 885     // Pick up 0, 1 or 2 words from SP+offset.
 886 
 887     assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
 888             "scrambled load targets?");
 889     // Load in argument order going down.
 890     int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
 891     // Point to interpreter value (vs. tag)
 892     int next_off = ld_off - Interpreter::stackElementSize;
 893     //
 894     //
 895     //
 896     VMReg r_1 = regs[i].first();
 897     VMReg r_2 = regs[i].second();
 898     if (!r_1->is_valid()) {
 899       assert(!r_2->is_valid(), "");
 900       continue;
 901     }

 903       // Convert stack slot to an SP offset (+ wordSize to account for return address )
 904       int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
 905 
 906       // We can use r13 as a temp here because compiled code doesn't need r13 as an input
 907       // and if we end up going thru a c2i because of a miss a reasonable value of r13
 908       // will be generated.
 909       if (!r_2->is_valid()) {
 910         // sign extend???
 911         __ movl(r13, Address(saved_sp, ld_off));
 912         __ movptr(Address(rsp, st_off), r13);
 913       } else {
 914         //
 915         // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
 916         // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
 917         // So we must adjust where to pick up the data to match the interpreter.
 918         //
 919         // Interpreter local[n] == MSW, local[n+1] == LSW however locals
 920         // are accessed as negative so LSW is at LOW address
 921 
 922         // ld_off is MSW so get LSW
 923         const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
 924                            next_off : ld_off;
 925         __ movq(r13, Address(saved_sp, offset));
 926         // st_off is LSW (i.e. reg.first())
 927         __ movq(Address(rsp, st_off), r13);
 928       }
 929     } else if (r_1->is_Register()) {  // Register argument
 930       Register r = r_1->as_Register();
 931       assert(r != rax, "must be different");
 932       if (r_2->is_valid()) {
 933         //
 934         // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
 935         // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
 936         // So we must adjust where to pick up the data to match the interpreter.
 937 
 938         const int offset = (sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
 939                            next_off : ld_off;
 940 
 941         // this can be a misaligned move
 942         __ movq(r, Address(saved_sp, offset));
 943       } else {
 944         // sign extend and use a full word?
 945         __ movl(r, Address(saved_sp, ld_off));
 946       }
 947     } else {
 948       if (!r_2->is_valid()) {
 949         __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
 950       } else {
 951         __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
 952       }
 953     }
 954   }
 955 
 956   __ push_cont_fastpath(); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
 957 
 958   // 6243940 We might end up in handle_wrong_method if
 959   // the callee is deoptimized as we race thru here. If that
 960   // happens we don't want to take a safepoint because the
 961   // caller frame will look interpreted and arguments are now
 962   // "compiled" so it is much better to make this transition
 963   // invisible to the stack walking code. Unfortunately if
 964   // we try and find the callee by normal means a safepoint
 965   // is possible. So we stash the desired callee in the thread
 966   // and the vm will find there should this case occur.
 967 
 968   __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
 969 
 970   // put Method* where a c2i would expect should we end up there
 971   // only needed because eof c2 resolve stubs return Method* as a result in
 972   // rax
 973   __ mov(rax, rbx);
 974   __ jmp(r11);
 975 }
 976 






















 977 // ---------------------------------------------------------------
 978 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
 979                                                             int total_args_passed,
 980                                                             int comp_args_on_stack,
 981                                                             const BasicType *sig_bt,
 982                                                             const VMRegPair *regs,
 983                                                             AdapterFingerPrint* fingerprint) {






 984   address i2c_entry = __ pc();
 985 
 986   gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
 987 
 988   // -------------------------------------------------------------------------
 989   // Generate a C2I adapter.  On entry we know rbx holds the Method* during calls
 990   // to the interpreter.  The args start out packed in the compiled layout.  They
 991   // need to be unpacked into the interpreter layout.  This will almost always
 992   // require some stack space.  We grow the current (compiled) stack, then repack
 993   // the args.  We  finally end in a jump to the generic interpreter entry point.
 994   // On exit from the interpreter, the interpreter will restore our SP (lest the
 995   // compiled code, which relies solely on SP and not RBP, get sick).
 996 
 997   address c2i_unverified_entry = __ pc();

 998   Label skip_fixup;
 999   Label ok;
1000 
1001   Register holder = rax;
1002   Register receiver = j_rarg0;
1003   Register temp = rbx;
1004 
1005   {
1006     __ load_klass(temp, receiver, rscratch1);
1007     __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset()));
1008     __ movptr(rbx, Address(holder, CompiledICHolder::holder_metadata_offset()));
1009     __ jcc(Assembler::equal, ok);
1010     __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1011 
1012     __ bind(ok);
1013     // Method might have been compiled since the call site was patched to
1014     // interpreted if that is the case treat it as a miss so we can get
1015     // the call site corrected.
1016     __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
1017     __ jcc(Assembler::equal, skip_fixup);
1018     __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1019   }
1020 
1021   address c2i_entry = __ pc();
1022 
1023   // Class initialization barrier for static methods
1024   address c2i_no_clinit_check_entry = nullptr;
1025   if (VM_Version::supports_fast_class_init_checks()) {
1026     Label L_skip_barrier;
1027     Register method = rbx;
1028 
1029     { // Bypass the barrier for non-static methods
1030       Register flags = rscratch1;
1031       __ movl(flags, Address(method, Method::access_flags_offset()));
1032       __ testl(flags, JVM_ACC_STATIC);
1033       __ jcc(Assembler::zero, L_skip_barrier); // non-static
1034     }
1035 
1036     Register klass = rscratch1;
1037     __ load_method_holder(klass, method);
1038     __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
1039 
1040     __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
1041 
1042     __ bind(L_skip_barrier);
1043     c2i_no_clinit_check_entry = __ pc();













1044   }
1045 
1046   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1047   bs->c2i_entry_barrier(masm);
1048 
1049   gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);





1050 
1051   return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry, c2i_no_clinit_check_entry);
1052 }
1053 
1054 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1055                                          VMRegPair *regs,
1056                                          int total_args_passed) {
1057 
1058 // We return the amount of VMRegImpl stack slots we need to reserve for all
1059 // the arguments NOT counting out_preserve_stack_slots.
1060 
1061 // NOTE: These arrays will have to change when c1 is ported
1062 #ifdef _WIN64
1063     static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1064       c_rarg0, c_rarg1, c_rarg2, c_rarg3
1065     };
1066     static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
1067       c_farg0, c_farg1, c_farg2, c_farg3
1068     };
1069 #else
1070     static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1071       c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5

1088       case T_BYTE:
1089       case T_SHORT:
1090       case T_INT:
1091         if (int_args < Argument::n_int_register_parameters_c) {
1092           regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
1093 #ifdef _WIN64
1094           fp_args++;
1095           // Allocate slots for callee to stuff register args the stack.
1096           stk_args += 2;
1097 #endif
1098         } else {
1099           regs[i].set1(VMRegImpl::stack2reg(stk_args));
1100           stk_args += 2;
1101         }
1102         break;
1103       case T_LONG:
1104         assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
1105         // fall through
1106       case T_OBJECT:
1107       case T_ARRAY:

1108       case T_ADDRESS:
1109       case T_METADATA:
1110         if (int_args < Argument::n_int_register_parameters_c) {
1111           regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
1112 #ifdef _WIN64
1113           fp_args++;
1114           stk_args += 2;
1115 #endif
1116         } else {
1117           regs[i].set2(VMRegImpl::stack2reg(stk_args));
1118           stk_args += 2;
1119         }
1120         break;
1121       case T_FLOAT:
1122         if (fp_args < Argument::n_float_register_parameters_c) {
1123           regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
1124 #ifdef _WIN64
1125           int_args++;
1126           // Allocate slots for callee to stuff register args the stack.
1127           stk_args += 2;

2014 
2015   int temploc = -1;
2016   for (int ai = 0; ai < arg_order.length(); ai += 2) {
2017     int i = arg_order.at(ai);
2018     int c_arg = arg_order.at(ai + 1);
2019     __ block_comment(err_msg("move %d -> %d", i, c_arg));
2020 #ifdef ASSERT
2021     if (in_regs[i].first()->is_Register()) {
2022       assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!");
2023     } else if (in_regs[i].first()->is_XMMRegister()) {
2024       assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!");
2025     }
2026     if (out_regs[c_arg].first()->is_Register()) {
2027       reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2028     } else if (out_regs[c_arg].first()->is_XMMRegister()) {
2029       freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
2030     }
2031 #endif /* ASSERT */
2032     switch (in_sig_bt[i]) {
2033       case T_ARRAY:

2034       case T_OBJECT:
2035         __ object_move(map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2036                     ((i == 0) && (!is_static)),
2037                     &receiver_offset);
2038         break;
2039       case T_VOID:
2040         break;
2041 
2042       case T_FLOAT:
2043         __ float_move(in_regs[i], out_regs[c_arg]);
2044           break;
2045 
2046       case T_DOUBLE:
2047         assert( i + 1 < total_in_args &&
2048                 in_sig_bt[i + 1] == T_VOID &&
2049                 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2050         __ double_move(in_regs[i], out_regs[c_arg]);
2051         break;
2052 
2053       case T_LONG :

2140     const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
2141 
2142     // Get the handle (the 2nd argument)
2143     __ mov(oop_handle_reg, c_rarg1);
2144 
2145     // Get address of the box
2146 
2147     __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2148 
2149     // Load the oop from the handle
2150     __ movptr(obj_reg, Address(oop_handle_reg, 0));
2151 
2152     if (LockingMode == LM_MONITOR) {
2153       __ jmp(slow_path_lock);
2154     } else if (LockingMode == LM_LEGACY) {
2155       // Load immediate 1 into swap_reg %rax
2156       __ movl(swap_reg, 1);
2157 
2158       // Load (object->mark() | 1) into swap_reg %rax
2159       __ orptr(swap_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));




2160 
2161       // Save (object->mark() | 1) into BasicLock's displaced header
2162       __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2163 
2164       // src -> dest iff dest == rax else rax <- dest
2165       __ lock();
2166       __ cmpxchgptr(lock_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
2167       __ jcc(Assembler::equal, count_mon);
2168 
2169       // Hmm should this move to the slow path code area???
2170 
2171       // Test if the oopMark is an obvious stack pointer, i.e.,
2172       //  1) (mark & 3) == 0, and
2173       //  2) rsp <= mark < mark + os::pagesize()
2174       // These 3 tests can be done by evaluating the following
2175       // expression: ((mark - rsp) & (3 - os::vm_page_size())),
2176       // assuming both stack pointer and pagesize have their
2177       // least significant 2 bits clear.
2178       // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
2179 

2204   // Now set thread in native
2205   __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
2206 
2207   __ call(RuntimeAddress(native_func));
2208 
2209   // Verify or restore cpu control state after JNI call
2210   __ restore_cpu_control_state_after_jni(rscratch1);
2211 
2212   // Unpack native results.
2213   switch (ret_type) {
2214   case T_BOOLEAN: __ c2bool(rax);            break;
2215   case T_CHAR   : __ movzwl(rax, rax);      break;
2216   case T_BYTE   : __ sign_extend_byte (rax); break;
2217   case T_SHORT  : __ sign_extend_short(rax); break;
2218   case T_INT    : /* nothing to do */        break;
2219   case T_DOUBLE :
2220   case T_FLOAT  :
2221     // Result is in xmm0 we'll save as needed
2222     break;
2223   case T_ARRAY:                 // Really a handle

2224   case T_OBJECT:                // Really a handle
2225       break; // can't de-handlize until after safepoint check
2226   case T_VOID: break;
2227   case T_LONG: break;
2228   default       : ShouldNotReachHere();
2229   }
2230 
2231   Label after_transition;
2232 
2233   // Switch thread to "native transition" state before reading the synchronization state.
2234   // This additional state is necessary because reading and testing the synchronization
2235   // state is not atomic w.r.t. GC, as this scenario demonstrates:
2236   //     Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2237   //     VM thread changes sync state to synchronizing and suspends threads for GC.
2238   //     Thread A is resumed to finish this native method, but doesn't block here since it
2239   //     didn't see any synchronization is progress, and escapes.
2240   __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
2241 
2242   // Force this write out before the read below
2243   if (!UseSystemMemoryBarrier) {

3701   __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), NULL_WORD);
3702 #endif
3703   // Clear the exception oop so GC no longer processes it as a root.
3704   __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), NULL_WORD);
3705 
3706   // rax: exception oop
3707   // r8:  exception handler
3708   // rdx: exception pc
3709   // Jump to handler
3710 
3711   __ jmp(r8);
3712 
3713   // Make sure all code is generated
3714   masm->flush();
3715 
3716   // Set exception blob
3717   _exception_blob =  ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
3718 }
3719 #endif // COMPILER2
3720 















































































































  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #ifndef _WINDOWS
  27 #include "alloca.h"
  28 #endif
  29 #include "asm/macroAssembler.hpp"
  30 #include "asm/macroAssembler.inline.hpp"
  31 #include "classfile/symbolTable.hpp"
  32 #include "code/compiledIC.hpp"
  33 #include "code/debugInfoRec.hpp"
  34 #include "code/icBuffer.hpp"
  35 #include "code/nativeInst.hpp"
  36 #include "code/vtableStubs.hpp"
  37 #include "compiler/oopMap.hpp"
  38 #include "gc/shared/collectedHeap.hpp"
  39 #include "gc/shared/gcLocker.hpp"
  40 #include "gc/shared/barrierSet.hpp"
  41 #include "gc/shared/barrierSetAssembler.hpp"
  42 #include "interpreter/interpreter.hpp"
  43 #include "logging/log.hpp"
  44 #include "memory/resourceArea.hpp"
  45 #include "memory/universe.hpp"
  46 #include "oops/compiledICHolder.hpp"
  47 #include "oops/klass.inline.hpp"
  48 #include "oops/method.inline.hpp"
  49 #include "prims/methodHandles.hpp"
  50 #include "runtime/continuation.hpp"
  51 #include "runtime/continuationEntry.inline.hpp"

 509     case T_SHORT:
 510     case T_INT:
 511       if (int_args < Argument::n_int_register_parameters_j) {
 512         regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
 513       } else {
 514         regs[i].set1(VMRegImpl::stack2reg(stk_args));
 515         stk_args += 2;
 516       }
 517       break;
 518     case T_VOID:
 519       // halves of T_LONG or T_DOUBLE
 520       assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
 521       regs[i].set_bad();
 522       break;
 523     case T_LONG:
 524       assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
 525       // fall through
 526     case T_OBJECT:
 527     case T_ARRAY:
 528     case T_ADDRESS:
 529     case T_PRIMITIVE_OBJECT:
 530       if (int_args < Argument::n_int_register_parameters_j) {
 531         regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
 532       } else {
 533         regs[i].set2(VMRegImpl::stack2reg(stk_args));
 534         stk_args += 2;
 535       }
 536       break;
 537     case T_FLOAT:
 538       if (fp_args < Argument::n_float_register_parameters_j) {
 539         regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
 540       } else {
 541         regs[i].set1(VMRegImpl::stack2reg(stk_args));
 542         stk_args += 2;
 543       }
 544       break;
 545     case T_DOUBLE:
 546       assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
 547       if (fp_args < Argument::n_float_register_parameters_j) {
 548         regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
 549       } else {
 550         regs[i].set2(VMRegImpl::stack2reg(stk_args));
 551         stk_args += 2;
 552       }
 553       break;
 554     default:
 555       ShouldNotReachHere();
 556       break;
 557     }
 558   }
 559 
 560   return align_up(stk_args, 2);
 561 }
 562 
 563 // Same as java_calling_convention() but for multiple return
 564 // values. There's no way to store them on the stack so if we don't
 565 // have enough registers, multiple values can't be returned.
 566 const uint SharedRuntime::java_return_convention_max_int = Argument::n_int_register_parameters_j+1;
 567 const uint SharedRuntime::java_return_convention_max_float = Argument::n_float_register_parameters_j;
 568 int SharedRuntime::java_return_convention(const BasicType *sig_bt,
 569                                           VMRegPair *regs,
 570                                           int total_args_passed) {
 571   // Create the mapping between argument positions and
 572   // registers.
 573   static const Register INT_ArgReg[java_return_convention_max_int] = {
 574     rax, j_rarg5, j_rarg4, j_rarg3, j_rarg2, j_rarg1, j_rarg0
 575   };
 576   static const XMMRegister FP_ArgReg[java_return_convention_max_float] = {
 577     j_farg0, j_farg1, j_farg2, j_farg3,
 578     j_farg4, j_farg5, j_farg6, j_farg7
 579   };
 580 
 581 
 582   uint int_args = 0;
 583   uint fp_args = 0;
 584 
 585   for (int i = 0; i < total_args_passed; i++) {
 586     switch (sig_bt[i]) {
 587     case T_BOOLEAN:
 588     case T_CHAR:
 589     case T_BYTE:
 590     case T_SHORT:
 591     case T_INT:
 592       if (int_args < Argument::n_int_register_parameters_j+1) {
 593         regs[i].set1(INT_ArgReg[int_args]->as_VMReg());
 594         int_args++;
 595       } else {
 596         return -1;
 597       }
 598       break;
 599     case T_VOID:
 600       // halves of T_LONG or T_DOUBLE
 601       assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
 602       regs[i].set_bad();
 603       break;
 604     case T_LONG:
 605       assert(sig_bt[i + 1] == T_VOID, "expecting half");
 606       // fall through
 607     case T_OBJECT:
 608     case T_PRIMITIVE_OBJECT:
 609     case T_ARRAY:
 610     case T_ADDRESS:
 611     case T_METADATA:
 612       if (int_args < Argument::n_int_register_parameters_j+1) {
 613         regs[i].set2(INT_ArgReg[int_args]->as_VMReg());
 614         int_args++;
 615       } else {
 616         return -1;
 617       }
 618       break;
 619     case T_FLOAT:
 620       if (fp_args < Argument::n_float_register_parameters_j) {
 621         regs[i].set1(FP_ArgReg[fp_args]->as_VMReg());
 622         fp_args++;
 623       } else {
 624         return -1;
 625       }
 626       break;
 627     case T_DOUBLE:
 628       assert(sig_bt[i + 1] == T_VOID, "expecting half");
 629       if (fp_args < Argument::n_float_register_parameters_j) {
 630         regs[i].set2(FP_ArgReg[fp_args]->as_VMReg());
 631         fp_args++;
 632       } else {
 633         return -1;
 634       }
 635       break;
 636     default:
 637       ShouldNotReachHere();
 638       break;
 639     }
 640   }
 641 
 642   return int_args + fp_args;
 643 }
 644 
 645 // Patch the callers callsite with entry to compiled code if it exists.
 646 static void patch_callers_callsite(MacroAssembler *masm) {
 647   Label L;
 648   __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
 649   __ jcc(Assembler::equal, L);
 650 
 651   // Save the current stack pointer
 652   __ mov(r13, rsp);
 653   // Schedule the branch target address early.
 654   // Call into the VM to patch the caller, then jump to compiled callee
 655   // rax isn't live so capture return address while we easily can
 656   __ movptr(rax, Address(rsp, 0));
 657 
 658   // align stack so push_CPU_state doesn't fault
 659   __ andptr(rsp, -(StackAlignmentInBytes));
 660   __ push_CPU_state();
 661   __ vzeroupper();
 662   // VM needs caller's callsite
 663   // VM needs target method
 664   // This needs to be a long call since we will relocate this adapter to

 667   // Allocate argument register save area
 668   if (frame::arg_reg_save_area_bytes != 0) {
 669     __ subptr(rsp, frame::arg_reg_save_area_bytes);
 670   }
 671   __ mov(c_rarg0, rbx);
 672   __ mov(c_rarg1, rax);
 673   __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)));
 674 
 675   // De-allocate argument register save area
 676   if (frame::arg_reg_save_area_bytes != 0) {
 677     __ addptr(rsp, frame::arg_reg_save_area_bytes);
 678   }
 679 
 680   __ vzeroupper();
 681   __ pop_CPU_state();
 682   // restore sp
 683   __ mov(rsp, r13);
 684   __ bind(L);
 685 }
 686 
 687 // For each inline type argument, sig includes the list of fields of
 688 // the inline type. This utility function computes the number of
 689 // arguments for the call if inline types are passed by reference (the
 690 // calling convention the interpreter expects).
 691 static int compute_total_args_passed_int(const GrowableArray<SigEntry>* sig_extended) {
 692   int total_args_passed = 0;
 693   if (InlineTypePassFieldsAsArgs) {
 694     for (int i = 0; i < sig_extended->length(); i++) {
 695       BasicType bt = sig_extended->at(i)._bt;
 696       if (bt == T_METADATA) {
 697         // In sig_extended, an inline type argument starts with:
 698         // T_METADATA, followed by the types of the fields of the
 699         // inline type and T_VOID to mark the end of the value
 700         // type. Inline types are flattened so, for instance, in the
 701         // case of an inline type with an int field and an inline type
 702         // field that itself has 2 fields, an int and a long:
 703         // T_METADATA T_INT T_METADATA T_INT T_LONG T_VOID (second
 704         // slot for the T_LONG) T_VOID (inner inline type) T_VOID
 705         // (outer inline type)
 706         total_args_passed++;
 707         int vt = 1;
 708         do {
 709           i++;
 710           BasicType bt = sig_extended->at(i)._bt;
 711           BasicType prev_bt = sig_extended->at(i-1)._bt;
 712           if (bt == T_METADATA) {
 713             vt++;
 714           } else if (bt == T_VOID &&
 715                      prev_bt != T_LONG &&
 716                      prev_bt != T_DOUBLE) {
 717             vt--;
 718           }
 719         } while (vt != 0);
 720       } else {
 721         total_args_passed++;
 722       }
 723     }
 724   } else {
 725     total_args_passed = sig_extended->length();
 726   }
 727   return total_args_passed;
 728 }
 729 
 730 
 731 static void gen_c2i_adapter_helper(MacroAssembler* masm,
 732                                    BasicType bt,
 733                                    BasicType prev_bt,
 734                                    size_t size_in_bytes,
 735                                    const VMRegPair& reg_pair,
 736                                    const Address& to,
 737                                    int extraspace,
 738                                    bool is_oop) {
 739   assert(bt != T_PRIMITIVE_OBJECT || !InlineTypePassFieldsAsArgs, "no inline type here");
 740   if (bt == T_VOID) {
 741     assert(prev_bt == T_LONG || prev_bt == T_DOUBLE, "missing half");
 742     return;
 743   }
 744 
 745   // Say 4 args:
 746   // i   st_off
 747   // 0   32 T_LONG
 748   // 1   24 T_VOID
 749   // 2   16 T_OBJECT
 750   // 3    8 T_BOOL
 751   // -    0 return address
 752   //
 753   // However to make thing extra confusing. Because we can fit a long/double in
 754   // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
 755   // leaves one slot empty and only stores to a single slot. In this case the
 756   // slot that is occupied is the T_VOID slot. See I said it was confusing.
 757 
 758   bool wide = (size_in_bytes == wordSize);
 759   VMReg r_1 = reg_pair.first();
 760   VMReg r_2 = reg_pair.second();
 761   assert(r_2->is_valid() == wide, "invalid size");
 762   if (!r_1->is_valid()) {
 763     assert(!r_2->is_valid(), "must be invalid");
 764     return;
 765   }
 766 
 767   if (!r_1->is_XMMRegister()) {
 768     Register val = rax;
 769     if (r_1->is_stack()) {
 770       int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
 771       __ load_sized_value(val, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
 772     } else {
 773       val = r_1->as_Register();
 774     }
 775     assert_different_registers(to.base(), val, rscratch1);
 776     if (is_oop) {
 777       __ push(r13);
 778       __ push(rbx);
 779       __ store_heap_oop(to, val, rscratch1, r13, rbx, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
 780       __ pop(rbx);
 781       __ pop(r13);
 782     } else {
 783       __ store_sized_value(to, val, size_in_bytes);
 784     }
 785   } else {
 786     if (wide) {
 787       __ movdbl(to, r_1->as_XMMRegister());
 788     } else {
 789       __ movflt(to, r_1->as_XMMRegister());
 790     }
 791   }
 792 }
 793 
 794 static void gen_c2i_adapter(MacroAssembler *masm,
 795                             const GrowableArray<SigEntry>* sig_extended,


 796                             const VMRegPair *regs,
 797                             bool requires_clinit_barrier,
 798                             address& c2i_no_clinit_check_entry,
 799                             Label& skip_fixup,
 800                             address start,
 801                             OopMapSet* oop_maps,
 802                             int& frame_complete,
 803                             int& frame_size_in_words,
 804                             bool alloc_inline_receiver) {
 805   if (requires_clinit_barrier && VM_Version::supports_fast_class_init_checks()) {
 806     Label L_skip_barrier;
 807     Register method = rbx;
 808 
 809     { // Bypass the barrier for non-static methods
 810       Register flags = rscratch1;
 811       __ movl(flags, Address(method, Method::access_flags_offset()));
 812       __ testl(flags, JVM_ACC_STATIC);
 813       __ jcc(Assembler::zero, L_skip_barrier); // non-static
 814     }
 815 
 816     Register klass = rscratch1;
 817     __ load_method_holder(klass, method);
 818     __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
 819 
 820     __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
 821 
 822     __ bind(L_skip_barrier);
 823     c2i_no_clinit_check_entry = __ pc();
 824   }
 825 
 826   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 827   bs->c2i_entry_barrier(masm);
 828 
 829   // Before we get into the guts of the C2I adapter, see if we should be here
 830   // at all.  We've come from compiled code and are attempting to jump to the
 831   // interpreter, which means the caller made a static call to get here
 832   // (vcalls always get a compiled target if there is one).  Check for a
 833   // compiled target.  If there is one, we need to patch the caller's call.
 834   patch_callers_callsite(masm);
 835 
 836   __ bind(skip_fixup);
 837 
 838   if (InlineTypePassFieldsAsArgs) {
 839     // Is there an inline type argument?
 840     bool has_inline_argument = false;
 841     for (int i = 0; i < sig_extended->length() && !has_inline_argument; i++) {
 842       has_inline_argument = (sig_extended->at(i)._bt == T_METADATA);
 843     }
 844     if (has_inline_argument) {
 845       // There is at least an inline type argument: we're coming from
 846       // compiled code so we have no buffers to back the inline types.
 847       // Allocate the buffers here with a runtime call.
 848       OopMap* map = RegisterSaver::save_live_registers(masm, 0, &frame_size_in_words, /*save_vectors*/ false);
 849 
 850       frame_complete = __ offset();
 851 
 852       __ set_last_Java_frame(noreg, noreg, nullptr, rscratch1);
 853 
 854       __ mov(c_rarg0, r15_thread);
 855       __ mov(c_rarg1, rbx);
 856       __ mov64(c_rarg2, (int64_t)alloc_inline_receiver);
 857       __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::allocate_inline_types)));
 858 
 859       oop_maps->add_gc_map((int)(__ pc() - start), map);
 860       __ reset_last_Java_frame(false);
 861 
 862       RegisterSaver::restore_live_registers(masm);
 863 
 864       Label no_exception;
 865       __ cmpptr(Address(r15_thread, Thread::pending_exception_offset()), NULL_WORD);
 866       __ jcc(Assembler::equal, no_exception);
 867 
 868       __ movptr(Address(r15_thread, JavaThread::vm_result_offset()), NULL_WORD);
 869       __ movptr(rax, Address(r15_thread, Thread::pending_exception_offset()));
 870       __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
 871 
 872       __ bind(no_exception);
 873 
 874       // We get an array of objects from the runtime call
 875       __ get_vm_result(rscratch2, r15_thread); // Use rscratch2 (r11) as temporary because rscratch1 (r10) is trashed by movptr()
 876       __ get_vm_result_2(rbx, r15_thread); // TODO: required to keep the callee Method live?
 877     }
 878   }
 879 
 880   // Since all args are passed on the stack, total_args_passed *
 881   // Interpreter::stackElementSize is the space we need.
 882   int total_args_passed = compute_total_args_passed_int(sig_extended);
 883   assert(total_args_passed >= 0, "total_args_passed is %d", total_args_passed);
 884 
 885   int extraspace = (total_args_passed * Interpreter::stackElementSize);
 886 
 887   // stack is aligned, keep it that way
 888   // This is not currently needed or enforced by the interpreter, but
 889   // we might as well conform to the ABI.
 890   extraspace = align_up(extraspace, 2*wordSize);
 891 
 892   // set senderSP value
 893   __ lea(r13, Address(rsp, wordSize));
 894 
 895 #ifdef ASSERT
 896   __ check_stack_alignment(r13, "sender stack not aligned");
 897 #endif
 898   if (extraspace > 0) {
 899     // Pop the return address
 900     __ pop(rax);
 901 
 902     __ subptr(rsp, extraspace);
 903 
 904     // Push the return address
 905     __ push(rax);
 906 
 907     // Account for the return address location since we store it first rather
 908     // than hold it in a register across all the shuffling
 909     extraspace += wordSize;
 910   }
 911 
 912 #ifdef ASSERT
 913   __ check_stack_alignment(rsp, "callee stack not aligned", wordSize, rax);
 914 #endif
 915 
 916   // Now write the args into the outgoing interpreter space









 917 
 918   // next_arg_comp is the next argument from the compiler point of
 919   // view (inline type fields are passed in registers/on the stack). In
 920   // sig_extended, an inline type argument starts with: T_METADATA,
 921   // followed by the types of the fields of the inline type and T_VOID
 922   // to mark the end of the inline type. ignored counts the number of
 923   // T_METADATA/T_VOID. next_vt_arg is the next inline type argument:
 924   // used to get the buffer for that argument from the pool of buffers
 925   // we allocated above and want to pass to the
 926   // interpreter. next_arg_int is the next argument from the
 927   // interpreter point of view (inline types are passed by reference).
 928   for (int next_arg_comp = 0, ignored = 0, next_vt_arg = 0, next_arg_int = 0;
 929        next_arg_comp < sig_extended->length(); next_arg_comp++) {
 930     assert(ignored <= next_arg_comp, "shouldn't skip over more slots than there are arguments");
 931     assert(next_arg_int <= total_args_passed, "more arguments for the interpreter than expected?");
 932     BasicType bt = sig_extended->at(next_arg_comp)._bt;
 933     int st_off = (total_args_passed - next_arg_int) * Interpreter::stackElementSize;
 934     if (!InlineTypePassFieldsAsArgs || bt != T_METADATA) {
 935       int next_off = st_off - Interpreter::stackElementSize;
 936       const int offset = (bt == T_LONG || bt == T_DOUBLE) ? next_off : st_off;
 937       const VMRegPair reg_pair = regs[next_arg_comp-ignored];
 938       size_t size_in_bytes = reg_pair.second()->is_valid() ? 8 : 4;
 939       gen_c2i_adapter_helper(masm, bt, next_arg_comp > 0 ? sig_extended->at(next_arg_comp-1)._bt : T_ILLEGAL,
 940                              size_in_bytes, reg_pair, Address(rsp, offset), extraspace, false);
 941       next_arg_int++;













 942 #ifdef ASSERT
 943       if (bt == T_LONG || bt == T_DOUBLE) {
 944         // Overwrite the unused slot with known junk
 945         __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
 946         __ movptr(Address(rsp, st_off), rax);



 947       }















 948 #endif /* ASSERT */
 949     } else {
 950       ignored++;
 951       // get the buffer from the just allocated pool of buffers
 952       int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + next_vt_arg * type2aelembytes(T_OBJECT);
 953       __ load_heap_oop(r14, Address(rscratch2, index));
 954       next_vt_arg++; next_arg_int++;
 955       int vt = 1;
 956       // write fields we get from compiled code in registers/stack
 957       // slots to the buffer: we know we are done with that inline type
 958       // argument when we hit the T_VOID that acts as an end of inline
 959       // type delimiter for this inline type. Inline types are flattened
 960       // so we might encounter embedded inline types. Each entry in
 961       // sig_extended contains a field offset in the buffer.
 962       Label L_null;
 963       do {
 964         next_arg_comp++;
 965         BasicType bt = sig_extended->at(next_arg_comp)._bt;
 966         BasicType prev_bt = sig_extended->at(next_arg_comp-1)._bt;
 967         if (bt == T_METADATA) {
 968           vt++;
 969           ignored++;
 970         } else if (bt == T_VOID &&
 971                    prev_bt != T_LONG &&
 972                    prev_bt != T_DOUBLE) {
 973           vt--;
 974           ignored++;
 975         } else {
 976           int off = sig_extended->at(next_arg_comp)._offset;
 977           if (off == -1) {
 978             // Nullable inline type argument, emit null check
 979             VMReg reg = regs[next_arg_comp-ignored].first();
 980             Label L_notNull;
 981             if (reg->is_stack()) {
 982               int ld_off = reg->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
 983               __ testb(Address(rsp, ld_off), 1);
 984             } else {
 985               __ testb(reg->as_Register(), 1);
 986             }
 987             __ jcc(Assembler::notZero, L_notNull);
 988             __ movptr(Address(rsp, st_off), 0);
 989             __ jmp(L_null);
 990             __ bind(L_notNull);
 991             continue;
 992           }
 993           assert(off > 0, "offset in object should be positive");
 994           size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
 995           bool is_oop = is_reference_type(bt);
 996           gen_c2i_adapter_helper(masm, bt, next_arg_comp > 0 ? sig_extended->at(next_arg_comp-1)._bt : T_ILLEGAL,
 997                                  size_in_bytes, regs[next_arg_comp-ignored], Address(r14, off), extraspace, is_oop);
 998         }
 999       } while (vt != 0);
1000       // pass the buffer to the interpreter
1001       __ movptr(Address(rsp, st_off), r14);
1002       __ bind(L_null);










1003     }
1004   }
1005 
1006   // Schedule the branch target address early.
1007   __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
1008   __ jmp(rcx);
1009 }
1010 
1011 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg,
1012                         address code_start, address code_end,
1013                         Label& L_ok) {
1014   Label L_fail;
1015   __ lea(temp_reg, ExternalAddress(code_start));
1016   __ cmpptr(pc_reg, temp_reg);
1017   __ jcc(Assembler::belowEqual, L_fail);
1018   __ lea(temp_reg, ExternalAddress(code_end));
1019   __ cmpptr(pc_reg, temp_reg);
1020   __ jcc(Assembler::below, L_ok);
1021   __ bind(L_fail);
1022 }
1023 
1024 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,

1025                                     int comp_args_on_stack,
1026                                     const GrowableArray<SigEntry>* sig,
1027                                     const VMRegPair *regs) {
1028 
1029   // Note: r13 contains the senderSP on entry. We must preserve it since
1030   // we may do a i2c -> c2i transition if we lose a race where compiled
1031   // code goes non-entrant while we get args ready.
1032   // In addition we use r13 to locate all the interpreter args as
1033   // we must align the stack to 16 bytes on an i2c entry else we
1034   // lose alignment we expect in all compiled code and register
1035   // save code can segv when fxsave instructions find improperly
1036   // aligned stack pointer.
1037 
1038   // Adapters can be frameless because they do not require the caller
1039   // to perform additional cleanup work, such as correcting the stack pointer.
1040   // An i2c adapter is frameless because the *caller* frame, which is interpreted,
1041   // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
1042   // even if a callee has modified the stack pointer.
1043   // A c2i adapter is frameless because the *callee* frame, which is interpreted,
1044   // routinely repairs its caller's stack pointer (from sender_sp, which is set
1045   // up via the senderSP register).
1046   // In other words, if *either* the caller or callee is interpreted, we can

1097   // Convert 4-byte c2 stack slots to words.
1098   int comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
1099 
1100   if (comp_args_on_stack) {
1101     __ subptr(rsp, comp_words_on_stack * wordSize);
1102   }
1103 
1104   // Ensure compiled code always sees stack at proper alignment
1105   __ andptr(rsp, -16);
1106 
1107   // push the return address and misalign the stack that youngest frame always sees
1108   // as far as the placement of the call instruction
1109   __ push(rax);
1110 
1111   // Put saved SP in another register
1112   const Register saved_sp = rax;
1113   __ movptr(saved_sp, r11);
1114 
1115   // Will jump to the compiled code just as if compiled code was doing it.
1116   // Pre-load the register-jump target early, to schedule it better.
1117   __ movptr(r11, Address(rbx, in_bytes(Method::from_compiled_inline_offset())));
1118 
1119 #if INCLUDE_JVMCI
1120   if (EnableJVMCI) {
1121     // check if this call should be routed towards a specific entry point
1122     __ cmpptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
1123     Label no_alternative_target;
1124     __ jcc(Assembler::equal, no_alternative_target);
1125     __ movptr(r11, Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
1126     __ movptr(Address(r15_thread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())), 0);
1127     __ bind(no_alternative_target);
1128   }
1129 #endif // INCLUDE_JVMCI
1130 
1131   int total_args_passed = sig->length();
1132 
1133   // Now generate the shuffle code.  Pick up all register args and move the
1134   // rest through the floating point stack top.
1135   for (int i = 0; i < total_args_passed; i++) {
1136     BasicType bt = sig->at(i)._bt;
1137     if (bt == T_VOID) {
1138       // Longs and doubles are passed in native word order, but misaligned
1139       // in the 32-bit build.
1140       BasicType prev_bt = (i > 0) ? sig->at(i-1)._bt : T_ILLEGAL;
1141       assert(i > 0 && (prev_bt == T_LONG || prev_bt == T_DOUBLE), "missing half");
1142       continue;
1143     }
1144 
1145     // Pick up 0, 1 or 2 words from SP+offset.
1146 
1147     assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
1148             "scrambled load targets?");
1149     // Load in argument order going down.
1150     int ld_off = (total_args_passed - i)*Interpreter::stackElementSize;
1151     // Point to interpreter value (vs. tag)
1152     int next_off = ld_off - Interpreter::stackElementSize;
1153     //
1154     //
1155     //
1156     VMReg r_1 = regs[i].first();
1157     VMReg r_2 = regs[i].second();
1158     if (!r_1->is_valid()) {
1159       assert(!r_2->is_valid(), "");
1160       continue;
1161     }

1163       // Convert stack slot to an SP offset (+ wordSize to account for return address )
1164       int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
1165 
1166       // We can use r13 as a temp here because compiled code doesn't need r13 as an input
1167       // and if we end up going thru a c2i because of a miss a reasonable value of r13
1168       // will be generated.
1169       if (!r_2->is_valid()) {
1170         // sign extend???
1171         __ movl(r13, Address(saved_sp, ld_off));
1172         __ movptr(Address(rsp, st_off), r13);
1173       } else {
1174         //
1175         // We are using two optoregs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
1176         // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
1177         // So we must adjust where to pick up the data to match the interpreter.
1178         //
1179         // Interpreter local[n] == MSW, local[n+1] == LSW however locals
1180         // are accessed as negative so LSW is at LOW address
1181 
1182         // ld_off is MSW so get LSW
1183         const int offset = (bt==T_LONG||bt==T_DOUBLE)?
1184                            next_off : ld_off;
1185         __ movq(r13, Address(saved_sp, offset));
1186         // st_off is LSW (i.e. reg.first())
1187         __ movq(Address(rsp, st_off), r13);
1188       }
1189     } else if (r_1->is_Register()) {  // Register argument
1190       Register r = r_1->as_Register();
1191       assert(r != rax, "must be different");
1192       if (r_2->is_valid()) {
1193         //
1194         // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
1195         // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
1196         // So we must adjust where to pick up the data to match the interpreter.
1197 
1198         const int offset = (bt==T_LONG||bt==T_DOUBLE)?
1199                            next_off : ld_off;
1200 
1201         // this can be a misaligned move
1202         __ movq(r, Address(saved_sp, offset));
1203       } else {
1204         // sign extend and use a full word?
1205         __ movl(r, Address(saved_sp, ld_off));
1206       }
1207     } else {
1208       if (!r_2->is_valid()) {
1209         __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
1210       } else {
1211         __ movdbl(r_1->as_XMMRegister(), Address(saved_sp, next_off));
1212       }
1213     }
1214   }
1215 
1216   __ push_cont_fastpath(); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
1217 
1218   // 6243940 We might end up in handle_wrong_method if
1219   // the callee is deoptimized as we race thru here. If that
1220   // happens we don't want to take a safepoint because the
1221   // caller frame will look interpreted and arguments are now
1222   // "compiled" so it is much better to make this transition
1223   // invisible to the stack walking code. Unfortunately if
1224   // we try and find the callee by normal means a safepoint
1225   // is possible. So we stash the desired callee in the thread
1226   // and the vm will find there should this case occur.
1227 
1228   __ movptr(Address(r15_thread, JavaThread::callee_target_offset()), rbx);
1229 
1230   // put Method* where a c2i would expect should we end up there
1231   // only needed because of c2 resolve stubs return Method* as a result in
1232   // rax
1233   __ mov(rax, rbx);
1234   __ jmp(r11);
1235 }
1236 
1237 static void gen_inline_cache_check(MacroAssembler *masm, Label& skip_fixup) {
1238   Label ok;
1239 
1240   Register holder = rax;
1241   Register receiver = j_rarg0;
1242   Register temp = rbx;
1243 
1244   __ load_klass(temp, receiver, rscratch1);
1245   __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset()));
1246   __ movptr(rbx, Address(holder, CompiledICHolder::holder_metadata_offset()));
1247   __ jcc(Assembler::equal, ok);
1248   __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1249 
1250   __ bind(ok);
1251   // Method might have been compiled since the call site was patched to
1252   // interpreted if that is the case treat it as a miss so we can get
1253   // the call site corrected.
1254   __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), NULL_WORD);
1255   __ jcc(Assembler::equal, skip_fixup);
1256   __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1257 }
1258 
1259 // ---------------------------------------------------------------
1260 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler* masm,

1261                                                             int comp_args_on_stack,
1262                                                             const GrowableArray<SigEntry>* sig,
1263                                                             const VMRegPair* regs,
1264                                                             const GrowableArray<SigEntry>* sig_cc,
1265                                                             const VMRegPair* regs_cc,
1266                                                             const GrowableArray<SigEntry>* sig_cc_ro,
1267                                                             const VMRegPair* regs_cc_ro,
1268                                                             AdapterFingerPrint* fingerprint,
1269                                                             AdapterBlob*& new_adapter,
1270                                                             bool allocate_code_blob) {
1271   address i2c_entry = __ pc();
1272   gen_i2c_adapter(masm, comp_args_on_stack, sig, regs);

1273 
1274   // -------------------------------------------------------------------------
1275   // Generate a C2I adapter.  On entry we know rbx holds the Method* during calls
1276   // to the interpreter.  The args start out packed in the compiled layout.  They
1277   // need to be unpacked into the interpreter layout.  This will almost always
1278   // require some stack space.  We grow the current (compiled) stack, then repack
1279   // the args.  We  finally end in a jump to the generic interpreter entry point.
1280   // On exit from the interpreter, the interpreter will restore our SP (lest the
1281   // compiled code, which relies solely on SP and not RBP, get sick).
1282 
1283   address c2i_unverified_entry        = __ pc();
1284   address c2i_unverified_inline_entry = __ pc();
1285   Label skip_fixup;





1286 
1287   gen_inline_cache_check(masm, skip_fixup);





1288 
1289   OopMapSet* oop_maps = new OopMapSet();
1290   int frame_complete = CodeOffsets::frame_never_safe;
1291   int frame_size_in_words = 0;







1292 
1293   // Scalarized c2i adapter with non-scalarized receiver (i.e., don't pack receiver)
1294   address c2i_no_clinit_check_entry = nullptr;
1295   address c2i_inline_ro_entry = __ pc();
1296   if (regs_cc != regs_cc_ro) {
1297     // No class init barrier needed because method is guaranteed to be non-static
1298     gen_c2i_adapter(masm, sig_cc_ro, regs_cc_ro, /* requires_clinit_barrier = */ false, c2i_no_clinit_check_entry,
1299                     skip_fixup, i2c_entry, oop_maps, frame_complete, frame_size_in_words, /* alloc_inline_receiver = */ false);
1300     skip_fixup.reset();
1301   }









1302 
1303   // Scalarized c2i adapter
1304   address c2i_entry        = __ pc();
1305   address c2i_inline_entry = __ pc();
1306   gen_c2i_adapter(masm, sig_cc, regs_cc, /* requires_clinit_barrier = */ true, c2i_no_clinit_check_entry,
1307                   skip_fixup, i2c_entry, oop_maps, frame_complete, frame_size_in_words, /* alloc_inline_receiver = */ true);
1308 
1309   // Non-scalarized c2i adapter
1310   if (regs != regs_cc) {
1311     c2i_unverified_inline_entry = __ pc();
1312     Label inline_entry_skip_fixup;
1313     gen_inline_cache_check(masm, inline_entry_skip_fixup);
1314 
1315     c2i_inline_entry = __ pc();
1316     gen_c2i_adapter(masm, sig, regs, /* requires_clinit_barrier = */ true, c2i_no_clinit_check_entry,
1317                     inline_entry_skip_fixup, i2c_entry, oop_maps, frame_complete, frame_size_in_words, /* alloc_inline_receiver = */ false);
1318   }
1319 


1320 
1321   // The c2i adapters might safepoint and trigger a GC. The caller must make sure that
1322   // the GC knows about the location of oop argument locations passed to the c2i adapter.
1323   if (allocate_code_blob) {
1324     bool caller_must_gc_arguments = (regs != regs_cc);
1325     new_adapter = AdapterBlob::create(masm->code(), frame_complete, frame_size_in_words, oop_maps, caller_must_gc_arguments);
1326   }
1327 
1328   return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_inline_entry, c2i_inline_ro_entry, c2i_unverified_entry, c2i_unverified_inline_entry, c2i_no_clinit_check_entry);
1329 }
1330 
1331 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1332                                          VMRegPair *regs,
1333                                          int total_args_passed) {
1334 
1335 // We return the amount of VMRegImpl stack slots we need to reserve for all
1336 // the arguments NOT counting out_preserve_stack_slots.
1337 
1338 // NOTE: These arrays will have to change when c1 is ported
1339 #ifdef _WIN64
1340     static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1341       c_rarg0, c_rarg1, c_rarg2, c_rarg3
1342     };
1343     static const XMMRegister FP_ArgReg[Argument::n_float_register_parameters_c] = {
1344       c_farg0, c_farg1, c_farg2, c_farg3
1345     };
1346 #else
1347     static const Register INT_ArgReg[Argument::n_int_register_parameters_c] = {
1348       c_rarg0, c_rarg1, c_rarg2, c_rarg3, c_rarg4, c_rarg5

1365       case T_BYTE:
1366       case T_SHORT:
1367       case T_INT:
1368         if (int_args < Argument::n_int_register_parameters_c) {
1369           regs[i].set1(INT_ArgReg[int_args++]->as_VMReg());
1370 #ifdef _WIN64
1371           fp_args++;
1372           // Allocate slots for callee to stuff register args the stack.
1373           stk_args += 2;
1374 #endif
1375         } else {
1376           regs[i].set1(VMRegImpl::stack2reg(stk_args));
1377           stk_args += 2;
1378         }
1379         break;
1380       case T_LONG:
1381         assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
1382         // fall through
1383       case T_OBJECT:
1384       case T_ARRAY:
1385       case T_PRIMITIVE_OBJECT:
1386       case T_ADDRESS:
1387       case T_METADATA:
1388         if (int_args < Argument::n_int_register_parameters_c) {
1389           regs[i].set2(INT_ArgReg[int_args++]->as_VMReg());
1390 #ifdef _WIN64
1391           fp_args++;
1392           stk_args += 2;
1393 #endif
1394         } else {
1395           regs[i].set2(VMRegImpl::stack2reg(stk_args));
1396           stk_args += 2;
1397         }
1398         break;
1399       case T_FLOAT:
1400         if (fp_args < Argument::n_float_register_parameters_c) {
1401           regs[i].set1(FP_ArgReg[fp_args++]->as_VMReg());
1402 #ifdef _WIN64
1403           int_args++;
1404           // Allocate slots for callee to stuff register args the stack.
1405           stk_args += 2;

2292 
2293   int temploc = -1;
2294   for (int ai = 0; ai < arg_order.length(); ai += 2) {
2295     int i = arg_order.at(ai);
2296     int c_arg = arg_order.at(ai + 1);
2297     __ block_comment(err_msg("move %d -> %d", i, c_arg));
2298 #ifdef ASSERT
2299     if (in_regs[i].first()->is_Register()) {
2300       assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "destroyed reg!");
2301     } else if (in_regs[i].first()->is_XMMRegister()) {
2302       assert(!freg_destroyed[in_regs[i].first()->as_XMMRegister()->encoding()], "destroyed reg!");
2303     }
2304     if (out_regs[c_arg].first()->is_Register()) {
2305       reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2306     } else if (out_regs[c_arg].first()->is_XMMRegister()) {
2307       freg_destroyed[out_regs[c_arg].first()->as_XMMRegister()->encoding()] = true;
2308     }
2309 #endif /* ASSERT */
2310     switch (in_sig_bt[i]) {
2311       case T_ARRAY:
2312       case T_PRIMITIVE_OBJECT:
2313       case T_OBJECT:
2314         __ object_move(map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2315                     ((i == 0) && (!is_static)),
2316                     &receiver_offset);
2317         break;
2318       case T_VOID:
2319         break;
2320 
2321       case T_FLOAT:
2322         __ float_move(in_regs[i], out_regs[c_arg]);
2323           break;
2324 
2325       case T_DOUBLE:
2326         assert( i + 1 < total_in_args &&
2327                 in_sig_bt[i + 1] == T_VOID &&
2328                 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2329         __ double_move(in_regs[i], out_regs[c_arg]);
2330         break;
2331 
2332       case T_LONG :

2419     const int mark_word_offset = BasicLock::displaced_header_offset_in_bytes();
2420 
2421     // Get the handle (the 2nd argument)
2422     __ mov(oop_handle_reg, c_rarg1);
2423 
2424     // Get address of the box
2425 
2426     __ lea(lock_reg, Address(rsp, lock_slot_offset * VMRegImpl::stack_slot_size));
2427 
2428     // Load the oop from the handle
2429     __ movptr(obj_reg, Address(oop_handle_reg, 0));
2430 
2431     if (LockingMode == LM_MONITOR) {
2432       __ jmp(slow_path_lock);
2433     } else if (LockingMode == LM_LEGACY) {
2434       // Load immediate 1 into swap_reg %rax
2435       __ movl(swap_reg, 1);
2436 
2437       // Load (object->mark() | 1) into swap_reg %rax
2438       __ orptr(swap_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
2439       if (EnableValhalla) {
2440         // Mask inline_type bit such that we go to the slow path if object is an inline type
2441         __ andptr(swap_reg, ~((int) markWord::inline_type_bit_in_place));
2442       }
2443 
2444       // Save (object->mark() | 1) into BasicLock's displaced header
2445       __ movptr(Address(lock_reg, mark_word_offset), swap_reg);
2446 
2447       // src -> dest iff dest == rax else rax <- dest
2448       __ lock();
2449       __ cmpxchgptr(lock_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
2450       __ jcc(Assembler::equal, count_mon);
2451 
2452       // Hmm should this move to the slow path code area???
2453 
2454       // Test if the oopMark is an obvious stack pointer, i.e.,
2455       //  1) (mark & 3) == 0, and
2456       //  2) rsp <= mark < mark + os::pagesize()
2457       // These 3 tests can be done by evaluating the following
2458       // expression: ((mark - rsp) & (3 - os::vm_page_size())),
2459       // assuming both stack pointer and pagesize have their
2460       // least significant 2 bits clear.
2461       // NOTE: the oopMark is in swap_reg %rax as the result of cmpxchg
2462 

2487   // Now set thread in native
2488   __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native);
2489 
2490   __ call(RuntimeAddress(native_func));
2491 
2492   // Verify or restore cpu control state after JNI call
2493   __ restore_cpu_control_state_after_jni(rscratch1);
2494 
2495   // Unpack native results.
2496   switch (ret_type) {
2497   case T_BOOLEAN: __ c2bool(rax);            break;
2498   case T_CHAR   : __ movzwl(rax, rax);      break;
2499   case T_BYTE   : __ sign_extend_byte (rax); break;
2500   case T_SHORT  : __ sign_extend_short(rax); break;
2501   case T_INT    : /* nothing to do */        break;
2502   case T_DOUBLE :
2503   case T_FLOAT  :
2504     // Result is in xmm0 we'll save as needed
2505     break;
2506   case T_ARRAY:                 // Really a handle
2507   case T_PRIMITIVE_OBJECT:           // Really a handle
2508   case T_OBJECT:                // Really a handle
2509       break; // can't de-handlize until after safepoint check
2510   case T_VOID: break;
2511   case T_LONG: break;
2512   default       : ShouldNotReachHere();
2513   }
2514 
2515   Label after_transition;
2516 
2517   // Switch thread to "native transition" state before reading the synchronization state.
2518   // This additional state is necessary because reading and testing the synchronization
2519   // state is not atomic w.r.t. GC, as this scenario demonstrates:
2520   //     Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2521   //     VM thread changes sync state to synchronizing and suspends threads for GC.
2522   //     Thread A is resumed to finish this native method, but doesn't block here since it
2523   //     didn't see any synchronization is progress, and escapes.
2524   __ movl(Address(r15_thread, JavaThread::thread_state_offset()), _thread_in_native_trans);
2525 
2526   // Force this write out before the read below
2527   if (!UseSystemMemoryBarrier) {

3985   __ movptr(Address(r15_thread, JavaThread::exception_pc_offset()), NULL_WORD);
3986 #endif
3987   // Clear the exception oop so GC no longer processes it as a root.
3988   __ movptr(Address(r15_thread, JavaThread::exception_oop_offset()), NULL_WORD);
3989 
3990   // rax: exception oop
3991   // r8:  exception handler
3992   // rdx: exception pc
3993   // Jump to handler
3994 
3995   __ jmp(r8);
3996 
3997   // Make sure all code is generated
3998   masm->flush();
3999 
4000   // Set exception blob
4001   _exception_blob =  ExceptionBlob::create(&buffer, oop_maps, SimpleRuntimeFrame::framesize >> 1);
4002 }
4003 #endif // COMPILER2
4004 
4005 BufferedInlineTypeBlob* SharedRuntime::generate_buffered_inline_type_adapter(const InlineKlass* vk) {
4006   BufferBlob* buf = BufferBlob::create("inline types pack/unpack", 16 * K);
4007   CodeBuffer buffer(buf);
4008   short buffer_locs[20];
4009   buffer.insts()->initialize_shared_locs((relocInfo*)buffer_locs,
4010                                          sizeof(buffer_locs)/sizeof(relocInfo));
4011 
4012   MacroAssembler* masm = new MacroAssembler(&buffer);
4013 
4014   const Array<SigEntry>* sig_vk = vk->extended_sig();
4015   const Array<VMRegPair>* regs = vk->return_regs();
4016 
4017   int pack_fields_jobject_off = __ offset();
4018   // Resolve pre-allocated buffer from JNI handle.
4019   // We cannot do this in generate_call_stub() because it requires GC code to be initialized.
4020   __ movptr(rax, Address(r13, 0));
4021   __ resolve_jobject(rax /* value */,
4022                      r15_thread /* thread */,
4023                      r12 /* tmp */);
4024   __ movptr(Address(r13, 0), rax);
4025 
4026   int pack_fields_off = __ offset();
4027 
4028   int j = 1;
4029   for (int i = 0; i < sig_vk->length(); i++) {
4030     BasicType bt = sig_vk->at(i)._bt;
4031     if (bt == T_METADATA) {
4032       continue;
4033     }
4034     if (bt == T_VOID) {
4035       if (sig_vk->at(i-1)._bt == T_LONG ||
4036           sig_vk->at(i-1)._bt == T_DOUBLE) {
4037         j++;
4038       }
4039       continue;
4040     }
4041     int off = sig_vk->at(i)._offset;
4042     assert(off > 0, "offset in object should be positive");
4043     VMRegPair pair = regs->at(j);
4044     VMReg r_1 = pair.first();
4045     VMReg r_2 = pair.second();
4046     Address to(rax, off);
4047     if (bt == T_FLOAT) {
4048       __ movflt(to, r_1->as_XMMRegister());
4049     } else if (bt == T_DOUBLE) {
4050       __ movdbl(to, r_1->as_XMMRegister());
4051     } else {
4052       Register val = r_1->as_Register();
4053       assert_different_registers(to.base(), val, r14, r13, rbx, rscratch1);
4054       if (is_reference_type(bt)) {
4055         __ store_heap_oop(to, val, r14, r13, rbx, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
4056       } else {
4057         __ store_sized_value(to, r_1->as_Register(), type2aelembytes(bt));
4058       }
4059     }
4060     j++;
4061   }
4062   assert(j == regs->length(), "missed a field?");
4063 
4064   __ ret(0);
4065 
4066   int unpack_fields_off = __ offset();
4067 
4068   Label skip;
4069   __ testptr(rax, rax);
4070   __ jcc(Assembler::zero, skip);
4071 
4072   j = 1;
4073   for (int i = 0; i < sig_vk->length(); i++) {
4074     BasicType bt = sig_vk->at(i)._bt;
4075     if (bt == T_METADATA) {
4076       continue;
4077     }
4078     if (bt == T_VOID) {
4079       if (sig_vk->at(i-1)._bt == T_LONG ||
4080           sig_vk->at(i-1)._bt == T_DOUBLE) {
4081         j++;
4082       }
4083       continue;
4084     }
4085     int off = sig_vk->at(i)._offset;
4086     assert(off > 0, "offset in object should be positive");
4087     VMRegPair pair = regs->at(j);
4088     VMReg r_1 = pair.first();
4089     VMReg r_2 = pair.second();
4090     Address from(rax, off);
4091     if (bt == T_FLOAT) {
4092       __ movflt(r_1->as_XMMRegister(), from);
4093     } else if (bt == T_DOUBLE) {
4094       __ movdbl(r_1->as_XMMRegister(), from);
4095     } else if (bt == T_OBJECT || bt == T_ARRAY) {
4096       assert_different_registers(rax, r_1->as_Register());
4097       __ load_heap_oop(r_1->as_Register(), from);
4098     } else {
4099       assert(is_java_primitive(bt), "unexpected basic type");
4100       assert_different_registers(rax, r_1->as_Register());
4101       size_t size_in_bytes = type2aelembytes(bt);
4102       __ load_sized_value(r_1->as_Register(), from, size_in_bytes, bt != T_CHAR && bt != T_BOOLEAN);
4103     }
4104     j++;
4105   }
4106   assert(j == regs->length(), "missed a field?");
4107 
4108   __ bind(skip);
4109   __ ret(0);
4110 
4111   __ flush();
4112 
4113   return BufferedInlineTypeBlob::create(&buffer, pack_fields_off, pack_fields_jobject_off, unpack_fields_off);
4114 }
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