1 /*
   2  * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/macroAssembler.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "code/codeBlob.hpp"
  30 #include "logging/log.hpp"
  31 #include "logging/logStream.hpp"
  32 #include "memory/resourceArea.hpp"
  33 #include "memory/universe.hpp"
  34 #include "runtime/globals_extension.hpp"
  35 #include "runtime/java.hpp"
  36 #include "runtime/os.hpp"
  37 #include "runtime/stubCodeGenerator.hpp"
  38 #include "runtime/vm_version.hpp"
  39 #include "utilities/powerOfTwo.hpp"
  40 #include "utilities/virtualizationSupport.hpp"
  41 
  42 #include OS_HEADER_INLINE(os)
  43 
  44 int VM_Version::_cpu;
  45 int VM_Version::_model;
  46 int VM_Version::_stepping;
  47 bool VM_Version::_has_intel_jcc_erratum;
  48 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
  49 
  50 #define DECLARE_CPU_FEATURE_NAME(id, name, bit) name,
  51 const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)};
  52 #undef DECLARE_CPU_FEATURE_FLAG
  53 
  54 // Address of instruction which causes SEGV
  55 address VM_Version::_cpuinfo_segv_addr = 0;
  56 // Address of instruction after the one which causes SEGV
  57 address VM_Version::_cpuinfo_cont_addr = 0;
  58 
  59 static BufferBlob* stub_blob;
  60 static const int stub_size = 2000;
  61 
  62 extern "C" {
  63   typedef void (*get_cpu_info_stub_t)(void*);
  64   typedef void (*detect_virt_stub_t)(uint32_t, uint32_t*);
  65 }
  66 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
  67 static detect_virt_stub_t detect_virt_stub = NULL;
  68 
  69 #ifdef _LP64
  70 
  71 bool VM_Version::supports_clflush() {
  72   // clflush should always be available on x86_64
  73   // if not we are in real trouble because we rely on it
  74   // to flush the code cache.
  75   // Unfortunately, Assembler::clflush is currently called as part
  76   // of generation of the code cache flush routine. This happens
  77   // under Universe::init before the processor features are set
  78   // up. Assembler::flush calls this routine to check that clflush
  79   // is allowed. So, we give the caller a free pass if Universe init
  80   // is still in progress.
  81   assert ((!Universe::is_fully_initialized() || (_features & CPU_FLUSH) != 0), "clflush should be available");
  82   return true;
  83 }
  84 #endif
  85 
  86 #define CPUID_STANDARD_FN   0x0
  87 #define CPUID_STANDARD_FN_1 0x1
  88 #define CPUID_STANDARD_FN_4 0x4
  89 #define CPUID_STANDARD_FN_B 0xb
  90 
  91 #define CPUID_EXTENDED_FN   0x80000000
  92 #define CPUID_EXTENDED_FN_1 0x80000001
  93 #define CPUID_EXTENDED_FN_2 0x80000002
  94 #define CPUID_EXTENDED_FN_3 0x80000003
  95 #define CPUID_EXTENDED_FN_4 0x80000004
  96 #define CPUID_EXTENDED_FN_7 0x80000007
  97 #define CPUID_EXTENDED_FN_8 0x80000008
  98 
  99 class VM_Version_StubGenerator: public StubCodeGenerator {
 100  public:
 101 
 102   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
 103 
 104   address generate_get_cpu_info() {
 105     // Flags to test CPU type.
 106     const uint32_t HS_EFL_AC = 0x40000;
 107     const uint32_t HS_EFL_ID = 0x200000;
 108     // Values for when we don't have a CPUID instruction.
 109     const int      CPU_FAMILY_SHIFT = 8;
 110     const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
 111     const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
 112     bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
 113 
 114     Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
 115     Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, ext_cpuid8, done, wrapup;
 116     Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
 117 
 118     StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
 119 #   define __ _masm->
 120 
 121     address start = __ pc();
 122 
 123     //
 124     // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
 125     //
 126     // LP64: rcx and rdx are first and second argument registers on windows
 127 
 128     __ push(rbp);
 129 #ifdef _LP64
 130     __ mov(rbp, c_rarg0); // cpuid_info address
 131 #else
 132     __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
 133 #endif
 134     __ push(rbx);
 135     __ push(rsi);
 136     __ pushf();          // preserve rbx, and flags
 137     __ pop(rax);
 138     __ push(rax);
 139     __ mov(rcx, rax);
 140     //
 141     // if we are unable to change the AC flag, we have a 386
 142     //
 143     __ xorl(rax, HS_EFL_AC);
 144     __ push(rax);
 145     __ popf();
 146     __ pushf();
 147     __ pop(rax);
 148     __ cmpptr(rax, rcx);
 149     __ jccb(Assembler::notEqual, detect_486);
 150 
 151     __ movl(rax, CPU_FAMILY_386);
 152     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 153     __ jmp(done);
 154 
 155     //
 156     // If we are unable to change the ID flag, we have a 486 which does
 157     // not support the "cpuid" instruction.
 158     //
 159     __ bind(detect_486);
 160     __ mov(rax, rcx);
 161     __ xorl(rax, HS_EFL_ID);
 162     __ push(rax);
 163     __ popf();
 164     __ pushf();
 165     __ pop(rax);
 166     __ cmpptr(rcx, rax);
 167     __ jccb(Assembler::notEqual, detect_586);
 168 
 169     __ bind(cpu486);
 170     __ movl(rax, CPU_FAMILY_486);
 171     __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
 172     __ jmp(done);
 173 
 174     //
 175     // At this point, we have a chip which supports the "cpuid" instruction
 176     //
 177     __ bind(detect_586);
 178     __ xorl(rax, rax);
 179     __ cpuid();
 180     __ orl(rax, rax);
 181     __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
 182                                         // value of at least 1, we give up and
 183                                         // assume a 486
 184     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 185     __ movl(Address(rsi, 0), rax);
 186     __ movl(Address(rsi, 4), rbx);
 187     __ movl(Address(rsi, 8), rcx);
 188     __ movl(Address(rsi,12), rdx);
 189 
 190     __ cmpl(rax, 0xa);                  // Is cpuid(0xB) supported?
 191     __ jccb(Assembler::belowEqual, std_cpuid4);
 192 
 193     //
 194     // cpuid(0xB) Processor Topology
 195     //
 196     __ movl(rax, 0xb);
 197     __ xorl(rcx, rcx);   // Threads level
 198     __ cpuid();
 199 
 200     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
 201     __ movl(Address(rsi, 0), rax);
 202     __ movl(Address(rsi, 4), rbx);
 203     __ movl(Address(rsi, 8), rcx);
 204     __ movl(Address(rsi,12), rdx);
 205 
 206     __ movl(rax, 0xb);
 207     __ movl(rcx, 1);     // Cores level
 208     __ cpuid();
 209     __ push(rax);
 210     __ andl(rax, 0x1f);  // Determine if valid topology level
 211     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 212     __ andl(rax, 0xffff);
 213     __ pop(rax);
 214     __ jccb(Assembler::equal, std_cpuid4);
 215 
 216     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
 217     __ movl(Address(rsi, 0), rax);
 218     __ movl(Address(rsi, 4), rbx);
 219     __ movl(Address(rsi, 8), rcx);
 220     __ movl(Address(rsi,12), rdx);
 221 
 222     __ movl(rax, 0xb);
 223     __ movl(rcx, 2);     // Packages level
 224     __ cpuid();
 225     __ push(rax);
 226     __ andl(rax, 0x1f);  // Determine if valid topology level
 227     __ orl(rax, rbx);    // eax[4:0] | ebx[0:15] == 0 indicates invalid level
 228     __ andl(rax, 0xffff);
 229     __ pop(rax);
 230     __ jccb(Assembler::equal, std_cpuid4);
 231 
 232     __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
 233     __ movl(Address(rsi, 0), rax);
 234     __ movl(Address(rsi, 4), rbx);
 235     __ movl(Address(rsi, 8), rcx);
 236     __ movl(Address(rsi,12), rdx);
 237 
 238     //
 239     // cpuid(0x4) Deterministic cache params
 240     //
 241     __ bind(std_cpuid4);
 242     __ movl(rax, 4);
 243     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
 244     __ jccb(Assembler::greater, std_cpuid1);
 245 
 246     __ xorl(rcx, rcx);   // L1 cache
 247     __ cpuid();
 248     __ push(rax);
 249     __ andl(rax, 0x1f);  // Determine if valid cache parameters used
 250     __ orl(rax, rax);    // eax[4:0] == 0 indicates invalid cache
 251     __ pop(rax);
 252     __ jccb(Assembler::equal, std_cpuid1);
 253 
 254     __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
 255     __ movl(Address(rsi, 0), rax);
 256     __ movl(Address(rsi, 4), rbx);
 257     __ movl(Address(rsi, 8), rcx);
 258     __ movl(Address(rsi,12), rdx);
 259 
 260     //
 261     // Standard cpuid(0x1)
 262     //
 263     __ bind(std_cpuid1);
 264     __ movl(rax, 1);
 265     __ cpuid();
 266     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 267     __ movl(Address(rsi, 0), rax);
 268     __ movl(Address(rsi, 4), rbx);
 269     __ movl(Address(rsi, 8), rcx);
 270     __ movl(Address(rsi,12), rdx);
 271 
 272     //
 273     // Check if OS has enabled XGETBV instruction to access XCR0
 274     // (OSXSAVE feature flag) and CPU supports AVX
 275     //
 276     __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 277     __ cmpl(rcx, 0x18000000);
 278     __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
 279 
 280     //
 281     // XCR0, XFEATURE_ENABLED_MASK register
 282     //
 283     __ xorl(rcx, rcx);   // zero for XCR0 register
 284     __ xgetbv();
 285     __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
 286     __ movl(Address(rsi, 0), rax);
 287     __ movl(Address(rsi, 4), rdx);
 288 
 289     //
 290     // cpuid(0x7) Structured Extended Features
 291     //
 292     __ bind(sef_cpuid);
 293     __ movl(rax, 7);
 294     __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
 295     __ jccb(Assembler::greater, ext_cpuid);
 296 
 297     __ xorl(rcx, rcx);
 298     __ cpuid();
 299     __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 300     __ movl(Address(rsi, 0), rax);
 301     __ movl(Address(rsi, 4), rbx);
 302     __ movl(Address(rsi, 8), rcx);
 303     __ movl(Address(rsi, 12), rdx);
 304 
 305     //
 306     // Extended cpuid(0x80000000)
 307     //
 308     __ bind(ext_cpuid);
 309     __ movl(rax, 0x80000000);
 310     __ cpuid();
 311     __ cmpl(rax, 0x80000000);     // Is cpuid(0x80000001) supported?
 312     __ jcc(Assembler::belowEqual, done);
 313     __ cmpl(rax, 0x80000004);     // Is cpuid(0x80000005) supported?
 314     __ jcc(Assembler::belowEqual, ext_cpuid1);
 315     __ cmpl(rax, 0x80000006);     // Is cpuid(0x80000007) supported?
 316     __ jccb(Assembler::belowEqual, ext_cpuid5);
 317     __ cmpl(rax, 0x80000007);     // Is cpuid(0x80000008) supported?
 318     __ jccb(Assembler::belowEqual, ext_cpuid7);
 319     __ cmpl(rax, 0x80000008);     // Is cpuid(0x80000009 and above) supported?
 320     __ jccb(Assembler::belowEqual, ext_cpuid8);
 321     __ cmpl(rax, 0x8000001E);     // Is cpuid(0x8000001E) supported?
 322     __ jccb(Assembler::below, ext_cpuid8);
 323     //
 324     // Extended cpuid(0x8000001E)
 325     //
 326     __ movl(rax, 0x8000001E);
 327     __ cpuid();
 328     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1E_offset())));
 329     __ movl(Address(rsi, 0), rax);
 330     __ movl(Address(rsi, 4), rbx);
 331     __ movl(Address(rsi, 8), rcx);
 332     __ movl(Address(rsi,12), rdx);
 333 
 334     //
 335     // Extended cpuid(0x80000008)
 336     //
 337     __ bind(ext_cpuid8);
 338     __ movl(rax, 0x80000008);
 339     __ cpuid();
 340     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
 341     __ movl(Address(rsi, 0), rax);
 342     __ movl(Address(rsi, 4), rbx);
 343     __ movl(Address(rsi, 8), rcx);
 344     __ movl(Address(rsi,12), rdx);
 345 
 346     //
 347     // Extended cpuid(0x80000007)
 348     //
 349     __ bind(ext_cpuid7);
 350     __ movl(rax, 0x80000007);
 351     __ cpuid();
 352     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
 353     __ movl(Address(rsi, 0), rax);
 354     __ movl(Address(rsi, 4), rbx);
 355     __ movl(Address(rsi, 8), rcx);
 356     __ movl(Address(rsi,12), rdx);
 357 
 358     //
 359     // Extended cpuid(0x80000005)
 360     //
 361     __ bind(ext_cpuid5);
 362     __ movl(rax, 0x80000005);
 363     __ cpuid();
 364     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
 365     __ movl(Address(rsi, 0), rax);
 366     __ movl(Address(rsi, 4), rbx);
 367     __ movl(Address(rsi, 8), rcx);
 368     __ movl(Address(rsi,12), rdx);
 369 
 370     //
 371     // Extended cpuid(0x80000001)
 372     //
 373     __ bind(ext_cpuid1);
 374     __ movl(rax, 0x80000001);
 375     __ cpuid();
 376     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
 377     __ movl(Address(rsi, 0), rax);
 378     __ movl(Address(rsi, 4), rbx);
 379     __ movl(Address(rsi, 8), rcx);
 380     __ movl(Address(rsi,12), rdx);
 381 
 382     //
 383     // Check if OS has enabled XGETBV instruction to access XCR0
 384     // (OSXSAVE feature flag) and CPU supports AVX
 385     //
 386     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 387     __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
 388     __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
 389     __ cmpl(rcx, 0x18000000);
 390     __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
 391 
 392     __ movl(rax, 0x6);
 393     __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 394     __ cmpl(rax, 0x6);
 395     __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
 396 
 397     // we need to bridge farther than imm8, so we use this island as a thunk
 398     __ bind(done);
 399     __ jmp(wrapup);
 400 
 401     __ bind(start_simd_check);
 402     //
 403     // Some OSs have a bug when upper 128/256bits of YMM/ZMM
 404     // registers are not restored after a signal processing.
 405     // Generate SEGV here (reference through NULL)
 406     // and check upper YMM/ZMM bits after it.
 407     //
 408     intx saved_useavx = UseAVX;
 409     intx saved_usesse = UseSSE;
 410 
 411     // If UseAVX is unitialized or is set by the user to include EVEX
 412     if (use_evex) {
 413       // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
 414       __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 415       __ movl(rax, 0x10000);
 416       __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
 417       __ cmpl(rax, 0x10000);
 418       __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
 419       // check _cpuid_info.xem_xcr0_eax.bits.opmask
 420       // check _cpuid_info.xem_xcr0_eax.bits.zmm512
 421       // check _cpuid_info.xem_xcr0_eax.bits.zmm32
 422       __ movl(rax, 0xE0);
 423       __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 424       __ cmpl(rax, 0xE0);
 425       __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
 426 
 427       if (FLAG_IS_DEFAULT(UseAVX)) {
 428         __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 429         __ movl(rax, Address(rsi, 0));
 430         __ cmpl(rax, 0x50654);              // If it is Skylake
 431         __ jcc(Assembler::equal, legacy_setup);
 432       }
 433       // EVEX setup: run in lowest evex mode
 434       VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
 435       UseAVX = 3;
 436       UseSSE = 2;
 437 #ifdef _WINDOWS
 438       // xmm5-xmm15 are not preserved by caller on windows
 439       // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
 440       __ subptr(rsp, 64);
 441       __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
 442 #ifdef _LP64
 443       __ subptr(rsp, 64);
 444       __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
 445       __ subptr(rsp, 64);
 446       __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
 447 #endif // _LP64
 448 #endif // _WINDOWS
 449 
 450       // load value into all 64 bytes of zmm7 register
 451       __ movl(rcx, VM_Version::ymm_test_value());
 452       __ movdl(xmm0, rcx);
 453       __ vpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
 454       __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
 455 #ifdef _LP64
 456       __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
 457       __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
 458 #endif
 459       VM_Version::clean_cpuFeatures();
 460       __ jmp(save_restore_except);
 461     }
 462 
 463     __ bind(legacy_setup);
 464     // AVX setup
 465     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 466     UseAVX = 1;
 467     UseSSE = 2;
 468 #ifdef _WINDOWS
 469     __ subptr(rsp, 32);
 470     __ vmovdqu(Address(rsp, 0), xmm7);
 471 #ifdef _LP64
 472     __ subptr(rsp, 32);
 473     __ vmovdqu(Address(rsp, 0), xmm8);
 474     __ subptr(rsp, 32);
 475     __ vmovdqu(Address(rsp, 0), xmm15);
 476 #endif // _LP64
 477 #endif // _WINDOWS
 478 
 479     // load value into all 32 bytes of ymm7 register
 480     __ movl(rcx, VM_Version::ymm_test_value());
 481 
 482     __ movdl(xmm0, rcx);
 483     __ pshufd(xmm0, xmm0, 0x00);
 484     __ vinsertf128_high(xmm0, xmm0);
 485     __ vmovdqu(xmm7, xmm0);
 486 #ifdef _LP64
 487     __ vmovdqu(xmm8, xmm0);
 488     __ vmovdqu(xmm15, xmm0);
 489 #endif
 490     VM_Version::clean_cpuFeatures();
 491 
 492     __ bind(save_restore_except);
 493     __ xorl(rsi, rsi);
 494     VM_Version::set_cpuinfo_segv_addr(__ pc());
 495     // Generate SEGV
 496     __ movl(rax, Address(rsi, 0));
 497 
 498     VM_Version::set_cpuinfo_cont_addr(__ pc());
 499     // Returns here after signal. Save xmm0 to check it later.
 500 
 501     // If UseAVX is unitialized or is set by the user to include EVEX
 502     if (use_evex) {
 503       // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
 504       __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
 505       __ movl(rax, 0x10000);
 506       __ andl(rax, Address(rsi, 4));
 507       __ cmpl(rax, 0x10000);
 508       __ jcc(Assembler::notEqual, legacy_save_restore);
 509       // check _cpuid_info.xem_xcr0_eax.bits.opmask
 510       // check _cpuid_info.xem_xcr0_eax.bits.zmm512
 511       // check _cpuid_info.xem_xcr0_eax.bits.zmm32
 512       __ movl(rax, 0xE0);
 513       __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
 514       __ cmpl(rax, 0xE0);
 515       __ jcc(Assembler::notEqual, legacy_save_restore);
 516 
 517       if (FLAG_IS_DEFAULT(UseAVX)) {
 518         __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 519         __ movl(rax, Address(rsi, 0));
 520         __ cmpl(rax, 0x50654);              // If it is Skylake
 521         __ jcc(Assembler::equal, legacy_save_restore);
 522       }
 523       // EVEX check: run in lowest evex mode
 524       VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
 525       UseAVX = 3;
 526       UseSSE = 2;
 527       __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
 528       __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
 529       __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
 530 #ifdef _LP64
 531       __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
 532       __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
 533 #endif
 534 
 535 #ifdef _WINDOWS
 536 #ifdef _LP64
 537       __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
 538       __ addptr(rsp, 64);
 539       __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
 540       __ addptr(rsp, 64);
 541 #endif // _LP64
 542       __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
 543       __ addptr(rsp, 64);
 544 #endif // _WINDOWS
 545       generate_vzeroupper(wrapup);
 546       VM_Version::clean_cpuFeatures();
 547       UseAVX = saved_useavx;
 548       UseSSE = saved_usesse;
 549       __ jmp(wrapup);
 550    }
 551 
 552     __ bind(legacy_save_restore);
 553     // AVX check
 554     VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
 555     UseAVX = 1;
 556     UseSSE = 2;
 557     __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
 558     __ vmovdqu(Address(rsi, 0), xmm0);
 559     __ vmovdqu(Address(rsi, 32), xmm7);
 560 #ifdef _LP64
 561     __ vmovdqu(Address(rsi, 64), xmm8);
 562     __ vmovdqu(Address(rsi, 96), xmm15);
 563 #endif
 564 
 565 #ifdef _WINDOWS
 566 #ifdef _LP64
 567     __ vmovdqu(xmm15, Address(rsp, 0));
 568     __ addptr(rsp, 32);
 569     __ vmovdqu(xmm8, Address(rsp, 0));
 570     __ addptr(rsp, 32);
 571 #endif // _LP64
 572     __ vmovdqu(xmm7, Address(rsp, 0));
 573     __ addptr(rsp, 32);
 574 #endif // _WINDOWS
 575     generate_vzeroupper(wrapup);
 576     VM_Version::clean_cpuFeatures();
 577     UseAVX = saved_useavx;
 578     UseSSE = saved_usesse;
 579 
 580     __ bind(wrapup);
 581     __ popf();
 582     __ pop(rsi);
 583     __ pop(rbx);
 584     __ pop(rbp);
 585     __ ret(0);
 586 
 587 #   undef __
 588 
 589     return start;
 590   };
 591   void generate_vzeroupper(Label& L_wrapup) {
 592 #   define __ _masm->
 593     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
 594     __ cmpl(Address(rsi, 4), 0x756e6547);  // 'uneG'
 595     __ jcc(Assembler::notEqual, L_wrapup);
 596     __ movl(rcx, 0x0FFF0FF0);
 597     __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
 598     __ andl(rcx, Address(rsi, 0));
 599     __ cmpl(rcx, 0x00050670);              // If it is Xeon Phi 3200/5200/7200
 600     __ jcc(Assembler::equal, L_wrapup);
 601     __ cmpl(rcx, 0x00080650);              // If it is Future Xeon Phi
 602     __ jcc(Assembler::equal, L_wrapup);
 603     // vzeroupper() will use a pre-computed instruction sequence that we
 604     // can't compute until after we've determined CPU capabilities. Use
 605     // uncached variant here directly to be able to bootstrap correctly
 606     __ vzeroupper_uncached();
 607 #   undef __
 608   }
 609   address generate_detect_virt() {
 610     StubCodeMark mark(this, "VM_Version", "detect_virt_stub");
 611 #   define __ _masm->
 612 
 613     address start = __ pc();
 614 
 615     // Evacuate callee-saved registers
 616     __ push(rbp);
 617     __ push(rbx);
 618     __ push(rsi); // for Windows
 619 
 620 #ifdef _LP64
 621     __ mov(rax, c_rarg0); // CPUID leaf
 622     __ mov(rsi, c_rarg1); // register array address (eax, ebx, ecx, edx)
 623 #else
 624     __ movptr(rax, Address(rsp, 16)); // CPUID leaf
 625     __ movptr(rsi, Address(rsp, 20)); // register array address
 626 #endif
 627 
 628     __ cpuid();
 629 
 630     // Store result to register array
 631     __ movl(Address(rsi,  0), rax);
 632     __ movl(Address(rsi,  4), rbx);
 633     __ movl(Address(rsi,  8), rcx);
 634     __ movl(Address(rsi, 12), rdx);
 635 
 636     // Epilogue
 637     __ pop(rsi);
 638     __ pop(rbx);
 639     __ pop(rbp);
 640     __ ret(0);
 641 
 642 #   undef __
 643 
 644     return start;
 645   };
 646 
 647 
 648   address generate_getCPUIDBrandString(void) {
 649     // Flags to test CPU type.
 650     const uint32_t HS_EFL_AC           = 0x40000;
 651     const uint32_t HS_EFL_ID           = 0x200000;
 652     // Values for when we don't have a CPUID instruction.
 653     const int      CPU_FAMILY_SHIFT = 8;
 654     const uint32_t CPU_FAMILY_386   = (3 << CPU_FAMILY_SHIFT);
 655     const uint32_t CPU_FAMILY_486   = (4 << CPU_FAMILY_SHIFT);
 656 
 657     Label detect_486, cpu486, detect_586, done, ext_cpuid;
 658 
 659     StubCodeMark mark(this, "VM_Version", "getCPUIDNameInfo_stub");
 660 #   define __ _masm->
 661 
 662     address start = __ pc();
 663 
 664     //
 665     // void getCPUIDBrandString(VM_Version::CpuidInfo* cpuid_info);
 666     //
 667     // LP64: rcx and rdx are first and second argument registers on windows
 668 
 669     __ push(rbp);
 670 #ifdef _LP64
 671     __ mov(rbp, c_rarg0); // cpuid_info address
 672 #else
 673     __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
 674 #endif
 675     __ push(rbx);
 676     __ push(rsi);
 677     __ pushf();          // preserve rbx, and flags
 678     __ pop(rax);
 679     __ push(rax);
 680     __ mov(rcx, rax);
 681     //
 682     // if we are unable to change the AC flag, we have a 386
 683     //
 684     __ xorl(rax, HS_EFL_AC);
 685     __ push(rax);
 686     __ popf();
 687     __ pushf();
 688     __ pop(rax);
 689     __ cmpptr(rax, rcx);
 690     __ jccb(Assembler::notEqual, detect_486);
 691 
 692     __ movl(rax, CPU_FAMILY_386);
 693     __ jmp(done);
 694 
 695     //
 696     // If we are unable to change the ID flag, we have a 486 which does
 697     // not support the "cpuid" instruction.
 698     //
 699     __ bind(detect_486);
 700     __ mov(rax, rcx);
 701     __ xorl(rax, HS_EFL_ID);
 702     __ push(rax);
 703     __ popf();
 704     __ pushf();
 705     __ pop(rax);
 706     __ cmpptr(rcx, rax);
 707     __ jccb(Assembler::notEqual, detect_586);
 708 
 709     __ bind(cpu486);
 710     __ movl(rax, CPU_FAMILY_486);
 711     __ jmp(done);
 712 
 713     //
 714     // At this point, we have a chip which supports the "cpuid" instruction
 715     //
 716     __ bind(detect_586);
 717     __ xorl(rax, rax);
 718     __ cpuid();
 719     __ orl(rax, rax);
 720     __ jcc(Assembler::equal, cpu486);   // if cpuid doesn't support an input
 721                                         // value of at least 1, we give up and
 722                                         // assume a 486
 723 
 724     //
 725     // Extended cpuid(0x80000000) for processor brand string detection
 726     //
 727     __ bind(ext_cpuid);
 728     __ movl(rax, CPUID_EXTENDED_FN);
 729     __ cpuid();
 730     __ cmpl(rax, CPUID_EXTENDED_FN_4);
 731     __ jcc(Assembler::below, done);
 732 
 733     //
 734     // Extended cpuid(0x80000002)  // first 16 bytes in brand string
 735     //
 736     __ movl(rax, CPUID_EXTENDED_FN_2);
 737     __ cpuid();
 738     __ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_0_offset())));
 739     __ movl(Address(rsi, 0), rax);
 740     __ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_1_offset())));
 741     __ movl(Address(rsi, 0), rbx);
 742     __ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_2_offset())));
 743     __ movl(Address(rsi, 0), rcx);
 744     __ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_3_offset())));
 745     __ movl(Address(rsi,0), rdx);
 746 
 747     //
 748     // Extended cpuid(0x80000003) // next 16 bytes in brand string
 749     //
 750     __ movl(rax, CPUID_EXTENDED_FN_3);
 751     __ cpuid();
 752     __ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_4_offset())));
 753     __ movl(Address(rsi, 0), rax);
 754     __ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_5_offset())));
 755     __ movl(Address(rsi, 0), rbx);
 756     __ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_6_offset())));
 757     __ movl(Address(rsi, 0), rcx);
 758     __ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_7_offset())));
 759     __ movl(Address(rsi,0), rdx);
 760 
 761     //
 762     // Extended cpuid(0x80000004) // last 16 bytes in brand string
 763     //
 764     __ movl(rax, CPUID_EXTENDED_FN_4);
 765     __ cpuid();
 766     __ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_8_offset())));
 767     __ movl(Address(rsi, 0), rax);
 768     __ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_9_offset())));
 769     __ movl(Address(rsi, 0), rbx);
 770     __ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_10_offset())));
 771     __ movl(Address(rsi, 0), rcx);
 772     __ lea(rsi, Address(rbp, in_bytes(VM_Version::proc_name_11_offset())));
 773     __ movl(Address(rsi,0), rdx);
 774 
 775     //
 776     // return
 777     //
 778     __ bind(done);
 779     __ popf();
 780     __ pop(rsi);
 781     __ pop(rbx);
 782     __ pop(rbp);
 783     __ ret(0);
 784 
 785 #   undef __
 786 
 787     return start;
 788   };
 789 };
 790 
 791 void VM_Version::get_processor_features() {
 792 
 793   _cpu = 4; // 486 by default
 794   _model = 0;
 795   _stepping = 0;
 796   _features = 0;
 797   _logical_processors_per_package = 1;
 798   // i486 internal cache is both I&D and has a 16-byte line size
 799   _L1_data_cache_line_size = 16;
 800 
 801   // Get raw processor info
 802 
 803   get_cpu_info_stub(&_cpuid_info);
 804 
 805   assert_is_initialized();
 806   _cpu = extended_cpu_family();
 807   _model = extended_cpu_model();
 808   _stepping = cpu_stepping();
 809 
 810   if (cpu_family() > 4) { // it supports CPUID
 811     _features = feature_flags();
 812     // Logical processors are only available on P4s and above,
 813     // and only if hyperthreading is available.
 814     _logical_processors_per_package = logical_processor_count();
 815     _L1_data_cache_line_size = L1_line_size();
 816   }
 817 
 818   _supports_cx8 = supports_cmpxchg8();
 819   // xchg and xadd instructions
 820   _supports_atomic_getset4 = true;
 821   _supports_atomic_getadd4 = true;
 822   LP64_ONLY(_supports_atomic_getset8 = true);
 823   LP64_ONLY(_supports_atomic_getadd8 = true);
 824 
 825 #ifdef _LP64
 826   // OS should support SSE for x64 and hardware should support at least SSE2.
 827   if (!VM_Version::supports_sse2()) {
 828     vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
 829   }
 830   // in 64 bit the use of SSE2 is the minimum
 831   if (UseSSE < 2) UseSSE = 2;
 832 #endif
 833 
 834 #ifdef AMD64
 835   // flush_icache_stub have to be generated first.
 836   // That is why Icache line size is hard coded in ICache class,
 837   // see icache_x86.hpp. It is also the reason why we can't use
 838   // clflush instruction in 32-bit VM since it could be running
 839   // on CPU which does not support it.
 840   //
 841   // The only thing we can do is to verify that flushed
 842   // ICache::line_size has correct value.
 843   guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
 844   // clflush_size is size in quadwords (8 bytes).
 845   guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
 846 #endif
 847 
 848 #ifdef _LP64
 849   // assigning this field effectively enables Unsafe.writebackMemory()
 850   // by initing UnsafeConstant.DATA_CACHE_LINE_FLUSH_SIZE to non-zero
 851   // that is only implemented on x86_64 and only if the OS plays ball
 852   if (os::supports_map_sync()) {
 853     // publish data cache line flush size to generic field, otherwise
 854     // let if default to zero thereby disabling writeback
 855     _data_cache_line_flush_size = _cpuid_info.std_cpuid1_ebx.bits.clflush_size * 8;
 856   }
 857 #endif
 858   // If the OS doesn't support SSE, we can't use this feature even if the HW does
 859   if (!os::supports_sse())
 860     _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
 861 
 862   if (UseSSE < 4) {
 863     _features &= ~CPU_SSE4_1;
 864     _features &= ~CPU_SSE4_2;
 865   }
 866 
 867   if (UseSSE < 3) {
 868     _features &= ~CPU_SSE3;
 869     _features &= ~CPU_SSSE3;
 870     _features &= ~CPU_SSE4A;
 871   }
 872 
 873   if (UseSSE < 2)
 874     _features &= ~CPU_SSE2;
 875 
 876   if (UseSSE < 1)
 877     _features &= ~CPU_SSE;
 878 
 879   //since AVX instructions is slower than SSE in some ZX cpus, force USEAVX=0.
 880   if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7))) {
 881     UseAVX = 0;
 882   }
 883 
 884   // first try initial setting and detect what we can support
 885   int use_avx_limit = 0;
 886   if (UseAVX > 0) {
 887     if (UseAVX > 2 && supports_evex()) {
 888       use_avx_limit = 3;
 889     } else if (UseAVX > 1 && supports_avx2()) {
 890       use_avx_limit = 2;
 891     } else if (UseAVX > 0 && supports_avx()) {
 892       use_avx_limit = 1;
 893     } else {
 894       use_avx_limit = 0;
 895     }
 896   }
 897   if (FLAG_IS_DEFAULT(UseAVX)) {
 898     // Don't use AVX-512 on older Skylakes unless explicitly requested.
 899     if (use_avx_limit > 2 && is_intel_skylake() && _stepping < 5) {
 900       FLAG_SET_DEFAULT(UseAVX, 2);
 901     } else {
 902       FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
 903     }
 904   }
 905   if (UseAVX > use_avx_limit) {
 906     warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", (int) UseAVX, use_avx_limit);
 907     FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
 908   } else if (UseAVX < 0) {
 909     warning("UseAVX=%d is not valid, setting it to UseAVX=0", (int) UseAVX);
 910     FLAG_SET_DEFAULT(UseAVX, 0);
 911   }
 912 
 913   if (UseAVX < 3) {
 914     _features &= ~CPU_AVX512F;
 915     _features &= ~CPU_AVX512DQ;
 916     _features &= ~CPU_AVX512CD;
 917     _features &= ~CPU_AVX512BW;
 918     _features &= ~CPU_AVX512VL;
 919     _features &= ~CPU_AVX512_VPOPCNTDQ;
 920     _features &= ~CPU_AVX512_VPCLMULQDQ;
 921     _features &= ~CPU_AVX512_VAES;
 922     _features &= ~CPU_AVX512_VNNI;
 923     _features &= ~CPU_AVX512_VBMI;
 924     _features &= ~CPU_AVX512_VBMI2;
 925   }
 926 
 927   if (UseAVX < 2)
 928     _features &= ~CPU_AVX2;
 929 
 930   if (UseAVX < 1) {
 931     _features &= ~CPU_AVX;
 932     _features &= ~CPU_VZEROUPPER;
 933   }
 934 
 935   if (logical_processors_per_package() == 1) {
 936     // HT processor could be installed on a system which doesn't support HT.
 937     _features &= ~CPU_HT;
 938   }
 939 
 940   if (is_intel()) { // Intel cpus specific settings
 941     if (is_knights_family()) {
 942       _features &= ~CPU_VZEROUPPER;
 943       _features &= ~CPU_AVX512BW;
 944       _features &= ~CPU_AVX512VL;
 945       _features &= ~CPU_AVX512DQ;
 946       _features &= ~CPU_AVX512_VNNI;
 947       _features &= ~CPU_AVX512_VAES;
 948       _features &= ~CPU_AVX512_VPOPCNTDQ;
 949       _features &= ~CPU_AVX512_VPCLMULQDQ;
 950       _features &= ~CPU_AVX512_VBMI;
 951       _features &= ~CPU_AVX512_VBMI2;
 952       _features &= ~CPU_CLWB;
 953       _features &= ~CPU_FLUSHOPT;
 954     }
 955   }
 956 
 957   if (FLAG_IS_DEFAULT(IntelJccErratumMitigation)) {
 958     _has_intel_jcc_erratum = compute_has_intel_jcc_erratum();
 959   } else {
 960     _has_intel_jcc_erratum = IntelJccErratumMitigation;
 961   }
 962 
 963   char buf[512];
 964   int res = jio_snprintf(
 965               buf, sizeof(buf),
 966               "(%u cores per cpu, %u threads per core) family %d model %d stepping %d microcode 0x%x",
 967               cores_per_cpu(), threads_per_core(),
 968               cpu_family(), _model, _stepping, os::cpu_microcode_revision());
 969   assert(res > 0, "not enough temporary space allocated");
 970   insert_features_names(buf + res, sizeof(buf) - res, _features_names);
 971 
 972   _features_string = os::strdup(buf);
 973 
 974   // UseSSE is set to the smaller of what hardware supports and what
 975   // the command line requires.  I.e., you cannot set UseSSE to 2 on
 976   // older Pentiums which do not support it.
 977   int use_sse_limit = 0;
 978   if (UseSSE > 0) {
 979     if (UseSSE > 3 && supports_sse4_1()) {
 980       use_sse_limit = 4;
 981     } else if (UseSSE > 2 && supports_sse3()) {
 982       use_sse_limit = 3;
 983     } else if (UseSSE > 1 && supports_sse2()) {
 984       use_sse_limit = 2;
 985     } else if (UseSSE > 0 && supports_sse()) {
 986       use_sse_limit = 1;
 987     } else {
 988       use_sse_limit = 0;
 989     }
 990   }
 991   if (FLAG_IS_DEFAULT(UseSSE)) {
 992     FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
 993   } else if (UseSSE > use_sse_limit) {
 994     warning("UseSSE=%d is not supported on this CPU, setting it to UseSSE=%d", (int) UseSSE, use_sse_limit);
 995     FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
 996   } else if (UseSSE < 0) {
 997     warning("UseSSE=%d is not valid, setting it to UseSSE=0", (int) UseSSE);
 998     FLAG_SET_DEFAULT(UseSSE, 0);
 999   }
1000 
1001   // Use AES instructions if available.
1002   if (supports_aes()) {
1003     if (FLAG_IS_DEFAULT(UseAES)) {
1004       FLAG_SET_DEFAULT(UseAES, true);
1005     }
1006     if (!UseAES) {
1007       if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1008         warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
1009       }
1010       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
1011     } else {
1012       if (UseSSE > 2) {
1013         if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1014           FLAG_SET_DEFAULT(UseAESIntrinsics, true);
1015         }
1016       } else {
1017         // The AES intrinsic stubs require AES instruction support (of course)
1018         // but also require sse3 mode or higher for instructions it use.
1019         if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1020           warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
1021         }
1022         FLAG_SET_DEFAULT(UseAESIntrinsics, false);
1023       }
1024 
1025       // --AES-CTR begins--
1026       if (!UseAESIntrinsics) {
1027         if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
1028           warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
1029           FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
1030         }
1031       } else {
1032         if (supports_sse4_1()) {
1033           if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
1034             FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
1035           }
1036         } else {
1037            // The AES-CTR intrinsic stubs require AES instruction support (of course)
1038            // but also require sse4.1 mode or higher for instructions it use.
1039           if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
1040              warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
1041            }
1042            FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
1043         }
1044       }
1045       // --AES-CTR ends--
1046     }
1047   } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
1048     if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
1049       warning("AES instructions are not available on this CPU");
1050       FLAG_SET_DEFAULT(UseAES, false);
1051     }
1052     if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1053       warning("AES intrinsics are not available on this CPU");
1054       FLAG_SET_DEFAULT(UseAESIntrinsics, false);
1055     }
1056     if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
1057       warning("AES-CTR intrinsics are not available on this CPU");
1058       FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
1059     }
1060   }
1061 
1062   // Use CLMUL instructions if available.
1063   if (supports_clmul()) {
1064     if (FLAG_IS_DEFAULT(UseCLMUL)) {
1065       UseCLMUL = true;
1066     }
1067   } else if (UseCLMUL) {
1068     if (!FLAG_IS_DEFAULT(UseCLMUL))
1069       warning("CLMUL instructions not available on this CPU (AVX may also be required)");
1070     FLAG_SET_DEFAULT(UseCLMUL, false);
1071   }
1072 
1073   if (UseCLMUL && (UseSSE > 2)) {
1074     if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
1075       UseCRC32Intrinsics = true;
1076     }
1077   } else if (UseCRC32Intrinsics) {
1078     if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
1079       warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
1080     FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
1081   }
1082 
1083 #ifdef _LP64
1084   if (supports_avx2()) {
1085     if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
1086       UseAdler32Intrinsics = true;
1087     }
1088   } else if (UseAdler32Intrinsics) {
1089     if (!FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
1090       warning("Adler32 Intrinsics requires avx2 instructions (not available on this CPU)");
1091     }
1092     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
1093   }
1094 #else
1095   if (UseAdler32Intrinsics) {
1096     warning("Adler32Intrinsics not available on this CPU.");
1097     FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
1098   }
1099 #endif
1100 
1101   if (supports_sse4_2() && supports_clmul()) {
1102     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
1103       UseCRC32CIntrinsics = true;
1104     }
1105   } else if (UseCRC32CIntrinsics) {
1106     if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
1107       warning("CRC32C intrinsics are not available on this CPU");
1108     }
1109     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
1110   }
1111 
1112   // GHASH/GCM intrinsics
1113   if (UseCLMUL && (UseSSE > 2)) {
1114     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
1115       UseGHASHIntrinsics = true;
1116     }
1117   } else if (UseGHASHIntrinsics) {
1118     if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
1119       warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
1120     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
1121   }
1122 
1123   // Base64 Intrinsics (Check the condition for which the intrinsic will be active)
1124   if ((UseAVX > 2) && supports_avx512vl() && supports_avx512bw()) {
1125     if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
1126       UseBASE64Intrinsics = true;
1127     }
1128   } else if (UseBASE64Intrinsics) {
1129      if (!FLAG_IS_DEFAULT(UseBASE64Intrinsics))
1130       warning("Base64 intrinsic requires EVEX instructions on this CPU");
1131     FLAG_SET_DEFAULT(UseBASE64Intrinsics, false);
1132   }
1133 
1134   if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions
1135     if (FLAG_IS_DEFAULT(UseFMA)) {
1136       UseFMA = true;
1137     }
1138   } else if (UseFMA) {
1139     warning("FMA instructions are not available on this CPU");
1140     FLAG_SET_DEFAULT(UseFMA, false);
1141   }
1142 
1143   if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
1144     UseMD5Intrinsics = true;
1145   }
1146 
1147   if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
1148     if (FLAG_IS_DEFAULT(UseSHA)) {
1149       UseSHA = true;
1150     }
1151   } else if (UseSHA) {
1152     warning("SHA instructions are not available on this CPU");
1153     FLAG_SET_DEFAULT(UseSHA, false);
1154   }
1155 
1156   if (supports_sha() && supports_sse4_1() && UseSHA) {
1157     if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
1158       FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
1159     }
1160   } else if (UseSHA1Intrinsics) {
1161     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
1162     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
1163   }
1164 
1165   if (supports_sse4_1() && UseSHA) {
1166     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
1167       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
1168     }
1169   } else if (UseSHA256Intrinsics) {
1170     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
1171     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
1172   }
1173 
1174 #ifdef _LP64
1175   // These are only supported on 64-bit
1176   if (UseSHA && supports_avx2() && supports_bmi2()) {
1177     if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
1178       FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
1179     }
1180   } else
1181 #endif
1182   if (UseSHA512Intrinsics) {
1183     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
1184     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
1185   }
1186 
1187   if (UseSHA3Intrinsics) {
1188     warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
1189     FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
1190   }
1191 
1192   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
1193     FLAG_SET_DEFAULT(UseSHA, false);
1194   }
1195 
1196   if (!supports_rtm() && UseRTMLocking) {
1197     vm_exit_during_initialization("RTM instructions are not available on this CPU");
1198   }
1199 
1200 #if INCLUDE_RTM_OPT
1201   if (UseRTMLocking) {
1202     if (!CompilerConfig::is_c2_enabled()) {
1203       // Only C2 does RTM locking optimization.
1204       vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
1205     }
1206     if (is_intel_family_core()) {
1207       if ((_model == CPU_MODEL_HASWELL_E3) ||
1208           (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
1209           (_model == CPU_MODEL_BROADWELL  && _stepping < 4)) {
1210         // currently a collision between SKL and HSW_E3
1211         if (!UnlockExperimentalVMOptions && UseAVX < 3) {
1212           vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this "
1213                                         "platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
1214         } else {
1215           warning("UseRTMLocking is only available as experimental option on this platform.");
1216         }
1217       }
1218     }
1219     if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
1220       // RTM locking should be used only for applications with
1221       // high lock contention. For now we do not use it by default.
1222       vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
1223     }
1224   } else { // !UseRTMLocking
1225     if (UseRTMForStackLocks) {
1226       if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
1227         warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
1228       }
1229       FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
1230     }
1231     if (UseRTMDeopt) {
1232       FLAG_SET_DEFAULT(UseRTMDeopt, false);
1233     }
1234     if (PrintPreciseRTMLockingStatistics) {
1235       FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
1236     }
1237   }
1238 #else
1239   if (UseRTMLocking) {
1240     // Only C2 does RTM locking optimization.
1241     vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
1242   }
1243 #endif
1244 
1245 #ifdef COMPILER2
1246   if (UseFPUForSpilling) {
1247     if (UseSSE < 2) {
1248       // Only supported with SSE2+
1249       FLAG_SET_DEFAULT(UseFPUForSpilling, false);
1250     }
1251   }
1252 #endif
1253 
1254 #if COMPILER2_OR_JVMCI
1255   int max_vector_size = 0;
1256   if (UseSSE < 2) {
1257     // Vectors (in XMM) are only supported with SSE2+
1258     // SSE is always 2 on x64.
1259     max_vector_size = 0;
1260   } else if (UseAVX == 0 || !os_supports_avx_vectors()) {
1261     // 16 byte vectors (in XMM) are supported with SSE2+
1262     max_vector_size = 16;
1263   } else if (UseAVX == 1 || UseAVX == 2) {
1264     // 32 bytes vectors (in YMM) are only supported with AVX+
1265     max_vector_size = 32;
1266   } else if (UseAVX > 2) {
1267     // 64 bytes vectors (in ZMM) are only supported with AVX 3
1268     max_vector_size = 64;
1269   }
1270 
1271 #ifdef _LP64
1272   int min_vector_size = 4; // We require MaxVectorSize to be at least 4 on 64bit
1273 #else
1274   int min_vector_size = 0;
1275 #endif
1276 
1277   if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
1278     if (MaxVectorSize < min_vector_size) {
1279       warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
1280       FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
1281     }
1282     if (MaxVectorSize > max_vector_size) {
1283       warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
1284       FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1285     }
1286     if (!is_power_of_2(MaxVectorSize)) {
1287       warning("MaxVectorSize must be a power of 2, setting to default: %i", max_vector_size);
1288       FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1289     }
1290   } else {
1291     // If default, use highest supported configuration
1292     FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1293   }
1294 
1295 #if defined(COMPILER2) && defined(ASSERT)
1296   if (MaxVectorSize > 0) {
1297     if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
1298       tty->print_cr("State of YMM registers after signal handle:");
1299       int nreg = 2 LP64_ONLY(+2);
1300       const char* ymm_name[4] = {"0", "7", "8", "15"};
1301       for (int i = 0; i < nreg; i++) {
1302         tty->print("YMM%s:", ymm_name[i]);
1303         for (int j = 7; j >=0; j--) {
1304           tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
1305         }
1306         tty->cr();
1307       }
1308     }
1309   }
1310 #endif // COMPILER2 && ASSERT
1311 
1312 #ifdef _LP64
1313   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1314     UseMultiplyToLenIntrinsic = true;
1315   }
1316   if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1317     UseSquareToLenIntrinsic = true;
1318   }
1319   if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1320     UseMulAddIntrinsic = true;
1321   }
1322   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1323     UseMontgomeryMultiplyIntrinsic = true;
1324   }
1325   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1326     UseMontgomerySquareIntrinsic = true;
1327   }
1328 #else
1329   if (UseMultiplyToLenIntrinsic) {
1330     if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1331       warning("multiplyToLen intrinsic is not available in 32-bit VM");
1332     }
1333     FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1334   }
1335   if (UseMontgomeryMultiplyIntrinsic) {
1336     if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1337       warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1338     }
1339     FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1340   }
1341   if (UseMontgomerySquareIntrinsic) {
1342     if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1343       warning("montgomerySquare intrinsic is not available in 32-bit VM");
1344     }
1345     FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1346   }
1347   if (UseSquareToLenIntrinsic) {
1348     if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1349       warning("squareToLen intrinsic is not available in 32-bit VM");
1350     }
1351     FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1352   }
1353   if (UseMulAddIntrinsic) {
1354     if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1355       warning("mulAdd intrinsic is not available in 32-bit VM");
1356     }
1357     FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1358   }
1359 #endif // _LP64
1360 #endif // COMPILER2_OR_JVMCI
1361 
1362   // On new cpus instructions which update whole XMM register should be used
1363   // to prevent partial register stall due to dependencies on high half.
1364   //
1365   // UseXmmLoadAndClearUpper == true  --> movsd(xmm, mem)
1366   // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1367   // UseXmmRegToRegMoveAll == true  --> movaps(xmm, xmm), movapd(xmm, xmm).
1368   // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm),  movsd(xmm, xmm).
1369 
1370 
1371   if (is_zx()) { // ZX cpus specific settings
1372     if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1373       UseStoreImmI16 = false; // don't use it on ZX cpus
1374     }
1375     if ((cpu_family() == 6) || (cpu_family() == 7)) {
1376       if (FLAG_IS_DEFAULT(UseAddressNop)) {
1377         // Use it on all ZX cpus
1378         UseAddressNop = true;
1379       }
1380     }
1381     if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1382       UseXmmLoadAndClearUpper = true; // use movsd on all ZX cpus
1383     }
1384     if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1385       if (supports_sse3()) {
1386         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new ZX cpus
1387       } else {
1388         UseXmmRegToRegMoveAll = false;
1389       }
1390     }
1391     if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) { // new ZX cpus
1392 #ifdef COMPILER2
1393       if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1394         // For new ZX cpus do the next optimization:
1395         // don't align the beginning of a loop if there are enough instructions
1396         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1397         // in current fetch line (OptoLoopAlignment) or the padding
1398         // is big (> MaxLoopPad).
1399         // Set MaxLoopPad to 11 for new ZX cpus to reduce number of
1400         // generated NOP instructions. 11 is the largest size of one
1401         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1402         MaxLoopPad = 11;
1403       }
1404 #endif // COMPILER2
1405       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1406         UseXMMForArrayCopy = true; // use SSE2 movq on new ZX cpus
1407       }
1408       if (supports_sse4_2()) { // new ZX cpus
1409         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1410           UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus
1411         }
1412       }
1413       if (supports_sse4_2()) {
1414         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1415           FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1416         }
1417       } else {
1418         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1419           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1420         }
1421         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1422       }
1423     }
1424 
1425     if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1426       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1427     }
1428   }
1429 
1430   if (is_amd_family()) { // AMD cpus specific settings
1431     if (supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop)) {
1432       // Use it on new AMD cpus starting from Opteron.
1433       UseAddressNop = true;
1434     }
1435     if (supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift)) {
1436       // Use it on new AMD cpus starting from Opteron.
1437       UseNewLongLShift = true;
1438     }
1439     if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1440       if (supports_sse4a()) {
1441         UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1442       } else {
1443         UseXmmLoadAndClearUpper = false;
1444       }
1445     }
1446     if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1447       if (supports_sse4a()) {
1448         UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1449       } else {
1450         UseXmmRegToRegMoveAll = false;
1451       }
1452     }
1453     if (FLAG_IS_DEFAULT(UseXmmI2F)) {
1454       if (supports_sse4a()) {
1455         UseXmmI2F = true;
1456       } else {
1457         UseXmmI2F = false;
1458       }
1459     }
1460     if (FLAG_IS_DEFAULT(UseXmmI2D)) {
1461       if (supports_sse4a()) {
1462         UseXmmI2D = true;
1463       } else {
1464         UseXmmI2D = false;
1465       }
1466     }
1467     if (supports_sse4_2()) {
1468       if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1469         FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1470       }
1471     } else {
1472       if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1473         warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1474       }
1475       FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1476     }
1477 
1478     // some defaults for AMD family 15h
1479     if (cpu_family() == 0x15) {
1480       // On family 15h processors default is no sw prefetch
1481       if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1482         FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1483       }
1484       // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1485       if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1486         FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1487       }
1488       // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1489       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1490         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1491       }
1492       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1493         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1494       }
1495     }
1496 
1497 #ifdef COMPILER2
1498     if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1499       // Limit vectors size to 16 bytes on AMD cpus < 17h.
1500       FLAG_SET_DEFAULT(MaxVectorSize, 16);
1501     }
1502 #endif // COMPILER2
1503 
1504     // Some defaults for AMD family >= 17h && Hygon family 18h
1505     if (cpu_family() >= 0x17) {
1506       // On family >=17h processors use XMM and UnalignedLoadStores
1507       // for Array Copy
1508       if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1509         FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1510       }
1511       if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1512         FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1513       }
1514 #ifdef COMPILER2
1515       if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1516         FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1517       }
1518 #endif
1519     }
1520   }
1521 
1522   if (is_intel()) { // Intel cpus specific settings
1523     if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1524       UseStoreImmI16 = false; // don't use it on Intel cpus
1525     }
1526     if (cpu_family() == 6 || cpu_family() == 15) {
1527       if (FLAG_IS_DEFAULT(UseAddressNop)) {
1528         // Use it on all Intel cpus starting from PentiumPro
1529         UseAddressNop = true;
1530       }
1531     }
1532     if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1533       UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1534     }
1535     if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1536       if (supports_sse3()) {
1537         UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1538       } else {
1539         UseXmmRegToRegMoveAll = false;
1540       }
1541     }
1542     if (cpu_family() == 6 && supports_sse3()) { // New Intel cpus
1543 #ifdef COMPILER2
1544       if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1545         // For new Intel cpus do the next optimization:
1546         // don't align the beginning of a loop if there are enough instructions
1547         // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1548         // in current fetch line (OptoLoopAlignment) or the padding
1549         // is big (> MaxLoopPad).
1550         // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1551         // generated NOP instructions. 11 is the largest size of one
1552         // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1553         MaxLoopPad = 11;
1554       }
1555 #endif // COMPILER2
1556 
1557       if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1558         UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1559       }
1560       if ((supports_sse4_2() && supports_ht()) || supports_avx()) { // Newest Intel cpus
1561         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1562           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1563         }
1564       }
1565       if (supports_sse4_2()) {
1566         if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1567           FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1568         }
1569       } else {
1570         if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1571           warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1572         }
1573         FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1574       }
1575     }
1576     if (is_atom_family() || is_knights_family()) {
1577 #ifdef COMPILER2
1578       if (FLAG_IS_DEFAULT(OptoScheduling)) {
1579         OptoScheduling = true;
1580       }
1581 #endif
1582       if (supports_sse4_2()) { // Silvermont
1583         if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1584           UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1585         }
1586       }
1587       if (FLAG_IS_DEFAULT(UseIncDec)) {
1588         FLAG_SET_DEFAULT(UseIncDec, false);
1589       }
1590     }
1591     if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1592       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1593     }
1594 #ifdef COMPILER2
1595     if (UseAVX > 2) {
1596       if (FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize) ||
1597           (!FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize) &&
1598            ArrayOperationPartialInlineSize != 0 &&
1599            ArrayOperationPartialInlineSize != 16 &&
1600            ArrayOperationPartialInlineSize != 32 &&
1601            ArrayOperationPartialInlineSize != 64)) {
1602         int inline_size = 0;
1603         if (MaxVectorSize >= 64 && AVX3Threshold == 0) {
1604           inline_size = 64;
1605         } else if (MaxVectorSize >= 32) {
1606           inline_size = 32;
1607         } else if (MaxVectorSize >= 16) {
1608           inline_size = 16;
1609         }
1610         if(!FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize)) {
1611           warning("Setting ArrayOperationPartialInlineSize as %d", inline_size);
1612         }
1613         ArrayOperationPartialInlineSize = inline_size;
1614       }
1615 
1616       if (ArrayOperationPartialInlineSize > MaxVectorSize) {
1617         ArrayOperationPartialInlineSize = MaxVectorSize >= 16 ? MaxVectorSize : 0;
1618         if (ArrayOperationPartialInlineSize) {
1619           warning("Setting ArrayOperationPartialInlineSize as MaxVectorSize" INTX_FORMAT ")", MaxVectorSize);
1620         } else {
1621           warning("Setting ArrayOperationPartialInlineSize as " INTX_FORMAT, ArrayOperationPartialInlineSize);
1622         }
1623       }
1624     }
1625 #endif
1626   }
1627 
1628 #ifdef COMPILER2
1629   if (FLAG_IS_DEFAULT(OptimizeFill)) {
1630     if (MaxVectorSize < 32 || !VM_Version::supports_avx512vlbw()) {
1631       OptimizeFill = false;
1632     }
1633   }
1634 #endif
1635 
1636 #ifdef _LP64
1637   if (UseSSE42Intrinsics) {
1638     if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1639       UseVectorizedMismatchIntrinsic = true;
1640     }
1641   } else if (UseVectorizedMismatchIntrinsic) {
1642     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1643       warning("vectorizedMismatch intrinsics are not available on this CPU");
1644     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1645   }
1646 #else
1647   if (UseVectorizedMismatchIntrinsic) {
1648     if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1649       warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1650     }
1651     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1652   }
1653 #endif // _LP64
1654 
1655   // Use count leading zeros count instruction if available.
1656   if (supports_lzcnt()) {
1657     if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1658       UseCountLeadingZerosInstruction = true;
1659     }
1660    } else if (UseCountLeadingZerosInstruction) {
1661     warning("lzcnt instruction is not available on this CPU");
1662     FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1663   }
1664 
1665   // Use count trailing zeros instruction if available
1666   if (supports_bmi1()) {
1667     // tzcnt does not require VEX prefix
1668     if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1669       if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1670         // Don't use tzcnt if BMI1 is switched off on command line.
1671         UseCountTrailingZerosInstruction = false;
1672       } else {
1673         UseCountTrailingZerosInstruction = true;
1674       }
1675     }
1676   } else if (UseCountTrailingZerosInstruction) {
1677     warning("tzcnt instruction is not available on this CPU");
1678     FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1679   }
1680 
1681   // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1682   // VEX prefix is generated only when AVX > 0.
1683   if (supports_bmi1() && supports_avx()) {
1684     if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1685       UseBMI1Instructions = true;
1686     }
1687   } else if (UseBMI1Instructions) {
1688     warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1689     FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1690   }
1691 
1692   if (supports_bmi2() && supports_avx()) {
1693     if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1694       UseBMI2Instructions = true;
1695     }
1696   } else if (UseBMI2Instructions) {
1697     warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1698     FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1699   }
1700 
1701   // Use population count instruction if available.
1702   if (supports_popcnt()) {
1703     if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1704       UsePopCountInstruction = true;
1705     }
1706   } else if (UsePopCountInstruction) {
1707     warning("POPCNT instruction is not available on this CPU");
1708     FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1709   }
1710 
1711   // Use fast-string operations if available.
1712   if (supports_erms()) {
1713     if (FLAG_IS_DEFAULT(UseFastStosb)) {
1714       UseFastStosb = true;
1715     }
1716   } else if (UseFastStosb) {
1717     warning("fast-string operations are not available on this CPU");
1718     FLAG_SET_DEFAULT(UseFastStosb, false);
1719   }
1720 
1721   // For AMD Processors use XMM/YMM MOVDQU instructions
1722   // for Object Initialization as default
1723   if (is_amd() && cpu_family() >= 0x19) {
1724     if (FLAG_IS_DEFAULT(UseFastStosb)) {
1725       UseFastStosb = false;
1726     }
1727   }
1728 
1729 #ifdef COMPILER2
1730   if (is_intel() && MaxVectorSize > 16) {
1731     if (FLAG_IS_DEFAULT(UseFastStosb)) {
1732       UseFastStosb = false;
1733     }
1734   }
1735 #endif
1736 
1737   // Use XMM/YMM MOVDQU instruction for Object Initialization
1738   if (!UseFastStosb && UseSSE >= 2 && UseUnalignedLoadStores) {
1739     if (FLAG_IS_DEFAULT(UseXMMForObjInit)) {
1740       UseXMMForObjInit = true;
1741     }
1742   } else if (UseXMMForObjInit) {
1743     warning("UseXMMForObjInit requires SSE2 and unaligned load/stores. Feature is switched off.");
1744     FLAG_SET_DEFAULT(UseXMMForObjInit, false);
1745   }
1746 
1747 #ifdef COMPILER2
1748   if (FLAG_IS_DEFAULT(AlignVector)) {
1749     // Modern processors allow misaligned memory operations for vectors.
1750     AlignVector = !UseUnalignedLoadStores;
1751   }
1752 #endif // COMPILER2
1753 
1754   if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1755     if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1756       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
1757     } else if (!supports_sse() && supports_3dnow_prefetch()) {
1758       FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1759     }
1760   }
1761 
1762   // Allocation prefetch settings
1763   intx cache_line_size = prefetch_data_size();
1764   if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
1765       (cache_line_size > AllocatePrefetchStepSize)) {
1766     FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
1767   }
1768 
1769   if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
1770     assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
1771     if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1772       warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
1773     }
1774     FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1775   }
1776 
1777   if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1778     bool use_watermark_prefetch = (AllocatePrefetchStyle == 2);
1779     FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch));
1780   }
1781 
1782   if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1783     if (FLAG_IS_DEFAULT(AllocatePrefetchLines) &&
1784         supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1785       FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1786     }
1787 #ifdef COMPILER2
1788     if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) {
1789       FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1790     }
1791 #endif
1792   }
1793 
1794   if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) {
1795 #ifdef COMPILER2
1796     if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1797       FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1798     }
1799 #endif
1800   }
1801 
1802 #ifdef _LP64
1803   // Prefetch settings
1804 
1805   // Prefetch interval for gc copy/scan == 9 dcache lines.  Derived from
1806   // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
1807   // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
1808   // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
1809 
1810   // gc copy/scan is disabled if prefetchw isn't supported, because
1811   // Prefetch::write emits an inlined prefetchw on Linux.
1812   // Do not use the 3dnow prefetchw instruction.  It isn't supported on em64t.
1813   // The used prefetcht0 instruction works for both amd64 and em64t.
1814 
1815   if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
1816     FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 576);
1817   }
1818   if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1819     FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1820   }
1821 #endif
1822 
1823   if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1824      (cache_line_size > ContendedPaddingWidth))
1825      ContendedPaddingWidth = cache_line_size;
1826 
1827   // This machine allows unaligned memory accesses
1828   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1829     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1830   }
1831 
1832 #ifndef PRODUCT
1833   if (log_is_enabled(Info, os, cpu)) {
1834     LogStream ls(Log(os, cpu)::info());
1835     outputStream* log = &ls;
1836     log->print_cr("Logical CPUs per core: %u",
1837                   logical_processors_per_package());
1838     log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1839     log->print("UseSSE=%d", (int) UseSSE);
1840     if (UseAVX > 0) {
1841       log->print("  UseAVX=%d", (int) UseAVX);
1842     }
1843     if (UseAES) {
1844       log->print("  UseAES=1");
1845     }
1846 #ifdef COMPILER2
1847     if (MaxVectorSize > 0) {
1848       log->print("  MaxVectorSize=%d", (int) MaxVectorSize);
1849     }
1850 #endif
1851     log->cr();
1852     log->print("Allocation");
1853     if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) {
1854       log->print_cr(": no prefetching");
1855     } else {
1856       log->print(" prefetching: ");
1857       if (UseSSE == 0 && supports_3dnow_prefetch()) {
1858         log->print("PREFETCHW");
1859       } else if (UseSSE >= 1) {
1860         if (AllocatePrefetchInstr == 0) {
1861           log->print("PREFETCHNTA");
1862         } else if (AllocatePrefetchInstr == 1) {
1863           log->print("PREFETCHT0");
1864         } else if (AllocatePrefetchInstr == 2) {
1865           log->print("PREFETCHT2");
1866         } else if (AllocatePrefetchInstr == 3) {
1867           log->print("PREFETCHW");
1868         }
1869       }
1870       if (AllocatePrefetchLines > 1) {
1871         log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1872       } else {
1873         log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1874       }
1875     }
1876 
1877     if (PrefetchCopyIntervalInBytes > 0) {
1878       log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1879     }
1880     if (PrefetchScanIntervalInBytes > 0) {
1881       log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1882     }
1883     if (ContendedPaddingWidth > 0) {
1884       log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1885     }
1886   }
1887 #endif // !PRODUCT
1888   if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
1889       FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
1890   }
1891   if (FLAG_IS_DEFAULT(UseCopySignIntrinsic)) {
1892       FLAG_SET_DEFAULT(UseCopySignIntrinsic, true);
1893   }
1894 }
1895 
1896 void VM_Version::print_platform_virtualization_info(outputStream* st) {
1897   VirtualizationType vrt = VM_Version::get_detected_virtualization();
1898   if (vrt == XenHVM) {
1899     st->print_cr("Xen hardware-assisted virtualization detected");
1900   } else if (vrt == KVM) {
1901     st->print_cr("KVM virtualization detected");
1902   } else if (vrt == VMWare) {
1903     st->print_cr("VMWare virtualization detected");
1904     VirtualizationSupport::print_virtualization_info(st);
1905   } else if (vrt == HyperV) {
1906     st->print_cr("Hyper-V virtualization detected");
1907   } else if (vrt == HyperVRole) {
1908     st->print_cr("Hyper-V role detected");
1909   }
1910 }
1911 
1912 bool VM_Version::compute_has_intel_jcc_erratum() {
1913   if (!is_intel_family_core()) {
1914     // Only Intel CPUs are affected.
1915     return false;
1916   }
1917   // The following table of affected CPUs is based on the following document released by Intel:
1918   // https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf
1919   switch (_model) {
1920   case 0x8E:
1921     // 06_8EH | 9 | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Amber Lake Y
1922     // 06_8EH | 9 | 7th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake U
1923     // 06_8EH | 9 | 7th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake U 23e
1924     // 06_8EH | 9 | 7th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake Y
1925     // 06_8EH | A | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Coffee Lake U43e
1926     // 06_8EH | B | 8th Generation Intel(R) Core(TM) Processors based on microarchitecture code name Whiskey Lake U
1927     // 06_8EH | C | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Amber Lake Y
1928     // 06_8EH | C | 10th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Comet Lake U42
1929     // 06_8EH | C | 8th Generation Intel(R) Core(TM) Processors based on microarchitecture code name Whiskey Lake U
1930     return _stepping == 0x9 || _stepping == 0xA || _stepping == 0xB || _stepping == 0xC;
1931   case 0x4E:
1932     // 06_4E  | 3 | 6th Generation Intel(R) Core(TM) Processors based on microarchitecture code name Skylake U
1933     // 06_4E  | 3 | 6th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Skylake U23e
1934     // 06_4E  | 3 | 6th Generation Intel(R) Core(TM) Processors based on microarchitecture code name Skylake Y
1935     return _stepping == 0x3;
1936   case 0x55:
1937     // 06_55H | 4 | Intel(R) Xeon(R) Processor D Family based on microarchitecture code name Skylake D, Bakerville
1938     // 06_55H | 4 | Intel(R) Xeon(R) Scalable Processors based on microarchitecture code name Skylake Server
1939     // 06_55H | 4 | Intel(R) Xeon(R) Processor W Family based on microarchitecture code name Skylake W
1940     // 06_55H | 4 | Intel(R) Core(TM) X-series Processors based on microarchitecture code name Skylake X
1941     // 06_55H | 4 | Intel(R) Xeon(R) Processor E3 v5 Family based on microarchitecture code name Skylake Xeon E3
1942     // 06_55  | 7 | 2nd Generation Intel(R) Xeon(R) Scalable Processors based on microarchitecture code name Cascade Lake (server)
1943     return _stepping == 0x4 || _stepping == 0x7;
1944   case 0x5E:
1945     // 06_5E  | 3 | 6th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Skylake H
1946     // 06_5E  | 3 | 6th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Skylake S
1947     return _stepping == 0x3;
1948   case 0x9E:
1949     // 06_9EH | 9 | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake G
1950     // 06_9EH | 9 | 7th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake H
1951     // 06_9EH | 9 | 7th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake S
1952     // 06_9EH | 9 | Intel(R) Core(TM) X-series Processors based on microarchitecture code name Kaby Lake X
1953     // 06_9EH | 9 | Intel(R) Xeon(R) Processor E3 v6 Family Kaby Lake Xeon E3
1954     // 06_9EH | A | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Coffee Lake H
1955     // 06_9EH | A | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Coffee Lake S
1956     // 06_9EH | A | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Coffee Lake S (6+2) x/KBP
1957     // 06_9EH | A | Intel(R) Xeon(R) Processor E Family based on microarchitecture code name Coffee Lake S (6+2)
1958     // 06_9EH | A | Intel(R) Xeon(R) Processor E Family based on microarchitecture code name Coffee Lake S (4+2)
1959     // 06_9EH | B | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Coffee Lake S (4+2)
1960     // 06_9EH | B | Intel(R) Celeron(R) Processor G Series based on microarchitecture code name Coffee Lake S (4+2)
1961     // 06_9EH | D | 9th Generation Intel(R) Core(TM) Processor Family based on microarchitecturecode name Coffee Lake H (8+2)
1962     // 06_9EH | D | 9th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Coffee Lake S (8+2)
1963     return _stepping == 0x9 || _stepping == 0xA || _stepping == 0xB || _stepping == 0xD;
1964   case 0xA5:
1965     // Not in Intel documentation.
1966     // 06_A5H |    | 10th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Comet Lake S/H
1967     return true;
1968   case 0xA6:
1969     // 06_A6H | 0  | 10th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Comet Lake U62
1970     return _stepping == 0x0;
1971   case 0xAE:
1972     // 06_AEH | A | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake Refresh U (4+2)
1973     return _stepping == 0xA;
1974   default:
1975     // If we are running on another intel machine not recognized in the table, we are okay.
1976     return false;
1977   }
1978 }
1979 
1980 // On Xen, the cpuid instruction returns
1981 //  eax / registers[0]: Version of Xen
1982 //  ebx / registers[1]: chars 'XenV'
1983 //  ecx / registers[2]: chars 'MMXe'
1984 //  edx / registers[3]: chars 'nVMM'
1985 //
1986 // On KVM / VMWare / MS Hyper-V, the cpuid instruction returns
1987 //  ebx / registers[1]: chars 'KVMK' / 'VMwa' / 'Micr'
1988 //  ecx / registers[2]: chars 'VMKV' / 'reVM' / 'osof'
1989 //  edx / registers[3]: chars 'M'    / 'ware' / 't Hv'
1990 //
1991 // more information :
1992 // https://kb.vmware.com/s/article/1009458
1993 //
1994 void VM_Version::check_virtualizations() {
1995   uint32_t registers[4] = {0};
1996   char signature[13] = {0};
1997 
1998   // Xen cpuid leaves can be found 0x100 aligned boundary starting
1999   // from 0x40000000 until 0x40010000.
2000   //   https://lists.linuxfoundation.org/pipermail/virtualization/2012-May/019974.html
2001   for (int leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
2002     detect_virt_stub(leaf, registers);
2003     memcpy(signature, &registers[1], 12);
2004 
2005     if (strncmp("VMwareVMware", signature, 12) == 0) {
2006       Abstract_VM_Version::_detected_virtualization = VMWare;
2007       // check for extended metrics from guestlib
2008       VirtualizationSupport::initialize();
2009     } else if (strncmp("Microsoft Hv", signature, 12) == 0) {
2010       Abstract_VM_Version::_detected_virtualization = HyperV;
2011 #ifdef _WINDOWS
2012       // CPUID leaf 0x40000007 is available to the root partition only.
2013       // See Hypervisor Top Level Functional Specification section 2.4.8 for more details.
2014       //   https://github.com/MicrosoftDocs/Virtualization-Documentation/raw/master/tlfs/Hypervisor%20Top%20Level%20Functional%20Specification%20v6.0b.pdf
2015       detect_virt_stub(0x40000007, registers);
2016       if ((registers[0] != 0x0) ||
2017           (registers[1] != 0x0) ||
2018           (registers[2] != 0x0) ||
2019           (registers[3] != 0x0)) {
2020         Abstract_VM_Version::_detected_virtualization = HyperVRole;
2021       }
2022 #endif
2023     } else if (strncmp("KVMKVMKVM", signature, 9) == 0) {
2024       Abstract_VM_Version::_detected_virtualization = KVM;
2025     } else if (strncmp("XenVMMXenVMM", signature, 12) == 0) {
2026       Abstract_VM_Version::_detected_virtualization = XenHVM;
2027     }
2028   }
2029 }
2030 
2031 // avx3_threshold() sets the threshold at which 64-byte instructions are used
2032 // for implementing the array copy and clear operations.
2033 // The Intel platforms that supports the serialize instruction
2034 // has improved implementation of 64-byte load/stores and so the default
2035 // threshold is set to 0 for these platforms.
2036 int VM_Version::avx3_threshold() {
2037   return (is_intel_family_core() &&
2038           supports_serialize() &&
2039           FLAG_IS_DEFAULT(AVX3Threshold)) ? 0 : AVX3Threshold;
2040 }
2041 
2042 static bool _vm_version_initialized = false;
2043 
2044 void VM_Version::initialize() {
2045   ResourceMark rm;
2046   // Making this stub must be FIRST use of assembler
2047   stub_blob = BufferBlob::create("VM_Version stub", stub_size);
2048   if (stub_blob == NULL) {
2049     vm_exit_during_initialization("Unable to allocate stub for VM_Version");
2050   }
2051   CodeBuffer c(stub_blob);
2052   VM_Version_StubGenerator g(&c);
2053 
2054   get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
2055                                      g.generate_get_cpu_info());
2056   detect_virt_stub = CAST_TO_FN_PTR(detect_virt_stub_t,
2057                                      g.generate_detect_virt());
2058 
2059   get_processor_features();
2060 
2061   LP64_ONLY(Assembler::precompute_instructions();)
2062 
2063   if (VM_Version::supports_hv()) { // Supports hypervisor
2064     check_virtualizations();
2065   }
2066   _vm_version_initialized = true;
2067 }
2068 
2069 typedef enum {
2070    CPU_FAMILY_8086_8088  = 0,
2071    CPU_FAMILY_INTEL_286  = 2,
2072    CPU_FAMILY_INTEL_386  = 3,
2073    CPU_FAMILY_INTEL_486  = 4,
2074    CPU_FAMILY_PENTIUM    = 5,
2075    CPU_FAMILY_PENTIUMPRO = 6,    // Same family several models
2076    CPU_FAMILY_PENTIUM_4  = 0xF
2077 } FamilyFlag;
2078 
2079 typedef enum {
2080   RDTSCP_FLAG  = 0x08000000, // bit 27
2081   INTEL64_FLAG = 0x20000000  // bit 29
2082 } _featureExtendedEdxFlag;
2083 
2084 typedef enum {
2085    FPU_FLAG     = 0x00000001,
2086    VME_FLAG     = 0x00000002,
2087    DE_FLAG      = 0x00000004,
2088    PSE_FLAG     = 0x00000008,
2089    TSC_FLAG     = 0x00000010,
2090    MSR_FLAG     = 0x00000020,
2091    PAE_FLAG     = 0x00000040,
2092    MCE_FLAG     = 0x00000080,
2093    CX8_FLAG     = 0x00000100,
2094    APIC_FLAG    = 0x00000200,
2095    SEP_FLAG     = 0x00000800,
2096    MTRR_FLAG    = 0x00001000,
2097    PGE_FLAG     = 0x00002000,
2098    MCA_FLAG     = 0x00004000,
2099    CMOV_FLAG    = 0x00008000,
2100    PAT_FLAG     = 0x00010000,
2101    PSE36_FLAG   = 0x00020000,
2102    PSNUM_FLAG   = 0x00040000,
2103    CLFLUSH_FLAG = 0x00080000,
2104    DTS_FLAG     = 0x00200000,
2105    ACPI_FLAG    = 0x00400000,
2106    MMX_FLAG     = 0x00800000,
2107    FXSR_FLAG    = 0x01000000,
2108    SSE_FLAG     = 0x02000000,
2109    SSE2_FLAG    = 0x04000000,
2110    SS_FLAG      = 0x08000000,
2111    HTT_FLAG     = 0x10000000,
2112    TM_FLAG      = 0x20000000
2113 } FeatureEdxFlag;
2114 
2115 static BufferBlob* cpuid_brand_string_stub_blob;
2116 static const int   cpuid_brand_string_stub_size = 550;
2117 
2118 extern "C" {
2119   typedef void (*getCPUIDBrandString_stub_t)(void*);
2120 }
2121 
2122 static getCPUIDBrandString_stub_t getCPUIDBrandString_stub = NULL;
2123 
2124 // VM_Version statics
2125 enum {
2126   ExtendedFamilyIdLength_INTEL = 16,
2127   ExtendedFamilyIdLength_AMD   = 24
2128 };
2129 
2130 const size_t VENDOR_LENGTH = 13;
2131 const size_t CPU_EBS_MAX_LENGTH = (3 * 4 * 4 + 1);
2132 static char* _cpu_brand_string = NULL;
2133 static int64_t _max_qualified_cpu_frequency = 0;
2134 
2135 static int _no_of_threads = 0;
2136 static int _no_of_cores = 0;
2137 
2138 const char* const _family_id_intel[ExtendedFamilyIdLength_INTEL] = {
2139   "8086/8088",
2140   "",
2141   "286",
2142   "386",
2143   "486",
2144   "Pentium",
2145   "Pentium Pro",   //or Pentium-M/Woodcrest depeding on model
2146   "",
2147   "",
2148   "",
2149   "",
2150   "",
2151   "",
2152   "",
2153   "",
2154   "Pentium 4"
2155 };
2156 
2157 const char* const _family_id_amd[ExtendedFamilyIdLength_AMD] = {
2158   "",
2159   "",
2160   "",
2161   "",
2162   "5x86",
2163   "K5/K6",
2164   "Athlon/AthlonXP",
2165   "",
2166   "",
2167   "",
2168   "",
2169   "",
2170   "",
2171   "",
2172   "",
2173   "Opteron/Athlon64",
2174   "Opteron QC/Phenom",  // Barcelona et.al.
2175   "",
2176   "",
2177   "",
2178   "",
2179   "",
2180   "",
2181   "Zen"
2182 };
2183 // Partially from Intel 64 and IA-32 Architecture Software Developer's Manual,
2184 // September 2013, Vol 3C Table 35-1
2185 const char* const _model_id_pentium_pro[] = {
2186   "",
2187   "Pentium Pro",
2188   "",
2189   "Pentium II model 3",
2190   "",
2191   "Pentium II model 5/Xeon/Celeron",
2192   "Celeron",
2193   "Pentium III/Pentium III Xeon",
2194   "Pentium III/Pentium III Xeon",
2195   "Pentium M model 9",    // Yonah
2196   "Pentium III, model A",
2197   "Pentium III, model B",
2198   "",
2199   "Pentium M model D",    // Dothan
2200   "",
2201   "Core 2",               // 0xf Woodcrest/Conroe/Merom/Kentsfield/Clovertown
2202   "",
2203   "",
2204   "",
2205   "",
2206   "",
2207   "",
2208   "Celeron",              // 0x16 Celeron 65nm
2209   "Core 2",               // 0x17 Penryn / Harpertown
2210   "",
2211   "",
2212   "Core i7",              // 0x1A CPU_MODEL_NEHALEM_EP
2213   "Atom",                 // 0x1B Z5xx series Silverthorn
2214   "",
2215   "Core 2",               // 0x1D Dunnington (6-core)
2216   "Nehalem",              // 0x1E CPU_MODEL_NEHALEM
2217   "",
2218   "",
2219   "",
2220   "",
2221   "",
2222   "",
2223   "Westmere",             // 0x25 CPU_MODEL_WESTMERE
2224   "",
2225   "",
2226   "",                     // 0x28
2227   "",
2228   "Sandy Bridge",         // 0x2a "2nd Generation Intel Core i7, i5, i3"
2229   "",
2230   "Westmere-EP",          // 0x2c CPU_MODEL_WESTMERE_EP
2231   "Sandy Bridge-EP",      // 0x2d CPU_MODEL_SANDYBRIDGE_EP
2232   "Nehalem-EX",           // 0x2e CPU_MODEL_NEHALEM_EX
2233   "Westmere-EX",          // 0x2f CPU_MODEL_WESTMERE_EX
2234   "",
2235   "",
2236   "",
2237   "",
2238   "",
2239   "",
2240   "",
2241   "",
2242   "",
2243   "",
2244   "Ivy Bridge",           // 0x3a
2245   "",
2246   "Haswell",              // 0x3c "4th Generation Intel Core Processor"
2247   "",                     // 0x3d "Next Generation Intel Core Processor"
2248   "Ivy Bridge-EP",        // 0x3e "Next Generation Intel Xeon Processor E7 Family"
2249   "",                     // 0x3f "Future Generation Intel Xeon Processor"
2250   "",
2251   "",
2252   "",
2253   "",
2254   "",
2255   "Haswell",              // 0x45 "4th Generation Intel Core Processor"
2256   "Haswell",              // 0x46 "4th Generation Intel Core Processor"
2257   NULL
2258 };
2259 
2260 /* Brand ID is for back compability
2261  * Newer CPUs uses the extended brand string */
2262 const char* const _brand_id[] = {
2263   "",
2264   "Celeron processor",
2265   "Pentium III processor",
2266   "Intel Pentium III Xeon processor",
2267   "",
2268   "",
2269   "",
2270   "",
2271   "Intel Pentium 4 processor",
2272   NULL
2273 };
2274 
2275 
2276 const char* const _feature_edx_id[] = {
2277   "On-Chip FPU",
2278   "Virtual Mode Extensions",
2279   "Debugging Extensions",
2280   "Page Size Extensions",
2281   "Time Stamp Counter",
2282   "Model Specific Registers",
2283   "Physical Address Extension",
2284   "Machine Check Exceptions",
2285   "CMPXCHG8B Instruction",
2286   "On-Chip APIC",
2287   "",
2288   "Fast System Call",
2289   "Memory Type Range Registers",
2290   "Page Global Enable",
2291   "Machine Check Architecture",
2292   "Conditional Mov Instruction",
2293   "Page Attribute Table",
2294   "36-bit Page Size Extension",
2295   "Processor Serial Number",
2296   "CLFLUSH Instruction",
2297   "",
2298   "Debug Trace Store feature",
2299   "ACPI registers in MSR space",
2300   "Intel Architecture MMX Technology",
2301   "Fast Float Point Save and Restore",
2302   "Streaming SIMD extensions",
2303   "Streaming SIMD extensions 2",
2304   "Self-Snoop",
2305   "Hyper Threading",
2306   "Thermal Monitor",
2307   "",
2308   "Pending Break Enable"
2309 };
2310 
2311 const char* const _feature_extended_edx_id[] = {
2312   "",
2313   "",
2314   "",
2315   "",
2316   "",
2317   "",
2318   "",
2319   "",
2320   "",
2321   "",
2322   "",
2323   "SYSCALL/SYSRET",
2324   "",
2325   "",
2326   "",
2327   "",
2328   "",
2329   "",
2330   "",
2331   "",
2332   "Execute Disable Bit",
2333   "",
2334   "",
2335   "",
2336   "",
2337   "",
2338   "",
2339   "RDTSCP",
2340   "",
2341   "Intel 64 Architecture",
2342   "",
2343   ""
2344 };
2345 
2346 const char* const _feature_ecx_id[] = {
2347   "Streaming SIMD Extensions 3",
2348   "PCLMULQDQ",
2349   "64-bit DS Area",
2350   "MONITOR/MWAIT instructions",
2351   "CPL Qualified Debug Store",
2352   "Virtual Machine Extensions",
2353   "Safer Mode Extensions",
2354   "Enhanced Intel SpeedStep technology",
2355   "Thermal Monitor 2",
2356   "Supplemental Streaming SIMD Extensions 3",
2357   "L1 Context ID",
2358   "",
2359   "Fused Multiply-Add",
2360   "CMPXCHG16B",
2361   "xTPR Update Control",
2362   "Perfmon and Debug Capability",
2363   "",
2364   "Process-context identifiers",
2365   "Direct Cache Access",
2366   "Streaming SIMD extensions 4.1",
2367   "Streaming SIMD extensions 4.2",
2368   "x2APIC",
2369   "MOVBE",
2370   "Popcount instruction",
2371   "TSC-Deadline",
2372   "AESNI",
2373   "XSAVE",
2374   "OSXSAVE",
2375   "AVX",
2376   "F16C",
2377   "RDRAND",
2378   ""
2379 };
2380 
2381 const char* const _feature_extended_ecx_id[] = {
2382   "LAHF/SAHF instruction support",
2383   "Core multi-processor legacy mode",
2384   "",
2385   "",
2386   "",
2387   "Advanced Bit Manipulations: LZCNT",
2388   "SSE4A: MOVNTSS, MOVNTSD, EXTRQ, INSERTQ",
2389   "Misaligned SSE mode",
2390   "",
2391   "",
2392   "",
2393   "",
2394   "",
2395   "",
2396   "",
2397   "",
2398   "",
2399   "",
2400   "",
2401   "",
2402   "",
2403   "",
2404   "",
2405   "",
2406   "",
2407   "",
2408   "",
2409   "",
2410   "",
2411   "",
2412   "",
2413   ""
2414 };
2415 
2416 void VM_Version::initialize_tsc(void) {
2417   ResourceMark rm;
2418 
2419   cpuid_brand_string_stub_blob = BufferBlob::create("getCPUIDBrandString_stub", cpuid_brand_string_stub_size);
2420   if (cpuid_brand_string_stub_blob == NULL) {
2421     vm_exit_during_initialization("Unable to allocate getCPUIDBrandString_stub");
2422   }
2423   CodeBuffer c(cpuid_brand_string_stub_blob);
2424   VM_Version_StubGenerator g(&c);
2425   getCPUIDBrandString_stub = CAST_TO_FN_PTR(getCPUIDBrandString_stub_t,
2426                                    g.generate_getCPUIDBrandString());
2427 }
2428 
2429 const char* VM_Version::cpu_model_description(void) {
2430   uint32_t cpu_family = extended_cpu_family();
2431   uint32_t cpu_model = extended_cpu_model();
2432   const char* model = NULL;
2433 
2434   if (cpu_family == CPU_FAMILY_PENTIUMPRO) {
2435     for (uint32_t i = 0; i <= cpu_model; i++) {
2436       model = _model_id_pentium_pro[i];
2437       if (model == NULL) {
2438         break;
2439       }
2440     }
2441   }
2442   return model;
2443 }
2444 
2445 const char* VM_Version::cpu_brand_string(void) {
2446   if (_cpu_brand_string == NULL) {
2447     _cpu_brand_string = NEW_C_HEAP_ARRAY_RETURN_NULL(char, CPU_EBS_MAX_LENGTH, mtInternal);
2448     if (NULL == _cpu_brand_string) {
2449       return NULL;
2450     }
2451     int ret_val = cpu_extended_brand_string(_cpu_brand_string, CPU_EBS_MAX_LENGTH);
2452     if (ret_val != OS_OK) {
2453       FREE_C_HEAP_ARRAY(char, _cpu_brand_string);
2454       _cpu_brand_string = NULL;
2455     }
2456   }
2457   return _cpu_brand_string;
2458 }
2459 
2460 const char* VM_Version::cpu_brand(void) {
2461   const char*  brand  = NULL;
2462 
2463   if ((_cpuid_info.std_cpuid1_ebx.value & 0xFF) > 0) {
2464     int brand_num = _cpuid_info.std_cpuid1_ebx.value & 0xFF;
2465     brand = _brand_id[0];
2466     for (int i = 0; brand != NULL && i <= brand_num; i += 1) {
2467       brand = _brand_id[i];
2468     }
2469   }
2470   return brand;
2471 }
2472 
2473 bool VM_Version::cpu_is_em64t(void) {
2474   return ((_cpuid_info.ext_cpuid1_edx.value & INTEL64_FLAG) == INTEL64_FLAG);
2475 }
2476 
2477 bool VM_Version::is_netburst(void) {
2478   return (is_intel() && (extended_cpu_family() == CPU_FAMILY_PENTIUM_4));
2479 }
2480 
2481 bool VM_Version::supports_tscinv_ext(void) {
2482   if (!supports_tscinv_bit()) {
2483     return false;
2484   }
2485 
2486   if (is_intel()) {
2487     return true;
2488   }
2489 
2490   if (is_amd()) {
2491     return !is_amd_Barcelona();
2492   }
2493 
2494   if (is_hygon()) {
2495     return true;
2496   }
2497 
2498   return false;
2499 }
2500 
2501 void VM_Version::resolve_cpu_information_details(void) {
2502 
2503   // in future we want to base this information on proper cpu
2504   // and cache topology enumeration such as:
2505   // Intel 64 Architecture Processor Topology Enumeration
2506   // which supports system cpu and cache topology enumeration
2507   // either using 2xAPICIDs or initial APICIDs
2508 
2509   // currently only rough cpu information estimates
2510   // which will not necessarily reflect the exact configuration of the system
2511 
2512   // this is the number of logical hardware threads
2513   // visible to the operating system
2514   _no_of_threads = os::processor_count();
2515 
2516   // find out number of threads per cpu package
2517   int threads_per_package = threads_per_core() * cores_per_cpu();
2518 
2519   // use amount of threads visible to the process in order to guess number of sockets
2520   _no_of_sockets = _no_of_threads / threads_per_package;
2521 
2522   // process might only see a subset of the total number of threads
2523   // from a single processor package. Virtualization/resource management for example.
2524   // If so then just write a hard 1 as num of pkgs.
2525   if (0 == _no_of_sockets) {
2526     _no_of_sockets = 1;
2527   }
2528 
2529   // estimate the number of cores
2530   _no_of_cores = cores_per_cpu() * _no_of_sockets;
2531 }
2532 
2533 
2534 const char* VM_Version::cpu_family_description(void) {
2535   int cpu_family_id = extended_cpu_family();
2536   if (is_amd()) {
2537     if (cpu_family_id < ExtendedFamilyIdLength_AMD) {
2538       return _family_id_amd[cpu_family_id];
2539     }
2540   }
2541   if (is_intel()) {
2542     if (cpu_family_id == CPU_FAMILY_PENTIUMPRO) {
2543       return cpu_model_description();
2544     }
2545     if (cpu_family_id < ExtendedFamilyIdLength_INTEL) {
2546       return _family_id_intel[cpu_family_id];
2547     }
2548   }
2549   if (is_hygon()) {
2550     return "Dhyana";
2551   }
2552   return "Unknown x86";
2553 }
2554 
2555 int VM_Version::cpu_type_description(char* const buf, size_t buf_len) {
2556   assert(buf != NULL, "buffer is NULL!");
2557   assert(buf_len >= CPU_TYPE_DESC_BUF_SIZE, "buffer len should at least be == CPU_TYPE_DESC_BUF_SIZE!");
2558 
2559   const char* cpu_type = NULL;
2560   const char* x64 = NULL;
2561 
2562   if (is_intel()) {
2563     cpu_type = "Intel";
2564     x64 = cpu_is_em64t() ? " Intel64" : "";
2565   } else if (is_amd()) {
2566     cpu_type = "AMD";
2567     x64 = cpu_is_em64t() ? " AMD64" : "";
2568   } else if (is_hygon()) {
2569     cpu_type = "Hygon";
2570     x64 = cpu_is_em64t() ? " AMD64" : "";
2571   } else {
2572     cpu_type = "Unknown x86";
2573     x64 = cpu_is_em64t() ? " x86_64" : "";
2574   }
2575 
2576   jio_snprintf(buf, buf_len, "%s %s%s SSE SSE2%s%s%s%s%s%s%s%s",
2577     cpu_type,
2578     cpu_family_description(),
2579     supports_ht() ? " (HT)" : "",
2580     supports_sse3() ? " SSE3" : "",
2581     supports_ssse3() ? " SSSE3" : "",
2582     supports_sse4_1() ? " SSE4.1" : "",
2583     supports_sse4_2() ? " SSE4.2" : "",
2584     supports_sse4a() ? " SSE4A" : "",
2585     is_netburst() ? " Netburst" : "",
2586     is_intel_family_core() ? " Core" : "",
2587     x64);
2588 
2589   return OS_OK;
2590 }
2591 
2592 int VM_Version::cpu_extended_brand_string(char* const buf, size_t buf_len) {
2593   assert(buf != NULL, "buffer is NULL!");
2594   assert(buf_len >= CPU_EBS_MAX_LENGTH, "buffer len should at least be == CPU_EBS_MAX_LENGTH!");
2595   assert(getCPUIDBrandString_stub != NULL, "not initialized");
2596 
2597   // invoke newly generated asm code to fetch CPU Brand String
2598   getCPUIDBrandString_stub(&_cpuid_info);
2599 
2600   // fetch results into buffer
2601   *((uint32_t*) &buf[0])  = _cpuid_info.proc_name_0;
2602   *((uint32_t*) &buf[4])  = _cpuid_info.proc_name_1;
2603   *((uint32_t*) &buf[8])  = _cpuid_info.proc_name_2;
2604   *((uint32_t*) &buf[12]) = _cpuid_info.proc_name_3;
2605   *((uint32_t*) &buf[16]) = _cpuid_info.proc_name_4;
2606   *((uint32_t*) &buf[20]) = _cpuid_info.proc_name_5;
2607   *((uint32_t*) &buf[24]) = _cpuid_info.proc_name_6;
2608   *((uint32_t*) &buf[28]) = _cpuid_info.proc_name_7;
2609   *((uint32_t*) &buf[32]) = _cpuid_info.proc_name_8;
2610   *((uint32_t*) &buf[36]) = _cpuid_info.proc_name_9;
2611   *((uint32_t*) &buf[40]) = _cpuid_info.proc_name_10;
2612   *((uint32_t*) &buf[44]) = _cpuid_info.proc_name_11;
2613 
2614   return OS_OK;
2615 }
2616 
2617 size_t VM_Version::cpu_write_support_string(char* const buf, size_t buf_len) {
2618   guarantee(buf != NULL, "buffer is NULL!");
2619   guarantee(buf_len > 0, "buffer len not enough!");
2620 
2621   unsigned int flag = 0;
2622   unsigned int fi = 0;
2623   size_t       written = 0;
2624   const char*  prefix = "";
2625 
2626 #define WRITE_TO_BUF(string)                                                          \
2627   {                                                                                   \
2628     int res = jio_snprintf(&buf[written], buf_len - written, "%s%s", prefix, string); \
2629     if (res < 0) {                                                                    \
2630       return buf_len - 1;                                                             \
2631     }                                                                                 \
2632     written += res;                                                                   \
2633     if (prefix[0] == '\0') {                                                          \
2634       prefix = ", ";                                                                  \
2635     }                                                                                 \
2636   }
2637 
2638   for (flag = 1, fi = 0; flag <= 0x20000000 ; flag <<= 1, fi++) {
2639     if (flag == HTT_FLAG && (((_cpuid_info.std_cpuid1_ebx.value >> 16) & 0xff) <= 1)) {
2640       continue; /* no hyperthreading */
2641     } else if (flag == SEP_FLAG && (cpu_family() == CPU_FAMILY_PENTIUMPRO && ((_cpuid_info.std_cpuid1_eax.value & 0xff) < 0x33))) {
2642       continue; /* no fast system call */
2643     }
2644     if ((_cpuid_info.std_cpuid1_edx.value & flag) && strlen(_feature_edx_id[fi]) > 0) {
2645       WRITE_TO_BUF(_feature_edx_id[fi]);
2646     }
2647   }
2648 
2649   for (flag = 1, fi = 0; flag <= 0x20000000; flag <<= 1, fi++) {
2650     if ((_cpuid_info.std_cpuid1_ecx.value & flag) && strlen(_feature_ecx_id[fi]) > 0) {
2651       WRITE_TO_BUF(_feature_ecx_id[fi]);
2652     }
2653   }
2654 
2655   for (flag = 1, fi = 0; flag <= 0x20000000 ; flag <<= 1, fi++) {
2656     if ((_cpuid_info.ext_cpuid1_ecx.value & flag) && strlen(_feature_extended_ecx_id[fi]) > 0) {
2657       WRITE_TO_BUF(_feature_extended_ecx_id[fi]);
2658     }
2659   }
2660 
2661   for (flag = 1, fi = 0; flag <= 0x20000000; flag <<= 1, fi++) {
2662     if ((_cpuid_info.ext_cpuid1_edx.value & flag) && strlen(_feature_extended_edx_id[fi]) > 0) {
2663       WRITE_TO_BUF(_feature_extended_edx_id[fi]);
2664     }
2665   }
2666 
2667   if (supports_tscinv_bit()) {
2668       WRITE_TO_BUF("Invariant TSC");
2669   }
2670 
2671   return written;
2672 }
2673 
2674 /**
2675  * Write a detailed description of the cpu to a given buffer, including
2676  * feature set.
2677  */
2678 int VM_Version::cpu_detailed_description(char* const buf, size_t buf_len) {
2679   assert(buf != NULL, "buffer is NULL!");
2680   assert(buf_len >= CPU_DETAILED_DESC_BUF_SIZE, "buffer len should at least be == CPU_DETAILED_DESC_BUF_SIZE!");
2681 
2682   static const char* unknown = "<unknown>";
2683   char               vendor_id[VENDOR_LENGTH];
2684   const char*        family = NULL;
2685   const char*        model = NULL;
2686   const char*        brand = NULL;
2687   int                outputLen = 0;
2688 
2689   family = cpu_family_description();
2690   if (family == NULL) {
2691     family = unknown;
2692   }
2693 
2694   model = cpu_model_description();
2695   if (model == NULL) {
2696     model = unknown;
2697   }
2698 
2699   brand = cpu_brand_string();
2700 
2701   if (brand == NULL) {
2702     brand = cpu_brand();
2703     if (brand == NULL) {
2704       brand = unknown;
2705     }
2706   }
2707 
2708   *((uint32_t*) &vendor_id[0]) = _cpuid_info.std_vendor_name_0;
2709   *((uint32_t*) &vendor_id[4]) = _cpuid_info.std_vendor_name_2;
2710   *((uint32_t*) &vendor_id[8]) = _cpuid_info.std_vendor_name_1;
2711   vendor_id[VENDOR_LENGTH-1] = '\0';
2712 
2713   outputLen = jio_snprintf(buf, buf_len, "Brand: %s, Vendor: %s\n"
2714     "Family: %s (0x%x), Model: %s (0x%x), Stepping: 0x%x\n"
2715     "Ext. family: 0x%x, Ext. model: 0x%x, Type: 0x%x, Signature: 0x%8.8x\n"
2716     "Features: ebx: 0x%8.8x, ecx: 0x%8.8x, edx: 0x%8.8x\n"
2717     "Ext. features: eax: 0x%8.8x, ebx: 0x%8.8x, ecx: 0x%8.8x, edx: 0x%8.8x\n"
2718     "Supports: ",
2719     brand,
2720     vendor_id,
2721     family,
2722     extended_cpu_family(),
2723     model,
2724     extended_cpu_model(),
2725     cpu_stepping(),
2726     _cpuid_info.std_cpuid1_eax.bits.ext_family,
2727     _cpuid_info.std_cpuid1_eax.bits.ext_model,
2728     _cpuid_info.std_cpuid1_eax.bits.proc_type,
2729     _cpuid_info.std_cpuid1_eax.value,
2730     _cpuid_info.std_cpuid1_ebx.value,
2731     _cpuid_info.std_cpuid1_ecx.value,
2732     _cpuid_info.std_cpuid1_edx.value,
2733     _cpuid_info.ext_cpuid1_eax,
2734     _cpuid_info.ext_cpuid1_ebx,
2735     _cpuid_info.ext_cpuid1_ecx,
2736     _cpuid_info.ext_cpuid1_edx);
2737 
2738   if (outputLen < 0 || (size_t) outputLen >= buf_len - 1) {
2739     if (buf_len > 0) { buf[buf_len-1] = '\0'; }
2740     return OS_ERR;
2741   }
2742 
2743   cpu_write_support_string(&buf[outputLen], buf_len - outputLen);
2744 
2745   return OS_OK;
2746 }
2747 
2748 
2749 // Fill in Abstract_VM_Version statics
2750 void VM_Version::initialize_cpu_information() {
2751   assert(_vm_version_initialized, "should have initialized VM_Version long ago");
2752   assert(!_initialized, "shouldn't be initialized yet");
2753   resolve_cpu_information_details();
2754 
2755   // initialize cpu_name and cpu_desc
2756   cpu_type_description(_cpu_name, CPU_TYPE_DESC_BUF_SIZE);
2757   cpu_detailed_description(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE);
2758   _initialized = true;
2759 }
2760 
2761 /**
2762  *  For information about extracting the frequency from the cpu brand string, please see:
2763  *
2764  *    Intel Processor Identification and the CPUID Instruction
2765  *    Application Note 485
2766  *    May 2012
2767  *
2768  * The return value is the frequency in Hz.
2769  */
2770 int64_t VM_Version::max_qualified_cpu_freq_from_brand_string(void) {
2771   const char* const brand_string = cpu_brand_string();
2772   if (brand_string == NULL) {
2773     return 0;
2774   }
2775   const int64_t MEGA = 1000000;
2776   int64_t multiplier = 0;
2777   int64_t frequency = 0;
2778   uint8_t idx = 0;
2779   // The brand string buffer is at most 48 bytes.
2780   // -2 is to prevent buffer overrun when looking for y in yHz, as z is +2 from y.
2781   for (; idx < 48-2; ++idx) {
2782     // Format is either "x.xxyHz" or "xxxxyHz", where y=M, G, T and x are digits.
2783     // Search brand string for "yHz" where y is M, G, or T.
2784     if (brand_string[idx+1] == 'H' && brand_string[idx+2] == 'z') {
2785       if (brand_string[idx] == 'M') {
2786         multiplier = MEGA;
2787       } else if (brand_string[idx] == 'G') {
2788         multiplier = MEGA * 1000;
2789       } else if (brand_string[idx] == 'T') {
2790         multiplier = MEGA * MEGA;
2791       }
2792       break;
2793     }
2794   }
2795   if (multiplier > 0) {
2796     // Compute freqency (in Hz) from brand string.
2797     if (brand_string[idx-3] == '.') { // if format is "x.xx"
2798       frequency =  (brand_string[idx-4] - '0') * multiplier;
2799       frequency += (brand_string[idx-2] - '0') * multiplier / 10;
2800       frequency += (brand_string[idx-1] - '0') * multiplier / 100;
2801     } else { // format is "xxxx"
2802       frequency =  (brand_string[idx-4] - '0') * 1000;
2803       frequency += (brand_string[idx-3] - '0') * 100;
2804       frequency += (brand_string[idx-2] - '0') * 10;
2805       frequency += (brand_string[idx-1] - '0');
2806       frequency *= multiplier;
2807     }
2808   }
2809   return frequency;
2810 }
2811 
2812 
2813 int64_t VM_Version::maximum_qualified_cpu_frequency(void) {
2814   if (_max_qualified_cpu_frequency == 0) {
2815     _max_qualified_cpu_frequency = max_qualified_cpu_freq_from_brand_string();
2816   }
2817   return _max_qualified_cpu_frequency;
2818 }
2819