1 /*
2 * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "jvm.h"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "code/codeBlob.hpp"
30 #include "logging/log.hpp"
31 #include "logging/logStream.hpp"
32 #include "memory/resourceArea.hpp"
33 #include "memory/universe.hpp"
34 #include "runtime/globals_extension.hpp"
35 #include "runtime/java.hpp"
36 #include "runtime/os.hpp"
37 #include "runtime/stubCodeGenerator.hpp"
38 #include "runtime/vm_version.hpp"
39 #include "utilities/powerOfTwo.hpp"
40 #include "utilities/virtualizationSupport.hpp"
41
42 #include OS_HEADER_INLINE(os)
43
44 int VM_Version::_cpu;
45 int VM_Version::_model;
46 int VM_Version::_stepping;
47 bool VM_Version::_has_intel_jcc_erratum;
48 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
49
50 #define DECLARE_CPU_FEATURE_NAME(id, name, bit) name,
51 const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)};
52 #undef DECLARE_CPU_FEATURE_FLAG
53
54 // Address of instruction which causes SEGV
55 address VM_Version::_cpuinfo_segv_addr = 0;
56 // Address of instruction after the one which causes SEGV
57 address VM_Version::_cpuinfo_cont_addr = 0;
58
59 static BufferBlob* stub_blob;
60 static const int stub_size = 2000;
61
62 extern "C" {
63 typedef void (*get_cpu_info_stub_t)(void*);
64 typedef void (*detect_virt_stub_t)(uint32_t, uint32_t*);
65 }
66 static get_cpu_info_stub_t get_cpu_info_stub = NULL;
67 static detect_virt_stub_t detect_virt_stub = NULL;
68
69 #ifdef _LP64
70
71 bool VM_Version::supports_clflush() {
72 // clflush should always be available on x86_64
73 // if not we are in real trouble because we rely on it
74 // to flush the code cache.
75 // Unfortunately, Assembler::clflush is currently called as part
76 // of generation of the code cache flush routine. This happens
77 // under Universe::init before the processor features are set
78 // up. Assembler::flush calls this routine to check that clflush
79 // is allowed. So, we give the caller a free pass if Universe init
80 // is still in progress.
81 assert ((!Universe::is_fully_initialized() || (_features & CPU_FLUSH) != 0), "clflush should be available");
82 return true;
83 }
84 #endif
85
86 class VM_Version_StubGenerator: public StubCodeGenerator {
87 public:
88
89 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
90
91 address generate_get_cpu_info() {
92 // Flags to test CPU type.
93 const uint32_t HS_EFL_AC = 0x40000;
94 const uint32_t HS_EFL_ID = 0x200000;
95 // Values for when we don't have a CPUID instruction.
96 const int CPU_FAMILY_SHIFT = 8;
97 const uint32_t CPU_FAMILY_386 = (3 << CPU_FAMILY_SHIFT);
98 const uint32_t CPU_FAMILY_486 = (4 << CPU_FAMILY_SHIFT);
99 bool use_evex = FLAG_IS_DEFAULT(UseAVX) || (UseAVX > 2);
100
101 Label detect_486, cpu486, detect_586, std_cpuid1, std_cpuid4;
102 Label sef_cpuid, ext_cpuid, ext_cpuid1, ext_cpuid5, ext_cpuid7, ext_cpuid8, done, wrapup;
103 Label legacy_setup, save_restore_except, legacy_save_restore, start_simd_check;
104
105 StubCodeMark mark(this, "VM_Version", "get_cpu_info_stub");
106 # define __ _masm->
107
108 address start = __ pc();
109
110 //
111 // void get_cpu_info(VM_Version::CpuidInfo* cpuid_info);
112 //
113 // LP64: rcx and rdx are first and second argument registers on windows
114
115 __ push(rbp);
116 #ifdef _LP64
117 __ mov(rbp, c_rarg0); // cpuid_info address
118 #else
119 __ movptr(rbp, Address(rsp, 8)); // cpuid_info address
120 #endif
121 __ push(rbx);
122 __ push(rsi);
123 __ pushf(); // preserve rbx, and flags
124 __ pop(rax);
125 __ push(rax);
126 __ mov(rcx, rax);
127 //
128 // if we are unable to change the AC flag, we have a 386
129 //
130 __ xorl(rax, HS_EFL_AC);
131 __ push(rax);
132 __ popf();
133 __ pushf();
134 __ pop(rax);
135 __ cmpptr(rax, rcx);
136 __ jccb(Assembler::notEqual, detect_486);
137
138 __ movl(rax, CPU_FAMILY_386);
139 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
140 __ jmp(done);
141
142 //
143 // If we are unable to change the ID flag, we have a 486 which does
144 // not support the "cpuid" instruction.
145 //
146 __ bind(detect_486);
147 __ mov(rax, rcx);
148 __ xorl(rax, HS_EFL_ID);
149 __ push(rax);
150 __ popf();
151 __ pushf();
152 __ pop(rax);
153 __ cmpptr(rcx, rax);
154 __ jccb(Assembler::notEqual, detect_586);
155
156 __ bind(cpu486);
157 __ movl(rax, CPU_FAMILY_486);
158 __ movl(Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())), rax);
159 __ jmp(done);
160
161 //
162 // At this point, we have a chip which supports the "cpuid" instruction
163 //
164 __ bind(detect_586);
165 __ xorl(rax, rax);
166 __ cpuid();
167 __ orl(rax, rax);
168 __ jcc(Assembler::equal, cpu486); // if cpuid doesn't support an input
169 // value of at least 1, we give up and
170 // assume a 486
171 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
172 __ movl(Address(rsi, 0), rax);
173 __ movl(Address(rsi, 4), rbx);
174 __ movl(Address(rsi, 8), rcx);
175 __ movl(Address(rsi,12), rdx);
176
177 __ cmpl(rax, 0xa); // Is cpuid(0xB) supported?
178 __ jccb(Assembler::belowEqual, std_cpuid4);
179
180 //
181 // cpuid(0xB) Processor Topology
182 //
183 __ movl(rax, 0xb);
184 __ xorl(rcx, rcx); // Threads level
185 __ cpuid();
186
187 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB0_offset())));
188 __ movl(Address(rsi, 0), rax);
189 __ movl(Address(rsi, 4), rbx);
190 __ movl(Address(rsi, 8), rcx);
191 __ movl(Address(rsi,12), rdx);
192
193 __ movl(rax, 0xb);
194 __ movl(rcx, 1); // Cores level
195 __ cpuid();
196 __ push(rax);
197 __ andl(rax, 0x1f); // Determine if valid topology level
198 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
199 __ andl(rax, 0xffff);
200 __ pop(rax);
201 __ jccb(Assembler::equal, std_cpuid4);
202
203 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB1_offset())));
204 __ movl(Address(rsi, 0), rax);
205 __ movl(Address(rsi, 4), rbx);
206 __ movl(Address(rsi, 8), rcx);
207 __ movl(Address(rsi,12), rdx);
208
209 __ movl(rax, 0xb);
210 __ movl(rcx, 2); // Packages level
211 __ cpuid();
212 __ push(rax);
213 __ andl(rax, 0x1f); // Determine if valid topology level
214 __ orl(rax, rbx); // eax[4:0] | ebx[0:15] == 0 indicates invalid level
215 __ andl(rax, 0xffff);
216 __ pop(rax);
217 __ jccb(Assembler::equal, std_cpuid4);
218
219 __ lea(rsi, Address(rbp, in_bytes(VM_Version::tpl_cpuidB2_offset())));
220 __ movl(Address(rsi, 0), rax);
221 __ movl(Address(rsi, 4), rbx);
222 __ movl(Address(rsi, 8), rcx);
223 __ movl(Address(rsi,12), rdx);
224
225 //
226 // cpuid(0x4) Deterministic cache params
227 //
228 __ bind(std_cpuid4);
229 __ movl(rax, 4);
230 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x4) supported?
231 __ jccb(Assembler::greater, std_cpuid1);
232
233 __ xorl(rcx, rcx); // L1 cache
234 __ cpuid();
235 __ push(rax);
236 __ andl(rax, 0x1f); // Determine if valid cache parameters used
237 __ orl(rax, rax); // eax[4:0] == 0 indicates invalid cache
238 __ pop(rax);
239 __ jccb(Assembler::equal, std_cpuid1);
240
241 __ lea(rsi, Address(rbp, in_bytes(VM_Version::dcp_cpuid4_offset())));
242 __ movl(Address(rsi, 0), rax);
243 __ movl(Address(rsi, 4), rbx);
244 __ movl(Address(rsi, 8), rcx);
245 __ movl(Address(rsi,12), rdx);
246
247 //
248 // Standard cpuid(0x1)
249 //
250 __ bind(std_cpuid1);
251 __ movl(rax, 1);
252 __ cpuid();
253 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
254 __ movl(Address(rsi, 0), rax);
255 __ movl(Address(rsi, 4), rbx);
256 __ movl(Address(rsi, 8), rcx);
257 __ movl(Address(rsi,12), rdx);
258
259 //
260 // Check if OS has enabled XGETBV instruction to access XCR0
261 // (OSXSAVE feature flag) and CPU supports AVX
262 //
263 __ andl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
264 __ cmpl(rcx, 0x18000000);
265 __ jccb(Assembler::notEqual, sef_cpuid); // jump if AVX is not supported
266
267 //
268 // XCR0, XFEATURE_ENABLED_MASK register
269 //
270 __ xorl(rcx, rcx); // zero for XCR0 register
271 __ xgetbv();
272 __ lea(rsi, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset())));
273 __ movl(Address(rsi, 0), rax);
274 __ movl(Address(rsi, 4), rdx);
275
276 //
277 // cpuid(0x7) Structured Extended Features
278 //
279 __ bind(sef_cpuid);
280 __ movl(rax, 7);
281 __ cmpl(rax, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset()))); // Is cpuid(0x7) supported?
282 __ jccb(Assembler::greater, ext_cpuid);
283
284 __ xorl(rcx, rcx);
285 __ cpuid();
286 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
287 __ movl(Address(rsi, 0), rax);
288 __ movl(Address(rsi, 4), rbx);
289 __ movl(Address(rsi, 8), rcx);
290 __ movl(Address(rsi, 12), rdx);
291
292 //
293 // Extended cpuid(0x80000000)
294 //
295 __ bind(ext_cpuid);
296 __ movl(rax, 0x80000000);
297 __ cpuid();
298 __ cmpl(rax, 0x80000000); // Is cpuid(0x80000001) supported?
299 __ jcc(Assembler::belowEqual, done);
300 __ cmpl(rax, 0x80000004); // Is cpuid(0x80000005) supported?
301 __ jcc(Assembler::belowEqual, ext_cpuid1);
302 __ cmpl(rax, 0x80000006); // Is cpuid(0x80000007) supported?
303 __ jccb(Assembler::belowEqual, ext_cpuid5);
304 __ cmpl(rax, 0x80000007); // Is cpuid(0x80000008) supported?
305 __ jccb(Assembler::belowEqual, ext_cpuid7);
306 __ cmpl(rax, 0x80000008); // Is cpuid(0x80000009 and above) supported?
307 __ jccb(Assembler::belowEqual, ext_cpuid8);
308 __ cmpl(rax, 0x8000001E); // Is cpuid(0x8000001E) supported?
309 __ jccb(Assembler::below, ext_cpuid8);
310 //
311 // Extended cpuid(0x8000001E)
312 //
313 __ movl(rax, 0x8000001E);
314 __ cpuid();
315 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1E_offset())));
316 __ movl(Address(rsi, 0), rax);
317 __ movl(Address(rsi, 4), rbx);
318 __ movl(Address(rsi, 8), rcx);
319 __ movl(Address(rsi,12), rdx);
320
321 //
322 // Extended cpuid(0x80000008)
323 //
324 __ bind(ext_cpuid8);
325 __ movl(rax, 0x80000008);
326 __ cpuid();
327 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid8_offset())));
328 __ movl(Address(rsi, 0), rax);
329 __ movl(Address(rsi, 4), rbx);
330 __ movl(Address(rsi, 8), rcx);
331 __ movl(Address(rsi,12), rdx);
332
333 //
334 // Extended cpuid(0x80000007)
335 //
336 __ bind(ext_cpuid7);
337 __ movl(rax, 0x80000007);
338 __ cpuid();
339 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid7_offset())));
340 __ movl(Address(rsi, 0), rax);
341 __ movl(Address(rsi, 4), rbx);
342 __ movl(Address(rsi, 8), rcx);
343 __ movl(Address(rsi,12), rdx);
344
345 //
346 // Extended cpuid(0x80000005)
347 //
348 __ bind(ext_cpuid5);
349 __ movl(rax, 0x80000005);
350 __ cpuid();
351 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid5_offset())));
352 __ movl(Address(rsi, 0), rax);
353 __ movl(Address(rsi, 4), rbx);
354 __ movl(Address(rsi, 8), rcx);
355 __ movl(Address(rsi,12), rdx);
356
357 //
358 // Extended cpuid(0x80000001)
359 //
360 __ bind(ext_cpuid1);
361 __ movl(rax, 0x80000001);
362 __ cpuid();
363 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ext_cpuid1_offset())));
364 __ movl(Address(rsi, 0), rax);
365 __ movl(Address(rsi, 4), rbx);
366 __ movl(Address(rsi, 8), rcx);
367 __ movl(Address(rsi,12), rdx);
368
369 //
370 // Check if OS has enabled XGETBV instruction to access XCR0
371 // (OSXSAVE feature flag) and CPU supports AVX
372 //
373 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
374 __ movl(rcx, 0x18000000); // cpuid1 bits osxsave | avx
375 __ andl(rcx, Address(rsi, 8)); // cpuid1 bits osxsave | avx
376 __ cmpl(rcx, 0x18000000);
377 __ jccb(Assembler::notEqual, done); // jump if AVX is not supported
378
379 __ movl(rax, 0x6);
380 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
381 __ cmpl(rax, 0x6);
382 __ jccb(Assembler::equal, start_simd_check); // return if AVX is not supported
383
384 // we need to bridge farther than imm8, so we use this island as a thunk
385 __ bind(done);
386 __ jmp(wrapup);
387
388 __ bind(start_simd_check);
389 //
390 // Some OSs have a bug when upper 128/256bits of YMM/ZMM
391 // registers are not restored after a signal processing.
392 // Generate SEGV here (reference through NULL)
393 // and check upper YMM/ZMM bits after it.
394 //
395 intx saved_useavx = UseAVX;
396 intx saved_usesse = UseSSE;
397
398 // If UseAVX is unitialized or is set by the user to include EVEX
399 if (use_evex) {
400 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
401 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
402 __ movl(rax, 0x10000);
403 __ andl(rax, Address(rsi, 4)); // xcr0 bits sse | ymm
404 __ cmpl(rax, 0x10000);
405 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
406 // check _cpuid_info.xem_xcr0_eax.bits.opmask
407 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
408 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
409 __ movl(rax, 0xE0);
410 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
411 __ cmpl(rax, 0xE0);
412 __ jccb(Assembler::notEqual, legacy_setup); // jump if EVEX is not supported
413
414 if (FLAG_IS_DEFAULT(UseAVX)) {
415 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
416 __ movl(rax, Address(rsi, 0));
417 __ cmpl(rax, 0x50654); // If it is Skylake
418 __ jcc(Assembler::equal, legacy_setup);
419 }
420 // EVEX setup: run in lowest evex mode
421 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
422 UseAVX = 3;
423 UseSSE = 2;
424 #ifdef _WINDOWS
425 // xmm5-xmm15 are not preserved by caller on windows
426 // https://msdn.microsoft.com/en-us/library/9z1stfyw.aspx
427 __ subptr(rsp, 64);
428 __ evmovdqul(Address(rsp, 0), xmm7, Assembler::AVX_512bit);
429 #ifdef _LP64
430 __ subptr(rsp, 64);
431 __ evmovdqul(Address(rsp, 0), xmm8, Assembler::AVX_512bit);
432 __ subptr(rsp, 64);
433 __ evmovdqul(Address(rsp, 0), xmm31, Assembler::AVX_512bit);
434 #endif // _LP64
435 #endif // _WINDOWS
436
437 // load value into all 64 bytes of zmm7 register
438 __ movl(rcx, VM_Version::ymm_test_value());
439 __ movdl(xmm0, rcx);
440 __ vpbroadcastd(xmm0, xmm0, Assembler::AVX_512bit);
441 __ evmovdqul(xmm7, xmm0, Assembler::AVX_512bit);
442 #ifdef _LP64
443 __ evmovdqul(xmm8, xmm0, Assembler::AVX_512bit);
444 __ evmovdqul(xmm31, xmm0, Assembler::AVX_512bit);
445 #endif
446 VM_Version::clean_cpuFeatures();
447 __ jmp(save_restore_except);
448 }
449
450 __ bind(legacy_setup);
451 // AVX setup
452 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
453 UseAVX = 1;
454 UseSSE = 2;
455 #ifdef _WINDOWS
456 __ subptr(rsp, 32);
457 __ vmovdqu(Address(rsp, 0), xmm7);
458 #ifdef _LP64
459 __ subptr(rsp, 32);
460 __ vmovdqu(Address(rsp, 0), xmm8);
461 __ subptr(rsp, 32);
462 __ vmovdqu(Address(rsp, 0), xmm15);
463 #endif // _LP64
464 #endif // _WINDOWS
465
466 // load value into all 32 bytes of ymm7 register
467 __ movl(rcx, VM_Version::ymm_test_value());
468
469 __ movdl(xmm0, rcx);
470 __ pshufd(xmm0, xmm0, 0x00);
471 __ vinsertf128_high(xmm0, xmm0);
472 __ vmovdqu(xmm7, xmm0);
473 #ifdef _LP64
474 __ vmovdqu(xmm8, xmm0);
475 __ vmovdqu(xmm15, xmm0);
476 #endif
477 VM_Version::clean_cpuFeatures();
478
479 __ bind(save_restore_except);
480 __ xorl(rsi, rsi);
481 VM_Version::set_cpuinfo_segv_addr(__ pc());
482 // Generate SEGV
483 __ movl(rax, Address(rsi, 0));
484
485 VM_Version::set_cpuinfo_cont_addr(__ pc());
486 // Returns here after signal. Save xmm0 to check it later.
487
488 // If UseAVX is unitialized or is set by the user to include EVEX
489 if (use_evex) {
490 // check _cpuid_info.sef_cpuid7_ebx.bits.avx512f
491 __ lea(rsi, Address(rbp, in_bytes(VM_Version::sef_cpuid7_offset())));
492 __ movl(rax, 0x10000);
493 __ andl(rax, Address(rsi, 4));
494 __ cmpl(rax, 0x10000);
495 __ jcc(Assembler::notEqual, legacy_save_restore);
496 // check _cpuid_info.xem_xcr0_eax.bits.opmask
497 // check _cpuid_info.xem_xcr0_eax.bits.zmm512
498 // check _cpuid_info.xem_xcr0_eax.bits.zmm32
499 __ movl(rax, 0xE0);
500 __ andl(rax, Address(rbp, in_bytes(VM_Version::xem_xcr0_offset()))); // xcr0 bits sse | ymm
501 __ cmpl(rax, 0xE0);
502 __ jcc(Assembler::notEqual, legacy_save_restore);
503
504 if (FLAG_IS_DEFAULT(UseAVX)) {
505 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
506 __ movl(rax, Address(rsi, 0));
507 __ cmpl(rax, 0x50654); // If it is Skylake
508 __ jcc(Assembler::equal, legacy_save_restore);
509 }
510 // EVEX check: run in lowest evex mode
511 VM_Version::set_evex_cpuFeatures(); // Enable temporary to pass asserts
512 UseAVX = 3;
513 UseSSE = 2;
514 __ lea(rsi, Address(rbp, in_bytes(VM_Version::zmm_save_offset())));
515 __ evmovdqul(Address(rsi, 0), xmm0, Assembler::AVX_512bit);
516 __ evmovdqul(Address(rsi, 64), xmm7, Assembler::AVX_512bit);
517 #ifdef _LP64
518 __ evmovdqul(Address(rsi, 128), xmm8, Assembler::AVX_512bit);
519 __ evmovdqul(Address(rsi, 192), xmm31, Assembler::AVX_512bit);
520 #endif
521
522 #ifdef _WINDOWS
523 #ifdef _LP64
524 __ evmovdqul(xmm31, Address(rsp, 0), Assembler::AVX_512bit);
525 __ addptr(rsp, 64);
526 __ evmovdqul(xmm8, Address(rsp, 0), Assembler::AVX_512bit);
527 __ addptr(rsp, 64);
528 #endif // _LP64
529 __ evmovdqul(xmm7, Address(rsp, 0), Assembler::AVX_512bit);
530 __ addptr(rsp, 64);
531 #endif // _WINDOWS
532 generate_vzeroupper(wrapup);
533 VM_Version::clean_cpuFeatures();
534 UseAVX = saved_useavx;
535 UseSSE = saved_usesse;
536 __ jmp(wrapup);
537 }
538
539 __ bind(legacy_save_restore);
540 // AVX check
541 VM_Version::set_avx_cpuFeatures(); // Enable temporary to pass asserts
542 UseAVX = 1;
543 UseSSE = 2;
544 __ lea(rsi, Address(rbp, in_bytes(VM_Version::ymm_save_offset())));
545 __ vmovdqu(Address(rsi, 0), xmm0);
546 __ vmovdqu(Address(rsi, 32), xmm7);
547 #ifdef _LP64
548 __ vmovdqu(Address(rsi, 64), xmm8);
549 __ vmovdqu(Address(rsi, 96), xmm15);
550 #endif
551
552 #ifdef _WINDOWS
553 #ifdef _LP64
554 __ vmovdqu(xmm15, Address(rsp, 0));
555 __ addptr(rsp, 32);
556 __ vmovdqu(xmm8, Address(rsp, 0));
557 __ addptr(rsp, 32);
558 #endif // _LP64
559 __ vmovdqu(xmm7, Address(rsp, 0));
560 __ addptr(rsp, 32);
561 #endif // _WINDOWS
562 generate_vzeroupper(wrapup);
563 VM_Version::clean_cpuFeatures();
564 UseAVX = saved_useavx;
565 UseSSE = saved_usesse;
566
567 __ bind(wrapup);
568 __ popf();
569 __ pop(rsi);
570 __ pop(rbx);
571 __ pop(rbp);
572 __ ret(0);
573
574 # undef __
575
576 return start;
577 };
578 void generate_vzeroupper(Label& L_wrapup) {
579 # define __ _masm->
580 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid0_offset())));
581 __ cmpl(Address(rsi, 4), 0x756e6547); // 'uneG'
582 __ jcc(Assembler::notEqual, L_wrapup);
583 __ movl(rcx, 0x0FFF0FF0);
584 __ lea(rsi, Address(rbp, in_bytes(VM_Version::std_cpuid1_offset())));
585 __ andl(rcx, Address(rsi, 0));
586 __ cmpl(rcx, 0x00050670); // If it is Xeon Phi 3200/5200/7200
587 __ jcc(Assembler::equal, L_wrapup);
588 __ cmpl(rcx, 0x00080650); // If it is Future Xeon Phi
589 __ jcc(Assembler::equal, L_wrapup);
590 // vzeroupper() will use a pre-computed instruction sequence that we
591 // can't compute until after we've determined CPU capabilities. Use
592 // uncached variant here directly to be able to bootstrap correctly
593 __ vzeroupper_uncached();
594 # undef __
595 }
596 address generate_detect_virt() {
597 StubCodeMark mark(this, "VM_Version", "detect_virt_stub");
598 # define __ _masm->
599
600 address start = __ pc();
601
602 // Evacuate callee-saved registers
603 __ push(rbp);
604 __ push(rbx);
605 __ push(rsi); // for Windows
606
607 #ifdef _LP64
608 __ mov(rax, c_rarg0); // CPUID leaf
609 __ mov(rsi, c_rarg1); // register array address (eax, ebx, ecx, edx)
610 #else
611 __ movptr(rax, Address(rsp, 16)); // CPUID leaf
612 __ movptr(rsi, Address(rsp, 20)); // register array address
613 #endif
614
615 __ cpuid();
616
617 // Store result to register array
618 __ movl(Address(rsi, 0), rax);
619 __ movl(Address(rsi, 4), rbx);
620 __ movl(Address(rsi, 8), rcx);
621 __ movl(Address(rsi, 12), rdx);
622
623 // Epilogue
624 __ pop(rsi);
625 __ pop(rbx);
626 __ pop(rbp);
627 __ ret(0);
628
629 # undef __
630
631 return start;
632 };
633 };
634
635 void VM_Version::get_processor_features() {
636
637 _cpu = 4; // 486 by default
638 _model = 0;
639 _stepping = 0;
640 _features = 0;
641 _logical_processors_per_package = 1;
642 // i486 internal cache is both I&D and has a 16-byte line size
643 _L1_data_cache_line_size = 16;
644
645 // Get raw processor info
646
647 get_cpu_info_stub(&_cpuid_info);
648
649 assert_is_initialized();
650 _cpu = extended_cpu_family();
651 _model = extended_cpu_model();
652 _stepping = cpu_stepping();
653
654 if (cpu_family() > 4) { // it supports CPUID
655 _features = feature_flags();
656 // Logical processors are only available on P4s and above,
657 // and only if hyperthreading is available.
658 _logical_processors_per_package = logical_processor_count();
659 _L1_data_cache_line_size = L1_line_size();
660 }
661
662 _supports_cx8 = supports_cmpxchg8();
663 // xchg and xadd instructions
664 _supports_atomic_getset4 = true;
665 _supports_atomic_getadd4 = true;
666 LP64_ONLY(_supports_atomic_getset8 = true);
667 LP64_ONLY(_supports_atomic_getadd8 = true);
668
669 #ifdef _LP64
670 // OS should support SSE for x64 and hardware should support at least SSE2.
671 if (!VM_Version::supports_sse2()) {
672 vm_exit_during_initialization("Unknown x64 processor: SSE2 not supported");
673 }
674 // in 64 bit the use of SSE2 is the minimum
675 if (UseSSE < 2) UseSSE = 2;
676 #endif
677
678 #ifdef AMD64
679 // flush_icache_stub have to be generated first.
680 // That is why Icache line size is hard coded in ICache class,
681 // see icache_x86.hpp. It is also the reason why we can't use
682 // clflush instruction in 32-bit VM since it could be running
683 // on CPU which does not support it.
684 //
685 // The only thing we can do is to verify that flushed
686 // ICache::line_size has correct value.
687 guarantee(_cpuid_info.std_cpuid1_edx.bits.clflush != 0, "clflush is not supported");
688 // clflush_size is size in quadwords (8 bytes).
689 guarantee(_cpuid_info.std_cpuid1_ebx.bits.clflush_size == 8, "such clflush size is not supported");
690 #endif
691
692 #ifdef _LP64
693 // assigning this field effectively enables Unsafe.writebackMemory()
694 // by initing UnsafeConstant.DATA_CACHE_LINE_FLUSH_SIZE to non-zero
695 // that is only implemented on x86_64 and only if the OS plays ball
696 if (os::supports_map_sync()) {
697 // publish data cache line flush size to generic field, otherwise
698 // let if default to zero thereby disabling writeback
699 _data_cache_line_flush_size = _cpuid_info.std_cpuid1_ebx.bits.clflush_size * 8;
700 }
701 #endif
702 // If the OS doesn't support SSE, we can't use this feature even if the HW does
703 if (!os::supports_sse())
704 _features &= ~(CPU_SSE|CPU_SSE2|CPU_SSE3|CPU_SSSE3|CPU_SSE4A|CPU_SSE4_1|CPU_SSE4_2);
705
706 if (UseSSE < 4) {
707 _features &= ~CPU_SSE4_1;
708 _features &= ~CPU_SSE4_2;
709 }
710
711 if (UseSSE < 3) {
712 _features &= ~CPU_SSE3;
713 _features &= ~CPU_SSSE3;
714 _features &= ~CPU_SSE4A;
715 }
716
717 if (UseSSE < 2)
718 _features &= ~CPU_SSE2;
719
720 if (UseSSE < 1)
721 _features &= ~CPU_SSE;
722
723 //since AVX instructions is slower than SSE in some ZX cpus, force USEAVX=0.
724 if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7))) {
725 UseAVX = 0;
726 }
727
728 // first try initial setting and detect what we can support
729 int use_avx_limit = 0;
730 if (UseAVX > 0) {
731 if (UseAVX > 2 && supports_evex()) {
732 use_avx_limit = 3;
733 } else if (UseAVX > 1 && supports_avx2()) {
734 use_avx_limit = 2;
735 } else if (UseAVX > 0 && supports_avx()) {
736 use_avx_limit = 1;
737 } else {
738 use_avx_limit = 0;
739 }
740 }
741 if (FLAG_IS_DEFAULT(UseAVX)) {
742 // Don't use AVX-512 on older Skylakes unless explicitly requested.
743 if (use_avx_limit > 2 && is_intel_skylake() && _stepping < 5) {
744 FLAG_SET_DEFAULT(UseAVX, 2);
745 } else {
746 FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
747 }
748 }
749 if (UseAVX > use_avx_limit) {
750 warning("UseAVX=%d is not supported on this CPU, setting it to UseAVX=%d", (int) UseAVX, use_avx_limit);
751 FLAG_SET_DEFAULT(UseAVX, use_avx_limit);
752 } else if (UseAVX < 0) {
753 warning("UseAVX=%d is not valid, setting it to UseAVX=0", (int) UseAVX);
754 FLAG_SET_DEFAULT(UseAVX, 0);
755 }
756
757 if (UseAVX < 3) {
758 _features &= ~CPU_AVX512F;
759 _features &= ~CPU_AVX512DQ;
760 _features &= ~CPU_AVX512CD;
761 _features &= ~CPU_AVX512BW;
762 _features &= ~CPU_AVX512VL;
763 _features &= ~CPU_AVX512_VPOPCNTDQ;
764 _features &= ~CPU_AVX512_VPCLMULQDQ;
765 _features &= ~CPU_AVX512_VAES;
766 _features &= ~CPU_AVX512_VNNI;
767 _features &= ~CPU_AVX512_VBMI;
768 _features &= ~CPU_AVX512_VBMI2;
769 }
770
771 if (UseAVX < 2)
772 _features &= ~CPU_AVX2;
773
774 if (UseAVX < 1) {
775 _features &= ~CPU_AVX;
776 _features &= ~CPU_VZEROUPPER;
777 }
778
779 if (logical_processors_per_package() == 1) {
780 // HT processor could be installed on a system which doesn't support HT.
781 _features &= ~CPU_HT;
782 }
783
784 if (is_intel()) { // Intel cpus specific settings
785 if (is_knights_family()) {
786 _features &= ~CPU_VZEROUPPER;
787 _features &= ~CPU_AVX512BW;
788 _features &= ~CPU_AVX512VL;
789 _features &= ~CPU_AVX512DQ;
790 _features &= ~CPU_AVX512_VNNI;
791 _features &= ~CPU_AVX512_VAES;
792 _features &= ~CPU_AVX512_VPOPCNTDQ;
793 _features &= ~CPU_AVX512_VPCLMULQDQ;
794 _features &= ~CPU_AVX512_VBMI;
795 _features &= ~CPU_AVX512_VBMI2;
796 _features &= ~CPU_CLWB;
797 _features &= ~CPU_FLUSHOPT;
798 }
799 }
800
801 if (FLAG_IS_DEFAULT(IntelJccErratumMitigation)) {
802 _has_intel_jcc_erratum = compute_has_intel_jcc_erratum();
803 } else {
804 _has_intel_jcc_erratum = IntelJccErratumMitigation;
805 }
806
807 char buf[512];
808 int res = jio_snprintf(
809 buf, sizeof(buf),
810 "(%u cores per cpu, %u threads per core) family %d model %d stepping %d microcode 0x%x",
811 cores_per_cpu(), threads_per_core(),
812 cpu_family(), _model, _stepping, os::cpu_microcode_revision());
813 assert(res > 0, "not enough temporary space allocated");
814 insert_features_names(buf + res, sizeof(buf) - res, _features_names);
815
816 _features_string = os::strdup(buf);
817
818 // UseSSE is set to the smaller of what hardware supports and what
819 // the command line requires. I.e., you cannot set UseSSE to 2 on
820 // older Pentiums which do not support it.
821 int use_sse_limit = 0;
822 if (UseSSE > 0) {
823 if (UseSSE > 3 && supports_sse4_1()) {
824 use_sse_limit = 4;
825 } else if (UseSSE > 2 && supports_sse3()) {
826 use_sse_limit = 3;
827 } else if (UseSSE > 1 && supports_sse2()) {
828 use_sse_limit = 2;
829 } else if (UseSSE > 0 && supports_sse()) {
830 use_sse_limit = 1;
831 } else {
832 use_sse_limit = 0;
833 }
834 }
835 if (FLAG_IS_DEFAULT(UseSSE)) {
836 FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
837 } else if (UseSSE > use_sse_limit) {
838 warning("UseSSE=%d is not supported on this CPU, setting it to UseSSE=%d", (int) UseSSE, use_sse_limit);
839 FLAG_SET_DEFAULT(UseSSE, use_sse_limit);
840 } else if (UseSSE < 0) {
841 warning("UseSSE=%d is not valid, setting it to UseSSE=0", (int) UseSSE);
842 FLAG_SET_DEFAULT(UseSSE, 0);
843 }
844
845 // Use AES instructions if available.
846 if (supports_aes()) {
847 if (FLAG_IS_DEFAULT(UseAES)) {
848 FLAG_SET_DEFAULT(UseAES, true);
849 }
850 if (!UseAES) {
851 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
852 warning("AES intrinsics require UseAES flag to be enabled. Intrinsics will be disabled.");
853 }
854 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
855 } else {
856 if (UseSSE > 2) {
857 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
858 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
859 }
860 } else {
861 // The AES intrinsic stubs require AES instruction support (of course)
862 // but also require sse3 mode or higher for instructions it use.
863 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
864 warning("X86 AES intrinsics require SSE3 instructions or higher. Intrinsics will be disabled.");
865 }
866 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
867 }
868
869 // --AES-CTR begins--
870 if (!UseAESIntrinsics) {
871 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
872 warning("AES-CTR intrinsics require UseAESIntrinsics flag to be enabled. Intrinsics will be disabled.");
873 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
874 }
875 } else {
876 if (supports_sse4_1()) {
877 if (FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
878 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, true);
879 }
880 } else {
881 // The AES-CTR intrinsic stubs require AES instruction support (of course)
882 // but also require sse4.1 mode or higher for instructions it use.
883 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
884 warning("X86 AES-CTR intrinsics require SSE4.1 instructions or higher. Intrinsics will be disabled.");
885 }
886 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
887 }
888 }
889 // --AES-CTR ends--
890 }
891 } else if (UseAES || UseAESIntrinsics || UseAESCTRIntrinsics) {
892 if (UseAES && !FLAG_IS_DEFAULT(UseAES)) {
893 warning("AES instructions are not available on this CPU");
894 FLAG_SET_DEFAULT(UseAES, false);
895 }
896 if (UseAESIntrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
897 warning("AES intrinsics are not available on this CPU");
898 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
899 }
900 if (UseAESCTRIntrinsics && !FLAG_IS_DEFAULT(UseAESCTRIntrinsics)) {
901 warning("AES-CTR intrinsics are not available on this CPU");
902 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
903 }
904 }
905
906 // Use CLMUL instructions if available.
907 if (supports_clmul()) {
908 if (FLAG_IS_DEFAULT(UseCLMUL)) {
909 UseCLMUL = true;
910 }
911 } else if (UseCLMUL) {
912 if (!FLAG_IS_DEFAULT(UseCLMUL))
913 warning("CLMUL instructions not available on this CPU (AVX may also be required)");
914 FLAG_SET_DEFAULT(UseCLMUL, false);
915 }
916
917 if (UseCLMUL && (UseSSE > 2)) {
918 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
919 UseCRC32Intrinsics = true;
920 }
921 } else if (UseCRC32Intrinsics) {
922 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
923 warning("CRC32 Intrinsics requires CLMUL instructions (not available on this CPU)");
924 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
925 }
926
927 #ifdef _LP64
928 if (supports_avx2()) {
929 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
930 UseAdler32Intrinsics = true;
931 }
932 } else if (UseAdler32Intrinsics) {
933 if (!FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
934 warning("Adler32 Intrinsics requires avx2 instructions (not available on this CPU)");
935 }
936 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
937 }
938 #else
939 if (UseAdler32Intrinsics) {
940 warning("Adler32Intrinsics not available on this CPU.");
941 FLAG_SET_DEFAULT(UseAdler32Intrinsics, false);
942 }
943 #endif
944
945 if (supports_sse4_2() && supports_clmul()) {
946 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
947 UseCRC32CIntrinsics = true;
948 }
949 } else if (UseCRC32CIntrinsics) {
950 if (!FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
951 warning("CRC32C intrinsics are not available on this CPU");
952 }
953 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
954 }
955
956 // GHASH/GCM intrinsics
957 if (UseCLMUL && (UseSSE > 2)) {
958 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
959 UseGHASHIntrinsics = true;
960 }
961 } else if (UseGHASHIntrinsics) {
962 if (!FLAG_IS_DEFAULT(UseGHASHIntrinsics))
963 warning("GHASH intrinsic requires CLMUL and SSE2 instructions on this CPU");
964 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
965 }
966
967 // Base64 Intrinsics (Check the condition for which the intrinsic will be active)
968 if ((UseAVX > 2) && supports_avx512vl() && supports_avx512bw()) {
969 if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
970 UseBASE64Intrinsics = true;
971 }
972 } else if (UseBASE64Intrinsics) {
973 if (!FLAG_IS_DEFAULT(UseBASE64Intrinsics))
974 warning("Base64 intrinsic requires EVEX instructions on this CPU");
975 FLAG_SET_DEFAULT(UseBASE64Intrinsics, false);
976 }
977
978 if (supports_fma() && UseSSE >= 2) { // Check UseSSE since FMA code uses SSE instructions
979 if (FLAG_IS_DEFAULT(UseFMA)) {
980 UseFMA = true;
981 }
982 } else if (UseFMA) {
983 warning("FMA instructions are not available on this CPU");
984 FLAG_SET_DEFAULT(UseFMA, false);
985 }
986
987 if (FLAG_IS_DEFAULT(UseMD5Intrinsics)) {
988 UseMD5Intrinsics = true;
989 }
990
991 if (supports_sha() LP64_ONLY(|| supports_avx2() && supports_bmi2())) {
992 if (FLAG_IS_DEFAULT(UseSHA)) {
993 UseSHA = true;
994 }
995 } else if (UseSHA) {
996 warning("SHA instructions are not available on this CPU");
997 FLAG_SET_DEFAULT(UseSHA, false);
998 }
999
1000 if (supports_sha() && supports_sse4_1() && UseSHA) {
1001 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
1002 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
1003 }
1004 } else if (UseSHA1Intrinsics) {
1005 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
1006 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
1007 }
1008
1009 if (supports_sse4_1() && UseSHA) {
1010 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
1011 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
1012 }
1013 } else if (UseSHA256Intrinsics) {
1014 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
1015 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
1016 }
1017
1018 #ifdef _LP64
1019 // These are only supported on 64-bit
1020 if (UseSHA && supports_avx2() && supports_bmi2()) {
1021 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
1022 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
1023 }
1024 } else
1025 #endif
1026 if (UseSHA512Intrinsics) {
1027 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
1028 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
1029 }
1030
1031 if (UseSHA3Intrinsics) {
1032 warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
1033 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
1034 }
1035
1036 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
1037 FLAG_SET_DEFAULT(UseSHA, false);
1038 }
1039
1040 if (!supports_rtm() && UseRTMLocking) {
1041 vm_exit_during_initialization("RTM instructions are not available on this CPU");
1042 }
1043
1044 #if INCLUDE_RTM_OPT
1045 if (UseRTMLocking) {
1046 if (!CompilerConfig::is_c2_enabled()) {
1047 // Only C2 does RTM locking optimization.
1048 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
1049 }
1050 if (is_intel_family_core()) {
1051 if ((_model == CPU_MODEL_HASWELL_E3) ||
1052 (_model == CPU_MODEL_HASWELL_E7 && _stepping < 3) ||
1053 (_model == CPU_MODEL_BROADWELL && _stepping < 4)) {
1054 // currently a collision between SKL and HSW_E3
1055 if (!UnlockExperimentalVMOptions && UseAVX < 3) {
1056 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this "
1057 "platform. It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
1058 } else {
1059 warning("UseRTMLocking is only available as experimental option on this platform.");
1060 }
1061 }
1062 }
1063 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
1064 // RTM locking should be used only for applications with
1065 // high lock contention. For now we do not use it by default.
1066 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
1067 }
1068 } else { // !UseRTMLocking
1069 if (UseRTMForStackLocks) {
1070 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
1071 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
1072 }
1073 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
1074 }
1075 if (UseRTMDeopt) {
1076 FLAG_SET_DEFAULT(UseRTMDeopt, false);
1077 }
1078 if (PrintPreciseRTMLockingStatistics) {
1079 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
1080 }
1081 }
1082 #else
1083 if (UseRTMLocking) {
1084 // Only C2 does RTM locking optimization.
1085 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
1086 }
1087 #endif
1088
1089 #ifdef COMPILER2
1090 if (UseFPUForSpilling) {
1091 if (UseSSE < 2) {
1092 // Only supported with SSE2+
1093 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
1094 }
1095 }
1096 #endif
1097
1098 #if COMPILER2_OR_JVMCI
1099 int max_vector_size = 0;
1100 if (UseSSE < 2) {
1101 // Vectors (in XMM) are only supported with SSE2+
1102 // SSE is always 2 on x64.
1103 max_vector_size = 0;
1104 } else if (UseAVX == 0 || !os_supports_avx_vectors()) {
1105 // 16 byte vectors (in XMM) are supported with SSE2+
1106 max_vector_size = 16;
1107 } else if (UseAVX == 1 || UseAVX == 2) {
1108 // 32 bytes vectors (in YMM) are only supported with AVX+
1109 max_vector_size = 32;
1110 } else if (UseAVX > 2) {
1111 // 64 bytes vectors (in ZMM) are only supported with AVX 3
1112 max_vector_size = 64;
1113 }
1114
1115 #ifdef _LP64
1116 int min_vector_size = 4; // We require MaxVectorSize to be at least 4 on 64bit
1117 #else
1118 int min_vector_size = 0;
1119 #endif
1120
1121 if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
1122 if (MaxVectorSize < min_vector_size) {
1123 warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
1124 FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
1125 }
1126 if (MaxVectorSize > max_vector_size) {
1127 warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
1128 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1129 }
1130 if (!is_power_of_2(MaxVectorSize)) {
1131 warning("MaxVectorSize must be a power of 2, setting to default: %i", max_vector_size);
1132 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1133 }
1134 } else {
1135 // If default, use highest supported configuration
1136 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1137 }
1138
1139 #if defined(COMPILER2) && defined(ASSERT)
1140 if (MaxVectorSize > 0) {
1141 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
1142 tty->print_cr("State of YMM registers after signal handle:");
1143 int nreg = 2 LP64_ONLY(+2);
1144 const char* ymm_name[4] = {"0", "7", "8", "15"};
1145 for (int i = 0; i < nreg; i++) {
1146 tty->print("YMM%s:", ymm_name[i]);
1147 for (int j = 7; j >=0; j--) {
1148 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
1149 }
1150 tty->cr();
1151 }
1152 }
1153 }
1154 #endif // COMPILER2 && ASSERT
1155
1156 #ifdef _LP64
1157 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1158 UseMultiplyToLenIntrinsic = true;
1159 }
1160 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1161 UseSquareToLenIntrinsic = true;
1162 }
1163 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1164 UseMulAddIntrinsic = true;
1165 }
1166 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1167 UseMontgomeryMultiplyIntrinsic = true;
1168 }
1169 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1170 UseMontgomerySquareIntrinsic = true;
1171 }
1172 #else
1173 if (UseMultiplyToLenIntrinsic) {
1174 if (!FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1175 warning("multiplyToLen intrinsic is not available in 32-bit VM");
1176 }
1177 FLAG_SET_DEFAULT(UseMultiplyToLenIntrinsic, false);
1178 }
1179 if (UseMontgomeryMultiplyIntrinsic) {
1180 if (!FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1181 warning("montgomeryMultiply intrinsic is not available in 32-bit VM");
1182 }
1183 FLAG_SET_DEFAULT(UseMontgomeryMultiplyIntrinsic, false);
1184 }
1185 if (UseMontgomerySquareIntrinsic) {
1186 if (!FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1187 warning("montgomerySquare intrinsic is not available in 32-bit VM");
1188 }
1189 FLAG_SET_DEFAULT(UseMontgomerySquareIntrinsic, false);
1190 }
1191 if (UseSquareToLenIntrinsic) {
1192 if (!FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1193 warning("squareToLen intrinsic is not available in 32-bit VM");
1194 }
1195 FLAG_SET_DEFAULT(UseSquareToLenIntrinsic, false);
1196 }
1197 if (UseMulAddIntrinsic) {
1198 if (!FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1199 warning("mulAdd intrinsic is not available in 32-bit VM");
1200 }
1201 FLAG_SET_DEFAULT(UseMulAddIntrinsic, false);
1202 }
1203 #endif // _LP64
1204 #endif // COMPILER2_OR_JVMCI
1205
1206 // On new cpus instructions which update whole XMM register should be used
1207 // to prevent partial register stall due to dependencies on high half.
1208 //
1209 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
1210 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1211 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
1212 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
1213
1214
1215 if (is_zx()) { // ZX cpus specific settings
1216 if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1217 UseStoreImmI16 = false; // don't use it on ZX cpus
1218 }
1219 if ((cpu_family() == 6) || (cpu_family() == 7)) {
1220 if (FLAG_IS_DEFAULT(UseAddressNop)) {
1221 // Use it on all ZX cpus
1222 UseAddressNop = true;
1223 }
1224 }
1225 if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1226 UseXmmLoadAndClearUpper = true; // use movsd on all ZX cpus
1227 }
1228 if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1229 if (supports_sse3()) {
1230 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new ZX cpus
1231 } else {
1232 UseXmmRegToRegMoveAll = false;
1233 }
1234 }
1235 if (((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse3()) { // new ZX cpus
1236 #ifdef COMPILER2
1237 if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1238 // For new ZX cpus do the next optimization:
1239 // don't align the beginning of a loop if there are enough instructions
1240 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1241 // in current fetch line (OptoLoopAlignment) or the padding
1242 // is big (> MaxLoopPad).
1243 // Set MaxLoopPad to 11 for new ZX cpus to reduce number of
1244 // generated NOP instructions. 11 is the largest size of one
1245 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1246 MaxLoopPad = 11;
1247 }
1248 #endif // COMPILER2
1249 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1250 UseXMMForArrayCopy = true; // use SSE2 movq on new ZX cpus
1251 }
1252 if (supports_sse4_2()) { // new ZX cpus
1253 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1254 UseUnalignedLoadStores = true; // use movdqu on newest ZX cpus
1255 }
1256 }
1257 if (supports_sse4_2()) {
1258 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1259 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1260 }
1261 } else {
1262 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1263 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1264 }
1265 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1266 }
1267 }
1268
1269 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1270 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1271 }
1272 }
1273
1274 if (is_amd_family()) { // AMD cpus specific settings
1275 if (supports_sse2() && FLAG_IS_DEFAULT(UseAddressNop)) {
1276 // Use it on new AMD cpus starting from Opteron.
1277 UseAddressNop = true;
1278 }
1279 if (supports_sse2() && FLAG_IS_DEFAULT(UseNewLongLShift)) {
1280 // Use it on new AMD cpus starting from Opteron.
1281 UseNewLongLShift = true;
1282 }
1283 if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1284 if (supports_sse4a()) {
1285 UseXmmLoadAndClearUpper = true; // use movsd only on '10h' Opteron
1286 } else {
1287 UseXmmLoadAndClearUpper = false;
1288 }
1289 }
1290 if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1291 if (supports_sse4a()) {
1292 UseXmmRegToRegMoveAll = true; // use movaps, movapd only on '10h'
1293 } else {
1294 UseXmmRegToRegMoveAll = false;
1295 }
1296 }
1297 if (FLAG_IS_DEFAULT(UseXmmI2F)) {
1298 if (supports_sse4a()) {
1299 UseXmmI2F = true;
1300 } else {
1301 UseXmmI2F = false;
1302 }
1303 }
1304 if (FLAG_IS_DEFAULT(UseXmmI2D)) {
1305 if (supports_sse4a()) {
1306 UseXmmI2D = true;
1307 } else {
1308 UseXmmI2D = false;
1309 }
1310 }
1311 if (supports_sse4_2()) {
1312 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1313 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1314 }
1315 } else {
1316 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1317 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1318 }
1319 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1320 }
1321
1322 // some defaults for AMD family 15h
1323 if (cpu_family() == 0x15) {
1324 // On family 15h processors default is no sw prefetch
1325 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1326 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1327 }
1328 // Also, if some other prefetch style is specified, default instruction type is PREFETCHW
1329 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1330 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1331 }
1332 // On family 15h processors use XMM and UnalignedLoadStores for Array Copy
1333 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1334 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1335 }
1336 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1337 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1338 }
1339 }
1340
1341 #ifdef COMPILER2
1342 if (cpu_family() < 0x17 && MaxVectorSize > 16) {
1343 // Limit vectors size to 16 bytes on AMD cpus < 17h.
1344 FLAG_SET_DEFAULT(MaxVectorSize, 16);
1345 }
1346 #endif // COMPILER2
1347
1348 // Some defaults for AMD family >= 17h && Hygon family 18h
1349 if (cpu_family() >= 0x17) {
1350 // On family >=17h processors use XMM and UnalignedLoadStores
1351 // for Array Copy
1352 if (supports_sse2() && FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1353 FLAG_SET_DEFAULT(UseXMMForArrayCopy, true);
1354 }
1355 if (supports_sse2() && FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1356 FLAG_SET_DEFAULT(UseUnalignedLoadStores, true);
1357 }
1358 #ifdef COMPILER2
1359 if (supports_sse4_2() && FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1360 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1361 }
1362 #endif
1363 }
1364 }
1365
1366 if (is_intel()) { // Intel cpus specific settings
1367 if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1368 UseStoreImmI16 = false; // don't use it on Intel cpus
1369 }
1370 if (cpu_family() == 6 || cpu_family() == 15) {
1371 if (FLAG_IS_DEFAULT(UseAddressNop)) {
1372 // Use it on all Intel cpus starting from PentiumPro
1373 UseAddressNop = true;
1374 }
1375 }
1376 if (FLAG_IS_DEFAULT(UseXmmLoadAndClearUpper)) {
1377 UseXmmLoadAndClearUpper = true; // use movsd on all Intel cpus
1378 }
1379 if (FLAG_IS_DEFAULT(UseXmmRegToRegMoveAll)) {
1380 if (supports_sse3()) {
1381 UseXmmRegToRegMoveAll = true; // use movaps, movapd on new Intel cpus
1382 } else {
1383 UseXmmRegToRegMoveAll = false;
1384 }
1385 }
1386 if (cpu_family() == 6 && supports_sse3()) { // New Intel cpus
1387 #ifdef COMPILER2
1388 if (FLAG_IS_DEFAULT(MaxLoopPad)) {
1389 // For new Intel cpus do the next optimization:
1390 // don't align the beginning of a loop if there are enough instructions
1391 // left (NumberOfLoopInstrToAlign defined in c2_globals.hpp)
1392 // in current fetch line (OptoLoopAlignment) or the padding
1393 // is big (> MaxLoopPad).
1394 // Set MaxLoopPad to 11 for new Intel cpus to reduce number of
1395 // generated NOP instructions. 11 is the largest size of one
1396 // address NOP instruction '0F 1F' (see Assembler::nop(i)).
1397 MaxLoopPad = 11;
1398 }
1399 #endif // COMPILER2
1400
1401 if (FLAG_IS_DEFAULT(UseXMMForArrayCopy)) {
1402 UseXMMForArrayCopy = true; // use SSE2 movq on new Intel cpus
1403 }
1404 if ((supports_sse4_2() && supports_ht()) || supports_avx()) { // Newest Intel cpus
1405 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1406 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1407 }
1408 }
1409 if (supports_sse4_2()) {
1410 if (FLAG_IS_DEFAULT(UseSSE42Intrinsics)) {
1411 FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
1412 }
1413 } else {
1414 if (UseSSE42Intrinsics && !FLAG_IS_DEFAULT(UseAESIntrinsics)) {
1415 warning("SSE4.2 intrinsics require SSE4.2 instructions or higher. Intrinsics will be disabled.");
1416 }
1417 FLAG_SET_DEFAULT(UseSSE42Intrinsics, false);
1418 }
1419 }
1420 if (is_atom_family() || is_knights_family()) {
1421 #ifdef COMPILER2
1422 if (FLAG_IS_DEFAULT(OptoScheduling)) {
1423 OptoScheduling = true;
1424 }
1425 #endif
1426 if (supports_sse4_2()) { // Silvermont
1427 if (FLAG_IS_DEFAULT(UseUnalignedLoadStores)) {
1428 UseUnalignedLoadStores = true; // use movdqu on newest Intel cpus
1429 }
1430 }
1431 if (FLAG_IS_DEFAULT(UseIncDec)) {
1432 FLAG_SET_DEFAULT(UseIncDec, false);
1433 }
1434 }
1435 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr) && supports_3dnow_prefetch()) {
1436 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1437 }
1438 #ifdef COMPILER2
1439 if (UseAVX > 2) {
1440 if (FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize) ||
1441 (!FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize) &&
1442 ArrayOperationPartialInlineSize != 0 &&
1443 ArrayOperationPartialInlineSize != 16 &&
1444 ArrayOperationPartialInlineSize != 32 &&
1445 ArrayOperationPartialInlineSize != 64)) {
1446 int inline_size = 0;
1447 if (MaxVectorSize >= 64 && AVX3Threshold == 0) {
1448 inline_size = 64;
1449 } else if (MaxVectorSize >= 32) {
1450 inline_size = 32;
1451 } else if (MaxVectorSize >= 16) {
1452 inline_size = 16;
1453 }
1454 if(!FLAG_IS_DEFAULT(ArrayOperationPartialInlineSize)) {
1455 warning("Setting ArrayOperationPartialInlineSize as %d", inline_size);
1456 }
1457 ArrayOperationPartialInlineSize = inline_size;
1458 }
1459
1460 if (ArrayOperationPartialInlineSize > MaxVectorSize) {
1461 ArrayOperationPartialInlineSize = MaxVectorSize >= 16 ? MaxVectorSize : 0;
1462 if (ArrayOperationPartialInlineSize) {
1463 warning("Setting ArrayOperationPartialInlineSize as MaxVectorSize" INTX_FORMAT ")", MaxVectorSize);
1464 } else {
1465 warning("Setting ArrayOperationPartialInlineSize as " INTX_FORMAT, ArrayOperationPartialInlineSize);
1466 }
1467 }
1468 }
1469 #endif
1470 }
1471
1472 #ifdef _LP64
1473 if (UseSSE42Intrinsics) {
1474 if (FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1475 UseVectorizedMismatchIntrinsic = true;
1476 }
1477 } else if (UseVectorizedMismatchIntrinsic) {
1478 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic))
1479 warning("vectorizedMismatch intrinsics are not available on this CPU");
1480 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1481 }
1482 #else
1483 if (UseVectorizedMismatchIntrinsic) {
1484 if (!FLAG_IS_DEFAULT(UseVectorizedMismatchIntrinsic)) {
1485 warning("vectorizedMismatch intrinsic is not available in 32-bit VM");
1486 }
1487 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
1488 }
1489 #endif // _LP64
1490
1491 // Use count leading zeros count instruction if available.
1492 if (supports_lzcnt()) {
1493 if (FLAG_IS_DEFAULT(UseCountLeadingZerosInstruction)) {
1494 UseCountLeadingZerosInstruction = true;
1495 }
1496 } else if (UseCountLeadingZerosInstruction) {
1497 warning("lzcnt instruction is not available on this CPU");
1498 FLAG_SET_DEFAULT(UseCountLeadingZerosInstruction, false);
1499 }
1500
1501 // Use count trailing zeros instruction if available
1502 if (supports_bmi1()) {
1503 // tzcnt does not require VEX prefix
1504 if (FLAG_IS_DEFAULT(UseCountTrailingZerosInstruction)) {
1505 if (!UseBMI1Instructions && !FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1506 // Don't use tzcnt if BMI1 is switched off on command line.
1507 UseCountTrailingZerosInstruction = false;
1508 } else {
1509 UseCountTrailingZerosInstruction = true;
1510 }
1511 }
1512 } else if (UseCountTrailingZerosInstruction) {
1513 warning("tzcnt instruction is not available on this CPU");
1514 FLAG_SET_DEFAULT(UseCountTrailingZerosInstruction, false);
1515 }
1516
1517 // BMI instructions (except tzcnt) use an encoding with VEX prefix.
1518 // VEX prefix is generated only when AVX > 0.
1519 if (supports_bmi1() && supports_avx()) {
1520 if (FLAG_IS_DEFAULT(UseBMI1Instructions)) {
1521 UseBMI1Instructions = true;
1522 }
1523 } else if (UseBMI1Instructions) {
1524 warning("BMI1 instructions are not available on this CPU (AVX is also required)");
1525 FLAG_SET_DEFAULT(UseBMI1Instructions, false);
1526 }
1527
1528 if (supports_bmi2() && supports_avx()) {
1529 if (FLAG_IS_DEFAULT(UseBMI2Instructions)) {
1530 UseBMI2Instructions = true;
1531 }
1532 } else if (UseBMI2Instructions) {
1533 warning("BMI2 instructions are not available on this CPU (AVX is also required)");
1534 FLAG_SET_DEFAULT(UseBMI2Instructions, false);
1535 }
1536
1537 // Use population count instruction if available.
1538 if (supports_popcnt()) {
1539 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
1540 UsePopCountInstruction = true;
1541 }
1542 } else if (UsePopCountInstruction) {
1543 warning("POPCNT instruction is not available on this CPU");
1544 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
1545 }
1546
1547 // Use fast-string operations if available.
1548 if (supports_erms()) {
1549 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1550 UseFastStosb = true;
1551 }
1552 } else if (UseFastStosb) {
1553 warning("fast-string operations are not available on this CPU");
1554 FLAG_SET_DEFAULT(UseFastStosb, false);
1555 }
1556
1557 // For AMD Processors use XMM/YMM MOVDQU instructions
1558 // for Object Initialization as default
1559 if (is_amd() && cpu_family() >= 0x19) {
1560 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1561 UseFastStosb = false;
1562 }
1563 }
1564
1565 #ifdef COMPILER2
1566 if (is_intel() && MaxVectorSize > 16) {
1567 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1568 UseFastStosb = false;
1569 }
1570 }
1571 #endif
1572
1573 // Use XMM/YMM MOVDQU instruction for Object Initialization
1574 if (UseSSE >= 2 && UseUnalignedLoadStores) {
1575 if (FLAG_IS_DEFAULT(UseXMMForObjInit)) {
1576 UseXMMForObjInit = true;
1577 }
1578 } else if (UseXMMForObjInit) {
1579 warning("UseXMMForObjInit requires SSE2 and unaligned load/stores. Feature is switched off.");
1580 FLAG_SET_DEFAULT(UseXMMForObjInit, false);
1581 }
1582
1583 #ifdef COMPILER2
1584 if (FLAG_IS_DEFAULT(AlignVector)) {
1585 // Modern processors allow misaligned memory operations for vectors.
1586 AlignVector = !UseUnalignedLoadStores;
1587 }
1588 if (FLAG_IS_DEFAULT(OptimizeFill)) {
1589 // 8247307: On x86, the auto-vectorized loop array fill code shows
1590 // better performance than the array fill stubs. We should reenable
1591 // this after the x86 stubs get improved.
1592 OptimizeFill = false;
1593 }
1594 #endif // COMPILER2
1595
1596 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1597 if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1598 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
1599 } else if (!supports_sse() && supports_3dnow_prefetch()) {
1600 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 3);
1601 }
1602 }
1603
1604 // Allocation prefetch settings
1605 intx cache_line_size = prefetch_data_size();
1606 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize) &&
1607 (cache_line_size > AllocatePrefetchStepSize)) {
1608 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, cache_line_size);
1609 }
1610
1611 if ((AllocatePrefetchDistance == 0) && (AllocatePrefetchStyle != 0)) {
1612 assert(!FLAG_IS_DEFAULT(AllocatePrefetchDistance), "default value should not be 0");
1613 if (!FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
1614 warning("AllocatePrefetchDistance is set to 0 which disable prefetching. Ignoring AllocatePrefetchStyle flag.");
1615 }
1616 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 0);
1617 }
1618
1619 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
1620 bool use_watermark_prefetch = (AllocatePrefetchStyle == 2);
1621 FLAG_SET_DEFAULT(AllocatePrefetchDistance, allocate_prefetch_distance(use_watermark_prefetch));
1622 }
1623
1624 if (is_intel() && cpu_family() == 6 && supports_sse3()) {
1625 if (FLAG_IS_DEFAULT(AllocatePrefetchLines) &&
1626 supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1627 FLAG_SET_DEFAULT(AllocatePrefetchLines, 4);
1628 }
1629 #ifdef COMPILER2
1630 if (FLAG_IS_DEFAULT(UseFPUForSpilling) && supports_sse4_2()) {
1631 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1632 }
1633 #endif
1634 }
1635
1636 if (is_zx() && ((cpu_family() == 6) || (cpu_family() == 7)) && supports_sse4_2()) {
1637 #ifdef COMPILER2
1638 if (FLAG_IS_DEFAULT(UseFPUForSpilling)) {
1639 FLAG_SET_DEFAULT(UseFPUForSpilling, true);
1640 }
1641 #endif
1642 }
1643
1644 #ifdef _LP64
1645 // Prefetch settings
1646
1647 // Prefetch interval for gc copy/scan == 9 dcache lines. Derived from
1648 // 50-warehouse specjbb runs on a 2-way 1.8ghz opteron using a 4gb heap.
1649 // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
1650 // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
1651
1652 // gc copy/scan is disabled if prefetchw isn't supported, because
1653 // Prefetch::write emits an inlined prefetchw on Linux.
1654 // Do not use the 3dnow prefetchw instruction. It isn't supported on em64t.
1655 // The used prefetcht0 instruction works for both amd64 and em64t.
1656
1657 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes)) {
1658 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 576);
1659 }
1660 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes)) {
1661 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 576);
1662 }
1663 if (FLAG_IS_DEFAULT(PrefetchFieldsAhead)) {
1664 FLAG_SET_DEFAULT(PrefetchFieldsAhead, 1);
1665 }
1666 #endif
1667
1668 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
1669 (cache_line_size > ContendedPaddingWidth))
1670 ContendedPaddingWidth = cache_line_size;
1671
1672 // This machine allows unaligned memory accesses
1673 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
1674 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
1675 }
1676
1677 #ifndef PRODUCT
1678 if (log_is_enabled(Info, os, cpu)) {
1679 LogStream ls(Log(os, cpu)::info());
1680 outputStream* log = &ls;
1681 log->print_cr("Logical CPUs per core: %u",
1682 logical_processors_per_package());
1683 log->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
1684 log->print("UseSSE=%d", (int) UseSSE);
1685 if (UseAVX > 0) {
1686 log->print(" UseAVX=%d", (int) UseAVX);
1687 }
1688 if (UseAES) {
1689 log->print(" UseAES=1");
1690 }
1691 #ifdef COMPILER2
1692 if (MaxVectorSize > 0) {
1693 log->print(" MaxVectorSize=%d", (int) MaxVectorSize);
1694 }
1695 #endif
1696 log->cr();
1697 log->print("Allocation");
1698 if (AllocatePrefetchStyle <= 0 || (UseSSE == 0 && !supports_3dnow_prefetch())) {
1699 log->print_cr(": no prefetching");
1700 } else {
1701 log->print(" prefetching: ");
1702 if (UseSSE == 0 && supports_3dnow_prefetch()) {
1703 log->print("PREFETCHW");
1704 } else if (UseSSE >= 1) {
1705 if (AllocatePrefetchInstr == 0) {
1706 log->print("PREFETCHNTA");
1707 } else if (AllocatePrefetchInstr == 1) {
1708 log->print("PREFETCHT0");
1709 } else if (AllocatePrefetchInstr == 2) {
1710 log->print("PREFETCHT2");
1711 } else if (AllocatePrefetchInstr == 3) {
1712 log->print("PREFETCHW");
1713 }
1714 }
1715 if (AllocatePrefetchLines > 1) {
1716 log->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
1717 } else {
1718 log->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
1719 }
1720 }
1721
1722 if (PrefetchCopyIntervalInBytes > 0) {
1723 log->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
1724 }
1725 if (PrefetchScanIntervalInBytes > 0) {
1726 log->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
1727 }
1728 if (PrefetchFieldsAhead > 0) {
1729 log->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
1730 }
1731 if (ContendedPaddingWidth > 0) {
1732 log->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
1733 }
1734 }
1735 #endif // !PRODUCT
1736 if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
1737 FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
1738 }
1739 if (FLAG_IS_DEFAULT(UseCopySignIntrinsic)) {
1740 FLAG_SET_DEFAULT(UseCopySignIntrinsic, true);
1741 }
1742 }
1743
1744 void VM_Version::print_platform_virtualization_info(outputStream* st) {
1745 VirtualizationType vrt = VM_Version::get_detected_virtualization();
1746 if (vrt == XenHVM) {
1747 st->print_cr("Xen hardware-assisted virtualization detected");
1748 } else if (vrt == KVM) {
1749 st->print_cr("KVM virtualization detected");
1750 } else if (vrt == VMWare) {
1751 st->print_cr("VMWare virtualization detected");
1752 VirtualizationSupport::print_virtualization_info(st);
1753 } else if (vrt == HyperV) {
1754 st->print_cr("Hyper-V virtualization detected");
1755 } else if (vrt == HyperVRole) {
1756 st->print_cr("Hyper-V role detected");
1757 }
1758 }
1759
1760 bool VM_Version::compute_has_intel_jcc_erratum() {
1761 if (!is_intel_family_core()) {
1762 // Only Intel CPUs are affected.
1763 return false;
1764 }
1765 // The following table of affected CPUs is based on the following document released by Intel:
1766 // https://www.intel.com/content/dam/support/us/en/documents/processors/mitigations-jump-conditional-code-erratum.pdf
1767 switch (_model) {
1768 case 0x8E:
1769 // 06_8EH | 9 | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Amber Lake Y
1770 // 06_8EH | 9 | 7th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake U
1771 // 06_8EH | 9 | 7th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake U 23e
1772 // 06_8EH | 9 | 7th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake Y
1773 // 06_8EH | A | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Coffee Lake U43e
1774 // 06_8EH | B | 8th Generation Intel(R) Core(TM) Processors based on microarchitecture code name Whiskey Lake U
1775 // 06_8EH | C | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Amber Lake Y
1776 // 06_8EH | C | 10th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Comet Lake U42
1777 // 06_8EH | C | 8th Generation Intel(R) Core(TM) Processors based on microarchitecture code name Whiskey Lake U
1778 return _stepping == 0x9 || _stepping == 0xA || _stepping == 0xB || _stepping == 0xC;
1779 case 0x4E:
1780 // 06_4E | 3 | 6th Generation Intel(R) Core(TM) Processors based on microarchitecture code name Skylake U
1781 // 06_4E | 3 | 6th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Skylake U23e
1782 // 06_4E | 3 | 6th Generation Intel(R) Core(TM) Processors based on microarchitecture code name Skylake Y
1783 return _stepping == 0x3;
1784 case 0x55:
1785 // 06_55H | 4 | Intel(R) Xeon(R) Processor D Family based on microarchitecture code name Skylake D, Bakerville
1786 // 06_55H | 4 | Intel(R) Xeon(R) Scalable Processors based on microarchitecture code name Skylake Server
1787 // 06_55H | 4 | Intel(R) Xeon(R) Processor W Family based on microarchitecture code name Skylake W
1788 // 06_55H | 4 | Intel(R) Core(TM) X-series Processors based on microarchitecture code name Skylake X
1789 // 06_55H | 4 | Intel(R) Xeon(R) Processor E3 v5 Family based on microarchitecture code name Skylake Xeon E3
1790 // 06_55 | 7 | 2nd Generation Intel(R) Xeon(R) Scalable Processors based on microarchitecture code name Cascade Lake (server)
1791 return _stepping == 0x4 || _stepping == 0x7;
1792 case 0x5E:
1793 // 06_5E | 3 | 6th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Skylake H
1794 // 06_5E | 3 | 6th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Skylake S
1795 return _stepping == 0x3;
1796 case 0x9E:
1797 // 06_9EH | 9 | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake G
1798 // 06_9EH | 9 | 7th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake H
1799 // 06_9EH | 9 | 7th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake S
1800 // 06_9EH | 9 | Intel(R) Core(TM) X-series Processors based on microarchitecture code name Kaby Lake X
1801 // 06_9EH | 9 | Intel(R) Xeon(R) Processor E3 v6 Family Kaby Lake Xeon E3
1802 // 06_9EH | A | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Coffee Lake H
1803 // 06_9EH | A | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Coffee Lake S
1804 // 06_9EH | A | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Coffee Lake S (6+2) x/KBP
1805 // 06_9EH | A | Intel(R) Xeon(R) Processor E Family based on microarchitecture code name Coffee Lake S (6+2)
1806 // 06_9EH | A | Intel(R) Xeon(R) Processor E Family based on microarchitecture code name Coffee Lake S (4+2)
1807 // 06_9EH | B | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Coffee Lake S (4+2)
1808 // 06_9EH | B | Intel(R) Celeron(R) Processor G Series based on microarchitecture code name Coffee Lake S (4+2)
1809 // 06_9EH | D | 9th Generation Intel(R) Core(TM) Processor Family based on microarchitecturecode name Coffee Lake H (8+2)
1810 // 06_9EH | D | 9th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Coffee Lake S (8+2)
1811 return _stepping == 0x9 || _stepping == 0xA || _stepping == 0xB || _stepping == 0xD;
1812 case 0xA5:
1813 // Not in Intel documentation.
1814 // 06_A5H | | 10th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Comet Lake S/H
1815 return true;
1816 case 0xA6:
1817 // 06_A6H | 0 | 10th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Comet Lake U62
1818 return _stepping == 0x0;
1819 case 0xAE:
1820 // 06_AEH | A | 8th Generation Intel(R) Core(TM) Processor Family based on microarchitecture code name Kaby Lake Refresh U (4+2)
1821 return _stepping == 0xA;
1822 default:
1823 // If we are running on another intel machine not recognized in the table, we are okay.
1824 return false;
1825 }
1826 }
1827
1828 // On Xen, the cpuid instruction returns
1829 // eax / registers[0]: Version of Xen
1830 // ebx / registers[1]: chars 'XenV'
1831 // ecx / registers[2]: chars 'MMXe'
1832 // edx / registers[3]: chars 'nVMM'
1833 //
1834 // On KVM / VMWare / MS Hyper-V, the cpuid instruction returns
1835 // ebx / registers[1]: chars 'KVMK' / 'VMwa' / 'Micr'
1836 // ecx / registers[2]: chars 'VMKV' / 'reVM' / 'osof'
1837 // edx / registers[3]: chars 'M' / 'ware' / 't Hv'
1838 //
1839 // more information :
1840 // https://kb.vmware.com/s/article/1009458
1841 //
1842 void VM_Version::check_virtualizations() {
1843 uint32_t registers[4] = {0};
1844 char signature[13] = {0};
1845
1846 // Xen cpuid leaves can be found 0x100 aligned boundary starting
1847 // from 0x40000000 until 0x40010000.
1848 // https://lists.linuxfoundation.org/pipermail/virtualization/2012-May/019974.html
1849 for (int leaf = 0x40000000; leaf < 0x40010000; leaf += 0x100) {
1850 detect_virt_stub(leaf, registers);
1851 memcpy(signature, ®isters[1], 12);
1852
1853 if (strncmp("VMwareVMware", signature, 12) == 0) {
1854 Abstract_VM_Version::_detected_virtualization = VMWare;
1855 // check for extended metrics from guestlib
1856 VirtualizationSupport::initialize();
1857 } else if (strncmp("Microsoft Hv", signature, 12) == 0) {
1858 Abstract_VM_Version::_detected_virtualization = HyperV;
1859 #ifdef _WINDOWS
1860 // CPUID leaf 0x40000007 is available to the root partition only.
1861 // See Hypervisor Top Level Functional Specification section 2.4.8 for more details.
1862 // https://github.com/MicrosoftDocs/Virtualization-Documentation/raw/master/tlfs/Hypervisor%20Top%20Level%20Functional%20Specification%20v6.0b.pdf
1863 detect_virt_stub(0x40000007, registers);
1864 if ((registers[0] != 0x0) ||
1865 (registers[1] != 0x0) ||
1866 (registers[2] != 0x0) ||
1867 (registers[3] != 0x0)) {
1868 Abstract_VM_Version::_detected_virtualization = HyperVRole;
1869 }
1870 #endif
1871 } else if (strncmp("KVMKVMKVM", signature, 9) == 0) {
1872 Abstract_VM_Version::_detected_virtualization = KVM;
1873 } else if (strncmp("XenVMMXenVMM", signature, 12) == 0) {
1874 Abstract_VM_Version::_detected_virtualization = XenHVM;
1875 }
1876 }
1877 }
1878
1879 void VM_Version::initialize() {
1880 ResourceMark rm;
1881 // Making this stub must be FIRST use of assembler
1882 stub_blob = BufferBlob::create("VM_Version stub", stub_size);
1883 if (stub_blob == NULL) {
1884 vm_exit_during_initialization("Unable to allocate stub for VM_Version");
1885 }
1886 CodeBuffer c(stub_blob);
1887 VM_Version_StubGenerator g(&c);
1888
1889 get_cpu_info_stub = CAST_TO_FN_PTR(get_cpu_info_stub_t,
1890 g.generate_get_cpu_info());
1891 detect_virt_stub = CAST_TO_FN_PTR(detect_virt_stub_t,
1892 g.generate_detect_virt());
1893
1894 get_processor_features();
1895
1896 LP64_ONLY(Assembler::precompute_instructions();)
1897
1898 if (VM_Version::supports_hv()) { // Supports hypervisor
1899 check_virtualizations();
1900 }
1901 }