48 int VM_Version::_stepping;
49 bool VM_Version::_has_intel_jcc_erratum;
50 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
51
52 #define DECLARE_CPU_FEATURE_NAME(id, name) XSTR(name),
53 const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)};
54 #undef DECLARE_CPU_FEATURE_NAME
55
56 // Address of instruction which causes SEGV
57 address VM_Version::_cpuinfo_segv_addr = nullptr;
58 // Address of instruction after the one which causes SEGV
59 address VM_Version::_cpuinfo_cont_addr = nullptr;
60 // Address of instruction which causes APX specific SEGV
61 address VM_Version::_cpuinfo_segv_addr_apx = nullptr;
62 // Address of instruction after the one which causes APX specific SEGV
63 address VM_Version::_cpuinfo_cont_addr_apx = nullptr;
64
65 static BufferBlob* stub_blob;
66 static const int stub_size = 2550;
67
68 int VM_Version::VM_Features::_features_bitmap_size = sizeof(VM_Version::VM_Features::_features_bitmap) / BytesPerLong;
69
70 VM_Version::VM_Features VM_Version::_features;
71 VM_Version::VM_Features VM_Version::_cpu_features;
72
73 extern "C" {
74 typedef void (*get_cpu_info_stub_t)(void*);
75 typedef void (*detect_virt_stub_t)(uint32_t, uint32_t*);
76 typedef void (*clear_apx_test_state_t)(void);
77 typedef void (*getCPUIDBrandString_stub_t)(void*);
78 }
79 static get_cpu_info_stub_t get_cpu_info_stub = nullptr;
80 static detect_virt_stub_t detect_virt_stub = nullptr;
81 static clear_apx_test_state_t clear_apx_test_state_stub = nullptr;
82 static getCPUIDBrandString_stub_t getCPUIDBrandString_stub = nullptr;
83
84 #define CPUID_STANDARD_FN 0x0
85 #define CPUID_STANDARD_FN_1 0x1
86 #define CPUID_STANDARD_FN_4 0x4
87 #define CPUID_STANDARD_FN_B 0xb
88
89 #define CPUID_EXTENDED_FN 0x80000000
1319 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
1320 }
1321 } else if (UseSHA512Intrinsics) {
1322 if (!FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
1323 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
1324 }
1325 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
1326 }
1327
1328 if (UseSHA && supports_evex() && supports_avx512bw()) {
1329 if (FLAG_IS_DEFAULT(UseSHA3Intrinsics)) {
1330 FLAG_SET_DEFAULT(UseSHA3Intrinsics, true);
1331 }
1332 } else if (UseSHA3Intrinsics) {
1333 if (!FLAG_IS_DEFAULT(UseSHA3Intrinsics)) {
1334 warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
1335 }
1336 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
1337 }
1338
1339 #if COMPILER2_OR_JVMCI
1340 int max_vector_size = 0;
1341 if (UseAVX == 0 || !os_supports_avx_vectors()) {
1342 // 16 byte vectors (in XMM) are supported with SSE2+
1343 max_vector_size = 16;
1344 } else if (UseAVX == 1 || UseAVX == 2) {
1345 // 32 bytes vectors (in YMM) are only supported with AVX+
1346 max_vector_size = 32;
1347 } else if (UseAVX > 2) {
1348 // 64 bytes vectors (in ZMM) are only supported with AVX 3
1349 max_vector_size = 64;
1350 }
1351
1352 int min_vector_size = 4; // We require MaxVectorSize to be at least 4 on 64bit
1353
1354 if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
1355 if (MaxVectorSize < min_vector_size) {
1356 warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
1357 FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
1358 }
1359 if (MaxVectorSize > max_vector_size) {
1360 warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
1361 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1362 }
1363 if (!is_power_of_2(MaxVectorSize)) {
1364 warning("MaxVectorSize must be a power of 2, setting to default: %i", max_vector_size);
1365 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1366 }
1367 } else {
1368 // If default, use highest supported configuration
1369 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1370 }
1371
1372 #if defined(COMPILER2) && defined(ASSERT)
1373 if (MaxVectorSize > 0) {
1374 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
1375 tty->print_cr("State of YMM registers after signal handle:");
1376 int nreg = 4;
1377 const char* ymm_name[4] = {"0", "7", "8", "15"};
1378 for (int i = 0; i < nreg; i++) {
1379 tty->print("YMM%s:", ymm_name[i]);
1380 for (int j = 7; j >=0; j--) {
1381 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
1382 }
1383 tty->cr();
1384 }
1385 }
1386 }
1387 #endif // COMPILER2 && ASSERT
1388
1389 if ((supports_avx512ifma() && supports_avx512vlbw()) || supports_avxifma()) {
1390 if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
1391 FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
1392 }
1393 } else if (UsePoly1305Intrinsics) {
1394 if (!FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
1395 warning("Intrinsics for Poly1305 crypto hash functions not available on this CPU.");
1396 }
1397 FLAG_SET_DEFAULT(UsePoly1305Intrinsics, false);
1398 }
1399
1400 if ((supports_avx512ifma() && supports_avx512vlbw()) || supports_avxifma()) {
1401 if (FLAG_IS_DEFAULT(UseIntPolyIntrinsics)) {
1402 FLAG_SET_DEFAULT(UseIntPolyIntrinsics, true);
1403 }
1404 } else if (UseIntPolyIntrinsics) {
1405 if (!FLAG_IS_DEFAULT(UseIntPolyIntrinsics)) {
1406 warning("Intrinsics for Polynomial crypto functions not available on this CPU.");
1407 }
1408 FLAG_SET_DEFAULT(UseIntPolyIntrinsics, false);
1409 }
1410
1411 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1412 UseMultiplyToLenIntrinsic = true;
1413 }
1414 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1415 UseSquareToLenIntrinsic = true;
1416 }
1417 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1418 UseMulAddIntrinsic = true;
1419 }
1420 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1421 UseMontgomeryMultiplyIntrinsic = true;
1422 }
1423 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1424 UseMontgomerySquareIntrinsic = true;
1425 }
1426 #endif // COMPILER2_OR_JVMCI
1427
1428 // On new cpus instructions which update whole XMM register should be used
1429 // to prevent partial register stall due to dependencies on high half.
1430 //
1431 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
1432 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1433 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
1434 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
1435
1436
1437 if (is_zx()) { // ZX cpus specific settings
1438 if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1439 UseStoreImmI16 = false; // don't use it on ZX cpus
1440 }
1441 if ((cpu_family() == 6) || (cpu_family() == 7)) {
1442 if (FLAG_IS_DEFAULT(UseAddressNop)) {
1443 // Use it on all ZX cpus
1444 UseAddressNop = true;
1445 }
1446 }
1704 FLAG_SET_DEFAULT(UseFastStosb, false);
1705 }
1706
1707 // For AMD Processors use XMM/YMM MOVDQU instructions
1708 // for Object Initialization as default
1709 if (is_amd() && cpu_family() >= 0x19) {
1710 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1711 UseFastStosb = false;
1712 }
1713 }
1714
1715 #ifdef COMPILER2
1716 if (is_intel() && MaxVectorSize > 16) {
1717 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1718 UseFastStosb = false;
1719 }
1720 }
1721 #endif
1722
1723 // Use XMM/YMM MOVDQU instruction for Object Initialization
1724 if (!UseFastStosb && UseUnalignedLoadStores) {
1725 if (FLAG_IS_DEFAULT(UseXMMForObjInit)) {
1726 UseXMMForObjInit = true;
1727 }
1728 } else if (UseXMMForObjInit) {
1729 if (!FLAG_IS_DEFAULT(UseXMMForObjInit)) {
1730 warning("UseXMMForObjInit requires SSE2 and unaligned load/stores. Feature is switched off.");
1731 }
1732 FLAG_SET_DEFAULT(UseXMMForObjInit, false);
1733 }
1734
1735 #ifdef COMPILER2
1736 if (FLAG_IS_DEFAULT(AlignVector)) {
1737 // Modern processors allow misaligned memory operations for vectors.
1738 AlignVector = !UseUnalignedLoadStores;
1739 }
1740 #endif // COMPILER2
1741
1742 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1743 if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1744 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
|
48 int VM_Version::_stepping;
49 bool VM_Version::_has_intel_jcc_erratum;
50 VM_Version::CpuidInfo VM_Version::_cpuid_info = { 0, };
51
52 #define DECLARE_CPU_FEATURE_NAME(id, name) XSTR(name),
53 const char* VM_Version::_features_names[] = { CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_NAME)};
54 #undef DECLARE_CPU_FEATURE_NAME
55
56 // Address of instruction which causes SEGV
57 address VM_Version::_cpuinfo_segv_addr = nullptr;
58 // Address of instruction after the one which causes SEGV
59 address VM_Version::_cpuinfo_cont_addr = nullptr;
60 // Address of instruction which causes APX specific SEGV
61 address VM_Version::_cpuinfo_segv_addr_apx = nullptr;
62 // Address of instruction after the one which causes APX specific SEGV
63 address VM_Version::_cpuinfo_cont_addr_apx = nullptr;
64
65 static BufferBlob* stub_blob;
66 static const int stub_size = 2550;
67
68 VM_Version::VM_Features VM_Version::_features;
69 VM_Version::VM_Features VM_Version::_cpu_features;
70
71 extern "C" {
72 typedef void (*get_cpu_info_stub_t)(void*);
73 typedef void (*detect_virt_stub_t)(uint32_t, uint32_t*);
74 typedef void (*clear_apx_test_state_t)(void);
75 typedef void (*getCPUIDBrandString_stub_t)(void*);
76 }
77 static get_cpu_info_stub_t get_cpu_info_stub = nullptr;
78 static detect_virt_stub_t detect_virt_stub = nullptr;
79 static clear_apx_test_state_t clear_apx_test_state_stub = nullptr;
80 static getCPUIDBrandString_stub_t getCPUIDBrandString_stub = nullptr;
81
82 #define CPUID_STANDARD_FN 0x0
83 #define CPUID_STANDARD_FN_1 0x1
84 #define CPUID_STANDARD_FN_4 0x4
85 #define CPUID_STANDARD_FN_B 0xb
86
87 #define CPUID_EXTENDED_FN 0x80000000
1317 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
1318 }
1319 } else if (UseSHA512Intrinsics) {
1320 if (!FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
1321 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
1322 }
1323 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
1324 }
1325
1326 if (UseSHA && supports_evex() && supports_avx512bw()) {
1327 if (FLAG_IS_DEFAULT(UseSHA3Intrinsics)) {
1328 FLAG_SET_DEFAULT(UseSHA3Intrinsics, true);
1329 }
1330 } else if (UseSHA3Intrinsics) {
1331 if (!FLAG_IS_DEFAULT(UseSHA3Intrinsics)) {
1332 warning("Intrinsics for SHA3-224, SHA3-256, SHA3-384 and SHA3-512 crypto hash functions not available on this CPU.");
1333 }
1334 FLAG_SET_DEFAULT(UseSHA3Intrinsics, false);
1335 }
1336
1337 #ifdef COMPILER2
1338 int max_vector_size = 0;
1339 if (UseAVX == 0 || !os_supports_avx_vectors()) {
1340 // 16 byte vectors (in XMM) are supported with SSE2+
1341 max_vector_size = 16;
1342 } else if (UseAVX == 1 || UseAVX == 2) {
1343 // 32 bytes vectors (in YMM) are only supported with AVX+
1344 max_vector_size = 32;
1345 } else if (UseAVX > 2) {
1346 // 64 bytes vectors (in ZMM) are only supported with AVX 3
1347 max_vector_size = 64;
1348 }
1349
1350 int min_vector_size = 4; // We require MaxVectorSize to be at least 4 on 64bit
1351
1352 if (!FLAG_IS_DEFAULT(MaxVectorSize)) {
1353 if (MaxVectorSize < min_vector_size) {
1354 warning("MaxVectorSize must be at least %i on this platform", min_vector_size);
1355 FLAG_SET_DEFAULT(MaxVectorSize, min_vector_size);
1356 }
1357 if (MaxVectorSize > max_vector_size) {
1358 warning("MaxVectorSize must be at most %i on this platform", max_vector_size);
1359 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1360 }
1361 if (!is_power_of_2(MaxVectorSize)) {
1362 warning("MaxVectorSize must be a power of 2, setting to default: %i", max_vector_size);
1363 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1364 }
1365 } else {
1366 // If default, use highest supported configuration
1367 FLAG_SET_DEFAULT(MaxVectorSize, max_vector_size);
1368 }
1369
1370 #ifdef ASSERT
1371 if (MaxVectorSize > 0) {
1372 if (supports_avx() && PrintMiscellaneous && Verbose && TraceNewVectors) {
1373 tty->print_cr("State of YMM registers after signal handle:");
1374 int nreg = 4;
1375 const char* ymm_name[4] = {"0", "7", "8", "15"};
1376 for (int i = 0; i < nreg; i++) {
1377 tty->print("YMM%s:", ymm_name[i]);
1378 for (int j = 7; j >=0; j--) {
1379 tty->print(" %x", _cpuid_info.ymm_save[i*8 + j]);
1380 }
1381 tty->cr();
1382 }
1383 }
1384 }
1385 #endif // ASSERT
1386
1387 if ((supports_avx512ifma() && supports_avx512vlbw()) || supports_avxifma()) {
1388 if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
1389 FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
1390 }
1391 } else if (UsePoly1305Intrinsics) {
1392 if (!FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
1393 warning("Intrinsics for Poly1305 crypto hash functions not available on this CPU.");
1394 }
1395 FLAG_SET_DEFAULT(UsePoly1305Intrinsics, false);
1396 }
1397
1398 if ((supports_avx512ifma() && supports_avx512vlbw()) || supports_avxifma()) {
1399 if (FLAG_IS_DEFAULT(UseIntPolyIntrinsics)) {
1400 FLAG_SET_DEFAULT(UseIntPolyIntrinsics, true);
1401 }
1402 } else if (UseIntPolyIntrinsics) {
1403 if (!FLAG_IS_DEFAULT(UseIntPolyIntrinsics)) {
1404 warning("Intrinsics for Polynomial crypto functions not available on this CPU.");
1405 }
1406 FLAG_SET_DEFAULT(UseIntPolyIntrinsics, false);
1407 }
1408
1409 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
1410 UseMultiplyToLenIntrinsic = true;
1411 }
1412 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
1413 UseSquareToLenIntrinsic = true;
1414 }
1415 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
1416 UseMulAddIntrinsic = true;
1417 }
1418 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
1419 UseMontgomeryMultiplyIntrinsic = true;
1420 }
1421 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
1422 UseMontgomerySquareIntrinsic = true;
1423 }
1424 #endif // COMPILER2
1425
1426 // On new cpus instructions which update whole XMM register should be used
1427 // to prevent partial register stall due to dependencies on high half.
1428 //
1429 // UseXmmLoadAndClearUpper == true --> movsd(xmm, mem)
1430 // UseXmmLoadAndClearUpper == false --> movlpd(xmm, mem)
1431 // UseXmmRegToRegMoveAll == true --> movaps(xmm, xmm), movapd(xmm, xmm).
1432 // UseXmmRegToRegMoveAll == false --> movss(xmm, xmm), movsd(xmm, xmm).
1433
1434
1435 if (is_zx()) { // ZX cpus specific settings
1436 if (FLAG_IS_DEFAULT(UseStoreImmI16)) {
1437 UseStoreImmI16 = false; // don't use it on ZX cpus
1438 }
1439 if ((cpu_family() == 6) || (cpu_family() == 7)) {
1440 if (FLAG_IS_DEFAULT(UseAddressNop)) {
1441 // Use it on all ZX cpus
1442 UseAddressNop = true;
1443 }
1444 }
1702 FLAG_SET_DEFAULT(UseFastStosb, false);
1703 }
1704
1705 // For AMD Processors use XMM/YMM MOVDQU instructions
1706 // for Object Initialization as default
1707 if (is_amd() && cpu_family() >= 0x19) {
1708 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1709 UseFastStosb = false;
1710 }
1711 }
1712
1713 #ifdef COMPILER2
1714 if (is_intel() && MaxVectorSize > 16) {
1715 if (FLAG_IS_DEFAULT(UseFastStosb)) {
1716 UseFastStosb = false;
1717 }
1718 }
1719 #endif
1720
1721 // Use XMM/YMM MOVDQU instruction for Object Initialization
1722 if (UseUnalignedLoadStores) {
1723 if (FLAG_IS_DEFAULT(UseXMMForObjInit)) {
1724 UseXMMForObjInit = true;
1725 }
1726 } else if (UseXMMForObjInit) {
1727 if (!FLAG_IS_DEFAULT(UseXMMForObjInit)) {
1728 warning("UseXMMForObjInit requires SSE2 and unaligned load/stores. Feature is switched off.");
1729 }
1730 FLAG_SET_DEFAULT(UseXMMForObjInit, false);
1731 }
1732
1733 #ifdef COMPILER2
1734 if (FLAG_IS_DEFAULT(AlignVector)) {
1735 // Modern processors allow misaligned memory operations for vectors.
1736 AlignVector = !UseUnalignedLoadStores;
1737 }
1738 #endif // COMPILER2
1739
1740 if (FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
1741 if (AllocatePrefetchInstr == 3 && !supports_3dnow_prefetch()) {
1742 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
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