1 //
2 // Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
165 //
166
167 // Empty register class.
168 reg_class no_reg();
169
170 // Class for all pointer/long registers
171 reg_class all_reg(RAX, RAX_H,
172 RDX, RDX_H,
173 RBP, RBP_H,
174 RDI, RDI_H,
175 RSI, RSI_H,
176 RCX, RCX_H,
177 RBX, RBX_H,
178 RSP, RSP_H,
179 R8, R8_H,
180 R9, R9_H,
181 R10, R10_H,
182 R11, R11_H,
183 R12, R12_H,
184 R13, R13_H,
185 R14, R14_H,
186 R15, R15_H);
187
188 // Class for all int registers
189 reg_class all_int_reg(RAX
190 RDX,
191 RBP,
192 RDI,
193 RSI,
194 RCX,
195 RBX,
196 R8,
197 R9,
198 R10,
199 R11,
200 R12,
201 R13,
202 R14);
203
204 // Class for all pointer registers
205 reg_class any_reg %{
206 return _ANY_REG_mask;
207 %}
208
209 // Class for all pointer registers (excluding RSP)
210 reg_class ptr_reg %{
211 return _PTR_REG_mask;
212 %}
213
214 // Class for all pointer registers (excluding RSP and RBP)
215 reg_class ptr_reg_no_rbp %{
216 return _PTR_REG_NO_RBP_mask;
217 %}
218
219 // Class for all pointer registers (excluding RAX and RSP)
220 reg_class ptr_no_rax_reg %{
221 return _PTR_NO_RAX_REG_mask;
222 %}
223
224 // Class for all pointer registers (excluding RAX, RBX, and RSP)
225 reg_class ptr_no_rax_rbx_reg %{
226 return _PTR_NO_RAX_RBX_REG_mask;
227 %}
228
229 // Class for all long registers (excluding RSP)
230 reg_class long_reg %{
231 return _LONG_REG_mask;
232 %}
233
234 // Class for all long registers (excluding RAX, RDX and RSP)
235 reg_class long_no_rax_rdx_reg %{
236 return _LONG_NO_RAX_RDX_REG_mask;
237 %}
238
239 // Class for all long registers (excluding RCX and RSP)
240 reg_class long_no_rcx_reg %{
241 return _LONG_NO_RCX_REG_mask;
242 %}
243
244 // Class for all int registers (excluding RSP)
245 reg_class int_reg %{
246 return _INT_REG_mask;
247 %}
248
249 // Class for all int registers (excluding RAX, RDX, and RSP)
250 reg_class int_no_rax_rdx_reg %{
251 return _INT_NO_RAX_RDX_REG_mask;
252 %}
253
254 // Class for all int registers (excluding RCX and RSP)
255 reg_class int_no_rcx_reg %{
256 return _INT_NO_RCX_REG_mask;
257 %}
258
259 // Singleton class for RAX pointer register
260 reg_class ptr_rax_reg(RAX, RAX_H);
261
262 // Singleton class for RBX pointer register
263 reg_class ptr_rbx_reg(RBX, RBX_H);
264
265 // Singleton class for RSI pointer register
266 reg_class ptr_rsi_reg(RSI, RSI_H);
267
268 // Singleton class for RBP pointer register
269 reg_class ptr_rbp_reg(RBP, RBP_H);
270
271 // Singleton class for RDI pointer register
272 reg_class ptr_rdi_reg(RDI, RDI_H);
273
274 // Singleton class for stack pointer
275 reg_class ptr_rsp_reg(RSP, RSP_H);
276
277 // Singleton class for TLS pointer
278 reg_class ptr_r15_reg(R15, R15_H);
279
280 // Singleton class for RAX long register
281 reg_class long_rax_reg(RAX, RAX_H);
282
283 // Singleton class for RCX long register
284 reg_class long_rcx_reg(RCX, RCX_H);
285
286 // Singleton class for RDX long register
287 reg_class long_rdx_reg(RDX, RDX_H);
288
289 // Singleton class for RAX int register
290 reg_class int_rax_reg(RAX);
291
292 // Singleton class for RBX int register
293 reg_class int_rbx_reg(RBX);
294
295 // Singleton class for RCX int register
296 reg_class int_rcx_reg(RCX);
297
298 // Singleton class for RCX int register
299 reg_class int_rdx_reg(RDX);
300
301 // Singleton class for RCX int register
302 reg_class int_rdi_reg(RDI);
303
304 // Singleton class for instruction pointer
305 // reg_class ip_reg(RIP);
306
307 %}
308
309 //----------SOURCE BLOCK-------------------------------------------------------
310 // This is a block of C++ code which provides values, functions, and
311 // definitions necessary in the rest of the architecture description
312 source_hpp %{
313
314 extern RegMask _ANY_REG_mask;
315 extern RegMask _PTR_REG_mask;
316 extern RegMask _PTR_REG_NO_RBP_mask;
317 extern RegMask _PTR_NO_RAX_REG_mask;
318 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
319 extern RegMask _LONG_REG_mask;
320 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
321 extern RegMask _LONG_NO_RCX_REG_mask;
322 extern RegMask _INT_REG_mask;
323 extern RegMask _INT_NO_RAX_RDX_REG_mask;
324 extern RegMask _INT_NO_RCX_REG_mask;
325 extern RegMask _FLOAT_REG_mask;
326
327 extern RegMask _STACK_OR_PTR_REG_mask;
328 extern RegMask _STACK_OR_LONG_REG_mask;
329 extern RegMask _STACK_OR_INT_REG_mask;
330
331 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
332 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
333 inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; }
334
335 %}
336
337 source %{
338 #define RELOC_IMM64 Assembler::imm_operand
339 #define RELOC_DISP32 Assembler::disp32_operand
340
341 #define __ _masm.
342
343 RegMask _ANY_REG_mask;
344 RegMask _PTR_REG_mask;
345 RegMask _PTR_REG_NO_RBP_mask;
346 RegMask _PTR_NO_RAX_REG_mask;
347 RegMask _PTR_NO_RAX_RBX_REG_mask;
348 RegMask _LONG_REG_mask;
349 RegMask _LONG_NO_RAX_RDX_REG_mask;
350 RegMask _LONG_NO_RCX_REG_mask;
351 RegMask _INT_REG_mask;
352 RegMask _INT_NO_RAX_RDX_REG_mask;
353 RegMask _INT_NO_RCX_REG_mask;
354 RegMask _FLOAT_REG_mask;
355 RegMask _STACK_OR_PTR_REG_mask;
356 RegMask _STACK_OR_LONG_REG_mask;
357 RegMask _STACK_OR_INT_REG_mask;
358
359 static bool need_r12_heapbase() {
360 return UseCompressedOops;
361 }
362
363 void reg_mask_init() {
364 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
365 // We derive a number of subsets from it.
366 _ANY_REG_mask = _ALL_REG_mask;
367
368 if (PreserveFramePointer) {
369 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
370 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
371 }
372 if (need_r12_heapbase()) {
373 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
374 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
375 }
376
377 _PTR_REG_mask = _ANY_REG_mask;
378 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
379 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
380 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
381 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
382
383 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
384 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
385
386 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
387 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
388 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
389
390 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
391 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
392 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
393
394 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
395 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
396 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
397
398 _LONG_REG_mask = _PTR_REG_mask;
399 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
400 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
401
402 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
403 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
404 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
405 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
406 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
407
408 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
409 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
410 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
411
412 _INT_REG_mask = _ALL_INT_REG_mask;
413 if (PreserveFramePointer) {
414 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
415 }
416 if (need_r12_heapbase()) {
417 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
418 }
419
420 _STACK_OR_INT_REG_mask = _INT_REG_mask;
421 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
422
423 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
424 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
425 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
426
427 _INT_NO_RCX_REG_mask = _INT_REG_mask;
428 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
429
430 // _FLOAT_REG_LEGACY_mask/_FLOAT_REG_EVEX_mask is generated by adlc
431 // from the float_reg_legacy/float_reg_evex register class.
432 _FLOAT_REG_mask = VM_Version::supports_evex() ? _FLOAT_REG_EVEX_mask : _FLOAT_REG_LEGACY_mask;
433
434 if (Matcher::has_predicated_vectors()) {
435 // Post-loop multi-versioning expects mask to be present in K1 register, till the time
436 // its fixed, RA should not be allocting K1 register, this shall prevent any accidental
437 // curruption of value held in K1 register.
438 if (PostLoopMultiversioning) {
439 const_cast<RegMask*>(&_VECTMASK_REG_mask)->Remove(OptoReg::as_OptoReg(k1->as_VMReg()));
440 const_cast<RegMask*>(&_VECTMASK_REG_mask)->Remove(OptoReg::as_OptoReg(k1->as_VMReg()->next()));
441 }
442 }
443 }
444
445 static bool generate_vzeroupper(Compile* C) {
446 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
447 }
448
449 static int clear_avx_size() {
450 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
451 }
452
453 // !!!!! Special hack to get all types of calls to specify the byte offset
454 // from the start of the call to the point where the return address
455 // will point.
456 int MachCallStaticJavaNode::ret_addr_offset()
457 {
458 int offset = 5; // 5 bytes from start of call to where return address points
459 offset += clear_avx_size();
460 return offset;
461 }
462
463 int MachCallDynamicJavaNode::ret_addr_offset()
464 {
465 int offset = 15; // 15 bytes from start of call to where return address points
466 offset += clear_avx_size();
467 return offset;
468 }
469
470 int MachCallRuntimeNode::ret_addr_offset() {
471 if (_entry_point == NULL) {
472 // CallLeafNoFPInDirect
473 return 3; // callq (register)
474 }
475 int offset = 13; // movq r10,#addr; callq (r10)
476 if (this->ideal_Opcode() != Op_CallLeafVector) {
477 offset += clear_avx_size();
478 }
479 return offset;
480 }
481
482 int MachCallNativeNode::ret_addr_offset() {
483 int offset = 13; // movq r10,#addr; callq (r10)
484 offset += clear_avx_size();
485 return offset;
486 }
487
488 //
489 // Compute padding required for nodes which need alignment
490 //
491
492 // The address of the call instruction needs to be 4-byte aligned to
493 // ensure that it does not span a cache line so that it can be patched.
494 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
495 {
496 current_offset += clear_avx_size(); // skip vzeroupper
497 current_offset += 1; // skip call opcode byte
498 return align_up(current_offset, alignment_required()) - current_offset;
499 }
500
501 // The address of the call instruction needs to be 4-byte aligned to
502 // ensure that it does not span a cache line so that it can be patched.
503 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
504 {
505 current_offset += clear_avx_size(); // skip vzeroupper
506 current_offset += 11; // skip movq instruction + call opcode byte
507 return align_up(current_offset, alignment_required()) - current_offset;
508 }
509
510 // EMIT_RM()
511 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
512 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
513 cbuf.insts()->emit_int8(c);
514 }
515
516 // EMIT_CC()
517 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
518 unsigned char c = (unsigned char) (f1 | f2);
519 cbuf.insts()->emit_int8(c);
520 }
521
522 // EMIT_OPCODE()
523 void emit_opcode(CodeBuffer &cbuf, int code) {
524 cbuf.insts()->emit_int8((unsigned char) code);
525 }
526
527 // EMIT_OPCODE() w/ relocation information
528 void emit_opcode(CodeBuffer &cbuf,
529 int code, relocInfo::relocType reloc, int offset, int format)
530 {
531 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
532 emit_opcode(cbuf, code);
533 }
534
535 // EMIT_D8()
536 void emit_d8(CodeBuffer &cbuf, int d8) {
537 cbuf.insts()->emit_int8((unsigned char) d8);
538 }
539
540 // EMIT_D16()
541 void emit_d16(CodeBuffer &cbuf, int d16) {
542 cbuf.insts()->emit_int16(d16);
543 }
544
545 // EMIT_D32()
546 void emit_d32(CodeBuffer &cbuf, int d32) {
547 cbuf.insts()->emit_int32(d32);
548 }
549
550 // EMIT_D64()
551 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
552 cbuf.insts()->emit_int64(d64);
553 }
554
555 // emit 32 bit value and construct relocation entry from relocInfo::relocType
556 void emit_d32_reloc(CodeBuffer& cbuf,
557 int d32,
558 relocInfo::relocType reloc,
559 int format)
560 {
561 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
562 cbuf.relocate(cbuf.insts_mark(), reloc, format);
563 cbuf.insts()->emit_int32(d32);
564 }
565
566 // emit 32 bit value and construct relocation entry from RelocationHolder
567 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
568 #ifdef ASSERT
569 if (rspec.reloc()->type() == relocInfo::oop_type &&
570 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
571 assert(Universe::heap()->is_in((address)(intptr_t)d32), "should be real oop");
572 assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code");
573 }
574 #endif
575 cbuf.relocate(cbuf.insts_mark(), rspec, format);
576 cbuf.insts()->emit_int32(d32);
577 }
578
579 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
580 address next_ip = cbuf.insts_end() + 4;
581 emit_d32_reloc(cbuf, (int) (addr - next_ip),
582 external_word_Relocation::spec(addr),
583 RELOC_DISP32);
584 }
585
586
587 // emit 64 bit value and construct relocation entry from relocInfo::relocType
588 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
589 cbuf.relocate(cbuf.insts_mark(), reloc, format);
590 cbuf.insts()->emit_int64(d64);
591 }
592
593 // emit 64 bit value and construct relocation entry from RelocationHolder
594 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
595 #ifdef ASSERT
596 if (rspec.reloc()->type() == relocInfo::oop_type &&
597 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
598 assert(Universe::heap()->is_in((address)d64), "should be real oop");
599 assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code");
600 }
601 #endif
602 cbuf.relocate(cbuf.insts_mark(), rspec, format);
603 cbuf.insts()->emit_int64(d64);
604 }
605
606 // Access stack slot for load or store
607 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
608 {
609 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
610 if (-0x80 <= disp && disp < 0x80) {
611 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
612 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
613 emit_d8(cbuf, disp); // Displacement // R/M byte
614 } else {
615 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
616 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
617 emit_d32(cbuf, disp); // Displacement // R/M byte
618 }
619 }
620
621 // rRegI ereg, memory mem) %{ // emit_reg_mem
622 void encode_RegMem(CodeBuffer &cbuf,
623 int reg,
624 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
625 {
626 assert(disp_reloc == relocInfo::none, "cannot have disp");
627 int regenc = reg & 7;
628 int baseenc = base & 7;
629 int indexenc = index & 7;
630
631 // There is no index & no scale, use form without SIB byte
632 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
633 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
634 if (disp == 0 && base != RBP_enc && base != R13_enc) {
635 emit_rm(cbuf, 0x0, regenc, baseenc); // *
636 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
637 // If 8-bit displacement, mode 0x1
638 emit_rm(cbuf, 0x1, regenc, baseenc); // *
639 emit_d8(cbuf, disp);
640 } else {
641 // If 32-bit displacement
642 if (base == -1) { // Special flag for absolute address
643 emit_rm(cbuf, 0x0, regenc, 0x5); // *
644 if (disp_reloc != relocInfo::none) {
645 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
646 } else {
647 emit_d32(cbuf, disp);
648 }
649 } else {
650 // Normal base + offset
651 emit_rm(cbuf, 0x2, regenc, baseenc); // *
652 if (disp_reloc != relocInfo::none) {
653 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
654 } else {
655 emit_d32(cbuf, disp);
656 }
657 }
658 }
659 } else {
660 // Else, encode with the SIB byte
661 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
662 if (disp == 0 && base != RBP_enc && base != R13_enc) {
663 // If no displacement
664 emit_rm(cbuf, 0x0, regenc, 0x4); // *
665 emit_rm(cbuf, scale, indexenc, baseenc);
666 } else {
667 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
668 // If 8-bit displacement, mode 0x1
669 emit_rm(cbuf, 0x1, regenc, 0x4); // *
670 emit_rm(cbuf, scale, indexenc, baseenc);
671 emit_d8(cbuf, disp);
672 } else {
673 // If 32-bit displacement
674 if (base == 0x04 ) {
675 emit_rm(cbuf, 0x2, regenc, 0x4);
676 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
677 } else {
678 emit_rm(cbuf, 0x2, regenc, 0x4);
679 emit_rm(cbuf, scale, indexenc, baseenc); // *
680 }
681 if (disp_reloc != relocInfo::none) {
682 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
683 } else {
684 emit_d32(cbuf, disp);
685 }
686 }
687 }
688 }
689 }
690
691 // This could be in MacroAssembler but it's fairly C2 specific
692 void emit_cmpfp_fixup(MacroAssembler& _masm) {
693 Label exit;
694 __ jccb(Assembler::noParity, exit);
695 __ pushf();
696 //
697 // comiss/ucomiss instructions set ZF,PF,CF flags and
698 // zero OF,AF,SF for NaN values.
699 // Fixup flags by zeroing ZF,PF so that compare of NaN
700 // values returns 'less than' result (CF is set).
701 // Leave the rest of flags unchanged.
702 //
703 // 7 6 5 4 3 2 1 0
704 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
705 // 0 0 1 0 1 0 1 1 (0x2B)
706 //
707 __ andq(Address(rsp, 0), 0xffffff2b);
708 __ popf();
709 __ bind(exit);
710 }
711
712 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
713 Label done;
714 __ movl(dst, -1);
715 __ jcc(Assembler::parity, done);
716 __ jcc(Assembler::below, done);
717 __ setb(Assembler::notEqual, dst);
718 __ movzbl(dst, dst);
719 __ bind(done);
720 }
721
722 // Math.min() # Math.max()
723 // --------------------------
724 // ucomis[s/d] #
725 // ja -> b # a
726 // jp -> NaN # NaN
727 // jb -> a # b
728 // je #
729 // |-jz -> a | b # a & b
730 // | -> a #
731 void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
732 XMMRegister a, XMMRegister b,
733 XMMRegister xmmt, Register rt,
734 bool min, bool single) {
735
736 Label nan, zero, below, above, done;
737
738 if (single)
739 __ ucomiss(a, b);
740 else
741 __ ucomisd(a, b);
742
743 if (dst->encoding() != (min ? b : a)->encoding())
744 __ jccb(Assembler::above, above); // CF=0 & ZF=0
745 else
746 __ jccb(Assembler::above, done);
747
748 __ jccb(Assembler::parity, nan); // PF=1
749 __ jccb(Assembler::below, below); // CF=1
750
751 // equal
752 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
753 if (single) {
754 __ ucomiss(a, xmmt);
755 __ jccb(Assembler::equal, zero);
756
757 __ movflt(dst, a);
758 __ jmp(done);
759 }
760 else {
761 __ ucomisd(a, xmmt);
762 __ jccb(Assembler::equal, zero);
763
764 __ movdbl(dst, a);
765 __ jmp(done);
766 }
767
768 __ bind(zero);
769 if (min)
770 __ vpor(dst, a, b, Assembler::AVX_128bit);
771 else
772 __ vpand(dst, a, b, Assembler::AVX_128bit);
773
774 __ jmp(done);
775
776 __ bind(above);
777 if (single)
778 __ movflt(dst, min ? b : a);
779 else
780 __ movdbl(dst, min ? b : a);
781
782 __ jmp(done);
783
784 __ bind(nan);
785 if (single) {
786 __ movl(rt, 0x7fc00000); // Float.NaN
787 __ movdl(dst, rt);
788 }
789 else {
790 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
791 __ movdq(dst, rt);
792 }
793 __ jmp(done);
794
795 __ bind(below);
796 if (single)
797 __ movflt(dst, min ? a : b);
798 else
799 __ movdbl(dst, min ? a : b);
800
801 __ bind(done);
802 }
803
804 //=============================================================================
805 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
806
807 int ConstantTable::calculate_table_base_offset() const {
808 return 0; // absolute addressing, no offset
809 }
810
811 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
812 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
813 ShouldNotReachHere();
814 }
815
816 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
817 // Empty encoding
818 }
819
820 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
821 return 0;
822 }
823
824 #ifndef PRODUCT
825 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
826 st->print("# MachConstantBaseNode (empty encoding)");
827 }
828 #endif
829
830
831 //=============================================================================
832 #ifndef PRODUCT
833 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
834 Compile* C = ra_->C;
835
836 int framesize = C->output()->frame_size_in_bytes();
837 int bangsize = C->output()->bang_size_in_bytes();
838 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
839 // Remove wordSize for return addr which is already pushed.
840 framesize -= wordSize;
841
842 if (C->output()->need_stack_bang(bangsize)) {
843 framesize -= wordSize;
844 st->print("# stack bang (%d bytes)", bangsize);
845 st->print("\n\t");
846 st->print("pushq rbp\t# Save rbp");
847 if (PreserveFramePointer) {
848 st->print("\n\t");
849 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
850 }
851 if (framesize) {
852 st->print("\n\t");
853 st->print("subq rsp, #%d\t# Create frame",framesize);
854 }
855 } else {
856 st->print("subq rsp, #%d\t# Create frame",framesize);
857 st->print("\n\t");
858 framesize -= wordSize;
859 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
860 if (PreserveFramePointer) {
861 st->print("\n\t");
862 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
863 if (framesize > 0) {
864 st->print("\n\t");
865 st->print("addq rbp, #%d", framesize);
866 }
867 }
868 }
869
870 if (VerifyStackAtCalls) {
871 st->print("\n\t");
872 framesize -= wordSize;
873 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
874 #ifdef ASSERT
875 st->print("\n\t");
876 st->print("# stack alignment check");
877 #endif
878 }
879 if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
880 st->print("\n\t");
881 st->print("cmpl [r15_thread + #disarmed_offset], #disarmed_value\t");
882 st->print("\n\t");
883 st->print("je fast_entry\t");
884 st->print("\n\t");
885 st->print("call #nmethod_entry_barrier_stub\t");
886 st->print("\n\tfast_entry:");
887 }
888 st->cr();
889 }
890 #endif
891
892 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
893 Compile* C = ra_->C;
894 MacroAssembler _masm(&cbuf);
895
896 if (C->clinit_barrier_on_entry()) {
897 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
898 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
899
900 Label L_skip_barrier;
901 Register klass = rscratch1;
902
903 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
904 __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
905
906 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
907
908 __ bind(L_skip_barrier);
909 }
910
911 __ verified_entry(C);
912 __ bind(*_verified_entry);
913
914 if (C->stub_function() == NULL) {
915 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
916 bs->nmethod_entry_barrier(&_masm);
917 }
918
919 C->output()->set_frame_complete(cbuf.insts_size());
920
921 if (C->has_mach_constant_base_node()) {
922 // NOTE: We set the table base offset here because users might be
923 // emitted before MachConstantBaseNode.
924 ConstantTable& constant_table = C->output()->constant_table();
925 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
926 }
927 }
928
929 int MachPrologNode::reloc() const
930 {
931 return 0; // a large enough number
932 }
933
934 //=============================================================================
935 #ifndef PRODUCT
936 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
937 {
938 Compile* C = ra_->C;
939 if (generate_vzeroupper(C)) {
940 st->print("vzeroupper");
941 st->cr(); st->print("\t");
942 }
943
944 int framesize = C->output()->frame_size_in_bytes();
945 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
946 // Remove word for return adr already pushed
947 // and RBP
948 framesize -= 2*wordSize;
949
950 if (framesize) {
951 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
952 st->print("\t");
953 }
954
955 st->print_cr("popq rbp");
956 if (do_polling() && C->is_method_compilation()) {
957 st->print("\t");
958 st->print_cr("cmpq rsp, poll_offset[r15_thread] \n\t"
959 "ja #safepoint_stub\t"
960 "# Safepoint: poll for GC");
961 }
962 }
963 #endif
964
965 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
966 {
967 Compile* C = ra_->C;
968 MacroAssembler _masm(&cbuf);
969
970 if (generate_vzeroupper(C)) {
971 // Clear upper bits of YMM registers when current compiled code uses
972 // wide vectors to avoid AVX <-> SSE transition penalty during call.
973 __ vzeroupper();
974 }
975
976 // Subtract two words to account for return address and rbp
977 int initial_framesize = C->output()->frame_size_in_bytes() - 2*wordSize;
978 __ remove_frame(initial_framesize, C->needs_stack_repair());
979
980 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
981 __ reserved_stack_check();
982 }
983
984 if (do_polling() && C->is_method_compilation()) {
985 MacroAssembler _masm(&cbuf);
986 Label dummy_label;
987 Label* code_stub = &dummy_label;
988 if (!C->output()->in_scratch_emit_size()) {
989 code_stub = &C->output()->safepoint_poll_table()->add_safepoint(__ offset());
990 }
991 __ relocate(relocInfo::poll_return_type);
992 __ safepoint_poll(*code_stub, r15_thread, true /* at_return */, true /* in_nmethod */);
993 }
994 }
995
996 int MachEpilogNode::reloc() const
997 {
998 return 2; // a large enough number
999 }
1000
1001 const Pipeline* MachEpilogNode::pipeline() const
1002 {
1003 return MachNode::pipeline_class();
1004 }
1005
1006 //=============================================================================
1007
1008 enum RC {
1009 rc_bad,
1010 rc_int,
1011 rc_kreg,
1012 rc_float,
1013 rc_stack
1014 };
1015
1016 static enum RC rc_class(OptoReg::Name reg)
1017 {
1018 if( !OptoReg::is_valid(reg) ) return rc_bad;
1019
1020 if (OptoReg::is_stack(reg)) return rc_stack;
1021
1022 VMReg r = OptoReg::as_VMReg(reg);
1023
1024 if (r->is_Register()) return rc_int;
1025
1026 if (r->is_KRegister()) return rc_kreg;
1027
1028 assert(r->is_XMMRegister(), "must be");
1029 return rc_float;
1030 }
1031
1032 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1033 static void vec_mov_helper(CodeBuffer *cbuf, int src_lo, int dst_lo,
1034 int src_hi, int dst_hi, uint ireg, outputStream* st);
1035
1036 void vec_spill_helper(CodeBuffer *cbuf, bool is_load,
1037 int stack_offset, int reg, uint ireg, outputStream* st);
1038
1039 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1040 int dst_offset, uint ireg, outputStream* st) {
1041 if (cbuf) {
1042 MacroAssembler _masm(cbuf);
1043 switch (ireg) {
1044 case Op_VecS:
1045 __ movq(Address(rsp, -8), rax);
1046 __ movl(rax, Address(rsp, src_offset));
1047 __ movl(Address(rsp, dst_offset), rax);
1048 __ movq(rax, Address(rsp, -8));
1049 break;
1050 case Op_VecD:
1051 __ pushq(Address(rsp, src_offset));
1052 __ popq (Address(rsp, dst_offset));
1053 break;
1054 case Op_VecX:
1055 __ pushq(Address(rsp, src_offset));
1056 __ popq (Address(rsp, dst_offset));
1057 __ pushq(Address(rsp, src_offset+8));
1058 __ popq (Address(rsp, dst_offset+8));
1059 break;
1060 case Op_VecY:
1061 __ vmovdqu(Address(rsp, -32), xmm0);
1062 __ vmovdqu(xmm0, Address(rsp, src_offset));
1063 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1064 __ vmovdqu(xmm0, Address(rsp, -32));
1065 break;
1066 case Op_VecZ:
1067 __ evmovdquq(Address(rsp, -64), xmm0, 2);
1068 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
1069 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
1070 __ evmovdquq(xmm0, Address(rsp, -64), 2);
1071 break;
1072 default:
1073 ShouldNotReachHere();
1074 }
1075 #ifndef PRODUCT
1076 } else {
1077 switch (ireg) {
1078 case Op_VecS:
1079 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1080 "movl rax, [rsp + #%d]\n\t"
1081 "movl [rsp + #%d], rax\n\t"
1082 "movq rax, [rsp - #8]",
1083 src_offset, dst_offset);
1084 break;
1085 case Op_VecD:
1086 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1087 "popq [rsp + #%d]",
1088 src_offset, dst_offset);
1089 break;
1090 case Op_VecX:
1091 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1092 "popq [rsp + #%d]\n\t"
1093 "pushq [rsp + #%d]\n\t"
1094 "popq [rsp + #%d]",
1095 src_offset, dst_offset, src_offset+8, dst_offset+8);
1096 break;
1097 case Op_VecY:
1098 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1099 "vmovdqu xmm0, [rsp + #%d]\n\t"
1100 "vmovdqu [rsp + #%d], xmm0\n\t"
1101 "vmovdqu xmm0, [rsp - #32]",
1102 src_offset, dst_offset);
1103 break;
1104 case Op_VecZ:
1105 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1106 "vmovdqu xmm0, [rsp + #%d]\n\t"
1107 "vmovdqu [rsp + #%d], xmm0\n\t"
1108 "vmovdqu xmm0, [rsp - #64]",
1109 src_offset, dst_offset);
1110 break;
1111 default:
1112 ShouldNotReachHere();
1113 }
1114 #endif
1115 }
1116 }
1117
1118 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1119 PhaseRegAlloc* ra_,
1120 bool do_size,
1121 outputStream* st) const {
1122 assert(cbuf != NULL || st != NULL, "sanity");
1123 // Get registers to move
1124 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1125 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1126 OptoReg::Name dst_second = ra_->get_reg_second(this);
1127 OptoReg::Name dst_first = ra_->get_reg_first(this);
1128
1129 enum RC src_second_rc = rc_class(src_second);
1130 enum RC src_first_rc = rc_class(src_first);
1131 enum RC dst_second_rc = rc_class(dst_second);
1132 enum RC dst_first_rc = rc_class(dst_first);
1133
1134 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1135 "must move at least 1 register" );
1136
1137 if (src_first == dst_first && src_second == dst_second) {
1138 // Self copy, no move
1139 return 0;
1140 }
1141 if (bottom_type()->isa_vect() != NULL && bottom_type()->isa_vectmask() == NULL) {
1142 uint ireg = ideal_reg();
1143 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1144 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1145 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1146 // mem -> mem
1147 int src_offset = ra_->reg2offset(src_first);
1148 int dst_offset = ra_->reg2offset(dst_first);
1149 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1150 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1151 vec_mov_helper(cbuf, src_first, dst_first, src_second, dst_second, ireg, st);
1152 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1153 int stack_offset = ra_->reg2offset(dst_first);
1154 vec_spill_helper(cbuf, false, stack_offset, src_first, ireg, st);
1155 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1156 int stack_offset = ra_->reg2offset(src_first);
1157 vec_spill_helper(cbuf, true, stack_offset, dst_first, ireg, st);
1158 } else {
1159 ShouldNotReachHere();
1160 }
1161 return 0;
1162 }
1163 if (src_first_rc == rc_stack) {
1164 // mem ->
1165 if (dst_first_rc == rc_stack) {
1166 // mem -> mem
1167 assert(src_second != dst_first, "overlap");
1168 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1169 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1170 // 64-bit
1171 int src_offset = ra_->reg2offset(src_first);
1172 int dst_offset = ra_->reg2offset(dst_first);
1173 if (cbuf) {
1174 MacroAssembler _masm(cbuf);
1175 __ pushq(Address(rsp, src_offset));
1176 __ popq (Address(rsp, dst_offset));
1177 #ifndef PRODUCT
1178 } else {
1179 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1180 "popq [rsp + #%d]",
1181 src_offset, dst_offset);
1182 #endif
1183 }
1184 } else {
1185 // 32-bit
1186 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1187 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1188 // No pushl/popl, so:
1189 int src_offset = ra_->reg2offset(src_first);
1190 int dst_offset = ra_->reg2offset(dst_first);
1191 if (cbuf) {
1192 MacroAssembler _masm(cbuf);
1193 __ movq(Address(rsp, -8), rax);
1194 __ movl(rax, Address(rsp, src_offset));
1195 __ movl(Address(rsp, dst_offset), rax);
1196 __ movq(rax, Address(rsp, -8));
1197 #ifndef PRODUCT
1198 } else {
1199 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1200 "movl rax, [rsp + #%d]\n\t"
1201 "movl [rsp + #%d], rax\n\t"
1202 "movq rax, [rsp - #8]",
1203 src_offset, dst_offset);
1204 #endif
1205 }
1206 }
1207 return 0;
1208 } else if (dst_first_rc == rc_int) {
1209 // mem -> gpr
1210 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1211 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1212 // 64-bit
1213 int offset = ra_->reg2offset(src_first);
1214 if (cbuf) {
1215 MacroAssembler _masm(cbuf);
1216 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1217 #ifndef PRODUCT
1218 } else {
1219 st->print("movq %s, [rsp + #%d]\t# spill",
1220 Matcher::regName[dst_first],
1221 offset);
1222 #endif
1223 }
1224 } else {
1225 // 32-bit
1226 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1227 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1228 int offset = ra_->reg2offset(src_first);
1229 if (cbuf) {
1230 MacroAssembler _masm(cbuf);
1231 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1232 #ifndef PRODUCT
1233 } else {
1234 st->print("movl %s, [rsp + #%d]\t# spill",
1235 Matcher::regName[dst_first],
1236 offset);
1237 #endif
1238 }
1239 }
1240 return 0;
1241 } else if (dst_first_rc == rc_float) {
1242 // mem-> xmm
1243 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1244 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1245 // 64-bit
1246 int offset = ra_->reg2offset(src_first);
1247 if (cbuf) {
1248 MacroAssembler _masm(cbuf);
1249 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1250 #ifndef PRODUCT
1251 } else {
1252 st->print("%s %s, [rsp + #%d]\t# spill",
1253 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1254 Matcher::regName[dst_first],
1255 offset);
1256 #endif
1257 }
1258 } else {
1259 // 32-bit
1260 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1261 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1262 int offset = ra_->reg2offset(src_first);
1263 if (cbuf) {
1264 MacroAssembler _masm(cbuf);
1265 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1266 #ifndef PRODUCT
1267 } else {
1268 st->print("movss %s, [rsp + #%d]\t# spill",
1269 Matcher::regName[dst_first],
1270 offset);
1271 #endif
1272 }
1273 }
1274 return 0;
1275 } else if (dst_first_rc == rc_kreg) {
1276 // mem -> kreg
1277 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1278 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1279 // 64-bit
1280 int offset = ra_->reg2offset(src_first);
1281 if (cbuf) {
1282 MacroAssembler _masm(cbuf);
1283 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1284 #ifndef PRODUCT
1285 } else {
1286 st->print("kmovq %s, [rsp + #%d]\t# spill",
1287 Matcher::regName[dst_first],
1288 offset);
1289 #endif
1290 }
1291 }
1292 return 0;
1293 }
1294 } else if (src_first_rc == rc_int) {
1295 // gpr ->
1296 if (dst_first_rc == rc_stack) {
1297 // gpr -> mem
1298 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1299 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1300 // 64-bit
1301 int offset = ra_->reg2offset(dst_first);
1302 if (cbuf) {
1303 MacroAssembler _masm(cbuf);
1304 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1305 #ifndef PRODUCT
1306 } else {
1307 st->print("movq [rsp + #%d], %s\t# spill",
1308 offset,
1309 Matcher::regName[src_first]);
1310 #endif
1311 }
1312 } else {
1313 // 32-bit
1314 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1315 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1316 int offset = ra_->reg2offset(dst_first);
1317 if (cbuf) {
1318 MacroAssembler _masm(cbuf);
1319 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1320 #ifndef PRODUCT
1321 } else {
1322 st->print("movl [rsp + #%d], %s\t# spill",
1323 offset,
1324 Matcher::regName[src_first]);
1325 #endif
1326 }
1327 }
1328 return 0;
1329 } else if (dst_first_rc == rc_int) {
1330 // gpr -> gpr
1331 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1332 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1333 // 64-bit
1334 if (cbuf) {
1335 MacroAssembler _masm(cbuf);
1336 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1337 as_Register(Matcher::_regEncode[src_first]));
1338 #ifndef PRODUCT
1339 } else {
1340 st->print("movq %s, %s\t# spill",
1341 Matcher::regName[dst_first],
1342 Matcher::regName[src_first]);
1343 #endif
1344 }
1345 return 0;
1346 } else {
1347 // 32-bit
1348 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1349 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1350 if (cbuf) {
1351 MacroAssembler _masm(cbuf);
1352 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1353 as_Register(Matcher::_regEncode[src_first]));
1354 #ifndef PRODUCT
1355 } else {
1356 st->print("movl %s, %s\t# spill",
1357 Matcher::regName[dst_first],
1358 Matcher::regName[src_first]);
1359 #endif
1360 }
1361 return 0;
1362 }
1363 } else if (dst_first_rc == rc_float) {
1364 // gpr -> xmm
1365 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1366 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1367 // 64-bit
1368 if (cbuf) {
1369 MacroAssembler _masm(cbuf);
1370 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1371 #ifndef PRODUCT
1372 } else {
1373 st->print("movdq %s, %s\t# spill",
1374 Matcher::regName[dst_first],
1375 Matcher::regName[src_first]);
1376 #endif
1377 }
1378 } else {
1379 // 32-bit
1380 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1381 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1382 if (cbuf) {
1383 MacroAssembler _masm(cbuf);
1384 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1385 #ifndef PRODUCT
1386 } else {
1387 st->print("movdl %s, %s\t# spill",
1388 Matcher::regName[dst_first],
1389 Matcher::regName[src_first]);
1390 #endif
1391 }
1392 }
1393 return 0;
1394 } else if (dst_first_rc == rc_kreg) {
1395 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1396 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1397 // 64-bit
1398 if (cbuf) {
1399 MacroAssembler _masm(cbuf);
1400 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1401 #ifndef PRODUCT
1402 } else {
1403 st->print("kmovq %s, %s\t# spill",
1404 Matcher::regName[dst_first],
1405 Matcher::regName[src_first]);
1406 #endif
1407 }
1408 }
1409 Unimplemented();
1410 return 0;
1411 }
1412 } else if (src_first_rc == rc_float) {
1413 // xmm ->
1414 if (dst_first_rc == rc_stack) {
1415 // xmm -> mem
1416 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1417 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1418 // 64-bit
1419 int offset = ra_->reg2offset(dst_first);
1420 if (cbuf) {
1421 MacroAssembler _masm(cbuf);
1422 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1423 #ifndef PRODUCT
1424 } else {
1425 st->print("movsd [rsp + #%d], %s\t# spill",
1426 offset,
1427 Matcher::regName[src_first]);
1428 #endif
1429 }
1430 } else {
1431 // 32-bit
1432 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1433 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1434 int offset = ra_->reg2offset(dst_first);
1435 if (cbuf) {
1436 MacroAssembler _masm(cbuf);
1437 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1438 #ifndef PRODUCT
1439 } else {
1440 st->print("movss [rsp + #%d], %s\t# spill",
1441 offset,
1442 Matcher::regName[src_first]);
1443 #endif
1444 }
1445 }
1446 return 0;
1447 } else if (dst_first_rc == rc_int) {
1448 // xmm -> gpr
1449 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1450 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1451 // 64-bit
1452 if (cbuf) {
1453 MacroAssembler _masm(cbuf);
1454 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1455 #ifndef PRODUCT
1456 } else {
1457 st->print("movdq %s, %s\t# spill",
1458 Matcher::regName[dst_first],
1459 Matcher::regName[src_first]);
1460 #endif
1461 }
1462 } else {
1463 // 32-bit
1464 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1465 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1466 if (cbuf) {
1467 MacroAssembler _masm(cbuf);
1468 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1469 #ifndef PRODUCT
1470 } else {
1471 st->print("movdl %s, %s\t# spill",
1472 Matcher::regName[dst_first],
1473 Matcher::regName[src_first]);
1474 #endif
1475 }
1476 }
1477 return 0;
1478 } else if (dst_first_rc == rc_float) {
1479 // xmm -> xmm
1480 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1481 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1482 // 64-bit
1483 if (cbuf) {
1484 MacroAssembler _masm(cbuf);
1485 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1486 #ifndef PRODUCT
1487 } else {
1488 st->print("%s %s, %s\t# spill",
1489 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1490 Matcher::regName[dst_first],
1491 Matcher::regName[src_first]);
1492 #endif
1493 }
1494 } else {
1495 // 32-bit
1496 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1497 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1498 if (cbuf) {
1499 MacroAssembler _masm(cbuf);
1500 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1501 #ifndef PRODUCT
1502 } else {
1503 st->print("%s %s, %s\t# spill",
1504 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1505 Matcher::regName[dst_first],
1506 Matcher::regName[src_first]);
1507 #endif
1508 }
1509 }
1510 return 0;
1511 } else if (dst_first_rc == rc_kreg) {
1512 assert(false, "Illegal spilling");
1513 return 0;
1514 }
1515 } else if (src_first_rc == rc_kreg) {
1516 if (dst_first_rc == rc_stack) {
1517 // mem -> kreg
1518 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1519 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1520 // 64-bit
1521 int offset = ra_->reg2offset(dst_first);
1522 if (cbuf) {
1523 MacroAssembler _masm(cbuf);
1524 __ kmov(Address(rsp, offset), as_KRegister(Matcher::_regEncode[src_first]));
1525 #ifndef PRODUCT
1526 } else {
1527 st->print("kmovq [rsp + #%d] , %s\t# spill",
1528 offset,
1529 Matcher::regName[src_first]);
1530 #endif
1531 }
1532 }
1533 return 0;
1534 } else if (dst_first_rc == rc_int) {
1535 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1536 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1537 // 64-bit
1538 if (cbuf) {
1539 MacroAssembler _masm(cbuf);
1540 __ kmov(as_Register(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1541 #ifndef PRODUCT
1542 } else {
1543 st->print("kmovq %s, %s\t# spill",
1544 Matcher::regName[dst_first],
1545 Matcher::regName[src_first]);
1546 #endif
1547 }
1548 }
1549 Unimplemented();
1550 return 0;
1551 } else if (dst_first_rc == rc_kreg) {
1552 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1553 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1554 // 64-bit
1555 if (cbuf) {
1556 MacroAssembler _masm(cbuf);
1557 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1558 #ifndef PRODUCT
1559 } else {
1560 st->print("kmovq %s, %s\t# spill",
1561 Matcher::regName[dst_first],
1562 Matcher::regName[src_first]);
1563 #endif
1564 }
1565 }
1566 return 0;
1567 } else if (dst_first_rc == rc_float) {
1568 assert(false, "Illegal spill");
1569 return 0;
1570 }
1571 }
1572
1573 assert(0," foo ");
1574 Unimplemented();
1575 return 0;
1576 }
1577
1578 #ifndef PRODUCT
1579 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1580 implementation(NULL, ra_, false, st);
1581 }
1582 #endif
1583
1584 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1585 implementation(&cbuf, ra_, false, NULL);
1586 }
1587
1588 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1589 return MachNode::size(ra_);
1590 }
1591
1592 //=============================================================================
1593 #ifndef PRODUCT
1594 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1595 {
1596 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1597 int reg = ra_->get_reg_first(this);
1598 st->print("leaq %s, [rsp + #%d]\t# box lock",
1599 Matcher::regName[reg], offset);
1600 }
1601 #endif
1602
1603 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1604 {
1605 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1606 int reg = ra_->get_encode(this);
1607 if (offset >= 0x80) {
1608 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1609 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1610 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1611 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1612 emit_d32(cbuf, offset);
1613 } else {
1614 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1615 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1616 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1617 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1618 emit_d8(cbuf, offset);
1619 }
1620 }
1621
1622 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1623 {
1624 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1625 return (offset < 0x80) ? 5 : 8; // REX
1626 }
1627
1628 //=============================================================================
1629 #ifndef PRODUCT
1630 void MachVEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1631 {
1632 st->print_cr("MachVEPNode");
1633 }
1634 #endif
1635
1636 void MachVEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1637 {
1638 MacroAssembler _masm(&cbuf);
1639 if (!_verified) {
1640 uint insts_size = cbuf.insts_size();
1641 if (UseCompressedClassPointers) {
1642 __ load_klass(rscratch1, j_rarg0, rscratch2);
1643 __ cmpptr(rax, rscratch1);
1644 } else {
1645 __ cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1646 }
1647 __ jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1648 } else {
1649 // Unpack inline type args passed as oop and then jump to
1650 // the verified entry point (skipping the unverified entry).
1651 int sp_inc = __ unpack_inline_args(ra_->C, _receiver_only);
1652 // Emit code for verified entry and save increment for stack repair on return
1653 __ verified_entry(ra_->C, sp_inc);
1654 __ jmp(*_verified_entry);
1655 }
1656 }
1657
1658 //=============================================================================
1659 #ifndef PRODUCT
1660 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1661 {
1662 if (UseCompressedClassPointers) {
1663 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1664 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1665 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1666 } else {
1667 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1668 "# Inline cache check");
1669 }
1670 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1671 st->print_cr("\tnop\t# nops to align entry point");
1672 }
1673 #endif
1674
1675 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1676 {
1677 MacroAssembler masm(&cbuf);
1678 uint insts_size = cbuf.insts_size();
1679 if (UseCompressedClassPointers) {
1680 masm.load_klass(rscratch1, j_rarg0, rscratch2);
1681 masm.cmpptr(rax, rscratch1);
1682 } else {
1683 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1684 }
1685
1686 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1687
1688 /* WARNING these NOPs are critical so that verified entry point is properly
1689 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1690 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1691 if (OptoBreakpoint) {
1692 // Leave space for int3
1693 nops_cnt -= 1;
1694 }
1695 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1696 if (nops_cnt > 0)
1697 masm.nop(nops_cnt);
1698 }
1699
1700 //=============================================================================
1701
1702 const bool Matcher::supports_vector_calling_convention(void) {
1703 if (EnableVectorSupport && UseVectorStubs) {
1704 return true;
1705 }
1706 return false;
1707 }
1708
1709 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1710 assert(EnableVectorSupport && UseVectorStubs, "sanity");
1711 int lo = XMM0_num;
1712 int hi = XMM0b_num;
1713 if (ideal_reg == Op_VecX) hi = XMM0d_num;
1714 else if (ideal_reg == Op_VecY) hi = XMM0h_num;
1715 else if (ideal_reg == Op_VecZ) hi = XMM0p_num;
1716 return OptoRegPair(hi, lo);
1717 }
1718
1719 // Is this branch offset short enough that a short branch can be used?
1720 //
1721 // NOTE: If the platform does not provide any short branch variants, then
1722 // this method should return false for offset 0.
1723 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1724 // The passed offset is relative to address of the branch.
1725 // On 86 a branch displacement is calculated relative to address
1726 // of a next instruction.
1727 offset -= br_size;
1728
1729 // the short version of jmpConUCF2 contains multiple branches,
1730 // making the reach slightly less
1731 if (rule == jmpConUCF2_rule)
1732 return (-126 <= offset && offset <= 125);
1733 return (-128 <= offset && offset <= 127);
1734 }
1735
1736 // Return whether or not this register is ever used as an argument.
1737 // This function is used on startup to build the trampoline stubs in
1738 // generateOptoStub. Registers not mentioned will be killed by the VM
1739 // call in the trampoline, and arguments in those registers not be
1740 // available to the callee.
1741 bool Matcher::can_be_java_arg(int reg)
1742 {
1743 return
1744 reg == RDI_num || reg == RDI_H_num ||
1745 reg == RSI_num || reg == RSI_H_num ||
1746 reg == RDX_num || reg == RDX_H_num ||
1747 reg == RCX_num || reg == RCX_H_num ||
1748 reg == R8_num || reg == R8_H_num ||
1749 reg == R9_num || reg == R9_H_num ||
1750 reg == R12_num || reg == R12_H_num ||
1751 reg == XMM0_num || reg == XMM0b_num ||
1752 reg == XMM1_num || reg == XMM1b_num ||
1753 reg == XMM2_num || reg == XMM2b_num ||
1754 reg == XMM3_num || reg == XMM3b_num ||
1755 reg == XMM4_num || reg == XMM4b_num ||
1756 reg == XMM5_num || reg == XMM5b_num ||
1757 reg == XMM6_num || reg == XMM6b_num ||
1758 reg == XMM7_num || reg == XMM7b_num;
1759 }
1760
1761 bool Matcher::is_spillable_arg(int reg)
1762 {
1763 return can_be_java_arg(reg);
1764 }
1765
1766 uint Matcher::int_pressure_limit()
1767 {
1768 return (INTPRESSURE == -1) ? _INT_REG_mask.Size() : INTPRESSURE;
1769 }
1770
1771 uint Matcher::float_pressure_limit()
1772 {
1773 // After experiment around with different values, the following default threshold
1774 // works best for LCM's register pressure scheduling on x64.
1775 uint dec_count = VM_Version::supports_evex() ? 4 : 2;
1776 uint default_float_pressure_threshold = _FLOAT_REG_mask.Size() - dec_count;
1777 return (FLOATPRESSURE == -1) ? default_float_pressure_threshold : FLOATPRESSURE;
1778 }
1779
1780 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1781 // In 64 bit mode a code which use multiply when
1782 // devisor is constant is faster than hardware
1783 // DIV instruction (it uses MulHiL).
1784 return false;
1785 }
1786
1787 // Register for DIVI projection of divmodI
1788 RegMask Matcher::divI_proj_mask() {
1789 return INT_RAX_REG_mask();
1790 }
1791
1792 // Register for MODI projection of divmodI
1793 RegMask Matcher::modI_proj_mask() {
1794 return INT_RDX_REG_mask();
1795 }
1796
1797 // Register for DIVL projection of divmodL
1798 RegMask Matcher::divL_proj_mask() {
1799 return LONG_RAX_REG_mask();
1800 }
1801
1802 // Register for MODL projection of divmodL
1803 RegMask Matcher::modL_proj_mask() {
1804 return LONG_RDX_REG_mask();
1805 }
1806
1807 // Register for saving SP into on method handle invokes. Not used on x86_64.
1808 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1809 return NO_REG_mask();
1810 }
1811
1812 %}
1813
1814 //----------ENCODING BLOCK-----------------------------------------------------
1815 // This block specifies the encoding classes used by the compiler to
1816 // output byte streams. Encoding classes are parameterized macros
1817 // used by Machine Instruction Nodes in order to generate the bit
1818 // encoding of the instruction. Operands specify their base encoding
1819 // interface with the interface keyword. There are currently
1820 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1821 // COND_INTER. REG_INTER causes an operand to generate a function
1822 // which returns its register number when queried. CONST_INTER causes
1823 // an operand to generate a function which returns the value of the
1824 // constant when queried. MEMORY_INTER causes an operand to generate
1825 // four functions which return the Base Register, the Index Register,
1826 // the Scale Value, and the Offset Value of the operand when queried.
1827 // COND_INTER causes an operand to generate six functions which return
1828 // the encoding code (ie - encoding bits for the instruction)
1829 // associated with each basic boolean condition for a conditional
1830 // instruction.
1831 //
1832 // Instructions specify two basic values for encoding. Again, a
1833 // function is available to check if the constant displacement is an
1834 // oop. They use the ins_encode keyword to specify their encoding
1835 // classes (which must be a sequence of enc_class names, and their
1836 // parameters, specified in the encoding block), and they use the
1837 // opcode keyword to specify, in order, their primary, secondary, and
1838 // tertiary opcode. Only the opcode sections which a particular
1839 // instruction needs for encoding need to be specified.
1840 encode %{
1841 // Build emit functions for each basic byte or larger field in the
1842 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1843 // from C++ code in the enc_class source block. Emit functions will
1844 // live in the main source block for now. In future, we can
1845 // generalize this by adding a syntax that specifies the sizes of
1846 // fields in an order, so that the adlc can build the emit functions
1847 // automagically
1848
1849 // Emit primary opcode
1850 enc_class OpcP
1851 %{
1852 emit_opcode(cbuf, $primary);
1853 %}
1854
1855 // Emit secondary opcode
1856 enc_class OpcS
1857 %{
1858 emit_opcode(cbuf, $secondary);
1859 %}
1860
1861 // Emit tertiary opcode
1862 enc_class OpcT
1863 %{
1864 emit_opcode(cbuf, $tertiary);
1865 %}
1866
1867 // Emit opcode directly
1868 enc_class Opcode(immI d8)
1869 %{
1870 emit_opcode(cbuf, $d8$$constant);
1871 %}
1872
1873 // Emit size prefix
1874 enc_class SizePrefix
1875 %{
1876 emit_opcode(cbuf, 0x66);
1877 %}
1878
1879 enc_class reg(rRegI reg)
1880 %{
1881 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1882 %}
1883
1884 enc_class reg_reg(rRegI dst, rRegI src)
1885 %{
1886 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1887 %}
1888
1889 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1890 %{
1891 emit_opcode(cbuf, $opcode$$constant);
1892 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1893 %}
1894
1895 enc_class cdql_enc(no_rax_rdx_RegI div)
1896 %{
1897 // Full implementation of Java idiv and irem; checks for
1898 // special case as described in JVM spec., p.243 & p.271.
1899 //
1900 // normal case special case
1901 //
1902 // input : rax: dividend min_int
1903 // reg: divisor -1
1904 //
1905 // output: rax: quotient (= rax idiv reg) min_int
1906 // rdx: remainder (= rax irem reg) 0
1907 //
1908 // Code sequnce:
1909 //
1910 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1911 // 5: 75 07/08 jne e <normal>
1912 // 7: 33 d2 xor %edx,%edx
1913 // [div >= 8 -> offset + 1]
1914 // [REX_B]
1915 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1916 // c: 74 03/04 je 11 <done>
1917 // 000000000000000e <normal>:
1918 // e: 99 cltd
1919 // [div >= 8 -> offset + 1]
1920 // [REX_B]
1921 // f: f7 f9 idiv $div
1922 // 0000000000000011 <done>:
1923 MacroAssembler _masm(&cbuf);
1924 Label normal;
1925 Label done;
1926
1927 // cmp $0x80000000,%eax
1928 __ cmp(as_Register(RAX_enc), 0x80000000);
1929
1930 // jne e <normal>
1931 __ jccb(Assembler::notEqual, normal);
1932
1933 // xor %edx,%edx
1934 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1935
1936 // cmp $0xffffffffffffffff,%ecx
1937 __ cmpl($div$$Register, -1);
1938
1939 // je 11 <done>
1940 __ jccb(Assembler::equal, done);
1941
1942 // <normal>
1943 // cltd
1944 __ bind(normal);
1945 __ cdql();
1946
1947 // idivl
1948 // <done>
1949 __ idivl($div$$Register);
1950 __ bind(done);
1951 %}
1952
1953 enc_class cdqq_enc(no_rax_rdx_RegL div)
1954 %{
1955 // Full implementation of Java ldiv and lrem; checks for
1956 // special case as described in JVM spec., p.243 & p.271.
1957 //
1958 // normal case special case
1959 //
1960 // input : rax: dividend min_long
1961 // reg: divisor -1
1962 //
1963 // output: rax: quotient (= rax idiv reg) min_long
1964 // rdx: remainder (= rax irem reg) 0
1965 //
1966 // Code sequnce:
1967 //
1968 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1969 // 7: 00 00 80
1970 // a: 48 39 d0 cmp %rdx,%rax
1971 // d: 75 08 jne 17 <normal>
1972 // f: 33 d2 xor %edx,%edx
1973 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1974 // 15: 74 05 je 1c <done>
1975 // 0000000000000017 <normal>:
1976 // 17: 48 99 cqto
1977 // 19: 48 f7 f9 idiv $div
1978 // 000000000000001c <done>:
1979 MacroAssembler _masm(&cbuf);
1980 Label normal;
1981 Label done;
1982
1983 // mov $0x8000000000000000,%rdx
1984 __ mov64(as_Register(RDX_enc), 0x8000000000000000);
1985
1986 // cmp %rdx,%rax
1987 __ cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
1988
1989 // jne 17 <normal>
1990 __ jccb(Assembler::notEqual, normal);
1991
1992 // xor %edx,%edx
1993 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1994
1995 // cmp $0xffffffffffffffff,$div
1996 __ cmpq($div$$Register, -1);
1997
1998 // je 1e <done>
1999 __ jccb(Assembler::equal, done);
2000
2001 // <normal>
2002 // cqto
2003 __ bind(normal);
2004 __ cdqq();
2005
2006 // idivq (note: must be emitted by the user of this rule)
2007 // <done>
2008 __ idivq($div$$Register);
2009 __ bind(done);
2010 %}
2011
2012 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
2013 enc_class OpcSE(immI imm)
2014 %{
2015 // Emit primary opcode and set sign-extend bit
2016 // Check for 8-bit immediate, and set sign extend bit in opcode
2017 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2018 emit_opcode(cbuf, $primary | 0x02);
2019 } else {
2020 // 32-bit immediate
2021 emit_opcode(cbuf, $primary);
2022 }
2023 %}
2024
2025 enc_class OpcSErm(rRegI dst, immI imm)
2026 %{
2027 // OpcSEr/m
2028 int dstenc = $dst$$reg;
2029 if (dstenc >= 8) {
2030 emit_opcode(cbuf, Assembler::REX_B);
2031 dstenc -= 8;
2032 }
2033 // Emit primary opcode and set sign-extend bit
2034 // Check for 8-bit immediate, and set sign extend bit in opcode
2035 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2036 emit_opcode(cbuf, $primary | 0x02);
2037 } else {
2038 // 32-bit immediate
2039 emit_opcode(cbuf, $primary);
2040 }
2041 // Emit r/m byte with secondary opcode, after primary opcode.
2042 emit_rm(cbuf, 0x3, $secondary, dstenc);
2043 %}
2044
2045 enc_class OpcSErm_wide(rRegL dst, immI imm)
2046 %{
2047 // OpcSEr/m
2048 int dstenc = $dst$$reg;
2049 if (dstenc < 8) {
2050 emit_opcode(cbuf, Assembler::REX_W);
2051 } else {
2052 emit_opcode(cbuf, Assembler::REX_WB);
2053 dstenc -= 8;
2054 }
2055 // Emit primary opcode and set sign-extend bit
2056 // Check for 8-bit immediate, and set sign extend bit in opcode
2057 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2058 emit_opcode(cbuf, $primary | 0x02);
2059 } else {
2060 // 32-bit immediate
2061 emit_opcode(cbuf, $primary);
2062 }
2063 // Emit r/m byte with secondary opcode, after primary opcode.
2064 emit_rm(cbuf, 0x3, $secondary, dstenc);
2065 %}
2066
2067 enc_class Con8or32(immI imm)
2068 %{
2069 // Check for 8-bit immediate, and set sign extend bit in opcode
2070 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2071 $$$emit8$imm$$constant;
2072 } else {
2073 // 32-bit immediate
2074 $$$emit32$imm$$constant;
2075 }
2076 %}
2077
2078 enc_class opc2_reg(rRegI dst)
2079 %{
2080 // BSWAP
2081 emit_cc(cbuf, $secondary, $dst$$reg);
2082 %}
2083
2084 enc_class opc3_reg(rRegI dst)
2085 %{
2086 // BSWAP
2087 emit_cc(cbuf, $tertiary, $dst$$reg);
2088 %}
2089
2090 enc_class reg_opc(rRegI div)
2091 %{
2092 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2093 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2094 %}
2095
2096 enc_class enc_cmov(cmpOp cop)
2097 %{
2098 // CMOV
2099 $$$emit8$primary;
2100 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2101 %}
2102
2103 enc_class enc_PartialSubtypeCheck()
2104 %{
2105 Register Rrdi = as_Register(RDI_enc); // result register
2106 Register Rrax = as_Register(RAX_enc); // super class
2107 Register Rrcx = as_Register(RCX_enc); // killed
2108 Register Rrsi = as_Register(RSI_enc); // sub class
2109 Label miss;
2110 const bool set_cond_codes = true;
2111
2112 MacroAssembler _masm(&cbuf);
2113 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2114 NULL, &miss,
2115 /*set_cond_codes:*/ true);
2116 if ($primary) {
2117 __ xorptr(Rrdi, Rrdi);
2118 }
2119 __ bind(miss);
2120 %}
2121
2122 enc_class clear_avx %{
2123 debug_only(int off0 = cbuf.insts_size());
2124 if (generate_vzeroupper(Compile::current())) {
2125 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
2126 // Clear upper bits of YMM registers when current compiled code uses
2127 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2128 MacroAssembler _masm(&cbuf);
2129 __ vzeroupper();
2130 }
2131 debug_only(int off1 = cbuf.insts_size());
2132 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2133 %}
2134
2135 enc_class Java_To_Runtime(method meth) %{
2136 // No relocation needed
2137 MacroAssembler _masm(&cbuf);
2138 __ mov64(r10, (int64_t) $meth$$method);
2139 __ call(r10);
2140 %}
2141
2142 enc_class Java_To_Interpreter(method meth)
2143 %{
2144 // CALL Java_To_Interpreter
2145 // This is the instruction starting address for relocation info.
2146 cbuf.set_insts_mark();
2147 $$$emit8$primary;
2148 // CALL directly to the runtime
2149 emit_d32_reloc(cbuf,
2150 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2151 runtime_call_Relocation::spec(),
2152 RELOC_DISP32);
2153 %}
2154
2155 enc_class Java_Static_Call(method meth)
2156 %{
2157 // JAVA STATIC CALL
2158 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2159 // determine who we intended to call.
2160 cbuf.set_insts_mark();
2161 $$$emit8$primary;
2162
2163 if (!_method) {
2164 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2165 runtime_call_Relocation::spec(),
2166 RELOC_DISP32);
2167 } else {
2168 int method_index = resolved_method_index(cbuf);
2169 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2170 : static_call_Relocation::spec(method_index);
2171 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2172 rspec, RELOC_DISP32);
2173 // Emit stubs for static call.
2174 address mark = cbuf.insts_mark();
2175 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2176 if (stub == NULL) {
2177 ciEnv::current()->record_failure("CodeCache is full");
2178 return;
2179 }
2180 }
2181 %}
2182
2183 enc_class Java_Dynamic_Call(method meth) %{
2184 MacroAssembler _masm(&cbuf);
2185 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2186 %}
2187
2188 enc_class Java_Compiled_Call(method meth)
2189 %{
2190 // JAVA COMPILED CALL
2191 int disp = in_bytes(Method:: from_compiled_offset());
2192
2193 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2194 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2195
2196 // callq *disp(%rax)
2197 cbuf.set_insts_mark();
2198 $$$emit8$primary;
2199 if (disp < 0x80) {
2200 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2201 emit_d8(cbuf, disp); // Displacement
2202 } else {
2203 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2204 emit_d32(cbuf, disp); // Displacement
2205 }
2206 %}
2207
2208 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2209 %{
2210 // SAL, SAR, SHR
2211 int dstenc = $dst$$reg;
2212 if (dstenc >= 8) {
2213 emit_opcode(cbuf, Assembler::REX_B);
2214 dstenc -= 8;
2215 }
2216 $$$emit8$primary;
2217 emit_rm(cbuf, 0x3, $secondary, dstenc);
2218 $$$emit8$shift$$constant;
2219 %}
2220
2221 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2222 %{
2223 // SAL, SAR, SHR
2224 int dstenc = $dst$$reg;
2225 if (dstenc < 8) {
2226 emit_opcode(cbuf, Assembler::REX_W);
2227 } else {
2228 emit_opcode(cbuf, Assembler::REX_WB);
2229 dstenc -= 8;
2230 }
2231 $$$emit8$primary;
2232 emit_rm(cbuf, 0x3, $secondary, dstenc);
2233 $$$emit8$shift$$constant;
2234 %}
2235
2236 enc_class load_immI(rRegI dst, immI src)
2237 %{
2238 int dstenc = $dst$$reg;
2239 if (dstenc >= 8) {
2240 emit_opcode(cbuf, Assembler::REX_B);
2241 dstenc -= 8;
2242 }
2243 emit_opcode(cbuf, 0xB8 | dstenc);
2244 $$$emit32$src$$constant;
2245 %}
2246
2247 enc_class load_immL(rRegL dst, immL src)
2248 %{
2249 int dstenc = $dst$$reg;
2250 if (dstenc < 8) {
2251 emit_opcode(cbuf, Assembler::REX_W);
2252 } else {
2253 emit_opcode(cbuf, Assembler::REX_WB);
2254 dstenc -= 8;
2255 }
2256 emit_opcode(cbuf, 0xB8 | dstenc);
2257 emit_d64(cbuf, $src$$constant);
2258 %}
2259
2260 enc_class load_immUL32(rRegL dst, immUL32 src)
2261 %{
2262 // same as load_immI, but this time we care about zeroes in the high word
2263 int dstenc = $dst$$reg;
2264 if (dstenc >= 8) {
2265 emit_opcode(cbuf, Assembler::REX_B);
2266 dstenc -= 8;
2267 }
2268 emit_opcode(cbuf, 0xB8 | dstenc);
2269 $$$emit32$src$$constant;
2270 %}
2271
2272 enc_class load_immL32(rRegL dst, immL32 src)
2273 %{
2274 int dstenc = $dst$$reg;
2275 if (dstenc < 8) {
2276 emit_opcode(cbuf, Assembler::REX_W);
2277 } else {
2278 emit_opcode(cbuf, Assembler::REX_WB);
2279 dstenc -= 8;
2280 }
2281 emit_opcode(cbuf, 0xC7);
2282 emit_rm(cbuf, 0x03, 0x00, dstenc);
2283 $$$emit32$src$$constant;
2284 %}
2285
2286 enc_class load_immP31(rRegP dst, immP32 src)
2287 %{
2288 // same as load_immI, but this time we care about zeroes in the high word
2289 int dstenc = $dst$$reg;
2290 if (dstenc >= 8) {
2291 emit_opcode(cbuf, Assembler::REX_B);
2292 dstenc -= 8;
2293 }
2294 emit_opcode(cbuf, 0xB8 | dstenc);
2295 $$$emit32$src$$constant;
2296 %}
2297
2298 enc_class load_immP(rRegP dst, immP src)
2299 %{
2300 int dstenc = $dst$$reg;
2301 if (dstenc < 8) {
2302 emit_opcode(cbuf, Assembler::REX_W);
2303 } else {
2304 emit_opcode(cbuf, Assembler::REX_WB);
2305 dstenc -= 8;
2306 }
2307 emit_opcode(cbuf, 0xB8 | dstenc);
2308 // This next line should be generated from ADLC
2309 if ($src->constant_reloc() != relocInfo::none) {
2310 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2311 } else {
2312 emit_d64(cbuf, $src$$constant);
2313 }
2314 %}
2315
2316 enc_class Con32(immI src)
2317 %{
2318 // Output immediate
2319 $$$emit32$src$$constant;
2320 %}
2321
2322 enc_class Con32F_as_bits(immF src)
2323 %{
2324 // Output Float immediate bits
2325 jfloat jf = $src$$constant;
2326 jint jf_as_bits = jint_cast(jf);
2327 emit_d32(cbuf, jf_as_bits);
2328 %}
2329
2330 enc_class Con16(immI src)
2331 %{
2332 // Output immediate
2333 $$$emit16$src$$constant;
2334 %}
2335
2336 // How is this different from Con32??? XXX
2337 enc_class Con_d32(immI src)
2338 %{
2339 emit_d32(cbuf,$src$$constant);
2340 %}
2341
2342 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2343 // Output immediate memory reference
2344 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2345 emit_d32(cbuf, 0x00);
2346 %}
2347
2348 enc_class lock_prefix()
2349 %{
2350 emit_opcode(cbuf, 0xF0); // lock
2351 %}
2352
2353 enc_class REX_mem(memory mem)
2354 %{
2355 if ($mem$$base >= 8) {
2356 if ($mem$$index < 8) {
2357 emit_opcode(cbuf, Assembler::REX_B);
2358 } else {
2359 emit_opcode(cbuf, Assembler::REX_XB);
2360 }
2361 } else {
2362 if ($mem$$index >= 8) {
2363 emit_opcode(cbuf, Assembler::REX_X);
2364 }
2365 }
2366 %}
2367
2368 enc_class REX_mem_wide(memory mem)
2369 %{
2370 if ($mem$$base >= 8) {
2371 if ($mem$$index < 8) {
2372 emit_opcode(cbuf, Assembler::REX_WB);
2373 } else {
2374 emit_opcode(cbuf, Assembler::REX_WXB);
2375 }
2376 } else {
2377 if ($mem$$index < 8) {
2378 emit_opcode(cbuf, Assembler::REX_W);
2379 } else {
2380 emit_opcode(cbuf, Assembler::REX_WX);
2381 }
2382 }
2383 %}
2384
2385 // for byte regs
2386 enc_class REX_breg(rRegI reg)
2387 %{
2388 if ($reg$$reg >= 4) {
2389 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2390 }
2391 %}
2392
2393 // for byte regs
2394 enc_class REX_reg_breg(rRegI dst, rRegI src)
2395 %{
2396 if ($dst$$reg < 8) {
2397 if ($src$$reg >= 4) {
2398 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2399 }
2400 } else {
2401 if ($src$$reg < 8) {
2402 emit_opcode(cbuf, Assembler::REX_R);
2403 } else {
2404 emit_opcode(cbuf, Assembler::REX_RB);
2405 }
2406 }
2407 %}
2408
2409 // for byte regs
2410 enc_class REX_breg_mem(rRegI reg, memory mem)
2411 %{
2412 if ($reg$$reg < 8) {
2413 if ($mem$$base < 8) {
2414 if ($mem$$index >= 8) {
2415 emit_opcode(cbuf, Assembler::REX_X);
2416 } else if ($reg$$reg >= 4) {
2417 emit_opcode(cbuf, Assembler::REX);
2418 }
2419 } else {
2420 if ($mem$$index < 8) {
2421 emit_opcode(cbuf, Assembler::REX_B);
2422 } else {
2423 emit_opcode(cbuf, Assembler::REX_XB);
2424 }
2425 }
2426 } else {
2427 if ($mem$$base < 8) {
2428 if ($mem$$index < 8) {
2429 emit_opcode(cbuf, Assembler::REX_R);
2430 } else {
2431 emit_opcode(cbuf, Assembler::REX_RX);
2432 }
2433 } else {
2434 if ($mem$$index < 8) {
2435 emit_opcode(cbuf, Assembler::REX_RB);
2436 } else {
2437 emit_opcode(cbuf, Assembler::REX_RXB);
2438 }
2439 }
2440 }
2441 %}
2442
2443 enc_class REX_reg(rRegI reg)
2444 %{
2445 if ($reg$$reg >= 8) {
2446 emit_opcode(cbuf, Assembler::REX_B);
2447 }
2448 %}
2449
2450 enc_class REX_reg_wide(rRegI reg)
2451 %{
2452 if ($reg$$reg < 8) {
2453 emit_opcode(cbuf, Assembler::REX_W);
2454 } else {
2455 emit_opcode(cbuf, Assembler::REX_WB);
2456 }
2457 %}
2458
2459 enc_class REX_reg_reg(rRegI dst, rRegI src)
2460 %{
2461 if ($dst$$reg < 8) {
2462 if ($src$$reg >= 8) {
2463 emit_opcode(cbuf, Assembler::REX_B);
2464 }
2465 } else {
2466 if ($src$$reg < 8) {
2467 emit_opcode(cbuf, Assembler::REX_R);
2468 } else {
2469 emit_opcode(cbuf, Assembler::REX_RB);
2470 }
2471 }
2472 %}
2473
2474 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2475 %{
2476 if ($dst$$reg < 8) {
2477 if ($src$$reg < 8) {
2478 emit_opcode(cbuf, Assembler::REX_W);
2479 } else {
2480 emit_opcode(cbuf, Assembler::REX_WB);
2481 }
2482 } else {
2483 if ($src$$reg < 8) {
2484 emit_opcode(cbuf, Assembler::REX_WR);
2485 } else {
2486 emit_opcode(cbuf, Assembler::REX_WRB);
2487 }
2488 }
2489 %}
2490
2491 enc_class REX_reg_mem(rRegI reg, memory mem)
2492 %{
2493 if ($reg$$reg < 8) {
2494 if ($mem$$base < 8) {
2495 if ($mem$$index >= 8) {
2496 emit_opcode(cbuf, Assembler::REX_X);
2497 }
2498 } else {
2499 if ($mem$$index < 8) {
2500 emit_opcode(cbuf, Assembler::REX_B);
2501 } else {
2502 emit_opcode(cbuf, Assembler::REX_XB);
2503 }
2504 }
2505 } else {
2506 if ($mem$$base < 8) {
2507 if ($mem$$index < 8) {
2508 emit_opcode(cbuf, Assembler::REX_R);
2509 } else {
2510 emit_opcode(cbuf, Assembler::REX_RX);
2511 }
2512 } else {
2513 if ($mem$$index < 8) {
2514 emit_opcode(cbuf, Assembler::REX_RB);
2515 } else {
2516 emit_opcode(cbuf, Assembler::REX_RXB);
2517 }
2518 }
2519 }
2520 %}
2521
2522 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2523 %{
2524 if ($reg$$reg < 8) {
2525 if ($mem$$base < 8) {
2526 if ($mem$$index < 8) {
2527 emit_opcode(cbuf, Assembler::REX_W);
2528 } else {
2529 emit_opcode(cbuf, Assembler::REX_WX);
2530 }
2531 } else {
2532 if ($mem$$index < 8) {
2533 emit_opcode(cbuf, Assembler::REX_WB);
2534 } else {
2535 emit_opcode(cbuf, Assembler::REX_WXB);
2536 }
2537 }
2538 } else {
2539 if ($mem$$base < 8) {
2540 if ($mem$$index < 8) {
2541 emit_opcode(cbuf, Assembler::REX_WR);
2542 } else {
2543 emit_opcode(cbuf, Assembler::REX_WRX);
2544 }
2545 } else {
2546 if ($mem$$index < 8) {
2547 emit_opcode(cbuf, Assembler::REX_WRB);
2548 } else {
2549 emit_opcode(cbuf, Assembler::REX_WRXB);
2550 }
2551 }
2552 }
2553 %}
2554
2555 enc_class reg_mem(rRegI ereg, memory mem)
2556 %{
2557 // High registers handle in encode_RegMem
2558 int reg = $ereg$$reg;
2559 int base = $mem$$base;
2560 int index = $mem$$index;
2561 int scale = $mem$$scale;
2562 int disp = $mem$$disp;
2563 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2564
2565 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2566 %}
2567
2568 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2569 %{
2570 int rm_byte_opcode = $rm_opcode$$constant;
2571
2572 // High registers handle in encode_RegMem
2573 int base = $mem$$base;
2574 int index = $mem$$index;
2575 int scale = $mem$$scale;
2576 int displace = $mem$$disp;
2577
2578 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2579 // working with static
2580 // globals
2581 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2582 disp_reloc);
2583 %}
2584
2585 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2586 %{
2587 int reg_encoding = $dst$$reg;
2588 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2589 int index = 0x04; // 0x04 indicates no index
2590 int scale = 0x00; // 0x00 indicates no scale
2591 int displace = $src1$$constant; // 0x00 indicates no displacement
2592 relocInfo::relocType disp_reloc = relocInfo::none;
2593 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2594 disp_reloc);
2595 %}
2596
2597 enc_class neg_reg(rRegI dst)
2598 %{
2599 int dstenc = $dst$$reg;
2600 if (dstenc >= 8) {
2601 emit_opcode(cbuf, Assembler::REX_B);
2602 dstenc -= 8;
2603 }
2604 // NEG $dst
2605 emit_opcode(cbuf, 0xF7);
2606 emit_rm(cbuf, 0x3, 0x03, dstenc);
2607 %}
2608
2609 enc_class neg_reg_wide(rRegI dst)
2610 %{
2611 int dstenc = $dst$$reg;
2612 if (dstenc < 8) {
2613 emit_opcode(cbuf, Assembler::REX_W);
2614 } else {
2615 emit_opcode(cbuf, Assembler::REX_WB);
2616 dstenc -= 8;
2617 }
2618 // NEG $dst
2619 emit_opcode(cbuf, 0xF7);
2620 emit_rm(cbuf, 0x3, 0x03, dstenc);
2621 %}
2622
2623 enc_class setLT_reg(rRegI dst)
2624 %{
2625 int dstenc = $dst$$reg;
2626 if (dstenc >= 8) {
2627 emit_opcode(cbuf, Assembler::REX_B);
2628 dstenc -= 8;
2629 } else if (dstenc >= 4) {
2630 emit_opcode(cbuf, Assembler::REX);
2631 }
2632 // SETLT $dst
2633 emit_opcode(cbuf, 0x0F);
2634 emit_opcode(cbuf, 0x9C);
2635 emit_rm(cbuf, 0x3, 0x0, dstenc);
2636 %}
2637
2638 enc_class setNZ_reg(rRegI dst)
2639 %{
2640 int dstenc = $dst$$reg;
2641 if (dstenc >= 8) {
2642 emit_opcode(cbuf, Assembler::REX_B);
2643 dstenc -= 8;
2644 } else if (dstenc >= 4) {
2645 emit_opcode(cbuf, Assembler::REX);
2646 }
2647 // SETNZ $dst
2648 emit_opcode(cbuf, 0x0F);
2649 emit_opcode(cbuf, 0x95);
2650 emit_rm(cbuf, 0x3, 0x0, dstenc);
2651 %}
2652
2653
2654 // Compare the lonogs and set -1, 0, or 1 into dst
2655 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2656 %{
2657 int src1enc = $src1$$reg;
2658 int src2enc = $src2$$reg;
2659 int dstenc = $dst$$reg;
2660
2661 // cmpq $src1, $src2
2662 if (src1enc < 8) {
2663 if (src2enc < 8) {
2664 emit_opcode(cbuf, Assembler::REX_W);
2665 } else {
2666 emit_opcode(cbuf, Assembler::REX_WB);
2667 }
2668 } else {
2669 if (src2enc < 8) {
2670 emit_opcode(cbuf, Assembler::REX_WR);
2671 } else {
2672 emit_opcode(cbuf, Assembler::REX_WRB);
2673 }
2674 }
2675 emit_opcode(cbuf, 0x3B);
2676 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2677
2678 // movl $dst, -1
2679 if (dstenc >= 8) {
2680 emit_opcode(cbuf, Assembler::REX_B);
2681 }
2682 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2683 emit_d32(cbuf, -1);
2684
2685 // jl,s done
2686 emit_opcode(cbuf, 0x7C);
2687 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2688
2689 // setne $dst
2690 if (dstenc >= 4) {
2691 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2692 }
2693 emit_opcode(cbuf, 0x0F);
2694 emit_opcode(cbuf, 0x95);
2695 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2696
2697 // movzbl $dst, $dst
2698 if (dstenc >= 4) {
2699 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2700 }
2701 emit_opcode(cbuf, 0x0F);
2702 emit_opcode(cbuf, 0xB6);
2703 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2704 %}
2705
2706 enc_class Push_ResultXD(regD dst) %{
2707 MacroAssembler _masm(&cbuf);
2708 __ fstp_d(Address(rsp, 0));
2709 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2710 __ addptr(rsp, 8);
2711 %}
2712
2713 enc_class Push_SrcXD(regD src) %{
2714 MacroAssembler _masm(&cbuf);
2715 __ subptr(rsp, 8);
2716 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2717 __ fld_d(Address(rsp, 0));
2718 %}
2719
2720
2721 enc_class enc_rethrow()
2722 %{
2723 cbuf.set_insts_mark();
2724 emit_opcode(cbuf, 0xE9); // jmp entry
2725 emit_d32_reloc(cbuf,
2726 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2727 runtime_call_Relocation::spec(),
2728 RELOC_DISP32);
2729 %}
2730
2731 %}
2732
2733
2734
2735 //----------FRAME--------------------------------------------------------------
2736 // Definition of frame structure and management information.
2737 //
2738 // S T A C K L A Y O U T Allocators stack-slot number
2739 // | (to get allocators register number
2740 // G Owned by | | v add OptoReg::stack0())
2741 // r CALLER | |
2742 // o | +--------+ pad to even-align allocators stack-slot
2743 // w V | pad0 | numbers; owned by CALLER
2744 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2745 // h ^ | in | 5
2746 // | | args | 4 Holes in incoming args owned by SELF
2747 // | | | | 3
2748 // | | +--------+
2749 // V | | old out| Empty on Intel, window on Sparc
2750 // | old |preserve| Must be even aligned.
2751 // | SP-+--------+----> Matcher::_old_SP, even aligned
2752 // | | in | 3 area for Intel ret address
2753 // Owned by |preserve| Empty on Sparc.
2754 // SELF +--------+
2755 // | | pad2 | 2 pad to align old SP
2756 // | +--------+ 1
2757 // | | locks | 0
2758 // | +--------+----> OptoReg::stack0(), even aligned
2759 // | | pad1 | 11 pad to align new SP
2760 // | +--------+
2761 // | | | 10
2762 // | | spills | 9 spills
2763 // V | | 8 (pad0 slot for callee)
2764 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2765 // ^ | out | 7
2766 // | | args | 6 Holes in outgoing args owned by CALLEE
2767 // Owned by +--------+
2768 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2769 // | new |preserve| Must be even-aligned.
2770 // | SP-+--------+----> Matcher::_new_SP, even aligned
2771 // | | |
2772 //
2773 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2774 // known from SELF's arguments and the Java calling convention.
2775 // Region 6-7 is determined per call site.
2776 // Note 2: If the calling convention leaves holes in the incoming argument
2777 // area, those holes are owned by SELF. Holes in the outgoing area
2778 // are owned by the CALLEE. Holes should not be nessecary in the
2779 // incoming area, as the Java calling convention is completely under
2780 // the control of the AD file. Doubles can be sorted and packed to
2781 // avoid holes. Holes in the outgoing arguments may be nessecary for
2782 // varargs C calling conventions.
2783 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2784 // even aligned with pad0 as needed.
2785 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2786 // region 6-11 is even aligned; it may be padded out more so that
2787 // the region from SP to FP meets the minimum stack alignment.
2788 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2789 // alignment. Region 11, pad1, may be dynamically extended so that
2790 // SP meets the minimum alignment.
2791
2792 frame
2793 %{
2794 // These three registers define part of the calling convention
2795 // between compiled code and the interpreter.
2796 inline_cache_reg(RAX); // Inline Cache Register
2797
2798 // Optional: name the operand used by cisc-spilling to access
2799 // [stack_pointer + offset]
2800 cisc_spilling_operand_name(indOffset32);
2801
2802 // Number of stack slots consumed by locking an object
2803 sync_stack_slots(2);
2804
2805 // Compiled code's Frame Pointer
2806 frame_pointer(RSP);
2807
2808 // Interpreter stores its frame pointer in a register which is
2809 // stored to the stack by I2CAdaptors.
2810 // I2CAdaptors convert from interpreted java to compiled java.
2811 interpreter_frame_pointer(RBP);
2812
2813 // Stack alignment requirement
2814 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2815
2816 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2817 // for calls to C. Supports the var-args backing area for register parms.
2818 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2819
2820 // The after-PROLOG location of the return address. Location of
2821 // return address specifies a type (REG or STACK) and a number
2822 // representing the register number (i.e. - use a register name) or
2823 // stack slot.
2824 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2825 // Otherwise, it is above the locks and verification slot and alignment word
2826 return_addr(STACK - 2 +
2827 align_up((Compile::current()->in_preserve_stack_slots() +
2828 Compile::current()->fixed_slots()),
2829 stack_alignment_in_slots()));
2830
2831 // Location of compiled Java return values. Same as C for now.
2832 return_value
2833 %{
2834 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2835 "only return normal values");
2836
2837 static const int lo[Op_RegL + 1] = {
2838 0,
2839 0,
2840 RAX_num, // Op_RegN
2841 RAX_num, // Op_RegI
2842 RAX_num, // Op_RegP
2843 XMM0_num, // Op_RegF
2844 XMM0_num, // Op_RegD
2845 RAX_num // Op_RegL
2846 };
2847 static const int hi[Op_RegL + 1] = {
2848 0,
2849 0,
2850 OptoReg::Bad, // Op_RegN
2851 OptoReg::Bad, // Op_RegI
2852 RAX_H_num, // Op_RegP
2853 OptoReg::Bad, // Op_RegF
2854 XMM0b_num, // Op_RegD
2855 RAX_H_num // Op_RegL
2856 };
2857 // Excluded flags and vector registers.
2858 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type");
2859 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2860 %}
2861 %}
2862
2863 //----------ATTRIBUTES---------------------------------------------------------
2864 //----------Operand Attributes-------------------------------------------------
2865 op_attrib op_cost(0); // Required cost attribute
2866
2867 //----------Instruction Attributes---------------------------------------------
2868 ins_attrib ins_cost(100); // Required cost attribute
2869 ins_attrib ins_size(8); // Required size attribute (in bits)
2870 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2871 // a non-matching short branch variant
2872 // of some long branch?
2873 ins_attrib ins_alignment(1); // Required alignment attribute (must
2874 // be a power of 2) specifies the
2875 // alignment that some part of the
2876 // instruction (not necessarily the
2877 // start) requires. If > 1, a
2878 // compute_padding() function must be
2879 // provided for the instruction
2880
2881 //----------OPERANDS-----------------------------------------------------------
2882 // Operand definitions must precede instruction definitions for correct parsing
2883 // in the ADLC because operands constitute user defined types which are used in
2884 // instruction definitions.
2885
2886 //----------Simple Operands----------------------------------------------------
2887 // Immediate Operands
2888 // Integer Immediate
2889 operand immI()
2890 %{
2891 match(ConI);
2892
2893 op_cost(10);
2894 format %{ %}
2895 interface(CONST_INTER);
2896 %}
2897
2898 // Constant for test vs zero
2899 operand immI_0()
2900 %{
2901 predicate(n->get_int() == 0);
2902 match(ConI);
2903
2904 op_cost(0);
2905 format %{ %}
2906 interface(CONST_INTER);
2907 %}
2908
2909 // Constant for increment
2910 operand immI_1()
2911 %{
2912 predicate(n->get_int() == 1);
2913 match(ConI);
2914
2915 op_cost(0);
2916 format %{ %}
2917 interface(CONST_INTER);
2918 %}
2919
2920 // Constant for decrement
2921 operand immI_M1()
2922 %{
2923 predicate(n->get_int() == -1);
2924 match(ConI);
2925
2926 op_cost(0);
2927 format %{ %}
2928 interface(CONST_INTER);
2929 %}
2930
2931 operand immI_2()
2932 %{
2933 predicate(n->get_int() == 2);
2934 match(ConI);
2935
2936 op_cost(0);
2937 format %{ %}
2938 interface(CONST_INTER);
2939 %}
2940
2941 operand immI_4()
2942 %{
2943 predicate(n->get_int() == 4);
2944 match(ConI);
2945
2946 op_cost(0);
2947 format %{ %}
2948 interface(CONST_INTER);
2949 %}
2950
2951 operand immI_8()
2952 %{
2953 predicate(n->get_int() == 8);
2954 match(ConI);
2955
2956 op_cost(0);
2957 format %{ %}
2958 interface(CONST_INTER);
2959 %}
2960
2961 // Valid scale values for addressing modes
2962 operand immI2()
2963 %{
2964 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2965 match(ConI);
2966
2967 format %{ %}
2968 interface(CONST_INTER);
2969 %}
2970
2971 operand immU7()
2972 %{
2973 predicate((0 <= n->get_int()) && (n->get_int() <= 0x7F));
2974 match(ConI);
2975
2976 op_cost(5);
2977 format %{ %}
2978 interface(CONST_INTER);
2979 %}
2980
2981 operand immI8()
2982 %{
2983 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2984 match(ConI);
2985
2986 op_cost(5);
2987 format %{ %}
2988 interface(CONST_INTER);
2989 %}
2990
2991 operand immU8()
2992 %{
2993 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2994 match(ConI);
2995
2996 op_cost(5);
2997 format %{ %}
2998 interface(CONST_INTER);
2999 %}
3000
3001 operand immI16()
3002 %{
3003 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
3004 match(ConI);
3005
3006 op_cost(10);
3007 format %{ %}
3008 interface(CONST_INTER);
3009 %}
3010
3011 // Int Immediate non-negative
3012 operand immU31()
3013 %{
3014 predicate(n->get_int() >= 0);
3015 match(ConI);
3016
3017 op_cost(0);
3018 format %{ %}
3019 interface(CONST_INTER);
3020 %}
3021
3022 // Constant for long shifts
3023 operand immI_32()
3024 %{
3025 predicate( n->get_int() == 32 );
3026 match(ConI);
3027
3028 op_cost(0);
3029 format %{ %}
3030 interface(CONST_INTER);
3031 %}
3032
3033 // Constant for long shifts
3034 operand immI_64()
3035 %{
3036 predicate( n->get_int() == 64 );
3037 match(ConI);
3038
3039 op_cost(0);
3040 format %{ %}
3041 interface(CONST_INTER);
3042 %}
3043
3044 // Pointer Immediate
3045 operand immP()
3046 %{
3047 match(ConP);
3048
3049 op_cost(10);
3050 format %{ %}
3051 interface(CONST_INTER);
3052 %}
3053
3054 // NULL Pointer Immediate
3055 operand immP0()
3056 %{
3057 predicate(n->get_ptr() == 0);
3058 match(ConP);
3059
3060 op_cost(5);
3061 format %{ %}
3062 interface(CONST_INTER);
3063 %}
3064
3065 // Pointer Immediate
3066 operand immN() %{
3067 match(ConN);
3068
3069 op_cost(10);
3070 format %{ %}
3071 interface(CONST_INTER);
3072 %}
3073
3074 operand immNKlass() %{
3075 match(ConNKlass);
3076
3077 op_cost(10);
3078 format %{ %}
3079 interface(CONST_INTER);
3080 %}
3081
3082 // NULL Pointer Immediate
3083 operand immN0() %{
3084 predicate(n->get_narrowcon() == 0);
3085 match(ConN);
3086
3087 op_cost(5);
3088 format %{ %}
3089 interface(CONST_INTER);
3090 %}
3091
3092 operand immP31()
3093 %{
3094 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3095 && (n->get_ptr() >> 31) == 0);
3096 match(ConP);
3097
3098 op_cost(5);
3099 format %{ %}
3100 interface(CONST_INTER);
3101 %}
3102
3103
3104 // Long Immediate
3105 operand immL()
3106 %{
3107 match(ConL);
3108
3109 op_cost(20);
3110 format %{ %}
3111 interface(CONST_INTER);
3112 %}
3113
3114 // Long Immediate 8-bit
3115 operand immL8()
3116 %{
3117 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3118 match(ConL);
3119
3120 op_cost(5);
3121 format %{ %}
3122 interface(CONST_INTER);
3123 %}
3124
3125 // Long Immediate 32-bit unsigned
3126 operand immUL32()
3127 %{
3128 predicate(n->get_long() == (unsigned int) (n->get_long()));
3129 match(ConL);
3130
3131 op_cost(10);
3132 format %{ %}
3133 interface(CONST_INTER);
3134 %}
3135
3136 // Long Immediate 32-bit signed
3137 operand immL32()
3138 %{
3139 predicate(n->get_long() == (int) (n->get_long()));
3140 match(ConL);
3141
3142 op_cost(15);
3143 format %{ %}
3144 interface(CONST_INTER);
3145 %}
3146
3147 operand immL_Pow2()
3148 %{
3149 predicate(is_power_of_2((julong)n->get_long()));
3150 match(ConL);
3151
3152 op_cost(15);
3153 format %{ %}
3154 interface(CONST_INTER);
3155 %}
3156
3157 operand immL_NotPow2()
3158 %{
3159 predicate(is_power_of_2((julong)~n->get_long()));
3160 match(ConL);
3161
3162 op_cost(15);
3163 format %{ %}
3164 interface(CONST_INTER);
3165 %}
3166
3167 // Long Immediate zero
3168 operand immL0()
3169 %{
3170 predicate(n->get_long() == 0L);
3171 match(ConL);
3172
3173 op_cost(10);
3174 format %{ %}
3175 interface(CONST_INTER);
3176 %}
3177
3178 // Constant for increment
3179 operand immL1()
3180 %{
3181 predicate(n->get_long() == 1);
3182 match(ConL);
3183
3184 format %{ %}
3185 interface(CONST_INTER);
3186 %}
3187
3188 // Constant for decrement
3189 operand immL_M1()
3190 %{
3191 predicate(n->get_long() == -1);
3192 match(ConL);
3193
3194 format %{ %}
3195 interface(CONST_INTER);
3196 %}
3197
3198 // Long Immediate: the value 10
3199 operand immL10()
3200 %{
3201 predicate(n->get_long() == 10);
3202 match(ConL);
3203
3204 format %{ %}
3205 interface(CONST_INTER);
3206 %}
3207
3208 // Long immediate from 0 to 127.
3209 // Used for a shorter form of long mul by 10.
3210 operand immL_127()
3211 %{
3212 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3213 match(ConL);
3214
3215 op_cost(10);
3216 format %{ %}
3217 interface(CONST_INTER);
3218 %}
3219
3220 // Long Immediate: low 32-bit mask
3221 operand immL_32bits()
3222 %{
3223 predicate(n->get_long() == 0xFFFFFFFFL);
3224 match(ConL);
3225 op_cost(20);
3226
3227 format %{ %}
3228 interface(CONST_INTER);
3229 %}
3230
3231 // Int Immediate: 2^n-1, postive
3232 operand immI_Pow2M1()
3233 %{
3234 predicate((n->get_int() > 0)
3235 && is_power_of_2(n->get_int() + 1));
3236 match(ConI);
3237
3238 op_cost(20);
3239 format %{ %}
3240 interface(CONST_INTER);
3241 %}
3242
3243 // Float Immediate zero
3244 operand immF0()
3245 %{
3246 predicate(jint_cast(n->getf()) == 0);
3247 match(ConF);
3248
3249 op_cost(5);
3250 format %{ %}
3251 interface(CONST_INTER);
3252 %}
3253
3254 // Float Immediate
3255 operand immF()
3256 %{
3257 match(ConF);
3258
3259 op_cost(15);
3260 format %{ %}
3261 interface(CONST_INTER);
3262 %}
3263
3264 // Double Immediate zero
3265 operand immD0()
3266 %{
3267 predicate(jlong_cast(n->getd()) == 0);
3268 match(ConD);
3269
3270 op_cost(5);
3271 format %{ %}
3272 interface(CONST_INTER);
3273 %}
3274
3275 // Double Immediate
3276 operand immD()
3277 %{
3278 match(ConD);
3279
3280 op_cost(15);
3281 format %{ %}
3282 interface(CONST_INTER);
3283 %}
3284
3285 // Immediates for special shifts (sign extend)
3286
3287 // Constants for increment
3288 operand immI_16()
3289 %{
3290 predicate(n->get_int() == 16);
3291 match(ConI);
3292
3293 format %{ %}
3294 interface(CONST_INTER);
3295 %}
3296
3297 operand immI_24()
3298 %{
3299 predicate(n->get_int() == 24);
3300 match(ConI);
3301
3302 format %{ %}
3303 interface(CONST_INTER);
3304 %}
3305
3306 // Constant for byte-wide masking
3307 operand immI_255()
3308 %{
3309 predicate(n->get_int() == 255);
3310 match(ConI);
3311
3312 format %{ %}
3313 interface(CONST_INTER);
3314 %}
3315
3316 // Constant for short-wide masking
3317 operand immI_65535()
3318 %{
3319 predicate(n->get_int() == 65535);
3320 match(ConI);
3321
3322 format %{ %}
3323 interface(CONST_INTER);
3324 %}
3325
3326 // Constant for byte-wide masking
3327 operand immL_255()
3328 %{
3329 predicate(n->get_long() == 255);
3330 match(ConL);
3331
3332 format %{ %}
3333 interface(CONST_INTER);
3334 %}
3335
3336 // Constant for short-wide masking
3337 operand immL_65535()
3338 %{
3339 predicate(n->get_long() == 65535);
3340 match(ConL);
3341
3342 format %{ %}
3343 interface(CONST_INTER);
3344 %}
3345
3346 operand kReg()
3347 %{
3348 constraint(ALLOC_IN_RC(vectmask_reg));
3349 match(RegVectMask);
3350 format %{%}
3351 interface(REG_INTER);
3352 %}
3353
3354 operand kReg_K1()
3355 %{
3356 constraint(ALLOC_IN_RC(vectmask_reg_K1));
3357 match(RegVectMask);
3358 format %{%}
3359 interface(REG_INTER);
3360 %}
3361
3362 operand kReg_K2()
3363 %{
3364 constraint(ALLOC_IN_RC(vectmask_reg_K2));
3365 match(RegVectMask);
3366 format %{%}
3367 interface(REG_INTER);
3368 %}
3369
3370 // Special Registers
3371 operand kReg_K3()
3372 %{
3373 constraint(ALLOC_IN_RC(vectmask_reg_K3));
3374 match(RegVectMask);
3375 format %{%}
3376 interface(REG_INTER);
3377 %}
3378
3379 operand kReg_K4()
3380 %{
3381 constraint(ALLOC_IN_RC(vectmask_reg_K4));
3382 match(RegVectMask);
3383 format %{%}
3384 interface(REG_INTER);
3385 %}
3386
3387 operand kReg_K5()
3388 %{
3389 constraint(ALLOC_IN_RC(vectmask_reg_K5));
3390 match(RegVectMask);
3391 format %{%}
3392 interface(REG_INTER);
3393 %}
3394
3395 operand kReg_K6()
3396 %{
3397 constraint(ALLOC_IN_RC(vectmask_reg_K6));
3398 match(RegVectMask);
3399 format %{%}
3400 interface(REG_INTER);
3401 %}
3402
3403 // Special Registers
3404 operand kReg_K7()
3405 %{
3406 constraint(ALLOC_IN_RC(vectmask_reg_K7));
3407 match(RegVectMask);
3408 format %{%}
3409 interface(REG_INTER);
3410 %}
3411
3412 // Register Operands
3413 // Integer Register
3414 operand rRegI()
3415 %{
3416 constraint(ALLOC_IN_RC(int_reg));
3417 match(RegI);
3418
3419 match(rax_RegI);
3420 match(rbx_RegI);
3421 match(rcx_RegI);
3422 match(rdx_RegI);
3423 match(rdi_RegI);
3424
3425 format %{ %}
3426 interface(REG_INTER);
3427 %}
3428
3429 // Special Registers
3430 operand rax_RegI()
3431 %{
3432 constraint(ALLOC_IN_RC(int_rax_reg));
3433 match(RegI);
3434 match(rRegI);
3435
3436 format %{ "RAX" %}
3437 interface(REG_INTER);
3438 %}
3439
3440 // Special Registers
3441 operand rbx_RegI()
3442 %{
3443 constraint(ALLOC_IN_RC(int_rbx_reg));
3444 match(RegI);
3445 match(rRegI);
3446
3447 format %{ "RBX" %}
3448 interface(REG_INTER);
3449 %}
3450
3451 operand rcx_RegI()
3452 %{
3453 constraint(ALLOC_IN_RC(int_rcx_reg));
3454 match(RegI);
3455 match(rRegI);
3456
3457 format %{ "RCX" %}
3458 interface(REG_INTER);
3459 %}
3460
3461 operand rdx_RegI()
3462 %{
3463 constraint(ALLOC_IN_RC(int_rdx_reg));
3464 match(RegI);
3465 match(rRegI);
3466
3467 format %{ "RDX" %}
3468 interface(REG_INTER);
3469 %}
3470
3471 operand rdi_RegI()
3472 %{
3473 constraint(ALLOC_IN_RC(int_rdi_reg));
3474 match(RegI);
3475 match(rRegI);
3476
3477 format %{ "RDI" %}
3478 interface(REG_INTER);
3479 %}
3480
3481 operand no_rax_rdx_RegI()
3482 %{
3483 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3484 match(RegI);
3485 match(rbx_RegI);
3486 match(rcx_RegI);
3487 match(rdi_RegI);
3488
3489 format %{ %}
3490 interface(REG_INTER);
3491 %}
3492
3493 // Pointer Register
3494 operand any_RegP()
3495 %{
3496 constraint(ALLOC_IN_RC(any_reg));
3497 match(RegP);
3498 match(rax_RegP);
3499 match(rbx_RegP);
3500 match(rdi_RegP);
3501 match(rsi_RegP);
3502 match(rbp_RegP);
3503 match(r15_RegP);
3504 match(rRegP);
3505
3506 format %{ %}
3507 interface(REG_INTER);
3508 %}
3509
3510 operand rRegP()
3511 %{
3512 constraint(ALLOC_IN_RC(ptr_reg));
3513 match(RegP);
3514 match(rax_RegP);
3515 match(rbx_RegP);
3516 match(rdi_RegP);
3517 match(rsi_RegP);
3518 match(rbp_RegP); // See Q&A below about
3519 match(r15_RegP); // r15_RegP and rbp_RegP.
3520
3521 format %{ %}
3522 interface(REG_INTER);
3523 %}
3524
3525 operand rRegN() %{
3526 constraint(ALLOC_IN_RC(int_reg));
3527 match(RegN);
3528
3529 format %{ %}
3530 interface(REG_INTER);
3531 %}
3532
3533 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3534 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3535 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3536 // The output of an instruction is controlled by the allocator, which respects
3537 // register class masks, not match rules. Unless an instruction mentions
3538 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3539 // by the allocator as an input.
3540 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3541 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3542 // result, RBP is not included in the output of the instruction either.
3543
3544 operand no_rax_RegP()
3545 %{
3546 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3547 match(RegP);
3548 match(rbx_RegP);
3549 match(rsi_RegP);
3550 match(rdi_RegP);
3551
3552 format %{ %}
3553 interface(REG_INTER);
3554 %}
3555
3556 // This operand is not allowed to use RBP even if
3557 // RBP is not used to hold the frame pointer.
3558 operand no_rbp_RegP()
3559 %{
3560 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3561 match(RegP);
3562 match(rbx_RegP);
3563 match(rsi_RegP);
3564 match(rdi_RegP);
3565
3566 format %{ %}
3567 interface(REG_INTER);
3568 %}
3569
3570 operand no_rax_rbx_RegP()
3571 %{
3572 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3573 match(RegP);
3574 match(rsi_RegP);
3575 match(rdi_RegP);
3576
3577 format %{ %}
3578 interface(REG_INTER);
3579 %}
3580
3581 // Special Registers
3582 // Return a pointer value
3583 operand rax_RegP()
3584 %{
3585 constraint(ALLOC_IN_RC(ptr_rax_reg));
3586 match(RegP);
3587 match(rRegP);
3588
3589 format %{ %}
3590 interface(REG_INTER);
3591 %}
3592
3593 // Special Registers
3594 // Return a compressed pointer value
3595 operand rax_RegN()
3596 %{
3597 constraint(ALLOC_IN_RC(int_rax_reg));
3598 match(RegN);
3599 match(rRegN);
3600
3601 format %{ %}
3602 interface(REG_INTER);
3603 %}
3604
3605 // Used in AtomicAdd
3606 operand rbx_RegP()
3607 %{
3608 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3609 match(RegP);
3610 match(rRegP);
3611
3612 format %{ %}
3613 interface(REG_INTER);
3614 %}
3615
3616 operand rsi_RegP()
3617 %{
3618 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3619 match(RegP);
3620 match(rRegP);
3621
3622 format %{ %}
3623 interface(REG_INTER);
3624 %}
3625
3626 operand rbp_RegP()
3627 %{
3628 constraint(ALLOC_IN_RC(ptr_rbp_reg));
3629 match(RegP);
3630 match(rRegP);
3631
3632 format %{ %}
3633 interface(REG_INTER);
3634 %}
3635
3636 // Used in rep stosq
3637 operand rdi_RegP()
3638 %{
3639 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3640 match(RegP);
3641 match(rRegP);
3642
3643 format %{ %}
3644 interface(REG_INTER);
3645 %}
3646
3647 operand r15_RegP()
3648 %{
3649 constraint(ALLOC_IN_RC(ptr_r15_reg));
3650 match(RegP);
3651 match(rRegP);
3652
3653 format %{ %}
3654 interface(REG_INTER);
3655 %}
3656
3657 operand rRegL()
3658 %{
3659 constraint(ALLOC_IN_RC(long_reg));
3660 match(RegL);
3661 match(rax_RegL);
3662 match(rdx_RegL);
3663
3664 format %{ %}
3665 interface(REG_INTER);
3666 %}
3667
3668 // Special Registers
3669 operand no_rax_rdx_RegL()
3670 %{
3671 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3672 match(RegL);
3673 match(rRegL);
3674
3675 format %{ %}
3676 interface(REG_INTER);
3677 %}
3678
3679 operand no_rax_RegL()
3680 %{
3681 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3682 match(RegL);
3683 match(rRegL);
3684 match(rdx_RegL);
3685
3686 format %{ %}
3687 interface(REG_INTER);
3688 %}
3689
3690 operand rax_RegL()
3691 %{
3692 constraint(ALLOC_IN_RC(long_rax_reg));
3693 match(RegL);
3694 match(rRegL);
3695
3696 format %{ "RAX" %}
3697 interface(REG_INTER);
3698 %}
3699
3700 operand rcx_RegL()
3701 %{
3702 constraint(ALLOC_IN_RC(long_rcx_reg));
3703 match(RegL);
3704 match(rRegL);
3705
3706 format %{ %}
3707 interface(REG_INTER);
3708 %}
3709
3710 operand rdx_RegL()
3711 %{
3712 constraint(ALLOC_IN_RC(long_rdx_reg));
3713 match(RegL);
3714 match(rRegL);
3715
3716 format %{ %}
3717 interface(REG_INTER);
3718 %}
3719
3720 // Flags register, used as output of compare instructions
3721 operand rFlagsReg()
3722 %{
3723 constraint(ALLOC_IN_RC(int_flags));
3724 match(RegFlags);
3725
3726 format %{ "RFLAGS" %}
3727 interface(REG_INTER);
3728 %}
3729
3730 // Flags register, used as output of FLOATING POINT compare instructions
3731 operand rFlagsRegU()
3732 %{
3733 constraint(ALLOC_IN_RC(int_flags));
3734 match(RegFlags);
3735
3736 format %{ "RFLAGS_U" %}
3737 interface(REG_INTER);
3738 %}
3739
3740 operand rFlagsRegUCF() %{
3741 constraint(ALLOC_IN_RC(int_flags));
3742 match(RegFlags);
3743 predicate(false);
3744
3745 format %{ "RFLAGS_U_CF" %}
3746 interface(REG_INTER);
3747 %}
3748
3749 // Float register operands
3750 operand regF() %{
3751 constraint(ALLOC_IN_RC(float_reg));
3752 match(RegF);
3753
3754 format %{ %}
3755 interface(REG_INTER);
3756 %}
3757
3758 // Float register operands
3759 operand legRegF() %{
3760 constraint(ALLOC_IN_RC(float_reg_legacy));
3761 match(RegF);
3762
3763 format %{ %}
3764 interface(REG_INTER);
3765 %}
3766
3767 // Float register operands
3768 operand vlRegF() %{
3769 constraint(ALLOC_IN_RC(float_reg_vl));
3770 match(RegF);
3771
3772 format %{ %}
3773 interface(REG_INTER);
3774 %}
3775
3776 // Double register operands
3777 operand regD() %{
3778 constraint(ALLOC_IN_RC(double_reg));
3779 match(RegD);
3780
3781 format %{ %}
3782 interface(REG_INTER);
3783 %}
3784
3785 // Double register operands
3786 operand legRegD() %{
3787 constraint(ALLOC_IN_RC(double_reg_legacy));
3788 match(RegD);
3789
3790 format %{ %}
3791 interface(REG_INTER);
3792 %}
3793
3794 // Double register operands
3795 operand vlRegD() %{
3796 constraint(ALLOC_IN_RC(double_reg_vl));
3797 match(RegD);
3798
3799 format %{ %}
3800 interface(REG_INTER);
3801 %}
3802
3803 //----------Memory Operands----------------------------------------------------
3804 // Direct Memory Operand
3805 // operand direct(immP addr)
3806 // %{
3807 // match(addr);
3808
3809 // format %{ "[$addr]" %}
3810 // interface(MEMORY_INTER) %{
3811 // base(0xFFFFFFFF);
3812 // index(0x4);
3813 // scale(0x0);
3814 // disp($addr);
3815 // %}
3816 // %}
3817
3818 // Indirect Memory Operand
3819 operand indirect(any_RegP reg)
3820 %{
3821 constraint(ALLOC_IN_RC(ptr_reg));
3822 match(reg);
3823
3824 format %{ "[$reg]" %}
3825 interface(MEMORY_INTER) %{
3826 base($reg);
3827 index(0x4);
3828 scale(0x0);
3829 disp(0x0);
3830 %}
3831 %}
3832
3833 // Indirect Memory Plus Short Offset Operand
3834 operand indOffset8(any_RegP reg, immL8 off)
3835 %{
3836 constraint(ALLOC_IN_RC(ptr_reg));
3837 match(AddP reg off);
3838
3839 format %{ "[$reg + $off (8-bit)]" %}
3840 interface(MEMORY_INTER) %{
3841 base($reg);
3842 index(0x4);
3843 scale(0x0);
3844 disp($off);
3845 %}
3846 %}
3847
3848 // Indirect Memory Plus Long Offset Operand
3849 operand indOffset32(any_RegP reg, immL32 off)
3850 %{
3851 constraint(ALLOC_IN_RC(ptr_reg));
3852 match(AddP reg off);
3853
3854 format %{ "[$reg + $off (32-bit)]" %}
3855 interface(MEMORY_INTER) %{
3856 base($reg);
3857 index(0x4);
3858 scale(0x0);
3859 disp($off);
3860 %}
3861 %}
3862
3863 // Indirect Memory Plus Index Register Plus Offset Operand
3864 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3865 %{
3866 constraint(ALLOC_IN_RC(ptr_reg));
3867 match(AddP (AddP reg lreg) off);
3868
3869 op_cost(10);
3870 format %{"[$reg + $off + $lreg]" %}
3871 interface(MEMORY_INTER) %{
3872 base($reg);
3873 index($lreg);
3874 scale(0x0);
3875 disp($off);
3876 %}
3877 %}
3878
3879 // Indirect Memory Plus Index Register Plus Offset Operand
3880 operand indIndex(any_RegP reg, rRegL lreg)
3881 %{
3882 constraint(ALLOC_IN_RC(ptr_reg));
3883 match(AddP reg lreg);
3884
3885 op_cost(10);
3886 format %{"[$reg + $lreg]" %}
3887 interface(MEMORY_INTER) %{
3888 base($reg);
3889 index($lreg);
3890 scale(0x0);
3891 disp(0x0);
3892 %}
3893 %}
3894
3895 // Indirect Memory Times Scale Plus Index Register
3896 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3897 %{
3898 constraint(ALLOC_IN_RC(ptr_reg));
3899 match(AddP reg (LShiftL lreg scale));
3900
3901 op_cost(10);
3902 format %{"[$reg + $lreg << $scale]" %}
3903 interface(MEMORY_INTER) %{
3904 base($reg);
3905 index($lreg);
3906 scale($scale);
3907 disp(0x0);
3908 %}
3909 %}
3910
3911 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3912 %{
3913 constraint(ALLOC_IN_RC(ptr_reg));
3914 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3915 match(AddP reg (LShiftL (ConvI2L idx) scale));
3916
3917 op_cost(10);
3918 format %{"[$reg + pos $idx << $scale]" %}
3919 interface(MEMORY_INTER) %{
3920 base($reg);
3921 index($idx);
3922 scale($scale);
3923 disp(0x0);
3924 %}
3925 %}
3926
3927 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3928 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3929 %{
3930 constraint(ALLOC_IN_RC(ptr_reg));
3931 match(AddP (AddP reg (LShiftL lreg scale)) off);
3932
3933 op_cost(10);
3934 format %{"[$reg + $off + $lreg << $scale]" %}
3935 interface(MEMORY_INTER) %{
3936 base($reg);
3937 index($lreg);
3938 scale($scale);
3939 disp($off);
3940 %}
3941 %}
3942
3943 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3944 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3945 %{
3946 constraint(ALLOC_IN_RC(ptr_reg));
3947 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3948 match(AddP (AddP reg (ConvI2L idx)) off);
3949
3950 op_cost(10);
3951 format %{"[$reg + $off + $idx]" %}
3952 interface(MEMORY_INTER) %{
3953 base($reg);
3954 index($idx);
3955 scale(0x0);
3956 disp($off);
3957 %}
3958 %}
3959
3960 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3961 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3962 %{
3963 constraint(ALLOC_IN_RC(ptr_reg));
3964 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3965 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3966
3967 op_cost(10);
3968 format %{"[$reg + $off + $idx << $scale]" %}
3969 interface(MEMORY_INTER) %{
3970 base($reg);
3971 index($idx);
3972 scale($scale);
3973 disp($off);
3974 %}
3975 %}
3976
3977 // Indirect Narrow Oop Operand
3978 operand indCompressedOop(rRegN reg) %{
3979 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3980 constraint(ALLOC_IN_RC(ptr_reg));
3981 match(DecodeN reg);
3982
3983 op_cost(10);
3984 format %{"[R12 + $reg << 3] (compressed oop addressing)" %}
3985 interface(MEMORY_INTER) %{
3986 base(0xc); // R12
3987 index($reg);
3988 scale(0x3);
3989 disp(0x0);
3990 %}
3991 %}
3992
3993 // Indirect Narrow Oop Plus Offset Operand
3994 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3995 // we can't free r12 even with CompressedOops::base() == NULL.
3996 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3997 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3998 constraint(ALLOC_IN_RC(ptr_reg));
3999 match(AddP (DecodeN reg) off);
4000
4001 op_cost(10);
4002 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
4003 interface(MEMORY_INTER) %{
4004 base(0xc); // R12
4005 index($reg);
4006 scale(0x3);
4007 disp($off);
4008 %}
4009 %}
4010
4011 // Indirect Memory Operand
4012 operand indirectNarrow(rRegN reg)
4013 %{
4014 predicate(CompressedOops::shift() == 0);
4015 constraint(ALLOC_IN_RC(ptr_reg));
4016 match(DecodeN reg);
4017
4018 format %{ "[$reg]" %}
4019 interface(MEMORY_INTER) %{
4020 base($reg);
4021 index(0x4);
4022 scale(0x0);
4023 disp(0x0);
4024 %}
4025 %}
4026
4027 // Indirect Memory Plus Short Offset Operand
4028 operand indOffset8Narrow(rRegN reg, immL8 off)
4029 %{
4030 predicate(CompressedOops::shift() == 0);
4031 constraint(ALLOC_IN_RC(ptr_reg));
4032 match(AddP (DecodeN reg) off);
4033
4034 format %{ "[$reg + $off (8-bit)]" %}
4035 interface(MEMORY_INTER) %{
4036 base($reg);
4037 index(0x4);
4038 scale(0x0);
4039 disp($off);
4040 %}
4041 %}
4042
4043 // Indirect Memory Plus Long Offset Operand
4044 operand indOffset32Narrow(rRegN reg, immL32 off)
4045 %{
4046 predicate(CompressedOops::shift() == 0);
4047 constraint(ALLOC_IN_RC(ptr_reg));
4048 match(AddP (DecodeN reg) off);
4049
4050 format %{ "[$reg + $off (32-bit)]" %}
4051 interface(MEMORY_INTER) %{
4052 base($reg);
4053 index(0x4);
4054 scale(0x0);
4055 disp($off);
4056 %}
4057 %}
4058
4059 // Indirect Memory Plus Index Register Plus Offset Operand
4060 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
4061 %{
4062 predicate(CompressedOops::shift() == 0);
4063 constraint(ALLOC_IN_RC(ptr_reg));
4064 match(AddP (AddP (DecodeN reg) lreg) off);
4065
4066 op_cost(10);
4067 format %{"[$reg + $off + $lreg]" %}
4068 interface(MEMORY_INTER) %{
4069 base($reg);
4070 index($lreg);
4071 scale(0x0);
4072 disp($off);
4073 %}
4074 %}
4075
4076 // Indirect Memory Plus Index Register Plus Offset Operand
4077 operand indIndexNarrow(rRegN reg, rRegL lreg)
4078 %{
4079 predicate(CompressedOops::shift() == 0);
4080 constraint(ALLOC_IN_RC(ptr_reg));
4081 match(AddP (DecodeN reg) lreg);
4082
4083 op_cost(10);
4084 format %{"[$reg + $lreg]" %}
4085 interface(MEMORY_INTER) %{
4086 base($reg);
4087 index($lreg);
4088 scale(0x0);
4089 disp(0x0);
4090 %}
4091 %}
4092
4093 // Indirect Memory Times Scale Plus Index Register
4094 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
4095 %{
4096 predicate(CompressedOops::shift() == 0);
4097 constraint(ALLOC_IN_RC(ptr_reg));
4098 match(AddP (DecodeN reg) (LShiftL lreg scale));
4099
4100 op_cost(10);
4101 format %{"[$reg + $lreg << $scale]" %}
4102 interface(MEMORY_INTER) %{
4103 base($reg);
4104 index($lreg);
4105 scale($scale);
4106 disp(0x0);
4107 %}
4108 %}
4109
4110 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
4111 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
4112 %{
4113 predicate(CompressedOops::shift() == 0);
4114 constraint(ALLOC_IN_RC(ptr_reg));
4115 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
4116
4117 op_cost(10);
4118 format %{"[$reg + $off + $lreg << $scale]" %}
4119 interface(MEMORY_INTER) %{
4120 base($reg);
4121 index($lreg);
4122 scale($scale);
4123 disp($off);
4124 %}
4125 %}
4126
4127 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
4128 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
4129 %{
4130 constraint(ALLOC_IN_RC(ptr_reg));
4131 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
4132 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
4133
4134 op_cost(10);
4135 format %{"[$reg + $off + $idx]" %}
4136 interface(MEMORY_INTER) %{
4137 base($reg);
4138 index($idx);
4139 scale(0x0);
4140 disp($off);
4141 %}
4142 %}
4143
4144 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
4145 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
4146 %{
4147 constraint(ALLOC_IN_RC(ptr_reg));
4148 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
4149 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
4150
4151 op_cost(10);
4152 format %{"[$reg + $off + $idx << $scale]" %}
4153 interface(MEMORY_INTER) %{
4154 base($reg);
4155 index($idx);
4156 scale($scale);
4157 disp($off);
4158 %}
4159 %}
4160
4161 //----------Special Memory Operands--------------------------------------------
4162 // Stack Slot Operand - This operand is used for loading and storing temporary
4163 // values on the stack where a match requires a value to
4164 // flow through memory.
4165 operand stackSlotP(sRegP reg)
4166 %{
4167 constraint(ALLOC_IN_RC(stack_slots));
4168 // No match rule because this operand is only generated in matching
4169
4170 format %{ "[$reg]" %}
4171 interface(MEMORY_INTER) %{
4172 base(0x4); // RSP
4173 index(0x4); // No Index
4174 scale(0x0); // No Scale
4175 disp($reg); // Stack Offset
4176 %}
4177 %}
4178
4179 operand stackSlotI(sRegI reg)
4180 %{
4181 constraint(ALLOC_IN_RC(stack_slots));
4182 // No match rule because this operand is only generated in matching
4183
4184 format %{ "[$reg]" %}
4185 interface(MEMORY_INTER) %{
4186 base(0x4); // RSP
4187 index(0x4); // No Index
4188 scale(0x0); // No Scale
4189 disp($reg); // Stack Offset
4190 %}
4191 %}
4192
4193 operand stackSlotF(sRegF reg)
4194 %{
4195 constraint(ALLOC_IN_RC(stack_slots));
4196 // No match rule because this operand is only generated in matching
4197
4198 format %{ "[$reg]" %}
4199 interface(MEMORY_INTER) %{
4200 base(0x4); // RSP
4201 index(0x4); // No Index
4202 scale(0x0); // No Scale
4203 disp($reg); // Stack Offset
4204 %}
4205 %}
4206
4207 operand stackSlotD(sRegD reg)
4208 %{
4209 constraint(ALLOC_IN_RC(stack_slots));
4210 // No match rule because this operand is only generated in matching
4211
4212 format %{ "[$reg]" %}
4213 interface(MEMORY_INTER) %{
4214 base(0x4); // RSP
4215 index(0x4); // No Index
4216 scale(0x0); // No Scale
4217 disp($reg); // Stack Offset
4218 %}
4219 %}
4220 operand stackSlotL(sRegL reg)
4221 %{
4222 constraint(ALLOC_IN_RC(stack_slots));
4223 // No match rule because this operand is only generated in matching
4224
4225 format %{ "[$reg]" %}
4226 interface(MEMORY_INTER) %{
4227 base(0x4); // RSP
4228 index(0x4); // No Index
4229 scale(0x0); // No Scale
4230 disp($reg); // Stack Offset
4231 %}
4232 %}
4233
4234 //----------Conditional Branch Operands----------------------------------------
4235 // Comparison Op - This is the operation of the comparison, and is limited to
4236 // the following set of codes:
4237 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4238 //
4239 // Other attributes of the comparison, such as unsignedness, are specified
4240 // by the comparison instruction that sets a condition code flags register.
4241 // That result is represented by a flags operand whose subtype is appropriate
4242 // to the unsignedness (etc.) of the comparison.
4243 //
4244 // Later, the instruction which matches both the Comparison Op (a Bool) and
4245 // the flags (produced by the Cmp) specifies the coding of the comparison op
4246 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4247
4248 // Comparision Code
4249 operand cmpOp()
4250 %{
4251 match(Bool);
4252
4253 format %{ "" %}
4254 interface(COND_INTER) %{
4255 equal(0x4, "e");
4256 not_equal(0x5, "ne");
4257 less(0xC, "l");
4258 greater_equal(0xD, "ge");
4259 less_equal(0xE, "le");
4260 greater(0xF, "g");
4261 overflow(0x0, "o");
4262 no_overflow(0x1, "no");
4263 %}
4264 %}
4265
4266 // Comparison Code, unsigned compare. Used by FP also, with
4267 // C2 (unordered) turned into GT or LT already. The other bits
4268 // C0 and C3 are turned into Carry & Zero flags.
4269 operand cmpOpU()
4270 %{
4271 match(Bool);
4272
4273 format %{ "" %}
4274 interface(COND_INTER) %{
4275 equal(0x4, "e");
4276 not_equal(0x5, "ne");
4277 less(0x2, "b");
4278 greater_equal(0x3, "nb");
4279 less_equal(0x6, "be");
4280 greater(0x7, "nbe");
4281 overflow(0x0, "o");
4282 no_overflow(0x1, "no");
4283 %}
4284 %}
4285
4286
4287 // Floating comparisons that don't require any fixup for the unordered case
4288 operand cmpOpUCF() %{
4289 match(Bool);
4290 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4291 n->as_Bool()->_test._test == BoolTest::ge ||
4292 n->as_Bool()->_test._test == BoolTest::le ||
4293 n->as_Bool()->_test._test == BoolTest::gt);
4294 format %{ "" %}
4295 interface(COND_INTER) %{
4296 equal(0x4, "e");
4297 not_equal(0x5, "ne");
4298 less(0x2, "b");
4299 greater_equal(0x3, "nb");
4300 less_equal(0x6, "be");
4301 greater(0x7, "nbe");
4302 overflow(0x0, "o");
4303 no_overflow(0x1, "no");
4304 %}
4305 %}
4306
4307
4308 // Floating comparisons that can be fixed up with extra conditional jumps
4309 operand cmpOpUCF2() %{
4310 match(Bool);
4311 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4312 n->as_Bool()->_test._test == BoolTest::eq);
4313 format %{ "" %}
4314 interface(COND_INTER) %{
4315 equal(0x4, "e");
4316 not_equal(0x5, "ne");
4317 less(0x2, "b");
4318 greater_equal(0x3, "nb");
4319 less_equal(0x6, "be");
4320 greater(0x7, "nbe");
4321 overflow(0x0, "o");
4322 no_overflow(0x1, "no");
4323 %}
4324 %}
4325
4326 //----------OPERAND CLASSES----------------------------------------------------
4327 // Operand Classes are groups of operands that are used as to simplify
4328 // instruction definitions by not requiring the AD writer to specify separate
4329 // instructions for every form of operand when the instruction accepts
4330 // multiple operand types with the same basic encoding and format. The classic
4331 // case of this is memory operands.
4332
4333 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4334 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4335 indCompressedOop, indCompressedOopOffset,
4336 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4337 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4338 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4339
4340 //----------PIPELINE-----------------------------------------------------------
4341 // Rules which define the behavior of the target architectures pipeline.
4342 pipeline %{
4343
4344 //----------ATTRIBUTES---------------------------------------------------------
4345 attributes %{
4346 variable_size_instructions; // Fixed size instructions
4347 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4348 instruction_unit_size = 1; // An instruction is 1 bytes long
4349 instruction_fetch_unit_size = 16; // The processor fetches one line
4350 instruction_fetch_units = 1; // of 16 bytes
4351
4352 // List of nop instructions
4353 nops( MachNop );
4354 %}
4355
4356 //----------RESOURCES----------------------------------------------------------
4357 // Resources are the functional units available to the machine
4358
4359 // Generic P2/P3 pipeline
4360 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4361 // 3 instructions decoded per cycle.
4362 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4363 // 3 ALU op, only ALU0 handles mul instructions.
4364 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4365 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4366 BR, FPU,
4367 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4368
4369 //----------PIPELINE DESCRIPTION-----------------------------------------------
4370 // Pipeline Description specifies the stages in the machine's pipeline
4371
4372 // Generic P2/P3 pipeline
4373 pipe_desc(S0, S1, S2, S3, S4, S5);
4374
4375 //----------PIPELINE CLASSES---------------------------------------------------
4376 // Pipeline Classes describe the stages in which input and output are
4377 // referenced by the hardware pipeline.
4378
4379 // Naming convention: ialu or fpu
4380 // Then: _reg
4381 // Then: _reg if there is a 2nd register
4382 // Then: _long if it's a pair of instructions implementing a long
4383 // Then: _fat if it requires the big decoder
4384 // Or: _mem if it requires the big decoder and a memory unit.
4385
4386 // Integer ALU reg operation
4387 pipe_class ialu_reg(rRegI dst)
4388 %{
4389 single_instruction;
4390 dst : S4(write);
4391 dst : S3(read);
4392 DECODE : S0; // any decoder
4393 ALU : S3; // any alu
4394 %}
4395
4396 // Long ALU reg operation
4397 pipe_class ialu_reg_long(rRegL dst)
4398 %{
4399 instruction_count(2);
4400 dst : S4(write);
4401 dst : S3(read);
4402 DECODE : S0(2); // any 2 decoders
4403 ALU : S3(2); // both alus
4404 %}
4405
4406 // Integer ALU reg operation using big decoder
4407 pipe_class ialu_reg_fat(rRegI dst)
4408 %{
4409 single_instruction;
4410 dst : S4(write);
4411 dst : S3(read);
4412 D0 : S0; // big decoder only
4413 ALU : S3; // any alu
4414 %}
4415
4416 // Integer ALU reg-reg operation
4417 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4418 %{
4419 single_instruction;
4420 dst : S4(write);
4421 src : S3(read);
4422 DECODE : S0; // any decoder
4423 ALU : S3; // any alu
4424 %}
4425
4426 // Integer ALU reg-reg operation
4427 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4428 %{
4429 single_instruction;
4430 dst : S4(write);
4431 src : S3(read);
4432 D0 : S0; // big decoder only
4433 ALU : S3; // any alu
4434 %}
4435
4436 // Integer ALU reg-mem operation
4437 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4438 %{
4439 single_instruction;
4440 dst : S5(write);
4441 mem : S3(read);
4442 D0 : S0; // big decoder only
4443 ALU : S4; // any alu
4444 MEM : S3; // any mem
4445 %}
4446
4447 // Integer mem operation (prefetch)
4448 pipe_class ialu_mem(memory mem)
4449 %{
4450 single_instruction;
4451 mem : S3(read);
4452 D0 : S0; // big decoder only
4453 MEM : S3; // any mem
4454 %}
4455
4456 // Integer Store to Memory
4457 pipe_class ialu_mem_reg(memory mem, rRegI src)
4458 %{
4459 single_instruction;
4460 mem : S3(read);
4461 src : S5(read);
4462 D0 : S0; // big decoder only
4463 ALU : S4; // any alu
4464 MEM : S3;
4465 %}
4466
4467 // // Long Store to Memory
4468 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4469 // %{
4470 // instruction_count(2);
4471 // mem : S3(read);
4472 // src : S5(read);
4473 // D0 : S0(2); // big decoder only; twice
4474 // ALU : S4(2); // any 2 alus
4475 // MEM : S3(2); // Both mems
4476 // %}
4477
4478 // Integer Store to Memory
4479 pipe_class ialu_mem_imm(memory mem)
4480 %{
4481 single_instruction;
4482 mem : S3(read);
4483 D0 : S0; // big decoder only
4484 ALU : S4; // any alu
4485 MEM : S3;
4486 %}
4487
4488 // Integer ALU0 reg-reg operation
4489 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4490 %{
4491 single_instruction;
4492 dst : S4(write);
4493 src : S3(read);
4494 D0 : S0; // Big decoder only
4495 ALU0 : S3; // only alu0
4496 %}
4497
4498 // Integer ALU0 reg-mem operation
4499 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4500 %{
4501 single_instruction;
4502 dst : S5(write);
4503 mem : S3(read);
4504 D0 : S0; // big decoder only
4505 ALU0 : S4; // ALU0 only
4506 MEM : S3; // any mem
4507 %}
4508
4509 // Integer ALU reg-reg operation
4510 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4511 %{
4512 single_instruction;
4513 cr : S4(write);
4514 src1 : S3(read);
4515 src2 : S3(read);
4516 DECODE : S0; // any decoder
4517 ALU : S3; // any alu
4518 %}
4519
4520 // Integer ALU reg-imm operation
4521 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4522 %{
4523 single_instruction;
4524 cr : S4(write);
4525 src1 : S3(read);
4526 DECODE : S0; // any decoder
4527 ALU : S3; // any alu
4528 %}
4529
4530 // Integer ALU reg-mem operation
4531 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4532 %{
4533 single_instruction;
4534 cr : S4(write);
4535 src1 : S3(read);
4536 src2 : S3(read);
4537 D0 : S0; // big decoder only
4538 ALU : S4; // any alu
4539 MEM : S3;
4540 %}
4541
4542 // Conditional move reg-reg
4543 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4544 %{
4545 instruction_count(4);
4546 y : S4(read);
4547 q : S3(read);
4548 p : S3(read);
4549 DECODE : S0(4); // any decoder
4550 %}
4551
4552 // Conditional move reg-reg
4553 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4554 %{
4555 single_instruction;
4556 dst : S4(write);
4557 src : S3(read);
4558 cr : S3(read);
4559 DECODE : S0; // any decoder
4560 %}
4561
4562 // Conditional move reg-mem
4563 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4564 %{
4565 single_instruction;
4566 dst : S4(write);
4567 src : S3(read);
4568 cr : S3(read);
4569 DECODE : S0; // any decoder
4570 MEM : S3;
4571 %}
4572
4573 // Conditional move reg-reg long
4574 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4575 %{
4576 single_instruction;
4577 dst : S4(write);
4578 src : S3(read);
4579 cr : S3(read);
4580 DECODE : S0(2); // any 2 decoders
4581 %}
4582
4583 // XXX
4584 // // Conditional move double reg-reg
4585 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4586 // %{
4587 // single_instruction;
4588 // dst : S4(write);
4589 // src : S3(read);
4590 // cr : S3(read);
4591 // DECODE : S0; // any decoder
4592 // %}
4593
4594 // Float reg-reg operation
4595 pipe_class fpu_reg(regD dst)
4596 %{
4597 instruction_count(2);
4598 dst : S3(read);
4599 DECODE : S0(2); // any 2 decoders
4600 FPU : S3;
4601 %}
4602
4603 // Float reg-reg operation
4604 pipe_class fpu_reg_reg(regD dst, regD src)
4605 %{
4606 instruction_count(2);
4607 dst : S4(write);
4608 src : S3(read);
4609 DECODE : S0(2); // any 2 decoders
4610 FPU : S3;
4611 %}
4612
4613 // Float reg-reg operation
4614 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4615 %{
4616 instruction_count(3);
4617 dst : S4(write);
4618 src1 : S3(read);
4619 src2 : S3(read);
4620 DECODE : S0(3); // any 3 decoders
4621 FPU : S3(2);
4622 %}
4623
4624 // Float reg-reg operation
4625 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4626 %{
4627 instruction_count(4);
4628 dst : S4(write);
4629 src1 : S3(read);
4630 src2 : S3(read);
4631 src3 : S3(read);
4632 DECODE : S0(4); // any 3 decoders
4633 FPU : S3(2);
4634 %}
4635
4636 // Float reg-reg operation
4637 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4638 %{
4639 instruction_count(4);
4640 dst : S4(write);
4641 src1 : S3(read);
4642 src2 : S3(read);
4643 src3 : S3(read);
4644 DECODE : S1(3); // any 3 decoders
4645 D0 : S0; // Big decoder only
4646 FPU : S3(2);
4647 MEM : S3;
4648 %}
4649
4650 // Float reg-mem operation
4651 pipe_class fpu_reg_mem(regD dst, memory mem)
4652 %{
4653 instruction_count(2);
4654 dst : S5(write);
4655 mem : S3(read);
4656 D0 : S0; // big decoder only
4657 DECODE : S1; // any decoder for FPU POP
4658 FPU : S4;
4659 MEM : S3; // any mem
4660 %}
4661
4662 // Float reg-mem operation
4663 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4664 %{
4665 instruction_count(3);
4666 dst : S5(write);
4667 src1 : S3(read);
4668 mem : S3(read);
4669 D0 : S0; // big decoder only
4670 DECODE : S1(2); // any decoder for FPU POP
4671 FPU : S4;
4672 MEM : S3; // any mem
4673 %}
4674
4675 // Float mem-reg operation
4676 pipe_class fpu_mem_reg(memory mem, regD src)
4677 %{
4678 instruction_count(2);
4679 src : S5(read);
4680 mem : S3(read);
4681 DECODE : S0; // any decoder for FPU PUSH
4682 D0 : S1; // big decoder only
4683 FPU : S4;
4684 MEM : S3; // any mem
4685 %}
4686
4687 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4688 %{
4689 instruction_count(3);
4690 src1 : S3(read);
4691 src2 : S3(read);
4692 mem : S3(read);
4693 DECODE : S0(2); // any decoder for FPU PUSH
4694 D0 : S1; // big decoder only
4695 FPU : S4;
4696 MEM : S3; // any mem
4697 %}
4698
4699 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4700 %{
4701 instruction_count(3);
4702 src1 : S3(read);
4703 src2 : S3(read);
4704 mem : S4(read);
4705 DECODE : S0; // any decoder for FPU PUSH
4706 D0 : S0(2); // big decoder only
4707 FPU : S4;
4708 MEM : S3(2); // any mem
4709 %}
4710
4711 pipe_class fpu_mem_mem(memory dst, memory src1)
4712 %{
4713 instruction_count(2);
4714 src1 : S3(read);
4715 dst : S4(read);
4716 D0 : S0(2); // big decoder only
4717 MEM : S3(2); // any mem
4718 %}
4719
4720 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4721 %{
4722 instruction_count(3);
4723 src1 : S3(read);
4724 src2 : S3(read);
4725 dst : S4(read);
4726 D0 : S0(3); // big decoder only
4727 FPU : S4;
4728 MEM : S3(3); // any mem
4729 %}
4730
4731 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4732 %{
4733 instruction_count(3);
4734 src1 : S4(read);
4735 mem : S4(read);
4736 DECODE : S0; // any decoder for FPU PUSH
4737 D0 : S0(2); // big decoder only
4738 FPU : S4;
4739 MEM : S3(2); // any mem
4740 %}
4741
4742 // Float load constant
4743 pipe_class fpu_reg_con(regD dst)
4744 %{
4745 instruction_count(2);
4746 dst : S5(write);
4747 D0 : S0; // big decoder only for the load
4748 DECODE : S1; // any decoder for FPU POP
4749 FPU : S4;
4750 MEM : S3; // any mem
4751 %}
4752
4753 // Float load constant
4754 pipe_class fpu_reg_reg_con(regD dst, regD src)
4755 %{
4756 instruction_count(3);
4757 dst : S5(write);
4758 src : S3(read);
4759 D0 : S0; // big decoder only for the load
4760 DECODE : S1(2); // any decoder for FPU POP
4761 FPU : S4;
4762 MEM : S3; // any mem
4763 %}
4764
4765 // UnConditional branch
4766 pipe_class pipe_jmp(label labl)
4767 %{
4768 single_instruction;
4769 BR : S3;
4770 %}
4771
4772 // Conditional branch
4773 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4774 %{
4775 single_instruction;
4776 cr : S1(read);
4777 BR : S3;
4778 %}
4779
4780 // Allocation idiom
4781 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4782 %{
4783 instruction_count(1); force_serialization;
4784 fixed_latency(6);
4785 heap_ptr : S3(read);
4786 DECODE : S0(3);
4787 D0 : S2;
4788 MEM : S3;
4789 ALU : S3(2);
4790 dst : S5(write);
4791 BR : S5;
4792 %}
4793
4794 // Generic big/slow expanded idiom
4795 pipe_class pipe_slow()
4796 %{
4797 instruction_count(10); multiple_bundles; force_serialization;
4798 fixed_latency(100);
4799 D0 : S0(2);
4800 MEM : S3(2);
4801 %}
4802
4803 // The real do-nothing guy
4804 pipe_class empty()
4805 %{
4806 instruction_count(0);
4807 %}
4808
4809 // Define the class for the Nop node
4810 define
4811 %{
4812 MachNop = empty;
4813 %}
4814
4815 %}
4816
4817 //----------INSTRUCTIONS-------------------------------------------------------
4818 //
4819 // match -- States which machine-independent subtree may be replaced
4820 // by this instruction.
4821 // ins_cost -- The estimated cost of this instruction is used by instruction
4822 // selection to identify a minimum cost tree of machine
4823 // instructions that matches a tree of machine-independent
4824 // instructions.
4825 // format -- A string providing the disassembly for this instruction.
4826 // The value of an instruction's operand may be inserted
4827 // by referring to it with a '$' prefix.
4828 // opcode -- Three instruction opcodes may be provided. These are referred
4829 // to within an encode class as $primary, $secondary, and $tertiary
4830 // rrspectively. The primary opcode is commonly used to
4831 // indicate the type of machine instruction, while secondary
4832 // and tertiary are often used for prefix options or addressing
4833 // modes.
4834 // ins_encode -- A list of encode classes with parameters. The encode class
4835 // name must have been defined in an 'enc_class' specification
4836 // in the encode section of the architecture description.
4837
4838 // Dummy reg-to-reg vector moves. Removed during post-selection cleanup.
4839 // Load Float
4840 instruct MoveF2VL(vlRegF dst, regF src) %{
4841 match(Set dst src);
4842 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
4843 ins_encode %{
4844 ShouldNotReachHere();
4845 %}
4846 ins_pipe( fpu_reg_reg );
4847 %}
4848
4849 // Load Float
4850 instruct MoveF2LEG(legRegF dst, regF src) %{
4851 match(Set dst src);
4852 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
4853 ins_encode %{
4854 ShouldNotReachHere();
4855 %}
4856 ins_pipe( fpu_reg_reg );
4857 %}
4858
4859 // Load Float
4860 instruct MoveVL2F(regF dst, vlRegF src) %{
4861 match(Set dst src);
4862 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
4863 ins_encode %{
4864 ShouldNotReachHere();
4865 %}
4866 ins_pipe( fpu_reg_reg );
4867 %}
4868
4869 // Load Float
4870 instruct MoveLEG2F(regF dst, legRegF src) %{
4871 match(Set dst src);
4872 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
4873 ins_encode %{
4874 ShouldNotReachHere();
4875 %}
4876 ins_pipe( fpu_reg_reg );
4877 %}
4878
4879 // Load Double
4880 instruct MoveD2VL(vlRegD dst, regD src) %{
4881 match(Set dst src);
4882 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
4883 ins_encode %{
4884 ShouldNotReachHere();
4885 %}
4886 ins_pipe( fpu_reg_reg );
4887 %}
4888
4889 // Load Double
4890 instruct MoveD2LEG(legRegD dst, regD src) %{
4891 match(Set dst src);
4892 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
4893 ins_encode %{
4894 ShouldNotReachHere();
4895 %}
4896 ins_pipe( fpu_reg_reg );
4897 %}
4898
4899 // Load Double
4900 instruct MoveVL2D(regD dst, vlRegD src) %{
4901 match(Set dst src);
4902 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
4903 ins_encode %{
4904 ShouldNotReachHere();
4905 %}
4906 ins_pipe( fpu_reg_reg );
4907 %}
4908
4909 // Load Double
4910 instruct MoveLEG2D(regD dst, legRegD src) %{
4911 match(Set dst src);
4912 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
4913 ins_encode %{
4914 ShouldNotReachHere();
4915 %}
4916 ins_pipe( fpu_reg_reg );
4917 %}
4918
4919 //----------Load/Store/Move Instructions---------------------------------------
4920 //----------Load Instructions--------------------------------------------------
4921
4922 // Load Byte (8 bit signed)
4923 instruct loadB(rRegI dst, memory mem)
4924 %{
4925 match(Set dst (LoadB mem));
4926
4927 ins_cost(125);
4928 format %{ "movsbl $dst, $mem\t# byte" %}
4929
4930 ins_encode %{
4931 __ movsbl($dst$$Register, $mem$$Address);
4932 %}
4933
4934 ins_pipe(ialu_reg_mem);
4935 %}
4936
4937 // Load Byte (8 bit signed) into Long Register
4938 instruct loadB2L(rRegL dst, memory mem)
4939 %{
4940 match(Set dst (ConvI2L (LoadB mem)));
4941
4942 ins_cost(125);
4943 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4944
4945 ins_encode %{
4946 __ movsbq($dst$$Register, $mem$$Address);
4947 %}
4948
4949 ins_pipe(ialu_reg_mem);
4950 %}
4951
4952 // Load Unsigned Byte (8 bit UNsigned)
4953 instruct loadUB(rRegI dst, memory mem)
4954 %{
4955 match(Set dst (LoadUB mem));
4956
4957 ins_cost(125);
4958 format %{ "movzbl $dst, $mem\t# ubyte" %}
4959
4960 ins_encode %{
4961 __ movzbl($dst$$Register, $mem$$Address);
4962 %}
4963
4964 ins_pipe(ialu_reg_mem);
4965 %}
4966
4967 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4968 instruct loadUB2L(rRegL dst, memory mem)
4969 %{
4970 match(Set dst (ConvI2L (LoadUB mem)));
4971
4972 ins_cost(125);
4973 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4974
4975 ins_encode %{
4976 __ movzbq($dst$$Register, $mem$$Address);
4977 %}
4978
4979 ins_pipe(ialu_reg_mem);
4980 %}
4981
4982 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4983 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4984 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4985 effect(KILL cr);
4986
4987 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4988 "andl $dst, right_n_bits($mask, 8)" %}
4989 ins_encode %{
4990 Register Rdst = $dst$$Register;
4991 __ movzbq(Rdst, $mem$$Address);
4992 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4993 %}
4994 ins_pipe(ialu_reg_mem);
4995 %}
4996
4997 // Load Short (16 bit signed)
4998 instruct loadS(rRegI dst, memory mem)
4999 %{
5000 match(Set dst (LoadS mem));
5001
5002 ins_cost(125);
5003 format %{ "movswl $dst, $mem\t# short" %}
5004
5005 ins_encode %{
5006 __ movswl($dst$$Register, $mem$$Address);
5007 %}
5008
5009 ins_pipe(ialu_reg_mem);
5010 %}
5011
5012 // Load Short (16 bit signed) to Byte (8 bit signed)
5013 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5014 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5015
5016 ins_cost(125);
5017 format %{ "movsbl $dst, $mem\t# short -> byte" %}
5018 ins_encode %{
5019 __ movsbl($dst$$Register, $mem$$Address);
5020 %}
5021 ins_pipe(ialu_reg_mem);
5022 %}
5023
5024 // Load Short (16 bit signed) into Long Register
5025 instruct loadS2L(rRegL dst, memory mem)
5026 %{
5027 match(Set dst (ConvI2L (LoadS mem)));
5028
5029 ins_cost(125);
5030 format %{ "movswq $dst, $mem\t# short -> long" %}
5031
5032 ins_encode %{
5033 __ movswq($dst$$Register, $mem$$Address);
5034 %}
5035
5036 ins_pipe(ialu_reg_mem);
5037 %}
5038
5039 // Load Unsigned Short/Char (16 bit UNsigned)
5040 instruct loadUS(rRegI dst, memory mem)
5041 %{
5042 match(Set dst (LoadUS mem));
5043
5044 ins_cost(125);
5045 format %{ "movzwl $dst, $mem\t# ushort/char" %}
5046
5047 ins_encode %{
5048 __ movzwl($dst$$Register, $mem$$Address);
5049 %}
5050
5051 ins_pipe(ialu_reg_mem);
5052 %}
5053
5054 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5055 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5056 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5057
5058 ins_cost(125);
5059 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
5060 ins_encode %{
5061 __ movsbl($dst$$Register, $mem$$Address);
5062 %}
5063 ins_pipe(ialu_reg_mem);
5064 %}
5065
5066 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
5067 instruct loadUS2L(rRegL dst, memory mem)
5068 %{
5069 match(Set dst (ConvI2L (LoadUS mem)));
5070
5071 ins_cost(125);
5072 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
5073
5074 ins_encode %{
5075 __ movzwq($dst$$Register, $mem$$Address);
5076 %}
5077
5078 ins_pipe(ialu_reg_mem);
5079 %}
5080
5081 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
5082 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5083 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5084
5085 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
5086 ins_encode %{
5087 __ movzbq($dst$$Register, $mem$$Address);
5088 %}
5089 ins_pipe(ialu_reg_mem);
5090 %}
5091
5092 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
5093 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
5094 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5095 effect(KILL cr);
5096
5097 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
5098 "andl $dst, right_n_bits($mask, 16)" %}
5099 ins_encode %{
5100 Register Rdst = $dst$$Register;
5101 __ movzwq(Rdst, $mem$$Address);
5102 __ andl(Rdst, $mask$$constant & right_n_bits(16));
5103 %}
5104 ins_pipe(ialu_reg_mem);
5105 %}
5106
5107 // Load Integer
5108 instruct loadI(rRegI dst, memory mem)
5109 %{
5110 match(Set dst (LoadI mem));
5111
5112 ins_cost(125);
5113 format %{ "movl $dst, $mem\t# int" %}
5114
5115 ins_encode %{
5116 __ movl($dst$$Register, $mem$$Address);
5117 %}
5118
5119 ins_pipe(ialu_reg_mem);
5120 %}
5121
5122 // Load Integer (32 bit signed) to Byte (8 bit signed)
5123 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
5124 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5125
5126 ins_cost(125);
5127 format %{ "movsbl $dst, $mem\t# int -> byte" %}
5128 ins_encode %{
5129 __ movsbl($dst$$Register, $mem$$Address);
5130 %}
5131 ins_pipe(ialu_reg_mem);
5132 %}
5133
5134 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
5135 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
5136 match(Set dst (AndI (LoadI mem) mask));
5137
5138 ins_cost(125);
5139 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
5140 ins_encode %{
5141 __ movzbl($dst$$Register, $mem$$Address);
5142 %}
5143 ins_pipe(ialu_reg_mem);
5144 %}
5145
5146 // Load Integer (32 bit signed) to Short (16 bit signed)
5147 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
5148 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5149
5150 ins_cost(125);
5151 format %{ "movswl $dst, $mem\t# int -> short" %}
5152 ins_encode %{
5153 __ movswl($dst$$Register, $mem$$Address);
5154 %}
5155 ins_pipe(ialu_reg_mem);
5156 %}
5157
5158 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
5159 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
5160 match(Set dst (AndI (LoadI mem) mask));
5161
5162 ins_cost(125);
5163 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
5164 ins_encode %{
5165 __ movzwl($dst$$Register, $mem$$Address);
5166 %}
5167 ins_pipe(ialu_reg_mem);
5168 %}
5169
5170 // Load Integer into Long Register
5171 instruct loadI2L(rRegL dst, memory mem)
5172 %{
5173 match(Set dst (ConvI2L (LoadI mem)));
5174
5175 ins_cost(125);
5176 format %{ "movslq $dst, $mem\t# int -> long" %}
5177
5178 ins_encode %{
5179 __ movslq($dst$$Register, $mem$$Address);
5180 %}
5181
5182 ins_pipe(ialu_reg_mem);
5183 %}
5184
5185 // Load Integer with mask 0xFF into Long Register
5186 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
5187 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5188
5189 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
5190 ins_encode %{
5191 __ movzbq($dst$$Register, $mem$$Address);
5192 %}
5193 ins_pipe(ialu_reg_mem);
5194 %}
5195
5196 // Load Integer with mask 0xFFFF into Long Register
5197 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
5198 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5199
5200 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
5201 ins_encode %{
5202 __ movzwq($dst$$Register, $mem$$Address);
5203 %}
5204 ins_pipe(ialu_reg_mem);
5205 %}
5206
5207 // Load Integer with a 31-bit mask into Long Register
5208 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5209 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5210 effect(KILL cr);
5211
5212 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5213 "andl $dst, $mask" %}
5214 ins_encode %{
5215 Register Rdst = $dst$$Register;
5216 __ movl(Rdst, $mem$$Address);
5217 __ andl(Rdst, $mask$$constant);
5218 %}
5219 ins_pipe(ialu_reg_mem);
5220 %}
5221
5222 // Load Unsigned Integer into Long Register
5223 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5224 %{
5225 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5226
5227 ins_cost(125);
5228 format %{ "movl $dst, $mem\t# uint -> long" %}
5229
5230 ins_encode %{
5231 __ movl($dst$$Register, $mem$$Address);
5232 %}
5233
5234 ins_pipe(ialu_reg_mem);
5235 %}
5236
5237 // Load Long
5238 instruct loadL(rRegL dst, memory mem)
5239 %{
5240 match(Set dst (LoadL mem));
5241
5242 ins_cost(125);
5243 format %{ "movq $dst, $mem\t# long" %}
5244
5245 ins_encode %{
5246 __ movq($dst$$Register, $mem$$Address);
5247 %}
5248
5249 ins_pipe(ialu_reg_mem); // XXX
5250 %}
5251
5252 // Load Range
5253 instruct loadRange(rRegI dst, memory mem)
5254 %{
5255 match(Set dst (LoadRange mem));
5256
5257 ins_cost(125); // XXX
5258 format %{ "movl $dst, $mem\t# range" %}
5259 ins_encode %{
5260 __ movl($dst$$Register, $mem$$Address);
5261 %}
5262 ins_pipe(ialu_reg_mem);
5263 %}
5264
5265 // Load Pointer
5266 instruct loadP(rRegP dst, memory mem)
5267 %{
5268 match(Set dst (LoadP mem));
5269 predicate(n->as_Load()->barrier_data() == 0);
5270
5271 ins_cost(125); // XXX
5272 format %{ "movq $dst, $mem\t# ptr" %}
5273 ins_encode %{
5274 __ movq($dst$$Register, $mem$$Address);
5275 %}
5276 ins_pipe(ialu_reg_mem); // XXX
5277 %}
5278
5279 // Load Compressed Pointer
5280 instruct loadN(rRegN dst, memory mem)
5281 %{
5282 match(Set dst (LoadN mem));
5283
5284 ins_cost(125); // XXX
5285 format %{ "movl $dst, $mem\t# compressed ptr" %}
5286 ins_encode %{
5287 __ movl($dst$$Register, $mem$$Address);
5288 %}
5289 ins_pipe(ialu_reg_mem); // XXX
5290 %}
5291
5292
5293 // Load Klass Pointer
5294 instruct loadKlass(rRegP dst, memory mem)
5295 %{
5296 match(Set dst (LoadKlass mem));
5297
5298 ins_cost(125); // XXX
5299 format %{ "movq $dst, $mem\t# class" %}
5300 ins_encode %{
5301 __ movq($dst$$Register, $mem$$Address);
5302 %}
5303 ins_pipe(ialu_reg_mem); // XXX
5304 %}
5305
5306 // Load narrow Klass Pointer
5307 instruct loadNKlass(rRegN dst, memory mem)
5308 %{
5309 match(Set dst (LoadNKlass mem));
5310
5311 ins_cost(125); // XXX
5312 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5313 ins_encode %{
5314 __ movl($dst$$Register, $mem$$Address);
5315 %}
5316 ins_pipe(ialu_reg_mem); // XXX
5317 %}
5318
5319 // Load Float
5320 instruct loadF(regF dst, memory mem)
5321 %{
5322 match(Set dst (LoadF mem));
5323
5324 ins_cost(145); // XXX
5325 format %{ "movss $dst, $mem\t# float" %}
5326 ins_encode %{
5327 __ movflt($dst$$XMMRegister, $mem$$Address);
5328 %}
5329 ins_pipe(pipe_slow); // XXX
5330 %}
5331
5332 // Load Double
5333 instruct loadD_partial(regD dst, memory mem)
5334 %{
5335 predicate(!UseXmmLoadAndClearUpper);
5336 match(Set dst (LoadD mem));
5337
5338 ins_cost(145); // XXX
5339 format %{ "movlpd $dst, $mem\t# double" %}
5340 ins_encode %{
5341 __ movdbl($dst$$XMMRegister, $mem$$Address);
5342 %}
5343 ins_pipe(pipe_slow); // XXX
5344 %}
5345
5346 instruct loadD(regD dst, memory mem)
5347 %{
5348 predicate(UseXmmLoadAndClearUpper);
5349 match(Set dst (LoadD mem));
5350
5351 ins_cost(145); // XXX
5352 format %{ "movsd $dst, $mem\t# double" %}
5353 ins_encode %{
5354 __ movdbl($dst$$XMMRegister, $mem$$Address);
5355 %}
5356 ins_pipe(pipe_slow); // XXX
5357 %}
5358
5359
5360 // Following pseudo code describes the algorithm for max[FD]:
5361 // Min algorithm is on similar lines
5362 // btmp = (b < +0.0) ? a : b
5363 // atmp = (b < +0.0) ? b : a
5364 // Tmp = Max_Float(atmp , btmp)
5365 // Res = (atmp == NaN) ? atmp : Tmp
5366
5367 // max = java.lang.Math.max(float a, float b)
5368 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5369 predicate(UseAVX > 0 && !n->is_reduction());
5370 match(Set dst (MaxF a b));
5371 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5372 format %{
5373 "vblendvps $btmp,$b,$a,$b \n\t"
5374 "vblendvps $atmp,$a,$b,$b \n\t"
5375 "vmaxss $tmp,$atmp,$btmp \n\t"
5376 "vcmpps.unordered $btmp,$atmp,$atmp \n\t"
5377 "vblendvps $dst,$tmp,$atmp,$btmp \n\t"
5378 %}
5379 ins_encode %{
5380 int vector_len = Assembler::AVX_128bit;
5381 __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5382 __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5383 __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5384 __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5385 __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5386 %}
5387 ins_pipe( pipe_slow );
5388 %}
5389
5390 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5391 predicate(UseAVX > 0 && n->is_reduction());
5392 match(Set dst (MaxF a b));
5393 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5394
5395 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
5396 ins_encode %{
5397 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5398 false /*min*/, true /*single*/);
5399 %}
5400 ins_pipe( pipe_slow );
5401 %}
5402
5403 // max = java.lang.Math.max(double a, double b)
5404 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5405 predicate(UseAVX > 0 && !n->is_reduction());
5406 match(Set dst (MaxD a b));
5407 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
5408 format %{
5409 "vblendvpd $btmp,$b,$a,$b \n\t"
5410 "vblendvpd $atmp,$a,$b,$b \n\t"
5411 "vmaxsd $tmp,$atmp,$btmp \n\t"
5412 "vcmppd.unordered $btmp,$atmp,$atmp \n\t"
5413 "vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
5414 %}
5415 ins_encode %{
5416 int vector_len = Assembler::AVX_128bit;
5417 __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
5418 __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
5419 __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5420 __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5421 __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5422 %}
5423 ins_pipe( pipe_slow );
5424 %}
5425
5426 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5427 predicate(UseAVX > 0 && n->is_reduction());
5428 match(Set dst (MaxD a b));
5429 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5430
5431 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
5432 ins_encode %{
5433 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5434 false /*min*/, false /*single*/);
5435 %}
5436 ins_pipe( pipe_slow );
5437 %}
5438
5439 // min = java.lang.Math.min(float a, float b)
5440 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
5441 predicate(UseAVX > 0 && !n->is_reduction());
5442 match(Set dst (MinF a b));
5443 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5444 format %{
5445 "vblendvps $atmp,$a,$b,$a \n\t"
5446 "vblendvps $btmp,$b,$a,$a \n\t"
5447 "vminss $tmp,$atmp,$btmp \n\t"
5448 "vcmpps.unordered $btmp,$atmp,$atmp \n\t"
5449 "vblendvps $dst,$tmp,$atmp,$btmp \n\t"
5450 %}
5451 ins_encode %{
5452 int vector_len = Assembler::AVX_128bit;
5453 __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5454 __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5455 __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5456 __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5457 __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5458 %}
5459 ins_pipe( pipe_slow );
5460 %}
5461
5462 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
5463 predicate(UseAVX > 0 && n->is_reduction());
5464 match(Set dst (MinF a b));
5465 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5466
5467 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
5468 ins_encode %{
5469 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5470 true /*min*/, true /*single*/);
5471 %}
5472 ins_pipe( pipe_slow );
5473 %}
5474
5475 // min = java.lang.Math.min(double a, double b)
5476 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
5477 predicate(UseAVX > 0 && !n->is_reduction());
5478 match(Set dst (MinD a b));
5479 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
5480 format %{
5481 "vblendvpd $atmp,$a,$b,$a \n\t"
5482 "vblendvpd $btmp,$b,$a,$a \n\t"
5483 "vminsd $tmp,$atmp,$btmp \n\t"
5484 "vcmppd.unordered $btmp,$atmp,$atmp \n\t"
5485 "vblendvpd $dst,$tmp,$atmp,$btmp \n\t"
5486 %}
5487 ins_encode %{
5488 int vector_len = Assembler::AVX_128bit;
5489 __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
5490 __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
5491 __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
5492 __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
5493 __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
5494 %}
5495 ins_pipe( pipe_slow );
5496 %}
5497
5498 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
5499 predicate(UseAVX > 0 && n->is_reduction());
5500 match(Set dst (MinD a b));
5501 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
5502
5503 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
5504 ins_encode %{
5505 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
5506 true /*min*/, false /*single*/);
5507 %}
5508 ins_pipe( pipe_slow );
5509 %}
5510
5511 // Load Effective Address
5512 instruct leaP8(rRegP dst, indOffset8 mem)
5513 %{
5514 match(Set dst mem);
5515
5516 ins_cost(110); // XXX
5517 format %{ "leaq $dst, $mem\t# ptr 8" %}
5518 ins_encode %{
5519 __ leaq($dst$$Register, $mem$$Address);
5520 %}
5521 ins_pipe(ialu_reg_reg_fat);
5522 %}
5523
5524 instruct leaP32(rRegP dst, indOffset32 mem)
5525 %{
5526 match(Set dst mem);
5527
5528 ins_cost(110);
5529 format %{ "leaq $dst, $mem\t# ptr 32" %}
5530 ins_encode %{
5531 __ leaq($dst$$Register, $mem$$Address);
5532 %}
5533 ins_pipe(ialu_reg_reg_fat);
5534 %}
5535
5536 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5537 %{
5538 match(Set dst mem);
5539
5540 ins_cost(110);
5541 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5542 ins_encode %{
5543 __ leaq($dst$$Register, $mem$$Address);
5544 %}
5545 ins_pipe(ialu_reg_reg_fat);
5546 %}
5547
5548 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5549 %{
5550 match(Set dst mem);
5551
5552 ins_cost(110);
5553 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5554 ins_encode %{
5555 __ leaq($dst$$Register, $mem$$Address);
5556 %}
5557 ins_pipe(ialu_reg_reg_fat);
5558 %}
5559
5560 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5561 %{
5562 match(Set dst mem);
5563
5564 ins_cost(110);
5565 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5566 ins_encode %{
5567 __ leaq($dst$$Register, $mem$$Address);
5568 %}
5569 ins_pipe(ialu_reg_reg_fat);
5570 %}
5571
5572 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5573 %{
5574 match(Set dst mem);
5575
5576 ins_cost(110);
5577 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5578 ins_encode %{
5579 __ leaq($dst$$Register, $mem$$Address);
5580 %}
5581 ins_pipe(ialu_reg_reg_fat);
5582 %}
5583
5584 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5585 %{
5586 match(Set dst mem);
5587
5588 ins_cost(110);
5589 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5590 ins_encode %{
5591 __ leaq($dst$$Register, $mem$$Address);
5592 %}
5593 ins_pipe(ialu_reg_reg_fat);
5594 %}
5595
5596 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5597 %{
5598 match(Set dst mem);
5599
5600 ins_cost(110);
5601 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5602 ins_encode %{
5603 __ leaq($dst$$Register, $mem$$Address);
5604 %}
5605 ins_pipe(ialu_reg_reg_fat);
5606 %}
5607
5608 // Load Effective Address which uses Narrow (32-bits) oop
5609 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5610 %{
5611 predicate(UseCompressedOops && (CompressedOops::shift() != 0));
5612 match(Set dst mem);
5613
5614 ins_cost(110);
5615 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5616 ins_encode %{
5617 __ leaq($dst$$Register, $mem$$Address);
5618 %}
5619 ins_pipe(ialu_reg_reg_fat);
5620 %}
5621
5622 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5623 %{
5624 predicate(CompressedOops::shift() == 0);
5625 match(Set dst mem);
5626
5627 ins_cost(110); // XXX
5628 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5629 ins_encode %{
5630 __ leaq($dst$$Register, $mem$$Address);
5631 %}
5632 ins_pipe(ialu_reg_reg_fat);
5633 %}
5634
5635 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5636 %{
5637 predicate(CompressedOops::shift() == 0);
5638 match(Set dst mem);
5639
5640 ins_cost(110);
5641 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5642 ins_encode %{
5643 __ leaq($dst$$Register, $mem$$Address);
5644 %}
5645 ins_pipe(ialu_reg_reg_fat);
5646 %}
5647
5648 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5649 %{
5650 predicate(CompressedOops::shift() == 0);
5651 match(Set dst mem);
5652
5653 ins_cost(110);
5654 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5655 ins_encode %{
5656 __ leaq($dst$$Register, $mem$$Address);
5657 %}
5658 ins_pipe(ialu_reg_reg_fat);
5659 %}
5660
5661 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5662 %{
5663 predicate(CompressedOops::shift() == 0);
5664 match(Set dst mem);
5665
5666 ins_cost(110);
5667 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5668 ins_encode %{
5669 __ leaq($dst$$Register, $mem$$Address);
5670 %}
5671 ins_pipe(ialu_reg_reg_fat);
5672 %}
5673
5674 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5675 %{
5676 predicate(CompressedOops::shift() == 0);
5677 match(Set dst mem);
5678
5679 ins_cost(110);
5680 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5681 ins_encode %{
5682 __ leaq($dst$$Register, $mem$$Address);
5683 %}
5684 ins_pipe(ialu_reg_reg_fat);
5685 %}
5686
5687 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5688 %{
5689 predicate(CompressedOops::shift() == 0);
5690 match(Set dst mem);
5691
5692 ins_cost(110);
5693 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5694 ins_encode %{
5695 __ leaq($dst$$Register, $mem$$Address);
5696 %}
5697 ins_pipe(ialu_reg_reg_fat);
5698 %}
5699
5700 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5701 %{
5702 predicate(CompressedOops::shift() == 0);
5703 match(Set dst mem);
5704
5705 ins_cost(110);
5706 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5707 ins_encode %{
5708 __ leaq($dst$$Register, $mem$$Address);
5709 %}
5710 ins_pipe(ialu_reg_reg_fat);
5711 %}
5712
5713 instruct loadConI(rRegI dst, immI src)
5714 %{
5715 match(Set dst src);
5716
5717 format %{ "movl $dst, $src\t# int" %}
5718 ins_encode %{
5719 __ movl($dst$$Register, $src$$constant);
5720 %}
5721 ins_pipe(ialu_reg_fat); // XXX
5722 %}
5723
5724 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
5725 %{
5726 match(Set dst src);
5727 effect(KILL cr);
5728
5729 ins_cost(50);
5730 format %{ "xorl $dst, $dst\t# int" %}
5731 ins_encode %{
5732 __ xorl($dst$$Register, $dst$$Register);
5733 %}
5734 ins_pipe(ialu_reg);
5735 %}
5736
5737 instruct loadConL(rRegL dst, immL src)
5738 %{
5739 match(Set dst src);
5740
5741 ins_cost(150);
5742 format %{ "movq $dst, $src\t# long" %}
5743 ins_encode %{
5744 __ mov64($dst$$Register, $src$$constant);
5745 %}
5746 ins_pipe(ialu_reg);
5747 %}
5748
5749 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5750 %{
5751 match(Set dst src);
5752 effect(KILL cr);
5753
5754 ins_cost(50);
5755 format %{ "xorl $dst, $dst\t# long" %}
5756 ins_encode %{
5757 __ xorl($dst$$Register, $dst$$Register);
5758 %}
5759 ins_pipe(ialu_reg); // XXX
5760 %}
5761
5762 instruct loadConUL32(rRegL dst, immUL32 src)
5763 %{
5764 match(Set dst src);
5765
5766 ins_cost(60);
5767 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5768 ins_encode %{
5769 __ movl($dst$$Register, $src$$constant);
5770 %}
5771 ins_pipe(ialu_reg);
5772 %}
5773
5774 instruct loadConL32(rRegL dst, immL32 src)
5775 %{
5776 match(Set dst src);
5777
5778 ins_cost(70);
5779 format %{ "movq $dst, $src\t# long (32-bit)" %}
5780 ins_encode %{
5781 __ movq($dst$$Register, $src$$constant);
5782 %}
5783 ins_pipe(ialu_reg);
5784 %}
5785
5786 instruct loadConP(rRegP dst, immP con) %{
5787 match(Set dst con);
5788
5789 format %{ "movq $dst, $con\t# ptr" %}
5790 ins_encode %{
5791 __ mov64($dst$$Register, $con$$constant, $con->constant_reloc(), RELOC_IMM64);
5792 %}
5793 ins_pipe(ialu_reg_fat); // XXX
5794 %}
5795
5796 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5797 %{
5798 match(Set dst src);
5799 effect(KILL cr);
5800
5801 ins_cost(50);
5802 format %{ "xorl $dst, $dst\t# ptr" %}
5803 ins_encode %{
5804 __ xorl($dst$$Register, $dst$$Register);
5805 %}
5806 ins_pipe(ialu_reg);
5807 %}
5808
5809 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5810 %{
5811 match(Set dst src);
5812 effect(KILL cr);
5813
5814 ins_cost(60);
5815 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5816 ins_encode %{
5817 __ movl($dst$$Register, $src$$constant);
5818 %}
5819 ins_pipe(ialu_reg);
5820 %}
5821
5822 instruct loadConF(regF dst, immF con) %{
5823 match(Set dst con);
5824 ins_cost(125);
5825 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5826 ins_encode %{
5827 __ movflt($dst$$XMMRegister, $constantaddress($con));
5828 %}
5829 ins_pipe(pipe_slow);
5830 %}
5831
5832 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5833 match(Set dst src);
5834 effect(KILL cr);
5835 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5836 ins_encode %{
5837 __ xorq($dst$$Register, $dst$$Register);
5838 %}
5839 ins_pipe(ialu_reg);
5840 %}
5841
5842 instruct loadConN(rRegN dst, immN src) %{
5843 match(Set dst src);
5844
5845 ins_cost(125);
5846 format %{ "movl $dst, $src\t# compressed ptr" %}
5847 ins_encode %{
5848 address con = (address)$src$$constant;
5849 if (con == NULL) {
5850 ShouldNotReachHere();
5851 } else {
5852 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5853 }
5854 %}
5855 ins_pipe(ialu_reg_fat); // XXX
5856 %}
5857
5858 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5859 match(Set dst src);
5860
5861 ins_cost(125);
5862 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5863 ins_encode %{
5864 address con = (address)$src$$constant;
5865 if (con == NULL) {
5866 ShouldNotReachHere();
5867 } else {
5868 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5869 }
5870 %}
5871 ins_pipe(ialu_reg_fat); // XXX
5872 %}
5873
5874 instruct loadConF0(regF dst, immF0 src)
5875 %{
5876 match(Set dst src);
5877 ins_cost(100);
5878
5879 format %{ "xorps $dst, $dst\t# float 0.0" %}
5880 ins_encode %{
5881 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5882 %}
5883 ins_pipe(pipe_slow);
5884 %}
5885
5886 // Use the same format since predicate() can not be used here.
5887 instruct loadConD(regD dst, immD con) %{
5888 match(Set dst con);
5889 ins_cost(125);
5890 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5891 ins_encode %{
5892 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5893 %}
5894 ins_pipe(pipe_slow);
5895 %}
5896
5897 instruct loadConD0(regD dst, immD0 src)
5898 %{
5899 match(Set dst src);
5900 ins_cost(100);
5901
5902 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5903 ins_encode %{
5904 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5905 %}
5906 ins_pipe(pipe_slow);
5907 %}
5908
5909 instruct loadSSI(rRegI dst, stackSlotI src)
5910 %{
5911 match(Set dst src);
5912
5913 ins_cost(125);
5914 format %{ "movl $dst, $src\t# int stk" %}
5915 opcode(0x8B);
5916 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5917 ins_pipe(ialu_reg_mem);
5918 %}
5919
5920 instruct loadSSL(rRegL dst, stackSlotL src)
5921 %{
5922 match(Set dst src);
5923
5924 ins_cost(125);
5925 format %{ "movq $dst, $src\t# long stk" %}
5926 opcode(0x8B);
5927 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5928 ins_pipe(ialu_reg_mem);
5929 %}
5930
5931 instruct loadSSP(rRegP dst, stackSlotP src)
5932 %{
5933 match(Set dst src);
5934
5935 ins_cost(125);
5936 format %{ "movq $dst, $src\t# ptr stk" %}
5937 opcode(0x8B);
5938 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5939 ins_pipe(ialu_reg_mem);
5940 %}
5941
5942 instruct loadSSF(regF dst, stackSlotF src)
5943 %{
5944 match(Set dst src);
5945
5946 ins_cost(125);
5947 format %{ "movss $dst, $src\t# float stk" %}
5948 ins_encode %{
5949 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5950 %}
5951 ins_pipe(pipe_slow); // XXX
5952 %}
5953
5954 // Use the same format since predicate() can not be used here.
5955 instruct loadSSD(regD dst, stackSlotD src)
5956 %{
5957 match(Set dst src);
5958
5959 ins_cost(125);
5960 format %{ "movsd $dst, $src\t# double stk" %}
5961 ins_encode %{
5962 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5963 %}
5964 ins_pipe(pipe_slow); // XXX
5965 %}
5966
5967 // Prefetch instructions for allocation.
5968 // Must be safe to execute with invalid address (cannot fault).
5969
5970 instruct prefetchAlloc( memory mem ) %{
5971 predicate(AllocatePrefetchInstr==3);
5972 match(PrefetchAllocation mem);
5973 ins_cost(125);
5974
5975 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5976 ins_encode %{
5977 __ prefetchw($mem$$Address);
5978 %}
5979 ins_pipe(ialu_mem);
5980 %}
5981
5982 instruct prefetchAllocNTA( memory mem ) %{
5983 predicate(AllocatePrefetchInstr==0);
5984 match(PrefetchAllocation mem);
5985 ins_cost(125);
5986
5987 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5988 ins_encode %{
5989 __ prefetchnta($mem$$Address);
5990 %}
5991 ins_pipe(ialu_mem);
5992 %}
5993
5994 instruct prefetchAllocT0( memory mem ) %{
5995 predicate(AllocatePrefetchInstr==1);
5996 match(PrefetchAllocation mem);
5997 ins_cost(125);
5998
5999 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
6000 ins_encode %{
6001 __ prefetcht0($mem$$Address);
6002 %}
6003 ins_pipe(ialu_mem);
6004 %}
6005
6006 instruct prefetchAllocT2( memory mem ) %{
6007 predicate(AllocatePrefetchInstr==2);
6008 match(PrefetchAllocation mem);
6009 ins_cost(125);
6010
6011 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
6012 ins_encode %{
6013 __ prefetcht2($mem$$Address);
6014 %}
6015 ins_pipe(ialu_mem);
6016 %}
6017
6018 //----------Store Instructions-------------------------------------------------
6019
6020 // Store Byte
6021 instruct storeB(memory mem, rRegI src)
6022 %{
6023 match(Set mem (StoreB mem src));
6024
6025 ins_cost(125); // XXX
6026 format %{ "movb $mem, $src\t# byte" %}
6027 ins_encode %{
6028 __ movb($mem$$Address, $src$$Register);
6029 %}
6030 ins_pipe(ialu_mem_reg);
6031 %}
6032
6033 // Store Char/Short
6034 instruct storeC(memory mem, rRegI src)
6035 %{
6036 match(Set mem (StoreC mem src));
6037
6038 ins_cost(125); // XXX
6039 format %{ "movw $mem, $src\t# char/short" %}
6040 ins_encode %{
6041 __ movw($mem$$Address, $src$$Register);
6042 %}
6043 ins_pipe(ialu_mem_reg);
6044 %}
6045
6046 // Store Integer
6047 instruct storeI(memory mem, rRegI src)
6048 %{
6049 match(Set mem (StoreI mem src));
6050
6051 ins_cost(125); // XXX
6052 format %{ "movl $mem, $src\t# int" %}
6053 ins_encode %{
6054 __ movl($mem$$Address, $src$$Register);
6055 %}
6056 ins_pipe(ialu_mem_reg);
6057 %}
6058
6059 // Store Long
6060 instruct storeL(memory mem, rRegL src)
6061 %{
6062 match(Set mem (StoreL mem src));
6063
6064 ins_cost(125); // XXX
6065 format %{ "movq $mem, $src\t# long" %}
6066 ins_encode %{
6067 __ movq($mem$$Address, $src$$Register);
6068 %}
6069 ins_pipe(ialu_mem_reg); // XXX
6070 %}
6071
6072 // Store Pointer
6073 instruct storeP(memory mem, any_RegP src)
6074 %{
6075 match(Set mem (StoreP mem src));
6076
6077 ins_cost(125); // XXX
6078 format %{ "movq $mem, $src\t# ptr" %}
6079 ins_encode %{
6080 __ movq($mem$$Address, $src$$Register);
6081 %}
6082 ins_pipe(ialu_mem_reg);
6083 %}
6084
6085 instruct storeImmP0(memory mem, immP0 zero)
6086 %{
6087 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6088 match(Set mem (StoreP mem zero));
6089
6090 ins_cost(125); // XXX
6091 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
6092 ins_encode %{
6093 __ movq($mem$$Address, r12);
6094 %}
6095 ins_pipe(ialu_mem_reg);
6096 %}
6097
6098 // Store NULL Pointer, mark word, or other simple pointer constant.
6099 instruct storeImmP(memory mem, immP31 src)
6100 %{
6101 match(Set mem (StoreP mem src));
6102
6103 ins_cost(150); // XXX
6104 format %{ "movq $mem, $src\t# ptr" %}
6105 ins_encode %{
6106 __ movq($mem$$Address, $src$$constant);
6107 %}
6108 ins_pipe(ialu_mem_imm);
6109 %}
6110
6111 // Store Compressed Pointer
6112 instruct storeN(memory mem, rRegN src)
6113 %{
6114 match(Set mem (StoreN mem src));
6115
6116 ins_cost(125); // XXX
6117 format %{ "movl $mem, $src\t# compressed ptr" %}
6118 ins_encode %{
6119 __ movl($mem$$Address, $src$$Register);
6120 %}
6121 ins_pipe(ialu_mem_reg);
6122 %}
6123
6124 instruct storeNKlass(memory mem, rRegN src)
6125 %{
6126 match(Set mem (StoreNKlass mem src));
6127
6128 ins_cost(125); // XXX
6129 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6130 ins_encode %{
6131 __ movl($mem$$Address, $src$$Register);
6132 %}
6133 ins_pipe(ialu_mem_reg);
6134 %}
6135
6136 instruct storeImmN0(memory mem, immN0 zero)
6137 %{
6138 predicate(CompressedOops::base() == NULL);
6139 match(Set mem (StoreN mem zero));
6140
6141 ins_cost(125); // XXX
6142 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
6143 ins_encode %{
6144 __ movl($mem$$Address, r12);
6145 %}
6146 ins_pipe(ialu_mem_reg);
6147 %}
6148
6149 instruct storeImmN(memory mem, immN src)
6150 %{
6151 match(Set mem (StoreN mem src));
6152
6153 ins_cost(150); // XXX
6154 format %{ "movl $mem, $src\t# compressed ptr" %}
6155 ins_encode %{
6156 address con = (address)$src$$constant;
6157 if (con == NULL) {
6158 __ movl($mem$$Address, (int32_t)0);
6159 } else {
6160 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
6161 }
6162 %}
6163 ins_pipe(ialu_mem_imm);
6164 %}
6165
6166 instruct storeImmNKlass(memory mem, immNKlass src)
6167 %{
6168 match(Set mem (StoreNKlass mem src));
6169
6170 ins_cost(150); // XXX
6171 format %{ "movl $mem, $src\t# compressed klass ptr" %}
6172 ins_encode %{
6173 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
6174 %}
6175 ins_pipe(ialu_mem_imm);
6176 %}
6177
6178 // Store Integer Immediate
6179 instruct storeImmI0(memory mem, immI_0 zero)
6180 %{
6181 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6182 match(Set mem (StoreI mem zero));
6183
6184 ins_cost(125); // XXX
6185 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
6186 ins_encode %{
6187 __ movl($mem$$Address, r12);
6188 %}
6189 ins_pipe(ialu_mem_reg);
6190 %}
6191
6192 instruct storeImmI(memory mem, immI src)
6193 %{
6194 match(Set mem (StoreI mem src));
6195
6196 ins_cost(150);
6197 format %{ "movl $mem, $src\t# int" %}
6198 ins_encode %{
6199 __ movl($mem$$Address, $src$$constant);
6200 %}
6201 ins_pipe(ialu_mem_imm);
6202 %}
6203
6204 // Store Long Immediate
6205 instruct storeImmL0(memory mem, immL0 zero)
6206 %{
6207 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6208 match(Set mem (StoreL mem zero));
6209
6210 ins_cost(125); // XXX
6211 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
6212 ins_encode %{
6213 __ movq($mem$$Address, r12);
6214 %}
6215 ins_pipe(ialu_mem_reg);
6216 %}
6217
6218 instruct storeImmL(memory mem, immL32 src)
6219 %{
6220 match(Set mem (StoreL mem src));
6221
6222 ins_cost(150);
6223 format %{ "movq $mem, $src\t# long" %}
6224 ins_encode %{
6225 __ movq($mem$$Address, $src$$constant);
6226 %}
6227 ins_pipe(ialu_mem_imm);
6228 %}
6229
6230 // Store Short/Char Immediate
6231 instruct storeImmC0(memory mem, immI_0 zero)
6232 %{
6233 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6234 match(Set mem (StoreC mem zero));
6235
6236 ins_cost(125); // XXX
6237 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
6238 ins_encode %{
6239 __ movw($mem$$Address, r12);
6240 %}
6241 ins_pipe(ialu_mem_reg);
6242 %}
6243
6244 instruct storeImmI16(memory mem, immI16 src)
6245 %{
6246 predicate(UseStoreImmI16);
6247 match(Set mem (StoreC mem src));
6248
6249 ins_cost(150);
6250 format %{ "movw $mem, $src\t# short/char" %}
6251 ins_encode %{
6252 __ movw($mem$$Address, $src$$constant);
6253 %}
6254 ins_pipe(ialu_mem_imm);
6255 %}
6256
6257 // Store Byte Immediate
6258 instruct storeImmB0(memory mem, immI_0 zero)
6259 %{
6260 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6261 match(Set mem (StoreB mem zero));
6262
6263 ins_cost(125); // XXX
6264 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
6265 ins_encode %{
6266 __ movb($mem$$Address, r12);
6267 %}
6268 ins_pipe(ialu_mem_reg);
6269 %}
6270
6271 instruct storeImmB(memory mem, immI8 src)
6272 %{
6273 match(Set mem (StoreB mem src));
6274
6275 ins_cost(150); // XXX
6276 format %{ "movb $mem, $src\t# byte" %}
6277 ins_encode %{
6278 __ movb($mem$$Address, $src$$constant);
6279 %}
6280 ins_pipe(ialu_mem_imm);
6281 %}
6282
6283 // Store CMS card-mark Immediate
6284 instruct storeImmCM0_reg(memory mem, immI_0 zero)
6285 %{
6286 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6287 match(Set mem (StoreCM mem zero));
6288
6289 ins_cost(125); // XXX
6290 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
6291 ins_encode %{
6292 __ movb($mem$$Address, r12);
6293 %}
6294 ins_pipe(ialu_mem_reg);
6295 %}
6296
6297 instruct storeImmCM0(memory mem, immI_0 src)
6298 %{
6299 match(Set mem (StoreCM mem src));
6300
6301 ins_cost(150); // XXX
6302 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
6303 ins_encode %{
6304 __ movb($mem$$Address, $src$$constant);
6305 %}
6306 ins_pipe(ialu_mem_imm);
6307 %}
6308
6309 // Store Float
6310 instruct storeF(memory mem, regF src)
6311 %{
6312 match(Set mem (StoreF mem src));
6313
6314 ins_cost(95); // XXX
6315 format %{ "movss $mem, $src\t# float" %}
6316 ins_encode %{
6317 __ movflt($mem$$Address, $src$$XMMRegister);
6318 %}
6319 ins_pipe(pipe_slow); // XXX
6320 %}
6321
6322 // Store immediate Float value (it is faster than store from XMM register)
6323 instruct storeF0(memory mem, immF0 zero)
6324 %{
6325 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6326 match(Set mem (StoreF mem zero));
6327
6328 ins_cost(25); // XXX
6329 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
6330 ins_encode %{
6331 __ movl($mem$$Address, r12);
6332 %}
6333 ins_pipe(ialu_mem_reg);
6334 %}
6335
6336 instruct storeF_imm(memory mem, immF src)
6337 %{
6338 match(Set mem (StoreF mem src));
6339
6340 ins_cost(50);
6341 format %{ "movl $mem, $src\t# float" %}
6342 ins_encode %{
6343 __ movl($mem$$Address, jint_cast($src$$constant));
6344 %}
6345 ins_pipe(ialu_mem_imm);
6346 %}
6347
6348 // Store Double
6349 instruct storeD(memory mem, regD src)
6350 %{
6351 match(Set mem (StoreD mem src));
6352
6353 ins_cost(95); // XXX
6354 format %{ "movsd $mem, $src\t# double" %}
6355 ins_encode %{
6356 __ movdbl($mem$$Address, $src$$XMMRegister);
6357 %}
6358 ins_pipe(pipe_slow); // XXX
6359 %}
6360
6361 // Store immediate double 0.0 (it is faster than store from XMM register)
6362 instruct storeD0_imm(memory mem, immD0 src)
6363 %{
6364 predicate(!UseCompressedOops || (CompressedOops::base() != NULL));
6365 match(Set mem (StoreD mem src));
6366
6367 ins_cost(50);
6368 format %{ "movq $mem, $src\t# double 0." %}
6369 ins_encode %{
6370 __ movq($mem$$Address, $src$$constant);
6371 %}
6372 ins_pipe(ialu_mem_imm);
6373 %}
6374
6375 instruct storeD0(memory mem, immD0 zero)
6376 %{
6377 predicate(UseCompressedOops && (CompressedOops::base() == NULL));
6378 match(Set mem (StoreD mem zero));
6379
6380 ins_cost(25); // XXX
6381 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
6382 ins_encode %{
6383 __ movq($mem$$Address, r12);
6384 %}
6385 ins_pipe(ialu_mem_reg);
6386 %}
6387
6388 instruct storeSSI(stackSlotI dst, rRegI src)
6389 %{
6390 match(Set dst src);
6391
6392 ins_cost(100);
6393 format %{ "movl $dst, $src\t# int stk" %}
6394 opcode(0x89);
6395 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6396 ins_pipe( ialu_mem_reg );
6397 %}
6398
6399 instruct storeSSL(stackSlotL dst, rRegL src)
6400 %{
6401 match(Set dst src);
6402
6403 ins_cost(100);
6404 format %{ "movq $dst, $src\t# long stk" %}
6405 opcode(0x89);
6406 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6407 ins_pipe(ialu_mem_reg);
6408 %}
6409
6410 instruct storeSSP(stackSlotP dst, rRegP src)
6411 %{
6412 match(Set dst src);
6413
6414 ins_cost(100);
6415 format %{ "movq $dst, $src\t# ptr stk" %}
6416 opcode(0x89);
6417 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6418 ins_pipe(ialu_mem_reg);
6419 %}
6420
6421 instruct storeSSF(stackSlotF dst, regF src)
6422 %{
6423 match(Set dst src);
6424
6425 ins_cost(95); // XXX
6426 format %{ "movss $dst, $src\t# float stk" %}
6427 ins_encode %{
6428 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6429 %}
6430 ins_pipe(pipe_slow); // XXX
6431 %}
6432
6433 instruct storeSSD(stackSlotD dst, regD src)
6434 %{
6435 match(Set dst src);
6436
6437 ins_cost(95); // XXX
6438 format %{ "movsd $dst, $src\t# double stk" %}
6439 ins_encode %{
6440 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6441 %}
6442 ins_pipe(pipe_slow); // XXX
6443 %}
6444
6445 instruct cacheWB(indirect addr)
6446 %{
6447 predicate(VM_Version::supports_data_cache_line_flush());
6448 match(CacheWB addr);
6449
6450 ins_cost(100);
6451 format %{"cache wb $addr" %}
6452 ins_encode %{
6453 assert($addr->index_position() < 0, "should be");
6454 assert($addr$$disp == 0, "should be");
6455 __ cache_wb(Address($addr$$base$$Register, 0));
6456 %}
6457 ins_pipe(pipe_slow); // XXX
6458 %}
6459
6460 instruct cacheWBPreSync()
6461 %{
6462 predicate(VM_Version::supports_data_cache_line_flush());
6463 match(CacheWBPreSync);
6464
6465 ins_cost(100);
6466 format %{"cache wb presync" %}
6467 ins_encode %{
6468 __ cache_wbsync(true);
6469 %}
6470 ins_pipe(pipe_slow); // XXX
6471 %}
6472
6473 instruct cacheWBPostSync()
6474 %{
6475 predicate(VM_Version::supports_data_cache_line_flush());
6476 match(CacheWBPostSync);
6477
6478 ins_cost(100);
6479 format %{"cache wb postsync" %}
6480 ins_encode %{
6481 __ cache_wbsync(false);
6482 %}
6483 ins_pipe(pipe_slow); // XXX
6484 %}
6485
6486 //----------BSWAP Instructions-------------------------------------------------
6487 instruct bytes_reverse_int(rRegI dst) %{
6488 match(Set dst (ReverseBytesI dst));
6489
6490 format %{ "bswapl $dst" %}
6491 ins_encode %{
6492 __ bswapl($dst$$Register);
6493 %}
6494 ins_pipe( ialu_reg );
6495 %}
6496
6497 instruct bytes_reverse_long(rRegL dst) %{
6498 match(Set dst (ReverseBytesL dst));
6499
6500 format %{ "bswapq $dst" %}
6501 ins_encode %{
6502 __ bswapq($dst$$Register);
6503 %}
6504 ins_pipe( ialu_reg);
6505 %}
6506
6507 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6508 match(Set dst (ReverseBytesUS dst));
6509 effect(KILL cr);
6510
6511 format %{ "bswapl $dst\n\t"
6512 "shrl $dst,16\n\t" %}
6513 ins_encode %{
6514 __ bswapl($dst$$Register);
6515 __ shrl($dst$$Register, 16);
6516 %}
6517 ins_pipe( ialu_reg );
6518 %}
6519
6520 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6521 match(Set dst (ReverseBytesS dst));
6522 effect(KILL cr);
6523
6524 format %{ "bswapl $dst\n\t"
6525 "sar $dst,16\n\t" %}
6526 ins_encode %{
6527 __ bswapl($dst$$Register);
6528 __ sarl($dst$$Register, 16);
6529 %}
6530 ins_pipe( ialu_reg );
6531 %}
6532
6533 //---------- Zeros Count Instructions ------------------------------------------
6534
6535 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6536 predicate(UseCountLeadingZerosInstruction);
6537 match(Set dst (CountLeadingZerosI src));
6538 effect(KILL cr);
6539
6540 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6541 ins_encode %{
6542 __ lzcntl($dst$$Register, $src$$Register);
6543 %}
6544 ins_pipe(ialu_reg);
6545 %}
6546
6547 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6548 predicate(!UseCountLeadingZerosInstruction);
6549 match(Set dst (CountLeadingZerosI src));
6550 effect(KILL cr);
6551
6552 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6553 "jnz skip\n\t"
6554 "movl $dst, -1\n"
6555 "skip:\n\t"
6556 "negl $dst\n\t"
6557 "addl $dst, 31" %}
6558 ins_encode %{
6559 Register Rdst = $dst$$Register;
6560 Register Rsrc = $src$$Register;
6561 Label skip;
6562 __ bsrl(Rdst, Rsrc);
6563 __ jccb(Assembler::notZero, skip);
6564 __ movl(Rdst, -1);
6565 __ bind(skip);
6566 __ negl(Rdst);
6567 __ addl(Rdst, BitsPerInt - 1);
6568 %}
6569 ins_pipe(ialu_reg);
6570 %}
6571
6572 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6573 predicate(UseCountLeadingZerosInstruction);
6574 match(Set dst (CountLeadingZerosL src));
6575 effect(KILL cr);
6576
6577 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6578 ins_encode %{
6579 __ lzcntq($dst$$Register, $src$$Register);
6580 %}
6581 ins_pipe(ialu_reg);
6582 %}
6583
6584 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6585 predicate(!UseCountLeadingZerosInstruction);
6586 match(Set dst (CountLeadingZerosL src));
6587 effect(KILL cr);
6588
6589 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6590 "jnz skip\n\t"
6591 "movl $dst, -1\n"
6592 "skip:\n\t"
6593 "negl $dst\n\t"
6594 "addl $dst, 63" %}
6595 ins_encode %{
6596 Register Rdst = $dst$$Register;
6597 Register Rsrc = $src$$Register;
6598 Label skip;
6599 __ bsrq(Rdst, Rsrc);
6600 __ jccb(Assembler::notZero, skip);
6601 __ movl(Rdst, -1);
6602 __ bind(skip);
6603 __ negl(Rdst);
6604 __ addl(Rdst, BitsPerLong - 1);
6605 %}
6606 ins_pipe(ialu_reg);
6607 %}
6608
6609 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6610 predicate(UseCountTrailingZerosInstruction);
6611 match(Set dst (CountTrailingZerosI src));
6612 effect(KILL cr);
6613
6614 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6615 ins_encode %{
6616 __ tzcntl($dst$$Register, $src$$Register);
6617 %}
6618 ins_pipe(ialu_reg);
6619 %}
6620
6621 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6622 predicate(!UseCountTrailingZerosInstruction);
6623 match(Set dst (CountTrailingZerosI src));
6624 effect(KILL cr);
6625
6626 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6627 "jnz done\n\t"
6628 "movl $dst, 32\n"
6629 "done:" %}
6630 ins_encode %{
6631 Register Rdst = $dst$$Register;
6632 Label done;
6633 __ bsfl(Rdst, $src$$Register);
6634 __ jccb(Assembler::notZero, done);
6635 __ movl(Rdst, BitsPerInt);
6636 __ bind(done);
6637 %}
6638 ins_pipe(ialu_reg);
6639 %}
6640
6641 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6642 predicate(UseCountTrailingZerosInstruction);
6643 match(Set dst (CountTrailingZerosL src));
6644 effect(KILL cr);
6645
6646 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6647 ins_encode %{
6648 __ tzcntq($dst$$Register, $src$$Register);
6649 %}
6650 ins_pipe(ialu_reg);
6651 %}
6652
6653 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6654 predicate(!UseCountTrailingZerosInstruction);
6655 match(Set dst (CountTrailingZerosL src));
6656 effect(KILL cr);
6657
6658 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6659 "jnz done\n\t"
6660 "movl $dst, 64\n"
6661 "done:" %}
6662 ins_encode %{
6663 Register Rdst = $dst$$Register;
6664 Label done;
6665 __ bsfq(Rdst, $src$$Register);
6666 __ jccb(Assembler::notZero, done);
6667 __ movl(Rdst, BitsPerLong);
6668 __ bind(done);
6669 %}
6670 ins_pipe(ialu_reg);
6671 %}
6672
6673
6674 //---------- Population Count Instructions -------------------------------------
6675
6676 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6677 predicate(UsePopCountInstruction);
6678 match(Set dst (PopCountI src));
6679 effect(KILL cr);
6680
6681 format %{ "popcnt $dst, $src" %}
6682 ins_encode %{
6683 __ popcntl($dst$$Register, $src$$Register);
6684 %}
6685 ins_pipe(ialu_reg);
6686 %}
6687
6688 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6689 predicate(UsePopCountInstruction);
6690 match(Set dst (PopCountI (LoadI mem)));
6691 effect(KILL cr);
6692
6693 format %{ "popcnt $dst, $mem" %}
6694 ins_encode %{
6695 __ popcntl($dst$$Register, $mem$$Address);
6696 %}
6697 ins_pipe(ialu_reg);
6698 %}
6699
6700 // Note: Long.bitCount(long) returns an int.
6701 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6702 predicate(UsePopCountInstruction);
6703 match(Set dst (PopCountL src));
6704 effect(KILL cr);
6705
6706 format %{ "popcnt $dst, $src" %}
6707 ins_encode %{
6708 __ popcntq($dst$$Register, $src$$Register);
6709 %}
6710 ins_pipe(ialu_reg);
6711 %}
6712
6713 // Note: Long.bitCount(long) returns an int.
6714 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6715 predicate(UsePopCountInstruction);
6716 match(Set dst (PopCountL (LoadL mem)));
6717 effect(KILL cr);
6718
6719 format %{ "popcnt $dst, $mem" %}
6720 ins_encode %{
6721 __ popcntq($dst$$Register, $mem$$Address);
6722 %}
6723 ins_pipe(ialu_reg);
6724 %}
6725
6726
6727 //----------MemBar Instructions-----------------------------------------------
6728 // Memory barrier flavors
6729
6730 instruct membar_acquire()
6731 %{
6732 match(MemBarAcquire);
6733 match(LoadFence);
6734 ins_cost(0);
6735
6736 size(0);
6737 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6738 ins_encode();
6739 ins_pipe(empty);
6740 %}
6741
6742 instruct membar_acquire_lock()
6743 %{
6744 match(MemBarAcquireLock);
6745 ins_cost(0);
6746
6747 size(0);
6748 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6749 ins_encode();
6750 ins_pipe(empty);
6751 %}
6752
6753 instruct membar_release()
6754 %{
6755 match(MemBarRelease);
6756 match(StoreFence);
6757 ins_cost(0);
6758
6759 size(0);
6760 format %{ "MEMBAR-release ! (empty encoding)" %}
6761 ins_encode();
6762 ins_pipe(empty);
6763 %}
6764
6765 instruct membar_release_lock()
6766 %{
6767 match(MemBarReleaseLock);
6768 ins_cost(0);
6769
6770 size(0);
6771 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6772 ins_encode();
6773 ins_pipe(empty);
6774 %}
6775
6776 instruct membar_volatile(rFlagsReg cr) %{
6777 match(MemBarVolatile);
6778 effect(KILL cr);
6779 ins_cost(400);
6780
6781 format %{
6782 $$template
6783 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6784 %}
6785 ins_encode %{
6786 __ membar(Assembler::StoreLoad);
6787 %}
6788 ins_pipe(pipe_slow);
6789 %}
6790
6791 instruct unnecessary_membar_volatile()
6792 %{
6793 match(MemBarVolatile);
6794 predicate(Matcher::post_store_load_barrier(n));
6795 ins_cost(0);
6796
6797 size(0);
6798 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6799 ins_encode();
6800 ins_pipe(empty);
6801 %}
6802
6803 instruct membar_storestore() %{
6804 match(MemBarStoreStore);
6805 ins_cost(0);
6806
6807 size(0);
6808 format %{ "MEMBAR-storestore (empty encoding)" %}
6809 ins_encode( );
6810 ins_pipe(empty);
6811 %}
6812
6813 //----------Move Instructions--------------------------------------------------
6814
6815 instruct castX2P(rRegP dst, rRegL src)
6816 %{
6817 match(Set dst (CastX2P src));
6818
6819 format %{ "movq $dst, $src\t# long->ptr" %}
6820 ins_encode %{
6821 if ($dst$$reg != $src$$reg) {
6822 __ movptr($dst$$Register, $src$$Register);
6823 }
6824 %}
6825 ins_pipe(ialu_reg_reg); // XXX
6826 %}
6827
6828 instruct castN2X(rRegL dst, rRegN src)
6829 %{
6830 match(Set dst (CastP2X src));
6831
6832 format %{ "movq $dst, $src\t# ptr -> long" %}
6833 ins_encode %{
6834 if ($dst$$reg != $src$$reg) {
6835 __ movptr($dst$$Register, $src$$Register);
6836 }
6837 %}
6838 ins_pipe(ialu_reg_reg); // XXX
6839 %}
6840
6841 instruct castP2X(rRegL dst, rRegP src)
6842 %{
6843 match(Set dst (CastP2X src));
6844
6845 format %{ "movq $dst, $src\t# ptr -> long" %}
6846 ins_encode %{
6847 if ($dst$$reg != $src$$reg) {
6848 __ movptr($dst$$Register, $src$$Register);
6849 }
6850 %}
6851 ins_pipe(ialu_reg_reg); // XXX
6852 %}
6853
6854 // Convert oop into int for vectors alignment masking
6855 instruct convP2I(rRegI dst, rRegP src)
6856 %{
6857 match(Set dst (ConvL2I (CastP2X src)));
6858
6859 format %{ "movl $dst, $src\t# ptr -> int" %}
6860 ins_encode %{
6861 __ movl($dst$$Register, $src$$Register);
6862 %}
6863 ins_pipe(ialu_reg_reg); // XXX
6864 %}
6865
6866 // Convert compressed oop into int for vectors alignment masking
6867 // in case of 32bit oops (heap < 4Gb).
6868 instruct convN2I(rRegI dst, rRegN src)
6869 %{
6870 predicate(CompressedOops::shift() == 0);
6871 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6872
6873 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6874 ins_encode %{
6875 __ movl($dst$$Register, $src$$Register);
6876 %}
6877 ins_pipe(ialu_reg_reg); // XXX
6878 %}
6879
6880 // Convert oop pointer into compressed form
6881 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6882 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6883 match(Set dst (EncodeP src));
6884 effect(KILL cr);
6885 format %{ "encode_heap_oop $dst,$src" %}
6886 ins_encode %{
6887 Register s = $src$$Register;
6888 Register d = $dst$$Register;
6889 if (s != d) {
6890 __ movq(d, s);
6891 }
6892 __ encode_heap_oop(d);
6893 %}
6894 ins_pipe(ialu_reg_long);
6895 %}
6896
6897 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6898 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6899 match(Set dst (EncodeP src));
6900 effect(KILL cr);
6901 format %{ "encode_heap_oop_not_null $dst,$src" %}
6902 ins_encode %{
6903 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6904 %}
6905 ins_pipe(ialu_reg_long);
6906 %}
6907
6908 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6909 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6910 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6911 match(Set dst (DecodeN src));
6912 effect(KILL cr);
6913 format %{ "decode_heap_oop $dst,$src" %}
6914 ins_encode %{
6915 Register s = $src$$Register;
6916 Register d = $dst$$Register;
6917 if (s != d) {
6918 __ movq(d, s);
6919 }
6920 __ decode_heap_oop(d);
6921 %}
6922 ins_pipe(ialu_reg_long);
6923 %}
6924
6925 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6926 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6927 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6928 match(Set dst (DecodeN src));
6929 effect(KILL cr);
6930 format %{ "decode_heap_oop_not_null $dst,$src" %}
6931 ins_encode %{
6932 Register s = $src$$Register;
6933 Register d = $dst$$Register;
6934 if (s != d) {
6935 __ decode_heap_oop_not_null(d, s);
6936 } else {
6937 __ decode_heap_oop_not_null(d);
6938 }
6939 %}
6940 ins_pipe(ialu_reg_long);
6941 %}
6942
6943 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6944 match(Set dst (EncodePKlass src));
6945 effect(TEMP dst, KILL cr);
6946 format %{ "encode_and_move_klass_not_null $dst,$src" %}
6947 ins_encode %{
6948 __ encode_and_move_klass_not_null($dst$$Register, $src$$Register);
6949 %}
6950 ins_pipe(ialu_reg_long);
6951 %}
6952
6953 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6954 match(Set dst (DecodeNKlass src));
6955 effect(TEMP dst, KILL cr);
6956 format %{ "decode_and_move_klass_not_null $dst,$src" %}
6957 ins_encode %{
6958 __ decode_and_move_klass_not_null($dst$$Register, $src$$Register);
6959 %}
6960 ins_pipe(ialu_reg_long);
6961 %}
6962
6963 //----------Conditional Move---------------------------------------------------
6964 // Jump
6965 // dummy instruction for generating temp registers
6966 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6967 match(Jump (LShiftL switch_val shift));
6968 ins_cost(350);
6969 predicate(false);
6970 effect(TEMP dest);
6971
6972 format %{ "leaq $dest, [$constantaddress]\n\t"
6973 "jmp [$dest + $switch_val << $shift]\n\t" %}
6974 ins_encode %{
6975 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6976 // to do that and the compiler is using that register as one it can allocate.
6977 // So we build it all by hand.
6978 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6979 // ArrayAddress dispatch(table, index);
6980 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6981 __ lea($dest$$Register, $constantaddress);
6982 __ jmp(dispatch);
6983 %}
6984 ins_pipe(pipe_jmp);
6985 %}
6986
6987 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6988 match(Jump (AddL (LShiftL switch_val shift) offset));
6989 ins_cost(350);
6990 effect(TEMP dest);
6991
6992 format %{ "leaq $dest, [$constantaddress]\n\t"
6993 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6994 ins_encode %{
6995 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6996 // to do that and the compiler is using that register as one it can allocate.
6997 // So we build it all by hand.
6998 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6999 // ArrayAddress dispatch(table, index);
7000 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
7001 __ lea($dest$$Register, $constantaddress);
7002 __ jmp(dispatch);
7003 %}
7004 ins_pipe(pipe_jmp);
7005 %}
7006
7007 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
7008 match(Jump switch_val);
7009 ins_cost(350);
7010 effect(TEMP dest);
7011
7012 format %{ "leaq $dest, [$constantaddress]\n\t"
7013 "jmp [$dest + $switch_val]\n\t" %}
7014 ins_encode %{
7015 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
7016 // to do that and the compiler is using that register as one it can allocate.
7017 // So we build it all by hand.
7018 // Address index(noreg, switch_reg, Address::times_1);
7019 // ArrayAddress dispatch(table, index);
7020 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
7021 __ lea($dest$$Register, $constantaddress);
7022 __ jmp(dispatch);
7023 %}
7024 ins_pipe(pipe_jmp);
7025 %}
7026
7027 // Conditional move
7028 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
7029 %{
7030 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7031
7032 ins_cost(200); // XXX
7033 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7034 ins_encode %{
7035 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7036 %}
7037 ins_pipe(pipe_cmov_reg);
7038 %}
7039
7040 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
7041 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7042
7043 ins_cost(200); // XXX
7044 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7045 ins_encode %{
7046 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7047 %}
7048 ins_pipe(pipe_cmov_reg);
7049 %}
7050
7051 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
7052 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
7053 ins_cost(200);
7054 expand %{
7055 cmovI_regU(cop, cr, dst, src);
7056 %}
7057 %}
7058
7059 // Conditional move
7060 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
7061 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7062
7063 ins_cost(250); // XXX
7064 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
7065 ins_encode %{
7066 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
7067 %}
7068 ins_pipe(pipe_cmov_mem);
7069 %}
7070
7071 // Conditional move
7072 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
7073 %{
7074 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7075
7076 ins_cost(250); // XXX
7077 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
7078 ins_encode %{
7079 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
7080 %}
7081 ins_pipe(pipe_cmov_mem);
7082 %}
7083
7084 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
7085 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
7086 ins_cost(250);
7087 expand %{
7088 cmovI_memU(cop, cr, dst, src);
7089 %}
7090 %}
7091
7092 // Conditional move
7093 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
7094 %{
7095 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7096
7097 ins_cost(200); // XXX
7098 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
7099 ins_encode %{
7100 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7101 %}
7102 ins_pipe(pipe_cmov_reg);
7103 %}
7104
7105 // Conditional move
7106 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
7107 %{
7108 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7109
7110 ins_cost(200); // XXX
7111 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
7112 ins_encode %{
7113 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7114 %}
7115 ins_pipe(pipe_cmov_reg);
7116 %}
7117
7118 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
7119 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
7120 ins_cost(200);
7121 expand %{
7122 cmovN_regU(cop, cr, dst, src);
7123 %}
7124 %}
7125
7126 // Conditional move
7127 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
7128 %{
7129 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7130
7131 ins_cost(200); // XXX
7132 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
7133 ins_encode %{
7134 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7135 %}
7136 ins_pipe(pipe_cmov_reg); // XXX
7137 %}
7138
7139 // Conditional move
7140 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
7141 %{
7142 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7143
7144 ins_cost(200); // XXX
7145 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
7146 ins_encode %{
7147 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7148 %}
7149 ins_pipe(pipe_cmov_reg); // XXX
7150 %}
7151
7152 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
7153 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
7154 ins_cost(200);
7155 expand %{
7156 cmovP_regU(cop, cr, dst, src);
7157 %}
7158 %}
7159
7160 // DISABLED: Requires the ADLC to emit a bottom_type call that
7161 // correctly meets the two pointer arguments; one is an incoming
7162 // register but the other is a memory operand. ALSO appears to
7163 // be buggy with implicit null checks.
7164 //
7165 //// Conditional move
7166 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
7167 //%{
7168 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7169 // ins_cost(250);
7170 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7171 // opcode(0x0F,0x40);
7172 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7173 // ins_pipe( pipe_cmov_mem );
7174 //%}
7175 //
7176 //// Conditional move
7177 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
7178 //%{
7179 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
7180 // ins_cost(250);
7181 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
7182 // opcode(0x0F,0x40);
7183 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
7184 // ins_pipe( pipe_cmov_mem );
7185 //%}
7186
7187 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
7188 %{
7189 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7190
7191 ins_cost(200); // XXX
7192 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7193 ins_encode %{
7194 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7195 %}
7196 ins_pipe(pipe_cmov_reg); // XXX
7197 %}
7198
7199 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
7200 %{
7201 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7202
7203 ins_cost(200); // XXX
7204 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
7205 ins_encode %{
7206 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
7207 %}
7208 ins_pipe(pipe_cmov_mem); // XXX
7209 %}
7210
7211 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
7212 %{
7213 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7214
7215 ins_cost(200); // XXX
7216 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7217 ins_encode %{
7218 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
7219 %}
7220 ins_pipe(pipe_cmov_reg); // XXX
7221 %}
7222
7223 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
7224 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
7225 ins_cost(200);
7226 expand %{
7227 cmovL_regU(cop, cr, dst, src);
7228 %}
7229 %}
7230
7231 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
7232 %{
7233 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7234
7235 ins_cost(200); // XXX
7236 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
7237 ins_encode %{
7238 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
7239 %}
7240 ins_pipe(pipe_cmov_mem); // XXX
7241 %}
7242
7243 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
7244 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
7245 ins_cost(200);
7246 expand %{
7247 cmovL_memU(cop, cr, dst, src);
7248 %}
7249 %}
7250
7251 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
7252 %{
7253 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7254
7255 ins_cost(200); // XXX
7256 format %{ "jn$cop skip\t# signed cmove float\n\t"
7257 "movss $dst, $src\n"
7258 "skip:" %}
7259 ins_encode %{
7260 Label Lskip;
7261 // Invert sense of branch from sense of CMOV
7262 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7263 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7264 __ bind(Lskip);
7265 %}
7266 ins_pipe(pipe_slow);
7267 %}
7268
7269 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
7270 // %{
7271 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
7272
7273 // ins_cost(200); // XXX
7274 // format %{ "jn$cop skip\t# signed cmove float\n\t"
7275 // "movss $dst, $src\n"
7276 // "skip:" %}
7277 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
7278 // ins_pipe(pipe_slow);
7279 // %}
7280
7281 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
7282 %{
7283 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7284
7285 ins_cost(200); // XXX
7286 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
7287 "movss $dst, $src\n"
7288 "skip:" %}
7289 ins_encode %{
7290 Label Lskip;
7291 // Invert sense of branch from sense of CMOV
7292 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7293 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
7294 __ bind(Lskip);
7295 %}
7296 ins_pipe(pipe_slow);
7297 %}
7298
7299 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
7300 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
7301 ins_cost(200);
7302 expand %{
7303 cmovF_regU(cop, cr, dst, src);
7304 %}
7305 %}
7306
7307 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
7308 %{
7309 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7310
7311 ins_cost(200); // XXX
7312 format %{ "jn$cop skip\t# signed cmove double\n\t"
7313 "movsd $dst, $src\n"
7314 "skip:" %}
7315 ins_encode %{
7316 Label Lskip;
7317 // Invert sense of branch from sense of CMOV
7318 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7319 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7320 __ bind(Lskip);
7321 %}
7322 ins_pipe(pipe_slow);
7323 %}
7324
7325 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
7326 %{
7327 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7328
7329 ins_cost(200); // XXX
7330 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
7331 "movsd $dst, $src\n"
7332 "skip:" %}
7333 ins_encode %{
7334 Label Lskip;
7335 // Invert sense of branch from sense of CMOV
7336 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
7337 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
7338 __ bind(Lskip);
7339 %}
7340 ins_pipe(pipe_slow);
7341 %}
7342
7343 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
7344 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
7345 ins_cost(200);
7346 expand %{
7347 cmovD_regU(cop, cr, dst, src);
7348 %}
7349 %}
7350
7351 //----------Arithmetic Instructions--------------------------------------------
7352 //----------Addition Instructions----------------------------------------------
7353
7354 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7355 %{
7356 match(Set dst (AddI dst src));
7357 effect(KILL cr);
7358
7359 format %{ "addl $dst, $src\t# int" %}
7360 ins_encode %{
7361 __ addl($dst$$Register, $src$$Register);
7362 %}
7363 ins_pipe(ialu_reg_reg);
7364 %}
7365
7366 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7367 %{
7368 match(Set dst (AddI dst src));
7369 effect(KILL cr);
7370
7371 format %{ "addl $dst, $src\t# int" %}
7372 ins_encode %{
7373 __ addl($dst$$Register, $src$$constant);
7374 %}
7375 ins_pipe( ialu_reg );
7376 %}
7377
7378 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7379 %{
7380 match(Set dst (AddI dst (LoadI src)));
7381 effect(KILL cr);
7382
7383 ins_cost(125); // XXX
7384 format %{ "addl $dst, $src\t# int" %}
7385 ins_encode %{
7386 __ addl($dst$$Register, $src$$Address);
7387 %}
7388 ins_pipe(ialu_reg_mem);
7389 %}
7390
7391 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7392 %{
7393 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7394 effect(KILL cr);
7395
7396 ins_cost(150); // XXX
7397 format %{ "addl $dst, $src\t# int" %}
7398 ins_encode %{
7399 __ addl($dst$$Address, $src$$Register);
7400 %}
7401 ins_pipe(ialu_mem_reg);
7402 %}
7403
7404 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
7405 %{
7406 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7407 effect(KILL cr);
7408
7409 ins_cost(125); // XXX
7410 format %{ "addl $dst, $src\t# int" %}
7411 ins_encode %{
7412 __ addl($dst$$Address, $src$$constant);
7413 %}
7414 ins_pipe(ialu_mem_imm);
7415 %}
7416
7417 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
7418 %{
7419 predicate(UseIncDec);
7420 match(Set dst (AddI dst src));
7421 effect(KILL cr);
7422
7423 format %{ "incl $dst\t# int" %}
7424 ins_encode %{
7425 __ incrementl($dst$$Register);
7426 %}
7427 ins_pipe(ialu_reg);
7428 %}
7429
7430 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
7431 %{
7432 predicate(UseIncDec);
7433 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7434 effect(KILL cr);
7435
7436 ins_cost(125); // XXX
7437 format %{ "incl $dst\t# int" %}
7438 ins_encode %{
7439 __ incrementl($dst$$Address);
7440 %}
7441 ins_pipe(ialu_mem_imm);
7442 %}
7443
7444 // XXX why does that use AddI
7445 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
7446 %{
7447 predicate(UseIncDec);
7448 match(Set dst (AddI dst src));
7449 effect(KILL cr);
7450
7451 format %{ "decl $dst\t# int" %}
7452 ins_encode %{
7453 __ decrementl($dst$$Register);
7454 %}
7455 ins_pipe(ialu_reg);
7456 %}
7457
7458 // XXX why does that use AddI
7459 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7460 %{
7461 predicate(UseIncDec);
7462 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7463 effect(KILL cr);
7464
7465 ins_cost(125); // XXX
7466 format %{ "decl $dst\t# int" %}
7467 ins_encode %{
7468 __ decrementl($dst$$Address);
7469 %}
7470 ins_pipe(ialu_mem_imm);
7471 %}
7472
7473 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7474 %{
7475 match(Set dst (AddI src0 src1));
7476
7477 ins_cost(110);
7478 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7479 ins_encode %{
7480 __ leal($dst$$Register, Address($src0$$Register, $src1$$constant));
7481 %}
7482 ins_pipe(ialu_reg_reg);
7483 %}
7484
7485 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7486 %{
7487 match(Set dst (AddL dst src));
7488 effect(KILL cr);
7489
7490 format %{ "addq $dst, $src\t# long" %}
7491 ins_encode %{
7492 __ addq($dst$$Register, $src$$Register);
7493 %}
7494 ins_pipe(ialu_reg_reg);
7495 %}
7496
7497 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7498 %{
7499 match(Set dst (AddL dst src));
7500 effect(KILL cr);
7501
7502 format %{ "addq $dst, $src\t# long" %}
7503 ins_encode %{
7504 __ addq($dst$$Register, $src$$constant);
7505 %}
7506 ins_pipe( ialu_reg );
7507 %}
7508
7509 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7510 %{
7511 match(Set dst (AddL dst (LoadL src)));
7512 effect(KILL cr);
7513
7514 ins_cost(125); // XXX
7515 format %{ "addq $dst, $src\t# long" %}
7516 ins_encode %{
7517 __ addq($dst$$Register, $src$$Address);
7518 %}
7519 ins_pipe(ialu_reg_mem);
7520 %}
7521
7522 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7523 %{
7524 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7525 effect(KILL cr);
7526
7527 ins_cost(150); // XXX
7528 format %{ "addq $dst, $src\t# long" %}
7529 ins_encode %{
7530 __ addq($dst$$Address, $src$$Register);
7531 %}
7532 ins_pipe(ialu_mem_reg);
7533 %}
7534
7535 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7536 %{
7537 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7538 effect(KILL cr);
7539
7540 ins_cost(125); // XXX
7541 format %{ "addq $dst, $src\t# long" %}
7542 ins_encode %{
7543 __ addq($dst$$Address, $src$$constant);
7544 %}
7545 ins_pipe(ialu_mem_imm);
7546 %}
7547
7548 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7549 %{
7550 predicate(UseIncDec);
7551 match(Set dst (AddL dst src));
7552 effect(KILL cr);
7553
7554 format %{ "incq $dst\t# long" %}
7555 ins_encode %{
7556 __ incrementq($dst$$Register);
7557 %}
7558 ins_pipe(ialu_reg);
7559 %}
7560
7561 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7562 %{
7563 predicate(UseIncDec);
7564 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7565 effect(KILL cr);
7566
7567 ins_cost(125); // XXX
7568 format %{ "incq $dst\t# long" %}
7569 ins_encode %{
7570 __ incrementq($dst$$Address);
7571 %}
7572 ins_pipe(ialu_mem_imm);
7573 %}
7574
7575 // XXX why does that use AddL
7576 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7577 %{
7578 predicate(UseIncDec);
7579 match(Set dst (AddL dst src));
7580 effect(KILL cr);
7581
7582 format %{ "decq $dst\t# long" %}
7583 ins_encode %{
7584 __ decrementq($dst$$Register);
7585 %}
7586 ins_pipe(ialu_reg);
7587 %}
7588
7589 // XXX why does that use AddL
7590 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7591 %{
7592 predicate(UseIncDec);
7593 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7594 effect(KILL cr);
7595
7596 ins_cost(125); // XXX
7597 format %{ "decq $dst\t# long" %}
7598 ins_encode %{
7599 __ decrementq($dst$$Address);
7600 %}
7601 ins_pipe(ialu_mem_imm);
7602 %}
7603
7604 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7605 %{
7606 match(Set dst (AddL src0 src1));
7607
7608 ins_cost(110);
7609 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7610 ins_encode %{
7611 __ leaq($dst$$Register, Address($src0$$Register, $src1$$constant));
7612 %}
7613 ins_pipe(ialu_reg_reg);
7614 %}
7615
7616 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7617 %{
7618 match(Set dst (AddP dst src));
7619 effect(KILL cr);
7620
7621 format %{ "addq $dst, $src\t# ptr" %}
7622 ins_encode %{
7623 __ addq($dst$$Register, $src$$Register);
7624 %}
7625 ins_pipe(ialu_reg_reg);
7626 %}
7627
7628 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7629 %{
7630 match(Set dst (AddP dst src));
7631 effect(KILL cr);
7632
7633 format %{ "addq $dst, $src\t# ptr" %}
7634 ins_encode %{
7635 __ addq($dst$$Register, $src$$constant);
7636 %}
7637 ins_pipe( ialu_reg );
7638 %}
7639
7640 // XXX addP mem ops ????
7641
7642 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7643 %{
7644 match(Set dst (AddP src0 src1));
7645
7646 ins_cost(110);
7647 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7648 ins_encode %{
7649 __ leaq($dst$$Register, Address($src0$$Register, $src1$$constant));
7650 %}
7651 ins_pipe(ialu_reg_reg);
7652 %}
7653
7654 instruct checkCastPP(rRegP dst)
7655 %{
7656 match(Set dst (CheckCastPP dst));
7657
7658 size(0);
7659 format %{ "# checkcastPP of $dst" %}
7660 ins_encode(/* empty encoding */);
7661 ins_pipe(empty);
7662 %}
7663
7664 instruct castPP(rRegP dst)
7665 %{
7666 match(Set dst (CastPP dst));
7667
7668 size(0);
7669 format %{ "# castPP of $dst" %}
7670 ins_encode(/* empty encoding */);
7671 ins_pipe(empty);
7672 %}
7673
7674 instruct castII(rRegI dst)
7675 %{
7676 match(Set dst (CastII dst));
7677
7678 size(0);
7679 format %{ "# castII of $dst" %}
7680 ins_encode(/* empty encoding */);
7681 ins_cost(0);
7682 ins_pipe(empty);
7683 %}
7684
7685 instruct castLL(rRegL dst)
7686 %{
7687 match(Set dst (CastLL dst));
7688
7689 size(0);
7690 format %{ "# castLL of $dst" %}
7691 ins_encode(/* empty encoding */);
7692 ins_cost(0);
7693 ins_pipe(empty);
7694 %}
7695
7696 instruct castFF(regF dst)
7697 %{
7698 match(Set dst (CastFF dst));
7699
7700 size(0);
7701 format %{ "# castFF of $dst" %}
7702 ins_encode(/* empty encoding */);
7703 ins_cost(0);
7704 ins_pipe(empty);
7705 %}
7706
7707 instruct castDD(regD dst)
7708 %{
7709 match(Set dst (CastDD dst));
7710
7711 size(0);
7712 format %{ "# castDD of $dst" %}
7713 ins_encode(/* empty encoding */);
7714 ins_cost(0);
7715 ins_pipe(empty);
7716 %}
7717
7718 // LoadP-locked same as a regular LoadP when used with compare-swap
7719 instruct loadPLocked(rRegP dst, memory mem)
7720 %{
7721 match(Set dst (LoadPLocked mem));
7722
7723 ins_cost(125); // XXX
7724 format %{ "movq $dst, $mem\t# ptr locked" %}
7725 ins_encode %{
7726 __ movq($dst$$Register, $mem$$Address);
7727 %}
7728 ins_pipe(ialu_reg_mem); // XXX
7729 %}
7730
7731 // Conditional-store of the updated heap-top.
7732 // Used during allocation of the shared heap.
7733 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7734
7735 instruct storePConditional(memory heap_top_ptr,
7736 rax_RegP oldval, rRegP newval,
7737 rFlagsReg cr)
7738 %{
7739 predicate(n->as_LoadStore()->barrier_data() == 0);
7740 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7741
7742 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7743 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7744 ins_encode %{
7745 __ lock();
7746 __ cmpxchgq($newval$$Register, $heap_top_ptr$$Address);
7747 %}
7748 ins_pipe(pipe_cmpxchg);
7749 %}
7750
7751 // Conditional-store of an int value.
7752 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7753 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7754 %{
7755 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7756 effect(KILL oldval);
7757
7758 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7759 opcode(0x0F, 0xB1);
7760 ins_encode(lock_prefix,
7761 REX_reg_mem(newval, mem),
7762 OpcP, OpcS,
7763 reg_mem(newval, mem));
7764 ins_pipe(pipe_cmpxchg);
7765 %}
7766
7767 // Conditional-store of a long value.
7768 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7769 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7770 %{
7771 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7772 effect(KILL oldval);
7773
7774 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7775 ins_encode %{
7776 __ lock();
7777 __ cmpxchgq($newval$$Register, $mem$$Address);
7778 %}
7779 ins_pipe(pipe_cmpxchg);
7780 %}
7781
7782
7783 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7784 instruct compareAndSwapP(rRegI res,
7785 memory mem_ptr,
7786 rax_RegP oldval, rRegP newval,
7787 rFlagsReg cr)
7788 %{
7789 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
7790 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7791 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7792 effect(KILL cr, KILL oldval);
7793
7794 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7795 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7796 "sete $res\n\t"
7797 "movzbl $res, $res" %}
7798 ins_encode %{
7799 __ lock();
7800 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7801 __ sete($res$$Register);
7802 __ movzbl($res$$Register, $res$$Register);
7803 %}
7804 ins_pipe( pipe_cmpxchg );
7805 %}
7806
7807 instruct compareAndSwapL(rRegI res,
7808 memory mem_ptr,
7809 rax_RegL oldval, rRegL newval,
7810 rFlagsReg cr)
7811 %{
7812 predicate(VM_Version::supports_cx8());
7813 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7814 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7815 effect(KILL cr, KILL oldval);
7816
7817 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7818 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7819 "sete $res\n\t"
7820 "movzbl $res, $res" %}
7821 ins_encode %{
7822 __ lock();
7823 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7824 __ sete($res$$Register);
7825 __ movzbl($res$$Register, $res$$Register);
7826 %}
7827 ins_pipe( pipe_cmpxchg );
7828 %}
7829
7830 instruct compareAndSwapI(rRegI res,
7831 memory mem_ptr,
7832 rax_RegI oldval, rRegI newval,
7833 rFlagsReg cr)
7834 %{
7835 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7836 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7837 effect(KILL cr, KILL oldval);
7838
7839 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7840 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7841 "sete $res\n\t"
7842 "movzbl $res, $res" %}
7843 ins_encode %{
7844 __ lock();
7845 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7846 __ sete($res$$Register);
7847 __ movzbl($res$$Register, $res$$Register);
7848 %}
7849 ins_pipe( pipe_cmpxchg );
7850 %}
7851
7852 instruct compareAndSwapB(rRegI res,
7853 memory mem_ptr,
7854 rax_RegI oldval, rRegI newval,
7855 rFlagsReg cr)
7856 %{
7857 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7858 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7859 effect(KILL cr, KILL oldval);
7860
7861 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7862 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7863 "sete $res\n\t"
7864 "movzbl $res, $res" %}
7865 ins_encode %{
7866 __ lock();
7867 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7868 __ sete($res$$Register);
7869 __ movzbl($res$$Register, $res$$Register);
7870 %}
7871 ins_pipe( pipe_cmpxchg );
7872 %}
7873
7874 instruct compareAndSwapS(rRegI res,
7875 memory mem_ptr,
7876 rax_RegI oldval, rRegI newval,
7877 rFlagsReg cr)
7878 %{
7879 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7880 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7881 effect(KILL cr, KILL oldval);
7882
7883 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7884 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7885 "sete $res\n\t"
7886 "movzbl $res, $res" %}
7887 ins_encode %{
7888 __ lock();
7889 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7890 __ sete($res$$Register);
7891 __ movzbl($res$$Register, $res$$Register);
7892 %}
7893 ins_pipe( pipe_cmpxchg );
7894 %}
7895
7896 instruct compareAndSwapN(rRegI res,
7897 memory mem_ptr,
7898 rax_RegN oldval, rRegN newval,
7899 rFlagsReg cr) %{
7900 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7901 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7902 effect(KILL cr, KILL oldval);
7903
7904 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7905 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7906 "sete $res\n\t"
7907 "movzbl $res, $res" %}
7908 ins_encode %{
7909 __ lock();
7910 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7911 __ sete($res$$Register);
7912 __ movzbl($res$$Register, $res$$Register);
7913 %}
7914 ins_pipe( pipe_cmpxchg );
7915 %}
7916
7917 instruct compareAndExchangeB(
7918 memory mem_ptr,
7919 rax_RegI oldval, rRegI newval,
7920 rFlagsReg cr)
7921 %{
7922 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7923 effect(KILL cr);
7924
7925 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7926 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7927 ins_encode %{
7928 __ lock();
7929 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7930 %}
7931 ins_pipe( pipe_cmpxchg );
7932 %}
7933
7934 instruct compareAndExchangeS(
7935 memory mem_ptr,
7936 rax_RegI oldval, rRegI newval,
7937 rFlagsReg cr)
7938 %{
7939 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7940 effect(KILL cr);
7941
7942 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7943 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7944 ins_encode %{
7945 __ lock();
7946 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7947 %}
7948 ins_pipe( pipe_cmpxchg );
7949 %}
7950
7951 instruct compareAndExchangeI(
7952 memory mem_ptr,
7953 rax_RegI oldval, rRegI newval,
7954 rFlagsReg cr)
7955 %{
7956 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7957 effect(KILL cr);
7958
7959 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7960 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7961 ins_encode %{
7962 __ lock();
7963 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7964 %}
7965 ins_pipe( pipe_cmpxchg );
7966 %}
7967
7968 instruct compareAndExchangeL(
7969 memory mem_ptr,
7970 rax_RegL oldval, rRegL newval,
7971 rFlagsReg cr)
7972 %{
7973 predicate(VM_Version::supports_cx8());
7974 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7975 effect(KILL cr);
7976
7977 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7978 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7979 ins_encode %{
7980 __ lock();
7981 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7982 %}
7983 ins_pipe( pipe_cmpxchg );
7984 %}
7985
7986 instruct compareAndExchangeN(
7987 memory mem_ptr,
7988 rax_RegN oldval, rRegN newval,
7989 rFlagsReg cr) %{
7990 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7991 effect(KILL cr);
7992
7993 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7994 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7995 ins_encode %{
7996 __ lock();
7997 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7998 %}
7999 ins_pipe( pipe_cmpxchg );
8000 %}
8001
8002 instruct compareAndExchangeP(
8003 memory mem_ptr,
8004 rax_RegP oldval, rRegP newval,
8005 rFlagsReg cr)
8006 %{
8007 predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
8008 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
8009 effect(KILL cr);
8010
8011 format %{ "cmpxchgq $mem_ptr,$newval\t# "
8012 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
8013 ins_encode %{
8014 __ lock();
8015 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
8016 %}
8017 ins_pipe( pipe_cmpxchg );
8018 %}
8019
8020 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8021 predicate(n->as_LoadStore()->result_not_used());
8022 match(Set dummy (GetAndAddB mem add));
8023 effect(KILL cr);
8024 format %{ "ADDB [$mem],$add" %}
8025 ins_encode %{
8026 __ lock();
8027 __ addb($mem$$Address, $add$$constant);
8028 %}
8029 ins_pipe( pipe_cmpxchg );
8030 %}
8031
8032 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
8033 match(Set newval (GetAndAddB mem newval));
8034 effect(KILL cr);
8035 format %{ "XADDB [$mem],$newval" %}
8036 ins_encode %{
8037 __ lock();
8038 __ xaddb($mem$$Address, $newval$$Register);
8039 %}
8040 ins_pipe( pipe_cmpxchg );
8041 %}
8042
8043 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8044 predicate(n->as_LoadStore()->result_not_used());
8045 match(Set dummy (GetAndAddS mem add));
8046 effect(KILL cr);
8047 format %{ "ADDW [$mem],$add" %}
8048 ins_encode %{
8049 __ lock();
8050 __ addw($mem$$Address, $add$$constant);
8051 %}
8052 ins_pipe( pipe_cmpxchg );
8053 %}
8054
8055 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
8056 match(Set newval (GetAndAddS mem newval));
8057 effect(KILL cr);
8058 format %{ "XADDW [$mem],$newval" %}
8059 ins_encode %{
8060 __ lock();
8061 __ xaddw($mem$$Address, $newval$$Register);
8062 %}
8063 ins_pipe( pipe_cmpxchg );
8064 %}
8065
8066 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
8067 predicate(n->as_LoadStore()->result_not_used());
8068 match(Set dummy (GetAndAddI mem add));
8069 effect(KILL cr);
8070 format %{ "ADDL [$mem],$add" %}
8071 ins_encode %{
8072 __ lock();
8073 __ addl($mem$$Address, $add$$constant);
8074 %}
8075 ins_pipe( pipe_cmpxchg );
8076 %}
8077
8078 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
8079 match(Set newval (GetAndAddI mem newval));
8080 effect(KILL cr);
8081 format %{ "XADDL [$mem],$newval" %}
8082 ins_encode %{
8083 __ lock();
8084 __ xaddl($mem$$Address, $newval$$Register);
8085 %}
8086 ins_pipe( pipe_cmpxchg );
8087 %}
8088
8089 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
8090 predicate(n->as_LoadStore()->result_not_used());
8091 match(Set dummy (GetAndAddL mem add));
8092 effect(KILL cr);
8093 format %{ "ADDQ [$mem],$add" %}
8094 ins_encode %{
8095 __ lock();
8096 __ addq($mem$$Address, $add$$constant);
8097 %}
8098 ins_pipe( pipe_cmpxchg );
8099 %}
8100
8101 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
8102 match(Set newval (GetAndAddL mem newval));
8103 effect(KILL cr);
8104 format %{ "XADDQ [$mem],$newval" %}
8105 ins_encode %{
8106 __ lock();
8107 __ xaddq($mem$$Address, $newval$$Register);
8108 %}
8109 ins_pipe( pipe_cmpxchg );
8110 %}
8111
8112 instruct xchgB( memory mem, rRegI newval) %{
8113 match(Set newval (GetAndSetB mem newval));
8114 format %{ "XCHGB $newval,[$mem]" %}
8115 ins_encode %{
8116 __ xchgb($newval$$Register, $mem$$Address);
8117 %}
8118 ins_pipe( pipe_cmpxchg );
8119 %}
8120
8121 instruct xchgS( memory mem, rRegI newval) %{
8122 match(Set newval (GetAndSetS mem newval));
8123 format %{ "XCHGW $newval,[$mem]" %}
8124 ins_encode %{
8125 __ xchgw($newval$$Register, $mem$$Address);
8126 %}
8127 ins_pipe( pipe_cmpxchg );
8128 %}
8129
8130 instruct xchgI( memory mem, rRegI newval) %{
8131 match(Set newval (GetAndSetI mem newval));
8132 format %{ "XCHGL $newval,[$mem]" %}
8133 ins_encode %{
8134 __ xchgl($newval$$Register, $mem$$Address);
8135 %}
8136 ins_pipe( pipe_cmpxchg );
8137 %}
8138
8139 instruct xchgL( memory mem, rRegL newval) %{
8140 match(Set newval (GetAndSetL mem newval));
8141 format %{ "XCHGL $newval,[$mem]" %}
8142 ins_encode %{
8143 __ xchgq($newval$$Register, $mem$$Address);
8144 %}
8145 ins_pipe( pipe_cmpxchg );
8146 %}
8147
8148 instruct xchgP( memory mem, rRegP newval) %{
8149 match(Set newval (GetAndSetP mem newval));
8150 predicate(n->as_LoadStore()->barrier_data() == 0);
8151 format %{ "XCHGQ $newval,[$mem]" %}
8152 ins_encode %{
8153 __ xchgq($newval$$Register, $mem$$Address);
8154 %}
8155 ins_pipe( pipe_cmpxchg );
8156 %}
8157
8158 instruct xchgN( memory mem, rRegN newval) %{
8159 match(Set newval (GetAndSetN mem newval));
8160 format %{ "XCHGL $newval,$mem]" %}
8161 ins_encode %{
8162 __ xchgl($newval$$Register, $mem$$Address);
8163 %}
8164 ins_pipe( pipe_cmpxchg );
8165 %}
8166
8167 //----------Abs Instructions-------------------------------------------
8168
8169 // Integer Absolute Instructions
8170 instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr)
8171 %{
8172 match(Set dst (AbsI src));
8173 effect(TEMP dst, TEMP tmp, KILL cr);
8174 format %{ "movl $tmp, $src\n\t"
8175 "sarl $tmp, 31\n\t"
8176 "movl $dst, $src\n\t"
8177 "xorl $dst, $tmp\n\t"
8178 "subl $dst, $tmp\n"
8179 %}
8180 ins_encode %{
8181 __ movl($tmp$$Register, $src$$Register);
8182 __ sarl($tmp$$Register, 31);
8183 __ movl($dst$$Register, $src$$Register);
8184 __ xorl($dst$$Register, $tmp$$Register);
8185 __ subl($dst$$Register, $tmp$$Register);
8186 %}
8187
8188 ins_pipe(ialu_reg_reg);
8189 %}
8190
8191 // Long Absolute Instructions
8192 instruct absL_rReg(rRegL dst, rRegL src, rRegL tmp, rFlagsReg cr)
8193 %{
8194 match(Set dst (AbsL src));
8195 effect(TEMP dst, TEMP tmp, KILL cr);
8196 format %{ "movq $tmp, $src\n\t"
8197 "sarq $tmp, 63\n\t"
8198 "movq $dst, $src\n\t"
8199 "xorq $dst, $tmp\n\t"
8200 "subq $dst, $tmp\n"
8201 %}
8202 ins_encode %{
8203 __ movq($tmp$$Register, $src$$Register);
8204 __ sarq($tmp$$Register, 63);
8205 __ movq($dst$$Register, $src$$Register);
8206 __ xorq($dst$$Register, $tmp$$Register);
8207 __ subq($dst$$Register, $tmp$$Register);
8208 %}
8209
8210 ins_pipe(ialu_reg_reg);
8211 %}
8212
8213 //----------Subtraction Instructions-------------------------------------------
8214
8215 // Integer Subtraction Instructions
8216 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8217 %{
8218 match(Set dst (SubI dst src));
8219 effect(KILL cr);
8220
8221 format %{ "subl $dst, $src\t# int" %}
8222 ins_encode %{
8223 __ subl($dst$$Register, $src$$Register);
8224 %}
8225 ins_pipe(ialu_reg_reg);
8226 %}
8227
8228 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8229 %{
8230 match(Set dst (SubI dst src));
8231 effect(KILL cr);
8232
8233 format %{ "subl $dst, $src\t# int" %}
8234 ins_encode %{
8235 __ subl($dst$$Register, $src$$constant);
8236 %}
8237 ins_pipe(ialu_reg);
8238 %}
8239
8240 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8241 %{
8242 match(Set dst (SubI dst (LoadI src)));
8243 effect(KILL cr);
8244
8245 ins_cost(125);
8246 format %{ "subl $dst, $src\t# int" %}
8247 ins_encode %{
8248 __ subl($dst$$Register, $src$$Address);
8249 %}
8250 ins_pipe(ialu_reg_mem);
8251 %}
8252
8253 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8254 %{
8255 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8256 effect(KILL cr);
8257
8258 ins_cost(150);
8259 format %{ "subl $dst, $src\t# int" %}
8260 ins_encode %{
8261 __ subl($dst$$Address, $src$$Register);
8262 %}
8263 ins_pipe(ialu_mem_reg);
8264 %}
8265
8266 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
8267 %{
8268 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
8269 effect(KILL cr);
8270
8271 ins_cost(125); // XXX
8272 format %{ "subl $dst, $src\t# int" %}
8273 ins_encode %{
8274 __ subl($dst$$Address, $src$$constant);
8275 %}
8276 ins_pipe(ialu_mem_imm);
8277 %}
8278
8279 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8280 %{
8281 match(Set dst (SubL dst src));
8282 effect(KILL cr);
8283
8284 format %{ "subq $dst, $src\t# long" %}
8285 ins_encode %{
8286 __ subq($dst$$Register, $src$$Register);
8287 %}
8288 ins_pipe(ialu_reg_reg);
8289 %}
8290
8291 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
8292 %{
8293 match(Set dst (SubL dst src));
8294 effect(KILL cr);
8295
8296 format %{ "subq $dst, $src\t# long" %}
8297 ins_encode %{
8298 __ subq($dst$$Register, $src$$constant);
8299 %}
8300 ins_pipe(ialu_reg);
8301 %}
8302
8303 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
8304 %{
8305 match(Set dst (SubL dst (LoadL src)));
8306 effect(KILL cr);
8307
8308 ins_cost(125);
8309 format %{ "subq $dst, $src\t# long" %}
8310 ins_encode %{
8311 __ subq($dst$$Register, $src$$Address);
8312 %}
8313 ins_pipe(ialu_reg_mem);
8314 %}
8315
8316 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
8317 %{
8318 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8319 effect(KILL cr);
8320
8321 ins_cost(150);
8322 format %{ "subq $dst, $src\t# long" %}
8323 ins_encode %{
8324 __ subq($dst$$Address, $src$$Register);
8325 %}
8326 ins_pipe(ialu_mem_reg);
8327 %}
8328
8329 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
8330 %{
8331 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
8332 effect(KILL cr);
8333
8334 ins_cost(125); // XXX
8335 format %{ "subq $dst, $src\t# long" %}
8336 ins_encode %{
8337 __ subq($dst$$Address, $src$$constant);
8338 %}
8339 ins_pipe(ialu_mem_imm);
8340 %}
8341
8342 // Subtract from a pointer
8343 // XXX hmpf???
8344 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
8345 %{
8346 match(Set dst (AddP dst (SubI zero src)));
8347 effect(KILL cr);
8348
8349 format %{ "subq $dst, $src\t# ptr - int" %}
8350 opcode(0x2B);
8351 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
8352 ins_pipe(ialu_reg_reg);
8353 %}
8354
8355 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
8356 %{
8357 match(Set dst (SubI zero dst));
8358 effect(KILL cr);
8359
8360 format %{ "negl $dst\t# int" %}
8361 ins_encode %{
8362 __ negl($dst$$Register);
8363 %}
8364 ins_pipe(ialu_reg);
8365 %}
8366
8367 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
8368 %{
8369 match(Set dst (NegI dst));
8370 effect(KILL cr);
8371
8372 format %{ "negl $dst\t# int" %}
8373 ins_encode %{
8374 __ negl($dst$$Register);
8375 %}
8376 ins_pipe(ialu_reg);
8377 %}
8378
8379 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
8380 %{
8381 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
8382 effect(KILL cr);
8383
8384 format %{ "negl $dst\t# int" %}
8385 ins_encode %{
8386 __ negl($dst$$Address);
8387 %}
8388 ins_pipe(ialu_reg);
8389 %}
8390
8391 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
8392 %{
8393 match(Set dst (SubL zero dst));
8394 effect(KILL cr);
8395
8396 format %{ "negq $dst\t# long" %}
8397 ins_encode %{
8398 __ negq($dst$$Register);
8399 %}
8400 ins_pipe(ialu_reg);
8401 %}
8402
8403 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
8404 %{
8405 match(Set dst (NegL dst));
8406 effect(KILL cr);
8407
8408 format %{ "negq $dst\t# int" %}
8409 ins_encode %{
8410 __ negq($dst$$Register);
8411 %}
8412 ins_pipe(ialu_reg);
8413 %}
8414
8415 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
8416 %{
8417 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
8418 effect(KILL cr);
8419
8420 format %{ "negq $dst\t# long" %}
8421 ins_encode %{
8422 __ negq($dst$$Address);
8423 %}
8424 ins_pipe(ialu_reg);
8425 %}
8426
8427 //----------Multiplication/Division Instructions-------------------------------
8428 // Integer Multiplication Instructions
8429 // Multiply Register
8430
8431 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8432 %{
8433 match(Set dst (MulI dst src));
8434 effect(KILL cr);
8435
8436 ins_cost(300);
8437 format %{ "imull $dst, $src\t# int" %}
8438 ins_encode %{
8439 __ imull($dst$$Register, $src$$Register);
8440 %}
8441 ins_pipe(ialu_reg_reg_alu0);
8442 %}
8443
8444 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
8445 %{
8446 match(Set dst (MulI src imm));
8447 effect(KILL cr);
8448
8449 ins_cost(300);
8450 format %{ "imull $dst, $src, $imm\t# int" %}
8451 ins_encode %{
8452 __ imull($dst$$Register, $src$$Register, $imm$$constant);
8453 %}
8454 ins_pipe(ialu_reg_reg_alu0);
8455 %}
8456
8457 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
8458 %{
8459 match(Set dst (MulI dst (LoadI src)));
8460 effect(KILL cr);
8461
8462 ins_cost(350);
8463 format %{ "imull $dst, $src\t# int" %}
8464 ins_encode %{
8465 __ imull($dst$$Register, $src$$Address);
8466 %}
8467 ins_pipe(ialu_reg_mem_alu0);
8468 %}
8469
8470 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
8471 %{
8472 match(Set dst (MulI (LoadI src) imm));
8473 effect(KILL cr);
8474
8475 ins_cost(300);
8476 format %{ "imull $dst, $src, $imm\t# int" %}
8477 ins_encode %{
8478 __ imull($dst$$Register, $src$$Address, $imm$$constant);
8479 %}
8480 ins_pipe(ialu_reg_mem_alu0);
8481 %}
8482
8483 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
8484 %{
8485 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
8486 effect(KILL cr, KILL src2);
8487
8488 expand %{ mulI_rReg(dst, src1, cr);
8489 mulI_rReg(src2, src3, cr);
8490 addI_rReg(dst, src2, cr); %}
8491 %}
8492
8493 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
8494 %{
8495 match(Set dst (MulL dst src));
8496 effect(KILL cr);
8497
8498 ins_cost(300);
8499 format %{ "imulq $dst, $src\t# long" %}
8500 ins_encode %{
8501 __ imulq($dst$$Register, $src$$Register);
8502 %}
8503 ins_pipe(ialu_reg_reg_alu0);
8504 %}
8505
8506 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
8507 %{
8508 match(Set dst (MulL src imm));
8509 effect(KILL cr);
8510
8511 ins_cost(300);
8512 format %{ "imulq $dst, $src, $imm\t# long" %}
8513 ins_encode %{
8514 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
8515 %}
8516 ins_pipe(ialu_reg_reg_alu0);
8517 %}
8518
8519 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
8520 %{
8521 match(Set dst (MulL dst (LoadL src)));
8522 effect(KILL cr);
8523
8524 ins_cost(350);
8525 format %{ "imulq $dst, $src\t# long" %}
8526 ins_encode %{
8527 __ imulq($dst$$Register, $src$$Address);
8528 %}
8529 ins_pipe(ialu_reg_mem_alu0);
8530 %}
8531
8532 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
8533 %{
8534 match(Set dst (MulL (LoadL src) imm));
8535 effect(KILL cr);
8536
8537 ins_cost(300);
8538 format %{ "imulq $dst, $src, $imm\t# long" %}
8539 ins_encode %{
8540 __ imulq($dst$$Register, $src$$Address, $imm$$constant);
8541 %}
8542 ins_pipe(ialu_reg_mem_alu0);
8543 %}
8544
8545 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8546 %{
8547 match(Set dst (MulHiL src rax));
8548 effect(USE_KILL rax, KILL cr);
8549
8550 ins_cost(300);
8551 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
8552 ins_encode %{
8553 __ imulq($src$$Register);
8554 %}
8555 ins_pipe(ialu_reg_reg_alu0);
8556 %}
8557
8558 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8559 rFlagsReg cr)
8560 %{
8561 match(Set rax (DivI rax div));
8562 effect(KILL rdx, KILL cr);
8563
8564 ins_cost(30*100+10*100); // XXX
8565 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8566 "jne,s normal\n\t"
8567 "xorl rdx, rdx\n\t"
8568 "cmpl $div, -1\n\t"
8569 "je,s done\n"
8570 "normal: cdql\n\t"
8571 "idivl $div\n"
8572 "done:" %}
8573 ins_encode(cdql_enc(div));
8574 ins_pipe(ialu_reg_reg_alu0);
8575 %}
8576
8577 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8578 rFlagsReg cr)
8579 %{
8580 match(Set rax (DivL rax div));
8581 effect(KILL rdx, KILL cr);
8582
8583 ins_cost(30*100+10*100); // XXX
8584 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8585 "cmpq rax, rdx\n\t"
8586 "jne,s normal\n\t"
8587 "xorl rdx, rdx\n\t"
8588 "cmpq $div, -1\n\t"
8589 "je,s done\n"
8590 "normal: cdqq\n\t"
8591 "idivq $div\n"
8592 "done:" %}
8593 ins_encode(cdqq_enc(div));
8594 ins_pipe(ialu_reg_reg_alu0);
8595 %}
8596
8597 // Integer DIVMOD with Register, both quotient and mod results
8598 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8599 rFlagsReg cr)
8600 %{
8601 match(DivModI rax div);
8602 effect(KILL cr);
8603
8604 ins_cost(30*100+10*100); // XXX
8605 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8606 "jne,s normal\n\t"
8607 "xorl rdx, rdx\n\t"
8608 "cmpl $div, -1\n\t"
8609 "je,s done\n"
8610 "normal: cdql\n\t"
8611 "idivl $div\n"
8612 "done:" %}
8613 ins_encode(cdql_enc(div));
8614 ins_pipe(pipe_slow);
8615 %}
8616
8617 // Long DIVMOD with Register, both quotient and mod results
8618 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8619 rFlagsReg cr)
8620 %{
8621 match(DivModL rax div);
8622 effect(KILL cr);
8623
8624 ins_cost(30*100+10*100); // XXX
8625 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8626 "cmpq rax, rdx\n\t"
8627 "jne,s normal\n\t"
8628 "xorl rdx, rdx\n\t"
8629 "cmpq $div, -1\n\t"
8630 "je,s done\n"
8631 "normal: cdqq\n\t"
8632 "idivq $div\n"
8633 "done:" %}
8634 ins_encode(cdqq_enc(div));
8635 ins_pipe(pipe_slow);
8636 %}
8637
8638 //----------- DivL-By-Constant-Expansions--------------------------------------
8639 // DivI cases are handled by the compiler
8640
8641 // Magic constant, reciprocal of 10
8642 instruct loadConL_0x6666666666666667(rRegL dst)
8643 %{
8644 effect(DEF dst);
8645
8646 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
8647 ins_encode(load_immL(dst, 0x6666666666666667));
8648 ins_pipe(ialu_reg);
8649 %}
8650
8651 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
8652 %{
8653 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
8654
8655 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
8656 ins_encode %{
8657 __ imulq($src$$Register);
8658 %}
8659 ins_pipe(ialu_reg_reg_alu0);
8660 %}
8661
8662 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
8663 %{
8664 effect(USE_DEF dst, KILL cr);
8665
8666 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
8667 ins_encode %{
8668 __ sarq($dst$$Register, 63);
8669 %}
8670 ins_pipe(ialu_reg);
8671 %}
8672
8673 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
8674 %{
8675 effect(USE_DEF dst, KILL cr);
8676
8677 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
8678 ins_encode %{
8679 __ sarq($dst$$Register, 2);
8680 %}
8681 ins_pipe(ialu_reg);
8682 %}
8683
8684 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
8685 %{
8686 match(Set dst (DivL src div));
8687
8688 ins_cost((5+8)*100);
8689 expand %{
8690 rax_RegL rax; // Killed temp
8691 rFlagsReg cr; // Killed
8692 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
8693 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
8694 sarL_rReg_63(src, cr); // sarq src, 63
8695 sarL_rReg_2(dst, cr); // sarq rdx, 2
8696 subL_rReg(dst, src, cr); // subl rdx, src
8697 %}
8698 %}
8699
8700 //-----------------------------------------------------------------------------
8701
8702 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8703 rFlagsReg cr)
8704 %{
8705 match(Set rdx (ModI rax div));
8706 effect(KILL rax, KILL cr);
8707
8708 ins_cost(300); // XXX
8709 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8710 "jne,s normal\n\t"
8711 "xorl rdx, rdx\n\t"
8712 "cmpl $div, -1\n\t"
8713 "je,s done\n"
8714 "normal: cdql\n\t"
8715 "idivl $div\n"
8716 "done:" %}
8717 ins_encode(cdql_enc(div));
8718 ins_pipe(ialu_reg_reg_alu0);
8719 %}
8720
8721 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8722 rFlagsReg cr)
8723 %{
8724 match(Set rdx (ModL rax div));
8725 effect(KILL rax, KILL cr);
8726
8727 ins_cost(300); // XXX
8728 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8729 "cmpq rax, rdx\n\t"
8730 "jne,s normal\n\t"
8731 "xorl rdx, rdx\n\t"
8732 "cmpq $div, -1\n\t"
8733 "je,s done\n"
8734 "normal: cdqq\n\t"
8735 "idivq $div\n"
8736 "done:" %}
8737 ins_encode(cdqq_enc(div));
8738 ins_pipe(ialu_reg_reg_alu0);
8739 %}
8740
8741 // Integer Shift Instructions
8742 // Shift Left by one
8743 instruct salI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8744 %{
8745 match(Set dst (LShiftI dst shift));
8746 effect(KILL cr);
8747
8748 format %{ "sall $dst, $shift" %}
8749 ins_encode %{
8750 __ sall($dst$$Register, $shift$$constant);
8751 %}
8752 ins_pipe(ialu_reg);
8753 %}
8754
8755 // Shift Left by one
8756 instruct salI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8757 %{
8758 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8759 effect(KILL cr);
8760
8761 format %{ "sall $dst, $shift\t" %}
8762 ins_encode %{
8763 __ sall($dst$$Address, $shift$$constant);
8764 %}
8765 ins_pipe(ialu_mem_imm);
8766 %}
8767
8768 // Shift Left by 8-bit immediate
8769 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8770 %{
8771 match(Set dst (LShiftI dst shift));
8772 effect(KILL cr);
8773
8774 format %{ "sall $dst, $shift" %}
8775 ins_encode %{
8776 __ sall($dst$$Register, $shift$$constant);
8777 %}
8778 ins_pipe(ialu_reg);
8779 %}
8780
8781 // Shift Left by 8-bit immediate
8782 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8783 %{
8784 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8785 effect(KILL cr);
8786
8787 format %{ "sall $dst, $shift" %}
8788 ins_encode %{
8789 __ sall($dst$$Address, $shift$$constant);
8790 %}
8791 ins_pipe(ialu_mem_imm);
8792 %}
8793
8794 // Shift Left by variable
8795 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8796 %{
8797 match(Set dst (LShiftI dst shift));
8798 effect(KILL cr);
8799
8800 format %{ "sall $dst, $shift" %}
8801 ins_encode %{
8802 __ sall($dst$$Register);
8803 %}
8804 ins_pipe(ialu_reg_reg);
8805 %}
8806
8807 // Shift Left by variable
8808 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8809 %{
8810 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8811 effect(KILL cr);
8812
8813 format %{ "sall $dst, $shift" %}
8814 ins_encode %{
8815 __ sall($dst$$Address);
8816 %}
8817 ins_pipe(ialu_mem_reg);
8818 %}
8819
8820 // Arithmetic shift right by one
8821 instruct sarI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8822 %{
8823 match(Set dst (RShiftI dst shift));
8824 effect(KILL cr);
8825
8826 format %{ "sarl $dst, $shift" %}
8827 ins_encode %{
8828 __ sarl($dst$$Register, $shift$$constant);
8829 %}
8830 ins_pipe(ialu_reg);
8831 %}
8832
8833 // Arithmetic shift right by one
8834 instruct sarI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8835 %{
8836 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8837 effect(KILL cr);
8838
8839 format %{ "sarl $dst, $shift" %}
8840 ins_encode %{
8841 __ sarl($dst$$Address, $shift$$constant);
8842 %}
8843 ins_pipe(ialu_mem_imm);
8844 %}
8845
8846 // Arithmetic Shift Right by 8-bit immediate
8847 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8848 %{
8849 match(Set dst (RShiftI dst shift));
8850 effect(KILL cr);
8851
8852 format %{ "sarl $dst, $shift" %}
8853 ins_encode %{
8854 __ sarl($dst$$Register, $shift$$constant);
8855 %}
8856 ins_pipe(ialu_mem_imm);
8857 %}
8858
8859 // Arithmetic Shift Right by 8-bit immediate
8860 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8861 %{
8862 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8863 effect(KILL cr);
8864
8865 format %{ "sarl $dst, $shift" %}
8866 ins_encode %{
8867 __ sarl($dst$$Address, $shift$$constant);
8868 %}
8869 ins_pipe(ialu_mem_imm);
8870 %}
8871
8872 // Arithmetic Shift Right by variable
8873 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8874 %{
8875 match(Set dst (RShiftI dst shift));
8876 effect(KILL cr);
8877 format %{ "sarl $dst, $shift" %}
8878 ins_encode %{
8879 __ sarl($dst$$Register);
8880 %}
8881 ins_pipe(ialu_reg_reg);
8882 %}
8883
8884 // Arithmetic Shift Right by variable
8885 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8886 %{
8887 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8888 effect(KILL cr);
8889
8890 format %{ "sarl $dst, $shift" %}
8891 ins_encode %{
8892 __ sarl($dst$$Address);
8893 %}
8894 ins_pipe(ialu_mem_reg);
8895 %}
8896
8897 // Logical shift right by one
8898 instruct shrI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
8899 %{
8900 match(Set dst (URShiftI dst shift));
8901 effect(KILL cr);
8902
8903 format %{ "shrl $dst, $shift" %}
8904 ins_encode %{
8905 __ shrl($dst$$Register, $shift$$constant);
8906 %}
8907 ins_pipe(ialu_reg);
8908 %}
8909
8910 // Logical shift right by one
8911 instruct shrI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8912 %{
8913 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8914 effect(KILL cr);
8915
8916 format %{ "shrl $dst, $shift" %}
8917 ins_encode %{
8918 __ shrl($dst$$Address, $shift$$constant);
8919 %}
8920 ins_pipe(ialu_mem_imm);
8921 %}
8922
8923 // Logical Shift Right by 8-bit immediate
8924 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8925 %{
8926 match(Set dst (URShiftI dst shift));
8927 effect(KILL cr);
8928
8929 format %{ "shrl $dst, $shift" %}
8930 ins_encode %{
8931 __ shrl($dst$$Register, $shift$$constant);
8932 %}
8933 ins_pipe(ialu_reg);
8934 %}
8935
8936 // Logical Shift Right by 8-bit immediate
8937 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8938 %{
8939 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8940 effect(KILL cr);
8941
8942 format %{ "shrl $dst, $shift" %}
8943 ins_encode %{
8944 __ shrl($dst$$Address, $shift$$constant);
8945 %}
8946 ins_pipe(ialu_mem_imm);
8947 %}
8948
8949 // Logical Shift Right by variable
8950 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8951 %{
8952 match(Set dst (URShiftI dst shift));
8953 effect(KILL cr);
8954
8955 format %{ "shrl $dst, $shift" %}
8956 ins_encode %{
8957 __ shrl($dst$$Register);
8958 %}
8959 ins_pipe(ialu_reg_reg);
8960 %}
8961
8962 // Logical Shift Right by variable
8963 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8964 %{
8965 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8966 effect(KILL cr);
8967
8968 format %{ "shrl $dst, $shift" %}
8969 ins_encode %{
8970 __ shrl($dst$$Address);
8971 %}
8972 ins_pipe(ialu_mem_reg);
8973 %}
8974
8975 // Long Shift Instructions
8976 // Shift Left by one
8977 instruct salL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
8978 %{
8979 match(Set dst (LShiftL dst shift));
8980 effect(KILL cr);
8981
8982 format %{ "salq $dst, $shift" %}
8983 ins_encode %{
8984 __ salq($dst$$Register, $shift$$constant);
8985 %}
8986 ins_pipe(ialu_reg);
8987 %}
8988
8989 // Shift Left by one
8990 instruct salL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
8991 %{
8992 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8993 effect(KILL cr);
8994
8995 format %{ "salq $dst, $shift" %}
8996 ins_encode %{
8997 __ salq($dst$$Address, $shift$$constant);
8998 %}
8999 ins_pipe(ialu_mem_imm);
9000 %}
9001
9002 // Shift Left by 8-bit immediate
9003 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9004 %{
9005 match(Set dst (LShiftL dst shift));
9006 effect(KILL cr);
9007
9008 format %{ "salq $dst, $shift" %}
9009 ins_encode %{
9010 __ salq($dst$$Register, $shift$$constant);
9011 %}
9012 ins_pipe(ialu_reg);
9013 %}
9014
9015 // Shift Left by 8-bit immediate
9016 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9017 %{
9018 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9019 effect(KILL cr);
9020
9021 format %{ "salq $dst, $shift" %}
9022 ins_encode %{
9023 __ salq($dst$$Address, $shift$$constant);
9024 %}
9025 ins_pipe(ialu_mem_imm);
9026 %}
9027
9028 // Shift Left by variable
9029 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9030 %{
9031 match(Set dst (LShiftL dst shift));
9032 effect(KILL cr);
9033
9034 format %{ "salq $dst, $shift" %}
9035 ins_encode %{
9036 __ salq($dst$$Register);
9037 %}
9038 ins_pipe(ialu_reg_reg);
9039 %}
9040
9041 // Shift Left by variable
9042 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9043 %{
9044 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
9045 effect(KILL cr);
9046
9047 format %{ "salq $dst, $shift" %}
9048 ins_encode %{
9049 __ salq($dst$$Address);
9050 %}
9051 ins_pipe(ialu_mem_reg);
9052 %}
9053
9054 // Arithmetic shift right by one
9055 instruct sarL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
9056 %{
9057 match(Set dst (RShiftL dst shift));
9058 effect(KILL cr);
9059
9060 format %{ "sarq $dst, $shift" %}
9061 ins_encode %{
9062 __ sarq($dst$$Register, $shift$$constant);
9063 %}
9064 ins_pipe(ialu_reg);
9065 %}
9066
9067 // Arithmetic shift right by one
9068 instruct sarL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
9069 %{
9070 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9071 effect(KILL cr);
9072
9073 format %{ "sarq $dst, $shift" %}
9074 ins_encode %{
9075 __ sarq($dst$$Address, $shift$$constant);
9076 %}
9077 ins_pipe(ialu_mem_imm);
9078 %}
9079
9080 // Arithmetic Shift Right by 8-bit immediate
9081 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9082 %{
9083 match(Set dst (RShiftL dst shift));
9084 effect(KILL cr);
9085
9086 format %{ "sarq $dst, $shift" %}
9087 ins_encode %{
9088 __ sarq($dst$$Register, (unsigned char)($shift$$constant & 0x3F));
9089 %}
9090 ins_pipe(ialu_mem_imm);
9091 %}
9092
9093 // Arithmetic Shift Right by 8-bit immediate
9094 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9095 %{
9096 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9097 effect(KILL cr);
9098
9099 format %{ "sarq $dst, $shift" %}
9100 ins_encode %{
9101 __ sarq($dst$$Address, (unsigned char)($shift$$constant & 0x3F));
9102 %}
9103 ins_pipe(ialu_mem_imm);
9104 %}
9105
9106 // Arithmetic Shift Right by variable
9107 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9108 %{
9109 match(Set dst (RShiftL dst shift));
9110 effect(KILL cr);
9111
9112 format %{ "sarq $dst, $shift" %}
9113 ins_encode %{
9114 __ sarq($dst$$Register);
9115 %}
9116 ins_pipe(ialu_reg_reg);
9117 %}
9118
9119 // Arithmetic Shift Right by variable
9120 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9121 %{
9122 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
9123 effect(KILL cr);
9124
9125 format %{ "sarq $dst, $shift" %}
9126 ins_encode %{
9127 __ sarq($dst$$Address);
9128 %}
9129 ins_pipe(ialu_mem_reg);
9130 %}
9131
9132 // Logical shift right by one
9133 instruct shrL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
9134 %{
9135 match(Set dst (URShiftL dst shift));
9136 effect(KILL cr);
9137
9138 format %{ "shrq $dst, $shift" %}
9139 ins_encode %{
9140 __ shrq($dst$$Register, $shift$$constant);
9141 %}
9142 ins_pipe(ialu_reg);
9143 %}
9144
9145 // Logical shift right by one
9146 instruct shrL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
9147 %{
9148 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9149 effect(KILL cr);
9150
9151 format %{ "shrq $dst, $shift" %}
9152 ins_encode %{
9153 __ shrq($dst$$Address, $shift$$constant);
9154 %}
9155 ins_pipe(ialu_mem_imm);
9156 %}
9157
9158 // Logical Shift Right by 8-bit immediate
9159 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
9160 %{
9161 match(Set dst (URShiftL dst shift));
9162 effect(KILL cr);
9163
9164 format %{ "shrq $dst, $shift" %}
9165 ins_encode %{
9166 __ shrq($dst$$Register, $shift$$constant);
9167 %}
9168 ins_pipe(ialu_reg);
9169 %}
9170
9171 // Logical Shift Right by 8-bit immediate
9172 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
9173 %{
9174 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9175 effect(KILL cr);
9176
9177 format %{ "shrq $dst, $shift" %}
9178 ins_encode %{
9179 __ shrq($dst$$Address, $shift$$constant);
9180 %}
9181 ins_pipe(ialu_mem_imm);
9182 %}
9183
9184 // Logical Shift Right by variable
9185 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9186 %{
9187 match(Set dst (URShiftL dst shift));
9188 effect(KILL cr);
9189
9190 format %{ "shrq $dst, $shift" %}
9191 ins_encode %{
9192 __ shrq($dst$$Register);
9193 %}
9194 ins_pipe(ialu_reg_reg);
9195 %}
9196
9197 // Logical Shift Right by variable
9198 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
9199 %{
9200 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
9201 effect(KILL cr);
9202
9203 format %{ "shrq $dst, $shift" %}
9204 ins_encode %{
9205 __ shrq($dst$$Address);
9206 %}
9207 ins_pipe(ialu_mem_reg);
9208 %}
9209
9210 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
9211 // This idiom is used by the compiler for the i2b bytecode.
9212 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
9213 %{
9214 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
9215
9216 format %{ "movsbl $dst, $src\t# i2b" %}
9217 ins_encode %{
9218 __ movsbl($dst$$Register, $src$$Register);
9219 %}
9220 ins_pipe(ialu_reg_reg);
9221 %}
9222
9223 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
9224 // This idiom is used by the compiler the i2s bytecode.
9225 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
9226 %{
9227 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
9228
9229 format %{ "movswl $dst, $src\t# i2s" %}
9230 ins_encode %{
9231 __ movswl($dst$$Register, $src$$Register);
9232 %}
9233 ins_pipe(ialu_reg_reg);
9234 %}
9235
9236 // ROL/ROR instructions
9237
9238 // Rotate left by constant.
9239 instruct rolI_imm(rRegI dst, immI8 shift, rFlagsReg cr)
9240 %{
9241 predicate(n->bottom_type()->basic_type() == T_INT);
9242 match(Set dst (RotateLeft dst shift));
9243 effect(KILL cr);
9244 format %{ "roll $dst, $shift" %}
9245 ins_encode %{
9246 __ roll($dst$$Register, $shift$$constant);
9247 %}
9248 ins_pipe(ialu_reg);
9249 %}
9250
9251 // Rotate Left by variable
9252 instruct rolI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9253 %{
9254 predicate(n->bottom_type()->basic_type() == T_INT);
9255 match(Set dst (RotateLeft dst shift));
9256 effect(KILL cr);
9257 format %{ "roll $dst, $shift" %}
9258 ins_encode %{
9259 __ roll($dst$$Register);
9260 %}
9261 ins_pipe(ialu_reg_reg);
9262 %}
9263
9264 // Rotate Right by constant.
9265 instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
9266 %{
9267 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9268 match(Set dst (RotateRight dst shift));
9269 effect(KILL cr);
9270 format %{ "rorl $dst, $shift" %}
9271 ins_encode %{
9272 __ rorl($dst$$Register, $shift$$constant);
9273 %}
9274 ins_pipe(ialu_reg);
9275 %}
9276
9277 // Rotate Right by constant.
9278 instruct rorI_immI8(rRegI dst, immI8 shift)
9279 %{
9280 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
9281 match(Set dst (RotateRight dst shift));
9282 format %{ "rorxd $dst, $shift" %}
9283 ins_encode %{
9284 __ rorxd($dst$$Register, $dst$$Register, $shift$$constant);
9285 %}
9286 ins_pipe(ialu_reg_reg);
9287 %}
9288
9289 // Rotate Right by variable
9290 instruct rorI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
9291 %{
9292 predicate(n->bottom_type()->basic_type() == T_INT);
9293 match(Set dst (RotateRight dst shift));
9294 effect(KILL cr);
9295 format %{ "rorl $dst, $shift" %}
9296 ins_encode %{
9297 __ rorl($dst$$Register);
9298 %}
9299 ins_pipe(ialu_reg_reg);
9300 %}
9301
9302
9303 // Rotate Left by constant.
9304 instruct rolL_immI8(rRegL dst, immI8 shift, rFlagsReg cr)
9305 %{
9306 predicate(n->bottom_type()->basic_type() == T_LONG);
9307 match(Set dst (RotateLeft dst shift));
9308 effect(KILL cr);
9309 format %{ "rolq $dst, $shift" %}
9310 ins_encode %{
9311 __ rolq($dst$$Register, $shift$$constant);
9312 %}
9313 ins_pipe(ialu_reg);
9314 %}
9315
9316 // Rotate Left by variable
9317 instruct rolL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9318 %{
9319 predicate(n->bottom_type()->basic_type() == T_LONG);
9320 match(Set dst (RotateLeft dst shift));
9321 effect(KILL cr);
9322 format %{ "rolq $dst, $shift" %}
9323 ins_encode %{
9324 __ rolq($dst$$Register);
9325 %}
9326 ins_pipe(ialu_reg_reg);
9327 %}
9328
9329
9330 // Rotate Right by constant.
9331 instruct rorL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
9332 %{
9333 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9334 match(Set dst (RotateRight dst shift));
9335 effect(KILL cr);
9336 format %{ "rorq $dst, $shift" %}
9337 ins_encode %{
9338 __ rorq($dst$$Register, $shift$$constant);
9339 %}
9340 ins_pipe(ialu_reg);
9341 %}
9342
9343
9344 // Rotate Right by constant
9345 instruct rorL_immI8(rRegL dst, immI8 shift)
9346 %{
9347 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
9348 match(Set dst (RotateRight dst shift));
9349 format %{ "rorxq $dst, $shift" %}
9350 ins_encode %{
9351 __ rorxq($dst$$Register, $dst$$Register, $shift$$constant);
9352 %}
9353 ins_pipe(ialu_reg_reg);
9354 %}
9355
9356 // Rotate Right by variable
9357 instruct rorL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
9358 %{
9359 predicate(n->bottom_type()->basic_type() == T_LONG);
9360 match(Set dst (RotateRight dst shift));
9361 effect(KILL cr);
9362 format %{ "rorq $dst, $shift" %}
9363 ins_encode %{
9364 __ rorq($dst$$Register);
9365 %}
9366 ins_pipe(ialu_reg_reg);
9367 %}
9368
9369
9370 // Logical Instructions
9371
9372 // Integer Logical Instructions
9373
9374 // And Instructions
9375 // And Register with Register
9376 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9377 %{
9378 match(Set dst (AndI dst src));
9379 effect(KILL cr);
9380
9381 format %{ "andl $dst, $src\t# int" %}
9382 ins_encode %{
9383 __ andl($dst$$Register, $src$$Register);
9384 %}
9385 ins_pipe(ialu_reg_reg);
9386 %}
9387
9388 // And Register with Immediate 255
9389 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
9390 %{
9391 match(Set dst (AndI dst src));
9392
9393 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
9394 ins_encode %{
9395 __ movzbl($dst$$Register, $dst$$Register);
9396 %}
9397 ins_pipe(ialu_reg);
9398 %}
9399
9400 // And Register with Immediate 255 and promote to long
9401 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
9402 %{
9403 match(Set dst (ConvI2L (AndI src mask)));
9404
9405 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
9406 ins_encode %{
9407 __ movzbl($dst$$Register, $src$$Register);
9408 %}
9409 ins_pipe(ialu_reg);
9410 %}
9411
9412 // And Register with Immediate 65535
9413 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
9414 %{
9415 match(Set dst (AndI dst src));
9416
9417 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
9418 ins_encode %{
9419 __ movzwl($dst$$Register, $dst$$Register);
9420 %}
9421 ins_pipe(ialu_reg);
9422 %}
9423
9424 // And Register with Immediate 65535 and promote to long
9425 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
9426 %{
9427 match(Set dst (ConvI2L (AndI src mask)));
9428
9429 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
9430 ins_encode %{
9431 __ movzwl($dst$$Register, $src$$Register);
9432 %}
9433 ins_pipe(ialu_reg);
9434 %}
9435
9436 // Can skip int2long conversions after AND with small bitmask
9437 instruct convI2LAndI_reg_immIbitmask(rRegL dst, rRegI src, immI_Pow2M1 mask, rRegI tmp, rFlagsReg cr)
9438 %{
9439 predicate(VM_Version::supports_bmi2());
9440 ins_cost(125);
9441 effect(TEMP tmp, KILL cr);
9442 match(Set dst (ConvI2L (AndI src mask)));
9443 format %{ "bzhiq $dst, $src, $mask \t# using $tmp as TEMP, int & immI_Pow2M1 -> long" %}
9444 ins_encode %{
9445 __ movl($tmp$$Register, exact_log2($mask$$constant + 1));
9446 __ bzhiq($dst$$Register, $src$$Register, $tmp$$Register);
9447 %}
9448 ins_pipe(ialu_reg_reg);
9449 %}
9450
9451 // And Register with Immediate
9452 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9453 %{
9454 match(Set dst (AndI dst src));
9455 effect(KILL cr);
9456
9457 format %{ "andl $dst, $src\t# int" %}
9458 ins_encode %{
9459 __ andl($dst$$Register, $src$$constant);
9460 %}
9461 ins_pipe(ialu_reg);
9462 %}
9463
9464 // And Register with Memory
9465 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9466 %{
9467 match(Set dst (AndI dst (LoadI src)));
9468 effect(KILL cr);
9469
9470 ins_cost(125);
9471 format %{ "andl $dst, $src\t# int" %}
9472 ins_encode %{
9473 __ andl($dst$$Register, $src$$Address);
9474 %}
9475 ins_pipe(ialu_reg_mem);
9476 %}
9477
9478 // And Memory with Register
9479 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9480 %{
9481 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
9482 effect(KILL cr);
9483
9484 ins_cost(150);
9485 format %{ "andb $dst, $src\t# byte" %}
9486 ins_encode %{
9487 __ andb($dst$$Address, $src$$Register);
9488 %}
9489 ins_pipe(ialu_mem_reg);
9490 %}
9491
9492 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9493 %{
9494 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9495 effect(KILL cr);
9496
9497 ins_cost(150);
9498 format %{ "andl $dst, $src\t# int" %}
9499 ins_encode %{
9500 __ andl($dst$$Address, $src$$Register);
9501 %}
9502 ins_pipe(ialu_mem_reg);
9503 %}
9504
9505 // And Memory with Immediate
9506 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9507 %{
9508 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9509 effect(KILL cr);
9510
9511 ins_cost(125);
9512 format %{ "andl $dst, $src\t# int" %}
9513 ins_encode %{
9514 __ andl($dst$$Address, $src$$constant);
9515 %}
9516 ins_pipe(ialu_mem_imm);
9517 %}
9518
9519 // BMI1 instructions
9520 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9521 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9522 predicate(UseBMI1Instructions);
9523 effect(KILL cr);
9524
9525 ins_cost(125);
9526 format %{ "andnl $dst, $src1, $src2" %}
9527
9528 ins_encode %{
9529 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9530 %}
9531 ins_pipe(ialu_reg_mem);
9532 %}
9533
9534 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9535 match(Set dst (AndI (XorI src1 minus_1) src2));
9536 predicate(UseBMI1Instructions);
9537 effect(KILL cr);
9538
9539 format %{ "andnl $dst, $src1, $src2" %}
9540
9541 ins_encode %{
9542 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9543 %}
9544 ins_pipe(ialu_reg);
9545 %}
9546
9547 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
9548 match(Set dst (AndI (SubI imm_zero src) src));
9549 predicate(UseBMI1Instructions);
9550 effect(KILL cr);
9551
9552 format %{ "blsil $dst, $src" %}
9553
9554 ins_encode %{
9555 __ blsil($dst$$Register, $src$$Register);
9556 %}
9557 ins_pipe(ialu_reg);
9558 %}
9559
9560 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
9561 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9562 predicate(UseBMI1Instructions);
9563 effect(KILL cr);
9564
9565 ins_cost(125);
9566 format %{ "blsil $dst, $src" %}
9567
9568 ins_encode %{
9569 __ blsil($dst$$Register, $src$$Address);
9570 %}
9571 ins_pipe(ialu_reg_mem);
9572 %}
9573
9574 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9575 %{
9576 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9577 predicate(UseBMI1Instructions);
9578 effect(KILL cr);
9579
9580 ins_cost(125);
9581 format %{ "blsmskl $dst, $src" %}
9582
9583 ins_encode %{
9584 __ blsmskl($dst$$Register, $src$$Address);
9585 %}
9586 ins_pipe(ialu_reg_mem);
9587 %}
9588
9589 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9590 %{
9591 match(Set dst (XorI (AddI src minus_1) src));
9592 predicate(UseBMI1Instructions);
9593 effect(KILL cr);
9594
9595 format %{ "blsmskl $dst, $src" %}
9596
9597 ins_encode %{
9598 __ blsmskl($dst$$Register, $src$$Register);
9599 %}
9600
9601 ins_pipe(ialu_reg);
9602 %}
9603
9604 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9605 %{
9606 match(Set dst (AndI (AddI src minus_1) src) );
9607 predicate(UseBMI1Instructions);
9608 effect(KILL cr);
9609
9610 format %{ "blsrl $dst, $src" %}
9611
9612 ins_encode %{
9613 __ blsrl($dst$$Register, $src$$Register);
9614 %}
9615
9616 ins_pipe(ialu_reg_mem);
9617 %}
9618
9619 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9620 %{
9621 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9622 predicate(UseBMI1Instructions);
9623 effect(KILL cr);
9624
9625 ins_cost(125);
9626 format %{ "blsrl $dst, $src" %}
9627
9628 ins_encode %{
9629 __ blsrl($dst$$Register, $src$$Address);
9630 %}
9631
9632 ins_pipe(ialu_reg);
9633 %}
9634
9635 // Or Instructions
9636 // Or Register with Register
9637 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9638 %{
9639 match(Set dst (OrI dst src));
9640 effect(KILL cr);
9641
9642 format %{ "orl $dst, $src\t# int" %}
9643 ins_encode %{
9644 __ orl($dst$$Register, $src$$Register);
9645 %}
9646 ins_pipe(ialu_reg_reg);
9647 %}
9648
9649 // Or Register with Immediate
9650 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9651 %{
9652 match(Set dst (OrI dst src));
9653 effect(KILL cr);
9654
9655 format %{ "orl $dst, $src\t# int" %}
9656 ins_encode %{
9657 __ orl($dst$$Register, $src$$constant);
9658 %}
9659 ins_pipe(ialu_reg);
9660 %}
9661
9662 // Or Register with Memory
9663 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9664 %{
9665 match(Set dst (OrI dst (LoadI src)));
9666 effect(KILL cr);
9667
9668 ins_cost(125);
9669 format %{ "orl $dst, $src\t# int" %}
9670 ins_encode %{
9671 __ orl($dst$$Register, $src$$Address);
9672 %}
9673 ins_pipe(ialu_reg_mem);
9674 %}
9675
9676 // Or Memory with Register
9677 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9678 %{
9679 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9680 effect(KILL cr);
9681
9682 ins_cost(150);
9683 format %{ "orb $dst, $src\t# byte" %}
9684 ins_encode %{
9685 __ orb($dst$$Address, $src$$Register);
9686 %}
9687 ins_pipe(ialu_mem_reg);
9688 %}
9689
9690 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9691 %{
9692 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9693 effect(KILL cr);
9694
9695 ins_cost(150);
9696 format %{ "orl $dst, $src\t# int" %}
9697 ins_encode %{
9698 __ orl($dst$$Address, $src$$Register);
9699 %}
9700 ins_pipe(ialu_mem_reg);
9701 %}
9702
9703 // Or Memory with Immediate
9704 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9705 %{
9706 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9707 effect(KILL cr);
9708
9709 ins_cost(125);
9710 format %{ "orl $dst, $src\t# int" %}
9711 ins_encode %{
9712 __ orl($dst$$Address, $src$$constant);
9713 %}
9714 ins_pipe(ialu_mem_imm);
9715 %}
9716
9717 // Xor Instructions
9718 // Xor Register with Register
9719 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9720 %{
9721 match(Set dst (XorI dst src));
9722 effect(KILL cr);
9723
9724 format %{ "xorl $dst, $src\t# int" %}
9725 ins_encode %{
9726 __ xorl($dst$$Register, $src$$Register);
9727 %}
9728 ins_pipe(ialu_reg_reg);
9729 %}
9730
9731 // Xor Register with Immediate -1
9732 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9733 match(Set dst (XorI dst imm));
9734
9735 format %{ "not $dst" %}
9736 ins_encode %{
9737 __ notl($dst$$Register);
9738 %}
9739 ins_pipe(ialu_reg);
9740 %}
9741
9742 // Xor Register with Immediate
9743 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9744 %{
9745 match(Set dst (XorI dst src));
9746 effect(KILL cr);
9747
9748 format %{ "xorl $dst, $src\t# int" %}
9749 ins_encode %{
9750 __ xorl($dst$$Register, $src$$constant);
9751 %}
9752 ins_pipe(ialu_reg);
9753 %}
9754
9755 // Xor Register with Memory
9756 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9757 %{
9758 match(Set dst (XorI dst (LoadI src)));
9759 effect(KILL cr);
9760
9761 ins_cost(125);
9762 format %{ "xorl $dst, $src\t# int" %}
9763 ins_encode %{
9764 __ xorl($dst$$Register, $src$$Address);
9765 %}
9766 ins_pipe(ialu_reg_mem);
9767 %}
9768
9769 // Xor Memory with Register
9770 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9771 %{
9772 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9773 effect(KILL cr);
9774
9775 ins_cost(150);
9776 format %{ "xorb $dst, $src\t# byte" %}
9777 ins_encode %{
9778 __ xorb($dst$$Address, $src$$Register);
9779 %}
9780 ins_pipe(ialu_mem_reg);
9781 %}
9782
9783 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9784 %{
9785 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9786 effect(KILL cr);
9787
9788 ins_cost(150);
9789 format %{ "xorl $dst, $src\t# int" %}
9790 ins_encode %{
9791 __ xorl($dst$$Address, $src$$Register);
9792 %}
9793 ins_pipe(ialu_mem_reg);
9794 %}
9795
9796 // Xor Memory with Immediate
9797 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9798 %{
9799 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9800 effect(KILL cr);
9801
9802 ins_cost(125);
9803 format %{ "xorl $dst, $src\t# int" %}
9804 ins_encode %{
9805 __ xorl($dst$$Address, $src$$constant);
9806 %}
9807 ins_pipe(ialu_mem_imm);
9808 %}
9809
9810
9811 // Long Logical Instructions
9812
9813 // And Instructions
9814 // And Register with Register
9815 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9816 %{
9817 match(Set dst (AndL dst src));
9818 effect(KILL cr);
9819
9820 format %{ "andq $dst, $src\t# long" %}
9821 ins_encode %{
9822 __ andq($dst$$Register, $src$$Register);
9823 %}
9824 ins_pipe(ialu_reg_reg);
9825 %}
9826
9827 // And Register with Immediate 255
9828 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9829 %{
9830 match(Set dst (AndL dst src));
9831
9832 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9833 ins_encode %{
9834 __ movzbq($dst$$Register, $dst$$Register);
9835 %}
9836 ins_pipe(ialu_reg);
9837 %}
9838
9839 // And Register with Immediate 65535
9840 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9841 %{
9842 match(Set dst (AndL dst src));
9843
9844 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9845 ins_encode %{
9846 __ movzwq($dst$$Register, $dst$$Register);
9847 %}
9848 ins_pipe(ialu_reg);
9849 %}
9850
9851 // And Register with Immediate
9852 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9853 %{
9854 match(Set dst (AndL dst src));
9855 effect(KILL cr);
9856
9857 format %{ "andq $dst, $src\t# long" %}
9858 ins_encode %{
9859 __ andq($dst$$Register, $src$$constant);
9860 %}
9861 ins_pipe(ialu_reg);
9862 %}
9863
9864 // And Register with Memory
9865 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9866 %{
9867 match(Set dst (AndL dst (LoadL src)));
9868 effect(KILL cr);
9869
9870 ins_cost(125);
9871 format %{ "andq $dst, $src\t# long" %}
9872 ins_encode %{
9873 __ andq($dst$$Register, $src$$Address);
9874 %}
9875 ins_pipe(ialu_reg_mem);
9876 %}
9877
9878 // And Memory with Register
9879 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9880 %{
9881 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9882 effect(KILL cr);
9883
9884 ins_cost(150);
9885 format %{ "andq $dst, $src\t# long" %}
9886 ins_encode %{
9887 __ andq($dst$$Address, $src$$Register);
9888 %}
9889 ins_pipe(ialu_mem_reg);
9890 %}
9891
9892 // And Memory with Immediate
9893 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9894 %{
9895 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9896 effect(KILL cr);
9897
9898 ins_cost(125);
9899 format %{ "andq $dst, $src\t# long" %}
9900 ins_encode %{
9901 __ andq($dst$$Address, $src$$constant);
9902 %}
9903 ins_pipe(ialu_mem_imm);
9904 %}
9905
9906 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
9907 %{
9908 // con should be a pure 64-bit immediate given that not(con) is a power of 2
9909 // because AND/OR works well enough for 8/32-bit values.
9910 predicate(log2i_graceful(~n->in(3)->in(2)->get_long()) > 30);
9911
9912 match(Set dst (StoreL dst (AndL (LoadL dst) con)));
9913 effect(KILL cr);
9914
9915 ins_cost(125);
9916 format %{ "btrq $dst, log2(not($con))\t# long" %}
9917 ins_encode %{
9918 __ btrq($dst$$Address, log2i_exact((julong)~$con$$constant));
9919 %}
9920 ins_pipe(ialu_mem_imm);
9921 %}
9922
9923 // BMI1 instructions
9924 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9925 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9926 predicate(UseBMI1Instructions);
9927 effect(KILL cr);
9928
9929 ins_cost(125);
9930 format %{ "andnq $dst, $src1, $src2" %}
9931
9932 ins_encode %{
9933 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9934 %}
9935 ins_pipe(ialu_reg_mem);
9936 %}
9937
9938 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9939 match(Set dst (AndL (XorL src1 minus_1) src2));
9940 predicate(UseBMI1Instructions);
9941 effect(KILL cr);
9942
9943 format %{ "andnq $dst, $src1, $src2" %}
9944
9945 ins_encode %{
9946 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9947 %}
9948 ins_pipe(ialu_reg_mem);
9949 %}
9950
9951 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9952 match(Set dst (AndL (SubL imm_zero src) src));
9953 predicate(UseBMI1Instructions);
9954 effect(KILL cr);
9955
9956 format %{ "blsiq $dst, $src" %}
9957
9958 ins_encode %{
9959 __ blsiq($dst$$Register, $src$$Register);
9960 %}
9961 ins_pipe(ialu_reg);
9962 %}
9963
9964 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9965 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9966 predicate(UseBMI1Instructions);
9967 effect(KILL cr);
9968
9969 ins_cost(125);
9970 format %{ "blsiq $dst, $src" %}
9971
9972 ins_encode %{
9973 __ blsiq($dst$$Register, $src$$Address);
9974 %}
9975 ins_pipe(ialu_reg_mem);
9976 %}
9977
9978 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9979 %{
9980 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9981 predicate(UseBMI1Instructions);
9982 effect(KILL cr);
9983
9984 ins_cost(125);
9985 format %{ "blsmskq $dst, $src" %}
9986
9987 ins_encode %{
9988 __ blsmskq($dst$$Register, $src$$Address);
9989 %}
9990 ins_pipe(ialu_reg_mem);
9991 %}
9992
9993 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9994 %{
9995 match(Set dst (XorL (AddL src minus_1) src));
9996 predicate(UseBMI1Instructions);
9997 effect(KILL cr);
9998
9999 format %{ "blsmskq $dst, $src" %}
10000
10001 ins_encode %{
10002 __ blsmskq($dst$$Register, $src$$Register);
10003 %}
10004
10005 ins_pipe(ialu_reg);
10006 %}
10007
10008 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
10009 %{
10010 match(Set dst (AndL (AddL src minus_1) src) );
10011 predicate(UseBMI1Instructions);
10012 effect(KILL cr);
10013
10014 format %{ "blsrq $dst, $src" %}
10015
10016 ins_encode %{
10017 __ blsrq($dst$$Register, $src$$Register);
10018 %}
10019
10020 ins_pipe(ialu_reg);
10021 %}
10022
10023 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
10024 %{
10025 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
10026 predicate(UseBMI1Instructions);
10027 effect(KILL cr);
10028
10029 ins_cost(125);
10030 format %{ "blsrq $dst, $src" %}
10031
10032 ins_encode %{
10033 __ blsrq($dst$$Register, $src$$Address);
10034 %}
10035
10036 ins_pipe(ialu_reg);
10037 %}
10038
10039 // Or Instructions
10040 // Or Register with Register
10041 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10042 %{
10043 match(Set dst (OrL dst src));
10044 effect(KILL cr);
10045
10046 format %{ "orq $dst, $src\t# long" %}
10047 ins_encode %{
10048 __ orq($dst$$Register, $src$$Register);
10049 %}
10050 ins_pipe(ialu_reg_reg);
10051 %}
10052
10053 // Use any_RegP to match R15 (TLS register) without spilling.
10054 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
10055 match(Set dst (OrL dst (CastP2X src)));
10056 effect(KILL cr);
10057
10058 format %{ "orq $dst, $src\t# long" %}
10059 ins_encode %{
10060 __ orq($dst$$Register, $src$$Register);
10061 %}
10062 ins_pipe(ialu_reg_reg);
10063 %}
10064
10065
10066 // Or Register with Immediate
10067 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10068 %{
10069 match(Set dst (OrL dst src));
10070 effect(KILL cr);
10071
10072 format %{ "orq $dst, $src\t# long" %}
10073 ins_encode %{
10074 __ orq($dst$$Register, $src$$constant);
10075 %}
10076 ins_pipe(ialu_reg);
10077 %}
10078
10079 // Or Register with Memory
10080 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10081 %{
10082 match(Set dst (OrL dst (LoadL src)));
10083 effect(KILL cr);
10084
10085 ins_cost(125);
10086 format %{ "orq $dst, $src\t# long" %}
10087 ins_encode %{
10088 __ orq($dst$$Register, $src$$Address);
10089 %}
10090 ins_pipe(ialu_reg_mem);
10091 %}
10092
10093 // Or Memory with Register
10094 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10095 %{
10096 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10097 effect(KILL cr);
10098
10099 ins_cost(150);
10100 format %{ "orq $dst, $src\t# long" %}
10101 ins_encode %{
10102 __ orq($dst$$Address, $src$$Register);
10103 %}
10104 ins_pipe(ialu_mem_reg);
10105 %}
10106
10107 // Or Memory with Immediate
10108 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10109 %{
10110 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10111 effect(KILL cr);
10112
10113 ins_cost(125);
10114 format %{ "orq $dst, $src\t# long" %}
10115 ins_encode %{
10116 __ orq($dst$$Address, $src$$constant);
10117 %}
10118 ins_pipe(ialu_mem_imm);
10119 %}
10120
10121 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr)
10122 %{
10123 // con should be a pure 64-bit power of 2 immediate
10124 // because AND/OR works well enough for 8/32-bit values.
10125 predicate(log2i_graceful(n->in(3)->in(2)->get_long()) > 31);
10126
10127 match(Set dst (StoreL dst (OrL (LoadL dst) con)));
10128 effect(KILL cr);
10129
10130 ins_cost(125);
10131 format %{ "btsq $dst, log2($con)\t# long" %}
10132 ins_encode %{
10133 __ btsq($dst$$Address, log2i_exact((julong)$con$$constant));
10134 %}
10135 ins_pipe(ialu_mem_imm);
10136 %}
10137
10138 // Xor Instructions
10139 // Xor Register with Register
10140 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10141 %{
10142 match(Set dst (XorL dst src));
10143 effect(KILL cr);
10144
10145 format %{ "xorq $dst, $src\t# long" %}
10146 ins_encode %{
10147 __ xorq($dst$$Register, $src$$Register);
10148 %}
10149 ins_pipe(ialu_reg_reg);
10150 %}
10151
10152 // Xor Register with Immediate -1
10153 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10154 match(Set dst (XorL dst imm));
10155
10156 format %{ "notq $dst" %}
10157 ins_encode %{
10158 __ notq($dst$$Register);
10159 %}
10160 ins_pipe(ialu_reg);
10161 %}
10162
10163 // Xor Register with Immediate
10164 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10165 %{
10166 match(Set dst (XorL dst src));
10167 effect(KILL cr);
10168
10169 format %{ "xorq $dst, $src\t# long" %}
10170 ins_encode %{
10171 __ xorq($dst$$Register, $src$$constant);
10172 %}
10173 ins_pipe(ialu_reg);
10174 %}
10175
10176 // Xor Register with Memory
10177 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10178 %{
10179 match(Set dst (XorL dst (LoadL src)));
10180 effect(KILL cr);
10181
10182 ins_cost(125);
10183 format %{ "xorq $dst, $src\t# long" %}
10184 ins_encode %{
10185 __ xorq($dst$$Register, $src$$Address);
10186 %}
10187 ins_pipe(ialu_reg_mem);
10188 %}
10189
10190 // Xor Memory with Register
10191 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10192 %{
10193 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10194 effect(KILL cr);
10195
10196 ins_cost(150);
10197 format %{ "xorq $dst, $src\t# long" %}
10198 ins_encode %{
10199 __ xorq($dst$$Address, $src$$Register);
10200 %}
10201 ins_pipe(ialu_mem_reg);
10202 %}
10203
10204 // Xor Memory with Immediate
10205 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10206 %{
10207 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10208 effect(KILL cr);
10209
10210 ins_cost(125);
10211 format %{ "xorq $dst, $src\t# long" %}
10212 ins_encode %{
10213 __ xorq($dst$$Address, $src$$constant);
10214 %}
10215 ins_pipe(ialu_mem_imm);
10216 %}
10217
10218 // Convert Int to Boolean
10219 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10220 %{
10221 match(Set dst (Conv2B src));
10222 effect(KILL cr);
10223
10224 format %{ "testl $src, $src\t# ci2b\n\t"
10225 "setnz $dst\n\t"
10226 "movzbl $dst, $dst" %}
10227 ins_encode %{
10228 __ testl($src$$Register, $src$$Register);
10229 __ set_byte_if_not_zero($dst$$Register);
10230 __ movzbl($dst$$Register, $dst$$Register);
10231 %}
10232 ins_pipe(pipe_slow); // XXX
10233 %}
10234
10235 // Convert Pointer to Boolean
10236 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10237 %{
10238 match(Set dst (Conv2B src));
10239 effect(KILL cr);
10240
10241 format %{ "testq $src, $src\t# cp2b\n\t"
10242 "setnz $dst\n\t"
10243 "movzbl $dst, $dst" %}
10244 ins_encode %{
10245 __ testq($src$$Register, $src$$Register);
10246 __ set_byte_if_not_zero($dst$$Register);
10247 __ movzbl($dst$$Register, $dst$$Register);
10248 %}
10249 ins_pipe(pipe_slow); // XXX
10250 %}
10251
10252 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10253 %{
10254 match(Set dst (CmpLTMask p q));
10255 effect(KILL cr);
10256
10257 ins_cost(400);
10258 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
10259 "setlt $dst\n\t"
10260 "movzbl $dst, $dst\n\t"
10261 "negl $dst" %}
10262 ins_encode %{
10263 __ cmpl($p$$Register, $q$$Register);
10264 __ setl($dst$$Register);
10265 __ movzbl($dst$$Register, $dst$$Register);
10266 __ negl($dst$$Register);
10267 %}
10268 ins_pipe(pipe_slow);
10269 %}
10270
10271 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
10272 %{
10273 match(Set dst (CmpLTMask dst zero));
10274 effect(KILL cr);
10275
10276 ins_cost(100);
10277 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
10278 ins_encode %{
10279 __ sarl($dst$$Register, 31);
10280 %}
10281 ins_pipe(ialu_reg);
10282 %}
10283
10284 /* Better to save a register than avoid a branch */
10285 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10286 %{
10287 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10288 effect(KILL cr);
10289 ins_cost(300);
10290 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
10291 "jge done\n\t"
10292 "addl $p,$y\n"
10293 "done: " %}
10294 ins_encode %{
10295 Register Rp = $p$$Register;
10296 Register Rq = $q$$Register;
10297 Register Ry = $y$$Register;
10298 Label done;
10299 __ subl(Rp, Rq);
10300 __ jccb(Assembler::greaterEqual, done);
10301 __ addl(Rp, Ry);
10302 __ bind(done);
10303 %}
10304 ins_pipe(pipe_cmplt);
10305 %}
10306
10307 /* Better to save a register than avoid a branch */
10308 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10309 %{
10310 match(Set y (AndI (CmpLTMask p q) y));
10311 effect(KILL cr);
10312
10313 ins_cost(300);
10314
10315 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
10316 "jlt done\n\t"
10317 "xorl $y, $y\n"
10318 "done: " %}
10319 ins_encode %{
10320 Register Rp = $p$$Register;
10321 Register Rq = $q$$Register;
10322 Register Ry = $y$$Register;
10323 Label done;
10324 __ cmpl(Rp, Rq);
10325 __ jccb(Assembler::less, done);
10326 __ xorl(Ry, Ry);
10327 __ bind(done);
10328 %}
10329 ins_pipe(pipe_cmplt);
10330 %}
10331
10332
10333 //---------- FP Instructions------------------------------------------------
10334
10335 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10336 %{
10337 match(Set cr (CmpF src1 src2));
10338
10339 ins_cost(145);
10340 format %{ "ucomiss $src1, $src2\n\t"
10341 "jnp,s exit\n\t"
10342 "pushfq\t# saw NaN, set CF\n\t"
10343 "andq [rsp], #0xffffff2b\n\t"
10344 "popfq\n"
10345 "exit:" %}
10346 ins_encode %{
10347 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10348 emit_cmpfp_fixup(_masm);
10349 %}
10350 ins_pipe(pipe_slow);
10351 %}
10352
10353 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10354 match(Set cr (CmpF src1 src2));
10355
10356 ins_cost(100);
10357 format %{ "ucomiss $src1, $src2" %}
10358 ins_encode %{
10359 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10360 %}
10361 ins_pipe(pipe_slow);
10362 %}
10363
10364 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10365 %{
10366 match(Set cr (CmpF src1 (LoadF src2)));
10367
10368 ins_cost(145);
10369 format %{ "ucomiss $src1, $src2\n\t"
10370 "jnp,s exit\n\t"
10371 "pushfq\t# saw NaN, set CF\n\t"
10372 "andq [rsp], #0xffffff2b\n\t"
10373 "popfq\n"
10374 "exit:" %}
10375 ins_encode %{
10376 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10377 emit_cmpfp_fixup(_masm);
10378 %}
10379 ins_pipe(pipe_slow);
10380 %}
10381
10382 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10383 match(Set cr (CmpF src1 (LoadF src2)));
10384
10385 ins_cost(100);
10386 format %{ "ucomiss $src1, $src2" %}
10387 ins_encode %{
10388 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10389 %}
10390 ins_pipe(pipe_slow);
10391 %}
10392
10393 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10394 match(Set cr (CmpF src con));
10395
10396 ins_cost(145);
10397 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10398 "jnp,s exit\n\t"
10399 "pushfq\t# saw NaN, set CF\n\t"
10400 "andq [rsp], #0xffffff2b\n\t"
10401 "popfq\n"
10402 "exit:" %}
10403 ins_encode %{
10404 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10405 emit_cmpfp_fixup(_masm);
10406 %}
10407 ins_pipe(pipe_slow);
10408 %}
10409
10410 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10411 match(Set cr (CmpF src con));
10412 ins_cost(100);
10413 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10414 ins_encode %{
10415 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10416 %}
10417 ins_pipe(pipe_slow);
10418 %}
10419
10420 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10421 %{
10422 match(Set cr (CmpD src1 src2));
10423
10424 ins_cost(145);
10425 format %{ "ucomisd $src1, $src2\n\t"
10426 "jnp,s exit\n\t"
10427 "pushfq\t# saw NaN, set CF\n\t"
10428 "andq [rsp], #0xffffff2b\n\t"
10429 "popfq\n"
10430 "exit:" %}
10431 ins_encode %{
10432 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10433 emit_cmpfp_fixup(_masm);
10434 %}
10435 ins_pipe(pipe_slow);
10436 %}
10437
10438 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10439 match(Set cr (CmpD src1 src2));
10440
10441 ins_cost(100);
10442 format %{ "ucomisd $src1, $src2 test" %}
10443 ins_encode %{
10444 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10445 %}
10446 ins_pipe(pipe_slow);
10447 %}
10448
10449 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10450 %{
10451 match(Set cr (CmpD src1 (LoadD src2)));
10452
10453 ins_cost(145);
10454 format %{ "ucomisd $src1, $src2\n\t"
10455 "jnp,s exit\n\t"
10456 "pushfq\t# saw NaN, set CF\n\t"
10457 "andq [rsp], #0xffffff2b\n\t"
10458 "popfq\n"
10459 "exit:" %}
10460 ins_encode %{
10461 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10462 emit_cmpfp_fixup(_masm);
10463 %}
10464 ins_pipe(pipe_slow);
10465 %}
10466
10467 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10468 match(Set cr (CmpD src1 (LoadD src2)));
10469
10470 ins_cost(100);
10471 format %{ "ucomisd $src1, $src2" %}
10472 ins_encode %{
10473 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10474 %}
10475 ins_pipe(pipe_slow);
10476 %}
10477
10478 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10479 match(Set cr (CmpD src con));
10480
10481 ins_cost(145);
10482 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10483 "jnp,s exit\n\t"
10484 "pushfq\t# saw NaN, set CF\n\t"
10485 "andq [rsp], #0xffffff2b\n\t"
10486 "popfq\n"
10487 "exit:" %}
10488 ins_encode %{
10489 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10490 emit_cmpfp_fixup(_masm);
10491 %}
10492 ins_pipe(pipe_slow);
10493 %}
10494
10495 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10496 match(Set cr (CmpD src con));
10497 ins_cost(100);
10498 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10499 ins_encode %{
10500 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10501 %}
10502 ins_pipe(pipe_slow);
10503 %}
10504
10505 // Compare into -1,0,1
10506 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10507 %{
10508 match(Set dst (CmpF3 src1 src2));
10509 effect(KILL cr);
10510
10511 ins_cost(275);
10512 format %{ "ucomiss $src1, $src2\n\t"
10513 "movl $dst, #-1\n\t"
10514 "jp,s done\n\t"
10515 "jb,s done\n\t"
10516 "setne $dst\n\t"
10517 "movzbl $dst, $dst\n"
10518 "done:" %}
10519 ins_encode %{
10520 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10521 emit_cmpfp3(_masm, $dst$$Register);
10522 %}
10523 ins_pipe(pipe_slow);
10524 %}
10525
10526 // Compare into -1,0,1
10527 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10528 %{
10529 match(Set dst (CmpF3 src1 (LoadF src2)));
10530 effect(KILL cr);
10531
10532 ins_cost(275);
10533 format %{ "ucomiss $src1, $src2\n\t"
10534 "movl $dst, #-1\n\t"
10535 "jp,s done\n\t"
10536 "jb,s done\n\t"
10537 "setne $dst\n\t"
10538 "movzbl $dst, $dst\n"
10539 "done:" %}
10540 ins_encode %{
10541 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10542 emit_cmpfp3(_masm, $dst$$Register);
10543 %}
10544 ins_pipe(pipe_slow);
10545 %}
10546
10547 // Compare into -1,0,1
10548 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10549 match(Set dst (CmpF3 src con));
10550 effect(KILL cr);
10551
10552 ins_cost(275);
10553 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10554 "movl $dst, #-1\n\t"
10555 "jp,s done\n\t"
10556 "jb,s done\n\t"
10557 "setne $dst\n\t"
10558 "movzbl $dst, $dst\n"
10559 "done:" %}
10560 ins_encode %{
10561 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10562 emit_cmpfp3(_masm, $dst$$Register);
10563 %}
10564 ins_pipe(pipe_slow);
10565 %}
10566
10567 // Compare into -1,0,1
10568 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10569 %{
10570 match(Set dst (CmpD3 src1 src2));
10571 effect(KILL cr);
10572
10573 ins_cost(275);
10574 format %{ "ucomisd $src1, $src2\n\t"
10575 "movl $dst, #-1\n\t"
10576 "jp,s done\n\t"
10577 "jb,s done\n\t"
10578 "setne $dst\n\t"
10579 "movzbl $dst, $dst\n"
10580 "done:" %}
10581 ins_encode %{
10582 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10583 emit_cmpfp3(_masm, $dst$$Register);
10584 %}
10585 ins_pipe(pipe_slow);
10586 %}
10587
10588 // Compare into -1,0,1
10589 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10590 %{
10591 match(Set dst (CmpD3 src1 (LoadD src2)));
10592 effect(KILL cr);
10593
10594 ins_cost(275);
10595 format %{ "ucomisd $src1, $src2\n\t"
10596 "movl $dst, #-1\n\t"
10597 "jp,s done\n\t"
10598 "jb,s done\n\t"
10599 "setne $dst\n\t"
10600 "movzbl $dst, $dst\n"
10601 "done:" %}
10602 ins_encode %{
10603 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10604 emit_cmpfp3(_masm, $dst$$Register);
10605 %}
10606 ins_pipe(pipe_slow);
10607 %}
10608
10609 // Compare into -1,0,1
10610 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10611 match(Set dst (CmpD3 src con));
10612 effect(KILL cr);
10613
10614 ins_cost(275);
10615 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10616 "movl $dst, #-1\n\t"
10617 "jp,s done\n\t"
10618 "jb,s done\n\t"
10619 "setne $dst\n\t"
10620 "movzbl $dst, $dst\n"
10621 "done:" %}
10622 ins_encode %{
10623 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10624 emit_cmpfp3(_masm, $dst$$Register);
10625 %}
10626 ins_pipe(pipe_slow);
10627 %}
10628
10629 //----------Arithmetic Conversion Instructions---------------------------------
10630
10631 instruct convF2D_reg_reg(regD dst, regF src)
10632 %{
10633 match(Set dst (ConvF2D src));
10634
10635 format %{ "cvtss2sd $dst, $src" %}
10636 ins_encode %{
10637 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10638 %}
10639 ins_pipe(pipe_slow); // XXX
10640 %}
10641
10642 instruct convF2D_reg_mem(regD dst, memory src)
10643 %{
10644 match(Set dst (ConvF2D (LoadF src)));
10645
10646 format %{ "cvtss2sd $dst, $src" %}
10647 ins_encode %{
10648 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10649 %}
10650 ins_pipe(pipe_slow); // XXX
10651 %}
10652
10653 instruct convD2F_reg_reg(regF dst, regD src)
10654 %{
10655 match(Set dst (ConvD2F src));
10656
10657 format %{ "cvtsd2ss $dst, $src" %}
10658 ins_encode %{
10659 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10660 %}
10661 ins_pipe(pipe_slow); // XXX
10662 %}
10663
10664 instruct convD2F_reg_mem(regF dst, memory src)
10665 %{
10666 match(Set dst (ConvD2F (LoadD src)));
10667
10668 format %{ "cvtsd2ss $dst, $src" %}
10669 ins_encode %{
10670 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10671 %}
10672 ins_pipe(pipe_slow); // XXX
10673 %}
10674
10675 // XXX do mem variants
10676 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10677 %{
10678 match(Set dst (ConvF2I src));
10679 effect(KILL cr);
10680 format %{ "convert_f2i $dst,$src" %}
10681 ins_encode %{
10682 __ convert_f2i($dst$$Register, $src$$XMMRegister);
10683 %}
10684 ins_pipe(pipe_slow);
10685 %}
10686
10687 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10688 %{
10689 match(Set dst (ConvF2L src));
10690 effect(KILL cr);
10691 format %{ "convert_f2l $dst,$src"%}
10692 ins_encode %{
10693 __ convert_f2l($dst$$Register, $src$$XMMRegister);
10694 %}
10695 ins_pipe(pipe_slow);
10696 %}
10697
10698 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10699 %{
10700 match(Set dst (ConvD2I src));
10701 effect(KILL cr);
10702 format %{ "convert_d2i $dst,$src"%}
10703 ins_encode %{
10704 __ convert_d2i($dst$$Register, $src$$XMMRegister);
10705 %}
10706 ins_pipe(pipe_slow);
10707 %}
10708
10709 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10710 %{
10711 match(Set dst (ConvD2L src));
10712 effect(KILL cr);
10713 format %{ "convert_d2l $dst,$src"%}
10714 ins_encode %{
10715 __ convert_d2l($dst$$Register, $src$$XMMRegister);
10716 %}
10717 ins_pipe(pipe_slow);
10718 %}
10719
10720 instruct convI2F_reg_reg(regF dst, rRegI src)
10721 %{
10722 predicate(!UseXmmI2F);
10723 match(Set dst (ConvI2F src));
10724
10725 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10726 ins_encode %{
10727 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10728 %}
10729 ins_pipe(pipe_slow); // XXX
10730 %}
10731
10732 instruct convI2F_reg_mem(regF dst, memory src)
10733 %{
10734 match(Set dst (ConvI2F (LoadI src)));
10735
10736 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10737 ins_encode %{
10738 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10739 %}
10740 ins_pipe(pipe_slow); // XXX
10741 %}
10742
10743 instruct convI2D_reg_reg(regD dst, rRegI src)
10744 %{
10745 predicate(!UseXmmI2D);
10746 match(Set dst (ConvI2D src));
10747
10748 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10749 ins_encode %{
10750 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10751 %}
10752 ins_pipe(pipe_slow); // XXX
10753 %}
10754
10755 instruct convI2D_reg_mem(regD dst, memory src)
10756 %{
10757 match(Set dst (ConvI2D (LoadI src)));
10758
10759 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10760 ins_encode %{
10761 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10762 %}
10763 ins_pipe(pipe_slow); // XXX
10764 %}
10765
10766 instruct convXI2F_reg(regF dst, rRegI src)
10767 %{
10768 predicate(UseXmmI2F);
10769 match(Set dst (ConvI2F src));
10770
10771 format %{ "movdl $dst, $src\n\t"
10772 "cvtdq2psl $dst, $dst\t# i2f" %}
10773 ins_encode %{
10774 __ movdl($dst$$XMMRegister, $src$$Register);
10775 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10776 %}
10777 ins_pipe(pipe_slow); // XXX
10778 %}
10779
10780 instruct convXI2D_reg(regD dst, rRegI src)
10781 %{
10782 predicate(UseXmmI2D);
10783 match(Set dst (ConvI2D src));
10784
10785 format %{ "movdl $dst, $src\n\t"
10786 "cvtdq2pdl $dst, $dst\t# i2d" %}
10787 ins_encode %{
10788 __ movdl($dst$$XMMRegister, $src$$Register);
10789 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10790 %}
10791 ins_pipe(pipe_slow); // XXX
10792 %}
10793
10794 instruct convL2F_reg_reg(regF dst, rRegL src)
10795 %{
10796 match(Set dst (ConvL2F src));
10797
10798 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10799 ins_encode %{
10800 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10801 %}
10802 ins_pipe(pipe_slow); // XXX
10803 %}
10804
10805 instruct convL2F_reg_mem(regF dst, memory src)
10806 %{
10807 match(Set dst (ConvL2F (LoadL src)));
10808
10809 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10810 ins_encode %{
10811 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10812 %}
10813 ins_pipe(pipe_slow); // XXX
10814 %}
10815
10816 instruct convL2D_reg_reg(regD dst, rRegL src)
10817 %{
10818 match(Set dst (ConvL2D src));
10819
10820 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10821 ins_encode %{
10822 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10823 %}
10824 ins_pipe(pipe_slow); // XXX
10825 %}
10826
10827 instruct convL2D_reg_mem(regD dst, memory src)
10828 %{
10829 match(Set dst (ConvL2D (LoadL src)));
10830
10831 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10832 ins_encode %{
10833 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10834 %}
10835 ins_pipe(pipe_slow); // XXX
10836 %}
10837
10838 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10839 %{
10840 match(Set dst (ConvI2L src));
10841
10842 ins_cost(125);
10843 format %{ "movslq $dst, $src\t# i2l" %}
10844 ins_encode %{
10845 __ movslq($dst$$Register, $src$$Register);
10846 %}
10847 ins_pipe(ialu_reg_reg);
10848 %}
10849
10850 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10851 // %{
10852 // match(Set dst (ConvI2L src));
10853 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10854 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10855 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10856 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10857 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10858 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10859
10860 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10861 // ins_encode(enc_copy(dst, src));
10862 // // opcode(0x63); // needs REX.W
10863 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10864 // ins_pipe(ialu_reg_reg);
10865 // %}
10866
10867 // Zero-extend convert int to long
10868 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10869 %{
10870 match(Set dst (AndL (ConvI2L src) mask));
10871
10872 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10873 ins_encode %{
10874 if ($dst$$reg != $src$$reg) {
10875 __ movl($dst$$Register, $src$$Register);
10876 }
10877 %}
10878 ins_pipe(ialu_reg_reg);
10879 %}
10880
10881 // Zero-extend convert int to long
10882 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10883 %{
10884 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10885
10886 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10887 ins_encode %{
10888 __ movl($dst$$Register, $src$$Address);
10889 %}
10890 ins_pipe(ialu_reg_mem);
10891 %}
10892
10893 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10894 %{
10895 match(Set dst (AndL src mask));
10896
10897 format %{ "movl $dst, $src\t# zero-extend long" %}
10898 ins_encode %{
10899 __ movl($dst$$Register, $src$$Register);
10900 %}
10901 ins_pipe(ialu_reg_reg);
10902 %}
10903
10904 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10905 %{
10906 match(Set dst (ConvL2I src));
10907
10908 format %{ "movl $dst, $src\t# l2i" %}
10909 ins_encode %{
10910 __ movl($dst$$Register, $src$$Register);
10911 %}
10912 ins_pipe(ialu_reg_reg);
10913 %}
10914
10915
10916 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10917 match(Set dst (MoveF2I src));
10918 effect(DEF dst, USE src);
10919
10920 ins_cost(125);
10921 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10922 ins_encode %{
10923 __ movl($dst$$Register, Address(rsp, $src$$disp));
10924 %}
10925 ins_pipe(ialu_reg_mem);
10926 %}
10927
10928 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10929 match(Set dst (MoveI2F src));
10930 effect(DEF dst, USE src);
10931
10932 ins_cost(125);
10933 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10934 ins_encode %{
10935 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10936 %}
10937 ins_pipe(pipe_slow);
10938 %}
10939
10940 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10941 match(Set dst (MoveD2L src));
10942 effect(DEF dst, USE src);
10943
10944 ins_cost(125);
10945 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10946 ins_encode %{
10947 __ movq($dst$$Register, Address(rsp, $src$$disp));
10948 %}
10949 ins_pipe(ialu_reg_mem);
10950 %}
10951
10952 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10953 predicate(!UseXmmLoadAndClearUpper);
10954 match(Set dst (MoveL2D src));
10955 effect(DEF dst, USE src);
10956
10957 ins_cost(125);
10958 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10959 ins_encode %{
10960 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10961 %}
10962 ins_pipe(pipe_slow);
10963 %}
10964
10965 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10966 predicate(UseXmmLoadAndClearUpper);
10967 match(Set dst (MoveL2D src));
10968 effect(DEF dst, USE src);
10969
10970 ins_cost(125);
10971 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10972 ins_encode %{
10973 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10974 %}
10975 ins_pipe(pipe_slow);
10976 %}
10977
10978
10979 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10980 match(Set dst (MoveF2I src));
10981 effect(DEF dst, USE src);
10982
10983 ins_cost(95); // XXX
10984 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10985 ins_encode %{
10986 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10987 %}
10988 ins_pipe(pipe_slow);
10989 %}
10990
10991 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10992 match(Set dst (MoveI2F src));
10993 effect(DEF dst, USE src);
10994
10995 ins_cost(100);
10996 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10997 ins_encode %{
10998 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10999 %}
11000 ins_pipe( ialu_mem_reg );
11001 %}
11002
11003 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
11004 match(Set dst (MoveD2L src));
11005 effect(DEF dst, USE src);
11006
11007 ins_cost(95); // XXX
11008 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
11009 ins_encode %{
11010 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
11011 %}
11012 ins_pipe(pipe_slow);
11013 %}
11014
11015 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
11016 match(Set dst (MoveL2D src));
11017 effect(DEF dst, USE src);
11018
11019 ins_cost(100);
11020 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
11021 ins_encode %{
11022 __ movq(Address(rsp, $dst$$disp), $src$$Register);
11023 %}
11024 ins_pipe(ialu_mem_reg);
11025 %}
11026
11027 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
11028 match(Set dst (MoveF2I src));
11029 effect(DEF dst, USE src);
11030 ins_cost(85);
11031 format %{ "movd $dst,$src\t# MoveF2I" %}
11032 ins_encode %{
11033 __ movdl($dst$$Register, $src$$XMMRegister);
11034 %}
11035 ins_pipe( pipe_slow );
11036 %}
11037
11038 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
11039 match(Set dst (MoveD2L src));
11040 effect(DEF dst, USE src);
11041 ins_cost(85);
11042 format %{ "movd $dst,$src\t# MoveD2L" %}
11043 ins_encode %{
11044 __ movdq($dst$$Register, $src$$XMMRegister);
11045 %}
11046 ins_pipe( pipe_slow );
11047 %}
11048
11049 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11050 match(Set dst (MoveI2F src));
11051 effect(DEF dst, USE src);
11052 ins_cost(100);
11053 format %{ "movd $dst,$src\t# MoveI2F" %}
11054 ins_encode %{
11055 __ movdl($dst$$XMMRegister, $src$$Register);
11056 %}
11057 ins_pipe( pipe_slow );
11058 %}
11059
11060 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11061 match(Set dst (MoveL2D src));
11062 effect(DEF dst, USE src);
11063 ins_cost(100);
11064 format %{ "movd $dst,$src\t# MoveL2D" %}
11065 ins_encode %{
11066 __ movdq($dst$$XMMRegister, $src$$Register);
11067 %}
11068 ins_pipe( pipe_slow );
11069 %}
11070
11071
11072 // Fast clearing of an array
11073 // Small ClearArray non-AVX512.
11074 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegL val,
11075 Universe dummy, rFlagsReg cr)
11076 %{
11077 predicate(!((ClearArrayNode*)n)->is_large() && !((ClearArrayNode*)n)->word_copy_only() && (UseAVX <= 2));
11078 match(Set dummy (ClearArray (Binary cnt base) val));
11079 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, USE_KILL val, KILL cr);
11080
11081 format %{ $$template
11082 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11083 $$emit$$"jg LARGE\n\t"
11084 $$emit$$"dec rcx\n\t"
11085 $$emit$$"js DONE\t# Zero length\n\t"
11086 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11087 $$emit$$"dec rcx\n\t"
11088 $$emit$$"jge LOOP\n\t"
11089 $$emit$$"jmp DONE\n\t"
11090 $$emit$$"# LARGE:\n\t"
11091 if (UseFastStosb) {
11092 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11093 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11094 } else if (UseXMMForObjInit) {
11095 $$emit$$"movdq $tmp, $val\n\t"
11096 $$emit$$"punpcklqdq $tmp, $tmp\n\t"
11097 $$emit$$"vinserti128_high $tmp, $tmp\n\t"
11098 $$emit$$"jmpq L_zero_64_bytes\n\t"
11099 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11100 $$emit$$"vmovdqu $tmp,(rax)\n\t"
11101 $$emit$$"vmovdqu $tmp,0x20(rax)\n\t"
11102 $$emit$$"add 0x40,rax\n\t"
11103 $$emit$$"# L_zero_64_bytes:\n\t"
11104 $$emit$$"sub 0x8,rcx\n\t"
11105 $$emit$$"jge L_loop\n\t"
11106 $$emit$$"add 0x4,rcx\n\t"
11107 $$emit$$"jl L_tail\n\t"
11108 $$emit$$"vmovdqu $tmp,(rax)\n\t"
11109 $$emit$$"add 0x20,rax\n\t"
11110 $$emit$$"sub 0x4,rcx\n\t"
11111 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11112 $$emit$$"add 0x4,rcx\n\t"
11113 $$emit$$"jle L_end\n\t"
11114 $$emit$$"dec rcx\n\t"
11115 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11116 $$emit$$"vmovq xmm0,(rax)\n\t"
11117 $$emit$$"add 0x8,rax\n\t"
11118 $$emit$$"dec rcx\n\t"
11119 $$emit$$"jge L_sloop\n\t"
11120 $$emit$$"# L_end:\n\t"
11121 } else {
11122 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11123 }
11124 $$emit$$"# DONE"
11125 %}
11126 ins_encode %{
11127 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
11128 $tmp$$XMMRegister, false, false);
11129 %}
11130 ins_pipe(pipe_slow);
11131 %}
11132
11133 instruct rep_stos_word_copy(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegL val,
11134 Universe dummy, rFlagsReg cr)
11135 %{
11136 predicate(!((ClearArrayNode*)n)->is_large() && ((ClearArrayNode*)n)->word_copy_only() && (UseAVX <= 2));
11137 match(Set dummy (ClearArray (Binary cnt base) val));
11138 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, USE_KILL val, KILL cr);
11139
11140 format %{ $$template
11141 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11142 $$emit$$"jg LARGE\n\t"
11143 $$emit$$"dec rcx\n\t"
11144 $$emit$$"js DONE\t# Zero length\n\t"
11145 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11146 $$emit$$"dec rcx\n\t"
11147 $$emit$$"jge LOOP\n\t"
11148 $$emit$$"jmp DONE\n\t"
11149 $$emit$$"# LARGE:\n\t"
11150 if (UseXMMForObjInit) {
11151 $$emit$$"movdq $tmp, $val\n\t"
11152 $$emit$$"punpcklqdq $tmp, $tmp\n\t"
11153 $$emit$$"vinserti128_high $tmp, $tmp\n\t"
11154 $$emit$$"jmpq L_zero_64_bytes\n\t"
11155 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11156 $$emit$$"vmovdqu $tmp,(rax)\n\t"
11157 $$emit$$"vmovdqu $tmp,0x20(rax)\n\t"
11158 $$emit$$"add 0x40,rax\n\t"
11159 $$emit$$"# L_zero_64_bytes:\n\t"
11160 $$emit$$"sub 0x8,rcx\n\t"
11161 $$emit$$"jge L_loop\n\t"
11162 $$emit$$"add 0x4,rcx\n\t"
11163 $$emit$$"jl L_tail\n\t"
11164 $$emit$$"vmovdqu $tmp,(rax)\n\t"
11165 $$emit$$"add 0x20,rax\n\t"
11166 $$emit$$"sub 0x4,rcx\n\t"
11167 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11168 $$emit$$"add 0x4,rcx\n\t"
11169 $$emit$$"jle L_end\n\t"
11170 $$emit$$"dec rcx\n\t"
11171 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11172 $$emit$$"vmovq xmm0,(rax)\n\t"
11173 $$emit$$"add 0x8,rax\n\t"
11174 $$emit$$"dec rcx\n\t"
11175 $$emit$$"jge L_sloop\n\t"
11176 $$emit$$"# L_end:\n\t"
11177 } else {
11178 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11179 }
11180 $$emit$$"# DONE"
11181 %}
11182 ins_encode %{
11183 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
11184 $tmp$$XMMRegister, false, true);
11185 %}
11186 ins_pipe(pipe_slow);
11187 %}
11188
11189 // Small ClearArray AVX512 non-constant length.
11190 instruct rep_stos_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegL val,
11191 Universe dummy, rFlagsReg cr)
11192 %{
11193 predicate(!((ClearArrayNode*)n)->is_large() && !((ClearArrayNode*)n)->word_copy_only() && (UseAVX > 2));
11194 match(Set dummy (ClearArray (Binary cnt base) val));
11195 ins_cost(125);
11196 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, USE_KILL val, KILL cr);
11197
11198 format %{ $$template
11199 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11200 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11201 $$emit$$"jg LARGE\n\t"
11202 $$emit$$"dec rcx\n\t"
11203 $$emit$$"js DONE\t# Zero length\n\t"
11204 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11205 $$emit$$"dec rcx\n\t"
11206 $$emit$$"jge LOOP\n\t"
11207 $$emit$$"jmp DONE\n\t"
11208 $$emit$$"# LARGE:\n\t"
11209 if (UseFastStosb) {
11210 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11211 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11212 } else if (UseXMMForObjInit) {
11213 $$emit$$"mov rdi,rax\n\t"
11214 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11215 $$emit$$"jmpq L_zero_64_bytes\n\t"
11216 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11217 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11218 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11219 $$emit$$"add 0x40,rax\n\t"
11220 $$emit$$"# L_zero_64_bytes:\n\t"
11221 $$emit$$"sub 0x8,rcx\n\t"
11222 $$emit$$"jge L_loop\n\t"
11223 $$emit$$"add 0x4,rcx\n\t"
11224 $$emit$$"jl L_tail\n\t"
11225 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11226 $$emit$$"add 0x20,rax\n\t"
11227 $$emit$$"sub 0x4,rcx\n\t"
11228 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11229 $$emit$$"add 0x4,rcx\n\t"
11230 $$emit$$"jle L_end\n\t"
11231 $$emit$$"dec rcx\n\t"
11232 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11233 $$emit$$"vmovq xmm0,(rax)\n\t"
11234 $$emit$$"add 0x8,rax\n\t"
11235 $$emit$$"dec rcx\n\t"
11236 $$emit$$"jge L_sloop\n\t"
11237 $$emit$$"# L_end:\n\t"
11238 } else {
11239 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11240 }
11241 $$emit$$"# DONE"
11242 %}
11243 ins_encode %{
11244 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
11245 $tmp$$XMMRegister, false, false, $ktmp$$KRegister);
11246 %}
11247 ins_pipe(pipe_slow);
11248 %}
11249
11250 instruct rep_stos_evex_word_copy(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegL val,
11251 Universe dummy, rFlagsReg cr)
11252 %{
11253 predicate(!((ClearArrayNode*)n)->is_large() && ((ClearArrayNode*)n)->word_copy_only() && (UseAVX > 2));
11254 match(Set dummy (ClearArray (Binary cnt base) val));
11255 ins_cost(125);
11256 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, USE_KILL val, KILL cr);
11257
11258 format %{ $$template
11259 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11260 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
11261 $$emit$$"jg LARGE\n\t"
11262 $$emit$$"dec rcx\n\t"
11263 $$emit$$"js DONE\t# Zero length\n\t"
11264 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
11265 $$emit$$"dec rcx\n\t"
11266 $$emit$$"jge LOOP\n\t"
11267 $$emit$$"jmp DONE\n\t"
11268 $$emit$$"# LARGE:\n\t"
11269 if (UseFastStosb) {
11270 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11271 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
11272 } else if (UseXMMForObjInit) {
11273 $$emit$$"mov rdi,rax\n\t"
11274 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11275 $$emit$$"jmpq L_zero_64_bytes\n\t"
11276 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11277 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11278 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11279 $$emit$$"add 0x40,rax\n\t"
11280 $$emit$$"# L_zero_64_bytes:\n\t"
11281 $$emit$$"sub 0x8,rcx\n\t"
11282 $$emit$$"jge L_loop\n\t"
11283 $$emit$$"add 0x4,rcx\n\t"
11284 $$emit$$"jl L_tail\n\t"
11285 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11286 $$emit$$"add 0x20,rax\n\t"
11287 $$emit$$"sub 0x4,rcx\n\t"
11288 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11289 $$emit$$"add 0x4,rcx\n\t"
11290 $$emit$$"jle L_end\n\t"
11291 $$emit$$"dec rcx\n\t"
11292 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11293 $$emit$$"vmovq xmm0,(rax)\n\t"
11294 $$emit$$"add 0x8,rax\n\t"
11295 $$emit$$"dec rcx\n\t"
11296 $$emit$$"jge L_sloop\n\t"
11297 $$emit$$"# L_end:\n\t"
11298 } else {
11299 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
11300 }
11301 $$emit$$"# DONE"
11302 %}
11303 ins_encode %{
11304 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
11305 $tmp$$XMMRegister, false, true, $ktmp$$KRegister);
11306 %}
11307 ins_pipe(pipe_slow);
11308 %}
11309
11310 // Large ClearArray non-AVX512.
11311 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegL val,
11312 Universe dummy, rFlagsReg cr)
11313 %{
11314 predicate(((ClearArrayNode*)n)->is_large() && !((ClearArrayNode*)n)->word_copy_only() && (UseAVX <= 2));
11315 match(Set dummy (ClearArray (Binary cnt base) val));
11316 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, USE_KILL val, KILL cr);
11317
11318 format %{ $$template
11319 if (UseFastStosb) {
11320 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11321 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11322 } else if (UseXMMForObjInit) {
11323 $$emit$$"movdq $tmp, $val\n\t"
11324 $$emit$$"punpcklqdq $tmp, $tmp\n\t"
11325 $$emit$$"vinserti128_high $tmp, $tmp\n\t"
11326 $$emit$$"jmpq L_zero_64_bytes\n\t"
11327 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11328 $$emit$$"vmovdqu $tmp,(rax)\n\t"
11329 $$emit$$"vmovdqu $tmp,0x20(rax)\n\t"
11330 $$emit$$"add 0x40,rax\n\t"
11331 $$emit$$"# L_zero_64_bytes:\n\t"
11332 $$emit$$"sub 0x8,rcx\n\t"
11333 $$emit$$"jge L_loop\n\t"
11334 $$emit$$"add 0x4,rcx\n\t"
11335 $$emit$$"jl L_tail\n\t"
11336 $$emit$$"vmovdqu $tmp,(rax)\n\t"
11337 $$emit$$"add 0x20,rax\n\t"
11338 $$emit$$"sub 0x4,rcx\n\t"
11339 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11340 $$emit$$"add 0x4,rcx\n\t"
11341 $$emit$$"jle L_end\n\t"
11342 $$emit$$"dec rcx\n\t"
11343 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11344 $$emit$$"vmovq xmm0,(rax)\n\t"
11345 $$emit$$"add 0x8,rax\n\t"
11346 $$emit$$"dec rcx\n\t"
11347 $$emit$$"jge L_sloop\n\t"
11348 $$emit$$"# L_end:\n\t"
11349 } else {
11350 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11351 }
11352 %}
11353 ins_encode %{
11354 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
11355 $tmp$$XMMRegister, true, false);
11356 %}
11357 ins_pipe(pipe_slow);
11358 %}
11359
11360 instruct rep_stos_large_word_copy(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegL val,
11361 Universe dummy, rFlagsReg cr)
11362 %{
11363 predicate(((ClearArrayNode*)n)->is_large() && ((ClearArrayNode*)n)->word_copy_only() && (UseAVX <= 2));
11364 match(Set dummy (ClearArray (Binary cnt base) val));
11365 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, USE_KILL val, KILL cr);
11366
11367 format %{ $$template
11368 if (UseXMMForObjInit) {
11369 $$emit$$"movdq $tmp, $val\n\t"
11370 $$emit$$"punpcklqdq $tmp, $tmp\n\t"
11371 $$emit$$"vinserti128_high $tmp, $tmp\n\t"
11372 $$emit$$"jmpq L_zero_64_bytes\n\t"
11373 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11374 $$emit$$"vmovdqu $tmp,(rax)\n\t"
11375 $$emit$$"vmovdqu $tmp,0x20(rax)\n\t"
11376 $$emit$$"add 0x40,rax\n\t"
11377 $$emit$$"# L_zero_64_bytes:\n\t"
11378 $$emit$$"sub 0x8,rcx\n\t"
11379 $$emit$$"jge L_loop\n\t"
11380 $$emit$$"add 0x4,rcx\n\t"
11381 $$emit$$"jl L_tail\n\t"
11382 $$emit$$"vmovdqu $tmp,(rax)\n\t"
11383 $$emit$$"add 0x20,rax\n\t"
11384 $$emit$$"sub 0x4,rcx\n\t"
11385 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11386 $$emit$$"add 0x4,rcx\n\t"
11387 $$emit$$"jle L_end\n\t"
11388 $$emit$$"dec rcx\n\t"
11389 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11390 $$emit$$"vmovq xmm0,(rax)\n\t"
11391 $$emit$$"add 0x8,rax\n\t"
11392 $$emit$$"dec rcx\n\t"
11393 $$emit$$"jge L_sloop\n\t"
11394 $$emit$$"# L_end:\n\t"
11395 } else {
11396 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11397 }
11398 %}
11399 ins_encode %{
11400 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
11401 $tmp$$XMMRegister, true, true);
11402 %}
11403 ins_pipe(pipe_slow);
11404 %}
11405
11406 // Large ClearArray AVX512.
11407 instruct rep_stos_large_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegL val,
11408 Universe dummy, rFlagsReg cr)
11409 %{
11410 predicate(((ClearArrayNode*)n)->is_large() && !((ClearArrayNode*)n)->word_copy_only() && (UseAVX > 2));
11411 match(Set dummy (ClearArray (Binary cnt base) val));
11412 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, USE_KILL val, KILL cr);
11413
11414 format %{ $$template
11415 if (UseFastStosb) {
11416 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11417 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11418 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11419 } else if (UseXMMForObjInit) {
11420 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
11421 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11422 $$emit$$"jmpq L_zero_64_bytes\n\t"
11423 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11424 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11425 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11426 $$emit$$"add 0x40,rax\n\t"
11427 $$emit$$"# L_zero_64_bytes:\n\t"
11428 $$emit$$"sub 0x8,rcx\n\t"
11429 $$emit$$"jge L_loop\n\t"
11430 $$emit$$"add 0x4,rcx\n\t"
11431 $$emit$$"jl L_tail\n\t"
11432 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11433 $$emit$$"add 0x20,rax\n\t"
11434 $$emit$$"sub 0x4,rcx\n\t"
11435 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11436 $$emit$$"add 0x4,rcx\n\t"
11437 $$emit$$"jle L_end\n\t"
11438 $$emit$$"dec rcx\n\t"
11439 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11440 $$emit$$"vmovq xmm0,(rax)\n\t"
11441 $$emit$$"add 0x8,rax\n\t"
11442 $$emit$$"dec rcx\n\t"
11443 $$emit$$"jge L_sloop\n\t"
11444 $$emit$$"# L_end:\n\t"
11445 } else {
11446 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11447 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11448 }
11449 %}
11450 ins_encode %{
11451 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
11452 $tmp$$XMMRegister, true, false, $ktmp$$KRegister);
11453 %}
11454 ins_pipe(pipe_slow);
11455 %}
11456
11457 instruct rep_stos_large_evex_word_copy(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegL val,
11458 Universe dummy, rFlagsReg cr)
11459 %{
11460 predicate(((ClearArrayNode*)n)->is_large() && ((ClearArrayNode*)n)->word_copy_only() && (UseAVX > 2));
11461 match(Set dummy (ClearArray (Binary cnt base) val));
11462 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, USE_KILL val, KILL cr);
11463
11464 format %{ $$template
11465 if (UseFastStosb) {
11466 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11467 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
11468 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
11469 } else if (UseXMMForObjInit) {
11470 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
11471 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
11472 $$emit$$"jmpq L_zero_64_bytes\n\t"
11473 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11474 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11475 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11476 $$emit$$"add 0x40,rax\n\t"
11477 $$emit$$"# L_zero_64_bytes:\n\t"
11478 $$emit$$"sub 0x8,rcx\n\t"
11479 $$emit$$"jge L_loop\n\t"
11480 $$emit$$"add 0x4,rcx\n\t"
11481 $$emit$$"jl L_tail\n\t"
11482 $$emit$$"vmovdqu ymm0,(rax)\n\t"
11483 $$emit$$"add 0x20,rax\n\t"
11484 $$emit$$"sub 0x4,rcx\n\t"
11485 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11486 $$emit$$"add 0x4,rcx\n\t"
11487 $$emit$$"jle L_end\n\t"
11488 $$emit$$"dec rcx\n\t"
11489 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11490 $$emit$$"vmovq xmm0,(rax)\n\t"
11491 $$emit$$"add 0x8,rax\n\t"
11492 $$emit$$"dec rcx\n\t"
11493 $$emit$$"jge L_sloop\n\t"
11494 $$emit$$"# L_end:\n\t"
11495 } else {
11496 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
11497 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
11498 }
11499 %}
11500 ins_encode %{
11501 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
11502 $tmp$$XMMRegister, true, true, $ktmp$$KRegister);
11503 %}
11504 ins_pipe(pipe_slow);
11505 %}
11506
11507 // Small ClearArray AVX512 constant length.
11508 instruct rep_stos_im(immL cnt, rRegP base, regD tmp, rax_RegL val, kReg ktmp, Universe dummy, rFlagsReg cr)
11509 %{
11510 predicate(!((ClearArrayNode*)n)->is_large() && !((ClearArrayNode*)n)->word_copy_only() &&
11511 ((UseAVX > 2) && VM_Version::supports_avx512vlbw()));
11512 match(Set dummy (ClearArray (Binary cnt base) val));
11513 ins_cost(100);
11514 effect(TEMP tmp, USE_KILL val, TEMP ktmp, KILL cr);
11515 format %{ "clear_mem_imm $base , $cnt \n\t" %}
11516 ins_encode %{
11517 __ clear_mem($base$$Register, $cnt$$constant, $val$$Register, $tmp$$XMMRegister, $ktmp$$KRegister);
11518 %}
11519 ins_pipe(pipe_slow);
11520 %}
11521
11522 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11523 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11524 %{
11525 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11526 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11527 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11528
11529 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11530 ins_encode %{
11531 __ string_compare($str1$$Register, $str2$$Register,
11532 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11533 $tmp1$$XMMRegister, StrIntrinsicNode::LL, knoreg);
11534 %}
11535 ins_pipe( pipe_slow );
11536 %}
11537
11538 instruct string_compareL_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11539 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11540 %{
11541 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11542 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11543 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11544
11545 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11546 ins_encode %{
11547 __ string_compare($str1$$Register, $str2$$Register,
11548 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11549 $tmp1$$XMMRegister, StrIntrinsicNode::LL, $ktmp$$KRegister);
11550 %}
11551 ins_pipe( pipe_slow );
11552 %}
11553
11554 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11555 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11556 %{
11557 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11558 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11559 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11560
11561 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11562 ins_encode %{
11563 __ string_compare($str1$$Register, $str2$$Register,
11564 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11565 $tmp1$$XMMRegister, StrIntrinsicNode::UU, knoreg);
11566 %}
11567 ins_pipe( pipe_slow );
11568 %}
11569
11570 instruct string_compareU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11571 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11572 %{
11573 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11574 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11575 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11576
11577 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11578 ins_encode %{
11579 __ string_compare($str1$$Register, $str2$$Register,
11580 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11581 $tmp1$$XMMRegister, StrIntrinsicNode::UU, $ktmp$$KRegister);
11582 %}
11583 ins_pipe( pipe_slow );
11584 %}
11585
11586 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11587 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11588 %{
11589 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11590 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11591 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11592
11593 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11594 ins_encode %{
11595 __ string_compare($str1$$Register, $str2$$Register,
11596 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11597 $tmp1$$XMMRegister, StrIntrinsicNode::LU, knoreg);
11598 %}
11599 ins_pipe( pipe_slow );
11600 %}
11601
11602 instruct string_compareLU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11603 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11604 %{
11605 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11606 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11607 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11608
11609 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11610 ins_encode %{
11611 __ string_compare($str1$$Register, $str2$$Register,
11612 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11613 $tmp1$$XMMRegister, StrIntrinsicNode::LU, $ktmp$$KRegister);
11614 %}
11615 ins_pipe( pipe_slow );
11616 %}
11617
11618 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11619 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11620 %{
11621 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11622 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11623 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11624
11625 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11626 ins_encode %{
11627 __ string_compare($str2$$Register, $str1$$Register,
11628 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11629 $tmp1$$XMMRegister, StrIntrinsicNode::UL, knoreg);
11630 %}
11631 ins_pipe( pipe_slow );
11632 %}
11633
11634 instruct string_compareUL_evex(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11635 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11636 %{
11637 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11638 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11639 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11640
11641 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11642 ins_encode %{
11643 __ string_compare($str2$$Register, $str1$$Register,
11644 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11645 $tmp1$$XMMRegister, StrIntrinsicNode::UL, $ktmp$$KRegister);
11646 %}
11647 ins_pipe( pipe_slow );
11648 %}
11649
11650 // fast search of substring with known size.
11651 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11652 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11653 %{
11654 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11655 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11656 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11657
11658 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11659 ins_encode %{
11660 int icnt2 = (int)$int_cnt2$$constant;
11661 if (icnt2 >= 16) {
11662 // IndexOf for constant substrings with size >= 16 elements
11663 // which don't need to be loaded through stack.
11664 __ string_indexofC8($str1$$Register, $str2$$Register,
11665 $cnt1$$Register, $cnt2$$Register,
11666 icnt2, $result$$Register,
11667 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11668 } else {
11669 // Small strings are loaded through stack if they cross page boundary.
11670 __ string_indexof($str1$$Register, $str2$$Register,
11671 $cnt1$$Register, $cnt2$$Register,
11672 icnt2, $result$$Register,
11673 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11674 }
11675 %}
11676 ins_pipe( pipe_slow );
11677 %}
11678
11679 // fast search of substring with known size.
11680 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11681 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11682 %{
11683 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11684 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11685 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11686
11687 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11688 ins_encode %{
11689 int icnt2 = (int)$int_cnt2$$constant;
11690 if (icnt2 >= 8) {
11691 // IndexOf for constant substrings with size >= 8 elements
11692 // which don't need to be loaded through stack.
11693 __ string_indexofC8($str1$$Register, $str2$$Register,
11694 $cnt1$$Register, $cnt2$$Register,
11695 icnt2, $result$$Register,
11696 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11697 } else {
11698 // Small strings are loaded through stack if they cross page boundary.
11699 __ string_indexof($str1$$Register, $str2$$Register,
11700 $cnt1$$Register, $cnt2$$Register,
11701 icnt2, $result$$Register,
11702 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11703 }
11704 %}
11705 ins_pipe( pipe_slow );
11706 %}
11707
11708 // fast search of substring with known size.
11709 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11710 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11711 %{
11712 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11713 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11714 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11715
11716 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11717 ins_encode %{
11718 int icnt2 = (int)$int_cnt2$$constant;
11719 if (icnt2 >= 8) {
11720 // IndexOf for constant substrings with size >= 8 elements
11721 // which don't need to be loaded through stack.
11722 __ string_indexofC8($str1$$Register, $str2$$Register,
11723 $cnt1$$Register, $cnt2$$Register,
11724 icnt2, $result$$Register,
11725 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11726 } else {
11727 // Small strings are loaded through stack if they cross page boundary.
11728 __ string_indexof($str1$$Register, $str2$$Register,
11729 $cnt1$$Register, $cnt2$$Register,
11730 icnt2, $result$$Register,
11731 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11732 }
11733 %}
11734 ins_pipe( pipe_slow );
11735 %}
11736
11737 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11738 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11739 %{
11740 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11741 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11742 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11743
11744 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11745 ins_encode %{
11746 __ string_indexof($str1$$Register, $str2$$Register,
11747 $cnt1$$Register, $cnt2$$Register,
11748 (-1), $result$$Register,
11749 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11750 %}
11751 ins_pipe( pipe_slow );
11752 %}
11753
11754 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11755 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11756 %{
11757 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11758 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11759 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11760
11761 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11762 ins_encode %{
11763 __ string_indexof($str1$$Register, $str2$$Register,
11764 $cnt1$$Register, $cnt2$$Register,
11765 (-1), $result$$Register,
11766 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11767 %}
11768 ins_pipe( pipe_slow );
11769 %}
11770
11771 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11772 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11773 %{
11774 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11775 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11776 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11777
11778 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11779 ins_encode %{
11780 __ string_indexof($str1$$Register, $str2$$Register,
11781 $cnt1$$Register, $cnt2$$Register,
11782 (-1), $result$$Register,
11783 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11784 %}
11785 ins_pipe( pipe_slow );
11786 %}
11787
11788 instruct string_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11789 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
11790 %{
11791 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
11792 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11793 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11794 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11795 ins_encode %{
11796 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11797 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
11798 %}
11799 ins_pipe( pipe_slow );
11800 %}
11801
11802 instruct stringL_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11803 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
11804 %{
11805 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
11806 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11807 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11808 format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11809 ins_encode %{
11810 __ stringL_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11811 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
11812 %}
11813 ins_pipe( pipe_slow );
11814 %}
11815
11816 // fast string equals
11817 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11818 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
11819 %{
11820 predicate(!VM_Version::supports_avx512vlbw());
11821 match(Set result (StrEquals (Binary str1 str2) cnt));
11822 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11823
11824 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11825 ins_encode %{
11826 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11827 $cnt$$Register, $result$$Register, $tmp3$$Register,
11828 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
11829 %}
11830 ins_pipe( pipe_slow );
11831 %}
11832
11833 instruct string_equals_evex(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11834 legRegD tmp1, legRegD tmp2, kReg ktmp, rbx_RegI tmp3, rFlagsReg cr)
11835 %{
11836 predicate(VM_Version::supports_avx512vlbw());
11837 match(Set result (StrEquals (Binary str1 str2) cnt));
11838 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11839
11840 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11841 ins_encode %{
11842 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11843 $cnt$$Register, $result$$Register, $tmp3$$Register,
11844 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
11845 %}
11846 ins_pipe( pipe_slow );
11847 %}
11848
11849 // fast array equals
11850 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11851 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11852 %{
11853 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11854 match(Set result (AryEq ary1 ary2));
11855 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11856
11857 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11858 ins_encode %{
11859 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11860 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11861 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
11862 %}
11863 ins_pipe( pipe_slow );
11864 %}
11865
11866 instruct array_equalsB_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11867 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11868 %{
11869 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11870 match(Set result (AryEq ary1 ary2));
11871 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11872
11873 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11874 ins_encode %{
11875 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11876 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11877 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
11878 %}
11879 ins_pipe( pipe_slow );
11880 %}
11881
11882 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11883 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11884 %{
11885 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11886 match(Set result (AryEq ary1 ary2));
11887 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11888
11889 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11890 ins_encode %{
11891 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11892 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11893 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, knoreg);
11894 %}
11895 ins_pipe( pipe_slow );
11896 %}
11897
11898 instruct array_equalsC_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11899 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11900 %{
11901 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11902 match(Set result (AryEq ary1 ary2));
11903 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11904
11905 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11906 ins_encode %{
11907 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11908 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11909 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, $ktmp$$KRegister);
11910 %}
11911 ins_pipe( pipe_slow );
11912 %}
11913
11914 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11915 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr,)
11916 %{
11917 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11918 match(Set result (HasNegatives ary1 len));
11919 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11920
11921 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11922 ins_encode %{
11923 __ has_negatives($ary1$$Register, $len$$Register,
11924 $result$$Register, $tmp3$$Register,
11925 $tmp1$$XMMRegister, $tmp2$$XMMRegister, knoreg, knoreg);
11926 %}
11927 ins_pipe( pipe_slow );
11928 %}
11929
11930 instruct has_negatives_evex(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11931 legRegD tmp1, legRegD tmp2, kReg ktmp1, kReg ktmp2, rbx_RegI tmp3, rFlagsReg cr,)
11932 %{
11933 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11934 match(Set result (HasNegatives ary1 len));
11935 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp1, TEMP ktmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11936
11937 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11938 ins_encode %{
11939 __ has_negatives($ary1$$Register, $len$$Register,
11940 $result$$Register, $tmp3$$Register,
11941 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $ktmp1$$KRegister, $ktmp2$$KRegister);
11942 %}
11943 ins_pipe( pipe_slow );
11944 %}
11945
11946 // fast char[] to byte[] compression
11947 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
11948 legRegD tmp4, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11949 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11950 match(Set result (StrCompressedCopy src (Binary dst len)));
11951 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst,
11952 USE_KILL len, KILL tmp5, KILL cr);
11953
11954 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11955 ins_encode %{
11956 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11957 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11958 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
11959 knoreg, knoreg);
11960 %}
11961 ins_pipe( pipe_slow );
11962 %}
11963
11964 instruct string_compress_evex(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
11965 legRegD tmp4, kReg ktmp1, kReg ktmp2, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11966 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11967 match(Set result (StrCompressedCopy src (Binary dst len)));
11968 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ktmp1, TEMP ktmp2, USE_KILL src, USE_KILL dst,
11969 USE_KILL len, KILL tmp5, KILL cr);
11970
11971 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11972 ins_encode %{
11973 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11974 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11975 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
11976 $ktmp1$$KRegister, $ktmp2$$KRegister);
11977 %}
11978 ins_pipe( pipe_slow );
11979 %}
11980 // fast byte[] to char[] inflation
11981 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11982 legRegD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11983 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11984 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11985 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11986
11987 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11988 ins_encode %{
11989 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11990 $tmp1$$XMMRegister, $tmp2$$Register, knoreg);
11991 %}
11992 ins_pipe( pipe_slow );
11993 %}
11994
11995 instruct string_inflate_evex(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11996 legRegD tmp1, kReg ktmp, rcx_RegI tmp2, rFlagsReg cr) %{
11997 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11998 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11999 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
12000
12001 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
12002 ins_encode %{
12003 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
12004 $tmp1$$XMMRegister, $tmp2$$Register, $ktmp$$KRegister);
12005 %}
12006 ins_pipe( pipe_slow );
12007 %}
12008
12009 // encode char[] to byte[] in ISO_8859_1
12010 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12011 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
12012 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12013 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
12014 match(Set result (EncodeISOArray src (Binary dst len)));
12015 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
12016
12017 format %{ "Encode iso array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
12018 ins_encode %{
12019 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
12020 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12021 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, false);
12022 %}
12023 ins_pipe( pipe_slow );
12024 %}
12025
12026 // encode char[] to byte[] in ASCII
12027 instruct encode_ascii_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12028 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
12029 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12030 predicate(((EncodeISOArrayNode*)n)->is_ascii());
12031 match(Set result (EncodeISOArray src (Binary dst len)));
12032 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
12033
12034 format %{ "Encode ascii array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
12035 ins_encode %{
12036 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
12037 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12038 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, true);
12039 %}
12040 ins_pipe( pipe_slow );
12041 %}
12042
12043 //----------Overflow Math Instructions-----------------------------------------
12044
12045 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
12046 %{
12047 match(Set cr (OverflowAddI op1 op2));
12048 effect(DEF cr, USE_KILL op1, USE op2);
12049
12050 format %{ "addl $op1, $op2\t# overflow check int" %}
12051
12052 ins_encode %{
12053 __ addl($op1$$Register, $op2$$Register);
12054 %}
12055 ins_pipe(ialu_reg_reg);
12056 %}
12057
12058 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
12059 %{
12060 match(Set cr (OverflowAddI op1 op2));
12061 effect(DEF cr, USE_KILL op1, USE op2);
12062
12063 format %{ "addl $op1, $op2\t# overflow check int" %}
12064
12065 ins_encode %{
12066 __ addl($op1$$Register, $op2$$constant);
12067 %}
12068 ins_pipe(ialu_reg_reg);
12069 %}
12070
12071 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
12072 %{
12073 match(Set cr (OverflowAddL op1 op2));
12074 effect(DEF cr, USE_KILL op1, USE op2);
12075
12076 format %{ "addq $op1, $op2\t# overflow check long" %}
12077 ins_encode %{
12078 __ addq($op1$$Register, $op2$$Register);
12079 %}
12080 ins_pipe(ialu_reg_reg);
12081 %}
12082
12083 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
12084 %{
12085 match(Set cr (OverflowAddL op1 op2));
12086 effect(DEF cr, USE_KILL op1, USE op2);
12087
12088 format %{ "addq $op1, $op2\t# overflow check long" %}
12089 ins_encode %{
12090 __ addq($op1$$Register, $op2$$constant);
12091 %}
12092 ins_pipe(ialu_reg_reg);
12093 %}
12094
12095 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
12096 %{
12097 match(Set cr (OverflowSubI op1 op2));
12098
12099 format %{ "cmpl $op1, $op2\t# overflow check int" %}
12100 ins_encode %{
12101 __ cmpl($op1$$Register, $op2$$Register);
12102 %}
12103 ins_pipe(ialu_reg_reg);
12104 %}
12105
12106 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
12107 %{
12108 match(Set cr (OverflowSubI op1 op2));
12109
12110 format %{ "cmpl $op1, $op2\t# overflow check int" %}
12111 ins_encode %{
12112 __ cmpl($op1$$Register, $op2$$constant);
12113 %}
12114 ins_pipe(ialu_reg_reg);
12115 %}
12116
12117 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
12118 %{
12119 match(Set cr (OverflowSubL op1 op2));
12120
12121 format %{ "cmpq $op1, $op2\t# overflow check long" %}
12122 ins_encode %{
12123 __ cmpq($op1$$Register, $op2$$Register);
12124 %}
12125 ins_pipe(ialu_reg_reg);
12126 %}
12127
12128 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
12129 %{
12130 match(Set cr (OverflowSubL op1 op2));
12131
12132 format %{ "cmpq $op1, $op2\t# overflow check long" %}
12133 ins_encode %{
12134 __ cmpq($op1$$Register, $op2$$constant);
12135 %}
12136 ins_pipe(ialu_reg_reg);
12137 %}
12138
12139 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
12140 %{
12141 match(Set cr (OverflowSubI zero op2));
12142 effect(DEF cr, USE_KILL op2);
12143
12144 format %{ "negl $op2\t# overflow check int" %}
12145 ins_encode %{
12146 __ negl($op2$$Register);
12147 %}
12148 ins_pipe(ialu_reg_reg);
12149 %}
12150
12151 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
12152 %{
12153 match(Set cr (OverflowSubL zero op2));
12154 effect(DEF cr, USE_KILL op2);
12155
12156 format %{ "negq $op2\t# overflow check long" %}
12157 ins_encode %{
12158 __ negq($op2$$Register);
12159 %}
12160 ins_pipe(ialu_reg_reg);
12161 %}
12162
12163 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
12164 %{
12165 match(Set cr (OverflowMulI op1 op2));
12166 effect(DEF cr, USE_KILL op1, USE op2);
12167
12168 format %{ "imull $op1, $op2\t# overflow check int" %}
12169 ins_encode %{
12170 __ imull($op1$$Register, $op2$$Register);
12171 %}
12172 ins_pipe(ialu_reg_reg_alu0);
12173 %}
12174
12175 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
12176 %{
12177 match(Set cr (OverflowMulI op1 op2));
12178 effect(DEF cr, TEMP tmp, USE op1, USE op2);
12179
12180 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
12181 ins_encode %{
12182 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
12183 %}
12184 ins_pipe(ialu_reg_reg_alu0);
12185 %}
12186
12187 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
12188 %{
12189 match(Set cr (OverflowMulL op1 op2));
12190 effect(DEF cr, USE_KILL op1, USE op2);
12191
12192 format %{ "imulq $op1, $op2\t# overflow check long" %}
12193 ins_encode %{
12194 __ imulq($op1$$Register, $op2$$Register);
12195 %}
12196 ins_pipe(ialu_reg_reg_alu0);
12197 %}
12198
12199 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
12200 %{
12201 match(Set cr (OverflowMulL op1 op2));
12202 effect(DEF cr, TEMP tmp, USE op1, USE op2);
12203
12204 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
12205 ins_encode %{
12206 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
12207 %}
12208 ins_pipe(ialu_reg_reg_alu0);
12209 %}
12210
12211
12212 //----------Control Flow Instructions------------------------------------------
12213 // Signed compare Instructions
12214
12215 // XXX more variants!!
12216 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
12217 %{
12218 match(Set cr (CmpI op1 op2));
12219 effect(DEF cr, USE op1, USE op2);
12220
12221 format %{ "cmpl $op1, $op2" %}
12222 ins_encode %{
12223 __ cmpl($op1$$Register, $op2$$Register);
12224 %}
12225 ins_pipe(ialu_cr_reg_reg);
12226 %}
12227
12228 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
12229 %{
12230 match(Set cr (CmpI op1 op2));
12231
12232 format %{ "cmpl $op1, $op2" %}
12233 ins_encode %{
12234 __ cmpl($op1$$Register, $op2$$constant);
12235 %}
12236 ins_pipe(ialu_cr_reg_imm);
12237 %}
12238
12239 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
12240 %{
12241 match(Set cr (CmpI op1 (LoadI op2)));
12242
12243 ins_cost(500); // XXX
12244 format %{ "cmpl $op1, $op2" %}
12245 ins_encode %{
12246 __ cmpl($op1$$Register, $op2$$Address);
12247 %}
12248 ins_pipe(ialu_cr_reg_mem);
12249 %}
12250
12251 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
12252 %{
12253 match(Set cr (CmpI src zero));
12254
12255 format %{ "testl $src, $src" %}
12256 ins_encode %{
12257 __ testl($src$$Register, $src$$Register);
12258 %}
12259 ins_pipe(ialu_cr_reg_imm);
12260 %}
12261
12262 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
12263 %{
12264 match(Set cr (CmpI (AndI src con) zero));
12265
12266 format %{ "testl $src, $con" %}
12267 ins_encode %{
12268 __ testl($src$$Register, $con$$constant);
12269 %}
12270 ins_pipe(ialu_cr_reg_imm);
12271 %}
12272
12273 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
12274 %{
12275 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
12276
12277 format %{ "testl $src, $mem" %}
12278 ins_encode %{
12279 __ testl($src$$Register, $mem$$Address);
12280 %}
12281 ins_pipe(ialu_cr_reg_mem);
12282 %}
12283
12284 // Unsigned compare Instructions; really, same as signed except they
12285 // produce an rFlagsRegU instead of rFlagsReg.
12286 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
12287 %{
12288 match(Set cr (CmpU op1 op2));
12289
12290 format %{ "cmpl $op1, $op2\t# unsigned" %}
12291 ins_encode %{
12292 __ cmpl($op1$$Register, $op2$$Register);
12293 %}
12294 ins_pipe(ialu_cr_reg_reg);
12295 %}
12296
12297 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
12298 %{
12299 match(Set cr (CmpU op1 op2));
12300
12301 format %{ "cmpl $op1, $op2\t# unsigned" %}
12302 ins_encode %{
12303 __ cmpl($op1$$Register, $op2$$constant);
12304 %}
12305 ins_pipe(ialu_cr_reg_imm);
12306 %}
12307
12308 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
12309 %{
12310 match(Set cr (CmpU op1 (LoadI op2)));
12311
12312 ins_cost(500); // XXX
12313 format %{ "cmpl $op1, $op2\t# unsigned" %}
12314 ins_encode %{
12315 __ cmpl($op1$$Register, $op2$$Address);
12316 %}
12317 ins_pipe(ialu_cr_reg_mem);
12318 %}
12319
12320 // // // Cisc-spilled version of cmpU_rReg
12321 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
12322 // //%{
12323 // // match(Set cr (CmpU (LoadI op1) op2));
12324 // //
12325 // // format %{ "CMPu $op1,$op2" %}
12326 // // ins_cost(500);
12327 // // opcode(0x39); /* Opcode 39 /r */
12328 // // ins_encode( OpcP, reg_mem( op1, op2) );
12329 // //%}
12330
12331 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
12332 %{
12333 match(Set cr (CmpU src zero));
12334
12335 format %{ "testl $src, $src\t# unsigned" %}
12336 ins_encode %{
12337 __ testl($src$$Register, $src$$Register);
12338 %}
12339 ins_pipe(ialu_cr_reg_imm);
12340 %}
12341
12342 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
12343 %{
12344 match(Set cr (CmpP op1 op2));
12345
12346 format %{ "cmpq $op1, $op2\t# ptr" %}
12347 ins_encode %{
12348 __ cmpq($op1$$Register, $op2$$Register);
12349 %}
12350 ins_pipe(ialu_cr_reg_reg);
12351 %}
12352
12353 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
12354 %{
12355 match(Set cr (CmpP op1 (LoadP op2)));
12356 predicate(n->in(2)->as_Load()->barrier_data() == 0);
12357
12358 ins_cost(500); // XXX
12359 format %{ "cmpq $op1, $op2\t# ptr" %}
12360 ins_encode %{
12361 __ cmpq($op1$$Register, $op2$$Address);
12362 %}
12363 ins_pipe(ialu_cr_reg_mem);
12364 %}
12365
12366 // // // Cisc-spilled version of cmpP_rReg
12367 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
12368 // //%{
12369 // // match(Set cr (CmpP (LoadP op1) op2));
12370 // //
12371 // // format %{ "CMPu $op1,$op2" %}
12372 // // ins_cost(500);
12373 // // opcode(0x39); /* Opcode 39 /r */
12374 // // ins_encode( OpcP, reg_mem( op1, op2) );
12375 // //%}
12376
12377 // XXX this is generalized by compP_rReg_mem???
12378 // Compare raw pointer (used in out-of-heap check).
12379 // Only works because non-oop pointers must be raw pointers
12380 // and raw pointers have no anti-dependencies.
12381 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
12382 %{
12383 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
12384 n->in(2)->as_Load()->barrier_data() == 0);
12385 match(Set cr (CmpP op1 (LoadP op2)));
12386
12387 format %{ "cmpq $op1, $op2\t# raw ptr" %}
12388 ins_encode %{
12389 __ cmpq($op1$$Register, $op2$$Address);
12390 %}
12391 ins_pipe(ialu_cr_reg_mem);
12392 %}
12393
12394 // This will generate a signed flags result. This should be OK since
12395 // any compare to a zero should be eq/neq.
12396 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
12397 %{
12398 match(Set cr (CmpP src zero));
12399
12400 format %{ "testq $src, $src\t# ptr" %}
12401 ins_encode %{
12402 __ testq($src$$Register, $src$$Register);
12403 %}
12404 ins_pipe(ialu_cr_reg_imm);
12405 %}
12406
12407 // This will generate a signed flags result. This should be OK since
12408 // any compare to a zero should be eq/neq.
12409 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
12410 %{
12411 predicate((!UseCompressedOops || (CompressedOops::base() != NULL)) &&
12412 n->in(1)->as_Load()->barrier_data() == 0);
12413 match(Set cr (CmpP (LoadP op) zero));
12414
12415 ins_cost(500); // XXX
12416 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
12417 ins_encode %{
12418 __ testq($op$$Address, 0xFFFFFFFF);
12419 %}
12420 ins_pipe(ialu_cr_reg_imm);
12421 %}
12422
12423 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
12424 %{
12425 predicate(UseCompressedOops && (CompressedOops::base() == NULL) &&
12426 n->in(1)->as_Load()->barrier_data() == 0);
12427 match(Set cr (CmpP (LoadP mem) zero));
12428
12429 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
12430 ins_encode %{
12431 __ cmpq(r12, $mem$$Address);
12432 %}
12433 ins_pipe(ialu_cr_reg_mem);
12434 %}
12435
12436 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
12437 %{
12438 match(Set cr (CmpN op1 op2));
12439
12440 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
12441 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
12442 ins_pipe(ialu_cr_reg_reg);
12443 %}
12444
12445 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
12446 %{
12447 match(Set cr (CmpN src (LoadN mem)));
12448
12449 format %{ "cmpl $src, $mem\t# compressed ptr" %}
12450 ins_encode %{
12451 __ cmpl($src$$Register, $mem$$Address);
12452 %}
12453 ins_pipe(ialu_cr_reg_mem);
12454 %}
12455
12456 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
12457 match(Set cr (CmpN op1 op2));
12458
12459 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
12460 ins_encode %{
12461 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
12462 %}
12463 ins_pipe(ialu_cr_reg_imm);
12464 %}
12465
12466 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
12467 %{
12468 match(Set cr (CmpN src (LoadN mem)));
12469
12470 format %{ "cmpl $mem, $src\t# compressed ptr" %}
12471 ins_encode %{
12472 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
12473 %}
12474 ins_pipe(ialu_cr_reg_mem);
12475 %}
12476
12477 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
12478 match(Set cr (CmpN op1 op2));
12479
12480 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
12481 ins_encode %{
12482 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
12483 %}
12484 ins_pipe(ialu_cr_reg_imm);
12485 %}
12486
12487 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
12488 %{
12489 match(Set cr (CmpN src (LoadNKlass mem)));
12490
12491 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
12492 ins_encode %{
12493 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
12494 %}
12495 ins_pipe(ialu_cr_reg_mem);
12496 %}
12497
12498 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
12499 match(Set cr (CmpN src zero));
12500
12501 format %{ "testl $src, $src\t# compressed ptr" %}
12502 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
12503 ins_pipe(ialu_cr_reg_imm);
12504 %}
12505
12506 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
12507 %{
12508 predicate(CompressedOops::base() != NULL);
12509 match(Set cr (CmpN (LoadN mem) zero));
12510
12511 ins_cost(500); // XXX
12512 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
12513 ins_encode %{
12514 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
12515 %}
12516 ins_pipe(ialu_cr_reg_mem);
12517 %}
12518
12519 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
12520 %{
12521 predicate(CompressedOops::base() == NULL);
12522 match(Set cr (CmpN (LoadN mem) zero));
12523
12524 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
12525 ins_encode %{
12526 __ cmpl(r12, $mem$$Address);
12527 %}
12528 ins_pipe(ialu_cr_reg_mem);
12529 %}
12530
12531 // Yanked all unsigned pointer compare operations.
12532 // Pointer compares are done with CmpP which is already unsigned.
12533
12534 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
12535 %{
12536 match(Set cr (CmpL op1 op2));
12537
12538 format %{ "cmpq $op1, $op2" %}
12539 ins_encode %{
12540 __ cmpq($op1$$Register, $op2$$Register);
12541 %}
12542 ins_pipe(ialu_cr_reg_reg);
12543 %}
12544
12545 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
12546 %{
12547 match(Set cr (CmpL op1 op2));
12548
12549 format %{ "cmpq $op1, $op2" %}
12550 ins_encode %{
12551 __ cmpq($op1$$Register, $op2$$constant);
12552 %}
12553 ins_pipe(ialu_cr_reg_imm);
12554 %}
12555
12556 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
12557 %{
12558 match(Set cr (CmpL op1 (LoadL op2)));
12559
12560 format %{ "cmpq $op1, $op2" %}
12561 ins_encode %{
12562 __ cmpq($op1$$Register, $op2$$Address);
12563 %}
12564 ins_pipe(ialu_cr_reg_mem);
12565 %}
12566
12567 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
12568 %{
12569 match(Set cr (CmpL src zero));
12570
12571 format %{ "testq $src, $src" %}
12572 ins_encode %{
12573 __ testq($src$$Register, $src$$Register);
12574 %}
12575 ins_pipe(ialu_cr_reg_imm);
12576 %}
12577
12578 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
12579 %{
12580 match(Set cr (CmpL (AndL src con) zero));
12581
12582 format %{ "testq $src, $con\t# long" %}
12583 ins_encode %{
12584 __ testq($src$$Register, $con$$constant);
12585 %}
12586 ins_pipe(ialu_cr_reg_imm);
12587 %}
12588
12589 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
12590 %{
12591 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
12592
12593 format %{ "testq $src, $mem" %}
12594 ins_encode %{
12595 __ testq($src$$Register, $mem$$Address);
12596 %}
12597 ins_pipe(ialu_cr_reg_mem);
12598 %}
12599
12600 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12601 %{
12602 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12603
12604 format %{ "testq $src, $mem" %}
12605 ins_encode %{
12606 __ testq($src$$Register, $mem$$Address);
12607 %}
12608 ins_pipe(ialu_cr_reg_mem);
12609 %}
12610
12611 // Manifest a CmpL result in an integer register. Very painful.
12612 // This is the test to avoid.
12613 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12614 %{
12615 match(Set dst (CmpL3 src1 src2));
12616 effect(KILL flags);
12617
12618 ins_cost(275); // XXX
12619 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12620 "movl $dst, -1\n\t"
12621 "jl,s done\n\t"
12622 "setne $dst\n\t"
12623 "movzbl $dst, $dst\n\t"
12624 "done:" %}
12625 ins_encode %{
12626 Label done;
12627 __ cmpq($src1$$Register, $src2$$Register);
12628 __ movl($dst$$Register, -1);
12629 __ jccb(Assembler::less, done);
12630 __ setne($dst$$Register);
12631 __ movzbl($dst$$Register, $dst$$Register);
12632 __ bind(done);
12633 %}
12634 ins_pipe(pipe_slow);
12635 %}
12636
12637 // Unsigned long compare Instructions; really, same as signed long except they
12638 // produce an rFlagsRegU instead of rFlagsReg.
12639 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12640 %{
12641 match(Set cr (CmpUL op1 op2));
12642
12643 format %{ "cmpq $op1, $op2\t# unsigned" %}
12644 ins_encode %{
12645 __ cmpq($op1$$Register, $op2$$Register);
12646 %}
12647 ins_pipe(ialu_cr_reg_reg);
12648 %}
12649
12650 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12651 %{
12652 match(Set cr (CmpUL op1 op2));
12653
12654 format %{ "cmpq $op1, $op2\t# unsigned" %}
12655 ins_encode %{
12656 __ cmpq($op1$$Register, $op2$$constant);
12657 %}
12658 ins_pipe(ialu_cr_reg_imm);
12659 %}
12660
12661 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12662 %{
12663 match(Set cr (CmpUL op1 (LoadL op2)));
12664
12665 format %{ "cmpq $op1, $op2\t# unsigned" %}
12666 ins_encode %{
12667 __ cmpq($op1$$Register, $op2$$Address);
12668 %}
12669 ins_pipe(ialu_cr_reg_mem);
12670 %}
12671
12672 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12673 %{
12674 match(Set cr (CmpUL src zero));
12675
12676 format %{ "testq $src, $src\t# unsigned" %}
12677 ins_encode %{
12678 __ testq($src$$Register, $src$$Register);
12679 %}
12680 ins_pipe(ialu_cr_reg_imm);
12681 %}
12682
12683 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12684 %{
12685 match(Set cr (CmpI (LoadB mem) imm));
12686
12687 ins_cost(125);
12688 format %{ "cmpb $mem, $imm" %}
12689 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12690 ins_pipe(ialu_cr_reg_mem);
12691 %}
12692
12693 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU7 imm, immI_0 zero)
12694 %{
12695 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12696
12697 ins_cost(125);
12698 format %{ "testb $mem, $imm\t# ubyte" %}
12699 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12700 ins_pipe(ialu_cr_reg_mem);
12701 %}
12702
12703 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
12704 %{
12705 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12706
12707 ins_cost(125);
12708 format %{ "testb $mem, $imm\t# byte" %}
12709 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12710 ins_pipe(ialu_cr_reg_mem);
12711 %}
12712
12713 //----------Max and Min--------------------------------------------------------
12714 // Min Instructions
12715
12716 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12717 %{
12718 effect(USE_DEF dst, USE src, USE cr);
12719
12720 format %{ "cmovlgt $dst, $src\t# min" %}
12721 ins_encode %{
12722 __ cmovl(Assembler::greater, $dst$$Register, $src$$Register);
12723 %}
12724 ins_pipe(pipe_cmov_reg);
12725 %}
12726
12727
12728 instruct minI_rReg(rRegI dst, rRegI src)
12729 %{
12730 match(Set dst (MinI dst src));
12731
12732 ins_cost(200);
12733 expand %{
12734 rFlagsReg cr;
12735 compI_rReg(cr, dst, src);
12736 cmovI_reg_g(dst, src, cr);
12737 %}
12738 %}
12739
12740 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12741 %{
12742 effect(USE_DEF dst, USE src, USE cr);
12743
12744 format %{ "cmovllt $dst, $src\t# max" %}
12745 ins_encode %{
12746 __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
12747 %}
12748 ins_pipe(pipe_cmov_reg);
12749 %}
12750
12751
12752 instruct maxI_rReg(rRegI dst, rRegI src)
12753 %{
12754 match(Set dst (MaxI dst src));
12755
12756 ins_cost(200);
12757 expand %{
12758 rFlagsReg cr;
12759 compI_rReg(cr, dst, src);
12760 cmovI_reg_l(dst, src, cr);
12761 %}
12762 %}
12763
12764 // ============================================================================
12765 // Branch Instructions
12766
12767 // Jump Direct - Label defines a relative address from JMP+1
12768 instruct jmpDir(label labl)
12769 %{
12770 match(Goto);
12771 effect(USE labl);
12772
12773 ins_cost(300);
12774 format %{ "jmp $labl" %}
12775 size(5);
12776 ins_encode %{
12777 Label* L = $labl$$label;
12778 __ jmp(*L, false); // Always long jump
12779 %}
12780 ins_pipe(pipe_jmp);
12781 %}
12782
12783 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12784 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12785 %{
12786 match(If cop cr);
12787 effect(USE labl);
12788
12789 ins_cost(300);
12790 format %{ "j$cop $labl" %}
12791 size(6);
12792 ins_encode %{
12793 Label* L = $labl$$label;
12794 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12795 %}
12796 ins_pipe(pipe_jcc);
12797 %}
12798
12799 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12800 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12801 %{
12802 predicate(!n->has_vector_mask_set());
12803 match(CountedLoopEnd cop cr);
12804 effect(USE labl);
12805
12806 ins_cost(300);
12807 format %{ "j$cop $labl\t# loop end" %}
12808 size(6);
12809 ins_encode %{
12810 Label* L = $labl$$label;
12811 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12812 %}
12813 ins_pipe(pipe_jcc);
12814 %}
12815
12816 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12817 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12818 predicate(!n->has_vector_mask_set());
12819 match(CountedLoopEnd cop cmp);
12820 effect(USE labl);
12821
12822 ins_cost(300);
12823 format %{ "j$cop,u $labl\t# loop end" %}
12824 size(6);
12825 ins_encode %{
12826 Label* L = $labl$$label;
12827 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12828 %}
12829 ins_pipe(pipe_jcc);
12830 %}
12831
12832 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12833 predicate(!n->has_vector_mask_set());
12834 match(CountedLoopEnd cop cmp);
12835 effect(USE labl);
12836
12837 ins_cost(200);
12838 format %{ "j$cop,u $labl\t# loop end" %}
12839 size(6);
12840 ins_encode %{
12841 Label* L = $labl$$label;
12842 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12843 %}
12844 ins_pipe(pipe_jcc);
12845 %}
12846
12847 // mask version
12848 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12849 // Bounded mask operand used in following patten is needed for
12850 // post-loop multiversioning.
12851 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, kReg_K1 ktmp, rFlagsReg cr, label labl)
12852 %{
12853 predicate(PostLoopMultiversioning && n->has_vector_mask_set());
12854 match(CountedLoopEnd cop cr);
12855 effect(USE labl, TEMP ktmp);
12856
12857 ins_cost(400);
12858 format %{ "j$cop $labl\t# loop end\n\t"
12859 "restorevectmask \t# vector mask restore for loops" %}
12860 size(10);
12861 ins_encode %{
12862 Label* L = $labl$$label;
12863 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12864 __ restorevectmask($ktmp$$KRegister);
12865 %}
12866 ins_pipe(pipe_jcc);
12867 %}
12868
12869 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12870 // Bounded mask operand used in following patten is needed for
12871 // post-loop multiversioning.
12872 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, kReg_K1 ktmp, rFlagsRegU cmp, label labl) %{
12873 predicate(PostLoopMultiversioning && n->has_vector_mask_set());
12874 match(CountedLoopEnd cop cmp);
12875 effect(USE labl, TEMP ktmp);
12876
12877 ins_cost(400);
12878 format %{ "j$cop,u $labl\t# loop end\n\t"
12879 "restorevectmask \t# vector mask restore for loops" %}
12880 size(10);
12881 ins_encode %{
12882 Label* L = $labl$$label;
12883 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12884 __ restorevectmask($ktmp$$KRegister);
12885 %}
12886 ins_pipe(pipe_jcc);
12887 %}
12888
12889 // Bounded mask operand used in following patten is needed for
12890 // post-loop multiversioning.
12891 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, kReg_K1 ktmp, rFlagsRegUCF cmp, label labl) %{
12892 predicate(PostLoopMultiversioning && n->has_vector_mask_set());
12893 match(CountedLoopEnd cop cmp);
12894 effect(USE labl, TEMP ktmp);
12895
12896 ins_cost(300);
12897 format %{ "j$cop,u $labl\t# loop end\n\t"
12898 "restorevectmask \t# vector mask restore for loops" %}
12899 size(10);
12900 ins_encode %{
12901 Label* L = $labl$$label;
12902 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12903 __ restorevectmask($ktmp$$KRegister);
12904 %}
12905 ins_pipe(pipe_jcc);
12906 %}
12907
12908 // Jump Direct Conditional - using unsigned comparison
12909 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12910 match(If cop cmp);
12911 effect(USE labl);
12912
12913 ins_cost(300);
12914 format %{ "j$cop,u $labl" %}
12915 size(6);
12916 ins_encode %{
12917 Label* L = $labl$$label;
12918 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12919 %}
12920 ins_pipe(pipe_jcc);
12921 %}
12922
12923 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12924 match(If cop cmp);
12925 effect(USE labl);
12926
12927 ins_cost(200);
12928 format %{ "j$cop,u $labl" %}
12929 size(6);
12930 ins_encode %{
12931 Label* L = $labl$$label;
12932 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12933 %}
12934 ins_pipe(pipe_jcc);
12935 %}
12936
12937 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12938 match(If cop cmp);
12939 effect(USE labl);
12940
12941 ins_cost(200);
12942 format %{ $$template
12943 if ($cop$$cmpcode == Assembler::notEqual) {
12944 $$emit$$"jp,u $labl\n\t"
12945 $$emit$$"j$cop,u $labl"
12946 } else {
12947 $$emit$$"jp,u done\n\t"
12948 $$emit$$"j$cop,u $labl\n\t"
12949 $$emit$$"done:"
12950 }
12951 %}
12952 ins_encode %{
12953 Label* l = $labl$$label;
12954 if ($cop$$cmpcode == Assembler::notEqual) {
12955 __ jcc(Assembler::parity, *l, false);
12956 __ jcc(Assembler::notEqual, *l, false);
12957 } else if ($cop$$cmpcode == Assembler::equal) {
12958 Label done;
12959 __ jccb(Assembler::parity, done);
12960 __ jcc(Assembler::equal, *l, false);
12961 __ bind(done);
12962 } else {
12963 ShouldNotReachHere();
12964 }
12965 %}
12966 ins_pipe(pipe_jcc);
12967 %}
12968
12969 // ============================================================================
12970 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12971 // superklass array for an instance of the superklass. Set a hidden
12972 // internal cache on a hit (cache is checked with exposed code in
12973 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12974 // encoding ALSO sets flags.
12975
12976 instruct partialSubtypeCheck(rdi_RegP result,
12977 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12978 rFlagsReg cr)
12979 %{
12980 match(Set result (PartialSubtypeCheck sub super));
12981 effect(KILL rcx, KILL cr);
12982
12983 ins_cost(1100); // slightly larger than the next version
12984 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12985 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12986 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12987 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12988 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12989 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12990 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12991 "miss:\t" %}
12992
12993 opcode(0x1); // Force a XOR of RDI
12994 ins_encode(enc_PartialSubtypeCheck());
12995 ins_pipe(pipe_slow);
12996 %}
12997
12998 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12999 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
13000 immP0 zero,
13001 rdi_RegP result)
13002 %{
13003 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
13004 effect(KILL rcx, KILL result);
13005
13006 ins_cost(1000);
13007 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
13008 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
13009 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
13010 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
13011 "jne,s miss\t\t# Missed: flags nz\n\t"
13012 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
13013 "miss:\t" %}
13014
13015 opcode(0x0); // No need to XOR RDI
13016 ins_encode(enc_PartialSubtypeCheck());
13017 ins_pipe(pipe_slow);
13018 %}
13019
13020 // ============================================================================
13021 // Branch Instructions -- short offset versions
13022 //
13023 // These instructions are used to replace jumps of a long offset (the default
13024 // match) with jumps of a shorter offset. These instructions are all tagged
13025 // with the ins_short_branch attribute, which causes the ADLC to suppress the
13026 // match rules in general matching. Instead, the ADLC generates a conversion
13027 // method in the MachNode which can be used to do in-place replacement of the
13028 // long variant with the shorter variant. The compiler will determine if a
13029 // branch can be taken by the is_short_branch_offset() predicate in the machine
13030 // specific code section of the file.
13031
13032 // Jump Direct - Label defines a relative address from JMP+1
13033 instruct jmpDir_short(label labl) %{
13034 match(Goto);
13035 effect(USE labl);
13036
13037 ins_cost(300);
13038 format %{ "jmp,s $labl" %}
13039 size(2);
13040 ins_encode %{
13041 Label* L = $labl$$label;
13042 __ jmpb(*L);
13043 %}
13044 ins_pipe(pipe_jmp);
13045 ins_short_branch(1);
13046 %}
13047
13048 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13049 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
13050 match(If cop cr);
13051 effect(USE labl);
13052
13053 ins_cost(300);
13054 format %{ "j$cop,s $labl" %}
13055 size(2);
13056 ins_encode %{
13057 Label* L = $labl$$label;
13058 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13059 %}
13060 ins_pipe(pipe_jcc);
13061 ins_short_branch(1);
13062 %}
13063
13064 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13065 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
13066 match(CountedLoopEnd cop cr);
13067 effect(USE labl);
13068
13069 ins_cost(300);
13070 format %{ "j$cop,s $labl\t# loop end" %}
13071 size(2);
13072 ins_encode %{
13073 Label* L = $labl$$label;
13074 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13075 %}
13076 ins_pipe(pipe_jcc);
13077 ins_short_branch(1);
13078 %}
13079
13080 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13081 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
13082 match(CountedLoopEnd cop cmp);
13083 effect(USE labl);
13084
13085 ins_cost(300);
13086 format %{ "j$cop,us $labl\t# loop end" %}
13087 size(2);
13088 ins_encode %{
13089 Label* L = $labl$$label;
13090 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13091 %}
13092 ins_pipe(pipe_jcc);
13093 ins_short_branch(1);
13094 %}
13095
13096 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
13097 match(CountedLoopEnd cop cmp);
13098 effect(USE labl);
13099
13100 ins_cost(300);
13101 format %{ "j$cop,us $labl\t# loop end" %}
13102 size(2);
13103 ins_encode %{
13104 Label* L = $labl$$label;
13105 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13106 %}
13107 ins_pipe(pipe_jcc);
13108 ins_short_branch(1);
13109 %}
13110
13111 // Jump Direct Conditional - using unsigned comparison
13112 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
13113 match(If cop cmp);
13114 effect(USE labl);
13115
13116 ins_cost(300);
13117 format %{ "j$cop,us $labl" %}
13118 size(2);
13119 ins_encode %{
13120 Label* L = $labl$$label;
13121 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13122 %}
13123 ins_pipe(pipe_jcc);
13124 ins_short_branch(1);
13125 %}
13126
13127 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
13128 match(If cop cmp);
13129 effect(USE labl);
13130
13131 ins_cost(300);
13132 format %{ "j$cop,us $labl" %}
13133 size(2);
13134 ins_encode %{
13135 Label* L = $labl$$label;
13136 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
13137 %}
13138 ins_pipe(pipe_jcc);
13139 ins_short_branch(1);
13140 %}
13141
13142 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
13143 match(If cop cmp);
13144 effect(USE labl);
13145
13146 ins_cost(300);
13147 format %{ $$template
13148 if ($cop$$cmpcode == Assembler::notEqual) {
13149 $$emit$$"jp,u,s $labl\n\t"
13150 $$emit$$"j$cop,u,s $labl"
13151 } else {
13152 $$emit$$"jp,u,s done\n\t"
13153 $$emit$$"j$cop,u,s $labl\n\t"
13154 $$emit$$"done:"
13155 }
13156 %}
13157 size(4);
13158 ins_encode %{
13159 Label* l = $labl$$label;
13160 if ($cop$$cmpcode == Assembler::notEqual) {
13161 __ jccb(Assembler::parity, *l);
13162 __ jccb(Assembler::notEqual, *l);
13163 } else if ($cop$$cmpcode == Assembler::equal) {
13164 Label done;
13165 __ jccb(Assembler::parity, done);
13166 __ jccb(Assembler::equal, *l);
13167 __ bind(done);
13168 } else {
13169 ShouldNotReachHere();
13170 }
13171 %}
13172 ins_pipe(pipe_jcc);
13173 ins_short_branch(1);
13174 %}
13175
13176 // ============================================================================
13177 // inlined locking and unlocking
13178
13179 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
13180 predicate(Compile::current()->use_rtm());
13181 match(Set cr (FastLock object box));
13182 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
13183 ins_cost(300);
13184 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
13185 ins_encode %{
13186 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
13187 $scr$$Register, $cx1$$Register, $cx2$$Register,
13188 _rtm_counters, _stack_rtm_counters,
13189 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
13190 true, ra_->C->profile_rtm());
13191 %}
13192 ins_pipe(pipe_slow);
13193 %}
13194
13195 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr, rRegP cx1) %{
13196 predicate(!Compile::current()->use_rtm());
13197 match(Set cr (FastLock object box));
13198 effect(TEMP tmp, TEMP scr, TEMP cx1, USE_KILL box);
13199 ins_cost(300);
13200 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
13201 ins_encode %{
13202 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
13203 $scr$$Register, $cx1$$Register, noreg, NULL, NULL, NULL, false, false);
13204 %}
13205 ins_pipe(pipe_slow);
13206 %}
13207
13208 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
13209 match(Set cr (FastUnlock object box));
13210 effect(TEMP tmp, USE_KILL box);
13211 ins_cost(300);
13212 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
13213 ins_encode %{
13214 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
13215 %}
13216 ins_pipe(pipe_slow);
13217 %}
13218
13219
13220 // ============================================================================
13221 // Safepoint Instructions
13222 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
13223 %{
13224 match(SafePoint poll);
13225 effect(KILL cr, USE poll);
13226
13227 format %{ "testl rax, [$poll]\t"
13228 "# Safepoint: poll for GC" %}
13229 ins_cost(125);
13230 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
13231 ins_encode %{
13232 __ relocate(relocInfo::poll_type);
13233 address pre_pc = __ pc();
13234 __ testl(rax, Address($poll$$Register, 0));
13235 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
13236 %}
13237 ins_pipe(ialu_reg_mem);
13238 %}
13239
13240 // ============================================================================
13241 // Procedure Call/Return Instructions
13242 // Call Java Static Instruction
13243 // Note: If this code changes, the corresponding ret_addr_offset() and
13244 // compute_padding() functions will have to be adjusted.
13245 instruct CallStaticJavaDirect(method meth) %{
13246 match(CallStaticJava);
13247 effect(USE meth);
13248
13249 ins_cost(300);
13250 format %{ "call,static " %}
13251 opcode(0xE8); /* E8 cd */
13252 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
13253 ins_pipe(pipe_slow);
13254 ins_alignment(4);
13255 %}
13256
13257 // Call Java Dynamic Instruction
13258 // Note: If this code changes, the corresponding ret_addr_offset() and
13259 // compute_padding() functions will have to be adjusted.
13260 instruct CallDynamicJavaDirect(method meth)
13261 %{
13262 match(CallDynamicJava);
13263 effect(USE meth);
13264
13265 ins_cost(300);
13266 format %{ "movq rax, #Universe::non_oop_word()\n\t"
13267 "call,dynamic " %}
13268 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
13269 ins_pipe(pipe_slow);
13270 ins_alignment(4);
13271 %}
13272
13273 // Call Runtime Instruction
13274 instruct CallRuntimeDirect(method meth)
13275 %{
13276 match(CallRuntime);
13277 effect(USE meth);
13278
13279 ins_cost(300);
13280 format %{ "call,runtime " %}
13281 ins_encode(clear_avx, Java_To_Runtime(meth));
13282 ins_pipe(pipe_slow);
13283 %}
13284
13285 // Call runtime without safepoint
13286 instruct CallLeafDirect(method meth)
13287 %{
13288 match(CallLeaf);
13289 effect(USE meth);
13290
13291 ins_cost(300);
13292 format %{ "call_leaf,runtime " %}
13293 ins_encode(clear_avx, Java_To_Runtime(meth));
13294 ins_pipe(pipe_slow);
13295 %}
13296
13297 // Call runtime without safepoint and with vector arguments
13298 instruct CallLeafDirectVector(method meth)
13299 %{
13300 match(CallLeafVector);
13301 effect(USE meth);
13302
13303 ins_cost(300);
13304 format %{ "call_leaf,vector " %}
13305 ins_encode(Java_To_Runtime(meth));
13306 ins_pipe(pipe_slow);
13307 %}
13308
13309 //
13310 instruct CallNativeDirect(method meth)
13311 %{
13312 match(CallNative);
13313 effect(USE meth);
13314
13315 ins_cost(300);
13316 format %{ "call_native " %}
13317 ins_encode(clear_avx, Java_To_Runtime(meth));
13318 ins_pipe(pipe_slow);
13319 %}
13320
13321 // Call runtime without safepoint
13322 // entry point is null, target holds the address to call
13323 instruct CallLeafNoFPInDirect(rRegP target)
13324 %{
13325 predicate(n->as_Call()->entry_point() == NULL);
13326 match(CallLeafNoFP target);
13327
13328 ins_cost(300);
13329 format %{ "call_leaf_nofp,runtime indirect " %}
13330 ins_encode %{
13331 __ call($target$$Register);
13332 %}
13333
13334 ins_pipe(pipe_slow);
13335 %}
13336
13337 instruct CallLeafNoFPDirect(method meth)
13338 %{
13339 predicate(n->as_Call()->entry_point() != NULL);
13340 match(CallLeafNoFP);
13341 effect(USE meth);
13342
13343 ins_cost(300);
13344 format %{ "call_leaf_nofp,runtime " %}
13345 ins_encode(clear_avx, Java_To_Runtime(meth));
13346 ins_pipe(pipe_slow);
13347 %}
13348
13349 // Return Instruction
13350 // Remove the return address & jump to it.
13351 // Notice: We always emit a nop after a ret to make sure there is room
13352 // for safepoint patching
13353 instruct Ret()
13354 %{
13355 match(Return);
13356
13357 format %{ "ret" %}
13358 ins_encode %{
13359 __ ret(0);
13360 %}
13361 ins_pipe(pipe_jmp);
13362 %}
13363
13364 // Tail Call; Jump from runtime stub to Java code.
13365 // Also known as an 'interprocedural jump'.
13366 // Target of jump will eventually return to caller.
13367 // TailJump below removes the return address.
13368 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_ptr)
13369 %{
13370 match(TailCall jump_target method_ptr);
13371
13372 ins_cost(300);
13373 format %{ "jmp $jump_target\t# rbx holds method" %}
13374 ins_encode %{
13375 __ jmp($jump_target$$Register);
13376 %}
13377 ins_pipe(pipe_jmp);
13378 %}
13379
13380 // Tail Jump; remove the return address; jump to target.
13381 // TailCall above leaves the return address around.
13382 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
13383 %{
13384 match(TailJump jump_target ex_oop);
13385
13386 ins_cost(300);
13387 format %{ "popq rdx\t# pop return address\n\t"
13388 "jmp $jump_target" %}
13389 ins_encode %{
13390 __ popq(as_Register(RDX_enc));
13391 __ jmp($jump_target$$Register);
13392 %}
13393 ins_pipe(pipe_jmp);
13394 %}
13395
13396 // Create exception oop: created by stack-crawling runtime code.
13397 // Created exception is now available to this handler, and is setup
13398 // just prior to jumping to this handler. No code emitted.
13399 instruct CreateException(rax_RegP ex_oop)
13400 %{
13401 match(Set ex_oop (CreateEx));
13402
13403 size(0);
13404 // use the following format syntax
13405 format %{ "# exception oop is in rax; no code emitted" %}
13406 ins_encode();
13407 ins_pipe(empty);
13408 %}
13409
13410 // Rethrow exception:
13411 // The exception oop will come in the first argument position.
13412 // Then JUMP (not call) to the rethrow stub code.
13413 instruct RethrowException()
13414 %{
13415 match(Rethrow);
13416
13417 // use the following format syntax
13418 format %{ "jmp rethrow_stub" %}
13419 ins_encode(enc_rethrow);
13420 ins_pipe(pipe_jmp);
13421 %}
13422
13423 // ============================================================================
13424 // This name is KNOWN by the ADLC and cannot be changed.
13425 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13426 // for this guy.
13427 instruct tlsLoadP(r15_RegP dst) %{
13428 match(Set dst (ThreadLocal));
13429 effect(DEF dst);
13430
13431 size(0);
13432 format %{ "# TLS is in R15" %}
13433 ins_encode( /*empty encoding*/ );
13434 ins_pipe(ialu_reg_reg);
13435 %}
13436
13437
13438 //----------PEEPHOLE RULES-----------------------------------------------------
13439 // These must follow all instruction definitions as they use the names
13440 // defined in the instructions definitions.
13441 //
13442 // peepmatch ( root_instr_name [preceding_instruction]* );
13443 //
13444 // peepconstraint %{
13445 // (instruction_number.operand_name relational_op instruction_number.operand_name
13446 // [, ...] );
13447 // // instruction numbers are zero-based using left to right order in peepmatch
13448 //
13449 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
13450 // // provide an instruction_number.operand_name for each operand that appears
13451 // // in the replacement instruction's match rule
13452 //
13453 // ---------VM FLAGS---------------------------------------------------------
13454 //
13455 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13456 //
13457 // Each peephole rule is given an identifying number starting with zero and
13458 // increasing by one in the order seen by the parser. An individual peephole
13459 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13460 // on the command-line.
13461 //
13462 // ---------CURRENT LIMITATIONS----------------------------------------------
13463 //
13464 // Only match adjacent instructions in same basic block
13465 // Only equality constraints
13466 // Only constraints between operands, not (0.dest_reg == RAX_enc)
13467 // Only one replacement instruction
13468 //
13469 // ---------EXAMPLE----------------------------------------------------------
13470 //
13471 // // pertinent parts of existing instructions in architecture description
13472 // instruct movI(rRegI dst, rRegI src)
13473 // %{
13474 // match(Set dst (CopyI src));
13475 // %}
13476 //
13477 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
13478 // %{
13479 // match(Set dst (AddI dst src));
13480 // effect(KILL cr);
13481 // %}
13482 //
13483 // // Change (inc mov) to lea
13484 // peephole %{
13485 // // increment preceeded by register-register move
13486 // peepmatch ( incI_rReg movI );
13487 // // require that the destination register of the increment
13488 // // match the destination register of the move
13489 // peepconstraint ( 0.dst == 1.dst );
13490 // // construct a replacement instruction that sets
13491 // // the destination to ( move's source register + one )
13492 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
13493 // %}
13494 //
13495
13496 // Implementation no longer uses movX instructions since
13497 // machine-independent system no longer uses CopyX nodes.
13498 //
13499 // peephole
13500 // %{
13501 // peepmatch (incI_rReg movI);
13502 // peepconstraint (0.dst == 1.dst);
13503 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13504 // %}
13505
13506 // peephole
13507 // %{
13508 // peepmatch (decI_rReg movI);
13509 // peepconstraint (0.dst == 1.dst);
13510 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13511 // %}
13512
13513 // peephole
13514 // %{
13515 // peepmatch (addI_rReg_imm movI);
13516 // peepconstraint (0.dst == 1.dst);
13517 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13518 // %}
13519
13520 // peephole
13521 // %{
13522 // peepmatch (incL_rReg movL);
13523 // peepconstraint (0.dst == 1.dst);
13524 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13525 // %}
13526
13527 // peephole
13528 // %{
13529 // peepmatch (decL_rReg movL);
13530 // peepconstraint (0.dst == 1.dst);
13531 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13532 // %}
13533
13534 // peephole
13535 // %{
13536 // peepmatch (addL_rReg_imm movL);
13537 // peepconstraint (0.dst == 1.dst);
13538 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13539 // %}
13540
13541 // peephole
13542 // %{
13543 // peepmatch (addP_rReg_imm movP);
13544 // peepconstraint (0.dst == 1.dst);
13545 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
13546 // %}
13547
13548 // // Change load of spilled value to only a spill
13549 // instruct storeI(memory mem, rRegI src)
13550 // %{
13551 // match(Set mem (StoreI mem src));
13552 // %}
13553 //
13554 // instruct loadI(rRegI dst, memory mem)
13555 // %{
13556 // match(Set dst (LoadI mem));
13557 // %}
13558 //
13559
13560 peephole
13561 %{
13562 peepmatch (loadI storeI);
13563 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13564 peepreplace (storeI(1.mem 1.mem 1.src));
13565 %}
13566
13567 peephole
13568 %{
13569 peepmatch (loadL storeL);
13570 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13571 peepreplace (storeL(1.mem 1.mem 1.src));
13572 %}
13573
13574 //----------SMARTSPILL RULES---------------------------------------------------
13575 // These must follow all instruction definitions as they use the names
13576 // defined in the instructions definitions.