1 //
2 // Copyright (c) 2003, 2024, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // architecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
165 //
166
167 // Empty register class.
168 reg_class no_reg();
169
170 // Class for all pointer/long registers
171 reg_class all_reg(RAX, RAX_H,
172 RDX, RDX_H,
173 RBP, RBP_H,
174 RDI, RDI_H,
175 RSI, RSI_H,
176 RCX, RCX_H,
177 RBX, RBX_H,
178 RSP, RSP_H,
179 R8, R8_H,
180 R9, R9_H,
181 R10, R10_H,
182 R11, R11_H,
183 R12, R12_H,
184 R13, R13_H,
185 R14, R14_H,
186 R15, R15_H);
187
188 // Class for all int registers
189 reg_class all_int_reg(RAX
190 RDX,
191 RBP,
192 RDI,
193 RSI,
194 RCX,
195 RBX,
196 R8,
197 R9,
198 R10,
199 R11,
200 R12,
201 R13,
202 R14);
203
204 // Class for all pointer registers
205 reg_class any_reg %{
206 return _ANY_REG_mask;
207 %}
208
209 // Class for all pointer registers (excluding RSP)
210 reg_class ptr_reg %{
211 return _PTR_REG_mask;
212 %}
213
214 // Class for all pointer registers (excluding RSP and RBP)
215 reg_class ptr_reg_no_rbp %{
216 return _PTR_REG_NO_RBP_mask;
217 %}
218
219 // Class for all pointer registers (excluding RAX and RSP)
220 reg_class ptr_no_rax_reg %{
221 return _PTR_NO_RAX_REG_mask;
222 %}
223
224 // Class for all pointer registers (excluding RAX, RBX, and RSP)
225 reg_class ptr_no_rax_rbx_reg %{
226 return _PTR_NO_RAX_RBX_REG_mask;
227 %}
228
229 // Class for all long registers (excluding RSP)
230 reg_class long_reg %{
231 return _LONG_REG_mask;
232 %}
233
234 // Class for all long registers (excluding RAX, RDX and RSP)
235 reg_class long_no_rax_rdx_reg %{
236 return _LONG_NO_RAX_RDX_REG_mask;
237 %}
238
239 // Class for all long registers (excluding RCX and RSP)
240 reg_class long_no_rcx_reg %{
241 return _LONG_NO_RCX_REG_mask;
242 %}
243
244 // Class for all long registers (excluding RBP and R13)
245 reg_class long_no_rbp_r13_reg %{
246 return _LONG_NO_RBP_R13_REG_mask;
247 %}
248
249 // Class for all int registers (excluding RSP)
250 reg_class int_reg %{
251 return _INT_REG_mask;
252 %}
253
254 // Class for all int registers (excluding RAX, RDX, and RSP)
255 reg_class int_no_rax_rdx_reg %{
256 return _INT_NO_RAX_RDX_REG_mask;
257 %}
258
259 // Class for all int registers (excluding RCX and RSP)
260 reg_class int_no_rcx_reg %{
261 return _INT_NO_RCX_REG_mask;
262 %}
263
264 // Class for all int registers (excluding RBP and R13)
265 reg_class int_no_rbp_r13_reg %{
266 return _INT_NO_RBP_R13_REG_mask;
267 %}
268
269 // Singleton class for RAX pointer register
270 reg_class ptr_rax_reg(RAX, RAX_H);
271
272 // Singleton class for RBX pointer register
273 reg_class ptr_rbx_reg(RBX, RBX_H);
274
275 // Singleton class for RSI pointer register
276 reg_class ptr_rsi_reg(RSI, RSI_H);
277
278 // Singleton class for RBP pointer register
279 reg_class ptr_rbp_reg(RBP, RBP_H);
280
281 // Singleton class for RDI pointer register
282 reg_class ptr_rdi_reg(RDI, RDI_H);
283
284 // Singleton class for stack pointer
285 reg_class ptr_rsp_reg(RSP, RSP_H);
286
287 // Singleton class for TLS pointer
288 reg_class ptr_r15_reg(R15, R15_H);
289
290 // Singleton class for RAX long register
291 reg_class long_rax_reg(RAX, RAX_H);
292
293 // Singleton class for RCX long register
294 reg_class long_rcx_reg(RCX, RCX_H);
295
296 // Singleton class for RDX long register
297 reg_class long_rdx_reg(RDX, RDX_H);
298
299 // Singleton class for RAX int register
300 reg_class int_rax_reg(RAX);
301
302 // Singleton class for RBX int register
303 reg_class int_rbx_reg(RBX);
304
305 // Singleton class for RCX int register
306 reg_class int_rcx_reg(RCX);
307
308 // Singleton class for RDX int register
309 reg_class int_rdx_reg(RDX);
310
311 // Singleton class for RDI int register
312 reg_class int_rdi_reg(RDI);
313
314 // Singleton class for instruction pointer
315 // reg_class ip_reg(RIP);
316
317 %}
318
319 //----------SOURCE BLOCK-------------------------------------------------------
320 // This is a block of C++ code which provides values, functions, and
321 // definitions necessary in the rest of the architecture description
322
323 source_hpp %{
324
325 #include "peephole_x86_64.hpp"
326
327 %}
328
329 // Register masks
330 source_hpp %{
331
332 extern RegMask _ANY_REG_mask;
333 extern RegMask _PTR_REG_mask;
334 extern RegMask _PTR_REG_NO_RBP_mask;
335 extern RegMask _PTR_NO_RAX_REG_mask;
336 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
337 extern RegMask _LONG_REG_mask;
338 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
339 extern RegMask _LONG_NO_RCX_REG_mask;
340 extern RegMask _LONG_NO_RBP_R13_REG_mask;
341 extern RegMask _INT_REG_mask;
342 extern RegMask _INT_NO_RAX_RDX_REG_mask;
343 extern RegMask _INT_NO_RCX_REG_mask;
344 extern RegMask _INT_NO_RBP_R13_REG_mask;
345 extern RegMask _FLOAT_REG_mask;
346
347 extern RegMask _STACK_OR_PTR_REG_mask;
348 extern RegMask _STACK_OR_LONG_REG_mask;
349 extern RegMask _STACK_OR_INT_REG_mask;
350
351 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
352 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
353 inline const RegMask& STACK_OR_INT_REG_mask() { return _STACK_OR_INT_REG_mask; }
354
355 %}
356
357 source %{
358 #define RELOC_IMM64 Assembler::imm_operand
359 #define RELOC_DISP32 Assembler::disp32_operand
360
361 #define __ _masm.
362
363 RegMask _ANY_REG_mask;
364 RegMask _PTR_REG_mask;
365 RegMask _PTR_REG_NO_RBP_mask;
366 RegMask _PTR_NO_RAX_REG_mask;
367 RegMask _PTR_NO_RAX_RBX_REG_mask;
368 RegMask _LONG_REG_mask;
369 RegMask _LONG_NO_RAX_RDX_REG_mask;
370 RegMask _LONG_NO_RCX_REG_mask;
371 RegMask _LONG_NO_RBP_R13_REG_mask;
372 RegMask _INT_REG_mask;
373 RegMask _INT_NO_RAX_RDX_REG_mask;
374 RegMask _INT_NO_RCX_REG_mask;
375 RegMask _INT_NO_RBP_R13_REG_mask;
376 RegMask _FLOAT_REG_mask;
377 RegMask _STACK_OR_PTR_REG_mask;
378 RegMask _STACK_OR_LONG_REG_mask;
379 RegMask _STACK_OR_INT_REG_mask;
380
381 static bool need_r12_heapbase() {
382 return UseCompressedOops;
383 }
384
385 void reg_mask_init() {
386 // _ALL_REG_mask is generated by adlc from the all_reg register class below.
387 // We derive a number of subsets from it.
388 _ANY_REG_mask = _ALL_REG_mask;
389
390 if (PreserveFramePointer) {
391 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
392 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
393 }
394 if (need_r12_heapbase()) {
395 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
396 _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
397 }
398
399 _PTR_REG_mask = _ANY_REG_mask;
400 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
401 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
402 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
403 _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
404
405 _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
406 _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
407
408 _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
409 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
410 _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
411
412 _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
413 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
414 _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
415
416 _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
417 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
418 _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
419
420 _LONG_REG_mask = _PTR_REG_mask;
421 _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
422 _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
423
424 _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
425 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
426 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
427 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
428 _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
429
430 _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
431 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
432 _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
433
434 _LONG_NO_RBP_R13_REG_mask = _LONG_REG_mask;
435 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
436 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
437 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()));
438 _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()->next()));
439
440 _INT_REG_mask = _ALL_INT_REG_mask;
441 if (PreserveFramePointer) {
442 _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
443 }
444 if (need_r12_heapbase()) {
445 _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
446 }
447
448 _STACK_OR_INT_REG_mask = _INT_REG_mask;
449 _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
450
451 _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
452 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
453 _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
454
455 _INT_NO_RCX_REG_mask = _INT_REG_mask;
456 _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
457
458 _INT_NO_RBP_R13_REG_mask = _INT_REG_mask;
459 _INT_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
460 _INT_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()));
461
462 // _FLOAT_REG_LEGACY_mask/_FLOAT_REG_EVEX_mask is generated by adlc
463 // from the float_reg_legacy/float_reg_evex register class.
464 _FLOAT_REG_mask = VM_Version::supports_evex() ? _FLOAT_REG_EVEX_mask : _FLOAT_REG_LEGACY_mask;
465 }
466
467 static bool generate_vzeroupper(Compile* C) {
468 return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false; // Generate vzeroupper
469 }
470
471 static int clear_avx_size() {
472 return generate_vzeroupper(Compile::current()) ? 3: 0; // vzeroupper
473 }
474
475 // !!!!! Special hack to get all types of calls to specify the byte offset
476 // from the start of the call to the point where the return address
477 // will point.
478 int MachCallStaticJavaNode::ret_addr_offset()
479 {
480 int offset = 5; // 5 bytes from start of call to where return address points
481 offset += clear_avx_size();
482 return offset;
483 }
484
485 int MachCallDynamicJavaNode::ret_addr_offset()
486 {
487 int offset = 15; // 15 bytes from start of call to where return address points
488 offset += clear_avx_size();
489 return offset;
490 }
491
492 int MachCallRuntimeNode::ret_addr_offset() {
493 if (_entry_point == nullptr) {
494 // CallLeafNoFPInDirect
495 return 3; // callq (register)
496 }
497 int offset = 13; // movq r10,#addr; callq (r10)
498 if (this->ideal_Opcode() != Op_CallLeafVector) {
499 offset += clear_avx_size();
500 }
501 return offset;
502 }
503
504 //
505 // Compute padding required for nodes which need alignment
506 //
507
508 // The address of the call instruction needs to be 4-byte aligned to
509 // ensure that it does not span a cache line so that it can be patched.
510 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
511 {
512 current_offset += clear_avx_size(); // skip vzeroupper
513 current_offset += 1; // skip call opcode byte
514 return align_up(current_offset, alignment_required()) - current_offset;
515 }
516
517 // The address of the call instruction needs to be 4-byte aligned to
518 // ensure that it does not span a cache line so that it can be patched.
519 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
520 {
521 current_offset += clear_avx_size(); // skip vzeroupper
522 current_offset += 11; // skip movq instruction + call opcode byte
523 return align_up(current_offset, alignment_required()) - current_offset;
524 }
525
526 // This could be in MacroAssembler but it's fairly C2 specific
527 static void emit_cmpfp_fixup(MacroAssembler& _masm) {
528 Label exit;
529 __ jccb(Assembler::noParity, exit);
530 __ pushf();
531 //
532 // comiss/ucomiss instructions set ZF,PF,CF flags and
533 // zero OF,AF,SF for NaN values.
534 // Fixup flags by zeroing ZF,PF so that compare of NaN
535 // values returns 'less than' result (CF is set).
536 // Leave the rest of flags unchanged.
537 //
538 // 7 6 5 4 3 2 1 0
539 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
540 // 0 0 1 0 1 0 1 1 (0x2B)
541 //
542 __ andq(Address(rsp, 0), 0xffffff2b);
543 __ popf();
544 __ bind(exit);
545 }
546
547 static void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
548 Label done;
549 __ movl(dst, -1);
550 __ jcc(Assembler::parity, done);
551 __ jcc(Assembler::below, done);
552 __ setb(Assembler::notEqual, dst);
553 __ movzbl(dst, dst);
554 __ bind(done);
555 }
556
557 // Math.min() # Math.max()
558 // --------------------------
559 // ucomis[s/d] #
560 // ja -> b # a
561 // jp -> NaN # NaN
562 // jb -> a # b
563 // je #
564 // |-jz -> a | b # a & b
565 // | -> a #
566 static void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
567 XMMRegister a, XMMRegister b,
568 XMMRegister xmmt, Register rt,
569 bool min, bool single) {
570
571 Label nan, zero, below, above, done;
572
573 if (single)
574 __ ucomiss(a, b);
575 else
576 __ ucomisd(a, b);
577
578 if (dst->encoding() != (min ? b : a)->encoding())
579 __ jccb(Assembler::above, above); // CF=0 & ZF=0
580 else
581 __ jccb(Assembler::above, done);
582
583 __ jccb(Assembler::parity, nan); // PF=1
584 __ jccb(Assembler::below, below); // CF=1
585
586 // equal
587 __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
588 if (single) {
589 __ ucomiss(a, xmmt);
590 __ jccb(Assembler::equal, zero);
591
592 __ movflt(dst, a);
593 __ jmp(done);
594 }
595 else {
596 __ ucomisd(a, xmmt);
597 __ jccb(Assembler::equal, zero);
598
599 __ movdbl(dst, a);
600 __ jmp(done);
601 }
602
603 __ bind(zero);
604 if (min)
605 __ vpor(dst, a, b, Assembler::AVX_128bit);
606 else
607 __ vpand(dst, a, b, Assembler::AVX_128bit);
608
609 __ jmp(done);
610
611 __ bind(above);
612 if (single)
613 __ movflt(dst, min ? b : a);
614 else
615 __ movdbl(dst, min ? b : a);
616
617 __ jmp(done);
618
619 __ bind(nan);
620 if (single) {
621 __ movl(rt, 0x7fc00000); // Float.NaN
622 __ movdl(dst, rt);
623 }
624 else {
625 __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
626 __ movdq(dst, rt);
627 }
628 __ jmp(done);
629
630 __ bind(below);
631 if (single)
632 __ movflt(dst, min ? a : b);
633 else
634 __ movdbl(dst, min ? a : b);
635
636 __ bind(done);
637 }
638
639 //=============================================================================
640 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
641
642 int ConstantTable::calculate_table_base_offset() const {
643 return 0; // absolute addressing, no offset
644 }
645
646 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
647 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
648 ShouldNotReachHere();
649 }
650
651 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
652 // Empty encoding
653 }
654
655 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
656 return 0;
657 }
658
659 #ifndef PRODUCT
660 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
661 st->print("# MachConstantBaseNode (empty encoding)");
662 }
663 #endif
664
665
666 //=============================================================================
667 #ifndef PRODUCT
668 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
669 Compile* C = ra_->C;
670
671 int framesize = C->output()->frame_size_in_bytes();
672 int bangsize = C->output()->bang_size_in_bytes();
673 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
674 // Remove wordSize for return addr which is already pushed.
675 framesize -= wordSize;
676
677 if (C->output()->need_stack_bang(bangsize)) {
678 framesize -= wordSize;
679 st->print("# stack bang (%d bytes)", bangsize);
680 st->print("\n\t");
681 st->print("pushq rbp\t# Save rbp");
682 if (PreserveFramePointer) {
683 st->print("\n\t");
684 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
685 }
686 if (framesize) {
687 st->print("\n\t");
688 st->print("subq rsp, #%d\t# Create frame",framesize);
689 }
690 } else {
691 st->print("subq rsp, #%d\t# Create frame",framesize);
692 st->print("\n\t");
693 framesize -= wordSize;
694 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
695 if (PreserveFramePointer) {
696 st->print("\n\t");
697 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
698 if (framesize > 0) {
699 st->print("\n\t");
700 st->print("addq rbp, #%d", framesize);
701 }
702 }
703 }
704
705 if (VerifyStackAtCalls) {
706 st->print("\n\t");
707 framesize -= wordSize;
708 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
709 #ifdef ASSERT
710 st->print("\n\t");
711 st->print("# stack alignment check");
712 #endif
713 }
714 if (C->stub_function() != nullptr && BarrierSet::barrier_set()->barrier_set_nmethod() != nullptr) {
715 st->print("\n\t");
716 st->print("cmpl [r15_thread + #disarmed_guard_value_offset], #disarmed_guard_value\t");
717 st->print("\n\t");
718 st->print("je fast_entry\t");
719 st->print("\n\t");
720 st->print("call #nmethod_entry_barrier_stub\t");
721 st->print("\n\tfast_entry:");
722 }
723 st->cr();
724 }
725 #endif
726
727 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
728 Compile* C = ra_->C;
729 C2_MacroAssembler _masm(&cbuf);
730
731 __ verified_entry(C);
732
733 if (ra_->C->stub_function() == nullptr) {
734 __ entry_barrier();
735 }
736
737 if (!Compile::current()->output()->in_scratch_emit_size()) {
738 __ bind(*_verified_entry);
739 }
740
741 C->output()->set_frame_complete(cbuf.insts_size());
742
743 if (C->has_mach_constant_base_node()) {
744 // NOTE: We set the table base offset here because users might be
745 // emitted before MachConstantBaseNode.
746 ConstantTable& constant_table = C->output()->constant_table();
747 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
748 }
749 }
750
751 int MachPrologNode::reloc() const
752 {
753 return 0; // a large enough number
754 }
755
756 //=============================================================================
757 #ifndef PRODUCT
758 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
759 {
760 Compile* C = ra_->C;
761 if (generate_vzeroupper(C)) {
762 st->print("vzeroupper");
763 st->cr(); st->print("\t");
764 }
765
766 int framesize = C->output()->frame_size_in_bytes();
767 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
768 // Remove word for return adr already pushed
769 // and RBP
770 framesize -= 2*wordSize;
771
772 if (framesize) {
773 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
774 st->print("\t");
775 }
776
777 st->print_cr("popq rbp");
778 if (do_polling() && C->is_method_compilation()) {
779 st->print("\t");
780 st->print_cr("cmpq rsp, poll_offset[r15_thread] \n\t"
781 "ja #safepoint_stub\t"
782 "# Safepoint: poll for GC");
783 }
784 }
785 #endif
786
787 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
788 {
789 Compile* C = ra_->C;
790 MacroAssembler _masm(&cbuf);
791
792 if (generate_vzeroupper(C)) {
793 // Clear upper bits of YMM registers when current compiled code uses
794 // wide vectors to avoid AVX <-> SSE transition penalty during call.
795 __ vzeroupper();
796 }
797
798 // Subtract two words to account for return address and rbp
799 int initial_framesize = C->output()->frame_size_in_bytes() - 2*wordSize;
800 __ remove_frame(initial_framesize, C->needs_stack_repair());
801
802 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
803 __ reserved_stack_check();
804 }
805
806 if (do_polling() && C->is_method_compilation()) {
807 MacroAssembler _masm(&cbuf);
808 Label dummy_label;
809 Label* code_stub = &dummy_label;
810 if (!C->output()->in_scratch_emit_size()) {
811 C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
812 C->output()->add_stub(stub);
813 code_stub = &stub->entry();
814 }
815 __ relocate(relocInfo::poll_return_type);
816 __ safepoint_poll(*code_stub, r15_thread, true /* at_return */, true /* in_nmethod */);
817 }
818 }
819
820 int MachEpilogNode::reloc() const
821 {
822 return 2; // a large enough number
823 }
824
825 const Pipeline* MachEpilogNode::pipeline() const
826 {
827 return MachNode::pipeline_class();
828 }
829
830 //=============================================================================
831
832 enum RC {
833 rc_bad,
834 rc_int,
835 rc_kreg,
836 rc_float,
837 rc_stack
838 };
839
840 static enum RC rc_class(OptoReg::Name reg)
841 {
842 if( !OptoReg::is_valid(reg) ) return rc_bad;
843
844 if (OptoReg::is_stack(reg)) return rc_stack;
845
846 VMReg r = OptoReg::as_VMReg(reg);
847
848 if (r->is_Register()) return rc_int;
849
850 if (r->is_KRegister()) return rc_kreg;
851
852 assert(r->is_XMMRegister(), "must be");
853 return rc_float;
854 }
855
856 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
857 static void vec_mov_helper(CodeBuffer *cbuf, int src_lo, int dst_lo,
858 int src_hi, int dst_hi, uint ireg, outputStream* st);
859
860 void vec_spill_helper(CodeBuffer *cbuf, bool is_load,
861 int stack_offset, int reg, uint ireg, outputStream* st);
862
863 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
864 int dst_offset, uint ireg, outputStream* st) {
865 if (cbuf) {
866 MacroAssembler _masm(cbuf);
867 switch (ireg) {
868 case Op_VecS:
869 __ movq(Address(rsp, -8), rax);
870 __ movl(rax, Address(rsp, src_offset));
871 __ movl(Address(rsp, dst_offset), rax);
872 __ movq(rax, Address(rsp, -8));
873 break;
874 case Op_VecD:
875 __ pushq(Address(rsp, src_offset));
876 __ popq (Address(rsp, dst_offset));
877 break;
878 case Op_VecX:
879 __ pushq(Address(rsp, src_offset));
880 __ popq (Address(rsp, dst_offset));
881 __ pushq(Address(rsp, src_offset+8));
882 __ popq (Address(rsp, dst_offset+8));
883 break;
884 case Op_VecY:
885 __ vmovdqu(Address(rsp, -32), xmm0);
886 __ vmovdqu(xmm0, Address(rsp, src_offset));
887 __ vmovdqu(Address(rsp, dst_offset), xmm0);
888 __ vmovdqu(xmm0, Address(rsp, -32));
889 break;
890 case Op_VecZ:
891 __ evmovdquq(Address(rsp, -64), xmm0, 2);
892 __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
893 __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
894 __ evmovdquq(xmm0, Address(rsp, -64), 2);
895 break;
896 default:
897 ShouldNotReachHere();
898 }
899 #ifndef PRODUCT
900 } else {
901 switch (ireg) {
902 case Op_VecS:
903 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
904 "movl rax, [rsp + #%d]\n\t"
905 "movl [rsp + #%d], rax\n\t"
906 "movq rax, [rsp - #8]",
907 src_offset, dst_offset);
908 break;
909 case Op_VecD:
910 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
911 "popq [rsp + #%d]",
912 src_offset, dst_offset);
913 break;
914 case Op_VecX:
915 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
916 "popq [rsp + #%d]\n\t"
917 "pushq [rsp + #%d]\n\t"
918 "popq [rsp + #%d]",
919 src_offset, dst_offset, src_offset+8, dst_offset+8);
920 break;
921 case Op_VecY:
922 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
923 "vmovdqu xmm0, [rsp + #%d]\n\t"
924 "vmovdqu [rsp + #%d], xmm0\n\t"
925 "vmovdqu xmm0, [rsp - #32]",
926 src_offset, dst_offset);
927 break;
928 case Op_VecZ:
929 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
930 "vmovdqu xmm0, [rsp + #%d]\n\t"
931 "vmovdqu [rsp + #%d], xmm0\n\t"
932 "vmovdqu xmm0, [rsp - #64]",
933 src_offset, dst_offset);
934 break;
935 default:
936 ShouldNotReachHere();
937 }
938 #endif
939 }
940 }
941
942 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
943 PhaseRegAlloc* ra_,
944 bool do_size,
945 outputStream* st) const {
946 assert(cbuf != nullptr || st != nullptr, "sanity");
947 // Get registers to move
948 OptoReg::Name src_second = ra_->get_reg_second(in(1));
949 OptoReg::Name src_first = ra_->get_reg_first(in(1));
950 OptoReg::Name dst_second = ra_->get_reg_second(this);
951 OptoReg::Name dst_first = ra_->get_reg_first(this);
952
953 enum RC src_second_rc = rc_class(src_second);
954 enum RC src_first_rc = rc_class(src_first);
955 enum RC dst_second_rc = rc_class(dst_second);
956 enum RC dst_first_rc = rc_class(dst_first);
957
958 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
959 "must move at least 1 register" );
960
961 if (src_first == dst_first && src_second == dst_second) {
962 // Self copy, no move
963 return 0;
964 }
965 if (bottom_type()->isa_vect() != nullptr && bottom_type()->isa_vectmask() == nullptr) {
966 uint ireg = ideal_reg();
967 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
968 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
969 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
970 // mem -> mem
971 int src_offset = ra_->reg2offset(src_first);
972 int dst_offset = ra_->reg2offset(dst_first);
973 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
974 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
975 vec_mov_helper(cbuf, src_first, dst_first, src_second, dst_second, ireg, st);
976 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
977 int stack_offset = ra_->reg2offset(dst_first);
978 vec_spill_helper(cbuf, false, stack_offset, src_first, ireg, st);
979 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
980 int stack_offset = ra_->reg2offset(src_first);
981 vec_spill_helper(cbuf, true, stack_offset, dst_first, ireg, st);
982 } else {
983 ShouldNotReachHere();
984 }
985 return 0;
986 }
987 if (src_first_rc == rc_stack) {
988 // mem ->
989 if (dst_first_rc == rc_stack) {
990 // mem -> mem
991 assert(src_second != dst_first, "overlap");
992 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
993 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
994 // 64-bit
995 int src_offset = ra_->reg2offset(src_first);
996 int dst_offset = ra_->reg2offset(dst_first);
997 if (cbuf) {
998 MacroAssembler _masm(cbuf);
999 __ pushq(Address(rsp, src_offset));
1000 __ popq (Address(rsp, dst_offset));
1001 #ifndef PRODUCT
1002 } else {
1003 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1004 "popq [rsp + #%d]",
1005 src_offset, dst_offset);
1006 #endif
1007 }
1008 } else {
1009 // 32-bit
1010 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1011 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1012 // No pushl/popl, so:
1013 int src_offset = ra_->reg2offset(src_first);
1014 int dst_offset = ra_->reg2offset(dst_first);
1015 if (cbuf) {
1016 MacroAssembler _masm(cbuf);
1017 __ movq(Address(rsp, -8), rax);
1018 __ movl(rax, Address(rsp, src_offset));
1019 __ movl(Address(rsp, dst_offset), rax);
1020 __ movq(rax, Address(rsp, -8));
1021 #ifndef PRODUCT
1022 } else {
1023 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1024 "movl rax, [rsp + #%d]\n\t"
1025 "movl [rsp + #%d], rax\n\t"
1026 "movq rax, [rsp - #8]",
1027 src_offset, dst_offset);
1028 #endif
1029 }
1030 }
1031 return 0;
1032 } else if (dst_first_rc == rc_int) {
1033 // mem -> gpr
1034 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1035 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1036 // 64-bit
1037 int offset = ra_->reg2offset(src_first);
1038 if (cbuf) {
1039 MacroAssembler _masm(cbuf);
1040 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1041 #ifndef PRODUCT
1042 } else {
1043 st->print("movq %s, [rsp + #%d]\t# spill",
1044 Matcher::regName[dst_first],
1045 offset);
1046 #endif
1047 }
1048 } else {
1049 // 32-bit
1050 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1051 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1052 int offset = ra_->reg2offset(src_first);
1053 if (cbuf) {
1054 MacroAssembler _masm(cbuf);
1055 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1056 #ifndef PRODUCT
1057 } else {
1058 st->print("movl %s, [rsp + #%d]\t# spill",
1059 Matcher::regName[dst_first],
1060 offset);
1061 #endif
1062 }
1063 }
1064 return 0;
1065 } else if (dst_first_rc == rc_float) {
1066 // mem-> xmm
1067 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1068 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1069 // 64-bit
1070 int offset = ra_->reg2offset(src_first);
1071 if (cbuf) {
1072 MacroAssembler _masm(cbuf);
1073 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1074 #ifndef PRODUCT
1075 } else {
1076 st->print("%s %s, [rsp + #%d]\t# spill",
1077 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1078 Matcher::regName[dst_first],
1079 offset);
1080 #endif
1081 }
1082 } else {
1083 // 32-bit
1084 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1085 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1086 int offset = ra_->reg2offset(src_first);
1087 if (cbuf) {
1088 MacroAssembler _masm(cbuf);
1089 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1090 #ifndef PRODUCT
1091 } else {
1092 st->print("movss %s, [rsp + #%d]\t# spill",
1093 Matcher::regName[dst_first],
1094 offset);
1095 #endif
1096 }
1097 }
1098 return 0;
1099 } else if (dst_first_rc == rc_kreg) {
1100 // mem -> kreg
1101 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1102 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1103 // 64-bit
1104 int offset = ra_->reg2offset(src_first);
1105 if (cbuf) {
1106 MacroAssembler _masm(cbuf);
1107 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1108 #ifndef PRODUCT
1109 } else {
1110 st->print("kmovq %s, [rsp + #%d]\t# spill",
1111 Matcher::regName[dst_first],
1112 offset);
1113 #endif
1114 }
1115 }
1116 return 0;
1117 }
1118 } else if (src_first_rc == rc_int) {
1119 // gpr ->
1120 if (dst_first_rc == rc_stack) {
1121 // gpr -> mem
1122 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1123 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1124 // 64-bit
1125 int offset = ra_->reg2offset(dst_first);
1126 if (cbuf) {
1127 MacroAssembler _masm(cbuf);
1128 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1129 #ifndef PRODUCT
1130 } else {
1131 st->print("movq [rsp + #%d], %s\t# spill",
1132 offset,
1133 Matcher::regName[src_first]);
1134 #endif
1135 }
1136 } else {
1137 // 32-bit
1138 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1139 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1140 int offset = ra_->reg2offset(dst_first);
1141 if (cbuf) {
1142 MacroAssembler _masm(cbuf);
1143 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1144 #ifndef PRODUCT
1145 } else {
1146 st->print("movl [rsp + #%d], %s\t# spill",
1147 offset,
1148 Matcher::regName[src_first]);
1149 #endif
1150 }
1151 }
1152 return 0;
1153 } else if (dst_first_rc == rc_int) {
1154 // gpr -> gpr
1155 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1156 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1157 // 64-bit
1158 if (cbuf) {
1159 MacroAssembler _masm(cbuf);
1160 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1161 as_Register(Matcher::_regEncode[src_first]));
1162 #ifndef PRODUCT
1163 } else {
1164 st->print("movq %s, %s\t# spill",
1165 Matcher::regName[dst_first],
1166 Matcher::regName[src_first]);
1167 #endif
1168 }
1169 return 0;
1170 } else {
1171 // 32-bit
1172 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1173 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1174 if (cbuf) {
1175 MacroAssembler _masm(cbuf);
1176 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1177 as_Register(Matcher::_regEncode[src_first]));
1178 #ifndef PRODUCT
1179 } else {
1180 st->print("movl %s, %s\t# spill",
1181 Matcher::regName[dst_first],
1182 Matcher::regName[src_first]);
1183 #endif
1184 }
1185 return 0;
1186 }
1187 } else if (dst_first_rc == rc_float) {
1188 // gpr -> xmm
1189 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1190 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1191 // 64-bit
1192 if (cbuf) {
1193 MacroAssembler _masm(cbuf);
1194 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1195 #ifndef PRODUCT
1196 } else {
1197 st->print("movdq %s, %s\t# spill",
1198 Matcher::regName[dst_first],
1199 Matcher::regName[src_first]);
1200 #endif
1201 }
1202 } else {
1203 // 32-bit
1204 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1205 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1206 if (cbuf) {
1207 MacroAssembler _masm(cbuf);
1208 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1209 #ifndef PRODUCT
1210 } else {
1211 st->print("movdl %s, %s\t# spill",
1212 Matcher::regName[dst_first],
1213 Matcher::regName[src_first]);
1214 #endif
1215 }
1216 }
1217 return 0;
1218 } else if (dst_first_rc == rc_kreg) {
1219 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1220 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1221 // 64-bit
1222 if (cbuf) {
1223 MacroAssembler _masm(cbuf);
1224 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1225 #ifndef PRODUCT
1226 } else {
1227 st->print("kmovq %s, %s\t# spill",
1228 Matcher::regName[dst_first],
1229 Matcher::regName[src_first]);
1230 #endif
1231 }
1232 }
1233 Unimplemented();
1234 return 0;
1235 }
1236 } else if (src_first_rc == rc_float) {
1237 // xmm ->
1238 if (dst_first_rc == rc_stack) {
1239 // xmm -> mem
1240 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1241 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1242 // 64-bit
1243 int offset = ra_->reg2offset(dst_first);
1244 if (cbuf) {
1245 MacroAssembler _masm(cbuf);
1246 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1247 #ifndef PRODUCT
1248 } else {
1249 st->print("movsd [rsp + #%d], %s\t# spill",
1250 offset,
1251 Matcher::regName[src_first]);
1252 #endif
1253 }
1254 } else {
1255 // 32-bit
1256 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1257 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1258 int offset = ra_->reg2offset(dst_first);
1259 if (cbuf) {
1260 MacroAssembler _masm(cbuf);
1261 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1262 #ifndef PRODUCT
1263 } else {
1264 st->print("movss [rsp + #%d], %s\t# spill",
1265 offset,
1266 Matcher::regName[src_first]);
1267 #endif
1268 }
1269 }
1270 return 0;
1271 } else if (dst_first_rc == rc_int) {
1272 // xmm -> gpr
1273 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1274 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1275 // 64-bit
1276 if (cbuf) {
1277 MacroAssembler _masm(cbuf);
1278 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1279 #ifndef PRODUCT
1280 } else {
1281 st->print("movdq %s, %s\t# spill",
1282 Matcher::regName[dst_first],
1283 Matcher::regName[src_first]);
1284 #endif
1285 }
1286 } else {
1287 // 32-bit
1288 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1289 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1290 if (cbuf) {
1291 MacroAssembler _masm(cbuf);
1292 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1293 #ifndef PRODUCT
1294 } else {
1295 st->print("movdl %s, %s\t# spill",
1296 Matcher::regName[dst_first],
1297 Matcher::regName[src_first]);
1298 #endif
1299 }
1300 }
1301 return 0;
1302 } else if (dst_first_rc == rc_float) {
1303 // xmm -> xmm
1304 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1305 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1306 // 64-bit
1307 if (cbuf) {
1308 MacroAssembler _masm(cbuf);
1309 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1310 #ifndef PRODUCT
1311 } else {
1312 st->print("%s %s, %s\t# spill",
1313 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1314 Matcher::regName[dst_first],
1315 Matcher::regName[src_first]);
1316 #endif
1317 }
1318 } else {
1319 // 32-bit
1320 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1321 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1322 if (cbuf) {
1323 MacroAssembler _masm(cbuf);
1324 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1325 #ifndef PRODUCT
1326 } else {
1327 st->print("%s %s, %s\t# spill",
1328 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1329 Matcher::regName[dst_first],
1330 Matcher::regName[src_first]);
1331 #endif
1332 }
1333 }
1334 return 0;
1335 } else if (dst_first_rc == rc_kreg) {
1336 assert(false, "Illegal spilling");
1337 return 0;
1338 }
1339 } else if (src_first_rc == rc_kreg) {
1340 if (dst_first_rc == rc_stack) {
1341 // mem -> kreg
1342 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1343 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1344 // 64-bit
1345 int offset = ra_->reg2offset(dst_first);
1346 if (cbuf) {
1347 MacroAssembler _masm(cbuf);
1348 __ kmov(Address(rsp, offset), as_KRegister(Matcher::_regEncode[src_first]));
1349 #ifndef PRODUCT
1350 } else {
1351 st->print("kmovq [rsp + #%d] , %s\t# spill",
1352 offset,
1353 Matcher::regName[src_first]);
1354 #endif
1355 }
1356 }
1357 return 0;
1358 } else if (dst_first_rc == rc_int) {
1359 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1360 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1361 // 64-bit
1362 if (cbuf) {
1363 MacroAssembler _masm(cbuf);
1364 __ kmov(as_Register(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1365 #ifndef PRODUCT
1366 } else {
1367 st->print("kmovq %s, %s\t# spill",
1368 Matcher::regName[dst_first],
1369 Matcher::regName[src_first]);
1370 #endif
1371 }
1372 }
1373 Unimplemented();
1374 return 0;
1375 } else if (dst_first_rc == rc_kreg) {
1376 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1377 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1378 // 64-bit
1379 if (cbuf) {
1380 MacroAssembler _masm(cbuf);
1381 __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
1382 #ifndef PRODUCT
1383 } else {
1384 st->print("kmovq %s, %s\t# spill",
1385 Matcher::regName[dst_first],
1386 Matcher::regName[src_first]);
1387 #endif
1388 }
1389 }
1390 return 0;
1391 } else if (dst_first_rc == rc_float) {
1392 assert(false, "Illegal spill");
1393 return 0;
1394 }
1395 }
1396
1397 assert(0," foo ");
1398 Unimplemented();
1399 return 0;
1400 }
1401
1402 #ifndef PRODUCT
1403 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1404 implementation(nullptr, ra_, false, st);
1405 }
1406 #endif
1407
1408 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1409 implementation(&cbuf, ra_, false, nullptr);
1410 }
1411
1412 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1413 return MachNode::size(ra_);
1414 }
1415
1416 //=============================================================================
1417 #ifndef PRODUCT
1418 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1419 {
1420 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1421 int reg = ra_->get_reg_first(this);
1422 st->print("leaq %s, [rsp + #%d]\t# box lock",
1423 Matcher::regName[reg], offset);
1424 }
1425 #endif
1426
1427 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1428 {
1429 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1430 int reg = ra_->get_encode(this);
1431
1432 MacroAssembler masm(&cbuf);
1433 masm.lea(as_Register(reg), Address(rsp, offset));
1434 }
1435
1436 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1437 {
1438 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1439 return (offset < 0x80) ? 5 : 8; // REX
1440 }
1441
1442 //=============================================================================
1443 #ifndef PRODUCT
1444 void MachVEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1445 {
1446 st->print_cr("MachVEPNode");
1447 }
1448 #endif
1449
1450 void MachVEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1451 {
1452 C2_MacroAssembler _masm(&cbuf);
1453 uint insts_size = cbuf.insts_size();
1454 if (!_verified) {
1455 if (UseCompressedClassPointers) {
1456 __ load_klass(rscratch1, j_rarg0, rscratch2);
1457 __ cmpptr(rax, rscratch1);
1458 } else {
1459 __ cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1460 }
1461 __ jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1462 } else {
1463 // TODO 8284443 Avoid creation of temporary frame
1464 if (ra_->C->stub_function() == nullptr) {
1465 __ verified_entry(ra_->C, 0);
1466 __ entry_barrier();
1467 int initial_framesize = ra_->C->output()->frame_size_in_bytes() - 2*wordSize;
1468 __ remove_frame(initial_framesize, false);
1469 }
1470 // Unpack inline type args passed as oop and then jump to
1471 // the verified entry point (skipping the unverified entry).
1472 int sp_inc = __ unpack_inline_args(ra_->C, _receiver_only);
1473 // Emit code for verified entry and save increment for stack repair on return
1474 __ verified_entry(ra_->C, sp_inc);
1475 if (Compile::current()->output()->in_scratch_emit_size()) {
1476 Label dummy_verified_entry;
1477 __ jmp(dummy_verified_entry);
1478 } else {
1479 __ jmp(*_verified_entry);
1480 }
1481 }
1482 /* WARNING these NOPs are critical so that verified entry point is properly
1483 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1484 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1485 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1486 if (nops_cnt > 0) {
1487 __ nop(nops_cnt);
1488 }
1489 }
1490
1491 //=============================================================================
1492 #ifndef PRODUCT
1493 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1494 {
1495 if (UseCompressedClassPointers) {
1496 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1497 st->print_cr("\tcmpl rscratch1, [rax + CompiledICData::speculated_klass_offset()]\t # Inline cache check");
1498 } else {
1499 st->print_cr("movq rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1500 st->print_cr("\tcmpq rscratch1, [rax + CompiledICData::speculated_klass_offset()]\t # Inline cache check");
1501 }
1502 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1503 }
1504 #endif
1505
1506 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1507 {
1508 MacroAssembler masm(&cbuf);
1509 masm.ic_check(InteriorEntryAlignment);
1510 }
1511
1512 //=============================================================================
1513
1514 bool Matcher::supports_vector_calling_convention(void) {
1515 if (EnableVectorSupport && UseVectorStubs) {
1516 return true;
1517 }
1518 return false;
1519 }
1520
1521 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
1522 assert(EnableVectorSupport && UseVectorStubs, "sanity");
1523 int lo = XMM0_num;
1524 int hi = XMM0b_num;
1525 if (ideal_reg == Op_VecX) hi = XMM0d_num;
1526 else if (ideal_reg == Op_VecY) hi = XMM0h_num;
1527 else if (ideal_reg == Op_VecZ) hi = XMM0p_num;
1528 return OptoRegPair(hi, lo);
1529 }
1530
1531 // Is this branch offset short enough that a short branch can be used?
1532 //
1533 // NOTE: If the platform does not provide any short branch variants, then
1534 // this method should return false for offset 0.
1535 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1536 // The passed offset is relative to address of the branch.
1537 // On 86 a branch displacement is calculated relative to address
1538 // of a next instruction.
1539 offset -= br_size;
1540
1541 // the short version of jmpConUCF2 contains multiple branches,
1542 // making the reach slightly less
1543 if (rule == jmpConUCF2_rule)
1544 return (-126 <= offset && offset <= 125);
1545 return (-128 <= offset && offset <= 127);
1546 }
1547
1548 // Return whether or not this register is ever used as an argument.
1549 // This function is used on startup to build the trampoline stubs in
1550 // generateOptoStub. Registers not mentioned will be killed by the VM
1551 // call in the trampoline, and arguments in those registers not be
1552 // available to the callee.
1553 bool Matcher::can_be_java_arg(int reg)
1554 {
1555 return
1556 reg == RDI_num || reg == RDI_H_num ||
1557 reg == RSI_num || reg == RSI_H_num ||
1558 reg == RDX_num || reg == RDX_H_num ||
1559 reg == RCX_num || reg == RCX_H_num ||
1560 reg == R8_num || reg == R8_H_num ||
1561 reg == R9_num || reg == R9_H_num ||
1562 reg == R12_num || reg == R12_H_num ||
1563 reg == XMM0_num || reg == XMM0b_num ||
1564 reg == XMM1_num || reg == XMM1b_num ||
1565 reg == XMM2_num || reg == XMM2b_num ||
1566 reg == XMM3_num || reg == XMM3b_num ||
1567 reg == XMM4_num || reg == XMM4b_num ||
1568 reg == XMM5_num || reg == XMM5b_num ||
1569 reg == XMM6_num || reg == XMM6b_num ||
1570 reg == XMM7_num || reg == XMM7b_num;
1571 }
1572
1573 bool Matcher::is_spillable_arg(int reg)
1574 {
1575 return can_be_java_arg(reg);
1576 }
1577
1578 uint Matcher::int_pressure_limit()
1579 {
1580 return (INTPRESSURE == -1) ? _INT_REG_mask.Size() : INTPRESSURE;
1581 }
1582
1583 uint Matcher::float_pressure_limit()
1584 {
1585 // After experiment around with different values, the following default threshold
1586 // works best for LCM's register pressure scheduling on x64.
1587 uint dec_count = VM_Version::supports_evex() ? 4 : 2;
1588 uint default_float_pressure_threshold = _FLOAT_REG_mask.Size() - dec_count;
1589 return (FLOATPRESSURE == -1) ? default_float_pressure_threshold : FLOATPRESSURE;
1590 }
1591
1592 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1593 // In 64 bit mode a code which use multiply when
1594 // devisor is constant is faster than hardware
1595 // DIV instruction (it uses MulHiL).
1596 return false;
1597 }
1598
1599 // Register for DIVI projection of divmodI
1600 RegMask Matcher::divI_proj_mask() {
1601 return INT_RAX_REG_mask();
1602 }
1603
1604 // Register for MODI projection of divmodI
1605 RegMask Matcher::modI_proj_mask() {
1606 return INT_RDX_REG_mask();
1607 }
1608
1609 // Register for DIVL projection of divmodL
1610 RegMask Matcher::divL_proj_mask() {
1611 return LONG_RAX_REG_mask();
1612 }
1613
1614 // Register for MODL projection of divmodL
1615 RegMask Matcher::modL_proj_mask() {
1616 return LONG_RDX_REG_mask();
1617 }
1618
1619 // Register for saving SP into on method handle invokes. Not used on x86_64.
1620 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1621 return NO_REG_mask();
1622 }
1623
1624 %}
1625
1626 //----------ENCODING BLOCK-----------------------------------------------------
1627 // This block specifies the encoding classes used by the compiler to
1628 // output byte streams. Encoding classes are parameterized macros
1629 // used by Machine Instruction Nodes in order to generate the bit
1630 // encoding of the instruction. Operands specify their base encoding
1631 // interface with the interface keyword. There are currently
1632 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1633 // COND_INTER. REG_INTER causes an operand to generate a function
1634 // which returns its register number when queried. CONST_INTER causes
1635 // an operand to generate a function which returns the value of the
1636 // constant when queried. MEMORY_INTER causes an operand to generate
1637 // four functions which return the Base Register, the Index Register,
1638 // the Scale Value, and the Offset Value of the operand when queried.
1639 // COND_INTER causes an operand to generate six functions which return
1640 // the encoding code (ie - encoding bits for the instruction)
1641 // associated with each basic boolean condition for a conditional
1642 // instruction.
1643 //
1644 // Instructions specify two basic values for encoding. Again, a
1645 // function is available to check if the constant displacement is an
1646 // oop. They use the ins_encode keyword to specify their encoding
1647 // classes (which must be a sequence of enc_class names, and their
1648 // parameters, specified in the encoding block), and they use the
1649 // opcode keyword to specify, in order, their primary, secondary, and
1650 // tertiary opcode. Only the opcode sections which a particular
1651 // instruction needs for encoding need to be specified.
1652 encode %{
1653 enc_class cdql_enc(no_rax_rdx_RegI div)
1654 %{
1655 // Full implementation of Java idiv and irem; checks for
1656 // special case as described in JVM spec., p.243 & p.271.
1657 //
1658 // normal case special case
1659 //
1660 // input : rax: dividend min_int
1661 // reg: divisor -1
1662 //
1663 // output: rax: quotient (= rax idiv reg) min_int
1664 // rdx: remainder (= rax irem reg) 0
1665 //
1666 // Code sequnce:
1667 //
1668 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1669 // 5: 75 07/08 jne e <normal>
1670 // 7: 33 d2 xor %edx,%edx
1671 // [div >= 8 -> offset + 1]
1672 // [REX_B]
1673 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1674 // c: 74 03/04 je 11 <done>
1675 // 000000000000000e <normal>:
1676 // e: 99 cltd
1677 // [div >= 8 -> offset + 1]
1678 // [REX_B]
1679 // f: f7 f9 idiv $div
1680 // 0000000000000011 <done>:
1681 MacroAssembler _masm(&cbuf);
1682 Label normal;
1683 Label done;
1684
1685 // cmp $0x80000000,%eax
1686 __ cmpl(as_Register(RAX_enc), 0x80000000);
1687
1688 // jne e <normal>
1689 __ jccb(Assembler::notEqual, normal);
1690
1691 // xor %edx,%edx
1692 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1693
1694 // cmp $0xffffffffffffffff,%ecx
1695 __ cmpl($div$$Register, -1);
1696
1697 // je 11 <done>
1698 __ jccb(Assembler::equal, done);
1699
1700 // <normal>
1701 // cltd
1702 __ bind(normal);
1703 __ cdql();
1704
1705 // idivl
1706 // <done>
1707 __ idivl($div$$Register);
1708 __ bind(done);
1709 %}
1710
1711 enc_class cdqq_enc(no_rax_rdx_RegL div)
1712 %{
1713 // Full implementation of Java ldiv and lrem; checks for
1714 // special case as described in JVM spec., p.243 & p.271.
1715 //
1716 // normal case special case
1717 //
1718 // input : rax: dividend min_long
1719 // reg: divisor -1
1720 //
1721 // output: rax: quotient (= rax idiv reg) min_long
1722 // rdx: remainder (= rax irem reg) 0
1723 //
1724 // Code sequnce:
1725 //
1726 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1727 // 7: 00 00 80
1728 // a: 48 39 d0 cmp %rdx,%rax
1729 // d: 75 08 jne 17 <normal>
1730 // f: 33 d2 xor %edx,%edx
1731 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1732 // 15: 74 05 je 1c <done>
1733 // 0000000000000017 <normal>:
1734 // 17: 48 99 cqto
1735 // 19: 48 f7 f9 idiv $div
1736 // 000000000000001c <done>:
1737 MacroAssembler _masm(&cbuf);
1738 Label normal;
1739 Label done;
1740
1741 // mov $0x8000000000000000,%rdx
1742 __ mov64(as_Register(RDX_enc), 0x8000000000000000);
1743
1744 // cmp %rdx,%rax
1745 __ cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
1746
1747 // jne 17 <normal>
1748 __ jccb(Assembler::notEqual, normal);
1749
1750 // xor %edx,%edx
1751 __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
1752
1753 // cmp $0xffffffffffffffff,$div
1754 __ cmpq($div$$Register, -1);
1755
1756 // je 1e <done>
1757 __ jccb(Assembler::equal, done);
1758
1759 // <normal>
1760 // cqto
1761 __ bind(normal);
1762 __ cdqq();
1763
1764 // idivq (note: must be emitted by the user of this rule)
1765 // <done>
1766 __ idivq($div$$Register);
1767 __ bind(done);
1768 %}
1769
1770 enc_class enc_PartialSubtypeCheck()
1771 %{
1772 Register Rrdi = as_Register(RDI_enc); // result register
1773 Register Rrax = as_Register(RAX_enc); // super class
1774 Register Rrcx = as_Register(RCX_enc); // killed
1775 Register Rrsi = as_Register(RSI_enc); // sub class
1776 Label miss;
1777 const bool set_cond_codes = true;
1778
1779 MacroAssembler _masm(&cbuf);
1780 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
1781 nullptr, &miss,
1782 /*set_cond_codes:*/ true);
1783 if ($primary) {
1784 __ xorptr(Rrdi, Rrdi);
1785 }
1786 __ bind(miss);
1787 %}
1788
1789 enc_class clear_avx %{
1790 debug_only(int off0 = cbuf.insts_size());
1791 if (generate_vzeroupper(Compile::current())) {
1792 // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
1793 // Clear upper bits of YMM registers when current compiled code uses
1794 // wide vectors to avoid AVX <-> SSE transition penalty during call.
1795 MacroAssembler _masm(&cbuf);
1796 __ vzeroupper();
1797 }
1798 debug_only(int off1 = cbuf.insts_size());
1799 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
1800 %}
1801
1802 enc_class Java_To_Runtime(method meth) %{
1803 // No relocation needed
1804 MacroAssembler _masm(&cbuf);
1805 __ mov64(r10, (int64_t) $meth$$method);
1806 __ call(r10);
1807 __ post_call_nop();
1808 %}
1809
1810 enc_class Java_Static_Call(method meth)
1811 %{
1812 // JAVA STATIC CALL
1813 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
1814 // determine who we intended to call.
1815 MacroAssembler _masm(&cbuf);
1816
1817 if (!_method) {
1818 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, $meth$$method)));
1819 } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
1820 // The NOP here is purely to ensure that eliding a call to
1821 // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
1822 __ addr_nop_5();
1823 __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
1824 } else {
1825 int method_index = resolved_method_index(cbuf);
1826 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
1827 : static_call_Relocation::spec(method_index);
1828 address mark = __ pc();
1829 int call_offset = __ offset();
1830 __ call(AddressLiteral(CAST_FROM_FN_PTR(address, $meth$$method), rspec));
1831 if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
1832 // Calls of the same statically bound method can share
1833 // a stub to the interpreter.
1834 cbuf.shared_stub_to_interp_for(_method, call_offset);
1835 } else {
1836 // Emit stubs for static call.
1837 address stub = CompiledDirectCall::emit_to_interp_stub(cbuf, mark);
1838 if (stub == nullptr) {
1839 ciEnv::current()->record_failure("CodeCache is full");
1840 return;
1841 }
1842 }
1843 }
1844 __ post_call_nop();
1845 %}
1846
1847 enc_class Java_Dynamic_Call(method meth) %{
1848 MacroAssembler _masm(&cbuf);
1849 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
1850 __ post_call_nop();
1851 %}
1852
1853 %}
1854
1855
1856
1857 //----------FRAME--------------------------------------------------------------
1858 // Definition of frame structure and management information.
1859 //
1860 // S T A C K L A Y O U T Allocators stack-slot number
1861 // | (to get allocators register number
1862 // G Owned by | | v add OptoReg::stack0())
1863 // r CALLER | |
1864 // o | +--------+ pad to even-align allocators stack-slot
1865 // w V | pad0 | numbers; owned by CALLER
1866 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
1867 // h ^ | in | 5
1868 // | | args | 4 Holes in incoming args owned by SELF
1869 // | | | | 3
1870 // | | +--------+
1871 // V | | old out| Empty on Intel, window on Sparc
1872 // | old |preserve| Must be even aligned.
1873 // | SP-+--------+----> Matcher::_old_SP, even aligned
1874 // | | in | 3 area for Intel ret address
1875 // Owned by |preserve| Empty on Sparc.
1876 // SELF +--------+
1877 // | | pad2 | 2 pad to align old SP
1878 // | +--------+ 1
1879 // | | locks | 0
1880 // | +--------+----> OptoReg::stack0(), even aligned
1881 // | | pad1 | 11 pad to align new SP
1882 // | +--------+
1883 // | | | 10
1884 // | | spills | 9 spills
1885 // V | | 8 (pad0 slot for callee)
1886 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
1887 // ^ | out | 7
1888 // | | args | 6 Holes in outgoing args owned by CALLEE
1889 // Owned by +--------+
1890 // CALLEE | new out| 6 Empty on Intel, window on Sparc
1891 // | new |preserve| Must be even-aligned.
1892 // | SP-+--------+----> Matcher::_new_SP, even aligned
1893 // | | |
1894 //
1895 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
1896 // known from SELF's arguments and the Java calling convention.
1897 // Region 6-7 is determined per call site.
1898 // Note 2: If the calling convention leaves holes in the incoming argument
1899 // area, those holes are owned by SELF. Holes in the outgoing area
1900 // are owned by the CALLEE. Holes should not be necessary in the
1901 // incoming area, as the Java calling convention is completely under
1902 // the control of the AD file. Doubles can be sorted and packed to
1903 // avoid holes. Holes in the outgoing arguments may be necessary for
1904 // varargs C calling conventions.
1905 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
1906 // even aligned with pad0 as needed.
1907 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
1908 // region 6-11 is even aligned; it may be padded out more so that
1909 // the region from SP to FP meets the minimum stack alignment.
1910 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
1911 // alignment. Region 11, pad1, may be dynamically extended so that
1912 // SP meets the minimum alignment.
1913
1914 frame
1915 %{
1916 // These three registers define part of the calling convention
1917 // between compiled code and the interpreter.
1918 inline_cache_reg(RAX); // Inline Cache Register
1919
1920 // Optional: name the operand used by cisc-spilling to access
1921 // [stack_pointer + offset]
1922 cisc_spilling_operand_name(indOffset32);
1923
1924 // Number of stack slots consumed by locking an object
1925 sync_stack_slots(2);
1926
1927 // Compiled code's Frame Pointer
1928 frame_pointer(RSP);
1929
1930 // Interpreter stores its frame pointer in a register which is
1931 // stored to the stack by I2CAdaptors.
1932 // I2CAdaptors convert from interpreted java to compiled java.
1933 interpreter_frame_pointer(RBP);
1934
1935 // Stack alignment requirement
1936 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
1937
1938 // Number of outgoing stack slots killed above the out_preserve_stack_slots
1939 // for calls to C. Supports the var-args backing area for register parms.
1940 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
1941
1942 // The after-PROLOG location of the return address. Location of
1943 // return address specifies a type (REG or STACK) and a number
1944 // representing the register number (i.e. - use a register name) or
1945 // stack slot.
1946 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
1947 // Otherwise, it is above the locks and verification slot and alignment word
1948 return_addr(STACK - 2 +
1949 align_up((Compile::current()->in_preserve_stack_slots() +
1950 Compile::current()->fixed_slots()),
1951 stack_alignment_in_slots()));
1952
1953 // Location of compiled Java return values. Same as C for now.
1954 return_value
1955 %{
1956 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
1957 "only return normal values");
1958
1959 static const int lo[Op_RegL + 1] = {
1960 0,
1961 0,
1962 RAX_num, // Op_RegN
1963 RAX_num, // Op_RegI
1964 RAX_num, // Op_RegP
1965 XMM0_num, // Op_RegF
1966 XMM0_num, // Op_RegD
1967 RAX_num // Op_RegL
1968 };
1969 static const int hi[Op_RegL + 1] = {
1970 0,
1971 0,
1972 OptoReg::Bad, // Op_RegN
1973 OptoReg::Bad, // Op_RegI
1974 RAX_H_num, // Op_RegP
1975 OptoReg::Bad, // Op_RegF
1976 XMM0b_num, // Op_RegD
1977 RAX_H_num // Op_RegL
1978 };
1979 // Excluded flags and vector registers.
1980 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type");
1981 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
1982 %}
1983 %}
1984
1985 //----------ATTRIBUTES---------------------------------------------------------
1986 //----------Operand Attributes-------------------------------------------------
1987 op_attrib op_cost(0); // Required cost attribute
1988
1989 //----------Instruction Attributes---------------------------------------------
1990 ins_attrib ins_cost(100); // Required cost attribute
1991 ins_attrib ins_size(8); // Required size attribute (in bits)
1992 ins_attrib ins_short_branch(0); // Required flag: is this instruction
1993 // a non-matching short branch variant
1994 // of some long branch?
1995 ins_attrib ins_alignment(1); // Required alignment attribute (must
1996 // be a power of 2) specifies the
1997 // alignment that some part of the
1998 // instruction (not necessarily the
1999 // start) requires. If > 1, a
2000 // compute_padding() function must be
2001 // provided for the instruction
2002
2003 //----------OPERANDS-----------------------------------------------------------
2004 // Operand definitions must precede instruction definitions for correct parsing
2005 // in the ADLC because operands constitute user defined types which are used in
2006 // instruction definitions.
2007
2008 //----------Simple Operands----------------------------------------------------
2009 // Immediate Operands
2010 // Integer Immediate
2011 operand immI()
2012 %{
2013 match(ConI);
2014
2015 op_cost(10);
2016 format %{ %}
2017 interface(CONST_INTER);
2018 %}
2019
2020 // Constant for test vs zero
2021 operand immI_0()
2022 %{
2023 predicate(n->get_int() == 0);
2024 match(ConI);
2025
2026 op_cost(0);
2027 format %{ %}
2028 interface(CONST_INTER);
2029 %}
2030
2031 // Constant for increment
2032 operand immI_1()
2033 %{
2034 predicate(n->get_int() == 1);
2035 match(ConI);
2036
2037 op_cost(0);
2038 format %{ %}
2039 interface(CONST_INTER);
2040 %}
2041
2042 // Constant for decrement
2043 operand immI_M1()
2044 %{
2045 predicate(n->get_int() == -1);
2046 match(ConI);
2047
2048 op_cost(0);
2049 format %{ %}
2050 interface(CONST_INTER);
2051 %}
2052
2053 operand immI_2()
2054 %{
2055 predicate(n->get_int() == 2);
2056 match(ConI);
2057
2058 op_cost(0);
2059 format %{ %}
2060 interface(CONST_INTER);
2061 %}
2062
2063 operand immI_4()
2064 %{
2065 predicate(n->get_int() == 4);
2066 match(ConI);
2067
2068 op_cost(0);
2069 format %{ %}
2070 interface(CONST_INTER);
2071 %}
2072
2073 operand immI_8()
2074 %{
2075 predicate(n->get_int() == 8);
2076 match(ConI);
2077
2078 op_cost(0);
2079 format %{ %}
2080 interface(CONST_INTER);
2081 %}
2082
2083 // Valid scale values for addressing modes
2084 operand immI2()
2085 %{
2086 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2087 match(ConI);
2088
2089 format %{ %}
2090 interface(CONST_INTER);
2091 %}
2092
2093 operand immU7()
2094 %{
2095 predicate((0 <= n->get_int()) && (n->get_int() <= 0x7F));
2096 match(ConI);
2097
2098 op_cost(5);
2099 format %{ %}
2100 interface(CONST_INTER);
2101 %}
2102
2103 operand immI8()
2104 %{
2105 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2106 match(ConI);
2107
2108 op_cost(5);
2109 format %{ %}
2110 interface(CONST_INTER);
2111 %}
2112
2113 operand immU8()
2114 %{
2115 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2116 match(ConI);
2117
2118 op_cost(5);
2119 format %{ %}
2120 interface(CONST_INTER);
2121 %}
2122
2123 operand immI16()
2124 %{
2125 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2126 match(ConI);
2127
2128 op_cost(10);
2129 format %{ %}
2130 interface(CONST_INTER);
2131 %}
2132
2133 // Int Immediate non-negative
2134 operand immU31()
2135 %{
2136 predicate(n->get_int() >= 0);
2137 match(ConI);
2138
2139 op_cost(0);
2140 format %{ %}
2141 interface(CONST_INTER);
2142 %}
2143
2144 // Constant for long shifts
2145 operand immI_32()
2146 %{
2147 predicate( n->get_int() == 32 );
2148 match(ConI);
2149
2150 op_cost(0);
2151 format %{ %}
2152 interface(CONST_INTER);
2153 %}
2154
2155 // Constant for long shifts
2156 operand immI_64()
2157 %{
2158 predicate( n->get_int() == 64 );
2159 match(ConI);
2160
2161 op_cost(0);
2162 format %{ %}
2163 interface(CONST_INTER);
2164 %}
2165
2166 // Pointer Immediate
2167 operand immP()
2168 %{
2169 match(ConP);
2170
2171 op_cost(10);
2172 format %{ %}
2173 interface(CONST_INTER);
2174 %}
2175
2176 // Null Pointer Immediate
2177 operand immP0()
2178 %{
2179 predicate(n->get_ptr() == 0);
2180 match(ConP);
2181
2182 op_cost(5);
2183 format %{ %}
2184 interface(CONST_INTER);
2185 %}
2186
2187 // Pointer Immediate
2188 operand immN() %{
2189 match(ConN);
2190
2191 op_cost(10);
2192 format %{ %}
2193 interface(CONST_INTER);
2194 %}
2195
2196 operand immNKlass() %{
2197 match(ConNKlass);
2198
2199 op_cost(10);
2200 format %{ %}
2201 interface(CONST_INTER);
2202 %}
2203
2204 // Null Pointer Immediate
2205 operand immN0() %{
2206 predicate(n->get_narrowcon() == 0);
2207 match(ConN);
2208
2209 op_cost(5);
2210 format %{ %}
2211 interface(CONST_INTER);
2212 %}
2213
2214 operand immP31()
2215 %{
2216 predicate(n->as_Type()->type()->reloc() == relocInfo::none
2217 && (n->get_ptr() >> 31) == 0);
2218 match(ConP);
2219
2220 op_cost(5);
2221 format %{ %}
2222 interface(CONST_INTER);
2223 %}
2224
2225
2226 // Long Immediate
2227 operand immL()
2228 %{
2229 match(ConL);
2230
2231 op_cost(20);
2232 format %{ %}
2233 interface(CONST_INTER);
2234 %}
2235
2236 // Long Immediate 8-bit
2237 operand immL8()
2238 %{
2239 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
2240 match(ConL);
2241
2242 op_cost(5);
2243 format %{ %}
2244 interface(CONST_INTER);
2245 %}
2246
2247 // Long Immediate 32-bit unsigned
2248 operand immUL32()
2249 %{
2250 predicate(n->get_long() == (unsigned int) (n->get_long()));
2251 match(ConL);
2252
2253 op_cost(10);
2254 format %{ %}
2255 interface(CONST_INTER);
2256 %}
2257
2258 // Long Immediate 32-bit signed
2259 operand immL32()
2260 %{
2261 predicate(n->get_long() == (int) (n->get_long()));
2262 match(ConL);
2263
2264 op_cost(15);
2265 format %{ %}
2266 interface(CONST_INTER);
2267 %}
2268
2269 operand immL_Pow2()
2270 %{
2271 predicate(is_power_of_2((julong)n->get_long()));
2272 match(ConL);
2273
2274 op_cost(15);
2275 format %{ %}
2276 interface(CONST_INTER);
2277 %}
2278
2279 operand immL_NotPow2()
2280 %{
2281 predicate(is_power_of_2((julong)~n->get_long()));
2282 match(ConL);
2283
2284 op_cost(15);
2285 format %{ %}
2286 interface(CONST_INTER);
2287 %}
2288
2289 // Long Immediate zero
2290 operand immL0()
2291 %{
2292 predicate(n->get_long() == 0L);
2293 match(ConL);
2294
2295 op_cost(10);
2296 format %{ %}
2297 interface(CONST_INTER);
2298 %}
2299
2300 // Constant for increment
2301 operand immL1()
2302 %{
2303 predicate(n->get_long() == 1);
2304 match(ConL);
2305
2306 format %{ %}
2307 interface(CONST_INTER);
2308 %}
2309
2310 // Constant for decrement
2311 operand immL_M1()
2312 %{
2313 predicate(n->get_long() == -1);
2314 match(ConL);
2315
2316 format %{ %}
2317 interface(CONST_INTER);
2318 %}
2319
2320 // Long Immediate: the value 10
2321 operand immL10()
2322 %{
2323 predicate(n->get_long() == 10);
2324 match(ConL);
2325
2326 format %{ %}
2327 interface(CONST_INTER);
2328 %}
2329
2330 // Long immediate from 0 to 127.
2331 // Used for a shorter form of long mul by 10.
2332 operand immL_127()
2333 %{
2334 predicate(0 <= n->get_long() && n->get_long() < 0x80);
2335 match(ConL);
2336
2337 op_cost(10);
2338 format %{ %}
2339 interface(CONST_INTER);
2340 %}
2341
2342 // Long Immediate: low 32-bit mask
2343 operand immL_32bits()
2344 %{
2345 predicate(n->get_long() == 0xFFFFFFFFL);
2346 match(ConL);
2347 op_cost(20);
2348
2349 format %{ %}
2350 interface(CONST_INTER);
2351 %}
2352
2353 // Int Immediate: 2^n-1, positive
2354 operand immI_Pow2M1()
2355 %{
2356 predicate((n->get_int() > 0)
2357 && is_power_of_2((juint)n->get_int() + 1));
2358 match(ConI);
2359
2360 op_cost(20);
2361 format %{ %}
2362 interface(CONST_INTER);
2363 %}
2364
2365 // Float Immediate zero
2366 operand immF0()
2367 %{
2368 predicate(jint_cast(n->getf()) == 0);
2369 match(ConF);
2370
2371 op_cost(5);
2372 format %{ %}
2373 interface(CONST_INTER);
2374 %}
2375
2376 // Float Immediate
2377 operand immF()
2378 %{
2379 match(ConF);
2380
2381 op_cost(15);
2382 format %{ %}
2383 interface(CONST_INTER);
2384 %}
2385
2386 // Double Immediate zero
2387 operand immD0()
2388 %{
2389 predicate(jlong_cast(n->getd()) == 0);
2390 match(ConD);
2391
2392 op_cost(5);
2393 format %{ %}
2394 interface(CONST_INTER);
2395 %}
2396
2397 // Double Immediate
2398 operand immD()
2399 %{
2400 match(ConD);
2401
2402 op_cost(15);
2403 format %{ %}
2404 interface(CONST_INTER);
2405 %}
2406
2407 // Immediates for special shifts (sign extend)
2408
2409 // Constants for increment
2410 operand immI_16()
2411 %{
2412 predicate(n->get_int() == 16);
2413 match(ConI);
2414
2415 format %{ %}
2416 interface(CONST_INTER);
2417 %}
2418
2419 operand immI_24()
2420 %{
2421 predicate(n->get_int() == 24);
2422 match(ConI);
2423
2424 format %{ %}
2425 interface(CONST_INTER);
2426 %}
2427
2428 // Constant for byte-wide masking
2429 operand immI_255()
2430 %{
2431 predicate(n->get_int() == 255);
2432 match(ConI);
2433
2434 format %{ %}
2435 interface(CONST_INTER);
2436 %}
2437
2438 // Constant for short-wide masking
2439 operand immI_65535()
2440 %{
2441 predicate(n->get_int() == 65535);
2442 match(ConI);
2443
2444 format %{ %}
2445 interface(CONST_INTER);
2446 %}
2447
2448 // Constant for byte-wide masking
2449 operand immL_255()
2450 %{
2451 predicate(n->get_long() == 255);
2452 match(ConL);
2453
2454 format %{ %}
2455 interface(CONST_INTER);
2456 %}
2457
2458 // Constant for short-wide masking
2459 operand immL_65535()
2460 %{
2461 predicate(n->get_long() == 65535);
2462 match(ConL);
2463
2464 format %{ %}
2465 interface(CONST_INTER);
2466 %}
2467
2468 operand kReg()
2469 %{
2470 constraint(ALLOC_IN_RC(vectmask_reg));
2471 match(RegVectMask);
2472 format %{%}
2473 interface(REG_INTER);
2474 %}
2475
2476 operand kReg_K1()
2477 %{
2478 constraint(ALLOC_IN_RC(vectmask_reg_K1));
2479 match(RegVectMask);
2480 format %{%}
2481 interface(REG_INTER);
2482 %}
2483
2484 operand kReg_K2()
2485 %{
2486 constraint(ALLOC_IN_RC(vectmask_reg_K2));
2487 match(RegVectMask);
2488 format %{%}
2489 interface(REG_INTER);
2490 %}
2491
2492 // Special Registers
2493 operand kReg_K3()
2494 %{
2495 constraint(ALLOC_IN_RC(vectmask_reg_K3));
2496 match(RegVectMask);
2497 format %{%}
2498 interface(REG_INTER);
2499 %}
2500
2501 operand kReg_K4()
2502 %{
2503 constraint(ALLOC_IN_RC(vectmask_reg_K4));
2504 match(RegVectMask);
2505 format %{%}
2506 interface(REG_INTER);
2507 %}
2508
2509 operand kReg_K5()
2510 %{
2511 constraint(ALLOC_IN_RC(vectmask_reg_K5));
2512 match(RegVectMask);
2513 format %{%}
2514 interface(REG_INTER);
2515 %}
2516
2517 operand kReg_K6()
2518 %{
2519 constraint(ALLOC_IN_RC(vectmask_reg_K6));
2520 match(RegVectMask);
2521 format %{%}
2522 interface(REG_INTER);
2523 %}
2524
2525 // Special Registers
2526 operand kReg_K7()
2527 %{
2528 constraint(ALLOC_IN_RC(vectmask_reg_K7));
2529 match(RegVectMask);
2530 format %{%}
2531 interface(REG_INTER);
2532 %}
2533
2534 // Register Operands
2535 // Integer Register
2536 operand rRegI()
2537 %{
2538 constraint(ALLOC_IN_RC(int_reg));
2539 match(RegI);
2540
2541 match(rax_RegI);
2542 match(rbx_RegI);
2543 match(rcx_RegI);
2544 match(rdx_RegI);
2545 match(rdi_RegI);
2546
2547 format %{ %}
2548 interface(REG_INTER);
2549 %}
2550
2551 // Special Registers
2552 operand rax_RegI()
2553 %{
2554 constraint(ALLOC_IN_RC(int_rax_reg));
2555 match(RegI);
2556 match(rRegI);
2557
2558 format %{ "RAX" %}
2559 interface(REG_INTER);
2560 %}
2561
2562 // Special Registers
2563 operand rbx_RegI()
2564 %{
2565 constraint(ALLOC_IN_RC(int_rbx_reg));
2566 match(RegI);
2567 match(rRegI);
2568
2569 format %{ "RBX" %}
2570 interface(REG_INTER);
2571 %}
2572
2573 operand rcx_RegI()
2574 %{
2575 constraint(ALLOC_IN_RC(int_rcx_reg));
2576 match(RegI);
2577 match(rRegI);
2578
2579 format %{ "RCX" %}
2580 interface(REG_INTER);
2581 %}
2582
2583 operand rdx_RegI()
2584 %{
2585 constraint(ALLOC_IN_RC(int_rdx_reg));
2586 match(RegI);
2587 match(rRegI);
2588
2589 format %{ "RDX" %}
2590 interface(REG_INTER);
2591 %}
2592
2593 operand rdi_RegI()
2594 %{
2595 constraint(ALLOC_IN_RC(int_rdi_reg));
2596 match(RegI);
2597 match(rRegI);
2598
2599 format %{ "RDI" %}
2600 interface(REG_INTER);
2601 %}
2602
2603 operand no_rax_rdx_RegI()
2604 %{
2605 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
2606 match(RegI);
2607 match(rbx_RegI);
2608 match(rcx_RegI);
2609 match(rdi_RegI);
2610
2611 format %{ %}
2612 interface(REG_INTER);
2613 %}
2614
2615 operand no_rbp_r13_RegI()
2616 %{
2617 constraint(ALLOC_IN_RC(int_no_rbp_r13_reg));
2618 match(RegI);
2619 match(rRegI);
2620 match(rax_RegI);
2621 match(rbx_RegI);
2622 match(rcx_RegI);
2623 match(rdx_RegI);
2624 match(rdi_RegI);
2625
2626 format %{ %}
2627 interface(REG_INTER);
2628 %}
2629
2630 // Pointer Register
2631 operand any_RegP()
2632 %{
2633 constraint(ALLOC_IN_RC(any_reg));
2634 match(RegP);
2635 match(rax_RegP);
2636 match(rbx_RegP);
2637 match(rdi_RegP);
2638 match(rsi_RegP);
2639 match(rbp_RegP);
2640 match(r15_RegP);
2641 match(rRegP);
2642
2643 format %{ %}
2644 interface(REG_INTER);
2645 %}
2646
2647 operand rRegP()
2648 %{
2649 constraint(ALLOC_IN_RC(ptr_reg));
2650 match(RegP);
2651 match(rax_RegP);
2652 match(rbx_RegP);
2653 match(rdi_RegP);
2654 match(rsi_RegP);
2655 match(rbp_RegP); // See Q&A below about
2656 match(r15_RegP); // r15_RegP and rbp_RegP.
2657
2658 format %{ %}
2659 interface(REG_INTER);
2660 %}
2661
2662 operand rRegN() %{
2663 constraint(ALLOC_IN_RC(int_reg));
2664 match(RegN);
2665
2666 format %{ %}
2667 interface(REG_INTER);
2668 %}
2669
2670 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
2671 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
2672 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
2673 // The output of an instruction is controlled by the allocator, which respects
2674 // register class masks, not match rules. Unless an instruction mentions
2675 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
2676 // by the allocator as an input.
2677 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
2678 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
2679 // result, RBP is not included in the output of the instruction either.
2680
2681 operand no_rax_RegP()
2682 %{
2683 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
2684 match(RegP);
2685 match(rbx_RegP);
2686 match(rsi_RegP);
2687 match(rdi_RegP);
2688
2689 format %{ %}
2690 interface(REG_INTER);
2691 %}
2692
2693 // This operand is not allowed to use RBP even if
2694 // RBP is not used to hold the frame pointer.
2695 operand no_rbp_RegP()
2696 %{
2697 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
2698 match(RegP);
2699 match(rbx_RegP);
2700 match(rsi_RegP);
2701 match(rdi_RegP);
2702
2703 format %{ %}
2704 interface(REG_INTER);
2705 %}
2706
2707 operand no_rax_rbx_RegP()
2708 %{
2709 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
2710 match(RegP);
2711 match(rsi_RegP);
2712 match(rdi_RegP);
2713
2714 format %{ %}
2715 interface(REG_INTER);
2716 %}
2717
2718 // Special Registers
2719 // Return a pointer value
2720 operand rax_RegP()
2721 %{
2722 constraint(ALLOC_IN_RC(ptr_rax_reg));
2723 match(RegP);
2724 match(rRegP);
2725
2726 format %{ %}
2727 interface(REG_INTER);
2728 %}
2729
2730 // Special Registers
2731 // Return a compressed pointer value
2732 operand rax_RegN()
2733 %{
2734 constraint(ALLOC_IN_RC(int_rax_reg));
2735 match(RegN);
2736 match(rRegN);
2737
2738 format %{ %}
2739 interface(REG_INTER);
2740 %}
2741
2742 // Used in AtomicAdd
2743 operand rbx_RegP()
2744 %{
2745 constraint(ALLOC_IN_RC(ptr_rbx_reg));
2746 match(RegP);
2747 match(rRegP);
2748
2749 format %{ %}
2750 interface(REG_INTER);
2751 %}
2752
2753 operand rsi_RegP()
2754 %{
2755 constraint(ALLOC_IN_RC(ptr_rsi_reg));
2756 match(RegP);
2757 match(rRegP);
2758
2759 format %{ %}
2760 interface(REG_INTER);
2761 %}
2762
2763 operand rbp_RegP()
2764 %{
2765 constraint(ALLOC_IN_RC(ptr_rbp_reg));
2766 match(RegP);
2767 match(rRegP);
2768
2769 format %{ %}
2770 interface(REG_INTER);
2771 %}
2772
2773 // Used in rep stosq
2774 operand rdi_RegP()
2775 %{
2776 constraint(ALLOC_IN_RC(ptr_rdi_reg));
2777 match(RegP);
2778 match(rRegP);
2779
2780 format %{ %}
2781 interface(REG_INTER);
2782 %}
2783
2784 operand r15_RegP()
2785 %{
2786 constraint(ALLOC_IN_RC(ptr_r15_reg));
2787 match(RegP);
2788 match(rRegP);
2789
2790 format %{ %}
2791 interface(REG_INTER);
2792 %}
2793
2794 operand rRegL()
2795 %{
2796 constraint(ALLOC_IN_RC(long_reg));
2797 match(RegL);
2798 match(rax_RegL);
2799 match(rdx_RegL);
2800
2801 format %{ %}
2802 interface(REG_INTER);
2803 %}
2804
2805 // Special Registers
2806 operand no_rax_rdx_RegL()
2807 %{
2808 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
2809 match(RegL);
2810 match(rRegL);
2811
2812 format %{ %}
2813 interface(REG_INTER);
2814 %}
2815
2816 operand rax_RegL()
2817 %{
2818 constraint(ALLOC_IN_RC(long_rax_reg));
2819 match(RegL);
2820 match(rRegL);
2821
2822 format %{ "RAX" %}
2823 interface(REG_INTER);
2824 %}
2825
2826 operand rcx_RegL()
2827 %{
2828 constraint(ALLOC_IN_RC(long_rcx_reg));
2829 match(RegL);
2830 match(rRegL);
2831
2832 format %{ %}
2833 interface(REG_INTER);
2834 %}
2835
2836 operand rdx_RegL()
2837 %{
2838 constraint(ALLOC_IN_RC(long_rdx_reg));
2839 match(RegL);
2840 match(rRegL);
2841
2842 format %{ %}
2843 interface(REG_INTER);
2844 %}
2845
2846 operand no_rbp_r13_RegL()
2847 %{
2848 constraint(ALLOC_IN_RC(long_no_rbp_r13_reg));
2849 match(RegL);
2850 match(rRegL);
2851 match(rax_RegL);
2852 match(rcx_RegL);
2853 match(rdx_RegL);
2854
2855 format %{ %}
2856 interface(REG_INTER);
2857 %}
2858
2859 // Flags register, used as output of compare instructions
2860 operand rFlagsReg()
2861 %{
2862 constraint(ALLOC_IN_RC(int_flags));
2863 match(RegFlags);
2864
2865 format %{ "RFLAGS" %}
2866 interface(REG_INTER);
2867 %}
2868
2869 // Flags register, used as output of FLOATING POINT compare instructions
2870 operand rFlagsRegU()
2871 %{
2872 constraint(ALLOC_IN_RC(int_flags));
2873 match(RegFlags);
2874
2875 format %{ "RFLAGS_U" %}
2876 interface(REG_INTER);
2877 %}
2878
2879 operand rFlagsRegUCF() %{
2880 constraint(ALLOC_IN_RC(int_flags));
2881 match(RegFlags);
2882 predicate(false);
2883
2884 format %{ "RFLAGS_U_CF" %}
2885 interface(REG_INTER);
2886 %}
2887
2888 // Float register operands
2889 operand regF() %{
2890 constraint(ALLOC_IN_RC(float_reg));
2891 match(RegF);
2892
2893 format %{ %}
2894 interface(REG_INTER);
2895 %}
2896
2897 // Float register operands
2898 operand legRegF() %{
2899 constraint(ALLOC_IN_RC(float_reg_legacy));
2900 match(RegF);
2901
2902 format %{ %}
2903 interface(REG_INTER);
2904 %}
2905
2906 // Float register operands
2907 operand vlRegF() %{
2908 constraint(ALLOC_IN_RC(float_reg_vl));
2909 match(RegF);
2910
2911 format %{ %}
2912 interface(REG_INTER);
2913 %}
2914
2915 // Double register operands
2916 operand regD() %{
2917 constraint(ALLOC_IN_RC(double_reg));
2918 match(RegD);
2919
2920 format %{ %}
2921 interface(REG_INTER);
2922 %}
2923
2924 // Double register operands
2925 operand legRegD() %{
2926 constraint(ALLOC_IN_RC(double_reg_legacy));
2927 match(RegD);
2928
2929 format %{ %}
2930 interface(REG_INTER);
2931 %}
2932
2933 // Double register operands
2934 operand vlRegD() %{
2935 constraint(ALLOC_IN_RC(double_reg_vl));
2936 match(RegD);
2937
2938 format %{ %}
2939 interface(REG_INTER);
2940 %}
2941
2942 //----------Memory Operands----------------------------------------------------
2943 // Direct Memory Operand
2944 // operand direct(immP addr)
2945 // %{
2946 // match(addr);
2947
2948 // format %{ "[$addr]" %}
2949 // interface(MEMORY_INTER) %{
2950 // base(0xFFFFFFFF);
2951 // index(0x4);
2952 // scale(0x0);
2953 // disp($addr);
2954 // %}
2955 // %}
2956
2957 // Indirect Memory Operand
2958 operand indirect(any_RegP reg)
2959 %{
2960 constraint(ALLOC_IN_RC(ptr_reg));
2961 match(reg);
2962
2963 format %{ "[$reg]" %}
2964 interface(MEMORY_INTER) %{
2965 base($reg);
2966 index(0x4);
2967 scale(0x0);
2968 disp(0x0);
2969 %}
2970 %}
2971
2972 // Indirect Memory Plus Short Offset Operand
2973 operand indOffset8(any_RegP reg, immL8 off)
2974 %{
2975 constraint(ALLOC_IN_RC(ptr_reg));
2976 match(AddP reg off);
2977
2978 format %{ "[$reg + $off (8-bit)]" %}
2979 interface(MEMORY_INTER) %{
2980 base($reg);
2981 index(0x4);
2982 scale(0x0);
2983 disp($off);
2984 %}
2985 %}
2986
2987 // Indirect Memory Plus Long Offset Operand
2988 operand indOffset32(any_RegP reg, immL32 off)
2989 %{
2990 constraint(ALLOC_IN_RC(ptr_reg));
2991 match(AddP reg off);
2992
2993 format %{ "[$reg + $off (32-bit)]" %}
2994 interface(MEMORY_INTER) %{
2995 base($reg);
2996 index(0x4);
2997 scale(0x0);
2998 disp($off);
2999 %}
3000 %}
3001
3002 // Indirect Memory Plus Index Register Plus Offset Operand
3003 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3004 %{
3005 constraint(ALLOC_IN_RC(ptr_reg));
3006 match(AddP (AddP reg lreg) off);
3007
3008 op_cost(10);
3009 format %{"[$reg + $off + $lreg]" %}
3010 interface(MEMORY_INTER) %{
3011 base($reg);
3012 index($lreg);
3013 scale(0x0);
3014 disp($off);
3015 %}
3016 %}
3017
3018 // Indirect Memory Plus Index Register Plus Offset Operand
3019 operand indIndex(any_RegP reg, rRegL lreg)
3020 %{
3021 constraint(ALLOC_IN_RC(ptr_reg));
3022 match(AddP reg lreg);
3023
3024 op_cost(10);
3025 format %{"[$reg + $lreg]" %}
3026 interface(MEMORY_INTER) %{
3027 base($reg);
3028 index($lreg);
3029 scale(0x0);
3030 disp(0x0);
3031 %}
3032 %}
3033
3034 // Indirect Memory Times Scale Plus Index Register
3035 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3036 %{
3037 constraint(ALLOC_IN_RC(ptr_reg));
3038 match(AddP reg (LShiftL lreg scale));
3039
3040 op_cost(10);
3041 format %{"[$reg + $lreg << $scale]" %}
3042 interface(MEMORY_INTER) %{
3043 base($reg);
3044 index($lreg);
3045 scale($scale);
3046 disp(0x0);
3047 %}
3048 %}
3049
3050 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3051 %{
3052 constraint(ALLOC_IN_RC(ptr_reg));
3053 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3054 match(AddP reg (LShiftL (ConvI2L idx) scale));
3055
3056 op_cost(10);
3057 format %{"[$reg + pos $idx << $scale]" %}
3058 interface(MEMORY_INTER) %{
3059 base($reg);
3060 index($idx);
3061 scale($scale);
3062 disp(0x0);
3063 %}
3064 %}
3065
3066 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3067 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3068 %{
3069 constraint(ALLOC_IN_RC(ptr_reg));
3070 match(AddP (AddP reg (LShiftL lreg scale)) off);
3071
3072 op_cost(10);
3073 format %{"[$reg + $off + $lreg << $scale]" %}
3074 interface(MEMORY_INTER) %{
3075 base($reg);
3076 index($lreg);
3077 scale($scale);
3078 disp($off);
3079 %}
3080 %}
3081
3082 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3083 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3084 %{
3085 constraint(ALLOC_IN_RC(ptr_reg));
3086 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3087 match(AddP (AddP reg (ConvI2L idx)) off);
3088
3089 op_cost(10);
3090 format %{"[$reg + $off + $idx]" %}
3091 interface(MEMORY_INTER) %{
3092 base($reg);
3093 index($idx);
3094 scale(0x0);
3095 disp($off);
3096 %}
3097 %}
3098
3099 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3100 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3101 %{
3102 constraint(ALLOC_IN_RC(ptr_reg));
3103 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3104 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3105
3106 op_cost(10);
3107 format %{"[$reg + $off + $idx << $scale]" %}
3108 interface(MEMORY_INTER) %{
3109 base($reg);
3110 index($idx);
3111 scale($scale);
3112 disp($off);
3113 %}
3114 %}
3115
3116 // Indirect Narrow Oop Operand
3117 operand indCompressedOop(rRegN reg) %{
3118 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3119 constraint(ALLOC_IN_RC(ptr_reg));
3120 match(DecodeN reg);
3121
3122 op_cost(10);
3123 format %{"[R12 + $reg << 3] (compressed oop addressing)" %}
3124 interface(MEMORY_INTER) %{
3125 base(0xc); // R12
3126 index($reg);
3127 scale(0x3);
3128 disp(0x0);
3129 %}
3130 %}
3131
3132 // Indirect Narrow Oop Plus Offset Operand
3133 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3134 // we can't free r12 even with CompressedOops::base() == nullptr.
3135 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3136 predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
3137 constraint(ALLOC_IN_RC(ptr_reg));
3138 match(AddP (DecodeN reg) off);
3139
3140 op_cost(10);
3141 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3142 interface(MEMORY_INTER) %{
3143 base(0xc); // R12
3144 index($reg);
3145 scale(0x3);
3146 disp($off);
3147 %}
3148 %}
3149
3150 // Indirect Memory Operand
3151 operand indirectNarrow(rRegN reg)
3152 %{
3153 predicate(CompressedOops::shift() == 0);
3154 constraint(ALLOC_IN_RC(ptr_reg));
3155 match(DecodeN reg);
3156
3157 format %{ "[$reg]" %}
3158 interface(MEMORY_INTER) %{
3159 base($reg);
3160 index(0x4);
3161 scale(0x0);
3162 disp(0x0);
3163 %}
3164 %}
3165
3166 // Indirect Memory Plus Short Offset Operand
3167 operand indOffset8Narrow(rRegN reg, immL8 off)
3168 %{
3169 predicate(CompressedOops::shift() == 0);
3170 constraint(ALLOC_IN_RC(ptr_reg));
3171 match(AddP (DecodeN reg) off);
3172
3173 format %{ "[$reg + $off (8-bit)]" %}
3174 interface(MEMORY_INTER) %{
3175 base($reg);
3176 index(0x4);
3177 scale(0x0);
3178 disp($off);
3179 %}
3180 %}
3181
3182 // Indirect Memory Plus Long Offset Operand
3183 operand indOffset32Narrow(rRegN reg, immL32 off)
3184 %{
3185 predicate(CompressedOops::shift() == 0);
3186 constraint(ALLOC_IN_RC(ptr_reg));
3187 match(AddP (DecodeN reg) off);
3188
3189 format %{ "[$reg + $off (32-bit)]" %}
3190 interface(MEMORY_INTER) %{
3191 base($reg);
3192 index(0x4);
3193 scale(0x0);
3194 disp($off);
3195 %}
3196 %}
3197
3198 // Indirect Memory Plus Index Register Plus Offset Operand
3199 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3200 %{
3201 predicate(CompressedOops::shift() == 0);
3202 constraint(ALLOC_IN_RC(ptr_reg));
3203 match(AddP (AddP (DecodeN reg) lreg) off);
3204
3205 op_cost(10);
3206 format %{"[$reg + $off + $lreg]" %}
3207 interface(MEMORY_INTER) %{
3208 base($reg);
3209 index($lreg);
3210 scale(0x0);
3211 disp($off);
3212 %}
3213 %}
3214
3215 // Indirect Memory Plus Index Register Plus Offset Operand
3216 operand indIndexNarrow(rRegN reg, rRegL lreg)
3217 %{
3218 predicate(CompressedOops::shift() == 0);
3219 constraint(ALLOC_IN_RC(ptr_reg));
3220 match(AddP (DecodeN reg) lreg);
3221
3222 op_cost(10);
3223 format %{"[$reg + $lreg]" %}
3224 interface(MEMORY_INTER) %{
3225 base($reg);
3226 index($lreg);
3227 scale(0x0);
3228 disp(0x0);
3229 %}
3230 %}
3231
3232 // Indirect Memory Times Scale Plus Index Register
3233 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3234 %{
3235 predicate(CompressedOops::shift() == 0);
3236 constraint(ALLOC_IN_RC(ptr_reg));
3237 match(AddP (DecodeN reg) (LShiftL lreg scale));
3238
3239 op_cost(10);
3240 format %{"[$reg + $lreg << $scale]" %}
3241 interface(MEMORY_INTER) %{
3242 base($reg);
3243 index($lreg);
3244 scale($scale);
3245 disp(0x0);
3246 %}
3247 %}
3248
3249 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3250 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3251 %{
3252 predicate(CompressedOops::shift() == 0);
3253 constraint(ALLOC_IN_RC(ptr_reg));
3254 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3255
3256 op_cost(10);
3257 format %{"[$reg + $off + $lreg << $scale]" %}
3258 interface(MEMORY_INTER) %{
3259 base($reg);
3260 index($lreg);
3261 scale($scale);
3262 disp($off);
3263 %}
3264 %}
3265
3266 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3267 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3268 %{
3269 constraint(ALLOC_IN_RC(ptr_reg));
3270 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3271 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3272
3273 op_cost(10);
3274 format %{"[$reg + $off + $idx]" %}
3275 interface(MEMORY_INTER) %{
3276 base($reg);
3277 index($idx);
3278 scale(0x0);
3279 disp($off);
3280 %}
3281 %}
3282
3283 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3284 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3285 %{
3286 constraint(ALLOC_IN_RC(ptr_reg));
3287 predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3288 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3289
3290 op_cost(10);
3291 format %{"[$reg + $off + $idx << $scale]" %}
3292 interface(MEMORY_INTER) %{
3293 base($reg);
3294 index($idx);
3295 scale($scale);
3296 disp($off);
3297 %}
3298 %}
3299
3300 //----------Special Memory Operands--------------------------------------------
3301 // Stack Slot Operand - This operand is used for loading and storing temporary
3302 // values on the stack where a match requires a value to
3303 // flow through memory.
3304 operand stackSlotP(sRegP reg)
3305 %{
3306 constraint(ALLOC_IN_RC(stack_slots));
3307 // No match rule because this operand is only generated in matching
3308
3309 format %{ "[$reg]" %}
3310 interface(MEMORY_INTER) %{
3311 base(0x4); // RSP
3312 index(0x4); // No Index
3313 scale(0x0); // No Scale
3314 disp($reg); // Stack Offset
3315 %}
3316 %}
3317
3318 operand stackSlotI(sRegI reg)
3319 %{
3320 constraint(ALLOC_IN_RC(stack_slots));
3321 // No match rule because this operand is only generated in matching
3322
3323 format %{ "[$reg]" %}
3324 interface(MEMORY_INTER) %{
3325 base(0x4); // RSP
3326 index(0x4); // No Index
3327 scale(0x0); // No Scale
3328 disp($reg); // Stack Offset
3329 %}
3330 %}
3331
3332 operand stackSlotF(sRegF reg)
3333 %{
3334 constraint(ALLOC_IN_RC(stack_slots));
3335 // No match rule because this operand is only generated in matching
3336
3337 format %{ "[$reg]" %}
3338 interface(MEMORY_INTER) %{
3339 base(0x4); // RSP
3340 index(0x4); // No Index
3341 scale(0x0); // No Scale
3342 disp($reg); // Stack Offset
3343 %}
3344 %}
3345
3346 operand stackSlotD(sRegD reg)
3347 %{
3348 constraint(ALLOC_IN_RC(stack_slots));
3349 // No match rule because this operand is only generated in matching
3350
3351 format %{ "[$reg]" %}
3352 interface(MEMORY_INTER) %{
3353 base(0x4); // RSP
3354 index(0x4); // No Index
3355 scale(0x0); // No Scale
3356 disp($reg); // Stack Offset
3357 %}
3358 %}
3359 operand stackSlotL(sRegL reg)
3360 %{
3361 constraint(ALLOC_IN_RC(stack_slots));
3362 // No match rule because this operand is only generated in matching
3363
3364 format %{ "[$reg]" %}
3365 interface(MEMORY_INTER) %{
3366 base(0x4); // RSP
3367 index(0x4); // No Index
3368 scale(0x0); // No Scale
3369 disp($reg); // Stack Offset
3370 %}
3371 %}
3372
3373 //----------Conditional Branch Operands----------------------------------------
3374 // Comparison Op - This is the operation of the comparison, and is limited to
3375 // the following set of codes:
3376 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
3377 //
3378 // Other attributes of the comparison, such as unsignedness, are specified
3379 // by the comparison instruction that sets a condition code flags register.
3380 // That result is represented by a flags operand whose subtype is appropriate
3381 // to the unsignedness (etc.) of the comparison.
3382 //
3383 // Later, the instruction which matches both the Comparison Op (a Bool) and
3384 // the flags (produced by the Cmp) specifies the coding of the comparison op
3385 // by matching a specific subtype of Bool operand below, such as cmpOpU.
3386
3387 // Comparison Code
3388 operand cmpOp()
3389 %{
3390 match(Bool);
3391
3392 format %{ "" %}
3393 interface(COND_INTER) %{
3394 equal(0x4, "e");
3395 not_equal(0x5, "ne");
3396 less(0xC, "l");
3397 greater_equal(0xD, "ge");
3398 less_equal(0xE, "le");
3399 greater(0xF, "g");
3400 overflow(0x0, "o");
3401 no_overflow(0x1, "no");
3402 %}
3403 %}
3404
3405 // Comparison Code, unsigned compare. Used by FP also, with
3406 // C2 (unordered) turned into GT or LT already. The other bits
3407 // C0 and C3 are turned into Carry & Zero flags.
3408 operand cmpOpU()
3409 %{
3410 match(Bool);
3411
3412 format %{ "" %}
3413 interface(COND_INTER) %{
3414 equal(0x4, "e");
3415 not_equal(0x5, "ne");
3416 less(0x2, "b");
3417 greater_equal(0x3, "ae");
3418 less_equal(0x6, "be");
3419 greater(0x7, "a");
3420 overflow(0x0, "o");
3421 no_overflow(0x1, "no");
3422 %}
3423 %}
3424
3425
3426 // Floating comparisons that don't require any fixup for the unordered case,
3427 // If both inputs of the comparison are the same, ZF is always set so we
3428 // don't need to use cmpOpUCF2 for eq/ne
3429 operand cmpOpUCF() %{
3430 match(Bool);
3431 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
3432 n->as_Bool()->_test._test == BoolTest::ge ||
3433 n->as_Bool()->_test._test == BoolTest::le ||
3434 n->as_Bool()->_test._test == BoolTest::gt ||
3435 n->in(1)->in(1) == n->in(1)->in(2));
3436 format %{ "" %}
3437 interface(COND_INTER) %{
3438 equal(0xb, "np");
3439 not_equal(0xa, "p");
3440 less(0x2, "b");
3441 greater_equal(0x3, "ae");
3442 less_equal(0x6, "be");
3443 greater(0x7, "a");
3444 overflow(0x0, "o");
3445 no_overflow(0x1, "no");
3446 %}
3447 %}
3448
3449
3450 // Floating comparisons that can be fixed up with extra conditional jumps
3451 operand cmpOpUCF2() %{
3452 match(Bool);
3453 predicate((n->as_Bool()->_test._test == BoolTest::ne ||
3454 n->as_Bool()->_test._test == BoolTest::eq) &&
3455 n->in(1)->in(1) != n->in(1)->in(2));
3456 format %{ "" %}
3457 interface(COND_INTER) %{
3458 equal(0x4, "e");
3459 not_equal(0x5, "ne");
3460 less(0x2, "b");
3461 greater_equal(0x3, "ae");
3462 less_equal(0x6, "be");
3463 greater(0x7, "a");
3464 overflow(0x0, "o");
3465 no_overflow(0x1, "no");
3466 %}
3467 %}
3468
3469 //----------OPERAND CLASSES----------------------------------------------------
3470 // Operand Classes are groups of operands that are used as to simplify
3471 // instruction definitions by not requiring the AD writer to specify separate
3472 // instructions for every form of operand when the instruction accepts
3473 // multiple operand types with the same basic encoding and format. The classic
3474 // case of this is memory operands.
3475
3476 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
3477 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
3478 indCompressedOop, indCompressedOopOffset,
3479 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
3480 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
3481 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
3482
3483 //----------PIPELINE-----------------------------------------------------------
3484 // Rules which define the behavior of the target architectures pipeline.
3485 pipeline %{
3486
3487 //----------ATTRIBUTES---------------------------------------------------------
3488 attributes %{
3489 variable_size_instructions; // Fixed size instructions
3490 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
3491 instruction_unit_size = 1; // An instruction is 1 bytes long
3492 instruction_fetch_unit_size = 16; // The processor fetches one line
3493 instruction_fetch_units = 1; // of 16 bytes
3494
3495 // List of nop instructions
3496 nops( MachNop );
3497 %}
3498
3499 //----------RESOURCES----------------------------------------------------------
3500 // Resources are the functional units available to the machine
3501
3502 // Generic P2/P3 pipeline
3503 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
3504 // 3 instructions decoded per cycle.
3505 // 2 load/store ops per cycle, 1 branch, 1 FPU,
3506 // 3 ALU op, only ALU0 handles mul instructions.
3507 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
3508 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
3509 BR, FPU,
3510 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
3511
3512 //----------PIPELINE DESCRIPTION-----------------------------------------------
3513 // Pipeline Description specifies the stages in the machine's pipeline
3514
3515 // Generic P2/P3 pipeline
3516 pipe_desc(S0, S1, S2, S3, S4, S5);
3517
3518 //----------PIPELINE CLASSES---------------------------------------------------
3519 // Pipeline Classes describe the stages in which input and output are
3520 // referenced by the hardware pipeline.
3521
3522 // Naming convention: ialu or fpu
3523 // Then: _reg
3524 // Then: _reg if there is a 2nd register
3525 // Then: _long if it's a pair of instructions implementing a long
3526 // Then: _fat if it requires the big decoder
3527 // Or: _mem if it requires the big decoder and a memory unit.
3528
3529 // Integer ALU reg operation
3530 pipe_class ialu_reg(rRegI dst)
3531 %{
3532 single_instruction;
3533 dst : S4(write);
3534 dst : S3(read);
3535 DECODE : S0; // any decoder
3536 ALU : S3; // any alu
3537 %}
3538
3539 // Long ALU reg operation
3540 pipe_class ialu_reg_long(rRegL dst)
3541 %{
3542 instruction_count(2);
3543 dst : S4(write);
3544 dst : S3(read);
3545 DECODE : S0(2); // any 2 decoders
3546 ALU : S3(2); // both alus
3547 %}
3548
3549 // Integer ALU reg operation using big decoder
3550 pipe_class ialu_reg_fat(rRegI dst)
3551 %{
3552 single_instruction;
3553 dst : S4(write);
3554 dst : S3(read);
3555 D0 : S0; // big decoder only
3556 ALU : S3; // any alu
3557 %}
3558
3559 // Integer ALU reg-reg operation
3560 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
3561 %{
3562 single_instruction;
3563 dst : S4(write);
3564 src : S3(read);
3565 DECODE : S0; // any decoder
3566 ALU : S3; // any alu
3567 %}
3568
3569 // Integer ALU reg-reg operation
3570 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
3571 %{
3572 single_instruction;
3573 dst : S4(write);
3574 src : S3(read);
3575 D0 : S0; // big decoder only
3576 ALU : S3; // any alu
3577 %}
3578
3579 // Integer ALU reg-mem operation
3580 pipe_class ialu_reg_mem(rRegI dst, memory mem)
3581 %{
3582 single_instruction;
3583 dst : S5(write);
3584 mem : S3(read);
3585 D0 : S0; // big decoder only
3586 ALU : S4; // any alu
3587 MEM : S3; // any mem
3588 %}
3589
3590 // Integer mem operation (prefetch)
3591 pipe_class ialu_mem(memory mem)
3592 %{
3593 single_instruction;
3594 mem : S3(read);
3595 D0 : S0; // big decoder only
3596 MEM : S3; // any mem
3597 %}
3598
3599 // Integer Store to Memory
3600 pipe_class ialu_mem_reg(memory mem, rRegI src)
3601 %{
3602 single_instruction;
3603 mem : S3(read);
3604 src : S5(read);
3605 D0 : S0; // big decoder only
3606 ALU : S4; // any alu
3607 MEM : S3;
3608 %}
3609
3610 // // Long Store to Memory
3611 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
3612 // %{
3613 // instruction_count(2);
3614 // mem : S3(read);
3615 // src : S5(read);
3616 // D0 : S0(2); // big decoder only; twice
3617 // ALU : S4(2); // any 2 alus
3618 // MEM : S3(2); // Both mems
3619 // %}
3620
3621 // Integer Store to Memory
3622 pipe_class ialu_mem_imm(memory mem)
3623 %{
3624 single_instruction;
3625 mem : S3(read);
3626 D0 : S0; // big decoder only
3627 ALU : S4; // any alu
3628 MEM : S3;
3629 %}
3630
3631 // Integer ALU0 reg-reg operation
3632 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
3633 %{
3634 single_instruction;
3635 dst : S4(write);
3636 src : S3(read);
3637 D0 : S0; // Big decoder only
3638 ALU0 : S3; // only alu0
3639 %}
3640
3641 // Integer ALU0 reg-mem operation
3642 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
3643 %{
3644 single_instruction;
3645 dst : S5(write);
3646 mem : S3(read);
3647 D0 : S0; // big decoder only
3648 ALU0 : S4; // ALU0 only
3649 MEM : S3; // any mem
3650 %}
3651
3652 // Integer ALU reg-reg operation
3653 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
3654 %{
3655 single_instruction;
3656 cr : S4(write);
3657 src1 : S3(read);
3658 src2 : S3(read);
3659 DECODE : S0; // any decoder
3660 ALU : S3; // any alu
3661 %}
3662
3663 // Integer ALU reg-imm operation
3664 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
3665 %{
3666 single_instruction;
3667 cr : S4(write);
3668 src1 : S3(read);
3669 DECODE : S0; // any decoder
3670 ALU : S3; // any alu
3671 %}
3672
3673 // Integer ALU reg-mem operation
3674 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
3675 %{
3676 single_instruction;
3677 cr : S4(write);
3678 src1 : S3(read);
3679 src2 : S3(read);
3680 D0 : S0; // big decoder only
3681 ALU : S4; // any alu
3682 MEM : S3;
3683 %}
3684
3685 // Conditional move reg-reg
3686 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
3687 %{
3688 instruction_count(4);
3689 y : S4(read);
3690 q : S3(read);
3691 p : S3(read);
3692 DECODE : S0(4); // any decoder
3693 %}
3694
3695 // Conditional move reg-reg
3696 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
3697 %{
3698 single_instruction;
3699 dst : S4(write);
3700 src : S3(read);
3701 cr : S3(read);
3702 DECODE : S0; // any decoder
3703 %}
3704
3705 // Conditional move reg-mem
3706 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
3707 %{
3708 single_instruction;
3709 dst : S4(write);
3710 src : S3(read);
3711 cr : S3(read);
3712 DECODE : S0; // any decoder
3713 MEM : S3;
3714 %}
3715
3716 // Conditional move reg-reg long
3717 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
3718 %{
3719 single_instruction;
3720 dst : S4(write);
3721 src : S3(read);
3722 cr : S3(read);
3723 DECODE : S0(2); // any 2 decoders
3724 %}
3725
3726 // Float reg-reg operation
3727 pipe_class fpu_reg(regD dst)
3728 %{
3729 instruction_count(2);
3730 dst : S3(read);
3731 DECODE : S0(2); // any 2 decoders
3732 FPU : S3;
3733 %}
3734
3735 // Float reg-reg operation
3736 pipe_class fpu_reg_reg(regD dst, regD src)
3737 %{
3738 instruction_count(2);
3739 dst : S4(write);
3740 src : S3(read);
3741 DECODE : S0(2); // any 2 decoders
3742 FPU : S3;
3743 %}
3744
3745 // Float reg-reg operation
3746 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
3747 %{
3748 instruction_count(3);
3749 dst : S4(write);
3750 src1 : S3(read);
3751 src2 : S3(read);
3752 DECODE : S0(3); // any 3 decoders
3753 FPU : S3(2);
3754 %}
3755
3756 // Float reg-reg operation
3757 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
3758 %{
3759 instruction_count(4);
3760 dst : S4(write);
3761 src1 : S3(read);
3762 src2 : S3(read);
3763 src3 : S3(read);
3764 DECODE : S0(4); // any 3 decoders
3765 FPU : S3(2);
3766 %}
3767
3768 // Float reg-reg operation
3769 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
3770 %{
3771 instruction_count(4);
3772 dst : S4(write);
3773 src1 : S3(read);
3774 src2 : S3(read);
3775 src3 : S3(read);
3776 DECODE : S1(3); // any 3 decoders
3777 D0 : S0; // Big decoder only
3778 FPU : S3(2);
3779 MEM : S3;
3780 %}
3781
3782 // Float reg-mem operation
3783 pipe_class fpu_reg_mem(regD dst, memory mem)
3784 %{
3785 instruction_count(2);
3786 dst : S5(write);
3787 mem : S3(read);
3788 D0 : S0; // big decoder only
3789 DECODE : S1; // any decoder for FPU POP
3790 FPU : S4;
3791 MEM : S3; // any mem
3792 %}
3793
3794 // Float reg-mem operation
3795 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
3796 %{
3797 instruction_count(3);
3798 dst : S5(write);
3799 src1 : S3(read);
3800 mem : S3(read);
3801 D0 : S0; // big decoder only
3802 DECODE : S1(2); // any decoder for FPU POP
3803 FPU : S4;
3804 MEM : S3; // any mem
3805 %}
3806
3807 // Float mem-reg operation
3808 pipe_class fpu_mem_reg(memory mem, regD src)
3809 %{
3810 instruction_count(2);
3811 src : S5(read);
3812 mem : S3(read);
3813 DECODE : S0; // any decoder for FPU PUSH
3814 D0 : S1; // big decoder only
3815 FPU : S4;
3816 MEM : S3; // any mem
3817 %}
3818
3819 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
3820 %{
3821 instruction_count(3);
3822 src1 : S3(read);
3823 src2 : S3(read);
3824 mem : S3(read);
3825 DECODE : S0(2); // any decoder for FPU PUSH
3826 D0 : S1; // big decoder only
3827 FPU : S4;
3828 MEM : S3; // any mem
3829 %}
3830
3831 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
3832 %{
3833 instruction_count(3);
3834 src1 : S3(read);
3835 src2 : S3(read);
3836 mem : S4(read);
3837 DECODE : S0; // any decoder for FPU PUSH
3838 D0 : S0(2); // big decoder only
3839 FPU : S4;
3840 MEM : S3(2); // any mem
3841 %}
3842
3843 pipe_class fpu_mem_mem(memory dst, memory src1)
3844 %{
3845 instruction_count(2);
3846 src1 : S3(read);
3847 dst : S4(read);
3848 D0 : S0(2); // big decoder only
3849 MEM : S3(2); // any mem
3850 %}
3851
3852 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
3853 %{
3854 instruction_count(3);
3855 src1 : S3(read);
3856 src2 : S3(read);
3857 dst : S4(read);
3858 D0 : S0(3); // big decoder only
3859 FPU : S4;
3860 MEM : S3(3); // any mem
3861 %}
3862
3863 pipe_class fpu_mem_reg_con(memory mem, regD src1)
3864 %{
3865 instruction_count(3);
3866 src1 : S4(read);
3867 mem : S4(read);
3868 DECODE : S0; // any decoder for FPU PUSH
3869 D0 : S0(2); // big decoder only
3870 FPU : S4;
3871 MEM : S3(2); // any mem
3872 %}
3873
3874 // Float load constant
3875 pipe_class fpu_reg_con(regD dst)
3876 %{
3877 instruction_count(2);
3878 dst : S5(write);
3879 D0 : S0; // big decoder only for the load
3880 DECODE : S1; // any decoder for FPU POP
3881 FPU : S4;
3882 MEM : S3; // any mem
3883 %}
3884
3885 // Float load constant
3886 pipe_class fpu_reg_reg_con(regD dst, regD src)
3887 %{
3888 instruction_count(3);
3889 dst : S5(write);
3890 src : S3(read);
3891 D0 : S0; // big decoder only for the load
3892 DECODE : S1(2); // any decoder for FPU POP
3893 FPU : S4;
3894 MEM : S3; // any mem
3895 %}
3896
3897 // UnConditional branch
3898 pipe_class pipe_jmp(label labl)
3899 %{
3900 single_instruction;
3901 BR : S3;
3902 %}
3903
3904 // Conditional branch
3905 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
3906 %{
3907 single_instruction;
3908 cr : S1(read);
3909 BR : S3;
3910 %}
3911
3912 // Allocation idiom
3913 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
3914 %{
3915 instruction_count(1); force_serialization;
3916 fixed_latency(6);
3917 heap_ptr : S3(read);
3918 DECODE : S0(3);
3919 D0 : S2;
3920 MEM : S3;
3921 ALU : S3(2);
3922 dst : S5(write);
3923 BR : S5;
3924 %}
3925
3926 // Generic big/slow expanded idiom
3927 pipe_class pipe_slow()
3928 %{
3929 instruction_count(10); multiple_bundles; force_serialization;
3930 fixed_latency(100);
3931 D0 : S0(2);
3932 MEM : S3(2);
3933 %}
3934
3935 // The real do-nothing guy
3936 pipe_class empty()
3937 %{
3938 instruction_count(0);
3939 %}
3940
3941 // Define the class for the Nop node
3942 define
3943 %{
3944 MachNop = empty;
3945 %}
3946
3947 %}
3948
3949 //----------INSTRUCTIONS-------------------------------------------------------
3950 //
3951 // match -- States which machine-independent subtree may be replaced
3952 // by this instruction.
3953 // ins_cost -- The estimated cost of this instruction is used by instruction
3954 // selection to identify a minimum cost tree of machine
3955 // instructions that matches a tree of machine-independent
3956 // instructions.
3957 // format -- A string providing the disassembly for this instruction.
3958 // The value of an instruction's operand may be inserted
3959 // by referring to it with a '$' prefix.
3960 // opcode -- Three instruction opcodes may be provided. These are referred
3961 // to within an encode class as $primary, $secondary, and $tertiary
3962 // rrspectively. The primary opcode is commonly used to
3963 // indicate the type of machine instruction, while secondary
3964 // and tertiary are often used for prefix options or addressing
3965 // modes.
3966 // ins_encode -- A list of encode classes with parameters. The encode class
3967 // name must have been defined in an 'enc_class' specification
3968 // in the encode section of the architecture description.
3969
3970 // Dummy reg-to-reg vector moves. Removed during post-selection cleanup.
3971 // Load Float
3972 instruct MoveF2VL(vlRegF dst, regF src) %{
3973 match(Set dst src);
3974 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
3975 ins_encode %{
3976 ShouldNotReachHere();
3977 %}
3978 ins_pipe( fpu_reg_reg );
3979 %}
3980
3981 // Load Float
3982 instruct MoveF2LEG(legRegF dst, regF src) %{
3983 match(Set dst src);
3984 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
3985 ins_encode %{
3986 ShouldNotReachHere();
3987 %}
3988 ins_pipe( fpu_reg_reg );
3989 %}
3990
3991 // Load Float
3992 instruct MoveVL2F(regF dst, vlRegF src) %{
3993 match(Set dst src);
3994 format %{ "movss $dst,$src\t! load float (4 bytes)" %}
3995 ins_encode %{
3996 ShouldNotReachHere();
3997 %}
3998 ins_pipe( fpu_reg_reg );
3999 %}
4000
4001 // Load Float
4002 instruct MoveLEG2F(regF dst, legRegF src) %{
4003 match(Set dst src);
4004 format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
4005 ins_encode %{
4006 ShouldNotReachHere();
4007 %}
4008 ins_pipe( fpu_reg_reg );
4009 %}
4010
4011 // Load Double
4012 instruct MoveD2VL(vlRegD dst, regD src) %{
4013 match(Set dst src);
4014 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
4015 ins_encode %{
4016 ShouldNotReachHere();
4017 %}
4018 ins_pipe( fpu_reg_reg );
4019 %}
4020
4021 // Load Double
4022 instruct MoveD2LEG(legRegD dst, regD src) %{
4023 match(Set dst src);
4024 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
4025 ins_encode %{
4026 ShouldNotReachHere();
4027 %}
4028 ins_pipe( fpu_reg_reg );
4029 %}
4030
4031 // Load Double
4032 instruct MoveVL2D(regD dst, vlRegD src) %{
4033 match(Set dst src);
4034 format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
4035 ins_encode %{
4036 ShouldNotReachHere();
4037 %}
4038 ins_pipe( fpu_reg_reg );
4039 %}
4040
4041 // Load Double
4042 instruct MoveLEG2D(regD dst, legRegD src) %{
4043 match(Set dst src);
4044 format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
4045 ins_encode %{
4046 ShouldNotReachHere();
4047 %}
4048 ins_pipe( fpu_reg_reg );
4049 %}
4050
4051 //----------Load/Store/Move Instructions---------------------------------------
4052 //----------Load Instructions--------------------------------------------------
4053
4054 // Load Byte (8 bit signed)
4055 instruct loadB(rRegI dst, memory mem)
4056 %{
4057 match(Set dst (LoadB mem));
4058
4059 ins_cost(125);
4060 format %{ "movsbl $dst, $mem\t# byte" %}
4061
4062 ins_encode %{
4063 __ movsbl($dst$$Register, $mem$$Address);
4064 %}
4065
4066 ins_pipe(ialu_reg_mem);
4067 %}
4068
4069 // Load Byte (8 bit signed) into Long Register
4070 instruct loadB2L(rRegL dst, memory mem)
4071 %{
4072 match(Set dst (ConvI2L (LoadB mem)));
4073
4074 ins_cost(125);
4075 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4076
4077 ins_encode %{
4078 __ movsbq($dst$$Register, $mem$$Address);
4079 %}
4080
4081 ins_pipe(ialu_reg_mem);
4082 %}
4083
4084 // Load Unsigned Byte (8 bit UNsigned)
4085 instruct loadUB(rRegI dst, memory mem)
4086 %{
4087 match(Set dst (LoadUB mem));
4088
4089 ins_cost(125);
4090 format %{ "movzbl $dst, $mem\t# ubyte" %}
4091
4092 ins_encode %{
4093 __ movzbl($dst$$Register, $mem$$Address);
4094 %}
4095
4096 ins_pipe(ialu_reg_mem);
4097 %}
4098
4099 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4100 instruct loadUB2L(rRegL dst, memory mem)
4101 %{
4102 match(Set dst (ConvI2L (LoadUB mem)));
4103
4104 ins_cost(125);
4105 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4106
4107 ins_encode %{
4108 __ movzbq($dst$$Register, $mem$$Address);
4109 %}
4110
4111 ins_pipe(ialu_reg_mem);
4112 %}
4113
4114 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4115 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4116 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4117 effect(KILL cr);
4118
4119 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4120 "andl $dst, right_n_bits($mask, 8)" %}
4121 ins_encode %{
4122 Register Rdst = $dst$$Register;
4123 __ movzbq(Rdst, $mem$$Address);
4124 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4125 %}
4126 ins_pipe(ialu_reg_mem);
4127 %}
4128
4129 // Load Short (16 bit signed)
4130 instruct loadS(rRegI dst, memory mem)
4131 %{
4132 match(Set dst (LoadS mem));
4133
4134 ins_cost(125);
4135 format %{ "movswl $dst, $mem\t# short" %}
4136
4137 ins_encode %{
4138 __ movswl($dst$$Register, $mem$$Address);
4139 %}
4140
4141 ins_pipe(ialu_reg_mem);
4142 %}
4143
4144 // Load Short (16 bit signed) to Byte (8 bit signed)
4145 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4146 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4147
4148 ins_cost(125);
4149 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4150 ins_encode %{
4151 __ movsbl($dst$$Register, $mem$$Address);
4152 %}
4153 ins_pipe(ialu_reg_mem);
4154 %}
4155
4156 // Load Short (16 bit signed) into Long Register
4157 instruct loadS2L(rRegL dst, memory mem)
4158 %{
4159 match(Set dst (ConvI2L (LoadS mem)));
4160
4161 ins_cost(125);
4162 format %{ "movswq $dst, $mem\t# short -> long" %}
4163
4164 ins_encode %{
4165 __ movswq($dst$$Register, $mem$$Address);
4166 %}
4167
4168 ins_pipe(ialu_reg_mem);
4169 %}
4170
4171 // Load Unsigned Short/Char (16 bit UNsigned)
4172 instruct loadUS(rRegI dst, memory mem)
4173 %{
4174 match(Set dst (LoadUS mem));
4175
4176 ins_cost(125);
4177 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4178
4179 ins_encode %{
4180 __ movzwl($dst$$Register, $mem$$Address);
4181 %}
4182
4183 ins_pipe(ialu_reg_mem);
4184 %}
4185
4186 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4187 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4188 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4189
4190 ins_cost(125);
4191 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4192 ins_encode %{
4193 __ movsbl($dst$$Register, $mem$$Address);
4194 %}
4195 ins_pipe(ialu_reg_mem);
4196 %}
4197
4198 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4199 instruct loadUS2L(rRegL dst, memory mem)
4200 %{
4201 match(Set dst (ConvI2L (LoadUS mem)));
4202
4203 ins_cost(125);
4204 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4205
4206 ins_encode %{
4207 __ movzwq($dst$$Register, $mem$$Address);
4208 %}
4209
4210 ins_pipe(ialu_reg_mem);
4211 %}
4212
4213 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4214 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4215 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4216
4217 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4218 ins_encode %{
4219 __ movzbq($dst$$Register, $mem$$Address);
4220 %}
4221 ins_pipe(ialu_reg_mem);
4222 %}
4223
4224 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4225 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4226 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4227 effect(KILL cr);
4228
4229 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4230 "andl $dst, right_n_bits($mask, 16)" %}
4231 ins_encode %{
4232 Register Rdst = $dst$$Register;
4233 __ movzwq(Rdst, $mem$$Address);
4234 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4235 %}
4236 ins_pipe(ialu_reg_mem);
4237 %}
4238
4239 // Load Integer
4240 instruct loadI(rRegI dst, memory mem)
4241 %{
4242 match(Set dst (LoadI mem));
4243
4244 ins_cost(125);
4245 format %{ "movl $dst, $mem\t# int" %}
4246
4247 ins_encode %{
4248 __ movl($dst$$Register, $mem$$Address);
4249 %}
4250
4251 ins_pipe(ialu_reg_mem);
4252 %}
4253
4254 // Load Integer (32 bit signed) to Byte (8 bit signed)
4255 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4256 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4257
4258 ins_cost(125);
4259 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4260 ins_encode %{
4261 __ movsbl($dst$$Register, $mem$$Address);
4262 %}
4263 ins_pipe(ialu_reg_mem);
4264 %}
4265
4266 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4267 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4268 match(Set dst (AndI (LoadI mem) mask));
4269
4270 ins_cost(125);
4271 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4272 ins_encode %{
4273 __ movzbl($dst$$Register, $mem$$Address);
4274 %}
4275 ins_pipe(ialu_reg_mem);
4276 %}
4277
4278 // Load Integer (32 bit signed) to Short (16 bit signed)
4279 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4280 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4281
4282 ins_cost(125);
4283 format %{ "movswl $dst, $mem\t# int -> short" %}
4284 ins_encode %{
4285 __ movswl($dst$$Register, $mem$$Address);
4286 %}
4287 ins_pipe(ialu_reg_mem);
4288 %}
4289
4290 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4291 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4292 match(Set dst (AndI (LoadI mem) mask));
4293
4294 ins_cost(125);
4295 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4296 ins_encode %{
4297 __ movzwl($dst$$Register, $mem$$Address);
4298 %}
4299 ins_pipe(ialu_reg_mem);
4300 %}
4301
4302 // Load Integer into Long Register
4303 instruct loadI2L(rRegL dst, memory mem)
4304 %{
4305 match(Set dst (ConvI2L (LoadI mem)));
4306
4307 ins_cost(125);
4308 format %{ "movslq $dst, $mem\t# int -> long" %}
4309
4310 ins_encode %{
4311 __ movslq($dst$$Register, $mem$$Address);
4312 %}
4313
4314 ins_pipe(ialu_reg_mem);
4315 %}
4316
4317 // Load Integer with mask 0xFF into Long Register
4318 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4319 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4320
4321 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4322 ins_encode %{
4323 __ movzbq($dst$$Register, $mem$$Address);
4324 %}
4325 ins_pipe(ialu_reg_mem);
4326 %}
4327
4328 // Load Integer with mask 0xFFFF into Long Register
4329 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4330 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4331
4332 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
4333 ins_encode %{
4334 __ movzwq($dst$$Register, $mem$$Address);
4335 %}
4336 ins_pipe(ialu_reg_mem);
4337 %}
4338
4339 // Load Integer with a 31-bit mask into Long Register
4340 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
4341 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4342 effect(KILL cr);
4343
4344 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
4345 "andl $dst, $mask" %}
4346 ins_encode %{
4347 Register Rdst = $dst$$Register;
4348 __ movl(Rdst, $mem$$Address);
4349 __ andl(Rdst, $mask$$constant);
4350 %}
4351 ins_pipe(ialu_reg_mem);
4352 %}
4353
4354 // Load Unsigned Integer into Long Register
4355 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
4356 %{
4357 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
4358
4359 ins_cost(125);
4360 format %{ "movl $dst, $mem\t# uint -> long" %}
4361
4362 ins_encode %{
4363 __ movl($dst$$Register, $mem$$Address);
4364 %}
4365
4366 ins_pipe(ialu_reg_mem);
4367 %}
4368
4369 // Load Long
4370 instruct loadL(rRegL dst, memory mem)
4371 %{
4372 match(Set dst (LoadL mem));
4373
4374 ins_cost(125);
4375 format %{ "movq $dst, $mem\t# long" %}
4376
4377 ins_encode %{
4378 __ movq($dst$$Register, $mem$$Address);
4379 %}
4380
4381 ins_pipe(ialu_reg_mem); // XXX
4382 %}
4383
4384 // Load Range
4385 instruct loadRange(rRegI dst, memory mem)
4386 %{
4387 match(Set dst (LoadRange mem));
4388
4389 ins_cost(125); // XXX
4390 format %{ "movl $dst, $mem\t# range" %}
4391 ins_encode %{
4392 __ movl($dst$$Register, $mem$$Address);
4393 %}
4394 ins_pipe(ialu_reg_mem);
4395 %}
4396
4397 // Load Pointer
4398 instruct loadP(rRegP dst, memory mem)
4399 %{
4400 match(Set dst (LoadP mem));
4401 predicate(n->as_Load()->barrier_data() == 0);
4402
4403 ins_cost(125); // XXX
4404 format %{ "movq $dst, $mem\t# ptr" %}
4405 ins_encode %{
4406 __ movq($dst$$Register, $mem$$Address);
4407 %}
4408 ins_pipe(ialu_reg_mem); // XXX
4409 %}
4410
4411 // Load Compressed Pointer
4412 instruct loadN(rRegN dst, memory mem)
4413 %{
4414 match(Set dst (LoadN mem));
4415
4416 ins_cost(125); // XXX
4417 format %{ "movl $dst, $mem\t# compressed ptr" %}
4418 ins_encode %{
4419 __ movl($dst$$Register, $mem$$Address);
4420 %}
4421 ins_pipe(ialu_reg_mem); // XXX
4422 %}
4423
4424
4425 // Load Klass Pointer
4426 instruct loadKlass(rRegP dst, memory mem)
4427 %{
4428 match(Set dst (LoadKlass mem));
4429
4430 ins_cost(125); // XXX
4431 format %{ "movq $dst, $mem\t# class" %}
4432 ins_encode %{
4433 __ movq($dst$$Register, $mem$$Address);
4434 %}
4435 ins_pipe(ialu_reg_mem); // XXX
4436 %}
4437
4438 // Load narrow Klass Pointer
4439 instruct loadNKlass(rRegN dst, memory mem)
4440 %{
4441 match(Set dst (LoadNKlass mem));
4442
4443 ins_cost(125); // XXX
4444 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
4445 ins_encode %{
4446 __ movl($dst$$Register, $mem$$Address);
4447 %}
4448 ins_pipe(ialu_reg_mem); // XXX
4449 %}
4450
4451 // Load Float
4452 instruct loadF(regF dst, memory mem)
4453 %{
4454 match(Set dst (LoadF mem));
4455
4456 ins_cost(145); // XXX
4457 format %{ "movss $dst, $mem\t# float" %}
4458 ins_encode %{
4459 __ movflt($dst$$XMMRegister, $mem$$Address);
4460 %}
4461 ins_pipe(pipe_slow); // XXX
4462 %}
4463
4464 // Load Double
4465 instruct loadD_partial(regD dst, memory mem)
4466 %{
4467 predicate(!UseXmmLoadAndClearUpper);
4468 match(Set dst (LoadD mem));
4469
4470 ins_cost(145); // XXX
4471 format %{ "movlpd $dst, $mem\t# double" %}
4472 ins_encode %{
4473 __ movdbl($dst$$XMMRegister, $mem$$Address);
4474 %}
4475 ins_pipe(pipe_slow); // XXX
4476 %}
4477
4478 instruct loadD(regD dst, memory mem)
4479 %{
4480 predicate(UseXmmLoadAndClearUpper);
4481 match(Set dst (LoadD mem));
4482
4483 ins_cost(145); // XXX
4484 format %{ "movsd $dst, $mem\t# double" %}
4485 ins_encode %{
4486 __ movdbl($dst$$XMMRegister, $mem$$Address);
4487 %}
4488 ins_pipe(pipe_slow); // XXX
4489 %}
4490
4491 // max = java.lang.Math.max(float a, float b)
4492 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4493 predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
4494 match(Set dst (MaxF a b));
4495 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4496 format %{ "maxF $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
4497 ins_encode %{
4498 __ vminmax_fp(Op_MaxV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4499 %}
4500 ins_pipe( pipe_slow );
4501 %}
4502
4503 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
4504 predicate(UseAVX > 0 && SuperWord::is_reduction(n));
4505 match(Set dst (MaxF a b));
4506 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
4507
4508 format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
4509 ins_encode %{
4510 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
4511 false /*min*/, true /*single*/);
4512 %}
4513 ins_pipe( pipe_slow );
4514 %}
4515
4516 // max = java.lang.Math.max(double a, double b)
4517 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
4518 predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
4519 match(Set dst (MaxD a b));
4520 effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
4521 format %{ "maxD $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
4522 ins_encode %{
4523 __ vminmax_fp(Op_MaxV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4524 %}
4525 ins_pipe( pipe_slow );
4526 %}
4527
4528 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
4529 predicate(UseAVX > 0 && SuperWord::is_reduction(n));
4530 match(Set dst (MaxD a b));
4531 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
4532
4533 format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
4534 ins_encode %{
4535 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
4536 false /*min*/, false /*single*/);
4537 %}
4538 ins_pipe( pipe_slow );
4539 %}
4540
4541 // min = java.lang.Math.min(float a, float b)
4542 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4543 predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
4544 match(Set dst (MinF a b));
4545 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4546 format %{ "minF $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
4547 ins_encode %{
4548 __ vminmax_fp(Op_MinV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4549 %}
4550 ins_pipe( pipe_slow );
4551 %}
4552
4553 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
4554 predicate(UseAVX > 0 && SuperWord::is_reduction(n));
4555 match(Set dst (MinF a b));
4556 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
4557
4558 format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
4559 ins_encode %{
4560 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
4561 true /*min*/, true /*single*/);
4562 %}
4563 ins_pipe( pipe_slow );
4564 %}
4565
4566 // min = java.lang.Math.min(double a, double b)
4567 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
4568 predicate(UseAVX > 0 && !SuperWord::is_reduction(n));
4569 match(Set dst (MinD a b));
4570 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4571 format %{ "minD $dst, $a, $b \t! using tmp, atmp and btmp as TEMP" %}
4572 ins_encode %{
4573 __ vminmax_fp(Op_MinV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4574 %}
4575 ins_pipe( pipe_slow );
4576 %}
4577
4578 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
4579 predicate(UseAVX > 0 && SuperWord::is_reduction(n));
4580 match(Set dst (MinD a b));
4581 effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
4582
4583 format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
4584 ins_encode %{
4585 emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
4586 true /*min*/, false /*single*/);
4587 %}
4588 ins_pipe( pipe_slow );
4589 %}
4590
4591 // Load Effective Address
4592 instruct leaP8(rRegP dst, indOffset8 mem)
4593 %{
4594 match(Set dst mem);
4595
4596 ins_cost(110); // XXX
4597 format %{ "leaq $dst, $mem\t# ptr 8" %}
4598 ins_encode %{
4599 __ leaq($dst$$Register, $mem$$Address);
4600 %}
4601 ins_pipe(ialu_reg_reg_fat);
4602 %}
4603
4604 instruct leaP32(rRegP dst, indOffset32 mem)
4605 %{
4606 match(Set dst mem);
4607
4608 ins_cost(110);
4609 format %{ "leaq $dst, $mem\t# ptr 32" %}
4610 ins_encode %{
4611 __ leaq($dst$$Register, $mem$$Address);
4612 %}
4613 ins_pipe(ialu_reg_reg_fat);
4614 %}
4615
4616 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
4617 %{
4618 match(Set dst mem);
4619
4620 ins_cost(110);
4621 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
4622 ins_encode %{
4623 __ leaq($dst$$Register, $mem$$Address);
4624 %}
4625 ins_pipe(ialu_reg_reg_fat);
4626 %}
4627
4628 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
4629 %{
4630 match(Set dst mem);
4631
4632 ins_cost(110);
4633 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
4634 ins_encode %{
4635 __ leaq($dst$$Register, $mem$$Address);
4636 %}
4637 ins_pipe(ialu_reg_reg_fat);
4638 %}
4639
4640 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
4641 %{
4642 match(Set dst mem);
4643
4644 ins_cost(110);
4645 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
4646 ins_encode %{
4647 __ leaq($dst$$Register, $mem$$Address);
4648 %}
4649 ins_pipe(ialu_reg_reg_fat);
4650 %}
4651
4652 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
4653 %{
4654 match(Set dst mem);
4655
4656 ins_cost(110);
4657 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
4658 ins_encode %{
4659 __ leaq($dst$$Register, $mem$$Address);
4660 %}
4661 ins_pipe(ialu_reg_reg_fat);
4662 %}
4663
4664 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
4665 %{
4666 match(Set dst mem);
4667
4668 ins_cost(110);
4669 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
4670 ins_encode %{
4671 __ leaq($dst$$Register, $mem$$Address);
4672 %}
4673 ins_pipe(ialu_reg_reg_fat);
4674 %}
4675
4676 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
4677 %{
4678 match(Set dst mem);
4679
4680 ins_cost(110);
4681 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
4682 ins_encode %{
4683 __ leaq($dst$$Register, $mem$$Address);
4684 %}
4685 ins_pipe(ialu_reg_reg_fat);
4686 %}
4687
4688 // Load Effective Address which uses Narrow (32-bits) oop
4689 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
4690 %{
4691 predicate(UseCompressedOops && (CompressedOops::shift() != 0));
4692 match(Set dst mem);
4693
4694 ins_cost(110);
4695 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
4696 ins_encode %{
4697 __ leaq($dst$$Register, $mem$$Address);
4698 %}
4699 ins_pipe(ialu_reg_reg_fat);
4700 %}
4701
4702 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
4703 %{
4704 predicate(CompressedOops::shift() == 0);
4705 match(Set dst mem);
4706
4707 ins_cost(110); // XXX
4708 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
4709 ins_encode %{
4710 __ leaq($dst$$Register, $mem$$Address);
4711 %}
4712 ins_pipe(ialu_reg_reg_fat);
4713 %}
4714
4715 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
4716 %{
4717 predicate(CompressedOops::shift() == 0);
4718 match(Set dst mem);
4719
4720 ins_cost(110);
4721 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
4722 ins_encode %{
4723 __ leaq($dst$$Register, $mem$$Address);
4724 %}
4725 ins_pipe(ialu_reg_reg_fat);
4726 %}
4727
4728 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
4729 %{
4730 predicate(CompressedOops::shift() == 0);
4731 match(Set dst mem);
4732
4733 ins_cost(110);
4734 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
4735 ins_encode %{
4736 __ leaq($dst$$Register, $mem$$Address);
4737 %}
4738 ins_pipe(ialu_reg_reg_fat);
4739 %}
4740
4741 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
4742 %{
4743 predicate(CompressedOops::shift() == 0);
4744 match(Set dst mem);
4745
4746 ins_cost(110);
4747 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
4748 ins_encode %{
4749 __ leaq($dst$$Register, $mem$$Address);
4750 %}
4751 ins_pipe(ialu_reg_reg_fat);
4752 %}
4753
4754 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
4755 %{
4756 predicate(CompressedOops::shift() == 0);
4757 match(Set dst mem);
4758
4759 ins_cost(110);
4760 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
4761 ins_encode %{
4762 __ leaq($dst$$Register, $mem$$Address);
4763 %}
4764 ins_pipe(ialu_reg_reg_fat);
4765 %}
4766
4767 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
4768 %{
4769 predicate(CompressedOops::shift() == 0);
4770 match(Set dst mem);
4771
4772 ins_cost(110);
4773 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
4774 ins_encode %{
4775 __ leaq($dst$$Register, $mem$$Address);
4776 %}
4777 ins_pipe(ialu_reg_reg_fat);
4778 %}
4779
4780 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
4781 %{
4782 predicate(CompressedOops::shift() == 0);
4783 match(Set dst mem);
4784
4785 ins_cost(110);
4786 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
4787 ins_encode %{
4788 __ leaq($dst$$Register, $mem$$Address);
4789 %}
4790 ins_pipe(ialu_reg_reg_fat);
4791 %}
4792
4793 instruct loadConI(rRegI dst, immI src)
4794 %{
4795 match(Set dst src);
4796
4797 format %{ "movl $dst, $src\t# int" %}
4798 ins_encode %{
4799 __ movl($dst$$Register, $src$$constant);
4800 %}
4801 ins_pipe(ialu_reg_fat); // XXX
4802 %}
4803
4804 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
4805 %{
4806 match(Set dst src);
4807 effect(KILL cr);
4808
4809 ins_cost(50);
4810 format %{ "xorl $dst, $dst\t# int" %}
4811 ins_encode %{
4812 __ xorl($dst$$Register, $dst$$Register);
4813 %}
4814 ins_pipe(ialu_reg);
4815 %}
4816
4817 instruct loadConL(rRegL dst, immL src)
4818 %{
4819 match(Set dst src);
4820
4821 ins_cost(150);
4822 format %{ "movq $dst, $src\t# long" %}
4823 ins_encode %{
4824 __ mov64($dst$$Register, $src$$constant);
4825 %}
4826 ins_pipe(ialu_reg);
4827 %}
4828
4829 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
4830 %{
4831 match(Set dst src);
4832 effect(KILL cr);
4833
4834 ins_cost(50);
4835 format %{ "xorl $dst, $dst\t# long" %}
4836 ins_encode %{
4837 __ xorl($dst$$Register, $dst$$Register);
4838 %}
4839 ins_pipe(ialu_reg); // XXX
4840 %}
4841
4842 instruct loadConUL32(rRegL dst, immUL32 src)
4843 %{
4844 match(Set dst src);
4845
4846 ins_cost(60);
4847 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
4848 ins_encode %{
4849 __ movl($dst$$Register, $src$$constant);
4850 %}
4851 ins_pipe(ialu_reg);
4852 %}
4853
4854 instruct loadConL32(rRegL dst, immL32 src)
4855 %{
4856 match(Set dst src);
4857
4858 ins_cost(70);
4859 format %{ "movq $dst, $src\t# long (32-bit)" %}
4860 ins_encode %{
4861 __ movq($dst$$Register, $src$$constant);
4862 %}
4863 ins_pipe(ialu_reg);
4864 %}
4865
4866 instruct loadConP(rRegP dst, immP con) %{
4867 match(Set dst con);
4868
4869 format %{ "movq $dst, $con\t# ptr" %}
4870 ins_encode %{
4871 __ mov64($dst$$Register, $con$$constant, $con->constant_reloc(), RELOC_IMM64);
4872 %}
4873 ins_pipe(ialu_reg_fat); // XXX
4874 %}
4875
4876 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
4877 %{
4878 match(Set dst src);
4879 effect(KILL cr);
4880
4881 ins_cost(50);
4882 format %{ "xorl $dst, $dst\t# ptr" %}
4883 ins_encode %{
4884 __ xorl($dst$$Register, $dst$$Register);
4885 %}
4886 ins_pipe(ialu_reg);
4887 %}
4888
4889 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
4890 %{
4891 match(Set dst src);
4892 effect(KILL cr);
4893
4894 ins_cost(60);
4895 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
4896 ins_encode %{
4897 __ movl($dst$$Register, $src$$constant);
4898 %}
4899 ins_pipe(ialu_reg);
4900 %}
4901
4902 instruct loadConF(regF dst, immF con) %{
4903 match(Set dst con);
4904 ins_cost(125);
4905 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
4906 ins_encode %{
4907 __ movflt($dst$$XMMRegister, $constantaddress($con));
4908 %}
4909 ins_pipe(pipe_slow);
4910 %}
4911
4912 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
4913 match(Set dst src);
4914 effect(KILL cr);
4915 format %{ "xorq $dst, $src\t# compressed null pointer" %}
4916 ins_encode %{
4917 __ xorq($dst$$Register, $dst$$Register);
4918 %}
4919 ins_pipe(ialu_reg);
4920 %}
4921
4922 instruct loadConN(rRegN dst, immN src) %{
4923 match(Set dst src);
4924
4925 ins_cost(125);
4926 format %{ "movl $dst, $src\t# compressed ptr" %}
4927 ins_encode %{
4928 address con = (address)$src$$constant;
4929 if (con == nullptr) {
4930 ShouldNotReachHere();
4931 } else {
4932 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
4933 }
4934 %}
4935 ins_pipe(ialu_reg_fat); // XXX
4936 %}
4937
4938 instruct loadConNKlass(rRegN dst, immNKlass src) %{
4939 match(Set dst src);
4940
4941 ins_cost(125);
4942 format %{ "movl $dst, $src\t# compressed klass ptr" %}
4943 ins_encode %{
4944 address con = (address)$src$$constant;
4945 if (con == nullptr) {
4946 ShouldNotReachHere();
4947 } else {
4948 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
4949 }
4950 %}
4951 ins_pipe(ialu_reg_fat); // XXX
4952 %}
4953
4954 instruct loadConF0(regF dst, immF0 src)
4955 %{
4956 match(Set dst src);
4957 ins_cost(100);
4958
4959 format %{ "xorps $dst, $dst\t# float 0.0" %}
4960 ins_encode %{
4961 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
4962 %}
4963 ins_pipe(pipe_slow);
4964 %}
4965
4966 // Use the same format since predicate() can not be used here.
4967 instruct loadConD(regD dst, immD con) %{
4968 match(Set dst con);
4969 ins_cost(125);
4970 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
4971 ins_encode %{
4972 __ movdbl($dst$$XMMRegister, $constantaddress($con));
4973 %}
4974 ins_pipe(pipe_slow);
4975 %}
4976
4977 instruct loadConD0(regD dst, immD0 src)
4978 %{
4979 match(Set dst src);
4980 ins_cost(100);
4981
4982 format %{ "xorpd $dst, $dst\t# double 0.0" %}
4983 ins_encode %{
4984 __ xorpd($dst$$XMMRegister, $dst$$XMMRegister);
4985 %}
4986 ins_pipe(pipe_slow);
4987 %}
4988
4989 instruct loadSSI(rRegI dst, stackSlotI src)
4990 %{
4991 match(Set dst src);
4992
4993 ins_cost(125);
4994 format %{ "movl $dst, $src\t# int stk" %}
4995 ins_encode %{
4996 __ movl($dst$$Register, $src$$Address);
4997 %}
4998 ins_pipe(ialu_reg_mem);
4999 %}
5000
5001 instruct loadSSL(rRegL dst, stackSlotL src)
5002 %{
5003 match(Set dst src);
5004
5005 ins_cost(125);
5006 format %{ "movq $dst, $src\t# long stk" %}
5007 ins_encode %{
5008 __ movq($dst$$Register, $src$$Address);
5009 %}
5010 ins_pipe(ialu_reg_mem);
5011 %}
5012
5013 instruct loadSSP(rRegP dst, stackSlotP src)
5014 %{
5015 match(Set dst src);
5016
5017 ins_cost(125);
5018 format %{ "movq $dst, $src\t# ptr stk" %}
5019 ins_encode %{
5020 __ movq($dst$$Register, $src$$Address);
5021 %}
5022 ins_pipe(ialu_reg_mem);
5023 %}
5024
5025 instruct loadSSF(regF dst, stackSlotF src)
5026 %{
5027 match(Set dst src);
5028
5029 ins_cost(125);
5030 format %{ "movss $dst, $src\t# float stk" %}
5031 ins_encode %{
5032 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5033 %}
5034 ins_pipe(pipe_slow); // XXX
5035 %}
5036
5037 // Use the same format since predicate() can not be used here.
5038 instruct loadSSD(regD dst, stackSlotD src)
5039 %{
5040 match(Set dst src);
5041
5042 ins_cost(125);
5043 format %{ "movsd $dst, $src\t# double stk" %}
5044 ins_encode %{
5045 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5046 %}
5047 ins_pipe(pipe_slow); // XXX
5048 %}
5049
5050 // Prefetch instructions for allocation.
5051 // Must be safe to execute with invalid address (cannot fault).
5052
5053 instruct prefetchAlloc( memory mem ) %{
5054 predicate(AllocatePrefetchInstr==3);
5055 match(PrefetchAllocation mem);
5056 ins_cost(125);
5057
5058 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5059 ins_encode %{
5060 __ prefetchw($mem$$Address);
5061 %}
5062 ins_pipe(ialu_mem);
5063 %}
5064
5065 instruct prefetchAllocNTA( memory mem ) %{
5066 predicate(AllocatePrefetchInstr==0);
5067 match(PrefetchAllocation mem);
5068 ins_cost(125);
5069
5070 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5071 ins_encode %{
5072 __ prefetchnta($mem$$Address);
5073 %}
5074 ins_pipe(ialu_mem);
5075 %}
5076
5077 instruct prefetchAllocT0( memory mem ) %{
5078 predicate(AllocatePrefetchInstr==1);
5079 match(PrefetchAllocation mem);
5080 ins_cost(125);
5081
5082 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5083 ins_encode %{
5084 __ prefetcht0($mem$$Address);
5085 %}
5086 ins_pipe(ialu_mem);
5087 %}
5088
5089 instruct prefetchAllocT2( memory mem ) %{
5090 predicate(AllocatePrefetchInstr==2);
5091 match(PrefetchAllocation mem);
5092 ins_cost(125);
5093
5094 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5095 ins_encode %{
5096 __ prefetcht2($mem$$Address);
5097 %}
5098 ins_pipe(ialu_mem);
5099 %}
5100
5101 //----------Store Instructions-------------------------------------------------
5102
5103 // Store Byte
5104 instruct storeB(memory mem, rRegI src)
5105 %{
5106 match(Set mem (StoreB mem src));
5107
5108 ins_cost(125); // XXX
5109 format %{ "movb $mem, $src\t# byte" %}
5110 ins_encode %{
5111 __ movb($mem$$Address, $src$$Register);
5112 %}
5113 ins_pipe(ialu_mem_reg);
5114 %}
5115
5116 // Store Char/Short
5117 instruct storeC(memory mem, rRegI src)
5118 %{
5119 match(Set mem (StoreC mem src));
5120
5121 ins_cost(125); // XXX
5122 format %{ "movw $mem, $src\t# char/short" %}
5123 ins_encode %{
5124 __ movw($mem$$Address, $src$$Register);
5125 %}
5126 ins_pipe(ialu_mem_reg);
5127 %}
5128
5129 // Store Integer
5130 instruct storeI(memory mem, rRegI src)
5131 %{
5132 match(Set mem (StoreI mem src));
5133
5134 ins_cost(125); // XXX
5135 format %{ "movl $mem, $src\t# int" %}
5136 ins_encode %{
5137 __ movl($mem$$Address, $src$$Register);
5138 %}
5139 ins_pipe(ialu_mem_reg);
5140 %}
5141
5142 // Store Long
5143 instruct storeL(memory mem, rRegL src)
5144 %{
5145 match(Set mem (StoreL mem src));
5146
5147 ins_cost(125); // XXX
5148 format %{ "movq $mem, $src\t# long" %}
5149 ins_encode %{
5150 __ movq($mem$$Address, $src$$Register);
5151 %}
5152 ins_pipe(ialu_mem_reg); // XXX
5153 %}
5154
5155 // Store Pointer
5156 instruct storeP(memory mem, any_RegP src)
5157 %{
5158 predicate(n->as_Store()->barrier_data() == 0);
5159 match(Set mem (StoreP mem src));
5160
5161 ins_cost(125); // XXX
5162 format %{ "movq $mem, $src\t# ptr" %}
5163 ins_encode %{
5164 __ movq($mem$$Address, $src$$Register);
5165 %}
5166 ins_pipe(ialu_mem_reg);
5167 %}
5168
5169 instruct storeImmP0(memory mem, immP0 zero)
5170 %{
5171 predicate(UseCompressedOops && (CompressedOops::base() == nullptr) && n->as_Store()->barrier_data() == 0);
5172 match(Set mem (StoreP mem zero));
5173
5174 ins_cost(125); // XXX
5175 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5176 ins_encode %{
5177 __ movq($mem$$Address, r12);
5178 %}
5179 ins_pipe(ialu_mem_reg);
5180 %}
5181
5182 // Store Null Pointer, mark word, or other simple pointer constant.
5183 instruct storeImmP(memory mem, immP31 src)
5184 %{
5185 predicate(n->as_Store()->barrier_data() == 0);
5186 match(Set mem (StoreP mem src));
5187
5188 ins_cost(150); // XXX
5189 format %{ "movq $mem, $src\t# ptr" %}
5190 ins_encode %{
5191 __ movq($mem$$Address, $src$$constant);
5192 %}
5193 ins_pipe(ialu_mem_imm);
5194 %}
5195
5196 // Store Compressed Pointer
5197 instruct storeN(memory mem, rRegN src)
5198 %{
5199 match(Set mem (StoreN mem src));
5200
5201 ins_cost(125); // XXX
5202 format %{ "movl $mem, $src\t# compressed ptr" %}
5203 ins_encode %{
5204 __ movl($mem$$Address, $src$$Register);
5205 %}
5206 ins_pipe(ialu_mem_reg);
5207 %}
5208
5209 instruct storeNKlass(memory mem, rRegN src)
5210 %{
5211 match(Set mem (StoreNKlass mem src));
5212
5213 ins_cost(125); // XXX
5214 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5215 ins_encode %{
5216 __ movl($mem$$Address, $src$$Register);
5217 %}
5218 ins_pipe(ialu_mem_reg);
5219 %}
5220
5221 instruct storeImmN0(memory mem, immN0 zero)
5222 %{
5223 predicate(CompressedOops::base() == nullptr);
5224 match(Set mem (StoreN mem zero));
5225
5226 ins_cost(125); // XXX
5227 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5228 ins_encode %{
5229 __ movl($mem$$Address, r12);
5230 %}
5231 ins_pipe(ialu_mem_reg);
5232 %}
5233
5234 instruct storeImmN(memory mem, immN src)
5235 %{
5236 match(Set mem (StoreN mem src));
5237
5238 ins_cost(150); // XXX
5239 format %{ "movl $mem, $src\t# compressed ptr" %}
5240 ins_encode %{
5241 address con = (address)$src$$constant;
5242 if (con == nullptr) {
5243 __ movl($mem$$Address, 0);
5244 } else {
5245 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5246 }
5247 %}
5248 ins_pipe(ialu_mem_imm);
5249 %}
5250
5251 instruct storeImmNKlass(memory mem, immNKlass src)
5252 %{
5253 match(Set mem (StoreNKlass mem src));
5254
5255 ins_cost(150); // XXX
5256 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5257 ins_encode %{
5258 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5259 %}
5260 ins_pipe(ialu_mem_imm);
5261 %}
5262
5263 // Store Integer Immediate
5264 instruct storeImmI0(memory mem, immI_0 zero)
5265 %{
5266 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5267 match(Set mem (StoreI mem zero));
5268
5269 ins_cost(125); // XXX
5270 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5271 ins_encode %{
5272 __ movl($mem$$Address, r12);
5273 %}
5274 ins_pipe(ialu_mem_reg);
5275 %}
5276
5277 instruct storeImmI(memory mem, immI src)
5278 %{
5279 match(Set mem (StoreI mem src));
5280
5281 ins_cost(150);
5282 format %{ "movl $mem, $src\t# int" %}
5283 ins_encode %{
5284 __ movl($mem$$Address, $src$$constant);
5285 %}
5286 ins_pipe(ialu_mem_imm);
5287 %}
5288
5289 // Store Long Immediate
5290 instruct storeImmL0(memory mem, immL0 zero)
5291 %{
5292 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5293 match(Set mem (StoreL mem zero));
5294
5295 ins_cost(125); // XXX
5296 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5297 ins_encode %{
5298 __ movq($mem$$Address, r12);
5299 %}
5300 ins_pipe(ialu_mem_reg);
5301 %}
5302
5303 instruct storeImmL(memory mem, immL32 src)
5304 %{
5305 match(Set mem (StoreL mem src));
5306
5307 ins_cost(150);
5308 format %{ "movq $mem, $src\t# long" %}
5309 ins_encode %{
5310 __ movq($mem$$Address, $src$$constant);
5311 %}
5312 ins_pipe(ialu_mem_imm);
5313 %}
5314
5315 // Store Short/Char Immediate
5316 instruct storeImmC0(memory mem, immI_0 zero)
5317 %{
5318 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5319 match(Set mem (StoreC mem zero));
5320
5321 ins_cost(125); // XXX
5322 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5323 ins_encode %{
5324 __ movw($mem$$Address, r12);
5325 %}
5326 ins_pipe(ialu_mem_reg);
5327 %}
5328
5329 instruct storeImmI16(memory mem, immI16 src)
5330 %{
5331 predicate(UseStoreImmI16);
5332 match(Set mem (StoreC mem src));
5333
5334 ins_cost(150);
5335 format %{ "movw $mem, $src\t# short/char" %}
5336 ins_encode %{
5337 __ movw($mem$$Address, $src$$constant);
5338 %}
5339 ins_pipe(ialu_mem_imm);
5340 %}
5341
5342 // Store Byte Immediate
5343 instruct storeImmB0(memory mem, immI_0 zero)
5344 %{
5345 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5346 match(Set mem (StoreB mem zero));
5347
5348 ins_cost(125); // XXX
5349 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5350 ins_encode %{
5351 __ movb($mem$$Address, r12);
5352 %}
5353 ins_pipe(ialu_mem_reg);
5354 %}
5355
5356 instruct storeImmB(memory mem, immI8 src)
5357 %{
5358 match(Set mem (StoreB mem src));
5359
5360 ins_cost(150); // XXX
5361 format %{ "movb $mem, $src\t# byte" %}
5362 ins_encode %{
5363 __ movb($mem$$Address, $src$$constant);
5364 %}
5365 ins_pipe(ialu_mem_imm);
5366 %}
5367
5368 // Store CMS card-mark Immediate
5369 instruct storeImmCM0_reg(memory mem, immI_0 zero)
5370 %{
5371 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5372 match(Set mem (StoreCM mem zero));
5373
5374 ins_cost(125); // XXX
5375 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5376 ins_encode %{
5377 __ movb($mem$$Address, r12);
5378 %}
5379 ins_pipe(ialu_mem_reg);
5380 %}
5381
5382 instruct storeImmCM0(memory mem, immI_0 src)
5383 %{
5384 match(Set mem (StoreCM mem src));
5385
5386 ins_cost(150); // XXX
5387 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5388 ins_encode %{
5389 __ movb($mem$$Address, $src$$constant);
5390 %}
5391 ins_pipe(ialu_mem_imm);
5392 %}
5393
5394 // Store Float
5395 instruct storeF(memory mem, regF src)
5396 %{
5397 match(Set mem (StoreF mem src));
5398
5399 ins_cost(95); // XXX
5400 format %{ "movss $mem, $src\t# float" %}
5401 ins_encode %{
5402 __ movflt($mem$$Address, $src$$XMMRegister);
5403 %}
5404 ins_pipe(pipe_slow); // XXX
5405 %}
5406
5407 // Store immediate Float value (it is faster than store from XMM register)
5408 instruct storeF0(memory mem, immF0 zero)
5409 %{
5410 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5411 match(Set mem (StoreF mem zero));
5412
5413 ins_cost(25); // XXX
5414 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5415 ins_encode %{
5416 __ movl($mem$$Address, r12);
5417 %}
5418 ins_pipe(ialu_mem_reg);
5419 %}
5420
5421 instruct storeF_imm(memory mem, immF src)
5422 %{
5423 match(Set mem (StoreF mem src));
5424
5425 ins_cost(50);
5426 format %{ "movl $mem, $src\t# float" %}
5427 ins_encode %{
5428 __ movl($mem$$Address, jint_cast($src$$constant));
5429 %}
5430 ins_pipe(ialu_mem_imm);
5431 %}
5432
5433 // Store Double
5434 instruct storeD(memory mem, regD src)
5435 %{
5436 match(Set mem (StoreD mem src));
5437
5438 ins_cost(95); // XXX
5439 format %{ "movsd $mem, $src\t# double" %}
5440 ins_encode %{
5441 __ movdbl($mem$$Address, $src$$XMMRegister);
5442 %}
5443 ins_pipe(pipe_slow); // XXX
5444 %}
5445
5446 // Store immediate double 0.0 (it is faster than store from XMM register)
5447 instruct storeD0_imm(memory mem, immD0 src)
5448 %{
5449 predicate(!UseCompressedOops || (CompressedOops::base() != nullptr));
5450 match(Set mem (StoreD mem src));
5451
5452 ins_cost(50);
5453 format %{ "movq $mem, $src\t# double 0." %}
5454 ins_encode %{
5455 __ movq($mem$$Address, $src$$constant);
5456 %}
5457 ins_pipe(ialu_mem_imm);
5458 %}
5459
5460 instruct storeD0(memory mem, immD0 zero)
5461 %{
5462 predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
5463 match(Set mem (StoreD mem zero));
5464
5465 ins_cost(25); // XXX
5466 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5467 ins_encode %{
5468 __ movq($mem$$Address, r12);
5469 %}
5470 ins_pipe(ialu_mem_reg);
5471 %}
5472
5473 instruct storeSSI(stackSlotI dst, rRegI src)
5474 %{
5475 match(Set dst src);
5476
5477 ins_cost(100);
5478 format %{ "movl $dst, $src\t# int stk" %}
5479 ins_encode %{
5480 __ movl($dst$$Address, $src$$Register);
5481 %}
5482 ins_pipe( ialu_mem_reg );
5483 %}
5484
5485 instruct storeSSL(stackSlotL dst, rRegL src)
5486 %{
5487 match(Set dst src);
5488
5489 ins_cost(100);
5490 format %{ "movq $dst, $src\t# long stk" %}
5491 ins_encode %{
5492 __ movq($dst$$Address, $src$$Register);
5493 %}
5494 ins_pipe(ialu_mem_reg);
5495 %}
5496
5497 instruct storeSSP(stackSlotP dst, rRegP src)
5498 %{
5499 match(Set dst src);
5500
5501 ins_cost(100);
5502 format %{ "movq $dst, $src\t# ptr stk" %}
5503 ins_encode %{
5504 __ movq($dst$$Address, $src$$Register);
5505 %}
5506 ins_pipe(ialu_mem_reg);
5507 %}
5508
5509 instruct storeSSF(stackSlotF dst, regF src)
5510 %{
5511 match(Set dst src);
5512
5513 ins_cost(95); // XXX
5514 format %{ "movss $dst, $src\t# float stk" %}
5515 ins_encode %{
5516 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
5517 %}
5518 ins_pipe(pipe_slow); // XXX
5519 %}
5520
5521 instruct storeSSD(stackSlotD dst, regD src)
5522 %{
5523 match(Set dst src);
5524
5525 ins_cost(95); // XXX
5526 format %{ "movsd $dst, $src\t# double stk" %}
5527 ins_encode %{
5528 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
5529 %}
5530 ins_pipe(pipe_slow); // XXX
5531 %}
5532
5533 instruct cacheWB(indirect addr)
5534 %{
5535 predicate(VM_Version::supports_data_cache_line_flush());
5536 match(CacheWB addr);
5537
5538 ins_cost(100);
5539 format %{"cache wb $addr" %}
5540 ins_encode %{
5541 assert($addr->index_position() < 0, "should be");
5542 assert($addr$$disp == 0, "should be");
5543 __ cache_wb(Address($addr$$base$$Register, 0));
5544 %}
5545 ins_pipe(pipe_slow); // XXX
5546 %}
5547
5548 instruct cacheWBPreSync()
5549 %{
5550 predicate(VM_Version::supports_data_cache_line_flush());
5551 match(CacheWBPreSync);
5552
5553 ins_cost(100);
5554 format %{"cache wb presync" %}
5555 ins_encode %{
5556 __ cache_wbsync(true);
5557 %}
5558 ins_pipe(pipe_slow); // XXX
5559 %}
5560
5561 instruct cacheWBPostSync()
5562 %{
5563 predicate(VM_Version::supports_data_cache_line_flush());
5564 match(CacheWBPostSync);
5565
5566 ins_cost(100);
5567 format %{"cache wb postsync" %}
5568 ins_encode %{
5569 __ cache_wbsync(false);
5570 %}
5571 ins_pipe(pipe_slow); // XXX
5572 %}
5573
5574 //----------BSWAP Instructions-------------------------------------------------
5575 instruct bytes_reverse_int(rRegI dst) %{
5576 match(Set dst (ReverseBytesI dst));
5577
5578 format %{ "bswapl $dst" %}
5579 ins_encode %{
5580 __ bswapl($dst$$Register);
5581 %}
5582 ins_pipe( ialu_reg );
5583 %}
5584
5585 instruct bytes_reverse_long(rRegL dst) %{
5586 match(Set dst (ReverseBytesL dst));
5587
5588 format %{ "bswapq $dst" %}
5589 ins_encode %{
5590 __ bswapq($dst$$Register);
5591 %}
5592 ins_pipe( ialu_reg);
5593 %}
5594
5595 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
5596 match(Set dst (ReverseBytesUS dst));
5597 effect(KILL cr);
5598
5599 format %{ "bswapl $dst\n\t"
5600 "shrl $dst,16\n\t" %}
5601 ins_encode %{
5602 __ bswapl($dst$$Register);
5603 __ shrl($dst$$Register, 16);
5604 %}
5605 ins_pipe( ialu_reg );
5606 %}
5607
5608 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
5609 match(Set dst (ReverseBytesS dst));
5610 effect(KILL cr);
5611
5612 format %{ "bswapl $dst\n\t"
5613 "sar $dst,16\n\t" %}
5614 ins_encode %{
5615 __ bswapl($dst$$Register);
5616 __ sarl($dst$$Register, 16);
5617 %}
5618 ins_pipe( ialu_reg );
5619 %}
5620
5621 //---------- Zeros Count Instructions ------------------------------------------
5622
5623 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5624 predicate(UseCountLeadingZerosInstruction);
5625 match(Set dst (CountLeadingZerosI src));
5626 effect(KILL cr);
5627
5628 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
5629 ins_encode %{
5630 __ lzcntl($dst$$Register, $src$$Register);
5631 %}
5632 ins_pipe(ialu_reg);
5633 %}
5634
5635 instruct countLeadingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
5636 predicate(UseCountLeadingZerosInstruction);
5637 match(Set dst (CountLeadingZerosI (LoadI src)));
5638 effect(KILL cr);
5639 ins_cost(175);
5640 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
5641 ins_encode %{
5642 __ lzcntl($dst$$Register, $src$$Address);
5643 %}
5644 ins_pipe(ialu_reg_mem);
5645 %}
5646
5647 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
5648 predicate(!UseCountLeadingZerosInstruction);
5649 match(Set dst (CountLeadingZerosI src));
5650 effect(KILL cr);
5651
5652 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
5653 "jnz skip\n\t"
5654 "movl $dst, -1\n"
5655 "skip:\n\t"
5656 "negl $dst\n\t"
5657 "addl $dst, 31" %}
5658 ins_encode %{
5659 Register Rdst = $dst$$Register;
5660 Register Rsrc = $src$$Register;
5661 Label skip;
5662 __ bsrl(Rdst, Rsrc);
5663 __ jccb(Assembler::notZero, skip);
5664 __ movl(Rdst, -1);
5665 __ bind(skip);
5666 __ negl(Rdst);
5667 __ addl(Rdst, BitsPerInt - 1);
5668 %}
5669 ins_pipe(ialu_reg);
5670 %}
5671
5672 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5673 predicate(UseCountLeadingZerosInstruction);
5674 match(Set dst (CountLeadingZerosL src));
5675 effect(KILL cr);
5676
5677 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
5678 ins_encode %{
5679 __ lzcntq($dst$$Register, $src$$Register);
5680 %}
5681 ins_pipe(ialu_reg);
5682 %}
5683
5684 instruct countLeadingZerosL_mem(rRegI dst, memory src, rFlagsReg cr) %{
5685 predicate(UseCountLeadingZerosInstruction);
5686 match(Set dst (CountLeadingZerosL (LoadL src)));
5687 effect(KILL cr);
5688 ins_cost(175);
5689 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
5690 ins_encode %{
5691 __ lzcntq($dst$$Register, $src$$Address);
5692 %}
5693 ins_pipe(ialu_reg_mem);
5694 %}
5695
5696 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
5697 predicate(!UseCountLeadingZerosInstruction);
5698 match(Set dst (CountLeadingZerosL src));
5699 effect(KILL cr);
5700
5701 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
5702 "jnz skip\n\t"
5703 "movl $dst, -1\n"
5704 "skip:\n\t"
5705 "negl $dst\n\t"
5706 "addl $dst, 63" %}
5707 ins_encode %{
5708 Register Rdst = $dst$$Register;
5709 Register Rsrc = $src$$Register;
5710 Label skip;
5711 __ bsrq(Rdst, Rsrc);
5712 __ jccb(Assembler::notZero, skip);
5713 __ movl(Rdst, -1);
5714 __ bind(skip);
5715 __ negl(Rdst);
5716 __ addl(Rdst, BitsPerLong - 1);
5717 %}
5718 ins_pipe(ialu_reg);
5719 %}
5720
5721 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
5722 predicate(UseCountTrailingZerosInstruction);
5723 match(Set dst (CountTrailingZerosI src));
5724 effect(KILL cr);
5725
5726 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
5727 ins_encode %{
5728 __ tzcntl($dst$$Register, $src$$Register);
5729 %}
5730 ins_pipe(ialu_reg);
5731 %}
5732
5733 instruct countTrailingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
5734 predicate(UseCountTrailingZerosInstruction);
5735 match(Set dst (CountTrailingZerosI (LoadI src)));
5736 effect(KILL cr);
5737 ins_cost(175);
5738 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
5739 ins_encode %{
5740 __ tzcntl($dst$$Register, $src$$Address);
5741 %}
5742 ins_pipe(ialu_reg_mem);
5743 %}
5744
5745 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
5746 predicate(!UseCountTrailingZerosInstruction);
5747 match(Set dst (CountTrailingZerosI src));
5748 effect(KILL cr);
5749
5750 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
5751 "jnz done\n\t"
5752 "movl $dst, 32\n"
5753 "done:" %}
5754 ins_encode %{
5755 Register Rdst = $dst$$Register;
5756 Label done;
5757 __ bsfl(Rdst, $src$$Register);
5758 __ jccb(Assembler::notZero, done);
5759 __ movl(Rdst, BitsPerInt);
5760 __ bind(done);
5761 %}
5762 ins_pipe(ialu_reg);
5763 %}
5764
5765 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
5766 predicate(UseCountTrailingZerosInstruction);
5767 match(Set dst (CountTrailingZerosL src));
5768 effect(KILL cr);
5769
5770 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
5771 ins_encode %{
5772 __ tzcntq($dst$$Register, $src$$Register);
5773 %}
5774 ins_pipe(ialu_reg);
5775 %}
5776
5777 instruct countTrailingZerosL_mem(rRegI dst, memory src, rFlagsReg cr) %{
5778 predicate(UseCountTrailingZerosInstruction);
5779 match(Set dst (CountTrailingZerosL (LoadL src)));
5780 effect(KILL cr);
5781 ins_cost(175);
5782 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
5783 ins_encode %{
5784 __ tzcntq($dst$$Register, $src$$Address);
5785 %}
5786 ins_pipe(ialu_reg_mem);
5787 %}
5788
5789 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
5790 predicate(!UseCountTrailingZerosInstruction);
5791 match(Set dst (CountTrailingZerosL src));
5792 effect(KILL cr);
5793
5794 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
5795 "jnz done\n\t"
5796 "movl $dst, 64\n"
5797 "done:" %}
5798 ins_encode %{
5799 Register Rdst = $dst$$Register;
5800 Label done;
5801 __ bsfq(Rdst, $src$$Register);
5802 __ jccb(Assembler::notZero, done);
5803 __ movl(Rdst, BitsPerLong);
5804 __ bind(done);
5805 %}
5806 ins_pipe(ialu_reg);
5807 %}
5808
5809 //--------------- Reverse Operation Instructions ----------------
5810 instruct bytes_reversebit_int(rRegI dst, rRegI src, rRegI rtmp, rFlagsReg cr) %{
5811 predicate(!VM_Version::supports_gfni());
5812 match(Set dst (ReverseI src));
5813 effect(TEMP dst, TEMP rtmp, KILL cr);
5814 format %{ "reverse_int $dst $src\t! using $rtmp as TEMP" %}
5815 ins_encode %{
5816 __ reverseI($dst$$Register, $src$$Register, xnoreg, xnoreg, $rtmp$$Register);
5817 %}
5818 ins_pipe( ialu_reg );
5819 %}
5820
5821 instruct bytes_reversebit_int_gfni(rRegI dst, rRegI src, regF xtmp1, regF xtmp2, rRegL rtmp, rFlagsReg cr) %{
5822 predicate(VM_Version::supports_gfni());
5823 match(Set dst (ReverseI src));
5824 effect(TEMP dst, TEMP xtmp1, TEMP xtmp2, TEMP rtmp, KILL cr);
5825 format %{ "reverse_int $dst $src\t! using $rtmp, $xtmp1 and $xtmp2 as TEMP" %}
5826 ins_encode %{
5827 __ reverseI($dst$$Register, $src$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $rtmp$$Register);
5828 %}
5829 ins_pipe( ialu_reg );
5830 %}
5831
5832 instruct bytes_reversebit_long(rRegL dst, rRegL src, rRegL rtmp1, rRegL rtmp2, rFlagsReg cr) %{
5833 predicate(!VM_Version::supports_gfni());
5834 match(Set dst (ReverseL src));
5835 effect(TEMP dst, TEMP rtmp1, TEMP rtmp2, KILL cr);
5836 format %{ "reverse_long $dst $src\t! using $rtmp1 and $rtmp2 as TEMP" %}
5837 ins_encode %{
5838 __ reverseL($dst$$Register, $src$$Register, xnoreg, xnoreg, $rtmp1$$Register, $rtmp2$$Register);
5839 %}
5840 ins_pipe( ialu_reg );
5841 %}
5842
5843 instruct bytes_reversebit_long_gfni(rRegL dst, rRegL src, regD xtmp1, regD xtmp2, rRegL rtmp, rFlagsReg cr) %{
5844 predicate(VM_Version::supports_gfni());
5845 match(Set dst (ReverseL src));
5846 effect(TEMP dst, TEMP xtmp1, TEMP xtmp2, TEMP rtmp, KILL cr);
5847 format %{ "reverse_long $dst $src\t! using $rtmp, $xtmp1 and $xtmp2 as TEMP" %}
5848 ins_encode %{
5849 __ reverseL($dst$$Register, $src$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $rtmp$$Register, noreg);
5850 %}
5851 ins_pipe( ialu_reg );
5852 %}
5853
5854 //---------- Population Count Instructions -------------------------------------
5855
5856 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
5857 predicate(UsePopCountInstruction);
5858 match(Set dst (PopCountI src));
5859 effect(KILL cr);
5860
5861 format %{ "popcnt $dst, $src" %}
5862 ins_encode %{
5863 __ popcntl($dst$$Register, $src$$Register);
5864 %}
5865 ins_pipe(ialu_reg);
5866 %}
5867
5868 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
5869 predicate(UsePopCountInstruction);
5870 match(Set dst (PopCountI (LoadI mem)));
5871 effect(KILL cr);
5872
5873 format %{ "popcnt $dst, $mem" %}
5874 ins_encode %{
5875 __ popcntl($dst$$Register, $mem$$Address);
5876 %}
5877 ins_pipe(ialu_reg);
5878 %}
5879
5880 // Note: Long.bitCount(long) returns an int.
5881 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
5882 predicate(UsePopCountInstruction);
5883 match(Set dst (PopCountL src));
5884 effect(KILL cr);
5885
5886 format %{ "popcnt $dst, $src" %}
5887 ins_encode %{
5888 __ popcntq($dst$$Register, $src$$Register);
5889 %}
5890 ins_pipe(ialu_reg);
5891 %}
5892
5893 // Note: Long.bitCount(long) returns an int.
5894 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
5895 predicate(UsePopCountInstruction);
5896 match(Set dst (PopCountL (LoadL mem)));
5897 effect(KILL cr);
5898
5899 format %{ "popcnt $dst, $mem" %}
5900 ins_encode %{
5901 __ popcntq($dst$$Register, $mem$$Address);
5902 %}
5903 ins_pipe(ialu_reg);
5904 %}
5905
5906
5907 //----------MemBar Instructions-----------------------------------------------
5908 // Memory barrier flavors
5909
5910 instruct membar_acquire()
5911 %{
5912 match(MemBarAcquire);
5913 match(LoadFence);
5914 ins_cost(0);
5915
5916 size(0);
5917 format %{ "MEMBAR-acquire ! (empty encoding)" %}
5918 ins_encode();
5919 ins_pipe(empty);
5920 %}
5921
5922 instruct membar_acquire_lock()
5923 %{
5924 match(MemBarAcquireLock);
5925 ins_cost(0);
5926
5927 size(0);
5928 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
5929 ins_encode();
5930 ins_pipe(empty);
5931 %}
5932
5933 instruct membar_release()
5934 %{
5935 match(MemBarRelease);
5936 match(StoreFence);
5937 ins_cost(0);
5938
5939 size(0);
5940 format %{ "MEMBAR-release ! (empty encoding)" %}
5941 ins_encode();
5942 ins_pipe(empty);
5943 %}
5944
5945 instruct membar_release_lock()
5946 %{
5947 match(MemBarReleaseLock);
5948 ins_cost(0);
5949
5950 size(0);
5951 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
5952 ins_encode();
5953 ins_pipe(empty);
5954 %}
5955
5956 instruct membar_volatile(rFlagsReg cr) %{
5957 match(MemBarVolatile);
5958 effect(KILL cr);
5959 ins_cost(400);
5960
5961 format %{
5962 $$template
5963 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
5964 %}
5965 ins_encode %{
5966 __ membar(Assembler::StoreLoad);
5967 %}
5968 ins_pipe(pipe_slow);
5969 %}
5970
5971 instruct unnecessary_membar_volatile()
5972 %{
5973 match(MemBarVolatile);
5974 predicate(Matcher::post_store_load_barrier(n));
5975 ins_cost(0);
5976
5977 size(0);
5978 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
5979 ins_encode();
5980 ins_pipe(empty);
5981 %}
5982
5983 instruct membar_storestore() %{
5984 match(MemBarStoreStore);
5985 match(StoreStoreFence);
5986 ins_cost(0);
5987
5988 size(0);
5989 format %{ "MEMBAR-storestore (empty encoding)" %}
5990 ins_encode( );
5991 ins_pipe(empty);
5992 %}
5993
5994 //----------Move Instructions--------------------------------------------------
5995
5996 instruct castX2P(rRegP dst, rRegL src)
5997 %{
5998 match(Set dst (CastX2P src));
5999
6000 format %{ "movq $dst, $src\t# long->ptr" %}
6001 ins_encode %{
6002 if ($dst$$reg != $src$$reg) {
6003 __ movptr($dst$$Register, $src$$Register);
6004 }
6005 %}
6006 ins_pipe(ialu_reg_reg); // XXX
6007 %}
6008
6009 instruct castN2X(rRegL dst, rRegN src)
6010 %{
6011 match(Set dst (CastP2X src));
6012
6013 format %{ "movq $dst, $src\t# ptr -> long" %}
6014 ins_encode %{
6015 if ($dst$$reg != $src$$reg) {
6016 __ movptr($dst$$Register, $src$$Register);
6017 }
6018 %}
6019 ins_pipe(ialu_reg_reg); // XXX
6020 %}
6021
6022 instruct castP2X(rRegL dst, rRegP src)
6023 %{
6024 match(Set dst (CastP2X src));
6025
6026 format %{ "movq $dst, $src\t# ptr -> long" %}
6027 ins_encode %{
6028 if ($dst$$reg != $src$$reg) {
6029 __ movptr($dst$$Register, $src$$Register);
6030 }
6031 %}
6032 ins_pipe(ialu_reg_reg); // XXX
6033 %}
6034
6035 // Convert oop into int for vectors alignment masking
6036 instruct convP2I(rRegI dst, rRegP src)
6037 %{
6038 match(Set dst (ConvL2I (CastP2X src)));
6039
6040 format %{ "movl $dst, $src\t# ptr -> int" %}
6041 ins_encode %{
6042 __ movl($dst$$Register, $src$$Register);
6043 %}
6044 ins_pipe(ialu_reg_reg); // XXX
6045 %}
6046
6047 // Convert compressed oop into int for vectors alignment masking
6048 // in case of 32bit oops (heap < 4Gb).
6049 instruct convN2I(rRegI dst, rRegN src)
6050 %{
6051 predicate(CompressedOops::shift() == 0);
6052 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6053
6054 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6055 ins_encode %{
6056 __ movl($dst$$Register, $src$$Register);
6057 %}
6058 ins_pipe(ialu_reg_reg); // XXX
6059 %}
6060
6061 // Convert oop pointer into compressed form
6062 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6063 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6064 match(Set dst (EncodeP src));
6065 effect(KILL cr);
6066 format %{ "encode_heap_oop $dst,$src" %}
6067 ins_encode %{
6068 Register s = $src$$Register;
6069 Register d = $dst$$Register;
6070 if (s != d) {
6071 __ movq(d, s);
6072 }
6073 __ encode_heap_oop(d);
6074 %}
6075 ins_pipe(ialu_reg_long);
6076 %}
6077
6078 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6079 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6080 match(Set dst (EncodeP src));
6081 effect(KILL cr);
6082 format %{ "encode_heap_oop_not_null $dst,$src" %}
6083 ins_encode %{
6084 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6085 %}
6086 ins_pipe(ialu_reg_long);
6087 %}
6088
6089 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6090 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6091 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6092 match(Set dst (DecodeN src));
6093 effect(KILL cr);
6094 format %{ "decode_heap_oop $dst,$src" %}
6095 ins_encode %{
6096 Register s = $src$$Register;
6097 Register d = $dst$$Register;
6098 if (s != d) {
6099 __ movq(d, s);
6100 }
6101 __ decode_heap_oop(d);
6102 %}
6103 ins_pipe(ialu_reg_long);
6104 %}
6105
6106 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6107 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6108 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6109 match(Set dst (DecodeN src));
6110 effect(KILL cr);
6111 format %{ "decode_heap_oop_not_null $dst,$src" %}
6112 ins_encode %{
6113 Register s = $src$$Register;
6114 Register d = $dst$$Register;
6115 if (s != d) {
6116 __ decode_heap_oop_not_null(d, s);
6117 } else {
6118 __ decode_heap_oop_not_null(d);
6119 }
6120 %}
6121 ins_pipe(ialu_reg_long);
6122 %}
6123
6124 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6125 match(Set dst (EncodePKlass src));
6126 effect(TEMP dst, KILL cr);
6127 format %{ "encode_and_move_klass_not_null $dst,$src" %}
6128 ins_encode %{
6129 __ encode_and_move_klass_not_null($dst$$Register, $src$$Register);
6130 %}
6131 ins_pipe(ialu_reg_long);
6132 %}
6133
6134 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6135 match(Set dst (DecodeNKlass src));
6136 effect(TEMP dst, KILL cr);
6137 format %{ "decode_and_move_klass_not_null $dst,$src" %}
6138 ins_encode %{
6139 __ decode_and_move_klass_not_null($dst$$Register, $src$$Register);
6140 %}
6141 ins_pipe(ialu_reg_long);
6142 %}
6143
6144 //----------Conditional Move---------------------------------------------------
6145 // Jump
6146 // dummy instruction for generating temp registers
6147 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6148 match(Jump (LShiftL switch_val shift));
6149 ins_cost(350);
6150 predicate(false);
6151 effect(TEMP dest);
6152
6153 format %{ "leaq $dest, [$constantaddress]\n\t"
6154 "jmp [$dest + $switch_val << $shift]\n\t" %}
6155 ins_encode %{
6156 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6157 // to do that and the compiler is using that register as one it can allocate.
6158 // So we build it all by hand.
6159 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6160 // ArrayAddress dispatch(table, index);
6161 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6162 __ lea($dest$$Register, $constantaddress);
6163 __ jmp(dispatch);
6164 %}
6165 ins_pipe(pipe_jmp);
6166 %}
6167
6168 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6169 match(Jump (AddL (LShiftL switch_val shift) offset));
6170 ins_cost(350);
6171 effect(TEMP dest);
6172
6173 format %{ "leaq $dest, [$constantaddress]\n\t"
6174 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6175 ins_encode %{
6176 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6177 // to do that and the compiler is using that register as one it can allocate.
6178 // So we build it all by hand.
6179 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6180 // ArrayAddress dispatch(table, index);
6181 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6182 __ lea($dest$$Register, $constantaddress);
6183 __ jmp(dispatch);
6184 %}
6185 ins_pipe(pipe_jmp);
6186 %}
6187
6188 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6189 match(Jump switch_val);
6190 ins_cost(350);
6191 effect(TEMP dest);
6192
6193 format %{ "leaq $dest, [$constantaddress]\n\t"
6194 "jmp [$dest + $switch_val]\n\t" %}
6195 ins_encode %{
6196 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6197 // to do that and the compiler is using that register as one it can allocate.
6198 // So we build it all by hand.
6199 // Address index(noreg, switch_reg, Address::times_1);
6200 // ArrayAddress dispatch(table, index);
6201 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6202 __ lea($dest$$Register, $constantaddress);
6203 __ jmp(dispatch);
6204 %}
6205 ins_pipe(pipe_jmp);
6206 %}
6207
6208 // Conditional move
6209 instruct cmovI_imm_01(rRegI dst, immI_1 src, rFlagsReg cr, cmpOp cop)
6210 %{
6211 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6212 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6213
6214 ins_cost(100); // XXX
6215 format %{ "setbn$cop $dst\t# signed, int" %}
6216 ins_encode %{
6217 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6218 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6219 %}
6220 ins_pipe(ialu_reg);
6221 %}
6222
6223 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6224 %{
6225 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6226
6227 ins_cost(200); // XXX
6228 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6229 ins_encode %{
6230 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6231 %}
6232 ins_pipe(pipe_cmov_reg);
6233 %}
6234
6235 instruct cmovI_imm_01U(rRegI dst, immI_1 src, rFlagsRegU cr, cmpOpU cop)
6236 %{
6237 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6238 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6239
6240 ins_cost(100); // XXX
6241 format %{ "setbn$cop $dst\t# unsigned, int" %}
6242 ins_encode %{
6243 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6244 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6245 %}
6246 ins_pipe(ialu_reg);
6247 %}
6248
6249 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6250 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6251
6252 ins_cost(200); // XXX
6253 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6254 ins_encode %{
6255 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6256 %}
6257 ins_pipe(pipe_cmov_reg);
6258 %}
6259
6260 instruct cmovI_imm_01UCF(rRegI dst, immI_1 src, rFlagsRegUCF cr, cmpOpUCF cop)
6261 %{
6262 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
6263 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6264
6265 ins_cost(100); // XXX
6266 format %{ "setbn$cop $dst\t# unsigned, int" %}
6267 ins_encode %{
6268 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6269 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6270 %}
6271 ins_pipe(ialu_reg);
6272 %}
6273
6274 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6275 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6276 ins_cost(200);
6277 expand %{
6278 cmovI_regU(cop, cr, dst, src);
6279 %}
6280 %}
6281
6282 instruct cmovI_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6283 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6284 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6285
6286 ins_cost(200); // XXX
6287 format %{ "cmovpl $dst, $src\n\t"
6288 "cmovnel $dst, $src" %}
6289 ins_encode %{
6290 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6291 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6292 %}
6293 ins_pipe(pipe_cmov_reg);
6294 %}
6295
6296 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6297 // inputs of the CMove
6298 instruct cmovI_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6299 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6300 match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
6301
6302 ins_cost(200); // XXX
6303 format %{ "cmovpl $dst, $src\n\t"
6304 "cmovnel $dst, $src" %}
6305 ins_encode %{
6306 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6307 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6308 %}
6309 ins_pipe(pipe_cmov_reg);
6310 %}
6311
6312 // Conditional move
6313 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6314 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6315
6316 ins_cost(250); // XXX
6317 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6318 ins_encode %{
6319 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6320 %}
6321 ins_pipe(pipe_cmov_mem);
6322 %}
6323
6324 // Conditional move
6325 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6326 %{
6327 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6328
6329 ins_cost(250); // XXX
6330 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6331 ins_encode %{
6332 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6333 %}
6334 ins_pipe(pipe_cmov_mem);
6335 %}
6336
6337 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6338 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6339 ins_cost(250);
6340 expand %{
6341 cmovI_memU(cop, cr, dst, src);
6342 %}
6343 %}
6344
6345 // Conditional move
6346 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6347 %{
6348 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6349
6350 ins_cost(200); // XXX
6351 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6352 ins_encode %{
6353 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6354 %}
6355 ins_pipe(pipe_cmov_reg);
6356 %}
6357
6358 // Conditional move
6359 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6360 %{
6361 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6362
6363 ins_cost(200); // XXX
6364 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6365 ins_encode %{
6366 __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6367 %}
6368 ins_pipe(pipe_cmov_reg);
6369 %}
6370
6371 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6372 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6373 ins_cost(200);
6374 expand %{
6375 cmovN_regU(cop, cr, dst, src);
6376 %}
6377 %}
6378
6379 instruct cmovN_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6380 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6381 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6382
6383 ins_cost(200); // XXX
6384 format %{ "cmovpl $dst, $src\n\t"
6385 "cmovnel $dst, $src" %}
6386 ins_encode %{
6387 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6388 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6389 %}
6390 ins_pipe(pipe_cmov_reg);
6391 %}
6392
6393 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6394 // inputs of the CMove
6395 instruct cmovN_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6396 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6397 match(Set dst (CMoveN (Binary cop cr) (Binary src dst)));
6398
6399 ins_cost(200); // XXX
6400 format %{ "cmovpl $dst, $src\n\t"
6401 "cmovnel $dst, $src" %}
6402 ins_encode %{
6403 __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
6404 __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
6405 %}
6406 ins_pipe(pipe_cmov_reg);
6407 %}
6408
6409 // Conditional move
6410 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6411 %{
6412 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6413
6414 ins_cost(200); // XXX
6415 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6416 ins_encode %{
6417 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6418 %}
6419 ins_pipe(pipe_cmov_reg); // XXX
6420 %}
6421
6422 // Conditional move
6423 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6424 %{
6425 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6426
6427 ins_cost(200); // XXX
6428 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6429 ins_encode %{
6430 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6431 %}
6432 ins_pipe(pipe_cmov_reg); // XXX
6433 %}
6434
6435 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6436 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6437 ins_cost(200);
6438 expand %{
6439 cmovP_regU(cop, cr, dst, src);
6440 %}
6441 %}
6442
6443 instruct cmovP_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6444 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6445 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6446
6447 ins_cost(200); // XXX
6448 format %{ "cmovpq $dst, $src\n\t"
6449 "cmovneq $dst, $src" %}
6450 ins_encode %{
6451 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6452 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6453 %}
6454 ins_pipe(pipe_cmov_reg);
6455 %}
6456
6457 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6458 // inputs of the CMove
6459 instruct cmovP_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6460 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6461 match(Set dst (CMoveP (Binary cop cr) (Binary src dst)));
6462
6463 ins_cost(200); // XXX
6464 format %{ "cmovpq $dst, $src\n\t"
6465 "cmovneq $dst, $src" %}
6466 ins_encode %{
6467 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6468 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6469 %}
6470 ins_pipe(pipe_cmov_reg);
6471 %}
6472
6473 instruct cmovL_imm_01(rRegL dst, immI_1 src, rFlagsReg cr, cmpOp cop)
6474 %{
6475 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6476 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6477
6478 ins_cost(100); // XXX
6479 format %{ "setbn$cop $dst\t# signed, long" %}
6480 ins_encode %{
6481 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6482 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6483 %}
6484 ins_pipe(ialu_reg);
6485 %}
6486
6487 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6488 %{
6489 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6490
6491 ins_cost(200); // XXX
6492 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6493 ins_encode %{
6494 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6495 %}
6496 ins_pipe(pipe_cmov_reg); // XXX
6497 %}
6498
6499 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6500 %{
6501 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6502
6503 ins_cost(200); // XXX
6504 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6505 ins_encode %{
6506 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6507 %}
6508 ins_pipe(pipe_cmov_mem); // XXX
6509 %}
6510
6511 instruct cmovL_imm_01U(rRegL dst, immI_1 src, rFlagsRegU cr, cmpOpU cop)
6512 %{
6513 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6514 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6515
6516 ins_cost(100); // XXX
6517 format %{ "setbn$cop $dst\t# unsigned, long" %}
6518 ins_encode %{
6519 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6520 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6521 %}
6522 ins_pipe(ialu_reg);
6523 %}
6524
6525 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6526 %{
6527 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6528
6529 ins_cost(200); // XXX
6530 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6531 ins_encode %{
6532 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
6533 %}
6534 ins_pipe(pipe_cmov_reg); // XXX
6535 %}
6536
6537 instruct cmovL_imm_01UCF(rRegL dst, immI_1 src, rFlagsRegUCF cr, cmpOpUCF cop)
6538 %{
6539 predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
6540 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6541
6542 ins_cost(100); // XXX
6543 format %{ "setbn$cop $dst\t# unsigned, long" %}
6544 ins_encode %{
6545 Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
6546 __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
6547 %}
6548 ins_pipe(ialu_reg);
6549 %}
6550
6551 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6552 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6553 ins_cost(200);
6554 expand %{
6555 cmovL_regU(cop, cr, dst, src);
6556 %}
6557 %}
6558
6559 instruct cmovL_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6560 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
6561 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6562
6563 ins_cost(200); // XXX
6564 format %{ "cmovpq $dst, $src\n\t"
6565 "cmovneq $dst, $src" %}
6566 ins_encode %{
6567 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6568 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6569 %}
6570 ins_pipe(pipe_cmov_reg);
6571 %}
6572
6573 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
6574 // inputs of the CMove
6575 instruct cmovL_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6576 predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
6577 match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
6578
6579 ins_cost(200); // XXX
6580 format %{ "cmovpq $dst, $src\n\t"
6581 "cmovneq $dst, $src" %}
6582 ins_encode %{
6583 __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
6584 __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
6585 %}
6586 ins_pipe(pipe_cmov_reg);
6587 %}
6588
6589 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6590 %{
6591 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6592
6593 ins_cost(200); // XXX
6594 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6595 ins_encode %{
6596 __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
6597 %}
6598 ins_pipe(pipe_cmov_mem); // XXX
6599 %}
6600
6601 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6602 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6603 ins_cost(200);
6604 expand %{
6605 cmovL_memU(cop, cr, dst, src);
6606 %}
6607 %}
6608
6609 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6610 %{
6611 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6612
6613 ins_cost(200); // XXX
6614 format %{ "jn$cop skip\t# signed cmove float\n\t"
6615 "movss $dst, $src\n"
6616 "skip:" %}
6617 ins_encode %{
6618 Label Lskip;
6619 // Invert sense of branch from sense of CMOV
6620 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6621 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6622 __ bind(Lskip);
6623 %}
6624 ins_pipe(pipe_slow);
6625 %}
6626
6627 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6628 %{
6629 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6630
6631 ins_cost(200); // XXX
6632 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6633 "movss $dst, $src\n"
6634 "skip:" %}
6635 ins_encode %{
6636 Label Lskip;
6637 // Invert sense of branch from sense of CMOV
6638 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6639 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6640 __ bind(Lskip);
6641 %}
6642 ins_pipe(pipe_slow);
6643 %}
6644
6645 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6646 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6647 ins_cost(200);
6648 expand %{
6649 cmovF_regU(cop, cr, dst, src);
6650 %}
6651 %}
6652
6653 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6654 %{
6655 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6656
6657 ins_cost(200); // XXX
6658 format %{ "jn$cop skip\t# signed cmove double\n\t"
6659 "movsd $dst, $src\n"
6660 "skip:" %}
6661 ins_encode %{
6662 Label Lskip;
6663 // Invert sense of branch from sense of CMOV
6664 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6665 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6666 __ bind(Lskip);
6667 %}
6668 ins_pipe(pipe_slow);
6669 %}
6670
6671 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6672 %{
6673 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6674
6675 ins_cost(200); // XXX
6676 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6677 "movsd $dst, $src\n"
6678 "skip:" %}
6679 ins_encode %{
6680 Label Lskip;
6681 // Invert sense of branch from sense of CMOV
6682 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6683 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6684 __ bind(Lskip);
6685 %}
6686 ins_pipe(pipe_slow);
6687 %}
6688
6689 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6690 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6691 ins_cost(200);
6692 expand %{
6693 cmovD_regU(cop, cr, dst, src);
6694 %}
6695 %}
6696
6697 //----------Arithmetic Instructions--------------------------------------------
6698 //----------Addition Instructions----------------------------------------------
6699
6700 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6701 %{
6702 match(Set dst (AddI dst src));
6703 effect(KILL cr);
6704 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6705 format %{ "addl $dst, $src\t# int" %}
6706 ins_encode %{
6707 __ addl($dst$$Register, $src$$Register);
6708 %}
6709 ins_pipe(ialu_reg_reg);
6710 %}
6711
6712 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6713 %{
6714 match(Set dst (AddI dst src));
6715 effect(KILL cr);
6716 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6717
6718 format %{ "addl $dst, $src\t# int" %}
6719 ins_encode %{
6720 __ addl($dst$$Register, $src$$constant);
6721 %}
6722 ins_pipe( ialu_reg );
6723 %}
6724
6725 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6726 %{
6727 match(Set dst (AddI dst (LoadI src)));
6728 effect(KILL cr);
6729 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6730
6731 ins_cost(150); // XXX
6732 format %{ "addl $dst, $src\t# int" %}
6733 ins_encode %{
6734 __ addl($dst$$Register, $src$$Address);
6735 %}
6736 ins_pipe(ialu_reg_mem);
6737 %}
6738
6739 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6740 %{
6741 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6742 effect(KILL cr);
6743 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6744
6745 ins_cost(150); // XXX
6746 format %{ "addl $dst, $src\t# int" %}
6747 ins_encode %{
6748 __ addl($dst$$Address, $src$$Register);
6749 %}
6750 ins_pipe(ialu_mem_reg);
6751 %}
6752
6753 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6754 %{
6755 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6756 effect(KILL cr);
6757 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6758
6759
6760 ins_cost(125); // XXX
6761 format %{ "addl $dst, $src\t# int" %}
6762 ins_encode %{
6763 __ addl($dst$$Address, $src$$constant);
6764 %}
6765 ins_pipe(ialu_mem_imm);
6766 %}
6767
6768 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
6769 %{
6770 predicate(UseIncDec);
6771 match(Set dst (AddI dst src));
6772 effect(KILL cr);
6773
6774 format %{ "incl $dst\t# int" %}
6775 ins_encode %{
6776 __ incrementl($dst$$Register);
6777 %}
6778 ins_pipe(ialu_reg);
6779 %}
6780
6781 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
6782 %{
6783 predicate(UseIncDec);
6784 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6785 effect(KILL cr);
6786
6787 ins_cost(125); // XXX
6788 format %{ "incl $dst\t# int" %}
6789 ins_encode %{
6790 __ incrementl($dst$$Address);
6791 %}
6792 ins_pipe(ialu_mem_imm);
6793 %}
6794
6795 // XXX why does that use AddI
6796 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6797 %{
6798 predicate(UseIncDec);
6799 match(Set dst (AddI dst src));
6800 effect(KILL cr);
6801
6802 format %{ "decl $dst\t# int" %}
6803 ins_encode %{
6804 __ decrementl($dst$$Register);
6805 %}
6806 ins_pipe(ialu_reg);
6807 %}
6808
6809 // XXX why does that use AddI
6810 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
6811 %{
6812 predicate(UseIncDec);
6813 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6814 effect(KILL cr);
6815
6816 ins_cost(125); // XXX
6817 format %{ "decl $dst\t# int" %}
6818 ins_encode %{
6819 __ decrementl($dst$$Address);
6820 %}
6821 ins_pipe(ialu_mem_imm);
6822 %}
6823
6824 instruct leaI_rReg_immI2_immI(rRegI dst, rRegI index, immI2 scale, immI disp)
6825 %{
6826 predicate(VM_Version::supports_fast_2op_lea());
6827 match(Set dst (AddI (LShiftI index scale) disp));
6828
6829 format %{ "leal $dst, [$index << $scale + $disp]\t# int" %}
6830 ins_encode %{
6831 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
6832 __ leal($dst$$Register, Address(noreg, $index$$Register, scale, $disp$$constant));
6833 %}
6834 ins_pipe(ialu_reg_reg);
6835 %}
6836
6837 instruct leaI_rReg_rReg_immI(rRegI dst, rRegI base, rRegI index, immI disp)
6838 %{
6839 predicate(VM_Version::supports_fast_3op_lea());
6840 match(Set dst (AddI (AddI base index) disp));
6841
6842 format %{ "leal $dst, [$base + $index + $disp]\t# int" %}
6843 ins_encode %{
6844 __ leal($dst$$Register, Address($base$$Register, $index$$Register, Address::times_1, $disp$$constant));
6845 %}
6846 ins_pipe(ialu_reg_reg);
6847 %}
6848
6849 instruct leaI_rReg_rReg_immI2(rRegI dst, no_rbp_r13_RegI base, rRegI index, immI2 scale)
6850 %{
6851 predicate(VM_Version::supports_fast_2op_lea());
6852 match(Set dst (AddI base (LShiftI index scale)));
6853
6854 format %{ "leal $dst, [$base + $index << $scale]\t# int" %}
6855 ins_encode %{
6856 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
6857 __ leal($dst$$Register, Address($base$$Register, $index$$Register, scale));
6858 %}
6859 ins_pipe(ialu_reg_reg);
6860 %}
6861
6862 instruct leaI_rReg_rReg_immI2_immI(rRegI dst, rRegI base, rRegI index, immI2 scale, immI disp)
6863 %{
6864 predicate(VM_Version::supports_fast_3op_lea());
6865 match(Set dst (AddI (AddI base (LShiftI index scale)) disp));
6866
6867 format %{ "leal $dst, [$base + $index << $scale + $disp]\t# int" %}
6868 ins_encode %{
6869 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
6870 __ leal($dst$$Register, Address($base$$Register, $index$$Register, scale, $disp$$constant));
6871 %}
6872 ins_pipe(ialu_reg_reg);
6873 %}
6874
6875 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
6876 %{
6877 match(Set dst (AddL dst src));
6878 effect(KILL cr);
6879 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6880
6881 format %{ "addq $dst, $src\t# long" %}
6882 ins_encode %{
6883 __ addq($dst$$Register, $src$$Register);
6884 %}
6885 ins_pipe(ialu_reg_reg);
6886 %}
6887
6888 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
6889 %{
6890 match(Set dst (AddL dst src));
6891 effect(KILL cr);
6892 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6893
6894 format %{ "addq $dst, $src\t# long" %}
6895 ins_encode %{
6896 __ addq($dst$$Register, $src$$constant);
6897 %}
6898 ins_pipe( ialu_reg );
6899 %}
6900
6901 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
6902 %{
6903 match(Set dst (AddL dst (LoadL src)));
6904 effect(KILL cr);
6905 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6906
6907 ins_cost(150); // XXX
6908 format %{ "addq $dst, $src\t# long" %}
6909 ins_encode %{
6910 __ addq($dst$$Register, $src$$Address);
6911 %}
6912 ins_pipe(ialu_reg_mem);
6913 %}
6914
6915 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
6916 %{
6917 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6918 effect(KILL cr);
6919 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6920
6921 ins_cost(150); // XXX
6922 format %{ "addq $dst, $src\t# long" %}
6923 ins_encode %{
6924 __ addq($dst$$Address, $src$$Register);
6925 %}
6926 ins_pipe(ialu_mem_reg);
6927 %}
6928
6929 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
6930 %{
6931 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6932 effect(KILL cr);
6933 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
6934
6935 ins_cost(125); // XXX
6936 format %{ "addq $dst, $src\t# long" %}
6937 ins_encode %{
6938 __ addq($dst$$Address, $src$$constant);
6939 %}
6940 ins_pipe(ialu_mem_imm);
6941 %}
6942
6943 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
6944 %{
6945 predicate(UseIncDec);
6946 match(Set dst (AddL dst src));
6947 effect(KILL cr);
6948
6949 format %{ "incq $dst\t# long" %}
6950 ins_encode %{
6951 __ incrementq($dst$$Register);
6952 %}
6953 ins_pipe(ialu_reg);
6954 %}
6955
6956 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
6957 %{
6958 predicate(UseIncDec);
6959 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6960 effect(KILL cr);
6961
6962 ins_cost(125); // XXX
6963 format %{ "incq $dst\t# long" %}
6964 ins_encode %{
6965 __ incrementq($dst$$Address);
6966 %}
6967 ins_pipe(ialu_mem_imm);
6968 %}
6969
6970 // XXX why does that use AddL
6971 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
6972 %{
6973 predicate(UseIncDec);
6974 match(Set dst (AddL dst src));
6975 effect(KILL cr);
6976
6977 format %{ "decq $dst\t# long" %}
6978 ins_encode %{
6979 __ decrementq($dst$$Register);
6980 %}
6981 ins_pipe(ialu_reg);
6982 %}
6983
6984 // XXX why does that use AddL
6985 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
6986 %{
6987 predicate(UseIncDec);
6988 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
6989 effect(KILL cr);
6990
6991 ins_cost(125); // XXX
6992 format %{ "decq $dst\t# long" %}
6993 ins_encode %{
6994 __ decrementq($dst$$Address);
6995 %}
6996 ins_pipe(ialu_mem_imm);
6997 %}
6998
6999 instruct leaL_rReg_immI2_immL32(rRegL dst, rRegL index, immI2 scale, immL32 disp)
7000 %{
7001 predicate(VM_Version::supports_fast_2op_lea());
7002 match(Set dst (AddL (LShiftL index scale) disp));
7003
7004 format %{ "leaq $dst, [$index << $scale + $disp]\t# long" %}
7005 ins_encode %{
7006 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7007 __ leaq($dst$$Register, Address(noreg, $index$$Register, scale, $disp$$constant));
7008 %}
7009 ins_pipe(ialu_reg_reg);
7010 %}
7011
7012 instruct leaL_rReg_rReg_immL32(rRegL dst, rRegL base, rRegL index, immL32 disp)
7013 %{
7014 predicate(VM_Version::supports_fast_3op_lea());
7015 match(Set dst (AddL (AddL base index) disp));
7016
7017 format %{ "leaq $dst, [$base + $index + $disp]\t# long" %}
7018 ins_encode %{
7019 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, Address::times_1, $disp$$constant));
7020 %}
7021 ins_pipe(ialu_reg_reg);
7022 %}
7023
7024 instruct leaL_rReg_rReg_immI2(rRegL dst, no_rbp_r13_RegL base, rRegL index, immI2 scale)
7025 %{
7026 predicate(VM_Version::supports_fast_2op_lea());
7027 match(Set dst (AddL base (LShiftL index scale)));
7028
7029 format %{ "leaq $dst, [$base + $index << $scale]\t# long" %}
7030 ins_encode %{
7031 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7032 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, scale));
7033 %}
7034 ins_pipe(ialu_reg_reg);
7035 %}
7036
7037 instruct leaL_rReg_rReg_immI2_immL32(rRegL dst, rRegL base, rRegL index, immI2 scale, immL32 disp)
7038 %{
7039 predicate(VM_Version::supports_fast_3op_lea());
7040 match(Set dst (AddL (AddL base (LShiftL index scale)) disp));
7041
7042 format %{ "leaq $dst, [$base + $index << $scale + $disp]\t# long" %}
7043 ins_encode %{
7044 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
7045 __ leaq($dst$$Register, Address($base$$Register, $index$$Register, scale, $disp$$constant));
7046 %}
7047 ins_pipe(ialu_reg_reg);
7048 %}
7049
7050 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7051 %{
7052 match(Set dst (AddP dst src));
7053 effect(KILL cr);
7054 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7055
7056 format %{ "addq $dst, $src\t# ptr" %}
7057 ins_encode %{
7058 __ addq($dst$$Register, $src$$Register);
7059 %}
7060 ins_pipe(ialu_reg_reg);
7061 %}
7062
7063 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7064 %{
7065 match(Set dst (AddP dst src));
7066 effect(KILL cr);
7067 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7068
7069 format %{ "addq $dst, $src\t# ptr" %}
7070 ins_encode %{
7071 __ addq($dst$$Register, $src$$constant);
7072 %}
7073 ins_pipe( ialu_reg );
7074 %}
7075
7076 // XXX addP mem ops ????
7077
7078 instruct checkCastPP(rRegP dst)
7079 %{
7080 match(Set dst (CheckCastPP dst));
7081
7082 size(0);
7083 format %{ "# checkcastPP of $dst" %}
7084 ins_encode(/* empty encoding */);
7085 ins_pipe(empty);
7086 %}
7087
7088 instruct castPP(rRegP dst)
7089 %{
7090 match(Set dst (CastPP dst));
7091
7092 size(0);
7093 format %{ "# castPP of $dst" %}
7094 ins_encode(/* empty encoding */);
7095 ins_pipe(empty);
7096 %}
7097
7098 instruct castII(rRegI dst)
7099 %{
7100 match(Set dst (CastII dst));
7101
7102 size(0);
7103 format %{ "# castII of $dst" %}
7104 ins_encode(/* empty encoding */);
7105 ins_cost(0);
7106 ins_pipe(empty);
7107 %}
7108
7109 instruct castLL(rRegL dst)
7110 %{
7111 match(Set dst (CastLL dst));
7112
7113 size(0);
7114 format %{ "# castLL of $dst" %}
7115 ins_encode(/* empty encoding */);
7116 ins_cost(0);
7117 ins_pipe(empty);
7118 %}
7119
7120 instruct castFF(regF dst)
7121 %{
7122 match(Set dst (CastFF dst));
7123
7124 size(0);
7125 format %{ "# castFF of $dst" %}
7126 ins_encode(/* empty encoding */);
7127 ins_cost(0);
7128 ins_pipe(empty);
7129 %}
7130
7131 instruct castDD(regD dst)
7132 %{
7133 match(Set dst (CastDD dst));
7134
7135 size(0);
7136 format %{ "# castDD of $dst" %}
7137 ins_encode(/* empty encoding */);
7138 ins_cost(0);
7139 ins_pipe(empty);
7140 %}
7141
7142 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7143 instruct compareAndSwapP(rRegI res,
7144 memory mem_ptr,
7145 rax_RegP oldval, rRegP newval,
7146 rFlagsReg cr)
7147 %{
7148 predicate(n->as_LoadStore()->barrier_data() == 0);
7149 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7150 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7151 effect(KILL cr, KILL oldval);
7152
7153 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7154 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7155 "sete $res\n\t"
7156 "movzbl $res, $res" %}
7157 ins_encode %{
7158 __ lock();
7159 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7160 __ setb(Assembler::equal, $res$$Register);
7161 __ movzbl($res$$Register, $res$$Register);
7162 %}
7163 ins_pipe( pipe_cmpxchg );
7164 %}
7165
7166 instruct compareAndSwapL(rRegI res,
7167 memory mem_ptr,
7168 rax_RegL oldval, rRegL newval,
7169 rFlagsReg cr)
7170 %{
7171 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7172 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7173 effect(KILL cr, KILL oldval);
7174
7175 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7176 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7177 "sete $res\n\t"
7178 "movzbl $res, $res" %}
7179 ins_encode %{
7180 __ lock();
7181 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7182 __ setb(Assembler::equal, $res$$Register);
7183 __ movzbl($res$$Register, $res$$Register);
7184 %}
7185 ins_pipe( pipe_cmpxchg );
7186 %}
7187
7188 instruct compareAndSwapI(rRegI res,
7189 memory mem_ptr,
7190 rax_RegI oldval, rRegI newval,
7191 rFlagsReg cr)
7192 %{
7193 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7194 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7195 effect(KILL cr, KILL oldval);
7196
7197 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7198 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7199 "sete $res\n\t"
7200 "movzbl $res, $res" %}
7201 ins_encode %{
7202 __ lock();
7203 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7204 __ setb(Assembler::equal, $res$$Register);
7205 __ movzbl($res$$Register, $res$$Register);
7206 %}
7207 ins_pipe( pipe_cmpxchg );
7208 %}
7209
7210 instruct compareAndSwapB(rRegI res,
7211 memory mem_ptr,
7212 rax_RegI oldval, rRegI newval,
7213 rFlagsReg cr)
7214 %{
7215 match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
7216 match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
7217 effect(KILL cr, KILL oldval);
7218
7219 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7220 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7221 "sete $res\n\t"
7222 "movzbl $res, $res" %}
7223 ins_encode %{
7224 __ lock();
7225 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7226 __ setb(Assembler::equal, $res$$Register);
7227 __ movzbl($res$$Register, $res$$Register);
7228 %}
7229 ins_pipe( pipe_cmpxchg );
7230 %}
7231
7232 instruct compareAndSwapS(rRegI res,
7233 memory mem_ptr,
7234 rax_RegI oldval, rRegI newval,
7235 rFlagsReg cr)
7236 %{
7237 match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
7238 match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
7239 effect(KILL cr, KILL oldval);
7240
7241 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7242 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7243 "sete $res\n\t"
7244 "movzbl $res, $res" %}
7245 ins_encode %{
7246 __ lock();
7247 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7248 __ setb(Assembler::equal, $res$$Register);
7249 __ movzbl($res$$Register, $res$$Register);
7250 %}
7251 ins_pipe( pipe_cmpxchg );
7252 %}
7253
7254 instruct compareAndSwapN(rRegI res,
7255 memory mem_ptr,
7256 rax_RegN oldval, rRegN newval,
7257 rFlagsReg cr) %{
7258 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7259 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7260 effect(KILL cr, KILL oldval);
7261
7262 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7263 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7264 "sete $res\n\t"
7265 "movzbl $res, $res" %}
7266 ins_encode %{
7267 __ lock();
7268 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7269 __ setb(Assembler::equal, $res$$Register);
7270 __ movzbl($res$$Register, $res$$Register);
7271 %}
7272 ins_pipe( pipe_cmpxchg );
7273 %}
7274
7275 instruct compareAndExchangeB(
7276 memory mem_ptr,
7277 rax_RegI oldval, rRegI newval,
7278 rFlagsReg cr)
7279 %{
7280 match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
7281 effect(KILL cr);
7282
7283 format %{ "cmpxchgb $mem_ptr,$newval\t# "
7284 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7285 ins_encode %{
7286 __ lock();
7287 __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
7288 %}
7289 ins_pipe( pipe_cmpxchg );
7290 %}
7291
7292 instruct compareAndExchangeS(
7293 memory mem_ptr,
7294 rax_RegI oldval, rRegI newval,
7295 rFlagsReg cr)
7296 %{
7297 match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
7298 effect(KILL cr);
7299
7300 format %{ "cmpxchgw $mem_ptr,$newval\t# "
7301 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7302 ins_encode %{
7303 __ lock();
7304 __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
7305 %}
7306 ins_pipe( pipe_cmpxchg );
7307 %}
7308
7309 instruct compareAndExchangeI(
7310 memory mem_ptr,
7311 rax_RegI oldval, rRegI newval,
7312 rFlagsReg cr)
7313 %{
7314 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7315 effect(KILL cr);
7316
7317 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7318 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7319 ins_encode %{
7320 __ lock();
7321 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7322 %}
7323 ins_pipe( pipe_cmpxchg );
7324 %}
7325
7326 instruct compareAndExchangeL(
7327 memory mem_ptr,
7328 rax_RegL oldval, rRegL newval,
7329 rFlagsReg cr)
7330 %{
7331 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7332 effect(KILL cr);
7333
7334 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7335 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7336 ins_encode %{
7337 __ lock();
7338 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7339 %}
7340 ins_pipe( pipe_cmpxchg );
7341 %}
7342
7343 instruct compareAndExchangeN(
7344 memory mem_ptr,
7345 rax_RegN oldval, rRegN newval,
7346 rFlagsReg cr) %{
7347 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7348 effect(KILL cr);
7349
7350 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7351 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7352 ins_encode %{
7353 __ lock();
7354 __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
7355 %}
7356 ins_pipe( pipe_cmpxchg );
7357 %}
7358
7359 instruct compareAndExchangeP(
7360 memory mem_ptr,
7361 rax_RegP oldval, rRegP newval,
7362 rFlagsReg cr)
7363 %{
7364 predicate(n->as_LoadStore()->barrier_data() == 0);
7365 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7366 effect(KILL cr);
7367
7368 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7369 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7370 ins_encode %{
7371 __ lock();
7372 __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
7373 %}
7374 ins_pipe( pipe_cmpxchg );
7375 %}
7376
7377 instruct xaddB_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7378 predicate(n->as_LoadStore()->result_not_used());
7379 match(Set dummy (GetAndAddB mem add));
7380 effect(KILL cr);
7381 format %{ "addb_lock $mem, $add" %}
7382 ins_encode %{
7383 __ lock();
7384 __ addb($mem$$Address, $add$$Register);
7385 %}
7386 ins_pipe(pipe_cmpxchg);
7387 %}
7388
7389 instruct xaddB_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7390 predicate(n->as_LoadStore()->result_not_used());
7391 match(Set dummy (GetAndAddB mem add));
7392 effect(KILL cr);
7393 format %{ "addb_lock $mem, $add" %}
7394 ins_encode %{
7395 __ lock();
7396 __ addb($mem$$Address, $add$$constant);
7397 %}
7398 ins_pipe(pipe_cmpxchg);
7399 %}
7400
7401 instruct xaddB(memory mem, rRegI newval, rFlagsReg cr) %{
7402 predicate(!n->as_LoadStore()->result_not_used());
7403 match(Set newval (GetAndAddB mem newval));
7404 effect(KILL cr);
7405 format %{ "xaddb_lock $mem, $newval" %}
7406 ins_encode %{
7407 __ lock();
7408 __ xaddb($mem$$Address, $newval$$Register);
7409 %}
7410 ins_pipe(pipe_cmpxchg);
7411 %}
7412
7413 instruct xaddS_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7414 predicate(n->as_LoadStore()->result_not_used());
7415 match(Set dummy (GetAndAddS mem add));
7416 effect(KILL cr);
7417 format %{ "addw_lock $mem, $add" %}
7418 ins_encode %{
7419 __ lock();
7420 __ addw($mem$$Address, $add$$Register);
7421 %}
7422 ins_pipe(pipe_cmpxchg);
7423 %}
7424
7425 instruct xaddS_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7426 predicate(UseStoreImmI16 && n->as_LoadStore()->result_not_used());
7427 match(Set dummy (GetAndAddS mem add));
7428 effect(KILL cr);
7429 format %{ "addw_lock $mem, $add" %}
7430 ins_encode %{
7431 __ lock();
7432 __ addw($mem$$Address, $add$$constant);
7433 %}
7434 ins_pipe(pipe_cmpxchg);
7435 %}
7436
7437 instruct xaddS(memory mem, rRegI newval, rFlagsReg cr) %{
7438 predicate(!n->as_LoadStore()->result_not_used());
7439 match(Set newval (GetAndAddS mem newval));
7440 effect(KILL cr);
7441 format %{ "xaddw_lock $mem, $newval" %}
7442 ins_encode %{
7443 __ lock();
7444 __ xaddw($mem$$Address, $newval$$Register);
7445 %}
7446 ins_pipe(pipe_cmpxchg);
7447 %}
7448
7449 instruct xaddI_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
7450 predicate(n->as_LoadStore()->result_not_used());
7451 match(Set dummy (GetAndAddI mem add));
7452 effect(KILL cr);
7453 format %{ "addl_lock $mem, $add" %}
7454 ins_encode %{
7455 __ lock();
7456 __ addl($mem$$Address, $add$$Register);
7457 %}
7458 ins_pipe(pipe_cmpxchg);
7459 %}
7460
7461 instruct xaddI_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7462 predicate(n->as_LoadStore()->result_not_used());
7463 match(Set dummy (GetAndAddI mem add));
7464 effect(KILL cr);
7465 format %{ "addl_lock $mem, $add" %}
7466 ins_encode %{
7467 __ lock();
7468 __ addl($mem$$Address, $add$$constant);
7469 %}
7470 ins_pipe(pipe_cmpxchg);
7471 %}
7472
7473 instruct xaddI(memory mem, rRegI newval, rFlagsReg cr) %{
7474 predicate(!n->as_LoadStore()->result_not_used());
7475 match(Set newval (GetAndAddI mem newval));
7476 effect(KILL cr);
7477 format %{ "xaddl_lock $mem, $newval" %}
7478 ins_encode %{
7479 __ lock();
7480 __ xaddl($mem$$Address, $newval$$Register);
7481 %}
7482 ins_pipe(pipe_cmpxchg);
7483 %}
7484
7485 instruct xaddL_reg_no_res(memory mem, Universe dummy, rRegL add, rFlagsReg cr) %{
7486 predicate(n->as_LoadStore()->result_not_used());
7487 match(Set dummy (GetAndAddL mem add));
7488 effect(KILL cr);
7489 format %{ "addq_lock $mem, $add" %}
7490 ins_encode %{
7491 __ lock();
7492 __ addq($mem$$Address, $add$$Register);
7493 %}
7494 ins_pipe(pipe_cmpxchg);
7495 %}
7496
7497 instruct xaddL_imm_no_res(memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7498 predicate(n->as_LoadStore()->result_not_used());
7499 match(Set dummy (GetAndAddL mem add));
7500 effect(KILL cr);
7501 format %{ "addq_lock $mem, $add" %}
7502 ins_encode %{
7503 __ lock();
7504 __ addq($mem$$Address, $add$$constant);
7505 %}
7506 ins_pipe(pipe_cmpxchg);
7507 %}
7508
7509 instruct xaddL(memory mem, rRegL newval, rFlagsReg cr) %{
7510 predicate(!n->as_LoadStore()->result_not_used());
7511 match(Set newval (GetAndAddL mem newval));
7512 effect(KILL cr);
7513 format %{ "xaddq_lock $mem, $newval" %}
7514 ins_encode %{
7515 __ lock();
7516 __ xaddq($mem$$Address, $newval$$Register);
7517 %}
7518 ins_pipe(pipe_cmpxchg);
7519 %}
7520
7521 instruct xchgB( memory mem, rRegI newval) %{
7522 match(Set newval (GetAndSetB mem newval));
7523 format %{ "XCHGB $newval,[$mem]" %}
7524 ins_encode %{
7525 __ xchgb($newval$$Register, $mem$$Address);
7526 %}
7527 ins_pipe( pipe_cmpxchg );
7528 %}
7529
7530 instruct xchgS( memory mem, rRegI newval) %{
7531 match(Set newval (GetAndSetS mem newval));
7532 format %{ "XCHGW $newval,[$mem]" %}
7533 ins_encode %{
7534 __ xchgw($newval$$Register, $mem$$Address);
7535 %}
7536 ins_pipe( pipe_cmpxchg );
7537 %}
7538
7539 instruct xchgI( memory mem, rRegI newval) %{
7540 match(Set newval (GetAndSetI mem newval));
7541 format %{ "XCHGL $newval,[$mem]" %}
7542 ins_encode %{
7543 __ xchgl($newval$$Register, $mem$$Address);
7544 %}
7545 ins_pipe( pipe_cmpxchg );
7546 %}
7547
7548 instruct xchgL( memory mem, rRegL newval) %{
7549 match(Set newval (GetAndSetL mem newval));
7550 format %{ "XCHGL $newval,[$mem]" %}
7551 ins_encode %{
7552 __ xchgq($newval$$Register, $mem$$Address);
7553 %}
7554 ins_pipe( pipe_cmpxchg );
7555 %}
7556
7557 instruct xchgP( memory mem, rRegP newval) %{
7558 match(Set newval (GetAndSetP mem newval));
7559 predicate(n->as_LoadStore()->barrier_data() == 0);
7560 format %{ "XCHGQ $newval,[$mem]" %}
7561 ins_encode %{
7562 __ xchgq($newval$$Register, $mem$$Address);
7563 %}
7564 ins_pipe( pipe_cmpxchg );
7565 %}
7566
7567 instruct xchgN( memory mem, rRegN newval) %{
7568 match(Set newval (GetAndSetN mem newval));
7569 format %{ "XCHGL $newval,$mem]" %}
7570 ins_encode %{
7571 __ xchgl($newval$$Register, $mem$$Address);
7572 %}
7573 ins_pipe( pipe_cmpxchg );
7574 %}
7575
7576 //----------Abs Instructions-------------------------------------------
7577
7578 // Integer Absolute Instructions
7579 instruct absI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7580 %{
7581 match(Set dst (AbsI src));
7582 effect(TEMP dst, KILL cr);
7583 format %{ "xorl $dst, $dst\t# abs int\n\t"
7584 "subl $dst, $src\n\t"
7585 "cmovll $dst, $src" %}
7586 ins_encode %{
7587 __ xorl($dst$$Register, $dst$$Register);
7588 __ subl($dst$$Register, $src$$Register);
7589 __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
7590 %}
7591
7592 ins_pipe(ialu_reg_reg);
7593 %}
7594
7595 // Long Absolute Instructions
7596 instruct absL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7597 %{
7598 match(Set dst (AbsL src));
7599 effect(TEMP dst, KILL cr);
7600 format %{ "xorl $dst, $dst\t# abs long\n\t"
7601 "subq $dst, $src\n\t"
7602 "cmovlq $dst, $src" %}
7603 ins_encode %{
7604 __ xorl($dst$$Register, $dst$$Register);
7605 __ subq($dst$$Register, $src$$Register);
7606 __ cmovq(Assembler::less, $dst$$Register, $src$$Register);
7607 %}
7608
7609 ins_pipe(ialu_reg_reg);
7610 %}
7611
7612 //----------Subtraction Instructions-------------------------------------------
7613
7614 // Integer Subtraction Instructions
7615 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7616 %{
7617 match(Set dst (SubI dst src));
7618 effect(KILL cr);
7619 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7620
7621 format %{ "subl $dst, $src\t# int" %}
7622 ins_encode %{
7623 __ subl($dst$$Register, $src$$Register);
7624 %}
7625 ins_pipe(ialu_reg_reg);
7626 %}
7627
7628 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7629 %{
7630 match(Set dst (SubI dst (LoadI src)));
7631 effect(KILL cr);
7632 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7633
7634 ins_cost(150);
7635 format %{ "subl $dst, $src\t# int" %}
7636 ins_encode %{
7637 __ subl($dst$$Register, $src$$Address);
7638 %}
7639 ins_pipe(ialu_reg_mem);
7640 %}
7641
7642 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7643 %{
7644 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7645 effect(KILL cr);
7646 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7647
7648 ins_cost(150);
7649 format %{ "subl $dst, $src\t# int" %}
7650 ins_encode %{
7651 __ subl($dst$$Address, $src$$Register);
7652 %}
7653 ins_pipe(ialu_mem_reg);
7654 %}
7655
7656 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7657 %{
7658 match(Set dst (SubL dst src));
7659 effect(KILL cr);
7660 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7661
7662 format %{ "subq $dst, $src\t# long" %}
7663 ins_encode %{
7664 __ subq($dst$$Register, $src$$Register);
7665 %}
7666 ins_pipe(ialu_reg_reg);
7667 %}
7668
7669 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7670 %{
7671 match(Set dst (SubL dst (LoadL src)));
7672 effect(KILL cr);
7673 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7674
7675 ins_cost(150);
7676 format %{ "subq $dst, $src\t# long" %}
7677 ins_encode %{
7678 __ subq($dst$$Register, $src$$Address);
7679 %}
7680 ins_pipe(ialu_reg_mem);
7681 %}
7682
7683 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7684 %{
7685 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7686 effect(KILL cr);
7687 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
7688
7689 ins_cost(150);
7690 format %{ "subq $dst, $src\t# long" %}
7691 ins_encode %{
7692 __ subq($dst$$Address, $src$$Register);
7693 %}
7694 ins_pipe(ialu_mem_reg);
7695 %}
7696
7697 // Subtract from a pointer
7698 // XXX hmpf???
7699 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
7700 %{
7701 match(Set dst (AddP dst (SubI zero src)));
7702 effect(KILL cr);
7703
7704 format %{ "subq $dst, $src\t# ptr - int" %}
7705 ins_encode %{
7706 __ subq($dst$$Register, $src$$Register);
7707 %}
7708 ins_pipe(ialu_reg_reg);
7709 %}
7710
7711 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
7712 %{
7713 match(Set dst (SubI zero dst));
7714 effect(KILL cr);
7715 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
7716
7717 format %{ "negl $dst\t# int" %}
7718 ins_encode %{
7719 __ negl($dst$$Register);
7720 %}
7721 ins_pipe(ialu_reg);
7722 %}
7723
7724 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
7725 %{
7726 match(Set dst (NegI dst));
7727 effect(KILL cr);
7728 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
7729
7730 format %{ "negl $dst\t# int" %}
7731 ins_encode %{
7732 __ negl($dst$$Register);
7733 %}
7734 ins_pipe(ialu_reg);
7735 %}
7736
7737 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
7738 %{
7739 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7740 effect(KILL cr);
7741 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
7742
7743 format %{ "negl $dst\t# int" %}
7744 ins_encode %{
7745 __ negl($dst$$Address);
7746 %}
7747 ins_pipe(ialu_reg);
7748 %}
7749
7750 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7751 %{
7752 match(Set dst (SubL zero dst));
7753 effect(KILL cr);
7754 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
7755
7756 format %{ "negq $dst\t# long" %}
7757 ins_encode %{
7758 __ negq($dst$$Register);
7759 %}
7760 ins_pipe(ialu_reg);
7761 %}
7762
7763 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
7764 %{
7765 match(Set dst (NegL dst));
7766 effect(KILL cr);
7767 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
7768
7769 format %{ "negq $dst\t# int" %}
7770 ins_encode %{
7771 __ negq($dst$$Register);
7772 %}
7773 ins_pipe(ialu_reg);
7774 %}
7775
7776 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7777 %{
7778 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7779 effect(KILL cr);
7780 flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
7781
7782 format %{ "negq $dst\t# long" %}
7783 ins_encode %{
7784 __ negq($dst$$Address);
7785 %}
7786 ins_pipe(ialu_reg);
7787 %}
7788
7789 //----------Multiplication/Division Instructions-------------------------------
7790 // Integer Multiplication Instructions
7791 // Multiply Register
7792
7793 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7794 %{
7795 match(Set dst (MulI dst src));
7796 effect(KILL cr);
7797
7798 ins_cost(300);
7799 format %{ "imull $dst, $src\t# int" %}
7800 ins_encode %{
7801 __ imull($dst$$Register, $src$$Register);
7802 %}
7803 ins_pipe(ialu_reg_reg_alu0);
7804 %}
7805
7806 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7807 %{
7808 match(Set dst (MulI src imm));
7809 effect(KILL cr);
7810
7811 ins_cost(300);
7812 format %{ "imull $dst, $src, $imm\t# int" %}
7813 ins_encode %{
7814 __ imull($dst$$Register, $src$$Register, $imm$$constant);
7815 %}
7816 ins_pipe(ialu_reg_reg_alu0);
7817 %}
7818
7819 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7820 %{
7821 match(Set dst (MulI dst (LoadI src)));
7822 effect(KILL cr);
7823
7824 ins_cost(350);
7825 format %{ "imull $dst, $src\t# int" %}
7826 ins_encode %{
7827 __ imull($dst$$Register, $src$$Address);
7828 %}
7829 ins_pipe(ialu_reg_mem_alu0);
7830 %}
7831
7832 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7833 %{
7834 match(Set dst (MulI (LoadI src) imm));
7835 effect(KILL cr);
7836
7837 ins_cost(300);
7838 format %{ "imull $dst, $src, $imm\t# int" %}
7839 ins_encode %{
7840 __ imull($dst$$Register, $src$$Address, $imm$$constant);
7841 %}
7842 ins_pipe(ialu_reg_mem_alu0);
7843 %}
7844
7845 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
7846 %{
7847 match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
7848 effect(KILL cr, KILL src2);
7849
7850 expand %{ mulI_rReg(dst, src1, cr);
7851 mulI_rReg(src2, src3, cr);
7852 addI_rReg(dst, src2, cr); %}
7853 %}
7854
7855 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7856 %{
7857 match(Set dst (MulL dst src));
7858 effect(KILL cr);
7859
7860 ins_cost(300);
7861 format %{ "imulq $dst, $src\t# long" %}
7862 ins_encode %{
7863 __ imulq($dst$$Register, $src$$Register);
7864 %}
7865 ins_pipe(ialu_reg_reg_alu0);
7866 %}
7867
7868 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7869 %{
7870 match(Set dst (MulL src imm));
7871 effect(KILL cr);
7872
7873 ins_cost(300);
7874 format %{ "imulq $dst, $src, $imm\t# long" %}
7875 ins_encode %{
7876 __ imulq($dst$$Register, $src$$Register, $imm$$constant);
7877 %}
7878 ins_pipe(ialu_reg_reg_alu0);
7879 %}
7880
7881 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7882 %{
7883 match(Set dst (MulL dst (LoadL src)));
7884 effect(KILL cr);
7885
7886 ins_cost(350);
7887 format %{ "imulq $dst, $src\t# long" %}
7888 ins_encode %{
7889 __ imulq($dst$$Register, $src$$Address);
7890 %}
7891 ins_pipe(ialu_reg_mem_alu0);
7892 %}
7893
7894 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7895 %{
7896 match(Set dst (MulL (LoadL src) imm));
7897 effect(KILL cr);
7898
7899 ins_cost(300);
7900 format %{ "imulq $dst, $src, $imm\t# long" %}
7901 ins_encode %{
7902 __ imulq($dst$$Register, $src$$Address, $imm$$constant);
7903 %}
7904 ins_pipe(ialu_reg_mem_alu0);
7905 %}
7906
7907 instruct mulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
7908 %{
7909 match(Set dst (MulHiL src rax));
7910 effect(USE_KILL rax, KILL cr);
7911
7912 ins_cost(300);
7913 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7914 ins_encode %{
7915 __ imulq($src$$Register);
7916 %}
7917 ins_pipe(ialu_reg_reg_alu0);
7918 %}
7919
7920 instruct umulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
7921 %{
7922 match(Set dst (UMulHiL src rax));
7923 effect(USE_KILL rax, KILL cr);
7924
7925 ins_cost(300);
7926 format %{ "mulq RDX:RAX, RAX, $src\t# umulhi" %}
7927 ins_encode %{
7928 __ mulq($src$$Register);
7929 %}
7930 ins_pipe(ialu_reg_reg_alu0);
7931 %}
7932
7933 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7934 rFlagsReg cr)
7935 %{
7936 match(Set rax (DivI rax div));
7937 effect(KILL rdx, KILL cr);
7938
7939 ins_cost(30*100+10*100); // XXX
7940 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7941 "jne,s normal\n\t"
7942 "xorl rdx, rdx\n\t"
7943 "cmpl $div, -1\n\t"
7944 "je,s done\n"
7945 "normal: cdql\n\t"
7946 "idivl $div\n"
7947 "done:" %}
7948 ins_encode(cdql_enc(div));
7949 ins_pipe(ialu_reg_reg_alu0);
7950 %}
7951
7952 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7953 rFlagsReg cr)
7954 %{
7955 match(Set rax (DivL rax div));
7956 effect(KILL rdx, KILL cr);
7957
7958 ins_cost(30*100+10*100); // XXX
7959 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7960 "cmpq rax, rdx\n\t"
7961 "jne,s normal\n\t"
7962 "xorl rdx, rdx\n\t"
7963 "cmpq $div, -1\n\t"
7964 "je,s done\n"
7965 "normal: cdqq\n\t"
7966 "idivq $div\n"
7967 "done:" %}
7968 ins_encode(cdqq_enc(div));
7969 ins_pipe(ialu_reg_reg_alu0);
7970 %}
7971
7972 instruct udivI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, rFlagsReg cr)
7973 %{
7974 match(Set rax (UDivI rax div));
7975 effect(KILL rdx, KILL cr);
7976
7977 ins_cost(300);
7978 format %{ "udivl $rax,$rax,$div\t# UDivI\n" %}
7979 ins_encode %{
7980 __ udivI($rax$$Register, $div$$Register, $rdx$$Register);
7981 %}
7982 ins_pipe(ialu_reg_reg_alu0);
7983 %}
7984
7985 instruct udivL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, rFlagsReg cr)
7986 %{
7987 match(Set rax (UDivL rax div));
7988 effect(KILL rdx, KILL cr);
7989
7990 ins_cost(300);
7991 format %{ "udivq $rax,$rax,$div\t# UDivL\n" %}
7992 ins_encode %{
7993 __ udivL($rax$$Register, $div$$Register, $rdx$$Register);
7994 %}
7995 ins_pipe(ialu_reg_reg_alu0);
7996 %}
7997
7998 // Integer DIVMOD with Register, both quotient and mod results
7999 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
8000 rFlagsReg cr)
8001 %{
8002 match(DivModI rax div);
8003 effect(KILL cr);
8004
8005 ins_cost(30*100+10*100); // XXX
8006 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
8007 "jne,s normal\n\t"
8008 "xorl rdx, rdx\n\t"
8009 "cmpl $div, -1\n\t"
8010 "je,s done\n"
8011 "normal: cdql\n\t"
8012 "idivl $div\n"
8013 "done:" %}
8014 ins_encode(cdql_enc(div));
8015 ins_pipe(pipe_slow);
8016 %}
8017
8018 // Long DIVMOD with Register, both quotient and mod results
8019 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
8020 rFlagsReg cr)
8021 %{
8022 match(DivModL rax div);
8023 effect(KILL cr);
8024
8025 ins_cost(30*100+10*100); // XXX
8026 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
8027 "cmpq rax, rdx\n\t"
8028 "jne,s normal\n\t"
8029 "xorl rdx, rdx\n\t"
8030 "cmpq $div, -1\n\t"
8031 "je,s done\n"
8032 "normal: cdqq\n\t"
8033 "idivq $div\n"
8034 "done:" %}
8035 ins_encode(cdqq_enc(div));
8036 ins_pipe(pipe_slow);
8037 %}
8038
8039 // Unsigned integer DIVMOD with Register, both quotient and mod results
8040 instruct udivModI_rReg_divmod(rax_RegI rax, no_rax_rdx_RegI tmp, rdx_RegI rdx,
8041 no_rax_rdx_RegI div, rFlagsReg cr)
8042 %{
8043 match(UDivModI rax div);
8044 effect(TEMP tmp, KILL cr);
8045
8046 ins_cost(300);
8047 format %{ "udivl $rax,$rax,$div\t# begin UDivModI\n\t"
8048 "umodl $rdx,$rax,$div\t! using $tmp as TEMP # end UDivModI\n"
8049 %}
8050 ins_encode %{
8051 __ udivmodI($rax$$Register, $div$$Register, $rdx$$Register, $tmp$$Register);
8052 %}
8053 ins_pipe(pipe_slow);
8054 %}
8055
8056 // Unsigned long DIVMOD with Register, both quotient and mod results
8057 instruct udivModL_rReg_divmod(rax_RegL rax, no_rax_rdx_RegL tmp, rdx_RegL rdx,
8058 no_rax_rdx_RegL div, rFlagsReg cr)
8059 %{
8060 match(UDivModL rax div);
8061 effect(TEMP tmp, KILL cr);
8062
8063 ins_cost(300);
8064 format %{ "udivq $rax,$rax,$div\t# begin UDivModL\n\t"
8065 "umodq $rdx,$rax,$div\t! using $tmp as TEMP # end UDivModL\n"
8066 %}
8067 ins_encode %{
8068 __ udivmodL($rax$$Register, $div$$Register, $rdx$$Register, $tmp$$Register);
8069 %}
8070 ins_pipe(pipe_slow);
8071 %}
8072
8073 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
8074 rFlagsReg cr)
8075 %{
8076 match(Set rdx (ModI rax div));
8077 effect(KILL rax, KILL cr);
8078
8079 ins_cost(300); // XXX
8080 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
8081 "jne,s normal\n\t"
8082 "xorl rdx, rdx\n\t"
8083 "cmpl $div, -1\n\t"
8084 "je,s done\n"
8085 "normal: cdql\n\t"
8086 "idivl $div\n"
8087 "done:" %}
8088 ins_encode(cdql_enc(div));
8089 ins_pipe(ialu_reg_reg_alu0);
8090 %}
8091
8092 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
8093 rFlagsReg cr)
8094 %{
8095 match(Set rdx (ModL rax div));
8096 effect(KILL rax, KILL cr);
8097
8098 ins_cost(300); // XXX
8099 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8100 "cmpq rax, rdx\n\t"
8101 "jne,s normal\n\t"
8102 "xorl rdx, rdx\n\t"
8103 "cmpq $div, -1\n\t"
8104 "je,s done\n"
8105 "normal: cdqq\n\t"
8106 "idivq $div\n"
8107 "done:" %}
8108 ins_encode(cdqq_enc(div));
8109 ins_pipe(ialu_reg_reg_alu0);
8110 %}
8111
8112 instruct umodI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, rFlagsReg cr)
8113 %{
8114 match(Set rdx (UModI rax div));
8115 effect(KILL rax, KILL cr);
8116
8117 ins_cost(300);
8118 format %{ "umodl $rdx,$rax,$div\t# UModI\n" %}
8119 ins_encode %{
8120 __ umodI($rax$$Register, $div$$Register, $rdx$$Register);
8121 %}
8122 ins_pipe(ialu_reg_reg_alu0);
8123 %}
8124
8125 instruct umodL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, rFlagsReg cr)
8126 %{
8127 match(Set rdx (UModL rax div));
8128 effect(KILL rax, KILL cr);
8129
8130 ins_cost(300);
8131 format %{ "umodq $rdx,$rax,$div\t# UModL\n" %}
8132 ins_encode %{
8133 __ umodL($rax$$Register, $div$$Register, $rdx$$Register);
8134 %}
8135 ins_pipe(ialu_reg_reg_alu0);
8136 %}
8137
8138 // Integer Shift Instructions
8139 // Shift Left by one, two, three
8140 instruct salI_rReg_immI2(rRegI dst, immI2 shift, rFlagsReg cr)
8141 %{
8142 match(Set dst (LShiftI dst shift));
8143 effect(KILL cr);
8144
8145 format %{ "sall $dst, $shift" %}
8146 ins_encode %{
8147 __ sall($dst$$Register, $shift$$constant);
8148 %}
8149 ins_pipe(ialu_reg);
8150 %}
8151
8152 // Shift Left by 8-bit immediate
8153 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8154 %{
8155 match(Set dst (LShiftI dst shift));
8156 effect(KILL cr);
8157
8158 format %{ "sall $dst, $shift" %}
8159 ins_encode %{
8160 __ sall($dst$$Register, $shift$$constant);
8161 %}
8162 ins_pipe(ialu_reg);
8163 %}
8164
8165 // Shift Left by 8-bit immediate
8166 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8167 %{
8168 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8169 effect(KILL cr);
8170
8171 format %{ "sall $dst, $shift" %}
8172 ins_encode %{
8173 __ sall($dst$$Address, $shift$$constant);
8174 %}
8175 ins_pipe(ialu_mem_imm);
8176 %}
8177
8178 // Shift Left by variable
8179 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8180 %{
8181 predicate(!VM_Version::supports_bmi2());
8182 match(Set dst (LShiftI dst shift));
8183 effect(KILL cr);
8184
8185 format %{ "sall $dst, $shift" %}
8186 ins_encode %{
8187 __ sall($dst$$Register);
8188 %}
8189 ins_pipe(ialu_reg_reg);
8190 %}
8191
8192 // Shift Left by variable
8193 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8194 %{
8195 predicate(!VM_Version::supports_bmi2());
8196 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8197 effect(KILL cr);
8198
8199 format %{ "sall $dst, $shift" %}
8200 ins_encode %{
8201 __ sall($dst$$Address);
8202 %}
8203 ins_pipe(ialu_mem_reg);
8204 %}
8205
8206 instruct salI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
8207 %{
8208 predicate(VM_Version::supports_bmi2());
8209 match(Set dst (LShiftI src shift));
8210
8211 format %{ "shlxl $dst, $src, $shift" %}
8212 ins_encode %{
8213 __ shlxl($dst$$Register, $src$$Register, $shift$$Register);
8214 %}
8215 ins_pipe(ialu_reg_reg);
8216 %}
8217
8218 instruct salI_mem_rReg(rRegI dst, memory src, rRegI shift)
8219 %{
8220 predicate(VM_Version::supports_bmi2());
8221 match(Set dst (LShiftI (LoadI src) shift));
8222 ins_cost(175);
8223 format %{ "shlxl $dst, $src, $shift" %}
8224 ins_encode %{
8225 __ shlxl($dst$$Register, $src$$Address, $shift$$Register);
8226 %}
8227 ins_pipe(ialu_reg_mem);
8228 %}
8229
8230 // Arithmetic Shift Right by 8-bit immediate
8231 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8232 %{
8233 match(Set dst (RShiftI dst shift));
8234 effect(KILL cr);
8235
8236 format %{ "sarl $dst, $shift" %}
8237 ins_encode %{
8238 __ sarl($dst$$Register, $shift$$constant);
8239 %}
8240 ins_pipe(ialu_mem_imm);
8241 %}
8242
8243 // Arithmetic Shift Right by 8-bit immediate
8244 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8245 %{
8246 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8247 effect(KILL cr);
8248
8249 format %{ "sarl $dst, $shift" %}
8250 ins_encode %{
8251 __ sarl($dst$$Address, $shift$$constant);
8252 %}
8253 ins_pipe(ialu_mem_imm);
8254 %}
8255
8256 // Arithmetic Shift Right by variable
8257 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8258 %{
8259 predicate(!VM_Version::supports_bmi2());
8260 match(Set dst (RShiftI dst shift));
8261 effect(KILL cr);
8262
8263 format %{ "sarl $dst, $shift" %}
8264 ins_encode %{
8265 __ sarl($dst$$Register);
8266 %}
8267 ins_pipe(ialu_reg_reg);
8268 %}
8269
8270 // Arithmetic Shift Right by variable
8271 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8272 %{
8273 predicate(!VM_Version::supports_bmi2());
8274 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8275 effect(KILL cr);
8276
8277 format %{ "sarl $dst, $shift" %}
8278 ins_encode %{
8279 __ sarl($dst$$Address);
8280 %}
8281 ins_pipe(ialu_mem_reg);
8282 %}
8283
8284 instruct sarI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
8285 %{
8286 predicate(VM_Version::supports_bmi2());
8287 match(Set dst (RShiftI src shift));
8288
8289 format %{ "sarxl $dst, $src, $shift" %}
8290 ins_encode %{
8291 __ sarxl($dst$$Register, $src$$Register, $shift$$Register);
8292 %}
8293 ins_pipe(ialu_reg_reg);
8294 %}
8295
8296 instruct sarI_mem_rReg(rRegI dst, memory src, rRegI shift)
8297 %{
8298 predicate(VM_Version::supports_bmi2());
8299 match(Set dst (RShiftI (LoadI src) shift));
8300 ins_cost(175);
8301 format %{ "sarxl $dst, $src, $shift" %}
8302 ins_encode %{
8303 __ sarxl($dst$$Register, $src$$Address, $shift$$Register);
8304 %}
8305 ins_pipe(ialu_reg_mem);
8306 %}
8307
8308 // Logical Shift Right by 8-bit immediate
8309 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8310 %{
8311 match(Set dst (URShiftI dst shift));
8312 effect(KILL cr);
8313
8314 format %{ "shrl $dst, $shift" %}
8315 ins_encode %{
8316 __ shrl($dst$$Register, $shift$$constant);
8317 %}
8318 ins_pipe(ialu_reg);
8319 %}
8320
8321 // Logical Shift Right by 8-bit immediate
8322 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8323 %{
8324 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8325 effect(KILL cr);
8326
8327 format %{ "shrl $dst, $shift" %}
8328 ins_encode %{
8329 __ shrl($dst$$Address, $shift$$constant);
8330 %}
8331 ins_pipe(ialu_mem_imm);
8332 %}
8333
8334 // Logical Shift Right by variable
8335 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8336 %{
8337 predicate(!VM_Version::supports_bmi2());
8338 match(Set dst (URShiftI dst shift));
8339 effect(KILL cr);
8340
8341 format %{ "shrl $dst, $shift" %}
8342 ins_encode %{
8343 __ shrl($dst$$Register);
8344 %}
8345 ins_pipe(ialu_reg_reg);
8346 %}
8347
8348 // Logical Shift Right by variable
8349 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8350 %{
8351 predicate(!VM_Version::supports_bmi2());
8352 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8353 effect(KILL cr);
8354
8355 format %{ "shrl $dst, $shift" %}
8356 ins_encode %{
8357 __ shrl($dst$$Address);
8358 %}
8359 ins_pipe(ialu_mem_reg);
8360 %}
8361
8362 instruct shrI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
8363 %{
8364 predicate(VM_Version::supports_bmi2());
8365 match(Set dst (URShiftI src shift));
8366
8367 format %{ "shrxl $dst, $src, $shift" %}
8368 ins_encode %{
8369 __ shrxl($dst$$Register, $src$$Register, $shift$$Register);
8370 %}
8371 ins_pipe(ialu_reg_reg);
8372 %}
8373
8374 instruct shrI_mem_rReg(rRegI dst, memory src, rRegI shift)
8375 %{
8376 predicate(VM_Version::supports_bmi2());
8377 match(Set dst (URShiftI (LoadI src) shift));
8378 ins_cost(175);
8379 format %{ "shrxl $dst, $src, $shift" %}
8380 ins_encode %{
8381 __ shrxl($dst$$Register, $src$$Address, $shift$$Register);
8382 %}
8383 ins_pipe(ialu_reg_mem);
8384 %}
8385
8386 // Long Shift Instructions
8387 // Shift Left by one, two, three
8388 instruct salL_rReg_immI2(rRegL dst, immI2 shift, rFlagsReg cr)
8389 %{
8390 match(Set dst (LShiftL dst shift));
8391 effect(KILL cr);
8392
8393 format %{ "salq $dst, $shift" %}
8394 ins_encode %{
8395 __ salq($dst$$Register, $shift$$constant);
8396 %}
8397 ins_pipe(ialu_reg);
8398 %}
8399
8400 // Shift Left by 8-bit immediate
8401 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8402 %{
8403 match(Set dst (LShiftL dst shift));
8404 effect(KILL cr);
8405
8406 format %{ "salq $dst, $shift" %}
8407 ins_encode %{
8408 __ salq($dst$$Register, $shift$$constant);
8409 %}
8410 ins_pipe(ialu_reg);
8411 %}
8412
8413 // Shift Left by 8-bit immediate
8414 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8415 %{
8416 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8417 effect(KILL cr);
8418
8419 format %{ "salq $dst, $shift" %}
8420 ins_encode %{
8421 __ salq($dst$$Address, $shift$$constant);
8422 %}
8423 ins_pipe(ialu_mem_imm);
8424 %}
8425
8426 // Shift Left by variable
8427 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8428 %{
8429 predicate(!VM_Version::supports_bmi2());
8430 match(Set dst (LShiftL dst shift));
8431 effect(KILL cr);
8432
8433 format %{ "salq $dst, $shift" %}
8434 ins_encode %{
8435 __ salq($dst$$Register);
8436 %}
8437 ins_pipe(ialu_reg_reg);
8438 %}
8439
8440 // Shift Left by variable
8441 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8442 %{
8443 predicate(!VM_Version::supports_bmi2());
8444 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8445 effect(KILL cr);
8446
8447 format %{ "salq $dst, $shift" %}
8448 ins_encode %{
8449 __ salq($dst$$Address);
8450 %}
8451 ins_pipe(ialu_mem_reg);
8452 %}
8453
8454 instruct salL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
8455 %{
8456 predicate(VM_Version::supports_bmi2());
8457 match(Set dst (LShiftL src shift));
8458
8459 format %{ "shlxq $dst, $src, $shift" %}
8460 ins_encode %{
8461 __ shlxq($dst$$Register, $src$$Register, $shift$$Register);
8462 %}
8463 ins_pipe(ialu_reg_reg);
8464 %}
8465
8466 instruct salL_mem_rReg(rRegL dst, memory src, rRegI shift)
8467 %{
8468 predicate(VM_Version::supports_bmi2());
8469 match(Set dst (LShiftL (LoadL src) shift));
8470 ins_cost(175);
8471 format %{ "shlxq $dst, $src, $shift" %}
8472 ins_encode %{
8473 __ shlxq($dst$$Register, $src$$Address, $shift$$Register);
8474 %}
8475 ins_pipe(ialu_reg_mem);
8476 %}
8477
8478 // Arithmetic Shift Right by 8-bit immediate
8479 instruct sarL_rReg_imm(rRegL dst, immI shift, rFlagsReg cr)
8480 %{
8481 match(Set dst (RShiftL dst shift));
8482 effect(KILL cr);
8483
8484 format %{ "sarq $dst, $shift" %}
8485 ins_encode %{
8486 __ sarq($dst$$Register, (unsigned char)($shift$$constant & 0x3F));
8487 %}
8488 ins_pipe(ialu_mem_imm);
8489 %}
8490
8491 // Arithmetic Shift Right by 8-bit immediate
8492 instruct sarL_mem_imm(memory dst, immI shift, rFlagsReg cr)
8493 %{
8494 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8495 effect(KILL cr);
8496
8497 format %{ "sarq $dst, $shift" %}
8498 ins_encode %{
8499 __ sarq($dst$$Address, (unsigned char)($shift$$constant & 0x3F));
8500 %}
8501 ins_pipe(ialu_mem_imm);
8502 %}
8503
8504 // Arithmetic Shift Right by variable
8505 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8506 %{
8507 predicate(!VM_Version::supports_bmi2());
8508 match(Set dst (RShiftL dst shift));
8509 effect(KILL cr);
8510
8511 format %{ "sarq $dst, $shift" %}
8512 ins_encode %{
8513 __ sarq($dst$$Register);
8514 %}
8515 ins_pipe(ialu_reg_reg);
8516 %}
8517
8518 // Arithmetic Shift Right by variable
8519 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8520 %{
8521 predicate(!VM_Version::supports_bmi2());
8522 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8523 effect(KILL cr);
8524
8525 format %{ "sarq $dst, $shift" %}
8526 ins_encode %{
8527 __ sarq($dst$$Address);
8528 %}
8529 ins_pipe(ialu_mem_reg);
8530 %}
8531
8532 instruct sarL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
8533 %{
8534 predicate(VM_Version::supports_bmi2());
8535 match(Set dst (RShiftL src shift));
8536
8537 format %{ "sarxq $dst, $src, $shift" %}
8538 ins_encode %{
8539 __ sarxq($dst$$Register, $src$$Register, $shift$$Register);
8540 %}
8541 ins_pipe(ialu_reg_reg);
8542 %}
8543
8544 instruct sarL_mem_rReg(rRegL dst, memory src, rRegI shift)
8545 %{
8546 predicate(VM_Version::supports_bmi2());
8547 match(Set dst (RShiftL (LoadL src) shift));
8548 ins_cost(175);
8549 format %{ "sarxq $dst, $src, $shift" %}
8550 ins_encode %{
8551 __ sarxq($dst$$Register, $src$$Address, $shift$$Register);
8552 %}
8553 ins_pipe(ialu_reg_mem);
8554 %}
8555
8556 // Logical Shift Right by 8-bit immediate
8557 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8558 %{
8559 match(Set dst (URShiftL dst shift));
8560 effect(KILL cr);
8561
8562 format %{ "shrq $dst, $shift" %}
8563 ins_encode %{
8564 __ shrq($dst$$Register, $shift$$constant);
8565 %}
8566 ins_pipe(ialu_reg);
8567 %}
8568
8569 // Logical Shift Right by 8-bit immediate
8570 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8571 %{
8572 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8573 effect(KILL cr);
8574
8575 format %{ "shrq $dst, $shift" %}
8576 ins_encode %{
8577 __ shrq($dst$$Address, $shift$$constant);
8578 %}
8579 ins_pipe(ialu_mem_imm);
8580 %}
8581
8582 // Logical Shift Right by variable
8583 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8584 %{
8585 predicate(!VM_Version::supports_bmi2());
8586 match(Set dst (URShiftL dst shift));
8587 effect(KILL cr);
8588
8589 format %{ "shrq $dst, $shift" %}
8590 ins_encode %{
8591 __ shrq($dst$$Register);
8592 %}
8593 ins_pipe(ialu_reg_reg);
8594 %}
8595
8596 // Logical Shift Right by variable
8597 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8598 %{
8599 predicate(!VM_Version::supports_bmi2());
8600 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8601 effect(KILL cr);
8602
8603 format %{ "shrq $dst, $shift" %}
8604 ins_encode %{
8605 __ shrq($dst$$Address);
8606 %}
8607 ins_pipe(ialu_mem_reg);
8608 %}
8609
8610 instruct shrL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
8611 %{
8612 predicate(VM_Version::supports_bmi2());
8613 match(Set dst (URShiftL src shift));
8614
8615 format %{ "shrxq $dst, $src, $shift" %}
8616 ins_encode %{
8617 __ shrxq($dst$$Register, $src$$Register, $shift$$Register);
8618 %}
8619 ins_pipe(ialu_reg_reg);
8620 %}
8621
8622 instruct shrL_mem_rReg(rRegL dst, memory src, rRegI shift)
8623 %{
8624 predicate(VM_Version::supports_bmi2());
8625 match(Set dst (URShiftL (LoadL src) shift));
8626 ins_cost(175);
8627 format %{ "shrxq $dst, $src, $shift" %}
8628 ins_encode %{
8629 __ shrxq($dst$$Register, $src$$Address, $shift$$Register);
8630 %}
8631 ins_pipe(ialu_reg_mem);
8632 %}
8633
8634 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8635 // This idiom is used by the compiler for the i2b bytecode.
8636 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8637 %{
8638 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8639
8640 format %{ "movsbl $dst, $src\t# i2b" %}
8641 ins_encode %{
8642 __ movsbl($dst$$Register, $src$$Register);
8643 %}
8644 ins_pipe(ialu_reg_reg);
8645 %}
8646
8647 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8648 // This idiom is used by the compiler the i2s bytecode.
8649 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8650 %{
8651 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8652
8653 format %{ "movswl $dst, $src\t# i2s" %}
8654 ins_encode %{
8655 __ movswl($dst$$Register, $src$$Register);
8656 %}
8657 ins_pipe(ialu_reg_reg);
8658 %}
8659
8660 // ROL/ROR instructions
8661
8662 // Rotate left by constant.
8663 instruct rolI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
8664 %{
8665 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
8666 match(Set dst (RotateLeft dst shift));
8667 effect(KILL cr);
8668 format %{ "roll $dst, $shift" %}
8669 ins_encode %{
8670 __ roll($dst$$Register, $shift$$constant);
8671 %}
8672 ins_pipe(ialu_reg);
8673 %}
8674
8675 instruct rolI_immI8(rRegI dst, rRegI src, immI8 shift)
8676 %{
8677 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
8678 match(Set dst (RotateLeft src shift));
8679 format %{ "rolxl $dst, $src, $shift" %}
8680 ins_encode %{
8681 int shift = 32 - ($shift$$constant & 31);
8682 __ rorxl($dst$$Register, $src$$Register, shift);
8683 %}
8684 ins_pipe(ialu_reg_reg);
8685 %}
8686
8687 instruct rolI_mem_immI8(rRegI dst, memory src, immI8 shift)
8688 %{
8689 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
8690 match(Set dst (RotateLeft (LoadI src) shift));
8691 ins_cost(175);
8692 format %{ "rolxl $dst, $src, $shift" %}
8693 ins_encode %{
8694 int shift = 32 - ($shift$$constant & 31);
8695 __ rorxl($dst$$Register, $src$$Address, shift);
8696 %}
8697 ins_pipe(ialu_reg_mem);
8698 %}
8699
8700 // Rotate Left by variable
8701 instruct rolI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8702 %{
8703 predicate(n->bottom_type()->basic_type() == T_INT);
8704 match(Set dst (RotateLeft dst shift));
8705 effect(KILL cr);
8706 format %{ "roll $dst, $shift" %}
8707 ins_encode %{
8708 __ roll($dst$$Register);
8709 %}
8710 ins_pipe(ialu_reg_reg);
8711 %}
8712
8713 // Rotate Right by constant.
8714 instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
8715 %{
8716 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
8717 match(Set dst (RotateRight dst shift));
8718 effect(KILL cr);
8719 format %{ "rorl $dst, $shift" %}
8720 ins_encode %{
8721 __ rorl($dst$$Register, $shift$$constant);
8722 %}
8723 ins_pipe(ialu_reg);
8724 %}
8725
8726 // Rotate Right by constant.
8727 instruct rorI_immI8(rRegI dst, rRegI src, immI8 shift)
8728 %{
8729 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
8730 match(Set dst (RotateRight src shift));
8731 format %{ "rorxl $dst, $src, $shift" %}
8732 ins_encode %{
8733 __ rorxl($dst$$Register, $src$$Register, $shift$$constant);
8734 %}
8735 ins_pipe(ialu_reg_reg);
8736 %}
8737
8738 instruct rorI_mem_immI8(rRegI dst, memory src, immI8 shift)
8739 %{
8740 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
8741 match(Set dst (RotateRight (LoadI src) shift));
8742 ins_cost(175);
8743 format %{ "rorxl $dst, $src, $shift" %}
8744 ins_encode %{
8745 __ rorxl($dst$$Register, $src$$Address, $shift$$constant);
8746 %}
8747 ins_pipe(ialu_reg_mem);
8748 %}
8749
8750 // Rotate Right by variable
8751 instruct rorI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8752 %{
8753 predicate(n->bottom_type()->basic_type() == T_INT);
8754 match(Set dst (RotateRight dst shift));
8755 effect(KILL cr);
8756 format %{ "rorl $dst, $shift" %}
8757 ins_encode %{
8758 __ rorl($dst$$Register);
8759 %}
8760 ins_pipe(ialu_reg_reg);
8761 %}
8762
8763 // Rotate Left by constant.
8764 instruct rolL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
8765 %{
8766 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
8767 match(Set dst (RotateLeft dst shift));
8768 effect(KILL cr);
8769 format %{ "rolq $dst, $shift" %}
8770 ins_encode %{
8771 __ rolq($dst$$Register, $shift$$constant);
8772 %}
8773 ins_pipe(ialu_reg);
8774 %}
8775
8776 instruct rolL_immI8(rRegL dst, rRegL src, immI8 shift)
8777 %{
8778 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
8779 match(Set dst (RotateLeft src shift));
8780 format %{ "rolxq $dst, $src, $shift" %}
8781 ins_encode %{
8782 int shift = 64 - ($shift$$constant & 63);
8783 __ rorxq($dst$$Register, $src$$Register, shift);
8784 %}
8785 ins_pipe(ialu_reg_reg);
8786 %}
8787
8788 instruct rolL_mem_immI8(rRegL dst, memory src, immI8 shift)
8789 %{
8790 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
8791 match(Set dst (RotateLeft (LoadL src) shift));
8792 ins_cost(175);
8793 format %{ "rolxq $dst, $src, $shift" %}
8794 ins_encode %{
8795 int shift = 64 - ($shift$$constant & 63);
8796 __ rorxq($dst$$Register, $src$$Address, shift);
8797 %}
8798 ins_pipe(ialu_reg_mem);
8799 %}
8800
8801 // Rotate Left by variable
8802 instruct rolL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8803 %{
8804 predicate(n->bottom_type()->basic_type() == T_LONG);
8805 match(Set dst (RotateLeft dst shift));
8806 effect(KILL cr);
8807 format %{ "rolq $dst, $shift" %}
8808 ins_encode %{
8809 __ rolq($dst$$Register);
8810 %}
8811 ins_pipe(ialu_reg_reg);
8812 %}
8813
8814 // Rotate Right by constant.
8815 instruct rorL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
8816 %{
8817 predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
8818 match(Set dst (RotateRight dst shift));
8819 effect(KILL cr);
8820 format %{ "rorq $dst, $shift" %}
8821 ins_encode %{
8822 __ rorq($dst$$Register, $shift$$constant);
8823 %}
8824 ins_pipe(ialu_reg);
8825 %}
8826
8827 // Rotate Right by constant
8828 instruct rorL_immI8(rRegL dst, rRegL src, immI8 shift)
8829 %{
8830 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
8831 match(Set dst (RotateRight src shift));
8832 format %{ "rorxq $dst, $src, $shift" %}
8833 ins_encode %{
8834 __ rorxq($dst$$Register, $src$$Register, $shift$$constant);
8835 %}
8836 ins_pipe(ialu_reg_reg);
8837 %}
8838
8839 instruct rorL_mem_immI8(rRegL dst, memory src, immI8 shift)
8840 %{
8841 predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
8842 match(Set dst (RotateRight (LoadL src) shift));
8843 ins_cost(175);
8844 format %{ "rorxq $dst, $src, $shift" %}
8845 ins_encode %{
8846 __ rorxq($dst$$Register, $src$$Address, $shift$$constant);
8847 %}
8848 ins_pipe(ialu_reg_mem);
8849 %}
8850
8851 // Rotate Right by variable
8852 instruct rorL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8853 %{
8854 predicate(n->bottom_type()->basic_type() == T_LONG);
8855 match(Set dst (RotateRight dst shift));
8856 effect(KILL cr);
8857 format %{ "rorq $dst, $shift" %}
8858 ins_encode %{
8859 __ rorq($dst$$Register);
8860 %}
8861 ins_pipe(ialu_reg_reg);
8862 %}
8863
8864 //----------------------------- CompressBits/ExpandBits ------------------------
8865
8866 instruct compressBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{
8867 predicate(n->bottom_type()->isa_long());
8868 match(Set dst (CompressBits src mask));
8869 format %{ "pextq $dst, $src, $mask\t! parallel bit extract" %}
8870 ins_encode %{
8871 __ pextq($dst$$Register, $src$$Register, $mask$$Register);
8872 %}
8873 ins_pipe( pipe_slow );
8874 %}
8875
8876 instruct expandBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{
8877 predicate(n->bottom_type()->isa_long());
8878 match(Set dst (ExpandBits src mask));
8879 format %{ "pdepq $dst, $src, $mask\t! parallel bit deposit" %}
8880 ins_encode %{
8881 __ pdepq($dst$$Register, $src$$Register, $mask$$Register);
8882 %}
8883 ins_pipe( pipe_slow );
8884 %}
8885
8886 instruct compressBitsL_mem(rRegL dst, rRegL src, memory mask) %{
8887 predicate(n->bottom_type()->isa_long());
8888 match(Set dst (CompressBits src (LoadL mask)));
8889 format %{ "pextq $dst, $src, $mask\t! parallel bit extract" %}
8890 ins_encode %{
8891 __ pextq($dst$$Register, $src$$Register, $mask$$Address);
8892 %}
8893 ins_pipe( pipe_slow );
8894 %}
8895
8896 instruct expandBitsL_mem(rRegL dst, rRegL src, memory mask) %{
8897 predicate(n->bottom_type()->isa_long());
8898 match(Set dst (ExpandBits src (LoadL mask)));
8899 format %{ "pdepq $dst, $src, $mask\t! parallel bit deposit" %}
8900 ins_encode %{
8901 __ pdepq($dst$$Register, $src$$Register, $mask$$Address);
8902 %}
8903 ins_pipe( pipe_slow );
8904 %}
8905
8906
8907 // Logical Instructions
8908
8909 // Integer Logical Instructions
8910
8911 // And Instructions
8912 // And Register with Register
8913 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8914 %{
8915 match(Set dst (AndI dst src));
8916 effect(KILL cr);
8917 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
8918
8919 format %{ "andl $dst, $src\t# int" %}
8920 ins_encode %{
8921 __ andl($dst$$Register, $src$$Register);
8922 %}
8923 ins_pipe(ialu_reg_reg);
8924 %}
8925
8926 // And Register with Immediate 255
8927 instruct andI_rReg_imm255(rRegI dst, rRegI src, immI_255 mask)
8928 %{
8929 match(Set dst (AndI src mask));
8930
8931 format %{ "movzbl $dst, $src\t# int & 0xFF" %}
8932 ins_encode %{
8933 __ movzbl($dst$$Register, $src$$Register);
8934 %}
8935 ins_pipe(ialu_reg);
8936 %}
8937
8938 // And Register with Immediate 255 and promote to long
8939 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8940 %{
8941 match(Set dst (ConvI2L (AndI src mask)));
8942
8943 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8944 ins_encode %{
8945 __ movzbl($dst$$Register, $src$$Register);
8946 %}
8947 ins_pipe(ialu_reg);
8948 %}
8949
8950 // And Register with Immediate 65535
8951 instruct andI_rReg_imm65535(rRegI dst, rRegI src, immI_65535 mask)
8952 %{
8953 match(Set dst (AndI src mask));
8954
8955 format %{ "movzwl $dst, $src\t# int & 0xFFFF" %}
8956 ins_encode %{
8957 __ movzwl($dst$$Register, $src$$Register);
8958 %}
8959 ins_pipe(ialu_reg);
8960 %}
8961
8962 // And Register with Immediate 65535 and promote to long
8963 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8964 %{
8965 match(Set dst (ConvI2L (AndI src mask)));
8966
8967 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8968 ins_encode %{
8969 __ movzwl($dst$$Register, $src$$Register);
8970 %}
8971 ins_pipe(ialu_reg);
8972 %}
8973
8974 // Can skip int2long conversions after AND with small bitmask
8975 instruct convI2LAndI_reg_immIbitmask(rRegL dst, rRegI src, immI_Pow2M1 mask, rRegI tmp, rFlagsReg cr)
8976 %{
8977 predicate(VM_Version::supports_bmi2());
8978 ins_cost(125);
8979 effect(TEMP tmp, KILL cr);
8980 match(Set dst (ConvI2L (AndI src mask)));
8981 format %{ "bzhiq $dst, $src, $mask \t# using $tmp as TEMP, int & immI_Pow2M1 -> long" %}
8982 ins_encode %{
8983 __ movl($tmp$$Register, exact_log2($mask$$constant + 1));
8984 __ bzhiq($dst$$Register, $src$$Register, $tmp$$Register);
8985 %}
8986 ins_pipe(ialu_reg_reg);
8987 %}
8988
8989 // And Register with Immediate
8990 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8991 %{
8992 match(Set dst (AndI dst src));
8993 effect(KILL cr);
8994 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
8995
8996 format %{ "andl $dst, $src\t# int" %}
8997 ins_encode %{
8998 __ andl($dst$$Register, $src$$constant);
8999 %}
9000 ins_pipe(ialu_reg);
9001 %}
9002
9003 // And Register with Memory
9004 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9005 %{
9006 match(Set dst (AndI dst (LoadI src)));
9007 effect(KILL cr);
9008 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9009
9010 ins_cost(150);
9011 format %{ "andl $dst, $src\t# int" %}
9012 ins_encode %{
9013 __ andl($dst$$Register, $src$$Address);
9014 %}
9015 ins_pipe(ialu_reg_mem);
9016 %}
9017
9018 // And Memory with Register
9019 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9020 %{
9021 match(Set dst (StoreB dst (AndI (LoadB dst) src)));
9022 effect(KILL cr);
9023 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9024
9025 ins_cost(150);
9026 format %{ "andb $dst, $src\t# byte" %}
9027 ins_encode %{
9028 __ andb($dst$$Address, $src$$Register);
9029 %}
9030 ins_pipe(ialu_mem_reg);
9031 %}
9032
9033 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9034 %{
9035 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9036 effect(KILL cr);
9037 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9038
9039 ins_cost(150);
9040 format %{ "andl $dst, $src\t# int" %}
9041 ins_encode %{
9042 __ andl($dst$$Address, $src$$Register);
9043 %}
9044 ins_pipe(ialu_mem_reg);
9045 %}
9046
9047 // And Memory with Immediate
9048 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
9049 %{
9050 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
9051 effect(KILL cr);
9052 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9053
9054 ins_cost(125);
9055 format %{ "andl $dst, $src\t# int" %}
9056 ins_encode %{
9057 __ andl($dst$$Address, $src$$constant);
9058 %}
9059 ins_pipe(ialu_mem_imm);
9060 %}
9061
9062 // BMI1 instructions
9063 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
9064 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
9065 predicate(UseBMI1Instructions);
9066 effect(KILL cr);
9067 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9068
9069 ins_cost(125);
9070 format %{ "andnl $dst, $src1, $src2" %}
9071
9072 ins_encode %{
9073 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
9074 %}
9075 ins_pipe(ialu_reg_mem);
9076 %}
9077
9078 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
9079 match(Set dst (AndI (XorI src1 minus_1) src2));
9080 predicate(UseBMI1Instructions);
9081 effect(KILL cr);
9082 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9083
9084 format %{ "andnl $dst, $src1, $src2" %}
9085
9086 ins_encode %{
9087 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
9088 %}
9089 ins_pipe(ialu_reg);
9090 %}
9091
9092 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
9093 match(Set dst (AndI (SubI imm_zero src) src));
9094 predicate(UseBMI1Instructions);
9095 effect(KILL cr);
9096 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9097
9098 format %{ "blsil $dst, $src" %}
9099
9100 ins_encode %{
9101 __ blsil($dst$$Register, $src$$Register);
9102 %}
9103 ins_pipe(ialu_reg);
9104 %}
9105
9106 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
9107 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
9108 predicate(UseBMI1Instructions);
9109 effect(KILL cr);
9110 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9111
9112 ins_cost(125);
9113 format %{ "blsil $dst, $src" %}
9114
9115 ins_encode %{
9116 __ blsil($dst$$Register, $src$$Address);
9117 %}
9118 ins_pipe(ialu_reg_mem);
9119 %}
9120
9121 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9122 %{
9123 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
9124 predicate(UseBMI1Instructions);
9125 effect(KILL cr);
9126 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
9127
9128 ins_cost(125);
9129 format %{ "blsmskl $dst, $src" %}
9130
9131 ins_encode %{
9132 __ blsmskl($dst$$Register, $src$$Address);
9133 %}
9134 ins_pipe(ialu_reg_mem);
9135 %}
9136
9137 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9138 %{
9139 match(Set dst (XorI (AddI src minus_1) src));
9140 predicate(UseBMI1Instructions);
9141 effect(KILL cr);
9142 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
9143
9144 format %{ "blsmskl $dst, $src" %}
9145
9146 ins_encode %{
9147 __ blsmskl($dst$$Register, $src$$Register);
9148 %}
9149
9150 ins_pipe(ialu_reg);
9151 %}
9152
9153 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
9154 %{
9155 match(Set dst (AndI (AddI src minus_1) src) );
9156 predicate(UseBMI1Instructions);
9157 effect(KILL cr);
9158 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9159
9160 format %{ "blsrl $dst, $src" %}
9161
9162 ins_encode %{
9163 __ blsrl($dst$$Register, $src$$Register);
9164 %}
9165
9166 ins_pipe(ialu_reg_mem);
9167 %}
9168
9169 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
9170 %{
9171 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
9172 predicate(UseBMI1Instructions);
9173 effect(KILL cr);
9174 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9175
9176 ins_cost(125);
9177 format %{ "blsrl $dst, $src" %}
9178
9179 ins_encode %{
9180 __ blsrl($dst$$Register, $src$$Address);
9181 %}
9182
9183 ins_pipe(ialu_reg);
9184 %}
9185
9186 // Or Instructions
9187 // Or Register with Register
9188 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9189 %{
9190 match(Set dst (OrI dst src));
9191 effect(KILL cr);
9192 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9193
9194 format %{ "orl $dst, $src\t# int" %}
9195 ins_encode %{
9196 __ orl($dst$$Register, $src$$Register);
9197 %}
9198 ins_pipe(ialu_reg_reg);
9199 %}
9200
9201 // Or Register with Immediate
9202 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9203 %{
9204 match(Set dst (OrI dst src));
9205 effect(KILL cr);
9206 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9207
9208 format %{ "orl $dst, $src\t# int" %}
9209 ins_encode %{
9210 __ orl($dst$$Register, $src$$constant);
9211 %}
9212 ins_pipe(ialu_reg);
9213 %}
9214
9215 // Or Register with Memory
9216 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9217 %{
9218 match(Set dst (OrI dst (LoadI src)));
9219 effect(KILL cr);
9220 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9221
9222 ins_cost(150);
9223 format %{ "orl $dst, $src\t# int" %}
9224 ins_encode %{
9225 __ orl($dst$$Register, $src$$Address);
9226 %}
9227 ins_pipe(ialu_reg_mem);
9228 %}
9229
9230 // Or Memory with Register
9231 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9232 %{
9233 match(Set dst (StoreB dst (OrI (LoadB dst) src)));
9234 effect(KILL cr);
9235 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9236
9237 ins_cost(150);
9238 format %{ "orb $dst, $src\t# byte" %}
9239 ins_encode %{
9240 __ orb($dst$$Address, $src$$Register);
9241 %}
9242 ins_pipe(ialu_mem_reg);
9243 %}
9244
9245 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9246 %{
9247 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9248 effect(KILL cr);
9249 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9250
9251 ins_cost(150);
9252 format %{ "orl $dst, $src\t# int" %}
9253 ins_encode %{
9254 __ orl($dst$$Address, $src$$Register);
9255 %}
9256 ins_pipe(ialu_mem_reg);
9257 %}
9258
9259 // Or Memory with Immediate
9260 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9261 %{
9262 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9263 effect(KILL cr);
9264 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9265
9266 ins_cost(125);
9267 format %{ "orl $dst, $src\t# int" %}
9268 ins_encode %{
9269 __ orl($dst$$Address, $src$$constant);
9270 %}
9271 ins_pipe(ialu_mem_imm);
9272 %}
9273
9274 // Xor Instructions
9275 // Xor Register with Register
9276 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9277 %{
9278 match(Set dst (XorI dst src));
9279 effect(KILL cr);
9280 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9281
9282 format %{ "xorl $dst, $src\t# int" %}
9283 ins_encode %{
9284 __ xorl($dst$$Register, $src$$Register);
9285 %}
9286 ins_pipe(ialu_reg_reg);
9287 %}
9288
9289 // Xor Register with Immediate -1
9290 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9291 match(Set dst (XorI dst imm));
9292
9293 format %{ "not $dst" %}
9294 ins_encode %{
9295 __ notl($dst$$Register);
9296 %}
9297 ins_pipe(ialu_reg);
9298 %}
9299
9300 // Xor Register with Immediate
9301 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9302 %{
9303 match(Set dst (XorI dst src));
9304 effect(KILL cr);
9305 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9306
9307 format %{ "xorl $dst, $src\t# int" %}
9308 ins_encode %{
9309 __ xorl($dst$$Register, $src$$constant);
9310 %}
9311 ins_pipe(ialu_reg);
9312 %}
9313
9314 // Xor Register with Memory
9315 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9316 %{
9317 match(Set dst (XorI dst (LoadI src)));
9318 effect(KILL cr);
9319 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9320
9321 ins_cost(150);
9322 format %{ "xorl $dst, $src\t# int" %}
9323 ins_encode %{
9324 __ xorl($dst$$Register, $src$$Address);
9325 %}
9326 ins_pipe(ialu_reg_mem);
9327 %}
9328
9329 // Xor Memory with Register
9330 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9331 %{
9332 match(Set dst (StoreB dst (XorI (LoadB dst) src)));
9333 effect(KILL cr);
9334 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9335
9336 ins_cost(150);
9337 format %{ "xorb $dst, $src\t# byte" %}
9338 ins_encode %{
9339 __ xorb($dst$$Address, $src$$Register);
9340 %}
9341 ins_pipe(ialu_mem_reg);
9342 %}
9343
9344 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9345 %{
9346 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9347 effect(KILL cr);
9348 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9349
9350 ins_cost(150);
9351 format %{ "xorl $dst, $src\t# int" %}
9352 ins_encode %{
9353 __ xorl($dst$$Address, $src$$Register);
9354 %}
9355 ins_pipe(ialu_mem_reg);
9356 %}
9357
9358 // Xor Memory with Immediate
9359 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9360 %{
9361 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9362 effect(KILL cr);
9363 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9364
9365 ins_cost(125);
9366 format %{ "xorl $dst, $src\t# int" %}
9367 ins_encode %{
9368 __ xorl($dst$$Address, $src$$constant);
9369 %}
9370 ins_pipe(ialu_mem_imm);
9371 %}
9372
9373
9374 // Long Logical Instructions
9375
9376 // And Instructions
9377 // And Register with Register
9378 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9379 %{
9380 match(Set dst (AndL dst src));
9381 effect(KILL cr);
9382 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9383
9384 format %{ "andq $dst, $src\t# long" %}
9385 ins_encode %{
9386 __ andq($dst$$Register, $src$$Register);
9387 %}
9388 ins_pipe(ialu_reg_reg);
9389 %}
9390
9391 // And Register with Immediate 255
9392 instruct andL_rReg_imm255(rRegL dst, rRegL src, immL_255 mask)
9393 %{
9394 match(Set dst (AndL src mask));
9395
9396 format %{ "movzbl $dst, $src\t# long & 0xFF" %}
9397 ins_encode %{
9398 // movzbl zeroes out the upper 32-bit and does not need REX.W
9399 __ movzbl($dst$$Register, $src$$Register);
9400 %}
9401 ins_pipe(ialu_reg);
9402 %}
9403
9404 // And Register with Immediate 65535
9405 instruct andL_rReg_imm65535(rRegL dst, rRegL src, immL_65535 mask)
9406 %{
9407 match(Set dst (AndL src mask));
9408
9409 format %{ "movzwl $dst, $src\t# long & 0xFFFF" %}
9410 ins_encode %{
9411 // movzwl zeroes out the upper 32-bit and does not need REX.W
9412 __ movzwl($dst$$Register, $src$$Register);
9413 %}
9414 ins_pipe(ialu_reg);
9415 %}
9416
9417 // And Register with Immediate
9418 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9419 %{
9420 match(Set dst (AndL dst src));
9421 effect(KILL cr);
9422 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9423
9424 format %{ "andq $dst, $src\t# long" %}
9425 ins_encode %{
9426 __ andq($dst$$Register, $src$$constant);
9427 %}
9428 ins_pipe(ialu_reg);
9429 %}
9430
9431 // And Register with Memory
9432 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9433 %{
9434 match(Set dst (AndL dst (LoadL src)));
9435 effect(KILL cr);
9436 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9437
9438 ins_cost(150);
9439 format %{ "andq $dst, $src\t# long" %}
9440 ins_encode %{
9441 __ andq($dst$$Register, $src$$Address);
9442 %}
9443 ins_pipe(ialu_reg_mem);
9444 %}
9445
9446 // And Memory with Register
9447 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9448 %{
9449 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9450 effect(KILL cr);
9451 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9452
9453 ins_cost(150);
9454 format %{ "andq $dst, $src\t# long" %}
9455 ins_encode %{
9456 __ andq($dst$$Address, $src$$Register);
9457 %}
9458 ins_pipe(ialu_mem_reg);
9459 %}
9460
9461 // And Memory with Immediate
9462 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9463 %{
9464 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9465 effect(KILL cr);
9466 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9467
9468 ins_cost(125);
9469 format %{ "andq $dst, $src\t# long" %}
9470 ins_encode %{
9471 __ andq($dst$$Address, $src$$constant);
9472 %}
9473 ins_pipe(ialu_mem_imm);
9474 %}
9475
9476 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
9477 %{
9478 // con should be a pure 64-bit immediate given that not(con) is a power of 2
9479 // because AND/OR works well enough for 8/32-bit values.
9480 predicate(log2i_graceful(~n->in(3)->in(2)->get_long()) > 30);
9481
9482 match(Set dst (StoreL dst (AndL (LoadL dst) con)));
9483 effect(KILL cr);
9484
9485 ins_cost(125);
9486 format %{ "btrq $dst, log2(not($con))\t# long" %}
9487 ins_encode %{
9488 __ btrq($dst$$Address, log2i_exact((julong)~$con$$constant));
9489 %}
9490 ins_pipe(ialu_mem_imm);
9491 %}
9492
9493 // BMI1 instructions
9494 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9495 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9496 predicate(UseBMI1Instructions);
9497 effect(KILL cr);
9498 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9499
9500 ins_cost(125);
9501 format %{ "andnq $dst, $src1, $src2" %}
9502
9503 ins_encode %{
9504 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9505 %}
9506 ins_pipe(ialu_reg_mem);
9507 %}
9508
9509 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9510 match(Set dst (AndL (XorL src1 minus_1) src2));
9511 predicate(UseBMI1Instructions);
9512 effect(KILL cr);
9513 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9514
9515 format %{ "andnq $dst, $src1, $src2" %}
9516
9517 ins_encode %{
9518 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9519 %}
9520 ins_pipe(ialu_reg_mem);
9521 %}
9522
9523 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9524 match(Set dst (AndL (SubL imm_zero src) src));
9525 predicate(UseBMI1Instructions);
9526 effect(KILL cr);
9527 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9528
9529 format %{ "blsiq $dst, $src" %}
9530
9531 ins_encode %{
9532 __ blsiq($dst$$Register, $src$$Register);
9533 %}
9534 ins_pipe(ialu_reg);
9535 %}
9536
9537 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9538 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9539 predicate(UseBMI1Instructions);
9540 effect(KILL cr);
9541 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9542
9543 ins_cost(125);
9544 format %{ "blsiq $dst, $src" %}
9545
9546 ins_encode %{
9547 __ blsiq($dst$$Register, $src$$Address);
9548 %}
9549 ins_pipe(ialu_reg_mem);
9550 %}
9551
9552 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9553 %{
9554 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9555 predicate(UseBMI1Instructions);
9556 effect(KILL cr);
9557 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
9558
9559 ins_cost(125);
9560 format %{ "blsmskq $dst, $src" %}
9561
9562 ins_encode %{
9563 __ blsmskq($dst$$Register, $src$$Address);
9564 %}
9565 ins_pipe(ialu_reg_mem);
9566 %}
9567
9568 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9569 %{
9570 match(Set dst (XorL (AddL src minus_1) src));
9571 predicate(UseBMI1Instructions);
9572 effect(KILL cr);
9573 flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
9574
9575 format %{ "blsmskq $dst, $src" %}
9576
9577 ins_encode %{
9578 __ blsmskq($dst$$Register, $src$$Register);
9579 %}
9580
9581 ins_pipe(ialu_reg);
9582 %}
9583
9584 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9585 %{
9586 match(Set dst (AndL (AddL src minus_1) src) );
9587 predicate(UseBMI1Instructions);
9588 effect(KILL cr);
9589 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9590
9591 format %{ "blsrq $dst, $src" %}
9592
9593 ins_encode %{
9594 __ blsrq($dst$$Register, $src$$Register);
9595 %}
9596
9597 ins_pipe(ialu_reg);
9598 %}
9599
9600 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9601 %{
9602 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9603 predicate(UseBMI1Instructions);
9604 effect(KILL cr);
9605 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
9606
9607 ins_cost(125);
9608 format %{ "blsrq $dst, $src" %}
9609
9610 ins_encode %{
9611 __ blsrq($dst$$Register, $src$$Address);
9612 %}
9613
9614 ins_pipe(ialu_reg);
9615 %}
9616
9617 // Or Instructions
9618 // Or Register with Register
9619 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9620 %{
9621 match(Set dst (OrL dst src));
9622 effect(KILL cr);
9623 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9624
9625 format %{ "orq $dst, $src\t# long" %}
9626 ins_encode %{
9627 __ orq($dst$$Register, $src$$Register);
9628 %}
9629 ins_pipe(ialu_reg_reg);
9630 %}
9631
9632 // Use any_RegP to match R15 (TLS register) without spilling.
9633 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9634 match(Set dst (OrL dst (CastP2X src)));
9635 effect(KILL cr);
9636 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9637
9638 format %{ "orq $dst, $src\t# long" %}
9639 ins_encode %{
9640 __ orq($dst$$Register, $src$$Register);
9641 %}
9642 ins_pipe(ialu_reg_reg);
9643 %}
9644
9645
9646 // Or Register with Immediate
9647 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9648 %{
9649 match(Set dst (OrL dst src));
9650 effect(KILL cr);
9651 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9652
9653 format %{ "orq $dst, $src\t# long" %}
9654 ins_encode %{
9655 __ orq($dst$$Register, $src$$constant);
9656 %}
9657 ins_pipe(ialu_reg);
9658 %}
9659
9660 // Or Register with Memory
9661 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9662 %{
9663 match(Set dst (OrL dst (LoadL src)));
9664 effect(KILL cr);
9665 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9666
9667 ins_cost(150);
9668 format %{ "orq $dst, $src\t# long" %}
9669 ins_encode %{
9670 __ orq($dst$$Register, $src$$Address);
9671 %}
9672 ins_pipe(ialu_reg_mem);
9673 %}
9674
9675 // Or Memory with Register
9676 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9677 %{
9678 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9679 effect(KILL cr);
9680 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9681
9682 ins_cost(150);
9683 format %{ "orq $dst, $src\t# long" %}
9684 ins_encode %{
9685 __ orq($dst$$Address, $src$$Register);
9686 %}
9687 ins_pipe(ialu_mem_reg);
9688 %}
9689
9690 // Or Memory with Immediate
9691 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9692 %{
9693 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9694 effect(KILL cr);
9695 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9696
9697 ins_cost(125);
9698 format %{ "orq $dst, $src\t# long" %}
9699 ins_encode %{
9700 __ orq($dst$$Address, $src$$constant);
9701 %}
9702 ins_pipe(ialu_mem_imm);
9703 %}
9704
9705 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr)
9706 %{
9707 // con should be a pure 64-bit power of 2 immediate
9708 // because AND/OR works well enough for 8/32-bit values.
9709 predicate(log2i_graceful(n->in(3)->in(2)->get_long()) > 31);
9710
9711 match(Set dst (StoreL dst (OrL (LoadL dst) con)));
9712 effect(KILL cr);
9713
9714 ins_cost(125);
9715 format %{ "btsq $dst, log2($con)\t# long" %}
9716 ins_encode %{
9717 __ btsq($dst$$Address, log2i_exact((julong)$con$$constant));
9718 %}
9719 ins_pipe(ialu_mem_imm);
9720 %}
9721
9722 // Xor Instructions
9723 // Xor Register with Register
9724 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9725 %{
9726 match(Set dst (XorL dst src));
9727 effect(KILL cr);
9728 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9729
9730 format %{ "xorq $dst, $src\t# long" %}
9731 ins_encode %{
9732 __ xorq($dst$$Register, $src$$Register);
9733 %}
9734 ins_pipe(ialu_reg_reg);
9735 %}
9736
9737 // Xor Register with Immediate -1
9738 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9739 match(Set dst (XorL dst imm));
9740
9741 format %{ "notq $dst" %}
9742 ins_encode %{
9743 __ notq($dst$$Register);
9744 %}
9745 ins_pipe(ialu_reg);
9746 %}
9747
9748 // Xor Register with Immediate
9749 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9750 %{
9751 match(Set dst (XorL dst src));
9752 effect(KILL cr);
9753 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9754
9755 format %{ "xorq $dst, $src\t# long" %}
9756 ins_encode %{
9757 __ xorq($dst$$Register, $src$$constant);
9758 %}
9759 ins_pipe(ialu_reg);
9760 %}
9761
9762 // Xor Register with Memory
9763 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9764 %{
9765 match(Set dst (XorL dst (LoadL src)));
9766 effect(KILL cr);
9767 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9768
9769 ins_cost(150);
9770 format %{ "xorq $dst, $src\t# long" %}
9771 ins_encode %{
9772 __ xorq($dst$$Register, $src$$Address);
9773 %}
9774 ins_pipe(ialu_reg_mem);
9775 %}
9776
9777 // Xor Memory with Register
9778 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9779 %{
9780 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9781 effect(KILL cr);
9782 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9783
9784 ins_cost(150);
9785 format %{ "xorq $dst, $src\t# long" %}
9786 ins_encode %{
9787 __ xorq($dst$$Address, $src$$Register);
9788 %}
9789 ins_pipe(ialu_mem_reg);
9790 %}
9791
9792 // Xor Memory with Immediate
9793 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9794 %{
9795 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9796 effect(KILL cr);
9797 flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
9798
9799 ins_cost(125);
9800 format %{ "xorq $dst, $src\t# long" %}
9801 ins_encode %{
9802 __ xorq($dst$$Address, $src$$constant);
9803 %}
9804 ins_pipe(ialu_mem_imm);
9805 %}
9806
9807 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9808 %{
9809 match(Set dst (CmpLTMask p q));
9810 effect(KILL cr);
9811
9812 ins_cost(400);
9813 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9814 "setlt $dst\n\t"
9815 "movzbl $dst, $dst\n\t"
9816 "negl $dst" %}
9817 ins_encode %{
9818 __ cmpl($p$$Register, $q$$Register);
9819 __ setb(Assembler::less, $dst$$Register);
9820 __ movzbl($dst$$Register, $dst$$Register);
9821 __ negl($dst$$Register);
9822 %}
9823 ins_pipe(pipe_slow);
9824 %}
9825
9826 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
9827 %{
9828 match(Set dst (CmpLTMask dst zero));
9829 effect(KILL cr);
9830
9831 ins_cost(100);
9832 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9833 ins_encode %{
9834 __ sarl($dst$$Register, 31);
9835 %}
9836 ins_pipe(ialu_reg);
9837 %}
9838
9839 /* Better to save a register than avoid a branch */
9840 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9841 %{
9842 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9843 effect(KILL cr);
9844 ins_cost(300);
9845 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9846 "jge done\n\t"
9847 "addl $p,$y\n"
9848 "done: " %}
9849 ins_encode %{
9850 Register Rp = $p$$Register;
9851 Register Rq = $q$$Register;
9852 Register Ry = $y$$Register;
9853 Label done;
9854 __ subl(Rp, Rq);
9855 __ jccb(Assembler::greaterEqual, done);
9856 __ addl(Rp, Ry);
9857 __ bind(done);
9858 %}
9859 ins_pipe(pipe_cmplt);
9860 %}
9861
9862 /* Better to save a register than avoid a branch */
9863 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9864 %{
9865 match(Set y (AndI (CmpLTMask p q) y));
9866 effect(KILL cr);
9867
9868 ins_cost(300);
9869
9870 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9871 "jlt done\n\t"
9872 "xorl $y, $y\n"
9873 "done: " %}
9874 ins_encode %{
9875 Register Rp = $p$$Register;
9876 Register Rq = $q$$Register;
9877 Register Ry = $y$$Register;
9878 Label done;
9879 __ cmpl(Rp, Rq);
9880 __ jccb(Assembler::less, done);
9881 __ xorl(Ry, Ry);
9882 __ bind(done);
9883 %}
9884 ins_pipe(pipe_cmplt);
9885 %}
9886
9887
9888 //---------- FP Instructions------------------------------------------------
9889
9890 // Really expensive, avoid
9891 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9892 %{
9893 match(Set cr (CmpF src1 src2));
9894
9895 ins_cost(500);
9896 format %{ "ucomiss $src1, $src2\n\t"
9897 "jnp,s exit\n\t"
9898 "pushfq\t# saw NaN, set CF\n\t"
9899 "andq [rsp], #0xffffff2b\n\t"
9900 "popfq\n"
9901 "exit:" %}
9902 ins_encode %{
9903 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9904 emit_cmpfp_fixup(_masm);
9905 %}
9906 ins_pipe(pipe_slow);
9907 %}
9908
9909 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9910 match(Set cr (CmpF src1 src2));
9911
9912 ins_cost(100);
9913 format %{ "ucomiss $src1, $src2" %}
9914 ins_encode %{
9915 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9916 %}
9917 ins_pipe(pipe_slow);
9918 %}
9919
9920 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9921 match(Set cr (CmpF src1 (LoadF src2)));
9922
9923 ins_cost(100);
9924 format %{ "ucomiss $src1, $src2" %}
9925 ins_encode %{
9926 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9927 %}
9928 ins_pipe(pipe_slow);
9929 %}
9930
9931 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9932 match(Set cr (CmpF src con));
9933 ins_cost(100);
9934 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9935 ins_encode %{
9936 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9937 %}
9938 ins_pipe(pipe_slow);
9939 %}
9940
9941 // Really expensive, avoid
9942 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9943 %{
9944 match(Set cr (CmpD src1 src2));
9945
9946 ins_cost(500);
9947 format %{ "ucomisd $src1, $src2\n\t"
9948 "jnp,s exit\n\t"
9949 "pushfq\t# saw NaN, set CF\n\t"
9950 "andq [rsp], #0xffffff2b\n\t"
9951 "popfq\n"
9952 "exit:" %}
9953 ins_encode %{
9954 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9955 emit_cmpfp_fixup(_masm);
9956 %}
9957 ins_pipe(pipe_slow);
9958 %}
9959
9960 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9961 match(Set cr (CmpD src1 src2));
9962
9963 ins_cost(100);
9964 format %{ "ucomisd $src1, $src2 test" %}
9965 ins_encode %{
9966 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9967 %}
9968 ins_pipe(pipe_slow);
9969 %}
9970
9971 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9972 match(Set cr (CmpD src1 (LoadD src2)));
9973
9974 ins_cost(100);
9975 format %{ "ucomisd $src1, $src2" %}
9976 ins_encode %{
9977 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9978 %}
9979 ins_pipe(pipe_slow);
9980 %}
9981
9982 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9983 match(Set cr (CmpD src con));
9984 ins_cost(100);
9985 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9986 ins_encode %{
9987 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9988 %}
9989 ins_pipe(pipe_slow);
9990 %}
9991
9992 // Compare into -1,0,1
9993 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9994 %{
9995 match(Set dst (CmpF3 src1 src2));
9996 effect(KILL cr);
9997
9998 ins_cost(275);
9999 format %{ "ucomiss $src1, $src2\n\t"
10000 "movl $dst, #-1\n\t"
10001 "jp,s done\n\t"
10002 "jb,s done\n\t"
10003 "setne $dst\n\t"
10004 "movzbl $dst, $dst\n"
10005 "done:" %}
10006 ins_encode %{
10007 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10008 emit_cmpfp3(_masm, $dst$$Register);
10009 %}
10010 ins_pipe(pipe_slow);
10011 %}
10012
10013 // Compare into -1,0,1
10014 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10015 %{
10016 match(Set dst (CmpF3 src1 (LoadF src2)));
10017 effect(KILL cr);
10018
10019 ins_cost(275);
10020 format %{ "ucomiss $src1, $src2\n\t"
10021 "movl $dst, #-1\n\t"
10022 "jp,s done\n\t"
10023 "jb,s done\n\t"
10024 "setne $dst\n\t"
10025 "movzbl $dst, $dst\n"
10026 "done:" %}
10027 ins_encode %{
10028 __ ucomiss($src1$$XMMRegister, $src2$$Address);
10029 emit_cmpfp3(_masm, $dst$$Register);
10030 %}
10031 ins_pipe(pipe_slow);
10032 %}
10033
10034 // Compare into -1,0,1
10035 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10036 match(Set dst (CmpF3 src con));
10037 effect(KILL cr);
10038
10039 ins_cost(275);
10040 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10041 "movl $dst, #-1\n\t"
10042 "jp,s done\n\t"
10043 "jb,s done\n\t"
10044 "setne $dst\n\t"
10045 "movzbl $dst, $dst\n"
10046 "done:" %}
10047 ins_encode %{
10048 __ ucomiss($src$$XMMRegister, $constantaddress($con));
10049 emit_cmpfp3(_masm, $dst$$Register);
10050 %}
10051 ins_pipe(pipe_slow);
10052 %}
10053
10054 // Compare into -1,0,1
10055 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10056 %{
10057 match(Set dst (CmpD3 src1 src2));
10058 effect(KILL cr);
10059
10060 ins_cost(275);
10061 format %{ "ucomisd $src1, $src2\n\t"
10062 "movl $dst, #-1\n\t"
10063 "jp,s done\n\t"
10064 "jb,s done\n\t"
10065 "setne $dst\n\t"
10066 "movzbl $dst, $dst\n"
10067 "done:" %}
10068 ins_encode %{
10069 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10070 emit_cmpfp3(_masm, $dst$$Register);
10071 %}
10072 ins_pipe(pipe_slow);
10073 %}
10074
10075 // Compare into -1,0,1
10076 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10077 %{
10078 match(Set dst (CmpD3 src1 (LoadD src2)));
10079 effect(KILL cr);
10080
10081 ins_cost(275);
10082 format %{ "ucomisd $src1, $src2\n\t"
10083 "movl $dst, #-1\n\t"
10084 "jp,s done\n\t"
10085 "jb,s done\n\t"
10086 "setne $dst\n\t"
10087 "movzbl $dst, $dst\n"
10088 "done:" %}
10089 ins_encode %{
10090 __ ucomisd($src1$$XMMRegister, $src2$$Address);
10091 emit_cmpfp3(_masm, $dst$$Register);
10092 %}
10093 ins_pipe(pipe_slow);
10094 %}
10095
10096 // Compare into -1,0,1
10097 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10098 match(Set dst (CmpD3 src con));
10099 effect(KILL cr);
10100
10101 ins_cost(275);
10102 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10103 "movl $dst, #-1\n\t"
10104 "jp,s done\n\t"
10105 "jb,s done\n\t"
10106 "setne $dst\n\t"
10107 "movzbl $dst, $dst\n"
10108 "done:" %}
10109 ins_encode %{
10110 __ ucomisd($src$$XMMRegister, $constantaddress($con));
10111 emit_cmpfp3(_masm, $dst$$Register);
10112 %}
10113 ins_pipe(pipe_slow);
10114 %}
10115
10116 //----------Arithmetic Conversion Instructions---------------------------------
10117
10118 instruct convF2D_reg_reg(regD dst, regF src)
10119 %{
10120 match(Set dst (ConvF2D src));
10121
10122 format %{ "cvtss2sd $dst, $src" %}
10123 ins_encode %{
10124 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10125 %}
10126 ins_pipe(pipe_slow); // XXX
10127 %}
10128
10129 instruct convF2D_reg_mem(regD dst, memory src)
10130 %{
10131 match(Set dst (ConvF2D (LoadF src)));
10132
10133 format %{ "cvtss2sd $dst, $src" %}
10134 ins_encode %{
10135 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10136 %}
10137 ins_pipe(pipe_slow); // XXX
10138 %}
10139
10140 instruct convD2F_reg_reg(regF dst, regD src)
10141 %{
10142 match(Set dst (ConvD2F src));
10143
10144 format %{ "cvtsd2ss $dst, $src" %}
10145 ins_encode %{
10146 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10147 %}
10148 ins_pipe(pipe_slow); // XXX
10149 %}
10150
10151 instruct convD2F_reg_mem(regF dst, memory src)
10152 %{
10153 match(Set dst (ConvD2F (LoadD src)));
10154
10155 format %{ "cvtsd2ss $dst, $src" %}
10156 ins_encode %{
10157 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10158 %}
10159 ins_pipe(pipe_slow); // XXX
10160 %}
10161
10162 // XXX do mem variants
10163 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10164 %{
10165 match(Set dst (ConvF2I src));
10166 effect(KILL cr);
10167 format %{ "convert_f2i $dst, $src" %}
10168 ins_encode %{
10169 __ convertF2I(T_INT, T_FLOAT, $dst$$Register, $src$$XMMRegister);
10170 %}
10171 ins_pipe(pipe_slow);
10172 %}
10173
10174 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10175 %{
10176 match(Set dst (ConvF2L src));
10177 effect(KILL cr);
10178 format %{ "convert_f2l $dst, $src"%}
10179 ins_encode %{
10180 __ convertF2I(T_LONG, T_FLOAT, $dst$$Register, $src$$XMMRegister);
10181 %}
10182 ins_pipe(pipe_slow);
10183 %}
10184
10185 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10186 %{
10187 match(Set dst (ConvD2I src));
10188 effect(KILL cr);
10189 format %{ "convert_d2i $dst, $src"%}
10190 ins_encode %{
10191 __ convertF2I(T_INT, T_DOUBLE, $dst$$Register, $src$$XMMRegister);
10192 %}
10193 ins_pipe(pipe_slow);
10194 %}
10195
10196 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10197 %{
10198 match(Set dst (ConvD2L src));
10199 effect(KILL cr);
10200 format %{ "convert_d2l $dst, $src"%}
10201 ins_encode %{
10202 __ convertF2I(T_LONG, T_DOUBLE, $dst$$Register, $src$$XMMRegister);
10203 %}
10204 ins_pipe(pipe_slow);
10205 %}
10206
10207 instruct round_double_reg(rRegL dst, regD src, rRegL rtmp, rcx_RegL rcx, rFlagsReg cr)
10208 %{
10209 match(Set dst (RoundD src));
10210 effect(TEMP dst, TEMP rtmp, TEMP rcx, KILL cr);
10211 format %{ "round_double $dst,$src \t! using $rtmp and $rcx as TEMP"%}
10212 ins_encode %{
10213 __ round_double($dst$$Register, $src$$XMMRegister, $rtmp$$Register, $rcx$$Register);
10214 %}
10215 ins_pipe(pipe_slow);
10216 %}
10217
10218 instruct round_float_reg(rRegI dst, regF src, rRegL rtmp, rcx_RegL rcx, rFlagsReg cr)
10219 %{
10220 match(Set dst (RoundF src));
10221 effect(TEMP dst, TEMP rtmp, TEMP rcx, KILL cr);
10222 format %{ "round_float $dst,$src" %}
10223 ins_encode %{
10224 __ round_float($dst$$Register, $src$$XMMRegister, $rtmp$$Register, $rcx$$Register);
10225 %}
10226 ins_pipe(pipe_slow);
10227 %}
10228
10229 instruct convI2F_reg_reg(regF dst, rRegI src)
10230 %{
10231 predicate(!UseXmmI2F);
10232 match(Set dst (ConvI2F src));
10233
10234 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10235 ins_encode %{
10236 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10237 %}
10238 ins_pipe(pipe_slow); // XXX
10239 %}
10240
10241 instruct convI2F_reg_mem(regF dst, memory src)
10242 %{
10243 match(Set dst (ConvI2F (LoadI src)));
10244
10245 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10246 ins_encode %{
10247 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10248 %}
10249 ins_pipe(pipe_slow); // XXX
10250 %}
10251
10252 instruct convI2D_reg_reg(regD dst, rRegI src)
10253 %{
10254 predicate(!UseXmmI2D);
10255 match(Set dst (ConvI2D src));
10256
10257 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10258 ins_encode %{
10259 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10260 %}
10261 ins_pipe(pipe_slow); // XXX
10262 %}
10263
10264 instruct convI2D_reg_mem(regD dst, memory src)
10265 %{
10266 match(Set dst (ConvI2D (LoadI src)));
10267
10268 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10269 ins_encode %{
10270 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10271 %}
10272 ins_pipe(pipe_slow); // XXX
10273 %}
10274
10275 instruct convXI2F_reg(regF dst, rRegI src)
10276 %{
10277 predicate(UseXmmI2F);
10278 match(Set dst (ConvI2F src));
10279
10280 format %{ "movdl $dst, $src\n\t"
10281 "cvtdq2psl $dst, $dst\t# i2f" %}
10282 ins_encode %{
10283 __ movdl($dst$$XMMRegister, $src$$Register);
10284 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10285 %}
10286 ins_pipe(pipe_slow); // XXX
10287 %}
10288
10289 instruct convXI2D_reg(regD dst, rRegI src)
10290 %{
10291 predicate(UseXmmI2D);
10292 match(Set dst (ConvI2D src));
10293
10294 format %{ "movdl $dst, $src\n\t"
10295 "cvtdq2pdl $dst, $dst\t# i2d" %}
10296 ins_encode %{
10297 __ movdl($dst$$XMMRegister, $src$$Register);
10298 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10299 %}
10300 ins_pipe(pipe_slow); // XXX
10301 %}
10302
10303 instruct convL2F_reg_reg(regF dst, rRegL src)
10304 %{
10305 match(Set dst (ConvL2F src));
10306
10307 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10308 ins_encode %{
10309 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10310 %}
10311 ins_pipe(pipe_slow); // XXX
10312 %}
10313
10314 instruct convL2F_reg_mem(regF dst, memory src)
10315 %{
10316 match(Set dst (ConvL2F (LoadL src)));
10317
10318 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10319 ins_encode %{
10320 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10321 %}
10322 ins_pipe(pipe_slow); // XXX
10323 %}
10324
10325 instruct convL2D_reg_reg(regD dst, rRegL src)
10326 %{
10327 match(Set dst (ConvL2D src));
10328
10329 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10330 ins_encode %{
10331 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10332 %}
10333 ins_pipe(pipe_slow); // XXX
10334 %}
10335
10336 instruct convL2D_reg_mem(regD dst, memory src)
10337 %{
10338 match(Set dst (ConvL2D (LoadL src)));
10339
10340 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10341 ins_encode %{
10342 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10343 %}
10344 ins_pipe(pipe_slow); // XXX
10345 %}
10346
10347 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10348 %{
10349 match(Set dst (ConvI2L src));
10350
10351 ins_cost(125);
10352 format %{ "movslq $dst, $src\t# i2l" %}
10353 ins_encode %{
10354 __ movslq($dst$$Register, $src$$Register);
10355 %}
10356 ins_pipe(ialu_reg_reg);
10357 %}
10358
10359 // Zero-extend convert int to long
10360 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10361 %{
10362 match(Set dst (AndL (ConvI2L src) mask));
10363
10364 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10365 ins_encode %{
10366 if ($dst$$reg != $src$$reg) {
10367 __ movl($dst$$Register, $src$$Register);
10368 }
10369 %}
10370 ins_pipe(ialu_reg_reg);
10371 %}
10372
10373 // Zero-extend convert int to long
10374 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10375 %{
10376 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10377
10378 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10379 ins_encode %{
10380 __ movl($dst$$Register, $src$$Address);
10381 %}
10382 ins_pipe(ialu_reg_mem);
10383 %}
10384
10385 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10386 %{
10387 match(Set dst (AndL src mask));
10388
10389 format %{ "movl $dst, $src\t# zero-extend long" %}
10390 ins_encode %{
10391 __ movl($dst$$Register, $src$$Register);
10392 %}
10393 ins_pipe(ialu_reg_reg);
10394 %}
10395
10396 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10397 %{
10398 match(Set dst (ConvL2I src));
10399
10400 format %{ "movl $dst, $src\t# l2i" %}
10401 ins_encode %{
10402 __ movl($dst$$Register, $src$$Register);
10403 %}
10404 ins_pipe(ialu_reg_reg);
10405 %}
10406
10407
10408 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10409 match(Set dst (MoveF2I src));
10410 effect(DEF dst, USE src);
10411
10412 ins_cost(125);
10413 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10414 ins_encode %{
10415 __ movl($dst$$Register, Address(rsp, $src$$disp));
10416 %}
10417 ins_pipe(ialu_reg_mem);
10418 %}
10419
10420 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10421 match(Set dst (MoveI2F src));
10422 effect(DEF dst, USE src);
10423
10424 ins_cost(125);
10425 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10426 ins_encode %{
10427 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10428 %}
10429 ins_pipe(pipe_slow);
10430 %}
10431
10432 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10433 match(Set dst (MoveD2L src));
10434 effect(DEF dst, USE src);
10435
10436 ins_cost(125);
10437 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10438 ins_encode %{
10439 __ movq($dst$$Register, Address(rsp, $src$$disp));
10440 %}
10441 ins_pipe(ialu_reg_mem);
10442 %}
10443
10444 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10445 predicate(!UseXmmLoadAndClearUpper);
10446 match(Set dst (MoveL2D src));
10447 effect(DEF dst, USE src);
10448
10449 ins_cost(125);
10450 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10451 ins_encode %{
10452 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10453 %}
10454 ins_pipe(pipe_slow);
10455 %}
10456
10457 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10458 predicate(UseXmmLoadAndClearUpper);
10459 match(Set dst (MoveL2D src));
10460 effect(DEF dst, USE src);
10461
10462 ins_cost(125);
10463 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10464 ins_encode %{
10465 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10466 %}
10467 ins_pipe(pipe_slow);
10468 %}
10469
10470
10471 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10472 match(Set dst (MoveF2I src));
10473 effect(DEF dst, USE src);
10474
10475 ins_cost(95); // XXX
10476 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10477 ins_encode %{
10478 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10479 %}
10480 ins_pipe(pipe_slow);
10481 %}
10482
10483 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10484 match(Set dst (MoveI2F src));
10485 effect(DEF dst, USE src);
10486
10487 ins_cost(100);
10488 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10489 ins_encode %{
10490 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10491 %}
10492 ins_pipe( ialu_mem_reg );
10493 %}
10494
10495 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10496 match(Set dst (MoveD2L src));
10497 effect(DEF dst, USE src);
10498
10499 ins_cost(95); // XXX
10500 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10501 ins_encode %{
10502 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10503 %}
10504 ins_pipe(pipe_slow);
10505 %}
10506
10507 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10508 match(Set dst (MoveL2D src));
10509 effect(DEF dst, USE src);
10510
10511 ins_cost(100);
10512 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10513 ins_encode %{
10514 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10515 %}
10516 ins_pipe(ialu_mem_reg);
10517 %}
10518
10519 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10520 match(Set dst (MoveF2I src));
10521 effect(DEF dst, USE src);
10522 ins_cost(85);
10523 format %{ "movd $dst,$src\t# MoveF2I" %}
10524 ins_encode %{
10525 __ movdl($dst$$Register, $src$$XMMRegister);
10526 %}
10527 ins_pipe( pipe_slow );
10528 %}
10529
10530 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10531 match(Set dst (MoveD2L src));
10532 effect(DEF dst, USE src);
10533 ins_cost(85);
10534 format %{ "movd $dst,$src\t# MoveD2L" %}
10535 ins_encode %{
10536 __ movdq($dst$$Register, $src$$XMMRegister);
10537 %}
10538 ins_pipe( pipe_slow );
10539 %}
10540
10541 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10542 match(Set dst (MoveI2F src));
10543 effect(DEF dst, USE src);
10544 ins_cost(100);
10545 format %{ "movd $dst,$src\t# MoveI2F" %}
10546 ins_encode %{
10547 __ movdl($dst$$XMMRegister, $src$$Register);
10548 %}
10549 ins_pipe( pipe_slow );
10550 %}
10551
10552 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10553 match(Set dst (MoveL2D src));
10554 effect(DEF dst, USE src);
10555 ins_cost(100);
10556 format %{ "movd $dst,$src\t# MoveL2D" %}
10557 ins_encode %{
10558 __ movdq($dst$$XMMRegister, $src$$Register);
10559 %}
10560 ins_pipe( pipe_slow );
10561 %}
10562
10563
10564 // Fast clearing of an array
10565 // Small ClearArray non-AVX512.
10566 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegL val,
10567 Universe dummy, rFlagsReg cr)
10568 %{
10569 predicate(!((ClearArrayNode*)n)->is_large() && !((ClearArrayNode*)n)->word_copy_only() && (UseAVX <= 2));
10570 match(Set dummy (ClearArray (Binary cnt base) val));
10571 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, USE_KILL val, KILL cr);
10572
10573 format %{ $$template
10574 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10575 $$emit$$"jg LARGE\n\t"
10576 $$emit$$"dec rcx\n\t"
10577 $$emit$$"js DONE\t# Zero length\n\t"
10578 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
10579 $$emit$$"dec rcx\n\t"
10580 $$emit$$"jge LOOP\n\t"
10581 $$emit$$"jmp DONE\n\t"
10582 $$emit$$"# LARGE:\n\t"
10583 if (UseFastStosb) {
10584 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10585 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
10586 } else if (UseXMMForObjInit) {
10587 $$emit$$"movdq $tmp, $val\n\t"
10588 $$emit$$"punpcklqdq $tmp, $tmp\n\t"
10589 $$emit$$"vinserti128_high $tmp, $tmp\n\t"
10590 $$emit$$"jmpq L_zero_64_bytes\n\t"
10591 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10592 $$emit$$"vmovdqu $tmp,(rax)\n\t"
10593 $$emit$$"vmovdqu $tmp,0x20(rax)\n\t"
10594 $$emit$$"add 0x40,rax\n\t"
10595 $$emit$$"# L_zero_64_bytes:\n\t"
10596 $$emit$$"sub 0x8,rcx\n\t"
10597 $$emit$$"jge L_loop\n\t"
10598 $$emit$$"add 0x4,rcx\n\t"
10599 $$emit$$"jl L_tail\n\t"
10600 $$emit$$"vmovdqu $tmp,(rax)\n\t"
10601 $$emit$$"add 0x20,rax\n\t"
10602 $$emit$$"sub 0x4,rcx\n\t"
10603 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10604 $$emit$$"add 0x4,rcx\n\t"
10605 $$emit$$"jle L_end\n\t"
10606 $$emit$$"dec rcx\n\t"
10607 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10608 $$emit$$"vmovq xmm0,(rax)\n\t"
10609 $$emit$$"add 0x8,rax\n\t"
10610 $$emit$$"dec rcx\n\t"
10611 $$emit$$"jge L_sloop\n\t"
10612 $$emit$$"# L_end:\n\t"
10613 } else {
10614 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
10615 }
10616 $$emit$$"# DONE"
10617 %}
10618 ins_encode %{
10619 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
10620 $tmp$$XMMRegister, false, false);
10621 %}
10622 ins_pipe(pipe_slow);
10623 %}
10624
10625 instruct rep_stos_word_copy(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegL val,
10626 Universe dummy, rFlagsReg cr)
10627 %{
10628 predicate(!((ClearArrayNode*)n)->is_large() && ((ClearArrayNode*)n)->word_copy_only() && (UseAVX <= 2));
10629 match(Set dummy (ClearArray (Binary cnt base) val));
10630 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, USE_KILL val, KILL cr);
10631
10632 format %{ $$template
10633 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10634 $$emit$$"jg LARGE\n\t"
10635 $$emit$$"dec rcx\n\t"
10636 $$emit$$"js DONE\t# Zero length\n\t"
10637 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
10638 $$emit$$"dec rcx\n\t"
10639 $$emit$$"jge LOOP\n\t"
10640 $$emit$$"jmp DONE\n\t"
10641 $$emit$$"# LARGE:\n\t"
10642 if (UseXMMForObjInit) {
10643 $$emit$$"movdq $tmp, $val\n\t"
10644 $$emit$$"punpcklqdq $tmp, $tmp\n\t"
10645 $$emit$$"vinserti128_high $tmp, $tmp\n\t"
10646 $$emit$$"jmpq L_zero_64_bytes\n\t"
10647 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10648 $$emit$$"vmovdqu $tmp,(rax)\n\t"
10649 $$emit$$"vmovdqu $tmp,0x20(rax)\n\t"
10650 $$emit$$"add 0x40,rax\n\t"
10651 $$emit$$"# L_zero_64_bytes:\n\t"
10652 $$emit$$"sub 0x8,rcx\n\t"
10653 $$emit$$"jge L_loop\n\t"
10654 $$emit$$"add 0x4,rcx\n\t"
10655 $$emit$$"jl L_tail\n\t"
10656 $$emit$$"vmovdqu $tmp,(rax)\n\t"
10657 $$emit$$"add 0x20,rax\n\t"
10658 $$emit$$"sub 0x4,rcx\n\t"
10659 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10660 $$emit$$"add 0x4,rcx\n\t"
10661 $$emit$$"jle L_end\n\t"
10662 $$emit$$"dec rcx\n\t"
10663 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10664 $$emit$$"vmovq xmm0,(rax)\n\t"
10665 $$emit$$"add 0x8,rax\n\t"
10666 $$emit$$"dec rcx\n\t"
10667 $$emit$$"jge L_sloop\n\t"
10668 $$emit$$"# L_end:\n\t"
10669 } else {
10670 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
10671 }
10672 $$emit$$"# DONE"
10673 %}
10674 ins_encode %{
10675 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
10676 $tmp$$XMMRegister, false, true);
10677 %}
10678 ins_pipe(pipe_slow);
10679 %}
10680
10681 // Small ClearArray AVX512 non-constant length.
10682 instruct rep_stos_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegL val,
10683 Universe dummy, rFlagsReg cr)
10684 %{
10685 predicate(!((ClearArrayNode*)n)->is_large() && !((ClearArrayNode*)n)->word_copy_only() && (UseAVX > 2));
10686 match(Set dummy (ClearArray (Binary cnt base) val));
10687 ins_cost(125);
10688 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, USE_KILL val, KILL cr);
10689
10690 format %{ $$template
10691 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10692 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10693 $$emit$$"jg LARGE\n\t"
10694 $$emit$$"dec rcx\n\t"
10695 $$emit$$"js DONE\t# Zero length\n\t"
10696 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
10697 $$emit$$"dec rcx\n\t"
10698 $$emit$$"jge LOOP\n\t"
10699 $$emit$$"jmp DONE\n\t"
10700 $$emit$$"# LARGE:\n\t"
10701 if (UseFastStosb) {
10702 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10703 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
10704 } else if (UseXMMForObjInit) {
10705 $$emit$$"mov rdi,rax\n\t"
10706 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
10707 $$emit$$"jmpq L_zero_64_bytes\n\t"
10708 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10709 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10710 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10711 $$emit$$"add 0x40,rax\n\t"
10712 $$emit$$"# L_zero_64_bytes:\n\t"
10713 $$emit$$"sub 0x8,rcx\n\t"
10714 $$emit$$"jge L_loop\n\t"
10715 $$emit$$"add 0x4,rcx\n\t"
10716 $$emit$$"jl L_tail\n\t"
10717 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10718 $$emit$$"add 0x20,rax\n\t"
10719 $$emit$$"sub 0x4,rcx\n\t"
10720 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10721 $$emit$$"add 0x4,rcx\n\t"
10722 $$emit$$"jle L_end\n\t"
10723 $$emit$$"dec rcx\n\t"
10724 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10725 $$emit$$"vmovq xmm0,(rax)\n\t"
10726 $$emit$$"add 0x8,rax\n\t"
10727 $$emit$$"dec rcx\n\t"
10728 $$emit$$"jge L_sloop\n\t"
10729 $$emit$$"# L_end:\n\t"
10730 } else {
10731 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
10732 }
10733 $$emit$$"# DONE"
10734 %}
10735 ins_encode %{
10736 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
10737 $tmp$$XMMRegister, false, false, $ktmp$$KRegister);
10738 %}
10739 ins_pipe(pipe_slow);
10740 %}
10741
10742 instruct rep_stos_evex_word_copy(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegL val,
10743 Universe dummy, rFlagsReg cr)
10744 %{
10745 predicate(!((ClearArrayNode*)n)->is_large() && ((ClearArrayNode*)n)->word_copy_only() && (UseAVX > 2));
10746 match(Set dummy (ClearArray (Binary cnt base) val));
10747 ins_cost(125);
10748 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, USE_KILL val, KILL cr);
10749
10750 format %{ $$template
10751 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10752 $$emit$$"cmp InitArrayShortSize,rcx\n\t"
10753 $$emit$$"jg LARGE\n\t"
10754 $$emit$$"dec rcx\n\t"
10755 $$emit$$"js DONE\t# Zero length\n\t"
10756 $$emit$$"mov rax,(rdi,rcx,8)\t# LOOP\n\t"
10757 $$emit$$"dec rcx\n\t"
10758 $$emit$$"jge LOOP\n\t"
10759 $$emit$$"jmp DONE\n\t"
10760 $$emit$$"# LARGE:\n\t"
10761 if (UseFastStosb) {
10762 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10763 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--\n\t"
10764 } else if (UseXMMForObjInit) {
10765 $$emit$$"mov rdi,rax\n\t"
10766 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
10767 $$emit$$"jmpq L_zero_64_bytes\n\t"
10768 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10769 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10770 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10771 $$emit$$"add 0x40,rax\n\t"
10772 $$emit$$"# L_zero_64_bytes:\n\t"
10773 $$emit$$"sub 0x8,rcx\n\t"
10774 $$emit$$"jge L_loop\n\t"
10775 $$emit$$"add 0x4,rcx\n\t"
10776 $$emit$$"jl L_tail\n\t"
10777 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10778 $$emit$$"add 0x20,rax\n\t"
10779 $$emit$$"sub 0x4,rcx\n\t"
10780 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10781 $$emit$$"add 0x4,rcx\n\t"
10782 $$emit$$"jle L_end\n\t"
10783 $$emit$$"dec rcx\n\t"
10784 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10785 $$emit$$"vmovq xmm0,(rax)\n\t"
10786 $$emit$$"add 0x8,rax\n\t"
10787 $$emit$$"dec rcx\n\t"
10788 $$emit$$"jge L_sloop\n\t"
10789 $$emit$$"# L_end:\n\t"
10790 } else {
10791 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--\n\t"
10792 }
10793 $$emit$$"# DONE"
10794 %}
10795 ins_encode %{
10796 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
10797 $tmp$$XMMRegister, false, true, $ktmp$$KRegister);
10798 %}
10799 ins_pipe(pipe_slow);
10800 %}
10801
10802 // Large ClearArray non-AVX512.
10803 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegL val,
10804 Universe dummy, rFlagsReg cr)
10805 %{
10806 predicate(((ClearArrayNode*)n)->is_large() && !((ClearArrayNode*)n)->word_copy_only() && (UseAVX <= 2));
10807 match(Set dummy (ClearArray (Binary cnt base) val));
10808 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, USE_KILL val, KILL cr);
10809
10810 format %{ $$template
10811 if (UseFastStosb) {
10812 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10813 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
10814 } else if (UseXMMForObjInit) {
10815 $$emit$$"movdq $tmp, $val\n\t"
10816 $$emit$$"punpcklqdq $tmp, $tmp\n\t"
10817 $$emit$$"vinserti128_high $tmp, $tmp\n\t"
10818 $$emit$$"jmpq L_zero_64_bytes\n\t"
10819 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10820 $$emit$$"vmovdqu $tmp,(rax)\n\t"
10821 $$emit$$"vmovdqu $tmp,0x20(rax)\n\t"
10822 $$emit$$"add 0x40,rax\n\t"
10823 $$emit$$"# L_zero_64_bytes:\n\t"
10824 $$emit$$"sub 0x8,rcx\n\t"
10825 $$emit$$"jge L_loop\n\t"
10826 $$emit$$"add 0x4,rcx\n\t"
10827 $$emit$$"jl L_tail\n\t"
10828 $$emit$$"vmovdqu $tmp,(rax)\n\t"
10829 $$emit$$"add 0x20,rax\n\t"
10830 $$emit$$"sub 0x4,rcx\n\t"
10831 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10832 $$emit$$"add 0x4,rcx\n\t"
10833 $$emit$$"jle L_end\n\t"
10834 $$emit$$"dec rcx\n\t"
10835 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10836 $$emit$$"vmovq xmm0,(rax)\n\t"
10837 $$emit$$"add 0x8,rax\n\t"
10838 $$emit$$"dec rcx\n\t"
10839 $$emit$$"jge L_sloop\n\t"
10840 $$emit$$"# L_end:\n\t"
10841 } else {
10842 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
10843 }
10844 %}
10845 ins_encode %{
10846 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
10847 $tmp$$XMMRegister, true, false);
10848 %}
10849 ins_pipe(pipe_slow);
10850 %}
10851
10852 instruct rep_stos_large_word_copy(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegL val,
10853 Universe dummy, rFlagsReg cr)
10854 %{
10855 predicate(((ClearArrayNode*)n)->is_large() && ((ClearArrayNode*)n)->word_copy_only() && (UseAVX <= 2));
10856 match(Set dummy (ClearArray (Binary cnt base) val));
10857 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, USE_KILL val, KILL cr);
10858
10859 format %{ $$template
10860 if (UseXMMForObjInit) {
10861 $$emit$$"movdq $tmp, $val\n\t"
10862 $$emit$$"punpcklqdq $tmp, $tmp\n\t"
10863 $$emit$$"vinserti128_high $tmp, $tmp\n\t"
10864 $$emit$$"jmpq L_zero_64_bytes\n\t"
10865 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10866 $$emit$$"vmovdqu $tmp,(rax)\n\t"
10867 $$emit$$"vmovdqu $tmp,0x20(rax)\n\t"
10868 $$emit$$"add 0x40,rax\n\t"
10869 $$emit$$"# L_zero_64_bytes:\n\t"
10870 $$emit$$"sub 0x8,rcx\n\t"
10871 $$emit$$"jge L_loop\n\t"
10872 $$emit$$"add 0x4,rcx\n\t"
10873 $$emit$$"jl L_tail\n\t"
10874 $$emit$$"vmovdqu $tmp,(rax)\n\t"
10875 $$emit$$"add 0x20,rax\n\t"
10876 $$emit$$"sub 0x4,rcx\n\t"
10877 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10878 $$emit$$"add 0x4,rcx\n\t"
10879 $$emit$$"jle L_end\n\t"
10880 $$emit$$"dec rcx\n\t"
10881 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10882 $$emit$$"vmovq xmm0,(rax)\n\t"
10883 $$emit$$"add 0x8,rax\n\t"
10884 $$emit$$"dec rcx\n\t"
10885 $$emit$$"jge L_sloop\n\t"
10886 $$emit$$"# L_end:\n\t"
10887 } else {
10888 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
10889 }
10890 %}
10891 ins_encode %{
10892 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
10893 $tmp$$XMMRegister, true, true);
10894 %}
10895 ins_pipe(pipe_slow);
10896 %}
10897
10898 // Large ClearArray AVX512.
10899 instruct rep_stos_large_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegL val,
10900 Universe dummy, rFlagsReg cr)
10901 %{
10902 predicate(((ClearArrayNode*)n)->is_large() && !((ClearArrayNode*)n)->word_copy_only() && (UseAVX > 2));
10903 match(Set dummy (ClearArray (Binary cnt base) val));
10904 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, USE_KILL val, KILL cr);
10905
10906 format %{ $$template
10907 if (UseFastStosb) {
10908 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10909 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10910 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
10911 } else if (UseXMMForObjInit) {
10912 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
10913 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
10914 $$emit$$"jmpq L_zero_64_bytes\n\t"
10915 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10916 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10917 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10918 $$emit$$"add 0x40,rax\n\t"
10919 $$emit$$"# L_zero_64_bytes:\n\t"
10920 $$emit$$"sub 0x8,rcx\n\t"
10921 $$emit$$"jge L_loop\n\t"
10922 $$emit$$"add 0x4,rcx\n\t"
10923 $$emit$$"jl L_tail\n\t"
10924 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10925 $$emit$$"add 0x20,rax\n\t"
10926 $$emit$$"sub 0x4,rcx\n\t"
10927 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10928 $$emit$$"add 0x4,rcx\n\t"
10929 $$emit$$"jle L_end\n\t"
10930 $$emit$$"dec rcx\n\t"
10931 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10932 $$emit$$"vmovq xmm0,(rax)\n\t"
10933 $$emit$$"add 0x8,rax\n\t"
10934 $$emit$$"dec rcx\n\t"
10935 $$emit$$"jge L_sloop\n\t"
10936 $$emit$$"# L_end:\n\t"
10937 } else {
10938 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10939 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
10940 }
10941 %}
10942 ins_encode %{
10943 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
10944 $tmp$$XMMRegister, true, false, $ktmp$$KRegister);
10945 %}
10946 ins_pipe(pipe_slow);
10947 %}
10948
10949 instruct rep_stos_large_evex_word_copy(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegL val,
10950 Universe dummy, rFlagsReg cr)
10951 %{
10952 predicate(((ClearArrayNode*)n)->is_large() && ((ClearArrayNode*)n)->word_copy_only() && (UseAVX > 2));
10953 match(Set dummy (ClearArray (Binary cnt base) val));
10954 effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, USE_KILL val, KILL cr);
10955
10956 format %{ $$template
10957 if (UseFastStosb) {
10958 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10959 $$emit$$"shlq rcx,3\t# Convert doublewords to bytes\n\t"
10960 $$emit$$"rep stosb\t# Store rax to *rdi++ while rcx--"
10961 } else if (UseXMMForObjInit) {
10962 $$emit$$"mov rdi,rax\t# ClearArray:\n\t"
10963 $$emit$$"vpxor ymm0,ymm0,ymm0\n\t"
10964 $$emit$$"jmpq L_zero_64_bytes\n\t"
10965 $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
10966 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10967 $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
10968 $$emit$$"add 0x40,rax\n\t"
10969 $$emit$$"# L_zero_64_bytes:\n\t"
10970 $$emit$$"sub 0x8,rcx\n\t"
10971 $$emit$$"jge L_loop\n\t"
10972 $$emit$$"add 0x4,rcx\n\t"
10973 $$emit$$"jl L_tail\n\t"
10974 $$emit$$"vmovdqu ymm0,(rax)\n\t"
10975 $$emit$$"add 0x20,rax\n\t"
10976 $$emit$$"sub 0x4,rcx\n\t"
10977 $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
10978 $$emit$$"add 0x4,rcx\n\t"
10979 $$emit$$"jle L_end\n\t"
10980 $$emit$$"dec rcx\n\t"
10981 $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
10982 $$emit$$"vmovq xmm0,(rax)\n\t"
10983 $$emit$$"add 0x8,rax\n\t"
10984 $$emit$$"dec rcx\n\t"
10985 $$emit$$"jge L_sloop\n\t"
10986 $$emit$$"# L_end:\n\t"
10987 } else {
10988 $$emit$$"xorq rax, rax\t# ClearArray:\n\t"
10989 $$emit$$"rep stosq\t# Store rax to *rdi++ while rcx--"
10990 }
10991 %}
10992 ins_encode %{
10993 __ clear_mem($base$$Register, $cnt$$Register, $val$$Register,
10994 $tmp$$XMMRegister, true, true, $ktmp$$KRegister);
10995 %}
10996 ins_pipe(pipe_slow);
10997 %}
10998
10999 // Small ClearArray AVX512 constant length.
11000 instruct rep_stos_im(immL cnt, rRegP base, regD tmp, rax_RegL val, kReg ktmp, Universe dummy, rFlagsReg cr)
11001 %{
11002 predicate(!((ClearArrayNode*)n)->is_large() && !((ClearArrayNode*)n)->word_copy_only() &&
11003 ((UseAVX > 2) && VM_Version::supports_avx512vlbw()));
11004 match(Set dummy (ClearArray (Binary cnt base) val));
11005 ins_cost(100);
11006 effect(TEMP tmp, USE_KILL val, TEMP ktmp, KILL cr);
11007 format %{ "clear_mem_imm $base , $cnt \n\t" %}
11008 ins_encode %{
11009 __ clear_mem($base$$Register, $cnt$$constant, $val$$Register, $tmp$$XMMRegister, $ktmp$$KRegister);
11010 %}
11011 ins_pipe(pipe_slow);
11012 %}
11013
11014 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11015 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11016 %{
11017 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11018 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11019 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11020
11021 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11022 ins_encode %{
11023 __ string_compare($str1$$Register, $str2$$Register,
11024 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11025 $tmp1$$XMMRegister, StrIntrinsicNode::LL, knoreg);
11026 %}
11027 ins_pipe( pipe_slow );
11028 %}
11029
11030 instruct string_compareL_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11031 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11032 %{
11033 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11034 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11035 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11036
11037 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11038 ins_encode %{
11039 __ string_compare($str1$$Register, $str2$$Register,
11040 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11041 $tmp1$$XMMRegister, StrIntrinsicNode::LL, $ktmp$$KRegister);
11042 %}
11043 ins_pipe( pipe_slow );
11044 %}
11045
11046 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11047 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11048 %{
11049 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11050 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11051 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11052
11053 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11054 ins_encode %{
11055 __ string_compare($str1$$Register, $str2$$Register,
11056 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11057 $tmp1$$XMMRegister, StrIntrinsicNode::UU, knoreg);
11058 %}
11059 ins_pipe( pipe_slow );
11060 %}
11061
11062 instruct string_compareU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11063 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11064 %{
11065 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11066 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11067 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11068
11069 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11070 ins_encode %{
11071 __ string_compare($str1$$Register, $str2$$Register,
11072 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11073 $tmp1$$XMMRegister, StrIntrinsicNode::UU, $ktmp$$KRegister);
11074 %}
11075 ins_pipe( pipe_slow );
11076 %}
11077
11078 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11079 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11080 %{
11081 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11082 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11083 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11084
11085 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11086 ins_encode %{
11087 __ string_compare($str1$$Register, $str2$$Register,
11088 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11089 $tmp1$$XMMRegister, StrIntrinsicNode::LU, knoreg);
11090 %}
11091 ins_pipe( pipe_slow );
11092 %}
11093
11094 instruct string_compareLU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11095 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11096 %{
11097 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11098 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11099 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11100
11101 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11102 ins_encode %{
11103 __ string_compare($str1$$Register, $str2$$Register,
11104 $cnt1$$Register, $cnt2$$Register, $result$$Register,
11105 $tmp1$$XMMRegister, StrIntrinsicNode::LU, $ktmp$$KRegister);
11106 %}
11107 ins_pipe( pipe_slow );
11108 %}
11109
11110 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11111 rax_RegI result, legRegD tmp1, rFlagsReg cr)
11112 %{
11113 predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11114 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11115 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11116
11117 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11118 ins_encode %{
11119 __ string_compare($str2$$Register, $str1$$Register,
11120 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11121 $tmp1$$XMMRegister, StrIntrinsicNode::UL, knoreg);
11122 %}
11123 ins_pipe( pipe_slow );
11124 %}
11125
11126 instruct string_compareUL_evex(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11127 rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11128 %{
11129 predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11130 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11131 effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11132
11133 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
11134 ins_encode %{
11135 __ string_compare($str2$$Register, $str1$$Register,
11136 $cnt2$$Register, $cnt1$$Register, $result$$Register,
11137 $tmp1$$XMMRegister, StrIntrinsicNode::UL, $ktmp$$KRegister);
11138 %}
11139 ins_pipe( pipe_slow );
11140 %}
11141
11142 // fast search of substring with known size.
11143 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11144 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11145 %{
11146 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11147 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11148 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11149
11150 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11151 ins_encode %{
11152 int icnt2 = (int)$int_cnt2$$constant;
11153 if (icnt2 >= 16) {
11154 // IndexOf for constant substrings with size >= 16 elements
11155 // which don't need to be loaded through stack.
11156 __ string_indexofC8($str1$$Register, $str2$$Register,
11157 $cnt1$$Register, $cnt2$$Register,
11158 icnt2, $result$$Register,
11159 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11160 } else {
11161 // Small strings are loaded through stack if they cross page boundary.
11162 __ string_indexof($str1$$Register, $str2$$Register,
11163 $cnt1$$Register, $cnt2$$Register,
11164 icnt2, $result$$Register,
11165 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11166 }
11167 %}
11168 ins_pipe( pipe_slow );
11169 %}
11170
11171 // fast search of substring with known size.
11172 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11173 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11174 %{
11175 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11176 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11177 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11178
11179 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11180 ins_encode %{
11181 int icnt2 = (int)$int_cnt2$$constant;
11182 if (icnt2 >= 8) {
11183 // IndexOf for constant substrings with size >= 8 elements
11184 // which don't need to be loaded through stack.
11185 __ string_indexofC8($str1$$Register, $str2$$Register,
11186 $cnt1$$Register, $cnt2$$Register,
11187 icnt2, $result$$Register,
11188 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11189 } else {
11190 // Small strings are loaded through stack if they cross page boundary.
11191 __ string_indexof($str1$$Register, $str2$$Register,
11192 $cnt1$$Register, $cnt2$$Register,
11193 icnt2, $result$$Register,
11194 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11195 }
11196 %}
11197 ins_pipe( pipe_slow );
11198 %}
11199
11200 // fast search of substring with known size.
11201 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11202 rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11203 %{
11204 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11205 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11206 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11207
11208 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11209 ins_encode %{
11210 int icnt2 = (int)$int_cnt2$$constant;
11211 if (icnt2 >= 8) {
11212 // IndexOf for constant substrings with size >= 8 elements
11213 // which don't need to be loaded through stack.
11214 __ string_indexofC8($str1$$Register, $str2$$Register,
11215 $cnt1$$Register, $cnt2$$Register,
11216 icnt2, $result$$Register,
11217 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11218 } else {
11219 // Small strings are loaded through stack if they cross page boundary.
11220 __ string_indexof($str1$$Register, $str2$$Register,
11221 $cnt1$$Register, $cnt2$$Register,
11222 icnt2, $result$$Register,
11223 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11224 }
11225 %}
11226 ins_pipe( pipe_slow );
11227 %}
11228
11229 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11230 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11231 %{
11232 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11233 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11234 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11235
11236 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11237 ins_encode %{
11238 __ string_indexof($str1$$Register, $str2$$Register,
11239 $cnt1$$Register, $cnt2$$Register,
11240 (-1), $result$$Register,
11241 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11242 %}
11243 ins_pipe( pipe_slow );
11244 %}
11245
11246 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11247 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11248 %{
11249 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11250 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11251 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11252
11253 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11254 ins_encode %{
11255 __ string_indexof($str1$$Register, $str2$$Register,
11256 $cnt1$$Register, $cnt2$$Register,
11257 (-1), $result$$Register,
11258 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11259 %}
11260 ins_pipe( pipe_slow );
11261 %}
11262
11263 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11264 rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11265 %{
11266 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11267 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11268 effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11269
11270 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
11271 ins_encode %{
11272 __ string_indexof($str1$$Register, $str2$$Register,
11273 $cnt1$$Register, $cnt2$$Register,
11274 (-1), $result$$Register,
11275 $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11276 %}
11277 ins_pipe( pipe_slow );
11278 %}
11279
11280 instruct string_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11281 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
11282 %{
11283 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
11284 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11285 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11286 format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11287 ins_encode %{
11288 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11289 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
11290 %}
11291 ins_pipe( pipe_slow );
11292 %}
11293
11294 instruct stringL_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11295 rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
11296 %{
11297 predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
11298 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11299 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11300 format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
11301 ins_encode %{
11302 __ stringL_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11303 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
11304 %}
11305 ins_pipe( pipe_slow );
11306 %}
11307
11308 // fast string equals
11309 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11310 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
11311 %{
11312 predicate(!VM_Version::supports_avx512vlbw());
11313 match(Set result (StrEquals (Binary str1 str2) cnt));
11314 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11315
11316 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11317 ins_encode %{
11318 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11319 $cnt$$Register, $result$$Register, $tmp3$$Register,
11320 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
11321 %}
11322 ins_pipe( pipe_slow );
11323 %}
11324
11325 instruct string_equals_evex(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11326 legRegD tmp1, legRegD tmp2, kReg ktmp, rbx_RegI tmp3, rFlagsReg cr)
11327 %{
11328 predicate(VM_Version::supports_avx512vlbw());
11329 match(Set result (StrEquals (Binary str1 str2) cnt));
11330 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11331
11332 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11333 ins_encode %{
11334 __ arrays_equals(false, $str1$$Register, $str2$$Register,
11335 $cnt$$Register, $result$$Register, $tmp3$$Register,
11336 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
11337 %}
11338 ins_pipe( pipe_slow );
11339 %}
11340
11341 // fast array equals
11342 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11343 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11344 %{
11345 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11346 match(Set result (AryEq ary1 ary2));
11347 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11348
11349 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11350 ins_encode %{
11351 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11352 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11353 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
11354 %}
11355 ins_pipe( pipe_slow );
11356 %}
11357
11358 instruct array_equalsB_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11359 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11360 %{
11361 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11362 match(Set result (AryEq ary1 ary2));
11363 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11364
11365 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11366 ins_encode %{
11367 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11368 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11369 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
11370 %}
11371 ins_pipe( pipe_slow );
11372 %}
11373
11374 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11375 legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11376 %{
11377 predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11378 match(Set result (AryEq ary1 ary2));
11379 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11380
11381 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11382 ins_encode %{
11383 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11384 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11385 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, knoreg);
11386 %}
11387 ins_pipe( pipe_slow );
11388 %}
11389
11390 instruct array_equalsC_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11391 legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11392 %{
11393 predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11394 match(Set result (AryEq ary1 ary2));
11395 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11396
11397 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11398 ins_encode %{
11399 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11400 $tmp3$$Register, $result$$Register, $tmp4$$Register,
11401 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, $ktmp$$KRegister);
11402 %}
11403 ins_pipe( pipe_slow );
11404 %}
11405
11406 instruct arrays_hashcode(rdi_RegP ary1, rdx_RegI cnt1, rbx_RegI result, immU8 basic_type,
11407 legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, legRegD tmp_vec4,
11408 legRegD tmp_vec5, legRegD tmp_vec6, legRegD tmp_vec7, legRegD tmp_vec8,
11409 legRegD tmp_vec9, legRegD tmp_vec10, legRegD tmp_vec11, legRegD tmp_vec12,
11410 legRegD tmp_vec13, rRegI tmp1, rRegI tmp2, rRegI tmp3, rFlagsReg cr)
11411 %{
11412 predicate(UseAVX >= 2);
11413 match(Set result (VectorizedHashCode (Binary ary1 cnt1) (Binary result basic_type)));
11414 effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, TEMP tmp_vec4, TEMP tmp_vec5, TEMP tmp_vec6,
11415 TEMP tmp_vec7, TEMP tmp_vec8, TEMP tmp_vec9, TEMP tmp_vec10, TEMP tmp_vec11, TEMP tmp_vec12,
11416 TEMP tmp_vec13, TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL ary1, USE_KILL cnt1,
11417 USE basic_type, KILL cr);
11418
11419 format %{ "Array HashCode array[] $ary1,$cnt1,$result,$basic_type -> $result // KILL all" %}
11420 ins_encode %{
11421 __ arrays_hashcode($ary1$$Register, $cnt1$$Register, $result$$Register,
11422 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
11423 $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister,
11424 $tmp_vec4$$XMMRegister, $tmp_vec5$$XMMRegister, $tmp_vec6$$XMMRegister,
11425 $tmp_vec7$$XMMRegister, $tmp_vec8$$XMMRegister, $tmp_vec9$$XMMRegister,
11426 $tmp_vec10$$XMMRegister, $tmp_vec11$$XMMRegister, $tmp_vec12$$XMMRegister,
11427 $tmp_vec13$$XMMRegister, (BasicType)$basic_type$$constant);
11428 %}
11429 ins_pipe( pipe_slow );
11430 %}
11431
11432 instruct count_positives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11433 legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr,)
11434 %{
11435 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11436 match(Set result (CountPositives ary1 len));
11437 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11438
11439 format %{ "countPositives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11440 ins_encode %{
11441 __ count_positives($ary1$$Register, $len$$Register,
11442 $result$$Register, $tmp3$$Register,
11443 $tmp1$$XMMRegister, $tmp2$$XMMRegister, knoreg, knoreg);
11444 %}
11445 ins_pipe( pipe_slow );
11446 %}
11447
11448 instruct count_positives_evex(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11449 legRegD tmp1, legRegD tmp2, kReg ktmp1, kReg ktmp2, rbx_RegI tmp3, rFlagsReg cr,)
11450 %{
11451 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11452 match(Set result (CountPositives ary1 len));
11453 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp1, TEMP ktmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11454
11455 format %{ "countPositives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
11456 ins_encode %{
11457 __ count_positives($ary1$$Register, $len$$Register,
11458 $result$$Register, $tmp3$$Register,
11459 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $ktmp1$$KRegister, $ktmp2$$KRegister);
11460 %}
11461 ins_pipe( pipe_slow );
11462 %}
11463
11464 // fast char[] to byte[] compression
11465 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
11466 legRegD tmp4, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11467 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11468 match(Set result (StrCompressedCopy src (Binary dst len)));
11469 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst,
11470 USE_KILL len, KILL tmp5, KILL cr);
11471
11472 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11473 ins_encode %{
11474 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11475 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11476 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
11477 knoreg, knoreg);
11478 %}
11479 ins_pipe( pipe_slow );
11480 %}
11481
11482 instruct string_compress_evex(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
11483 legRegD tmp4, kReg ktmp1, kReg ktmp2, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11484 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11485 match(Set result (StrCompressedCopy src (Binary dst len)));
11486 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ktmp1, TEMP ktmp2, USE_KILL src, USE_KILL dst,
11487 USE_KILL len, KILL tmp5, KILL cr);
11488
11489 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
11490 ins_encode %{
11491 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11492 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11493 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
11494 $ktmp1$$KRegister, $ktmp2$$KRegister);
11495 %}
11496 ins_pipe( pipe_slow );
11497 %}
11498 // fast byte[] to char[] inflation
11499 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11500 legRegD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11501 predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11502 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11503 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11504
11505 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11506 ins_encode %{
11507 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11508 $tmp1$$XMMRegister, $tmp2$$Register, knoreg);
11509 %}
11510 ins_pipe( pipe_slow );
11511 %}
11512
11513 instruct string_inflate_evex(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11514 legRegD tmp1, kReg ktmp, rcx_RegI tmp2, rFlagsReg cr) %{
11515 predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11516 match(Set dummy (StrInflatedCopy src (Binary dst len)));
11517 effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11518
11519 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
11520 ins_encode %{
11521 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11522 $tmp1$$XMMRegister, $tmp2$$Register, $ktmp$$KRegister);
11523 %}
11524 ins_pipe( pipe_slow );
11525 %}
11526
11527 // encode char[] to byte[] in ISO_8859_1
11528 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11529 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11530 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11531 predicate(!((EncodeISOArrayNode*)n)->is_ascii());
11532 match(Set result (EncodeISOArray src (Binary dst len)));
11533 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11534
11535 format %{ "Encode iso array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11536 ins_encode %{
11537 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11538 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11539 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, false);
11540 %}
11541 ins_pipe( pipe_slow );
11542 %}
11543
11544 // encode char[] to byte[] in ASCII
11545 instruct encode_ascii_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11546 legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11547 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11548 predicate(((EncodeISOArrayNode*)n)->is_ascii());
11549 match(Set result (EncodeISOArray src (Binary dst len)));
11550 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11551
11552 format %{ "Encode ascii array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11553 ins_encode %{
11554 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11555 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11556 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, true);
11557 %}
11558 ins_pipe( pipe_slow );
11559 %}
11560
11561 //----------Overflow Math Instructions-----------------------------------------
11562
11563 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11564 %{
11565 match(Set cr (OverflowAddI op1 op2));
11566 effect(DEF cr, USE_KILL op1, USE op2);
11567
11568 format %{ "addl $op1, $op2\t# overflow check int" %}
11569
11570 ins_encode %{
11571 __ addl($op1$$Register, $op2$$Register);
11572 %}
11573 ins_pipe(ialu_reg_reg);
11574 %}
11575
11576 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11577 %{
11578 match(Set cr (OverflowAddI op1 op2));
11579 effect(DEF cr, USE_KILL op1, USE op2);
11580
11581 format %{ "addl $op1, $op2\t# overflow check int" %}
11582
11583 ins_encode %{
11584 __ addl($op1$$Register, $op2$$constant);
11585 %}
11586 ins_pipe(ialu_reg_reg);
11587 %}
11588
11589 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11590 %{
11591 match(Set cr (OverflowAddL op1 op2));
11592 effect(DEF cr, USE_KILL op1, USE op2);
11593
11594 format %{ "addq $op1, $op2\t# overflow check long" %}
11595 ins_encode %{
11596 __ addq($op1$$Register, $op2$$Register);
11597 %}
11598 ins_pipe(ialu_reg_reg);
11599 %}
11600
11601 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11602 %{
11603 match(Set cr (OverflowAddL op1 op2));
11604 effect(DEF cr, USE_KILL op1, USE op2);
11605
11606 format %{ "addq $op1, $op2\t# overflow check long" %}
11607 ins_encode %{
11608 __ addq($op1$$Register, $op2$$constant);
11609 %}
11610 ins_pipe(ialu_reg_reg);
11611 %}
11612
11613 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11614 %{
11615 match(Set cr (OverflowSubI op1 op2));
11616
11617 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11618 ins_encode %{
11619 __ cmpl($op1$$Register, $op2$$Register);
11620 %}
11621 ins_pipe(ialu_reg_reg);
11622 %}
11623
11624 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11625 %{
11626 match(Set cr (OverflowSubI op1 op2));
11627
11628 format %{ "cmpl $op1, $op2\t# overflow check int" %}
11629 ins_encode %{
11630 __ cmpl($op1$$Register, $op2$$constant);
11631 %}
11632 ins_pipe(ialu_reg_reg);
11633 %}
11634
11635 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11636 %{
11637 match(Set cr (OverflowSubL op1 op2));
11638
11639 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11640 ins_encode %{
11641 __ cmpq($op1$$Register, $op2$$Register);
11642 %}
11643 ins_pipe(ialu_reg_reg);
11644 %}
11645
11646 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11647 %{
11648 match(Set cr (OverflowSubL op1 op2));
11649
11650 format %{ "cmpq $op1, $op2\t# overflow check long" %}
11651 ins_encode %{
11652 __ cmpq($op1$$Register, $op2$$constant);
11653 %}
11654 ins_pipe(ialu_reg_reg);
11655 %}
11656
11657 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
11658 %{
11659 match(Set cr (OverflowSubI zero op2));
11660 effect(DEF cr, USE_KILL op2);
11661
11662 format %{ "negl $op2\t# overflow check int" %}
11663 ins_encode %{
11664 __ negl($op2$$Register);
11665 %}
11666 ins_pipe(ialu_reg_reg);
11667 %}
11668
11669 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11670 %{
11671 match(Set cr (OverflowSubL zero op2));
11672 effect(DEF cr, USE_KILL op2);
11673
11674 format %{ "negq $op2\t# overflow check long" %}
11675 ins_encode %{
11676 __ negq($op2$$Register);
11677 %}
11678 ins_pipe(ialu_reg_reg);
11679 %}
11680
11681 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11682 %{
11683 match(Set cr (OverflowMulI op1 op2));
11684 effect(DEF cr, USE_KILL op1, USE op2);
11685
11686 format %{ "imull $op1, $op2\t# overflow check int" %}
11687 ins_encode %{
11688 __ imull($op1$$Register, $op2$$Register);
11689 %}
11690 ins_pipe(ialu_reg_reg_alu0);
11691 %}
11692
11693 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11694 %{
11695 match(Set cr (OverflowMulI op1 op2));
11696 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11697
11698 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
11699 ins_encode %{
11700 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11701 %}
11702 ins_pipe(ialu_reg_reg_alu0);
11703 %}
11704
11705 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11706 %{
11707 match(Set cr (OverflowMulL op1 op2));
11708 effect(DEF cr, USE_KILL op1, USE op2);
11709
11710 format %{ "imulq $op1, $op2\t# overflow check long" %}
11711 ins_encode %{
11712 __ imulq($op1$$Register, $op2$$Register);
11713 %}
11714 ins_pipe(ialu_reg_reg_alu0);
11715 %}
11716
11717 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11718 %{
11719 match(Set cr (OverflowMulL op1 op2));
11720 effect(DEF cr, TEMP tmp, USE op1, USE op2);
11721
11722 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
11723 ins_encode %{
11724 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11725 %}
11726 ins_pipe(ialu_reg_reg_alu0);
11727 %}
11728
11729
11730 //----------Control Flow Instructions------------------------------------------
11731 // Signed compare Instructions
11732
11733 // XXX more variants!!
11734 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11735 %{
11736 match(Set cr (CmpI op1 op2));
11737 effect(DEF cr, USE op1, USE op2);
11738
11739 format %{ "cmpl $op1, $op2" %}
11740 ins_encode %{
11741 __ cmpl($op1$$Register, $op2$$Register);
11742 %}
11743 ins_pipe(ialu_cr_reg_reg);
11744 %}
11745
11746 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11747 %{
11748 match(Set cr (CmpI op1 op2));
11749
11750 format %{ "cmpl $op1, $op2" %}
11751 ins_encode %{
11752 __ cmpl($op1$$Register, $op2$$constant);
11753 %}
11754 ins_pipe(ialu_cr_reg_imm);
11755 %}
11756
11757 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11758 %{
11759 match(Set cr (CmpI op1 (LoadI op2)));
11760
11761 ins_cost(500); // XXX
11762 format %{ "cmpl $op1, $op2" %}
11763 ins_encode %{
11764 __ cmpl($op1$$Register, $op2$$Address);
11765 %}
11766 ins_pipe(ialu_cr_reg_mem);
11767 %}
11768
11769 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
11770 %{
11771 match(Set cr (CmpI src zero));
11772
11773 format %{ "testl $src, $src" %}
11774 ins_encode %{
11775 __ testl($src$$Register, $src$$Register);
11776 %}
11777 ins_pipe(ialu_cr_reg_imm);
11778 %}
11779
11780 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
11781 %{
11782 match(Set cr (CmpI (AndI src con) zero));
11783
11784 format %{ "testl $src, $con" %}
11785 ins_encode %{
11786 __ testl($src$$Register, $con$$constant);
11787 %}
11788 ins_pipe(ialu_cr_reg_imm);
11789 %}
11790
11791 instruct testI_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2, immI_0 zero)
11792 %{
11793 match(Set cr (CmpI (AndI src1 src2) zero));
11794
11795 format %{ "testl $src1, $src2" %}
11796 ins_encode %{
11797 __ testl($src1$$Register, $src2$$Register);
11798 %}
11799 ins_pipe(ialu_cr_reg_imm);
11800 %}
11801
11802 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
11803 %{
11804 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11805
11806 format %{ "testl $src, $mem" %}
11807 ins_encode %{
11808 __ testl($src$$Register, $mem$$Address);
11809 %}
11810 ins_pipe(ialu_cr_reg_mem);
11811 %}
11812
11813 // Unsigned compare Instructions; really, same as signed except they
11814 // produce an rFlagsRegU instead of rFlagsReg.
11815 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11816 %{
11817 match(Set cr (CmpU op1 op2));
11818
11819 format %{ "cmpl $op1, $op2\t# unsigned" %}
11820 ins_encode %{
11821 __ cmpl($op1$$Register, $op2$$Register);
11822 %}
11823 ins_pipe(ialu_cr_reg_reg);
11824 %}
11825
11826 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11827 %{
11828 match(Set cr (CmpU op1 op2));
11829
11830 format %{ "cmpl $op1, $op2\t# unsigned" %}
11831 ins_encode %{
11832 __ cmpl($op1$$Register, $op2$$constant);
11833 %}
11834 ins_pipe(ialu_cr_reg_imm);
11835 %}
11836
11837 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11838 %{
11839 match(Set cr (CmpU op1 (LoadI op2)));
11840
11841 ins_cost(500); // XXX
11842 format %{ "cmpl $op1, $op2\t# unsigned" %}
11843 ins_encode %{
11844 __ cmpl($op1$$Register, $op2$$Address);
11845 %}
11846 ins_pipe(ialu_cr_reg_mem);
11847 %}
11848
11849 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
11850 %{
11851 match(Set cr (CmpU src zero));
11852
11853 format %{ "testl $src, $src\t# unsigned" %}
11854 ins_encode %{
11855 __ testl($src$$Register, $src$$Register);
11856 %}
11857 ins_pipe(ialu_cr_reg_imm);
11858 %}
11859
11860 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11861 %{
11862 match(Set cr (CmpP op1 op2));
11863
11864 format %{ "cmpq $op1, $op2\t# ptr" %}
11865 ins_encode %{
11866 __ cmpq($op1$$Register, $op2$$Register);
11867 %}
11868 ins_pipe(ialu_cr_reg_reg);
11869 %}
11870
11871 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11872 %{
11873 match(Set cr (CmpP op1 (LoadP op2)));
11874 predicate(n->in(2)->as_Load()->barrier_data() == 0);
11875
11876 ins_cost(500); // XXX
11877 format %{ "cmpq $op1, $op2\t# ptr" %}
11878 ins_encode %{
11879 __ cmpq($op1$$Register, $op2$$Address);
11880 %}
11881 ins_pipe(ialu_cr_reg_mem);
11882 %}
11883
11884 // XXX this is generalized by compP_rReg_mem???
11885 // Compare raw pointer (used in out-of-heap check).
11886 // Only works because non-oop pointers must be raw pointers
11887 // and raw pointers have no anti-dependencies.
11888 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11889 %{
11890 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
11891 n->in(2)->as_Load()->barrier_data() == 0);
11892 match(Set cr (CmpP op1 (LoadP op2)));
11893
11894 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11895 ins_encode %{
11896 __ cmpq($op1$$Register, $op2$$Address);
11897 %}
11898 ins_pipe(ialu_cr_reg_mem);
11899 %}
11900
11901 // This will generate a signed flags result. This should be OK since
11902 // any compare to a zero should be eq/neq.
11903 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11904 %{
11905 match(Set cr (CmpP src zero));
11906
11907 format %{ "testq $src, $src\t# ptr" %}
11908 ins_encode %{
11909 __ testq($src$$Register, $src$$Register);
11910 %}
11911 ins_pipe(ialu_cr_reg_imm);
11912 %}
11913
11914 // This will generate a signed flags result. This should be OK since
11915 // any compare to a zero should be eq/neq.
11916 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11917 %{
11918 predicate((!UseCompressedOops || (CompressedOops::base() != nullptr)) &&
11919 n->in(1)->as_Load()->barrier_data() == 0);
11920 match(Set cr (CmpP (LoadP op) zero));
11921
11922 ins_cost(500); // XXX
11923 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11924 ins_encode %{
11925 __ testq($op$$Address, 0xFFFFFFFF);
11926 %}
11927 ins_pipe(ialu_cr_reg_imm);
11928 %}
11929
11930 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11931 %{
11932 predicate(UseCompressedOops && (CompressedOops::base() == nullptr) &&
11933 n->in(1)->as_Load()->barrier_data() == 0);
11934 match(Set cr (CmpP (LoadP mem) zero));
11935
11936 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11937 ins_encode %{
11938 __ cmpq(r12, $mem$$Address);
11939 %}
11940 ins_pipe(ialu_cr_reg_mem);
11941 %}
11942
11943 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11944 %{
11945 match(Set cr (CmpN op1 op2));
11946
11947 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11948 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11949 ins_pipe(ialu_cr_reg_reg);
11950 %}
11951
11952 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11953 %{
11954 match(Set cr (CmpN src (LoadN mem)));
11955
11956 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11957 ins_encode %{
11958 __ cmpl($src$$Register, $mem$$Address);
11959 %}
11960 ins_pipe(ialu_cr_reg_mem);
11961 %}
11962
11963 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11964 match(Set cr (CmpN op1 op2));
11965
11966 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11967 ins_encode %{
11968 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11969 %}
11970 ins_pipe(ialu_cr_reg_imm);
11971 %}
11972
11973 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11974 %{
11975 match(Set cr (CmpN src (LoadN mem)));
11976
11977 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11978 ins_encode %{
11979 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11980 %}
11981 ins_pipe(ialu_cr_reg_mem);
11982 %}
11983
11984 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11985 match(Set cr (CmpN op1 op2));
11986
11987 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11988 ins_encode %{
11989 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11990 %}
11991 ins_pipe(ialu_cr_reg_imm);
11992 %}
11993
11994 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11995 %{
11996 match(Set cr (CmpN src (LoadNKlass mem)));
11997
11998 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11999 ins_encode %{
12000 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
12001 %}
12002 ins_pipe(ialu_cr_reg_mem);
12003 %}
12004
12005 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
12006 match(Set cr (CmpN src zero));
12007
12008 format %{ "testl $src, $src\t# compressed ptr" %}
12009 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
12010 ins_pipe(ialu_cr_reg_imm);
12011 %}
12012
12013 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
12014 %{
12015 predicate(CompressedOops::base() != nullptr);
12016 match(Set cr (CmpN (LoadN mem) zero));
12017
12018 ins_cost(500); // XXX
12019 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
12020 ins_encode %{
12021 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
12022 %}
12023 ins_pipe(ialu_cr_reg_mem);
12024 %}
12025
12026 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
12027 %{
12028 predicate(CompressedOops::base() == nullptr);
12029 match(Set cr (CmpN (LoadN mem) zero));
12030
12031 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
12032 ins_encode %{
12033 __ cmpl(r12, $mem$$Address);
12034 %}
12035 ins_pipe(ialu_cr_reg_mem);
12036 %}
12037
12038 // Yanked all unsigned pointer compare operations.
12039 // Pointer compares are done with CmpP which is already unsigned.
12040
12041 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
12042 %{
12043 match(Set cr (CmpL op1 op2));
12044
12045 format %{ "cmpq $op1, $op2" %}
12046 ins_encode %{
12047 __ cmpq($op1$$Register, $op2$$Register);
12048 %}
12049 ins_pipe(ialu_cr_reg_reg);
12050 %}
12051
12052 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
12053 %{
12054 match(Set cr (CmpL op1 op2));
12055
12056 format %{ "cmpq $op1, $op2" %}
12057 ins_encode %{
12058 __ cmpq($op1$$Register, $op2$$constant);
12059 %}
12060 ins_pipe(ialu_cr_reg_imm);
12061 %}
12062
12063 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
12064 %{
12065 match(Set cr (CmpL op1 (LoadL op2)));
12066
12067 format %{ "cmpq $op1, $op2" %}
12068 ins_encode %{
12069 __ cmpq($op1$$Register, $op2$$Address);
12070 %}
12071 ins_pipe(ialu_cr_reg_mem);
12072 %}
12073
12074 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
12075 %{
12076 match(Set cr (CmpL src zero));
12077
12078 format %{ "testq $src, $src" %}
12079 ins_encode %{
12080 __ testq($src$$Register, $src$$Register);
12081 %}
12082 ins_pipe(ialu_cr_reg_imm);
12083 %}
12084
12085 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
12086 %{
12087 match(Set cr (CmpL (AndL src con) zero));
12088
12089 format %{ "testq $src, $con\t# long" %}
12090 ins_encode %{
12091 __ testq($src$$Register, $con$$constant);
12092 %}
12093 ins_pipe(ialu_cr_reg_imm);
12094 %}
12095
12096 instruct testL_reg_reg(rFlagsReg cr, rRegL src1, rRegL src2, immL0 zero)
12097 %{
12098 match(Set cr (CmpL (AndL src1 src2) zero));
12099
12100 format %{ "testq $src1, $src2\t# long" %}
12101 ins_encode %{
12102 __ testq($src1$$Register, $src2$$Register);
12103 %}
12104 ins_pipe(ialu_cr_reg_imm);
12105 %}
12106
12107 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
12108 %{
12109 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
12110
12111 format %{ "testq $src, $mem" %}
12112 ins_encode %{
12113 __ testq($src$$Register, $mem$$Address);
12114 %}
12115 ins_pipe(ialu_cr_reg_mem);
12116 %}
12117
12118 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12119 %{
12120 match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12121
12122 format %{ "testq $src, $mem" %}
12123 ins_encode %{
12124 __ testq($src$$Register, $mem$$Address);
12125 %}
12126 ins_pipe(ialu_cr_reg_mem);
12127 %}
12128
12129 // Manifest a CmpU result in an integer register. Very painful.
12130 // This is the test to avoid.
12131 instruct cmpU3_reg_reg(rRegI dst, rRegI src1, rRegI src2, rFlagsReg flags)
12132 %{
12133 match(Set dst (CmpU3 src1 src2));
12134 effect(KILL flags);
12135
12136 ins_cost(275); // XXX
12137 format %{ "cmpl $src1, $src2\t# CmpL3\n\t"
12138 "movl $dst, -1\n\t"
12139 "jb,u done\n\t"
12140 "setne $dst\n\t"
12141 "movzbl $dst, $dst\n\t"
12142 "done:" %}
12143 ins_encode %{
12144 Label done;
12145 __ cmpl($src1$$Register, $src2$$Register);
12146 __ movl($dst$$Register, -1);
12147 __ jccb(Assembler::below, done);
12148 __ setb(Assembler::notZero, $dst$$Register);
12149 __ movzbl($dst$$Register, $dst$$Register);
12150 __ bind(done);
12151 %}
12152 ins_pipe(pipe_slow);
12153 %}
12154
12155 // Manifest a CmpL result in an integer register. Very painful.
12156 // This is the test to avoid.
12157 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12158 %{
12159 match(Set dst (CmpL3 src1 src2));
12160 effect(KILL flags);
12161
12162 ins_cost(275); // XXX
12163 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12164 "movl $dst, -1\n\t"
12165 "jl,s done\n\t"
12166 "setne $dst\n\t"
12167 "movzbl $dst, $dst\n\t"
12168 "done:" %}
12169 ins_encode %{
12170 Label done;
12171 __ cmpq($src1$$Register, $src2$$Register);
12172 __ movl($dst$$Register, -1);
12173 __ jccb(Assembler::less, done);
12174 __ setb(Assembler::notZero, $dst$$Register);
12175 __ movzbl($dst$$Register, $dst$$Register);
12176 __ bind(done);
12177 %}
12178 ins_pipe(pipe_slow);
12179 %}
12180
12181 // Manifest a CmpUL result in an integer register. Very painful.
12182 // This is the test to avoid.
12183 instruct cmpUL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12184 %{
12185 match(Set dst (CmpUL3 src1 src2));
12186 effect(KILL flags);
12187
12188 ins_cost(275); // XXX
12189 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
12190 "movl $dst, -1\n\t"
12191 "jb,u done\n\t"
12192 "setne $dst\n\t"
12193 "movzbl $dst, $dst\n\t"
12194 "done:" %}
12195 ins_encode %{
12196 Label done;
12197 __ cmpq($src1$$Register, $src2$$Register);
12198 __ movl($dst$$Register, -1);
12199 __ jccb(Assembler::below, done);
12200 __ setb(Assembler::notZero, $dst$$Register);
12201 __ movzbl($dst$$Register, $dst$$Register);
12202 __ bind(done);
12203 %}
12204 ins_pipe(pipe_slow);
12205 %}
12206
12207 // Unsigned long compare Instructions; really, same as signed long except they
12208 // produce an rFlagsRegU instead of rFlagsReg.
12209 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12210 %{
12211 match(Set cr (CmpUL op1 op2));
12212
12213 format %{ "cmpq $op1, $op2\t# unsigned" %}
12214 ins_encode %{
12215 __ cmpq($op1$$Register, $op2$$Register);
12216 %}
12217 ins_pipe(ialu_cr_reg_reg);
12218 %}
12219
12220 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12221 %{
12222 match(Set cr (CmpUL op1 op2));
12223
12224 format %{ "cmpq $op1, $op2\t# unsigned" %}
12225 ins_encode %{
12226 __ cmpq($op1$$Register, $op2$$constant);
12227 %}
12228 ins_pipe(ialu_cr_reg_imm);
12229 %}
12230
12231 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12232 %{
12233 match(Set cr (CmpUL op1 (LoadL op2)));
12234
12235 format %{ "cmpq $op1, $op2\t# unsigned" %}
12236 ins_encode %{
12237 __ cmpq($op1$$Register, $op2$$Address);
12238 %}
12239 ins_pipe(ialu_cr_reg_mem);
12240 %}
12241
12242 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12243 %{
12244 match(Set cr (CmpUL src zero));
12245
12246 format %{ "testq $src, $src\t# unsigned" %}
12247 ins_encode %{
12248 __ testq($src$$Register, $src$$Register);
12249 %}
12250 ins_pipe(ialu_cr_reg_imm);
12251 %}
12252
12253 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12254 %{
12255 match(Set cr (CmpI (LoadB mem) imm));
12256
12257 ins_cost(125);
12258 format %{ "cmpb $mem, $imm" %}
12259 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12260 ins_pipe(ialu_cr_reg_mem);
12261 %}
12262
12263 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU7 imm, immI_0 zero)
12264 %{
12265 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12266
12267 ins_cost(125);
12268 format %{ "testb $mem, $imm\t# ubyte" %}
12269 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12270 ins_pipe(ialu_cr_reg_mem);
12271 %}
12272
12273 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
12274 %{
12275 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12276
12277 ins_cost(125);
12278 format %{ "testb $mem, $imm\t# byte" %}
12279 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12280 ins_pipe(ialu_cr_reg_mem);
12281 %}
12282
12283 //----------Max and Min--------------------------------------------------------
12284 // Min Instructions
12285
12286 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12287 %{
12288 effect(USE_DEF dst, USE src, USE cr);
12289
12290 format %{ "cmovlgt $dst, $src\t# min" %}
12291 ins_encode %{
12292 __ cmovl(Assembler::greater, $dst$$Register, $src$$Register);
12293 %}
12294 ins_pipe(pipe_cmov_reg);
12295 %}
12296
12297
12298 instruct minI_rReg(rRegI dst, rRegI src)
12299 %{
12300 match(Set dst (MinI dst src));
12301
12302 ins_cost(200);
12303 expand %{
12304 rFlagsReg cr;
12305 compI_rReg(cr, dst, src);
12306 cmovI_reg_g(dst, src, cr);
12307 %}
12308 %}
12309
12310 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12311 %{
12312 effect(USE_DEF dst, USE src, USE cr);
12313
12314 format %{ "cmovllt $dst, $src\t# max" %}
12315 ins_encode %{
12316 __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
12317 %}
12318 ins_pipe(pipe_cmov_reg);
12319 %}
12320
12321
12322 instruct maxI_rReg(rRegI dst, rRegI src)
12323 %{
12324 match(Set dst (MaxI dst src));
12325
12326 ins_cost(200);
12327 expand %{
12328 rFlagsReg cr;
12329 compI_rReg(cr, dst, src);
12330 cmovI_reg_l(dst, src, cr);
12331 %}
12332 %}
12333
12334 // ============================================================================
12335 // Branch Instructions
12336
12337 // Jump Direct - Label defines a relative address from JMP+1
12338 instruct jmpDir(label labl)
12339 %{
12340 match(Goto);
12341 effect(USE labl);
12342
12343 ins_cost(300);
12344 format %{ "jmp $labl" %}
12345 size(5);
12346 ins_encode %{
12347 Label* L = $labl$$label;
12348 __ jmp(*L, false); // Always long jump
12349 %}
12350 ins_pipe(pipe_jmp);
12351 %}
12352
12353 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12354 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12355 %{
12356 match(If cop cr);
12357 effect(USE labl);
12358
12359 ins_cost(300);
12360 format %{ "j$cop $labl" %}
12361 size(6);
12362 ins_encode %{
12363 Label* L = $labl$$label;
12364 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12365 %}
12366 ins_pipe(pipe_jcc);
12367 %}
12368
12369 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12370 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12371 %{
12372 match(CountedLoopEnd cop cr);
12373 effect(USE labl);
12374
12375 ins_cost(300);
12376 format %{ "j$cop $labl\t# loop end" %}
12377 size(6);
12378 ins_encode %{
12379 Label* L = $labl$$label;
12380 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12381 %}
12382 ins_pipe(pipe_jcc);
12383 %}
12384
12385 // Jump Direct Conditional - using unsigned comparison
12386 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12387 match(If cop cmp);
12388 effect(USE labl);
12389
12390 ins_cost(300);
12391 format %{ "j$cop,u $labl" %}
12392 size(6);
12393 ins_encode %{
12394 Label* L = $labl$$label;
12395 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12396 %}
12397 ins_pipe(pipe_jcc);
12398 %}
12399
12400 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12401 match(If cop cmp);
12402 effect(USE labl);
12403
12404 ins_cost(200);
12405 format %{ "j$cop,u $labl" %}
12406 size(6);
12407 ins_encode %{
12408 Label* L = $labl$$label;
12409 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12410 %}
12411 ins_pipe(pipe_jcc);
12412 %}
12413
12414 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12415 match(If cop cmp);
12416 effect(USE labl);
12417
12418 ins_cost(200);
12419 format %{ $$template
12420 if ($cop$$cmpcode == Assembler::notEqual) {
12421 $$emit$$"jp,u $labl\n\t"
12422 $$emit$$"j$cop,u $labl"
12423 } else {
12424 $$emit$$"jp,u done\n\t"
12425 $$emit$$"j$cop,u $labl\n\t"
12426 $$emit$$"done:"
12427 }
12428 %}
12429 ins_encode %{
12430 Label* l = $labl$$label;
12431 if ($cop$$cmpcode == Assembler::notEqual) {
12432 __ jcc(Assembler::parity, *l, false);
12433 __ jcc(Assembler::notEqual, *l, false);
12434 } else if ($cop$$cmpcode == Assembler::equal) {
12435 Label done;
12436 __ jccb(Assembler::parity, done);
12437 __ jcc(Assembler::equal, *l, false);
12438 __ bind(done);
12439 } else {
12440 ShouldNotReachHere();
12441 }
12442 %}
12443 ins_pipe(pipe_jcc);
12444 %}
12445
12446 // ============================================================================
12447 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
12448 // superklass array for an instance of the superklass. Set a hidden
12449 // internal cache on a hit (cache is checked with exposed code in
12450 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
12451 // encoding ALSO sets flags.
12452
12453 instruct partialSubtypeCheck(rdi_RegP result,
12454 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12455 rFlagsReg cr)
12456 %{
12457 match(Set result (PartialSubtypeCheck sub super));
12458 effect(KILL rcx, KILL cr);
12459
12460 ins_cost(1100); // slightly larger than the next version
12461 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12462 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12463 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12464 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12465 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
12466 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12467 "xorq $result, $result\t\t Hit: rdi zero\n\t"
12468 "miss:\t" %}
12469
12470 opcode(0x1); // Force a XOR of RDI
12471 ins_encode(enc_PartialSubtypeCheck());
12472 ins_pipe(pipe_slow);
12473 %}
12474
12475 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12476 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12477 immP0 zero,
12478 rdi_RegP result)
12479 %{
12480 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12481 effect(KILL rcx, KILL result);
12482
12483 ins_cost(1000);
12484 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12485 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12486 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12487 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12488 "jne,s miss\t\t# Missed: flags nz\n\t"
12489 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12490 "miss:\t" %}
12491
12492 opcode(0x0); // No need to XOR RDI
12493 ins_encode(enc_PartialSubtypeCheck());
12494 ins_pipe(pipe_slow);
12495 %}
12496
12497 // ============================================================================
12498 // Branch Instructions -- short offset versions
12499 //
12500 // These instructions are used to replace jumps of a long offset (the default
12501 // match) with jumps of a shorter offset. These instructions are all tagged
12502 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12503 // match rules in general matching. Instead, the ADLC generates a conversion
12504 // method in the MachNode which can be used to do in-place replacement of the
12505 // long variant with the shorter variant. The compiler will determine if a
12506 // branch can be taken by the is_short_branch_offset() predicate in the machine
12507 // specific code section of the file.
12508
12509 // Jump Direct - Label defines a relative address from JMP+1
12510 instruct jmpDir_short(label labl) %{
12511 match(Goto);
12512 effect(USE labl);
12513
12514 ins_cost(300);
12515 format %{ "jmp,s $labl" %}
12516 size(2);
12517 ins_encode %{
12518 Label* L = $labl$$label;
12519 __ jmpb(*L);
12520 %}
12521 ins_pipe(pipe_jmp);
12522 ins_short_branch(1);
12523 %}
12524
12525 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12526 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12527 match(If cop cr);
12528 effect(USE labl);
12529
12530 ins_cost(300);
12531 format %{ "j$cop,s $labl" %}
12532 size(2);
12533 ins_encode %{
12534 Label* L = $labl$$label;
12535 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12536 %}
12537 ins_pipe(pipe_jcc);
12538 ins_short_branch(1);
12539 %}
12540
12541 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12542 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12543 match(CountedLoopEnd cop cr);
12544 effect(USE labl);
12545
12546 ins_cost(300);
12547 format %{ "j$cop,s $labl\t# loop end" %}
12548 size(2);
12549 ins_encode %{
12550 Label* L = $labl$$label;
12551 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12552 %}
12553 ins_pipe(pipe_jcc);
12554 ins_short_branch(1);
12555 %}
12556
12557 // Jump Direct Conditional - using unsigned comparison
12558 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12559 match(If cop cmp);
12560 effect(USE labl);
12561
12562 ins_cost(300);
12563 format %{ "j$cop,us $labl" %}
12564 size(2);
12565 ins_encode %{
12566 Label* L = $labl$$label;
12567 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12568 %}
12569 ins_pipe(pipe_jcc);
12570 ins_short_branch(1);
12571 %}
12572
12573 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12574 match(If cop cmp);
12575 effect(USE labl);
12576
12577 ins_cost(300);
12578 format %{ "j$cop,us $labl" %}
12579 size(2);
12580 ins_encode %{
12581 Label* L = $labl$$label;
12582 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12583 %}
12584 ins_pipe(pipe_jcc);
12585 ins_short_branch(1);
12586 %}
12587
12588 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12589 match(If cop cmp);
12590 effect(USE labl);
12591
12592 ins_cost(300);
12593 format %{ $$template
12594 if ($cop$$cmpcode == Assembler::notEqual) {
12595 $$emit$$"jp,u,s $labl\n\t"
12596 $$emit$$"j$cop,u,s $labl"
12597 } else {
12598 $$emit$$"jp,u,s done\n\t"
12599 $$emit$$"j$cop,u,s $labl\n\t"
12600 $$emit$$"done:"
12601 }
12602 %}
12603 size(4);
12604 ins_encode %{
12605 Label* l = $labl$$label;
12606 if ($cop$$cmpcode == Assembler::notEqual) {
12607 __ jccb(Assembler::parity, *l);
12608 __ jccb(Assembler::notEqual, *l);
12609 } else if ($cop$$cmpcode == Assembler::equal) {
12610 Label done;
12611 __ jccb(Assembler::parity, done);
12612 __ jccb(Assembler::equal, *l);
12613 __ bind(done);
12614 } else {
12615 ShouldNotReachHere();
12616 }
12617 %}
12618 ins_pipe(pipe_jcc);
12619 ins_short_branch(1);
12620 %}
12621
12622 // ============================================================================
12623 // inlined locking and unlocking
12624
12625 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12626 predicate(Compile::current()->use_rtm());
12627 match(Set cr (FastLock object box));
12628 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12629 ins_cost(300);
12630 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12631 ins_encode %{
12632 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12633 $scr$$Register, $cx1$$Register, $cx2$$Register, r15_thread,
12634 _rtm_counters, _stack_rtm_counters,
12635 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12636 true, ra_->C->profile_rtm());
12637 %}
12638 ins_pipe(pipe_slow);
12639 %}
12640
12641 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
12642 predicate(LockingMode != LM_LIGHTWEIGHT && !Compile::current()->use_rtm());
12643 match(Set cr (FastLock object box));
12644 effect(TEMP tmp, TEMP scr, USE_KILL box);
12645 ins_cost(300);
12646 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12647 ins_encode %{
12648 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12649 $scr$$Register, noreg, noreg, r15_thread, nullptr, nullptr, nullptr, false, false);
12650 %}
12651 ins_pipe(pipe_slow);
12652 %}
12653
12654 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12655 predicate(LockingMode != LM_LIGHTWEIGHT);
12656 match(Set cr (FastUnlock object box));
12657 effect(TEMP tmp, USE_KILL box);
12658 ins_cost(300);
12659 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12660 ins_encode %{
12661 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12662 %}
12663 ins_pipe(pipe_slow);
12664 %}
12665
12666 instruct cmpFastLockLightweight(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI rax_reg, rRegP tmp) %{
12667 predicate(LockingMode == LM_LIGHTWEIGHT);
12668 match(Set cr (FastLock object box));
12669 effect(TEMP rax_reg, TEMP tmp, USE_KILL box);
12670 ins_cost(300);
12671 format %{ "fastlock $object,$box\t! kills $box,$rax_reg,$tmp" %}
12672 ins_encode %{
12673 __ fast_lock_lightweight($object$$Register, $box$$Register, $rax_reg$$Register, $tmp$$Register, r15_thread);
12674 %}
12675 ins_pipe(pipe_slow);
12676 %}
12677
12678 instruct cmpFastUnlockLightweight(rFlagsReg cr, rRegP object, rax_RegP rax_reg, rRegP tmp) %{
12679 predicate(LockingMode == LM_LIGHTWEIGHT);
12680 match(Set cr (FastUnlock object rax_reg));
12681 effect(TEMP tmp, USE_KILL rax_reg);
12682 ins_cost(300);
12683 format %{ "fastunlock $object,$rax_reg\t! kills $rax_reg,$tmp" %}
12684 ins_encode %{
12685 __ fast_unlock_lightweight($object$$Register, $rax_reg$$Register, $tmp$$Register, r15_thread);
12686 %}
12687 ins_pipe(pipe_slow);
12688 %}
12689
12690
12691 // ============================================================================
12692 // Safepoint Instructions
12693 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12694 %{
12695 match(SafePoint poll);
12696 effect(KILL cr, USE poll);
12697
12698 format %{ "testl rax, [$poll]\t"
12699 "# Safepoint: poll for GC" %}
12700 ins_cost(125);
12701 size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
12702 ins_encode %{
12703 __ relocate(relocInfo::poll_type);
12704 address pre_pc = __ pc();
12705 __ testl(rax, Address($poll$$Register, 0));
12706 assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
12707 %}
12708 ins_pipe(ialu_reg_mem);
12709 %}
12710
12711 instruct mask_all_evexL(kReg dst, rRegL src) %{
12712 match(Set dst (MaskAll src));
12713 format %{ "mask_all_evexL $dst, $src \t! mask all operation" %}
12714 ins_encode %{
12715 int mask_len = Matcher::vector_length(this);
12716 __ vector_maskall_operation($dst$$KRegister, $src$$Register, mask_len);
12717 %}
12718 ins_pipe( pipe_slow );
12719 %}
12720
12721 instruct mask_all_evexI_GT32(kReg dst, rRegI src, rRegL tmp) %{
12722 predicate(Matcher::vector_length(n) > 32);
12723 match(Set dst (MaskAll src));
12724 effect(TEMP tmp);
12725 format %{ "mask_all_evexI_GT32 $dst, $src \t! using $tmp as TEMP" %}
12726 ins_encode %{
12727 int mask_len = Matcher::vector_length(this);
12728 __ movslq($tmp$$Register, $src$$Register);
12729 __ vector_maskall_operation($dst$$KRegister, $tmp$$Register, mask_len);
12730 %}
12731 ins_pipe( pipe_slow );
12732 %}
12733
12734 // ============================================================================
12735 // Procedure Call/Return Instructions
12736 // Call Java Static Instruction
12737 // Note: If this code changes, the corresponding ret_addr_offset() and
12738 // compute_padding() functions will have to be adjusted.
12739 instruct CallStaticJavaDirect(method meth) %{
12740 match(CallStaticJava);
12741 effect(USE meth);
12742
12743 ins_cost(300);
12744 format %{ "call,static " %}
12745 opcode(0xE8); /* E8 cd */
12746 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
12747 ins_pipe(pipe_slow);
12748 ins_alignment(4);
12749 %}
12750
12751 // Call Java Dynamic Instruction
12752 // Note: If this code changes, the corresponding ret_addr_offset() and
12753 // compute_padding() functions will have to be adjusted.
12754 instruct CallDynamicJavaDirect(method meth)
12755 %{
12756 match(CallDynamicJava);
12757 effect(USE meth);
12758
12759 ins_cost(300);
12760 format %{ "movq rax, #Universe::non_oop_word()\n\t"
12761 "call,dynamic " %}
12762 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
12763 ins_pipe(pipe_slow);
12764 ins_alignment(4);
12765 %}
12766
12767 // Call Runtime Instruction
12768 instruct CallRuntimeDirect(method meth)
12769 %{
12770 match(CallRuntime);
12771 effect(USE meth);
12772
12773 ins_cost(300);
12774 format %{ "call,runtime " %}
12775 ins_encode(clear_avx, Java_To_Runtime(meth));
12776 ins_pipe(pipe_slow);
12777 %}
12778
12779 // Call runtime without safepoint
12780 instruct CallLeafDirect(method meth)
12781 %{
12782 match(CallLeaf);
12783 effect(USE meth);
12784
12785 ins_cost(300);
12786 format %{ "call_leaf,runtime " %}
12787 ins_encode(clear_avx, Java_To_Runtime(meth));
12788 ins_pipe(pipe_slow);
12789 %}
12790
12791 // Call runtime without safepoint and with vector arguments
12792 instruct CallLeafDirectVector(method meth)
12793 %{
12794 match(CallLeafVector);
12795 effect(USE meth);
12796
12797 ins_cost(300);
12798 format %{ "call_leaf,vector " %}
12799 ins_encode(Java_To_Runtime(meth));
12800 ins_pipe(pipe_slow);
12801 %}
12802
12803 // Call runtime without safepoint
12804 // entry point is null, target holds the address to call
12805 instruct CallLeafNoFPInDirect(rRegP target)
12806 %{
12807 predicate(n->as_Call()->entry_point() == nullptr);
12808 match(CallLeafNoFP target);
12809
12810 ins_cost(300);
12811 format %{ "call_leaf_nofp,runtime indirect " %}
12812 ins_encode %{
12813 __ call($target$$Register);
12814 %}
12815
12816 ins_pipe(pipe_slow);
12817 %}
12818
12819 instruct CallLeafNoFPDirect(method meth)
12820 %{
12821 predicate(n->as_Call()->entry_point() != nullptr);
12822 match(CallLeafNoFP);
12823 effect(USE meth);
12824
12825 ins_cost(300);
12826 format %{ "call_leaf_nofp,runtime " %}
12827 ins_encode(clear_avx, Java_To_Runtime(meth));
12828 ins_pipe(pipe_slow);
12829 %}
12830
12831 // Return Instruction
12832 // Remove the return address & jump to it.
12833 // Notice: We always emit a nop after a ret to make sure there is room
12834 // for safepoint patching
12835 instruct Ret()
12836 %{
12837 match(Return);
12838
12839 format %{ "ret" %}
12840 ins_encode %{
12841 __ ret(0);
12842 %}
12843 ins_pipe(pipe_jmp);
12844 %}
12845
12846 // Tail Call; Jump from runtime stub to Java code.
12847 // Also known as an 'interprocedural jump'.
12848 // Target of jump will eventually return to caller.
12849 // TailJump below removes the return address.
12850 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_ptr)
12851 %{
12852 match(TailCall jump_target method_ptr);
12853
12854 ins_cost(300);
12855 format %{ "jmp $jump_target\t# rbx holds method" %}
12856 ins_encode %{
12857 __ jmp($jump_target$$Register);
12858 %}
12859 ins_pipe(pipe_jmp);
12860 %}
12861
12862 // Tail Jump; remove the return address; jump to target.
12863 // TailCall above leaves the return address around.
12864 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
12865 %{
12866 match(TailJump jump_target ex_oop);
12867
12868 ins_cost(300);
12869 format %{ "popq rdx\t# pop return address\n\t"
12870 "jmp $jump_target" %}
12871 ins_encode %{
12872 __ popq(as_Register(RDX_enc));
12873 __ jmp($jump_target$$Register);
12874 %}
12875 ins_pipe(pipe_jmp);
12876 %}
12877
12878 // Create exception oop: created by stack-crawling runtime code.
12879 // Created exception is now available to this handler, and is setup
12880 // just prior to jumping to this handler. No code emitted.
12881 instruct CreateException(rax_RegP ex_oop)
12882 %{
12883 match(Set ex_oop (CreateEx));
12884
12885 size(0);
12886 // use the following format syntax
12887 format %{ "# exception oop is in rax; no code emitted" %}
12888 ins_encode();
12889 ins_pipe(empty);
12890 %}
12891
12892 // Rethrow exception:
12893 // The exception oop will come in the first argument position.
12894 // Then JUMP (not call) to the rethrow stub code.
12895 instruct RethrowException()
12896 %{
12897 match(Rethrow);
12898
12899 // use the following format syntax
12900 format %{ "jmp rethrow_stub" %}
12901 ins_encode %{
12902 __ jump(RuntimeAddress(OptoRuntime::rethrow_stub()), noreg);
12903 %}
12904 ins_pipe(pipe_jmp);
12905 %}
12906
12907 // ============================================================================
12908 // This name is KNOWN by the ADLC and cannot be changed.
12909 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
12910 // for this guy.
12911 instruct tlsLoadP(r15_RegP dst) %{
12912 match(Set dst (ThreadLocal));
12913 effect(DEF dst);
12914
12915 size(0);
12916 format %{ "# TLS is in R15" %}
12917 ins_encode( /*empty encoding*/ );
12918 ins_pipe(ialu_reg_reg);
12919 %}
12920
12921
12922 //----------PEEPHOLE RULES-----------------------------------------------------
12923 // These must follow all instruction definitions as they use the names
12924 // defined in the instructions definitions.
12925 //
12926 // peeppredicate ( rule_predicate );
12927 // // the predicate unless which the peephole rule will be ignored
12928 //
12929 // peepmatch ( root_instr_name [preceding_instruction]* );
12930 //
12931 // peepprocedure ( procedure_name );
12932 // // provide a procedure name to perform the optimization, the procedure should
12933 // // reside in the architecture dependent peephole file, the method has the
12934 // // signature of MachNode* (Block*, int, PhaseRegAlloc*, (MachNode*)(*)(), int...)
12935 // // with the arguments being the basic block, the current node index inside the
12936 // // block, the register allocator, the functions upon invoked return a new node
12937 // // defined in peepreplace, and the rules of the nodes appearing in the
12938 // // corresponding peepmatch, the function return true if successful, else
12939 // // return false
12940 //
12941 // peepconstraint %{
12942 // (instruction_number.operand_name relational_op instruction_number.operand_name
12943 // [, ...] );
12944 // // instruction numbers are zero-based using left to right order in peepmatch
12945 //
12946 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12947 // // provide an instruction_number.operand_name for each operand that appears
12948 // // in the replacement instruction's match rule
12949 //
12950 // ---------VM FLAGS---------------------------------------------------------
12951 //
12952 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12953 //
12954 // Each peephole rule is given an identifying number starting with zero and
12955 // increasing by one in the order seen by the parser. An individual peephole
12956 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12957 // on the command-line.
12958 //
12959 // ---------CURRENT LIMITATIONS----------------------------------------------
12960 //
12961 // Only transformations inside a basic block (do we need more for peephole)
12962 //
12963 // ---------EXAMPLE----------------------------------------------------------
12964 //
12965 // // pertinent parts of existing instructions in architecture description
12966 // instruct movI(rRegI dst, rRegI src)
12967 // %{
12968 // match(Set dst (CopyI src));
12969 // %}
12970 //
12971 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
12972 // %{
12973 // match(Set dst (AddI dst src));
12974 // effect(KILL cr);
12975 // %}
12976 //
12977 // instruct leaI_rReg_immI(rRegI dst, immI_1 src)
12978 // %{
12979 // match(Set dst (AddI dst src));
12980 // %}
12981 //
12982 // 1. Simple replacement
12983 // - Only match adjacent instructions in same basic block
12984 // - Only equality constraints
12985 // - Only constraints between operands, not (0.dest_reg == RAX_enc)
12986 // - Only one replacement instruction
12987 //
12988 // // Change (inc mov) to lea
12989 // peephole %{
12990 // // lea should only be emitted when beneficial
12991 // peeppredicate( VM_Version::supports_fast_2op_lea() );
12992 // // increment preceded by register-register move
12993 // peepmatch ( incI_rReg movI );
12994 // // require that the destination register of the increment
12995 // // match the destination register of the move
12996 // peepconstraint ( 0.dst == 1.dst );
12997 // // construct a replacement instruction that sets
12998 // // the destination to ( move's source register + one )
12999 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
13000 // %}
13001 //
13002 // 2. Procedural replacement
13003 // - More flexible finding relevent nodes
13004 // - More flexible constraints
13005 // - More flexible transformations
13006 // - May utilise architecture-dependent API more effectively
13007 // - Currently only one replacement instruction due to adlc parsing capabilities
13008 //
13009 // // Change (inc mov) to lea
13010 // peephole %{
13011 // // lea should only be emitted when beneficial
13012 // peeppredicate( VM_Version::supports_fast_2op_lea() );
13013 // // the rule numbers of these nodes inside are passed into the function below
13014 // peepmatch ( incI_rReg movI );
13015 // // the method that takes the responsibility of transformation
13016 // peepprocedure ( inc_mov_to_lea );
13017 // // the replacement is a leaI_rReg_immI, a lambda upon invoked creating this
13018 // // node is passed into the function above
13019 // peepreplace ( leaI_rReg_immI() );
13020 // %}
13021
13022 // These instructions is not matched by the matcher but used by the peephole
13023 instruct leaI_rReg_rReg_peep(rRegI dst, rRegI src1, rRegI src2)
13024 %{
13025 predicate(false);
13026 match(Set dst (AddI src1 src2));
13027 format %{ "leal $dst, [$src1 + $src2]" %}
13028 ins_encode %{
13029 Register dst = $dst$$Register;
13030 Register src1 = $src1$$Register;
13031 Register src2 = $src2$$Register;
13032 if (src1 != rbp && src1 != r13) {
13033 __ leal(dst, Address(src1, src2, Address::times_1));
13034 } else {
13035 assert(src2 != rbp && src2 != r13, "");
13036 __ leal(dst, Address(src2, src1, Address::times_1));
13037 }
13038 %}
13039 ins_pipe(ialu_reg_reg);
13040 %}
13041
13042 instruct leaI_rReg_immI_peep(rRegI dst, rRegI src1, immI src2)
13043 %{
13044 predicate(false);
13045 match(Set dst (AddI src1 src2));
13046 format %{ "leal $dst, [$src1 + $src2]" %}
13047 ins_encode %{
13048 __ leal($dst$$Register, Address($src1$$Register, $src2$$constant));
13049 %}
13050 ins_pipe(ialu_reg_reg);
13051 %}
13052
13053 instruct leaI_rReg_immI2_peep(rRegI dst, rRegI src, immI2 shift)
13054 %{
13055 predicate(false);
13056 match(Set dst (LShiftI src shift));
13057 format %{ "leal $dst, [$src << $shift]" %}
13058 ins_encode %{
13059 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($shift$$constant);
13060 Register src = $src$$Register;
13061 if (scale == Address::times_2 && src != rbp && src != r13) {
13062 __ leal($dst$$Register, Address(src, src, Address::times_1));
13063 } else {
13064 __ leal($dst$$Register, Address(noreg, src, scale));
13065 }
13066 %}
13067 ins_pipe(ialu_reg_reg);
13068 %}
13069
13070 instruct leaL_rReg_rReg_peep(rRegL dst, rRegL src1, rRegL src2)
13071 %{
13072 predicate(false);
13073 match(Set dst (AddL src1 src2));
13074 format %{ "leaq $dst, [$src1 + $src2]" %}
13075 ins_encode %{
13076 Register dst = $dst$$Register;
13077 Register src1 = $src1$$Register;
13078 Register src2 = $src2$$Register;
13079 if (src1 != rbp && src1 != r13) {
13080 __ leaq(dst, Address(src1, src2, Address::times_1));
13081 } else {
13082 assert(src2 != rbp && src2 != r13, "");
13083 __ leaq(dst, Address(src2, src1, Address::times_1));
13084 }
13085 %}
13086 ins_pipe(ialu_reg_reg);
13087 %}
13088
13089 instruct leaL_rReg_immL32_peep(rRegL dst, rRegL src1, immL32 src2)
13090 %{
13091 predicate(false);
13092 match(Set dst (AddL src1 src2));
13093 format %{ "leaq $dst, [$src1 + $src2]" %}
13094 ins_encode %{
13095 __ leaq($dst$$Register, Address($src1$$Register, $src2$$constant));
13096 %}
13097 ins_pipe(ialu_reg_reg);
13098 %}
13099
13100 instruct leaL_rReg_immI2_peep(rRegL dst, rRegL src, immI2 shift)
13101 %{
13102 predicate(false);
13103 match(Set dst (LShiftL src shift));
13104 format %{ "leaq $dst, [$src << $shift]" %}
13105 ins_encode %{
13106 Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($shift$$constant);
13107 Register src = $src$$Register;
13108 if (scale == Address::times_2 && src != rbp && src != r13) {
13109 __ leaq($dst$$Register, Address(src, src, Address::times_1));
13110 } else {
13111 __ leaq($dst$$Register, Address(noreg, src, scale));
13112 }
13113 %}
13114 ins_pipe(ialu_reg_reg);
13115 %}
13116
13117 // These peephole rules replace mov + I pairs (where I is one of {add, inc, dec,
13118 // sal}) with lea instructions. The {add, sal} rules are beneficial in
13119 // processors with at least partial ALU support for lea
13120 // (supports_fast_2op_lea()), whereas the {inc, dec} rules are only generally
13121 // beneficial for processors with full ALU support
13122 // (VM_Version::supports_fast_3op_lea()) and Intel Cascade Lake.
13123
13124 peephole
13125 %{
13126 peeppredicate(VM_Version::supports_fast_2op_lea());
13127 peepmatch (addI_rReg);
13128 peepprocedure (lea_coalesce_reg);
13129 peepreplace (leaI_rReg_rReg_peep());
13130 %}
13131
13132 peephole
13133 %{
13134 peeppredicate(VM_Version::supports_fast_2op_lea());
13135 peepmatch (addI_rReg_imm);
13136 peepprocedure (lea_coalesce_imm);
13137 peepreplace (leaI_rReg_immI_peep());
13138 %}
13139
13140 peephole
13141 %{
13142 peeppredicate(VM_Version::supports_fast_3op_lea() ||
13143 VM_Version::is_intel_cascade_lake());
13144 peepmatch (incI_rReg);
13145 peepprocedure (lea_coalesce_imm);
13146 peepreplace (leaI_rReg_immI_peep());
13147 %}
13148
13149 peephole
13150 %{
13151 peeppredicate(VM_Version::supports_fast_3op_lea() ||
13152 VM_Version::is_intel_cascade_lake());
13153 peepmatch (decI_rReg);
13154 peepprocedure (lea_coalesce_imm);
13155 peepreplace (leaI_rReg_immI_peep());
13156 %}
13157
13158 peephole
13159 %{
13160 peeppredicate(VM_Version::supports_fast_2op_lea());
13161 peepmatch (salI_rReg_immI2);
13162 peepprocedure (lea_coalesce_imm);
13163 peepreplace (leaI_rReg_immI2_peep());
13164 %}
13165
13166 peephole
13167 %{
13168 peeppredicate(VM_Version::supports_fast_2op_lea());
13169 peepmatch (addL_rReg);
13170 peepprocedure (lea_coalesce_reg);
13171 peepreplace (leaL_rReg_rReg_peep());
13172 %}
13173
13174 peephole
13175 %{
13176 peeppredicate(VM_Version::supports_fast_2op_lea());
13177 peepmatch (addL_rReg_imm);
13178 peepprocedure (lea_coalesce_imm);
13179 peepreplace (leaL_rReg_immL32_peep());
13180 %}
13181
13182 peephole
13183 %{
13184 peeppredicate(VM_Version::supports_fast_3op_lea() ||
13185 VM_Version::is_intel_cascade_lake());
13186 peepmatch (incL_rReg);
13187 peepprocedure (lea_coalesce_imm);
13188 peepreplace (leaL_rReg_immL32_peep());
13189 %}
13190
13191 peephole
13192 %{
13193 peeppredicate(VM_Version::supports_fast_3op_lea() ||
13194 VM_Version::is_intel_cascade_lake());
13195 peepmatch (decL_rReg);
13196 peepprocedure (lea_coalesce_imm);
13197 peepreplace (leaL_rReg_immL32_peep());
13198 %}
13199
13200 peephole
13201 %{
13202 peeppredicate(VM_Version::supports_fast_2op_lea());
13203 peepmatch (salL_rReg_immI2);
13204 peepprocedure (lea_coalesce_imm);
13205 peepreplace (leaL_rReg_immI2_peep());
13206 %}
13207
13208 // These peephole rules matches instructions which set flags and are followed by a testI/L_reg
13209 // The test instruction is redudanent in case the downstream instuctions (like JCC or CMOV) only use flags that are already set by the previous instruction
13210
13211 //int variant
13212 peephole
13213 %{
13214 peepmatch (testI_reg);
13215 peepprocedure (test_may_remove);
13216 %}
13217
13218 //long variant
13219 peephole
13220 %{
13221 peepmatch (testL_reg);
13222 peepprocedure (test_may_remove);
13223 %}
13224
13225
13226 //----------SMARTSPILL RULES---------------------------------------------------
13227 // These must follow all instruction definitions as they use the names
13228 // defined in the instructions definitions.