1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.inline.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_Instruction.hpp"
28 #include "c1/c1_InstructionPrinter.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "compiler/compilerDefinitions.inline.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "runtime/os.hpp"
35 #include "runtime/vm_version.hpp"
36
37 void LIR_Assembler::patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info) {
38 // We must have enough patching space so that call can be inserted.
39 // We cannot use fat nops here, since the concurrent code rewrite may transiently
40 // create the illegal instruction sequence.
41 while ((intx) _masm->pc() - (intx) patch->pc_start() < NativeGeneralJump::instruction_size) {
42 _masm->nop();
43 }
44 info->set_force_reexecute();
45 patch->install(_masm, patch_code, obj, info);
46 append_code_stub(patch);
47
48 #ifdef ASSERT
49 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
50 if (patch->id() == PatchingStub::access_field_id) {
51 switch (code) {
52 case Bytecodes::_putstatic:
53 case Bytecodes::_getstatic:
54 case Bytecodes::_putfield:
55 case Bytecodes::_getfield:
56 break;
57 default:
58 ShouldNotReachHere();
59 }
60 } else if (patch->id() == PatchingStub::load_klass_id) {
61 switch (code) {
62 case Bytecodes::_new:
63 case Bytecodes::_anewarray:
64 case Bytecodes::_multianewarray:
65 case Bytecodes::_instanceof:
66 case Bytecodes::_checkcast:
67 break;
68 default:
69 ShouldNotReachHere();
70 }
71 } else if (patch->id() == PatchingStub::load_mirror_id) {
72 switch (code) {
73 case Bytecodes::_putstatic:
74 case Bytecodes::_getstatic:
75 case Bytecodes::_ldc:
76 case Bytecodes::_ldc_w:
77 case Bytecodes::_ldc2_w:
78 break;
79 default:
80 ShouldNotReachHere();
81 }
82 } else if (patch->id() == PatchingStub::load_appendix_id) {
83 Bytecodes::Code bc_raw = info->scope()->method()->raw_code_at_bci(info->stack()->bci());
84 assert(Bytecodes::has_optional_appendix(bc_raw), "unexpected appendix resolution");
85 } else {
86 ShouldNotReachHere();
87 }
88 #endif
89 }
90
91 PatchingStub::PatchID LIR_Assembler::patching_id(CodeEmitInfo* info) {
92 IRScope* scope = info->scope();
93 Bytecodes::Code bc_raw = scope->method()->raw_code_at_bci(info->stack()->bci());
94 if (Bytecodes::has_optional_appendix(bc_raw)) {
95 return PatchingStub::load_appendix_id;
96 }
97 return PatchingStub::load_mirror_id;
98 }
99
100 //---------------------------------------------------------------
101
102
103 LIR_Assembler::LIR_Assembler(Compilation* c):
104 _masm(c->masm())
105 , _compilation(c)
106 , _frame_map(c->frame_map())
107 , _current_block(nullptr)
108 , _pending_non_safepoint(nullptr)
109 , _pending_non_safepoint_offset(0)
110 , _immediate_oops_patched(0)
111 {
112 _slow_case_stubs = new CodeStubList();
113 }
114
115
116 LIR_Assembler::~LIR_Assembler() {
117 // The unwind handler label may be unnbound if this destructor is invoked because of a bail-out.
118 // Reset it here to avoid an assertion.
119 _unwind_handler_entry.reset();
120 }
121
122
123 void LIR_Assembler::check_codespace() {
124 CodeSection* cs = _masm->code_section();
125 if (cs->remaining() < (int)(NOT_LP64(1*K)LP64_ONLY(2*K))) {
126 BAILOUT("CodeBuffer overflow");
127 }
128 }
129
130
131 void LIR_Assembler::append_code_stub(CodeStub* stub) {
132 _immediate_oops_patched += stub->nr_immediate_oops_patched();
133 _slow_case_stubs->append(stub);
134 }
135
136 void LIR_Assembler::emit_stubs(CodeStubList* stub_list) {
137 for (int m = 0; m < stub_list->length(); m++) {
138 CodeStub* s = stub_list->at(m);
139
140 check_codespace();
141 CHECK_BAILOUT();
142
143 #ifndef PRODUCT
144 if (CommentedAssembly) {
145 stringStream st;
146 s->print_name(&st);
147 st.print(" slow case");
148 _masm->block_comment(st.freeze());
149 }
150 #endif
151 s->emit_code(this);
152 #ifdef ASSERT
153 s->assert_no_unbound_labels();
154 #endif
155 }
156 }
157
158
159 void LIR_Assembler::emit_slow_case_stubs() {
160 emit_stubs(_slow_case_stubs);
161 }
162
163
164 bool LIR_Assembler::needs_icache(ciMethod* method) const {
165 return !method->is_static();
166 }
167
168 bool LIR_Assembler::needs_clinit_barrier_on_entry(ciMethod* method) const {
169 return VM_Version::supports_fast_class_init_checks() && method->needs_clinit_barrier();
170 }
171
172 int LIR_Assembler::code_offset() const {
173 return _masm->offset();
174 }
175
176
177 address LIR_Assembler::pc() const {
178 return _masm->pc();
179 }
180
181 // To bang the stack of this compiled method we use the stack size
182 // that the interpreter would need in case of a deoptimization. This
183 // removes the need to bang the stack in the deoptimization blob which
184 // in turn simplifies stack overflow handling.
185 int LIR_Assembler::bang_size_in_bytes() const {
186 return MAX2(initial_frame_size_in_bytes() + os::extra_bang_size_in_bytes(), _compilation->interpreter_frame_size());
187 }
188
189 void LIR_Assembler::emit_exception_entries(ExceptionInfoList* info_list) {
190 for (int i = 0; i < info_list->length(); i++) {
191 XHandlers* handlers = info_list->at(i)->exception_handlers();
192
193 for (int j = 0; j < handlers->length(); j++) {
194 XHandler* handler = handlers->handler_at(j);
195 assert(handler->lir_op_id() != -1, "handler not processed by LinearScan");
196 assert(handler->entry_code() == nullptr ||
197 handler->entry_code()->instructions_list()->last()->code() == lir_branch ||
198 handler->entry_code()->instructions_list()->last()->code() == lir_delay_slot, "last operation must be branch");
199
200 if (handler->entry_pco() == -1) {
201 // entry code not emitted yet
202 if (handler->entry_code() != nullptr && handler->entry_code()->instructions_list()->length() > 1) {
203 handler->set_entry_pco(code_offset());
204 if (CommentedAssembly) {
205 _masm->block_comment("Exception adapter block");
206 }
207 emit_lir_list(handler->entry_code());
208 } else {
209 handler->set_entry_pco(handler->entry_block()->exception_handler_pco());
210 }
211
212 assert(handler->entry_pco() != -1, "must be set now");
213 }
214 }
215 }
216 }
217
218
219 void LIR_Assembler::emit_code(BlockList* hir) {
220 if (PrintLIR) {
221 print_LIR(hir);
222 }
223
224 int n = hir->length();
225 for (int i = 0; i < n; i++) {
226 emit_block(hir->at(i));
227 CHECK_BAILOUT();
228 }
229
230 flush_debug_info(code_offset());
231
232 DEBUG_ONLY(check_no_unbound_labels());
233 }
234
235
236 void LIR_Assembler::emit_block(BlockBegin* block) {
237 if (block->is_set(BlockBegin::backward_branch_target_flag)) {
238 align_backward_branch_target();
239 }
240
241 // if this block is the start of an exception handler, record the
242 // PC offset of the first instruction for later construction of
243 // the ExceptionHandlerTable
244 if (block->is_set(BlockBegin::exception_entry_flag)) {
245 block->set_exception_handler_pco(code_offset());
246 }
247
248 #ifndef PRODUCT
249 if (PrintLIRWithAssembly) {
250 // don't print Phi's
251 InstructionPrinter ip(false);
252 block->print(ip);
253 }
254 #endif /* PRODUCT */
255
256 assert(block->lir() != nullptr, "must have LIR");
257 X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
258
259 #ifndef PRODUCT
260 if (CommentedAssembly) {
261 stringStream st;
262 st.print_cr(" block B%d [%d, %d]", block->block_id(), block->bci(), block->end()->printable_bci());
263 _masm->block_comment(st.freeze());
264 }
265 #endif
266
267 emit_lir_list(block->lir());
268
269 X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
270 }
271
272
273 void LIR_Assembler::emit_lir_list(LIR_List* list) {
274 peephole(list);
275
276 int n = list->length();
277 for (int i = 0; i < n; i++) {
278 LIR_Op* op = list->at(i);
279
280 check_codespace();
281 CHECK_BAILOUT();
282
283 #ifndef PRODUCT
284 if (CommentedAssembly) {
285 // Don't record out every op since that's too verbose. Print
286 // branches since they include block and stub names. Also print
287 // patching moves since they generate funny looking code.
288 if (op->code() == lir_branch ||
289 (op->code() == lir_move && op->as_Op1()->patch_code() != lir_patch_none) ||
290 (op->code() == lir_leal && op->as_Op1()->patch_code() != lir_patch_none)) {
291 stringStream st;
292 op->print_on(&st);
293 _masm->block_comment(st.freeze());
294 }
295 }
296 if (PrintLIRWithAssembly) {
297 // print out the LIR operation followed by the resulting assembly
298 list->at(i)->print(); tty->cr();
299 }
300 #endif /* PRODUCT */
301
302 op->emit_code(this);
303
304 if (compilation()->debug_info_recorder()->recording_non_safepoints()) {
305 process_debug_info(op);
306 }
307
308 #ifndef PRODUCT
309 if (PrintLIRWithAssembly) {
310 _masm->code()->decode();
311 }
312 #endif /* PRODUCT */
313 }
314 }
315
316 #ifdef ASSERT
317 void LIR_Assembler::check_no_unbound_labels() {
318 CHECK_BAILOUT();
319
320 for (int i = 0; i < _branch_target_blocks.length() - 1; i++) {
321 if (!_branch_target_blocks.at(i)->label()->is_bound()) {
322 tty->print_cr("label of block B%d is not bound", _branch_target_blocks.at(i)->block_id());
323 assert(false, "unbound label");
324 }
325 }
326 }
327 #endif
328
329 //----------------------------------debug info--------------------------------
330
331
332 void LIR_Assembler::add_debug_info_for_branch(CodeEmitInfo* info) {
333 int pc_offset = code_offset();
334 flush_debug_info(pc_offset);
335 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
336 if (info->exception_handlers() != nullptr) {
337 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
338 }
339 }
340
341
342 void LIR_Assembler::add_call_info(int pc_offset, CodeEmitInfo* cinfo) {
343 flush_debug_info(pc_offset);
344 cinfo->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
345 if (cinfo->exception_handlers() != nullptr) {
346 compilation()->add_exception_handlers_for_pco(pc_offset, cinfo->exception_handlers());
347 }
348 }
349
350 static ValueStack* debug_info(Instruction* ins) {
351 StateSplit* ss = ins->as_StateSplit();
352 if (ss != nullptr) return ss->state();
353 return ins->state_before();
354 }
355
356 void LIR_Assembler::process_debug_info(LIR_Op* op) {
357 Instruction* src = op->source();
358 if (src == nullptr) return;
359 int pc_offset = code_offset();
360 if (_pending_non_safepoint == src) {
361 _pending_non_safepoint_offset = pc_offset;
362 return;
363 }
364 ValueStack* vstack = debug_info(src);
365 if (vstack == nullptr) return;
366 if (_pending_non_safepoint != nullptr) {
367 // Got some old debug info. Get rid of it.
368 if (debug_info(_pending_non_safepoint) == vstack) {
369 _pending_non_safepoint_offset = pc_offset;
370 return;
371 }
372 if (_pending_non_safepoint_offset < pc_offset) {
373 record_non_safepoint_debug_info();
374 }
375 _pending_non_safepoint = nullptr;
376 }
377 // Remember the debug info.
378 if (pc_offset > compilation()->debug_info_recorder()->last_pc_offset()) {
379 _pending_non_safepoint = src;
380 _pending_non_safepoint_offset = pc_offset;
381 }
382 }
383
384 // Index caller states in s, where 0 is the oldest, 1 its callee, etc.
385 // Return null if n is too large.
386 // Returns the caller_bci for the next-younger state, also.
387 static ValueStack* nth_oldest(ValueStack* s, int n, int& bci_result) {
388 ValueStack* t = s;
389 for (int i = 0; i < n; i++) {
390 if (t == nullptr) break;
391 t = t->caller_state();
392 }
393 if (t == nullptr) return nullptr;
394 for (;;) {
395 ValueStack* tc = t->caller_state();
396 if (tc == nullptr) return s;
397 t = tc;
398 bci_result = tc->bci();
399 s = s->caller_state();
400 }
401 }
402
403 void LIR_Assembler::record_non_safepoint_debug_info() {
404 int pc_offset = _pending_non_safepoint_offset;
405 ValueStack* vstack = debug_info(_pending_non_safepoint);
406 int bci = vstack->bci();
407
408 DebugInformationRecorder* debug_info = compilation()->debug_info_recorder();
409 assert(debug_info->recording_non_safepoints(), "sanity");
410
411 debug_info->add_non_safepoint(pc_offset);
412
413 // Visit scopes from oldest to youngest.
414 for (int n = 0; ; n++) {
415 int s_bci = bci;
416 ValueStack* s = nth_oldest(vstack, n, s_bci);
417 if (s == nullptr) break;
418 IRScope* scope = s->scope();
419 //Always pass false for reexecute since these ScopeDescs are never used for deopt
420 methodHandle null_mh;
421 debug_info->describe_scope(pc_offset, null_mh, scope->method(), s->bci(), false/*reexecute*/);
422 }
423
424 debug_info->end_non_safepoint(pc_offset);
425 }
426
427
428 ImplicitNullCheckStub* LIR_Assembler::add_debug_info_for_null_check_here(CodeEmitInfo* cinfo) {
429 return add_debug_info_for_null_check(code_offset(), cinfo);
430 }
431
432 ImplicitNullCheckStub* LIR_Assembler::add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo) {
433 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(pc_offset, cinfo);
434 append_code_stub(stub);
435 return stub;
436 }
437
438 void LIR_Assembler::add_debug_info_for_div0_here(CodeEmitInfo* info) {
439 add_debug_info_for_div0(code_offset(), info);
440 }
441
442 void LIR_Assembler::add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo) {
443 DivByZeroStub* stub = new DivByZeroStub(pc_offset, cinfo);
444 append_code_stub(stub);
445 }
446
447 void LIR_Assembler::emit_rtcall(LIR_OpRTCall* op) {
448 rt_call(op->result_opr(), op->addr(), op->arguments(), op->tmp(), op->info());
449 }
450
451 void LIR_Assembler::emit_call(LIR_OpJavaCall* op) {
452 verify_oop_map(op->info());
453
454 // must align calls sites, otherwise they can't be updated atomically
455 align_call(op->code());
456
457 if (CodeBuffer::supports_shared_stubs() && op->method()->can_be_statically_bound()) {
458 // Calls of the same statically bound method can share
459 // a stub to the interpreter.
460 CodeBuffer::csize_t call_offset = pc() - _masm->code()->insts_begin();
461 _masm->code()->shared_stub_to_interp_for(op->method(), call_offset);
462 } else {
463 emit_static_call_stub();
464 }
465 CHECK_BAILOUT();
466
467 switch (op->code()) {
468 case lir_static_call:
469 case lir_dynamic_call:
470 call(op, relocInfo::static_call_type);
471 break;
472 case lir_optvirtual_call:
473 call(op, relocInfo::opt_virtual_call_type);
474 break;
475 case lir_icvirtual_call:
476 ic_call(op);
477 break;
478 default:
479 fatal("unexpected op code: %s", op->name());
480 break;
481 }
482
483 // JSR 292
484 // Record if this method has MethodHandle invokes.
485 if (op->is_method_handle_invoke()) {
486 compilation()->set_has_method_handle_invokes(true);
487 }
488
489 #if defined(IA32) && defined(COMPILER2)
490 // C2 leave fpu stack dirty clean it
491 if (UseSSE < 2 && !CompilerConfig::is_c1_only_no_jvmci()) {
492 int i;
493 for ( i = 1; i <= 7 ; i++ ) {
494 ffree(i);
495 }
496 if (!op->result_opr()->is_float_kind()) {
497 ffree(0);
498 }
499 }
500 #endif // IA32 && COMPILER2
501 }
502
503
504 void LIR_Assembler::emit_opLabel(LIR_OpLabel* op) {
505 _masm->bind (*(op->label()));
506 }
507
508
509 void LIR_Assembler::emit_op1(LIR_Op1* op) {
510 switch (op->code()) {
511 case lir_move:
512 if (op->move_kind() == lir_move_volatile) {
513 assert(op->patch_code() == lir_patch_none, "can't patch volatiles");
514 volatile_move_op(op->in_opr(), op->result_opr(), op->type(), op->info());
515 } else {
516 move_op(op->in_opr(), op->result_opr(), op->type(),
517 op->patch_code(), op->info(), op->pop_fpu_stack(),
518 op->move_kind() == lir_move_wide);
519 }
520 break;
521
522 case lir_roundfp: {
523 LIR_OpRoundFP* round_op = op->as_OpRoundFP();
524 roundfp_op(round_op->in_opr(), round_op->tmp(), round_op->result_opr(), round_op->pop_fpu_stack());
525 break;
526 }
527
528 case lir_abs:
529 case lir_sqrt:
530 case lir_f2hf:
531 case lir_hf2f:
532 intrinsic_op(op->code(), op->in_opr(), op->tmp_opr(), op->result_opr(), op);
533 break;
534
535 case lir_neg:
536 negate(op->in_opr(), op->result_opr(), op->tmp_opr());
537 break;
538
539 case lir_return: {
540 assert(op->as_OpReturn() != nullptr, "sanity");
541 LIR_OpReturn *ret_op = (LIR_OpReturn*)op;
542 return_op(ret_op->in_opr(), ret_op->stub());
543 if (ret_op->stub() != nullptr) {
544 append_code_stub(ret_op->stub());
545 }
546 break;
547 }
548
549 case lir_safepoint:
550 if (compilation()->debug_info_recorder()->last_pc_offset() == code_offset()) {
551 _masm->nop();
552 }
553 safepoint_poll(op->in_opr(), op->info());
554 break;
555
556 #ifdef IA32
557 case lir_fxch:
558 fxch(op->in_opr()->as_jint());
559 break;
560
561 case lir_fld:
562 fld(op->in_opr()->as_jint());
563 break;
564 #endif // IA32
565
566 case lir_branch:
567 break;
568
569 case lir_push:
570 push(op->in_opr());
571 break;
572
573 case lir_pop:
574 pop(op->in_opr());
575 break;
576
577 case lir_leal:
578 leal(op->in_opr(), op->result_opr(), op->patch_code(), op->info());
579 break;
580
581 case lir_null_check: {
582 ImplicitNullCheckStub* stub = add_debug_info_for_null_check_here(op->info());
583
584 if (op->in_opr()->is_single_cpu()) {
585 _masm->null_check(op->in_opr()->as_register(), stub->entry());
586 } else {
587 Unimplemented();
588 }
589 break;
590 }
591
592 case lir_monaddr:
593 monitor_address(op->in_opr()->as_constant_ptr()->as_jint(), op->result_opr());
594 break;
595
596 case lir_unwind:
597 unwind_op(op->in_opr());
598 break;
599
600 default:
601 Unimplemented();
602 break;
603 }
604 }
605
606
607 void LIR_Assembler::emit_op0(LIR_Op0* op) {
608 switch (op->code()) {
609 case lir_nop:
610 assert(op->info() == nullptr, "not supported");
611 _masm->nop();
612 break;
613
614 case lir_label:
615 Unimplemented();
616 break;
617
618 case lir_std_entry: {
619 // init offsets
620 offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
621 if (needs_icache(compilation()->method())) {
622 int offset = check_icache();
623 offsets()->set_value(CodeOffsets::Entry, offset);
624 }
625 _masm->align(CodeEntryAlignment);
626 offsets()->set_value(CodeOffsets::Verified_Entry, _masm->offset());
627 _masm->verified_entry(compilation()->directive()->BreakAtExecuteOption);
628 if (needs_clinit_barrier_on_entry(compilation()->method())) {
629 clinit_barrier(compilation()->method());
630 }
631 build_frame();
632 offsets()->set_value(CodeOffsets::Frame_Complete, _masm->offset());
633 break;
634 }
635
636 case lir_osr_entry:
637 offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
638 osr_entry();
639 break;
640
641 #ifdef IA32
642 case lir_fpop_raw:
643 fpop();
644 break;
645 #endif // IA32
646
647 case lir_breakpoint:
648 breakpoint();
649 break;
650
651 case lir_membar:
652 membar();
653 break;
654
655 case lir_membar_acquire:
656 membar_acquire();
657 break;
658
659 case lir_membar_release:
660 membar_release();
661 break;
662
663 case lir_membar_loadload:
664 membar_loadload();
665 break;
666
667 case lir_membar_storestore:
668 membar_storestore();
669 break;
670
671 case lir_membar_loadstore:
672 membar_loadstore();
673 break;
674
675 case lir_membar_storeload:
676 membar_storeload();
677 break;
678
679 case lir_get_thread:
680 get_thread(op->result_opr());
681 break;
682
683 case lir_on_spin_wait:
684 on_spin_wait();
685 break;
686
687 default:
688 ShouldNotReachHere();
689 break;
690 }
691 }
692
693
694 void LIR_Assembler::emit_op2(LIR_Op2* op) {
695 switch (op->code()) {
696 case lir_cmp:
697 if (op->info() != nullptr) {
698 assert(op->in_opr1()->is_address() || op->in_opr2()->is_address(),
699 "shouldn't be codeemitinfo for non-address operands");
700 add_debug_info_for_null_check_here(op->info()); // exception possible
701 }
702 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
703 break;
704
705 case lir_cmp_l2i:
706 case lir_cmp_fd2i:
707 case lir_ucmp_fd2i:
708 comp_fl2i(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
709 break;
710
711 case lir_shl:
712 case lir_shr:
713 case lir_ushr:
714 if (op->in_opr2()->is_constant()) {
715 shift_op(op->code(), op->in_opr1(), op->in_opr2()->as_constant_ptr()->as_jint(), op->result_opr());
716 } else {
717 shift_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
718 }
719 break;
720
721 case lir_add:
722 case lir_sub:
723 case lir_mul:
724 case lir_div:
725 case lir_rem:
726 assert(op->fpu_pop_count() < 2, "");
727 arith_op(
728 op->code(),
729 op->in_opr1(),
730 op->in_opr2(),
731 op->result_opr(),
732 op->info(),
733 op->fpu_pop_count() == 1);
734 break;
735
736 case lir_logic_and:
737 case lir_logic_or:
738 case lir_logic_xor:
739 logic_op(
740 op->code(),
741 op->in_opr1(),
742 op->in_opr2(),
743 op->result_opr());
744 break;
745
746 case lir_throw:
747 throw_op(op->in_opr1(), op->in_opr2(), op->info());
748 break;
749
750 case lir_xadd:
751 case lir_xchg:
752 atomic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
753 break;
754
755 default:
756 Unimplemented();
757 break;
758 }
759 }
760
761 void LIR_Assembler::emit_op4(LIR_Op4* op) {
762 switch(op->code()) {
763 case lir_cmove:
764 cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->type(), op->in_opr3(), op->in_opr4());
765 break;
766
767 default:
768 Unimplemented();
769 break;
770 }
771 }
772
773 void LIR_Assembler::build_frame() {
774 _masm->build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
775 }
776
777
778 void LIR_Assembler::roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack) {
779 assert(strict_fp_requires_explicit_rounding, "not required");
780 assert((src->is_single_fpu() && dest->is_single_stack()) ||
781 (src->is_double_fpu() && dest->is_double_stack()),
782 "round_fp: rounds register -> stack location");
783
784 reg2stack (src, dest, src->type(), pop_fpu_stack);
785 }
786
787
788 void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
789 if (src->is_register()) {
790 if (dest->is_register()) {
791 assert(patch_code == lir_patch_none && info == nullptr, "no patching and info allowed here");
792 reg2reg(src, dest);
793 } else if (dest->is_stack()) {
794 assert(patch_code == lir_patch_none && info == nullptr, "no patching and info allowed here");
795 reg2stack(src, dest, type, pop_fpu_stack);
796 } else if (dest->is_address()) {
797 reg2mem(src, dest, type, patch_code, info, pop_fpu_stack, wide);
798 } else {
799 ShouldNotReachHere();
800 }
801
802 } else if (src->is_stack()) {
803 assert(patch_code == lir_patch_none && info == nullptr, "no patching and info allowed here");
804 if (dest->is_register()) {
805 stack2reg(src, dest, type);
806 } else if (dest->is_stack()) {
807 stack2stack(src, dest, type);
808 } else {
809 ShouldNotReachHere();
810 }
811
812 } else if (src->is_constant()) {
813 if (dest->is_register()) {
814 const2reg(src, dest, patch_code, info); // patching is possible
815 } else if (dest->is_stack()) {
816 assert(patch_code == lir_patch_none && info == nullptr, "no patching and info allowed here");
817 const2stack(src, dest);
818 } else if (dest->is_address()) {
819 assert(patch_code == lir_patch_none, "no patching allowed here");
820 const2mem(src, dest, type, info, wide);
821 } else {
822 ShouldNotReachHere();
823 }
824
825 } else if (src->is_address()) {
826 mem2reg(src, dest, type, patch_code, info, wide);
827 } else {
828 ShouldNotReachHere();
829 }
830 }
831
832
833 void LIR_Assembler::verify_oop_map(CodeEmitInfo* info) {
834 #ifndef PRODUCT
835 if (VerifyOops) {
836 OopMapStream s(info->oop_map());
837 while (!s.is_done()) {
838 OopMapValue v = s.current();
839 if (v.is_oop()) {
840 VMReg r = v.reg();
841 if (!r->is_stack()) {
842 _masm->verify_oop(r->as_Register());
843 } else {
844 _masm->verify_stack_oop(r->reg2stack() * VMRegImpl::stack_slot_size);
845 }
846 }
847 check_codespace();
848 CHECK_BAILOUT();
849
850 s.next();
851 }
852 }
853 #endif
854 }