1 /*
2 * Copyright (c) 2000, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.inline.hpp"
26 #include "c1/c1_Compilation.hpp"
27 #include "c1/c1_Instruction.hpp"
28 #include "c1/c1_InstructionPrinter.hpp"
29 #include "c1/c1_LIRAssembler.hpp"
30 #include "c1/c1_MacroAssembler.hpp"
31 #include "c1/c1_ValueStack.hpp"
32 #include "compiler/compilerDefinitions.inline.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "runtime/os.hpp"
35 #include "runtime/vm_version.hpp"
36
37 void LIR_Assembler::patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info) {
38 // We must have enough patching space so that call can be inserted.
39 // We cannot use fat nops here, since the concurrent code rewrite may transiently
40 // create the illegal instruction sequence.
41 while ((intx) _masm->pc() - (intx) patch->pc_start() < NativeGeneralJump::instruction_size) {
42 _masm->nop();
43 }
44 info->set_force_reexecute();
45 patch->install(_masm, patch_code, obj, info);
46 append_code_stub(patch);
47
48 #ifdef ASSERT
49 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
50 if (patch->id() == PatchingStub::access_field_id) {
51 switch (code) {
52 case Bytecodes::_putstatic:
53 case Bytecodes::_getstatic:
54 case Bytecodes::_putfield:
55 case Bytecodes::_getfield:
56 break;
57 default:
58 ShouldNotReachHere();
59 }
60 } else if (patch->id() == PatchingStub::load_klass_id) {
61 switch (code) {
62 case Bytecodes::_new:
63 case Bytecodes::_anewarray:
64 case Bytecodes::_multianewarray:
65 case Bytecodes::_instanceof:
66 case Bytecodes::_checkcast:
67 break;
68 default:
69 ShouldNotReachHere();
70 }
71 } else if (patch->id() == PatchingStub::load_mirror_id) {
72 switch (code) {
73 case Bytecodes::_putstatic:
74 case Bytecodes::_getstatic:
75 case Bytecodes::_ldc:
76 case Bytecodes::_ldc_w:
77 case Bytecodes::_ldc2_w:
78 break;
79 default:
80 ShouldNotReachHere();
81 }
82 } else if (patch->id() == PatchingStub::load_appendix_id) {
83 Bytecodes::Code bc_raw = info->scope()->method()->raw_code_at_bci(info->stack()->bci());
84 assert(Bytecodes::has_optional_appendix(bc_raw), "unexpected appendix resolution");
85 } else {
86 ShouldNotReachHere();
87 }
88 #endif
89 }
90
91 PatchingStub::PatchID LIR_Assembler::patching_id(CodeEmitInfo* info) {
92 IRScope* scope = info->scope();
93 Bytecodes::Code bc_raw = scope->method()->raw_code_at_bci(info->stack()->bci());
94 if (Bytecodes::has_optional_appendix(bc_raw)) {
95 return PatchingStub::load_appendix_id;
96 }
97 return PatchingStub::load_mirror_id;
98 }
99
100 //---------------------------------------------------------------
101
102
103 LIR_Assembler::LIR_Assembler(Compilation* c):
104 _masm(c->masm())
105 , _compilation(c)
106 , _frame_map(c->frame_map())
107 , _current_block(nullptr)
108 , _pending_non_safepoint(nullptr)
109 , _pending_non_safepoint_offset(0)
110 , _immediate_oops_patched(0)
111 {
112 _slow_case_stubs = new CodeStubList();
113 }
114
115
116 LIR_Assembler::~LIR_Assembler() {
117 // The unwind handler label may be unnbound if this destructor is invoked because of a bail-out.
118 // Reset it here to avoid an assertion.
119 _unwind_handler_entry.reset();
120 }
121
122
123 void LIR_Assembler::check_codespace() {
124 CodeSection* cs = _masm->code_section();
125 if (cs->remaining() < (int)(NOT_LP64(1*K)LP64_ONLY(2*K))) {
126 BAILOUT("CodeBuffer overflow");
127 }
128 }
129
130
131 void LIR_Assembler::append_code_stub(CodeStub* stub) {
132 _immediate_oops_patched += stub->nr_immediate_oops_patched();
133 _slow_case_stubs->append(stub);
134 }
135
136 void LIR_Assembler::emit_stubs(CodeStubList* stub_list) {
137 for (int m = 0; m < stub_list->length(); m++) {
138 CodeStub* s = stub_list->at(m);
139
140 check_codespace();
141 CHECK_BAILOUT();
142
143 #ifndef PRODUCT
144 if (CommentedAssembly) {
145 stringStream st;
146 s->print_name(&st);
147 st.print(" slow case");
148 _masm->block_comment(st.freeze());
149 }
150 #endif
151 s->emit_code(this);
152 #ifdef ASSERT
153 s->assert_no_unbound_labels();
154 #endif
155 }
156 }
157
158
159 void LIR_Assembler::emit_slow_case_stubs() {
160 emit_stubs(_slow_case_stubs);
161 }
162
163
164 bool LIR_Assembler::needs_icache(ciMethod* method) const {
165 return !method->is_static();
166 }
167
168 bool LIR_Assembler::needs_clinit_barrier_on_entry(ciMethod* method) const {
169 return VM_Version::supports_fast_class_init_checks() && method->needs_clinit_barrier();
170 }
171
172 int LIR_Assembler::code_offset() const {
173 return _masm->offset();
174 }
175
176
177 address LIR_Assembler::pc() const {
178 return _masm->pc();
179 }
180
181 // To bang the stack of this compiled method we use the stack size
182 // that the interpreter would need in case of a deoptimization. This
183 // removes the need to bang the stack in the deoptimization blob which
184 // in turn simplifies stack overflow handling.
185 int LIR_Assembler::bang_size_in_bytes() const {
186 return MAX2(initial_frame_size_in_bytes() + os::extra_bang_size_in_bytes(), _compilation->interpreter_frame_size());
187 }
188
189 void LIR_Assembler::emit_exception_entries(ExceptionInfoList* info_list) {
190 for (int i = 0; i < info_list->length(); i++) {
191 XHandlers* handlers = info_list->at(i)->exception_handlers();
192
193 for (int j = 0; j < handlers->length(); j++) {
194 XHandler* handler = handlers->handler_at(j);
195 assert(handler->lir_op_id() != -1, "handler not processed by LinearScan");
196 assert(handler->entry_code() == nullptr ||
197 handler->entry_code()->instructions_list()->last()->code() == lir_branch, "last operation must be branch");
198
199 if (handler->entry_pco() == -1) {
200 // entry code not emitted yet
201 if (handler->entry_code() != nullptr && handler->entry_code()->instructions_list()->length() > 1) {
202 handler->set_entry_pco(code_offset());
203 if (CommentedAssembly) {
204 _masm->block_comment("Exception adapter block");
205 }
206 emit_lir_list(handler->entry_code());
207 } else {
208 handler->set_entry_pco(handler->entry_block()->exception_handler_pco());
209 }
210
211 assert(handler->entry_pco() != -1, "must be set now");
212 }
213 }
214 }
215 }
216
217
218 void LIR_Assembler::emit_code(BlockList* hir) {
219 if (PrintLIR) {
220 print_LIR(hir);
221 }
222
223 int n = hir->length();
224 for (int i = 0; i < n; i++) {
225 emit_block(hir->at(i));
226 CHECK_BAILOUT();
227 }
228
229 flush_debug_info(code_offset());
230
231 DEBUG_ONLY(check_no_unbound_labels());
232 }
233
234
235 void LIR_Assembler::emit_block(BlockBegin* block) {
236 if (block->is_set(BlockBegin::backward_branch_target_flag)) {
237 align_backward_branch_target();
238 }
239
240 // if this block is the start of an exception handler, record the
241 // PC offset of the first instruction for later construction of
242 // the ExceptionHandlerTable
243 if (block->is_set(BlockBegin::exception_entry_flag)) {
244 block->set_exception_handler_pco(code_offset());
245 }
246
247 #ifndef PRODUCT
248 if (PrintLIRWithAssembly) {
249 // don't print Phi's
250 InstructionPrinter ip(false);
251 block->print(ip);
252 }
253 #endif /* PRODUCT */
254
255 assert(block->lir() != nullptr, "must have LIR");
256 X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
257
258 #ifndef PRODUCT
259 if (CommentedAssembly) {
260 stringStream st;
261 st.print_cr(" block B%d [%d, %d]", block->block_id(), block->bci(), block->end()->printable_bci());
262 _masm->block_comment(st.freeze());
263 }
264 #endif
265
266 emit_lir_list(block->lir());
267
268 X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
269 }
270
271
272 void LIR_Assembler::emit_lir_list(LIR_List* list) {
273 peephole(list);
274
275 int n = list->length();
276 for (int i = 0; i < n; i++) {
277 LIR_Op* op = list->at(i);
278
279 check_codespace();
280 CHECK_BAILOUT();
281
282 #ifndef PRODUCT
283 if (CommentedAssembly) {
284 // Don't record out every op since that's too verbose. Print
285 // branches since they include block and stub names. Also print
286 // patching moves since they generate funny looking code.
287 if (op->code() == lir_branch ||
288 (op->code() == lir_move && op->as_Op1()->patch_code() != lir_patch_none) ||
289 (op->code() == lir_leal && op->as_Op1()->patch_code() != lir_patch_none)) {
290 stringStream st;
291 op->print_on(&st);
292 _masm->block_comment(st.freeze());
293 }
294 }
295 if (PrintLIRWithAssembly) {
296 // print out the LIR operation followed by the resulting assembly
297 list->at(i)->print(); tty->cr();
298 }
299 #endif /* PRODUCT */
300
301 op->emit_code(this);
302
303 if (compilation()->debug_info_recorder()->recording_non_safepoints()) {
304 process_debug_info(op);
305 }
306
307 #ifndef PRODUCT
308 if (PrintLIRWithAssembly) {
309 _masm->code()->decode();
310 }
311 #endif /* PRODUCT */
312 }
313 }
314
315 #ifdef ASSERT
316 void LIR_Assembler::check_no_unbound_labels() {
317 CHECK_BAILOUT();
318
319 for (int i = 0; i < _branch_target_blocks.length() - 1; i++) {
320 if (!_branch_target_blocks.at(i)->label()->is_bound()) {
321 tty->print_cr("label of block B%d is not bound", _branch_target_blocks.at(i)->block_id());
322 assert(false, "unbound label");
323 }
324 }
325 }
326 #endif
327
328 //----------------------------------debug info--------------------------------
329
330
331 void LIR_Assembler::add_debug_info_for_branch(CodeEmitInfo* info) {
332 int pc_offset = code_offset();
333 flush_debug_info(pc_offset);
334 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
335 if (info->exception_handlers() != nullptr) {
336 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
337 }
338 }
339
340
341 void LIR_Assembler::add_call_info(int pc_offset, CodeEmitInfo* cinfo) {
342 flush_debug_info(pc_offset);
343 cinfo->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
344 if (cinfo->exception_handlers() != nullptr) {
345 compilation()->add_exception_handlers_for_pco(pc_offset, cinfo->exception_handlers());
346 }
347 }
348
349 static ValueStack* debug_info(Instruction* ins) {
350 StateSplit* ss = ins->as_StateSplit();
351 if (ss != nullptr) return ss->state();
352 return ins->state_before();
353 }
354
355 void LIR_Assembler::process_debug_info(LIR_Op* op) {
356 Instruction* src = op->source();
357 if (src == nullptr) return;
358 int pc_offset = code_offset();
359 if (_pending_non_safepoint == src) {
360 _pending_non_safepoint_offset = pc_offset;
361 return;
362 }
363 ValueStack* vstack = debug_info(src);
364 if (vstack == nullptr) return;
365 if (_pending_non_safepoint != nullptr) {
366 // Got some old debug info. Get rid of it.
367 if (debug_info(_pending_non_safepoint) == vstack) {
368 _pending_non_safepoint_offset = pc_offset;
369 return;
370 }
371 if (_pending_non_safepoint_offset < pc_offset) {
372 record_non_safepoint_debug_info();
373 }
374 _pending_non_safepoint = nullptr;
375 }
376 // Remember the debug info.
377 if (pc_offset > compilation()->debug_info_recorder()->last_pc_offset()) {
378 _pending_non_safepoint = src;
379 _pending_non_safepoint_offset = pc_offset;
380 }
381 }
382
383 // Index caller states in s, where 0 is the oldest, 1 its callee, etc.
384 // Return null if n is too large.
385 // Returns the caller_bci for the next-younger state, also.
386 static ValueStack* nth_oldest(ValueStack* s, int n, int& bci_result) {
387 ValueStack* t = s;
388 for (int i = 0; i < n; i++) {
389 if (t == nullptr) break;
390 t = t->caller_state();
391 }
392 if (t == nullptr) return nullptr;
393 for (;;) {
394 ValueStack* tc = t->caller_state();
395 if (tc == nullptr) return s;
396 t = tc;
397 bci_result = tc->bci();
398 s = s->caller_state();
399 }
400 }
401
402 void LIR_Assembler::record_non_safepoint_debug_info() {
403 int pc_offset = _pending_non_safepoint_offset;
404 ValueStack* vstack = debug_info(_pending_non_safepoint);
405 int bci = vstack->bci();
406
407 DebugInformationRecorder* debug_info = compilation()->debug_info_recorder();
408 assert(debug_info->recording_non_safepoints(), "sanity");
409
410 debug_info->add_non_safepoint(pc_offset);
411
412 // Visit scopes from oldest to youngest.
413 for (int n = 0; ; n++) {
414 int s_bci = bci;
415 ValueStack* s = nth_oldest(vstack, n, s_bci);
416 if (s == nullptr) break;
417 IRScope* scope = s->scope();
418 //Always pass false for reexecute since these ScopeDescs are never used for deopt
419 methodHandle null_mh;
420 debug_info->describe_scope(pc_offset, null_mh, scope->method(), s->bci(), false/*reexecute*/);
421 }
422
423 debug_info->end_non_safepoint(pc_offset);
424 }
425
426
427 ImplicitNullCheckStub* LIR_Assembler::add_debug_info_for_null_check_here(CodeEmitInfo* cinfo) {
428 return add_debug_info_for_null_check(code_offset(), cinfo);
429 }
430
431 ImplicitNullCheckStub* LIR_Assembler::add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo) {
432 ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(pc_offset, cinfo);
433 append_code_stub(stub);
434 return stub;
435 }
436
437 void LIR_Assembler::add_debug_info_for_div0_here(CodeEmitInfo* info) {
438 add_debug_info_for_div0(code_offset(), info);
439 }
440
441 void LIR_Assembler::add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo) {
442 DivByZeroStub* stub = new DivByZeroStub(pc_offset, cinfo);
443 append_code_stub(stub);
444 }
445
446 void LIR_Assembler::emit_rtcall(LIR_OpRTCall* op) {
447 rt_call(op->result_opr(), op->addr(), op->arguments(), op->tmp(), op->info());
448 }
449
450 void LIR_Assembler::emit_call(LIR_OpJavaCall* op) {
451 verify_oop_map(op->info());
452
453 // must align calls sites, otherwise they can't be updated atomically
454 align_call(op->code());
455
456 if (CodeBuffer::supports_shared_stubs() && op->method()->can_be_statically_bound()) {
457 // Calls of the same statically bound method can share
458 // a stub to the interpreter.
459 CodeBuffer::csize_t call_offset = pc() - _masm->code()->insts_begin();
460 _masm->code()->shared_stub_to_interp_for(op->method(), call_offset);
461 } else {
462 emit_static_call_stub();
463 }
464 CHECK_BAILOUT();
465
466 switch (op->code()) {
467 case lir_static_call:
468 case lir_dynamic_call:
469 call(op, relocInfo::static_call_type);
470 break;
471 case lir_optvirtual_call:
472 call(op, relocInfo::opt_virtual_call_type);
473 break;
474 case lir_icvirtual_call:
475 ic_call(op);
476 break;
477 default:
478 fatal("unexpected op code: %s", op->name());
479 break;
480 }
481 }
482
483
484 void LIR_Assembler::emit_opLabel(LIR_OpLabel* op) {
485 _masm->bind (*(op->label()));
486 }
487
488
489 void LIR_Assembler::emit_op1(LIR_Op1* op) {
490 switch (op->code()) {
491 case lir_move:
492 if (op->move_kind() == lir_move_volatile) {
493 assert(op->patch_code() == lir_patch_none, "can't patch volatiles");
494 volatile_move_op(op->in_opr(), op->result_opr(), op->type(), op->info());
495 } else {
496 move_op(op->in_opr(), op->result_opr(), op->type(),
497 op->patch_code(), op->info(),
498 op->move_kind() == lir_move_wide);
499 }
500 break;
501
502 case lir_abs:
503 case lir_sqrt:
504 case lir_f2hf:
505 case lir_hf2f:
506 intrinsic_op(op->code(), op->in_opr(), op->tmp_opr(), op->result_opr(), op);
507 break;
508
509 case lir_neg:
510 negate(op->in_opr(), op->result_opr(), op->tmp_opr());
511 break;
512
513 case lir_return: {
514 assert(op->as_OpReturn() != nullptr, "sanity");
515 LIR_OpReturn *ret_op = (LIR_OpReturn*)op;
516 return_op(ret_op->in_opr(), ret_op->stub());
517 if (ret_op->stub() != nullptr) {
518 append_code_stub(ret_op->stub());
519 }
520 break;
521 }
522
523 case lir_safepoint:
524 if (compilation()->debug_info_recorder()->last_pc_offset() == code_offset()) {
525 _masm->nop();
526 }
527 safepoint_poll(op->in_opr(), op->info());
528 break;
529
530 #ifdef IA32
531 case lir_fxch:
532 fxch(op->in_opr()->as_jint());
533 break;
534
535 case lir_fld:
536 fld(op->in_opr()->as_jint());
537 break;
538 #endif // IA32
539
540 case lir_branch:
541 break;
542
543 case lir_push:
544 push(op->in_opr());
545 break;
546
547 case lir_pop:
548 pop(op->in_opr());
549 break;
550
551 case lir_leal:
552 leal(op->in_opr(), op->result_opr(), op->patch_code(), op->info());
553 break;
554
555 case lir_null_check: {
556 ImplicitNullCheckStub* stub = add_debug_info_for_null_check_here(op->info());
557
558 if (op->in_opr()->is_single_cpu()) {
559 _masm->null_check(op->in_opr()->as_register(), stub->entry());
560 } else {
561 Unimplemented();
562 }
563 break;
564 }
565
566 case lir_monaddr:
567 monitor_address(op->in_opr()->as_constant_ptr()->as_jint(), op->result_opr());
568 break;
569
570 case lir_unwind:
571 unwind_op(op->in_opr());
572 break;
573
574 default:
575 Unimplemented();
576 break;
577 }
578 }
579
580
581 void LIR_Assembler::emit_op0(LIR_Op0* op) {
582 switch (op->code()) {
583 case lir_nop:
584 assert(op->info() == nullptr, "not supported");
585 _masm->nop();
586 break;
587
588 case lir_label:
589 Unimplemented();
590 break;
591
592 case lir_std_entry: {
593 // init offsets
594 offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
595 if (needs_icache(compilation()->method())) {
596 int offset = check_icache();
597 offsets()->set_value(CodeOffsets::Entry, offset);
598 }
599 _masm->align(CodeEntryAlignment);
600 offsets()->set_value(CodeOffsets::Verified_Entry, _masm->offset());
601 _masm->verified_entry(compilation()->directive()->BreakAtExecuteOption);
602 if (needs_clinit_barrier_on_entry(compilation()->method())) {
603 clinit_barrier(compilation()->method());
604 }
605 build_frame();
606 offsets()->set_value(CodeOffsets::Frame_Complete, _masm->offset());
607 break;
608 }
609
610 case lir_osr_entry:
611 offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
612 osr_entry();
613 break;
614
615 #ifdef IA32
616 case lir_fpop_raw:
617 fpop();
618 break;
619 #endif // IA32
620
621 case lir_breakpoint:
622 breakpoint();
623 break;
624
625 case lir_membar:
626 membar();
627 break;
628
629 case lir_membar_acquire:
630 membar_acquire();
631 break;
632
633 case lir_membar_release:
634 membar_release();
635 break;
636
637 case lir_membar_loadload:
638 membar_loadload();
639 break;
640
641 case lir_membar_storestore:
642 membar_storestore();
643 break;
644
645 case lir_membar_loadstore:
646 membar_loadstore();
647 break;
648
649 case lir_membar_storeload:
650 membar_storeload();
651 break;
652
653 case lir_get_thread:
654 get_thread(op->result_opr());
655 break;
656
657 case lir_on_spin_wait:
658 on_spin_wait();
659 break;
660
661 default:
662 ShouldNotReachHere();
663 break;
664 }
665 }
666
667
668 void LIR_Assembler::emit_op2(LIR_Op2* op) {
669 switch (op->code()) {
670 case lir_cmp:
671 if (op->info() != nullptr) {
672 assert(op->in_opr1()->is_address() || op->in_opr2()->is_address(),
673 "shouldn't be codeemitinfo for non-address operands");
674 add_debug_info_for_null_check_here(op->info()); // exception possible
675 }
676 comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
677 break;
678
679 case lir_cmp_l2i:
680 case lir_cmp_fd2i:
681 case lir_ucmp_fd2i:
682 comp_fl2i(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
683 break;
684
685 case lir_shl:
686 case lir_shr:
687 case lir_ushr:
688 if (op->in_opr2()->is_constant()) {
689 shift_op(op->code(), op->in_opr1(), op->in_opr2()->as_constant_ptr()->as_jint(), op->result_opr());
690 } else {
691 shift_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
692 }
693 break;
694
695 case lir_add:
696 case lir_sub:
697 case lir_mul:
698 case lir_div:
699 case lir_rem:
700 arith_op(
701 op->code(),
702 op->in_opr1(),
703 op->in_opr2(),
704 op->result_opr(),
705 op->info());
706 break;
707
708 case lir_logic_and:
709 case lir_logic_or:
710 case lir_logic_xor:
711 logic_op(
712 op->code(),
713 op->in_opr1(),
714 op->in_opr2(),
715 op->result_opr());
716 break;
717
718 case lir_throw:
719 throw_op(op->in_opr1(), op->in_opr2(), op->info());
720 break;
721
722 case lir_xadd:
723 case lir_xchg:
724 atomic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
725 break;
726
727 default:
728 Unimplemented();
729 break;
730 }
731 }
732
733 void LIR_Assembler::emit_op4(LIR_Op4* op) {
734 switch(op->code()) {
735 case lir_cmove:
736 cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->type(), op->in_opr3(), op->in_opr4());
737 break;
738
739 default:
740 Unimplemented();
741 break;
742 }
743 }
744
745 void LIR_Assembler::build_frame() {
746 _masm->build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
747 }
748
749
750 void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
751 if (src->is_register()) {
752 if (dest->is_register()) {
753 assert(patch_code == lir_patch_none && info == nullptr, "no patching and info allowed here");
754 reg2reg(src, dest);
755 } else if (dest->is_stack()) {
756 assert(patch_code == lir_patch_none && info == nullptr, "no patching and info allowed here");
757 reg2stack(src, dest, type);
758 } else if (dest->is_address()) {
759 reg2mem(src, dest, type, patch_code, info, wide);
760 } else {
761 ShouldNotReachHere();
762 }
763
764 } else if (src->is_stack()) {
765 assert(patch_code == lir_patch_none && info == nullptr, "no patching and info allowed here");
766 if (dest->is_register()) {
767 stack2reg(src, dest, type);
768 } else if (dest->is_stack()) {
769 stack2stack(src, dest, type);
770 } else {
771 ShouldNotReachHere();
772 }
773
774 } else if (src->is_constant()) {
775 if (dest->is_register()) {
776 const2reg(src, dest, patch_code, info); // patching is possible
777 } else if (dest->is_stack()) {
778 assert(patch_code == lir_patch_none && info == nullptr, "no patching and info allowed here");
779 const2stack(src, dest);
780 } else if (dest->is_address()) {
781 assert(patch_code == lir_patch_none, "no patching allowed here");
782 const2mem(src, dest, type, info, wide);
783 } else {
784 ShouldNotReachHere();
785 }
786
787 } else if (src->is_address()) {
788 mem2reg(src, dest, type, patch_code, info, wide);
789 } else {
790 ShouldNotReachHere();
791 }
792 }
793
794
795 void LIR_Assembler::verify_oop_map(CodeEmitInfo* info) {
796 #ifndef PRODUCT
797 if (VerifyOops) {
798 OopMapStream s(info->oop_map());
799 while (!s.is_done()) {
800 OopMapValue v = s.current();
801 if (v.is_oop()) {
802 VMReg r = v.reg();
803 if (!r->is_stack()) {
804 _masm->verify_oop(r->as_Register());
805 } else {
806 _masm->verify_stack_oop(r->reg2stack() * VMRegImpl::stack_slot_size);
807 }
808 }
809 check_codespace();
810 CHECK_BAILOUT();
811
812 s.next();
813 }
814 }
815 #endif
816 }