1 /*
  2  * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
  3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  4  *
  5  * This code is free software; you can redistribute it and/or modify it
  6  * under the terms of the GNU General Public License version 2 only, as
  7  * published by the Free Software Foundation.
  8  *
  9  * This code is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 12  * version 2 for more details (a copy is included in the LICENSE file that
 13  * accompanied this code).
 14  *
 15  * You should have received a copy of the GNU General Public License version
 16  * 2 along with this work; if not, write to the Free Software Foundation,
 17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 18  *
 19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 20  * or visit www.oracle.com if you need additional information or have any
 21  * questions.
 22  *
 23  */
 24 
 25 #include "precompiled.hpp"
 26 #include "asm/assembler.inline.hpp"
 27 #include "c1/c1_Compilation.hpp"
 28 #include "c1/c1_Instruction.hpp"
 29 #include "c1/c1_InstructionPrinter.hpp"
 30 #include "c1/c1_LIRAssembler.hpp"
 31 #include "c1/c1_MacroAssembler.hpp"
 32 #include "c1/c1_ValueStack.hpp"
 33 #include "ci/ciInlineKlass.hpp"
 34 #include "ci/ciInstance.hpp"
 35 #include "compiler/oopMap.hpp"
 36 #include "gc/shared/barrierSet.hpp"
 37 #include "runtime/os.hpp"
 38 #include "runtime/sharedRuntime.hpp"
 39 #include "runtime/vm_version.hpp"
 40 
 41 void LIR_Assembler::patching_epilog(PatchingStub* patch, LIR_PatchCode patch_code, Register obj, CodeEmitInfo* info) {
 42   // We must have enough patching space so that call can be inserted.
 43   // We cannot use fat nops here, since the concurrent code rewrite may transiently
 44   // create the illegal instruction sequence.
 45   while ((intx) _masm->pc() - (intx) patch->pc_start() < NativeGeneralJump::instruction_size) {
 46     _masm->nop();
 47   }
 48   patch->install(_masm, patch_code, obj, info);
 49   append_code_stub(patch);
 50 
 51 #ifdef ASSERT
 52   Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
 53   if (patch->id() == PatchingStub::access_field_id) {
 54     switch (code) {
 55       case Bytecodes::_putstatic:
 56       case Bytecodes::_getstatic:
 57       case Bytecodes::_putfield:
 58       case Bytecodes::_getfield:
 59       case Bytecodes::_withfield:
 60         break;
 61       default:
 62         ShouldNotReachHere();
 63     }
 64   } else if (patch->id() == PatchingStub::load_klass_id) {
 65     switch (code) {
 66       case Bytecodes::_new:
 67       case Bytecodes::_defaultvalue:
 68       case Bytecodes::_anewarray:
 69       case Bytecodes::_multianewarray:
 70       case Bytecodes::_instanceof:
 71       case Bytecodes::_checkcast:
 72         break;
 73       default:
 74         ShouldNotReachHere();
 75     }
 76   } else if (patch->id() == PatchingStub::load_mirror_id) {
 77     switch (code) {
 78       case Bytecodes::_putstatic:
 79       case Bytecodes::_getstatic:
 80       case Bytecodes::_ldc:
 81       case Bytecodes::_ldc_w:
 82         break;
 83       default:
 84         ShouldNotReachHere();
 85     }
 86   } else if (patch->id() == PatchingStub::load_appendix_id) {
 87     Bytecodes::Code bc_raw = info->scope()->method()->raw_code_at_bci(info->stack()->bci());
 88     assert(Bytecodes::has_optional_appendix(bc_raw), "unexpected appendix resolution");
 89   } else {
 90     ShouldNotReachHere();
 91   }
 92 #endif
 93 }
 94 
 95 PatchingStub::PatchID LIR_Assembler::patching_id(CodeEmitInfo* info) {
 96   IRScope* scope = info->scope();
 97   Bytecodes::Code bc_raw = scope->method()->raw_code_at_bci(info->stack()->bci());
 98   if (Bytecodes::has_optional_appendix(bc_raw)) {
 99     return PatchingStub::load_appendix_id;
100   }
101   return PatchingStub::load_mirror_id;
102 }
103 
104 //---------------------------------------------------------------
105 
106 
107 LIR_Assembler::LIR_Assembler(Compilation* c):
108    _masm(c->masm())
109  , _bs(BarrierSet::barrier_set())
110  , _compilation(c)
111  , _frame_map(c->frame_map())
112  , _current_block(NULL)
113  , _pending_non_safepoint(NULL)
114  , _pending_non_safepoint_offset(0)
115 {
116   _slow_case_stubs = new CodeStubList();
117 }
118 
119 
120 LIR_Assembler::~LIR_Assembler() {
121   // The unwind handler label may be unnbound if this destructor is invoked because of a bail-out.
122   // Reset it here to avoid an assertion.
123   _unwind_handler_entry.reset();
124   _verified_inline_entry.reset();
125 }
126 
127 
128 void LIR_Assembler::check_codespace() {
129   CodeSection* cs = _masm->code_section();
130   if (cs->remaining() < (int)(NOT_LP64(1*K)LP64_ONLY(2*K))) {
131     BAILOUT("CodeBuffer overflow");
132   }
133 }
134 
135 
136 void LIR_Assembler::append_code_stub(CodeStub* stub) {
137   _slow_case_stubs->append(stub);
138 }
139 
140 void LIR_Assembler::emit_stubs(CodeStubList* stub_list) {
141   for (int m = 0; m < stub_list->length(); m++) {
142     CodeStub* s = stub_list->at(m);
143 
144     check_codespace();
145     CHECK_BAILOUT();
146 
147 #ifndef PRODUCT
148     if (CommentedAssembly) {
149       stringStream st;
150       s->print_name(&st);
151       st.print(" slow case");
152       _masm->block_comment(st.as_string());
153     }
154 #endif
155     s->emit_code(this);
156 #ifdef ASSERT
157     s->assert_no_unbound_labels();
158 #endif
159   }
160 }
161 
162 
163 void LIR_Assembler::emit_slow_case_stubs() {
164   emit_stubs(_slow_case_stubs);
165 }
166 
167 
168 bool LIR_Assembler::needs_icache(ciMethod* method) const {
169   return !method->is_static();
170 }
171 
172 bool LIR_Assembler::needs_clinit_barrier_on_entry(ciMethod* method) const {
173   return VM_Version::supports_fast_class_init_checks() && method->needs_clinit_barrier();
174 }
175 
176 int LIR_Assembler::code_offset() const {
177   return _masm->offset();
178 }
179 
180 
181 address LIR_Assembler::pc() const {
182   return _masm->pc();
183 }
184 
185 // To bang the stack of this compiled method we use the stack size
186 // that the interpreter would need in case of a deoptimization. This
187 // removes the need to bang the stack in the deoptimization blob which
188 // in turn simplifies stack overflow handling.
189 int LIR_Assembler::bang_size_in_bytes() const {
190   return MAX2(initial_frame_size_in_bytes() + os::extra_bang_size_in_bytes(), _compilation->interpreter_frame_size());
191 }
192 
193 void LIR_Assembler::emit_exception_entries(ExceptionInfoList* info_list) {
194   for (int i = 0; i < info_list->length(); i++) {
195     XHandlers* handlers = info_list->at(i)->exception_handlers();
196 
197     for (int j = 0; j < handlers->length(); j++) {
198       XHandler* handler = handlers->handler_at(j);
199       assert(handler->lir_op_id() != -1, "handler not processed by LinearScan");
200       assert(handler->entry_code() == NULL ||
201              handler->entry_code()->instructions_list()->last()->code() == lir_branch ||
202              handler->entry_code()->instructions_list()->last()->code() == lir_delay_slot, "last operation must be branch");
203 
204       if (handler->entry_pco() == -1) {
205         // entry code not emitted yet
206         if (handler->entry_code() != NULL && handler->entry_code()->instructions_list()->length() > 1) {
207           handler->set_entry_pco(code_offset());
208           if (CommentedAssembly) {
209             _masm->block_comment("Exception adapter block");
210           }
211           emit_lir_list(handler->entry_code());
212         } else {
213           handler->set_entry_pco(handler->entry_block()->exception_handler_pco());
214         }
215 
216         assert(handler->entry_pco() != -1, "must be set now");
217       }
218     }
219   }
220 }
221 
222 
223 void LIR_Assembler::emit_code(BlockList* hir) {
224   if (PrintLIR) {
225     print_LIR(hir);
226   }
227 
228   int n = hir->length();
229   for (int i = 0; i < n; i++) {
230     emit_block(hir->at(i));
231     CHECK_BAILOUT();
232   }
233 
234   flush_debug_info(code_offset());
235 
236   DEBUG_ONLY(check_no_unbound_labels());
237 }
238 
239 
240 void LIR_Assembler::emit_block(BlockBegin* block) {
241   if (block->is_set(BlockBegin::backward_branch_target_flag)) {
242     align_backward_branch_target();
243   }
244 
245   // if this block is the start of an exception handler, record the
246   // PC offset of the first instruction for later construction of
247   // the ExceptionHandlerTable
248   if (block->is_set(BlockBegin::exception_entry_flag)) {
249     block->set_exception_handler_pco(code_offset());
250   }
251 
252 #ifndef PRODUCT
253   if (PrintLIRWithAssembly) {
254     // don't print Phi's
255     InstructionPrinter ip(false);
256     block->print(ip);
257   }
258 #endif /* PRODUCT */
259 
260   assert(block->lir() != NULL, "must have LIR");
261   X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
262 
263 #ifndef PRODUCT
264   if (CommentedAssembly) {
265     stringStream st;
266     st.print_cr(" block B%d [%d, %d]", block->block_id(), block->bci(), block->end()->printable_bci());
267     _masm->block_comment(st.as_string());
268   }
269 #endif
270 
271   emit_lir_list(block->lir());
272 
273   X86_ONLY(assert(_masm->rsp_offset() == 0, "frame size should be fixed"));
274 }
275 
276 
277 void LIR_Assembler::emit_lir_list(LIR_List* list) {
278   peephole(list);
279 
280   int n = list->length();
281   for (int i = 0; i < n; i++) {
282     LIR_Op* op = list->at(i);
283 
284     check_codespace();
285     CHECK_BAILOUT();
286 
287 #ifndef PRODUCT
288     if (CommentedAssembly) {
289       // Don't record out every op since that's too verbose.  Print
290       // branches since they include block and stub names.  Also print
291       // patching moves since they generate funny looking code.
292       if (op->code() == lir_branch ||
293           (op->code() == lir_move && op->as_Op1()->patch_code() != lir_patch_none) ||
294           (op->code() == lir_leal && op->as_Op1()->patch_code() != lir_patch_none)) {
295         stringStream st;
296         op->print_on(&st);
297         _masm->block_comment(st.as_string());
298       }
299     }
300     if (PrintLIRWithAssembly) {
301       // print out the LIR operation followed by the resulting assembly
302       list->at(i)->print(); tty->cr();
303     }
304 #endif /* PRODUCT */
305 
306     op->emit_code(this);
307 
308     if (compilation()->debug_info_recorder()->recording_non_safepoints()) {
309       process_debug_info(op);
310     }
311 
312 #ifndef PRODUCT
313     if (PrintLIRWithAssembly) {
314       _masm->code()->decode();
315     }
316 #endif /* PRODUCT */
317   }
318 }
319 
320 #ifdef ASSERT
321 void LIR_Assembler::check_no_unbound_labels() {
322   CHECK_BAILOUT();
323 
324   for (int i = 0; i < _branch_target_blocks.length() - 1; i++) {
325     if (!_branch_target_blocks.at(i)->label()->is_bound()) {
326       tty->print_cr("label of block B%d is not bound", _branch_target_blocks.at(i)->block_id());
327       assert(false, "unbound label");
328     }
329   }
330 }
331 #endif
332 
333 //----------------------------------debug info--------------------------------
334 
335 void LIR_Assembler::add_debug_info_for_branch(CodeEmitInfo* info) {
336   int pc_offset = code_offset();
337   flush_debug_info(pc_offset);
338   info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
339   if (info->exception_handlers() != NULL) {
340     compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
341   }
342 }
343 
344 void LIR_Assembler::add_call_info(int pc_offset, CodeEmitInfo* cinfo, bool maybe_return_as_fields) {
345   flush_debug_info(pc_offset);
346   cinfo->record_debug_info(compilation()->debug_info_recorder(), pc_offset, maybe_return_as_fields);
347   if (cinfo->exception_handlers() != NULL) {
348     compilation()->add_exception_handlers_for_pco(pc_offset, cinfo->exception_handlers());
349   }
350 }
351 
352 static ValueStack* debug_info(Instruction* ins) {
353   StateSplit* ss = ins->as_StateSplit();
354   if (ss != NULL) return ss->state();
355   return ins->state_before();
356 }
357 
358 void LIR_Assembler::process_debug_info(LIR_Op* op) {
359   Instruction* src = op->source();
360   if (src == NULL)  return;
361   int pc_offset = code_offset();
362   if (_pending_non_safepoint == src) {
363     _pending_non_safepoint_offset = pc_offset;
364     return;
365   }
366   ValueStack* vstack = debug_info(src);
367   if (vstack == NULL)  return;
368   if (_pending_non_safepoint != NULL) {
369     // Got some old debug info.  Get rid of it.
370     if (debug_info(_pending_non_safepoint) == vstack) {
371       _pending_non_safepoint_offset = pc_offset;
372       return;
373     }
374     if (_pending_non_safepoint_offset < pc_offset) {
375       record_non_safepoint_debug_info();
376     }
377     _pending_non_safepoint = NULL;
378   }
379   // Remember the debug info.
380   if (pc_offset > compilation()->debug_info_recorder()->last_pc_offset()) {
381     _pending_non_safepoint = src;
382     _pending_non_safepoint_offset = pc_offset;
383   }
384 }
385 
386 // Index caller states in s, where 0 is the oldest, 1 its callee, etc.
387 // Return NULL if n is too large.
388 // Returns the caller_bci for the next-younger state, also.
389 static ValueStack* nth_oldest(ValueStack* s, int n, int& bci_result) {
390   ValueStack* t = s;
391   for (int i = 0; i < n; i++) {
392     if (t == NULL)  break;
393     t = t->caller_state();
394   }
395   if (t == NULL)  return NULL;
396   for (;;) {
397     ValueStack* tc = t->caller_state();
398     if (tc == NULL)  return s;
399     t = tc;
400     bci_result = tc->bci();
401     s = s->caller_state();
402   }
403 }
404 
405 void LIR_Assembler::record_non_safepoint_debug_info() {
406   int         pc_offset = _pending_non_safepoint_offset;
407   ValueStack* vstack    = debug_info(_pending_non_safepoint);
408   int         bci       = vstack->bci();
409 
410   DebugInformationRecorder* debug_info = compilation()->debug_info_recorder();
411   assert(debug_info->recording_non_safepoints(), "sanity");
412 
413   debug_info->add_non_safepoint(pc_offset);
414 
415   // Visit scopes from oldest to youngest.
416   for (int n = 0; ; n++) {
417     int s_bci = bci;
418     ValueStack* s = nth_oldest(vstack, n, s_bci);
419     if (s == NULL)  break;
420     IRScope* scope = s->scope();
421     //Always pass false for reexecute since these ScopeDescs are never used for deopt
422     methodHandle null_mh;
423     debug_info->describe_scope(pc_offset, null_mh, scope->method(), s->bci(), false/*reexecute*/);
424   }
425 
426   debug_info->end_non_safepoint(pc_offset);
427 }
428 
429 
430 ImplicitNullCheckStub* LIR_Assembler::add_debug_info_for_null_check_here(CodeEmitInfo* cinfo) {
431   return add_debug_info_for_null_check(code_offset(), cinfo);
432 }
433 
434 ImplicitNullCheckStub* LIR_Assembler::add_debug_info_for_null_check(int pc_offset, CodeEmitInfo* cinfo) {
435   ImplicitNullCheckStub* stub = new ImplicitNullCheckStub(pc_offset, cinfo);
436   append_code_stub(stub);
437   return stub;
438 }
439 
440 void LIR_Assembler::add_debug_info_for_div0_here(CodeEmitInfo* info) {
441   add_debug_info_for_div0(code_offset(), info);
442 }
443 
444 void LIR_Assembler::add_debug_info_for_div0(int pc_offset, CodeEmitInfo* cinfo) {
445   DivByZeroStub* stub = new DivByZeroStub(pc_offset, cinfo);
446   append_code_stub(stub);
447 }
448 
449 void LIR_Assembler::emit_rtcall(LIR_OpRTCall* op) {
450   rt_call(op->result_opr(), op->addr(), op->arguments(), op->tmp(), op->info());
451 }
452 
453 
454 void LIR_Assembler::emit_call(LIR_OpJavaCall* op) {
455   verify_oop_map(op->info());
456 
457   // must align calls sites, otherwise they can't be updated atomically
458   align_call(op->code());
459 
460   // emit the static call stub stuff out of line
461   emit_static_call_stub();
462   CHECK_BAILOUT();
463 
464   switch (op->code()) {
465   case lir_static_call:
466   case lir_dynamic_call:
467     call(op, relocInfo::static_call_type);
468     break;
469   case lir_optvirtual_call:
470     call(op, relocInfo::opt_virtual_call_type);
471     break;
472   case lir_icvirtual_call:
473     ic_call(op);
474     break;
475   default:
476     fatal("unexpected op code: %s", op->name());
477     break;
478   }
479 
480   // JSR 292
481   // Record if this method has MethodHandle invokes.
482   if (op->is_method_handle_invoke()) {
483     compilation()->set_has_method_handle_invokes(true);
484   }
485 
486   ciInlineKlass* vk = NULL;
487   if (op->maybe_return_as_fields(&vk)) {
488     int offset = store_inline_type_fields_to_buf(vk);
489     add_call_info(offset, op->info(), true);
490   }
491 
492 #if defined(IA32) && defined(COMPILER2)
493   // C2 leave fpu stack dirty clean it
494   if (UseSSE < 2 && !CompilerConfig::is_c1_only_no_jvmci()) {
495     int i;
496     for ( i = 1; i <= 7 ; i++ ) {
497       ffree(i);
498     }
499     if (!op->result_opr()->is_float_kind()) {
500       ffree(0);
501     }
502   }
503 #endif // IA32 && COMPILER2
504 }
505 
506 
507 void LIR_Assembler::emit_opLabel(LIR_OpLabel* op) {
508   _masm->bind (*(op->label()));
509 }
510 
511 
512 void LIR_Assembler::emit_op1(LIR_Op1* op) {
513   switch (op->code()) {
514     case lir_move:
515       if (op->move_kind() == lir_move_volatile) {
516         assert(op->patch_code() == lir_patch_none, "can't patch volatiles");
517         volatile_move_op(op->in_opr(), op->result_opr(), op->type(), op->info());
518       } else {
519         move_op(op->in_opr(), op->result_opr(), op->type(),
520                 op->patch_code(), op->info(), op->pop_fpu_stack(),
521                 op->move_kind() == lir_move_wide);
522       }
523       break;
524 
525     case lir_roundfp: {
526       LIR_OpRoundFP* round_op = op->as_OpRoundFP();
527       roundfp_op(round_op->in_opr(), round_op->tmp(), round_op->result_opr(), round_op->pop_fpu_stack());
528       break;
529     }
530 
531     case lir_return: {
532       assert(op->as_OpReturn() != NULL, "sanity");
533       LIR_OpReturn *ret_op = (LIR_OpReturn*)op;
534       return_op(ret_op->in_opr(), ret_op->stub());
535       if (ret_op->stub() != NULL) {
536         append_code_stub(ret_op->stub());
537       }
538       break;
539     }
540 
541     case lir_safepoint:
542       if (compilation()->debug_info_recorder()->last_pc_offset() == code_offset()) {
543         _masm->nop();
544       }
545       safepoint_poll(op->in_opr(), op->info());
546       break;
547 
548 #ifdef IA32
549     case lir_fxch:
550       fxch(op->in_opr()->as_jint());
551       break;
552 
553     case lir_fld:
554       fld(op->in_opr()->as_jint());
555       break;
556 #endif // IA32
557 
558     case lir_branch:
559       break;
560 
561     case lir_push:
562       push(op->in_opr());
563       break;
564 
565     case lir_pop:
566       pop(op->in_opr());
567       break;
568 
569     case lir_leal:
570       leal(op->in_opr(), op->result_opr(), op->patch_code(), op->info());
571       break;
572 
573     case lir_null_check: {
574       ImplicitNullCheckStub* stub = add_debug_info_for_null_check_here(op->info());
575 
576       if (op->in_opr()->is_single_cpu()) {
577         _masm->null_check(op->in_opr()->as_register(), stub->entry());
578       } else {
579         Unimplemented();
580       }
581       break;
582     }
583 
584     case lir_monaddr:
585       monitor_address(op->in_opr()->as_constant_ptr()->as_jint(), op->result_opr());
586       break;
587 
588     case lir_unwind:
589       unwind_op(op->in_opr());
590       break;
591 
592     default:
593       Unimplemented();
594       break;
595   }
596 }
597 
598 void LIR_Assembler::add_scalarized_entry_info(int pc_offset) {
599   flush_debug_info(pc_offset);
600   DebugInformationRecorder* debug_info = compilation()->debug_info_recorder();
601   // The VEP and VIEP(RO) of a C1-compiled method call buffer_inline_args_xxx()
602   // before doing any argument shuffling. This call may cause GC. When GC happens,
603   // all the parameters are still as passed by the caller, so we just use
604   // map->set_include_argument_oops() inside frame::sender_for_compiled_frame(RegisterMap* map).
605   // There's no need to build a GC map here.
606   OopMap* oop_map = new OopMap(0, 0);
607   debug_info->add_safepoint(pc_offset, oop_map);
608   DebugToken* locvals = debug_info->create_scope_values(NULL); // FIXME is this needed (for Java debugging to work properly??)
609   DebugToken* expvals = debug_info->create_scope_values(NULL); // FIXME is this needed (for Java debugging to work properly??)
610   DebugToken* monvals = debug_info->create_monitor_values(NULL); // FIXME: need testing with synchronized method
611   bool reexecute = false;
612   bool return_oop = false; // This flag will be ignored since it used only for C2 with escape analysis.
613   bool rethrow_exception = false;
614   bool is_method_handle_invoke = false;
615   debug_info->describe_scope(pc_offset, methodHandle(), method(), 0, reexecute, rethrow_exception, is_method_handle_invoke, return_oop, false, locvals, expvals, monvals);
616   debug_info->end_safepoint(pc_offset);
617 }
618 
619 // The entries points of C1-compiled methods can have the following types:
620 // (1) Methods with no inline type args
621 // (2) Methods with inline type receiver but no inline type args
622 //     VIEP_RO is the same as VIEP
623 // (3) Methods with non-inline type receiver and some inline type args
624 //     VIEP_RO is the same as VEP
625 // (4) Methods with inline type receiver and other inline type args
626 //     Separate VEP, VIEP and VIEP_RO
627 //
628 // (1)               (2)                 (3)                    (4)
629 // UEP/UIEP:         VEP:                UEP:                   UEP:
630 //   check_icache      pack receiver       check_icache           check_icache
631 // VEP/VIEP/VIEP_RO    jump to VIEP      VEP/VIEP_RO:           VIEP_RO:
632 //   body            UEP/UIEP:             pack inline args       pack inline args (except receiver)
633 //                     check_icache        jump to VIEP           jump to VIEP
634 //                   VIEP/VIEP_RO        UIEP:                  VEP:
635 //                     body                check_icache           pack all inline args
636 //                                       VIEP:                    jump to VIEP
637 //                                         body                 UIEP:
638 //                                                                check_icache
639 //                                                              VIEP:
640 //                                                                body
641 void LIR_Assembler::emit_std_entries() {
642   offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
643 
644   _masm->align(CodeEntryAlignment);
645   const CompiledEntrySignature* ces = compilation()->compiled_entry_signature();
646   if (ces->has_scalarized_args()) {
647     assert(InlineTypePassFieldsAsArgs && method()->get_Method()->has_scalarized_args(), "must be");
648     CodeOffsets::Entries ro_entry_type = ces->c1_inline_ro_entry_type();
649 
650     // UEP: check icache and fall-through
651     if (ro_entry_type != CodeOffsets::Verified_Inline_Entry) {
652       offsets()->set_value(CodeOffsets::Entry, _masm->offset());
653       if (needs_icache(method())) {
654         check_icache();
655       }
656     }
657 
658     // VIEP_RO: pack all value parameters, except the receiver
659     if (ro_entry_type == CodeOffsets::Verified_Inline_Entry_RO) {
660       emit_std_entry(CodeOffsets::Verified_Inline_Entry_RO, ces);
661     }
662 
663     // VEP: pack all value parameters
664     _masm->align(CodeEntryAlignment);
665     emit_std_entry(CodeOffsets::Verified_Entry, ces);
666 
667     // UIEP: check icache and fall-through
668     _masm->align(CodeEntryAlignment);
669     offsets()->set_value(CodeOffsets::Inline_Entry, _masm->offset());
670     if (ro_entry_type == CodeOffsets::Verified_Inline_Entry) {
671       // Special case if we have VIEP == VIEP(RO):
672       // this means UIEP (called by C1) == UEP (called by C2).
673       offsets()->set_value(CodeOffsets::Entry, _masm->offset());
674     }
675     if (needs_icache(method())) {
676       check_icache();
677     }
678 
679     // VIEP: all value parameters are passed as refs - no packing.
680     emit_std_entry(CodeOffsets::Verified_Inline_Entry, NULL);
681 
682     if (ro_entry_type != CodeOffsets::Verified_Inline_Entry_RO) {
683       // The VIEP(RO) is the same as VEP or VIEP
684       assert(ro_entry_type == CodeOffsets::Verified_Entry ||
685              ro_entry_type == CodeOffsets::Verified_Inline_Entry, "must be");
686       offsets()->set_value(CodeOffsets::Verified_Inline_Entry_RO,
687                            offsets()->value(ro_entry_type));
688     }
689   } else {
690     // All 3 entries are the same (no inline type packing)
691     offsets()->set_value(CodeOffsets::Entry, _masm->offset());
692     offsets()->set_value(CodeOffsets::Inline_Entry, _masm->offset());
693     if (needs_icache(method())) {
694       check_icache();
695     }
696     emit_std_entry(CodeOffsets::Verified_Inline_Entry, NULL);
697     offsets()->set_value(CodeOffsets::Verified_Entry, offsets()->value(CodeOffsets::Verified_Inline_Entry));
698     offsets()->set_value(CodeOffsets::Verified_Inline_Entry_RO, offsets()->value(CodeOffsets::Verified_Inline_Entry));
699   }
700 }
701 
702 void LIR_Assembler::emit_std_entry(CodeOffsets::Entries entry, const CompiledEntrySignature* ces) {
703   offsets()->set_value(entry, _masm->offset());
704   _masm->verified_entry();
705   switch (entry) {
706   case CodeOffsets::Verified_Entry: {
707     if (needs_clinit_barrier_on_entry(method())) {
708       clinit_barrier(method());
709     }
710     int rt_call_offset = _masm->verified_entry(ces, initial_frame_size_in_bytes(), bang_size_in_bytes(), in_bytes(frame_map()->sp_offset_for_orig_pc()), _verified_inline_entry);
711     add_scalarized_entry_info(rt_call_offset);
712     break;
713   }
714   case CodeOffsets::Verified_Inline_Entry_RO: {
715     assert(!needs_clinit_barrier_on_entry(method()), "can't be static");
716     int rt_call_offset = _masm->verified_inline_ro_entry(ces, initial_frame_size_in_bytes(), bang_size_in_bytes(), in_bytes(frame_map()->sp_offset_for_orig_pc()), _verified_inline_entry);
717     add_scalarized_entry_info(rt_call_offset);
718     break;
719   }
720   case CodeOffsets::Verified_Inline_Entry: {
721     if (needs_clinit_barrier_on_entry(method())) {
722       clinit_barrier(method());
723     }
724     build_frame();
725     offsets()->set_value(CodeOffsets::Frame_Complete, _masm->offset());
726     break;
727   }
728   default:
729     ShouldNotReachHere();
730     break;
731   }
732 }
733 
734 void LIR_Assembler::emit_op0(LIR_Op0* op) {
735   switch (op->code()) {
736     case lir_nop:
737       assert(op->info() == NULL, "not supported");
738       _masm->nop();
739       break;
740 
741     case lir_label:
742       Unimplemented();
743       break;
744 
745     case lir_std_entry:
746       emit_std_entries();
747       break;
748 
749     case lir_osr_entry:
750       offsets()->set_value(CodeOffsets::OSR_Entry, _masm->offset());
751       osr_entry();
752       break;
753 
754 #ifdef IA32
755     case lir_fpop_raw:
756       fpop();
757       break;
758 #endif // IA32
759 
760     case lir_breakpoint:
761       breakpoint();
762       break;
763 
764     case lir_membar:
765       membar();
766       break;
767 
768     case lir_membar_acquire:
769       membar_acquire();
770       break;
771 
772     case lir_membar_release:
773       membar_release();
774       break;
775 
776     case lir_membar_loadload:
777       membar_loadload();
778       break;
779 
780     case lir_membar_storestore:
781       membar_storestore();
782       break;
783 
784     case lir_membar_loadstore:
785       membar_loadstore();
786       break;
787 
788     case lir_membar_storeload:
789       membar_storeload();
790       break;
791 
792     case lir_get_thread:
793       get_thread(op->result_opr());
794       break;
795 
796     case lir_on_spin_wait:
797       on_spin_wait();
798       break;
799 
800     case lir_check_orig_pc:
801       check_orig_pc();
802       break;
803 
804     default:
805       ShouldNotReachHere();
806       break;
807   }
808 }
809 
810 
811 void LIR_Assembler::emit_op2(LIR_Op2* op) {
812   switch (op->code()) {
813     case lir_cmp:
814       if (op->info() != NULL) {
815         assert(op->in_opr1()->is_address() || op->in_opr2()->is_address(),
816                "shouldn't be codeemitinfo for non-address operands");
817         add_debug_info_for_null_check_here(op->info()); // exception possible
818       }
819       comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
820       break;
821 
822     case lir_cmp_l2i:
823     case lir_cmp_fd2i:
824     case lir_ucmp_fd2i:
825       comp_fl2i(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
826       break;
827 
828     case lir_cmove:
829       cmove(op->condition(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->type());
830       break;
831 
832     case lir_shl:
833     case lir_shr:
834     case lir_ushr:
835       if (op->in_opr2()->is_constant()) {
836         shift_op(op->code(), op->in_opr1(), op->in_opr2()->as_constant_ptr()->as_jint(), op->result_opr());
837       } else {
838         shift_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
839       }
840       break;
841 
842     case lir_add:
843     case lir_sub:
844     case lir_mul:
845     case lir_div:
846     case lir_rem:
847       assert(op->fpu_pop_count() < 2, "");
848       arith_op(
849         op->code(),
850         op->in_opr1(),
851         op->in_opr2(),
852         op->result_opr(),
853         op->info(),
854         op->fpu_pop_count() == 1);
855       break;
856 
857     case lir_abs:
858     case lir_sqrt:
859     case lir_tan:
860     case lir_log10:
861       intrinsic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op);
862       break;
863 
864     case lir_neg:
865       negate(op->in_opr1(), op->result_opr(), op->in_opr2());
866       break;
867 
868     case lir_logic_and:
869     case lir_logic_or:
870     case lir_logic_xor:
871       logic_op(
872         op->code(),
873         op->in_opr1(),
874         op->in_opr2(),
875         op->result_opr());
876       break;
877 
878     case lir_throw:
879       throw_op(op->in_opr1(), op->in_opr2(), op->info());
880       break;
881 
882     case lir_xadd:
883     case lir_xchg:
884       atomic_op(op->code(), op->in_opr1(), op->in_opr2(), op->result_opr(), op->tmp1_opr());
885       break;
886 
887     default:
888       Unimplemented();
889       break;
890   }
891 }
892 
893 
894 void LIR_Assembler::build_frame() {
895   _masm->build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes(), in_bytes(frame_map()->sp_offset_for_orig_pc()),
896                      needs_stack_repair(), method()->has_scalarized_args(), &_verified_inline_entry);
897 }
898 
899 
900 void LIR_Assembler::roundfp_op(LIR_Opr src, LIR_Opr tmp, LIR_Opr dest, bool pop_fpu_stack) {
901   assert(strict_fp_requires_explicit_rounding, "not required");
902   assert((src->is_single_fpu() && dest->is_single_stack()) ||
903          (src->is_double_fpu() && dest->is_double_stack()),
904          "round_fp: rounds register -> stack location");
905 
906   reg2stack (src, dest, src->type(), pop_fpu_stack);
907 }
908 
909 
910 void LIR_Assembler::move_op(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
911   if (src->is_register()) {
912     if (dest->is_register()) {
913       assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
914       reg2reg(src,  dest);
915     } else if (dest->is_stack()) {
916       assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
917       reg2stack(src, dest, type, pop_fpu_stack);
918     } else if (dest->is_address()) {
919       reg2mem(src, dest, type, patch_code, info, pop_fpu_stack, wide);
920     } else {
921       ShouldNotReachHere();
922     }
923 
924   } else if (src->is_stack()) {
925     assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
926     if (dest->is_register()) {
927       stack2reg(src, dest, type);
928     } else if (dest->is_stack()) {
929       stack2stack(src, dest, type);
930     } else {
931       ShouldNotReachHere();
932     }
933 
934   } else if (src->is_constant()) {
935     if (dest->is_register()) {
936       const2reg(src, dest, patch_code, info); // patching is possible
937     } else if (dest->is_stack()) {
938       assert(patch_code == lir_patch_none && info == NULL, "no patching and info allowed here");
939       const2stack(src, dest);
940     } else if (dest->is_address()) {
941       assert(patch_code == lir_patch_none, "no patching allowed here");
942       const2mem(src, dest, type, info, wide);
943     } else {
944       ShouldNotReachHere();
945     }
946 
947   } else if (src->is_address()) {
948     mem2reg(src, dest, type, patch_code, info, wide);
949   } else {
950     ShouldNotReachHere();
951   }
952 }
953 
954 
955 void LIR_Assembler::verify_oop_map(CodeEmitInfo* info) {
956 #ifndef PRODUCT
957   if (VerifyOops) {
958     OopMapStream s(info->oop_map());
959     while (!s.is_done()) {
960       OopMapValue v = s.current();
961       if (v.is_oop()) {
962         VMReg r = v.reg();
963         if (!r->is_stack()) {
964           stringStream st;
965           st.print("bad oop %s at %d", r->as_Register()->name(), _masm->offset());
966           _masm->verify_oop(r->as_Register());
967         } else {
968           _masm->verify_stack_oop(r->reg2stack() * VMRegImpl::stack_slot_size);
969         }
970       }
971       check_codespace();
972       CHECK_BAILOUT();
973 
974       s.next();
975     }
976   }
977 #endif
978 }