1 /*
   2  * Copyright (c) 2005, 2024, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_CFGPrinter.hpp"
  27 #include "c1/c1_CodeStubs.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_FrameMap.hpp"
  30 #include "c1/c1_IR.hpp"
  31 #include "c1/c1_LIRGenerator.hpp"
  32 #include "c1/c1_LinearScan.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "code/vmreg.inline.hpp"
  35 #include "runtime/timerTrace.hpp"
  36 #include "utilities/bitMap.inline.hpp"
  37 
  38 #ifndef PRODUCT
  39 
  40   static LinearScanStatistic _stat_before_alloc;
  41   static LinearScanStatistic _stat_after_asign;
  42   static LinearScanStatistic _stat_final;
  43 
  44   static LinearScanTimers _total_timer;
  45 
  46   // helper macro for short definition of timer
  47   #define TIME_LINEAR_SCAN(timer_name)  TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
  48 
  49 #else
  50   #define TIME_LINEAR_SCAN(timer_name)
  51 #endif
  52 
  53 #ifdef ASSERT
  54 
  55   // helper macro for short definition of trace-output inside code
  56   #define TRACE_LINEAR_SCAN(level, code)       \
  57     if (TraceLinearScanLevel >= level) {       \
  58       code;                                    \
  59     }
  60 #else
  61   #define TRACE_LINEAR_SCAN(level, code)
  62 #endif
  63 
  64 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
  65 #ifdef _LP64
  66 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2,  1, 2, 1, -1};
  67 #else
  68 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1};
  69 #endif
  70 
  71 
  72 // Implementation of LinearScan
  73 
  74 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
  75  : _compilation(ir->compilation())
  76  , _ir(ir)
  77  , _gen(gen)
  78  , _frame_map(frame_map)
  79  , _cached_blocks(*ir->linear_scan_order())
  80  , _num_virtual_regs(gen->max_virtual_register_number())
  81  , _has_fpu_registers(false)
  82  , _num_calls(-1)
  83  , _max_spills(0)
  84  , _unused_spill_slot(-1)
  85  , _intervals(0)   // initialized later with correct length
  86  , _new_intervals_from_allocation(nullptr)
  87  , _sorted_intervals(nullptr)
  88  , _needs_full_resort(false)
  89  , _lir_ops(0)     // initialized later with correct length
  90  , _block_of_op(0) // initialized later with correct length
  91  , _has_info(0)
  92  , _has_call(0)
  93  , _interval_in_loop(0)  // initialized later with correct length
  94  , _scope_value_cache(0) // initialized later with correct length
  95 #ifdef IA32
  96  , _fpu_stack_allocator(nullptr)
  97 #endif
  98 {
  99   assert(this->ir() != nullptr,          "check if valid");
 100   assert(this->compilation() != nullptr, "check if valid");
 101   assert(this->gen() != nullptr,         "check if valid");
 102   assert(this->frame_map() != nullptr,   "check if valid");
 103 }
 104 
 105 
 106 // ********** functions for converting LIR-Operands to register numbers
 107 //
 108 // Emulate a flat register file comprising physical integer registers,
 109 // physical floating-point registers and virtual registers, in that order.
 110 // Virtual registers already have appropriate numbers, since V0 is
 111 // the number of physical registers.
 112 // Returns -1 for hi word if opr is a single word operand.
 113 //
 114 // Note: the inverse operation (calculating an operand for register numbers)
 115 //       is done in calc_operand_for_interval()
 116 
 117 int LinearScan::reg_num(LIR_Opr opr) {
 118   assert(opr->is_register(), "should not call this otherwise");
 119 
 120   if (opr->is_virtual_register()) {
 121     assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
 122     return opr->vreg_number();
 123   } else if (opr->is_single_cpu()) {
 124     return opr->cpu_regnr();
 125   } else if (opr->is_double_cpu()) {
 126     return opr->cpu_regnrLo();
 127 #ifdef X86
 128   } else if (opr->is_single_xmm()) {
 129     return opr->fpu_regnr() + pd_first_xmm_reg;
 130   } else if (opr->is_double_xmm()) {
 131     return opr->fpu_regnrLo() + pd_first_xmm_reg;
 132 #endif
 133   } else if (opr->is_single_fpu()) {
 134     return opr->fpu_regnr() + pd_first_fpu_reg;
 135   } else if (opr->is_double_fpu()) {
 136     return opr->fpu_regnrLo() + pd_first_fpu_reg;
 137   } else {
 138     ShouldNotReachHere();
 139     return -1;
 140   }
 141 }
 142 
 143 int LinearScan::reg_numHi(LIR_Opr opr) {
 144   assert(opr->is_register(), "should not call this otherwise");
 145 
 146   if (opr->is_virtual_register()) {
 147     return -1;
 148   } else if (opr->is_single_cpu()) {
 149     return -1;
 150   } else if (opr->is_double_cpu()) {
 151     return opr->cpu_regnrHi();
 152 #ifdef X86
 153   } else if (opr->is_single_xmm()) {
 154     return -1;
 155   } else if (opr->is_double_xmm()) {
 156     return -1;
 157 #endif
 158   } else if (opr->is_single_fpu()) {
 159     return -1;
 160   } else if (opr->is_double_fpu()) {
 161     return opr->fpu_regnrHi() + pd_first_fpu_reg;
 162   } else {
 163     ShouldNotReachHere();
 164     return -1;
 165   }
 166 }
 167 
 168 
 169 // ********** functions for classification of intervals
 170 
 171 bool LinearScan::is_precolored_interval(const Interval* i) {
 172   return i->reg_num() < LinearScan::nof_regs;
 173 }
 174 
 175 bool LinearScan::is_virtual_interval(const Interval* i) {
 176   return i->reg_num() >= LIR_Opr::vreg_base;
 177 }
 178 
 179 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
 180   return i->reg_num() < LinearScan::nof_cpu_regs;
 181 }
 182 
 183 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
 184 #if defined(__SOFTFP__) || defined(E500V2)
 185   return i->reg_num() >= LIR_Opr::vreg_base;
 186 #else
 187   return i->reg_num() >= LIR_Opr::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
 188 #endif // __SOFTFP__ or E500V2
 189 }
 190 
 191 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
 192   return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
 193 }
 194 
 195 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
 196 #if defined(__SOFTFP__) || defined(E500V2)
 197   return false;
 198 #else
 199   return i->reg_num() >= LIR_Opr::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
 200 #endif // __SOFTFP__ or E500V2
 201 }
 202 
 203 bool LinearScan::is_in_fpu_register(const Interval* i) {
 204   // fixed intervals not needed for FPU stack allocation
 205   return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
 206 }
 207 
 208 bool LinearScan::is_oop_interval(const Interval* i) {
 209   // fixed intervals never contain oops
 210   return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
 211 }
 212 
 213 
 214 // ********** General helper functions
 215 
 216 // compute next unused stack index that can be used for spilling
 217 int LinearScan::allocate_spill_slot(bool double_word) {
 218   int spill_slot;
 219   if (double_word) {
 220     if ((_max_spills & 1) == 1) {
 221       // alignment of double-word values
 222       // the hole because of the alignment is filled with the next single-word value
 223       assert(_unused_spill_slot == -1, "wasting a spill slot");
 224       _unused_spill_slot = _max_spills;
 225       _max_spills++;
 226     }
 227     spill_slot = _max_spills;
 228     _max_spills += 2;
 229 
 230   } else if (_unused_spill_slot != -1) {
 231     // re-use hole that was the result of a previous double-word alignment
 232     spill_slot = _unused_spill_slot;
 233     _unused_spill_slot = -1;
 234 
 235   } else {
 236     spill_slot = _max_spills;
 237     _max_spills++;
 238   }
 239 
 240   int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
 241 
 242   // if too many slots used, bailout compilation.
 243   if (result > 2000) {
 244     bailout("too many stack slots used");
 245   }
 246 
 247   return result;
 248 }
 249 
 250 void LinearScan::assign_spill_slot(Interval* it) {
 251   // assign the canonical spill slot of the parent (if a part of the interval
 252   // is already spilled) or allocate a new spill slot
 253   if (it->canonical_spill_slot() >= 0) {
 254     it->assign_reg(it->canonical_spill_slot());
 255   } else {
 256     int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
 257     it->set_canonical_spill_slot(spill);
 258     it->assign_reg(spill);
 259   }
 260 }
 261 
 262 void LinearScan::propagate_spill_slots() {
 263   if (!frame_map()->finalize_frame(max_spills())) {
 264     bailout("frame too large");
 265   }
 266 }
 267 
 268 // create a new interval with a predefined reg_num
 269 // (only used for parent intervals that are created during the building phase)
 270 Interval* LinearScan::create_interval(int reg_num) {
 271   assert(_intervals.at(reg_num) == nullptr, "overwriting existing interval");
 272 
 273   Interval* interval = new Interval(reg_num);
 274   _intervals.at_put(reg_num, interval);
 275 
 276   // assign register number for precolored intervals
 277   if (reg_num < LIR_Opr::vreg_base) {
 278     interval->assign_reg(reg_num);
 279   }
 280   return interval;
 281 }
 282 
 283 // assign a new reg_num to the interval and append it to the list of intervals
 284 // (only used for child intervals that are created during register allocation)
 285 void LinearScan::append_interval(Interval* it) {
 286   it->set_reg_num(_intervals.length());
 287   _intervals.append(it);
 288   IntervalList* new_intervals = _new_intervals_from_allocation;
 289   if (new_intervals == nullptr) {
 290     new_intervals = _new_intervals_from_allocation = new IntervalList();
 291   }
 292   new_intervals->append(it);
 293 }
 294 
 295 // copy the vreg-flags if an interval is split
 296 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
 297   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
 298     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
 299   }
 300   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
 301     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
 302   }
 303 
 304   // Note: do not copy the must_start_in_memory flag because it is not necessary for child
 305   //       intervals (only the very beginning of the interval must be in memory)
 306 }
 307 
 308 
 309 // ********** spill move optimization
 310 // eliminate moves from register to stack if stack slot is known to be correct
 311 
 312 // called during building of intervals
 313 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
 314   assert(interval->is_split_parent(), "can only be called for split parents");
 315 
 316   switch (interval->spill_state()) {
 317     case noDefinitionFound:
 318       assert(interval->spill_definition_pos() == -1, "must no be set before");
 319       interval->set_spill_definition_pos(def_pos);
 320       interval->set_spill_state(oneDefinitionFound);
 321       break;
 322 
 323     case oneDefinitionFound:
 324       assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
 325       if (def_pos < interval->spill_definition_pos() - 2) {
 326         // second definition found, so no spill optimization possible for this interval
 327         interval->set_spill_state(noOptimization);
 328       } else {
 329         // two consecutive definitions (because of two-operand LIR form)
 330         assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
 331       }
 332       break;
 333 
 334     case noOptimization:
 335       // nothing to do
 336       break;
 337 
 338     default:
 339       assert(false, "other states not allowed at this time");
 340   }
 341 }
 342 
 343 // called during register allocation
 344 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
 345   switch (interval->spill_state()) {
 346     case oneDefinitionFound: {
 347       int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
 348       int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
 349 
 350       if (def_loop_depth < spill_loop_depth) {
 351         // the loop depth of the spilling position is higher then the loop depth
 352         // at the definition of the interval -> move write to memory out of loop
 353         // by storing at definitin of the interval
 354         interval->set_spill_state(storeAtDefinition);
 355       } else {
 356         // the interval is currently spilled only once, so for now there is no
 357         // reason to store the interval at the definition
 358         interval->set_spill_state(oneMoveInserted);
 359       }
 360       break;
 361     }
 362 
 363     case oneMoveInserted: {
 364       // the interval is spilled more then once, so it is better to store it to
 365       // memory at the definition
 366       interval->set_spill_state(storeAtDefinition);
 367       break;
 368     }
 369 
 370     case storeAtDefinition:
 371     case startInMemory:
 372     case noOptimization:
 373     case noDefinitionFound:
 374       // nothing to do
 375       break;
 376 
 377     default:
 378       assert(false, "other states not allowed at this time");
 379   }
 380 }
 381 
 382 
 383 bool LinearScan::must_store_at_definition(const Interval* i) {
 384   return i->is_split_parent() && i->spill_state() == storeAtDefinition;
 385 }
 386 
 387 // called once before assignment of register numbers
 388 void LinearScan::eliminate_spill_moves() {
 389   TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
 390   TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
 391 
 392   // collect all intervals that must be stored after their definion.
 393   // the list is sorted by Interval::spill_definition_pos
 394   Interval* interval;
 395   Interval* temp_list;
 396   create_unhandled_lists(&interval, &temp_list, must_store_at_definition, nullptr);
 397 
 398 #ifdef ASSERT
 399   Interval* prev = nullptr;
 400   Interval* temp = interval;
 401   while (temp != Interval::end()) {
 402     assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
 403     if (prev != nullptr) {
 404       assert(temp->from() >= prev->from(), "intervals not sorted");
 405       assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
 406     }
 407 
 408     assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
 409     assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
 410     assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
 411 
 412     TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
 413 
 414     temp = temp->next();
 415   }
 416 #endif
 417 
 418   LIR_InsertionBuffer insertion_buffer;
 419   int num_blocks = block_count();
 420   for (int i = 0; i < num_blocks; i++) {
 421     BlockBegin* block = block_at(i);
 422     LIR_OpList* instructions = block->lir()->instructions_list();
 423     int         num_inst = instructions->length();
 424     bool        has_new = false;
 425 
 426     // iterate all instructions of the block. skip the first because it is always a label
 427     for (int j = 1; j < num_inst; j++) {
 428       LIR_Op* op = instructions->at(j);
 429       int op_id = op->id();
 430 
 431       if (op_id == -1) {
 432         // remove move from register to stack if the stack slot is guaranteed to be correct.
 433         // only moves that have been inserted by LinearScan can be removed.
 434         assert(op->code() == lir_move, "only moves can have a op_id of -1");
 435         assert(op->as_Op1() != nullptr, "move must be LIR_Op1");
 436         assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
 437 
 438         LIR_Op1* op1 = (LIR_Op1*)op;
 439         Interval* interval = interval_at(op1->result_opr()->vreg_number());
 440 
 441         if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
 442           // move target is a stack slot that is always correct, so eliminate instruction
 443           TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
 444           instructions->at_put(j, nullptr); // null-instructions are deleted by assign_reg_num
 445         }
 446 
 447       } else {
 448         // insert move from register to stack just after the beginning of the interval
 449         assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
 450         assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
 451 
 452         while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
 453           if (!has_new) {
 454             // prepare insertion buffer (appended when all instructions of the block are processed)
 455             insertion_buffer.init(block->lir());
 456             has_new = true;
 457           }
 458 
 459           LIR_Opr from_opr = operand_for_interval(interval);
 460           LIR_Opr to_opr = canonical_spill_opr(interval);
 461           assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
 462           assert(to_opr->is_stack(), "to operand must be a stack slot");
 463 
 464           insertion_buffer.move(j, from_opr, to_opr);
 465           TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
 466 
 467           interval = interval->next();
 468         }
 469       }
 470     } // end of instruction iteration
 471 
 472     if (has_new) {
 473       block->lir()->append(&insertion_buffer);
 474     }
 475   } // end of block iteration
 476 
 477   assert(interval == Interval::end(), "missed an interval");
 478 }
 479 
 480 
 481 // ********** Phase 1: number all instructions in all blocks
 482 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
 483 
 484 void LinearScan::number_instructions() {
 485   {
 486     // dummy-timer to measure the cost of the timer itself
 487     // (this time is then subtracted from all other timers to get the real value)
 488     TIME_LINEAR_SCAN(timer_do_nothing);
 489   }
 490   TIME_LINEAR_SCAN(timer_number_instructions);
 491 
 492   // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
 493   int num_blocks = block_count();
 494   int num_instructions = 0;
 495   int i;
 496   for (i = 0; i < num_blocks; i++) {
 497     num_instructions += block_at(i)->lir()->instructions_list()->length();
 498   }
 499 
 500   // initialize with correct length
 501   _lir_ops = LIR_OpArray(num_instructions, num_instructions, nullptr);
 502   _block_of_op = BlockBeginArray(num_instructions, num_instructions, nullptr);
 503 
 504   int op_id = 0;
 505   int idx = 0;
 506 
 507   for (i = 0; i < num_blocks; i++) {
 508     BlockBegin* block = block_at(i);
 509     block->set_first_lir_instruction_id(op_id);
 510     LIR_OpList* instructions = block->lir()->instructions_list();
 511 
 512     int num_inst = instructions->length();
 513     for (int j = 0; j < num_inst; j++) {
 514       LIR_Op* op = instructions->at(j);
 515       op->set_id(op_id);
 516 
 517       _lir_ops.at_put(idx, op);
 518       _block_of_op.at_put(idx, block);
 519       assert(lir_op_with_id(op_id) == op, "must match");
 520 
 521       idx++;
 522       op_id += 2; // numbering of lir_ops by two
 523     }
 524     block->set_last_lir_instruction_id(op_id - 2);
 525   }
 526   assert(idx == num_instructions, "must match");
 527   assert(idx * 2 == op_id, "must match");
 528 
 529   _has_call.initialize(num_instructions);
 530   _has_info.initialize(num_instructions);
 531 }
 532 
 533 
 534 // ********** Phase 2: compute local live sets separately for each block
 535 // (sets live_gen and live_kill for each block)
 536 
 537 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
 538   LIR_Opr opr = value->operand();
 539   Constant* con = value->as_Constant();
 540 
 541   // check some asumptions about debug information
 542   assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
 543   assert(con == nullptr || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "assumption: Constant instructions have only constant operands");
 544   assert(con != nullptr || opr->is_virtual(), "assumption: non-Constant instructions have only virtual operands");
 545 
 546   if ((con == nullptr || con->is_pinned()) && opr->is_register()) {
 547     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 548     int reg = opr->vreg_number();
 549     if (!live_kill.at(reg)) {
 550       live_gen.set_bit(reg);
 551       TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
 552     }
 553   }
 554 }
 555 
 556 
 557 void LinearScan::compute_local_live_sets() {
 558   TIME_LINEAR_SCAN(timer_compute_local_live_sets);
 559 
 560   int  num_blocks = block_count();
 561   int  live_size = live_set_size();
 562   bool local_has_fpu_registers = false;
 563   int  local_num_calls = 0;
 564   LIR_OpVisitState visitor;
 565 
 566   BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
 567 
 568   // iterate all blocks
 569   for (int i = 0; i < num_blocks; i++) {
 570     BlockBegin* block = block_at(i);
 571 
 572     ResourceBitMap live_gen(live_size);
 573     ResourceBitMap live_kill(live_size);
 574 
 575     if (block->is_set(BlockBegin::exception_entry_flag)) {
 576       // Phi functions at the begin of an exception handler are
 577       // implicitly defined (= killed) at the beginning of the block.
 578       for_each_phi_fun(block, phi,
 579         if (!phi->is_illegal()) { live_kill.set_bit(phi->operand()->vreg_number()); }
 580       );
 581     }
 582 
 583     LIR_OpList* instructions = block->lir()->instructions_list();
 584     int num_inst = instructions->length();
 585 
 586     // iterate all instructions of the block. skip the first because it is always a label
 587     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
 588     for (int j = 1; j < num_inst; j++) {
 589       LIR_Op* op = instructions->at(j);
 590 
 591       // visit operation to collect all operands
 592       visitor.visit(op);
 593 
 594       if (visitor.has_call()) {
 595         _has_call.set_bit(op->id() >> 1);
 596         local_num_calls++;
 597       }
 598       if (visitor.info_count() > 0) {
 599         _has_info.set_bit(op->id() >> 1);
 600       }
 601 
 602       // iterate input operands of instruction
 603       int k, n, reg;
 604       n = visitor.opr_count(LIR_OpVisitState::inputMode);
 605       for (k = 0; k < n; k++) {
 606         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
 607         assert(opr->is_register(), "visitor should only return register operands");
 608 
 609         if (opr->is_virtual_register()) {
 610           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 611           reg = opr->vreg_number();
 612           if (!live_kill.at(reg)) {
 613             live_gen.set_bit(reg);
 614             TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for register %d at instruction %d", reg, op->id()));
 615           }
 616           if (block->loop_index() >= 0) {
 617             local_interval_in_loop.set_bit(reg, block->loop_index());
 618           }
 619           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 620         }
 621 
 622 #ifdef ASSERT
 623         // fixed intervals are never live at block boundaries, so
 624         // they need not be processed in live sets.
 625         // this is checked by these assertions to be sure about it.
 626         // the entry block may have incoming values in registers, which is ok.
 627         if (!opr->is_virtual_register() && block != ir()->start()) {
 628           reg = reg_num(opr);
 629           if (is_processed_reg_num(reg)) {
 630             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 631           }
 632           reg = reg_numHi(opr);
 633           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 634             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 635           }
 636         }
 637 #endif
 638       }
 639 
 640       // Add uses of live locals from interpreter's point of view for proper debug information generation
 641       n = visitor.info_count();
 642       for (k = 0; k < n; k++) {
 643         CodeEmitInfo* info = visitor.info_at(k);
 644         ValueStack* stack = info->stack();
 645         for_each_state_value(stack, value,
 646           set_live_gen_kill(value, op, live_gen, live_kill);
 647           local_has_fpu_registers = local_has_fpu_registers || value->type()->is_float_kind();
 648         );
 649       }
 650 
 651       // iterate temp operands of instruction
 652       n = visitor.opr_count(LIR_OpVisitState::tempMode);
 653       for (k = 0; k < n; k++) {
 654         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
 655         assert(opr->is_register(), "visitor should only return register operands");
 656 
 657         if (opr->is_virtual_register()) {
 658           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 659           reg = opr->vreg_number();
 660           live_kill.set_bit(reg);
 661           if (block->loop_index() >= 0) {
 662             local_interval_in_loop.set_bit(reg, block->loop_index());
 663           }
 664           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 665         }
 666 
 667 #ifdef ASSERT
 668         // fixed intervals are never live at block boundaries, so
 669         // they need not be processed in live sets
 670         // process them only in debug mode so that this can be checked
 671         if (!opr->is_virtual_register()) {
 672           reg = reg_num(opr);
 673           if (is_processed_reg_num(reg)) {
 674             live_kill.set_bit(reg_num(opr));
 675           }
 676           reg = reg_numHi(opr);
 677           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 678             live_kill.set_bit(reg);
 679           }
 680         }
 681 #endif
 682       }
 683 
 684       // iterate output operands of instruction
 685       n = visitor.opr_count(LIR_OpVisitState::outputMode);
 686       for (k = 0; k < n; k++) {
 687         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
 688         assert(opr->is_register(), "visitor should only return register operands");
 689 
 690         if (opr->is_virtual_register()) {
 691           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 692           reg = opr->vreg_number();
 693           live_kill.set_bit(reg);
 694           if (block->loop_index() >= 0) {
 695             local_interval_in_loop.set_bit(reg, block->loop_index());
 696           }
 697           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 698         }
 699 
 700 #ifdef ASSERT
 701         // fixed intervals are never live at block boundaries, so
 702         // they need not be processed in live sets
 703         // process them only in debug mode so that this can be checked
 704         if (!opr->is_virtual_register()) {
 705           reg = reg_num(opr);
 706           if (is_processed_reg_num(reg)) {
 707             live_kill.set_bit(reg_num(opr));
 708           }
 709           reg = reg_numHi(opr);
 710           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 711             live_kill.set_bit(reg);
 712           }
 713         }
 714 #endif
 715       }
 716     } // end of instruction iteration
 717 
 718     block->set_live_gen (live_gen);
 719     block->set_live_kill(live_kill);
 720     block->set_live_in  (ResourceBitMap(live_size));
 721     block->set_live_out (ResourceBitMap(live_size));
 722 
 723     TRACE_LINEAR_SCAN(4, tty->print("live_gen  B%d ", block->block_id()); print_bitmap(block->live_gen()));
 724     TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
 725   } // end of block iteration
 726 
 727   // propagate local calculated information into LinearScan object
 728   _has_fpu_registers = local_has_fpu_registers;
 729   compilation()->set_has_fpu_code(local_has_fpu_registers);
 730 
 731   _num_calls = local_num_calls;
 732   _interval_in_loop = local_interval_in_loop;
 733 }
 734 
 735 
 736 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
 737 // (sets live_in and live_out for each block)
 738 
 739 void LinearScan::compute_global_live_sets() {
 740   TIME_LINEAR_SCAN(timer_compute_global_live_sets);
 741 
 742   int  num_blocks = block_count();
 743   bool change_occurred;
 744   bool change_occurred_in_block;
 745   int  iteration_count = 0;
 746   ResourceBitMap live_out(live_set_size()); // scratch set for calculations
 747 
 748   // Perform a backward dataflow analysis to compute live_out and live_in for each block.
 749   // The loop is executed until a fixpoint is reached (no changes in an iteration)
 750   // Exception handlers must be processed because not all live values are
 751   // present in the state array, e.g. because of global value numbering
 752   do {
 753     change_occurred = false;
 754 
 755     // iterate all blocks in reverse order
 756     for (int i = num_blocks - 1; i >= 0; i--) {
 757       BlockBegin* block = block_at(i);
 758 
 759       change_occurred_in_block = false;
 760 
 761       // live_out(block) is the union of live_in(sux), for successors sux of block
 762       int n = block->number_of_sux();
 763       int e = block->number_of_exception_handlers();
 764       if (n + e > 0) {
 765         // block has successors
 766         if (n > 0) {
 767           live_out.set_from(block->sux_at(0)->live_in());
 768           for (int j = 1; j < n; j++) {
 769             live_out.set_union(block->sux_at(j)->live_in());
 770           }
 771         } else {
 772           live_out.clear();
 773         }
 774         for (int j = 0; j < e; j++) {
 775           live_out.set_union(block->exception_handler_at(j)->live_in());
 776         }
 777 
 778         if (!block->live_out().is_same(live_out)) {
 779           // A change occurred.  Swap the old and new live out sets to avoid copying.
 780           ResourceBitMap temp = block->live_out();
 781           block->set_live_out(live_out);
 782           live_out = temp;
 783 
 784           change_occurred = true;
 785           change_occurred_in_block = true;
 786         }
 787       }
 788 
 789       if (iteration_count == 0 || change_occurred_in_block) {
 790         // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
 791         // note: live_in has to be computed only in first iteration or if live_out has changed!
 792         ResourceBitMap live_in = block->live_in();
 793         live_in.set_from(block->live_out());
 794         live_in.set_difference(block->live_kill());
 795         live_in.set_union(block->live_gen());
 796       }
 797 
 798 #ifdef ASSERT
 799       if (TraceLinearScanLevel >= 4) {
 800         char c = ' ';
 801         if (iteration_count == 0 || change_occurred_in_block) {
 802           c = '*';
 803         }
 804         tty->print("(%d) live_in%c  B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
 805         tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
 806       }
 807 #endif
 808     }
 809     iteration_count++;
 810 
 811     if (change_occurred && iteration_count > 50) {
 812       BAILOUT("too many iterations in compute_global_live_sets");
 813     }
 814   } while (change_occurred);
 815 
 816 
 817 #ifdef ASSERT
 818   // check that fixed intervals are not live at block boundaries
 819   // (live set must be empty at fixed intervals)
 820   for (int i = 0; i < num_blocks; i++) {
 821     BlockBegin* block = block_at(i);
 822     for (int j = 0; j < LIR_Opr::vreg_base; j++) {
 823       assert(block->live_in().at(j)  == false, "live_in  set of fixed register must be empty");
 824       assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
 825       assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
 826     }
 827   }
 828 #endif
 829 
 830   // check that the live_in set of the first block is empty
 831   ResourceBitMap live_in_args(ir()->start()->live_in().size());
 832   if (!ir()->start()->live_in().is_same(live_in_args)) {
 833 #ifdef ASSERT
 834     tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
 835     tty->print_cr("affected registers:");
 836     print_bitmap(ir()->start()->live_in());
 837 
 838     // print some additional information to simplify debugging
 839     for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
 840       if (ir()->start()->live_in().at(i)) {
 841         Instruction* instr = gen()->instruction_for_vreg(i);
 842         tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == nullptr ? ' ' : instr->type()->tchar(), instr == nullptr ? 0 : instr->id());
 843 
 844         for (int j = 0; j < num_blocks; j++) {
 845           BlockBegin* block = block_at(j);
 846           if (block->live_gen().at(i)) {
 847             tty->print_cr("  used in block B%d", block->block_id());
 848           }
 849           if (block->live_kill().at(i)) {
 850             tty->print_cr("  defined in block B%d", block->block_id());
 851           }
 852         }
 853       }
 854     }
 855 
 856 #endif
 857     // when this fails, virtual registers are used before they are defined.
 858     assert(false, "live_in set of first block must be empty");
 859     // bailout of if this occurs in product mode.
 860     bailout("live_in set of first block not empty");
 861   }
 862 }
 863 
 864 
 865 // ********** Phase 4: build intervals
 866 // (fills the list _intervals)
 867 
 868 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
 869   assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
 870   LIR_Opr opr = value->operand();
 871   Constant* con = value->as_Constant();
 872 
 873   if ((con == nullptr || con->is_pinned()) && opr->is_register()) {
 874     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 875     add_use(opr, from, to, use_kind);
 876   }
 877 }
 878 
 879 
 880 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
 881   TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
 882   assert(opr->is_register(), "should not be called otherwise");
 883 
 884   if (opr->is_virtual_register()) {
 885     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 886     add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
 887 
 888   } else {
 889     int reg = reg_num(opr);
 890     if (is_processed_reg_num(reg)) {
 891       add_def(reg, def_pos, use_kind, opr->type_register());
 892     }
 893     reg = reg_numHi(opr);
 894     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 895       add_def(reg, def_pos, use_kind, opr->type_register());
 896     }
 897   }
 898 }
 899 
 900 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
 901   TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
 902   assert(opr->is_register(), "should not be called otherwise");
 903 
 904   if (opr->is_virtual_register()) {
 905     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 906     add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
 907 
 908   } else {
 909     int reg = reg_num(opr);
 910     if (is_processed_reg_num(reg)) {
 911       add_use(reg, from, to, use_kind, opr->type_register());
 912     }
 913     reg = reg_numHi(opr);
 914     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 915       add_use(reg, from, to, use_kind, opr->type_register());
 916     }
 917   }
 918 }
 919 
 920 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
 921   TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
 922   assert(opr->is_register(), "should not be called otherwise");
 923 
 924   if (opr->is_virtual_register()) {
 925     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 926     add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
 927 
 928   } else {
 929     int reg = reg_num(opr);
 930     if (is_processed_reg_num(reg)) {
 931       add_temp(reg, temp_pos, use_kind, opr->type_register());
 932     }
 933     reg = reg_numHi(opr);
 934     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 935       add_temp(reg, temp_pos, use_kind, opr->type_register());
 936     }
 937   }
 938 }
 939 
 940 
 941 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
 942   Interval* interval = interval_at(reg_num);
 943   if (interval != nullptr) {
 944     assert(interval->reg_num() == reg_num, "wrong interval");
 945 
 946     if (type != T_ILLEGAL) {
 947       interval->set_type(type);
 948     }
 949 
 950     Range* r = interval->first();
 951     if (r->from() <= def_pos) {
 952       // Update the starting point (when a range is first created for a use, its
 953       // start is the beginning of the current block until a def is encountered.)
 954       r->set_from(def_pos);
 955       interval->add_use_pos(def_pos, use_kind);
 956 
 957     } else {
 958       // Dead value - make vacuous interval
 959       // also add use_kind for dead intervals
 960       interval->add_range(def_pos, def_pos + 1);
 961       interval->add_use_pos(def_pos, use_kind);
 962       TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
 963     }
 964 
 965   } else {
 966     // Dead value - make vacuous interval
 967     // also add use_kind for dead intervals
 968     interval = create_interval(reg_num);
 969     if (type != T_ILLEGAL) {
 970       interval->set_type(type);
 971     }
 972 
 973     interval->add_range(def_pos, def_pos + 1);
 974     interval->add_use_pos(def_pos, use_kind);
 975     TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
 976   }
 977 
 978   change_spill_definition_pos(interval, def_pos);
 979   if (use_kind == noUse && interval->spill_state() <= startInMemory) {
 980         // detection of method-parameters and roundfp-results
 981         // TODO: move this directly to position where use-kind is computed
 982     interval->set_spill_state(startInMemory);
 983   }
 984 }
 985 
 986 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
 987   Interval* interval = interval_at(reg_num);
 988   if (interval == nullptr) {
 989     interval = create_interval(reg_num);
 990   }
 991   assert(interval->reg_num() == reg_num, "wrong interval");
 992 
 993   if (type != T_ILLEGAL) {
 994     interval->set_type(type);
 995   }
 996 
 997   interval->add_range(from, to);
 998   interval->add_use_pos(to, use_kind);
 999 }
1000 
1001 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1002   Interval* interval = interval_at(reg_num);
1003   if (interval == nullptr) {
1004     interval = create_interval(reg_num);
1005   }
1006   assert(interval->reg_num() == reg_num, "wrong interval");
1007 
1008   if (type != T_ILLEGAL) {
1009     interval->set_type(type);
1010   }
1011 
1012   interval->add_range(temp_pos, temp_pos + 1);
1013   interval->add_use_pos(temp_pos, use_kind);
1014 }
1015 
1016 
1017 // the results of this functions are used for optimizing spilling and reloading
1018 // if the functions return shouldHaveRegister and the interval is spilled,
1019 // it is not reloaded to a register.
1020 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1021   if (op->code() == lir_move) {
1022     assert(op->as_Op1() != nullptr, "lir_move must be LIR_Op1");
1023     LIR_Op1* move = (LIR_Op1*)op;
1024     LIR_Opr res = move->result_opr();
1025     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1026 
1027     if (result_in_memory) {
1028       // Begin of an interval with must_start_in_memory set.
1029       // This interval will always get a stack slot first, so return noUse.
1030       return noUse;
1031 
1032     } else if (move->in_opr()->is_stack()) {
1033       // method argument (condition must be equal to handle_method_arguments)
1034       return noUse;
1035 
1036     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1037       // Move from register to register
1038       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1039         // special handling of phi-function moves inside osr-entry blocks
1040         // input operand must have a register instead of output operand (leads to better register allocation)
1041         return shouldHaveRegister;
1042       }
1043     }
1044   }
1045 
1046   if (opr->is_virtual() &&
1047       gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1048     // result is a stack-slot, so prevent immediate reloading
1049     return noUse;
1050   }
1051 
1052   // all other operands require a register
1053   return mustHaveRegister;
1054 }
1055 
1056 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1057   if (op->code() == lir_move) {
1058     assert(op->as_Op1() != nullptr, "lir_move must be LIR_Op1");
1059     LIR_Op1* move = (LIR_Op1*)op;
1060     LIR_Opr res = move->result_opr();
1061     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1062 
1063     if (result_in_memory) {
1064       // Move to an interval with must_start_in_memory set.
1065       // To avoid moves from stack to stack (not allowed) force the input operand to a register
1066       return mustHaveRegister;
1067 
1068     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1069       // Move from register to register
1070       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1071         // special handling of phi-function moves inside osr-entry blocks
1072         // input operand must have a register instead of output operand (leads to better register allocation)
1073         return mustHaveRegister;
1074       }
1075 
1076       // The input operand is not forced to a register (moves from stack to register are allowed),
1077       // but it is faster if the input operand is in a register
1078       return shouldHaveRegister;
1079     }
1080   }
1081 
1082 
1083 #if defined(X86) || defined(S390)
1084   if (op->code() == lir_cmove) {
1085     // conditional moves can handle stack operands
1086     assert(op->result_opr()->is_register(), "result must always be in a register");
1087     return shouldHaveRegister;
1088   }
1089 
1090   // optimizations for second input operand of arithmehtic operations on Intel
1091   // this operand is allowed to be on the stack in some cases
1092   BasicType opr_type = opr->type_register();
1093   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1094     if (IA32_ONLY( (UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 ) NOT_IA32( true )) {
1095       // SSE float instruction (T_DOUBLE only supported with SSE2)
1096       switch (op->code()) {
1097         case lir_cmp:
1098         case lir_add:
1099         case lir_sub:
1100         case lir_mul:
1101         case lir_div:
1102         {
1103           assert(op->as_Op2() != nullptr, "must be LIR_Op2");
1104           LIR_Op2* op2 = (LIR_Op2*)op;
1105           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1106             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1107             return shouldHaveRegister;
1108           }
1109         }
1110         default:
1111           break;
1112       }
1113     } else {
1114       // FPU stack float instruction
1115       switch (op->code()) {
1116         case lir_add:
1117         case lir_sub:
1118         case lir_mul:
1119         case lir_div:
1120         {
1121           assert(op->as_Op2() != nullptr, "must be LIR_Op2");
1122           LIR_Op2* op2 = (LIR_Op2*)op;
1123           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1124             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1125             return shouldHaveRegister;
1126           }
1127         }
1128         default:
1129           break;
1130       }
1131     }
1132     // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1133     // Since 64bit logical operations do not current support operands on stack, we have to make sure
1134     // T_OBJECT doesn't get spilled along with T_LONG.
1135   } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1136     // integer instruction (note: long operands must always be in register)
1137     switch (op->code()) {
1138       case lir_cmp:
1139       case lir_add:
1140       case lir_sub:
1141       case lir_logic_and:
1142       case lir_logic_or:
1143       case lir_logic_xor:
1144       {
1145         assert(op->as_Op2() != nullptr, "must be LIR_Op2");
1146         LIR_Op2* op2 = (LIR_Op2*)op;
1147         if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1148           assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1149           return shouldHaveRegister;
1150         }
1151       }
1152       default:
1153         break;
1154     }
1155   }
1156 #endif // X86 || S390
1157 
1158   // all other operands require a register
1159   return mustHaveRegister;
1160 }
1161 
1162 
1163 void LinearScan::handle_method_arguments(LIR_Op* op) {
1164   // special handling for method arguments (moves from stack to virtual register):
1165   // the interval gets no register assigned, but the stack slot.
1166   // it is split before the first use by the register allocator.
1167 
1168   if (op->code() == lir_move) {
1169     assert(op->as_Op1() != nullptr, "must be LIR_Op1");
1170     LIR_Op1* move = (LIR_Op1*)op;
1171 
1172     if (move->in_opr()->is_stack()) {
1173 #ifdef ASSERT
1174       int arg_size = compilation()->method()->arg_size();
1175       LIR_Opr o = move->in_opr();
1176       if (o->is_single_stack()) {
1177         assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1178       } else if (o->is_double_stack()) {
1179         assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1180       } else {
1181         ShouldNotReachHere();
1182       }
1183 
1184       assert(move->id() > 0, "invalid id");
1185       assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1186       assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1187 
1188       TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1189 #endif
1190 
1191       Interval* interval = interval_at(reg_num(move->result_opr()));
1192 
1193       int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1194       interval->set_canonical_spill_slot(stack_slot);
1195       interval->assign_reg(stack_slot);
1196     }
1197   }
1198 }
1199 
1200 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1201   // special handling for doubleword move from memory to register:
1202   // in this case the registers of the input address and the result
1203   // registers must not overlap -> add a temp range for the input registers
1204   if (op->code() == lir_move) {
1205     assert(op->as_Op1() != nullptr, "must be LIR_Op1");
1206     LIR_Op1* move = (LIR_Op1*)op;
1207 
1208     if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1209       LIR_Address* address = move->in_opr()->as_address_ptr();
1210       if (address != nullptr) {
1211         if (address->base()->is_valid()) {
1212           add_temp(address->base(), op->id(), noUse);
1213         }
1214         if (address->index()->is_valid()) {
1215           add_temp(address->index(), op->id(), noUse);
1216         }
1217       }
1218     }
1219   }
1220 }
1221 
1222 void LinearScan::add_register_hints(LIR_Op* op) {
1223   switch (op->code()) {
1224     case lir_move:      // fall through
1225     case lir_convert: {
1226       assert(op->as_Op1() != nullptr, "lir_move, lir_convert must be LIR_Op1");
1227       LIR_Op1* move = (LIR_Op1*)op;
1228 
1229       LIR_Opr move_from = move->in_opr();
1230       LIR_Opr move_to = move->result_opr();
1231 
1232       if (move_to->is_register() && move_from->is_register()) {
1233         Interval* from = interval_at(reg_num(move_from));
1234         Interval* to = interval_at(reg_num(move_to));
1235         if (from != nullptr && to != nullptr) {
1236           to->set_register_hint(from);
1237           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1238         }
1239       }
1240       break;
1241     }
1242     case lir_cmove: {
1243       assert(op->as_Op4() != nullptr, "lir_cmove must be LIR_Op4");
1244       LIR_Op4* cmove = (LIR_Op4*)op;
1245 
1246       LIR_Opr move_from = cmove->in_opr1();
1247       LIR_Opr move_to   = cmove->result_opr();
1248 
1249       if (move_to->is_register() && move_from->is_register()) {
1250         Interval* from = interval_at(reg_num(move_from));
1251         Interval* to = interval_at(reg_num(move_to));
1252         if (from != nullptr && to != nullptr) {
1253           to->set_register_hint(from);
1254           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1255         }
1256       }
1257       break;
1258     }
1259     default:
1260       break;
1261   }
1262 }
1263 
1264 
1265 void LinearScan::build_intervals() {
1266   TIME_LINEAR_SCAN(timer_build_intervals);
1267 
1268   // initialize interval list with expected number of intervals
1269   // (32 is added to have some space for split children without having to resize the list)
1270   _intervals = IntervalList(num_virtual_regs() + 32);
1271   // initialize all slots that are used by build_intervals
1272   _intervals.at_put_grow(num_virtual_regs() - 1, nullptr, nullptr);
1273 
1274   // create a list with all caller-save registers (cpu, fpu, xmm)
1275   // when an instruction is a call, a temp range is created for all these registers
1276   int num_caller_save_registers = 0;
1277   int caller_save_registers[LinearScan::nof_regs];
1278 
1279   int i;
1280   for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1281     LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1282     assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1283     assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1284     caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1285   }
1286 
1287   // temp ranges for fpu registers are only created when the method has
1288   // virtual fpu operands. Otherwise no allocation for fpu registers is
1289   // performed and so the temp ranges would be useless
1290   if (has_fpu_registers()) {
1291 #ifdef X86
1292     if (UseSSE < 2) {
1293 #endif // X86
1294       for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1295         LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1296         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1297         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1298         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1299       }
1300 #ifdef X86
1301     }
1302 #endif // X86
1303 
1304 #ifdef X86
1305     if (UseSSE > 0) {
1306       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
1307       for (i = 0; i < num_caller_save_xmm_regs; i ++) {
1308         LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1309         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1310         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1311         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1312       }
1313     }
1314 #endif // X86
1315   }
1316   assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1317 
1318 
1319   LIR_OpVisitState visitor;
1320 
1321   // iterate all blocks in reverse order
1322   for (i = block_count() - 1; i >= 0; i--) {
1323     BlockBegin* block = block_at(i);
1324     LIR_OpList* instructions = block->lir()->instructions_list();
1325     int         block_from =   block->first_lir_instruction_id();
1326     int         block_to =     block->last_lir_instruction_id();
1327 
1328     assert(block_from == instructions->at(0)->id(), "must be");
1329     assert(block_to   == instructions->at(instructions->length() - 1)->id(), "must be");
1330 
1331     // Update intervals for registers live at the end of this block;
1332     ResourceBitMap& live = block->live_out();
1333     auto updater = [&](BitMap::idx_t index) {
1334       int number = static_cast<int>(index);
1335       assert(number >= LIR_Opr::vreg_base, "fixed intervals must not be live on block bounds");
1336       TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1337 
1338       add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1339 
1340       // add special use positions for loop-end blocks when the
1341       // interval is used anywhere inside this loop.  It's possible
1342       // that the block was part of a non-natural loop, so it might
1343       // have an invalid loop index.
1344       if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1345           block->loop_index() != -1 &&
1346           is_interval_in_loop(number, block->loop_index())) {
1347         interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1348       }
1349     };
1350     live.iterate(updater);
1351 
1352     // iterate all instructions of the block in reverse order.
1353     // skip the first instruction because it is always a label
1354     // definitions of intervals are processed before uses
1355     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1356     for (int j = instructions->length() - 1; j >= 1; j--) {
1357       LIR_Op* op = instructions->at(j);
1358       int op_id = op->id();
1359 
1360       // visit operation to collect all operands
1361       visitor.visit(op);
1362 
1363       // add a temp range for each register if operation destroys caller-save registers
1364       if (visitor.has_call()) {
1365         for (int k = 0; k < num_caller_save_registers; k++) {
1366           add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1367         }
1368         TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1369       }
1370 
1371       // Add any platform dependent temps
1372       pd_add_temps(op);
1373 
1374       // visit definitions (output and temp operands)
1375       int k, n;
1376       n = visitor.opr_count(LIR_OpVisitState::outputMode);
1377       for (k = 0; k < n; k++) {
1378         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1379         assert(opr->is_register(), "visitor should only return register operands");
1380         add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1381       }
1382 
1383       n = visitor.opr_count(LIR_OpVisitState::tempMode);
1384       for (k = 0; k < n; k++) {
1385         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1386         assert(opr->is_register(), "visitor should only return register operands");
1387         add_temp(opr, op_id, mustHaveRegister);
1388       }
1389 
1390       // visit uses (input operands)
1391       n = visitor.opr_count(LIR_OpVisitState::inputMode);
1392       for (k = 0; k < n; k++) {
1393         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1394         assert(opr->is_register(), "visitor should only return register operands");
1395         add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1396       }
1397 
1398       // Add uses of live locals from interpreter's point of view for proper
1399       // debug information generation
1400       // Treat these operands as temp values (if the life range is extended
1401       // to a call site, the value would be in a register at the call otherwise)
1402       n = visitor.info_count();
1403       for (k = 0; k < n; k++) {
1404         CodeEmitInfo* info = visitor.info_at(k);
1405         ValueStack* stack = info->stack();
1406         for_each_state_value(stack, value,
1407           add_use(value, block_from, op_id + 1, noUse);
1408         );
1409       }
1410 
1411       // special steps for some instructions (especially moves)
1412       handle_method_arguments(op);
1413       handle_doubleword_moves(op);
1414       add_register_hints(op);
1415 
1416     } // end of instruction iteration
1417   } // end of block iteration
1418 
1419 
1420   // add the range [0, 1[ to all fixed intervals
1421   // -> the register allocator need not handle unhandled fixed intervals
1422   for (int n = 0; n < LinearScan::nof_regs; n++) {
1423     Interval* interval = interval_at(n);
1424     if (interval != nullptr) {
1425       interval->add_range(0, 1);
1426     }
1427   }
1428 }
1429 
1430 
1431 // ********** Phase 5: actual register allocation
1432 
1433 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1434   if (*a != nullptr) {
1435     if (*b != nullptr) {
1436       return (*a)->from() - (*b)->from();
1437     } else {
1438       return -1;
1439     }
1440   } else {
1441     if (*b != nullptr) {
1442       return 1;
1443     } else {
1444       return 0;
1445     }
1446   }
1447 }
1448 
1449 #ifdef ASSERT
1450 static int interval_cmp(Interval* const& l, Interval* const& r) {
1451   return l->from() - r->from();
1452 }
1453 
1454 static bool find_interval(Interval* interval, IntervalArray* intervals) {
1455   bool found;
1456   int idx = intervals->find_sorted<Interval*, interval_cmp>(interval, found);
1457 
1458   if (!found) {
1459     return false;
1460   }
1461 
1462   int from = interval->from();
1463 
1464   // The index we've found using binary search is pointing to an interval
1465   // that is defined in the same place as the interval we were looking for.
1466   // So now we have to look around that index and find exact interval.
1467   for (int i = idx; i >= 0; i--) {
1468     if (intervals->at(i) == interval) {
1469       return true;
1470     }
1471     if (intervals->at(i)->from() != from) {
1472       break;
1473     }
1474   }
1475 
1476   for (int i = idx + 1; i < intervals->length(); i++) {
1477     if (intervals->at(i) == interval) {
1478       return true;
1479     }
1480     if (intervals->at(i)->from() != from) {
1481       break;
1482     }
1483   }
1484 
1485   return false;
1486 }
1487 
1488 bool LinearScan::is_sorted(IntervalArray* intervals) {
1489   int from = -1;
1490   int null_count = 0;
1491 
1492   for (int i = 0; i < intervals->length(); i++) {
1493     Interval* it = intervals->at(i);
1494     if (it != nullptr) {
1495       assert(from <= it->from(), "Intervals are unordered");
1496       from = it->from();
1497     } else {
1498       null_count++;
1499     }
1500   }
1501 
1502   assert(null_count == 0, "Sorted intervals should not contain nulls");
1503 
1504   null_count = 0;
1505 
1506   for (int i = 0; i < interval_count(); i++) {
1507     Interval* interval = interval_at(i);
1508     if (interval != nullptr) {
1509       assert(find_interval(interval, intervals), "Lists do not contain same intervals");
1510     } else {
1511       null_count++;
1512     }
1513   }
1514 
1515   assert(interval_count() - null_count == intervals->length(),
1516       "Sorted list should contain the same amount of non-null intervals as unsorted list");
1517 
1518   return true;
1519 }
1520 #endif
1521 
1522 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1523   if (*prev != nullptr) {
1524     (*prev)->set_next(interval);
1525   } else {
1526     *first = interval;
1527   }
1528   *prev = interval;
1529 }
1530 
1531 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1532   assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1533 
1534   *list1 = *list2 = Interval::end();
1535 
1536   Interval* list1_prev = nullptr;
1537   Interval* list2_prev = nullptr;
1538   Interval* v;
1539 
1540   const int n = _sorted_intervals->length();
1541   for (int i = 0; i < n; i++) {
1542     v = _sorted_intervals->at(i);
1543     if (v == nullptr) continue;
1544 
1545     if (is_list1(v)) {
1546       add_to_list(list1, &list1_prev, v);
1547     } else if (is_list2 == nullptr || is_list2(v)) {
1548       add_to_list(list2, &list2_prev, v);
1549     }
1550   }
1551 
1552   if (list1_prev != nullptr) list1_prev->set_next(Interval::end());
1553   if (list2_prev != nullptr) list2_prev->set_next(Interval::end());
1554 
1555   assert(list1_prev == nullptr || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1556   assert(list2_prev == nullptr || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1557 }
1558 
1559 
1560 void LinearScan::sort_intervals_before_allocation() {
1561   TIME_LINEAR_SCAN(timer_sort_intervals_before);
1562 
1563   if (_needs_full_resort) {
1564     // There is no known reason why this should occur but just in case...
1565     assert(false, "should never occur");
1566     // Re-sort existing interval list because an Interval::from() has changed
1567     _sorted_intervals->sort(interval_cmp);
1568     _needs_full_resort = false;
1569   }
1570 
1571   IntervalList* unsorted_list = &_intervals;
1572   int unsorted_len = unsorted_list->length();
1573   int sorted_len = 0;
1574   int unsorted_idx;
1575   int sorted_idx = 0;
1576   int sorted_from_max = -1;
1577 
1578   // calc number of items for sorted list (sorted list must not contain null values)
1579   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1580     if (unsorted_list->at(unsorted_idx) != nullptr) {
1581       sorted_len++;
1582     }
1583   }
1584   IntervalArray* sorted_list = new IntervalArray(sorted_len, sorted_len, nullptr);
1585 
1586   // special sorting algorithm: the original interval-list is almost sorted,
1587   // only some intervals are swapped. So this is much faster than a complete QuickSort
1588   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1589     Interval* cur_interval = unsorted_list->at(unsorted_idx);
1590 
1591     if (cur_interval != nullptr) {
1592       int cur_from = cur_interval->from();
1593 
1594       if (sorted_from_max <= cur_from) {
1595         sorted_list->at_put(sorted_idx++, cur_interval);
1596         sorted_from_max = cur_interval->from();
1597       } else {
1598         // the assumption that the intervals are already sorted failed,
1599         // so this interval must be sorted in manually
1600         int j;
1601         for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1602           sorted_list->at_put(j + 1, sorted_list->at(j));
1603         }
1604         sorted_list->at_put(j + 1, cur_interval);
1605         sorted_idx++;
1606       }
1607     }
1608   }
1609   _sorted_intervals = sorted_list;
1610   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1611 }
1612 
1613 void LinearScan::sort_intervals_after_allocation() {
1614   TIME_LINEAR_SCAN(timer_sort_intervals_after);
1615 
1616   if (_needs_full_resort) {
1617     // Re-sort existing interval list because an Interval::from() has changed
1618     _sorted_intervals->sort(interval_cmp);
1619     _needs_full_resort = false;
1620   }
1621 
1622   IntervalArray* old_list = _sorted_intervals;
1623   IntervalList* new_list = _new_intervals_from_allocation;
1624   int old_len = old_list->length();
1625   int new_len = new_list == nullptr ? 0 : new_list->length();
1626 
1627   if (new_len == 0) {
1628     // no intervals have been added during allocation, so sorted list is already up to date
1629     assert(is_sorted(_sorted_intervals), "intervals unsorted");
1630     return;
1631   }
1632 
1633   // conventional sort-algorithm for new intervals
1634   new_list->sort(interval_cmp);
1635 
1636   // merge old and new list (both already sorted) into one combined list
1637   int combined_list_len = old_len + new_len;
1638   IntervalArray* combined_list = new IntervalArray(combined_list_len, combined_list_len, nullptr);
1639   int old_idx = 0;
1640   int new_idx = 0;
1641 
1642   while (old_idx + new_idx < old_len + new_len) {
1643     if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1644       combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1645       old_idx++;
1646     } else {
1647       combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1648       new_idx++;
1649     }
1650   }
1651 
1652   _sorted_intervals = combined_list;
1653   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1654 }
1655 
1656 
1657 void LinearScan::allocate_registers() {
1658   TIME_LINEAR_SCAN(timer_allocate_registers);
1659 
1660   Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1661   Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1662 
1663   // collect cpu intervals
1664   create_unhandled_lists(&precolored_cpu_intervals, &not_precolored_cpu_intervals,
1665                          is_precolored_cpu_interval, is_virtual_cpu_interval);
1666 
1667   // collect fpu intervals
1668   create_unhandled_lists(&precolored_fpu_intervals, &not_precolored_fpu_intervals,
1669                          is_precolored_fpu_interval, is_virtual_fpu_interval);
1670   // this fpu interval collection cannot be moved down below with the allocation section as
1671   // the cpu_lsw.walk() changes interval positions.
1672 
1673   if (!has_fpu_registers()) {
1674 #ifdef ASSERT
1675     assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval");
1676 #else
1677     if (not_precolored_fpu_intervals != Interval::end()) {
1678       BAILOUT("missed an uncolored fpu interval");
1679     }
1680 #endif
1681   }
1682 
1683   // allocate cpu registers
1684   LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1685   cpu_lsw.walk();
1686   cpu_lsw.finish_allocation();
1687 
1688   if (has_fpu_registers()) {
1689     // allocate fpu registers
1690     LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1691     fpu_lsw.walk();
1692     fpu_lsw.finish_allocation();
1693   }
1694 }
1695 
1696 
1697 // ********** Phase 6: resolve data flow
1698 // (insert moves at edges between blocks if intervals have been split)
1699 
1700 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1701 // instead of returning null
1702 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1703   Interval* result = interval->split_child_at_op_id(op_id, mode);
1704   if (result != nullptr) {
1705     return result;
1706   }
1707 
1708   assert(false, "must find an interval, but do a clean bailout in product mode");
1709   result = new Interval(LIR_Opr::vreg_base);
1710   result->assign_reg(0);
1711   result->set_type(T_INT);
1712   BAILOUT_("LinearScan: interval is null", result);
1713 }
1714 
1715 
1716 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1717   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1718   assert(interval_at(reg_num) != nullptr, "no interval found");
1719 
1720   return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1721 }
1722 
1723 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1724   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1725   assert(interval_at(reg_num) != nullptr, "no interval found");
1726 
1727   return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1728 }
1729 
1730 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1731   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1732   assert(interval_at(reg_num) != nullptr, "no interval found");
1733 
1734   return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1735 }
1736 
1737 
1738 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1739   DEBUG_ONLY(move_resolver.check_empty());
1740 
1741   // visit all registers where the live_at_edge bit is set
1742   const ResourceBitMap& live_at_edge = to_block->live_in();
1743   auto visitor = [&](BitMap::idx_t index) {
1744     int r = static_cast<int>(index);
1745     assert(r < num_virtual_regs(), "live information set for not existing interval");
1746     assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1747 
1748     Interval* from_interval = interval_at_block_end(from_block, r);
1749     Interval* to_interval = interval_at_block_begin(to_block, r);
1750 
1751     if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1752       // need to insert move instruction
1753       move_resolver.add_mapping(from_interval, to_interval);
1754     }
1755   };
1756   live_at_edge.iterate(visitor, 0, live_set_size());
1757 }
1758 
1759 
1760 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1761   if (from_block->number_of_sux() <= 1) {
1762     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1763 
1764     LIR_OpList* instructions = from_block->lir()->instructions_list();
1765     LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1766     if (branch != nullptr) {
1767       // insert moves before branch
1768       assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1769       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1770     } else {
1771       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1772     }
1773 
1774   } else {
1775     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1776 #ifdef ASSERT
1777     assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != nullptr, "block does not start with a label");
1778 
1779     // because the number of predecessor edges matches the number of
1780     // successor edges, blocks which are reached by switch statements
1781     // may have be more than one predecessor but it will be guaranteed
1782     // that all predecessors will be the same.
1783     for (int i = 0; i < to_block->number_of_preds(); i++) {
1784       assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1785     }
1786 #endif
1787 
1788     move_resolver.set_insert_position(to_block->lir(), 0);
1789   }
1790 }
1791 
1792 
1793 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1794 void LinearScan::resolve_data_flow() {
1795   TIME_LINEAR_SCAN(timer_resolve_data_flow);
1796 
1797   int num_blocks = block_count();
1798   MoveResolver move_resolver(this);
1799   ResourceBitMap block_completed(num_blocks);
1800   ResourceBitMap already_resolved(num_blocks);
1801 
1802   int i;
1803   for (i = 0; i < num_blocks; i++) {
1804     BlockBegin* block = block_at(i);
1805 
1806     // check if block has only one predecessor and only one successor
1807     if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1808       LIR_OpList* instructions = block->lir()->instructions_list();
1809       assert(instructions->at(0)->code() == lir_label, "block must start with label");
1810       assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1811       assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1812 
1813       // check if block is empty (only label and branch)
1814       if (instructions->length() == 2) {
1815         BlockBegin* pred = block->pred_at(0);
1816         BlockBegin* sux = block->sux_at(0);
1817 
1818         // prevent optimization of two consecutive blocks
1819         if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1820           TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1821           block_completed.set_bit(block->linear_scan_number());
1822 
1823           // directly resolve between pred and sux (without looking at the empty block between)
1824           resolve_collect_mappings(pred, sux, move_resolver);
1825           if (move_resolver.has_mappings()) {
1826             move_resolver.set_insert_position(block->lir(), 0);
1827             move_resolver.resolve_and_append_moves();
1828           }
1829         }
1830       }
1831     }
1832   }
1833 
1834 
1835   for (i = 0; i < num_blocks; i++) {
1836     if (!block_completed.at(i)) {
1837       BlockBegin* from_block = block_at(i);
1838       already_resolved.set_from(block_completed);
1839 
1840       int num_sux = from_block->number_of_sux();
1841       for (int s = 0; s < num_sux; s++) {
1842         BlockBegin* to_block = from_block->sux_at(s);
1843 
1844         // check for duplicate edges between the same blocks (can happen with switch blocks)
1845         if (!already_resolved.at(to_block->linear_scan_number())) {
1846           TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1847           already_resolved.set_bit(to_block->linear_scan_number());
1848 
1849           // collect all intervals that have been split between from_block and to_block
1850           resolve_collect_mappings(from_block, to_block, move_resolver);
1851           if (move_resolver.has_mappings()) {
1852             resolve_find_insert_pos(from_block, to_block, move_resolver);
1853             move_resolver.resolve_and_append_moves();
1854           }
1855         }
1856       }
1857     }
1858   }
1859 }
1860 
1861 
1862 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1863   if (interval_at(reg_num) == nullptr) {
1864     // if a phi function is never used, no interval is created -> ignore this
1865     return;
1866   }
1867 
1868   Interval* interval = interval_at_block_begin(block, reg_num);
1869   int reg = interval->assigned_reg();
1870   int regHi = interval->assigned_regHi();
1871 
1872   if ((reg < nof_regs && interval->always_in_memory()) ||
1873       (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1874     // the interval is split to get a short range that is located on the stack
1875     // in the following two cases:
1876     // * the interval started in memory (e.g. method parameter), but is currently in a register
1877     //   this is an optimization for exception handling that reduces the number of moves that
1878     //   are necessary for resolving the states when an exception uses this exception handler
1879     // * the interval would be on the fpu stack at the begin of the exception handler
1880     //   this is not allowed because of the complicated fpu stack handling on Intel
1881 
1882     // range that will be spilled to memory
1883     int from_op_id = block->first_lir_instruction_id();
1884     int to_op_id = from_op_id + 1;  // short live range of length 1
1885     assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1886            "no split allowed between exception entry and first instruction");
1887 
1888     if (interval->from() != from_op_id) {
1889       // the part before from_op_id is unchanged
1890       interval = interval->split(from_op_id);
1891       interval->assign_reg(reg, regHi);
1892       append_interval(interval);
1893     } else {
1894       _needs_full_resort = true;
1895     }
1896     assert(interval->from() == from_op_id, "must be true now");
1897 
1898     Interval* spilled_part = interval;
1899     if (interval->to() != to_op_id) {
1900       // the part after to_op_id is unchanged
1901       spilled_part = interval->split_from_start(to_op_id);
1902       append_interval(spilled_part);
1903       move_resolver.add_mapping(spilled_part, interval);
1904     }
1905     assign_spill_slot(spilled_part);
1906 
1907     assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1908   }
1909 }
1910 
1911 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1912   assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1913   DEBUG_ONLY(move_resolver.check_empty());
1914 
1915   // visit all registers where the live_in bit is set
1916   auto resolver = [&](BitMap::idx_t index) {
1917     int r = static_cast<int>(index);
1918     resolve_exception_entry(block, r, move_resolver);
1919   };
1920   block->live_in().iterate(resolver, 0, live_set_size());
1921 
1922   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1923   for_each_phi_fun(block, phi,
1924     if (!phi->is_illegal()) { resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver); }
1925   );
1926 
1927   if (move_resolver.has_mappings()) {
1928     // insert moves after first instruction
1929     move_resolver.set_insert_position(block->lir(), 0);
1930     move_resolver.resolve_and_append_moves();
1931   }
1932 }
1933 
1934 
1935 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1936   if (interval_at(reg_num) == nullptr) {
1937     // if a phi function is never used, no interval is created -> ignore this
1938     return;
1939   }
1940 
1941   // the computation of to_interval is equal to resolve_collect_mappings,
1942   // but from_interval is more complicated because of phi functions
1943   BlockBegin* to_block = handler->entry_block();
1944   Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1945 
1946   if (phi != nullptr) {
1947     // phi function of the exception entry block
1948     // no moves are created for this phi function in the LIR_Generator, so the
1949     // interval at the throwing instruction must be searched using the operands
1950     // of the phi function
1951     Value from_value = phi->operand_at(handler->phi_operand());
1952     if (from_value == nullptr) {
1953       // We have reached here in a kotlin application running with JVMTI
1954       // capability "can_access_local_variables".
1955       // The illegal state is not yet propagated to this phi. Do it here.
1956       phi->make_illegal();
1957       // We can skip the illegal phi edge.
1958       return;
1959     }
1960 
1961     // with phi functions it can happen that the same from_value is used in
1962     // multiple mappings, so notify move-resolver that this is allowed
1963     move_resolver.set_multiple_reads_allowed();
1964 
1965     Constant* con = from_value->as_Constant();
1966     if (con != nullptr && (!con->is_pinned() || con->operand()->is_constant())) {
1967       // Need a mapping from constant to interval if unpinned (may have no register) or if the operand is a constant (no register).
1968       move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1969     } else {
1970       // search split child at the throwing op_id
1971       Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1972       move_resolver.add_mapping(from_interval, to_interval);
1973     }
1974   } else {
1975     // no phi function, so use reg_num also for from_interval
1976     // search split child at the throwing op_id
1977     Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1978     if (from_interval != to_interval) {
1979       // optimization to reduce number of moves: when to_interval is on stack and
1980       // the stack slot is known to be always correct, then no move is necessary
1981       if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1982         move_resolver.add_mapping(from_interval, to_interval);
1983       }
1984     }
1985   }
1986 }
1987 
1988 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1989   TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1990 
1991   DEBUG_ONLY(move_resolver.check_empty());
1992   assert(handler->lir_op_id() == -1, "already processed this xhandler");
1993   DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1994   assert(handler->entry_code() == nullptr, "code already present");
1995 
1996   // visit all registers where the live_in bit is set
1997   BlockBegin* block = handler->entry_block();
1998   auto resolver = [&](BitMap::idx_t index) {
1999     int r = static_cast<int>(index);
2000     resolve_exception_edge(handler, throwing_op_id, r, nullptr, move_resolver);
2001   };
2002   block->live_in().iterate(resolver, 0, live_set_size());
2003 
2004   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
2005   for_each_phi_fun(block, phi,
2006     if (!phi->is_illegal()) { resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver); }
2007   );
2008 
2009   if (move_resolver.has_mappings()) {
2010     LIR_List* entry_code = new LIR_List(compilation());
2011     move_resolver.set_insert_position(entry_code, 0);
2012     move_resolver.resolve_and_append_moves();
2013 
2014     entry_code->jump(handler->entry_block());
2015     handler->set_entry_code(entry_code);
2016   }
2017 }
2018 
2019 
2020 void LinearScan::resolve_exception_handlers() {
2021   MoveResolver move_resolver(this);
2022   LIR_OpVisitState visitor;
2023   int num_blocks = block_count();
2024 
2025   int i;
2026   for (i = 0; i < num_blocks; i++) {
2027     BlockBegin* block = block_at(i);
2028     if (block->is_set(BlockBegin::exception_entry_flag)) {
2029       resolve_exception_entry(block, move_resolver);
2030     }
2031   }
2032 
2033   for (i = 0; i < num_blocks; i++) {
2034     BlockBegin* block = block_at(i);
2035     LIR_List* ops = block->lir();
2036     int num_ops = ops->length();
2037 
2038     // iterate all instructions of the block. skip the first because it is always a label
2039     assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
2040     for (int j = 1; j < num_ops; j++) {
2041       LIR_Op* op = ops->at(j);
2042       int op_id = op->id();
2043 
2044       if (op_id != -1 && has_info(op_id)) {
2045         // visit operation to collect all operands
2046         visitor.visit(op);
2047         assert(visitor.info_count() > 0, "should not visit otherwise");
2048 
2049         XHandlers* xhandlers = visitor.all_xhandler();
2050         int n = xhandlers->length();
2051         for (int k = 0; k < n; k++) {
2052           resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
2053         }
2054 
2055 #ifdef ASSERT
2056       } else {
2057         visitor.visit(op);
2058         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2059 #endif
2060       }
2061     }
2062   }
2063 }
2064 
2065 
2066 // ********** Phase 7: assign register numbers back to LIR
2067 // (includes computation of debug information and oop maps)
2068 
2069 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2070   VMReg reg = interval->cached_vm_reg();
2071   if (!reg->is_valid() ) {
2072     reg = vm_reg_for_operand(operand_for_interval(interval));
2073     interval->set_cached_vm_reg(reg);
2074   }
2075   assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2076   return reg;
2077 }
2078 
2079 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2080   assert(opr->is_oop(), "currently only implemented for oop operands");
2081   return frame_map()->regname(opr);
2082 }
2083 
2084 
2085 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2086   LIR_Opr opr = interval->cached_opr();
2087   if (opr->is_illegal()) {
2088     opr = calc_operand_for_interval(interval);
2089     interval->set_cached_opr(opr);
2090   }
2091 
2092   assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2093   return opr;
2094 }
2095 
2096 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2097   int assigned_reg = interval->assigned_reg();
2098   BasicType type = interval->type();
2099 
2100   if (assigned_reg >= nof_regs) {
2101     // stack slot
2102     assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2103     return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2104 
2105   } else {
2106     // register
2107     switch (type) {
2108       case T_OBJECT: {
2109         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2110         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2111         return LIR_OprFact::single_cpu_oop(assigned_reg);
2112       }
2113 
2114       case T_ADDRESS: {
2115         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2116         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2117         return LIR_OprFact::single_cpu_address(assigned_reg);
2118       }
2119 
2120       case T_METADATA: {
2121         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2122         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2123         return LIR_OprFact::single_cpu_metadata(assigned_reg);
2124       }
2125 
2126 #ifdef __SOFTFP__
2127       case T_FLOAT:  // fall through
2128 #endif // __SOFTFP__
2129       case T_INT: {
2130         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2131         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2132         return LIR_OprFact::single_cpu(assigned_reg);
2133       }
2134 
2135 #ifdef __SOFTFP__
2136       case T_DOUBLE:  // fall through
2137 #endif // __SOFTFP__
2138       case T_LONG: {
2139         int assigned_regHi = interval->assigned_regHi();
2140         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2141         assert(num_physical_regs(T_LONG) == 1 ||
2142                (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2143 
2144         assert(assigned_reg != assigned_regHi, "invalid allocation");
2145         assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2146                "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2147         assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2148         if (requires_adjacent_regs(T_LONG)) {
2149           assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2150         }
2151 
2152 #ifdef _LP64
2153         return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2154 #else
2155         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2156 #endif // LP64
2157       }
2158 
2159 #ifndef __SOFTFP__
2160       case T_FLOAT: {
2161 #ifdef X86
2162         if (UseSSE >= 1) {
2163           int last_xmm_reg = pd_last_xmm_reg;
2164 #ifdef _LP64
2165           if (UseAVX < 3) {
2166             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2167           }
2168 #endif // LP64
2169           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2170           assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2171           return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2172         }
2173 #endif // X86
2174 
2175         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2176         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2177         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2178       }
2179 
2180       case T_DOUBLE: {
2181 #ifdef X86
2182         if (UseSSE >= 2) {
2183           int last_xmm_reg = pd_last_xmm_reg;
2184 #ifdef _LP64
2185           if (UseAVX < 3) {
2186             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2187           }
2188 #endif // LP64
2189           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2190           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2191           return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2192         }
2193 #endif // X86
2194 
2195 #if defined(ARM32)
2196         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2197         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2198         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2199         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2200 #else
2201         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2202         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2203         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2204 #endif
2205         return result;
2206       }
2207 #endif // __SOFTFP__
2208 
2209       default: {
2210         ShouldNotReachHere();
2211         return LIR_OprFact::illegalOpr;
2212       }
2213     }
2214   }
2215 }
2216 
2217 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2218   assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2219   return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2220 }
2221 
2222 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2223   assert(opr->is_virtual(), "should not call this otherwise");
2224 
2225   Interval* interval = interval_at(opr->vreg_number());
2226   assert(interval != nullptr, "interval must exist");
2227 
2228   if (op_id != -1) {
2229 #ifdef ASSERT
2230     BlockBegin* block = block_of_op_with_id(op_id);
2231     if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2232       // check if spill moves could have been appended at the end of this block, but
2233       // before the branch instruction. So the split child information for this branch would
2234       // be incorrect.
2235       LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2236       if (branch != nullptr) {
2237         if (block->live_out().at(opr->vreg_number())) {
2238           assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2239           assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2240         }
2241       }
2242     }
2243 #endif
2244 
2245     // operands are not changed when an interval is split during allocation,
2246     // so search the right interval here
2247     interval = split_child_at_op_id(interval, op_id, mode);
2248   }
2249 
2250   LIR_Opr res = operand_for_interval(interval);
2251 
2252 #ifdef X86
2253   // new semantic for is_last_use: not only set on definite end of interval,
2254   // but also before hole
2255   // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2256   // last use information is completely correct
2257   // information is only needed for fpu stack allocation
2258   if (res->is_fpu_register()) {
2259     if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2260       assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2261       res = res->make_last_use();
2262     }
2263   }
2264 #endif
2265 
2266   assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2267 
2268   return res;
2269 }
2270 
2271 
2272 #ifdef ASSERT
2273 // some methods used to check correctness of debug information
2274 
2275 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2276   if (values == nullptr) {
2277     return;
2278   }
2279 
2280   for (int i = 0; i < values->length(); i++) {
2281     ScopeValue* value = values->at(i);
2282 
2283     if (value->is_location()) {
2284       Location location = ((LocationValue*)value)->location();
2285       assert(location.where() == Location::on_stack, "value is in register");
2286     }
2287   }
2288 }
2289 
2290 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2291   if (values == nullptr) {
2292     return;
2293   }
2294 
2295   for (int i = 0; i < values->length(); i++) {
2296     MonitorValue* value = values->at(i);
2297 
2298     if (value->owner()->is_location()) {
2299       Location location = ((LocationValue*)value->owner())->location();
2300       assert(location.where() == Location::on_stack, "owner is in register");
2301     }
2302     assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2303   }
2304 }
2305 
2306 static void assert_equal(Location l1, Location l2) {
2307   assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2308 }
2309 
2310 static void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2311   if (v1->is_location()) {
2312     assert(v2->is_location(), "");
2313     assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2314   } else if (v1->is_constant_int()) {
2315     assert(v2->is_constant_int(), "");
2316     assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2317   } else if (v1->is_constant_double()) {
2318     assert(v2->is_constant_double(), "");
2319     assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2320   } else if (v1->is_constant_long()) {
2321     assert(v2->is_constant_long(), "");
2322     assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2323   } else if (v1->is_constant_oop()) {
2324     assert(v2->is_constant_oop(), "");
2325     assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2326   } else {
2327     ShouldNotReachHere();
2328   }
2329 }
2330 
2331 static void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2332   assert_equal(m1->owner(), m2->owner());
2333   assert_equal(m1->basic_lock(), m2->basic_lock());
2334 }
2335 
2336 static void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2337   assert(d1->scope() == d2->scope(), "not equal");
2338   assert(d1->bci() == d2->bci(), "not equal");
2339 
2340   if (d1->locals() != nullptr) {
2341     assert(d1->locals() != nullptr && d2->locals() != nullptr, "not equal");
2342     assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2343     for (int i = 0; i < d1->locals()->length(); i++) {
2344       assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2345     }
2346   } else {
2347     assert(d1->locals() == nullptr && d2->locals() == nullptr, "not equal");
2348   }
2349 
2350   if (d1->expressions() != nullptr) {
2351     assert(d1->expressions() != nullptr && d2->expressions() != nullptr, "not equal");
2352     assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2353     for (int i = 0; i < d1->expressions()->length(); i++) {
2354       assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2355     }
2356   } else {
2357     assert(d1->expressions() == nullptr && d2->expressions() == nullptr, "not equal");
2358   }
2359 
2360   if (d1->monitors() != nullptr) {
2361     assert(d1->monitors() != nullptr && d2->monitors() != nullptr, "not equal");
2362     assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2363     for (int i = 0; i < d1->monitors()->length(); i++) {
2364       assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2365     }
2366   } else {
2367     assert(d1->monitors() == nullptr && d2->monitors() == nullptr, "not equal");
2368   }
2369 
2370   if (d1->caller() != nullptr) {
2371     assert(d1->caller() != nullptr && d2->caller() != nullptr, "not equal");
2372     assert_equal(d1->caller(), d2->caller());
2373   } else {
2374     assert(d1->caller() == nullptr && d2->caller() == nullptr, "not equal");
2375   }
2376 }
2377 
2378 static void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2379   if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2380     Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2381     switch (code) {
2382       case Bytecodes::_ifnull    : // fall through
2383       case Bytecodes::_ifnonnull : // fall through
2384       case Bytecodes::_ifeq      : // fall through
2385       case Bytecodes::_ifne      : // fall through
2386       case Bytecodes::_iflt      : // fall through
2387       case Bytecodes::_ifge      : // fall through
2388       case Bytecodes::_ifgt      : // fall through
2389       case Bytecodes::_ifle      : // fall through
2390       case Bytecodes::_if_icmpeq : // fall through
2391       case Bytecodes::_if_icmpne : // fall through
2392       case Bytecodes::_if_icmplt : // fall through
2393       case Bytecodes::_if_icmpge : // fall through
2394       case Bytecodes::_if_icmpgt : // fall through
2395       case Bytecodes::_if_icmple : // fall through
2396       case Bytecodes::_if_acmpeq : // fall through
2397       case Bytecodes::_if_acmpne :
2398         assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2399         break;
2400       default:
2401         break;
2402     }
2403   }
2404 }
2405 
2406 #endif // ASSERT
2407 
2408 
2409 IntervalWalker* LinearScan::init_compute_oop_maps() {
2410   // setup lists of potential oops for walking
2411   Interval* oop_intervals;
2412   Interval* non_oop_intervals;
2413 
2414   create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, nullptr);
2415 
2416   // intervals that have no oops inside need not to be processed
2417   // to ensure a walking until the last instruction id, add a dummy interval
2418   // with a high operation id
2419   non_oop_intervals = new Interval(any_reg);
2420   non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2421 
2422   return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2423 }
2424 
2425 
2426 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2427   TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2428 
2429   // walk before the current operation -> intervals that start at
2430   // the operation (= output operands of the operation) are not
2431   // included in the oop map
2432   iw->walk_before(op->id());
2433 
2434   int frame_size = frame_map()->framesize();
2435   int arg_count = frame_map()->oop_map_arg_count();
2436   OopMap* map = new OopMap(frame_size, arg_count);
2437 
2438   // Iterate through active intervals
2439   for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2440     int assigned_reg = interval->assigned_reg();
2441 
2442     assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2443     assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2444     assert(interval->reg_num() >= LIR_Opr::vreg_base, "fixed interval found");
2445 
2446     // Check if this range covers the instruction. Intervals that
2447     // start or end at the current operation are not included in the
2448     // oop map, except in the case of patching moves.  For patching
2449     // moves, any intervals which end at this instruction are included
2450     // in the oop map since we may safepoint while doing the patch
2451     // before we've consumed the inputs.
2452     if (op->is_patching() || op->id() < interval->current_to()) {
2453 
2454       // caller-save registers must not be included into oop-maps at calls
2455       assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2456 
2457       VMReg name = vm_reg_for_interval(interval);
2458       set_oop(map, name);
2459 
2460       // Spill optimization: when the stack value is guaranteed to be always correct,
2461       // then it must be added to the oop map even if the interval is currently in a register
2462       if (interval->always_in_memory() &&
2463           op->id() > interval->spill_definition_pos() &&
2464           interval->assigned_reg() != interval->canonical_spill_slot()) {
2465         assert(interval->spill_definition_pos() > 0, "position not set correctly");
2466         assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2467         assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2468 
2469         set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2470       }
2471     }
2472   }
2473 
2474   // add oops from lock stack
2475   assert(info->stack() != nullptr, "CodeEmitInfo must always have a stack");
2476   int locks_count = info->stack()->total_locks_size();
2477   for (int i = 0; i < locks_count; i++) {
2478     set_oop(map, frame_map()->monitor_object_regname(i));
2479   }
2480 
2481   return map;
2482 }
2483 
2484 
2485 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2486   assert(visitor.info_count() > 0, "no oop map needed");
2487 
2488   // compute oop_map only for first CodeEmitInfo
2489   // because it is (in most cases) equal for all other infos of the same operation
2490   CodeEmitInfo* first_info = visitor.info_at(0);
2491   OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2492 
2493   for (int i = 0; i < visitor.info_count(); i++) {
2494     CodeEmitInfo* info = visitor.info_at(i);
2495     OopMap* oop_map = first_oop_map;
2496 
2497     // compute worst case interpreter size in case of a deoptimization
2498     _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2499 
2500     if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2501       // this info has a different number of locks then the precomputed oop map
2502       // (possible for lock and unlock instructions) -> compute oop map with
2503       // correct lock information
2504       oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2505     }
2506 
2507     if (info->_oop_map == nullptr) {
2508       info->_oop_map = oop_map;
2509     } else {
2510       // a CodeEmitInfo can not be shared between different LIR-instructions
2511       // because interval splitting can occur anywhere between two instructions
2512       // and so the oop maps must be different
2513       // -> check if the already set oop_map is exactly the one calculated for this operation
2514       assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2515     }
2516   }
2517 }
2518 
2519 
2520 // frequently used constants
2521 // Allocate them with new so they are never destroyed (otherwise, a
2522 // forced exit could destroy these objects while they are still in
2523 // use).
2524 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (mtCompiler) ConstantOopWriteValue(nullptr);
2525 ConstantIntValue*      LinearScan::_int_m1_scope_value = new (mtCompiler) ConstantIntValue(-1);
2526 ConstantIntValue*      LinearScan::_int_0_scope_value =  new (mtCompiler) ConstantIntValue((jint)0);
2527 ConstantIntValue*      LinearScan::_int_1_scope_value =  new (mtCompiler) ConstantIntValue(1);
2528 ConstantIntValue*      LinearScan::_int_2_scope_value =  new (mtCompiler) ConstantIntValue(2);
2529 LocationValue*         _illegal_value = new (mtCompiler) LocationValue(Location());
2530 
2531 void LinearScan::init_compute_debug_info() {
2532   // cache for frequently used scope values
2533   // (cpu registers and stack slots)
2534   int cache_size = (LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2;
2535   _scope_value_cache = ScopeValueArray(cache_size, cache_size, nullptr);
2536 }
2537 
2538 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2539   Location loc;
2540   if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2541     bailout("too large frame");
2542   }
2543   ScopeValue* object_scope_value = new LocationValue(loc);
2544 
2545   if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2546     bailout("too large frame");
2547   }
2548   return new MonitorValue(object_scope_value, loc);
2549 }
2550 
2551 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2552   Location loc;
2553   if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2554     bailout("too large frame");
2555   }
2556   return new LocationValue(loc);
2557 }
2558 
2559 
2560 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2561   assert(opr->is_constant(), "should not be called otherwise");
2562 
2563   LIR_Const* c = opr->as_constant_ptr();
2564   BasicType t = c->type();
2565   switch (t) {
2566     case T_OBJECT: {
2567       jobject value = c->as_jobject();
2568       if (value == nullptr) {
2569         scope_values->append(_oop_null_scope_value);
2570       } else {
2571         scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2572       }
2573       return 1;
2574     }
2575 
2576     case T_INT: // fall through
2577     case T_FLOAT: {
2578       int value = c->as_jint_bits();
2579       switch (value) {
2580         case -1: scope_values->append(_int_m1_scope_value); break;
2581         case 0:  scope_values->append(_int_0_scope_value); break;
2582         case 1:  scope_values->append(_int_1_scope_value); break;
2583         case 2:  scope_values->append(_int_2_scope_value); break;
2584         default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2585       }
2586       return 1;
2587     }
2588 
2589     case T_LONG: // fall through
2590     case T_DOUBLE: {
2591 #ifdef _LP64
2592       scope_values->append(_int_0_scope_value);
2593       scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2594 #else
2595       if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2596         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2597         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2598       } else {
2599         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2600         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2601       }
2602 #endif
2603       return 2;
2604     }
2605 
2606     case T_ADDRESS: {
2607 #ifdef _LP64
2608       scope_values->append(new ConstantLongValue(c->as_jint()));
2609 #else
2610       scope_values->append(new ConstantIntValue(c->as_jint()));
2611 #endif
2612       return 1;
2613     }
2614 
2615     default:
2616       ShouldNotReachHere();
2617       return -1;
2618   }
2619 }
2620 
2621 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2622   if (opr->is_single_stack()) {
2623     int stack_idx = opr->single_stack_ix();
2624     bool is_oop = opr->is_oop_register();
2625     int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2626 
2627     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2628     if (sv == nullptr) {
2629       Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2630       sv = location_for_name(stack_idx, loc_type);
2631       _scope_value_cache.at_put(cache_idx, sv);
2632     }
2633 
2634     // check if cached value is correct
2635     DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2636 
2637     scope_values->append(sv);
2638     return 1;
2639 
2640   } else if (opr->is_single_cpu()) {
2641     bool is_oop = opr->is_oop_register();
2642     int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2643     Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2644 
2645     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2646     if (sv == nullptr) {
2647       Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2648       VMReg rname = frame_map()->regname(opr);
2649       sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2650       _scope_value_cache.at_put(cache_idx, sv);
2651     }
2652 
2653     // check if cached value is correct
2654     DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2655 
2656     scope_values->append(sv);
2657     return 1;
2658 
2659 #ifdef X86
2660   } else if (opr->is_single_xmm()) {
2661     VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2662     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2663 
2664     scope_values->append(sv);
2665     return 1;
2666 #endif
2667 
2668   } else if (opr->is_single_fpu()) {
2669 #ifdef IA32
2670     // the exact location of fpu stack values is only known
2671     // during fpu stack allocation, so the stack allocator object
2672     // must be present
2673     assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2674     assert(_fpu_stack_allocator != nullptr, "must be present");
2675     opr = _fpu_stack_allocator->to_fpu_stack(opr);
2676 #elif defined(AMD64)
2677     assert(false, "FPU not used on x86-64");
2678 #endif
2679 
2680     Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2681     VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2682 #ifndef __SOFTFP__
2683 #ifndef VM_LITTLE_ENDIAN
2684     // On S390 a (single precision) float value occupies only the high
2685     // word of the full double register. So when the double register is
2686     // stored to memory (e.g. by the RegisterSaver), then the float value
2687     // is found at offset 0. I.e. the code below is not needed on S390.
2688 #ifndef S390
2689     if (! float_saved_as_double) {
2690       // On big endian system, we may have an issue if float registers use only
2691       // the low half of the (same) double registers.
2692       // Both the float and the double could have the same regnr but would correspond
2693       // to two different addresses once saved.
2694 
2695       // get next safely (no assertion checks)
2696       VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2697       if (next->is_reg() &&
2698           (next->as_FloatRegister() == rname->as_FloatRegister())) {
2699         // the back-end does use the same numbering for the double and the float
2700         rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2701       }
2702     }
2703 #endif // !S390
2704 #endif
2705 #endif
2706     LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2707 
2708     scope_values->append(sv);
2709     return 1;
2710 
2711   } else {
2712     // double-size operands
2713 
2714     ScopeValue* first;
2715     ScopeValue* second;
2716 
2717     if (opr->is_double_stack()) {
2718 #ifdef _LP64
2719       Location loc1;
2720       Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2721       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, nullptr)) {
2722         bailout("too large frame");
2723       }
2724 
2725       first =  new LocationValue(loc1);
2726       second = _int_0_scope_value;
2727 #else
2728       Location loc1, loc2;
2729       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2730         bailout("too large frame");
2731       }
2732       first =  new LocationValue(loc1);
2733       second = new LocationValue(loc2);
2734 #endif // _LP64
2735 
2736     } else if (opr->is_double_cpu()) {
2737 #ifdef _LP64
2738       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2739       first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2740       second = _int_0_scope_value;
2741 #else
2742       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2743       VMReg rname_second = opr->as_register_hi()->as_VMReg();
2744 
2745       if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2746         // lo/hi and swapped relative to first and second, so swap them
2747         VMReg tmp = rname_first;
2748         rname_first = rname_second;
2749         rname_second = tmp;
2750       }
2751 
2752       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2753       second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2754 #endif //_LP64
2755 
2756 
2757 #ifdef X86
2758     } else if (opr->is_double_xmm()) {
2759       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2760       VMReg rname_first  = opr->as_xmm_double_reg()->as_VMReg();
2761 #  ifdef _LP64
2762       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2763       second = _int_0_scope_value;
2764 #  else
2765       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2766       // %%% This is probably a waste but we'll keep things as they were for now
2767       if (true) {
2768         VMReg rname_second = rname_first->next();
2769         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2770       }
2771 #  endif
2772 #endif
2773 
2774     } else if (opr->is_double_fpu()) {
2775       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2776       // the double as float registers in the native ordering. On X86,
2777       // fpu_regnrLo is a FPU stack slot whose VMReg represents
2778       // the low-order word of the double and fpu_regnrLo + 1 is the
2779       // name for the other half.  *first and *second must represent the
2780       // least and most significant words, respectively.
2781 
2782 #ifdef IA32
2783       // the exact location of fpu stack values is only known
2784       // during fpu stack allocation, so the stack allocator object
2785       // must be present
2786       assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2787       assert(_fpu_stack_allocator != nullptr, "must be present");
2788       opr = _fpu_stack_allocator->to_fpu_stack(opr);
2789 
2790       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2791 #endif
2792 #ifdef AMD64
2793       assert(false, "FPU not used on x86-64");
2794 #endif
2795 #ifdef ARM32
2796       assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2797 #endif
2798 
2799 #ifdef VM_LITTLE_ENDIAN
2800       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2801 #else
2802       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2803 #endif
2804 
2805 #ifdef _LP64
2806       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2807       second = _int_0_scope_value;
2808 #else
2809       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2810       // %%% This is probably a waste but we'll keep things as they were for now
2811       if (true) {
2812         VMReg rname_second = rname_first->next();
2813         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2814       }
2815 #endif
2816 
2817     } else {
2818       ShouldNotReachHere();
2819       first = nullptr;
2820       second = nullptr;
2821     }
2822 
2823     assert(first != nullptr && second != nullptr, "must be set");
2824     // The convention the interpreter uses is that the second local
2825     // holds the first raw word of the native double representation.
2826     // This is actually reasonable, since locals and stack arrays
2827     // grow downwards in all implementations.
2828     // (If, on some machine, the interpreter's Java locals or stack
2829     // were to grow upwards, the embedded doubles would be word-swapped.)
2830     scope_values->append(second);
2831     scope_values->append(first);
2832     return 2;
2833   }
2834 }
2835 
2836 
2837 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2838   if (value != nullptr) {
2839     LIR_Opr opr = value->operand();
2840     Constant* con = value->as_Constant();
2841 
2842     assert(con == nullptr || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "assumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2843     assert(con != nullptr || opr->is_virtual(), "assumption: non-Constant instructions have only virtual operands");
2844 
2845     if (con != nullptr && !con->is_pinned() && !opr->is_constant()) {
2846       // Unpinned constants may have a virtual operand for a part of the lifetime
2847       // or may be illegal when it was optimized away,
2848       // so always use a constant operand
2849       opr = LIR_OprFact::value_type(con->type());
2850     }
2851     assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2852 
2853     if (opr->is_virtual()) {
2854       LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2855 
2856       BlockBegin* block = block_of_op_with_id(op_id);
2857       if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2858         // generating debug information for the last instruction of a block.
2859         // if this instruction is a branch, spill moves are inserted before this branch
2860         // and so the wrong operand would be returned (spill moves at block boundaries are not
2861         // considered in the live ranges of intervals)
2862         // Solution: use the first op_id of the branch target block instead.
2863         if (block->lir()->instructions_list()->last()->as_OpBranch() != nullptr) {
2864           if (block->live_out().at(opr->vreg_number())) {
2865             op_id = block->sux_at(0)->first_lir_instruction_id();
2866             mode = LIR_OpVisitState::outputMode;
2867           }
2868         }
2869       }
2870 
2871       // Get current location of operand
2872       // The operand must be live because debug information is considered when building the intervals
2873       // if the interval is not live, color_lir_opr will cause an assertion failure
2874       opr = color_lir_opr(opr, op_id, mode);
2875       assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2876 
2877       // Append to ScopeValue array
2878       return append_scope_value_for_operand(opr, scope_values);
2879 
2880     } else {
2881       assert(value->as_Constant() != nullptr, "all other instructions have only virtual operands");
2882       assert(opr->is_constant(), "operand must be constant");
2883 
2884       return append_scope_value_for_constant(opr, scope_values);
2885     }
2886   } else {
2887     // append a dummy value because real value not needed
2888     scope_values->append(_illegal_value);
2889     return 1;
2890   }
2891 }
2892 
2893 
2894 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2895   IRScopeDebugInfo* caller_debug_info = nullptr;
2896 
2897   ValueStack* caller_state = cur_state->caller_state();
2898   if (caller_state != nullptr) {
2899     // process recursively to compute outermost scope first
2900     caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2901   }
2902 
2903   // initialize these to null.
2904   // If we don't need deopt info or there are no locals, expressions or monitors,
2905   // then these get recorded as no information and avoids the allocation of 0 length arrays.
2906   GrowableArray<ScopeValue*>*   locals      = nullptr;
2907   GrowableArray<ScopeValue*>*   expressions = nullptr;
2908   GrowableArray<MonitorValue*>* monitors    = nullptr;
2909 
2910   // describe local variable values
2911   int nof_locals = cur_state->locals_size();
2912   if (nof_locals > 0) {
2913     locals = new GrowableArray<ScopeValue*>(nof_locals);
2914 
2915     int pos = 0;
2916     while (pos < nof_locals) {
2917       assert(pos < cur_state->locals_size(), "why not?");
2918 
2919       Value local = cur_state->local_at(pos);
2920       pos += append_scope_value(op_id, local, locals);
2921 
2922       assert(locals->length() == pos, "must match");
2923     }
2924     assert(locals->length() == nof_locals, "wrong number of locals");
2925   }
2926   assert(nof_locals == cur_scope->method()->max_locals(), "wrong number of locals");
2927   assert(nof_locals == cur_state->locals_size(), "wrong number of locals");
2928 
2929   // describe expression stack
2930   int nof_stack = cur_state->stack_size();
2931   if (nof_stack > 0) {
2932     expressions = new GrowableArray<ScopeValue*>(nof_stack);
2933 
2934     int pos = 0;
2935     while (pos < nof_stack) {
2936       Value expression = cur_state->stack_at(pos);
2937       pos += append_scope_value(op_id, expression, expressions);
2938 
2939       assert(expressions->length() == pos, "must match");
2940     }
2941     assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2942   }
2943 
2944   // describe monitors
2945   int nof_locks = cur_state->locks_size();
2946   if (nof_locks > 0) {
2947     int lock_offset = cur_state->caller_state() != nullptr ? cur_state->caller_state()->total_locks_size() : 0;
2948     monitors = new GrowableArray<MonitorValue*>(nof_locks);
2949     for (int i = 0; i < nof_locks; i++) {
2950       monitors->append(location_for_monitor_index(lock_offset + i));
2951     }
2952   }
2953 
2954   return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
2955 }
2956 
2957 
2958 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2959   TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2960 
2961   IRScope* innermost_scope = info->scope();
2962   ValueStack* innermost_state = info->stack();
2963 
2964   assert(innermost_scope != nullptr && innermost_state != nullptr, "why is it missing?");
2965 
2966   DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2967 
2968   if (info->_scope_debug_info == nullptr) {
2969     // compute debug information
2970     info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2971   } else {
2972     // debug information already set. Check that it is correct from the current point of view
2973     DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2974   }
2975 }
2976 
2977 
2978 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2979   LIR_OpVisitState visitor;
2980   int num_inst = instructions->length();
2981   bool has_dead = false;
2982 
2983   for (int j = 0; j < num_inst; j++) {
2984     LIR_Op* op = instructions->at(j);
2985     if (op == nullptr) { // this can happen when spill-moves are removed in eliminate_spill_moves
2986       has_dead = true;
2987       continue;
2988     }
2989     int op_id = op->id();
2990 
2991     // visit instruction to get list of operands
2992     visitor.visit(op);
2993 
2994     // iterate all modes of the visitor and process all virtual operands
2995     for_each_visitor_mode(mode) {
2996       int n = visitor.opr_count(mode);
2997       for (int k = 0; k < n; k++) {
2998         LIR_Opr opr = visitor.opr_at(mode, k);
2999         if (opr->is_virtual_register()) {
3000           visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
3001         }
3002       }
3003     }
3004 
3005     if (visitor.info_count() > 0) {
3006       // exception handling
3007       if (compilation()->has_exception_handlers()) {
3008         XHandlers* xhandlers = visitor.all_xhandler();
3009         int n = xhandlers->length();
3010         for (int k = 0; k < n; k++) {
3011           XHandler* handler = xhandlers->handler_at(k);
3012           if (handler->entry_code() != nullptr) {
3013             assign_reg_num(handler->entry_code()->instructions_list(), nullptr);
3014           }
3015         }
3016       } else {
3017         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
3018       }
3019 
3020       // compute oop map
3021       assert(iw != nullptr, "needed for compute_oop_map");
3022       compute_oop_map(iw, visitor, op);
3023 
3024       // compute debug information
3025       if (!use_fpu_stack_allocation()) {
3026         // compute debug information if fpu stack allocation is not needed.
3027         // when fpu stack allocation is needed, the debug information can not
3028         // be computed here because the exact location of fpu operands is not known
3029         // -> debug information is created inside the fpu stack allocator
3030         int n = visitor.info_count();
3031         for (int k = 0; k < n; k++) {
3032           compute_debug_info(visitor.info_at(k), op_id);
3033         }
3034       }
3035     }
3036 
3037 #ifdef ASSERT
3038     // make sure we haven't made the op invalid.
3039     op->verify();
3040 #endif
3041 
3042     // remove useless moves
3043     if (op->code() == lir_move) {
3044       assert(op->as_Op1() != nullptr, "move must be LIR_Op1");
3045       LIR_Op1* move = (LIR_Op1*)op;
3046       LIR_Opr src = move->in_opr();
3047       LIR_Opr dst = move->result_opr();
3048       if (dst == src ||
3049           (!dst->is_pointer() && !src->is_pointer() &&
3050            src->is_same_register(dst))) {
3051         instructions->at_put(j, nullptr);
3052         has_dead = true;
3053       }
3054     }
3055   }
3056 
3057   if (has_dead) {
3058     // iterate all instructions of the block and remove all null-values.
3059     int insert_point = 0;
3060     for (int j = 0; j < num_inst; j++) {
3061       LIR_Op* op = instructions->at(j);
3062       if (op != nullptr) {
3063         if (insert_point != j) {
3064           instructions->at_put(insert_point, op);
3065         }
3066         insert_point++;
3067       }
3068     }
3069     instructions->trunc_to(insert_point);
3070   }
3071 }
3072 
3073 void LinearScan::assign_reg_num() {
3074   TIME_LINEAR_SCAN(timer_assign_reg_num);
3075 
3076   init_compute_debug_info();
3077   IntervalWalker* iw = init_compute_oop_maps();
3078 
3079   int num_blocks = block_count();
3080   for (int i = 0; i < num_blocks; i++) {
3081     BlockBegin* block = block_at(i);
3082     assign_reg_num(block->lir()->instructions_list(), iw);
3083   }
3084 }
3085 
3086 
3087 void LinearScan::do_linear_scan() {
3088   NOT_PRODUCT(_total_timer.begin_method());
3089 
3090   number_instructions();
3091 
3092   NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3093 
3094   compute_local_live_sets();
3095   compute_global_live_sets();
3096   CHECK_BAILOUT();
3097 
3098   build_intervals();
3099   CHECK_BAILOUT();
3100   sort_intervals_before_allocation();
3101 
3102   NOT_PRODUCT(print_intervals("Before Register Allocation"));
3103   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3104 
3105   allocate_registers();
3106   CHECK_BAILOUT();
3107 
3108   resolve_data_flow();
3109   if (compilation()->has_exception_handlers()) {
3110     resolve_exception_handlers();
3111   }
3112   // fill in number of spill slots into frame_map
3113   propagate_spill_slots();
3114   CHECK_BAILOUT();
3115 
3116   NOT_PRODUCT(print_intervals("After Register Allocation"));
3117   NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3118 
3119   sort_intervals_after_allocation();
3120 
3121   DEBUG_ONLY(verify());
3122 
3123   eliminate_spill_moves();
3124   assign_reg_num();
3125   CHECK_BAILOUT();
3126 
3127   NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3128   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3129 
3130   { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3131 
3132     if (use_fpu_stack_allocation()) {
3133       allocate_fpu_stack(); // Only has effect on Intel
3134       NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3135     }
3136   }
3137 
3138 #ifndef RISCV
3139   // Disable these optimizations on riscv temporarily, because it does not
3140   // work when the comparison operands are bound to branches or cmoves.
3141   { TIME_LINEAR_SCAN(timer_optimize_lir);
3142 
3143     EdgeMoveOptimizer::optimize(ir()->code());
3144     ControlFlowOptimizer::optimize(ir()->code());
3145     // check that cfg is still correct after optimizations
3146     ir()->verify();
3147   }
3148 #endif
3149 
3150   NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3151   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3152   NOT_PRODUCT(_total_timer.end_method(this));
3153 }
3154 
3155 
3156 // ********** Printing functions
3157 
3158 #ifndef PRODUCT
3159 
3160 void LinearScan::print_timers(double total) {
3161   _total_timer.print(total);
3162 }
3163 
3164 void LinearScan::print_statistics() {
3165   _stat_before_alloc.print("before allocation");
3166   _stat_after_asign.print("after assignment of register");
3167   _stat_final.print("after optimization");
3168 }
3169 
3170 void LinearScan::print_bitmap(BitMap& b) {
3171   for (unsigned int i = 0; i < b.size(); i++) {
3172     if (b.at(i)) tty->print("%d ", i);
3173   }
3174   tty->cr();
3175 }
3176 
3177 void LinearScan::print_intervals(const char* label) {
3178   if (TraceLinearScanLevel >= 1) {
3179     int i;
3180     tty->cr();
3181     tty->print_cr("%s", label);
3182 
3183     for (i = 0; i < interval_count(); i++) {
3184       Interval* interval = interval_at(i);
3185       if (interval != nullptr) {
3186         interval->print();
3187       }
3188     }
3189 
3190     tty->cr();
3191     tty->print_cr("--- Basic Blocks ---");
3192     for (i = 0; i < block_count(); i++) {
3193       BlockBegin* block = block_at(i);
3194       tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3195     }
3196     tty->cr();
3197     tty->cr();
3198   }
3199 
3200   if (PrintCFGToFile) {
3201     CFGPrinter::print_intervals(&_intervals, label);
3202   }
3203 }
3204 
3205 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3206   if (TraceLinearScanLevel >= level) {
3207     tty->cr();
3208     tty->print_cr("%s", label);
3209     print_LIR(ir()->linear_scan_order());
3210     tty->cr();
3211   }
3212 
3213   if (level == 1 && PrintCFGToFile) {
3214     CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3215   }
3216 }
3217 
3218 void LinearScan::print_reg_num(outputStream* out, int reg_num) {
3219   if (reg_num == -1) {
3220     out->print("[ANY]");
3221     return;
3222   } else if (reg_num >= LIR_Opr::vreg_base) {
3223     out->print("[VREG %d]", reg_num);
3224     return;
3225   }
3226 
3227   LIR_Opr opr = get_operand(reg_num);
3228   assert(opr->is_valid(), "unknown register");
3229   opr->print(out);
3230 }
3231 
3232 LIR_Opr LinearScan::get_operand(int reg_num) {
3233   LIR_Opr opr = LIR_OprFact::illegal();
3234 
3235 #ifdef X86
3236   int last_xmm_reg = pd_last_xmm_reg;
3237 #ifdef _LP64
3238   if (UseAVX < 3) {
3239     last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
3240   }
3241 #endif
3242 #endif
3243   if (reg_num >= pd_first_cpu_reg && reg_num <= pd_last_cpu_reg) {
3244     opr = LIR_OprFact::single_cpu(reg_num);
3245   } else if (reg_num >= pd_first_fpu_reg && reg_num <= pd_last_fpu_reg) {
3246     opr = LIR_OprFact::single_fpu(reg_num - pd_first_fpu_reg);
3247 #ifdef X86
3248   } else if (reg_num >= pd_first_xmm_reg && reg_num <= last_xmm_reg) {
3249     opr = LIR_OprFact::single_xmm(reg_num - pd_first_xmm_reg);
3250 #endif
3251   } else {
3252     // reg_num == -1 or a virtual register, return the illegal operand
3253   }
3254   return opr;
3255 }
3256 
3257 Interval* LinearScan::find_interval_at(int reg_num) const {
3258   if (reg_num < 0 || reg_num >= _intervals.length()) {
3259     return nullptr;
3260   }
3261   return interval_at(reg_num);
3262 }
3263 
3264 #endif // PRODUCT
3265 
3266 
3267 // ********** verification functions for allocation
3268 // (check that all intervals have a correct register and that no registers are overwritten)
3269 #ifdef ASSERT
3270 
3271 void LinearScan::verify() {
3272   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3273   verify_intervals();
3274 
3275   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3276   verify_no_oops_in_fixed_intervals();
3277 
3278   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3279   verify_constants();
3280 
3281   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3282   verify_registers();
3283 
3284   TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3285 }
3286 
3287 void LinearScan::verify_intervals() {
3288   int len = interval_count();
3289   bool has_error = false;
3290 
3291   for (int i = 0; i < len; i++) {
3292     Interval* i1 = interval_at(i);
3293     if (i1 == nullptr) continue;
3294 
3295     i1->check_split_children();
3296 
3297     if (i1->reg_num() != i) {
3298       tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3299       has_error = true;
3300     }
3301 
3302     if (i1->reg_num() >= LIR_Opr::vreg_base && i1->type() == T_ILLEGAL) {
3303       tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3304       has_error = true;
3305     }
3306 
3307     if (i1->assigned_reg() == any_reg) {
3308       tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3309       has_error = true;
3310     }
3311 
3312     if (i1->assigned_reg() == i1->assigned_regHi()) {
3313       tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3314       has_error = true;
3315     }
3316 
3317     if (!is_processed_reg_num(i1->assigned_reg())) {
3318       tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3319       has_error = true;
3320     }
3321 
3322     // special intervals that are created in MoveResolver
3323     // -> ignore them because the range information has no meaning there
3324     if (i1->from() == 1 && i1->to() == 2) continue;
3325 
3326     if (i1->first() == Range::end()) {
3327       tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3328       has_error = true;
3329     }
3330 
3331     for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3332       if (r->from() >= r->to()) {
3333         tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3334         has_error = true;
3335       }
3336     }
3337 
3338     for (int j = i + 1; j < len; j++) {
3339       Interval* i2 = interval_at(j);
3340       if (i2 == nullptr || (i2->from() == 1 && i2->to() == 2)) continue;
3341 
3342       int r1 = i1->assigned_reg();
3343       int r1Hi = i1->assigned_regHi();
3344       int r2 = i2->assigned_reg();
3345       int r2Hi = i2->assigned_regHi();
3346       if ((r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi))) && i1->intersects(i2)) {
3347         tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3348         i1->print(); tty->cr();
3349         i2->print(); tty->cr();
3350         has_error = true;
3351       }
3352     }
3353   }
3354 
3355   assert(has_error == false, "register allocation invalid");
3356 }
3357 
3358 
3359 void LinearScan::verify_no_oops_in_fixed_intervals() {
3360   Interval* fixed_intervals;
3361   Interval* other_intervals;
3362   create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, nullptr);
3363 
3364   // to ensure a walking until the last instruction id, add a dummy interval
3365   // with a high operation id
3366   other_intervals = new Interval(any_reg);
3367   other_intervals->add_range(max_jint - 2, max_jint - 1);
3368   IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3369 
3370   LIR_OpVisitState visitor;
3371   for (int i = 0; i < block_count(); i++) {
3372     BlockBegin* block = block_at(i);
3373 
3374     LIR_OpList* instructions = block->lir()->instructions_list();
3375 
3376     for (int j = 0; j < instructions->length(); j++) {
3377       LIR_Op* op = instructions->at(j);
3378       int op_id = op->id();
3379 
3380       visitor.visit(op);
3381 
3382       if (visitor.info_count() > 0) {
3383         iw->walk_before(op->id());
3384         bool check_live = true;
3385         if (op->code() == lir_move) {
3386           LIR_Op1* move = (LIR_Op1*)op;
3387           check_live = (move->patch_code() == lir_patch_none);
3388         }
3389         LIR_OpBranch* branch = op->as_OpBranch();
3390         if (branch != nullptr && branch->stub() != nullptr && branch->stub()->is_exception_throw_stub()) {
3391           // Don't bother checking the stub in this case since the
3392           // exception stub will never return to normal control flow.
3393           check_live = false;
3394         }
3395 
3396         // Make sure none of the fixed registers is live across an
3397         // oopmap since we can't handle that correctly.
3398         if (check_live) {
3399           for (Interval* interval = iw->active_first(fixedKind);
3400                interval != Interval::end();
3401                interval = interval->next()) {
3402             if (interval->current_to() > op->id() + 1) {
3403               // This interval is live out of this op so make sure
3404               // that this interval represents some value that's
3405               // referenced by this op either as an input or output.
3406               bool ok = false;
3407               for_each_visitor_mode(mode) {
3408                 int n = visitor.opr_count(mode);
3409                 for (int k = 0; k < n; k++) {
3410                   LIR_Opr opr = visitor.opr_at(mode, k);
3411                   if (opr->is_fixed_cpu()) {
3412                     if (interval_at(reg_num(opr)) == interval) {
3413                       ok = true;
3414                       break;
3415                     }
3416                     int hi = reg_numHi(opr);
3417                     if (hi != -1 && interval_at(hi) == interval) {
3418                       ok = true;
3419                       break;
3420                     }
3421                   }
3422                 }
3423               }
3424               assert(ok, "fixed intervals should never be live across an oopmap point");
3425             }
3426           }
3427         }
3428       }
3429 
3430       // oop-maps at calls do not contain registers, so check is not needed
3431       if (!visitor.has_call()) {
3432 
3433         for_each_visitor_mode(mode) {
3434           int n = visitor.opr_count(mode);
3435           for (int k = 0; k < n; k++) {
3436             LIR_Opr opr = visitor.opr_at(mode, k);
3437 
3438             if (opr->is_fixed_cpu() && opr->is_oop()) {
3439               // operand is a non-virtual cpu register and contains an oop
3440               TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3441 
3442               Interval* interval = interval_at(reg_num(opr));
3443               assert(interval != nullptr, "no interval");
3444 
3445               if (mode == LIR_OpVisitState::inputMode) {
3446                 if (interval->to() >= op_id + 1) {
3447                   assert(interval->to() < op_id + 2 ||
3448                          interval->has_hole_between(op_id, op_id + 2),
3449                          "oop input operand live after instruction");
3450                 }
3451               } else if (mode == LIR_OpVisitState::outputMode) {
3452                 if (interval->from() <= op_id - 1) {
3453                   assert(interval->has_hole_between(op_id - 1, op_id),
3454                          "oop input operand live after instruction");
3455                 }
3456               }
3457             }
3458           }
3459         }
3460       }
3461     }
3462   }
3463 }
3464 
3465 
3466 void LinearScan::verify_constants() {
3467   int num_regs = num_virtual_regs();
3468   int size = live_set_size();
3469   int num_blocks = block_count();
3470 
3471   for (int i = 0; i < num_blocks; i++) {
3472     BlockBegin* block = block_at(i);
3473     ResourceBitMap& live_at_edge = block->live_in();
3474 
3475     // visit all registers where the live_at_edge bit is set
3476     auto visitor = [&](BitMap::idx_t index) {
3477       int r = static_cast<int>(index);
3478       TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3479 
3480       Value value = gen()->instruction_for_vreg(r);
3481 
3482       assert(value != nullptr, "all intervals live across block boundaries must have Value");
3483       assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3484       assert(value->operand()->vreg_number() == r, "register number must match");
3485       // TKR assert(value->as_Constant() == nullptr || value->is_pinned(), "only pinned constants can be alive across block boundaries");
3486     };
3487     live_at_edge.iterate(visitor, 0, size);
3488   }
3489 }
3490 
3491 
3492 class RegisterVerifier: public StackObj {
3493  private:
3494   LinearScan*   _allocator;
3495   BlockList     _work_list;      // all blocks that must be processed
3496   IntervalsList _saved_states;   // saved information of previous check
3497 
3498   // simplified access to methods of LinearScan
3499   Compilation*  compilation() const              { return _allocator->compilation(); }
3500   Interval*     interval_at(int reg_num) const   { return _allocator->interval_at(reg_num); }
3501   int           reg_num(LIR_Opr opr) const       { return _allocator->reg_num(opr); }
3502 
3503   // currently, only registers are processed
3504   int           state_size()                     { return LinearScan::nof_regs; }
3505 
3506   // accessors
3507   IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3508   void          set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3509   void          add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3510 
3511   // helper functions
3512   IntervalList* copy(IntervalList* input_state);
3513   void          state_put(IntervalList* input_state, int reg, Interval* interval);
3514   bool          check_state(IntervalList* input_state, int reg, Interval* interval);
3515 
3516   void process_block(BlockBegin* block);
3517   void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3518   void process_successor(BlockBegin* block, IntervalList* input_state);
3519   void process_operations(LIR_List* ops, IntervalList* input_state);
3520 
3521  public:
3522   RegisterVerifier(LinearScan* allocator)
3523     : _allocator(allocator)
3524     , _work_list(16)
3525     , _saved_states(BlockBegin::number_of_blocks(), BlockBegin::number_of_blocks(), nullptr)
3526   { }
3527 
3528   void verify(BlockBegin* start);
3529 };
3530 
3531 
3532 // entry function from LinearScan that starts the verification
3533 void LinearScan::verify_registers() {
3534   RegisterVerifier verifier(this);
3535   verifier.verify(block_at(0));
3536 }
3537 
3538 
3539 void RegisterVerifier::verify(BlockBegin* start) {
3540   // setup input registers (method arguments) for first block
3541   int input_state_len = state_size();
3542   IntervalList* input_state = new IntervalList(input_state_len, input_state_len, nullptr);
3543   CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3544   for (int n = 0; n < args->length(); n++) {
3545     LIR_Opr opr = args->at(n);
3546     if (opr->is_register()) {
3547       Interval* interval = interval_at(reg_num(opr));
3548 
3549       if (interval->assigned_reg() < state_size()) {
3550         input_state->at_put(interval->assigned_reg(), interval);
3551       }
3552       if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3553         input_state->at_put(interval->assigned_regHi(), interval);
3554       }
3555     }
3556   }
3557 
3558   set_state_for_block(start, input_state);
3559   add_to_work_list(start);
3560 
3561   // main loop for verification
3562   do {
3563     BlockBegin* block = _work_list.at(0);
3564     _work_list.remove_at(0);
3565 
3566     process_block(block);
3567   } while (!_work_list.is_empty());
3568 }
3569 
3570 void RegisterVerifier::process_block(BlockBegin* block) {
3571   TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3572 
3573   // must copy state because it is modified
3574   IntervalList* input_state = copy(state_for_block(block));
3575 
3576   if (TraceLinearScanLevel >= 4) {
3577     tty->print_cr("Input-State of intervals:");
3578     tty->print("    ");
3579     for (int i = 0; i < state_size(); i++) {
3580       if (input_state->at(i) != nullptr) {
3581         tty->print(" %4d", input_state->at(i)->reg_num());
3582       } else {
3583         tty->print("   __");
3584       }
3585     }
3586     tty->cr();
3587     tty->cr();
3588   }
3589 
3590   // process all operations of the block
3591   process_operations(block->lir(), input_state);
3592 
3593   // iterate all successors
3594   for (int i = 0; i < block->number_of_sux(); i++) {
3595     process_successor(block->sux_at(i), input_state);
3596   }
3597 }
3598 
3599 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3600   TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3601 
3602   // must copy state because it is modified
3603   input_state = copy(input_state);
3604 
3605   if (xhandler->entry_code() != nullptr) {
3606     process_operations(xhandler->entry_code(), input_state);
3607   }
3608   process_successor(xhandler->entry_block(), input_state);
3609 }
3610 
3611 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3612   IntervalList* saved_state = state_for_block(block);
3613 
3614   if (saved_state != nullptr) {
3615     // this block was already processed before.
3616     // check if new input_state is consistent with saved_state
3617 
3618     bool saved_state_correct = true;
3619     for (int i = 0; i < state_size(); i++) {
3620       if (input_state->at(i) != saved_state->at(i)) {
3621         // current input_state and previous saved_state assume a different
3622         // interval in this register -> assume that this register is invalid
3623         if (saved_state->at(i) != nullptr) {
3624           // invalidate old calculation only if it assumed that
3625           // register was valid. when the register was already invalid,
3626           // then the old calculation was correct.
3627           saved_state_correct = false;
3628           saved_state->at_put(i, nullptr);
3629 
3630           TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3631         }
3632       }
3633     }
3634 
3635     if (saved_state_correct) {
3636       // already processed block with correct input_state
3637       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3638     } else {
3639       // must re-visit this block
3640       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3641       add_to_work_list(block);
3642     }
3643 
3644   } else {
3645     // block was not processed before, so set initial input_state
3646     TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3647 
3648     set_state_for_block(block, copy(input_state));
3649     add_to_work_list(block);
3650   }
3651 }
3652 
3653 
3654 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3655   IntervalList* copy_state = new IntervalList(input_state->length());
3656   copy_state->appendAll(input_state);
3657   return copy_state;
3658 }
3659 
3660 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3661   if (reg != LinearScan::any_reg && reg < state_size()) {
3662     if (interval != nullptr) {
3663       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = %d", reg, interval->reg_num()));
3664     } else if (input_state->at(reg) != nullptr) {
3665       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = null", reg));
3666     }
3667 
3668     input_state->at_put(reg, interval);
3669   }
3670 }
3671 
3672 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3673   if (reg != LinearScan::any_reg && reg < state_size()) {
3674     if (input_state->at(reg) != interval) {
3675       tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3676       return true;
3677     }
3678   }
3679   return false;
3680 }
3681 
3682 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3683   // visit all instructions of the block
3684   LIR_OpVisitState visitor;
3685   bool has_error = false;
3686 
3687   for (int i = 0; i < ops->length(); i++) {
3688     LIR_Op* op = ops->at(i);
3689     visitor.visit(op);
3690 
3691     TRACE_LINEAR_SCAN(4, op->print_on(tty));
3692 
3693     // check if input operands are correct
3694     int j;
3695     int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3696     for (j = 0; j < n; j++) {
3697       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3698       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3699         Interval* interval = interval_at(reg_num(opr));
3700         if (op->id() != -1) {
3701           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3702         }
3703 
3704         has_error |= check_state(input_state, interval->assigned_reg(),   interval->split_parent());
3705         has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3706 
3707         // When an operand is marked with is_last_use, then the fpu stack allocator
3708         // removes the register from the fpu stack -> the register contains no value
3709         if (opr->is_last_use()) {
3710           state_put(input_state, interval->assigned_reg(),   nullptr);
3711           state_put(input_state, interval->assigned_regHi(), nullptr);
3712         }
3713       }
3714     }
3715 
3716     // invalidate all caller save registers at calls
3717     if (visitor.has_call()) {
3718       for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3719         state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), nullptr);
3720       }
3721       for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3722         state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), nullptr);
3723       }
3724 
3725 #ifdef X86
3726       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
3727       for (j = 0; j < num_caller_save_xmm_regs; j++) {
3728         state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), nullptr);
3729       }
3730 #endif
3731     }
3732 
3733     // process xhandler before output and temp operands
3734     XHandlers* xhandlers = visitor.all_xhandler();
3735     n = xhandlers->length();
3736     for (int k = 0; k < n; k++) {
3737       process_xhandler(xhandlers->handler_at(k), input_state);
3738     }
3739 
3740     // set temp operands (some operations use temp operands also as output operands, so can't set them null)
3741     n = visitor.opr_count(LIR_OpVisitState::tempMode);
3742     for (j = 0; j < n; j++) {
3743       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3744       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3745         Interval* interval = interval_at(reg_num(opr));
3746         if (op->id() != -1) {
3747           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3748         }
3749 
3750         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3751         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3752       }
3753     }
3754 
3755     // set output operands
3756     n = visitor.opr_count(LIR_OpVisitState::outputMode);
3757     for (j = 0; j < n; j++) {
3758       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3759       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3760         Interval* interval = interval_at(reg_num(opr));
3761         if (op->id() != -1) {
3762           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3763         }
3764 
3765         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3766         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3767       }
3768     }
3769   }
3770   assert(has_error == false, "Error in register allocation");
3771 }
3772 
3773 #endif // ASSERT
3774 
3775 
3776 
3777 // **** Implementation of MoveResolver ******************************
3778 
3779 MoveResolver::MoveResolver(LinearScan* allocator) :
3780   _allocator(allocator),
3781   _insert_list(nullptr),
3782   _insert_idx(-1),
3783   _insertion_buffer(),
3784   _mapping_from(8),
3785   _mapping_from_opr(8),
3786   _mapping_to(8),
3787   _multiple_reads_allowed(false)
3788 {
3789   for (int i = 0; i < LinearScan::nof_regs; i++) {
3790     _register_blocked[i] = 0;
3791   }
3792   DEBUG_ONLY(check_empty());
3793 }
3794 
3795 
3796 #ifdef ASSERT
3797 
3798 void MoveResolver::check_empty() {
3799   assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3800   for (int i = 0; i < LinearScan::nof_regs; i++) {
3801     assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3802   }
3803   assert(_multiple_reads_allowed == false, "must have default value");
3804 }
3805 
3806 void MoveResolver::verify_before_resolve() {
3807   assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3808   assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3809   assert(_insert_list != nullptr && _insert_idx != -1, "insert position not set");
3810 
3811   int i, j;
3812   if (!_multiple_reads_allowed) {
3813     for (i = 0; i < _mapping_from.length(); i++) {
3814       for (j = i + 1; j < _mapping_from.length(); j++) {
3815         assert(_mapping_from.at(i) == nullptr || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3816       }
3817     }
3818   }
3819 
3820   for (i = 0; i < _mapping_to.length(); i++) {
3821     for (j = i + 1; j < _mapping_to.length(); j++) {
3822       assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3823     }
3824   }
3825 
3826 
3827   ResourceBitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3828   if (!_multiple_reads_allowed) {
3829     for (i = 0; i < _mapping_from.length(); i++) {
3830       Interval* it = _mapping_from.at(i);
3831       if (it != nullptr) {
3832         assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3833         used_regs.set_bit(it->assigned_reg());
3834 
3835         if (it->assigned_regHi() != LinearScan::any_reg) {
3836           assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3837           used_regs.set_bit(it->assigned_regHi());
3838         }
3839       }
3840     }
3841   }
3842 
3843   used_regs.clear();
3844   for (i = 0; i < _mapping_to.length(); i++) {
3845     Interval* it = _mapping_to.at(i);
3846     assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3847     used_regs.set_bit(it->assigned_reg());
3848 
3849     if (it->assigned_regHi() != LinearScan::any_reg) {
3850       assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3851       used_regs.set_bit(it->assigned_regHi());
3852     }
3853   }
3854 
3855   used_regs.clear();
3856   for (i = 0; i < _mapping_from.length(); i++) {
3857     Interval* it = _mapping_from.at(i);
3858     if (it != nullptr && it->assigned_reg() >= LinearScan::nof_regs) {
3859       used_regs.set_bit(it->assigned_reg());
3860     }
3861   }
3862   for (i = 0; i < _mapping_to.length(); i++) {
3863     Interval* it = _mapping_to.at(i);
3864     assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3865   }
3866 }
3867 
3868 #endif // ASSERT
3869 
3870 
3871 // mark assigned_reg and assigned_regHi of the interval as blocked
3872 void MoveResolver::block_registers(Interval* it) {
3873   int reg = it->assigned_reg();
3874   if (reg < LinearScan::nof_regs) {
3875     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3876     set_register_blocked(reg, 1);
3877   }
3878   reg = it->assigned_regHi();
3879   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3880     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3881     set_register_blocked(reg, 1);
3882   }
3883 }
3884 
3885 // mark assigned_reg and assigned_regHi of the interval as unblocked
3886 void MoveResolver::unblock_registers(Interval* it) {
3887   int reg = it->assigned_reg();
3888   if (reg < LinearScan::nof_regs) {
3889     assert(register_blocked(reg) > 0, "register already marked as unused");
3890     set_register_blocked(reg, -1);
3891   }
3892   reg = it->assigned_regHi();
3893   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3894     assert(register_blocked(reg) > 0, "register already marked as unused");
3895     set_register_blocked(reg, -1);
3896   }
3897 }
3898 
3899 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3900 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3901   int from_reg = -1;
3902   int from_regHi = -1;
3903   if (from != nullptr) {
3904     from_reg = from->assigned_reg();
3905     from_regHi = from->assigned_regHi();
3906   }
3907 
3908   int reg = to->assigned_reg();
3909   if (reg < LinearScan::nof_regs) {
3910     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3911       return false;
3912     }
3913   }
3914   reg = to->assigned_regHi();
3915   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3916     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3917       return false;
3918     }
3919   }
3920 
3921   return true;
3922 }
3923 
3924 
3925 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3926   assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3927   _insertion_buffer.init(list);
3928 }
3929 
3930 void MoveResolver::append_insertion_buffer() {
3931   if (_insertion_buffer.initialized()) {
3932     _insertion_buffer.lir_list()->append(&_insertion_buffer);
3933   }
3934   assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3935 
3936   _insert_list = nullptr;
3937   _insert_idx = -1;
3938 }
3939 
3940 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3941   assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3942   assert(from_interval->type() == to_interval->type(), "move between different types");
3943   assert(_insert_list != nullptr && _insert_idx != -1, "must setup insert position first");
3944   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3945 
3946   LIR_Opr from_opr = get_virtual_register(from_interval);
3947   LIR_Opr to_opr = get_virtual_register(to_interval);
3948 
3949   if (!_multiple_reads_allowed) {
3950     // the last_use flag is an optimization for FPU stack allocation. When the same
3951     // input interval is used in more than one move, then it is too difficult to determine
3952     // if this move is really the last use.
3953     from_opr = from_opr->make_last_use();
3954   }
3955   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3956 
3957   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3958 }
3959 
3960 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3961   assert(from_opr->type() == to_interval->type(), "move between different types");
3962   assert(_insert_list != nullptr && _insert_idx != -1, "must setup insert position first");
3963   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3964 
3965   LIR_Opr to_opr = get_virtual_register(to_interval);
3966   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3967 
3968   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr("  to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3969 }
3970 
3971 LIR_Opr MoveResolver::get_virtual_register(Interval* interval) {
3972   // Add a little fudge factor for the bailout since the bailout is only checked periodically. This allows us to hand out
3973   // a few extra registers before we really run out which helps to avoid to trip over assertions.
3974   int reg_num = interval->reg_num();
3975   if (reg_num + 20 >= LIR_Opr::vreg_max) {
3976     _allocator->bailout("out of virtual registers in linear scan");
3977     if (reg_num + 2 >= LIR_Opr::vreg_max) {
3978       // Wrap it around and continue until bailout really happens to avoid hitting assertions.
3979       reg_num = LIR_Opr::vreg_base;
3980     }
3981   }
3982   LIR_Opr vreg = LIR_OprFact::virtual_register(reg_num, interval->type());
3983   assert(vreg != LIR_OprFact::illegal(), "ran out of virtual registers");
3984   return vreg;
3985 }
3986 
3987 void MoveResolver::resolve_mappings() {
3988   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != nullptr ? _insert_list->block()->block_id() : -1, _insert_idx));
3989   DEBUG_ONLY(verify_before_resolve());
3990 
3991   // Block all registers that are used as input operands of a move.
3992   // When a register is blocked, no move to this register is emitted.
3993   // This is necessary for detecting cycles in moves.
3994   int i;
3995   for (i = _mapping_from.length() - 1; i >= 0; i--) {
3996     Interval* from_interval = _mapping_from.at(i);
3997     if (from_interval != nullptr) {
3998       block_registers(from_interval);
3999     }
4000   }
4001 
4002   int spill_candidate = -1;
4003   while (_mapping_from.length() > 0) {
4004     bool processed_interval = false;
4005 
4006     for (i = _mapping_from.length() - 1; i >= 0; i--) {
4007       Interval* from_interval = _mapping_from.at(i);
4008       Interval* to_interval = _mapping_to.at(i);
4009 
4010       if (save_to_process_move(from_interval, to_interval)) {
4011         // this interval can be processed because target is free
4012         if (from_interval != nullptr) {
4013           insert_move(from_interval, to_interval);
4014           unblock_registers(from_interval);
4015         } else {
4016           insert_move(_mapping_from_opr.at(i), to_interval);
4017         }
4018         _mapping_from.remove_at(i);
4019         _mapping_from_opr.remove_at(i);
4020         _mapping_to.remove_at(i);
4021 
4022         processed_interval = true;
4023       } else if (from_interval != nullptr && from_interval->assigned_reg() < LinearScan::nof_regs) {
4024         // this interval cannot be processed now because target is not free
4025         // it starts in a register, so it is a possible candidate for spilling
4026         spill_candidate = i;
4027       }
4028     }
4029 
4030     if (!processed_interval) {
4031       // no move could be processed because there is a cycle in the move list
4032       // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
4033       guarantee(spill_candidate != -1, "no interval in register for spilling found");
4034 
4035       // create a new spill interval and assign a stack slot to it
4036       Interval* from_interval = _mapping_from.at(spill_candidate);
4037       Interval* spill_interval = new Interval(-1);
4038       spill_interval->set_type(from_interval->type());
4039 
4040       // add a dummy range because real position is difficult to calculate
4041       // Note: this range is a special case when the integrity of the allocation is checked
4042       spill_interval->add_range(1, 2);
4043 
4044       //       do not allocate a new spill slot for temporary interval, but
4045       //       use spill slot assigned to from_interval. Otherwise moves from
4046       //       one stack slot to another can happen (not allowed by LIR_Assembler
4047       int spill_slot = from_interval->canonical_spill_slot();
4048       if (spill_slot < 0) {
4049         spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
4050         from_interval->set_canonical_spill_slot(spill_slot);
4051       }
4052       spill_interval->assign_reg(spill_slot);
4053       allocator()->append_interval(spill_interval);
4054 
4055       TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
4056 
4057       // insert a move from register to stack and update the mapping
4058       insert_move(from_interval, spill_interval);
4059       _mapping_from.at_put(spill_candidate, spill_interval);
4060       unblock_registers(from_interval);
4061     }
4062   }
4063 
4064   // reset to default value
4065   _multiple_reads_allowed = false;
4066 
4067   // check that all intervals have been processed
4068   DEBUG_ONLY(check_empty());
4069 }
4070 
4071 
4072 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
4073   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != nullptr ? insert_list->block()->block_id() : -1, insert_idx));
4074   assert(_insert_list == nullptr && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
4075 
4076   create_insertion_buffer(insert_list);
4077   _insert_list = insert_list;
4078   _insert_idx = insert_idx;
4079 }
4080 
4081 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
4082   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != nullptr ? insert_list->block()->block_id() : -1, insert_idx));
4083 
4084   if (_insert_list != nullptr && (insert_list != _insert_list || insert_idx != _insert_idx)) {
4085     // insert position changed -> resolve current mappings
4086     resolve_mappings();
4087   }
4088 
4089   if (insert_list != _insert_list) {
4090     // block changed -> append insertion_buffer because it is
4091     // bound to a specific block and create a new insertion_buffer
4092     append_insertion_buffer();
4093     create_insertion_buffer(insert_list);
4094   }
4095 
4096   _insert_list = insert_list;
4097   _insert_idx = insert_idx;
4098 }
4099 
4100 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
4101   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4102 
4103   _mapping_from.append(from_interval);
4104   _mapping_from_opr.append(LIR_OprFact::illegalOpr);
4105   _mapping_to.append(to_interval);
4106 }
4107 
4108 
4109 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
4110   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4111   assert(from_opr->is_constant(), "only for constants");
4112 
4113   _mapping_from.append(nullptr);
4114   _mapping_from_opr.append(from_opr);
4115   _mapping_to.append(to_interval);
4116 }
4117 
4118 void MoveResolver::resolve_and_append_moves() {
4119   if (has_mappings()) {
4120     resolve_mappings();
4121   }
4122   append_insertion_buffer();
4123 }
4124 
4125 
4126 
4127 // **** Implementation of Range *************************************
4128 
4129 Range::Range(int from, int to, Range* next) :
4130   _from(from),
4131   _to(to),
4132   _next(next)
4133 {
4134 }
4135 
4136 // initialize sentinel
4137 Range* Range::_end = nullptr;
4138 void Range::initialize() {
4139   assert(_end == nullptr, "Range initialized more than once");
4140   alignas(Range) static uint8_t end_storage[sizeof(Range)];
4141   _end = ::new(static_cast<void*>(end_storage)) Range(max_jint, max_jint, nullptr);
4142 }
4143 
4144 int Range::intersects_at(Range* r2) const {
4145   const Range* r1 = this;
4146 
4147   assert(r1 != nullptr && r2 != nullptr, "null ranges not allowed");
4148   assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4149 
4150   do {
4151     if (r1->from() < r2->from()) {
4152       if (r1->to() <= r2->from()) {
4153         r1 = r1->next(); if (r1 == _end) return -1;
4154       } else {
4155         return r2->from();
4156       }
4157     } else if (r2->from() < r1->from()) {
4158       if (r2->to() <= r1->from()) {
4159         r2 = r2->next(); if (r2 == _end) return -1;
4160       } else {
4161         return r1->from();
4162       }
4163     } else { // r1->from() == r2->from()
4164       if (r1->from() == r1->to()) {
4165         r1 = r1->next(); if (r1 == _end) return -1;
4166       } else if (r2->from() == r2->to()) {
4167         r2 = r2->next(); if (r2 == _end) return -1;
4168       } else {
4169         return r1->from();
4170       }
4171     }
4172   } while (true);
4173 }
4174 
4175 #ifndef PRODUCT
4176 void Range::print(outputStream* out) const {
4177   out->print("[%d, %d[ ", _from, _to);
4178 }
4179 #endif
4180 
4181 
4182 
4183 // **** Implementation of Interval **********************************
4184 
4185 // initialize sentinel
4186 Interval* Interval::_end = nullptr;
4187 void Interval::initialize() {
4188   Range::initialize();
4189   assert(_end == nullptr, "Interval initialized more than once");
4190   alignas(Interval) static uint8_t end_storage[sizeof(Interval)];
4191   _end = ::new(static_cast<void*>(end_storage)) Interval(-1);
4192 }
4193 
4194 Interval::Interval(int reg_num) :
4195   _reg_num(reg_num),
4196   _type(T_ILLEGAL),
4197   _first(Range::end()),
4198   _use_pos_and_kinds(12),
4199   _current(Range::end()),
4200   _next(_end),
4201   _state(invalidState),
4202   _assigned_reg(LinearScan::any_reg),
4203   _assigned_regHi(LinearScan::any_reg),
4204   _cached_to(-1),
4205   _cached_opr(LIR_OprFact::illegalOpr),
4206   _cached_vm_reg(VMRegImpl::Bad()),
4207   _split_children(nullptr),
4208   _canonical_spill_slot(-1),
4209   _insert_move_when_activated(false),
4210   _spill_state(noDefinitionFound),
4211   _spill_definition_pos(-1),
4212   _register_hint(nullptr)
4213 {
4214   _split_parent = this;
4215   _current_split_child = this;
4216 }
4217 
4218 int Interval::calc_to() {
4219   assert(_first != Range::end(), "interval has no range");
4220 
4221   Range* r = _first;
4222   while (r->next() != Range::end()) {
4223     r = r->next();
4224   }
4225   return r->to();
4226 }
4227 
4228 
4229 #ifdef ASSERT
4230 // consistency check of split-children
4231 void Interval::check_split_children() {
4232   if (_split_children != nullptr && _split_children->length() > 0) {
4233     assert(is_split_parent(), "only split parents can have children");
4234 
4235     for (int i = 0; i < _split_children->length(); i++) {
4236       Interval* i1 = _split_children->at(i);
4237 
4238       assert(i1->split_parent() == this, "not a split child of this interval");
4239       assert(i1->type() == type(), "must be equal for all split children");
4240       assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4241 
4242       for (int j = i + 1; j < _split_children->length(); j++) {
4243         Interval* i2 = _split_children->at(j);
4244 
4245         assert(i1->reg_num() != i2->reg_num(), "same register number");
4246 
4247         if (i1->from() < i2->from()) {
4248           assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4249         } else {
4250           assert(i2->from() < i1->from(), "intervals start at same op_id");
4251           assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4252         }
4253       }
4254     }
4255   }
4256 }
4257 #endif // ASSERT
4258 
4259 Interval* Interval::register_hint(bool search_split_child) const {
4260   if (!search_split_child) {
4261     return _register_hint;
4262   }
4263 
4264   if (_register_hint != nullptr) {
4265     assert(_register_hint->is_split_parent(), "only split parents are valid hint registers");
4266 
4267     if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4268       return _register_hint;
4269 
4270     } else if (_register_hint->_split_children != nullptr && _register_hint->_split_children->length() > 0) {
4271       // search the first split child that has a register assigned
4272       int len = _register_hint->_split_children->length();
4273       for (int i = 0; i < len; i++) {
4274         Interval* cur = _register_hint->_split_children->at(i);
4275 
4276         if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4277           return cur;
4278         }
4279       }
4280     }
4281   }
4282 
4283   // no hint interval found that has a register assigned
4284   return nullptr;
4285 }
4286 
4287 
4288 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4289   assert(is_split_parent(), "can only be called for split parents");
4290   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4291 
4292   Interval* result;
4293   if (_split_children == nullptr || _split_children->length() == 0) {
4294     result = this;
4295   } else {
4296     result = nullptr;
4297     int len = _split_children->length();
4298 
4299     // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4300     int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4301 
4302     int i;
4303     for (i = 0; i < len; i++) {
4304       Interval* cur = _split_children->at(i);
4305       if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4306         if (i > 0) {
4307           // exchange current split child to start of list (faster access for next call)
4308           _split_children->at_put(i, _split_children->at(0));
4309           _split_children->at_put(0, cur);
4310         }
4311 
4312         // interval found
4313         result = cur;
4314         break;
4315       }
4316     }
4317 
4318 #ifdef ASSERT
4319     for (i = 0; i < len; i++) {
4320       Interval* tmp = _split_children->at(i);
4321       if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4322         tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4323         result->print();
4324         tmp->print();
4325         assert(false, "two valid result intervals found");
4326       }
4327     }
4328 #endif
4329   }
4330 
4331   assert(result != nullptr, "no matching interval found");
4332   assert(result->covers(op_id, mode), "op_id not covered by interval");
4333 
4334   return result;
4335 }
4336 
4337 
4338 // returns the last split child that ends before the given op_id
4339 Interval* Interval::split_child_before_op_id(int op_id) {
4340   assert(op_id >= 0, "invalid op_id");
4341 
4342   Interval* parent = split_parent();
4343   Interval* result = nullptr;
4344 
4345   assert(parent->_split_children != nullptr, "no split children available");
4346   int len = parent->_split_children->length();
4347   assert(len > 0, "no split children available");
4348 
4349   for (int i = len - 1; i >= 0; i--) {
4350     Interval* cur = parent->_split_children->at(i);
4351     if (cur->to() <= op_id && (result == nullptr || result->to() < cur->to())) {
4352       result = cur;
4353     }
4354   }
4355 
4356   assert(result != nullptr, "no split child found");
4357   return result;
4358 }
4359 
4360 
4361 // Note: use positions are sorted descending -> first use has highest index
4362 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4363   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4364 
4365   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4366     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4367       return _use_pos_and_kinds.at(i);
4368     }
4369   }
4370   return max_jint;
4371 }
4372 
4373 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4374   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4375 
4376   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4377     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4378       return _use_pos_and_kinds.at(i);
4379     }
4380   }
4381   return max_jint;
4382 }
4383 
4384 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4385   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4386 
4387   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4388     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4389       return _use_pos_and_kinds.at(i);
4390     }
4391   }
4392   return max_jint;
4393 }
4394 
4395 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4396   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4397 
4398   int prev = 0;
4399   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4400     if (_use_pos_and_kinds.at(i) > from) {
4401       return prev;
4402     }
4403     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4404       prev = _use_pos_and_kinds.at(i);
4405     }
4406   }
4407   return prev;
4408 }
4409 
4410 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4411   assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4412 
4413   // do not add use positions for precolored intervals because
4414   // they are never used
4415   if (use_kind != noUse && reg_num() >= LIR_Opr::vreg_base) {
4416 #ifdef ASSERT
4417     assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4418     for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4419       assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4420       assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4421       if (i > 0) {
4422         assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4423       }
4424     }
4425 #endif
4426 
4427     // Note: add_use is called in descending order, so list gets sorted
4428     //       automatically by just appending new use positions
4429     int len = _use_pos_and_kinds.length();
4430     if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4431       _use_pos_and_kinds.append(pos);
4432       _use_pos_and_kinds.append(use_kind);
4433     } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4434       assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4435       _use_pos_and_kinds.at_put(len - 1, use_kind);
4436     }
4437   }
4438 }
4439 
4440 void Interval::add_range(int from, int to) {
4441   assert(from < to, "invalid range");
4442   assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4443   assert(from <= first()->to(), "not inserting at begin of interval");
4444 
4445   if (first()->from() <= to) {
4446     // join intersecting ranges
4447     first()->set_from(MIN2(from, first()->from()));
4448     first()->set_to  (MAX2(to,   first()->to()));
4449   } else {
4450     // insert new range
4451     _first = new Range(from, to, first());
4452   }
4453 }
4454 
4455 Interval* Interval::new_split_child() {
4456   // allocate new interval
4457   Interval* result = new Interval(-1);
4458   result->set_type(type());
4459 
4460   Interval* parent = split_parent();
4461   result->_split_parent = parent;
4462   result->set_register_hint(parent);
4463 
4464   // insert new interval in children-list of parent
4465   if (parent->_split_children == nullptr) {
4466     assert(is_split_parent(), "list must be initialized at first split");
4467 
4468     parent->_split_children = new IntervalList(4);
4469     parent->_split_children->append(this);
4470   }
4471   parent->_split_children->append(result);
4472 
4473   return result;
4474 }
4475 
4476 // split this interval at the specified position and return
4477 // the remainder as a new interval.
4478 //
4479 // when an interval is split, a bi-directional link is established between the original interval
4480 // (the split parent) and the intervals that are split off this interval (the split children)
4481 // When a split child is split again, the new created interval is also a direct child
4482 // of the original parent (there is no tree of split children stored, but a flat list)
4483 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4484 //
4485 // Note: The new interval has no valid reg_num
4486 Interval* Interval::split(int split_pos) {
4487   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4488 
4489   // allocate new interval
4490   Interval* result = new_split_child();
4491 
4492   // split the ranges
4493   Range* prev = nullptr;
4494   Range* cur = _first;
4495   while (cur != Range::end() && cur->to() <= split_pos) {
4496     prev = cur;
4497     cur = cur->next();
4498   }
4499   assert(cur != Range::end(), "split interval after end of last range");
4500 
4501   if (cur->from() < split_pos) {
4502     result->_first = new Range(split_pos, cur->to(), cur->next());
4503     cur->set_to(split_pos);
4504     cur->set_next(Range::end());
4505 
4506   } else {
4507     assert(prev != nullptr, "split before start of first range");
4508     result->_first = cur;
4509     prev->set_next(Range::end());
4510   }
4511   result->_current = result->_first;
4512   _cached_to = -1; // clear cached value
4513 
4514   // split list of use positions
4515   int total_len = _use_pos_and_kinds.length();
4516   int start_idx = total_len - 2;
4517   while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4518     start_idx -= 2;
4519   }
4520 
4521   intStack new_use_pos_and_kinds(total_len - start_idx);
4522   int i;
4523   for (i = start_idx + 2; i < total_len; i++) {
4524     new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4525   }
4526 
4527   _use_pos_and_kinds.trunc_to(start_idx + 2);
4528   result->_use_pos_and_kinds = _use_pos_and_kinds;
4529   _use_pos_and_kinds = new_use_pos_and_kinds;
4530 
4531 #ifdef ASSERT
4532   assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4533   assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4534   assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4535 
4536   for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4537     assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4538     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4539   }
4540   for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4541     assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4542     assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4543   }
4544 #endif
4545 
4546   return result;
4547 }
4548 
4549 // split this interval at the specified position and return
4550 // the head as a new interval (the original interval is the tail)
4551 //
4552 // Currently, only the first range can be split, and the new interval
4553 // must not have split positions
4554 Interval* Interval::split_from_start(int split_pos) {
4555   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4556   assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4557   assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4558   assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4559 
4560   // allocate new interval
4561   Interval* result = new_split_child();
4562 
4563   // the new created interval has only one range (checked by assertion above),
4564   // so the splitting of the ranges is very simple
4565   result->add_range(_first->from(), split_pos);
4566 
4567   if (split_pos == _first->to()) {
4568     assert(_first->next() != Range::end(), "must not be at end");
4569     _first = _first->next();
4570   } else {
4571     _first->set_from(split_pos);
4572   }
4573 
4574   return result;
4575 }
4576 
4577 
4578 // returns true if the op_id is inside the interval
4579 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4580   Range* cur  = _first;
4581 
4582   while (cur != Range::end() && cur->to() < op_id) {
4583     cur = cur->next();
4584   }
4585   if (cur != Range::end()) {
4586     assert(cur->to() != cur->next()->from(), "ranges not separated");
4587 
4588     if (mode == LIR_OpVisitState::outputMode) {
4589       return cur->from() <= op_id && op_id < cur->to();
4590     } else {
4591       return cur->from() <= op_id && op_id <= cur->to();
4592     }
4593   }
4594   return false;
4595 }
4596 
4597 // returns true if the interval has any hole between hole_from and hole_to
4598 // (even if the hole has only the length 1)
4599 bool Interval::has_hole_between(int hole_from, int hole_to) {
4600   assert(hole_from < hole_to, "check");
4601   assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4602 
4603   Range* cur  = _first;
4604   while (cur != Range::end()) {
4605     assert(cur->to() < cur->next()->from(), "no space between ranges");
4606 
4607     // hole-range starts before this range -> hole
4608     if (hole_from < cur->from()) {
4609       return true;
4610 
4611     // hole-range completely inside this range -> no hole
4612     } else if (hole_to <= cur->to()) {
4613       return false;
4614 
4615     // overlapping of hole-range with this range -> hole
4616     } else if (hole_from <= cur->to()) {
4617       return true;
4618     }
4619 
4620     cur = cur->next();
4621   }
4622 
4623   return false;
4624 }
4625 
4626 // Check if there is an intersection with any of the split children of 'interval'
4627 bool Interval::intersects_any_children_of(Interval* interval) const {
4628   if (interval->_split_children != nullptr) {
4629     for (int i = 0; i < interval->_split_children->length(); i++) {
4630       if (intersects(interval->_split_children->at(i))) {
4631         return true;
4632       }
4633     }
4634   }
4635   return false;
4636 }
4637 
4638 
4639 #ifndef PRODUCT
4640 void Interval::print_on(outputStream* out, bool is_cfg_printer) const {
4641   const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4642   const char* UseKind2Name[] = { "N", "L", "S", "M" };
4643 
4644   const char* type_name;
4645   if (reg_num() < LIR_Opr::vreg_base) {
4646     type_name = "fixed";
4647   } else {
4648     type_name = type2name(type());
4649   }
4650   out->print("%d %s ", reg_num(), type_name);
4651 
4652   if (is_cfg_printer) {
4653     // Special version for compatibility with C1 Visualizer.
4654     LIR_Opr opr = LinearScan::get_operand(reg_num());
4655     if (opr->is_valid()) {
4656       out->print("\"");
4657       opr->print(out);
4658       out->print("\" ");
4659     }
4660   } else {
4661     // Improved output for normal debugging.
4662     if (reg_num() < LIR_Opr::vreg_base) {
4663       LinearScan::print_reg_num(out, assigned_reg());
4664     } else if (assigned_reg() != -1 && (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4665       LinearScan::calc_operand_for_interval(this)->print(out);
4666     } else {
4667       // Virtual register that has no assigned register yet.
4668       out->print("[ANY]");
4669     }
4670     out->print(" ");
4671   }
4672   out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != nullptr ? register_hint(false)->reg_num() : -1));
4673 
4674   // print ranges
4675   Range* cur = _first;
4676   while (cur != Range::end()) {
4677     cur->print(out);
4678     cur = cur->next();
4679     assert(cur != nullptr, "range list not closed with range sentinel");
4680   }
4681 
4682   // print use positions
4683   int prev = 0;
4684   assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4685   for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4686     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4687     assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4688 
4689     out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4690     prev = _use_pos_and_kinds.at(i);
4691   }
4692 
4693   out->print(" \"%s\"", SpillState2Name[spill_state()]);
4694   out->cr();
4695 }
4696 
4697 void Interval::print_parent() const {
4698   if (_split_parent != this) {
4699     _split_parent->print_on(tty);
4700   } else {
4701     tty->print_cr("Parent: this");
4702   }
4703 }
4704 
4705 void Interval::print_children() const {
4706   if (_split_children == nullptr) {
4707     tty->print_cr("Children: []");
4708   } else {
4709     tty->print_cr("Children:");
4710     for (int i = 0; i < _split_children->length(); i++) {
4711       tty->print("%d: ", i);
4712       _split_children->at(i)->print_on(tty);
4713     }
4714   }
4715 }
4716 #endif // NOT PRODUCT
4717 
4718 
4719 
4720 
4721 // **** Implementation of IntervalWalker ****************************
4722 
4723 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4724  : _compilation(allocator->compilation())
4725  , _allocator(allocator)
4726 {
4727   _unhandled_first[fixedKind] = unhandled_fixed_first;
4728   _unhandled_first[anyKind]   = unhandled_any_first;
4729   _active_first[fixedKind]    = Interval::end();
4730   _inactive_first[fixedKind]  = Interval::end();
4731   _active_first[anyKind]      = Interval::end();
4732   _inactive_first[anyKind]    = Interval::end();
4733   _current_position = -1;
4734   _current = nullptr;
4735   next_interval();
4736 }
4737 
4738 
4739 // append interval in order of current range from()
4740 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4741   Interval* prev = nullptr;
4742   Interval* cur  = *list;
4743   while (cur->current_from() < interval->current_from()) {
4744     prev = cur; cur = cur->next();
4745   }
4746   if (prev == nullptr) {
4747     *list = interval;
4748   } else {
4749     prev->set_next(interval);
4750   }
4751   interval->set_next(cur);
4752 }
4753 
4754 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4755   assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4756 
4757   Interval* prev = nullptr;
4758   Interval* cur  = *list;
4759   while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4760     prev = cur; cur = cur->next();
4761   }
4762   if (prev == nullptr) {
4763     *list = interval;
4764   } else {
4765     prev->set_next(interval);
4766   }
4767   interval->set_next(cur);
4768 }
4769 
4770 
4771 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4772   while (*list != Interval::end() && *list != i) {
4773     list = (*list)->next_addr();
4774   }
4775   if (*list != Interval::end()) {
4776     assert(*list == i, "check");
4777     *list = (*list)->next();
4778     return true;
4779   } else {
4780     return false;
4781   }
4782 }
4783 
4784 void IntervalWalker::remove_from_list(Interval* i) {
4785   bool deleted;
4786 
4787   if (i->state() == activeState) {
4788     deleted = remove_from_list(active_first_addr(anyKind), i);
4789   } else {
4790     assert(i->state() == inactiveState, "invalid state");
4791     deleted = remove_from_list(inactive_first_addr(anyKind), i);
4792   }
4793 
4794   assert(deleted, "interval has not been found in list");
4795 }
4796 
4797 
4798 void IntervalWalker::walk_to(IntervalState state, int from) {
4799   assert (state == activeState || state == inactiveState, "wrong state");
4800   for_each_interval_kind(kind) {
4801     Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4802     Interval* next   = *prev;
4803     while (next->current_from() <= from) {
4804       Interval* cur = next;
4805       next = cur->next();
4806 
4807       bool range_has_changed = false;
4808       while (cur->current_to() <= from) {
4809         cur->next_range();
4810         range_has_changed = true;
4811       }
4812 
4813       // also handle move from inactive list to active list
4814       range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4815 
4816       if (range_has_changed) {
4817         // remove cur from list
4818         *prev = next;
4819         if (cur->current_at_end()) {
4820           // move to handled state (not maintained as a list)
4821           cur->set_state(handledState);
4822           DEBUG_ONLY(interval_moved(cur, kind, state, handledState);)
4823         } else if (cur->current_from() <= from){
4824           // sort into active list
4825           append_sorted(active_first_addr(kind), cur);
4826           cur->set_state(activeState);
4827           if (*prev == cur) {
4828             assert(state == activeState, "check");
4829             prev = cur->next_addr();
4830           }
4831           DEBUG_ONLY(interval_moved(cur, kind, state, activeState);)
4832         } else {
4833           // sort into inactive list
4834           append_sorted(inactive_first_addr(kind), cur);
4835           cur->set_state(inactiveState);
4836           if (*prev == cur) {
4837             assert(state == inactiveState, "check");
4838             prev = cur->next_addr();
4839           }
4840           DEBUG_ONLY(interval_moved(cur, kind, state, inactiveState);)
4841         }
4842       } else {
4843         prev = cur->next_addr();
4844         continue;
4845       }
4846     }
4847   }
4848 }
4849 
4850 
4851 void IntervalWalker::next_interval() {
4852   IntervalKind kind;
4853   Interval* any   = _unhandled_first[anyKind];
4854   Interval* fixed = _unhandled_first[fixedKind];
4855 
4856   if (any != Interval::end()) {
4857     // intervals may start at same position -> prefer fixed interval
4858     kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4859 
4860     assert((kind == fixedKind && fixed->from() <= any->from()) ||
4861            (kind == anyKind   && any->from() <= fixed->from()), "wrong interval!!!");
4862     assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4863 
4864   } else if (fixed != Interval::end()) {
4865     kind = fixedKind;
4866   } else {
4867     _current = nullptr; return;
4868   }
4869   _current_kind = kind;
4870   _current = _unhandled_first[kind];
4871   _unhandled_first[kind] = _current->next();
4872   _current->set_next(Interval::end());
4873   _current->rewind_range();
4874 }
4875 
4876 
4877 void IntervalWalker::walk_to(int lir_op_id) {
4878   assert(_current_position <= lir_op_id, "can not walk backwards");
4879   while (current() != nullptr) {
4880     bool is_active = current()->from() <= lir_op_id;
4881     int id = is_active ? current()->from() : lir_op_id;
4882 
4883     TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4884 
4885     // set _current_position prior to call of walk_to
4886     _current_position = id;
4887 
4888     // call walk_to even if _current_position == id
4889     walk_to(activeState, id);
4890     walk_to(inactiveState, id);
4891 
4892     if (is_active) {
4893       current()->set_state(activeState);
4894       if (activate_current()) {
4895         append_sorted(active_first_addr(current_kind()), current());
4896         DEBUG_ONLY(interval_moved(current(), current_kind(), unhandledState, activeState);)
4897       }
4898 
4899       next_interval();
4900     } else {
4901       return;
4902     }
4903   }
4904 }
4905 
4906 #ifdef ASSERT
4907 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4908   if (TraceLinearScanLevel >= 4) {
4909     #define print_state(state) \
4910     switch(state) {\
4911       case unhandledState: tty->print("unhandled"); break;\
4912       case activeState: tty->print("active"); break;\
4913       case inactiveState: tty->print("inactive"); break;\
4914       case handledState: tty->print("handled"); break;\
4915       default: ShouldNotReachHere(); \
4916     }
4917 
4918     print_state(from); tty->print(" to "); print_state(to);
4919     tty->fill_to(23);
4920     interval->print();
4921 
4922     #undef print_state
4923   }
4924 }
4925 #endif // ASSERT
4926 
4927 // **** Implementation of LinearScanWalker **************************
4928 
4929 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4930   : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4931   , _move_resolver(allocator)
4932 {
4933   for (int i = 0; i < LinearScan::nof_regs; i++) {
4934     _spill_intervals[i] = new IntervalList(2);
4935   }
4936 }
4937 
4938 
4939 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4940   for (int i = _first_reg; i <= _last_reg; i++) {
4941     _use_pos[i] = max_jint;
4942 
4943     if (!only_process_use_pos) {
4944       _block_pos[i] = max_jint;
4945       _spill_intervals[i]->clear();
4946     }
4947   }
4948 }
4949 
4950 inline void LinearScanWalker::exclude_from_use(int reg) {
4951   assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4952   if (reg >= _first_reg && reg <= _last_reg) {
4953     _use_pos[reg] = 0;
4954   }
4955 }
4956 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4957   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4958 
4959   exclude_from_use(i->assigned_reg());
4960   exclude_from_use(i->assigned_regHi());
4961 }
4962 
4963 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4964   assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4965 
4966   if (reg >= _first_reg && reg <= _last_reg) {
4967     if (_use_pos[reg] > use_pos) {
4968       _use_pos[reg] = use_pos;
4969     }
4970     if (!only_process_use_pos) {
4971       _spill_intervals[reg]->append(i);
4972     }
4973   }
4974 }
4975 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4976   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4977   if (use_pos != -1) {
4978     set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4979     set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4980   }
4981 }
4982 
4983 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4984   if (reg >= _first_reg && reg <= _last_reg) {
4985     if (_block_pos[reg] > block_pos) {
4986       _block_pos[reg] = block_pos;
4987     }
4988     if (_use_pos[reg] > block_pos) {
4989       _use_pos[reg] = block_pos;
4990     }
4991   }
4992 }
4993 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4994   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4995   if (block_pos != -1) {
4996     set_block_pos(i->assigned_reg(), i, block_pos);
4997     set_block_pos(i->assigned_regHi(), i, block_pos);
4998   }
4999 }
5000 
5001 
5002 void LinearScanWalker::free_exclude_active_fixed() {
5003   Interval* list = active_first(fixedKind);
5004   while (list != Interval::end()) {
5005     assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
5006     exclude_from_use(list);
5007     list = list->next();
5008   }
5009 }
5010 
5011 void LinearScanWalker::free_exclude_active_any() {
5012   Interval* list = active_first(anyKind);
5013   while (list != Interval::end()) {
5014     exclude_from_use(list);
5015     list = list->next();
5016   }
5017 }
5018 
5019 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
5020   Interval* list = inactive_first(fixedKind);
5021   while (list != Interval::end()) {
5022     if (cur->to() <= list->current_from()) {
5023       assert(list->current_intersects_at(cur) == -1, "must not intersect");
5024       set_use_pos(list, list->current_from(), true);
5025     } else {
5026       set_use_pos(list, list->current_intersects_at(cur), true);
5027     }
5028     list = list->next();
5029   }
5030 }
5031 
5032 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
5033   Interval* list = inactive_first(anyKind);
5034   while (list != Interval::end()) {
5035     set_use_pos(list, list->current_intersects_at(cur), true);
5036     list = list->next();
5037   }
5038 }
5039 
5040 void LinearScanWalker::spill_exclude_active_fixed() {
5041   Interval* list = active_first(fixedKind);
5042   while (list != Interval::end()) {
5043     exclude_from_use(list);
5044     list = list->next();
5045   }
5046 }
5047 
5048 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
5049   Interval* list = inactive_first(fixedKind);
5050   while (list != Interval::end()) {
5051     if (cur->to() > list->current_from()) {
5052       set_block_pos(list, list->current_intersects_at(cur));
5053     } else {
5054       assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
5055     }
5056 
5057     list = list->next();
5058   }
5059 }
5060 
5061 void LinearScanWalker::spill_collect_active_any() {
5062   Interval* list = active_first(anyKind);
5063   while (list != Interval::end()) {
5064     set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5065     list = list->next();
5066   }
5067 }
5068 
5069 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
5070   Interval* list = inactive_first(anyKind);
5071   while (list != Interval::end()) {
5072     if (list->current_intersects(cur)) {
5073       set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5074     }
5075     list = list->next();
5076   }
5077 }
5078 
5079 
5080 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
5081   // output all moves here. When source and target are equal, the move is
5082   // optimized away later in assign_reg_nums
5083 
5084   op_id = (op_id + 1) & ~1;
5085   BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
5086   assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
5087 
5088   // calculate index of instruction inside instruction list of current block
5089   // the minimal index (for a block with no spill moves) can be calculated because the
5090   // numbering of instructions is known.
5091   // When the block already contains spill moves, the index must be increased until the
5092   // correct index is reached.
5093   LIR_OpList* list = op_block->lir()->instructions_list();
5094   int index = (op_id - list->at(0)->id()) / 2;
5095   assert(list->at(index)->id() <= op_id, "error in calculation");
5096 
5097   while (list->at(index)->id() != op_id) {
5098     index++;
5099     assert(0 <= index && index < list->length(), "index out of bounds");
5100   }
5101   assert(1 <= index && index < list->length(), "index out of bounds");
5102   assert(list->at(index)->id() == op_id, "error in calculation");
5103 
5104   // insert new instruction before instruction at position index
5105   _move_resolver.move_insert_position(op_block->lir(), index - 1);
5106   _move_resolver.add_mapping(src_it, dst_it);
5107 }
5108 
5109 
5110 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
5111   int from_block_nr = min_block->linear_scan_number();
5112   int to_block_nr = max_block->linear_scan_number();
5113 
5114   assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
5115   assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
5116   assert(from_block_nr < to_block_nr, "must cross block boundary");
5117 
5118   // Try to split at end of max_block. If this would be after
5119   // max_split_pos, then use the begin of max_block
5120   int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
5121   if (optimal_split_pos > max_split_pos) {
5122     optimal_split_pos = max_block->first_lir_instruction_id();
5123   }
5124 
5125   int min_loop_depth = max_block->loop_depth();
5126   for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5127     BlockBegin* cur = block_at(i);
5128 
5129     if (cur->loop_depth() < min_loop_depth) {
5130       // block with lower loop-depth found -> split at the end of this block
5131       min_loop_depth = cur->loop_depth();
5132       optimal_split_pos = cur->last_lir_instruction_id() + 2;
5133     }
5134   }
5135   assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5136 
5137   return optimal_split_pos;
5138 }
5139 
5140 
5141 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5142   int optimal_split_pos = -1;
5143   if (min_split_pos == max_split_pos) {
5144     // trivial case, no optimization of split position possible
5145     TRACE_LINEAR_SCAN(4, tty->print_cr("      min-pos and max-pos are equal, no optimization possible"));
5146     optimal_split_pos = min_split_pos;
5147 
5148   } else {
5149     assert(min_split_pos < max_split_pos, "must be true then");
5150     assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5151 
5152     // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5153     // beginning of a block, then min_split_pos is also a possible split position.
5154     // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5155     BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5156 
5157     // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5158     // when an interval ends at the end of the last block of the method
5159     // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5160     // block at this op_id)
5161     BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5162 
5163     assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5164     if (min_block == max_block) {
5165       // split position cannot be moved to block boundary, so split as late as possible
5166       TRACE_LINEAR_SCAN(4, tty->print_cr("      cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5167       optimal_split_pos = max_split_pos;
5168 
5169     } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5170       // Do not move split position if the interval has a hole before max_split_pos.
5171       // Intervals resulting from Phi-Functions have more than one definition (marked
5172       // as mustHaveRegister) with a hole before each definition. When the register is needed
5173       // for the second definition, an earlier reloading is unnecessary.
5174       TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has hole just before max_split_pos, so splitting at max_split_pos"));
5175       optimal_split_pos = max_split_pos;
5176 
5177     } else {
5178       // search optimal block boundary between min_split_pos and max_split_pos
5179       TRACE_LINEAR_SCAN(4, tty->print_cr("      moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5180 
5181       if (do_loop_optimization) {
5182         // Loop optimization: if a loop-end marker is found between min- and max-position,
5183         // then split before this loop
5184         int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5185         TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization: loop end found at pos %d", loop_end_pos));
5186 
5187         assert(loop_end_pos > min_split_pos, "invalid order");
5188         if (loop_end_pos < max_split_pos) {
5189           // loop-end marker found between min- and max-position
5190           // if it is not the end marker for the same loop as the min-position, then move
5191           // the max-position to this loop block.
5192           // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5193           // of the interval (normally, only mustHaveRegister causes a reloading)
5194           BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5195 
5196           TRACE_LINEAR_SCAN(4, tty->print_cr("      interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5197           assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5198 
5199           optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5200           if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5201             optimal_split_pos = -1;
5202             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization not necessary"));
5203           } else {
5204             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization successful"));
5205           }
5206         }
5207       }
5208 
5209       if (optimal_split_pos == -1) {
5210         // not calculated by loop optimization
5211         optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5212       }
5213     }
5214   }
5215   TRACE_LINEAR_SCAN(4, tty->print_cr("      optimal split position: %d", optimal_split_pos));
5216 
5217   return optimal_split_pos;
5218 }
5219 
5220 
5221 /*
5222   split an interval at the optimal position between min_split_pos and
5223   max_split_pos in two parts:
5224   1) the left part has already a location assigned
5225   2) the right part is sorted into to the unhandled-list
5226 */
5227 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5228   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting interval: "); it->print());
5229   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5230 
5231   assert(it->from() < min_split_pos,         "cannot split at start of interval");
5232   assert(current_position() < min_split_pos, "cannot split before current position");
5233   assert(min_split_pos <= max_split_pos,     "invalid order");
5234   assert(max_split_pos <= it->to(),          "cannot split after end of interval");
5235 
5236   int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5237 
5238   assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5239   assert(optimal_split_pos <= it->to(),  "cannot split after end of interval");
5240   assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5241 
5242   if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5243     // the split position would be just before the end of the interval
5244     // -> no split at all necessary
5245     TRACE_LINEAR_SCAN(4, tty->print_cr("      no split necessary because optimal split position is at end of interval"));
5246     return;
5247   }
5248 
5249   // must calculate this before the actual split is performed and before split position is moved to odd op_id
5250   bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5251 
5252   if (!allocator()->is_block_begin(optimal_split_pos)) {
5253     // move position before actual instruction (odd op_id)
5254     optimal_split_pos = (optimal_split_pos - 1) | 1;
5255   }
5256 
5257   TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5258   assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5259   assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5260 
5261   Interval* split_part = it->split(optimal_split_pos);
5262 
5263   allocator()->append_interval(split_part);
5264   allocator()->copy_register_flags(it, split_part);
5265   split_part->set_insert_move_when_activated(move_necessary);
5266   append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5267 
5268   TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5269   TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5270   TRACE_LINEAR_SCAN(2, tty->print   ("      "); split_part->print());
5271 }
5272 
5273 /*
5274   split an interval at the optimal position between min_split_pos and
5275   max_split_pos in two parts:
5276   1) the left part has already a location assigned
5277   2) the right part is always on the stack and therefore ignored in further processing
5278 */
5279 void LinearScanWalker::split_for_spilling(Interval* it) {
5280   // calculate allowed range of splitting position
5281   int max_split_pos = current_position();
5282   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5283 
5284   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting and spilling interval: "); it->print());
5285   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5286 
5287   assert(it->state() == activeState,     "why spill interval that is not active?");
5288   assert(it->from() <= min_split_pos,    "cannot split before start of interval");
5289   assert(min_split_pos <= max_split_pos, "invalid order");
5290   assert(max_split_pos < it->to(),       "cannot split at end end of interval");
5291   assert(current_position() < it->to(),  "interval must not end before current position");
5292 
5293   if (min_split_pos == it->from()) {
5294     // the whole interval is never used, so spill it entirely to memory
5295     TRACE_LINEAR_SCAN(2, tty->print_cr("      spilling entire interval because split pos is at beginning of interval"));
5296     assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5297 
5298     allocator()->assign_spill_slot(it);
5299     allocator()->change_spill_state(it, min_split_pos);
5300 
5301     // Also kick parent intervals out of register to memory when they have no use
5302     // position. This avoids short interval in register surrounded by intervals in
5303     // memory -> avoid useless moves from memory to register and back
5304     Interval* parent = it;
5305     while (parent != nullptr && parent->is_split_child()) {
5306       parent = parent->split_child_before_op_id(parent->from());
5307 
5308       if (parent->assigned_reg() < LinearScan::nof_regs) {
5309         if (parent->first_usage(shouldHaveRegister) == max_jint) {
5310           // parent is never used, so kick it out of its assigned register
5311           TRACE_LINEAR_SCAN(4, tty->print_cr("      kicking out interval %d out of its register because it is never used", parent->reg_num()));
5312           allocator()->assign_spill_slot(parent);
5313         } else {
5314           // do not go further back because the register is actually used by the interval
5315           parent = nullptr;
5316         }
5317       }
5318     }
5319 
5320   } else {
5321     // search optimal split pos, split interval and spill only the right hand part
5322     int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5323 
5324     assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5325     assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5326     assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5327 
5328     if (!allocator()->is_block_begin(optimal_split_pos)) {
5329       // move position before actual instruction (odd op_id)
5330       optimal_split_pos = (optimal_split_pos - 1) | 1;
5331     }
5332 
5333     TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5334     assert(allocator()->is_block_begin(optimal_split_pos)  || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5335     assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5336 
5337     Interval* spilled_part = it->split(optimal_split_pos);
5338     allocator()->append_interval(spilled_part);
5339     allocator()->assign_spill_slot(spilled_part);
5340     allocator()->change_spill_state(spilled_part, optimal_split_pos);
5341 
5342     if (!allocator()->is_block_begin(optimal_split_pos)) {
5343       TRACE_LINEAR_SCAN(4, tty->print_cr("      inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5344       insert_move(optimal_split_pos, it, spilled_part);
5345     }
5346 
5347     // the current_split_child is needed later when moves are inserted for reloading
5348     assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5349     spilled_part->make_current_split_child();
5350 
5351     TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts"));
5352     TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5353     TRACE_LINEAR_SCAN(2, tty->print   ("      "); spilled_part->print());
5354   }
5355 }
5356 
5357 
5358 void LinearScanWalker::split_stack_interval(Interval* it) {
5359   int min_split_pos = current_position() + 1;
5360   int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5361 
5362   split_before_usage(it, min_split_pos, max_split_pos);
5363 }
5364 
5365 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5366   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5367   int max_split_pos = register_available_until;
5368 
5369   split_before_usage(it, min_split_pos, max_split_pos);
5370 }
5371 
5372 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5373   assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5374 
5375   int current_pos = current_position();
5376   if (it->state() == inactiveState) {
5377     // the interval is currently inactive, so no spill slot is needed for now.
5378     // when the split part is activated, the interval has a new chance to get a register,
5379     // so in the best case no stack slot is necessary
5380     assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5381     split_before_usage(it, current_pos + 1, current_pos + 1);
5382 
5383   } else {
5384     // search the position where the interval must have a register and split
5385     // at the optimal position before.
5386     // The new created part is added to the unhandled list and will get a register
5387     // when it is activated
5388     int min_split_pos = current_pos + 1;
5389     int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5390 
5391     split_before_usage(it, min_split_pos, max_split_pos);
5392 
5393     assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5394     split_for_spilling(it);
5395   }
5396 }
5397 
5398 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5399   int min_full_reg = any_reg;
5400   int max_partial_reg = any_reg;
5401 
5402   for (int i = _first_reg; i <= _last_reg; i++) {
5403     if (i == ignore_reg) {
5404       // this register must be ignored
5405 
5406     } else if (_use_pos[i] >= interval_to) {
5407       // this register is free for the full interval
5408       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5409         min_full_reg = i;
5410       }
5411     } else if (_use_pos[i] > reg_needed_until) {
5412       // this register is at least free until reg_needed_until
5413       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5414         max_partial_reg = i;
5415       }
5416     }
5417   }
5418 
5419   if (min_full_reg != any_reg) {
5420     return min_full_reg;
5421   } else if (max_partial_reg != any_reg) {
5422     *need_split = true;
5423     return max_partial_reg;
5424   } else {
5425     return any_reg;
5426   }
5427 }
5428 
5429 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5430   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5431 
5432   int min_full_reg = any_reg;
5433   int max_partial_reg = any_reg;
5434 
5435   for (int i = _first_reg; i < _last_reg; i+=2) {
5436     if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5437       // this register is free for the full interval
5438       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5439         min_full_reg = i;
5440       }
5441     } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5442       // this register is at least free until reg_needed_until
5443       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5444         max_partial_reg = i;
5445       }
5446     }
5447   }
5448 
5449   if (min_full_reg != any_reg) {
5450     return min_full_reg;
5451   } else if (max_partial_reg != any_reg) {
5452     *need_split = true;
5453     return max_partial_reg;
5454   } else {
5455     return any_reg;
5456   }
5457 }
5458 
5459 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5460   TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5461 
5462   init_use_lists(true);
5463   free_exclude_active_fixed();
5464   free_exclude_active_any();
5465   free_collect_inactive_fixed(cur);
5466   free_collect_inactive_any(cur);
5467   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5468 
5469   // _use_pos contains the start of the next interval that has this register assigned
5470   // (either as a fixed register or a normal allocated register in the past)
5471   // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5472 #ifdef ASSERT
5473   if (TraceLinearScanLevel >= 4) {
5474     tty->print_cr("      state of registers:");
5475     for (int i = _first_reg; i <= _last_reg; i++) {
5476       tty->print("      reg %d (", i);
5477       LinearScan::print_reg_num(i);
5478       tty->print_cr("): use_pos: %d", _use_pos[i]);
5479     }
5480   }
5481 #endif
5482 
5483   int hint_reg, hint_regHi;
5484   Interval* register_hint = cur->register_hint();
5485   if (register_hint != nullptr) {
5486     hint_reg = register_hint->assigned_reg();
5487     hint_regHi = register_hint->assigned_regHi();
5488 
5489     if (_num_phys_regs == 2 && allocator()->is_precolored_cpu_interval(register_hint)) {
5490       assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5491       hint_regHi = hint_reg + 1;  // connect e.g. eax-edx
5492     }
5493 #ifdef ASSERT
5494     if (TraceLinearScanLevel >= 4) {
5495       tty->print("      hint registers %d (", hint_reg);
5496       LinearScan::print_reg_num(hint_reg);
5497       tty->print("), %d (", hint_regHi);
5498       LinearScan::print_reg_num(hint_regHi);
5499       tty->print(") from interval ");
5500       register_hint->print();
5501     }
5502 #endif
5503   } else {
5504     hint_reg = any_reg;
5505     hint_regHi = any_reg;
5506   }
5507   assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5508   assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5509 
5510   // the register must be free at least until this position
5511   int reg_needed_until = cur->from() + 1;
5512   int interval_to = cur->to();
5513 
5514   bool need_split = false;
5515   int split_pos;
5516   int reg;
5517   int regHi = any_reg;
5518 
5519   if (_adjacent_regs) {
5520     reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5521     regHi = reg + 1;
5522     if (reg == any_reg) {
5523       return false;
5524     }
5525     split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5526 
5527   } else {
5528     reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5529     if (reg == any_reg) {
5530       return false;
5531     }
5532     split_pos = _use_pos[reg];
5533 
5534     if (_num_phys_regs == 2) {
5535       regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5536 
5537       if (_use_pos[reg] < interval_to && regHi == any_reg) {
5538         // do not split interval if only one register can be assigned until the split pos
5539         // (when one register is found for the whole interval, split&spill is only
5540         // performed for the hi register)
5541         return false;
5542 
5543       } else if (regHi != any_reg) {
5544         split_pos = MIN2(split_pos, _use_pos[regHi]);
5545 
5546         // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5547         if (reg > regHi) {
5548           int temp = reg;
5549           reg = regHi;
5550           regHi = temp;
5551         }
5552       }
5553     }
5554   }
5555 
5556   cur->assign_reg(reg, regHi);
5557 #ifdef ASSERT
5558   if (TraceLinearScanLevel >= 2) {
5559     tty->print("      selected registers %d (", reg);
5560     LinearScan::print_reg_num(reg);
5561     tty->print("), %d (", regHi);
5562     LinearScan::print_reg_num(regHi);
5563     tty->print_cr(")");
5564   }
5565 #endif
5566   assert(split_pos > 0, "invalid split_pos");
5567   if (need_split) {
5568     // register not available for full interval, so split it
5569     split_when_partial_register_available(cur, split_pos);
5570   }
5571 
5572   // only return true if interval is completely assigned
5573   return _num_phys_regs == 1 || regHi != any_reg;
5574 }
5575 
5576 
5577 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int ignore_reg, bool* need_split) {
5578   int max_reg = any_reg;
5579 
5580   for (int i = _first_reg; i <= _last_reg; i++) {
5581     if (i == ignore_reg) {
5582       // this register must be ignored
5583 
5584     } else if (_use_pos[i] > reg_needed_until) {
5585       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5586         max_reg = i;
5587       }
5588     }
5589   }
5590 
5591   if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5592     *need_split = true;
5593   }
5594 
5595   return max_reg;
5596 }
5597 
5598 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, bool* need_split) {
5599   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5600 
5601   int max_reg = any_reg;
5602 
5603   for (int i = _first_reg; i < _last_reg; i+=2) {
5604     if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5605       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5606         max_reg = i;
5607       }
5608     }
5609   }
5610 
5611   if (max_reg != any_reg &&
5612       (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to)) {
5613     *need_split = true;
5614   }
5615 
5616   return max_reg;
5617 }
5618 
5619 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5620   assert(reg != any_reg, "no register assigned");
5621 
5622   for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5623     Interval* it = _spill_intervals[reg]->at(i);
5624     remove_from_list(it);
5625     split_and_spill_interval(it);
5626   }
5627 
5628   if (regHi != any_reg) {
5629     IntervalList* processed = _spill_intervals[reg];
5630     for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5631       Interval* it = _spill_intervals[regHi]->at(i);
5632       if (processed->find(it) == -1) {
5633         remove_from_list(it);
5634         split_and_spill_interval(it);
5635       }
5636     }
5637   }
5638 }
5639 
5640 
5641 // Split an Interval and spill it to memory so that cur can be placed in a register
5642 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5643   TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5644 
5645   // collect current usage of registers
5646   init_use_lists(false);
5647   spill_exclude_active_fixed();
5648   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5649   spill_block_inactive_fixed(cur);
5650   spill_collect_active_any();
5651   spill_collect_inactive_any(cur);
5652 
5653 #ifdef ASSERT
5654   if (TraceLinearScanLevel >= 4) {
5655     tty->print_cr("      state of registers:");
5656     for (int i = _first_reg; i <= _last_reg; i++) {
5657       tty->print("      reg %d(", i);
5658       LinearScan::print_reg_num(i);
5659       tty->print("): use_pos: %d, block_pos: %d, intervals: ", _use_pos[i], _block_pos[i]);
5660       for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5661         tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5662       }
5663       tty->cr();
5664     }
5665   }
5666 #endif
5667 
5668   // the register must be free at least until this position
5669   int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5670   int interval_to = cur->to();
5671   assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5672 
5673   int split_pos = 0;
5674   int use_pos = 0;
5675   bool need_split = false;
5676   int reg, regHi;
5677 
5678   if (_adjacent_regs) {
5679     reg = find_locked_double_reg(reg_needed_until, interval_to, &need_split);
5680     regHi = reg + 1;
5681 
5682     if (reg != any_reg) {
5683       use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5684       split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5685     }
5686   } else {
5687     reg = find_locked_reg(reg_needed_until, interval_to, cur->assigned_reg(), &need_split);
5688     regHi = any_reg;
5689 
5690     if (reg != any_reg) {
5691       use_pos = _use_pos[reg];
5692       split_pos = _block_pos[reg];
5693 
5694       if (_num_phys_regs == 2) {
5695         if (cur->assigned_reg() != any_reg) {
5696           regHi = reg;
5697           reg = cur->assigned_reg();
5698         } else {
5699           regHi = find_locked_reg(reg_needed_until, interval_to, reg, &need_split);
5700           if (regHi != any_reg) {
5701             use_pos = MIN2(use_pos, _use_pos[regHi]);
5702             split_pos = MIN2(split_pos, _block_pos[regHi]);
5703           }
5704         }
5705 
5706         if (regHi != any_reg && reg > regHi) {
5707           // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5708           int temp = reg;
5709           reg = regHi;
5710           regHi = temp;
5711         }
5712       }
5713     }
5714   }
5715 
5716   if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5717     // the first use of cur is later than the spilling position -> spill cur
5718     TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5719 
5720     if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5721       assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5722       // assign a reasonable register and do a bailout in product mode to avoid errors
5723       allocator()->assign_spill_slot(cur);
5724       BAILOUT("LinearScan: no register found");
5725     }
5726 
5727     split_and_spill_interval(cur);
5728   } else {
5729 #ifdef ASSERT
5730     if (TraceLinearScanLevel >= 4) {
5731       tty->print("decided to use register %d (", reg);
5732       LinearScan::print_reg_num(reg);
5733       tty->print("), %d (", regHi);
5734       LinearScan::print_reg_num(regHi);
5735       tty->print_cr(")");
5736     }
5737 #endif
5738     assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5739     assert(split_pos > 0, "invalid split_pos");
5740     assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5741 
5742     cur->assign_reg(reg, regHi);
5743     if (need_split) {
5744       // register not available for full interval, so split it
5745       split_when_partial_register_available(cur, split_pos);
5746     }
5747 
5748     // perform splitting and spilling for all affected intervals
5749     split_and_spill_intersecting_intervals(reg, regHi);
5750   }
5751 }
5752 
5753 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5754 #ifdef X86
5755   // fast calculation of intervals that can never get a register because the
5756   // the next instruction is a call that blocks all registers
5757   // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5758 
5759   // check if this interval is the result of a split operation
5760   // (an interval got a register until this position)
5761   int pos = cur->from();
5762   if ((pos & 1) == 1) {
5763     // the current instruction is a call that blocks all registers
5764     if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5765       TRACE_LINEAR_SCAN(4, tty->print_cr("      free register cannot be available because all registers blocked by following call"));
5766 
5767       // safety check that there is really no register available
5768       assert(alloc_free_reg(cur) == false, "found a register for this interval");
5769       return true;
5770     }
5771 
5772   }
5773 #endif
5774   return false;
5775 }
5776 
5777 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5778   BasicType type = cur->type();
5779   _num_phys_regs = LinearScan::num_physical_regs(type);
5780   _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5781 
5782   if (pd_init_regs_for_alloc(cur)) {
5783     // the appropriate register range was selected.
5784   } else if (type == T_FLOAT || type == T_DOUBLE) {
5785     _first_reg = pd_first_fpu_reg;
5786     _last_reg = pd_last_fpu_reg;
5787   } else {
5788     _first_reg = pd_first_cpu_reg;
5789     _last_reg = FrameMap::last_cpu_reg();
5790   }
5791 
5792   assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5793   assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5794 }
5795 
5796 
5797 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5798   if (op->code() != lir_move) {
5799     return false;
5800   }
5801   assert(op->as_Op1() != nullptr, "move must be LIR_Op1");
5802 
5803   LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5804   LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5805   return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5806 }
5807 
5808 // optimization (especially for phi functions of nested loops):
5809 // assign same spill slot to non-intersecting intervals
5810 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5811   if (cur->is_split_child()) {
5812     // optimization is only suitable for split parents
5813     return;
5814   }
5815 
5816   Interval* register_hint = cur->register_hint(false);
5817   if (register_hint == nullptr) {
5818     // cur is not the target of a move, otherwise register_hint would be set
5819     return;
5820   }
5821   assert(register_hint->is_split_parent(), "register hint must be split parent");
5822 
5823   if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5824     // combining the stack slots for intervals where spill move optimization is applied
5825     // is not benefitial and would cause problems
5826     return;
5827   }
5828 
5829   int begin_pos = cur->from();
5830   int end_pos = cur->to();
5831   if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5832     // safety check that lir_op_with_id is allowed
5833     return;
5834   }
5835 
5836   if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5837     // cur and register_hint are not connected with two moves
5838     return;
5839   }
5840 
5841   Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5842   Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5843   if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5844     // register_hint must be split, otherwise the re-writing of use positions does not work
5845     return;
5846   }
5847 
5848   assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5849   assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5850   assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5851   assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5852 
5853   if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5854     // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5855     return;
5856   }
5857   assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5858   assert(!cur->intersects(register_hint), "cur should not intersect register_hint");
5859 
5860   if (cur->intersects_any_children_of(register_hint)) {
5861     // Bail out if cur intersects any split children of register_hint, which have the same spill slot as their parent. An overlap of two intervals with
5862     // the same spill slot could result in a situation where both intervals are spilled at the same time to the same stack location which is not correct.
5863     return;
5864   }
5865 
5866   // modify intervals such that cur gets the same stack slot as register_hint
5867   // delete use positions to prevent the intervals to get a register at beginning
5868   cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5869   cur->remove_first_use_pos();
5870   end_hint->remove_first_use_pos();
5871 }
5872 
5873 
5874 // allocate a physical register or memory location to an interval
5875 bool LinearScanWalker::activate_current() {
5876   Interval* cur = current();
5877   bool result = true;
5878 
5879   TRACE_LINEAR_SCAN(2, tty->print   ("+++++ activating interval "); cur->print());
5880   TRACE_LINEAR_SCAN(4, tty->print_cr("      split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5881 
5882   if (cur->assigned_reg() >= LinearScan::nof_regs) {
5883     // activating an interval that has a stack slot assigned -> split it at first use position
5884     // used for method parameters
5885     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has spill slot assigned (method parameter) -> split it before first use"));
5886 
5887     split_stack_interval(cur);
5888     result = false;
5889 
5890   } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5891     // activating an interval that must start in a stack slot, but may get a register later
5892     // used for lir_roundfp: rounding is done by store to stack and reload later
5893     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval must start in stack slot -> split it before first use"));
5894     assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5895 
5896     allocator()->assign_spill_slot(cur);
5897     split_stack_interval(cur);
5898     result = false;
5899 
5900   } else if (cur->assigned_reg() == any_reg) {
5901     // interval has not assigned register -> normal allocation
5902     // (this is the normal case for most intervals)
5903     TRACE_LINEAR_SCAN(4, tty->print_cr("      normal allocation of register"));
5904 
5905     // assign same spill slot to non-intersecting intervals
5906     combine_spilled_intervals(cur);
5907 
5908     init_vars_for_alloc(cur);
5909     if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5910       // no empty register available.
5911       // split and spill another interval so that this interval gets a register
5912       alloc_locked_reg(cur);
5913     }
5914 
5915     // spilled intervals need not be move to active-list
5916     if (cur->assigned_reg() >= LinearScan::nof_regs) {
5917       result = false;
5918     }
5919   }
5920 
5921   // load spilled values that become active from stack slot to register
5922   if (cur->insert_move_when_activated()) {
5923     assert(cur->is_split_child(), "must be");
5924     assert(cur->current_split_child() != nullptr, "must be");
5925     assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5926     TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5927 
5928     insert_move(cur->from(), cur->current_split_child(), cur);
5929   }
5930   cur->make_current_split_child();
5931 
5932   return result; // true = interval is moved to active list
5933 }
5934 
5935 
5936 // Implementation of EdgeMoveOptimizer
5937 
5938 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5939   _edge_instructions(4),
5940   _edge_instructions_idx(4)
5941 {
5942 }
5943 
5944 void EdgeMoveOptimizer::optimize(BlockList* code) {
5945   EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5946 
5947   // ignore the first block in the list (index 0 is not processed)
5948   for (int i = code->length() - 1; i >= 1; i--) {
5949     BlockBegin* block = code->at(i);
5950 
5951     if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5952       optimizer.optimize_moves_at_block_end(block);
5953     }
5954     if (block->number_of_sux() == 2) {
5955       optimizer.optimize_moves_at_block_begin(block);
5956     }
5957   }
5958 }
5959 
5960 
5961 // clear all internal data structures
5962 void EdgeMoveOptimizer::init_instructions() {
5963   _edge_instructions.clear();
5964   _edge_instructions_idx.clear();
5965 }
5966 
5967 // append a lir-instruction-list and the index of the current operation in to the list
5968 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5969   _edge_instructions.append(instructions);
5970   _edge_instructions_idx.append(instructions_idx);
5971 }
5972 
5973 // return the current operation of the given edge (predecessor or successor)
5974 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5975   LIR_OpList* instructions = _edge_instructions.at(edge);
5976   int idx = _edge_instructions_idx.at(edge);
5977 
5978   if (idx < instructions->length()) {
5979     return instructions->at(idx);
5980   } else {
5981     return nullptr;
5982   }
5983 }
5984 
5985 // removes the current operation of the given edge (predecessor or successor)
5986 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5987   LIR_OpList* instructions = _edge_instructions.at(edge);
5988   int idx = _edge_instructions_idx.at(edge);
5989   instructions->remove_at(idx);
5990 
5991   if (decrement_index) {
5992     _edge_instructions_idx.at_put(edge, idx - 1);
5993   }
5994 }
5995 
5996 
5997 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5998   if (op1 == nullptr || op2 == nullptr) {
5999     // at least one block is already empty -> no optimization possible
6000     return true;
6001   }
6002 
6003   if (op1->code() == lir_move && op2->code() == lir_move) {
6004     assert(op1->as_Op1() != nullptr, "move must be LIR_Op1");
6005     assert(op2->as_Op1() != nullptr, "move must be LIR_Op1");
6006     LIR_Op1* move1 = (LIR_Op1*)op1;
6007     LIR_Op1* move2 = (LIR_Op1*)op2;
6008     if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
6009       // these moves are exactly equal and can be optimized
6010       return false;
6011     }
6012 
6013   } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
6014     assert(op1->as_Op1() != nullptr, "fxch must be LIR_Op1");
6015     assert(op2->as_Op1() != nullptr, "fxch must be LIR_Op1");
6016     LIR_Op1* fxch1 = (LIR_Op1*)op1;
6017     LIR_Op1* fxch2 = (LIR_Op1*)op2;
6018     if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
6019       // equal FPU stack operations can be optimized
6020       return false;
6021     }
6022 
6023   } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
6024     // equal FPU stack operations can be optimized
6025     return false;
6026   }
6027 
6028   // no optimization possible
6029   return true;
6030 }
6031 
6032 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
6033   TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
6034 
6035   if (block->is_predecessor(block)) {
6036     // currently we can't handle this correctly.
6037     return;
6038   }
6039 
6040   init_instructions();
6041   int num_preds = block->number_of_preds();
6042   assert(num_preds > 1, "do not call otherwise");
6043   assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6044 
6045   // setup a list with the lir-instructions of all predecessors
6046   int i;
6047   for (i = 0; i < num_preds; i++) {
6048     BlockBegin* pred = block->pred_at(i);
6049     LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6050 
6051     if (pred->number_of_sux() != 1) {
6052       // this can happen with switch-statements where multiple edges are between
6053       // the same blocks.
6054       return;
6055     }
6056 
6057     assert(pred->number_of_sux() == 1, "can handle only one successor");
6058     assert(pred->sux_at(0) == block, "invalid control flow");
6059     assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6060     assert(pred_instructions->last()->as_OpBranch() != nullptr, "branch must be LIR_OpBranch");
6061     assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6062 
6063     if (pred_instructions->last()->info() != nullptr) {
6064       // can not optimize instructions when debug info is needed
6065       return;
6066     }
6067 
6068     // ignore the unconditional branch at the end of the block
6069     append_instructions(pred_instructions, pred_instructions->length() - 2);
6070   }
6071 
6072 
6073   // process lir-instructions while all predecessors end with the same instruction
6074   while (true) {
6075     LIR_Op* op = instruction_at(0);
6076     for (i = 1; i < num_preds; i++) {
6077       if (operations_different(op, instruction_at(i))) {
6078         // these instructions are different and cannot be optimized ->
6079         // no further optimization possible
6080         return;
6081       }
6082     }
6083 
6084     TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
6085 
6086     // insert the instruction at the beginning of the current block
6087     block->lir()->insert_before(1, op);
6088 
6089     // delete the instruction at the end of all predecessors
6090     for (i = 0; i < num_preds; i++) {
6091       remove_cur_instruction(i, true);
6092     }
6093   }
6094 }
6095 
6096 
6097 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
6098   TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
6099 
6100   init_instructions();
6101   int num_sux = block->number_of_sux();
6102 
6103   LIR_OpList* cur_instructions = block->lir()->instructions_list();
6104 
6105   assert(num_sux == 2, "method should not be called otherwise");
6106   assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6107   assert(cur_instructions->last()->as_OpBranch() != nullptr, "branch must be LIR_OpBranch");
6108   assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6109 
6110   if (cur_instructions->last()->info() != nullptr) {
6111     // can no optimize instructions when debug info is needed
6112     return;
6113   }
6114 
6115   LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
6116   if (branch->info() != nullptr || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
6117     // not a valid case for optimization
6118     // currently, only blocks that end with two branches (conditional branch followed
6119     // by unconditional branch) are optimized
6120     return;
6121   }
6122 
6123   // now it is guaranteed that the block ends with two branch instructions.
6124   // the instructions are inserted at the end of the block before these two branches
6125   int insert_idx = cur_instructions->length() - 2;
6126 
6127   int i;
6128 #ifdef ASSERT
6129   for (i = insert_idx - 1; i >= 0; i--) {
6130     LIR_Op* op = cur_instructions->at(i);
6131     if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != nullptr) {
6132       assert(false, "block with two successors can have only two branch instructions");
6133     }
6134   }
6135 #endif
6136 
6137   // setup a list with the lir-instructions of all successors
6138   for (i = 0; i < num_sux; i++) {
6139     BlockBegin* sux = block->sux_at(i);
6140     LIR_OpList* sux_instructions = sux->lir()->instructions_list();
6141 
6142     assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
6143 
6144     if (sux->number_of_preds() != 1) {
6145       // this can happen with switch-statements where multiple edges are between
6146       // the same blocks.
6147       return;
6148     }
6149     assert(sux->pred_at(0) == block, "invalid control flow");
6150     assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6151 
6152     // ignore the label at the beginning of the block
6153     append_instructions(sux_instructions, 1);
6154   }
6155 
6156   // process lir-instructions while all successors begin with the same instruction
6157   while (true) {
6158     LIR_Op* op = instruction_at(0);
6159     for (i = 1; i < num_sux; i++) {
6160       if (operations_different(op, instruction_at(i))) {
6161         // these instructions are different and cannot be optimized ->
6162         // no further optimization possible
6163         return;
6164       }
6165     }
6166 
6167     TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6168 
6169     // insert instruction at end of current block
6170     block->lir()->insert_before(insert_idx, op);
6171     insert_idx++;
6172 
6173     // delete the instructions at the beginning of all successors
6174     for (i = 0; i < num_sux; i++) {
6175       remove_cur_instruction(i, false);
6176     }
6177   }
6178 }
6179 
6180 
6181 // Implementation of ControlFlowOptimizer
6182 
6183 ControlFlowOptimizer::ControlFlowOptimizer() :
6184   _original_preds(4)
6185 {
6186 }
6187 
6188 void ControlFlowOptimizer::optimize(BlockList* code) {
6189   ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6190 
6191   // push the OSR entry block to the end so that we're not jumping over it.
6192   BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6193   if (osr_entry) {
6194     int index = osr_entry->linear_scan_number();
6195     assert(code->at(index) == osr_entry, "wrong index");
6196     code->remove_at(index);
6197     code->append(osr_entry);
6198   }
6199 
6200   optimizer.reorder_short_loops(code);
6201   optimizer.delete_empty_blocks(code);
6202   optimizer.delete_unnecessary_jumps(code);
6203   optimizer.delete_jumps_to_return(code);
6204 }
6205 
6206 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6207   int i = header_idx + 1;
6208   int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6209   while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6210     i++;
6211   }
6212 
6213   if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6214     int end_idx = i - 1;
6215     BlockBegin* end_block = code->at(end_idx);
6216 
6217     if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6218       // short loop from header_idx to end_idx found -> reorder blocks such that
6219       // the header_block is the last block instead of the first block of the loop
6220       TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6221                                          end_idx - header_idx + 1,
6222                                          header_block->block_id(), end_block->block_id()));
6223 
6224       for (int j = header_idx; j < end_idx; j++) {
6225         code->at_put(j, code->at(j + 1));
6226       }
6227       code->at_put(end_idx, header_block);
6228 
6229       // correct the flags so that any loop alignment occurs in the right place.
6230       assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6231       code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6232       code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6233     }
6234   }
6235 }
6236 
6237 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6238   for (int i = code->length() - 1; i >= 0; i--) {
6239     BlockBegin* block = code->at(i);
6240 
6241     if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6242       reorder_short_loop(code, block, i);
6243     }
6244   }
6245 
6246   DEBUG_ONLY(verify(code));
6247 }
6248 
6249 // only blocks with exactly one successor can be deleted. Such blocks
6250 // must always end with an unconditional branch to this successor
6251 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6252   if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6253     return false;
6254   }
6255 
6256   LIR_OpList* instructions = block->lir()->instructions_list();
6257 
6258   assert(instructions->length() >= 2, "block must have label and branch");
6259   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6260   assert(instructions->last()->as_OpBranch() != nullptr, "last instruction must always be a branch");
6261   assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6262   assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6263 
6264   // block must have exactly one successor
6265 
6266   if (instructions->length() == 2 && instructions->last()->info() == nullptr) {
6267     return true;
6268   }
6269   return false;
6270 }
6271 
6272 // substitute branch targets in all branch-instructions of this blocks
6273 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6274   TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6275 
6276   LIR_OpList* instructions = block->lir()->instructions_list();
6277 
6278   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6279   for (int i = instructions->length() - 1; i >= 1; i--) {
6280     LIR_Op* op = instructions->at(i);
6281 
6282     if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6283       assert(op->as_OpBranch() != nullptr, "branch must be of type LIR_OpBranch");
6284       LIR_OpBranch* branch = (LIR_OpBranch*)op;
6285 
6286       if (branch->block() == target_from) {
6287         branch->change_block(target_to);
6288       }
6289       if (branch->ublock() == target_from) {
6290         branch->change_ublock(target_to);
6291       }
6292     }
6293   }
6294 }
6295 
6296 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6297   int old_pos = 0;
6298   int new_pos = 0;
6299   int num_blocks = code->length();
6300 
6301   while (old_pos < num_blocks) {
6302     BlockBegin* block = code->at(old_pos);
6303 
6304     if (can_delete_block(block)) {
6305       BlockBegin* new_target = block->sux_at(0);
6306 
6307       // propagate backward branch target flag for correct code alignment
6308       if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6309         new_target->set(BlockBegin::backward_branch_target_flag);
6310       }
6311 
6312       // collect a list with all predecessors that contains each predecessor only once
6313       // the predecessors of cur are changed during the substitution, so a copy of the
6314       // predecessor list is necessary
6315       int j;
6316       _original_preds.clear();
6317       for (j = block->number_of_preds() - 1; j >= 0; j--) {
6318         BlockBegin* pred = block->pred_at(j);
6319         if (_original_preds.find(pred) == -1) {
6320           _original_preds.append(pred);
6321         }
6322       }
6323 
6324       for (j = _original_preds.length() - 1; j >= 0; j--) {
6325         BlockBegin* pred = _original_preds.at(j);
6326         substitute_branch_target(pred, block, new_target);
6327         pred->substitute_sux(block, new_target);
6328       }
6329     } else {
6330       // adjust position of this block in the block list if blocks before
6331       // have been deleted
6332       if (new_pos != old_pos) {
6333         code->at_put(new_pos, code->at(old_pos));
6334       }
6335       new_pos++;
6336     }
6337     old_pos++;
6338   }
6339   code->trunc_to(new_pos);
6340 
6341   DEBUG_ONLY(verify(code));
6342 }
6343 
6344 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6345   // skip the last block because there a branch is always necessary
6346   for (int i = code->length() - 2; i >= 0; i--) {
6347     BlockBegin* block = code->at(i);
6348     LIR_OpList* instructions = block->lir()->instructions_list();
6349 
6350     LIR_Op* last_op = instructions->last();
6351     if (last_op->code() == lir_branch) {
6352       assert(last_op->as_OpBranch() != nullptr, "branch must be of type LIR_OpBranch");
6353       LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6354 
6355       assert(last_branch->block() != nullptr, "last branch must always have a block as target");
6356       assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6357 
6358       if (last_branch->info() == nullptr) {
6359         if (last_branch->block() == code->at(i + 1)) {
6360 
6361           TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6362 
6363           // delete last branch instruction
6364           instructions->trunc_to(instructions->length() - 1);
6365 
6366         } else {
6367           LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6368           if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6369             assert(prev_op->as_OpBranch() != nullptr, "branch must be of type LIR_OpBranch");
6370             LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6371 
6372             if (prev_branch->stub() == nullptr) {
6373 
6374               LIR_Op2* prev_cmp = nullptr;
6375               // There might be a cmove inserted for profiling which depends on the same
6376               // compare. If we change the condition of the respective compare, we have
6377               // to take care of this cmove as well.
6378               LIR_Op4* prev_cmove = nullptr;
6379 
6380               for(int j = instructions->length() - 3; j >= 0 && prev_cmp == nullptr; j--) {
6381                 prev_op = instructions->at(j);
6382                 // check for the cmove
6383                 if (prev_op->code() == lir_cmove) {
6384                   assert(prev_op->as_Op4() != nullptr, "cmove must be of type LIR_Op4");
6385                   prev_cmove = (LIR_Op4*)prev_op;
6386                   assert(prev_branch->cond() == prev_cmove->condition(), "should be the same");
6387                 }
6388                 if (prev_op->code() == lir_cmp) {
6389                   assert(prev_op->as_Op2() != nullptr, "branch must be of type LIR_Op2");
6390                   prev_cmp = (LIR_Op2*)prev_op;
6391                   assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6392                 }
6393               }
6394               // Guarantee because it is dereferenced below.
6395               guarantee(prev_cmp != nullptr, "should have found comp instruction for branch");
6396               if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == nullptr) {
6397 
6398                 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6399 
6400                 // eliminate a conditional branch to the immediate successor
6401                 prev_branch->change_block(last_branch->block());
6402                 prev_branch->negate_cond();
6403                 prev_cmp->set_condition(prev_branch->cond());
6404                 instructions->trunc_to(instructions->length() - 1);
6405                 // if we do change the condition, we have to change the cmove as well
6406                 if (prev_cmove != nullptr) {
6407                   prev_cmove->set_condition(prev_branch->cond());
6408                   LIR_Opr t = prev_cmove->in_opr1();
6409                   prev_cmove->set_in_opr1(prev_cmove->in_opr2());
6410                   prev_cmove->set_in_opr2(t);
6411                 }
6412               }
6413             }
6414           }
6415         }
6416       }
6417     }
6418   }
6419 
6420   DEBUG_ONLY(verify(code));
6421 }
6422 
6423 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6424 #ifdef ASSERT
6425   ResourceBitMap return_converted(BlockBegin::number_of_blocks());
6426 #endif
6427 
6428   for (int i = code->length() - 1; i >= 0; i--) {
6429     BlockBegin* block = code->at(i);
6430     LIR_OpList* cur_instructions = block->lir()->instructions_list();
6431     LIR_Op*     cur_last_op = cur_instructions->last();
6432 
6433     assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6434     if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6435       // the block contains only a label and a return
6436       // if a predecessor ends with an unconditional jump to this block, then the jump
6437       // can be replaced with a return instruction
6438       //
6439       // Note: the original block with only a return statement cannot be deleted completely
6440       //       because the predecessors might have other (conditional) jumps to this block
6441       //       -> this may lead to unnecessary return instructions in the final code
6442 
6443       assert(cur_last_op->info() == nullptr, "return instructions do not have debug information");
6444       assert(block->number_of_sux() == 0 ||
6445              (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6446              "blocks that end with return must not have successors");
6447 
6448       assert(cur_last_op->as_Op1() != nullptr, "return must be LIR_Op1");
6449       LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6450 
6451       for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6452         BlockBegin* pred = block->pred_at(j);
6453         LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6454         LIR_Op*     pred_last_op = pred_instructions->last();
6455 
6456         if (pred_last_op->code() == lir_branch) {
6457           assert(pred_last_op->as_OpBranch() != nullptr, "branch must be LIR_OpBranch");
6458           LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6459 
6460           if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == nullptr) {
6461             // replace the jump to a return with a direct return
6462             // Note: currently the edge between the blocks is not deleted
6463             pred_instructions->at_put(pred_instructions->length() - 1, new LIR_OpReturn(return_opr));
6464 #ifdef ASSERT
6465             return_converted.set_bit(pred->block_id());
6466 #endif
6467           }
6468         }
6469       }
6470     }
6471   }
6472 }
6473 
6474 
6475 #ifdef ASSERT
6476 void ControlFlowOptimizer::verify(BlockList* code) {
6477   for (int i = 0; i < code->length(); i++) {
6478     BlockBegin* block = code->at(i);
6479     LIR_OpList* instructions = block->lir()->instructions_list();
6480 
6481     int j;
6482     for (j = 0; j < instructions->length(); j++) {
6483       LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6484 
6485       if (op_branch != nullptr) {
6486         assert(op_branch->block() == nullptr || code->find(op_branch->block()) != -1, "branch target not valid");
6487         assert(op_branch->ublock() == nullptr || code->find(op_branch->ublock()) != -1, "branch target not valid");
6488       }
6489     }
6490 
6491     for (j = 0; j < block->number_of_sux() - 1; j++) {
6492       BlockBegin* sux = block->sux_at(j);
6493       assert(code->find(sux) != -1, "successor not valid");
6494     }
6495 
6496     for (j = 0; j < block->number_of_preds() - 1; j++) {
6497       BlockBegin* pred = block->pred_at(j);
6498       assert(code->find(pred) != -1, "successor not valid");
6499     }
6500   }
6501 }
6502 #endif
6503 
6504 
6505 #ifndef PRODUCT
6506 
6507 // Implementation of LinearStatistic
6508 
6509 const char* LinearScanStatistic::counter_name(int counter_idx) {
6510   switch (counter_idx) {
6511     case counter_method:          return "compiled methods";
6512     case counter_fpu_method:      return "methods using fpu";
6513     case counter_loop_method:     return "methods with loops";
6514     case counter_exception_method:return "methods with xhandler";
6515 
6516     case counter_loop:            return "loops";
6517     case counter_block:           return "blocks";
6518     case counter_loop_block:      return "blocks inside loop";
6519     case counter_exception_block: return "exception handler entries";
6520     case counter_interval:        return "intervals";
6521     case counter_fixed_interval:  return "fixed intervals";
6522     case counter_range:           return "ranges";
6523     case counter_fixed_range:     return "fixed ranges";
6524     case counter_use_pos:         return "use positions";
6525     case counter_fixed_use_pos:   return "fixed use positions";
6526     case counter_spill_slots:     return "spill slots";
6527 
6528     // counter for classes of lir instructions
6529     case counter_instruction:     return "total instructions";
6530     case counter_label:           return "labels";
6531     case counter_entry:           return "method entries";
6532     case counter_return:          return "method returns";
6533     case counter_call:            return "method calls";
6534     case counter_move:            return "moves";
6535     case counter_cmp:             return "compare";
6536     case counter_cond_branch:     return "conditional branches";
6537     case counter_uncond_branch:   return "unconditional branches";
6538     case counter_stub_branch:     return "branches to stub";
6539     case counter_alu:             return "artithmetic + logic";
6540     case counter_alloc:           return "allocations";
6541     case counter_sync:            return "synchronisation";
6542     case counter_throw:           return "throw";
6543     case counter_unwind:          return "unwind";
6544     case counter_typecheck:       return "type+null-checks";
6545     case counter_fpu_stack:       return "fpu-stack";
6546     case counter_misc_inst:       return "other instructions";
6547     case counter_other_inst:      return "misc. instructions";
6548 
6549     // counter for different types of moves
6550     case counter_move_total:      return "total moves";
6551     case counter_move_reg_reg:    return "register->register";
6552     case counter_move_reg_stack:  return "register->stack";
6553     case counter_move_stack_reg:  return "stack->register";
6554     case counter_move_stack_stack:return "stack->stack";
6555     case counter_move_reg_mem:    return "register->memory";
6556     case counter_move_mem_reg:    return "memory->register";
6557     case counter_move_const_any:  return "constant->any";
6558 
6559     case blank_line_1:            return "";
6560     case blank_line_2:            return "";
6561 
6562     default: ShouldNotReachHere(); return "";
6563   }
6564 }
6565 
6566 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6567   if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6568     return counter_method;
6569   } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6570     return counter_block;
6571   } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6572     return counter_instruction;
6573   } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6574     return counter_move_total;
6575   }
6576   return invalid_counter;
6577 }
6578 
6579 LinearScanStatistic::LinearScanStatistic() {
6580   for (int i = 0; i < number_of_counters; i++) {
6581     _counters_sum[i] = 0;
6582     _counters_max[i] = -1;
6583   }
6584 
6585 }
6586 
6587 // add the method-local numbers to the total sum
6588 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6589   for (int i = 0; i < number_of_counters; i++) {
6590     _counters_sum[i] += method_statistic._counters_sum[i];
6591     _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6592   }
6593 }
6594 
6595 void LinearScanStatistic::print(const char* title) {
6596   if (CountLinearScan || TraceLinearScanLevel > 0) {
6597     tty->cr();
6598     tty->print_cr("***** LinearScan statistic - %s *****", title);
6599 
6600     for (int i = 0; i < number_of_counters; i++) {
6601       if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6602         tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6603 
6604         LinearScanStatistic::Counter cntr = base_counter(i);
6605         if (cntr != invalid_counter) {
6606           tty->print("  (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[cntr]);
6607         } else {
6608           tty->print("           ");
6609         }
6610 
6611         if (_counters_max[i] >= 0) {
6612           tty->print("%8d", _counters_max[i]);
6613         }
6614       }
6615       tty->cr();
6616     }
6617   }
6618 }
6619 
6620 void LinearScanStatistic::collect(LinearScan* allocator) {
6621   inc_counter(counter_method);
6622   if (allocator->has_fpu_registers()) {
6623     inc_counter(counter_fpu_method);
6624   }
6625   if (allocator->num_loops() > 0) {
6626     inc_counter(counter_loop_method);
6627   }
6628   inc_counter(counter_loop, allocator->num_loops());
6629   inc_counter(counter_spill_slots, allocator->max_spills());
6630 
6631   int i;
6632   for (i = 0; i < allocator->interval_count(); i++) {
6633     Interval* cur = allocator->interval_at(i);
6634 
6635     if (cur != nullptr) {
6636       inc_counter(counter_interval);
6637       inc_counter(counter_use_pos, cur->num_use_positions());
6638       if (LinearScan::is_precolored_interval(cur)) {
6639         inc_counter(counter_fixed_interval);
6640         inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6641       }
6642 
6643       Range* range = cur->first();
6644       while (range != Range::end()) {
6645         inc_counter(counter_range);
6646         if (LinearScan::is_precolored_interval(cur)) {
6647           inc_counter(counter_fixed_range);
6648         }
6649         range = range->next();
6650       }
6651     }
6652   }
6653 
6654   bool has_xhandlers = false;
6655   // Note: only count blocks that are in code-emit order
6656   for (i = 0; i < allocator->ir()->code()->length(); i++) {
6657     BlockBegin* cur = allocator->ir()->code()->at(i);
6658 
6659     inc_counter(counter_block);
6660     if (cur->loop_depth() > 0) {
6661       inc_counter(counter_loop_block);
6662     }
6663     if (cur->is_set(BlockBegin::exception_entry_flag)) {
6664       inc_counter(counter_exception_block);
6665       has_xhandlers = true;
6666     }
6667 
6668     LIR_OpList* instructions = cur->lir()->instructions_list();
6669     for (int j = 0; j < instructions->length(); j++) {
6670       LIR_Op* op = instructions->at(j);
6671 
6672       inc_counter(counter_instruction);
6673 
6674       switch (op->code()) {
6675         case lir_label:           inc_counter(counter_label); break;
6676         case lir_std_entry:
6677         case lir_osr_entry:       inc_counter(counter_entry); break;
6678         case lir_return:          inc_counter(counter_return); break;
6679 
6680         case lir_rtcall:
6681         case lir_static_call:
6682         case lir_optvirtual_call: inc_counter(counter_call); break;
6683 
6684         case lir_move: {
6685           inc_counter(counter_move);
6686           inc_counter(counter_move_total);
6687 
6688           LIR_Opr in = op->as_Op1()->in_opr();
6689           LIR_Opr res = op->as_Op1()->result_opr();
6690           if (in->is_register()) {
6691             if (res->is_register()) {
6692               inc_counter(counter_move_reg_reg);
6693             } else if (res->is_stack()) {
6694               inc_counter(counter_move_reg_stack);
6695             } else if (res->is_address()) {
6696               inc_counter(counter_move_reg_mem);
6697             } else {
6698               ShouldNotReachHere();
6699             }
6700           } else if (in->is_stack()) {
6701             if (res->is_register()) {
6702               inc_counter(counter_move_stack_reg);
6703             } else {
6704               inc_counter(counter_move_stack_stack);
6705             }
6706           } else if (in->is_address()) {
6707             assert(res->is_register(), "must be");
6708             inc_counter(counter_move_mem_reg);
6709           } else if (in->is_constant()) {
6710             inc_counter(counter_move_const_any);
6711           } else {
6712             ShouldNotReachHere();
6713           }
6714           break;
6715         }
6716 
6717         case lir_cmp:             inc_counter(counter_cmp); break;
6718 
6719         case lir_branch:
6720         case lir_cond_float_branch: {
6721           LIR_OpBranch* branch = op->as_OpBranch();
6722           if (branch->block() == nullptr) {
6723             inc_counter(counter_stub_branch);
6724           } else if (branch->cond() == lir_cond_always) {
6725             inc_counter(counter_uncond_branch);
6726           } else {
6727             inc_counter(counter_cond_branch);
6728           }
6729           break;
6730         }
6731 
6732         case lir_neg:
6733         case lir_add:
6734         case lir_sub:
6735         case lir_mul:
6736         case lir_div:
6737         case lir_rem:
6738         case lir_sqrt:
6739         case lir_abs:
6740         case lir_f2hf:
6741         case lir_hf2f:
6742         case lir_log10:
6743         case lir_logic_and:
6744         case lir_logic_or:
6745         case lir_logic_xor:
6746         case lir_shl:
6747         case lir_shr:
6748         case lir_ushr:            inc_counter(counter_alu); break;
6749 
6750         case lir_alloc_object:
6751         case lir_alloc_array:     inc_counter(counter_alloc); break;
6752 
6753         case lir_monaddr:
6754         case lir_lock:
6755         case lir_unlock:          inc_counter(counter_sync); break;
6756 
6757         case lir_throw:           inc_counter(counter_throw); break;
6758 
6759         case lir_unwind:          inc_counter(counter_unwind); break;
6760 
6761         case lir_null_check:
6762         case lir_leal:
6763         case lir_instanceof:
6764         case lir_checkcast:
6765         case lir_store_check:     inc_counter(counter_typecheck); break;
6766 
6767         case lir_fpop_raw:
6768         case lir_fxch:
6769         case lir_fld:             inc_counter(counter_fpu_stack); break;
6770 
6771         case lir_nop:
6772         case lir_push:
6773         case lir_pop:
6774         case lir_convert:
6775         case lir_roundfp:
6776         case lir_cmove:           inc_counter(counter_misc_inst); break;
6777 
6778         default:                  inc_counter(counter_other_inst); break;
6779       }
6780     }
6781   }
6782 
6783   if (has_xhandlers) {
6784     inc_counter(counter_exception_method);
6785   }
6786 }
6787 
6788 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6789   if (CountLinearScan || TraceLinearScanLevel > 0) {
6790 
6791     LinearScanStatistic local_statistic = LinearScanStatistic();
6792 
6793     local_statistic.collect(allocator);
6794     global_statistic.sum_up(local_statistic);
6795 
6796     if (TraceLinearScanLevel > 2) {
6797       local_statistic.print("current local statistic");
6798     }
6799   }
6800 }
6801 
6802 
6803 // Implementation of LinearTimers
6804 
6805 LinearScanTimers::LinearScanTimers() {
6806   for (int i = 0; i < number_of_timers; i++) {
6807     timer(i)->reset();
6808   }
6809 }
6810 
6811 const char* LinearScanTimers::timer_name(int idx) {
6812   switch (idx) {
6813     case timer_do_nothing:               return "Nothing (Time Check)";
6814     case timer_number_instructions:      return "Number Instructions";
6815     case timer_compute_local_live_sets:  return "Local Live Sets";
6816     case timer_compute_global_live_sets: return "Global Live Sets";
6817     case timer_build_intervals:          return "Build Intervals";
6818     case timer_sort_intervals_before:    return "Sort Intervals Before";
6819     case timer_allocate_registers:       return "Allocate Registers";
6820     case timer_resolve_data_flow:        return "Resolve Data Flow";
6821     case timer_sort_intervals_after:     return "Sort Intervals After";
6822     case timer_eliminate_spill_moves:    return "Spill optimization";
6823     case timer_assign_reg_num:           return "Assign Reg Num";
6824     case timer_allocate_fpu_stack:       return "Allocate FPU Stack";
6825     case timer_optimize_lir:             return "Optimize LIR";
6826     default: ShouldNotReachHere();       return "";
6827   }
6828 }
6829 
6830 void LinearScanTimers::begin_method() {
6831   if (TimeEachLinearScan) {
6832     // reset all timers to measure only current method
6833     for (int i = 0; i < number_of_timers; i++) {
6834       timer(i)->reset();
6835     }
6836   }
6837 }
6838 
6839 void LinearScanTimers::end_method(LinearScan* allocator) {
6840   if (TimeEachLinearScan) {
6841 
6842     double c = timer(timer_do_nothing)->seconds();
6843     double total = 0;
6844     for (int i = 1; i < number_of_timers; i++) {
6845       total += timer(i)->seconds() - c;
6846     }
6847 
6848     if (total >= 0.0005) {
6849       // print all information in one line for automatic processing
6850       tty->print("@"); allocator->compilation()->method()->print_name();
6851 
6852       tty->print("@ %d ", allocator->compilation()->method()->code_size());
6853       tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6854       tty->print("@ %d ", allocator->block_count());
6855       tty->print("@ %d ", allocator->num_virtual_regs());
6856       tty->print("@ %d ", allocator->interval_count());
6857       tty->print("@ %d ", allocator->_num_calls);
6858       tty->print("@ %d ", allocator->num_loops());
6859 
6860       tty->print("@ %6.6f ", total);
6861       for (int i = 1; i < number_of_timers; i++) {
6862         tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6863       }
6864       tty->cr();
6865     }
6866   }
6867 }
6868 
6869 void LinearScanTimers::print(double total_time) {
6870   if (TimeLinearScan) {
6871     // correction value: sum of dummy-timer that only measures the time that
6872     // is necessary to start and stop itself
6873     double c = timer(timer_do_nothing)->seconds();
6874 
6875     for (int i = 0; i < number_of_timers; i++) {
6876       double t = timer(i)->seconds();
6877       tty->print_cr("    %25s: %6.3f s (%4.1f%%)  corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6878     }
6879   }
6880 }
6881 
6882 #endif // #ifndef PRODUCT