1 /*
2 * Copyright (c) 2005, 2022, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "c1/c1_CFGPrinter.hpp"
27 #include "c1/c1_CodeStubs.hpp"
28 #include "c1/c1_Compilation.hpp"
29 #include "c1/c1_FrameMap.hpp"
30 #include "c1/c1_IR.hpp"
31 #include "c1/c1_LIRGenerator.hpp"
32 #include "c1/c1_LinearScan.hpp"
33 #include "c1/c1_ValueStack.hpp"
34 #include "code/vmreg.inline.hpp"
35 #include "runtime/timerTrace.hpp"
36 #include "utilities/bitMap.inline.hpp"
37
38 #ifndef PRODUCT
39
40 static LinearScanStatistic _stat_before_alloc;
41 static LinearScanStatistic _stat_after_asign;
42 static LinearScanStatistic _stat_final;
43
44 static LinearScanTimers _total_timer;
45
46 // helper macro for short definition of timer
47 #define TIME_LINEAR_SCAN(timer_name) TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
48
49 #else
50 #define TIME_LINEAR_SCAN(timer_name)
51 #endif
52
53 #ifdef ASSERT
54
55 // helper macro for short definition of trace-output inside code
56 #define TRACE_LINEAR_SCAN(level, code) \
57 if (TraceLinearScanLevel >= level) { \
58 code; \
59 }
60 #else
61 #define TRACE_LINEAR_SCAN(level, code)
62 #endif
63
64 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
65 #ifdef _LP64
66 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 2, 0, 2, 1, 2, 1, -1};
67 #else
68 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 1, 0, 1, -1, 1, 1, -1};
69 #endif
70
71
72 // Implementation of LinearScan
73
74 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
75 : _compilation(ir->compilation())
76 , _ir(ir)
77 , _gen(gen)
78 , _frame_map(frame_map)
79 , _cached_blocks(*ir->linear_scan_order())
80 , _num_virtual_regs(gen->max_virtual_register_number())
81 , _has_fpu_registers(false)
82 , _num_calls(-1)
83 , _max_spills(0)
84 , _unused_spill_slot(-1)
85 , _intervals(0) // initialized later with correct length
86 , _new_intervals_from_allocation(NULL)
87 , _sorted_intervals(NULL)
88 , _needs_full_resort(false)
89 , _lir_ops(0) // initialized later with correct length
90 , _block_of_op(0) // initialized later with correct length
91 , _has_info(0)
92 , _has_call(0)
93 , _interval_in_loop(0) // initialized later with correct length
94 , _scope_value_cache(0) // initialized later with correct length
95 #ifdef IA32
96 , _fpu_stack_allocator(NULL)
97 #endif
98 {
99 assert(this->ir() != NULL, "check if valid");
100 assert(this->compilation() != NULL, "check if valid");
101 assert(this->gen() != NULL, "check if valid");
102 assert(this->frame_map() != NULL, "check if valid");
103 }
104
105
106 // ********** functions for converting LIR-Operands to register numbers
107 //
108 // Emulate a flat register file comprising physical integer registers,
109 // physical floating-point registers and virtual registers, in that order.
110 // Virtual registers already have appropriate numbers, since V0 is
111 // the number of physical registers.
112 // Returns -1 for hi word if opr is a single word operand.
113 //
114 // Note: the inverse operation (calculating an operand for register numbers)
115 // is done in calc_operand_for_interval()
116
117 int LinearScan::reg_num(LIR_Opr opr) {
118 assert(opr->is_register(), "should not call this otherwise");
119
120 if (opr->is_virtual_register()) {
121 assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
122 return opr->vreg_number();
123 } else if (opr->is_single_cpu()) {
124 return opr->cpu_regnr();
125 } else if (opr->is_double_cpu()) {
126 return opr->cpu_regnrLo();
127 #ifdef X86
128 } else if (opr->is_single_xmm()) {
129 return opr->fpu_regnr() + pd_first_xmm_reg;
130 } else if (opr->is_double_xmm()) {
131 return opr->fpu_regnrLo() + pd_first_xmm_reg;
132 #endif
133 } else if (opr->is_single_fpu()) {
134 return opr->fpu_regnr() + pd_first_fpu_reg;
135 } else if (opr->is_double_fpu()) {
136 return opr->fpu_regnrLo() + pd_first_fpu_reg;
137 } else {
138 ShouldNotReachHere();
139 return -1;
140 }
141 }
142
143 int LinearScan::reg_numHi(LIR_Opr opr) {
144 assert(opr->is_register(), "should not call this otherwise");
145
146 if (opr->is_virtual_register()) {
147 return -1;
148 } else if (opr->is_single_cpu()) {
149 return -1;
150 } else if (opr->is_double_cpu()) {
151 return opr->cpu_regnrHi();
152 #ifdef X86
153 } else if (opr->is_single_xmm()) {
154 return -1;
155 } else if (opr->is_double_xmm()) {
156 return -1;
157 #endif
158 } else if (opr->is_single_fpu()) {
159 return -1;
160 } else if (opr->is_double_fpu()) {
161 return opr->fpu_regnrHi() + pd_first_fpu_reg;
162 } else {
163 ShouldNotReachHere();
164 return -1;
165 }
166 }
167
168
169 // ********** functions for classification of intervals
170
171 bool LinearScan::is_precolored_interval(const Interval* i) {
172 return i->reg_num() < LinearScan::nof_regs;
173 }
174
175 bool LinearScan::is_virtual_interval(const Interval* i) {
176 return i->reg_num() >= LIR_Opr::vreg_base;
177 }
178
179 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
180 return i->reg_num() < LinearScan::nof_cpu_regs;
181 }
182
183 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
184 #if defined(__SOFTFP__) || defined(E500V2)
185 return i->reg_num() >= LIR_Opr::vreg_base;
186 #else
187 return i->reg_num() >= LIR_Opr::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
188 #endif // __SOFTFP__ or E500V2
189 }
190
191 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
192 return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
193 }
194
195 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
196 #if defined(__SOFTFP__) || defined(E500V2)
197 return false;
198 #else
199 return i->reg_num() >= LIR_Opr::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
200 #endif // __SOFTFP__ or E500V2
201 }
202
203 bool LinearScan::is_in_fpu_register(const Interval* i) {
204 // fixed intervals not needed for FPU stack allocation
205 return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
206 }
207
208 bool LinearScan::is_oop_interval(const Interval* i) {
209 // fixed intervals never contain oops
210 return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
211 }
212
213
214 // ********** General helper functions
215
216 // compute next unused stack index that can be used for spilling
217 int LinearScan::allocate_spill_slot(bool double_word) {
218 int spill_slot;
219 if (double_word) {
220 if ((_max_spills & 1) == 1) {
221 // alignment of double-word values
222 // the hole because of the alignment is filled with the next single-word value
223 assert(_unused_spill_slot == -1, "wasting a spill slot");
224 _unused_spill_slot = _max_spills;
225 _max_spills++;
226 }
227 spill_slot = _max_spills;
228 _max_spills += 2;
229
230 } else if (_unused_spill_slot != -1) {
231 // re-use hole that was the result of a previous double-word alignment
232 spill_slot = _unused_spill_slot;
233 _unused_spill_slot = -1;
234
235 } else {
236 spill_slot = _max_spills;
237 _max_spills++;
238 }
239
240 int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
241
242 // if too many slots used, bailout compilation.
243 if (result > 2000) {
244 bailout("too many stack slots used");
245 }
246
247 return result;
248 }
249
250 void LinearScan::assign_spill_slot(Interval* it) {
251 // assign the canonical spill slot of the parent (if a part of the interval
252 // is already spilled) or allocate a new spill slot
253 if (it->canonical_spill_slot() >= 0) {
254 it->assign_reg(it->canonical_spill_slot());
255 } else {
256 int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
257 it->set_canonical_spill_slot(spill);
258 it->assign_reg(spill);
259 }
260 }
261
262 void LinearScan::propagate_spill_slots() {
263 if (!frame_map()->finalize_frame(max_spills(), compilation()->needs_stack_repair())) {
264 bailout("frame too large");
265 }
266 }
267
268 // create a new interval with a predefined reg_num
269 // (only used for parent intervals that are created during the building phase)
270 Interval* LinearScan::create_interval(int reg_num) {
271 assert(_intervals.at(reg_num) == NULL, "overwriting existing interval");
272
273 Interval* interval = new Interval(reg_num);
274 _intervals.at_put(reg_num, interval);
275
276 // assign register number for precolored intervals
277 if (reg_num < LIR_Opr::vreg_base) {
278 interval->assign_reg(reg_num);
279 }
280 return interval;
281 }
282
283 // assign a new reg_num to the interval and append it to the list of intervals
284 // (only used for child intervals that are created during register allocation)
285 void LinearScan::append_interval(Interval* it) {
286 it->set_reg_num(_intervals.length());
287 _intervals.append(it);
288 IntervalList* new_intervals = _new_intervals_from_allocation;
289 if (new_intervals == NULL) {
290 new_intervals = _new_intervals_from_allocation = new IntervalList();
291 }
292 new_intervals->append(it);
293 }
294
295 // copy the vreg-flags if an interval is split
296 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
297 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
298 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
299 }
300 if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
301 gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
302 }
303
304 // Note: do not copy the must_start_in_memory flag because it is not necessary for child
305 // intervals (only the very beginning of the interval must be in memory)
306 }
307
308
309 // ********** spill move optimization
310 // eliminate moves from register to stack if stack slot is known to be correct
311
312 // called during building of intervals
313 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
314 assert(interval->is_split_parent(), "can only be called for split parents");
315
316 switch (interval->spill_state()) {
317 case noDefinitionFound:
318 assert(interval->spill_definition_pos() == -1, "must no be set before");
319 interval->set_spill_definition_pos(def_pos);
320 interval->set_spill_state(oneDefinitionFound);
321 break;
322
323 case oneDefinitionFound:
324 assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
325 if (def_pos < interval->spill_definition_pos() - 2) {
326 // second definition found, so no spill optimization possible for this interval
327 interval->set_spill_state(noOptimization);
328 } else {
329 // two consecutive definitions (because of two-operand LIR form)
330 assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
331 }
332 break;
333
334 case noOptimization:
335 // nothing to do
336 break;
337
338 default:
339 assert(false, "other states not allowed at this time");
340 }
341 }
342
343 // called during register allocation
344 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
345 switch (interval->spill_state()) {
346 case oneDefinitionFound: {
347 int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
348 int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
349
350 if (def_loop_depth < spill_loop_depth) {
351 // the loop depth of the spilling position is higher then the loop depth
352 // at the definition of the interval -> move write to memory out of loop
353 // by storing at definitin of the interval
354 interval->set_spill_state(storeAtDefinition);
355 } else {
356 // the interval is currently spilled only once, so for now there is no
357 // reason to store the interval at the definition
358 interval->set_spill_state(oneMoveInserted);
359 }
360 break;
361 }
362
363 case oneMoveInserted: {
364 // the interval is spilled more then once, so it is better to store it to
365 // memory at the definition
366 interval->set_spill_state(storeAtDefinition);
367 break;
368 }
369
370 case storeAtDefinition:
371 case startInMemory:
372 case noOptimization:
373 case noDefinitionFound:
374 // nothing to do
375 break;
376
377 default:
378 assert(false, "other states not allowed at this time");
379 }
380 }
381
382
383 bool LinearScan::must_store_at_definition(const Interval* i) {
384 return i->is_split_parent() && i->spill_state() == storeAtDefinition;
385 }
386
387 // called once before assignment of register numbers
388 void LinearScan::eliminate_spill_moves() {
389 TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
390 TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
391
392 // collect all intervals that must be stored after their definion.
393 // the list is sorted by Interval::spill_definition_pos
394 Interval* interval;
395 Interval* temp_list;
396 create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
397
398 #ifdef ASSERT
399 Interval* prev = NULL;
400 Interval* temp = interval;
401 while (temp != Interval::end()) {
402 assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
403 if (prev != NULL) {
404 assert(temp->from() >= prev->from(), "intervals not sorted");
405 assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
406 }
407
408 assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
409 assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
410 assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
411
412 TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
413
414 temp = temp->next();
415 }
416 #endif
417
418 LIR_InsertionBuffer insertion_buffer;
419 int num_blocks = block_count();
420 for (int i = 0; i < num_blocks; i++) {
421 BlockBegin* block = block_at(i);
422 LIR_OpList* instructions = block->lir()->instructions_list();
423 int num_inst = instructions->length();
424 bool has_new = false;
425
426 // iterate all instructions of the block. skip the first because it is always a label
427 for (int j = 1; j < num_inst; j++) {
428 LIR_Op* op = instructions->at(j);
429 int op_id = op->id();
430
431 if (op_id == -1) {
432 // remove move from register to stack if the stack slot is guaranteed to be correct.
433 // only moves that have been inserted by LinearScan can be removed.
434 assert(op->code() == lir_move, "only moves can have a op_id of -1");
435 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
436 assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
437
438 LIR_Op1* op1 = (LIR_Op1*)op;
439 Interval* interval = interval_at(op1->result_opr()->vreg_number());
440
441 if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
442 // move target is a stack slot that is always correct, so eliminate instruction
443 TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
444 instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
445 }
446
447 } else {
448 // insert move from register to stack just after the beginning of the interval
449 assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
450 assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
451
452 while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
453 if (!has_new) {
454 // prepare insertion buffer (appended when all instructions of the block are processed)
455 insertion_buffer.init(block->lir());
456 has_new = true;
457 }
458
459 LIR_Opr from_opr = operand_for_interval(interval);
460 LIR_Opr to_opr = canonical_spill_opr(interval);
461 assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
462 assert(to_opr->is_stack(), "to operand must be a stack slot");
463
464 insertion_buffer.move(j, from_opr, to_opr);
465 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
466
467 interval = interval->next();
468 }
469 }
470 } // end of instruction iteration
471
472 if (has_new) {
473 block->lir()->append(&insertion_buffer);
474 }
475 } // end of block iteration
476
477 assert(interval == Interval::end(), "missed an interval");
478 }
479
480
481 // ********** Phase 1: number all instructions in all blocks
482 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
483
484 void LinearScan::number_instructions() {
485 {
486 // dummy-timer to measure the cost of the timer itself
487 // (this time is then subtracted from all other timers to get the real value)
488 TIME_LINEAR_SCAN(timer_do_nothing);
489 }
490 TIME_LINEAR_SCAN(timer_number_instructions);
491
492 // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
493 int num_blocks = block_count();
494 int num_instructions = 0;
495 int i;
496 for (i = 0; i < num_blocks; i++) {
497 num_instructions += block_at(i)->lir()->instructions_list()->length();
498 }
499
500 // initialize with correct length
501 _lir_ops = LIR_OpArray(num_instructions, num_instructions, NULL);
502 _block_of_op = BlockBeginArray(num_instructions, num_instructions, NULL);
503
504 int op_id = 0;
505 int idx = 0;
506
507 for (i = 0; i < num_blocks; i++) {
508 BlockBegin* block = block_at(i);
509 block->set_first_lir_instruction_id(op_id);
510 LIR_OpList* instructions = block->lir()->instructions_list();
511
512 int num_inst = instructions->length();
513 for (int j = 0; j < num_inst; j++) {
514 LIR_Op* op = instructions->at(j);
515 op->set_id(op_id);
516
517 _lir_ops.at_put(idx, op);
518 _block_of_op.at_put(idx, block);
519 assert(lir_op_with_id(op_id) == op, "must match");
520
521 idx++;
522 op_id += 2; // numbering of lir_ops by two
523 }
524 block->set_last_lir_instruction_id(op_id - 2);
525 }
526 assert(idx == num_instructions, "must match");
527 assert(idx * 2 == op_id, "must match");
528
529 _has_call.initialize(num_instructions);
530 _has_info.initialize(num_instructions);
531 }
532
533
534 // ********** Phase 2: compute local live sets separately for each block
535 // (sets live_gen and live_kill for each block)
536
537 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
538 LIR_Opr opr = value->operand();
539 Constant* con = value->as_Constant();
540
541 // check some asumptions about debug information
542 assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
543 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "assumption: Constant instructions have only constant operands");
544 assert(con != NULL || opr->is_virtual(), "assumption: non-Constant instructions have only virtual operands");
545
546 if ((con == NULL || con->is_pinned()) && opr->is_register()) {
547 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
548 int reg = opr->vreg_number();
549 if (!live_kill.at(reg)) {
550 live_gen.set_bit(reg);
551 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
552 }
553 }
554 }
555
556
557 void LinearScan::compute_local_live_sets() {
558 TIME_LINEAR_SCAN(timer_compute_local_live_sets);
559
560 int num_blocks = block_count();
561 int live_size = live_set_size();
562 bool local_has_fpu_registers = false;
563 int local_num_calls = 0;
564 LIR_OpVisitState visitor;
565
566 BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
567
568 // iterate all blocks
569 for (int i = 0; i < num_blocks; i++) {
570 BlockBegin* block = block_at(i);
571
572 ResourceBitMap live_gen(live_size);
573 ResourceBitMap live_kill(live_size);
574
575 if (block->is_set(BlockBegin::exception_entry_flag)) {
576 // Phi functions at the begin of an exception handler are
577 // implicitly defined (= killed) at the beginning of the block.
578 for_each_phi_fun(block, phi,
579 if (!phi->is_illegal()) { live_kill.set_bit(phi->operand()->vreg_number()); }
580 );
581 }
582
583 LIR_OpList* instructions = block->lir()->instructions_list();
584 int num_inst = instructions->length();
585
586 // iterate all instructions of the block. skip the first because it is always a label
587 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
588 for (int j = 1; j < num_inst; j++) {
589 LIR_Op* op = instructions->at(j);
590
591 // visit operation to collect all operands
592 visitor.visit(op);
593
594 if (visitor.has_call()) {
595 _has_call.set_bit(op->id() >> 1);
596 local_num_calls++;
597 }
598 if (visitor.info_count() > 0) {
599 _has_info.set_bit(op->id() >> 1);
600 }
601
602 // iterate input operands of instruction
603 int k, n, reg;
604 n = visitor.opr_count(LIR_OpVisitState::inputMode);
605 for (k = 0; k < n; k++) {
606 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
607 assert(opr->is_register(), "visitor should only return register operands");
608
609 if (opr->is_virtual_register()) {
610 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
611 reg = opr->vreg_number();
612 if (!live_kill.at(reg)) {
613 live_gen.set_bit(reg);
614 TRACE_LINEAR_SCAN(4, tty->print_cr(" Setting live_gen for register %d at instruction %d", reg, op->id()));
615 }
616 if (block->loop_index() >= 0) {
617 local_interval_in_loop.set_bit(reg, block->loop_index());
618 }
619 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
620 }
621
622 #ifdef ASSERT
623 // fixed intervals are never live at block boundaries, so
624 // they need not be processed in live sets.
625 // this is checked by these assertions to be sure about it.
626 // the entry block may have incoming values in registers, which is ok.
627 if (!opr->is_virtual_register() && block != ir()->start()) {
628 reg = reg_num(opr);
629 if (is_processed_reg_num(reg)) {
630 assert(live_kill.at(reg), "using fixed register that is not defined in this block");
631 }
632 reg = reg_numHi(opr);
633 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
634 assert(live_kill.at(reg), "using fixed register that is not defined in this block");
635 }
636 }
637 #endif
638 }
639
640 // Add uses of live locals from interpreter's point of view for proper debug information generation
641 n = visitor.info_count();
642 for (k = 0; k < n; k++) {
643 CodeEmitInfo* info = visitor.info_at(k);
644 ValueStack* stack = info->stack();
645 for_each_state_value(stack, value,
646 set_live_gen_kill(value, op, live_gen, live_kill);
647 local_has_fpu_registers = local_has_fpu_registers || value->type()->is_float_kind();
648 );
649 }
650
651 // iterate temp operands of instruction
652 n = visitor.opr_count(LIR_OpVisitState::tempMode);
653 for (k = 0; k < n; k++) {
654 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
655 assert(opr->is_register(), "visitor should only return register operands");
656
657 if (opr->is_virtual_register()) {
658 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
659 reg = opr->vreg_number();
660 live_kill.set_bit(reg);
661 if (block->loop_index() >= 0) {
662 local_interval_in_loop.set_bit(reg, block->loop_index());
663 }
664 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
665 }
666
667 #ifdef ASSERT
668 // fixed intervals are never live at block boundaries, so
669 // they need not be processed in live sets
670 // process them only in debug mode so that this can be checked
671 if (!opr->is_virtual_register()) {
672 reg = reg_num(opr);
673 if (is_processed_reg_num(reg)) {
674 live_kill.set_bit(reg_num(opr));
675 }
676 reg = reg_numHi(opr);
677 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
678 live_kill.set_bit(reg);
679 }
680 }
681 #endif
682 }
683
684 // iterate output operands of instruction
685 n = visitor.opr_count(LIR_OpVisitState::outputMode);
686 for (k = 0; k < n; k++) {
687 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
688 assert(opr->is_register(), "visitor should only return register operands");
689
690 if (opr->is_virtual_register()) {
691 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
692 reg = opr->vreg_number();
693 live_kill.set_bit(reg);
694 if (block->loop_index() >= 0) {
695 local_interval_in_loop.set_bit(reg, block->loop_index());
696 }
697 local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
698 }
699
700 #ifdef ASSERT
701 // fixed intervals are never live at block boundaries, so
702 // they need not be processed in live sets
703 // process them only in debug mode so that this can be checked
704 if (!opr->is_virtual_register()) {
705 reg = reg_num(opr);
706 if (is_processed_reg_num(reg)) {
707 live_kill.set_bit(reg_num(opr));
708 }
709 reg = reg_numHi(opr);
710 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
711 live_kill.set_bit(reg);
712 }
713 }
714 #endif
715 }
716 } // end of instruction iteration
717
718 block->set_live_gen (live_gen);
719 block->set_live_kill(live_kill);
720 block->set_live_in (ResourceBitMap(live_size));
721 block->set_live_out (ResourceBitMap(live_size));
722
723 TRACE_LINEAR_SCAN(4, tty->print("live_gen B%d ", block->block_id()); print_bitmap(block->live_gen()));
724 TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
725 } // end of block iteration
726
727 // propagate local calculated information into LinearScan object
728 _has_fpu_registers = local_has_fpu_registers;
729 compilation()->set_has_fpu_code(local_has_fpu_registers);
730
731 _num_calls = local_num_calls;
732 _interval_in_loop = local_interval_in_loop;
733 }
734
735
736 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
737 // (sets live_in and live_out for each block)
738
739 void LinearScan::compute_global_live_sets() {
740 TIME_LINEAR_SCAN(timer_compute_global_live_sets);
741
742 int num_blocks = block_count();
743 bool change_occurred;
744 bool change_occurred_in_block;
745 int iteration_count = 0;
746 ResourceBitMap live_out(live_set_size()); // scratch set for calculations
747
748 // Perform a backward dataflow analysis to compute live_out and live_in for each block.
749 // The loop is executed until a fixpoint is reached (no changes in an iteration)
750 // Exception handlers must be processed because not all live values are
751 // present in the state array, e.g. because of global value numbering
752 do {
753 change_occurred = false;
754
755 // iterate all blocks in reverse order
756 for (int i = num_blocks - 1; i >= 0; i--) {
757 BlockBegin* block = block_at(i);
758
759 change_occurred_in_block = false;
760
761 // live_out(block) is the union of live_in(sux), for successors sux of block
762 int n = block->number_of_sux();
763 int e = block->number_of_exception_handlers();
764 if (n + e > 0) {
765 // block has successors
766 if (n > 0) {
767 live_out.set_from(block->sux_at(0)->live_in());
768 for (int j = 1; j < n; j++) {
769 live_out.set_union(block->sux_at(j)->live_in());
770 }
771 } else {
772 live_out.clear();
773 }
774 for (int j = 0; j < e; j++) {
775 live_out.set_union(block->exception_handler_at(j)->live_in());
776 }
777
778 if (!block->live_out().is_same(live_out)) {
779 // A change occurred. Swap the old and new live out sets to avoid copying.
780 ResourceBitMap temp = block->live_out();
781 block->set_live_out(live_out);
782 live_out = temp;
783
784 change_occurred = true;
785 change_occurred_in_block = true;
786 }
787 }
788
789 if (iteration_count == 0 || change_occurred_in_block) {
790 // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
791 // note: live_in has to be computed only in first iteration or if live_out has changed!
792 ResourceBitMap live_in = block->live_in();
793 live_in.set_from(block->live_out());
794 live_in.set_difference(block->live_kill());
795 live_in.set_union(block->live_gen());
796 }
797
798 #ifdef ASSERT
799 if (TraceLinearScanLevel >= 4) {
800 char c = ' ';
801 if (iteration_count == 0 || change_occurred_in_block) {
802 c = '*';
803 }
804 tty->print("(%d) live_in%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
805 tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
806 }
807 #endif
808 }
809 iteration_count++;
810
811 if (change_occurred && iteration_count > 50) {
812 BAILOUT("too many iterations in compute_global_live_sets");
813 }
814 } while (change_occurred);
815
816
817 #ifdef ASSERT
818 // check that fixed intervals are not live at block boundaries
819 // (live set must be empty at fixed intervals)
820 for (int i = 0; i < num_blocks; i++) {
821 BlockBegin* block = block_at(i);
822 for (int j = 0; j < LIR_Opr::vreg_base; j++) {
823 assert(block->live_in().at(j) == false, "live_in set of fixed register must be empty");
824 assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
825 assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
826 }
827 }
828 #endif
829
830 // check that the live_in set of the first block is empty
831 ResourceBitMap live_in_args(ir()->start()->live_in().size());
832 if (!ir()->start()->live_in().is_same(live_in_args)) {
833 #ifdef ASSERT
834 tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
835 tty->print_cr("affected registers:");
836 print_bitmap(ir()->start()->live_in());
837
838 // print some additional information to simplify debugging
839 for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
840 if (ir()->start()->live_in().at(i)) {
841 Instruction* instr = gen()->instruction_for_vreg(i);
842 tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
843
844 for (int j = 0; j < num_blocks; j++) {
845 BlockBegin* block = block_at(j);
846 if (block->live_gen().at(i)) {
847 tty->print_cr(" used in block B%d", block->block_id());
848 }
849 if (block->live_kill().at(i)) {
850 tty->print_cr(" defined in block B%d", block->block_id());
851 }
852 }
853 }
854 }
855
856 #endif
857 // when this fails, virtual registers are used before they are defined.
858 assert(false, "live_in set of first block must be empty");
859 // bailout of if this occurs in product mode.
860 bailout("live_in set of first block not empty");
861 }
862 }
863
864
865 // ********** Phase 4: build intervals
866 // (fills the list _intervals)
867
868 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
869 assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
870 LIR_Opr opr = value->operand();
871 Constant* con = value->as_Constant();
872
873 if ((con == NULL || con->is_pinned()) && opr->is_register()) {
874 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
875 add_use(opr, from, to, use_kind);
876 }
877 }
878
879
880 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
881 TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
882 assert(opr->is_register(), "should not be called otherwise");
883
884 if (opr->is_virtual_register()) {
885 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
886 add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
887
888 } else {
889 int reg = reg_num(opr);
890 if (is_processed_reg_num(reg)) {
891 add_def(reg, def_pos, use_kind, opr->type_register());
892 }
893 reg = reg_numHi(opr);
894 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
895 add_def(reg, def_pos, use_kind, opr->type_register());
896 }
897 }
898 }
899
900 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
901 TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
902 assert(opr->is_register(), "should not be called otherwise");
903
904 if (opr->is_virtual_register()) {
905 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
906 add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
907
908 } else {
909 int reg = reg_num(opr);
910 if (is_processed_reg_num(reg)) {
911 add_use(reg, from, to, use_kind, opr->type_register());
912 }
913 reg = reg_numHi(opr);
914 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
915 add_use(reg, from, to, use_kind, opr->type_register());
916 }
917 }
918 }
919
920 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
921 TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
922 assert(opr->is_register(), "should not be called otherwise");
923
924 if (opr->is_virtual_register()) {
925 assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
926 add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
927
928 } else {
929 int reg = reg_num(opr);
930 if (is_processed_reg_num(reg)) {
931 add_temp(reg, temp_pos, use_kind, opr->type_register());
932 }
933 reg = reg_numHi(opr);
934 if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
935 add_temp(reg, temp_pos, use_kind, opr->type_register());
936 }
937 }
938 }
939
940
941 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
942 Interval* interval = interval_at(reg_num);
943 if (interval != NULL) {
944 assert(interval->reg_num() == reg_num, "wrong interval");
945
946 if (type != T_ILLEGAL) {
947 interval->set_type(type);
948 }
949
950 Range* r = interval->first();
951 if (r->from() <= def_pos) {
952 // Update the starting point (when a range is first created for a use, its
953 // start is the beginning of the current block until a def is encountered.)
954 r->set_from(def_pos);
955 interval->add_use_pos(def_pos, use_kind);
956
957 } else {
958 // Dead value - make vacuous interval
959 // also add use_kind for dead intervals
960 interval->add_range(def_pos, def_pos + 1);
961 interval->add_use_pos(def_pos, use_kind);
962 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
963 }
964
965 } else {
966 // Dead value - make vacuous interval
967 // also add use_kind for dead intervals
968 interval = create_interval(reg_num);
969 if (type != T_ILLEGAL) {
970 interval->set_type(type);
971 }
972
973 interval->add_range(def_pos, def_pos + 1);
974 interval->add_use_pos(def_pos, use_kind);
975 TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
976 }
977
978 change_spill_definition_pos(interval, def_pos);
979 if (use_kind == noUse && interval->spill_state() <= startInMemory) {
980 // detection of method-parameters and roundfp-results
981 // TODO: move this directly to position where use-kind is computed
982 interval->set_spill_state(startInMemory);
983 }
984 }
985
986 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
987 Interval* interval = interval_at(reg_num);
988 if (interval == NULL) {
989 interval = create_interval(reg_num);
990 }
991 assert(interval->reg_num() == reg_num, "wrong interval");
992
993 if (type != T_ILLEGAL) {
994 interval->set_type(type);
995 }
996
997 interval->add_range(from, to);
998 interval->add_use_pos(to, use_kind);
999 }
1000
1001 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1002 Interval* interval = interval_at(reg_num);
1003 if (interval == NULL) {
1004 interval = create_interval(reg_num);
1005 }
1006 assert(interval->reg_num() == reg_num, "wrong interval");
1007
1008 if (type != T_ILLEGAL) {
1009 interval->set_type(type);
1010 }
1011
1012 interval->add_range(temp_pos, temp_pos + 1);
1013 interval->add_use_pos(temp_pos, use_kind);
1014 }
1015
1016
1017 // the results of this functions are used for optimizing spilling and reloading
1018 // if the functions return shouldHaveRegister and the interval is spilled,
1019 // it is not reloaded to a register.
1020 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1021 if (op->code() == lir_move) {
1022 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1023 LIR_Op1* move = (LIR_Op1*)op;
1024 LIR_Opr res = move->result_opr();
1025 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1026
1027 if (result_in_memory) {
1028 // Begin of an interval with must_start_in_memory set.
1029 // This interval will always get a stack slot first, so return noUse.
1030 return noUse;
1031
1032 } else if (move->in_opr()->is_stack()) {
1033 // method argument (condition must be equal to handle_method_arguments)
1034 return noUse;
1035
1036 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1037 // Move from register to register
1038 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1039 // special handling of phi-function moves inside osr-entry blocks
1040 // input operand must have a register instead of output operand (leads to better register allocation)
1041 return shouldHaveRegister;
1042 }
1043 }
1044 }
1045
1046 if (opr->is_virtual() &&
1047 gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1048 // result is a stack-slot, so prevent immediate reloading
1049 return noUse;
1050 }
1051
1052 // all other operands require a register
1053 return mustHaveRegister;
1054 }
1055
1056 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1057 if (op->code() == lir_move) {
1058 assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1059 LIR_Op1* move = (LIR_Op1*)op;
1060 LIR_Opr res = move->result_opr();
1061 bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1062
1063 if (result_in_memory) {
1064 // Move to an interval with must_start_in_memory set.
1065 // To avoid moves from stack to stack (not allowed) force the input operand to a register
1066 return mustHaveRegister;
1067
1068 } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1069 // Move from register to register
1070 if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1071 // special handling of phi-function moves inside osr-entry blocks
1072 // input operand must have a register instead of output operand (leads to better register allocation)
1073 return mustHaveRegister;
1074 }
1075
1076 // The input operand is not forced to a register (moves from stack to register are allowed),
1077 // but it is faster if the input operand is in a register
1078 return shouldHaveRegister;
1079 }
1080 }
1081
1082
1083 #if defined(X86) || defined(S390)
1084 if (op->code() == lir_cmove) {
1085 // conditional moves can handle stack operands
1086 assert(op->result_opr()->is_register(), "result must always be in a register");
1087 return shouldHaveRegister;
1088 }
1089
1090 // optimizations for second input operand of arithmehtic operations on Intel
1091 // this operand is allowed to be on the stack in some cases
1092 BasicType opr_type = opr->type_register();
1093 if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1094 if (IA32_ONLY( (UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 ) NOT_IA32( true )) {
1095 // SSE float instruction (T_DOUBLE only supported with SSE2)
1096 switch (op->code()) {
1097 case lir_cmp:
1098 case lir_add:
1099 case lir_sub:
1100 case lir_mul:
1101 case lir_div:
1102 {
1103 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1104 LIR_Op2* op2 = (LIR_Op2*)op;
1105 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1106 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1107 return shouldHaveRegister;
1108 }
1109 }
1110 default:
1111 break;
1112 }
1113 } else {
1114 // FPU stack float instruction
1115 switch (op->code()) {
1116 case lir_add:
1117 case lir_sub:
1118 case lir_mul:
1119 case lir_div:
1120 {
1121 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1122 LIR_Op2* op2 = (LIR_Op2*)op;
1123 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1124 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1125 return shouldHaveRegister;
1126 }
1127 }
1128 default:
1129 break;
1130 }
1131 }
1132 // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1133 // Since 64bit logical operations do not current support operands on stack, we have to make sure
1134 // T_OBJECT doesn't get spilled along with T_LONG.
1135 } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1136 // integer instruction (note: long operands must always be in register)
1137 switch (op->code()) {
1138 case lir_cmp:
1139 case lir_add:
1140 case lir_sub:
1141 case lir_logic_and:
1142 case lir_logic_or:
1143 case lir_logic_xor:
1144 {
1145 assert(op->as_Op2() != NULL, "must be LIR_Op2");
1146 LIR_Op2* op2 = (LIR_Op2*)op;
1147 if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1148 assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1149 return shouldHaveRegister;
1150 }
1151 }
1152 default:
1153 break;
1154 }
1155 }
1156 #endif // X86 || S390
1157
1158 // all other operands require a register
1159 return mustHaveRegister;
1160 }
1161
1162
1163 void LinearScan::handle_method_arguments(LIR_Op* op) {
1164 // special handling for method arguments (moves from stack to virtual register):
1165 // the interval gets no register assigned, but the stack slot.
1166 // it is split before the first use by the register allocator.
1167
1168 if (op->code() == lir_move) {
1169 assert(op->as_Op1() != NULL, "must be LIR_Op1");
1170 LIR_Op1* move = (LIR_Op1*)op;
1171
1172 if (move->in_opr()->is_stack()) {
1173 #ifdef ASSERT
1174 int arg_size = compilation()->method()->arg_size();
1175 LIR_Opr o = move->in_opr();
1176 if (o->is_single_stack()) {
1177 assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1178 } else if (o->is_double_stack()) {
1179 assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1180 } else {
1181 ShouldNotReachHere();
1182 }
1183
1184 assert(move->id() > 0, "invalid id");
1185 assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1186 assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1187
1188 TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1189 #endif
1190
1191 Interval* interval = interval_at(reg_num(move->result_opr()));
1192
1193 int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1194 interval->set_canonical_spill_slot(stack_slot);
1195 interval->assign_reg(stack_slot);
1196 }
1197 }
1198 }
1199
1200 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1201 // special handling for doubleword move from memory to register:
1202 // in this case the registers of the input address and the result
1203 // registers must not overlap -> add a temp range for the input registers
1204 if (op->code() == lir_move) {
1205 assert(op->as_Op1() != NULL, "must be LIR_Op1");
1206 LIR_Op1* move = (LIR_Op1*)op;
1207
1208 if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1209 LIR_Address* address = move->in_opr()->as_address_ptr();
1210 if (address != NULL) {
1211 if (address->base()->is_valid()) {
1212 add_temp(address->base(), op->id(), noUse);
1213 }
1214 if (address->index()->is_valid()) {
1215 add_temp(address->index(), op->id(), noUse);
1216 }
1217 }
1218 }
1219 }
1220 }
1221
1222 void LinearScan::add_register_hints(LIR_Op* op) {
1223 switch (op->code()) {
1224 case lir_move: // fall through
1225 case lir_convert: {
1226 assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1227 LIR_Op1* move = (LIR_Op1*)op;
1228
1229 LIR_Opr move_from = move->in_opr();
1230 LIR_Opr move_to = move->result_opr();
1231
1232 if (move_to->is_register() && move_from->is_register()) {
1233 Interval* from = interval_at(reg_num(move_from));
1234 Interval* to = interval_at(reg_num(move_to));
1235 if (from != NULL && to != NULL) {
1236 to->set_register_hint(from);
1237 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1238 }
1239 }
1240 break;
1241 }
1242 case lir_cmove: {
1243 assert(op->as_Op4() != NULL, "lir_cmove must be LIR_Op4");
1244 LIR_Op4* cmove = (LIR_Op4*)op;
1245
1246 LIR_Opr move_from = cmove->in_opr1();
1247 LIR_Opr move_to = cmove->result_opr();
1248
1249 if (move_to->is_register() && move_from->is_register()) {
1250 Interval* from = interval_at(reg_num(move_from));
1251 Interval* to = interval_at(reg_num(move_to));
1252 if (from != NULL && to != NULL) {
1253 to->set_register_hint(from);
1254 TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1255 }
1256 }
1257 break;
1258 }
1259 default:
1260 break;
1261 }
1262 }
1263
1264
1265 void LinearScan::build_intervals() {
1266 TIME_LINEAR_SCAN(timer_build_intervals);
1267
1268 // initialize interval list with expected number of intervals
1269 // (32 is added to have some space for split children without having to resize the list)
1270 _intervals = IntervalList(num_virtual_regs() + 32);
1271 // initialize all slots that are used by build_intervals
1272 _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1273
1274 // create a list with all caller-save registers (cpu, fpu, xmm)
1275 // when an instruction is a call, a temp range is created for all these registers
1276 int num_caller_save_registers = 0;
1277 int caller_save_registers[LinearScan::nof_regs];
1278
1279 int i;
1280 for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1281 LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1282 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1283 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1284 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1285 }
1286
1287 // temp ranges for fpu registers are only created when the method has
1288 // virtual fpu operands. Otherwise no allocation for fpu registers is
1289 // performed and so the temp ranges would be useless
1290 if (has_fpu_registers()) {
1291 #ifdef X86
1292 if (UseSSE < 2) {
1293 #endif // X86
1294 for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1295 LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1296 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1297 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1298 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1299 }
1300 #ifdef X86
1301 }
1302 #endif // X86
1303
1304 #ifdef X86
1305 if (UseSSE > 0) {
1306 int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
1307 for (i = 0; i < num_caller_save_xmm_regs; i ++) {
1308 LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1309 assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1310 assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1311 caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1312 }
1313 }
1314 #endif // X86
1315 }
1316 assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1317
1318
1319 LIR_OpVisitState visitor;
1320
1321 // iterate all blocks in reverse order
1322 for (i = block_count() - 1; i >= 0; i--) {
1323 BlockBegin* block = block_at(i);
1324 LIR_OpList* instructions = block->lir()->instructions_list();
1325 int block_from = block->first_lir_instruction_id();
1326 int block_to = block->last_lir_instruction_id();
1327
1328 assert(block_from == instructions->at(0)->id(), "must be");
1329 assert(block_to == instructions->at(instructions->length() - 1)->id(), "must be");
1330
1331 // Update intervals for registers live at the end of this block;
1332 ResourceBitMap live = block->live_out();
1333 int size = (int)live.size();
1334 for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1335 assert(live.at(number), "should not stop here otherwise");
1336 assert(number >= LIR_Opr::vreg_base, "fixed intervals must not be live on block bounds");
1337 TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1338
1339 add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1340
1341 // add special use positions for loop-end blocks when the
1342 // interval is used anywhere inside this loop. It's possible
1343 // that the block was part of a non-natural loop, so it might
1344 // have an invalid loop index.
1345 if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1346 block->loop_index() != -1 &&
1347 is_interval_in_loop(number, block->loop_index())) {
1348 interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1349 }
1350 }
1351
1352 // iterate all instructions of the block in reverse order.
1353 // skip the first instruction because it is always a label
1354 // definitions of intervals are processed before uses
1355 assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1356 for (int j = instructions->length() - 1; j >= 1; j--) {
1357 LIR_Op* op = instructions->at(j);
1358 int op_id = op->id();
1359
1360 // visit operation to collect all operands
1361 visitor.visit(op);
1362
1363 // add a temp range for each register if operation destroys caller-save registers
1364 if (visitor.has_call()) {
1365 for (int k = 0; k < num_caller_save_registers; k++) {
1366 add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1367 }
1368 TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1369 }
1370
1371 // Add any platform dependent temps
1372 pd_add_temps(op);
1373
1374 // visit definitions (output and temp operands)
1375 int k, n;
1376 n = visitor.opr_count(LIR_OpVisitState::outputMode);
1377 for (k = 0; k < n; k++) {
1378 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1379 assert(opr->is_register(), "visitor should only return register operands");
1380 add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1381 }
1382
1383 n = visitor.opr_count(LIR_OpVisitState::tempMode);
1384 for (k = 0; k < n; k++) {
1385 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1386 assert(opr->is_register(), "visitor should only return register operands");
1387 add_temp(opr, op_id, mustHaveRegister);
1388 }
1389
1390 // visit uses (input operands)
1391 n = visitor.opr_count(LIR_OpVisitState::inputMode);
1392 for (k = 0; k < n; k++) {
1393 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1394 assert(opr->is_register(), "visitor should only return register operands");
1395 add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1396 }
1397
1398 // Add uses of live locals from interpreter's point of view for proper
1399 // debug information generation
1400 // Treat these operands as temp values (if the life range is extended
1401 // to a call site, the value would be in a register at the call otherwise)
1402 n = visitor.info_count();
1403 for (k = 0; k < n; k++) {
1404 CodeEmitInfo* info = visitor.info_at(k);
1405 ValueStack* stack = info->stack();
1406 for_each_state_value(stack, value,
1407 add_use(value, block_from, op_id + 1, noUse);
1408 );
1409 }
1410
1411 // special steps for some instructions (especially moves)
1412 handle_method_arguments(op);
1413 handle_doubleword_moves(op);
1414 add_register_hints(op);
1415
1416 } // end of instruction iteration
1417 } // end of block iteration
1418
1419
1420 // add the range [0, 1[ to all fixed intervals
1421 // -> the register allocator need not handle unhandled fixed intervals
1422 for (int n = 0; n < LinearScan::nof_regs; n++) {
1423 Interval* interval = interval_at(n);
1424 if (interval != NULL) {
1425 interval->add_range(0, 1);
1426 }
1427 }
1428 }
1429
1430
1431 // ********** Phase 5: actual register allocation
1432
1433 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1434 if (*a != NULL) {
1435 if (*b != NULL) {
1436 return (*a)->from() - (*b)->from();
1437 } else {
1438 return -1;
1439 }
1440 } else {
1441 if (*b != NULL) {
1442 return 1;
1443 } else {
1444 return 0;
1445 }
1446 }
1447 }
1448
1449 #ifndef PRODUCT
1450 int interval_cmp(Interval* const& l, Interval* const& r) {
1451 return l->from() - r->from();
1452 }
1453
1454 bool find_interval(Interval* interval, IntervalArray* intervals) {
1455 bool found;
1456 int idx = intervals->find_sorted<Interval*, interval_cmp>(interval, found);
1457
1458 if (!found) {
1459 return false;
1460 }
1461
1462 int from = interval->from();
1463
1464 // The index we've found using binary search is pointing to an interval
1465 // that is defined in the same place as the interval we were looking for.
1466 // So now we have to look around that index and find exact interval.
1467 for (int i = idx; i >= 0; i--) {
1468 if (intervals->at(i) == interval) {
1469 return true;
1470 }
1471 if (intervals->at(i)->from() != from) {
1472 break;
1473 }
1474 }
1475
1476 for (int i = idx + 1; i < intervals->length(); i++) {
1477 if (intervals->at(i) == interval) {
1478 return true;
1479 }
1480 if (intervals->at(i)->from() != from) {
1481 break;
1482 }
1483 }
1484
1485 return false;
1486 }
1487
1488 bool LinearScan::is_sorted(IntervalArray* intervals) {
1489 int from = -1;
1490 int null_count = 0;
1491
1492 for (int i = 0; i < intervals->length(); i++) {
1493 Interval* it = intervals->at(i);
1494 if (it != NULL) {
1495 assert(from <= it->from(), "Intervals are unordered");
1496 from = it->from();
1497 } else {
1498 null_count++;
1499 }
1500 }
1501
1502 assert(null_count == 0, "Sorted intervals should not contain nulls");
1503
1504 null_count = 0;
1505
1506 for (int i = 0; i < interval_count(); i++) {
1507 Interval* interval = interval_at(i);
1508 if (interval != NULL) {
1509 assert(find_interval(interval, intervals), "Lists do not contain same intervals");
1510 } else {
1511 null_count++;
1512 }
1513 }
1514
1515 assert(interval_count() - null_count == intervals->length(),
1516 "Sorted list should contain the same amount of non-NULL intervals as unsorted list");
1517
1518 return true;
1519 }
1520 #endif
1521
1522 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1523 if (*prev != NULL) {
1524 (*prev)->set_next(interval);
1525 } else {
1526 *first = interval;
1527 }
1528 *prev = interval;
1529 }
1530
1531 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1532 assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1533
1534 *list1 = *list2 = Interval::end();
1535
1536 Interval* list1_prev = NULL;
1537 Interval* list2_prev = NULL;
1538 Interval* v;
1539
1540 const int n = _sorted_intervals->length();
1541 for (int i = 0; i < n; i++) {
1542 v = _sorted_intervals->at(i);
1543 if (v == NULL) continue;
1544
1545 if (is_list1(v)) {
1546 add_to_list(list1, &list1_prev, v);
1547 } else if (is_list2 == NULL || is_list2(v)) {
1548 add_to_list(list2, &list2_prev, v);
1549 }
1550 }
1551
1552 if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1553 if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1554
1555 assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1556 assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1557 }
1558
1559
1560 void LinearScan::sort_intervals_before_allocation() {
1561 TIME_LINEAR_SCAN(timer_sort_intervals_before);
1562
1563 if (_needs_full_resort) {
1564 // There is no known reason why this should occur but just in case...
1565 assert(false, "should never occur");
1566 // Re-sort existing interval list because an Interval::from() has changed
1567 _sorted_intervals->sort(interval_cmp);
1568 _needs_full_resort = false;
1569 }
1570
1571 IntervalList* unsorted_list = &_intervals;
1572 int unsorted_len = unsorted_list->length();
1573 int sorted_len = 0;
1574 int unsorted_idx;
1575 int sorted_idx = 0;
1576 int sorted_from_max = -1;
1577
1578 // calc number of items for sorted list (sorted list must not contain NULL values)
1579 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1580 if (unsorted_list->at(unsorted_idx) != NULL) {
1581 sorted_len++;
1582 }
1583 }
1584 IntervalArray* sorted_list = new IntervalArray(sorted_len, sorted_len, NULL);
1585
1586 // special sorting algorithm: the original interval-list is almost sorted,
1587 // only some intervals are swapped. So this is much faster than a complete QuickSort
1588 for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1589 Interval* cur_interval = unsorted_list->at(unsorted_idx);
1590
1591 if (cur_interval != NULL) {
1592 int cur_from = cur_interval->from();
1593
1594 if (sorted_from_max <= cur_from) {
1595 sorted_list->at_put(sorted_idx++, cur_interval);
1596 sorted_from_max = cur_interval->from();
1597 } else {
1598 // the assumption that the intervals are already sorted failed,
1599 // so this interval must be sorted in manually
1600 int j;
1601 for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1602 sorted_list->at_put(j + 1, sorted_list->at(j));
1603 }
1604 sorted_list->at_put(j + 1, cur_interval);
1605 sorted_idx++;
1606 }
1607 }
1608 }
1609 _sorted_intervals = sorted_list;
1610 assert(is_sorted(_sorted_intervals), "intervals unsorted");
1611 }
1612
1613 void LinearScan::sort_intervals_after_allocation() {
1614 TIME_LINEAR_SCAN(timer_sort_intervals_after);
1615
1616 if (_needs_full_resort) {
1617 // Re-sort existing interval list because an Interval::from() has changed
1618 _sorted_intervals->sort(interval_cmp);
1619 _needs_full_resort = false;
1620 }
1621
1622 IntervalArray* old_list = _sorted_intervals;
1623 IntervalList* new_list = _new_intervals_from_allocation;
1624 int old_len = old_list->length();
1625 int new_len = new_list == NULL ? 0 : new_list->length();
1626
1627 if (new_len == 0) {
1628 // no intervals have been added during allocation, so sorted list is already up to date
1629 assert(is_sorted(_sorted_intervals), "intervals unsorted");
1630 return;
1631 }
1632
1633 // conventional sort-algorithm for new intervals
1634 new_list->sort(interval_cmp);
1635
1636 // merge old and new list (both already sorted) into one combined list
1637 int combined_list_len = old_len + new_len;
1638 IntervalArray* combined_list = new IntervalArray(combined_list_len, combined_list_len, NULL);
1639 int old_idx = 0;
1640 int new_idx = 0;
1641
1642 while (old_idx + new_idx < old_len + new_len) {
1643 if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1644 combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1645 old_idx++;
1646 } else {
1647 combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1648 new_idx++;
1649 }
1650 }
1651
1652 _sorted_intervals = combined_list;
1653 assert(is_sorted(_sorted_intervals), "intervals unsorted");
1654 }
1655
1656
1657 void LinearScan::allocate_registers() {
1658 TIME_LINEAR_SCAN(timer_allocate_registers);
1659
1660 Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1661 Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1662
1663 // collect cpu intervals
1664 create_unhandled_lists(&precolored_cpu_intervals, ¬_precolored_cpu_intervals,
1665 is_precolored_cpu_interval, is_virtual_cpu_interval);
1666
1667 // collect fpu intervals
1668 create_unhandled_lists(&precolored_fpu_intervals, ¬_precolored_fpu_intervals,
1669 is_precolored_fpu_interval, is_virtual_fpu_interval);
1670 // this fpu interval collection cannot be moved down below with the allocation section as
1671 // the cpu_lsw.walk() changes interval positions.
1672
1673 if (!has_fpu_registers()) {
1674 #ifdef ASSERT
1675 assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval");
1676 #else
1677 if (not_precolored_fpu_intervals != Interval::end()) {
1678 BAILOUT("missed an uncolored fpu interval");
1679 }
1680 #endif
1681 }
1682
1683 // allocate cpu registers
1684 LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1685 cpu_lsw.walk();
1686 cpu_lsw.finish_allocation();
1687
1688 if (has_fpu_registers()) {
1689 // allocate fpu registers
1690 LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1691 fpu_lsw.walk();
1692 fpu_lsw.finish_allocation();
1693 }
1694 }
1695
1696
1697 // ********** Phase 6: resolve data flow
1698 // (insert moves at edges between blocks if intervals have been split)
1699
1700 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1701 // instead of returning NULL
1702 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1703 Interval* result = interval->split_child_at_op_id(op_id, mode);
1704 if (result != NULL) {
1705 return result;
1706 }
1707
1708 assert(false, "must find an interval, but do a clean bailout in product mode");
1709 result = new Interval(LIR_Opr::vreg_base);
1710 result->assign_reg(0);
1711 result->set_type(T_INT);
1712 BAILOUT_("LinearScan: interval is NULL", result);
1713 }
1714
1715
1716 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1717 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1718 assert(interval_at(reg_num) != NULL, "no interval found");
1719
1720 return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1721 }
1722
1723 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1724 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1725 assert(interval_at(reg_num) != NULL, "no interval found");
1726
1727 return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1728 }
1729
1730 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1731 assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1732 assert(interval_at(reg_num) != NULL, "no interval found");
1733
1734 return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1735 }
1736
1737
1738 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1739 DEBUG_ONLY(move_resolver.check_empty());
1740
1741 const int size = live_set_size();
1742 const ResourceBitMap live_at_edge = to_block->live_in();
1743
1744 // visit all registers where the live_at_edge bit is set
1745 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1746 assert(r < num_virtual_regs(), "live information set for not existing interval");
1747 assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1748
1749 Interval* from_interval = interval_at_block_end(from_block, r);
1750 Interval* to_interval = interval_at_block_begin(to_block, r);
1751
1752 if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1753 // need to insert move instruction
1754 move_resolver.add_mapping(from_interval, to_interval);
1755 }
1756 }
1757 }
1758
1759
1760 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1761 if (from_block->number_of_sux() <= 1) {
1762 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1763
1764 LIR_OpList* instructions = from_block->lir()->instructions_list();
1765 LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1766 if (branch != NULL) {
1767 // insert moves before branch
1768 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1769 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1770 } else {
1771 move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1772 }
1773
1774 } else {
1775 TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1776 #ifdef ASSERT
1777 assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1778
1779 // because the number of predecessor edges matches the number of
1780 // successor edges, blocks which are reached by switch statements
1781 // may have be more than one predecessor but it will be guaranteed
1782 // that all predecessors will be the same.
1783 for (int i = 0; i < to_block->number_of_preds(); i++) {
1784 assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1785 }
1786 #endif
1787
1788 move_resolver.set_insert_position(to_block->lir(), 0);
1789 }
1790 }
1791
1792
1793 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1794 void LinearScan::resolve_data_flow() {
1795 TIME_LINEAR_SCAN(timer_resolve_data_flow);
1796
1797 int num_blocks = block_count();
1798 MoveResolver move_resolver(this);
1799 ResourceBitMap block_completed(num_blocks);
1800 ResourceBitMap already_resolved(num_blocks);
1801
1802 int i;
1803 for (i = 0; i < num_blocks; i++) {
1804 BlockBegin* block = block_at(i);
1805
1806 // check if block has only one predecessor and only one successor
1807 if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1808 LIR_OpList* instructions = block->lir()->instructions_list();
1809 assert(instructions->at(0)->code() == lir_label, "block must start with label");
1810 assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1811 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1812
1813 // check if block is empty (only label and branch)
1814 if (instructions->length() == 2) {
1815 BlockBegin* pred = block->pred_at(0);
1816 BlockBegin* sux = block->sux_at(0);
1817
1818 // prevent optimization of two consecutive blocks
1819 if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1820 TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1821 block_completed.set_bit(block->linear_scan_number());
1822
1823 // directly resolve between pred and sux (without looking at the empty block between)
1824 resolve_collect_mappings(pred, sux, move_resolver);
1825 if (move_resolver.has_mappings()) {
1826 move_resolver.set_insert_position(block->lir(), 0);
1827 move_resolver.resolve_and_append_moves();
1828 }
1829 }
1830 }
1831 }
1832 }
1833
1834
1835 for (i = 0; i < num_blocks; i++) {
1836 if (!block_completed.at(i)) {
1837 BlockBegin* from_block = block_at(i);
1838 already_resolved.set_from(block_completed);
1839
1840 int num_sux = from_block->number_of_sux();
1841 for (int s = 0; s < num_sux; s++) {
1842 BlockBegin* to_block = from_block->sux_at(s);
1843
1844 // check for duplicate edges between the same blocks (can happen with switch blocks)
1845 if (!already_resolved.at(to_block->linear_scan_number())) {
1846 TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1847 already_resolved.set_bit(to_block->linear_scan_number());
1848
1849 // collect all intervals that have been split between from_block and to_block
1850 resolve_collect_mappings(from_block, to_block, move_resolver);
1851 if (move_resolver.has_mappings()) {
1852 resolve_find_insert_pos(from_block, to_block, move_resolver);
1853 move_resolver.resolve_and_append_moves();
1854 }
1855 }
1856 }
1857 }
1858 }
1859 }
1860
1861
1862 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1863 if (interval_at(reg_num) == NULL) {
1864 // if a phi function is never used, no interval is created -> ignore this
1865 return;
1866 }
1867
1868 Interval* interval = interval_at_block_begin(block, reg_num);
1869 int reg = interval->assigned_reg();
1870 int regHi = interval->assigned_regHi();
1871
1872 if ((reg < nof_regs && interval->always_in_memory()) ||
1873 (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1874 // the interval is split to get a short range that is located on the stack
1875 // in the following two cases:
1876 // * the interval started in memory (e.g. method parameter), but is currently in a register
1877 // this is an optimization for exception handling that reduces the number of moves that
1878 // are necessary for resolving the states when an exception uses this exception handler
1879 // * the interval would be on the fpu stack at the begin of the exception handler
1880 // this is not allowed because of the complicated fpu stack handling on Intel
1881
1882 // range that will be spilled to memory
1883 int from_op_id = block->first_lir_instruction_id();
1884 int to_op_id = from_op_id + 1; // short live range of length 1
1885 assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1886 "no split allowed between exception entry and first instruction");
1887
1888 if (interval->from() != from_op_id) {
1889 // the part before from_op_id is unchanged
1890 interval = interval->split(from_op_id);
1891 interval->assign_reg(reg, regHi);
1892 append_interval(interval);
1893 } else {
1894 _needs_full_resort = true;
1895 }
1896 assert(interval->from() == from_op_id, "must be true now");
1897
1898 Interval* spilled_part = interval;
1899 if (interval->to() != to_op_id) {
1900 // the part after to_op_id is unchanged
1901 spilled_part = interval->split_from_start(to_op_id);
1902 append_interval(spilled_part);
1903 move_resolver.add_mapping(spilled_part, interval);
1904 }
1905 assign_spill_slot(spilled_part);
1906
1907 assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1908 }
1909 }
1910
1911 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1912 assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1913 DEBUG_ONLY(move_resolver.check_empty());
1914
1915 // visit all registers where the live_in bit is set
1916 int size = live_set_size();
1917 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1918 resolve_exception_entry(block, r, move_resolver);
1919 }
1920
1921 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1922 for_each_phi_fun(block, phi,
1923 if (!phi->is_illegal()) { resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver); }
1924 );
1925
1926 if (move_resolver.has_mappings()) {
1927 // insert moves after first instruction
1928 move_resolver.set_insert_position(block->lir(), 0);
1929 move_resolver.resolve_and_append_moves();
1930 }
1931 }
1932
1933
1934 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1935 if (interval_at(reg_num) == NULL) {
1936 // if a phi function is never used, no interval is created -> ignore this
1937 return;
1938 }
1939
1940 // the computation of to_interval is equal to resolve_collect_mappings,
1941 // but from_interval is more complicated because of phi functions
1942 BlockBegin* to_block = handler->entry_block();
1943 Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1944
1945 if (phi != NULL) {
1946 // phi function of the exception entry block
1947 // no moves are created for this phi function in the LIR_Generator, so the
1948 // interval at the throwing instruction must be searched using the operands
1949 // of the phi function
1950 Value from_value = phi->operand_at(handler->phi_operand());
1951
1952 // with phi functions it can happen that the same from_value is used in
1953 // multiple mappings, so notify move-resolver that this is allowed
1954 move_resolver.set_multiple_reads_allowed();
1955
1956 Constant* con = from_value->as_Constant();
1957 if (con != NULL && (!con->is_pinned() || con->operand()->is_constant())) {
1958 // Need a mapping from constant to interval if unpinned (may have no register) or if the operand is a constant (no register).
1959 move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1960 } else {
1961 // search split child at the throwing op_id
1962 Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1963 move_resolver.add_mapping(from_interval, to_interval);
1964 }
1965 } else {
1966 // no phi function, so use reg_num also for from_interval
1967 // search split child at the throwing op_id
1968 Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1969 if (from_interval != to_interval) {
1970 // optimization to reduce number of moves: when to_interval is on stack and
1971 // the stack slot is known to be always correct, then no move is necessary
1972 if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1973 move_resolver.add_mapping(from_interval, to_interval);
1974 }
1975 }
1976 }
1977 }
1978
1979 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1980 TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1981
1982 DEBUG_ONLY(move_resolver.check_empty());
1983 assert(handler->lir_op_id() == -1, "already processed this xhandler");
1984 DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1985 assert(handler->entry_code() == NULL, "code already present");
1986
1987 // visit all registers where the live_in bit is set
1988 BlockBegin* block = handler->entry_block();
1989 int size = live_set_size();
1990 for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1991 resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1992 }
1993
1994 // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1995 for_each_phi_fun(block, phi,
1996 if (!phi->is_illegal()) { resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver); }
1997 );
1998
1999 if (move_resolver.has_mappings()) {
2000 LIR_List* entry_code = new LIR_List(compilation());
2001 move_resolver.set_insert_position(entry_code, 0);
2002 move_resolver.resolve_and_append_moves();
2003
2004 entry_code->jump(handler->entry_block());
2005 handler->set_entry_code(entry_code);
2006 }
2007 }
2008
2009
2010 void LinearScan::resolve_exception_handlers() {
2011 MoveResolver move_resolver(this);
2012 LIR_OpVisitState visitor;
2013 int num_blocks = block_count();
2014
2015 int i;
2016 for (i = 0; i < num_blocks; i++) {
2017 BlockBegin* block = block_at(i);
2018 if (block->is_set(BlockBegin::exception_entry_flag)) {
2019 resolve_exception_entry(block, move_resolver);
2020 }
2021 }
2022
2023 for (i = 0; i < num_blocks; i++) {
2024 BlockBegin* block = block_at(i);
2025 LIR_List* ops = block->lir();
2026 int num_ops = ops->length();
2027
2028 // iterate all instructions of the block. skip the first because it is always a label
2029 assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
2030 for (int j = 1; j < num_ops; j++) {
2031 LIR_Op* op = ops->at(j);
2032 int op_id = op->id();
2033
2034 if (op_id != -1 && has_info(op_id)) {
2035 // visit operation to collect all operands
2036 visitor.visit(op);
2037 assert(visitor.info_count() > 0, "should not visit otherwise");
2038
2039 XHandlers* xhandlers = visitor.all_xhandler();
2040 int n = xhandlers->length();
2041 for (int k = 0; k < n; k++) {
2042 resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
2043 }
2044
2045 #ifdef ASSERT
2046 } else {
2047 visitor.visit(op);
2048 assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2049 #endif
2050 }
2051 }
2052 }
2053 }
2054
2055
2056 // ********** Phase 7: assign register numbers back to LIR
2057 // (includes computation of debug information and oop maps)
2058
2059 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2060 VMReg reg = interval->cached_vm_reg();
2061 if (!reg->is_valid() ) {
2062 reg = vm_reg_for_operand(operand_for_interval(interval));
2063 interval->set_cached_vm_reg(reg);
2064 }
2065 assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2066 return reg;
2067 }
2068
2069 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2070 assert(opr->is_oop(), "currently only implemented for oop operands");
2071 return frame_map()->regname(opr);
2072 }
2073
2074
2075 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2076 LIR_Opr opr = interval->cached_opr();
2077 if (opr->is_illegal()) {
2078 opr = calc_operand_for_interval(interval);
2079 interval->set_cached_opr(opr);
2080 }
2081
2082 assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2083 return opr;
2084 }
2085
2086 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2087 int assigned_reg = interval->assigned_reg();
2088 BasicType type = interval->type();
2089
2090 if (assigned_reg >= nof_regs) {
2091 // stack slot
2092 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2093 return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2094
2095 } else {
2096 // register
2097 switch (type) {
2098 case T_OBJECT: {
2099 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2100 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2101 return LIR_OprFact::single_cpu_oop(assigned_reg);
2102 }
2103
2104 case T_ADDRESS: {
2105 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2106 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2107 return LIR_OprFact::single_cpu_address(assigned_reg);
2108 }
2109
2110 case T_METADATA: {
2111 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2112 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2113 return LIR_OprFact::single_cpu_metadata(assigned_reg);
2114 }
2115
2116 #ifdef __SOFTFP__
2117 case T_FLOAT: // fall through
2118 #endif // __SOFTFP__
2119 case T_INT: {
2120 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2121 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2122 return LIR_OprFact::single_cpu(assigned_reg);
2123 }
2124
2125 #ifdef __SOFTFP__
2126 case T_DOUBLE: // fall through
2127 #endif // __SOFTFP__
2128 case T_LONG: {
2129 int assigned_regHi = interval->assigned_regHi();
2130 assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2131 assert(num_physical_regs(T_LONG) == 1 ||
2132 (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2133
2134 assert(assigned_reg != assigned_regHi, "invalid allocation");
2135 assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2136 "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2137 assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2138 if (requires_adjacent_regs(T_LONG)) {
2139 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2140 }
2141
2142 #ifdef _LP64
2143 return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2144 #else
2145 return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2146 #endif // LP64
2147 }
2148
2149 #ifndef __SOFTFP__
2150 case T_FLOAT: {
2151 #ifdef X86
2152 if (UseSSE >= 1) {
2153 int last_xmm_reg = pd_last_xmm_reg;
2154 #ifdef _LP64
2155 if (UseAVX < 3) {
2156 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2157 }
2158 #endif // LP64
2159 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2160 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2161 return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2162 }
2163 #endif // X86
2164
2165 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2166 assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2167 return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2168 }
2169
2170 case T_DOUBLE: {
2171 #ifdef X86
2172 if (UseSSE >= 2) {
2173 int last_xmm_reg = pd_last_xmm_reg;
2174 #ifdef _LP64
2175 if (UseAVX < 3) {
2176 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2177 }
2178 #endif // LP64
2179 assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2180 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2181 return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2182 }
2183 #endif // X86
2184
2185 #if defined(ARM32)
2186 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2187 assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2188 assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2189 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2190 #else
2191 assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2192 assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2193 LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2194 #endif
2195 return result;
2196 }
2197 #endif // __SOFTFP__
2198
2199 default: {
2200 ShouldNotReachHere();
2201 return LIR_OprFact::illegalOpr;
2202 }
2203 }
2204 }
2205 }
2206
2207 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2208 assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2209 return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2210 }
2211
2212 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2213 assert(opr->is_virtual(), "should not call this otherwise");
2214
2215 Interval* interval = interval_at(opr->vreg_number());
2216 assert(interval != NULL, "interval must exist");
2217
2218 if (op_id != -1) {
2219 #ifdef ASSERT
2220 BlockBegin* block = block_of_op_with_id(op_id);
2221 if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2222 // check if spill moves could have been appended at the end of this block, but
2223 // before the branch instruction. So the split child information for this branch would
2224 // be incorrect.
2225 LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2226 if (branch != NULL) {
2227 if (block->live_out().at(opr->vreg_number())) {
2228 assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2229 assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2230 }
2231 }
2232 }
2233 #endif
2234
2235 // operands are not changed when an interval is split during allocation,
2236 // so search the right interval here
2237 interval = split_child_at_op_id(interval, op_id, mode);
2238 }
2239
2240 LIR_Opr res = operand_for_interval(interval);
2241
2242 #ifdef X86
2243 // new semantic for is_last_use: not only set on definite end of interval,
2244 // but also before hole
2245 // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2246 // last use information is completely correct
2247 // information is only needed for fpu stack allocation
2248 if (res->is_fpu_register()) {
2249 if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2250 assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2251 res = res->make_last_use();
2252 }
2253 }
2254 #endif
2255
2256 assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2257
2258 return res;
2259 }
2260
2261
2262 #ifdef ASSERT
2263 // some methods used to check correctness of debug information
2264
2265 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2266 if (values == NULL) {
2267 return;
2268 }
2269
2270 for (int i = 0; i < values->length(); i++) {
2271 ScopeValue* value = values->at(i);
2272
2273 if (value->is_location()) {
2274 Location location = ((LocationValue*)value)->location();
2275 assert(location.where() == Location::on_stack, "value is in register");
2276 }
2277 }
2278 }
2279
2280 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2281 if (values == NULL) {
2282 return;
2283 }
2284
2285 for (int i = 0; i < values->length(); i++) {
2286 MonitorValue* value = values->at(i);
2287
2288 if (value->owner()->is_location()) {
2289 Location location = ((LocationValue*)value->owner())->location();
2290 assert(location.where() == Location::on_stack, "owner is in register");
2291 }
2292 assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2293 }
2294 }
2295
2296 void assert_equal(Location l1, Location l2) {
2297 assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2298 }
2299
2300 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2301 if (v1->is_location()) {
2302 assert(v2->is_location(), "");
2303 assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2304 } else if (v1->is_constant_int()) {
2305 assert(v2->is_constant_int(), "");
2306 assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2307 } else if (v1->is_constant_double()) {
2308 assert(v2->is_constant_double(), "");
2309 assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2310 } else if (v1->is_constant_long()) {
2311 assert(v2->is_constant_long(), "");
2312 assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2313 } else if (v1->is_constant_oop()) {
2314 assert(v2->is_constant_oop(), "");
2315 assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2316 } else {
2317 ShouldNotReachHere();
2318 }
2319 }
2320
2321 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2322 assert_equal(m1->owner(), m2->owner());
2323 assert_equal(m1->basic_lock(), m2->basic_lock());
2324 }
2325
2326 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2327 assert(d1->scope() == d2->scope(), "not equal");
2328 assert(d1->bci() == d2->bci(), "not equal");
2329
2330 if (d1->locals() != NULL) {
2331 assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2332 assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2333 for (int i = 0; i < d1->locals()->length(); i++) {
2334 assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2335 }
2336 } else {
2337 assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2338 }
2339
2340 if (d1->expressions() != NULL) {
2341 assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2342 assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2343 for (int i = 0; i < d1->expressions()->length(); i++) {
2344 assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2345 }
2346 } else {
2347 assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2348 }
2349
2350 if (d1->monitors() != NULL) {
2351 assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2352 assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2353 for (int i = 0; i < d1->monitors()->length(); i++) {
2354 assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2355 }
2356 } else {
2357 assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2358 }
2359
2360 if (d1->caller() != NULL) {
2361 assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2362 assert_equal(d1->caller(), d2->caller());
2363 } else {
2364 assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2365 }
2366 }
2367
2368 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2369 if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2370 Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2371 switch (code) {
2372 case Bytecodes::_ifnull : // fall through
2373 case Bytecodes::_ifnonnull : // fall through
2374 case Bytecodes::_ifeq : // fall through
2375 case Bytecodes::_ifne : // fall through
2376 case Bytecodes::_iflt : // fall through
2377 case Bytecodes::_ifge : // fall through
2378 case Bytecodes::_ifgt : // fall through
2379 case Bytecodes::_ifle : // fall through
2380 case Bytecodes::_if_icmpeq : // fall through
2381 case Bytecodes::_if_icmpne : // fall through
2382 case Bytecodes::_if_icmplt : // fall through
2383 case Bytecodes::_if_icmpge : // fall through
2384 case Bytecodes::_if_icmpgt : // fall through
2385 case Bytecodes::_if_icmple : // fall through
2386 case Bytecodes::_if_acmpeq : // fall through
2387 case Bytecodes::_if_acmpne :
2388 assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2389 break;
2390 default:
2391 break;
2392 }
2393 }
2394 }
2395
2396 #endif // ASSERT
2397
2398
2399 IntervalWalker* LinearScan::init_compute_oop_maps() {
2400 // setup lists of potential oops for walking
2401 Interval* oop_intervals;
2402 Interval* non_oop_intervals;
2403
2404 create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2405
2406 // intervals that have no oops inside need not to be processed
2407 // to ensure a walking until the last instruction id, add a dummy interval
2408 // with a high operation id
2409 non_oop_intervals = new Interval(any_reg);
2410 non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2411
2412 return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2413 }
2414
2415
2416 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2417 TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2418
2419 // walk before the current operation -> intervals that start at
2420 // the operation (= output operands of the operation) are not
2421 // included in the oop map
2422 iw->walk_before(op->id());
2423
2424 int frame_size = frame_map()->framesize();
2425 int arg_count = frame_map()->oop_map_arg_count();
2426 OopMap* map = new OopMap(frame_size, arg_count);
2427
2428 // Iterate through active intervals
2429 for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2430 int assigned_reg = interval->assigned_reg();
2431
2432 assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2433 assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2434 assert(interval->reg_num() >= LIR_Opr::vreg_base, "fixed interval found");
2435
2436 // Check if this range covers the instruction. Intervals that
2437 // start or end at the current operation are not included in the
2438 // oop map, except in the case of patching moves. For patching
2439 // moves, any intervals which end at this instruction are included
2440 // in the oop map since we may safepoint while doing the patch
2441 // before we've consumed the inputs.
2442 if (op->is_patching() || op->id() < interval->current_to()) {
2443
2444 // caller-save registers must not be included into oop-maps at calls
2445 assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2446
2447 VMReg name = vm_reg_for_interval(interval);
2448 set_oop(map, name);
2449
2450 // Spill optimization: when the stack value is guaranteed to be always correct,
2451 // then it must be added to the oop map even if the interval is currently in a register
2452 if (interval->always_in_memory() &&
2453 op->id() > interval->spill_definition_pos() &&
2454 interval->assigned_reg() != interval->canonical_spill_slot()) {
2455 assert(interval->spill_definition_pos() > 0, "position not set correctly");
2456 assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2457 assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2458
2459 set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2460 }
2461 }
2462 }
2463
2464 // add oops from lock stack
2465 assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2466 int locks_count = info->stack()->total_locks_size();
2467 for (int i = 0; i < locks_count; i++) {
2468 set_oop(map, frame_map()->monitor_object_regname(i));
2469 }
2470
2471 return map;
2472 }
2473
2474
2475 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2476 assert(visitor.info_count() > 0, "no oop map needed");
2477
2478 // compute oop_map only for first CodeEmitInfo
2479 // because it is (in most cases) equal for all other infos of the same operation
2480 CodeEmitInfo* first_info = visitor.info_at(0);
2481 OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2482
2483 for (int i = 0; i < visitor.info_count(); i++) {
2484 CodeEmitInfo* info = visitor.info_at(i);
2485 OopMap* oop_map = first_oop_map;
2486
2487 // compute worst case interpreter size in case of a deoptimization
2488 _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2489
2490 if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2491 // this info has a different number of locks then the precomputed oop map
2492 // (possible for lock and unlock instructions) -> compute oop map with
2493 // correct lock information
2494 oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2495 }
2496
2497 if (info->_oop_map == NULL) {
2498 info->_oop_map = oop_map;
2499 } else {
2500 // a CodeEmitInfo can not be shared between different LIR-instructions
2501 // because interval splitting can occur anywhere between two instructions
2502 // and so the oop maps must be different
2503 // -> check if the already set oop_map is exactly the one calculated for this operation
2504 assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2505 }
2506 }
2507 }
2508
2509
2510 // frequently used constants
2511 // Allocate them with new so they are never destroyed (otherwise, a
2512 // forced exit could destroy these objects while they are still in
2513 // use).
2514 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (mtCompiler) ConstantOopWriteValue(NULL);
2515 ConstantIntValue* LinearScan::_int_m1_scope_value = new (mtCompiler) ConstantIntValue(-1);
2516 ConstantIntValue* LinearScan::_int_0_scope_value = new (mtCompiler) ConstantIntValue((jint)0);
2517 ConstantIntValue* LinearScan::_int_1_scope_value = new (mtCompiler) ConstantIntValue(1);
2518 ConstantIntValue* LinearScan::_int_2_scope_value = new (mtCompiler) ConstantIntValue(2);
2519 LocationValue* _illegal_value = new (mtCompiler) LocationValue(Location());
2520
2521 void LinearScan::init_compute_debug_info() {
2522 // cache for frequently used scope values
2523 // (cpu registers and stack slots)
2524 int cache_size = (LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2;
2525 _scope_value_cache = ScopeValueArray(cache_size, cache_size, NULL);
2526 }
2527
2528 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2529 Location loc;
2530 if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2531 bailout("too large frame");
2532 }
2533 ScopeValue* object_scope_value = new LocationValue(loc);
2534
2535 if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2536 bailout("too large frame");
2537 }
2538 return new MonitorValue(object_scope_value, loc);
2539 }
2540
2541 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2542 Location loc;
2543 if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2544 bailout("too large frame");
2545 }
2546 return new LocationValue(loc);
2547 }
2548
2549
2550 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2551 assert(opr->is_constant(), "should not be called otherwise");
2552
2553 LIR_Const* c = opr->as_constant_ptr();
2554 BasicType t = c->type();
2555 switch (t) {
2556 case T_OBJECT: {
2557 jobject value = c->as_jobject();
2558 if (value == NULL) {
2559 scope_values->append(_oop_null_scope_value);
2560 } else {
2561 scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2562 }
2563 return 1;
2564 }
2565
2566 case T_INT: // fall through
2567 case T_FLOAT: {
2568 int value = c->as_jint_bits();
2569 switch (value) {
2570 case -1: scope_values->append(_int_m1_scope_value); break;
2571 case 0: scope_values->append(_int_0_scope_value); break;
2572 case 1: scope_values->append(_int_1_scope_value); break;
2573 case 2: scope_values->append(_int_2_scope_value); break;
2574 default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2575 }
2576 return 1;
2577 }
2578
2579 case T_LONG: // fall through
2580 case T_DOUBLE: {
2581 #ifdef _LP64
2582 scope_values->append(_int_0_scope_value);
2583 scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2584 #else
2585 if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2586 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2587 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2588 } else {
2589 scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2590 scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2591 }
2592 #endif
2593 return 2;
2594 }
2595
2596 case T_ADDRESS: {
2597 #ifdef _LP64
2598 scope_values->append(new ConstantLongValue(c->as_jint()));
2599 #else
2600 scope_values->append(new ConstantIntValue(c->as_jint()));
2601 #endif
2602 return 1;
2603 }
2604
2605 default:
2606 ShouldNotReachHere();
2607 return -1;
2608 }
2609 }
2610
2611 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2612 if (opr->is_single_stack()) {
2613 int stack_idx = opr->single_stack_ix();
2614 bool is_oop = opr->is_oop_register();
2615 int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2616
2617 ScopeValue* sv = _scope_value_cache.at(cache_idx);
2618 if (sv == NULL) {
2619 Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2620 sv = location_for_name(stack_idx, loc_type);
2621 _scope_value_cache.at_put(cache_idx, sv);
2622 }
2623
2624 // check if cached value is correct
2625 DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2626
2627 scope_values->append(sv);
2628 return 1;
2629
2630 } else if (opr->is_single_cpu()) {
2631 bool is_oop = opr->is_oop_register();
2632 int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2633 Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2634
2635 ScopeValue* sv = _scope_value_cache.at(cache_idx);
2636 if (sv == NULL) {
2637 Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2638 VMReg rname = frame_map()->regname(opr);
2639 sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2640 _scope_value_cache.at_put(cache_idx, sv);
2641 }
2642
2643 // check if cached value is correct
2644 DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2645
2646 scope_values->append(sv);
2647 return 1;
2648
2649 #ifdef X86
2650 } else if (opr->is_single_xmm()) {
2651 VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2652 LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2653
2654 scope_values->append(sv);
2655 return 1;
2656 #endif
2657
2658 } else if (opr->is_single_fpu()) {
2659 #ifdef IA32
2660 // the exact location of fpu stack values is only known
2661 // during fpu stack allocation, so the stack allocator object
2662 // must be present
2663 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2664 assert(_fpu_stack_allocator != NULL, "must be present");
2665 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2666 #elif defined(AMD64)
2667 assert(false, "FPU not used on x86-64");
2668 #endif
2669
2670 Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2671 VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2672 #ifndef __SOFTFP__
2673 #ifndef VM_LITTLE_ENDIAN
2674 // On S390 a (single precision) float value occupies only the high
2675 // word of the full double register. So when the double register is
2676 // stored to memory (e.g. by the RegisterSaver), then the float value
2677 // is found at offset 0. I.e. the code below is not needed on S390.
2678 #ifndef S390
2679 if (! float_saved_as_double) {
2680 // On big endian system, we may have an issue if float registers use only
2681 // the low half of the (same) double registers.
2682 // Both the float and the double could have the same regnr but would correspond
2683 // to two different addresses once saved.
2684
2685 // get next safely (no assertion checks)
2686 VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2687 if (next->is_reg() &&
2688 (next->as_FloatRegister() == rname->as_FloatRegister())) {
2689 // the back-end does use the same numbering for the double and the float
2690 rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2691 }
2692 }
2693 #endif // !S390
2694 #endif
2695 #endif
2696 LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2697
2698 scope_values->append(sv);
2699 return 1;
2700
2701 } else {
2702 // double-size operands
2703
2704 ScopeValue* first;
2705 ScopeValue* second;
2706
2707 if (opr->is_double_stack()) {
2708 #ifdef _LP64
2709 Location loc1;
2710 Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2711 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2712 bailout("too large frame");
2713 }
2714
2715 first = new LocationValue(loc1);
2716 second = _int_0_scope_value;
2717 #else
2718 Location loc1, loc2;
2719 if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2720 bailout("too large frame");
2721 }
2722 first = new LocationValue(loc1);
2723 second = new LocationValue(loc2);
2724 #endif // _LP64
2725
2726 } else if (opr->is_double_cpu()) {
2727 #ifdef _LP64
2728 VMReg rname_first = opr->as_register_lo()->as_VMReg();
2729 first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2730 second = _int_0_scope_value;
2731 #else
2732 VMReg rname_first = opr->as_register_lo()->as_VMReg();
2733 VMReg rname_second = opr->as_register_hi()->as_VMReg();
2734
2735 if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2736 // lo/hi and swapped relative to first and second, so swap them
2737 VMReg tmp = rname_first;
2738 rname_first = rname_second;
2739 rname_second = tmp;
2740 }
2741
2742 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2743 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2744 #endif //_LP64
2745
2746
2747 #ifdef X86
2748 } else if (opr->is_double_xmm()) {
2749 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2750 VMReg rname_first = opr->as_xmm_double_reg()->as_VMReg();
2751 # ifdef _LP64
2752 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2753 second = _int_0_scope_value;
2754 # else
2755 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2756 // %%% This is probably a waste but we'll keep things as they were for now
2757 if (true) {
2758 VMReg rname_second = rname_first->next();
2759 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2760 }
2761 # endif
2762 #endif
2763
2764 } else if (opr->is_double_fpu()) {
2765 // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2766 // the double as float registers in the native ordering. On X86,
2767 // fpu_regnrLo is a FPU stack slot whose VMReg represents
2768 // the low-order word of the double and fpu_regnrLo + 1 is the
2769 // name for the other half. *first and *second must represent the
2770 // least and most significant words, respectively.
2771
2772 #ifdef IA32
2773 // the exact location of fpu stack values is only known
2774 // during fpu stack allocation, so the stack allocator object
2775 // must be present
2776 assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2777 assert(_fpu_stack_allocator != NULL, "must be present");
2778 opr = _fpu_stack_allocator->to_fpu_stack(opr);
2779
2780 assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2781 #endif
2782 #ifdef AMD64
2783 assert(false, "FPU not used on x86-64");
2784 #endif
2785 #ifdef ARM32
2786 assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2787 #endif
2788
2789 #ifdef VM_LITTLE_ENDIAN
2790 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2791 #else
2792 VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2793 #endif
2794
2795 #ifdef _LP64
2796 first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2797 second = _int_0_scope_value;
2798 #else
2799 first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2800 // %%% This is probably a waste but we'll keep things as they were for now
2801 if (true) {
2802 VMReg rname_second = rname_first->next();
2803 second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2804 }
2805 #endif
2806
2807 } else {
2808 ShouldNotReachHere();
2809 first = NULL;
2810 second = NULL;
2811 }
2812
2813 assert(first != NULL && second != NULL, "must be set");
2814 // The convention the interpreter uses is that the second local
2815 // holds the first raw word of the native double representation.
2816 // This is actually reasonable, since locals and stack arrays
2817 // grow downwards in all implementations.
2818 // (If, on some machine, the interpreter's Java locals or stack
2819 // were to grow upwards, the embedded doubles would be word-swapped.)
2820 scope_values->append(second);
2821 scope_values->append(first);
2822 return 2;
2823 }
2824 }
2825
2826
2827 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2828 if (value != NULL) {
2829 LIR_Opr opr = value->operand();
2830 Constant* con = value->as_Constant();
2831
2832 assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "assumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2833 assert(con != NULL || opr->is_virtual(), "assumption: non-Constant instructions have only virtual operands");
2834
2835 if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2836 // Unpinned constants may have a virtual operand for a part of the lifetime
2837 // or may be illegal when it was optimized away,
2838 // so always use a constant operand
2839 opr = LIR_OprFact::value_type(con->type());
2840 }
2841 assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2842
2843 if (opr->is_virtual()) {
2844 LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2845
2846 BlockBegin* block = block_of_op_with_id(op_id);
2847 if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2848 // generating debug information for the last instruction of a block.
2849 // if this instruction is a branch, spill moves are inserted before this branch
2850 // and so the wrong operand would be returned (spill moves at block boundaries are not
2851 // considered in the live ranges of intervals)
2852 // Solution: use the first op_id of the branch target block instead.
2853 if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2854 if (block->live_out().at(opr->vreg_number())) {
2855 op_id = block->sux_at(0)->first_lir_instruction_id();
2856 mode = LIR_OpVisitState::outputMode;
2857 }
2858 }
2859 }
2860
2861 // Get current location of operand
2862 // The operand must be live because debug information is considered when building the intervals
2863 // if the interval is not live, color_lir_opr will cause an assertion failure
2864 opr = color_lir_opr(opr, op_id, mode);
2865 assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2866
2867 // Append to ScopeValue array
2868 return append_scope_value_for_operand(opr, scope_values);
2869
2870 } else {
2871 assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2872 assert(opr->is_constant(), "operand must be constant");
2873
2874 return append_scope_value_for_constant(opr, scope_values);
2875 }
2876 } else {
2877 // append a dummy value because real value not needed
2878 scope_values->append(_illegal_value);
2879 return 1;
2880 }
2881 }
2882
2883
2884 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2885 IRScopeDebugInfo* caller_debug_info = NULL;
2886
2887 ValueStack* caller_state = cur_state->caller_state();
2888 if (caller_state != NULL) {
2889 // process recursively to compute outermost scope first
2890 caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2891 }
2892
2893 // initialize these to null.
2894 // If we don't need deopt info or there are no locals, expressions or monitors,
2895 // then these get recorded as no information and avoids the allocation of 0 length arrays.
2896 GrowableArray<ScopeValue*>* locals = NULL;
2897 GrowableArray<ScopeValue*>* expressions = NULL;
2898 GrowableArray<MonitorValue*>* monitors = NULL;
2899
2900 // describe local variable values
2901 int nof_locals = cur_state->locals_size();
2902 if (nof_locals > 0) {
2903 locals = new GrowableArray<ScopeValue*>(nof_locals);
2904
2905 int pos = 0;
2906 while (pos < nof_locals) {
2907 assert(pos < cur_state->locals_size(), "why not?");
2908
2909 Value local = cur_state->local_at(pos);
2910 pos += append_scope_value(op_id, local, locals);
2911
2912 assert(locals->length() == pos, "must match");
2913 }
2914 assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2915 assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2916 } else if (cur_scope->method()->max_locals() > 0) {
2917 assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2918 nof_locals = cur_scope->method()->max_locals();
2919 locals = new GrowableArray<ScopeValue*>(nof_locals);
2920 for(int i = 0; i < nof_locals; i++) {
2921 locals->append(_illegal_value);
2922 }
2923 }
2924
2925 // describe expression stack
2926 int nof_stack = cur_state->stack_size();
2927 if (nof_stack > 0) {
2928 expressions = new GrowableArray<ScopeValue*>(nof_stack);
2929
2930 int pos = 0;
2931 while (pos < nof_stack) {
2932 Value expression = cur_state->stack_at_inc(pos);
2933 append_scope_value(op_id, expression, expressions);
2934
2935 assert(expressions->length() == pos, "must match");
2936 }
2937 assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2938 }
2939
2940 // describe monitors
2941 int nof_locks = cur_state->locks_size();
2942 if (nof_locks > 0) {
2943 int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2944 monitors = new GrowableArray<MonitorValue*>(nof_locks);
2945 for (int i = 0; i < nof_locks; i++) {
2946 monitors->append(location_for_monitor_index(lock_offset + i));
2947 }
2948 }
2949
2950 return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info, cur_state->should_reexecute());
2951 }
2952
2953
2954 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2955 TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2956
2957 IRScope* innermost_scope = info->scope();
2958 ValueStack* innermost_state = info->stack();
2959
2960 assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2961
2962 DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2963
2964 if (info->_scope_debug_info == NULL) {
2965 // compute debug information
2966 info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2967 } else {
2968 // debug information already set. Check that it is correct from the current point of view
2969 DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2970 }
2971 }
2972
2973
2974 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2975 LIR_OpVisitState visitor;
2976 int num_inst = instructions->length();
2977 bool has_dead = false;
2978
2979 for (int j = 0; j < num_inst; j++) {
2980 LIR_Op* op = instructions->at(j);
2981 if (op == NULL) { // this can happen when spill-moves are removed in eliminate_spill_moves
2982 has_dead = true;
2983 continue;
2984 }
2985 int op_id = op->id();
2986
2987 // visit instruction to get list of operands
2988 visitor.visit(op);
2989
2990 // iterate all modes of the visitor and process all virtual operands
2991 for_each_visitor_mode(mode) {
2992 int n = visitor.opr_count(mode);
2993 for (int k = 0; k < n; k++) {
2994 LIR_Opr opr = visitor.opr_at(mode, k);
2995 if (opr->is_virtual_register()) {
2996 visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
2997 }
2998 }
2999 }
3000
3001 if (visitor.info_count() > 0) {
3002 // exception handling
3003 if (compilation()->has_exception_handlers()) {
3004 XHandlers* xhandlers = visitor.all_xhandler();
3005 int n = xhandlers->length();
3006 for (int k = 0; k < n; k++) {
3007 XHandler* handler = xhandlers->handler_at(k);
3008 if (handler->entry_code() != NULL) {
3009 assign_reg_num(handler->entry_code()->instructions_list(), NULL);
3010 }
3011 }
3012 } else {
3013 assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
3014 }
3015
3016 // compute oop map
3017 assert(iw != NULL, "needed for compute_oop_map");
3018 compute_oop_map(iw, visitor, op);
3019
3020 // compute debug information
3021 if (!use_fpu_stack_allocation()) {
3022 // compute debug information if fpu stack allocation is not needed.
3023 // when fpu stack allocation is needed, the debug information can not
3024 // be computed here because the exact location of fpu operands is not known
3025 // -> debug information is created inside the fpu stack allocator
3026 int n = visitor.info_count();
3027 for (int k = 0; k < n; k++) {
3028 compute_debug_info(visitor.info_at(k), op_id);
3029 }
3030 }
3031 }
3032
3033 #ifdef ASSERT
3034 // make sure we haven't made the op invalid.
3035 op->verify();
3036 #endif
3037
3038 // remove useless moves
3039 if (op->code() == lir_move) {
3040 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
3041 LIR_Op1* move = (LIR_Op1*)op;
3042 LIR_Opr src = move->in_opr();
3043 LIR_Opr dst = move->result_opr();
3044 if (dst == src ||
3045 (!dst->is_pointer() && !src->is_pointer() &&
3046 src->is_same_register(dst))) {
3047 instructions->at_put(j, NULL);
3048 has_dead = true;
3049 }
3050 }
3051 }
3052
3053 if (has_dead) {
3054 // iterate all instructions of the block and remove all null-values.
3055 int insert_point = 0;
3056 for (int j = 0; j < num_inst; j++) {
3057 LIR_Op* op = instructions->at(j);
3058 if (op != NULL) {
3059 if (insert_point != j) {
3060 instructions->at_put(insert_point, op);
3061 }
3062 insert_point++;
3063 }
3064 }
3065 instructions->trunc_to(insert_point);
3066 }
3067 }
3068
3069 void LinearScan::assign_reg_num() {
3070 TIME_LINEAR_SCAN(timer_assign_reg_num);
3071
3072 init_compute_debug_info();
3073 IntervalWalker* iw = init_compute_oop_maps();
3074
3075 int num_blocks = block_count();
3076 for (int i = 0; i < num_blocks; i++) {
3077 BlockBegin* block = block_at(i);
3078 assign_reg_num(block->lir()->instructions_list(), iw);
3079 }
3080 }
3081
3082
3083 void LinearScan::do_linear_scan() {
3084 NOT_PRODUCT(_total_timer.begin_method());
3085
3086 number_instructions();
3087
3088 NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3089
3090 compute_local_live_sets();
3091 compute_global_live_sets();
3092 CHECK_BAILOUT();
3093
3094 build_intervals();
3095 CHECK_BAILOUT();
3096 sort_intervals_before_allocation();
3097
3098 NOT_PRODUCT(print_intervals("Before Register Allocation"));
3099 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3100
3101 allocate_registers();
3102 CHECK_BAILOUT();
3103
3104 resolve_data_flow();
3105 if (compilation()->has_exception_handlers()) {
3106 resolve_exception_handlers();
3107 }
3108 // fill in number of spill slots into frame_map
3109 propagate_spill_slots();
3110 CHECK_BAILOUT();
3111
3112 NOT_PRODUCT(print_intervals("After Register Allocation"));
3113 NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3114
3115 sort_intervals_after_allocation();
3116
3117 DEBUG_ONLY(verify());
3118
3119 eliminate_spill_moves();
3120 assign_reg_num();
3121 CHECK_BAILOUT();
3122
3123 NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3124 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3125
3126 { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3127
3128 if (use_fpu_stack_allocation()) {
3129 allocate_fpu_stack(); // Only has effect on Intel
3130 NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3131 }
3132 }
3133
3134 #ifndef RISCV
3135 // Disable these optimizations on riscv temporarily, because it does not
3136 // work when the comparison operands are bound to branches or cmoves.
3137 { TIME_LINEAR_SCAN(timer_optimize_lir);
3138
3139 EdgeMoveOptimizer::optimize(ir()->code());
3140 ControlFlowOptimizer::optimize(ir()->code());
3141 // check that cfg is still correct after optimizations
3142 ir()->verify();
3143 }
3144 #endif
3145
3146 NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3147 NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3148 NOT_PRODUCT(_total_timer.end_method(this));
3149 }
3150
3151
3152 // ********** Printing functions
3153
3154 #ifndef PRODUCT
3155
3156 void LinearScan::print_timers(double total) {
3157 _total_timer.print(total);
3158 }
3159
3160 void LinearScan::print_statistics() {
3161 _stat_before_alloc.print("before allocation");
3162 _stat_after_asign.print("after assignment of register");
3163 _stat_final.print("after optimization");
3164 }
3165
3166 void LinearScan::print_bitmap(BitMap& b) {
3167 for (unsigned int i = 0; i < b.size(); i++) {
3168 if (b.at(i)) tty->print("%d ", i);
3169 }
3170 tty->cr();
3171 }
3172
3173 void LinearScan::print_intervals(const char* label) {
3174 if (TraceLinearScanLevel >= 1) {
3175 int i;
3176 tty->cr();
3177 tty->print_cr("%s", label);
3178
3179 for (i = 0; i < interval_count(); i++) {
3180 Interval* interval = interval_at(i);
3181 if (interval != NULL) {
3182 interval->print();
3183 }
3184 }
3185
3186 tty->cr();
3187 tty->print_cr("--- Basic Blocks ---");
3188 for (i = 0; i < block_count(); i++) {
3189 BlockBegin* block = block_at(i);
3190 tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3191 }
3192 tty->cr();
3193 tty->cr();
3194 }
3195
3196 if (PrintCFGToFile) {
3197 CFGPrinter::print_intervals(&_intervals, label);
3198 }
3199 }
3200
3201 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3202 if (TraceLinearScanLevel >= level) {
3203 tty->cr();
3204 tty->print_cr("%s", label);
3205 print_LIR(ir()->linear_scan_order());
3206 tty->cr();
3207 }
3208
3209 if (level == 1 && PrintCFGToFile) {
3210 CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3211 }
3212 }
3213
3214 void LinearScan::print_reg_num(outputStream* out, int reg_num) {
3215 if (reg_num == -1) {
3216 out->print("[ANY]");
3217 return;
3218 } else if (reg_num >= LIR_Opr::vreg_base) {
3219 out->print("[VREG %d]", reg_num);
3220 return;
3221 }
3222
3223 LIR_Opr opr = get_operand(reg_num);
3224 assert(opr->is_valid(), "unknown register");
3225 opr->print(out);
3226 }
3227
3228 LIR_Opr LinearScan::get_operand(int reg_num) {
3229 LIR_Opr opr = LIR_OprFact::illegal();
3230
3231 #ifdef X86
3232 int last_xmm_reg = pd_last_xmm_reg;
3233 #ifdef _LP64
3234 if (UseAVX < 3) {
3235 last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
3236 }
3237 #endif
3238 #endif
3239 if (reg_num >= pd_first_cpu_reg && reg_num <= pd_last_cpu_reg) {
3240 opr = LIR_OprFact::single_cpu(reg_num);
3241 } else if (reg_num >= pd_first_fpu_reg && reg_num <= pd_last_fpu_reg) {
3242 opr = LIR_OprFact::single_fpu(reg_num - pd_first_fpu_reg);
3243 #ifdef X86
3244 } else if (reg_num >= pd_first_xmm_reg && reg_num <= last_xmm_reg) {
3245 opr = LIR_OprFact::single_xmm(reg_num - pd_first_xmm_reg);
3246 #endif
3247 } else {
3248 // reg_num == -1 or a virtual register, return the illegal operand
3249 }
3250 return opr;
3251 }
3252
3253 Interval* LinearScan::find_interval_at(int reg_num) const {
3254 if (reg_num < 0 || reg_num >= _intervals.length()) {
3255 return NULL;
3256 }
3257 return interval_at(reg_num);
3258 }
3259
3260 #endif // PRODUCT
3261
3262
3263 // ********** verification functions for allocation
3264 // (check that all intervals have a correct register and that no registers are overwritten)
3265 #ifdef ASSERT
3266
3267 void LinearScan::verify() {
3268 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3269 verify_intervals();
3270
3271 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3272 verify_no_oops_in_fixed_intervals();
3273
3274 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3275 verify_constants();
3276
3277 TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3278 verify_registers();
3279
3280 TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3281 }
3282
3283 void LinearScan::verify_intervals() {
3284 int len = interval_count();
3285 bool has_error = false;
3286
3287 for (int i = 0; i < len; i++) {
3288 Interval* i1 = interval_at(i);
3289 if (i1 == NULL) continue;
3290
3291 i1->check_split_children();
3292
3293 if (i1->reg_num() != i) {
3294 tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3295 has_error = true;
3296 }
3297
3298 if (i1->reg_num() >= LIR_Opr::vreg_base && i1->type() == T_ILLEGAL) {
3299 tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3300 has_error = true;
3301 }
3302
3303 if (i1->assigned_reg() == any_reg) {
3304 tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3305 has_error = true;
3306 }
3307
3308 if (i1->assigned_reg() == i1->assigned_regHi()) {
3309 tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3310 has_error = true;
3311 }
3312
3313 if (!is_processed_reg_num(i1->assigned_reg())) {
3314 tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3315 has_error = true;
3316 }
3317
3318 // special intervals that are created in MoveResolver
3319 // -> ignore them because the range information has no meaning there
3320 if (i1->from() == 1 && i1->to() == 2) continue;
3321
3322 if (i1->first() == Range::end()) {
3323 tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3324 has_error = true;
3325 }
3326
3327 for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3328 if (r->from() >= r->to()) {
3329 tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3330 has_error = true;
3331 }
3332 }
3333
3334 for (int j = i + 1; j < len; j++) {
3335 Interval* i2 = interval_at(j);
3336 if (i2 == NULL || (i2->from() == 1 && i2->to() == 2)) continue;
3337
3338 int r1 = i1->assigned_reg();
3339 int r1Hi = i1->assigned_regHi();
3340 int r2 = i2->assigned_reg();
3341 int r2Hi = i2->assigned_regHi();
3342 if ((r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi))) && i1->intersects(i2)) {
3343 tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3344 i1->print(); tty->cr();
3345 i2->print(); tty->cr();
3346 has_error = true;
3347 }
3348 }
3349 }
3350
3351 assert(has_error == false, "register allocation invalid");
3352 }
3353
3354
3355 void LinearScan::verify_no_oops_in_fixed_intervals() {
3356 Interval* fixed_intervals;
3357 Interval* other_intervals;
3358 create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3359
3360 // to ensure a walking until the last instruction id, add a dummy interval
3361 // with a high operation id
3362 other_intervals = new Interval(any_reg);
3363 other_intervals->add_range(max_jint - 2, max_jint - 1);
3364 IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3365
3366 LIR_OpVisitState visitor;
3367 for (int i = 0; i < block_count(); i++) {
3368 BlockBegin* block = block_at(i);
3369
3370 LIR_OpList* instructions = block->lir()->instructions_list();
3371
3372 for (int j = 0; j < instructions->length(); j++) {
3373 LIR_Op* op = instructions->at(j);
3374 int op_id = op->id();
3375
3376 visitor.visit(op);
3377
3378 if (visitor.info_count() > 0) {
3379 iw->walk_before(op->id());
3380 bool check_live = true;
3381 if (op->code() == lir_move) {
3382 LIR_Op1* move = (LIR_Op1*)op;
3383 check_live = (move->patch_code() == lir_patch_none);
3384 }
3385 LIR_OpBranch* branch = op->as_OpBranch();
3386 if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3387 // Don't bother checking the stub in this case since the
3388 // exception stub will never return to normal control flow.
3389 check_live = false;
3390 }
3391
3392 // Make sure none of the fixed registers is live across an
3393 // oopmap since we can't handle that correctly.
3394 if (check_live) {
3395 for (Interval* interval = iw->active_first(fixedKind);
3396 interval != Interval::end();
3397 interval = interval->next()) {
3398 if (interval->current_to() > op->id() + 1) {
3399 // This interval is live out of this op so make sure
3400 // that this interval represents some value that's
3401 // referenced by this op either as an input or output.
3402 bool ok = false;
3403 for_each_visitor_mode(mode) {
3404 int n = visitor.opr_count(mode);
3405 for (int k = 0; k < n; k++) {
3406 LIR_Opr opr = visitor.opr_at(mode, k);
3407 if (opr->is_fixed_cpu()) {
3408 if (interval_at(reg_num(opr)) == interval) {
3409 ok = true;
3410 break;
3411 }
3412 int hi = reg_numHi(opr);
3413 if (hi != -1 && interval_at(hi) == interval) {
3414 ok = true;
3415 break;
3416 }
3417 }
3418 }
3419 }
3420 assert(ok, "fixed intervals should never be live across an oopmap point");
3421 }
3422 }
3423 }
3424 }
3425
3426 // oop-maps at calls do not contain registers, so check is not needed
3427 if (!visitor.has_call()) {
3428
3429 for_each_visitor_mode(mode) {
3430 int n = visitor.opr_count(mode);
3431 for (int k = 0; k < n; k++) {
3432 LIR_Opr opr = visitor.opr_at(mode, k);
3433
3434 if (opr->is_fixed_cpu() && opr->is_oop()) {
3435 // operand is a non-virtual cpu register and contains an oop
3436 TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3437
3438 Interval* interval = interval_at(reg_num(opr));
3439 assert(interval != NULL, "no interval");
3440
3441 if (mode == LIR_OpVisitState::inputMode) {
3442 if (interval->to() >= op_id + 1) {
3443 assert(interval->to() < op_id + 2 ||
3444 interval->has_hole_between(op_id, op_id + 2),
3445 "oop input operand live after instruction");
3446 }
3447 } else if (mode == LIR_OpVisitState::outputMode) {
3448 if (interval->from() <= op_id - 1) {
3449 assert(interval->has_hole_between(op_id - 1, op_id),
3450 "oop input operand live after instruction");
3451 }
3452 }
3453 }
3454 }
3455 }
3456 }
3457 }
3458 }
3459 }
3460
3461
3462 void LinearScan::verify_constants() {
3463 int num_regs = num_virtual_regs();
3464 int size = live_set_size();
3465 int num_blocks = block_count();
3466
3467 for (int i = 0; i < num_blocks; i++) {
3468 BlockBegin* block = block_at(i);
3469 ResourceBitMap live_at_edge = block->live_in();
3470
3471 // visit all registers where the live_at_edge bit is set
3472 for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3473 TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3474
3475 Value value = gen()->instruction_for_vreg(r);
3476
3477 assert(value != NULL, "all intervals live across block boundaries must have Value");
3478 assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3479 assert(value->operand()->vreg_number() == r, "register number must match");
3480 // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive across block boundaries");
3481 }
3482 }
3483 }
3484
3485
3486 class RegisterVerifier: public StackObj {
3487 private:
3488 LinearScan* _allocator;
3489 BlockList _work_list; // all blocks that must be processed
3490 IntervalsList _saved_states; // saved information of previous check
3491
3492 // simplified access to methods of LinearScan
3493 Compilation* compilation() const { return _allocator->compilation(); }
3494 Interval* interval_at(int reg_num) const { return _allocator->interval_at(reg_num); }
3495 int reg_num(LIR_Opr opr) const { return _allocator->reg_num(opr); }
3496
3497 // currently, only registers are processed
3498 int state_size() { return LinearScan::nof_regs; }
3499
3500 // accessors
3501 IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3502 void set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3503 void add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3504
3505 // helper functions
3506 IntervalList* copy(IntervalList* input_state);
3507 void state_put(IntervalList* input_state, int reg, Interval* interval);
3508 bool check_state(IntervalList* input_state, int reg, Interval* interval);
3509
3510 void process_block(BlockBegin* block);
3511 void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3512 void process_successor(BlockBegin* block, IntervalList* input_state);
3513 void process_operations(LIR_List* ops, IntervalList* input_state);
3514
3515 public:
3516 RegisterVerifier(LinearScan* allocator)
3517 : _allocator(allocator)
3518 , _work_list(16)
3519 , _saved_states(BlockBegin::number_of_blocks(), BlockBegin::number_of_blocks(), NULL)
3520 { }
3521
3522 void verify(BlockBegin* start);
3523 };
3524
3525
3526 // entry function from LinearScan that starts the verification
3527 void LinearScan::verify_registers() {
3528 RegisterVerifier verifier(this);
3529 verifier.verify(block_at(0));
3530 }
3531
3532
3533 void RegisterVerifier::verify(BlockBegin* start) {
3534 // setup input registers (method arguments) for first block
3535 int input_state_len = state_size();
3536 IntervalList* input_state = new IntervalList(input_state_len, input_state_len, NULL);
3537 CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3538 for (int n = 0; n < args->length(); n++) {
3539 LIR_Opr opr = args->at(n);
3540 if (opr->is_register()) {
3541 Interval* interval = interval_at(reg_num(opr));
3542
3543 if (interval->assigned_reg() < state_size()) {
3544 input_state->at_put(interval->assigned_reg(), interval);
3545 }
3546 if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3547 input_state->at_put(interval->assigned_regHi(), interval);
3548 }
3549 }
3550 }
3551
3552 set_state_for_block(start, input_state);
3553 add_to_work_list(start);
3554
3555 // main loop for verification
3556 do {
3557 BlockBegin* block = _work_list.at(0);
3558 _work_list.remove_at(0);
3559
3560 process_block(block);
3561 } while (!_work_list.is_empty());
3562 }
3563
3564 void RegisterVerifier::process_block(BlockBegin* block) {
3565 TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3566
3567 // must copy state because it is modified
3568 IntervalList* input_state = copy(state_for_block(block));
3569
3570 if (TraceLinearScanLevel >= 4) {
3571 tty->print_cr("Input-State of intervals:");
3572 tty->print(" ");
3573 for (int i = 0; i < state_size(); i++) {
3574 if (input_state->at(i) != NULL) {
3575 tty->print(" %4d", input_state->at(i)->reg_num());
3576 } else {
3577 tty->print(" __");
3578 }
3579 }
3580 tty->cr();
3581 tty->cr();
3582 }
3583
3584 // process all operations of the block
3585 process_operations(block->lir(), input_state);
3586
3587 // iterate all successors
3588 for (int i = 0; i < block->number_of_sux(); i++) {
3589 process_successor(block->sux_at(i), input_state);
3590 }
3591 }
3592
3593 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3594 TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3595
3596 // must copy state because it is modified
3597 input_state = copy(input_state);
3598
3599 if (xhandler->entry_code() != NULL) {
3600 process_operations(xhandler->entry_code(), input_state);
3601 }
3602 process_successor(xhandler->entry_block(), input_state);
3603 }
3604
3605 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3606 IntervalList* saved_state = state_for_block(block);
3607
3608 if (saved_state != NULL) {
3609 // this block was already processed before.
3610 // check if new input_state is consistent with saved_state
3611
3612 bool saved_state_correct = true;
3613 for (int i = 0; i < state_size(); i++) {
3614 if (input_state->at(i) != saved_state->at(i)) {
3615 // current input_state and previous saved_state assume a different
3616 // interval in this register -> assume that this register is invalid
3617 if (saved_state->at(i) != NULL) {
3618 // invalidate old calculation only if it assumed that
3619 // register was valid. when the register was already invalid,
3620 // then the old calculation was correct.
3621 saved_state_correct = false;
3622 saved_state->at_put(i, NULL);
3623
3624 TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3625 }
3626 }
3627 }
3628
3629 if (saved_state_correct) {
3630 // already processed block with correct input_state
3631 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3632 } else {
3633 // must re-visit this block
3634 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3635 add_to_work_list(block);
3636 }
3637
3638 } else {
3639 // block was not processed before, so set initial input_state
3640 TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3641
3642 set_state_for_block(block, copy(input_state));
3643 add_to_work_list(block);
3644 }
3645 }
3646
3647
3648 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3649 IntervalList* copy_state = new IntervalList(input_state->length());
3650 copy_state->appendAll(input_state);
3651 return copy_state;
3652 }
3653
3654 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3655 if (reg != LinearScan::any_reg && reg < state_size()) {
3656 if (interval != NULL) {
3657 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = %d", reg, interval->reg_num()));
3658 } else if (input_state->at(reg) != NULL) {
3659 TRACE_LINEAR_SCAN(4, tty->print_cr(" reg[%d] = NULL", reg));
3660 }
3661
3662 input_state->at_put(reg, interval);
3663 }
3664 }
3665
3666 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3667 if (reg != LinearScan::any_reg && reg < state_size()) {
3668 if (input_state->at(reg) != interval) {
3669 tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3670 return true;
3671 }
3672 }
3673 return false;
3674 }
3675
3676 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3677 // visit all instructions of the block
3678 LIR_OpVisitState visitor;
3679 bool has_error = false;
3680
3681 for (int i = 0; i < ops->length(); i++) {
3682 LIR_Op* op = ops->at(i);
3683 visitor.visit(op);
3684
3685 TRACE_LINEAR_SCAN(4, op->print_on(tty));
3686
3687 // check if input operands are correct
3688 int j;
3689 int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3690 for (j = 0; j < n; j++) {
3691 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3692 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3693 Interval* interval = interval_at(reg_num(opr));
3694 if (op->id() != -1) {
3695 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3696 }
3697
3698 has_error |= check_state(input_state, interval->assigned_reg(), interval->split_parent());
3699 has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3700
3701 // When an operand is marked with is_last_use, then the fpu stack allocator
3702 // removes the register from the fpu stack -> the register contains no value
3703 if (opr->is_last_use()) {
3704 state_put(input_state, interval->assigned_reg(), NULL);
3705 state_put(input_state, interval->assigned_regHi(), NULL);
3706 }
3707 }
3708 }
3709
3710 // invalidate all caller save registers at calls
3711 if (visitor.has_call()) {
3712 for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3713 state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3714 }
3715 for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3716 state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3717 }
3718
3719 #ifdef X86
3720 int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
3721 for (j = 0; j < num_caller_save_xmm_regs; j++) {
3722 state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3723 }
3724 #endif
3725 }
3726
3727 // process xhandler before output and temp operands
3728 XHandlers* xhandlers = visitor.all_xhandler();
3729 n = xhandlers->length();
3730 for (int k = 0; k < n; k++) {
3731 process_xhandler(xhandlers->handler_at(k), input_state);
3732 }
3733
3734 // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3735 n = visitor.opr_count(LIR_OpVisitState::tempMode);
3736 for (j = 0; j < n; j++) {
3737 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3738 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3739 Interval* interval = interval_at(reg_num(opr));
3740 if (op->id() != -1) {
3741 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3742 }
3743
3744 state_put(input_state, interval->assigned_reg(), interval->split_parent());
3745 state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3746 }
3747 }
3748
3749 // set output operands
3750 n = visitor.opr_count(LIR_OpVisitState::outputMode);
3751 for (j = 0; j < n; j++) {
3752 LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3753 if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3754 Interval* interval = interval_at(reg_num(opr));
3755 if (op->id() != -1) {
3756 interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3757 }
3758
3759 state_put(input_state, interval->assigned_reg(), interval->split_parent());
3760 state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3761 }
3762 }
3763 }
3764 assert(has_error == false, "Error in register allocation");
3765 }
3766
3767 #endif // ASSERT
3768
3769
3770
3771 // **** Implementation of MoveResolver ******************************
3772
3773 MoveResolver::MoveResolver(LinearScan* allocator) :
3774 _allocator(allocator),
3775 _insert_list(NULL),
3776 _insert_idx(-1),
3777 _insertion_buffer(),
3778 _mapping_from(8),
3779 _mapping_from_opr(8),
3780 _mapping_to(8),
3781 _multiple_reads_allowed(false)
3782 {
3783 for (int i = 0; i < LinearScan::nof_regs; i++) {
3784 _register_blocked[i] = 0;
3785 }
3786 DEBUG_ONLY(check_empty());
3787 }
3788
3789
3790 #ifdef ASSERT
3791
3792 void MoveResolver::check_empty() {
3793 assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3794 for (int i = 0; i < LinearScan::nof_regs; i++) {
3795 assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3796 }
3797 assert(_multiple_reads_allowed == false, "must have default value");
3798 }
3799
3800 void MoveResolver::verify_before_resolve() {
3801 assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3802 assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3803 assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3804
3805 int i, j;
3806 if (!_multiple_reads_allowed) {
3807 for (i = 0; i < _mapping_from.length(); i++) {
3808 for (j = i + 1; j < _mapping_from.length(); j++) {
3809 assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3810 }
3811 }
3812 }
3813
3814 for (i = 0; i < _mapping_to.length(); i++) {
3815 for (j = i + 1; j < _mapping_to.length(); j++) {
3816 assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3817 }
3818 }
3819
3820
3821 ResourceBitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3822 if (!_multiple_reads_allowed) {
3823 for (i = 0; i < _mapping_from.length(); i++) {
3824 Interval* it = _mapping_from.at(i);
3825 if (it != NULL) {
3826 assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3827 used_regs.set_bit(it->assigned_reg());
3828
3829 if (it->assigned_regHi() != LinearScan::any_reg) {
3830 assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3831 used_regs.set_bit(it->assigned_regHi());
3832 }
3833 }
3834 }
3835 }
3836
3837 used_regs.clear();
3838 for (i = 0; i < _mapping_to.length(); i++) {
3839 Interval* it = _mapping_to.at(i);
3840 assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3841 used_regs.set_bit(it->assigned_reg());
3842
3843 if (it->assigned_regHi() != LinearScan::any_reg) {
3844 assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3845 used_regs.set_bit(it->assigned_regHi());
3846 }
3847 }
3848
3849 used_regs.clear();
3850 for (i = 0; i < _mapping_from.length(); i++) {
3851 Interval* it = _mapping_from.at(i);
3852 if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3853 used_regs.set_bit(it->assigned_reg());
3854 }
3855 }
3856 for (i = 0; i < _mapping_to.length(); i++) {
3857 Interval* it = _mapping_to.at(i);
3858 assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3859 }
3860 }
3861
3862 #endif // ASSERT
3863
3864
3865 // mark assigned_reg and assigned_regHi of the interval as blocked
3866 void MoveResolver::block_registers(Interval* it) {
3867 int reg = it->assigned_reg();
3868 if (reg < LinearScan::nof_regs) {
3869 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3870 set_register_blocked(reg, 1);
3871 }
3872 reg = it->assigned_regHi();
3873 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3874 assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3875 set_register_blocked(reg, 1);
3876 }
3877 }
3878
3879 // mark assigned_reg and assigned_regHi of the interval as unblocked
3880 void MoveResolver::unblock_registers(Interval* it) {
3881 int reg = it->assigned_reg();
3882 if (reg < LinearScan::nof_regs) {
3883 assert(register_blocked(reg) > 0, "register already marked as unused");
3884 set_register_blocked(reg, -1);
3885 }
3886 reg = it->assigned_regHi();
3887 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3888 assert(register_blocked(reg) > 0, "register already marked as unused");
3889 set_register_blocked(reg, -1);
3890 }
3891 }
3892
3893 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3894 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3895 int from_reg = -1;
3896 int from_regHi = -1;
3897 if (from != NULL) {
3898 from_reg = from->assigned_reg();
3899 from_regHi = from->assigned_regHi();
3900 }
3901
3902 int reg = to->assigned_reg();
3903 if (reg < LinearScan::nof_regs) {
3904 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3905 return false;
3906 }
3907 }
3908 reg = to->assigned_regHi();
3909 if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3910 if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3911 return false;
3912 }
3913 }
3914
3915 return true;
3916 }
3917
3918
3919 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3920 assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3921 _insertion_buffer.init(list);
3922 }
3923
3924 void MoveResolver::append_insertion_buffer() {
3925 if (_insertion_buffer.initialized()) {
3926 _insertion_buffer.lir_list()->append(&_insertion_buffer);
3927 }
3928 assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3929
3930 _insert_list = NULL;
3931 _insert_idx = -1;
3932 }
3933
3934 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3935 assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3936 assert(from_interval->type() == to_interval->type(), "move between different types");
3937 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3938 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3939
3940 LIR_Opr from_opr = get_virtual_register(from_interval);
3941 LIR_Opr to_opr = get_virtual_register(to_interval);
3942
3943 if (!_multiple_reads_allowed) {
3944 // the last_use flag is an optimization for FPU stack allocation. When the same
3945 // input interval is used in more than one move, then it is too difficult to determine
3946 // if this move is really the last use.
3947 from_opr = from_opr->make_last_use();
3948 }
3949 _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3950
3951 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3952 }
3953
3954 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3955 assert(from_opr->type() == to_interval->type(), "move between different types");
3956 assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3957 assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3958
3959 LIR_Opr to_opr = get_virtual_register(to_interval);
3960 _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3961
3962 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3963 }
3964
3965 LIR_Opr MoveResolver::get_virtual_register(Interval* interval) {
3966 // Add a little fudge factor for the bailout since the bailout is only checked periodically. This allows us to hand out
3967 // a few extra registers before we really run out which helps to avoid to trip over assertions.
3968 int reg_num = interval->reg_num();
3969 if (reg_num + 20 >= LIR_Opr::vreg_max) {
3970 _allocator->bailout("out of virtual registers in linear scan");
3971 if (reg_num + 2 >= LIR_Opr::vreg_max) {
3972 // Wrap it around and continue until bailout really happens to avoid hitting assertions.
3973 reg_num = LIR_Opr::vreg_base;
3974 }
3975 }
3976 LIR_Opr vreg = LIR_OprFact::virtual_register(reg_num, interval->type());
3977 assert(vreg != LIR_OprFact::illegal(), "ran out of virtual registers");
3978 return vreg;
3979 }
3980
3981 void MoveResolver::resolve_mappings() {
3982 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3983 DEBUG_ONLY(verify_before_resolve());
3984
3985 // Block all registers that are used as input operands of a move.
3986 // When a register is blocked, no move to this register is emitted.
3987 // This is necessary for detecting cycles in moves.
3988 int i;
3989 for (i = _mapping_from.length() - 1; i >= 0; i--) {
3990 Interval* from_interval = _mapping_from.at(i);
3991 if (from_interval != NULL) {
3992 block_registers(from_interval);
3993 }
3994 }
3995
3996 int spill_candidate = -1;
3997 while (_mapping_from.length() > 0) {
3998 bool processed_interval = false;
3999
4000 for (i = _mapping_from.length() - 1; i >= 0; i--) {
4001 Interval* from_interval = _mapping_from.at(i);
4002 Interval* to_interval = _mapping_to.at(i);
4003
4004 if (save_to_process_move(from_interval, to_interval)) {
4005 // this interval can be processed because target is free
4006 if (from_interval != NULL) {
4007 insert_move(from_interval, to_interval);
4008 unblock_registers(from_interval);
4009 } else {
4010 insert_move(_mapping_from_opr.at(i), to_interval);
4011 }
4012 _mapping_from.remove_at(i);
4013 _mapping_from_opr.remove_at(i);
4014 _mapping_to.remove_at(i);
4015
4016 processed_interval = true;
4017 } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
4018 // this interval cannot be processed now because target is not free
4019 // it starts in a register, so it is a possible candidate for spilling
4020 spill_candidate = i;
4021 }
4022 }
4023
4024 if (!processed_interval) {
4025 // no move could be processed because there is a cycle in the move list
4026 // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
4027 guarantee(spill_candidate != -1, "no interval in register for spilling found");
4028
4029 // create a new spill interval and assign a stack slot to it
4030 Interval* from_interval = _mapping_from.at(spill_candidate);
4031 Interval* spill_interval = new Interval(-1);
4032 spill_interval->set_type(from_interval->type());
4033
4034 // add a dummy range because real position is difficult to calculate
4035 // Note: this range is a special case when the integrity of the allocation is checked
4036 spill_interval->add_range(1, 2);
4037
4038 // do not allocate a new spill slot for temporary interval, but
4039 // use spill slot assigned to from_interval. Otherwise moves from
4040 // one stack slot to another can happen (not allowed by LIR_Assembler
4041 int spill_slot = from_interval->canonical_spill_slot();
4042 if (spill_slot < 0) {
4043 spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
4044 from_interval->set_canonical_spill_slot(spill_slot);
4045 }
4046 spill_interval->assign_reg(spill_slot);
4047 allocator()->append_interval(spill_interval);
4048
4049 TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
4050
4051 // insert a move from register to stack and update the mapping
4052 insert_move(from_interval, spill_interval);
4053 _mapping_from.at_put(spill_candidate, spill_interval);
4054 unblock_registers(from_interval);
4055 }
4056 }
4057
4058 // reset to default value
4059 _multiple_reads_allowed = false;
4060
4061 // check that all intervals have been processed
4062 DEBUG_ONLY(check_empty());
4063 }
4064
4065
4066 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
4067 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4068 assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
4069
4070 create_insertion_buffer(insert_list);
4071 _insert_list = insert_list;
4072 _insert_idx = insert_idx;
4073 }
4074
4075 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
4076 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4077
4078 if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
4079 // insert position changed -> resolve current mappings
4080 resolve_mappings();
4081 }
4082
4083 if (insert_list != _insert_list) {
4084 // block changed -> append insertion_buffer because it is
4085 // bound to a specific block and create a new insertion_buffer
4086 append_insertion_buffer();
4087 create_insertion_buffer(insert_list);
4088 }
4089
4090 _insert_list = insert_list;
4091 _insert_idx = insert_idx;
4092 }
4093
4094 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
4095 TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4096
4097 _mapping_from.append(from_interval);
4098 _mapping_from_opr.append(LIR_OprFact::illegalOpr);
4099 _mapping_to.append(to_interval);
4100 }
4101
4102
4103 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
4104 TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4105 assert(from_opr->is_constant(), "only for constants");
4106
4107 _mapping_from.append(NULL);
4108 _mapping_from_opr.append(from_opr);
4109 _mapping_to.append(to_interval);
4110 }
4111
4112 void MoveResolver::resolve_and_append_moves() {
4113 if (has_mappings()) {
4114 resolve_mappings();
4115 }
4116 append_insertion_buffer();
4117 }
4118
4119
4120
4121 // **** Implementation of Range *************************************
4122
4123 Range::Range(int from, int to, Range* next) :
4124 _from(from),
4125 _to(to),
4126 _next(next)
4127 {
4128 }
4129
4130 // initialize sentinel
4131 Range* Range::_end = NULL;
4132 void Range::initialize(Arena* arena) {
4133 _end = new (arena) Range(max_jint, max_jint, NULL);
4134 }
4135
4136 int Range::intersects_at(Range* r2) const {
4137 const Range* r1 = this;
4138
4139 assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
4140 assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4141
4142 do {
4143 if (r1->from() < r2->from()) {
4144 if (r1->to() <= r2->from()) {
4145 r1 = r1->next(); if (r1 == _end) return -1;
4146 } else {
4147 return r2->from();
4148 }
4149 } else if (r2->from() < r1->from()) {
4150 if (r2->to() <= r1->from()) {
4151 r2 = r2->next(); if (r2 == _end) return -1;
4152 } else {
4153 return r1->from();
4154 }
4155 } else { // r1->from() == r2->from()
4156 if (r1->from() == r1->to()) {
4157 r1 = r1->next(); if (r1 == _end) return -1;
4158 } else if (r2->from() == r2->to()) {
4159 r2 = r2->next(); if (r2 == _end) return -1;
4160 } else {
4161 return r1->from();
4162 }
4163 }
4164 } while (true);
4165 }
4166
4167 #ifndef PRODUCT
4168 void Range::print(outputStream* out) const {
4169 out->print("[%d, %d[ ", _from, _to);
4170 }
4171 #endif
4172
4173
4174
4175 // **** Implementation of Interval **********************************
4176
4177 // initialize sentinel
4178 Interval* Interval::_end = NULL;
4179 void Interval::initialize(Arena* arena) {
4180 Range::initialize(arena);
4181 _end = new (arena) Interval(-1);
4182 }
4183
4184 Interval::Interval(int reg_num) :
4185 _reg_num(reg_num),
4186 _type(T_ILLEGAL),
4187 _first(Range::end()),
4188 _use_pos_and_kinds(12),
4189 _current(Range::end()),
4190 _next(_end),
4191 _state(invalidState),
4192 _assigned_reg(LinearScan::any_reg),
4193 _assigned_regHi(LinearScan::any_reg),
4194 _cached_to(-1),
4195 _cached_opr(LIR_OprFact::illegalOpr),
4196 _cached_vm_reg(VMRegImpl::Bad()),
4197 _split_children(NULL),
4198 _canonical_spill_slot(-1),
4199 _insert_move_when_activated(false),
4200 _spill_state(noDefinitionFound),
4201 _spill_definition_pos(-1),
4202 _register_hint(NULL)
4203 {
4204 _split_parent = this;
4205 _current_split_child = this;
4206 }
4207
4208 int Interval::calc_to() {
4209 assert(_first != Range::end(), "interval has no range");
4210
4211 Range* r = _first;
4212 while (r->next() != Range::end()) {
4213 r = r->next();
4214 }
4215 return r->to();
4216 }
4217
4218
4219 #ifdef ASSERT
4220 // consistency check of split-children
4221 void Interval::check_split_children() {
4222 if (_split_children != NULL && _split_children->length() > 0) {
4223 assert(is_split_parent(), "only split parents can have children");
4224
4225 for (int i = 0; i < _split_children->length(); i++) {
4226 Interval* i1 = _split_children->at(i);
4227
4228 assert(i1->split_parent() == this, "not a split child of this interval");
4229 assert(i1->type() == type(), "must be equal for all split children");
4230 assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4231
4232 for (int j = i + 1; j < _split_children->length(); j++) {
4233 Interval* i2 = _split_children->at(j);
4234
4235 assert(i1->reg_num() != i2->reg_num(), "same register number");
4236
4237 if (i1->from() < i2->from()) {
4238 assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4239 } else {
4240 assert(i2->from() < i1->from(), "intervals start at same op_id");
4241 assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4242 }
4243 }
4244 }
4245 }
4246 }
4247 #endif // ASSERT
4248
4249 Interval* Interval::register_hint(bool search_split_child) const {
4250 if (!search_split_child) {
4251 return _register_hint;
4252 }
4253
4254 if (_register_hint != NULL) {
4255 assert(_register_hint->is_split_parent(), "only split parents are valid hint registers");
4256
4257 if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4258 return _register_hint;
4259
4260 } else if (_register_hint->_split_children != NULL && _register_hint->_split_children->length() > 0) {
4261 // search the first split child that has a register assigned
4262 int len = _register_hint->_split_children->length();
4263 for (int i = 0; i < len; i++) {
4264 Interval* cur = _register_hint->_split_children->at(i);
4265
4266 if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4267 return cur;
4268 }
4269 }
4270 }
4271 }
4272
4273 // no hint interval found that has a register assigned
4274 return NULL;
4275 }
4276
4277
4278 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4279 assert(is_split_parent(), "can only be called for split parents");
4280 assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4281
4282 Interval* result;
4283 if (_split_children == NULL || _split_children->length() == 0) {
4284 result = this;
4285 } else {
4286 result = NULL;
4287 int len = _split_children->length();
4288
4289 // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4290 int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4291
4292 int i;
4293 for (i = 0; i < len; i++) {
4294 Interval* cur = _split_children->at(i);
4295 if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4296 if (i > 0) {
4297 // exchange current split child to start of list (faster access for next call)
4298 _split_children->at_put(i, _split_children->at(0));
4299 _split_children->at_put(0, cur);
4300 }
4301
4302 // interval found
4303 result = cur;
4304 break;
4305 }
4306 }
4307
4308 #ifdef ASSERT
4309 for (i = 0; i < len; i++) {
4310 Interval* tmp = _split_children->at(i);
4311 if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4312 tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4313 result->print();
4314 tmp->print();
4315 assert(false, "two valid result intervals found");
4316 }
4317 }
4318 #endif
4319 }
4320
4321 assert(result != NULL, "no matching interval found");
4322 assert(result->covers(op_id, mode), "op_id not covered by interval");
4323
4324 return result;
4325 }
4326
4327
4328 // returns the last split child that ends before the given op_id
4329 Interval* Interval::split_child_before_op_id(int op_id) {
4330 assert(op_id >= 0, "invalid op_id");
4331
4332 Interval* parent = split_parent();
4333 Interval* result = NULL;
4334
4335 assert(parent->_split_children != NULL, "no split children available");
4336 int len = parent->_split_children->length();
4337 assert(len > 0, "no split children available");
4338
4339 for (int i = len - 1; i >= 0; i--) {
4340 Interval* cur = parent->_split_children->at(i);
4341 if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4342 result = cur;
4343 }
4344 }
4345
4346 assert(result != NULL, "no split child found");
4347 return result;
4348 }
4349
4350
4351 // Note: use positions are sorted descending -> first use has highest index
4352 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4353 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4354
4355 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4356 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4357 return _use_pos_and_kinds.at(i);
4358 }
4359 }
4360 return max_jint;
4361 }
4362
4363 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4364 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4365
4366 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4367 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4368 return _use_pos_and_kinds.at(i);
4369 }
4370 }
4371 return max_jint;
4372 }
4373
4374 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4375 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4376
4377 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4378 if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4379 return _use_pos_and_kinds.at(i);
4380 }
4381 }
4382 return max_jint;
4383 }
4384
4385 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4386 assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4387
4388 int prev = 0;
4389 for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4390 if (_use_pos_and_kinds.at(i) > from) {
4391 return prev;
4392 }
4393 if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4394 prev = _use_pos_and_kinds.at(i);
4395 }
4396 }
4397 return prev;
4398 }
4399
4400 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4401 assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4402
4403 // do not add use positions for precolored intervals because
4404 // they are never used
4405 if (use_kind != noUse && reg_num() >= LIR_Opr::vreg_base) {
4406 #ifdef ASSERT
4407 assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4408 for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4409 assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4410 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4411 if (i > 0) {
4412 assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4413 }
4414 }
4415 #endif
4416
4417 // Note: add_use is called in descending order, so list gets sorted
4418 // automatically by just appending new use positions
4419 int len = _use_pos_and_kinds.length();
4420 if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4421 _use_pos_and_kinds.append(pos);
4422 _use_pos_and_kinds.append(use_kind);
4423 } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4424 assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4425 _use_pos_and_kinds.at_put(len - 1, use_kind);
4426 }
4427 }
4428 }
4429
4430 void Interval::add_range(int from, int to) {
4431 assert(from < to, "invalid range");
4432 assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4433 assert(from <= first()->to(), "not inserting at begin of interval");
4434
4435 if (first()->from() <= to) {
4436 // join intersecting ranges
4437 first()->set_from(MIN2(from, first()->from()));
4438 first()->set_to (MAX2(to, first()->to()));
4439 } else {
4440 // insert new range
4441 _first = new Range(from, to, first());
4442 }
4443 }
4444
4445 Interval* Interval::new_split_child() {
4446 // allocate new interval
4447 Interval* result = new Interval(-1);
4448 result->set_type(type());
4449
4450 Interval* parent = split_parent();
4451 result->_split_parent = parent;
4452 result->set_register_hint(parent);
4453
4454 // insert new interval in children-list of parent
4455 if (parent->_split_children == NULL) {
4456 assert(is_split_parent(), "list must be initialized at first split");
4457
4458 parent->_split_children = new IntervalList(4);
4459 parent->_split_children->append(this);
4460 }
4461 parent->_split_children->append(result);
4462
4463 return result;
4464 }
4465
4466 // split this interval at the specified position and return
4467 // the remainder as a new interval.
4468 //
4469 // when an interval is split, a bi-directional link is established between the original interval
4470 // (the split parent) and the intervals that are split off this interval (the split children)
4471 // When a split child is split again, the new created interval is also a direct child
4472 // of the original parent (there is no tree of split children stored, but a flat list)
4473 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4474 //
4475 // Note: The new interval has no valid reg_num
4476 Interval* Interval::split(int split_pos) {
4477 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4478
4479 // allocate new interval
4480 Interval* result = new_split_child();
4481
4482 // split the ranges
4483 Range* prev = NULL;
4484 Range* cur = _first;
4485 while (cur != Range::end() && cur->to() <= split_pos) {
4486 prev = cur;
4487 cur = cur->next();
4488 }
4489 assert(cur != Range::end(), "split interval after end of last range");
4490
4491 if (cur->from() < split_pos) {
4492 result->_first = new Range(split_pos, cur->to(), cur->next());
4493 cur->set_to(split_pos);
4494 cur->set_next(Range::end());
4495
4496 } else {
4497 assert(prev != NULL, "split before start of first range");
4498 result->_first = cur;
4499 prev->set_next(Range::end());
4500 }
4501 result->_current = result->_first;
4502 _cached_to = -1; // clear cached value
4503
4504 // split list of use positions
4505 int total_len = _use_pos_and_kinds.length();
4506 int start_idx = total_len - 2;
4507 while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4508 start_idx -= 2;
4509 }
4510
4511 intStack new_use_pos_and_kinds(total_len - start_idx);
4512 int i;
4513 for (i = start_idx + 2; i < total_len; i++) {
4514 new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4515 }
4516
4517 _use_pos_and_kinds.trunc_to(start_idx + 2);
4518 result->_use_pos_and_kinds = _use_pos_and_kinds;
4519 _use_pos_and_kinds = new_use_pos_and_kinds;
4520
4521 #ifdef ASSERT
4522 assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4523 assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4524 assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4525
4526 for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4527 assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4528 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4529 }
4530 for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4531 assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4532 assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4533 }
4534 #endif
4535
4536 return result;
4537 }
4538
4539 // split this interval at the specified position and return
4540 // the head as a new interval (the original interval is the tail)
4541 //
4542 // Currently, only the first range can be split, and the new interval
4543 // must not have split positions
4544 Interval* Interval::split_from_start(int split_pos) {
4545 assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4546 assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4547 assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4548 assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4549
4550 // allocate new interval
4551 Interval* result = new_split_child();
4552
4553 // the new created interval has only one range (checked by assertion above),
4554 // so the splitting of the ranges is very simple
4555 result->add_range(_first->from(), split_pos);
4556
4557 if (split_pos == _first->to()) {
4558 assert(_first->next() != Range::end(), "must not be at end");
4559 _first = _first->next();
4560 } else {
4561 _first->set_from(split_pos);
4562 }
4563
4564 return result;
4565 }
4566
4567
4568 // returns true if the op_id is inside the interval
4569 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4570 Range* cur = _first;
4571
4572 while (cur != Range::end() && cur->to() < op_id) {
4573 cur = cur->next();
4574 }
4575 if (cur != Range::end()) {
4576 assert(cur->to() != cur->next()->from(), "ranges not separated");
4577
4578 if (mode == LIR_OpVisitState::outputMode) {
4579 return cur->from() <= op_id && op_id < cur->to();
4580 } else {
4581 return cur->from() <= op_id && op_id <= cur->to();
4582 }
4583 }
4584 return false;
4585 }
4586
4587 // returns true if the interval has any hole between hole_from and hole_to
4588 // (even if the hole has only the length 1)
4589 bool Interval::has_hole_between(int hole_from, int hole_to) {
4590 assert(hole_from < hole_to, "check");
4591 assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4592
4593 Range* cur = _first;
4594 while (cur != Range::end()) {
4595 assert(cur->to() < cur->next()->from(), "no space between ranges");
4596
4597 // hole-range starts before this range -> hole
4598 if (hole_from < cur->from()) {
4599 return true;
4600
4601 // hole-range completely inside this range -> no hole
4602 } else if (hole_to <= cur->to()) {
4603 return false;
4604
4605 // overlapping of hole-range with this range -> hole
4606 } else if (hole_from <= cur->to()) {
4607 return true;
4608 }
4609
4610 cur = cur->next();
4611 }
4612
4613 return false;
4614 }
4615
4616 // Check if there is an intersection with any of the split children of 'interval'
4617 bool Interval::intersects_any_children_of(Interval* interval) const {
4618 if (interval->_split_children != NULL) {
4619 for (int i = 0; i < interval->_split_children->length(); i++) {
4620 if (intersects(interval->_split_children->at(i))) {
4621 return true;
4622 }
4623 }
4624 }
4625 return false;
4626 }
4627
4628
4629 #ifndef PRODUCT
4630 void Interval::print_on(outputStream* out, bool is_cfg_printer) const {
4631 const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4632 const char* UseKind2Name[] = { "N", "L", "S", "M" };
4633
4634 const char* type_name;
4635 if (reg_num() < LIR_Opr::vreg_base) {
4636 type_name = "fixed";
4637 } else {
4638 type_name = type2name(type());
4639 }
4640 out->print("%d %s ", reg_num(), type_name);
4641
4642 if (is_cfg_printer) {
4643 // Special version for compatibility with C1 Visualizer.
4644 LIR_Opr opr = LinearScan::get_operand(reg_num());
4645 if (opr->is_valid()) {
4646 out->print("\"");
4647 opr->print(out);
4648 out->print("\" ");
4649 }
4650 } else {
4651 // Improved output for normal debugging.
4652 if (reg_num() < LIR_Opr::vreg_base) {
4653 LinearScan::print_reg_num(out, assigned_reg());
4654 } else if (assigned_reg() != -1 && (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4655 LinearScan::calc_operand_for_interval(this)->print(out);
4656 } else {
4657 // Virtual register that has no assigned register yet.
4658 out->print("[ANY]");
4659 }
4660 out->print(" ");
4661 }
4662 out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4663
4664 // print ranges
4665 Range* cur = _first;
4666 while (cur != Range::end()) {
4667 cur->print(out);
4668 cur = cur->next();
4669 assert(cur != NULL, "range list not closed with range sentinel");
4670 }
4671
4672 // print use positions
4673 int prev = 0;
4674 assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4675 for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4676 assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4677 assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4678
4679 out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4680 prev = _use_pos_and_kinds.at(i);
4681 }
4682
4683 out->print(" \"%s\"", SpillState2Name[spill_state()]);
4684 out->cr();
4685 }
4686
4687 void Interval::print_parent() const {
4688 if (_split_parent != this) {
4689 _split_parent->print_on(tty);
4690 } else {
4691 tty->print_cr("Parent: this");
4692 }
4693 }
4694
4695 void Interval::print_children() const {
4696 if (_split_children == NULL) {
4697 tty->print_cr("Children: []");
4698 } else {
4699 tty->print_cr("Children:");
4700 for (int i = 0; i < _split_children->length(); i++) {
4701 tty->print("%d: ", i);
4702 _split_children->at(i)->print_on(tty);
4703 }
4704 }
4705 }
4706 #endif // NOT PRODUCT
4707
4708
4709
4710
4711 // **** Implementation of IntervalWalker ****************************
4712
4713 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4714 : _compilation(allocator->compilation())
4715 , _allocator(allocator)
4716 {
4717 _unhandled_first[fixedKind] = unhandled_fixed_first;
4718 _unhandled_first[anyKind] = unhandled_any_first;
4719 _active_first[fixedKind] = Interval::end();
4720 _inactive_first[fixedKind] = Interval::end();
4721 _active_first[anyKind] = Interval::end();
4722 _inactive_first[anyKind] = Interval::end();
4723 _current_position = -1;
4724 _current = NULL;
4725 next_interval();
4726 }
4727
4728
4729 // append interval in order of current range from()
4730 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4731 Interval* prev = NULL;
4732 Interval* cur = *list;
4733 while (cur->current_from() < interval->current_from()) {
4734 prev = cur; cur = cur->next();
4735 }
4736 if (prev == NULL) {
4737 *list = interval;
4738 } else {
4739 prev->set_next(interval);
4740 }
4741 interval->set_next(cur);
4742 }
4743
4744 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4745 assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4746
4747 Interval* prev = NULL;
4748 Interval* cur = *list;
4749 while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4750 prev = cur; cur = cur->next();
4751 }
4752 if (prev == NULL) {
4753 *list = interval;
4754 } else {
4755 prev->set_next(interval);
4756 }
4757 interval->set_next(cur);
4758 }
4759
4760
4761 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4762 while (*list != Interval::end() && *list != i) {
4763 list = (*list)->next_addr();
4764 }
4765 if (*list != Interval::end()) {
4766 assert(*list == i, "check");
4767 *list = (*list)->next();
4768 return true;
4769 } else {
4770 return false;
4771 }
4772 }
4773
4774 void IntervalWalker::remove_from_list(Interval* i) {
4775 bool deleted;
4776
4777 if (i->state() == activeState) {
4778 deleted = remove_from_list(active_first_addr(anyKind), i);
4779 } else {
4780 assert(i->state() == inactiveState, "invalid state");
4781 deleted = remove_from_list(inactive_first_addr(anyKind), i);
4782 }
4783
4784 assert(deleted, "interval has not been found in list");
4785 }
4786
4787
4788 void IntervalWalker::walk_to(IntervalState state, int from) {
4789 assert (state == activeState || state == inactiveState, "wrong state");
4790 for_each_interval_kind(kind) {
4791 Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4792 Interval* next = *prev;
4793 while (next->current_from() <= from) {
4794 Interval* cur = next;
4795 next = cur->next();
4796
4797 bool range_has_changed = false;
4798 while (cur->current_to() <= from) {
4799 cur->next_range();
4800 range_has_changed = true;
4801 }
4802
4803 // also handle move from inactive list to active list
4804 range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4805
4806 if (range_has_changed) {
4807 // remove cur from list
4808 *prev = next;
4809 if (cur->current_at_end()) {
4810 // move to handled state (not maintained as a list)
4811 cur->set_state(handledState);
4812 DEBUG_ONLY(interval_moved(cur, kind, state, handledState);)
4813 } else if (cur->current_from() <= from){
4814 // sort into active list
4815 append_sorted(active_first_addr(kind), cur);
4816 cur->set_state(activeState);
4817 if (*prev == cur) {
4818 assert(state == activeState, "check");
4819 prev = cur->next_addr();
4820 }
4821 DEBUG_ONLY(interval_moved(cur, kind, state, activeState);)
4822 } else {
4823 // sort into inactive list
4824 append_sorted(inactive_first_addr(kind), cur);
4825 cur->set_state(inactiveState);
4826 if (*prev == cur) {
4827 assert(state == inactiveState, "check");
4828 prev = cur->next_addr();
4829 }
4830 DEBUG_ONLY(interval_moved(cur, kind, state, inactiveState);)
4831 }
4832 } else {
4833 prev = cur->next_addr();
4834 continue;
4835 }
4836 }
4837 }
4838 }
4839
4840
4841 void IntervalWalker::next_interval() {
4842 IntervalKind kind;
4843 Interval* any = _unhandled_first[anyKind];
4844 Interval* fixed = _unhandled_first[fixedKind];
4845
4846 if (any != Interval::end()) {
4847 // intervals may start at same position -> prefer fixed interval
4848 kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4849
4850 assert (kind == fixedKind && fixed->from() <= any->from() ||
4851 kind == anyKind && any->from() <= fixed->from(), "wrong interval!!!");
4852 assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4853
4854 } else if (fixed != Interval::end()) {
4855 kind = fixedKind;
4856 } else {
4857 _current = NULL; return;
4858 }
4859 _current_kind = kind;
4860 _current = _unhandled_first[kind];
4861 _unhandled_first[kind] = _current->next();
4862 _current->set_next(Interval::end());
4863 _current->rewind_range();
4864 }
4865
4866
4867 void IntervalWalker::walk_to(int lir_op_id) {
4868 assert(_current_position <= lir_op_id, "can not walk backwards");
4869 while (current() != NULL) {
4870 bool is_active = current()->from() <= lir_op_id;
4871 int id = is_active ? current()->from() : lir_op_id;
4872
4873 TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4874
4875 // set _current_position prior to call of walk_to
4876 _current_position = id;
4877
4878 // call walk_to even if _current_position == id
4879 walk_to(activeState, id);
4880 walk_to(inactiveState, id);
4881
4882 if (is_active) {
4883 current()->set_state(activeState);
4884 if (activate_current()) {
4885 append_sorted(active_first_addr(current_kind()), current());
4886 DEBUG_ONLY(interval_moved(current(), current_kind(), unhandledState, activeState);)
4887 }
4888
4889 next_interval();
4890 } else {
4891 return;
4892 }
4893 }
4894 }
4895
4896 #ifdef ASSERT
4897 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4898 if (TraceLinearScanLevel >= 4) {
4899 #define print_state(state) \
4900 switch(state) {\
4901 case unhandledState: tty->print("unhandled"); break;\
4902 case activeState: tty->print("active"); break;\
4903 case inactiveState: tty->print("inactive"); break;\
4904 case handledState: tty->print("handled"); break;\
4905 default: ShouldNotReachHere(); \
4906 }
4907
4908 print_state(from); tty->print(" to "); print_state(to);
4909 tty->fill_to(23);
4910 interval->print();
4911
4912 #undef print_state
4913 }
4914 }
4915 #endif // ASSERT
4916
4917 // **** Implementation of LinearScanWalker **************************
4918
4919 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4920 : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4921 , _move_resolver(allocator)
4922 {
4923 for (int i = 0; i < LinearScan::nof_regs; i++) {
4924 _spill_intervals[i] = new IntervalList(2);
4925 }
4926 }
4927
4928
4929 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4930 for (int i = _first_reg; i <= _last_reg; i++) {
4931 _use_pos[i] = max_jint;
4932
4933 if (!only_process_use_pos) {
4934 _block_pos[i] = max_jint;
4935 _spill_intervals[i]->clear();
4936 }
4937 }
4938 }
4939
4940 inline void LinearScanWalker::exclude_from_use(int reg) {
4941 assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4942 if (reg >= _first_reg && reg <= _last_reg) {
4943 _use_pos[reg] = 0;
4944 }
4945 }
4946 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4947 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4948
4949 exclude_from_use(i->assigned_reg());
4950 exclude_from_use(i->assigned_regHi());
4951 }
4952
4953 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4954 assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4955
4956 if (reg >= _first_reg && reg <= _last_reg) {
4957 if (_use_pos[reg] > use_pos) {
4958 _use_pos[reg] = use_pos;
4959 }
4960 if (!only_process_use_pos) {
4961 _spill_intervals[reg]->append(i);
4962 }
4963 }
4964 }
4965 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4966 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4967 if (use_pos != -1) {
4968 set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4969 set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4970 }
4971 }
4972
4973 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4974 if (reg >= _first_reg && reg <= _last_reg) {
4975 if (_block_pos[reg] > block_pos) {
4976 _block_pos[reg] = block_pos;
4977 }
4978 if (_use_pos[reg] > block_pos) {
4979 _use_pos[reg] = block_pos;
4980 }
4981 }
4982 }
4983 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4984 assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4985 if (block_pos != -1) {
4986 set_block_pos(i->assigned_reg(), i, block_pos);
4987 set_block_pos(i->assigned_regHi(), i, block_pos);
4988 }
4989 }
4990
4991
4992 void LinearScanWalker::free_exclude_active_fixed() {
4993 Interval* list = active_first(fixedKind);
4994 while (list != Interval::end()) {
4995 assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
4996 exclude_from_use(list);
4997 list = list->next();
4998 }
4999 }
5000
5001 void LinearScanWalker::free_exclude_active_any() {
5002 Interval* list = active_first(anyKind);
5003 while (list != Interval::end()) {
5004 exclude_from_use(list);
5005 list = list->next();
5006 }
5007 }
5008
5009 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
5010 Interval* list = inactive_first(fixedKind);
5011 while (list != Interval::end()) {
5012 if (cur->to() <= list->current_from()) {
5013 assert(list->current_intersects_at(cur) == -1, "must not intersect");
5014 set_use_pos(list, list->current_from(), true);
5015 } else {
5016 set_use_pos(list, list->current_intersects_at(cur), true);
5017 }
5018 list = list->next();
5019 }
5020 }
5021
5022 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
5023 Interval* list = inactive_first(anyKind);
5024 while (list != Interval::end()) {
5025 set_use_pos(list, list->current_intersects_at(cur), true);
5026 list = list->next();
5027 }
5028 }
5029
5030 void LinearScanWalker::spill_exclude_active_fixed() {
5031 Interval* list = active_first(fixedKind);
5032 while (list != Interval::end()) {
5033 exclude_from_use(list);
5034 list = list->next();
5035 }
5036 }
5037
5038 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
5039 Interval* list = inactive_first(fixedKind);
5040 while (list != Interval::end()) {
5041 if (cur->to() > list->current_from()) {
5042 set_block_pos(list, list->current_intersects_at(cur));
5043 } else {
5044 assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
5045 }
5046
5047 list = list->next();
5048 }
5049 }
5050
5051 void LinearScanWalker::spill_collect_active_any() {
5052 Interval* list = active_first(anyKind);
5053 while (list != Interval::end()) {
5054 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5055 list = list->next();
5056 }
5057 }
5058
5059 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
5060 Interval* list = inactive_first(anyKind);
5061 while (list != Interval::end()) {
5062 if (list->current_intersects(cur)) {
5063 set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5064 }
5065 list = list->next();
5066 }
5067 }
5068
5069
5070 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
5071 // output all moves here. When source and target are equal, the move is
5072 // optimized away later in assign_reg_nums
5073
5074 op_id = (op_id + 1) & ~1;
5075 BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
5076 assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
5077
5078 // calculate index of instruction inside instruction list of current block
5079 // the minimal index (for a block with no spill moves) can be calculated because the
5080 // numbering of instructions is known.
5081 // When the block already contains spill moves, the index must be increased until the
5082 // correct index is reached.
5083 LIR_OpList* list = op_block->lir()->instructions_list();
5084 int index = (op_id - list->at(0)->id()) / 2;
5085 assert(list->at(index)->id() <= op_id, "error in calculation");
5086
5087 while (list->at(index)->id() != op_id) {
5088 index++;
5089 assert(0 <= index && index < list->length(), "index out of bounds");
5090 }
5091 assert(1 <= index && index < list->length(), "index out of bounds");
5092 assert(list->at(index)->id() == op_id, "error in calculation");
5093
5094 // insert new instruction before instruction at position index
5095 _move_resolver.move_insert_position(op_block->lir(), index - 1);
5096 _move_resolver.add_mapping(src_it, dst_it);
5097 }
5098
5099
5100 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
5101 int from_block_nr = min_block->linear_scan_number();
5102 int to_block_nr = max_block->linear_scan_number();
5103
5104 assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
5105 assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
5106 assert(from_block_nr < to_block_nr, "must cross block boundary");
5107
5108 // Try to split at end of max_block. If this would be after
5109 // max_split_pos, then use the begin of max_block
5110 int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
5111 if (optimal_split_pos > max_split_pos) {
5112 optimal_split_pos = max_block->first_lir_instruction_id();
5113 }
5114
5115 int min_loop_depth = max_block->loop_depth();
5116 for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5117 BlockBegin* cur = block_at(i);
5118
5119 if (cur->loop_depth() < min_loop_depth) {
5120 // block with lower loop-depth found -> split at the end of this block
5121 min_loop_depth = cur->loop_depth();
5122 optimal_split_pos = cur->last_lir_instruction_id() + 2;
5123 }
5124 }
5125 assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5126
5127 return optimal_split_pos;
5128 }
5129
5130
5131 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5132 int optimal_split_pos = -1;
5133 if (min_split_pos == max_split_pos) {
5134 // trivial case, no optimization of split position possible
5135 TRACE_LINEAR_SCAN(4, tty->print_cr(" min-pos and max-pos are equal, no optimization possible"));
5136 optimal_split_pos = min_split_pos;
5137
5138 } else {
5139 assert(min_split_pos < max_split_pos, "must be true then");
5140 assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5141
5142 // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5143 // beginning of a block, then min_split_pos is also a possible split position.
5144 // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5145 BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5146
5147 // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5148 // when an interval ends at the end of the last block of the method
5149 // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5150 // block at this op_id)
5151 BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5152
5153 assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5154 if (min_block == max_block) {
5155 // split position cannot be moved to block boundary, so split as late as possible
5156 TRACE_LINEAR_SCAN(4, tty->print_cr(" cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5157 optimal_split_pos = max_split_pos;
5158
5159 } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5160 // Do not move split position if the interval has a hole before max_split_pos.
5161 // Intervals resulting from Phi-Functions have more than one definition (marked
5162 // as mustHaveRegister) with a hole before each definition. When the register is needed
5163 // for the second definition, an earlier reloading is unnecessary.
5164 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has hole just before max_split_pos, so splitting at max_split_pos"));
5165 optimal_split_pos = max_split_pos;
5166
5167 } else {
5168 // search optimal block boundary between min_split_pos and max_split_pos
5169 TRACE_LINEAR_SCAN(4, tty->print_cr(" moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5170
5171 if (do_loop_optimization) {
5172 // Loop optimization: if a loop-end marker is found between min- and max-position,
5173 // then split before this loop
5174 int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5175 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization: loop end found at pos %d", loop_end_pos));
5176
5177 assert(loop_end_pos > min_split_pos, "invalid order");
5178 if (loop_end_pos < max_split_pos) {
5179 // loop-end marker found between min- and max-position
5180 // if it is not the end marker for the same loop as the min-position, then move
5181 // the max-position to this loop block.
5182 // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5183 // of the interval (normally, only mustHaveRegister causes a reloading)
5184 BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5185
5186 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5187 assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5188
5189 optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5190 if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5191 optimal_split_pos = -1;
5192 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization not necessary"));
5193 } else {
5194 TRACE_LINEAR_SCAN(4, tty->print_cr(" loop optimization successful"));
5195 }
5196 }
5197 }
5198
5199 if (optimal_split_pos == -1) {
5200 // not calculated by loop optimization
5201 optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5202 }
5203 }
5204 }
5205 TRACE_LINEAR_SCAN(4, tty->print_cr(" optimal split position: %d", optimal_split_pos));
5206
5207 return optimal_split_pos;
5208 }
5209
5210
5211 /*
5212 split an interval at the optimal position between min_split_pos and
5213 max_split_pos in two parts:
5214 1) the left part has already a location assigned
5215 2) the right part is sorted into to the unhandled-list
5216 */
5217 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5218 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting interval: "); it->print());
5219 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos));
5220
5221 assert(it->from() < min_split_pos, "cannot split at start of interval");
5222 assert(current_position() < min_split_pos, "cannot split before current position");
5223 assert(min_split_pos <= max_split_pos, "invalid order");
5224 assert(max_split_pos <= it->to(), "cannot split after end of interval");
5225
5226 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5227
5228 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5229 assert(optimal_split_pos <= it->to(), "cannot split after end of interval");
5230 assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5231
5232 if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5233 // the split position would be just before the end of the interval
5234 // -> no split at all necessary
5235 TRACE_LINEAR_SCAN(4, tty->print_cr(" no split necessary because optimal split position is at end of interval"));
5236 return;
5237 }
5238
5239 // must calculate this before the actual split is performed and before split position is moved to odd op_id
5240 bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5241
5242 if (!allocator()->is_block_begin(optimal_split_pos)) {
5243 // move position before actual instruction (odd op_id)
5244 optimal_split_pos = (optimal_split_pos - 1) | 1;
5245 }
5246
5247 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos));
5248 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5249 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5250
5251 Interval* split_part = it->split(optimal_split_pos);
5252
5253 allocator()->append_interval(split_part);
5254 allocator()->copy_register_flags(it, split_part);
5255 split_part->set_insert_move_when_activated(move_necessary);
5256 append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5257
5258 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5259 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print());
5260 TRACE_LINEAR_SCAN(2, tty->print (" "); split_part->print());
5261 }
5262
5263 /*
5264 split an interval at the optimal position between min_split_pos and
5265 max_split_pos in two parts:
5266 1) the left part has already a location assigned
5267 2) the right part is always on the stack and therefore ignored in further processing
5268 */
5269 void LinearScanWalker::split_for_spilling(Interval* it) {
5270 // calculate allowed range of splitting position
5271 int max_split_pos = current_position();
5272 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5273
5274 TRACE_LINEAR_SCAN(2, tty->print ("----- splitting and spilling interval: "); it->print());
5275 TRACE_LINEAR_SCAN(2, tty->print_cr(" between %d and %d", min_split_pos, max_split_pos));
5276
5277 assert(it->state() == activeState, "why spill interval that is not active?");
5278 assert(it->from() <= min_split_pos, "cannot split before start of interval");
5279 assert(min_split_pos <= max_split_pos, "invalid order");
5280 assert(max_split_pos < it->to(), "cannot split at end end of interval");
5281 assert(current_position() < it->to(), "interval must not end before current position");
5282
5283 if (min_split_pos == it->from()) {
5284 // the whole interval is never used, so spill it entirely to memory
5285 TRACE_LINEAR_SCAN(2, tty->print_cr(" spilling entire interval because split pos is at beginning of interval"));
5286 assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5287
5288 allocator()->assign_spill_slot(it);
5289 allocator()->change_spill_state(it, min_split_pos);
5290
5291 // Also kick parent intervals out of register to memory when they have no use
5292 // position. This avoids short interval in register surrounded by intervals in
5293 // memory -> avoid useless moves from memory to register and back
5294 Interval* parent = it;
5295 while (parent != NULL && parent->is_split_child()) {
5296 parent = parent->split_child_before_op_id(parent->from());
5297
5298 if (parent->assigned_reg() < LinearScan::nof_regs) {
5299 if (parent->first_usage(shouldHaveRegister) == max_jint) {
5300 // parent is never used, so kick it out of its assigned register
5301 TRACE_LINEAR_SCAN(4, tty->print_cr(" kicking out interval %d out of its register because it is never used", parent->reg_num()));
5302 allocator()->assign_spill_slot(parent);
5303 } else {
5304 // do not go further back because the register is actually used by the interval
5305 parent = NULL;
5306 }
5307 }
5308 }
5309
5310 } else {
5311 // search optimal split pos, split interval and spill only the right hand part
5312 int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5313
5314 assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5315 assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5316 assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5317
5318 if (!allocator()->is_block_begin(optimal_split_pos)) {
5319 // move position before actual instruction (odd op_id)
5320 optimal_split_pos = (optimal_split_pos - 1) | 1;
5321 }
5322
5323 TRACE_LINEAR_SCAN(4, tty->print_cr(" splitting at position %d", optimal_split_pos));
5324 assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5325 assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5326
5327 Interval* spilled_part = it->split(optimal_split_pos);
5328 allocator()->append_interval(spilled_part);
5329 allocator()->assign_spill_slot(spilled_part);
5330 allocator()->change_spill_state(spilled_part, optimal_split_pos);
5331
5332 if (!allocator()->is_block_begin(optimal_split_pos)) {
5333 TRACE_LINEAR_SCAN(4, tty->print_cr(" inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5334 insert_move(optimal_split_pos, it, spilled_part);
5335 }
5336
5337 // the current_split_child is needed later when moves are inserted for reloading
5338 assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5339 spilled_part->make_current_split_child();
5340
5341 TRACE_LINEAR_SCAN(2, tty->print_cr(" split interval in two parts"));
5342 TRACE_LINEAR_SCAN(2, tty->print (" "); it->print());
5343 TRACE_LINEAR_SCAN(2, tty->print (" "); spilled_part->print());
5344 }
5345 }
5346
5347
5348 void LinearScanWalker::split_stack_interval(Interval* it) {
5349 int min_split_pos = current_position() + 1;
5350 int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5351
5352 split_before_usage(it, min_split_pos, max_split_pos);
5353 }
5354
5355 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5356 int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5357 int max_split_pos = register_available_until;
5358
5359 split_before_usage(it, min_split_pos, max_split_pos);
5360 }
5361
5362 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5363 assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5364
5365 int current_pos = current_position();
5366 if (it->state() == inactiveState) {
5367 // the interval is currently inactive, so no spill slot is needed for now.
5368 // when the split part is activated, the interval has a new chance to get a register,
5369 // so in the best case no stack slot is necessary
5370 assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5371 split_before_usage(it, current_pos + 1, current_pos + 1);
5372
5373 } else {
5374 // search the position where the interval must have a register and split
5375 // at the optimal position before.
5376 // The new created part is added to the unhandled list and will get a register
5377 // when it is activated
5378 int min_split_pos = current_pos + 1;
5379 int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5380
5381 split_before_usage(it, min_split_pos, max_split_pos);
5382
5383 assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5384 split_for_spilling(it);
5385 }
5386 }
5387
5388 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5389 int min_full_reg = any_reg;
5390 int max_partial_reg = any_reg;
5391
5392 for (int i = _first_reg; i <= _last_reg; i++) {
5393 if (i == ignore_reg) {
5394 // this register must be ignored
5395
5396 } else if (_use_pos[i] >= interval_to) {
5397 // this register is free for the full interval
5398 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5399 min_full_reg = i;
5400 }
5401 } else if (_use_pos[i] > reg_needed_until) {
5402 // this register is at least free until reg_needed_until
5403 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5404 max_partial_reg = i;
5405 }
5406 }
5407 }
5408
5409 if (min_full_reg != any_reg) {
5410 return min_full_reg;
5411 } else if (max_partial_reg != any_reg) {
5412 *need_split = true;
5413 return max_partial_reg;
5414 } else {
5415 return any_reg;
5416 }
5417 }
5418
5419 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5420 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5421
5422 int min_full_reg = any_reg;
5423 int max_partial_reg = any_reg;
5424
5425 for (int i = _first_reg; i < _last_reg; i+=2) {
5426 if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5427 // this register is free for the full interval
5428 if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5429 min_full_reg = i;
5430 }
5431 } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5432 // this register is at least free until reg_needed_until
5433 if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5434 max_partial_reg = i;
5435 }
5436 }
5437 }
5438
5439 if (min_full_reg != any_reg) {
5440 return min_full_reg;
5441 } else if (max_partial_reg != any_reg) {
5442 *need_split = true;
5443 return max_partial_reg;
5444 } else {
5445 return any_reg;
5446 }
5447 }
5448
5449 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5450 TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5451
5452 init_use_lists(true);
5453 free_exclude_active_fixed();
5454 free_exclude_active_any();
5455 free_collect_inactive_fixed(cur);
5456 free_collect_inactive_any(cur);
5457 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5458
5459 // _use_pos contains the start of the next interval that has this register assigned
5460 // (either as a fixed register or a normal allocated register in the past)
5461 // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5462 #ifdef ASSERT
5463 if (TraceLinearScanLevel >= 4) {
5464 tty->print_cr(" state of registers:");
5465 for (int i = _first_reg; i <= _last_reg; i++) {
5466 tty->print(" reg %d (", i);
5467 LinearScan::print_reg_num(i);
5468 tty->print_cr("): use_pos: %d", _use_pos[i]);
5469 }
5470 }
5471 #endif
5472
5473 int hint_reg, hint_regHi;
5474 Interval* register_hint = cur->register_hint();
5475 if (register_hint != NULL) {
5476 hint_reg = register_hint->assigned_reg();
5477 hint_regHi = register_hint->assigned_regHi();
5478
5479 if (_num_phys_regs == 2 && allocator()->is_precolored_cpu_interval(register_hint)) {
5480 assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5481 hint_regHi = hint_reg + 1; // connect e.g. eax-edx
5482 }
5483 #ifdef ASSERT
5484 if (TraceLinearScanLevel >= 4) {
5485 tty->print(" hint registers %d (", hint_reg);
5486 LinearScan::print_reg_num(hint_reg);
5487 tty->print("), %d (", hint_regHi);
5488 LinearScan::print_reg_num(hint_regHi);
5489 tty->print(") from interval ");
5490 register_hint->print();
5491 }
5492 #endif
5493 } else {
5494 hint_reg = any_reg;
5495 hint_regHi = any_reg;
5496 }
5497 assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5498 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5499
5500 // the register must be free at least until this position
5501 int reg_needed_until = cur->from() + 1;
5502 int interval_to = cur->to();
5503
5504 bool need_split = false;
5505 int split_pos;
5506 int reg;
5507 int regHi = any_reg;
5508
5509 if (_adjacent_regs) {
5510 reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5511 regHi = reg + 1;
5512 if (reg == any_reg) {
5513 return false;
5514 }
5515 split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5516
5517 } else {
5518 reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5519 if (reg == any_reg) {
5520 return false;
5521 }
5522 split_pos = _use_pos[reg];
5523
5524 if (_num_phys_regs == 2) {
5525 regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5526
5527 if (_use_pos[reg] < interval_to && regHi == any_reg) {
5528 // do not split interval if only one register can be assigned until the split pos
5529 // (when one register is found for the whole interval, split&spill is only
5530 // performed for the hi register)
5531 return false;
5532
5533 } else if (regHi != any_reg) {
5534 split_pos = MIN2(split_pos, _use_pos[regHi]);
5535
5536 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5537 if (reg > regHi) {
5538 int temp = reg;
5539 reg = regHi;
5540 regHi = temp;
5541 }
5542 }
5543 }
5544 }
5545
5546 cur->assign_reg(reg, regHi);
5547 #ifdef ASSERT
5548 if (TraceLinearScanLevel >= 2) {
5549 tty->print(" selected registers %d (", reg);
5550 LinearScan::print_reg_num(reg);
5551 tty->print("), %d (", regHi);
5552 LinearScan::print_reg_num(regHi);
5553 tty->print_cr(")");
5554 }
5555 #endif
5556 assert(split_pos > 0, "invalid split_pos");
5557 if (need_split) {
5558 // register not available for full interval, so split it
5559 split_when_partial_register_available(cur, split_pos);
5560 }
5561
5562 // only return true if interval is completely assigned
5563 return _num_phys_regs == 1 || regHi != any_reg;
5564 }
5565
5566
5567 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int ignore_reg, bool* need_split) {
5568 int max_reg = any_reg;
5569
5570 for (int i = _first_reg; i <= _last_reg; i++) {
5571 if (i == ignore_reg) {
5572 // this register must be ignored
5573
5574 } else if (_use_pos[i] > reg_needed_until) {
5575 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5576 max_reg = i;
5577 }
5578 }
5579 }
5580
5581 if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5582 *need_split = true;
5583 }
5584
5585 return max_reg;
5586 }
5587
5588 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, bool* need_split) {
5589 assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5590
5591 int max_reg = any_reg;
5592
5593 for (int i = _first_reg; i < _last_reg; i+=2) {
5594 if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5595 if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5596 max_reg = i;
5597 }
5598 }
5599 }
5600
5601 if (max_reg != any_reg &&
5602 (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to)) {
5603 *need_split = true;
5604 }
5605
5606 return max_reg;
5607 }
5608
5609 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5610 assert(reg != any_reg, "no register assigned");
5611
5612 for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5613 Interval* it = _spill_intervals[reg]->at(i);
5614 remove_from_list(it);
5615 split_and_spill_interval(it);
5616 }
5617
5618 if (regHi != any_reg) {
5619 IntervalList* processed = _spill_intervals[reg];
5620 for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5621 Interval* it = _spill_intervals[regHi]->at(i);
5622 if (processed->find(it) == -1) {
5623 remove_from_list(it);
5624 split_and_spill_interval(it);
5625 }
5626 }
5627 }
5628 }
5629
5630
5631 // Split an Interval and spill it to memory so that cur can be placed in a register
5632 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5633 TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5634
5635 // collect current usage of registers
5636 init_use_lists(false);
5637 spill_exclude_active_fixed();
5638 assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5639 spill_block_inactive_fixed(cur);
5640 spill_collect_active_any();
5641 spill_collect_inactive_any(cur);
5642
5643 #ifdef ASSERT
5644 if (TraceLinearScanLevel >= 4) {
5645 tty->print_cr(" state of registers:");
5646 for (int i = _first_reg; i <= _last_reg; i++) {
5647 tty->print(" reg %d(", i);
5648 LinearScan::print_reg_num(i);
5649 tty->print("): use_pos: %d, block_pos: %d, intervals: ", _use_pos[i], _block_pos[i]);
5650 for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5651 tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5652 }
5653 tty->cr();
5654 }
5655 }
5656 #endif
5657
5658 // the register must be free at least until this position
5659 int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5660 int interval_to = cur->to();
5661 assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5662
5663 int split_pos = 0;
5664 int use_pos = 0;
5665 bool need_split = false;
5666 int reg, regHi;
5667
5668 if (_adjacent_regs) {
5669 reg = find_locked_double_reg(reg_needed_until, interval_to, &need_split);
5670 regHi = reg + 1;
5671
5672 if (reg != any_reg) {
5673 use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5674 split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5675 }
5676 } else {
5677 reg = find_locked_reg(reg_needed_until, interval_to, cur->assigned_reg(), &need_split);
5678 regHi = any_reg;
5679
5680 if (reg != any_reg) {
5681 use_pos = _use_pos[reg];
5682 split_pos = _block_pos[reg];
5683
5684 if (_num_phys_regs == 2) {
5685 if (cur->assigned_reg() != any_reg) {
5686 regHi = reg;
5687 reg = cur->assigned_reg();
5688 } else {
5689 regHi = find_locked_reg(reg_needed_until, interval_to, reg, &need_split);
5690 if (regHi != any_reg) {
5691 use_pos = MIN2(use_pos, _use_pos[regHi]);
5692 split_pos = MIN2(split_pos, _block_pos[regHi]);
5693 }
5694 }
5695
5696 if (regHi != any_reg && reg > regHi) {
5697 // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5698 int temp = reg;
5699 reg = regHi;
5700 regHi = temp;
5701 }
5702 }
5703 }
5704 }
5705
5706 if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5707 // the first use of cur is later than the spilling position -> spill cur
5708 TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5709
5710 if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5711 assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5712 // assign a reasonable register and do a bailout in product mode to avoid errors
5713 allocator()->assign_spill_slot(cur);
5714 BAILOUT("LinearScan: no register found");
5715 }
5716
5717 split_and_spill_interval(cur);
5718 } else {
5719 #ifdef ASSERT
5720 if (TraceLinearScanLevel >= 4) {
5721 tty->print("decided to use register %d (", reg);
5722 LinearScan::print_reg_num(reg);
5723 tty->print("), %d (", regHi);
5724 LinearScan::print_reg_num(regHi);
5725 tty->print_cr(")");
5726 }
5727 #endif
5728 assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5729 assert(split_pos > 0, "invalid split_pos");
5730 assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5731
5732 cur->assign_reg(reg, regHi);
5733 if (need_split) {
5734 // register not available for full interval, so split it
5735 split_when_partial_register_available(cur, split_pos);
5736 }
5737
5738 // perform splitting and spilling for all affected intervals
5739 split_and_spill_intersecting_intervals(reg, regHi);
5740 }
5741 }
5742
5743 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5744 #ifdef X86
5745 // fast calculation of intervals that can never get a register because the
5746 // the next instruction is a call that blocks all registers
5747 // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5748
5749 // check if this interval is the result of a split operation
5750 // (an interval got a register until this position)
5751 int pos = cur->from();
5752 if ((pos & 1) == 1) {
5753 // the current instruction is a call that blocks all registers
5754 if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5755 TRACE_LINEAR_SCAN(4, tty->print_cr(" free register cannot be available because all registers blocked by following call"));
5756
5757 // safety check that there is really no register available
5758 assert(alloc_free_reg(cur) == false, "found a register for this interval");
5759 return true;
5760 }
5761
5762 }
5763 #endif
5764 return false;
5765 }
5766
5767 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5768 BasicType type = cur->type();
5769 _num_phys_regs = LinearScan::num_physical_regs(type);
5770 _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5771
5772 if (pd_init_regs_for_alloc(cur)) {
5773 // the appropriate register range was selected.
5774 } else if (type == T_FLOAT || type == T_DOUBLE) {
5775 _first_reg = pd_first_fpu_reg;
5776 _last_reg = pd_last_fpu_reg;
5777 } else {
5778 _first_reg = pd_first_cpu_reg;
5779 _last_reg = FrameMap::last_cpu_reg();
5780 }
5781
5782 assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5783 assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5784 }
5785
5786
5787 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5788 if (op->code() != lir_move) {
5789 return false;
5790 }
5791 assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5792
5793 LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5794 LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5795 return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5796 }
5797
5798 // optimization (especially for phi functions of nested loops):
5799 // assign same spill slot to non-intersecting intervals
5800 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5801 if (cur->is_split_child()) {
5802 // optimization is only suitable for split parents
5803 return;
5804 }
5805
5806 Interval* register_hint = cur->register_hint(false);
5807 if (register_hint == NULL) {
5808 // cur is not the target of a move, otherwise register_hint would be set
5809 return;
5810 }
5811 assert(register_hint->is_split_parent(), "register hint must be split parent");
5812
5813 if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5814 // combining the stack slots for intervals where spill move optimization is applied
5815 // is not benefitial and would cause problems
5816 return;
5817 }
5818
5819 int begin_pos = cur->from();
5820 int end_pos = cur->to();
5821 if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5822 // safety check that lir_op_with_id is allowed
5823 return;
5824 }
5825
5826 if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5827 // cur and register_hint are not connected with two moves
5828 return;
5829 }
5830
5831 Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5832 Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5833 if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5834 // register_hint must be split, otherwise the re-writing of use positions does not work
5835 return;
5836 }
5837
5838 assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5839 assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5840 assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5841 assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5842
5843 if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5844 // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5845 return;
5846 }
5847 assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5848 assert(!cur->intersects(register_hint), "cur should not intersect register_hint");
5849
5850 if (cur->intersects_any_children_of(register_hint)) {
5851 // Bail out if cur intersects any split children of register_hint, which have the same spill slot as their parent. An overlap of two intervals with
5852 // the same spill slot could result in a situation where both intervals are spilled at the same time to the same stack location which is not correct.
5853 return;
5854 }
5855
5856 // modify intervals such that cur gets the same stack slot as register_hint
5857 // delete use positions to prevent the intervals to get a register at beginning
5858 cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5859 cur->remove_first_use_pos();
5860 end_hint->remove_first_use_pos();
5861 }
5862
5863
5864 // allocate a physical register or memory location to an interval
5865 bool LinearScanWalker::activate_current() {
5866 Interval* cur = current();
5867 bool result = true;
5868
5869 TRACE_LINEAR_SCAN(2, tty->print ("+++++ activating interval "); cur->print());
5870 TRACE_LINEAR_SCAN(4, tty->print_cr(" split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5871
5872 if (cur->assigned_reg() >= LinearScan::nof_regs) {
5873 // activating an interval that has a stack slot assigned -> split it at first use position
5874 // used for method parameters
5875 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval has spill slot assigned (method parameter) -> split it before first use"));
5876
5877 split_stack_interval(cur);
5878 result = false;
5879
5880 } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5881 // activating an interval that must start in a stack slot, but may get a register later
5882 // used for lir_roundfp: rounding is done by store to stack and reload later
5883 TRACE_LINEAR_SCAN(4, tty->print_cr(" interval must start in stack slot -> split it before first use"));
5884 assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5885
5886 allocator()->assign_spill_slot(cur);
5887 split_stack_interval(cur);
5888 result = false;
5889
5890 } else if (cur->assigned_reg() == any_reg) {
5891 // interval has not assigned register -> normal allocation
5892 // (this is the normal case for most intervals)
5893 TRACE_LINEAR_SCAN(4, tty->print_cr(" normal allocation of register"));
5894
5895 // assign same spill slot to non-intersecting intervals
5896 combine_spilled_intervals(cur);
5897
5898 init_vars_for_alloc(cur);
5899 if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5900 // no empty register available.
5901 // split and spill another interval so that this interval gets a register
5902 alloc_locked_reg(cur);
5903 }
5904
5905 // spilled intervals need not be move to active-list
5906 if (cur->assigned_reg() >= LinearScan::nof_regs) {
5907 result = false;
5908 }
5909 }
5910
5911 // load spilled values that become active from stack slot to register
5912 if (cur->insert_move_when_activated()) {
5913 assert(cur->is_split_child(), "must be");
5914 assert(cur->current_split_child() != NULL, "must be");
5915 assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5916 TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5917
5918 insert_move(cur->from(), cur->current_split_child(), cur);
5919 }
5920 cur->make_current_split_child();
5921
5922 return result; // true = interval is moved to active list
5923 }
5924
5925
5926 // Implementation of EdgeMoveOptimizer
5927
5928 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5929 _edge_instructions(4),
5930 _edge_instructions_idx(4)
5931 {
5932 }
5933
5934 void EdgeMoveOptimizer::optimize(BlockList* code) {
5935 EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5936
5937 // ignore the first block in the list (index 0 is not processed)
5938 for (int i = code->length() - 1; i >= 1; i--) {
5939 BlockBegin* block = code->at(i);
5940
5941 if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5942 optimizer.optimize_moves_at_block_end(block);
5943 }
5944 if (block->number_of_sux() == 2) {
5945 optimizer.optimize_moves_at_block_begin(block);
5946 }
5947 }
5948 }
5949
5950
5951 // clear all internal data structures
5952 void EdgeMoveOptimizer::init_instructions() {
5953 _edge_instructions.clear();
5954 _edge_instructions_idx.clear();
5955 }
5956
5957 // append a lir-instruction-list and the index of the current operation in to the list
5958 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5959 _edge_instructions.append(instructions);
5960 _edge_instructions_idx.append(instructions_idx);
5961 }
5962
5963 // return the current operation of the given edge (predecessor or successor)
5964 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5965 LIR_OpList* instructions = _edge_instructions.at(edge);
5966 int idx = _edge_instructions_idx.at(edge);
5967
5968 if (idx < instructions->length()) {
5969 return instructions->at(idx);
5970 } else {
5971 return NULL;
5972 }
5973 }
5974
5975 // removes the current operation of the given edge (predecessor or successor)
5976 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5977 LIR_OpList* instructions = _edge_instructions.at(edge);
5978 int idx = _edge_instructions_idx.at(edge);
5979 instructions->remove_at(idx);
5980
5981 if (decrement_index) {
5982 _edge_instructions_idx.at_put(edge, idx - 1);
5983 }
5984 }
5985
5986
5987 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5988 if (op1 == NULL || op2 == NULL) {
5989 // at least one block is already empty -> no optimization possible
5990 return true;
5991 }
5992
5993 if (op1->code() == lir_move && op2->code() == lir_move) {
5994 assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
5995 assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
5996 LIR_Op1* move1 = (LIR_Op1*)op1;
5997 LIR_Op1* move2 = (LIR_Op1*)op2;
5998 if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
5999 // these moves are exactly equal and can be optimized
6000 return false;
6001 }
6002
6003 } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
6004 assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
6005 assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
6006 LIR_Op1* fxch1 = (LIR_Op1*)op1;
6007 LIR_Op1* fxch2 = (LIR_Op1*)op2;
6008 if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
6009 // equal FPU stack operations can be optimized
6010 return false;
6011 }
6012
6013 } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
6014 // equal FPU stack operations can be optimized
6015 return false;
6016 }
6017
6018 // no optimization possible
6019 return true;
6020 }
6021
6022 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
6023 TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
6024
6025 if (block->is_predecessor(block)) {
6026 // currently we can't handle this correctly.
6027 return;
6028 }
6029
6030 init_instructions();
6031 int num_preds = block->number_of_preds();
6032 assert(num_preds > 1, "do not call otherwise");
6033 assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6034
6035 // setup a list with the lir-instructions of all predecessors
6036 int i;
6037 for (i = 0; i < num_preds; i++) {
6038 BlockBegin* pred = block->pred_at(i);
6039 LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6040
6041 if (pred->number_of_sux() != 1) {
6042 // this can happen with switch-statements where multiple edges are between
6043 // the same blocks.
6044 return;
6045 }
6046
6047 assert(pred->number_of_sux() == 1, "can handle only one successor");
6048 assert(pred->sux_at(0) == block, "invalid control flow");
6049 assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6050 assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6051 assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6052
6053 if (pred_instructions->last()->info() != NULL) {
6054 // can not optimize instructions when debug info is needed
6055 return;
6056 }
6057
6058 // ignore the unconditional branch at the end of the block
6059 append_instructions(pred_instructions, pred_instructions->length() - 2);
6060 }
6061
6062
6063 // process lir-instructions while all predecessors end with the same instruction
6064 while (true) {
6065 LIR_Op* op = instruction_at(0);
6066 for (i = 1; i < num_preds; i++) {
6067 if (operations_different(op, instruction_at(i))) {
6068 // these instructions are different and cannot be optimized ->
6069 // no further optimization possible
6070 return;
6071 }
6072 }
6073
6074 TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
6075
6076 // insert the instruction at the beginning of the current block
6077 block->lir()->insert_before(1, op);
6078
6079 // delete the instruction at the end of all predecessors
6080 for (i = 0; i < num_preds; i++) {
6081 remove_cur_instruction(i, true);
6082 }
6083 }
6084 }
6085
6086
6087 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
6088 TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
6089
6090 init_instructions();
6091 int num_sux = block->number_of_sux();
6092
6093 LIR_OpList* cur_instructions = block->lir()->instructions_list();
6094
6095 assert(num_sux == 2, "method should not be called otherwise");
6096 assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6097 assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6098 assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6099
6100 if (cur_instructions->last()->info() != NULL) {
6101 // can no optimize instructions when debug info is needed
6102 return;
6103 }
6104
6105 LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
6106 if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
6107 // not a valid case for optimization
6108 // currently, only blocks that end with two branches (conditional branch followed
6109 // by unconditional branch) are optimized
6110 return;
6111 }
6112
6113 // now it is guaranteed that the block ends with two branch instructions.
6114 // the instructions are inserted at the end of the block before these two branches
6115 int insert_idx = cur_instructions->length() - 2;
6116
6117 int i;
6118 #ifdef ASSERT
6119 for (i = insert_idx - 1; i >= 0; i--) {
6120 LIR_Op* op = cur_instructions->at(i);
6121 if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
6122 assert(false, "block with two successors can have only two branch instructions");
6123 }
6124 }
6125 #endif
6126
6127 // setup a list with the lir-instructions of all successors
6128 for (i = 0; i < num_sux; i++) {
6129 BlockBegin* sux = block->sux_at(i);
6130 LIR_OpList* sux_instructions = sux->lir()->instructions_list();
6131
6132 assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
6133
6134 if (sux->number_of_preds() != 1) {
6135 // this can happen with switch-statements where multiple edges are between
6136 // the same blocks.
6137 return;
6138 }
6139 assert(sux->pred_at(0) == block, "invalid control flow");
6140 assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6141
6142 // ignore the label at the beginning of the block
6143 append_instructions(sux_instructions, 1);
6144 }
6145
6146 // process lir-instructions while all successors begin with the same instruction
6147 while (true) {
6148 LIR_Op* op = instruction_at(0);
6149 for (i = 1; i < num_sux; i++) {
6150 if (operations_different(op, instruction_at(i))) {
6151 // these instructions are different and cannot be optimized ->
6152 // no further optimization possible
6153 return;
6154 }
6155 }
6156
6157 TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6158
6159 // insert instruction at end of current block
6160 block->lir()->insert_before(insert_idx, op);
6161 insert_idx++;
6162
6163 // delete the instructions at the beginning of all successors
6164 for (i = 0; i < num_sux; i++) {
6165 remove_cur_instruction(i, false);
6166 }
6167 }
6168 }
6169
6170
6171 // Implementation of ControlFlowOptimizer
6172
6173 ControlFlowOptimizer::ControlFlowOptimizer() :
6174 _original_preds(4)
6175 {
6176 }
6177
6178 void ControlFlowOptimizer::optimize(BlockList* code) {
6179 ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6180
6181 // push the OSR entry block to the end so that we're not jumping over it.
6182 BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6183 if (osr_entry) {
6184 int index = osr_entry->linear_scan_number();
6185 assert(code->at(index) == osr_entry, "wrong index");
6186 code->remove_at(index);
6187 code->append(osr_entry);
6188 }
6189
6190 optimizer.reorder_short_loops(code);
6191 optimizer.delete_empty_blocks(code);
6192 optimizer.delete_unnecessary_jumps(code);
6193 optimizer.delete_jumps_to_return(code);
6194 }
6195
6196 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6197 int i = header_idx + 1;
6198 int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6199 while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6200 i++;
6201 }
6202
6203 if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6204 int end_idx = i - 1;
6205 BlockBegin* end_block = code->at(end_idx);
6206
6207 if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6208 // short loop from header_idx to end_idx found -> reorder blocks such that
6209 // the header_block is the last block instead of the first block of the loop
6210 TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6211 end_idx - header_idx + 1,
6212 header_block->block_id(), end_block->block_id()));
6213
6214 for (int j = header_idx; j < end_idx; j++) {
6215 code->at_put(j, code->at(j + 1));
6216 }
6217 code->at_put(end_idx, header_block);
6218
6219 // correct the flags so that any loop alignment occurs in the right place.
6220 assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6221 code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6222 code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6223 }
6224 }
6225 }
6226
6227 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6228 for (int i = code->length() - 1; i >= 0; i--) {
6229 BlockBegin* block = code->at(i);
6230
6231 if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6232 reorder_short_loop(code, block, i);
6233 }
6234 }
6235
6236 DEBUG_ONLY(verify(code));
6237 }
6238
6239 // only blocks with exactly one successor can be deleted. Such blocks
6240 // must always end with an unconditional branch to this successor
6241 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6242 if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6243 return false;
6244 }
6245
6246 LIR_OpList* instructions = block->lir()->instructions_list();
6247
6248 assert(instructions->length() >= 2, "block must have label and branch");
6249 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6250 assert(instructions->last()->as_OpBranch() != NULL, "last instruction must always be a branch");
6251 assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6252 assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6253
6254 // block must have exactly one successor
6255
6256 if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6257 return true;
6258 }
6259 return false;
6260 }
6261
6262 // substitute branch targets in all branch-instructions of this blocks
6263 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6264 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6265
6266 LIR_OpList* instructions = block->lir()->instructions_list();
6267
6268 assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6269 for (int i = instructions->length() - 1; i >= 1; i--) {
6270 LIR_Op* op = instructions->at(i);
6271
6272 if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6273 assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6274 LIR_OpBranch* branch = (LIR_OpBranch*)op;
6275
6276 if (branch->block() == target_from) {
6277 branch->change_block(target_to);
6278 }
6279 if (branch->ublock() == target_from) {
6280 branch->change_ublock(target_to);
6281 }
6282 }
6283 }
6284 }
6285
6286 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6287 int old_pos = 0;
6288 int new_pos = 0;
6289 int num_blocks = code->length();
6290
6291 while (old_pos < num_blocks) {
6292 BlockBegin* block = code->at(old_pos);
6293
6294 if (can_delete_block(block)) {
6295 BlockBegin* new_target = block->sux_at(0);
6296
6297 // propagate backward branch target flag for correct code alignment
6298 if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6299 new_target->set(BlockBegin::backward_branch_target_flag);
6300 }
6301
6302 // collect a list with all predecessors that contains each predecessor only once
6303 // the predecessors of cur are changed during the substitution, so a copy of the
6304 // predecessor list is necessary
6305 int j;
6306 _original_preds.clear();
6307 for (j = block->number_of_preds() - 1; j >= 0; j--) {
6308 BlockBegin* pred = block->pred_at(j);
6309 if (_original_preds.find(pred) == -1) {
6310 _original_preds.append(pred);
6311 }
6312 }
6313
6314 for (j = _original_preds.length() - 1; j >= 0; j--) {
6315 BlockBegin* pred = _original_preds.at(j);
6316 substitute_branch_target(pred, block, new_target);
6317 pred->substitute_sux(block, new_target);
6318 }
6319 } else {
6320 // adjust position of this block in the block list if blocks before
6321 // have been deleted
6322 if (new_pos != old_pos) {
6323 code->at_put(new_pos, code->at(old_pos));
6324 }
6325 new_pos++;
6326 }
6327 old_pos++;
6328 }
6329 code->trunc_to(new_pos);
6330
6331 DEBUG_ONLY(verify(code));
6332 }
6333
6334 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6335 // skip the last block because there a branch is always necessary
6336 for (int i = code->length() - 2; i >= 0; i--) {
6337 BlockBegin* block = code->at(i);
6338 LIR_OpList* instructions = block->lir()->instructions_list();
6339
6340 LIR_Op* last_op = instructions->last();
6341 if (last_op->code() == lir_branch) {
6342 assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6343 LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6344
6345 assert(last_branch->block() != NULL, "last branch must always have a block as target");
6346 assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6347
6348 if (last_branch->info() == NULL) {
6349 if (last_branch->block() == code->at(i + 1)) {
6350
6351 TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6352
6353 // delete last branch instruction
6354 instructions->trunc_to(instructions->length() - 1);
6355
6356 } else {
6357 LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6358 if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6359 assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6360 LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6361
6362 if (prev_branch->stub() == NULL) {
6363
6364 LIR_Op2* prev_cmp = NULL;
6365 // There might be a cmove inserted for profiling which depends on the same
6366 // compare. If we change the condition of the respective compare, we have
6367 // to take care of this cmove as well.
6368 LIR_Op4* prev_cmove = NULL;
6369
6370 for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6371 prev_op = instructions->at(j);
6372 // check for the cmove
6373 if (prev_op->code() == lir_cmove) {
6374 assert(prev_op->as_Op4() != NULL, "cmove must be of type LIR_Op4");
6375 prev_cmove = (LIR_Op4*)prev_op;
6376 assert(prev_branch->cond() == prev_cmove->condition(), "should be the same");
6377 }
6378 if (prev_op->code() == lir_cmp) {
6379 assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6380 prev_cmp = (LIR_Op2*)prev_op;
6381 assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6382 }
6383 }
6384 // Guarantee because it is dereferenced below.
6385 guarantee(prev_cmp != NULL, "should have found comp instruction for branch");
6386 if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6387
6388 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6389
6390 // eliminate a conditional branch to the immediate successor
6391 prev_branch->change_block(last_branch->block());
6392 prev_branch->negate_cond();
6393 prev_cmp->set_condition(prev_branch->cond());
6394 instructions->trunc_to(instructions->length() - 1);
6395 // if we do change the condition, we have to change the cmove as well
6396 if (prev_cmove != NULL) {
6397 prev_cmove->set_condition(prev_branch->cond());
6398 LIR_Opr t = prev_cmove->in_opr1();
6399 prev_cmove->set_in_opr1(prev_cmove->in_opr2());
6400 prev_cmove->set_in_opr2(t);
6401 }
6402 }
6403 }
6404 }
6405 }
6406 }
6407 }
6408 }
6409
6410 DEBUG_ONLY(verify(code));
6411 }
6412
6413 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6414 #ifdef ASSERT
6415 ResourceBitMap return_converted(BlockBegin::number_of_blocks());
6416 #endif
6417
6418 for (int i = code->length() - 1; i >= 0; i--) {
6419 BlockBegin* block = code->at(i);
6420 LIR_OpList* cur_instructions = block->lir()->instructions_list();
6421 LIR_Op* cur_last_op = cur_instructions->last();
6422
6423 assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6424 if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6425 // the block contains only a label and a return
6426 // if a predecessor ends with an unconditional jump to this block, then the jump
6427 // can be replaced with a return instruction
6428 //
6429 // Note: the original block with only a return statement cannot be deleted completely
6430 // because the predecessors might have other (conditional) jumps to this block
6431 // -> this may lead to unnecessary return instructions in the final code
6432
6433 assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6434 assert(block->number_of_sux() == 0 ||
6435 (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6436 "blocks that end with return must not have successors");
6437
6438 assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6439 LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6440
6441 for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6442 BlockBegin* pred = block->pred_at(j);
6443 LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6444 LIR_Op* pred_last_op = pred_instructions->last();
6445
6446 if (pred_last_op->code() == lir_branch) {
6447 assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6448 LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6449
6450 if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6451 // replace the jump to a return with a direct return
6452 // Note: currently the edge between the blocks is not deleted
6453 pred_instructions->at_put(pred_instructions->length() - 1, new LIR_OpReturn(return_opr));
6454 #ifdef ASSERT
6455 return_converted.set_bit(pred->block_id());
6456 #endif
6457 }
6458 }
6459 }
6460 }
6461 }
6462 }
6463
6464
6465 #ifdef ASSERT
6466 void ControlFlowOptimizer::verify(BlockList* code) {
6467 for (int i = 0; i < code->length(); i++) {
6468 BlockBegin* block = code->at(i);
6469 LIR_OpList* instructions = block->lir()->instructions_list();
6470
6471 int j;
6472 for (j = 0; j < instructions->length(); j++) {
6473 LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6474
6475 if (op_branch != NULL) {
6476 assert(op_branch->block() == NULL || code->find(op_branch->block()) != -1, "branch target not valid");
6477 assert(op_branch->ublock() == NULL || code->find(op_branch->ublock()) != -1, "branch target not valid");
6478 }
6479 }
6480
6481 for (j = 0; j < block->number_of_sux() - 1; j++) {
6482 BlockBegin* sux = block->sux_at(j);
6483 assert(code->find(sux) != -1, "successor not valid");
6484 }
6485
6486 for (j = 0; j < block->number_of_preds() - 1; j++) {
6487 BlockBegin* pred = block->pred_at(j);
6488 assert(code->find(pred) != -1, "successor not valid");
6489 }
6490 }
6491 }
6492 #endif
6493
6494
6495 #ifndef PRODUCT
6496
6497 // Implementation of LinearStatistic
6498
6499 const char* LinearScanStatistic::counter_name(int counter_idx) {
6500 switch (counter_idx) {
6501 case counter_method: return "compiled methods";
6502 case counter_fpu_method: return "methods using fpu";
6503 case counter_loop_method: return "methods with loops";
6504 case counter_exception_method:return "methods with xhandler";
6505
6506 case counter_loop: return "loops";
6507 case counter_block: return "blocks";
6508 case counter_loop_block: return "blocks inside loop";
6509 case counter_exception_block: return "exception handler entries";
6510 case counter_interval: return "intervals";
6511 case counter_fixed_interval: return "fixed intervals";
6512 case counter_range: return "ranges";
6513 case counter_fixed_range: return "fixed ranges";
6514 case counter_use_pos: return "use positions";
6515 case counter_fixed_use_pos: return "fixed use positions";
6516 case counter_spill_slots: return "spill slots";
6517
6518 // counter for classes of lir instructions
6519 case counter_instruction: return "total instructions";
6520 case counter_label: return "labels";
6521 case counter_entry: return "method entries";
6522 case counter_return: return "method returns";
6523 case counter_call: return "method calls";
6524 case counter_move: return "moves";
6525 case counter_cmp: return "compare";
6526 case counter_cond_branch: return "conditional branches";
6527 case counter_uncond_branch: return "unconditional branches";
6528 case counter_stub_branch: return "branches to stub";
6529 case counter_alu: return "artithmetic + logic";
6530 case counter_alloc: return "allocations";
6531 case counter_sync: return "synchronisation";
6532 case counter_throw: return "throw";
6533 case counter_unwind: return "unwind";
6534 case counter_typecheck: return "type+null-checks";
6535 case counter_fpu_stack: return "fpu-stack";
6536 case counter_misc_inst: return "other instructions";
6537 case counter_other_inst: return "misc. instructions";
6538
6539 // counter for different types of moves
6540 case counter_move_total: return "total moves";
6541 case counter_move_reg_reg: return "register->register";
6542 case counter_move_reg_stack: return "register->stack";
6543 case counter_move_stack_reg: return "stack->register";
6544 case counter_move_stack_stack:return "stack->stack";
6545 case counter_move_reg_mem: return "register->memory";
6546 case counter_move_mem_reg: return "memory->register";
6547 case counter_move_const_any: return "constant->any";
6548
6549 case blank_line_1: return "";
6550 case blank_line_2: return "";
6551
6552 default: ShouldNotReachHere(); return "";
6553 }
6554 }
6555
6556 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6557 if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6558 return counter_method;
6559 } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6560 return counter_block;
6561 } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6562 return counter_instruction;
6563 } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6564 return counter_move_total;
6565 }
6566 return invalid_counter;
6567 }
6568
6569 LinearScanStatistic::LinearScanStatistic() {
6570 for (int i = 0; i < number_of_counters; i++) {
6571 _counters_sum[i] = 0;
6572 _counters_max[i] = -1;
6573 }
6574
6575 }
6576
6577 // add the method-local numbers to the total sum
6578 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6579 for (int i = 0; i < number_of_counters; i++) {
6580 _counters_sum[i] += method_statistic._counters_sum[i];
6581 _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6582 }
6583 }
6584
6585 void LinearScanStatistic::print(const char* title) {
6586 if (CountLinearScan || TraceLinearScanLevel > 0) {
6587 tty->cr();
6588 tty->print_cr("***** LinearScan statistic - %s *****", title);
6589
6590 for (int i = 0; i < number_of_counters; i++) {
6591 if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6592 tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6593
6594 LinearScanStatistic::Counter cntr = base_counter(i);
6595 if (cntr != invalid_counter) {
6596 tty->print(" (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[cntr]);
6597 } else {
6598 tty->print(" ");
6599 }
6600
6601 if (_counters_max[i] >= 0) {
6602 tty->print("%8d", _counters_max[i]);
6603 }
6604 }
6605 tty->cr();
6606 }
6607 }
6608 }
6609
6610 void LinearScanStatistic::collect(LinearScan* allocator) {
6611 inc_counter(counter_method);
6612 if (allocator->has_fpu_registers()) {
6613 inc_counter(counter_fpu_method);
6614 }
6615 if (allocator->num_loops() > 0) {
6616 inc_counter(counter_loop_method);
6617 }
6618 inc_counter(counter_loop, allocator->num_loops());
6619 inc_counter(counter_spill_slots, allocator->max_spills());
6620
6621 int i;
6622 for (i = 0; i < allocator->interval_count(); i++) {
6623 Interval* cur = allocator->interval_at(i);
6624
6625 if (cur != NULL) {
6626 inc_counter(counter_interval);
6627 inc_counter(counter_use_pos, cur->num_use_positions());
6628 if (LinearScan::is_precolored_interval(cur)) {
6629 inc_counter(counter_fixed_interval);
6630 inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6631 }
6632
6633 Range* range = cur->first();
6634 while (range != Range::end()) {
6635 inc_counter(counter_range);
6636 if (LinearScan::is_precolored_interval(cur)) {
6637 inc_counter(counter_fixed_range);
6638 }
6639 range = range->next();
6640 }
6641 }
6642 }
6643
6644 bool has_xhandlers = false;
6645 // Note: only count blocks that are in code-emit order
6646 for (i = 0; i < allocator->ir()->code()->length(); i++) {
6647 BlockBegin* cur = allocator->ir()->code()->at(i);
6648
6649 inc_counter(counter_block);
6650 if (cur->loop_depth() > 0) {
6651 inc_counter(counter_loop_block);
6652 }
6653 if (cur->is_set(BlockBegin::exception_entry_flag)) {
6654 inc_counter(counter_exception_block);
6655 has_xhandlers = true;
6656 }
6657
6658 LIR_OpList* instructions = cur->lir()->instructions_list();
6659 for (int j = 0; j < instructions->length(); j++) {
6660 LIR_Op* op = instructions->at(j);
6661
6662 inc_counter(counter_instruction);
6663
6664 switch (op->code()) {
6665 case lir_label: inc_counter(counter_label); break;
6666 case lir_std_entry:
6667 case lir_osr_entry: inc_counter(counter_entry); break;
6668 case lir_return: inc_counter(counter_return); break;
6669
6670 case lir_rtcall:
6671 case lir_static_call:
6672 case lir_optvirtual_call: inc_counter(counter_call); break;
6673
6674 case lir_move: {
6675 inc_counter(counter_move);
6676 inc_counter(counter_move_total);
6677
6678 LIR_Opr in = op->as_Op1()->in_opr();
6679 LIR_Opr res = op->as_Op1()->result_opr();
6680 if (in->is_register()) {
6681 if (res->is_register()) {
6682 inc_counter(counter_move_reg_reg);
6683 } else if (res->is_stack()) {
6684 inc_counter(counter_move_reg_stack);
6685 } else if (res->is_address()) {
6686 inc_counter(counter_move_reg_mem);
6687 } else {
6688 ShouldNotReachHere();
6689 }
6690 } else if (in->is_stack()) {
6691 if (res->is_register()) {
6692 inc_counter(counter_move_stack_reg);
6693 } else {
6694 inc_counter(counter_move_stack_stack);
6695 }
6696 } else if (in->is_address()) {
6697 assert(res->is_register(), "must be");
6698 inc_counter(counter_move_mem_reg);
6699 } else if (in->is_constant()) {
6700 inc_counter(counter_move_const_any);
6701 } else {
6702 ShouldNotReachHere();
6703 }
6704 break;
6705 }
6706
6707 case lir_cmp: inc_counter(counter_cmp); break;
6708
6709 case lir_branch:
6710 case lir_cond_float_branch: {
6711 LIR_OpBranch* branch = op->as_OpBranch();
6712 if (branch->block() == NULL) {
6713 inc_counter(counter_stub_branch);
6714 } else if (branch->cond() == lir_cond_always) {
6715 inc_counter(counter_uncond_branch);
6716 } else {
6717 inc_counter(counter_cond_branch);
6718 }
6719 break;
6720 }
6721
6722 case lir_neg:
6723 case lir_add:
6724 case lir_sub:
6725 case lir_mul:
6726 case lir_div:
6727 case lir_rem:
6728 case lir_sqrt:
6729 case lir_abs:
6730 case lir_log10:
6731 case lir_logic_and:
6732 case lir_logic_or:
6733 case lir_logic_xor:
6734 case lir_shl:
6735 case lir_shr:
6736 case lir_ushr: inc_counter(counter_alu); break;
6737
6738 case lir_alloc_object:
6739 case lir_alloc_array: inc_counter(counter_alloc); break;
6740
6741 case lir_monaddr:
6742 case lir_lock:
6743 case lir_unlock: inc_counter(counter_sync); break;
6744
6745 case lir_throw: inc_counter(counter_throw); break;
6746
6747 case lir_unwind: inc_counter(counter_unwind); break;
6748
6749 case lir_null_check:
6750 case lir_leal:
6751 case lir_instanceof:
6752 case lir_checkcast:
6753 case lir_store_check: inc_counter(counter_typecheck); break;
6754
6755 case lir_fpop_raw:
6756 case lir_fxch:
6757 case lir_fld: inc_counter(counter_fpu_stack); break;
6758
6759 case lir_nop:
6760 case lir_push:
6761 case lir_pop:
6762 case lir_convert:
6763 case lir_roundfp:
6764 case lir_cmove: inc_counter(counter_misc_inst); break;
6765
6766 default: inc_counter(counter_other_inst); break;
6767 }
6768 }
6769 }
6770
6771 if (has_xhandlers) {
6772 inc_counter(counter_exception_method);
6773 }
6774 }
6775
6776 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6777 if (CountLinearScan || TraceLinearScanLevel > 0) {
6778
6779 LinearScanStatistic local_statistic = LinearScanStatistic();
6780
6781 local_statistic.collect(allocator);
6782 global_statistic.sum_up(local_statistic);
6783
6784 if (TraceLinearScanLevel > 2) {
6785 local_statistic.print("current local statistic");
6786 }
6787 }
6788 }
6789
6790
6791 // Implementation of LinearTimers
6792
6793 LinearScanTimers::LinearScanTimers() {
6794 for (int i = 0; i < number_of_timers; i++) {
6795 timer(i)->reset();
6796 }
6797 }
6798
6799 const char* LinearScanTimers::timer_name(int idx) {
6800 switch (idx) {
6801 case timer_do_nothing: return "Nothing (Time Check)";
6802 case timer_number_instructions: return "Number Instructions";
6803 case timer_compute_local_live_sets: return "Local Live Sets";
6804 case timer_compute_global_live_sets: return "Global Live Sets";
6805 case timer_build_intervals: return "Build Intervals";
6806 case timer_sort_intervals_before: return "Sort Intervals Before";
6807 case timer_allocate_registers: return "Allocate Registers";
6808 case timer_resolve_data_flow: return "Resolve Data Flow";
6809 case timer_sort_intervals_after: return "Sort Intervals After";
6810 case timer_eliminate_spill_moves: return "Spill optimization";
6811 case timer_assign_reg_num: return "Assign Reg Num";
6812 case timer_allocate_fpu_stack: return "Allocate FPU Stack";
6813 case timer_optimize_lir: return "Optimize LIR";
6814 default: ShouldNotReachHere(); return "";
6815 }
6816 }
6817
6818 void LinearScanTimers::begin_method() {
6819 if (TimeEachLinearScan) {
6820 // reset all timers to measure only current method
6821 for (int i = 0; i < number_of_timers; i++) {
6822 timer(i)->reset();
6823 }
6824 }
6825 }
6826
6827 void LinearScanTimers::end_method(LinearScan* allocator) {
6828 if (TimeEachLinearScan) {
6829
6830 double c = timer(timer_do_nothing)->seconds();
6831 double total = 0;
6832 for (int i = 1; i < number_of_timers; i++) {
6833 total += timer(i)->seconds() - c;
6834 }
6835
6836 if (total >= 0.0005) {
6837 // print all information in one line for automatic processing
6838 tty->print("@"); allocator->compilation()->method()->print_name();
6839
6840 tty->print("@ %d ", allocator->compilation()->method()->code_size());
6841 tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6842 tty->print("@ %d ", allocator->block_count());
6843 tty->print("@ %d ", allocator->num_virtual_regs());
6844 tty->print("@ %d ", allocator->interval_count());
6845 tty->print("@ %d ", allocator->_num_calls);
6846 tty->print("@ %d ", allocator->num_loops());
6847
6848 tty->print("@ %6.6f ", total);
6849 for (int i = 1; i < number_of_timers; i++) {
6850 tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6851 }
6852 tty->cr();
6853 }
6854 }
6855 }
6856
6857 void LinearScanTimers::print(double total_time) {
6858 if (TimeLinearScan) {
6859 // correction value: sum of dummy-timer that only measures the time that
6860 // is necessary to start and stop itself
6861 double c = timer(timer_do_nothing)->seconds();
6862
6863 for (int i = 0; i < number_of_timers; i++) {
6864 double t = timer(i)->seconds();
6865 tty->print_cr(" %25s: %6.3f s (%4.1f%%) corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6866 }
6867 }
6868 }
6869
6870 #endif // #ifndef PRODUCT