1 /*
   2  * Copyright (c) 2005, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_CFGPrinter.hpp"
  27 #include "c1/c1_CodeStubs.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_FrameMap.hpp"
  30 #include "c1/c1_IR.hpp"
  31 #include "c1/c1_LIRGenerator.hpp"
  32 #include "c1/c1_LinearScan.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "code/vmreg.inline.hpp"
  35 #include "runtime/timerTrace.hpp"
  36 #include "utilities/bitMap.inline.hpp"
  37 
  38 #ifndef PRODUCT
  39 
  40   static LinearScanStatistic _stat_before_alloc;
  41   static LinearScanStatistic _stat_after_asign;
  42   static LinearScanStatistic _stat_final;
  43 
  44   static LinearScanTimers _total_timer;
  45 
  46   // helper macro for short definition of timer
  47   #define TIME_LINEAR_SCAN(timer_name)  TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
  48 
  49 #else
  50   #define TIME_LINEAR_SCAN(timer_name)
  51 #endif
  52 
  53 #ifdef ASSERT
  54 
  55   // helper macro for short definition of trace-output inside code
  56   #define TRACE_LINEAR_SCAN(level, code)       \
  57     if (TraceLinearScanLevel >= level) {       \
  58       code;                                    \
  59     }
  60 #else
  61   #define TRACE_LINEAR_SCAN(level, code)
  62 #endif
  63 
  64 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
  65 #ifdef _LP64
  66 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2,  1, 2, 1, 2, -1};
  67 #else
  68 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, 1, -1};
  69 #endif
  70 
  71 
  72 // Implementation of LinearScan
  73 
  74 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
  75  : _compilation(ir->compilation())
  76  , _ir(ir)
  77  , _gen(gen)
  78  , _frame_map(frame_map)
  79  , _cached_blocks(*ir->linear_scan_order())
  80  , _num_virtual_regs(gen->max_virtual_register_number())
  81  , _has_fpu_registers(false)
  82  , _num_calls(-1)
  83  , _max_spills(0)
  84  , _unused_spill_slot(-1)
  85  , _intervals(0)   // initialized later with correct length
  86  , _new_intervals_from_allocation(NULL)
  87  , _sorted_intervals(NULL)
  88  , _needs_full_resort(false)
  89  , _lir_ops(0)     // initialized later with correct length
  90  , _block_of_op(0) // initialized later with correct length
  91  , _has_info(0)
  92  , _has_call(0)
  93  , _interval_in_loop(0)  // initialized later with correct length
  94  , _scope_value_cache(0) // initialized later with correct length
  95 #ifdef IA32
  96  , _fpu_stack_allocator(NULL)
  97 #endif
  98 {
  99   assert(this->ir() != NULL,          "check if valid");
 100   assert(this->compilation() != NULL, "check if valid");
 101   assert(this->gen() != NULL,         "check if valid");
 102   assert(this->frame_map() != NULL,   "check if valid");
 103 }
 104 
 105 
 106 // ********** functions for converting LIR-Operands to register numbers
 107 //
 108 // Emulate a flat register file comprising physical integer registers,
 109 // physical floating-point registers and virtual registers, in that order.
 110 // Virtual registers already have appropriate numbers, since V0 is
 111 // the number of physical registers.
 112 // Returns -1 for hi word if opr is a single word operand.
 113 //
 114 // Note: the inverse operation (calculating an operand for register numbers)
 115 //       is done in calc_operand_for_interval()
 116 
 117 int LinearScan::reg_num(LIR_Opr opr) {
 118   assert(opr->is_register(), "should not call this otherwise");
 119 
 120   if (opr->is_virtual_register()) {
 121     assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
 122     return opr->vreg_number();
 123   } else if (opr->is_single_cpu()) {
 124     return opr->cpu_regnr();
 125   } else if (opr->is_double_cpu()) {
 126     return opr->cpu_regnrLo();
 127 #ifdef X86
 128   } else if (opr->is_single_xmm()) {
 129     return opr->fpu_regnr() + pd_first_xmm_reg;
 130   } else if (opr->is_double_xmm()) {
 131     return opr->fpu_regnrLo() + pd_first_xmm_reg;
 132 #endif
 133   } else if (opr->is_single_fpu()) {
 134     return opr->fpu_regnr() + pd_first_fpu_reg;
 135   } else if (opr->is_double_fpu()) {
 136     return opr->fpu_regnrLo() + pd_first_fpu_reg;
 137   } else {
 138     ShouldNotReachHere();
 139     return -1;
 140   }
 141 }
 142 
 143 int LinearScan::reg_numHi(LIR_Opr opr) {
 144   assert(opr->is_register(), "should not call this otherwise");
 145 
 146   if (opr->is_virtual_register()) {
 147     return -1;
 148   } else if (opr->is_single_cpu()) {
 149     return -1;
 150   } else if (opr->is_double_cpu()) {
 151     return opr->cpu_regnrHi();
 152 #ifdef X86
 153   } else if (opr->is_single_xmm()) {
 154     return -1;
 155   } else if (opr->is_double_xmm()) {
 156     return -1;
 157 #endif
 158   } else if (opr->is_single_fpu()) {
 159     return -1;
 160   } else if (opr->is_double_fpu()) {
 161     return opr->fpu_regnrHi() + pd_first_fpu_reg;
 162   } else {
 163     ShouldNotReachHere();
 164     return -1;
 165   }
 166 }
 167 
 168 
 169 // ********** functions for classification of intervals
 170 
 171 bool LinearScan::is_precolored_interval(const Interval* i) {
 172   return i->reg_num() < LinearScan::nof_regs;
 173 }
 174 
 175 bool LinearScan::is_virtual_interval(const Interval* i) {
 176   return i->reg_num() >= LIR_OprDesc::vreg_base;
 177 }
 178 
 179 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
 180   return i->reg_num() < LinearScan::nof_cpu_regs;
 181 }
 182 
 183 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
 184 #if defined(__SOFTFP__) || defined(E500V2)
 185   return i->reg_num() >= LIR_OprDesc::vreg_base;
 186 #else
 187   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
 188 #endif // __SOFTFP__ or E500V2
 189 }
 190 
 191 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
 192   return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
 193 }
 194 
 195 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
 196 #if defined(__SOFTFP__) || defined(E500V2)
 197   return false;
 198 #else
 199   return i->reg_num() >= LIR_OprDesc::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
 200 #endif // __SOFTFP__ or E500V2
 201 }
 202 
 203 bool LinearScan::is_in_fpu_register(const Interval* i) {
 204   // fixed intervals not needed for FPU stack allocation
 205   return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
 206 }
 207 
 208 bool LinearScan::is_oop_interval(const Interval* i) {
 209   // fixed intervals never contain oops
 210   return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
 211 }
 212 
 213 
 214 // ********** General helper functions
 215 
 216 // compute next unused stack index that can be used for spilling
 217 int LinearScan::allocate_spill_slot(bool double_word) {
 218   int spill_slot;
 219   if (double_word) {
 220     if ((_max_spills & 1) == 1) {
 221       // alignment of double-word values
 222       // the hole because of the alignment is filled with the next single-word value
 223       assert(_unused_spill_slot == -1, "wasting a spill slot");
 224       _unused_spill_slot = _max_spills;
 225       _max_spills++;
 226     }
 227     spill_slot = _max_spills;
 228     _max_spills += 2;
 229 
 230   } else if (_unused_spill_slot != -1) {
 231     // re-use hole that was the result of a previous double-word alignment
 232     spill_slot = _unused_spill_slot;
 233     _unused_spill_slot = -1;
 234 
 235   } else {
 236     spill_slot = _max_spills;
 237     _max_spills++;
 238   }
 239 
 240   int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
 241 
 242   // if too many slots used, bailout compilation.
 243   if (result > 2000) {
 244     bailout("too many stack slots used");
 245   }
 246 
 247   return result;
 248 }
 249 
 250 void LinearScan::assign_spill_slot(Interval* it) {
 251   // assign the canonical spill slot of the parent (if a part of the interval
 252   // is already spilled) or allocate a new spill slot
 253   if (it->canonical_spill_slot() >= 0) {
 254     it->assign_reg(it->canonical_spill_slot());
 255   } else {
 256     int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
 257     it->set_canonical_spill_slot(spill);
 258     it->assign_reg(spill);
 259   }
 260 }
 261 
 262 void LinearScan::propagate_spill_slots() {
 263   if (!frame_map()->finalize_frame(max_spills(), compilation()->needs_stack_repair())) {
 264     bailout("frame too large");
 265   }
 266 }
 267 
 268 // create a new interval with a predefined reg_num
 269 // (only used for parent intervals that are created during the building phase)
 270 Interval* LinearScan::create_interval(int reg_num) {
 271   assert(_intervals.at(reg_num) == NULL, "overwriting exisiting interval");
 272 
 273   Interval* interval = new Interval(reg_num);
 274   _intervals.at_put(reg_num, interval);
 275 
 276   // assign register number for precolored intervals
 277   if (reg_num < LIR_OprDesc::vreg_base) {
 278     interval->assign_reg(reg_num);
 279   }
 280   return interval;
 281 }
 282 
 283 // assign a new reg_num to the interval and append it to the list of intervals
 284 // (only used for child intervals that are created during register allocation)
 285 void LinearScan::append_interval(Interval* it) {
 286   it->set_reg_num(_intervals.length());
 287   _intervals.append(it);
 288   IntervalList* new_intervals = _new_intervals_from_allocation;
 289   if (new_intervals == NULL) {
 290     new_intervals = _new_intervals_from_allocation = new IntervalList();
 291   }
 292   new_intervals->append(it);
 293 }
 294 
 295 // copy the vreg-flags if an interval is split
 296 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
 297   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
 298     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
 299   }
 300   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
 301     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
 302   }
 303 
 304   // Note: do not copy the must_start_in_memory flag because it is not necessary for child
 305   //       intervals (only the very beginning of the interval must be in memory)
 306 }
 307 
 308 
 309 // ********** spill move optimization
 310 // eliminate moves from register to stack if stack slot is known to be correct
 311 
 312 // called during building of intervals
 313 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
 314   assert(interval->is_split_parent(), "can only be called for split parents");
 315 
 316   switch (interval->spill_state()) {
 317     case noDefinitionFound:
 318       assert(interval->spill_definition_pos() == -1, "must no be set before");
 319       interval->set_spill_definition_pos(def_pos);
 320       interval->set_spill_state(oneDefinitionFound);
 321       break;
 322 
 323     case oneDefinitionFound:
 324       assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
 325       if (def_pos < interval->spill_definition_pos() - 2) {
 326         // second definition found, so no spill optimization possible for this interval
 327         interval->set_spill_state(noOptimization);
 328       } else {
 329         // two consecutive definitions (because of two-operand LIR form)
 330         assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
 331       }
 332       break;
 333 
 334     case noOptimization:
 335       // nothing to do
 336       break;
 337 
 338     default:
 339       assert(false, "other states not allowed at this time");
 340   }
 341 }
 342 
 343 // called during register allocation
 344 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
 345   switch (interval->spill_state()) {
 346     case oneDefinitionFound: {
 347       int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
 348       int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
 349 
 350       if (def_loop_depth < spill_loop_depth) {
 351         // the loop depth of the spilling position is higher then the loop depth
 352         // at the definition of the interval -> move write to memory out of loop
 353         // by storing at definitin of the interval
 354         interval->set_spill_state(storeAtDefinition);
 355       } else {
 356         // the interval is currently spilled only once, so for now there is no
 357         // reason to store the interval at the definition
 358         interval->set_spill_state(oneMoveInserted);
 359       }
 360       break;
 361     }
 362 
 363     case oneMoveInserted: {
 364       // the interval is spilled more then once, so it is better to store it to
 365       // memory at the definition
 366       interval->set_spill_state(storeAtDefinition);
 367       break;
 368     }
 369 
 370     case storeAtDefinition:
 371     case startInMemory:
 372     case noOptimization:
 373     case noDefinitionFound:
 374       // nothing to do
 375       break;
 376 
 377     default:
 378       assert(false, "other states not allowed at this time");
 379   }
 380 }
 381 
 382 
 383 bool LinearScan::must_store_at_definition(const Interval* i) {
 384   return i->is_split_parent() && i->spill_state() == storeAtDefinition;
 385 }
 386 
 387 // called once before asignment of register numbers
 388 void LinearScan::eliminate_spill_moves() {
 389   TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
 390   TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
 391 
 392   // collect all intervals that must be stored after their definion.
 393   // the list is sorted by Interval::spill_definition_pos
 394   Interval* interval;
 395   Interval* temp_list;
 396   create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
 397 
 398 #ifdef ASSERT
 399   Interval* prev = NULL;
 400   Interval* temp = interval;
 401   while (temp != Interval::end()) {
 402     assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
 403     if (prev != NULL) {
 404       assert(temp->from() >= prev->from(), "intervals not sorted");
 405       assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
 406     }
 407 
 408     assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
 409     assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
 410     assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
 411 
 412     TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
 413 
 414     temp = temp->next();
 415   }
 416 #endif
 417 
 418   LIR_InsertionBuffer insertion_buffer;
 419   int num_blocks = block_count();
 420   for (int i = 0; i < num_blocks; i++) {
 421     BlockBegin* block = block_at(i);
 422     LIR_OpList* instructions = block->lir()->instructions_list();
 423     int         num_inst = instructions->length();
 424     bool        has_new = false;
 425 
 426     // iterate all instructions of the block. skip the first because it is always a label
 427     for (int j = 1; j < num_inst; j++) {
 428       LIR_Op* op = instructions->at(j);
 429       int op_id = op->id();
 430 
 431       if (op_id == -1) {
 432         // remove move from register to stack if the stack slot is guaranteed to be correct.
 433         // only moves that have been inserted by LinearScan can be removed.
 434         assert(op->code() == lir_move, "only moves can have a op_id of -1");
 435         assert(op->as_Op1() != NULL, "move must be LIR_Op1");
 436         assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
 437 
 438         LIR_Op1* op1 = (LIR_Op1*)op;
 439         Interval* interval = interval_at(op1->result_opr()->vreg_number());
 440 
 441         if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
 442           // move target is a stack slot that is always correct, so eliminate instruction
 443           TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
 444           instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
 445         }
 446 
 447       } else {
 448         // insert move from register to stack just after the beginning of the interval
 449         assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
 450         assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
 451 
 452         while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
 453           if (!has_new) {
 454             // prepare insertion buffer (appended when all instructions of the block are processed)
 455             insertion_buffer.init(block->lir());
 456             has_new = true;
 457           }
 458 
 459           LIR_Opr from_opr = operand_for_interval(interval);
 460           LIR_Opr to_opr = canonical_spill_opr(interval);
 461           assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
 462           assert(to_opr->is_stack(), "to operand must be a stack slot");
 463 
 464           insertion_buffer.move(j, from_opr, to_opr);
 465           TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
 466 
 467           interval = interval->next();
 468         }
 469       }
 470     } // end of instruction iteration
 471 
 472     if (has_new) {
 473       block->lir()->append(&insertion_buffer);
 474     }
 475   } // end of block iteration
 476 
 477   assert(interval == Interval::end(), "missed an interval");
 478 }
 479 
 480 
 481 // ********** Phase 1: number all instructions in all blocks
 482 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
 483 
 484 void LinearScan::number_instructions() {
 485   {
 486     // dummy-timer to measure the cost of the timer itself
 487     // (this time is then subtracted from all other timers to get the real value)
 488     TIME_LINEAR_SCAN(timer_do_nothing);
 489   }
 490   TIME_LINEAR_SCAN(timer_number_instructions);
 491 
 492   // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
 493   int num_blocks = block_count();
 494   int num_instructions = 0;
 495   int i;
 496   for (i = 0; i < num_blocks; i++) {
 497     num_instructions += block_at(i)->lir()->instructions_list()->length();
 498   }
 499 
 500   // initialize with correct length
 501   _lir_ops = LIR_OpArray(num_instructions, num_instructions, NULL);
 502   _block_of_op = BlockBeginArray(num_instructions, num_instructions, NULL);
 503 
 504   int op_id = 0;
 505   int idx = 0;
 506 
 507   for (i = 0; i < num_blocks; i++) {
 508     BlockBegin* block = block_at(i);
 509     block->set_first_lir_instruction_id(op_id);
 510     LIR_OpList* instructions = block->lir()->instructions_list();
 511 
 512     int num_inst = instructions->length();
 513     for (int j = 0; j < num_inst; j++) {
 514       LIR_Op* op = instructions->at(j);
 515       op->set_id(op_id);
 516 
 517       _lir_ops.at_put(idx, op);
 518       _block_of_op.at_put(idx, block);
 519       assert(lir_op_with_id(op_id) == op, "must match");
 520 
 521       idx++;
 522       op_id += 2; // numbering of lir_ops by two
 523     }
 524     block->set_last_lir_instruction_id(op_id - 2);
 525   }
 526   assert(idx == num_instructions, "must match");
 527   assert(idx * 2 == op_id, "must match");
 528 
 529   _has_call.initialize(num_instructions);
 530   _has_info.initialize(num_instructions);
 531 }
 532 
 533 
 534 // ********** Phase 2: compute local live sets separately for each block
 535 // (sets live_gen and live_kill for each block)
 536 
 537 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
 538   LIR_Opr opr = value->operand();
 539   Constant* con = value->as_Constant();
 540 
 541   // check some asumptions about debug information
 542   assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
 543   assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands");
 544   assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
 545 
 546   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 547     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 548     int reg = opr->vreg_number();
 549     if (!live_kill.at(reg)) {
 550       live_gen.set_bit(reg);
 551       TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
 552     }
 553   }
 554 }
 555 
 556 
 557 void LinearScan::compute_local_live_sets() {
 558   TIME_LINEAR_SCAN(timer_compute_local_live_sets);
 559 
 560   int  num_blocks = block_count();
 561   int  live_size = live_set_size();
 562   bool local_has_fpu_registers = false;
 563   int  local_num_calls = 0;
 564   LIR_OpVisitState visitor;
 565 
 566   BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
 567 
 568   // iterate all blocks
 569   for (int i = 0; i < num_blocks; i++) {
 570     BlockBegin* block = block_at(i);
 571 
 572     ResourceBitMap live_gen(live_size);
 573     ResourceBitMap live_kill(live_size);
 574 
 575     if (block->is_set(BlockBegin::exception_entry_flag)) {
 576       // Phi functions at the begin of an exception handler are
 577       // implicitly defined (= killed) at the beginning of the block.
 578       for_each_phi_fun(block, phi,
 579         if (!phi->is_illegal()) { live_kill.set_bit(phi->operand()->vreg_number()); }
 580       );
 581     }
 582 
 583     LIR_OpList* instructions = block->lir()->instructions_list();
 584     int num_inst = instructions->length();
 585 
 586     // iterate all instructions of the block. skip the first because it is always a label
 587     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
 588     for (int j = 1; j < num_inst; j++) {
 589       LIR_Op* op = instructions->at(j);
 590 
 591       // visit operation to collect all operands
 592       visitor.visit(op);
 593 
 594       if (visitor.has_call()) {
 595         _has_call.set_bit(op->id() >> 1);
 596         local_num_calls++;
 597       }
 598       if (visitor.info_count() > 0) {
 599         _has_info.set_bit(op->id() >> 1);
 600       }
 601 
 602       // iterate input operands of instruction
 603       int k, n, reg;
 604       n = visitor.opr_count(LIR_OpVisitState::inputMode);
 605       for (k = 0; k < n; k++) {
 606         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
 607         assert(opr->is_register(), "visitor should only return register operands");
 608 
 609         if (opr->is_virtual_register()) {
 610           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 611           reg = opr->vreg_number();
 612           if (!live_kill.at(reg)) {
 613             live_gen.set_bit(reg);
 614             TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for register %d at instruction %d", reg, op->id()));
 615           }
 616           if (block->loop_index() >= 0) {
 617             local_interval_in_loop.set_bit(reg, block->loop_index());
 618           }
 619           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 620         }
 621 
 622 #ifdef ASSERT
 623         // fixed intervals are never live at block boundaries, so
 624         // they need not be processed in live sets.
 625         // this is checked by these assertions to be sure about it.
 626         // the entry block may have incoming values in registers, which is ok.
 627         if (!opr->is_virtual_register() && block != ir()->start()) {
 628           reg = reg_num(opr);
 629           if (is_processed_reg_num(reg)) {
 630             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 631           }
 632           reg = reg_numHi(opr);
 633           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 634             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 635           }
 636         }
 637 #endif
 638       }
 639 
 640       // Add uses of live locals from interpreter's point of view for proper debug information generation
 641       n = visitor.info_count();
 642       for (k = 0; k < n; k++) {
 643         CodeEmitInfo* info = visitor.info_at(k);
 644         ValueStack* stack = info->stack();
 645         for_each_state_value(stack, value,
 646           set_live_gen_kill(value, op, live_gen, live_kill);
 647           local_has_fpu_registers = local_has_fpu_registers || value->type()->is_float_kind();
 648         );
 649       }
 650 
 651       // iterate temp operands of instruction
 652       n = visitor.opr_count(LIR_OpVisitState::tempMode);
 653       for (k = 0; k < n; k++) {
 654         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
 655         assert(opr->is_register(), "visitor should only return register operands");
 656 
 657         if (opr->is_virtual_register()) {
 658           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 659           reg = opr->vreg_number();
 660           live_kill.set_bit(reg);
 661           if (block->loop_index() >= 0) {
 662             local_interval_in_loop.set_bit(reg, block->loop_index());
 663           }
 664           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 665         }
 666 
 667 #ifdef ASSERT
 668         // fixed intervals are never live at block boundaries, so
 669         // they need not be processed in live sets
 670         // process them only in debug mode so that this can be checked
 671         if (!opr->is_virtual_register()) {
 672           reg = reg_num(opr);
 673           if (is_processed_reg_num(reg)) {
 674             live_kill.set_bit(reg_num(opr));
 675           }
 676           reg = reg_numHi(opr);
 677           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 678             live_kill.set_bit(reg);
 679           }
 680         }
 681 #endif
 682       }
 683 
 684       // iterate output operands of instruction
 685       n = visitor.opr_count(LIR_OpVisitState::outputMode);
 686       for (k = 0; k < n; k++) {
 687         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
 688         assert(opr->is_register(), "visitor should only return register operands");
 689 
 690         if (opr->is_virtual_register()) {
 691           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 692           reg = opr->vreg_number();
 693           live_kill.set_bit(reg);
 694           if (block->loop_index() >= 0) {
 695             local_interval_in_loop.set_bit(reg, block->loop_index());
 696           }
 697           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 698         }
 699 
 700 #ifdef ASSERT
 701         // fixed intervals are never live at block boundaries, so
 702         // they need not be processed in live sets
 703         // process them only in debug mode so that this can be checked
 704         if (!opr->is_virtual_register()) {
 705           reg = reg_num(opr);
 706           if (is_processed_reg_num(reg)) {
 707             live_kill.set_bit(reg_num(opr));
 708           }
 709           reg = reg_numHi(opr);
 710           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 711             live_kill.set_bit(reg);
 712           }
 713         }
 714 #endif
 715       }
 716     } // end of instruction iteration
 717 
 718     block->set_live_gen (live_gen);
 719     block->set_live_kill(live_kill);
 720     block->set_live_in  (ResourceBitMap(live_size));
 721     block->set_live_out (ResourceBitMap(live_size));
 722 
 723     TRACE_LINEAR_SCAN(4, tty->print("live_gen  B%d ", block->block_id()); print_bitmap(block->live_gen()));
 724     TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
 725   } // end of block iteration
 726 
 727   // propagate local calculated information into LinearScan object
 728   _has_fpu_registers = local_has_fpu_registers;
 729   compilation()->set_has_fpu_code(local_has_fpu_registers);
 730 
 731   _num_calls = local_num_calls;
 732   _interval_in_loop = local_interval_in_loop;
 733 }
 734 
 735 
 736 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
 737 // (sets live_in and live_out for each block)
 738 
 739 void LinearScan::compute_global_live_sets() {
 740   TIME_LINEAR_SCAN(timer_compute_global_live_sets);
 741 
 742   int  num_blocks = block_count();
 743   bool change_occurred;
 744   bool change_occurred_in_block;
 745   int  iteration_count = 0;
 746   ResourceBitMap live_out(live_set_size()); // scratch set for calculations
 747 
 748   // Perform a backward dataflow analysis to compute live_out and live_in for each block.
 749   // The loop is executed until a fixpoint is reached (no changes in an iteration)
 750   // Exception handlers must be processed because not all live values are
 751   // present in the state array, e.g. because of global value numbering
 752   do {
 753     change_occurred = false;
 754 
 755     // iterate all blocks in reverse order
 756     for (int i = num_blocks - 1; i >= 0; i--) {
 757       BlockBegin* block = block_at(i);
 758 
 759       change_occurred_in_block = false;
 760 
 761       // live_out(block) is the union of live_in(sux), for successors sux of block
 762       int n = block->number_of_sux();
 763       int e = block->number_of_exception_handlers();
 764       if (n + e > 0) {
 765         // block has successors
 766         if (n > 0) {
 767           live_out.set_from(block->sux_at(0)->live_in());
 768           for (int j = 1; j < n; j++) {
 769             live_out.set_union(block->sux_at(j)->live_in());
 770           }
 771         } else {
 772           live_out.clear();
 773         }
 774         for (int j = 0; j < e; j++) {
 775           live_out.set_union(block->exception_handler_at(j)->live_in());
 776         }
 777 
 778         if (!block->live_out().is_same(live_out)) {
 779           // A change occurred.  Swap the old and new live out sets to avoid copying.
 780           ResourceBitMap temp = block->live_out();
 781           block->set_live_out(live_out);
 782           live_out = temp;
 783 
 784           change_occurred = true;
 785           change_occurred_in_block = true;
 786         }
 787       }
 788 
 789       if (iteration_count == 0 || change_occurred_in_block) {
 790         // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
 791         // note: live_in has to be computed only in first iteration or if live_out has changed!
 792         ResourceBitMap live_in = block->live_in();
 793         live_in.set_from(block->live_out());
 794         live_in.set_difference(block->live_kill());
 795         live_in.set_union(block->live_gen());
 796       }
 797 
 798 #ifdef ASSERT
 799       if (TraceLinearScanLevel >= 4) {
 800         char c = ' ';
 801         if (iteration_count == 0 || change_occurred_in_block) {
 802           c = '*';
 803         }
 804         tty->print("(%d) live_in%c  B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
 805         tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
 806       }
 807 #endif
 808     }
 809     iteration_count++;
 810 
 811     if (change_occurred && iteration_count > 50) {
 812       BAILOUT("too many iterations in compute_global_live_sets");
 813     }
 814   } while (change_occurred);
 815 
 816 
 817 #ifdef ASSERT
 818   // check that fixed intervals are not live at block boundaries
 819   // (live set must be empty at fixed intervals)
 820   for (int i = 0; i < num_blocks; i++) {
 821     BlockBegin* block = block_at(i);
 822     for (int j = 0; j < LIR_OprDesc::vreg_base; j++) {
 823       assert(block->live_in().at(j)  == false, "live_in  set of fixed register must be empty");
 824       assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
 825       assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
 826     }
 827   }
 828 #endif
 829 
 830   // check that the live_in set of the first block is empty
 831   ResourceBitMap live_in_args(ir()->start()->live_in().size());
 832   if (!ir()->start()->live_in().is_same(live_in_args)) {
 833 #ifdef ASSERT
 834     tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
 835     tty->print_cr("affected registers:");
 836     print_bitmap(ir()->start()->live_in());
 837 
 838     // print some additional information to simplify debugging
 839     for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
 840       if (ir()->start()->live_in().at(i)) {
 841         Instruction* instr = gen()->instruction_for_vreg(i);
 842         tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
 843 
 844         for (int j = 0; j < num_blocks; j++) {
 845           BlockBegin* block = block_at(j);
 846           if (block->live_gen().at(i)) {
 847             tty->print_cr("  used in block B%d", block->block_id());
 848           }
 849           if (block->live_kill().at(i)) {
 850             tty->print_cr("  defined in block B%d", block->block_id());
 851           }
 852         }
 853       }
 854     }
 855 
 856 #endif
 857     // when this fails, virtual registers are used before they are defined.
 858     assert(false, "live_in set of first block must be empty");
 859     // bailout of if this occurs in product mode.
 860     bailout("live_in set of first block not empty");
 861   }
 862 }
 863 
 864 
 865 // ********** Phase 4: build intervals
 866 // (fills the list _intervals)
 867 
 868 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
 869   assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
 870   LIR_Opr opr = value->operand();
 871   Constant* con = value->as_Constant();
 872 
 873   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 874     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 875     add_use(opr, from, to, use_kind);
 876   }
 877 }
 878 
 879 
 880 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
 881   TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
 882   assert(opr->is_register(), "should not be called otherwise");
 883 
 884   if (opr->is_virtual_register()) {
 885     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 886     add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
 887 
 888   } else {
 889     int reg = reg_num(opr);
 890     if (is_processed_reg_num(reg)) {
 891       add_def(reg, def_pos, use_kind, opr->type_register());
 892     }
 893     reg = reg_numHi(opr);
 894     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 895       add_def(reg, def_pos, use_kind, opr->type_register());
 896     }
 897   }
 898 }
 899 
 900 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
 901   TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
 902   assert(opr->is_register(), "should not be called otherwise");
 903 
 904   if (opr->is_virtual_register()) {
 905     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 906     add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
 907 
 908   } else {
 909     int reg = reg_num(opr);
 910     if (is_processed_reg_num(reg)) {
 911       add_use(reg, from, to, use_kind, opr->type_register());
 912     }
 913     reg = reg_numHi(opr);
 914     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 915       add_use(reg, from, to, use_kind, opr->type_register());
 916     }
 917   }
 918 }
 919 
 920 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
 921   TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
 922   assert(opr->is_register(), "should not be called otherwise");
 923 
 924   if (opr->is_virtual_register()) {
 925     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 926     add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
 927 
 928   } else {
 929     int reg = reg_num(opr);
 930     if (is_processed_reg_num(reg)) {
 931       add_temp(reg, temp_pos, use_kind, opr->type_register());
 932     }
 933     reg = reg_numHi(opr);
 934     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 935       add_temp(reg, temp_pos, use_kind, opr->type_register());
 936     }
 937   }
 938 }
 939 
 940 
 941 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
 942   Interval* interval = interval_at(reg_num);
 943   if (interval != NULL) {
 944     assert(interval->reg_num() == reg_num, "wrong interval");
 945 
 946     if (type != T_ILLEGAL) {
 947       interval->set_type(type);
 948     }
 949 
 950     Range* r = interval->first();
 951     if (r->from() <= def_pos) {
 952       // Update the starting point (when a range is first created for a use, its
 953       // start is the beginning of the current block until a def is encountered.)
 954       r->set_from(def_pos);
 955       interval->add_use_pos(def_pos, use_kind);
 956 
 957     } else {
 958       // Dead value - make vacuous interval
 959       // also add use_kind for dead intervals
 960       interval->add_range(def_pos, def_pos + 1);
 961       interval->add_use_pos(def_pos, use_kind);
 962       TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
 963     }
 964 
 965   } else {
 966     // Dead value - make vacuous interval
 967     // also add use_kind for dead intervals
 968     interval = create_interval(reg_num);
 969     if (type != T_ILLEGAL) {
 970       interval->set_type(type);
 971     }
 972 
 973     interval->add_range(def_pos, def_pos + 1);
 974     interval->add_use_pos(def_pos, use_kind);
 975     TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
 976   }
 977 
 978   change_spill_definition_pos(interval, def_pos);
 979   if (use_kind == noUse && interval->spill_state() <= startInMemory) {
 980         // detection of method-parameters and roundfp-results
 981         // TODO: move this directly to position where use-kind is computed
 982     interval->set_spill_state(startInMemory);
 983   }
 984 }
 985 
 986 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
 987   Interval* interval = interval_at(reg_num);
 988   if (interval == NULL) {
 989     interval = create_interval(reg_num);
 990   }
 991   assert(interval->reg_num() == reg_num, "wrong interval");
 992 
 993   if (type != T_ILLEGAL) {
 994     interval->set_type(type);
 995   }
 996 
 997   interval->add_range(from, to);
 998   interval->add_use_pos(to, use_kind);
 999 }
1000 
1001 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1002   Interval* interval = interval_at(reg_num);
1003   if (interval == NULL) {
1004     interval = create_interval(reg_num);
1005   }
1006   assert(interval->reg_num() == reg_num, "wrong interval");
1007 
1008   if (type != T_ILLEGAL) {
1009     interval->set_type(type);
1010   }
1011 
1012   interval->add_range(temp_pos, temp_pos + 1);
1013   interval->add_use_pos(temp_pos, use_kind);
1014 }
1015 
1016 
1017 // the results of this functions are used for optimizing spilling and reloading
1018 // if the functions return shouldHaveRegister and the interval is spilled,
1019 // it is not reloaded to a register.
1020 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1021   if (op->code() == lir_move) {
1022     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1023     LIR_Op1* move = (LIR_Op1*)op;
1024     LIR_Opr res = move->result_opr();
1025     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1026 
1027     if (result_in_memory) {
1028       // Begin of an interval with must_start_in_memory set.
1029       // This interval will always get a stack slot first, so return noUse.
1030       return noUse;
1031 
1032     } else if (move->in_opr()->is_stack()) {
1033       // method argument (condition must be equal to handle_method_arguments)
1034       return noUse;
1035 
1036     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1037       // Move from register to register
1038       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1039         // special handling of phi-function moves inside osr-entry blocks
1040         // input operand must have a register instead of output operand (leads to better register allocation)
1041         return shouldHaveRegister;
1042       }
1043     }
1044   }
1045 
1046   if (opr->is_virtual() &&
1047       gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1048     // result is a stack-slot, so prevent immediate reloading
1049     return noUse;
1050   }
1051 
1052   // all other operands require a register
1053   return mustHaveRegister;
1054 }
1055 
1056 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1057   if (op->code() == lir_move) {
1058     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1059     LIR_Op1* move = (LIR_Op1*)op;
1060     LIR_Opr res = move->result_opr();
1061     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1062 
1063     if (result_in_memory) {
1064       // Move to an interval with must_start_in_memory set.
1065       // To avoid moves from stack to stack (not allowed) force the input operand to a register
1066       return mustHaveRegister;
1067 
1068     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1069       // Move from register to register
1070       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1071         // special handling of phi-function moves inside osr-entry blocks
1072         // input operand must have a register instead of output operand (leads to better register allocation)
1073         return mustHaveRegister;
1074       }
1075 
1076       // The input operand is not forced to a register (moves from stack to register are allowed),
1077       // but it is faster if the input operand is in a register
1078       return shouldHaveRegister;
1079     }
1080   }
1081 
1082 
1083 #if defined(X86) || defined(S390)
1084   if (op->code() == lir_cmove) {
1085     // conditional moves can handle stack operands
1086     assert(op->result_opr()->is_register(), "result must always be in a register");
1087     return shouldHaveRegister;
1088   }
1089 
1090   // optimizations for second input operand of arithmehtic operations on Intel
1091   // this operand is allowed to be on the stack in some cases
1092   BasicType opr_type = opr->type_register();
1093   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1094     if (IA32_ONLY( (UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 ) NOT_IA32( true )) {
1095       // SSE float instruction (T_DOUBLE only supported with SSE2)
1096       switch (op->code()) {
1097         case lir_cmp:
1098         case lir_add:
1099         case lir_sub:
1100         case lir_mul:
1101         case lir_div:
1102         {
1103           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1104           LIR_Op2* op2 = (LIR_Op2*)op;
1105           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1106             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1107             return shouldHaveRegister;
1108           }
1109         }
1110         default:
1111           break;
1112       }
1113     } else {
1114       // FPU stack float instruction
1115       switch (op->code()) {
1116         case lir_add:
1117         case lir_sub:
1118         case lir_mul:
1119         case lir_div:
1120         {
1121           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1122           LIR_Op2* op2 = (LIR_Op2*)op;
1123           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1124             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1125             return shouldHaveRegister;
1126           }
1127         }
1128         default:
1129           break;
1130       }
1131     }
1132     // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1133     // Since 64bit logical operations do not current support operands on stack, we have to make sure
1134     // T_OBJECT doesn't get spilled along with T_LONG.
1135   } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1136     // integer instruction (note: long operands must always be in register)
1137     switch (op->code()) {
1138       case lir_cmp:
1139       case lir_add:
1140       case lir_sub:
1141       case lir_logic_and:
1142       case lir_logic_or:
1143       case lir_logic_xor:
1144       {
1145         assert(op->as_Op2() != NULL, "must be LIR_Op2");
1146         LIR_Op2* op2 = (LIR_Op2*)op;
1147         if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1148           assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1149           return shouldHaveRegister;
1150         }
1151       }
1152       default:
1153         break;
1154     }
1155   }
1156 #endif // X86 || S390
1157 
1158   // all other operands require a register
1159   return mustHaveRegister;
1160 }
1161 
1162 
1163 void LinearScan::handle_method_arguments(LIR_Op* op) {
1164   // special handling for method arguments (moves from stack to virtual register):
1165   // the interval gets no register assigned, but the stack slot.
1166   // it is split before the first use by the register allocator.
1167 
1168   if (op->code() == lir_move) {
1169     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1170     LIR_Op1* move = (LIR_Op1*)op;
1171 
1172     if (move->in_opr()->is_stack()) {
1173 #ifdef ASSERT
1174       int arg_size = compilation()->method()->arg_size();
1175       LIR_Opr o = move->in_opr();
1176       if (o->is_single_stack()) {
1177         assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1178       } else if (o->is_double_stack()) {
1179         assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1180       } else {
1181         ShouldNotReachHere();
1182       }
1183 
1184       assert(move->id() > 0, "invalid id");
1185       assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1186       assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1187 
1188       TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1189 #endif
1190 
1191       Interval* interval = interval_at(reg_num(move->result_opr()));
1192 
1193       int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1194       interval->set_canonical_spill_slot(stack_slot);
1195       interval->assign_reg(stack_slot);
1196     }
1197   }
1198 }
1199 
1200 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1201   // special handling for doubleword move from memory to register:
1202   // in this case the registers of the input address and the result
1203   // registers must not overlap -> add a temp range for the input registers
1204   if (op->code() == lir_move) {
1205     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1206     LIR_Op1* move = (LIR_Op1*)op;
1207 
1208     if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1209       LIR_Address* address = move->in_opr()->as_address_ptr();
1210       if (address != NULL) {
1211         if (address->base()->is_valid()) {
1212           add_temp(address->base(), op->id(), noUse);
1213         }
1214         if (address->index()->is_valid()) {
1215           add_temp(address->index(), op->id(), noUse);
1216         }
1217       }
1218     }
1219   }
1220 }
1221 
1222 void LinearScan::add_register_hints(LIR_Op* op) {
1223   switch (op->code()) {
1224     case lir_move:      // fall through
1225     case lir_convert: {
1226       assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1227       LIR_Op1* move = (LIR_Op1*)op;
1228 
1229       LIR_Opr move_from = move->in_opr();
1230       LIR_Opr move_to = move->result_opr();
1231 
1232       if (move_to->is_register() && move_from->is_register()) {
1233         Interval* from = interval_at(reg_num(move_from));
1234         Interval* to = interval_at(reg_num(move_to));
1235         if (from != NULL && to != NULL) {
1236           to->set_register_hint(from);
1237           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1238         }
1239       }
1240       break;
1241     }
1242     case lir_cmove: {
1243       assert(op->as_Op2() != NULL, "lir_cmove must be LIR_Op2");
1244       LIR_Op2* cmove = (LIR_Op2*)op;
1245 
1246       LIR_Opr move_from = cmove->in_opr1();
1247       LIR_Opr move_to = cmove->result_opr();
1248 
1249       if (move_to->is_register() && move_from->is_register()) {
1250         Interval* from = interval_at(reg_num(move_from));
1251         Interval* to = interval_at(reg_num(move_to));
1252         if (from != NULL && to != NULL) {
1253           to->set_register_hint(from);
1254           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1255         }
1256       }
1257       break;
1258     }
1259     default:
1260       break;
1261   }
1262 }
1263 
1264 
1265 void LinearScan::build_intervals() {
1266   TIME_LINEAR_SCAN(timer_build_intervals);
1267 
1268   // initialize interval list with expected number of intervals
1269   // (32 is added to have some space for split children without having to resize the list)
1270   _intervals = IntervalList(num_virtual_regs() + 32);
1271   // initialize all slots that are used by build_intervals
1272   _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1273 
1274   // create a list with all caller-save registers (cpu, fpu, xmm)
1275   // when an instruction is a call, a temp range is created for all these registers
1276   int num_caller_save_registers = 0;
1277   int caller_save_registers[LinearScan::nof_regs];
1278 
1279   int i;
1280   for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1281     LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1282     assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1283     assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1284     caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1285   }
1286 
1287   // temp ranges for fpu registers are only created when the method has
1288   // virtual fpu operands. Otherwise no allocation for fpu registers is
1289   // performed and so the temp ranges would be useless
1290   if (has_fpu_registers()) {
1291 #ifdef X86
1292     if (UseSSE < 2) {
1293 #endif // X86
1294       for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1295         LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1296         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1297         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1298         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1299       }
1300 #ifdef X86
1301     }
1302 #endif // X86
1303 
1304 #ifdef X86
1305     if (UseSSE > 0) {
1306       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
1307       for (i = 0; i < num_caller_save_xmm_regs; i ++) {
1308         LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1309         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1310         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1311         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1312       }
1313     }
1314 #endif // X86
1315   }
1316   assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1317 
1318 
1319   LIR_OpVisitState visitor;
1320 
1321   // iterate all blocks in reverse order
1322   for (i = block_count() - 1; i >= 0; i--) {
1323     BlockBegin* block = block_at(i);
1324     LIR_OpList* instructions = block->lir()->instructions_list();
1325     int         block_from =   block->first_lir_instruction_id();
1326     int         block_to =     block->last_lir_instruction_id();
1327 
1328     assert(block_from == instructions->at(0)->id(), "must be");
1329     assert(block_to   == instructions->at(instructions->length() - 1)->id(), "must be");
1330 
1331     // Update intervals for registers live at the end of this block;
1332     ResourceBitMap live = block->live_out();
1333     int size = (int)live.size();
1334     for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1335       assert(live.at(number), "should not stop here otherwise");
1336       assert(number >= LIR_OprDesc::vreg_base, "fixed intervals must not be live on block bounds");
1337       TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1338 
1339       add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1340 
1341       // add special use positions for loop-end blocks when the
1342       // interval is used anywhere inside this loop.  It's possible
1343       // that the block was part of a non-natural loop, so it might
1344       // have an invalid loop index.
1345       if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1346           block->loop_index() != -1 &&
1347           is_interval_in_loop(number, block->loop_index())) {
1348         interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1349       }
1350     }
1351 
1352     // iterate all instructions of the block in reverse order.
1353     // skip the first instruction because it is always a label
1354     // definitions of intervals are processed before uses
1355     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1356     for (int j = instructions->length() - 1; j >= 1; j--) {
1357       LIR_Op* op = instructions->at(j);
1358       int op_id = op->id();
1359 
1360       // visit operation to collect all operands
1361       visitor.visit(op);
1362 
1363       // add a temp range for each register if operation destroys caller-save registers
1364       if (visitor.has_call()) {
1365         for (int k = 0; k < num_caller_save_registers; k++) {
1366           add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1367         }
1368         TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1369       }
1370 
1371       // Add any platform dependent temps
1372       pd_add_temps(op);
1373 
1374       // visit definitions (output and temp operands)
1375       int k, n;
1376       n = visitor.opr_count(LIR_OpVisitState::outputMode);
1377       for (k = 0; k < n; k++) {
1378         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1379         assert(opr->is_register(), "visitor should only return register operands");
1380         add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1381       }
1382 
1383       n = visitor.opr_count(LIR_OpVisitState::tempMode);
1384       for (k = 0; k < n; k++) {
1385         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1386         assert(opr->is_register(), "visitor should only return register operands");
1387         add_temp(opr, op_id, mustHaveRegister);
1388       }
1389 
1390       // visit uses (input operands)
1391       n = visitor.opr_count(LIR_OpVisitState::inputMode);
1392       for (k = 0; k < n; k++) {
1393         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1394         assert(opr->is_register(), "visitor should only return register operands");
1395         add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1396       }
1397 
1398       // Add uses of live locals from interpreter's point of view for proper
1399       // debug information generation
1400       // Treat these operands as temp values (if the life range is extended
1401       // to a call site, the value would be in a register at the call otherwise)
1402       n = visitor.info_count();
1403       for (k = 0; k < n; k++) {
1404         CodeEmitInfo* info = visitor.info_at(k);
1405         ValueStack* stack = info->stack();
1406         for_each_state_value(stack, value,
1407           add_use(value, block_from, op_id + 1, noUse);
1408         );
1409       }
1410 
1411       // special steps for some instructions (especially moves)
1412       handle_method_arguments(op);
1413       handle_doubleword_moves(op);
1414       add_register_hints(op);
1415 
1416     } // end of instruction iteration
1417   } // end of block iteration
1418 
1419 
1420   // add the range [0, 1[ to all fixed intervals
1421   // -> the register allocator need not handle unhandled fixed intervals
1422   for (int n = 0; n < LinearScan::nof_regs; n++) {
1423     Interval* interval = interval_at(n);
1424     if (interval != NULL) {
1425       interval->add_range(0, 1);
1426     }
1427   }
1428 }
1429 
1430 
1431 // ********** Phase 5: actual register allocation
1432 
1433 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1434   if (*a != NULL) {
1435     if (*b != NULL) {
1436       return (*a)->from() - (*b)->from();
1437     } else {
1438       return -1;
1439     }
1440   } else {
1441     if (*b != NULL) {
1442       return 1;
1443     } else {
1444       return 0;
1445     }
1446   }
1447 }
1448 
1449 #ifndef PRODUCT
1450 int interval_cmp(Interval* const& l, Interval* const& r) {
1451   return l->from() - r->from();
1452 }
1453 
1454 bool find_interval(Interval* interval, IntervalArray* intervals) {
1455   bool found;
1456   int idx = intervals->find_sorted<Interval*, interval_cmp>(interval, found);
1457 
1458   if (!found) {
1459     return false;
1460   }
1461 
1462   int from = interval->from();
1463 
1464   // The index we've found using binary search is pointing to an interval
1465   // that is defined in the same place as the interval we were looking for.
1466   // So now we have to look around that index and find exact interval.
1467   for (int i = idx; i >= 0; i--) {
1468     if (intervals->at(i) == interval) {
1469       return true;
1470     }
1471     if (intervals->at(i)->from() != from) {
1472       break;
1473     }
1474   }
1475 
1476   for (int i = idx + 1; i < intervals->length(); i++) {
1477     if (intervals->at(i) == interval) {
1478       return true;
1479     }
1480     if (intervals->at(i)->from() != from) {
1481       break;
1482     }
1483   }
1484 
1485   return false;
1486 }
1487 
1488 bool LinearScan::is_sorted(IntervalArray* intervals) {
1489   int from = -1;
1490   int null_count = 0;
1491 
1492   for (int i = 0; i < intervals->length(); i++) {
1493     Interval* it = intervals->at(i);
1494     if (it != NULL) {
1495       assert(from <= it->from(), "Intervals are unordered");
1496       from = it->from();
1497     } else {
1498       null_count++;
1499     }
1500   }
1501 
1502   assert(null_count == 0, "Sorted intervals should not contain nulls");
1503 
1504   null_count = 0;
1505 
1506   for (int i = 0; i < interval_count(); i++) {
1507     Interval* interval = interval_at(i);
1508     if (interval != NULL) {
1509       assert(find_interval(interval, intervals), "Lists do not contain same intervals");
1510     } else {
1511       null_count++;
1512     }
1513   }
1514 
1515   assert(interval_count() - null_count == intervals->length(),
1516       "Sorted list should contain the same amount of non-NULL intervals as unsorted list");
1517 
1518   return true;
1519 }
1520 #endif
1521 
1522 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1523   if (*prev != NULL) {
1524     (*prev)->set_next(interval);
1525   } else {
1526     *first = interval;
1527   }
1528   *prev = interval;
1529 }
1530 
1531 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1532   assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1533 
1534   *list1 = *list2 = Interval::end();
1535 
1536   Interval* list1_prev = NULL;
1537   Interval* list2_prev = NULL;
1538   Interval* v;
1539 
1540   const int n = _sorted_intervals->length();
1541   for (int i = 0; i < n; i++) {
1542     v = _sorted_intervals->at(i);
1543     if (v == NULL) continue;
1544 
1545     if (is_list1(v)) {
1546       add_to_list(list1, &list1_prev, v);
1547     } else if (is_list2 == NULL || is_list2(v)) {
1548       add_to_list(list2, &list2_prev, v);
1549     }
1550   }
1551 
1552   if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1553   if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1554 
1555   assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1556   assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1557 }
1558 
1559 
1560 void LinearScan::sort_intervals_before_allocation() {
1561   TIME_LINEAR_SCAN(timer_sort_intervals_before);
1562 
1563   if (_needs_full_resort) {
1564     // There is no known reason why this should occur but just in case...
1565     assert(false, "should never occur");
1566     // Re-sort existing interval list because an Interval::from() has changed
1567     _sorted_intervals->sort(interval_cmp);
1568     _needs_full_resort = false;
1569   }
1570 
1571   IntervalList* unsorted_list = &_intervals;
1572   int unsorted_len = unsorted_list->length();
1573   int sorted_len = 0;
1574   int unsorted_idx;
1575   int sorted_idx = 0;
1576   int sorted_from_max = -1;
1577 
1578   // calc number of items for sorted list (sorted list must not contain NULL values)
1579   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1580     if (unsorted_list->at(unsorted_idx) != NULL) {
1581       sorted_len++;
1582     }
1583   }
1584   IntervalArray* sorted_list = new IntervalArray(sorted_len, sorted_len, NULL);
1585 
1586   // special sorting algorithm: the original interval-list is almost sorted,
1587   // only some intervals are swapped. So this is much faster than a complete QuickSort
1588   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1589     Interval* cur_interval = unsorted_list->at(unsorted_idx);
1590 
1591     if (cur_interval != NULL) {
1592       int cur_from = cur_interval->from();
1593 
1594       if (sorted_from_max <= cur_from) {
1595         sorted_list->at_put(sorted_idx++, cur_interval);
1596         sorted_from_max = cur_interval->from();
1597       } else {
1598         // the asumption that the intervals are already sorted failed,
1599         // so this interval must be sorted in manually
1600         int j;
1601         for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1602           sorted_list->at_put(j + 1, sorted_list->at(j));
1603         }
1604         sorted_list->at_put(j + 1, cur_interval);
1605         sorted_idx++;
1606       }
1607     }
1608   }
1609   _sorted_intervals = sorted_list;
1610   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1611 }
1612 
1613 void LinearScan::sort_intervals_after_allocation() {
1614   TIME_LINEAR_SCAN(timer_sort_intervals_after);
1615 
1616   if (_needs_full_resort) {
1617     // Re-sort existing interval list because an Interval::from() has changed
1618     _sorted_intervals->sort(interval_cmp);
1619     _needs_full_resort = false;
1620   }
1621 
1622   IntervalArray* old_list = _sorted_intervals;
1623   IntervalList* new_list = _new_intervals_from_allocation;
1624   int old_len = old_list->length();
1625   int new_len = new_list == NULL ? 0 : new_list->length();
1626 
1627   if (new_len == 0) {
1628     // no intervals have been added during allocation, so sorted list is already up to date
1629     assert(is_sorted(_sorted_intervals), "intervals unsorted");
1630     return;
1631   }
1632 
1633   // conventional sort-algorithm for new intervals
1634   new_list->sort(interval_cmp);
1635 
1636   // merge old and new list (both already sorted) into one combined list
1637   int combined_list_len = old_len + new_len;
1638   IntervalArray* combined_list = new IntervalArray(combined_list_len, combined_list_len, NULL);
1639   int old_idx = 0;
1640   int new_idx = 0;
1641 
1642   while (old_idx + new_idx < old_len + new_len) {
1643     if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1644       combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1645       old_idx++;
1646     } else {
1647       combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1648       new_idx++;
1649     }
1650   }
1651 
1652   _sorted_intervals = combined_list;
1653   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1654 }
1655 
1656 
1657 void LinearScan::allocate_registers() {
1658   TIME_LINEAR_SCAN(timer_allocate_registers);
1659 
1660   Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1661   Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1662 
1663   // collect cpu intervals
1664   create_unhandled_lists(&precolored_cpu_intervals, &not_precolored_cpu_intervals,
1665                          is_precolored_cpu_interval, is_virtual_cpu_interval);
1666 
1667   // collect fpu intervals
1668   create_unhandled_lists(&precolored_fpu_intervals, &not_precolored_fpu_intervals,
1669                          is_precolored_fpu_interval, is_virtual_fpu_interval);
1670   // this fpu interval collection cannot be moved down below with the allocation section as
1671   // the cpu_lsw.walk() changes interval positions.
1672 
1673   if (!has_fpu_registers()) {
1674 #ifdef ASSERT
1675     assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval");
1676 #else
1677     if (not_precolored_fpu_intervals != Interval::end()) {
1678       BAILOUT("missed an uncolored fpu interval");
1679     }
1680 #endif
1681   }
1682 
1683   // allocate cpu registers
1684   LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1685   cpu_lsw.walk();
1686   cpu_lsw.finish_allocation();
1687 
1688   if (has_fpu_registers()) {
1689     // allocate fpu registers
1690     LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1691     fpu_lsw.walk();
1692     fpu_lsw.finish_allocation();
1693   }
1694 }
1695 
1696 
1697 // ********** Phase 6: resolve data flow
1698 // (insert moves at edges between blocks if intervals have been split)
1699 
1700 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1701 // instead of returning NULL
1702 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1703   Interval* result = interval->split_child_at_op_id(op_id, mode);
1704   if (result != NULL) {
1705     return result;
1706   }
1707 
1708   assert(false, "must find an interval, but do a clean bailout in product mode");
1709   result = new Interval(LIR_OprDesc::vreg_base);
1710   result->assign_reg(0);
1711   result->set_type(T_INT);
1712   BAILOUT_("LinearScan: interval is NULL", result);
1713 }
1714 
1715 
1716 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1717   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1718   assert(interval_at(reg_num) != NULL, "no interval found");
1719 
1720   return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1721 }
1722 
1723 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1724   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1725   assert(interval_at(reg_num) != NULL, "no interval found");
1726 
1727   return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1728 }
1729 
1730 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1731   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1732   assert(interval_at(reg_num) != NULL, "no interval found");
1733 
1734   return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1735 }
1736 
1737 
1738 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1739   DEBUG_ONLY(move_resolver.check_empty());
1740 
1741   const int size = live_set_size();
1742   const ResourceBitMap live_at_edge = to_block->live_in();
1743 
1744   // visit all registers where the live_at_edge bit is set
1745   for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1746     assert(r < num_virtual_regs(), "live information set for not exisiting interval");
1747     assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1748 
1749     Interval* from_interval = interval_at_block_end(from_block, r);
1750     Interval* to_interval = interval_at_block_begin(to_block, r);
1751 
1752     if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1753       // need to insert move instruction
1754       move_resolver.add_mapping(from_interval, to_interval);
1755     }
1756   }
1757 }
1758 
1759 
1760 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1761   if (from_block->number_of_sux() <= 1) {
1762     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1763 
1764     LIR_OpList* instructions = from_block->lir()->instructions_list();
1765     LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1766     if (branch != NULL) {
1767       // insert moves before branch
1768       assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1769       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1770     } else {
1771       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1772     }
1773 
1774   } else {
1775     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1776 #ifdef ASSERT
1777     assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1778 
1779     // because the number of predecessor edges matches the number of
1780     // successor edges, blocks which are reached by switch statements
1781     // may have be more than one predecessor but it will be guaranteed
1782     // that all predecessors will be the same.
1783     for (int i = 0; i < to_block->number_of_preds(); i++) {
1784       assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1785     }
1786 #endif
1787 
1788     move_resolver.set_insert_position(to_block->lir(), 0);
1789   }
1790 }
1791 
1792 
1793 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1794 void LinearScan::resolve_data_flow() {
1795   TIME_LINEAR_SCAN(timer_resolve_data_flow);
1796 
1797   int num_blocks = block_count();
1798   MoveResolver move_resolver(this);
1799   ResourceBitMap block_completed(num_blocks);
1800   ResourceBitMap already_resolved(num_blocks);
1801 
1802   int i;
1803   for (i = 0; i < num_blocks; i++) {
1804     BlockBegin* block = block_at(i);
1805 
1806     // check if block has only one predecessor and only one successor
1807     if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1808       LIR_OpList* instructions = block->lir()->instructions_list();
1809       assert(instructions->at(0)->code() == lir_label, "block must start with label");
1810       assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1811       assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1812 
1813       // check if block is empty (only label and branch)
1814       if (instructions->length() == 2) {
1815         BlockBegin* pred = block->pred_at(0);
1816         BlockBegin* sux = block->sux_at(0);
1817 
1818         // prevent optimization of two consecutive blocks
1819         if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1820           TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1821           block_completed.set_bit(block->linear_scan_number());
1822 
1823           // directly resolve between pred and sux (without looking at the empty block between)
1824           resolve_collect_mappings(pred, sux, move_resolver);
1825           if (move_resolver.has_mappings()) {
1826             move_resolver.set_insert_position(block->lir(), 0);
1827             move_resolver.resolve_and_append_moves();
1828           }
1829         }
1830       }
1831     }
1832   }
1833 
1834 
1835   for (i = 0; i < num_blocks; i++) {
1836     if (!block_completed.at(i)) {
1837       BlockBegin* from_block = block_at(i);
1838       already_resolved.set_from(block_completed);
1839 
1840       int num_sux = from_block->number_of_sux();
1841       for (int s = 0; s < num_sux; s++) {
1842         BlockBegin* to_block = from_block->sux_at(s);
1843 
1844         // check for duplicate edges between the same blocks (can happen with switch blocks)
1845         if (!already_resolved.at(to_block->linear_scan_number())) {
1846           TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1847           already_resolved.set_bit(to_block->linear_scan_number());
1848 
1849           // collect all intervals that have been split between from_block and to_block
1850           resolve_collect_mappings(from_block, to_block, move_resolver);
1851           if (move_resolver.has_mappings()) {
1852             resolve_find_insert_pos(from_block, to_block, move_resolver);
1853             move_resolver.resolve_and_append_moves();
1854           }
1855         }
1856       }
1857     }
1858   }
1859 }
1860 
1861 
1862 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1863   if (interval_at(reg_num) == NULL) {
1864     // if a phi function is never used, no interval is created -> ignore this
1865     return;
1866   }
1867 
1868   Interval* interval = interval_at_block_begin(block, reg_num);
1869   int reg = interval->assigned_reg();
1870   int regHi = interval->assigned_regHi();
1871 
1872   if ((reg < nof_regs && interval->always_in_memory()) ||
1873       (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1874     // the interval is split to get a short range that is located on the stack
1875     // in the following two cases:
1876     // * the interval started in memory (e.g. method parameter), but is currently in a register
1877     //   this is an optimization for exception handling that reduces the number of moves that
1878     //   are necessary for resolving the states when an exception uses this exception handler
1879     // * the interval would be on the fpu stack at the begin of the exception handler
1880     //   this is not allowed because of the complicated fpu stack handling on Intel
1881 
1882     // range that will be spilled to memory
1883     int from_op_id = block->first_lir_instruction_id();
1884     int to_op_id = from_op_id + 1;  // short live range of length 1
1885     assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1886            "no split allowed between exception entry and first instruction");
1887 
1888     if (interval->from() != from_op_id) {
1889       // the part before from_op_id is unchanged
1890       interval = interval->split(from_op_id);
1891       interval->assign_reg(reg, regHi);
1892       append_interval(interval);
1893     } else {
1894       _needs_full_resort = true;
1895     }
1896     assert(interval->from() == from_op_id, "must be true now");
1897 
1898     Interval* spilled_part = interval;
1899     if (interval->to() != to_op_id) {
1900       // the part after to_op_id is unchanged
1901       spilled_part = interval->split_from_start(to_op_id);
1902       append_interval(spilled_part);
1903       move_resolver.add_mapping(spilled_part, interval);
1904     }
1905     assign_spill_slot(spilled_part);
1906 
1907     assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1908   }
1909 }
1910 
1911 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1912   assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1913   DEBUG_ONLY(move_resolver.check_empty());
1914 
1915   // visit all registers where the live_in bit is set
1916   int size = live_set_size();
1917   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1918     resolve_exception_entry(block, r, move_resolver);
1919   }
1920 
1921   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1922   for_each_phi_fun(block, phi,
1923     if (!phi->is_illegal()) { resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver); }
1924   );
1925 
1926   if (move_resolver.has_mappings()) {
1927     // insert moves after first instruction
1928     move_resolver.set_insert_position(block->lir(), 0);
1929     move_resolver.resolve_and_append_moves();
1930   }
1931 }
1932 
1933 
1934 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1935   if (interval_at(reg_num) == NULL) {
1936     // if a phi function is never used, no interval is created -> ignore this
1937     return;
1938   }
1939 
1940   // the computation of to_interval is equal to resolve_collect_mappings,
1941   // but from_interval is more complicated because of phi functions
1942   BlockBegin* to_block = handler->entry_block();
1943   Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1944 
1945   if (phi != NULL) {
1946     // phi function of the exception entry block
1947     // no moves are created for this phi function in the LIR_Generator, so the
1948     // interval at the throwing instruction must be searched using the operands
1949     // of the phi function
1950     Value from_value = phi->operand_at(handler->phi_operand());
1951 
1952     // with phi functions it can happen that the same from_value is used in
1953     // multiple mappings, so notify move-resolver that this is allowed
1954     move_resolver.set_multiple_reads_allowed();
1955 
1956     Constant* con = from_value->as_Constant();
1957     if (con != NULL && (!con->is_pinned() || con->operand()->is_constant())) {
1958       // Need a mapping from constant to interval if unpinned (may have no register) or if the operand is a constant (no register).
1959       move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1960     } else {
1961       // search split child at the throwing op_id
1962       Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1963       move_resolver.add_mapping(from_interval, to_interval);
1964     }
1965   } else {
1966     // no phi function, so use reg_num also for from_interval
1967     // search split child at the throwing op_id
1968     Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1969     if (from_interval != to_interval) {
1970       // optimization to reduce number of moves: when to_interval is on stack and
1971       // the stack slot is known to be always correct, then no move is necessary
1972       if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1973         move_resolver.add_mapping(from_interval, to_interval);
1974       }
1975     }
1976   }
1977 }
1978 
1979 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1980   TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1981 
1982   DEBUG_ONLY(move_resolver.check_empty());
1983   assert(handler->lir_op_id() == -1, "already processed this xhandler");
1984   DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1985   assert(handler->entry_code() == NULL, "code already present");
1986 
1987   // visit all registers where the live_in bit is set
1988   BlockBegin* block = handler->entry_block();
1989   int size = live_set_size();
1990   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1991     resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1992   }
1993 
1994   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1995   for_each_phi_fun(block, phi,
1996     if (!phi->is_illegal()) { resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver); }
1997   );
1998 
1999   if (move_resolver.has_mappings()) {
2000     LIR_List* entry_code = new LIR_List(compilation());
2001     move_resolver.set_insert_position(entry_code, 0);
2002     move_resolver.resolve_and_append_moves();
2003 
2004     entry_code->jump(handler->entry_block());
2005     handler->set_entry_code(entry_code);
2006   }
2007 }
2008 
2009 
2010 void LinearScan::resolve_exception_handlers() {
2011   MoveResolver move_resolver(this);
2012   LIR_OpVisitState visitor;
2013   int num_blocks = block_count();
2014 
2015   int i;
2016   for (i = 0; i < num_blocks; i++) {
2017     BlockBegin* block = block_at(i);
2018     if (block->is_set(BlockBegin::exception_entry_flag)) {
2019       resolve_exception_entry(block, move_resolver);
2020     }
2021   }
2022 
2023   for (i = 0; i < num_blocks; i++) {
2024     BlockBegin* block = block_at(i);
2025     LIR_List* ops = block->lir();
2026     int num_ops = ops->length();
2027 
2028     // iterate all instructions of the block. skip the first because it is always a label
2029     assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
2030     for (int j = 1; j < num_ops; j++) {
2031       LIR_Op* op = ops->at(j);
2032       int op_id = op->id();
2033 
2034       if (op_id != -1 && has_info(op_id)) {
2035         // visit operation to collect all operands
2036         visitor.visit(op);
2037         assert(visitor.info_count() > 0, "should not visit otherwise");
2038 
2039         XHandlers* xhandlers = visitor.all_xhandler();
2040         int n = xhandlers->length();
2041         for (int k = 0; k < n; k++) {
2042           resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
2043         }
2044 
2045 #ifdef ASSERT
2046       } else {
2047         visitor.visit(op);
2048         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2049 #endif
2050       }
2051     }
2052   }
2053 }
2054 
2055 
2056 // ********** Phase 7: assign register numbers back to LIR
2057 // (includes computation of debug information and oop maps)
2058 
2059 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2060   VMReg reg = interval->cached_vm_reg();
2061   if (!reg->is_valid() ) {
2062     reg = vm_reg_for_operand(operand_for_interval(interval));
2063     interval->set_cached_vm_reg(reg);
2064   }
2065   assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2066   return reg;
2067 }
2068 
2069 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2070   assert(opr->is_oop(), "currently only implemented for oop operands");
2071   return frame_map()->regname(opr);
2072 }
2073 
2074 
2075 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2076   LIR_Opr opr = interval->cached_opr();
2077   if (opr->is_illegal()) {
2078     opr = calc_operand_for_interval(interval);
2079     interval->set_cached_opr(opr);
2080   }
2081 
2082   assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2083   return opr;
2084 }
2085 
2086 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2087   int assigned_reg = interval->assigned_reg();
2088   BasicType type = interval->type();
2089 
2090   if (assigned_reg >= nof_regs) {
2091     // stack slot
2092     assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2093     return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2094 
2095   } else {
2096     // register
2097     switch (type) {
2098       case T_OBJECT: {
2099         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2100         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2101         return LIR_OprFact::single_cpu_oop(assigned_reg);
2102       }
2103 
2104       case T_ADDRESS: {
2105         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2106         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2107         return LIR_OprFact::single_cpu_address(assigned_reg);
2108       }
2109 
2110       case T_METADATA: {
2111         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2112         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2113         return LIR_OprFact::single_cpu_metadata(assigned_reg);
2114       }
2115 
2116 #ifdef __SOFTFP__
2117       case T_FLOAT:  // fall through
2118 #endif // __SOFTFP__
2119       case T_INT: {
2120         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2121         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2122         return LIR_OprFact::single_cpu(assigned_reg);
2123       }
2124 
2125 #ifdef __SOFTFP__
2126       case T_DOUBLE:  // fall through
2127 #endif // __SOFTFP__
2128       case T_LONG: {
2129         int assigned_regHi = interval->assigned_regHi();
2130         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2131         assert(num_physical_regs(T_LONG) == 1 ||
2132                (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2133 
2134         assert(assigned_reg != assigned_regHi, "invalid allocation");
2135         assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2136                "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2137         assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2138         if (requires_adjacent_regs(T_LONG)) {
2139           assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2140         }
2141 
2142 #ifdef _LP64
2143         return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2144 #else
2145 #if defined(PPC32)
2146         return LIR_OprFact::double_cpu(assigned_regHi, assigned_reg);
2147 #else
2148         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2149 #endif // PPC32
2150 #endif // LP64
2151       }
2152 
2153 #ifndef __SOFTFP__
2154       case T_FLOAT: {
2155 #ifdef X86
2156         if (UseSSE >= 1) {
2157           int last_xmm_reg = pd_last_xmm_reg;
2158 #ifdef _LP64
2159           if (UseAVX < 3) {
2160             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2161           }
2162 #endif // LP64
2163           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2164           assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2165           return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2166         }
2167 #endif // X86
2168 
2169         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2170         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2171         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2172       }
2173 
2174       case T_DOUBLE: {
2175 #ifdef X86
2176         if (UseSSE >= 2) {
2177           int last_xmm_reg = pd_last_xmm_reg;
2178 #ifdef _LP64
2179           if (UseAVX < 3) {
2180             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2181           }
2182 #endif // LP64
2183           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2184           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2185           return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2186         }
2187 #endif // X86
2188 
2189 #if defined(ARM32)
2190         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2191         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2192         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2193         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2194 #else
2195         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2196         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2197         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2198 #endif
2199         return result;
2200       }
2201 #endif // __SOFTFP__
2202 
2203       default: {
2204         ShouldNotReachHere();
2205         return LIR_OprFact::illegalOpr;
2206       }
2207     }
2208   }
2209 }
2210 
2211 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2212   assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2213   return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2214 }
2215 
2216 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2217   assert(opr->is_virtual(), "should not call this otherwise");
2218 
2219   Interval* interval = interval_at(opr->vreg_number());
2220   assert(interval != NULL, "interval must exist");
2221 
2222   if (op_id != -1) {
2223 #ifdef ASSERT
2224     BlockBegin* block = block_of_op_with_id(op_id);
2225     if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2226       // check if spill moves could have been appended at the end of this block, but
2227       // before the branch instruction. So the split child information for this branch would
2228       // be incorrect.
2229       LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2230       if (branch != NULL) {
2231         if (block->live_out().at(opr->vreg_number())) {
2232           assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2233           assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2234         }
2235       }
2236     }
2237 #endif
2238 
2239     // operands are not changed when an interval is split during allocation,
2240     // so search the right interval here
2241     interval = split_child_at_op_id(interval, op_id, mode);
2242   }
2243 
2244   LIR_Opr res = operand_for_interval(interval);
2245 
2246 #ifdef X86
2247   // new semantic for is_last_use: not only set on definite end of interval,
2248   // but also before hole
2249   // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2250   // last use information is completely correct
2251   // information is only needed for fpu stack allocation
2252   if (res->is_fpu_register()) {
2253     if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2254       assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2255       res = res->make_last_use();
2256     }
2257   }
2258 #endif
2259 
2260   assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2261 
2262   return res;
2263 }
2264 
2265 
2266 #ifdef ASSERT
2267 // some methods used to check correctness of debug information
2268 
2269 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2270   if (values == NULL) {
2271     return;
2272   }
2273 
2274   for (int i = 0; i < values->length(); i++) {
2275     ScopeValue* value = values->at(i);
2276 
2277     if (value->is_location()) {
2278       Location location = ((LocationValue*)value)->location();
2279       assert(location.where() == Location::on_stack, "value is in register");
2280     }
2281   }
2282 }
2283 
2284 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2285   if (values == NULL) {
2286     return;
2287   }
2288 
2289   for (int i = 0; i < values->length(); i++) {
2290     MonitorValue* value = values->at(i);
2291 
2292     if (value->owner()->is_location()) {
2293       Location location = ((LocationValue*)value->owner())->location();
2294       assert(location.where() == Location::on_stack, "owner is in register");
2295     }
2296     assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2297   }
2298 }
2299 
2300 void assert_equal(Location l1, Location l2) {
2301   assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2302 }
2303 
2304 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2305   if (v1->is_location()) {
2306     assert(v2->is_location(), "");
2307     assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2308   } else if (v1->is_constant_int()) {
2309     assert(v2->is_constant_int(), "");
2310     assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2311   } else if (v1->is_constant_double()) {
2312     assert(v2->is_constant_double(), "");
2313     assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2314   } else if (v1->is_constant_long()) {
2315     assert(v2->is_constant_long(), "");
2316     assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2317   } else if (v1->is_constant_oop()) {
2318     assert(v2->is_constant_oop(), "");
2319     assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2320   } else {
2321     ShouldNotReachHere();
2322   }
2323 }
2324 
2325 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2326   assert_equal(m1->owner(), m2->owner());
2327   assert_equal(m1->basic_lock(), m2->basic_lock());
2328 }
2329 
2330 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2331   assert(d1->scope() == d2->scope(), "not equal");
2332   assert(d1->bci() == d2->bci(), "not equal");
2333 
2334   if (d1->locals() != NULL) {
2335     assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2336     assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2337     for (int i = 0; i < d1->locals()->length(); i++) {
2338       assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2339     }
2340   } else {
2341     assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2342   }
2343 
2344   if (d1->expressions() != NULL) {
2345     assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2346     assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2347     for (int i = 0; i < d1->expressions()->length(); i++) {
2348       assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2349     }
2350   } else {
2351     assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2352   }
2353 
2354   if (d1->monitors() != NULL) {
2355     assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2356     assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2357     for (int i = 0; i < d1->monitors()->length(); i++) {
2358       assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2359     }
2360   } else {
2361     assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2362   }
2363 
2364   if (d1->caller() != NULL) {
2365     assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2366     assert_equal(d1->caller(), d2->caller());
2367   } else {
2368     assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2369   }
2370 }
2371 
2372 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2373   if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2374     Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2375     switch (code) {
2376       case Bytecodes::_ifnull    : // fall through
2377       case Bytecodes::_ifnonnull : // fall through
2378       case Bytecodes::_ifeq      : // fall through
2379       case Bytecodes::_ifne      : // fall through
2380       case Bytecodes::_iflt      : // fall through
2381       case Bytecodes::_ifge      : // fall through
2382       case Bytecodes::_ifgt      : // fall through
2383       case Bytecodes::_ifle      : // fall through
2384       case Bytecodes::_if_icmpeq : // fall through
2385       case Bytecodes::_if_icmpne : // fall through
2386       case Bytecodes::_if_icmplt : // fall through
2387       case Bytecodes::_if_icmpge : // fall through
2388       case Bytecodes::_if_icmpgt : // fall through
2389       case Bytecodes::_if_icmple : // fall through
2390       case Bytecodes::_if_acmpeq : // fall through
2391       case Bytecodes::_if_acmpne :
2392         assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2393         break;
2394       default:
2395         break;
2396     }
2397   }
2398 }
2399 
2400 #endif // ASSERT
2401 
2402 
2403 IntervalWalker* LinearScan::init_compute_oop_maps() {
2404   // setup lists of potential oops for walking
2405   Interval* oop_intervals;
2406   Interval* non_oop_intervals;
2407 
2408   create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2409 
2410   // intervals that have no oops inside need not to be processed
2411   // to ensure a walking until the last instruction id, add a dummy interval
2412   // with a high operation id
2413   non_oop_intervals = new Interval(any_reg);
2414   non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2415 
2416   return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2417 }
2418 
2419 
2420 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2421   TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2422 
2423   // walk before the current operation -> intervals that start at
2424   // the operation (= output operands of the operation) are not
2425   // included in the oop map
2426   iw->walk_before(op->id());
2427 
2428   int frame_size = frame_map()->framesize();
2429   int arg_count = frame_map()->oop_map_arg_count();
2430   OopMap* map = new OopMap(frame_size, arg_count);
2431 
2432   // Iterate through active intervals
2433   for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2434     int assigned_reg = interval->assigned_reg();
2435 
2436     assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2437     assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2438     assert(interval->reg_num() >= LIR_OprDesc::vreg_base, "fixed interval found");
2439 
2440     // Check if this range covers the instruction. Intervals that
2441     // start or end at the current operation are not included in the
2442     // oop map, except in the case of patching moves.  For patching
2443     // moves, any intervals which end at this instruction are included
2444     // in the oop map since we may safepoint while doing the patch
2445     // before we've consumed the inputs.
2446     if (op->is_patching() || op->id() < interval->current_to()) {
2447 
2448       // caller-save registers must not be included into oop-maps at calls
2449       assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2450 
2451       VMReg name = vm_reg_for_interval(interval);
2452       set_oop(map, name);
2453 
2454       // Spill optimization: when the stack value is guaranteed to be always correct,
2455       // then it must be added to the oop map even if the interval is currently in a register
2456       if (interval->always_in_memory() &&
2457           op->id() > interval->spill_definition_pos() &&
2458           interval->assigned_reg() != interval->canonical_spill_slot()) {
2459         assert(interval->spill_definition_pos() > 0, "position not set correctly");
2460         assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2461         assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2462 
2463         set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2464       }
2465     }
2466   }
2467 
2468   // add oops from lock stack
2469   assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2470   int locks_count = info->stack()->total_locks_size();
2471   for (int i = 0; i < locks_count; i++) {
2472     set_oop(map, frame_map()->monitor_object_regname(i));
2473   }
2474 
2475   return map;
2476 }
2477 
2478 
2479 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2480   assert(visitor.info_count() > 0, "no oop map needed");
2481 
2482   // compute oop_map only for first CodeEmitInfo
2483   // because it is (in most cases) equal for all other infos of the same operation
2484   CodeEmitInfo* first_info = visitor.info_at(0);
2485   OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2486 
2487   for (int i = 0; i < visitor.info_count(); i++) {
2488     CodeEmitInfo* info = visitor.info_at(i);
2489     OopMap* oop_map = first_oop_map;
2490 
2491     // compute worst case interpreter size in case of a deoptimization
2492     _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2493 
2494     if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2495       // this info has a different number of locks then the precomputed oop map
2496       // (possible for lock and unlock instructions) -> compute oop map with
2497       // correct lock information
2498       oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2499     }
2500 
2501     if (info->_oop_map == NULL) {
2502       info->_oop_map = oop_map;
2503     } else {
2504       // a CodeEmitInfo can not be shared between different LIR-instructions
2505       // because interval splitting can occur anywhere between two instructions
2506       // and so the oop maps must be different
2507       // -> check if the already set oop_map is exactly the one calculated for this operation
2508       assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2509     }
2510   }
2511 }
2512 
2513 
2514 // frequently used constants
2515 // Allocate them with new so they are never destroyed (otherwise, a
2516 // forced exit could destroy these objects while they are still in
2517 // use).
2518 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
2519 ConstantIntValue*      LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
2520 ConstantIntValue*      LinearScan::_int_0_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue((jint)0);
2521 ConstantIntValue*      LinearScan::_int_1_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
2522 ConstantIntValue*      LinearScan::_int_2_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
2523 LocationValue*         _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location());
2524 
2525 void LinearScan::init_compute_debug_info() {
2526   // cache for frequently used scope values
2527   // (cpu registers and stack slots)
2528   int cache_size = (LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2;
2529   _scope_value_cache = ScopeValueArray(cache_size, cache_size, NULL);
2530 }
2531 
2532 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2533   Location loc;
2534   if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2535     bailout("too large frame");
2536   }
2537   ScopeValue* object_scope_value = new LocationValue(loc);
2538 
2539   if (!frame_map()->location_for_monitor_lock(monitor_index, &loc)) {
2540     bailout("too large frame");
2541   }
2542   return new MonitorValue(object_scope_value, loc);
2543 }
2544 
2545 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2546   Location loc;
2547   if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2548     bailout("too large frame");
2549   }
2550   return new LocationValue(loc);
2551 }
2552 
2553 
2554 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2555   assert(opr->is_constant(), "should not be called otherwise");
2556 
2557   LIR_Const* c = opr->as_constant_ptr();
2558   BasicType t = c->type();
2559   switch (t) {
2560     case T_OBJECT: {
2561       jobject value = c->as_jobject();
2562       if (value == NULL) {
2563         scope_values->append(_oop_null_scope_value);
2564       } else {
2565         scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2566       }
2567       return 1;
2568     }
2569 
2570     case T_INT: // fall through
2571     case T_FLOAT: {
2572       int value = c->as_jint_bits();
2573       switch (value) {
2574         case -1: scope_values->append(_int_m1_scope_value); break;
2575         case 0:  scope_values->append(_int_0_scope_value); break;
2576         case 1:  scope_values->append(_int_1_scope_value); break;
2577         case 2:  scope_values->append(_int_2_scope_value); break;
2578         default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2579       }
2580       return 1;
2581     }
2582 
2583     case T_LONG: // fall through
2584     case T_DOUBLE: {
2585 #ifdef _LP64
2586       scope_values->append(_int_0_scope_value);
2587       scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2588 #else
2589       if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2590         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2591         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2592       } else {
2593         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2594         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2595       }
2596 #endif
2597       return 2;
2598     }
2599 
2600     case T_ADDRESS: {
2601 #ifdef _LP64
2602       scope_values->append(new ConstantLongValue(c->as_jint()));
2603 #else
2604       scope_values->append(new ConstantIntValue(c->as_jint()));
2605 #endif
2606       return 1;
2607     }
2608 
2609     default:
2610       ShouldNotReachHere();
2611       return -1;
2612   }
2613 }
2614 
2615 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2616   if (opr->is_single_stack()) {
2617     int stack_idx = opr->single_stack_ix();
2618     bool is_oop = opr->is_oop_register();
2619     int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2620 
2621     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2622     if (sv == NULL) {
2623       Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2624       sv = location_for_name(stack_idx, loc_type);
2625       _scope_value_cache.at_put(cache_idx, sv);
2626     }
2627 
2628     // check if cached value is correct
2629     DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2630 
2631     scope_values->append(sv);
2632     return 1;
2633 
2634   } else if (opr->is_single_cpu()) {
2635     bool is_oop = opr->is_oop_register();
2636     int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2637     Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2638 
2639     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2640     if (sv == NULL) {
2641       Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2642       VMReg rname = frame_map()->regname(opr);
2643       sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2644       _scope_value_cache.at_put(cache_idx, sv);
2645     }
2646 
2647     // check if cached value is correct
2648     DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2649 
2650     scope_values->append(sv);
2651     return 1;
2652 
2653 #ifdef X86
2654   } else if (opr->is_single_xmm()) {
2655     VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2656     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2657 
2658     scope_values->append(sv);
2659     return 1;
2660 #endif
2661 
2662   } else if (opr->is_single_fpu()) {
2663 #ifdef IA32
2664     // the exact location of fpu stack values is only known
2665     // during fpu stack allocation, so the stack allocator object
2666     // must be present
2667     assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2668     assert(_fpu_stack_allocator != NULL, "must be present");
2669     opr = _fpu_stack_allocator->to_fpu_stack(opr);
2670 #elif defined(AMD64)
2671     assert(false, "FPU not used on x86-64");
2672 #endif
2673 
2674     Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2675     VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2676 #ifndef __SOFTFP__
2677 #ifndef VM_LITTLE_ENDIAN
2678     // On S390 a (single precision) float value occupies only the high
2679     // word of the full double register. So when the double register is
2680     // stored to memory (e.g. by the RegisterSaver), then the float value
2681     // is found at offset 0. I.e. the code below is not needed on S390.
2682 #ifndef S390
2683     if (! float_saved_as_double) {
2684       // On big endian system, we may have an issue if float registers use only
2685       // the low half of the (same) double registers.
2686       // Both the float and the double could have the same regnr but would correspond
2687       // to two different addresses once saved.
2688 
2689       // get next safely (no assertion checks)
2690       VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2691       if (next->is_reg() &&
2692           (next->as_FloatRegister() == rname->as_FloatRegister())) {
2693         // the back-end does use the same numbering for the double and the float
2694         rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2695       }
2696     }
2697 #endif // !S390
2698 #endif
2699 #endif
2700     LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2701 
2702     scope_values->append(sv);
2703     return 1;
2704 
2705   } else {
2706     // double-size operands
2707 
2708     ScopeValue* first;
2709     ScopeValue* second;
2710 
2711     if (opr->is_double_stack()) {
2712 #ifdef _LP64
2713       Location loc1;
2714       Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2715       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2716         bailout("too large frame");
2717       }
2718 
2719       first =  new LocationValue(loc1);
2720       second = _int_0_scope_value;
2721 #else
2722       Location loc1, loc2;
2723       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2724         bailout("too large frame");
2725       }
2726       first =  new LocationValue(loc1);
2727       second = new LocationValue(loc2);
2728 #endif // _LP64
2729 
2730     } else if (opr->is_double_cpu()) {
2731 #ifdef _LP64
2732       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2733       first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2734       second = _int_0_scope_value;
2735 #else
2736       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2737       VMReg rname_second = opr->as_register_hi()->as_VMReg();
2738 
2739       if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2740         // lo/hi and swapped relative to first and second, so swap them
2741         VMReg tmp = rname_first;
2742         rname_first = rname_second;
2743         rname_second = tmp;
2744       }
2745 
2746       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2747       second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2748 #endif //_LP64
2749 
2750 
2751 #ifdef X86
2752     } else if (opr->is_double_xmm()) {
2753       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2754       VMReg rname_first  = opr->as_xmm_double_reg()->as_VMReg();
2755 #  ifdef _LP64
2756       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2757       second = _int_0_scope_value;
2758 #  else
2759       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2760       // %%% This is probably a waste but we'll keep things as they were for now
2761       if (true) {
2762         VMReg rname_second = rname_first->next();
2763         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2764       }
2765 #  endif
2766 #endif
2767 
2768     } else if (opr->is_double_fpu()) {
2769       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2770       // the double as float registers in the native ordering. On X86,
2771       // fpu_regnrLo is a FPU stack slot whose VMReg represents
2772       // the low-order word of the double and fpu_regnrLo + 1 is the
2773       // name for the other half.  *first and *second must represent the
2774       // least and most significant words, respectively.
2775 
2776 #ifdef IA32
2777       // the exact location of fpu stack values is only known
2778       // during fpu stack allocation, so the stack allocator object
2779       // must be present
2780       assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2781       assert(_fpu_stack_allocator != NULL, "must be present");
2782       opr = _fpu_stack_allocator->to_fpu_stack(opr);
2783 
2784       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2785 #endif
2786 #ifdef AMD64
2787       assert(false, "FPU not used on x86-64");
2788 #endif
2789 #ifdef ARM32
2790       assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2791 #endif
2792 #ifdef PPC32
2793       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrHi is used)");
2794 #endif
2795 
2796 #ifdef VM_LITTLE_ENDIAN
2797       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2798 #else
2799       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2800 #endif
2801 
2802 #ifdef _LP64
2803       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2804       second = _int_0_scope_value;
2805 #else
2806       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2807       // %%% This is probably a waste but we'll keep things as they were for now
2808       if (true) {
2809         VMReg rname_second = rname_first->next();
2810         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2811       }
2812 #endif
2813 
2814     } else {
2815       ShouldNotReachHere();
2816       first = NULL;
2817       second = NULL;
2818     }
2819 
2820     assert(first != NULL && second != NULL, "must be set");
2821     // The convention the interpreter uses is that the second local
2822     // holds the first raw word of the native double representation.
2823     // This is actually reasonable, since locals and stack arrays
2824     // grow downwards in all implementations.
2825     // (If, on some machine, the interpreter's Java locals or stack
2826     // were to grow upwards, the embedded doubles would be word-swapped.)
2827     scope_values->append(second);
2828     scope_values->append(first);
2829     return 2;
2830   }
2831 }
2832 
2833 
2834 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2835   if (value != NULL) {
2836     LIR_Opr opr = value->operand();
2837     Constant* con = value->as_Constant();
2838 
2839     assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "asumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2840     assert(con != NULL || opr->is_virtual(), "asumption: non-Constant instructions have only virtual operands");
2841 
2842     if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2843       // Unpinned constants may have a virtual operand for a part of the lifetime
2844       // or may be illegal when it was optimized away,
2845       // so always use a constant operand
2846       opr = LIR_OprFact::value_type(con->type());
2847     }
2848     assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2849 
2850     if (opr->is_virtual()) {
2851       LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2852 
2853       BlockBegin* block = block_of_op_with_id(op_id);
2854       if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2855         // generating debug information for the last instruction of a block.
2856         // if this instruction is a branch, spill moves are inserted before this branch
2857         // and so the wrong operand would be returned (spill moves at block boundaries are not
2858         // considered in the live ranges of intervals)
2859         // Solution: use the first op_id of the branch target block instead.
2860         if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2861           if (block->live_out().at(opr->vreg_number())) {
2862             op_id = block->sux_at(0)->first_lir_instruction_id();
2863             mode = LIR_OpVisitState::outputMode;
2864           }
2865         }
2866       }
2867 
2868       // Get current location of operand
2869       // The operand must be live because debug information is considered when building the intervals
2870       // if the interval is not live, color_lir_opr will cause an assertion failure
2871       opr = color_lir_opr(opr, op_id, mode);
2872       assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2873 
2874       // Append to ScopeValue array
2875       return append_scope_value_for_operand(opr, scope_values);
2876 
2877     } else {
2878       assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2879       assert(opr->is_constant(), "operand must be constant");
2880 
2881       return append_scope_value_for_constant(opr, scope_values);
2882     }
2883   } else {
2884     // append a dummy value because real value not needed
2885     scope_values->append(_illegal_value);
2886     return 1;
2887   }
2888 }
2889 
2890 
2891 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2892   IRScopeDebugInfo* caller_debug_info = NULL;
2893 
2894   ValueStack* caller_state = cur_state->caller_state();
2895   if (caller_state != NULL) {
2896     // process recursively to compute outermost scope first
2897     caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2898   }
2899 
2900   // initialize these to null.
2901   // If we don't need deopt info or there are no locals, expressions or monitors,
2902   // then these get recorded as no information and avoids the allocation of 0 length arrays.
2903   GrowableArray<ScopeValue*>*   locals      = NULL;
2904   GrowableArray<ScopeValue*>*   expressions = NULL;
2905   GrowableArray<MonitorValue*>* monitors    = NULL;
2906 
2907   // describe local variable values
2908   int nof_locals = cur_state->locals_size();
2909   if (nof_locals > 0) {
2910     locals = new GrowableArray<ScopeValue*>(nof_locals);
2911 
2912     int pos = 0;
2913     while (pos < nof_locals) {
2914       assert(pos < cur_state->locals_size(), "why not?");
2915 
2916       Value local = cur_state->local_at(pos);
2917       pos += append_scope_value(op_id, local, locals);
2918 
2919       assert(locals->length() == pos, "must match");
2920     }
2921     assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2922     assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2923   } else if (cur_scope->method()->max_locals() > 0) {
2924     assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2925     nof_locals = cur_scope->method()->max_locals();
2926     locals = new GrowableArray<ScopeValue*>(nof_locals);
2927     for(int i = 0; i < nof_locals; i++) {
2928       locals->append(_illegal_value);
2929     }
2930   }
2931 
2932   // describe expression stack
2933   int nof_stack = cur_state->stack_size();
2934   if (nof_stack > 0) {
2935     expressions = new GrowableArray<ScopeValue*>(nof_stack);
2936 
2937     int pos = 0;
2938     while (pos < nof_stack) {
2939       Value expression = cur_state->stack_at_inc(pos);
2940       append_scope_value(op_id, expression, expressions);
2941 
2942       assert(expressions->length() == pos, "must match");
2943     }
2944     assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2945   }
2946 
2947   // describe monitors
2948   int nof_locks = cur_state->locks_size();
2949   if (nof_locks > 0) {
2950     int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2951     monitors = new GrowableArray<MonitorValue*>(nof_locks);
2952     for (int i = 0; i < nof_locks; i++) {
2953       monitors->append(location_for_monitor_index(lock_offset + i));
2954     }
2955   }
2956 
2957   return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info, cur_state->should_reexecute());
2958 }
2959 
2960 
2961 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2962   TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2963 
2964   IRScope* innermost_scope = info->scope();
2965   ValueStack* innermost_state = info->stack();
2966 
2967   assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2968 
2969   DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2970 
2971   if (info->_scope_debug_info == NULL) {
2972     // compute debug information
2973     info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2974   } else {
2975     // debug information already set. Check that it is correct from the current point of view
2976     DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2977   }
2978 }
2979 
2980 
2981 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2982   LIR_OpVisitState visitor;
2983   int num_inst = instructions->length();
2984   bool has_dead = false;
2985 
2986   for (int j = 0; j < num_inst; j++) {
2987     LIR_Op* op = instructions->at(j);
2988     if (op == NULL) {  // this can happen when spill-moves are removed in eliminate_spill_moves
2989       has_dead = true;
2990       continue;
2991     }
2992     int op_id = op->id();
2993 
2994     // visit instruction to get list of operands
2995     visitor.visit(op);
2996 
2997     // iterate all modes of the visitor and process all virtual operands
2998     for_each_visitor_mode(mode) {
2999       int n = visitor.opr_count(mode);
3000       for (int k = 0; k < n; k++) {
3001         LIR_Opr opr = visitor.opr_at(mode, k);
3002         if (opr->is_virtual_register()) {
3003           visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
3004         }
3005       }
3006     }
3007 
3008     if (visitor.info_count() > 0) {
3009       // exception handling
3010       if (compilation()->has_exception_handlers()) {
3011         XHandlers* xhandlers = visitor.all_xhandler();
3012         int n = xhandlers->length();
3013         for (int k = 0; k < n; k++) {
3014           XHandler* handler = xhandlers->handler_at(k);
3015           if (handler->entry_code() != NULL) {
3016             assign_reg_num(handler->entry_code()->instructions_list(), NULL);
3017           }
3018         }
3019       } else {
3020         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
3021       }
3022 
3023       // compute oop map
3024       assert(iw != NULL, "needed for compute_oop_map");
3025       compute_oop_map(iw, visitor, op);
3026 
3027       // compute debug information
3028       if (!use_fpu_stack_allocation()) {
3029         // compute debug information if fpu stack allocation is not needed.
3030         // when fpu stack allocation is needed, the debug information can not
3031         // be computed here because the exact location of fpu operands is not known
3032         // -> debug information is created inside the fpu stack allocator
3033         int n = visitor.info_count();
3034         for (int k = 0; k < n; k++) {
3035           compute_debug_info(visitor.info_at(k), op_id);
3036         }
3037       }
3038     }
3039 
3040 #ifdef ASSERT
3041     // make sure we haven't made the op invalid.
3042     op->verify();
3043 #endif
3044 
3045     // remove useless moves
3046     if (op->code() == lir_move) {
3047       assert(op->as_Op1() != NULL, "move must be LIR_Op1");
3048       LIR_Op1* move = (LIR_Op1*)op;
3049       LIR_Opr src = move->in_opr();
3050       LIR_Opr dst = move->result_opr();
3051       if (dst == src ||
3052           (!dst->is_pointer() && !src->is_pointer() &&
3053            src->is_same_register(dst))) {
3054         instructions->at_put(j, NULL);
3055         has_dead = true;
3056       }
3057     }
3058   }
3059 
3060   if (has_dead) {
3061     // iterate all instructions of the block and remove all null-values.
3062     int insert_point = 0;
3063     for (int j = 0; j < num_inst; j++) {
3064       LIR_Op* op = instructions->at(j);
3065       if (op != NULL) {
3066         if (insert_point != j) {
3067           instructions->at_put(insert_point, op);
3068         }
3069         insert_point++;
3070       }
3071     }
3072     instructions->trunc_to(insert_point);
3073   }
3074 }
3075 
3076 void LinearScan::assign_reg_num() {
3077   TIME_LINEAR_SCAN(timer_assign_reg_num);
3078 
3079   init_compute_debug_info();
3080   IntervalWalker* iw = init_compute_oop_maps();
3081 
3082   int num_blocks = block_count();
3083   for (int i = 0; i < num_blocks; i++) {
3084     BlockBegin* block = block_at(i);
3085     assign_reg_num(block->lir()->instructions_list(), iw);
3086   }
3087 }
3088 
3089 
3090 void LinearScan::do_linear_scan() {
3091   NOT_PRODUCT(_total_timer.begin_method());
3092 
3093   number_instructions();
3094 
3095   NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3096 
3097   compute_local_live_sets();
3098   compute_global_live_sets();
3099   CHECK_BAILOUT();
3100 
3101   build_intervals();
3102   CHECK_BAILOUT();
3103   sort_intervals_before_allocation();
3104 
3105   NOT_PRODUCT(print_intervals("Before Register Allocation"));
3106   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3107 
3108   allocate_registers();
3109   CHECK_BAILOUT();
3110 
3111   resolve_data_flow();
3112   if (compilation()->has_exception_handlers()) {
3113     resolve_exception_handlers();
3114   }
3115   // fill in number of spill slots into frame_map
3116   propagate_spill_slots();
3117   CHECK_BAILOUT();
3118 
3119   NOT_PRODUCT(print_intervals("After Register Allocation"));
3120   NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3121 
3122   sort_intervals_after_allocation();
3123 
3124   DEBUG_ONLY(verify());
3125 
3126   eliminate_spill_moves();
3127   assign_reg_num();
3128   CHECK_BAILOUT();
3129 
3130   NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3131   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3132 
3133   { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3134 
3135     if (use_fpu_stack_allocation()) {
3136       allocate_fpu_stack(); // Only has effect on Intel
3137       NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3138     }
3139   }
3140 
3141   { TIME_LINEAR_SCAN(timer_optimize_lir);
3142 
3143     EdgeMoveOptimizer::optimize(ir()->code());
3144     ControlFlowOptimizer::optimize(ir()->code());
3145     // check that cfg is still correct after optimizations
3146     ir()->verify();
3147   }
3148 
3149   NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3150   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3151   NOT_PRODUCT(_total_timer.end_method(this));
3152 }
3153 
3154 
3155 // ********** Printing functions
3156 
3157 #ifndef PRODUCT
3158 
3159 void LinearScan::print_timers(double total) {
3160   _total_timer.print(total);
3161 }
3162 
3163 void LinearScan::print_statistics() {
3164   _stat_before_alloc.print("before allocation");
3165   _stat_after_asign.print("after assignment of register");
3166   _stat_final.print("after optimization");
3167 }
3168 
3169 void LinearScan::print_bitmap(BitMap& b) {
3170   for (unsigned int i = 0; i < b.size(); i++) {
3171     if (b.at(i)) tty->print("%d ", i);
3172   }
3173   tty->cr();
3174 }
3175 
3176 void LinearScan::print_intervals(const char* label) {
3177   if (TraceLinearScanLevel >= 1) {
3178     int i;
3179     tty->cr();
3180     tty->print_cr("%s", label);
3181 
3182     for (i = 0; i < interval_count(); i++) {
3183       Interval* interval = interval_at(i);
3184       if (interval != NULL) {
3185         interval->print();
3186       }
3187     }
3188 
3189     tty->cr();
3190     tty->print_cr("--- Basic Blocks ---");
3191     for (i = 0; i < block_count(); i++) {
3192       BlockBegin* block = block_at(i);
3193       tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3194     }
3195     tty->cr();
3196     tty->cr();
3197   }
3198 
3199   if (PrintCFGToFile) {
3200     CFGPrinter::print_intervals(&_intervals, label);
3201   }
3202 }
3203 
3204 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3205   if (TraceLinearScanLevel >= level) {
3206     tty->cr();
3207     tty->print_cr("%s", label);
3208     print_LIR(ir()->linear_scan_order());
3209     tty->cr();
3210   }
3211 
3212   if (level == 1 && PrintCFGToFile) {
3213     CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3214   }
3215 }
3216 
3217 void LinearScan::print_reg_num(outputStream* out, int reg_num) {
3218   if (reg_num == -1) {
3219     out->print("[ANY]");
3220     return;
3221   } else if (reg_num >= LIR_OprDesc::vreg_base) {
3222     out->print("[VREG %d]", reg_num);
3223     return;
3224   }
3225 
3226   LIR_Opr opr = get_operand(reg_num);
3227   assert(opr->is_valid(), "unknown register");
3228   opr->print(out);
3229 }
3230 
3231 LIR_Opr LinearScan::get_operand(int reg_num) {
3232   LIR_Opr opr = LIR_OprFact::illegal();
3233 
3234 #ifdef X86
3235   int last_xmm_reg = pd_last_xmm_reg;
3236 #ifdef _LP64
3237   if (UseAVX < 3) {
3238     last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
3239   }
3240 #endif
3241 #endif
3242   if (reg_num >= pd_first_cpu_reg && reg_num <= pd_last_cpu_reg) {
3243     opr = LIR_OprFact::single_cpu(reg_num);
3244   } else if (reg_num >= pd_first_fpu_reg && reg_num <= pd_last_fpu_reg) {
3245     opr = LIR_OprFact::single_fpu(reg_num - pd_first_fpu_reg);
3246 #ifdef X86
3247   } else if (reg_num >= pd_first_xmm_reg && reg_num <= last_xmm_reg) {
3248     opr = LIR_OprFact::single_xmm(reg_num - pd_first_xmm_reg);
3249 #endif
3250   } else {
3251     // reg_num == -1 or a virtual register, return the illegal operand
3252   }
3253   return opr;
3254 }
3255 
3256 Interval* LinearScan::find_interval_at(int reg_num) const {
3257   if (reg_num < 0 || reg_num >= _intervals.length()) {
3258     return NULL;
3259   }
3260   return interval_at(reg_num);
3261 }
3262 
3263 #endif // PRODUCT
3264 
3265 
3266 // ********** verification functions for allocation
3267 // (check that all intervals have a correct register and that no registers are overwritten)
3268 #ifdef ASSERT
3269 
3270 void LinearScan::verify() {
3271   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3272   verify_intervals();
3273 
3274   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3275   verify_no_oops_in_fixed_intervals();
3276 
3277   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3278   verify_constants();
3279 
3280   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3281   verify_registers();
3282 
3283   TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3284 }
3285 
3286 void LinearScan::verify_intervals() {
3287   int len = interval_count();
3288   bool has_error = false;
3289 
3290   for (int i = 0; i < len; i++) {
3291     Interval* i1 = interval_at(i);
3292     if (i1 == NULL) continue;
3293 
3294     i1->check_split_children();
3295 
3296     if (i1->reg_num() != i) {
3297       tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3298       has_error = true;
3299     }
3300 
3301     if (i1->reg_num() >= LIR_OprDesc::vreg_base && i1->type() == T_ILLEGAL) {
3302       tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3303       has_error = true;
3304     }
3305 
3306     if (i1->assigned_reg() == any_reg) {
3307       tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3308       has_error = true;
3309     }
3310 
3311     if (i1->assigned_reg() == i1->assigned_regHi()) {
3312       tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3313       has_error = true;
3314     }
3315 
3316     if (!is_processed_reg_num(i1->assigned_reg())) {
3317       tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3318       has_error = true;
3319     }
3320 
3321     // special intervals that are created in MoveResolver
3322     // -> ignore them because the range information has no meaning there
3323     if (i1->from() == 1 && i1->to() == 2) continue;
3324 
3325     if (i1->first() == Range::end()) {
3326       tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3327       has_error = true;
3328     }
3329 
3330     for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3331       if (r->from() >= r->to()) {
3332         tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3333         has_error = true;
3334       }
3335     }
3336 
3337     for (int j = i + 1; j < len; j++) {
3338       Interval* i2 = interval_at(j);
3339       if (i2 == NULL || (i2->from() == 1 && i2->to() == 2)) continue;
3340 
3341       int r1 = i1->assigned_reg();
3342       int r1Hi = i1->assigned_regHi();
3343       int r2 = i2->assigned_reg();
3344       int r2Hi = i2->assigned_regHi();
3345       if ((r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi))) && i1->intersects(i2)) {
3346         tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3347         i1->print(); tty->cr();
3348         i2->print(); tty->cr();
3349         has_error = true;
3350       }
3351     }
3352   }
3353 
3354   assert(has_error == false, "register allocation invalid");
3355 }
3356 
3357 
3358 void LinearScan::verify_no_oops_in_fixed_intervals() {
3359   Interval* fixed_intervals;
3360   Interval* other_intervals;
3361   create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3362 
3363   // to ensure a walking until the last instruction id, add a dummy interval
3364   // with a high operation id
3365   other_intervals = new Interval(any_reg);
3366   other_intervals->add_range(max_jint - 2, max_jint - 1);
3367   IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3368 
3369   LIR_OpVisitState visitor;
3370   for (int i = 0; i < block_count(); i++) {
3371     BlockBegin* block = block_at(i);
3372 
3373     LIR_OpList* instructions = block->lir()->instructions_list();
3374 
3375     for (int j = 0; j < instructions->length(); j++) {
3376       LIR_Op* op = instructions->at(j);
3377       int op_id = op->id();
3378 
3379       visitor.visit(op);
3380 
3381       if (visitor.info_count() > 0) {
3382         iw->walk_before(op->id());
3383         bool check_live = true;
3384         if (op->code() == lir_move) {
3385           LIR_Op1* move = (LIR_Op1*)op;
3386           check_live = (move->patch_code() == lir_patch_none);
3387         }
3388         LIR_OpBranch* branch = op->as_OpBranch();
3389         if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3390           // Don't bother checking the stub in this case since the
3391           // exception stub will never return to normal control flow.
3392           check_live = false;
3393         }
3394 
3395         // Make sure none of the fixed registers is live across an
3396         // oopmap since we can't handle that correctly.
3397         if (check_live) {
3398           for (Interval* interval = iw->active_first(fixedKind);
3399                interval != Interval::end();
3400                interval = interval->next()) {
3401             if (interval->current_to() > op->id() + 1) {
3402               // This interval is live out of this op so make sure
3403               // that this interval represents some value that's
3404               // referenced by this op either as an input or output.
3405               bool ok = false;
3406               for_each_visitor_mode(mode) {
3407                 int n = visitor.opr_count(mode);
3408                 for (int k = 0; k < n; k++) {
3409                   LIR_Opr opr = visitor.opr_at(mode, k);
3410                   if (opr->is_fixed_cpu()) {
3411                     if (interval_at(reg_num(opr)) == interval) {
3412                       ok = true;
3413                       break;
3414                     }
3415                     int hi = reg_numHi(opr);
3416                     if (hi != -1 && interval_at(hi) == interval) {
3417                       ok = true;
3418                       break;
3419                     }
3420                   }
3421                 }
3422               }
3423               assert(ok, "fixed intervals should never be live across an oopmap point");
3424             }
3425           }
3426         }
3427       }
3428 
3429       // oop-maps at calls do not contain registers, so check is not needed
3430       if (!visitor.has_call()) {
3431 
3432         for_each_visitor_mode(mode) {
3433           int n = visitor.opr_count(mode);
3434           for (int k = 0; k < n; k++) {
3435             LIR_Opr opr = visitor.opr_at(mode, k);
3436 
3437             if (opr->is_fixed_cpu() && opr->is_oop()) {
3438               // operand is a non-virtual cpu register and contains an oop
3439               TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3440 
3441               Interval* interval = interval_at(reg_num(opr));
3442               assert(interval != NULL, "no interval");
3443 
3444               if (mode == LIR_OpVisitState::inputMode) {
3445                 if (interval->to() >= op_id + 1) {
3446                   assert(interval->to() < op_id + 2 ||
3447                          interval->has_hole_between(op_id, op_id + 2),
3448                          "oop input operand live after instruction");
3449                 }
3450               } else if (mode == LIR_OpVisitState::outputMode) {
3451                 if (interval->from() <= op_id - 1) {
3452                   assert(interval->has_hole_between(op_id - 1, op_id),
3453                          "oop input operand live after instruction");
3454                 }
3455               }
3456             }
3457           }
3458         }
3459       }
3460     }
3461   }
3462 }
3463 
3464 
3465 void LinearScan::verify_constants() {
3466   int num_regs = num_virtual_regs();
3467   int size = live_set_size();
3468   int num_blocks = block_count();
3469 
3470   for (int i = 0; i < num_blocks; i++) {
3471     BlockBegin* block = block_at(i);
3472     ResourceBitMap live_at_edge = block->live_in();
3473 
3474     // visit all registers where the live_at_edge bit is set
3475     for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3476       TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3477 
3478       Value value = gen()->instruction_for_vreg(r);
3479 
3480       assert(value != NULL, "all intervals live across block boundaries must have Value");
3481       assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3482       assert(value->operand()->vreg_number() == r, "register number must match");
3483       // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive accross block boundaries");
3484     }
3485   }
3486 }
3487 
3488 
3489 class RegisterVerifier: public StackObj {
3490  private:
3491   LinearScan*   _allocator;
3492   BlockList     _work_list;      // all blocks that must be processed
3493   IntervalsList _saved_states;   // saved information of previous check
3494 
3495   // simplified access to methods of LinearScan
3496   Compilation*  compilation() const              { return _allocator->compilation(); }
3497   Interval*     interval_at(int reg_num) const   { return _allocator->interval_at(reg_num); }
3498   int           reg_num(LIR_Opr opr) const       { return _allocator->reg_num(opr); }
3499 
3500   // currently, only registers are processed
3501   int           state_size()                     { return LinearScan::nof_regs; }
3502 
3503   // accessors
3504   IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3505   void          set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3506   void          add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3507 
3508   // helper functions
3509   IntervalList* copy(IntervalList* input_state);
3510   void          state_put(IntervalList* input_state, int reg, Interval* interval);
3511   bool          check_state(IntervalList* input_state, int reg, Interval* interval);
3512 
3513   void process_block(BlockBegin* block);
3514   void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3515   void process_successor(BlockBegin* block, IntervalList* input_state);
3516   void process_operations(LIR_List* ops, IntervalList* input_state);
3517 
3518  public:
3519   RegisterVerifier(LinearScan* allocator)
3520     : _allocator(allocator)
3521     , _work_list(16)
3522     , _saved_states(BlockBegin::number_of_blocks(), BlockBegin::number_of_blocks(), NULL)
3523   { }
3524 
3525   void verify(BlockBegin* start);
3526 };
3527 
3528 
3529 // entry function from LinearScan that starts the verification
3530 void LinearScan::verify_registers() {
3531   RegisterVerifier verifier(this);
3532   verifier.verify(block_at(0));
3533 }
3534 
3535 
3536 void RegisterVerifier::verify(BlockBegin* start) {
3537   // setup input registers (method arguments) for first block
3538   int input_state_len = state_size();
3539   IntervalList* input_state = new IntervalList(input_state_len, input_state_len, NULL);
3540   CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3541   for (int n = 0; n < args->length(); n++) {
3542     LIR_Opr opr = args->at(n);
3543     if (opr->is_register()) {
3544       Interval* interval = interval_at(reg_num(opr));
3545 
3546       if (interval->assigned_reg() < state_size()) {
3547         input_state->at_put(interval->assigned_reg(), interval);
3548       }
3549       if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3550         input_state->at_put(interval->assigned_regHi(), interval);
3551       }
3552     }
3553   }
3554 
3555   set_state_for_block(start, input_state);
3556   add_to_work_list(start);
3557 
3558   // main loop for verification
3559   do {
3560     BlockBegin* block = _work_list.at(0);
3561     _work_list.remove_at(0);
3562 
3563     process_block(block);
3564   } while (!_work_list.is_empty());
3565 }
3566 
3567 void RegisterVerifier::process_block(BlockBegin* block) {
3568   TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3569 
3570   // must copy state because it is modified
3571   IntervalList* input_state = copy(state_for_block(block));
3572 
3573   if (TraceLinearScanLevel >= 4) {
3574     tty->print_cr("Input-State of intervals:");
3575     tty->print("    ");
3576     for (int i = 0; i < state_size(); i++) {
3577       if (input_state->at(i) != NULL) {
3578         tty->print(" %4d", input_state->at(i)->reg_num());
3579       } else {
3580         tty->print("   __");
3581       }
3582     }
3583     tty->cr();
3584     tty->cr();
3585   }
3586 
3587   // process all operations of the block
3588   process_operations(block->lir(), input_state);
3589 
3590   // iterate all successors
3591   for (int i = 0; i < block->number_of_sux(); i++) {
3592     process_successor(block->sux_at(i), input_state);
3593   }
3594 }
3595 
3596 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3597   TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3598 
3599   // must copy state because it is modified
3600   input_state = copy(input_state);
3601 
3602   if (xhandler->entry_code() != NULL) {
3603     process_operations(xhandler->entry_code(), input_state);
3604   }
3605   process_successor(xhandler->entry_block(), input_state);
3606 }
3607 
3608 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3609   IntervalList* saved_state = state_for_block(block);
3610 
3611   if (saved_state != NULL) {
3612     // this block was already processed before.
3613     // check if new input_state is consistent with saved_state
3614 
3615     bool saved_state_correct = true;
3616     for (int i = 0; i < state_size(); i++) {
3617       if (input_state->at(i) != saved_state->at(i)) {
3618         // current input_state and previous saved_state assume a different
3619         // interval in this register -> assume that this register is invalid
3620         if (saved_state->at(i) != NULL) {
3621           // invalidate old calculation only if it assumed that
3622           // register was valid. when the register was already invalid,
3623           // then the old calculation was correct.
3624           saved_state_correct = false;
3625           saved_state->at_put(i, NULL);
3626 
3627           TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3628         }
3629       }
3630     }
3631 
3632     if (saved_state_correct) {
3633       // already processed block with correct input_state
3634       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3635     } else {
3636       // must re-visit this block
3637       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3638       add_to_work_list(block);
3639     }
3640 
3641   } else {
3642     // block was not processed before, so set initial input_state
3643     TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3644 
3645     set_state_for_block(block, copy(input_state));
3646     add_to_work_list(block);
3647   }
3648 }
3649 
3650 
3651 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3652   IntervalList* copy_state = new IntervalList(input_state->length());
3653   copy_state->appendAll(input_state);
3654   return copy_state;
3655 }
3656 
3657 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3658   if (reg != LinearScan::any_reg && reg < state_size()) {
3659     if (interval != NULL) {
3660       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = %d", reg, interval->reg_num()));
3661     } else if (input_state->at(reg) != NULL) {
3662       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = NULL", reg));
3663     }
3664 
3665     input_state->at_put(reg, interval);
3666   }
3667 }
3668 
3669 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3670   if (reg != LinearScan::any_reg && reg < state_size()) {
3671     if (input_state->at(reg) != interval) {
3672       tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3673       return true;
3674     }
3675   }
3676   return false;
3677 }
3678 
3679 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3680   // visit all instructions of the block
3681   LIR_OpVisitState visitor;
3682   bool has_error = false;
3683 
3684   for (int i = 0; i < ops->length(); i++) {
3685     LIR_Op* op = ops->at(i);
3686     visitor.visit(op);
3687 
3688     TRACE_LINEAR_SCAN(4, op->print_on(tty));
3689 
3690     // check if input operands are correct
3691     int j;
3692     int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3693     for (j = 0; j < n; j++) {
3694       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3695       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3696         Interval* interval = interval_at(reg_num(opr));
3697         if (op->id() != -1) {
3698           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3699         }
3700 
3701         has_error |= check_state(input_state, interval->assigned_reg(),   interval->split_parent());
3702         has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3703 
3704         // When an operand is marked with is_last_use, then the fpu stack allocator
3705         // removes the register from the fpu stack -> the register contains no value
3706         if (opr->is_last_use()) {
3707           state_put(input_state, interval->assigned_reg(),   NULL);
3708           state_put(input_state, interval->assigned_regHi(), NULL);
3709         }
3710       }
3711     }
3712 
3713     // invalidate all caller save registers at calls
3714     if (visitor.has_call()) {
3715       for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3716         state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3717       }
3718       for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3719         state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3720       }
3721 
3722 #ifdef X86
3723       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
3724       for (j = 0; j < num_caller_save_xmm_regs; j++) {
3725         state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3726       }
3727 #endif
3728     }
3729 
3730     // process xhandler before output and temp operands
3731     XHandlers* xhandlers = visitor.all_xhandler();
3732     n = xhandlers->length();
3733     for (int k = 0; k < n; k++) {
3734       process_xhandler(xhandlers->handler_at(k), input_state);
3735     }
3736 
3737     // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3738     n = visitor.opr_count(LIR_OpVisitState::tempMode);
3739     for (j = 0; j < n; j++) {
3740       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3741       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3742         Interval* interval = interval_at(reg_num(opr));
3743         if (op->id() != -1) {
3744           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3745         }
3746 
3747         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3748         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3749       }
3750     }
3751 
3752     // set output operands
3753     n = visitor.opr_count(LIR_OpVisitState::outputMode);
3754     for (j = 0; j < n; j++) {
3755       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3756       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3757         Interval* interval = interval_at(reg_num(opr));
3758         if (op->id() != -1) {
3759           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3760         }
3761 
3762         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3763         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3764       }
3765     }
3766   }
3767   assert(has_error == false, "Error in register allocation");
3768 }
3769 
3770 #endif // ASSERT
3771 
3772 
3773 
3774 // **** Implementation of MoveResolver ******************************
3775 
3776 MoveResolver::MoveResolver(LinearScan* allocator) :
3777   _allocator(allocator),
3778   _insert_list(NULL),
3779   _insert_idx(-1),
3780   _insertion_buffer(),
3781   _mapping_from(8),
3782   _mapping_from_opr(8),
3783   _mapping_to(8),
3784   _multiple_reads_allowed(false)
3785 {
3786   for (int i = 0; i < LinearScan::nof_regs; i++) {
3787     _register_blocked[i] = 0;
3788   }
3789   DEBUG_ONLY(check_empty());
3790 }
3791 
3792 
3793 #ifdef ASSERT
3794 
3795 void MoveResolver::check_empty() {
3796   assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3797   for (int i = 0; i < LinearScan::nof_regs; i++) {
3798     assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3799   }
3800   assert(_multiple_reads_allowed == false, "must have default value");
3801 }
3802 
3803 void MoveResolver::verify_before_resolve() {
3804   assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3805   assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3806   assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3807 
3808   int i, j;
3809   if (!_multiple_reads_allowed) {
3810     for (i = 0; i < _mapping_from.length(); i++) {
3811       for (j = i + 1; j < _mapping_from.length(); j++) {
3812         assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3813       }
3814     }
3815   }
3816 
3817   for (i = 0; i < _mapping_to.length(); i++) {
3818     for (j = i + 1; j < _mapping_to.length(); j++) {
3819       assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3820     }
3821   }
3822 
3823 
3824   ResourceBitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3825   if (!_multiple_reads_allowed) {
3826     for (i = 0; i < _mapping_from.length(); i++) {
3827       Interval* it = _mapping_from.at(i);
3828       if (it != NULL) {
3829         assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3830         used_regs.set_bit(it->assigned_reg());
3831 
3832         if (it->assigned_regHi() != LinearScan::any_reg) {
3833           assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3834           used_regs.set_bit(it->assigned_regHi());
3835         }
3836       }
3837     }
3838   }
3839 
3840   used_regs.clear();
3841   for (i = 0; i < _mapping_to.length(); i++) {
3842     Interval* it = _mapping_to.at(i);
3843     assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3844     used_regs.set_bit(it->assigned_reg());
3845 
3846     if (it->assigned_regHi() != LinearScan::any_reg) {
3847       assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3848       used_regs.set_bit(it->assigned_regHi());
3849     }
3850   }
3851 
3852   used_regs.clear();
3853   for (i = 0; i < _mapping_from.length(); i++) {
3854     Interval* it = _mapping_from.at(i);
3855     if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3856       used_regs.set_bit(it->assigned_reg());
3857     }
3858   }
3859   for (i = 0; i < _mapping_to.length(); i++) {
3860     Interval* it = _mapping_to.at(i);
3861     assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3862   }
3863 }
3864 
3865 #endif // ASSERT
3866 
3867 
3868 // mark assigned_reg and assigned_regHi of the interval as blocked
3869 void MoveResolver::block_registers(Interval* it) {
3870   int reg = it->assigned_reg();
3871   if (reg < LinearScan::nof_regs) {
3872     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3873     set_register_blocked(reg, 1);
3874   }
3875   reg = it->assigned_regHi();
3876   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3877     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3878     set_register_blocked(reg, 1);
3879   }
3880 }
3881 
3882 // mark assigned_reg and assigned_regHi of the interval as unblocked
3883 void MoveResolver::unblock_registers(Interval* it) {
3884   int reg = it->assigned_reg();
3885   if (reg < LinearScan::nof_regs) {
3886     assert(register_blocked(reg) > 0, "register already marked as unused");
3887     set_register_blocked(reg, -1);
3888   }
3889   reg = it->assigned_regHi();
3890   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3891     assert(register_blocked(reg) > 0, "register already marked as unused");
3892     set_register_blocked(reg, -1);
3893   }
3894 }
3895 
3896 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3897 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3898   int from_reg = -1;
3899   int from_regHi = -1;
3900   if (from != NULL) {
3901     from_reg = from->assigned_reg();
3902     from_regHi = from->assigned_regHi();
3903   }
3904 
3905   int reg = to->assigned_reg();
3906   if (reg < LinearScan::nof_regs) {
3907     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3908       return false;
3909     }
3910   }
3911   reg = to->assigned_regHi();
3912   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3913     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3914       return false;
3915     }
3916   }
3917 
3918   return true;
3919 }
3920 
3921 
3922 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3923   assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3924   _insertion_buffer.init(list);
3925 }
3926 
3927 void MoveResolver::append_insertion_buffer() {
3928   if (_insertion_buffer.initialized()) {
3929     _insertion_buffer.lir_list()->append(&_insertion_buffer);
3930   }
3931   assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3932 
3933   _insert_list = NULL;
3934   _insert_idx = -1;
3935 }
3936 
3937 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3938   assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3939   assert(from_interval->type() == to_interval->type(), "move between different types");
3940   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3941   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3942 
3943   LIR_Opr from_opr = get_virtual_register(from_interval);
3944   LIR_Opr to_opr = get_virtual_register(to_interval);
3945 
3946   if (!_multiple_reads_allowed) {
3947     // the last_use flag is an optimization for FPU stack allocation. When the same
3948     // input interval is used in more than one move, then it is too difficult to determine
3949     // if this move is really the last use.
3950     from_opr = from_opr->make_last_use();
3951   }
3952   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3953 
3954   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3955 }
3956 
3957 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3958   assert(from_opr->type() == to_interval->type(), "move between different types");
3959   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3960   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3961 
3962   LIR_Opr to_opr = get_virtual_register(to_interval);
3963   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3964 
3965   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr("  to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3966 }
3967 
3968 LIR_Opr MoveResolver::get_virtual_register(Interval* interval) {
3969   // Add a little fudge factor for the bailout since the bailout is only checked periodically. This allows us to hand out
3970   // a few extra registers before we really run out which helps to avoid to trip over assertions.
3971   int reg_num = interval->reg_num();
3972   if (reg_num + 20 >= LIR_OprDesc::vreg_max) {
3973     _allocator->bailout("out of virtual registers in linear scan");
3974     if (reg_num + 2 >= LIR_OprDesc::vreg_max) {
3975       // Wrap it around and continue until bailout really happens to avoid hitting assertions.
3976       reg_num = LIR_OprDesc::vreg_base;
3977     }
3978   }
3979   LIR_Opr vreg = LIR_OprFact::virtual_register(reg_num, interval->type());
3980   assert(vreg != LIR_OprFact::illegal(), "ran out of virtual registers");
3981   return vreg;
3982 }
3983 
3984 void MoveResolver::resolve_mappings() {
3985   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3986   DEBUG_ONLY(verify_before_resolve());
3987 
3988   // Block all registers that are used as input operands of a move.
3989   // When a register is blocked, no move to this register is emitted.
3990   // This is necessary for detecting cycles in moves.
3991   int i;
3992   for (i = _mapping_from.length() - 1; i >= 0; i--) {
3993     Interval* from_interval = _mapping_from.at(i);
3994     if (from_interval != NULL) {
3995       block_registers(from_interval);
3996     }
3997   }
3998 
3999   int spill_candidate = -1;
4000   while (_mapping_from.length() > 0) {
4001     bool processed_interval = false;
4002 
4003     for (i = _mapping_from.length() - 1; i >= 0; i--) {
4004       Interval* from_interval = _mapping_from.at(i);
4005       Interval* to_interval = _mapping_to.at(i);
4006 
4007       if (save_to_process_move(from_interval, to_interval)) {
4008         // this inverval can be processed because target is free
4009         if (from_interval != NULL) {
4010           insert_move(from_interval, to_interval);
4011           unblock_registers(from_interval);
4012         } else {
4013           insert_move(_mapping_from_opr.at(i), to_interval);
4014         }
4015         _mapping_from.remove_at(i);
4016         _mapping_from_opr.remove_at(i);
4017         _mapping_to.remove_at(i);
4018 
4019         processed_interval = true;
4020       } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
4021         // this interval cannot be processed now because target is not free
4022         // it starts in a register, so it is a possible candidate for spilling
4023         spill_candidate = i;
4024       }
4025     }
4026 
4027     if (!processed_interval) {
4028       // no move could be processed because there is a cycle in the move list
4029       // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
4030       guarantee(spill_candidate != -1, "no interval in register for spilling found");
4031 
4032       // create a new spill interval and assign a stack slot to it
4033       Interval* from_interval = _mapping_from.at(spill_candidate);
4034       Interval* spill_interval = new Interval(-1);
4035       spill_interval->set_type(from_interval->type());
4036 
4037       // add a dummy range because real position is difficult to calculate
4038       // Note: this range is a special case when the integrity of the allocation is checked
4039       spill_interval->add_range(1, 2);
4040 
4041       //       do not allocate a new spill slot for temporary interval, but
4042       //       use spill slot assigned to from_interval. Otherwise moves from
4043       //       one stack slot to another can happen (not allowed by LIR_Assembler
4044       int spill_slot = from_interval->canonical_spill_slot();
4045       if (spill_slot < 0) {
4046         spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
4047         from_interval->set_canonical_spill_slot(spill_slot);
4048       }
4049       spill_interval->assign_reg(spill_slot);
4050       allocator()->append_interval(spill_interval);
4051 
4052       TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
4053 
4054       // insert a move from register to stack and update the mapping
4055       insert_move(from_interval, spill_interval);
4056       _mapping_from.at_put(spill_candidate, spill_interval);
4057       unblock_registers(from_interval);
4058     }
4059   }
4060 
4061   // reset to default value
4062   _multiple_reads_allowed = false;
4063 
4064   // check that all intervals have been processed
4065   DEBUG_ONLY(check_empty());
4066 }
4067 
4068 
4069 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
4070   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4071   assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
4072 
4073   create_insertion_buffer(insert_list);
4074   _insert_list = insert_list;
4075   _insert_idx = insert_idx;
4076 }
4077 
4078 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
4079   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4080 
4081   if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
4082     // insert position changed -> resolve current mappings
4083     resolve_mappings();
4084   }
4085 
4086   if (insert_list != _insert_list) {
4087     // block changed -> append insertion_buffer because it is
4088     // bound to a specific block and create a new insertion_buffer
4089     append_insertion_buffer();
4090     create_insertion_buffer(insert_list);
4091   }
4092 
4093   _insert_list = insert_list;
4094   _insert_idx = insert_idx;
4095 }
4096 
4097 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
4098   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4099 
4100   _mapping_from.append(from_interval);
4101   _mapping_from_opr.append(LIR_OprFact::illegalOpr);
4102   _mapping_to.append(to_interval);
4103 }
4104 
4105 
4106 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
4107   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4108   assert(from_opr->is_constant(), "only for constants");
4109 
4110   _mapping_from.append(NULL);
4111   _mapping_from_opr.append(from_opr);
4112   _mapping_to.append(to_interval);
4113 }
4114 
4115 void MoveResolver::resolve_and_append_moves() {
4116   if (has_mappings()) {
4117     resolve_mappings();
4118   }
4119   append_insertion_buffer();
4120 }
4121 
4122 
4123 
4124 // **** Implementation of Range *************************************
4125 
4126 Range::Range(int from, int to, Range* next) :
4127   _from(from),
4128   _to(to),
4129   _next(next)
4130 {
4131 }
4132 
4133 // initialize sentinel
4134 Range* Range::_end = NULL;
4135 void Range::initialize(Arena* arena) {
4136   _end = new (arena) Range(max_jint, max_jint, NULL);
4137 }
4138 
4139 int Range::intersects_at(Range* r2) const {
4140   const Range* r1 = this;
4141 
4142   assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
4143   assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4144 
4145   do {
4146     if (r1->from() < r2->from()) {
4147       if (r1->to() <= r2->from()) {
4148         r1 = r1->next(); if (r1 == _end) return -1;
4149       } else {
4150         return r2->from();
4151       }
4152     } else if (r2->from() < r1->from()) {
4153       if (r2->to() <= r1->from()) {
4154         r2 = r2->next(); if (r2 == _end) return -1;
4155       } else {
4156         return r1->from();
4157       }
4158     } else { // r1->from() == r2->from()
4159       if (r1->from() == r1->to()) {
4160         r1 = r1->next(); if (r1 == _end) return -1;
4161       } else if (r2->from() == r2->to()) {
4162         r2 = r2->next(); if (r2 == _end) return -1;
4163       } else {
4164         return r1->from();
4165       }
4166     }
4167   } while (true);
4168 }
4169 
4170 #ifndef PRODUCT
4171 void Range::print(outputStream* out) const {
4172   out->print("[%d, %d[ ", _from, _to);
4173 }
4174 #endif
4175 
4176 
4177 
4178 // **** Implementation of Interval **********************************
4179 
4180 // initialize sentinel
4181 Interval* Interval::_end = NULL;
4182 void Interval::initialize(Arena* arena) {
4183   Range::initialize(arena);
4184   _end = new (arena) Interval(-1);
4185 }
4186 
4187 Interval::Interval(int reg_num) :
4188   _reg_num(reg_num),
4189   _type(T_ILLEGAL),
4190   _first(Range::end()),
4191   _use_pos_and_kinds(12),
4192   _current(Range::end()),
4193   _next(_end),
4194   _state(invalidState),
4195   _assigned_reg(LinearScan::any_reg),
4196   _assigned_regHi(LinearScan::any_reg),
4197   _cached_to(-1),
4198   _cached_opr(LIR_OprFact::illegalOpr),
4199   _cached_vm_reg(VMRegImpl::Bad()),
4200   _split_children(NULL),
4201   _canonical_spill_slot(-1),
4202   _insert_move_when_activated(false),
4203   _spill_state(noDefinitionFound),
4204   _spill_definition_pos(-1),
4205   _register_hint(NULL)
4206 {
4207   _split_parent = this;
4208   _current_split_child = this;
4209 }
4210 
4211 int Interval::calc_to() {
4212   assert(_first != Range::end(), "interval has no range");
4213 
4214   Range* r = _first;
4215   while (r->next() != Range::end()) {
4216     r = r->next();
4217   }
4218   return r->to();
4219 }
4220 
4221 
4222 #ifdef ASSERT
4223 // consistency check of split-children
4224 void Interval::check_split_children() {
4225   if (_split_children != NULL && _split_children->length() > 0) {
4226     assert(is_split_parent(), "only split parents can have children");
4227 
4228     for (int i = 0; i < _split_children->length(); i++) {
4229       Interval* i1 = _split_children->at(i);
4230 
4231       assert(i1->split_parent() == this, "not a split child of this interval");
4232       assert(i1->type() == type(), "must be equal for all split children");
4233       assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4234 
4235       for (int j = i + 1; j < _split_children->length(); j++) {
4236         Interval* i2 = _split_children->at(j);
4237 
4238         assert(i1->reg_num() != i2->reg_num(), "same register number");
4239 
4240         if (i1->from() < i2->from()) {
4241           assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4242         } else {
4243           assert(i2->from() < i1->from(), "intervals start at same op_id");
4244           assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4245         }
4246       }
4247     }
4248   }
4249 }
4250 #endif // ASSERT
4251 
4252 Interval* Interval::register_hint(bool search_split_child) const {
4253   if (!search_split_child) {
4254     return _register_hint;
4255   }
4256 
4257   if (_register_hint != NULL) {
4258     assert(_register_hint->is_split_parent(), "ony split parents are valid hint registers");
4259 
4260     if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4261       return _register_hint;
4262 
4263     } else if (_register_hint->_split_children != NULL && _register_hint->_split_children->length() > 0) {
4264       // search the first split child that has a register assigned
4265       int len = _register_hint->_split_children->length();
4266       for (int i = 0; i < len; i++) {
4267         Interval* cur = _register_hint->_split_children->at(i);
4268 
4269         if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4270           return cur;
4271         }
4272       }
4273     }
4274   }
4275 
4276   // no hint interval found that has a register assigned
4277   return NULL;
4278 }
4279 
4280 
4281 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4282   assert(is_split_parent(), "can only be called for split parents");
4283   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4284 
4285   Interval* result;
4286   if (_split_children == NULL || _split_children->length() == 0) {
4287     result = this;
4288   } else {
4289     result = NULL;
4290     int len = _split_children->length();
4291 
4292     // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4293     int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4294 
4295     int i;
4296     for (i = 0; i < len; i++) {
4297       Interval* cur = _split_children->at(i);
4298       if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4299         if (i > 0) {
4300           // exchange current split child to start of list (faster access for next call)
4301           _split_children->at_put(i, _split_children->at(0));
4302           _split_children->at_put(0, cur);
4303         }
4304 
4305         // interval found
4306         result = cur;
4307         break;
4308       }
4309     }
4310 
4311 #ifdef ASSERT
4312     for (i = 0; i < len; i++) {
4313       Interval* tmp = _split_children->at(i);
4314       if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4315         tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4316         result->print();
4317         tmp->print();
4318         assert(false, "two valid result intervals found");
4319       }
4320     }
4321 #endif
4322   }
4323 
4324   assert(result != NULL, "no matching interval found");
4325   assert(result->covers(op_id, mode), "op_id not covered by interval");
4326 
4327   return result;
4328 }
4329 
4330 
4331 // returns the last split child that ends before the given op_id
4332 Interval* Interval::split_child_before_op_id(int op_id) {
4333   assert(op_id >= 0, "invalid op_id");
4334 
4335   Interval* parent = split_parent();
4336   Interval* result = NULL;
4337 
4338   assert(parent->_split_children != NULL, "no split children available");
4339   int len = parent->_split_children->length();
4340   assert(len > 0, "no split children available");
4341 
4342   for (int i = len - 1; i >= 0; i--) {
4343     Interval* cur = parent->_split_children->at(i);
4344     if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4345       result = cur;
4346     }
4347   }
4348 
4349   assert(result != NULL, "no split child found");
4350   return result;
4351 }
4352 
4353 
4354 // Note: use positions are sorted descending -> first use has highest index
4355 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4356   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4357 
4358   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4359     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4360       return _use_pos_and_kinds.at(i);
4361     }
4362   }
4363   return max_jint;
4364 }
4365 
4366 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4367   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4368 
4369   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4370     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4371       return _use_pos_and_kinds.at(i);
4372     }
4373   }
4374   return max_jint;
4375 }
4376 
4377 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4378   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4379 
4380   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4381     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4382       return _use_pos_and_kinds.at(i);
4383     }
4384   }
4385   return max_jint;
4386 }
4387 
4388 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4389   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4390 
4391   int prev = 0;
4392   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4393     if (_use_pos_and_kinds.at(i) > from) {
4394       return prev;
4395     }
4396     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4397       prev = _use_pos_and_kinds.at(i);
4398     }
4399   }
4400   return prev;
4401 }
4402 
4403 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4404   assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4405 
4406   // do not add use positions for precolored intervals because
4407   // they are never used
4408   if (use_kind != noUse && reg_num() >= LIR_OprDesc::vreg_base) {
4409 #ifdef ASSERT
4410     assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4411     for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4412       assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4413       assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4414       if (i > 0) {
4415         assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4416       }
4417     }
4418 #endif
4419 
4420     // Note: add_use is called in descending order, so list gets sorted
4421     //       automatically by just appending new use positions
4422     int len = _use_pos_and_kinds.length();
4423     if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4424       _use_pos_and_kinds.append(pos);
4425       _use_pos_and_kinds.append(use_kind);
4426     } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4427       assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4428       _use_pos_and_kinds.at_put(len - 1, use_kind);
4429     }
4430   }
4431 }
4432 
4433 void Interval::add_range(int from, int to) {
4434   assert(from < to, "invalid range");
4435   assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4436   assert(from <= first()->to(), "not inserting at begin of interval");
4437 
4438   if (first()->from() <= to) {
4439     // join intersecting ranges
4440     first()->set_from(MIN2(from, first()->from()));
4441     first()->set_to  (MAX2(to,   first()->to()));
4442   } else {
4443     // insert new range
4444     _first = new Range(from, to, first());
4445   }
4446 }
4447 
4448 Interval* Interval::new_split_child() {
4449   // allocate new interval
4450   Interval* result = new Interval(-1);
4451   result->set_type(type());
4452 
4453   Interval* parent = split_parent();
4454   result->_split_parent = parent;
4455   result->set_register_hint(parent);
4456 
4457   // insert new interval in children-list of parent
4458   if (parent->_split_children == NULL) {
4459     assert(is_split_parent(), "list must be initialized at first split");
4460 
4461     parent->_split_children = new IntervalList(4);
4462     parent->_split_children->append(this);
4463   }
4464   parent->_split_children->append(result);
4465 
4466   return result;
4467 }
4468 
4469 // split this interval at the specified position and return
4470 // the remainder as a new interval.
4471 //
4472 // when an interval is split, a bi-directional link is established between the original interval
4473 // (the split parent) and the intervals that are split off this interval (the split children)
4474 // When a split child is split again, the new created interval is also a direct child
4475 // of the original parent (there is no tree of split children stored, but a flat list)
4476 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4477 //
4478 // Note: The new interval has no valid reg_num
4479 Interval* Interval::split(int split_pos) {
4480   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4481 
4482   // allocate new interval
4483   Interval* result = new_split_child();
4484 
4485   // split the ranges
4486   Range* prev = NULL;
4487   Range* cur = _first;
4488   while (cur != Range::end() && cur->to() <= split_pos) {
4489     prev = cur;
4490     cur = cur->next();
4491   }
4492   assert(cur != Range::end(), "split interval after end of last range");
4493 
4494   if (cur->from() < split_pos) {
4495     result->_first = new Range(split_pos, cur->to(), cur->next());
4496     cur->set_to(split_pos);
4497     cur->set_next(Range::end());
4498 
4499   } else {
4500     assert(prev != NULL, "split before start of first range");
4501     result->_first = cur;
4502     prev->set_next(Range::end());
4503   }
4504   result->_current = result->_first;
4505   _cached_to = -1; // clear cached value
4506 
4507   // split list of use positions
4508   int total_len = _use_pos_and_kinds.length();
4509   int start_idx = total_len - 2;
4510   while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4511     start_idx -= 2;
4512   }
4513 
4514   intStack new_use_pos_and_kinds(total_len - start_idx);
4515   int i;
4516   for (i = start_idx + 2; i < total_len; i++) {
4517     new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4518   }
4519 
4520   _use_pos_and_kinds.trunc_to(start_idx + 2);
4521   result->_use_pos_and_kinds = _use_pos_and_kinds;
4522   _use_pos_and_kinds = new_use_pos_and_kinds;
4523 
4524 #ifdef ASSERT
4525   assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4526   assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4527   assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4528 
4529   for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4530     assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4531     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4532   }
4533   for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4534     assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4535     assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4536   }
4537 #endif
4538 
4539   return result;
4540 }
4541 
4542 // split this interval at the specified position and return
4543 // the head as a new interval (the original interval is the tail)
4544 //
4545 // Currently, only the first range can be split, and the new interval
4546 // must not have split positions
4547 Interval* Interval::split_from_start(int split_pos) {
4548   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4549   assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4550   assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4551   assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4552 
4553   // allocate new interval
4554   Interval* result = new_split_child();
4555 
4556   // the new created interval has only one range (checked by assertion above),
4557   // so the splitting of the ranges is very simple
4558   result->add_range(_first->from(), split_pos);
4559 
4560   if (split_pos == _first->to()) {
4561     assert(_first->next() != Range::end(), "must not be at end");
4562     _first = _first->next();
4563   } else {
4564     _first->set_from(split_pos);
4565   }
4566 
4567   return result;
4568 }
4569 
4570 
4571 // returns true if the op_id is inside the interval
4572 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4573   Range* cur  = _first;
4574 
4575   while (cur != Range::end() && cur->to() < op_id) {
4576     cur = cur->next();
4577   }
4578   if (cur != Range::end()) {
4579     assert(cur->to() != cur->next()->from(), "ranges not separated");
4580 
4581     if (mode == LIR_OpVisitState::outputMode) {
4582       return cur->from() <= op_id && op_id < cur->to();
4583     } else {
4584       return cur->from() <= op_id && op_id <= cur->to();
4585     }
4586   }
4587   return false;
4588 }
4589 
4590 // returns true if the interval has any hole between hole_from and hole_to
4591 // (even if the hole has only the length 1)
4592 bool Interval::has_hole_between(int hole_from, int hole_to) {
4593   assert(hole_from < hole_to, "check");
4594   assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4595 
4596   Range* cur  = _first;
4597   while (cur != Range::end()) {
4598     assert(cur->to() < cur->next()->from(), "no space between ranges");
4599 
4600     // hole-range starts before this range -> hole
4601     if (hole_from < cur->from()) {
4602       return true;
4603 
4604     // hole-range completely inside this range -> no hole
4605     } else if (hole_to <= cur->to()) {
4606       return false;
4607 
4608     // overlapping of hole-range with this range -> hole
4609     } else if (hole_from <= cur->to()) {
4610       return true;
4611     }
4612 
4613     cur = cur->next();
4614   }
4615 
4616   return false;
4617 }
4618 
4619 // Check if there is an intersection with any of the split children of 'interval'
4620 bool Interval::intersects_any_children_of(Interval* interval) const {
4621   if (interval->_split_children != NULL) {
4622     for (int i = 0; i < interval->_split_children->length(); i++) {
4623       if (intersects(interval->_split_children->at(i))) {
4624         return true;
4625       }
4626     }
4627   }
4628   return false;
4629 }
4630 
4631 
4632 #ifndef PRODUCT
4633 void Interval::print_on(outputStream* out, bool is_cfg_printer) const {
4634   const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4635   const char* UseKind2Name[] = { "N", "L", "S", "M" };
4636 
4637   const char* type_name;
4638   if (reg_num() < LIR_OprDesc::vreg_base) {
4639     type_name = "fixed";
4640   } else {
4641     type_name = type2name(type());
4642   }
4643   out->print("%d %s ", reg_num(), type_name);
4644 
4645   if (is_cfg_printer) {
4646     // Special version for compatibility with C1 Visualizer.
4647     LIR_Opr opr = LinearScan::get_operand(reg_num());
4648     if (opr->is_valid()) {
4649       out->print("\"");
4650       opr->print(out);
4651       out->print("\" ");
4652     }
4653   } else {
4654     // Improved output for normal debugging.
4655     if (reg_num() < LIR_OprDesc::vreg_base) {
4656       LinearScan::print_reg_num(out, assigned_reg());
4657     } else if (assigned_reg() != -1 && (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4658       LinearScan::calc_operand_for_interval(this)->print(out);
4659     } else {
4660       // Virtual register that has no assigned register yet.
4661       out->print("[ANY]");
4662     }
4663     out->print(" ");
4664   }
4665   out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4666 
4667   // print ranges
4668   Range* cur = _first;
4669   while (cur != Range::end()) {
4670     cur->print(out);
4671     cur = cur->next();
4672     assert(cur != NULL, "range list not closed with range sentinel");
4673   }
4674 
4675   // print use positions
4676   int prev = 0;
4677   assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4678   for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4679     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4680     assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4681 
4682     out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4683     prev = _use_pos_and_kinds.at(i);
4684   }
4685 
4686   out->print(" \"%s\"", SpillState2Name[spill_state()]);
4687   out->cr();
4688 }
4689 
4690 void Interval::print_parent() const {
4691   if (_split_parent != this) {
4692     _split_parent->print_on(tty);
4693   } else {
4694     tty->print_cr("Parent: this");
4695   }
4696 }
4697 
4698 void Interval::print_children() const {
4699   if (_split_children == NULL) {
4700     tty->print_cr("Children: []");
4701   } else {
4702     tty->print_cr("Children:");
4703     for (int i = 0; i < _split_children->length(); i++) {
4704       tty->print("%d: ", i);
4705       _split_children->at(i)->print_on(tty);
4706     }
4707   }
4708 }
4709 #endif // NOT PRODUCT
4710 
4711 
4712 
4713 
4714 // **** Implementation of IntervalWalker ****************************
4715 
4716 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4717  : _compilation(allocator->compilation())
4718  , _allocator(allocator)
4719 {
4720   _unhandled_first[fixedKind] = unhandled_fixed_first;
4721   _unhandled_first[anyKind]   = unhandled_any_first;
4722   _active_first[fixedKind]    = Interval::end();
4723   _inactive_first[fixedKind]  = Interval::end();
4724   _active_first[anyKind]      = Interval::end();
4725   _inactive_first[anyKind]    = Interval::end();
4726   _current_position = -1;
4727   _current = NULL;
4728   next_interval();
4729 }
4730 
4731 
4732 // append interval in order of current range from()
4733 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4734   Interval* prev = NULL;
4735   Interval* cur  = *list;
4736   while (cur->current_from() < interval->current_from()) {
4737     prev = cur; cur = cur->next();
4738   }
4739   if (prev == NULL) {
4740     *list = interval;
4741   } else {
4742     prev->set_next(interval);
4743   }
4744   interval->set_next(cur);
4745 }
4746 
4747 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4748   assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4749 
4750   Interval* prev = NULL;
4751   Interval* cur  = *list;
4752   while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4753     prev = cur; cur = cur->next();
4754   }
4755   if (prev == NULL) {
4756     *list = interval;
4757   } else {
4758     prev->set_next(interval);
4759   }
4760   interval->set_next(cur);
4761 }
4762 
4763 
4764 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4765   while (*list != Interval::end() && *list != i) {
4766     list = (*list)->next_addr();
4767   }
4768   if (*list != Interval::end()) {
4769     assert(*list == i, "check");
4770     *list = (*list)->next();
4771     return true;
4772   } else {
4773     return false;
4774   }
4775 }
4776 
4777 void IntervalWalker::remove_from_list(Interval* i) {
4778   bool deleted;
4779 
4780   if (i->state() == activeState) {
4781     deleted = remove_from_list(active_first_addr(anyKind), i);
4782   } else {
4783     assert(i->state() == inactiveState, "invalid state");
4784     deleted = remove_from_list(inactive_first_addr(anyKind), i);
4785   }
4786 
4787   assert(deleted, "interval has not been found in list");
4788 }
4789 
4790 
4791 void IntervalWalker::walk_to(IntervalState state, int from) {
4792   assert (state == activeState || state == inactiveState, "wrong state");
4793   for_each_interval_kind(kind) {
4794     Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4795     Interval* next   = *prev;
4796     while (next->current_from() <= from) {
4797       Interval* cur = next;
4798       next = cur->next();
4799 
4800       bool range_has_changed = false;
4801       while (cur->current_to() <= from) {
4802         cur->next_range();
4803         range_has_changed = true;
4804       }
4805 
4806       // also handle move from inactive list to active list
4807       range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4808 
4809       if (range_has_changed) {
4810         // remove cur from list
4811         *prev = next;
4812         if (cur->current_at_end()) {
4813           // move to handled state (not maintained as a list)
4814           cur->set_state(handledState);
4815           DEBUG_ONLY(interval_moved(cur, kind, state, handledState);)
4816         } else if (cur->current_from() <= from){
4817           // sort into active list
4818           append_sorted(active_first_addr(kind), cur);
4819           cur->set_state(activeState);
4820           if (*prev == cur) {
4821             assert(state == activeState, "check");
4822             prev = cur->next_addr();
4823           }
4824           DEBUG_ONLY(interval_moved(cur, kind, state, activeState);)
4825         } else {
4826           // sort into inactive list
4827           append_sorted(inactive_first_addr(kind), cur);
4828           cur->set_state(inactiveState);
4829           if (*prev == cur) {
4830             assert(state == inactiveState, "check");
4831             prev = cur->next_addr();
4832           }
4833           DEBUG_ONLY(interval_moved(cur, kind, state, inactiveState);)
4834         }
4835       } else {
4836         prev = cur->next_addr();
4837         continue;
4838       }
4839     }
4840   }
4841 }
4842 
4843 
4844 void IntervalWalker::next_interval() {
4845   IntervalKind kind;
4846   Interval* any   = _unhandled_first[anyKind];
4847   Interval* fixed = _unhandled_first[fixedKind];
4848 
4849   if (any != Interval::end()) {
4850     // intervals may start at same position -> prefer fixed interval
4851     kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4852 
4853     assert (kind == fixedKind && fixed->from() <= any->from() ||
4854             kind == anyKind   && any->from() <= fixed->from(), "wrong interval!!!");
4855     assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4856 
4857   } else if (fixed != Interval::end()) {
4858     kind = fixedKind;
4859   } else {
4860     _current = NULL; return;
4861   }
4862   _current_kind = kind;
4863   _current = _unhandled_first[kind];
4864   _unhandled_first[kind] = _current->next();
4865   _current->set_next(Interval::end());
4866   _current->rewind_range();
4867 }
4868 
4869 
4870 void IntervalWalker::walk_to(int lir_op_id) {
4871   assert(_current_position <= lir_op_id, "can not walk backwards");
4872   while (current() != NULL) {
4873     bool is_active = current()->from() <= lir_op_id;
4874     int id = is_active ? current()->from() : lir_op_id;
4875 
4876     TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4877 
4878     // set _current_position prior to call of walk_to
4879     _current_position = id;
4880 
4881     // call walk_to even if _current_position == id
4882     walk_to(activeState, id);
4883     walk_to(inactiveState, id);
4884 
4885     if (is_active) {
4886       current()->set_state(activeState);
4887       if (activate_current()) {
4888         append_sorted(active_first_addr(current_kind()), current());
4889         DEBUG_ONLY(interval_moved(current(), current_kind(), unhandledState, activeState);)
4890       }
4891 
4892       next_interval();
4893     } else {
4894       return;
4895     }
4896   }
4897 }
4898 
4899 #ifdef ASSERT
4900 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4901   if (TraceLinearScanLevel >= 4) {
4902     #define print_state(state) \
4903     switch(state) {\
4904       case unhandledState: tty->print("unhandled"); break;\
4905       case activeState: tty->print("active"); break;\
4906       case inactiveState: tty->print("inactive"); break;\
4907       case handledState: tty->print("handled"); break;\
4908       default: ShouldNotReachHere(); \
4909     }
4910 
4911     print_state(from); tty->print(" to "); print_state(to);
4912     tty->fill_to(23);
4913     interval->print();
4914 
4915     #undef print_state
4916   }
4917 }
4918 #endif // ASSERT
4919 
4920 // **** Implementation of LinearScanWalker **************************
4921 
4922 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4923   : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4924   , _move_resolver(allocator)
4925 {
4926   for (int i = 0; i < LinearScan::nof_regs; i++) {
4927     _spill_intervals[i] = new IntervalList(2);
4928   }
4929 }
4930 
4931 
4932 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4933   for (int i = _first_reg; i <= _last_reg; i++) {
4934     _use_pos[i] = max_jint;
4935 
4936     if (!only_process_use_pos) {
4937       _block_pos[i] = max_jint;
4938       _spill_intervals[i]->clear();
4939     }
4940   }
4941 }
4942 
4943 inline void LinearScanWalker::exclude_from_use(int reg) {
4944   assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4945   if (reg >= _first_reg && reg <= _last_reg) {
4946     _use_pos[reg] = 0;
4947   }
4948 }
4949 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4950   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4951 
4952   exclude_from_use(i->assigned_reg());
4953   exclude_from_use(i->assigned_regHi());
4954 }
4955 
4956 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4957   assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4958 
4959   if (reg >= _first_reg && reg <= _last_reg) {
4960     if (_use_pos[reg] > use_pos) {
4961       _use_pos[reg] = use_pos;
4962     }
4963     if (!only_process_use_pos) {
4964       _spill_intervals[reg]->append(i);
4965     }
4966   }
4967 }
4968 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4969   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4970   if (use_pos != -1) {
4971     set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4972     set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4973   }
4974 }
4975 
4976 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4977   if (reg >= _first_reg && reg <= _last_reg) {
4978     if (_block_pos[reg] > block_pos) {
4979       _block_pos[reg] = block_pos;
4980     }
4981     if (_use_pos[reg] > block_pos) {
4982       _use_pos[reg] = block_pos;
4983     }
4984   }
4985 }
4986 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4987   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4988   if (block_pos != -1) {
4989     set_block_pos(i->assigned_reg(), i, block_pos);
4990     set_block_pos(i->assigned_regHi(), i, block_pos);
4991   }
4992 }
4993 
4994 
4995 void LinearScanWalker::free_exclude_active_fixed() {
4996   Interval* list = active_first(fixedKind);
4997   while (list != Interval::end()) {
4998     assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
4999     exclude_from_use(list);
5000     list = list->next();
5001   }
5002 }
5003 
5004 void LinearScanWalker::free_exclude_active_any() {
5005   Interval* list = active_first(anyKind);
5006   while (list != Interval::end()) {
5007     exclude_from_use(list);
5008     list = list->next();
5009   }
5010 }
5011 
5012 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
5013   Interval* list = inactive_first(fixedKind);
5014   while (list != Interval::end()) {
5015     if (cur->to() <= list->current_from()) {
5016       assert(list->current_intersects_at(cur) == -1, "must not intersect");
5017       set_use_pos(list, list->current_from(), true);
5018     } else {
5019       set_use_pos(list, list->current_intersects_at(cur), true);
5020     }
5021     list = list->next();
5022   }
5023 }
5024 
5025 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
5026   Interval* list = inactive_first(anyKind);
5027   while (list != Interval::end()) {
5028     set_use_pos(list, list->current_intersects_at(cur), true);
5029     list = list->next();
5030   }
5031 }
5032 
5033 void LinearScanWalker::spill_exclude_active_fixed() {
5034   Interval* list = active_first(fixedKind);
5035   while (list != Interval::end()) {
5036     exclude_from_use(list);
5037     list = list->next();
5038   }
5039 }
5040 
5041 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
5042   Interval* list = inactive_first(fixedKind);
5043   while (list != Interval::end()) {
5044     if (cur->to() > list->current_from()) {
5045       set_block_pos(list, list->current_intersects_at(cur));
5046     } else {
5047       assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
5048     }
5049 
5050     list = list->next();
5051   }
5052 }
5053 
5054 void LinearScanWalker::spill_collect_active_any() {
5055   Interval* list = active_first(anyKind);
5056   while (list != Interval::end()) {
5057     set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5058     list = list->next();
5059   }
5060 }
5061 
5062 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
5063   Interval* list = inactive_first(anyKind);
5064   while (list != Interval::end()) {
5065     if (list->current_intersects(cur)) {
5066       set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5067     }
5068     list = list->next();
5069   }
5070 }
5071 
5072 
5073 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
5074   // output all moves here. When source and target are equal, the move is
5075   // optimized away later in assign_reg_nums
5076 
5077   op_id = (op_id + 1) & ~1;
5078   BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
5079   assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
5080 
5081   // calculate index of instruction inside instruction list of current block
5082   // the minimal index (for a block with no spill moves) can be calculated because the
5083   // numbering of instructions is known.
5084   // When the block already contains spill moves, the index must be increased until the
5085   // correct index is reached.
5086   LIR_OpList* list = op_block->lir()->instructions_list();
5087   int index = (op_id - list->at(0)->id()) / 2;
5088   assert(list->at(index)->id() <= op_id, "error in calculation");
5089 
5090   while (list->at(index)->id() != op_id) {
5091     index++;
5092     assert(0 <= index && index < list->length(), "index out of bounds");
5093   }
5094   assert(1 <= index && index < list->length(), "index out of bounds");
5095   assert(list->at(index)->id() == op_id, "error in calculation");
5096 
5097   // insert new instruction before instruction at position index
5098   _move_resolver.move_insert_position(op_block->lir(), index - 1);
5099   _move_resolver.add_mapping(src_it, dst_it);
5100 }
5101 
5102 
5103 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
5104   int from_block_nr = min_block->linear_scan_number();
5105   int to_block_nr = max_block->linear_scan_number();
5106 
5107   assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
5108   assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
5109   assert(from_block_nr < to_block_nr, "must cross block boundary");
5110 
5111   // Try to split at end of max_block. If this would be after
5112   // max_split_pos, then use the begin of max_block
5113   int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
5114   if (optimal_split_pos > max_split_pos) {
5115     optimal_split_pos = max_block->first_lir_instruction_id();
5116   }
5117 
5118   int min_loop_depth = max_block->loop_depth();
5119   for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5120     BlockBegin* cur = block_at(i);
5121 
5122     if (cur->loop_depth() < min_loop_depth) {
5123       // block with lower loop-depth found -> split at the end of this block
5124       min_loop_depth = cur->loop_depth();
5125       optimal_split_pos = cur->last_lir_instruction_id() + 2;
5126     }
5127   }
5128   assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5129 
5130   return optimal_split_pos;
5131 }
5132 
5133 
5134 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5135   int optimal_split_pos = -1;
5136   if (min_split_pos == max_split_pos) {
5137     // trivial case, no optimization of split position possible
5138     TRACE_LINEAR_SCAN(4, tty->print_cr("      min-pos and max-pos are equal, no optimization possible"));
5139     optimal_split_pos = min_split_pos;
5140 
5141   } else {
5142     assert(min_split_pos < max_split_pos, "must be true then");
5143     assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5144 
5145     // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5146     // beginning of a block, then min_split_pos is also a possible split position.
5147     // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5148     BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5149 
5150     // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5151     // when an interval ends at the end of the last block of the method
5152     // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5153     // block at this op_id)
5154     BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5155 
5156     assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5157     if (min_block == max_block) {
5158       // split position cannot be moved to block boundary, so split as late as possible
5159       TRACE_LINEAR_SCAN(4, tty->print_cr("      cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5160       optimal_split_pos = max_split_pos;
5161 
5162     } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5163       // Do not move split position if the interval has a hole before max_split_pos.
5164       // Intervals resulting from Phi-Functions have more than one definition (marked
5165       // as mustHaveRegister) with a hole before each definition. When the register is needed
5166       // for the second definition, an earlier reloading is unnecessary.
5167       TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has hole just before max_split_pos, so splitting at max_split_pos"));
5168       optimal_split_pos = max_split_pos;
5169 
5170     } else {
5171       // seach optimal block boundary between min_split_pos and max_split_pos
5172       TRACE_LINEAR_SCAN(4, tty->print_cr("      moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5173 
5174       if (do_loop_optimization) {
5175         // Loop optimization: if a loop-end marker is found between min- and max-position,
5176         // then split before this loop
5177         int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5178         TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization: loop end found at pos %d", loop_end_pos));
5179 
5180         assert(loop_end_pos > min_split_pos, "invalid order");
5181         if (loop_end_pos < max_split_pos) {
5182           // loop-end marker found between min- and max-position
5183           // if it is not the end marker for the same loop as the min-position, then move
5184           // the max-position to this loop block.
5185           // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5186           // of the interval (normally, only mustHaveRegister causes a reloading)
5187           BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5188 
5189           TRACE_LINEAR_SCAN(4, tty->print_cr("      interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5190           assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5191 
5192           optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5193           if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5194             optimal_split_pos = -1;
5195             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization not necessary"));
5196           } else {
5197             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization successful"));
5198           }
5199         }
5200       }
5201 
5202       if (optimal_split_pos == -1) {
5203         // not calculated by loop optimization
5204         optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5205       }
5206     }
5207   }
5208   TRACE_LINEAR_SCAN(4, tty->print_cr("      optimal split position: %d", optimal_split_pos));
5209 
5210   return optimal_split_pos;
5211 }
5212 
5213 
5214 /*
5215   split an interval at the optimal position between min_split_pos and
5216   max_split_pos in two parts:
5217   1) the left part has already a location assigned
5218   2) the right part is sorted into to the unhandled-list
5219 */
5220 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5221   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting interval: "); it->print());
5222   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5223 
5224   assert(it->from() < min_split_pos,         "cannot split at start of interval");
5225   assert(current_position() < min_split_pos, "cannot split before current position");
5226   assert(min_split_pos <= max_split_pos,     "invalid order");
5227   assert(max_split_pos <= it->to(),          "cannot split after end of interval");
5228 
5229   int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5230 
5231   assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5232   assert(optimal_split_pos <= it->to(),  "cannot split after end of interval");
5233   assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5234 
5235   if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5236     // the split position would be just before the end of the interval
5237     // -> no split at all necessary
5238     TRACE_LINEAR_SCAN(4, tty->print_cr("      no split necessary because optimal split position is at end of interval"));
5239     return;
5240   }
5241 
5242   // must calculate this before the actual split is performed and before split position is moved to odd op_id
5243   bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5244 
5245   if (!allocator()->is_block_begin(optimal_split_pos)) {
5246     // move position before actual instruction (odd op_id)
5247     optimal_split_pos = (optimal_split_pos - 1) | 1;
5248   }
5249 
5250   TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5251   assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5252   assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5253 
5254   Interval* split_part = it->split(optimal_split_pos);
5255 
5256   allocator()->append_interval(split_part);
5257   allocator()->copy_register_flags(it, split_part);
5258   split_part->set_insert_move_when_activated(move_necessary);
5259   append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5260 
5261   TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5262   TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5263   TRACE_LINEAR_SCAN(2, tty->print   ("      "); split_part->print());
5264 }
5265 
5266 /*
5267   split an interval at the optimal position between min_split_pos and
5268   max_split_pos in two parts:
5269   1) the left part has already a location assigned
5270   2) the right part is always on the stack and therefore ignored in further processing
5271 */
5272 void LinearScanWalker::split_for_spilling(Interval* it) {
5273   // calculate allowed range of splitting position
5274   int max_split_pos = current_position();
5275   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5276 
5277   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting and spilling interval: "); it->print());
5278   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5279 
5280   assert(it->state() == activeState,     "why spill interval that is not active?");
5281   assert(it->from() <= min_split_pos,    "cannot split before start of interval");
5282   assert(min_split_pos <= max_split_pos, "invalid order");
5283   assert(max_split_pos < it->to(),       "cannot split at end end of interval");
5284   assert(current_position() < it->to(),  "interval must not end before current position");
5285 
5286   if (min_split_pos == it->from()) {
5287     // the whole interval is never used, so spill it entirely to memory
5288     TRACE_LINEAR_SCAN(2, tty->print_cr("      spilling entire interval because split pos is at beginning of interval"));
5289     assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5290 
5291     allocator()->assign_spill_slot(it);
5292     allocator()->change_spill_state(it, min_split_pos);
5293 
5294     // Also kick parent intervals out of register to memory when they have no use
5295     // position. This avoids short interval in register surrounded by intervals in
5296     // memory -> avoid useless moves from memory to register and back
5297     Interval* parent = it;
5298     while (parent != NULL && parent->is_split_child()) {
5299       parent = parent->split_child_before_op_id(parent->from());
5300 
5301       if (parent->assigned_reg() < LinearScan::nof_regs) {
5302         if (parent->first_usage(shouldHaveRegister) == max_jint) {
5303           // parent is never used, so kick it out of its assigned register
5304           TRACE_LINEAR_SCAN(4, tty->print_cr("      kicking out interval %d out of its register because it is never used", parent->reg_num()));
5305           allocator()->assign_spill_slot(parent);
5306         } else {
5307           // do not go further back because the register is actually used by the interval
5308           parent = NULL;
5309         }
5310       }
5311     }
5312 
5313   } else {
5314     // search optimal split pos, split interval and spill only the right hand part
5315     int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5316 
5317     assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5318     assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5319     assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5320 
5321     if (!allocator()->is_block_begin(optimal_split_pos)) {
5322       // move position before actual instruction (odd op_id)
5323       optimal_split_pos = (optimal_split_pos - 1) | 1;
5324     }
5325 
5326     TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5327     assert(allocator()->is_block_begin(optimal_split_pos)  || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5328     assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5329 
5330     Interval* spilled_part = it->split(optimal_split_pos);
5331     allocator()->append_interval(spilled_part);
5332     allocator()->assign_spill_slot(spilled_part);
5333     allocator()->change_spill_state(spilled_part, optimal_split_pos);
5334 
5335     if (!allocator()->is_block_begin(optimal_split_pos)) {
5336       TRACE_LINEAR_SCAN(4, tty->print_cr("      inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5337       insert_move(optimal_split_pos, it, spilled_part);
5338     }
5339 
5340     // the current_split_child is needed later when moves are inserted for reloading
5341     assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5342     spilled_part->make_current_split_child();
5343 
5344     TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts"));
5345     TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5346     TRACE_LINEAR_SCAN(2, tty->print   ("      "); spilled_part->print());
5347   }
5348 }
5349 
5350 
5351 void LinearScanWalker::split_stack_interval(Interval* it) {
5352   int min_split_pos = current_position() + 1;
5353   int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5354 
5355   split_before_usage(it, min_split_pos, max_split_pos);
5356 }
5357 
5358 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5359   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5360   int max_split_pos = register_available_until;
5361 
5362   split_before_usage(it, min_split_pos, max_split_pos);
5363 }
5364 
5365 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5366   assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5367 
5368   int current_pos = current_position();
5369   if (it->state() == inactiveState) {
5370     // the interval is currently inactive, so no spill slot is needed for now.
5371     // when the split part is activated, the interval has a new chance to get a register,
5372     // so in the best case no stack slot is necessary
5373     assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5374     split_before_usage(it, current_pos + 1, current_pos + 1);
5375 
5376   } else {
5377     // search the position where the interval must have a register and split
5378     // at the optimal position before.
5379     // The new created part is added to the unhandled list and will get a register
5380     // when it is activated
5381     int min_split_pos = current_pos + 1;
5382     int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5383 
5384     split_before_usage(it, min_split_pos, max_split_pos);
5385 
5386     assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5387     split_for_spilling(it);
5388   }
5389 }
5390 
5391 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5392   int min_full_reg = any_reg;
5393   int max_partial_reg = any_reg;
5394 
5395   for (int i = _first_reg; i <= _last_reg; i++) {
5396     if (i == ignore_reg) {
5397       // this register must be ignored
5398 
5399     } else if (_use_pos[i] >= interval_to) {
5400       // this register is free for the full interval
5401       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5402         min_full_reg = i;
5403       }
5404     } else if (_use_pos[i] > reg_needed_until) {
5405       // this register is at least free until reg_needed_until
5406       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5407         max_partial_reg = i;
5408       }
5409     }
5410   }
5411 
5412   if (min_full_reg != any_reg) {
5413     return min_full_reg;
5414   } else if (max_partial_reg != any_reg) {
5415     *need_split = true;
5416     return max_partial_reg;
5417   } else {
5418     return any_reg;
5419   }
5420 }
5421 
5422 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5423   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5424 
5425   int min_full_reg = any_reg;
5426   int max_partial_reg = any_reg;
5427 
5428   for (int i = _first_reg; i < _last_reg; i+=2) {
5429     if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5430       // this register is free for the full interval
5431       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5432         min_full_reg = i;
5433       }
5434     } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5435       // this register is at least free until reg_needed_until
5436       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5437         max_partial_reg = i;
5438       }
5439     }
5440   }
5441 
5442   if (min_full_reg != any_reg) {
5443     return min_full_reg;
5444   } else if (max_partial_reg != any_reg) {
5445     *need_split = true;
5446     return max_partial_reg;
5447   } else {
5448     return any_reg;
5449   }
5450 }
5451 
5452 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5453   TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5454 
5455   init_use_lists(true);
5456   free_exclude_active_fixed();
5457   free_exclude_active_any();
5458   free_collect_inactive_fixed(cur);
5459   free_collect_inactive_any(cur);
5460   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5461 
5462   // _use_pos contains the start of the next interval that has this register assigned
5463   // (either as a fixed register or a normal allocated register in the past)
5464   // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5465 #ifdef ASSERT
5466   if (TraceLinearScanLevel >= 4) {
5467     tty->print_cr("      state of registers:");
5468     for (int i = _first_reg; i <= _last_reg; i++) {
5469       tty->print("      reg %d (", i);
5470       LinearScan::print_reg_num(i);
5471       tty->print_cr("): use_pos: %d", _use_pos[i]);
5472     }
5473   }
5474 #endif
5475 
5476   int hint_reg, hint_regHi;
5477   Interval* register_hint = cur->register_hint();
5478   if (register_hint != NULL) {
5479     hint_reg = register_hint->assigned_reg();
5480     hint_regHi = register_hint->assigned_regHi();
5481 
5482     if (_num_phys_regs == 2 && allocator()->is_precolored_cpu_interval(register_hint)) {
5483       assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5484       hint_regHi = hint_reg + 1;  // connect e.g. eax-edx
5485     }
5486 #ifdef ASSERT
5487     if (TraceLinearScanLevel >= 4) {
5488       tty->print("      hint registers %d (", hint_reg);
5489       LinearScan::print_reg_num(hint_reg);
5490       tty->print("), %d (", hint_regHi);
5491       LinearScan::print_reg_num(hint_regHi);
5492       tty->print(") from interval ");
5493       register_hint->print();
5494     }
5495 #endif
5496   } else {
5497     hint_reg = any_reg;
5498     hint_regHi = any_reg;
5499   }
5500   assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5501   assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5502 
5503   // the register must be free at least until this position
5504   int reg_needed_until = cur->from() + 1;
5505   int interval_to = cur->to();
5506 
5507   bool need_split = false;
5508   int split_pos;
5509   int reg;
5510   int regHi = any_reg;
5511 
5512   if (_adjacent_regs) {
5513     reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5514     regHi = reg + 1;
5515     if (reg == any_reg) {
5516       return false;
5517     }
5518     split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5519 
5520   } else {
5521     reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5522     if (reg == any_reg) {
5523       return false;
5524     }
5525     split_pos = _use_pos[reg];
5526 
5527     if (_num_phys_regs == 2) {
5528       regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5529 
5530       if (_use_pos[reg] < interval_to && regHi == any_reg) {
5531         // do not split interval if only one register can be assigned until the split pos
5532         // (when one register is found for the whole interval, split&spill is only
5533         // performed for the hi register)
5534         return false;
5535 
5536       } else if (regHi != any_reg) {
5537         split_pos = MIN2(split_pos, _use_pos[regHi]);
5538 
5539         // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5540         if (reg > regHi) {
5541           int temp = reg;
5542           reg = regHi;
5543           regHi = temp;
5544         }
5545       }
5546     }
5547   }
5548 
5549   cur->assign_reg(reg, regHi);
5550 #ifdef ASSERT
5551   if (TraceLinearScanLevel >= 2) {
5552     tty->print("      selected registers %d (", reg);
5553     LinearScan::print_reg_num(reg);
5554     tty->print("), %d (", regHi);
5555     LinearScan::print_reg_num(regHi);
5556     tty->print_cr(")");
5557   }
5558 #endif
5559   assert(split_pos > 0, "invalid split_pos");
5560   if (need_split) {
5561     // register not available for full interval, so split it
5562     split_when_partial_register_available(cur, split_pos);
5563   }
5564 
5565   // only return true if interval is completely assigned
5566   return _num_phys_regs == 1 || regHi != any_reg;
5567 }
5568 
5569 
5570 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int ignore_reg, bool* need_split) {
5571   int max_reg = any_reg;
5572 
5573   for (int i = _first_reg; i <= _last_reg; i++) {
5574     if (i == ignore_reg) {
5575       // this register must be ignored
5576 
5577     } else if (_use_pos[i] > reg_needed_until) {
5578       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5579         max_reg = i;
5580       }
5581     }
5582   }
5583 
5584   if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5585     *need_split = true;
5586   }
5587 
5588   return max_reg;
5589 }
5590 
5591 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, bool* need_split) {
5592   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5593 
5594   int max_reg = any_reg;
5595 
5596   for (int i = _first_reg; i < _last_reg; i+=2) {
5597     if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5598       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5599         max_reg = i;
5600       }
5601     }
5602   }
5603 
5604   if (max_reg != any_reg &&
5605       (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to)) {
5606     *need_split = true;
5607   }
5608 
5609   return max_reg;
5610 }
5611 
5612 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5613   assert(reg != any_reg, "no register assigned");
5614 
5615   for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5616     Interval* it = _spill_intervals[reg]->at(i);
5617     remove_from_list(it);
5618     split_and_spill_interval(it);
5619   }
5620 
5621   if (regHi != any_reg) {
5622     IntervalList* processed = _spill_intervals[reg];
5623     for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5624       Interval* it = _spill_intervals[regHi]->at(i);
5625       if (processed->find(it) == -1) {
5626         remove_from_list(it);
5627         split_and_spill_interval(it);
5628       }
5629     }
5630   }
5631 }
5632 
5633 
5634 // Split an Interval and spill it to memory so that cur can be placed in a register
5635 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5636   TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5637 
5638   // collect current usage of registers
5639   init_use_lists(false);
5640   spill_exclude_active_fixed();
5641   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5642   spill_block_inactive_fixed(cur);
5643   spill_collect_active_any();
5644   spill_collect_inactive_any(cur);
5645 
5646 #ifdef ASSERT
5647   if (TraceLinearScanLevel >= 4) {
5648     tty->print_cr("      state of registers:");
5649     for (int i = _first_reg; i <= _last_reg; i++) {
5650       tty->print("      reg %d(", i);
5651       LinearScan::print_reg_num(i);
5652       tty->print("): use_pos: %d, block_pos: %d, intervals: ", _use_pos[i], _block_pos[i]);
5653       for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5654         tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5655       }
5656       tty->cr();
5657     }
5658   }
5659 #endif
5660 
5661   // the register must be free at least until this position
5662   int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5663   int interval_to = cur->to();
5664   assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5665 
5666   int split_pos = 0;
5667   int use_pos = 0;
5668   bool need_split = false;
5669   int reg, regHi;
5670 
5671   if (_adjacent_regs) {
5672     reg = find_locked_double_reg(reg_needed_until, interval_to, &need_split);
5673     regHi = reg + 1;
5674 
5675     if (reg != any_reg) {
5676       use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5677       split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5678     }
5679   } else {
5680     reg = find_locked_reg(reg_needed_until, interval_to, cur->assigned_reg(), &need_split);
5681     regHi = any_reg;
5682 
5683     if (reg != any_reg) {
5684       use_pos = _use_pos[reg];
5685       split_pos = _block_pos[reg];
5686 
5687       if (_num_phys_regs == 2) {
5688         if (cur->assigned_reg() != any_reg) {
5689           regHi = reg;
5690           reg = cur->assigned_reg();
5691         } else {
5692           regHi = find_locked_reg(reg_needed_until, interval_to, reg, &need_split);
5693           if (regHi != any_reg) {
5694             use_pos = MIN2(use_pos, _use_pos[regHi]);
5695             split_pos = MIN2(split_pos, _block_pos[regHi]);
5696           }
5697         }
5698 
5699         if (regHi != any_reg && reg > regHi) {
5700           // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5701           int temp = reg;
5702           reg = regHi;
5703           regHi = temp;
5704         }
5705       }
5706     }
5707   }
5708 
5709   if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5710     // the first use of cur is later than the spilling position -> spill cur
5711     TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5712 
5713     if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5714       assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5715       // assign a reasonable register and do a bailout in product mode to avoid errors
5716       allocator()->assign_spill_slot(cur);
5717       BAILOUT("LinearScan: no register found");
5718     }
5719 
5720     split_and_spill_interval(cur);
5721   } else {
5722 #ifdef ASSERT
5723     if (TraceLinearScanLevel >= 4) {
5724       tty->print("decided to use register %d (", reg);
5725       LinearScan::print_reg_num(reg);
5726       tty->print("), %d (", regHi);
5727       LinearScan::print_reg_num(regHi);
5728       tty->print_cr(")");
5729     }
5730 #endif
5731     assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5732     assert(split_pos > 0, "invalid split_pos");
5733     assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5734 
5735     cur->assign_reg(reg, regHi);
5736     if (need_split) {
5737       // register not available for full interval, so split it
5738       split_when_partial_register_available(cur, split_pos);
5739     }
5740 
5741     // perform splitting and spilling for all affected intervalls
5742     split_and_spill_intersecting_intervals(reg, regHi);
5743   }
5744 }
5745 
5746 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5747 #ifdef X86
5748   // fast calculation of intervals that can never get a register because the
5749   // the next instruction is a call that blocks all registers
5750   // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5751 
5752   // check if this interval is the result of a split operation
5753   // (an interval got a register until this position)
5754   int pos = cur->from();
5755   if ((pos & 1) == 1) {
5756     // the current instruction is a call that blocks all registers
5757     if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5758       TRACE_LINEAR_SCAN(4, tty->print_cr("      free register cannot be available because all registers blocked by following call"));
5759 
5760       // safety check that there is really no register available
5761       assert(alloc_free_reg(cur) == false, "found a register for this interval");
5762       return true;
5763     }
5764 
5765   }
5766 #endif
5767   return false;
5768 }
5769 
5770 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5771   BasicType type = cur->type();
5772   _num_phys_regs = LinearScan::num_physical_regs(type);
5773   _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5774 
5775   if (pd_init_regs_for_alloc(cur)) {
5776     // the appropriate register range was selected.
5777   } else if (type == T_FLOAT || type == T_DOUBLE) {
5778     _first_reg = pd_first_fpu_reg;
5779     _last_reg = pd_last_fpu_reg;
5780   } else {
5781     _first_reg = pd_first_cpu_reg;
5782     _last_reg = FrameMap::last_cpu_reg();
5783   }
5784 
5785   assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5786   assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5787 }
5788 
5789 
5790 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5791   if (op->code() != lir_move) {
5792     return false;
5793   }
5794   assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5795 
5796   LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5797   LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5798   return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5799 }
5800 
5801 // optimization (especially for phi functions of nested loops):
5802 // assign same spill slot to non-intersecting intervals
5803 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5804   if (cur->is_split_child()) {
5805     // optimization is only suitable for split parents
5806     return;
5807   }
5808 
5809   Interval* register_hint = cur->register_hint(false);
5810   if (register_hint == NULL) {
5811     // cur is not the target of a move, otherwise register_hint would be set
5812     return;
5813   }
5814   assert(register_hint->is_split_parent(), "register hint must be split parent");
5815 
5816   if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5817     // combining the stack slots for intervals where spill move optimization is applied
5818     // is not benefitial and would cause problems
5819     return;
5820   }
5821 
5822   int begin_pos = cur->from();
5823   int end_pos = cur->to();
5824   if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5825     // safety check that lir_op_with_id is allowed
5826     return;
5827   }
5828 
5829   if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5830     // cur and register_hint are not connected with two moves
5831     return;
5832   }
5833 
5834   Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5835   Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5836   if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5837     // register_hint must be split, otherwise the re-writing of use positions does not work
5838     return;
5839   }
5840 
5841   assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5842   assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5843   assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5844   assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5845 
5846   if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5847     // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5848     return;
5849   }
5850   assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5851   assert(!cur->intersects(register_hint), "cur should not intersect register_hint");
5852 
5853   if (cur->intersects_any_children_of(register_hint)) {
5854     // Bail out if cur intersects any split children of register_hint, which have the same spill slot as their parent. An overlap of two intervals with
5855     // the same spill slot could result in a situation where both intervals are spilled at the same time to the same stack location which is not correct.
5856     return;
5857   }
5858 
5859   // modify intervals such that cur gets the same stack slot as register_hint
5860   // delete use positions to prevent the intervals to get a register at beginning
5861   cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5862   cur->remove_first_use_pos();
5863   end_hint->remove_first_use_pos();
5864 }
5865 
5866 
5867 // allocate a physical register or memory location to an interval
5868 bool LinearScanWalker::activate_current() {
5869   Interval* cur = current();
5870   bool result = true;
5871 
5872   TRACE_LINEAR_SCAN(2, tty->print   ("+++++ activating interval "); cur->print());
5873   TRACE_LINEAR_SCAN(4, tty->print_cr("      split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5874 
5875   if (cur->assigned_reg() >= LinearScan::nof_regs) {
5876     // activating an interval that has a stack slot assigned -> split it at first use position
5877     // used for method parameters
5878     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has spill slot assigned (method parameter) -> split it before first use"));
5879 
5880     split_stack_interval(cur);
5881     result = false;
5882 
5883   } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5884     // activating an interval that must start in a stack slot, but may get a register later
5885     // used for lir_roundfp: rounding is done by store to stack and reload later
5886     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval must start in stack slot -> split it before first use"));
5887     assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5888 
5889     allocator()->assign_spill_slot(cur);
5890     split_stack_interval(cur);
5891     result = false;
5892 
5893   } else if (cur->assigned_reg() == any_reg) {
5894     // interval has not assigned register -> normal allocation
5895     // (this is the normal case for most intervals)
5896     TRACE_LINEAR_SCAN(4, tty->print_cr("      normal allocation of register"));
5897 
5898     // assign same spill slot to non-intersecting intervals
5899     combine_spilled_intervals(cur);
5900 
5901     init_vars_for_alloc(cur);
5902     if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5903       // no empty register available.
5904       // split and spill another interval so that this interval gets a register
5905       alloc_locked_reg(cur);
5906     }
5907 
5908     // spilled intervals need not be move to active-list
5909     if (cur->assigned_reg() >= LinearScan::nof_regs) {
5910       result = false;
5911     }
5912   }
5913 
5914   // load spilled values that become active from stack slot to register
5915   if (cur->insert_move_when_activated()) {
5916     assert(cur->is_split_child(), "must be");
5917     assert(cur->current_split_child() != NULL, "must be");
5918     assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5919     TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5920 
5921     insert_move(cur->from(), cur->current_split_child(), cur);
5922   }
5923   cur->make_current_split_child();
5924 
5925   return result; // true = interval is moved to active list
5926 }
5927 
5928 
5929 // Implementation of EdgeMoveOptimizer
5930 
5931 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5932   _edge_instructions(4),
5933   _edge_instructions_idx(4)
5934 {
5935 }
5936 
5937 void EdgeMoveOptimizer::optimize(BlockList* code) {
5938   EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5939 
5940   // ignore the first block in the list (index 0 is not processed)
5941   for (int i = code->length() - 1; i >= 1; i--) {
5942     BlockBegin* block = code->at(i);
5943 
5944     if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5945       optimizer.optimize_moves_at_block_end(block);
5946     }
5947     if (block->number_of_sux() == 2) {
5948       optimizer.optimize_moves_at_block_begin(block);
5949     }
5950   }
5951 }
5952 
5953 
5954 // clear all internal data structures
5955 void EdgeMoveOptimizer::init_instructions() {
5956   _edge_instructions.clear();
5957   _edge_instructions_idx.clear();
5958 }
5959 
5960 // append a lir-instruction-list and the index of the current operation in to the list
5961 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5962   _edge_instructions.append(instructions);
5963   _edge_instructions_idx.append(instructions_idx);
5964 }
5965 
5966 // return the current operation of the given edge (predecessor or successor)
5967 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5968   LIR_OpList* instructions = _edge_instructions.at(edge);
5969   int idx = _edge_instructions_idx.at(edge);
5970 
5971   if (idx < instructions->length()) {
5972     return instructions->at(idx);
5973   } else {
5974     return NULL;
5975   }
5976 }
5977 
5978 // removes the current operation of the given edge (predecessor or successor)
5979 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5980   LIR_OpList* instructions = _edge_instructions.at(edge);
5981   int idx = _edge_instructions_idx.at(edge);
5982   instructions->remove_at(idx);
5983 
5984   if (decrement_index) {
5985     _edge_instructions_idx.at_put(edge, idx - 1);
5986   }
5987 }
5988 
5989 
5990 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5991   if (op1 == NULL || op2 == NULL) {
5992     // at least one block is already empty -> no optimization possible
5993     return true;
5994   }
5995 
5996   if (op1->code() == lir_move && op2->code() == lir_move) {
5997     assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
5998     assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
5999     LIR_Op1* move1 = (LIR_Op1*)op1;
6000     LIR_Op1* move2 = (LIR_Op1*)op2;
6001     if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
6002       // these moves are exactly equal and can be optimized
6003       return false;
6004     }
6005 
6006   } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
6007     assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
6008     assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
6009     LIR_Op1* fxch1 = (LIR_Op1*)op1;
6010     LIR_Op1* fxch2 = (LIR_Op1*)op2;
6011     if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
6012       // equal FPU stack operations can be optimized
6013       return false;
6014     }
6015 
6016   } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
6017     // equal FPU stack operations can be optimized
6018     return false;
6019   }
6020 
6021   // no optimization possible
6022   return true;
6023 }
6024 
6025 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
6026   TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
6027 
6028   if (block->is_predecessor(block)) {
6029     // currently we can't handle this correctly.
6030     return;
6031   }
6032 
6033   init_instructions();
6034   int num_preds = block->number_of_preds();
6035   assert(num_preds > 1, "do not call otherwise");
6036   assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6037 
6038   // setup a list with the lir-instructions of all predecessors
6039   int i;
6040   for (i = 0; i < num_preds; i++) {
6041     BlockBegin* pred = block->pred_at(i);
6042     LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6043 
6044     if (pred->number_of_sux() != 1) {
6045       // this can happen with switch-statements where multiple edges are between
6046       // the same blocks.
6047       return;
6048     }
6049 
6050     assert(pred->number_of_sux() == 1, "can handle only one successor");
6051     assert(pred->sux_at(0) == block, "invalid control flow");
6052     assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6053     assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6054     assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6055 
6056     if (pred_instructions->last()->info() != NULL) {
6057       // can not optimize instructions when debug info is needed
6058       return;
6059     }
6060 
6061     // ignore the unconditional branch at the end of the block
6062     append_instructions(pred_instructions, pred_instructions->length() - 2);
6063   }
6064 
6065 
6066   // process lir-instructions while all predecessors end with the same instruction
6067   while (true) {
6068     LIR_Op* op = instruction_at(0);
6069     for (i = 1; i < num_preds; i++) {
6070       if (operations_different(op, instruction_at(i))) {
6071         // these instructions are different and cannot be optimized ->
6072         // no further optimization possible
6073         return;
6074       }
6075     }
6076 
6077     TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
6078 
6079     // insert the instruction at the beginning of the current block
6080     block->lir()->insert_before(1, op);
6081 
6082     // delete the instruction at the end of all predecessors
6083     for (i = 0; i < num_preds; i++) {
6084       remove_cur_instruction(i, true);
6085     }
6086   }
6087 }
6088 
6089 
6090 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
6091   TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
6092 
6093   init_instructions();
6094   int num_sux = block->number_of_sux();
6095 
6096   LIR_OpList* cur_instructions = block->lir()->instructions_list();
6097 
6098   assert(num_sux == 2, "method should not be called otherwise");
6099   assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6100   assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6101   assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6102 
6103   if (cur_instructions->last()->info() != NULL) {
6104     // can no optimize instructions when debug info is needed
6105     return;
6106   }
6107 
6108   LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
6109   if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
6110     // not a valid case for optimization
6111     // currently, only blocks that end with two branches (conditional branch followed
6112     // by unconditional branch) are optimized
6113     return;
6114   }
6115 
6116   // now it is guaranteed that the block ends with two branch instructions.
6117   // the instructions are inserted at the end of the block before these two branches
6118   int insert_idx = cur_instructions->length() - 2;
6119 
6120   int i;
6121 #ifdef ASSERT
6122   for (i = insert_idx - 1; i >= 0; i--) {
6123     LIR_Op* op = cur_instructions->at(i);
6124     if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
6125       assert(false, "block with two successors can have only two branch instructions");
6126     }
6127   }
6128 #endif
6129 
6130   // setup a list with the lir-instructions of all successors
6131   for (i = 0; i < num_sux; i++) {
6132     BlockBegin* sux = block->sux_at(i);
6133     LIR_OpList* sux_instructions = sux->lir()->instructions_list();
6134 
6135     assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
6136 
6137     if (sux->number_of_preds() != 1) {
6138       // this can happen with switch-statements where multiple edges are between
6139       // the same blocks.
6140       return;
6141     }
6142     assert(sux->pred_at(0) == block, "invalid control flow");
6143     assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6144 
6145     // ignore the label at the beginning of the block
6146     append_instructions(sux_instructions, 1);
6147   }
6148 
6149   // process lir-instructions while all successors begin with the same instruction
6150   while (true) {
6151     LIR_Op* op = instruction_at(0);
6152     for (i = 1; i < num_sux; i++) {
6153       if (operations_different(op, instruction_at(i))) {
6154         // these instructions are different and cannot be optimized ->
6155         // no further optimization possible
6156         return;
6157       }
6158     }
6159 
6160     TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6161 
6162     // insert instruction at end of current block
6163     block->lir()->insert_before(insert_idx, op);
6164     insert_idx++;
6165 
6166     // delete the instructions at the beginning of all successors
6167     for (i = 0; i < num_sux; i++) {
6168       remove_cur_instruction(i, false);
6169     }
6170   }
6171 }
6172 
6173 
6174 // Implementation of ControlFlowOptimizer
6175 
6176 ControlFlowOptimizer::ControlFlowOptimizer() :
6177   _original_preds(4)
6178 {
6179 }
6180 
6181 void ControlFlowOptimizer::optimize(BlockList* code) {
6182   ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6183 
6184   // push the OSR entry block to the end so that we're not jumping over it.
6185   BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6186   if (osr_entry) {
6187     int index = osr_entry->linear_scan_number();
6188     assert(code->at(index) == osr_entry, "wrong index");
6189     code->remove_at(index);
6190     code->append(osr_entry);
6191   }
6192 
6193   optimizer.reorder_short_loops(code);
6194   optimizer.delete_empty_blocks(code);
6195   optimizer.delete_unnecessary_jumps(code);
6196   optimizer.delete_jumps_to_return(code);
6197 }
6198 
6199 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6200   int i = header_idx + 1;
6201   int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6202   while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6203     i++;
6204   }
6205 
6206   if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6207     int end_idx = i - 1;
6208     BlockBegin* end_block = code->at(end_idx);
6209 
6210     if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6211       // short loop from header_idx to end_idx found -> reorder blocks such that
6212       // the header_block is the last block instead of the first block of the loop
6213       TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6214                                          end_idx - header_idx + 1,
6215                                          header_block->block_id(), end_block->block_id()));
6216 
6217       for (int j = header_idx; j < end_idx; j++) {
6218         code->at_put(j, code->at(j + 1));
6219       }
6220       code->at_put(end_idx, header_block);
6221 
6222       // correct the flags so that any loop alignment occurs in the right place.
6223       assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6224       code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6225       code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6226     }
6227   }
6228 }
6229 
6230 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6231   for (int i = code->length() - 1; i >= 0; i--) {
6232     BlockBegin* block = code->at(i);
6233 
6234     if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6235       reorder_short_loop(code, block, i);
6236     }
6237   }
6238 
6239   DEBUG_ONLY(verify(code));
6240 }
6241 
6242 // only blocks with exactly one successor can be deleted. Such blocks
6243 // must always end with an unconditional branch to this successor
6244 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6245   if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6246     return false;
6247   }
6248 
6249   LIR_OpList* instructions = block->lir()->instructions_list();
6250 
6251   assert(instructions->length() >= 2, "block must have label and branch");
6252   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6253   assert(instructions->last()->as_OpBranch() != NULL, "last instrcution must always be a branch");
6254   assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6255   assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6256 
6257   // block must have exactly one successor
6258 
6259   if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6260     return true;
6261   }
6262   return false;
6263 }
6264 
6265 // substitute branch targets in all branch-instructions of this blocks
6266 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6267   TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6268 
6269   LIR_OpList* instructions = block->lir()->instructions_list();
6270 
6271   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6272   for (int i = instructions->length() - 1; i >= 1; i--) {
6273     LIR_Op* op = instructions->at(i);
6274 
6275     if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6276       assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6277       LIR_OpBranch* branch = (LIR_OpBranch*)op;
6278 
6279       if (branch->block() == target_from) {
6280         branch->change_block(target_to);
6281       }
6282       if (branch->ublock() == target_from) {
6283         branch->change_ublock(target_to);
6284       }
6285     }
6286   }
6287 }
6288 
6289 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6290   int old_pos = 0;
6291   int new_pos = 0;
6292   int num_blocks = code->length();
6293 
6294   while (old_pos < num_blocks) {
6295     BlockBegin* block = code->at(old_pos);
6296 
6297     if (can_delete_block(block)) {
6298       BlockBegin* new_target = block->sux_at(0);
6299 
6300       // propagate backward branch target flag for correct code alignment
6301       if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6302         new_target->set(BlockBegin::backward_branch_target_flag);
6303       }
6304 
6305       // collect a list with all predecessors that contains each predecessor only once
6306       // the predecessors of cur are changed during the substitution, so a copy of the
6307       // predecessor list is necessary
6308       int j;
6309       _original_preds.clear();
6310       for (j = block->number_of_preds() - 1; j >= 0; j--) {
6311         BlockBegin* pred = block->pred_at(j);
6312         if (_original_preds.find(pred) == -1) {
6313           _original_preds.append(pred);
6314         }
6315       }
6316 
6317       for (j = _original_preds.length() - 1; j >= 0; j--) {
6318         BlockBegin* pred = _original_preds.at(j);
6319         substitute_branch_target(pred, block, new_target);
6320         pred->substitute_sux(block, new_target);
6321       }
6322     } else {
6323       // adjust position of this block in the block list if blocks before
6324       // have been deleted
6325       if (new_pos != old_pos) {
6326         code->at_put(new_pos, code->at(old_pos));
6327       }
6328       new_pos++;
6329     }
6330     old_pos++;
6331   }
6332   code->trunc_to(new_pos);
6333 
6334   DEBUG_ONLY(verify(code));
6335 }
6336 
6337 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6338   // skip the last block because there a branch is always necessary
6339   for (int i = code->length() - 2; i >= 0; i--) {
6340     BlockBegin* block = code->at(i);
6341     LIR_OpList* instructions = block->lir()->instructions_list();
6342 
6343     LIR_Op* last_op = instructions->last();
6344     if (last_op->code() == lir_branch) {
6345       assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6346       LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6347 
6348       assert(last_branch->block() != NULL, "last branch must always have a block as target");
6349       assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6350 
6351       if (last_branch->info() == NULL) {
6352         if (last_branch->block() == code->at(i + 1)) {
6353 
6354           TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6355 
6356           // delete last branch instruction
6357           instructions->trunc_to(instructions->length() - 1);
6358 
6359         } else {
6360           LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6361           if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6362             assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6363             LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6364 
6365             if (prev_branch->stub() == NULL) {
6366 
6367               LIR_Op2* prev_cmp = NULL;
6368               // There might be a cmove inserted for profiling which depends on the same
6369               // compare. If we change the condition of the respective compare, we have
6370               // to take care of this cmove as well.
6371               LIR_Op2* prev_cmove = NULL;
6372 
6373               for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6374                 prev_op = instructions->at(j);
6375                 // check for the cmove
6376                 if (prev_op->code() == lir_cmove) {
6377                   assert(prev_op->as_Op2() != NULL, "cmove must be of type LIR_Op2");
6378                   prev_cmove = (LIR_Op2*)prev_op;
6379                   assert(prev_branch->cond() == prev_cmove->condition(), "should be the same");
6380                 }
6381                 if (prev_op->code() == lir_cmp) {
6382                   assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6383                   prev_cmp = (LIR_Op2*)prev_op;
6384                   assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6385                 }
6386               }
6387               // Guarantee because it is dereferenced below.
6388               guarantee(prev_cmp != NULL, "should have found comp instruction for branch");
6389               if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6390 
6391                 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6392 
6393                 // eliminate a conditional branch to the immediate successor
6394                 prev_branch->change_block(last_branch->block());
6395                 prev_branch->negate_cond();
6396                 prev_cmp->set_condition(prev_branch->cond());
6397                 instructions->trunc_to(instructions->length() - 1);
6398                 // if we do change the condition, we have to change the cmove as well
6399                 if (prev_cmove != NULL) {
6400                   prev_cmove->set_condition(prev_branch->cond());
6401                   LIR_Opr t = prev_cmove->in_opr1();
6402                   prev_cmove->set_in_opr1(prev_cmove->in_opr2());
6403                   prev_cmove->set_in_opr2(t);
6404                 }
6405               }
6406             }
6407           }
6408         }
6409       }
6410     }
6411   }
6412 
6413   DEBUG_ONLY(verify(code));
6414 }
6415 
6416 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6417 #ifdef ASSERT
6418   ResourceBitMap return_converted(BlockBegin::number_of_blocks());
6419 #endif
6420 
6421   for (int i = code->length() - 1; i >= 0; i--) {
6422     BlockBegin* block = code->at(i);
6423     LIR_OpList* cur_instructions = block->lir()->instructions_list();
6424     LIR_Op*     cur_last_op = cur_instructions->last();
6425 
6426     assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6427     if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6428       // the block contains only a label and a return
6429       // if a predecessor ends with an unconditional jump to this block, then the jump
6430       // can be replaced with a return instruction
6431       //
6432       // Note: the original block with only a return statement cannot be deleted completely
6433       //       because the predecessors might have other (conditional) jumps to this block
6434       //       -> this may lead to unnecesary return instructions in the final code
6435 
6436       assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6437       assert(block->number_of_sux() == 0 ||
6438              (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6439              "blocks that end with return must not have successors");
6440 
6441       assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6442       LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6443 
6444       for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6445         BlockBegin* pred = block->pred_at(j);
6446         LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6447         LIR_Op*     pred_last_op = pred_instructions->last();
6448 
6449         if (pred_last_op->code() == lir_branch) {
6450           assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6451           LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6452 
6453           if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6454             // replace the jump to a return with a direct return
6455             // Note: currently the edge between the blocks is not deleted
6456             pred_instructions->at_put(pred_instructions->length() - 1, new LIR_OpReturn(return_opr));
6457 #ifdef ASSERT
6458             return_converted.set_bit(pred->block_id());
6459 #endif
6460           }
6461         }
6462       }
6463     }
6464   }
6465 }
6466 
6467 
6468 #ifdef ASSERT
6469 void ControlFlowOptimizer::verify(BlockList* code) {
6470   for (int i = 0; i < code->length(); i++) {
6471     BlockBegin* block = code->at(i);
6472     LIR_OpList* instructions = block->lir()->instructions_list();
6473 
6474     int j;
6475     for (j = 0; j < instructions->length(); j++) {
6476       LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6477 
6478       if (op_branch != NULL) {
6479         assert(op_branch->block() == NULL || code->find(op_branch->block()) != -1, "branch target not valid");
6480         assert(op_branch->ublock() == NULL || code->find(op_branch->ublock()) != -1, "branch target not valid");
6481       }
6482     }
6483 
6484     for (j = 0; j < block->number_of_sux() - 1; j++) {
6485       BlockBegin* sux = block->sux_at(j);
6486       assert(code->find(sux) != -1, "successor not valid");
6487     }
6488 
6489     for (j = 0; j < block->number_of_preds() - 1; j++) {
6490       BlockBegin* pred = block->pred_at(j);
6491       assert(code->find(pred) != -1, "successor not valid");
6492     }
6493   }
6494 }
6495 #endif
6496 
6497 
6498 #ifndef PRODUCT
6499 
6500 // Implementation of LinearStatistic
6501 
6502 const char* LinearScanStatistic::counter_name(int counter_idx) {
6503   switch (counter_idx) {
6504     case counter_method:          return "compiled methods";
6505     case counter_fpu_method:      return "methods using fpu";
6506     case counter_loop_method:     return "methods with loops";
6507     case counter_exception_method:return "methods with xhandler";
6508 
6509     case counter_loop:            return "loops";
6510     case counter_block:           return "blocks";
6511     case counter_loop_block:      return "blocks inside loop";
6512     case counter_exception_block: return "exception handler entries";
6513     case counter_interval:        return "intervals";
6514     case counter_fixed_interval:  return "fixed intervals";
6515     case counter_range:           return "ranges";
6516     case counter_fixed_range:     return "fixed ranges";
6517     case counter_use_pos:         return "use positions";
6518     case counter_fixed_use_pos:   return "fixed use positions";
6519     case counter_spill_slots:     return "spill slots";
6520 
6521     // counter for classes of lir instructions
6522     case counter_instruction:     return "total instructions";
6523     case counter_label:           return "labels";
6524     case counter_entry:           return "method entries";
6525     case counter_return:          return "method returns";
6526     case counter_call:            return "method calls";
6527     case counter_move:            return "moves";
6528     case counter_cmp:             return "compare";
6529     case counter_cond_branch:     return "conditional branches";
6530     case counter_uncond_branch:   return "unconditional branches";
6531     case counter_stub_branch:     return "branches to stub";
6532     case counter_alu:             return "artithmetic + logic";
6533     case counter_alloc:           return "allocations";
6534     case counter_sync:            return "synchronisation";
6535     case counter_throw:           return "throw";
6536     case counter_unwind:          return "unwind";
6537     case counter_typecheck:       return "type+null-checks";
6538     case counter_fpu_stack:       return "fpu-stack";
6539     case counter_misc_inst:       return "other instructions";
6540     case counter_other_inst:      return "misc. instructions";
6541 
6542     // counter for different types of moves
6543     case counter_move_total:      return "total moves";
6544     case counter_move_reg_reg:    return "register->register";
6545     case counter_move_reg_stack:  return "register->stack";
6546     case counter_move_stack_reg:  return "stack->register";
6547     case counter_move_stack_stack:return "stack->stack";
6548     case counter_move_reg_mem:    return "register->memory";
6549     case counter_move_mem_reg:    return "memory->register";
6550     case counter_move_const_any:  return "constant->any";
6551 
6552     case blank_line_1:            return "";
6553     case blank_line_2:            return "";
6554 
6555     default: ShouldNotReachHere(); return "";
6556   }
6557 }
6558 
6559 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6560   if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6561     return counter_method;
6562   } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6563     return counter_block;
6564   } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6565     return counter_instruction;
6566   } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6567     return counter_move_total;
6568   }
6569   return invalid_counter;
6570 }
6571 
6572 LinearScanStatistic::LinearScanStatistic() {
6573   for (int i = 0; i < number_of_counters; i++) {
6574     _counters_sum[i] = 0;
6575     _counters_max[i] = -1;
6576   }
6577 
6578 }
6579 
6580 // add the method-local numbers to the total sum
6581 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6582   for (int i = 0; i < number_of_counters; i++) {
6583     _counters_sum[i] += method_statistic._counters_sum[i];
6584     _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6585   }
6586 }
6587 
6588 void LinearScanStatistic::print(const char* title) {
6589   if (CountLinearScan || TraceLinearScanLevel > 0) {
6590     tty->cr();
6591     tty->print_cr("***** LinearScan statistic - %s *****", title);
6592 
6593     for (int i = 0; i < number_of_counters; i++) {
6594       if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6595         tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6596 
6597         LinearScanStatistic::Counter cntr = base_counter(i);
6598         if (cntr != invalid_counter) {
6599           tty->print("  (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[cntr]);
6600         } else {
6601           tty->print("           ");
6602         }
6603 
6604         if (_counters_max[i] >= 0) {
6605           tty->print("%8d", _counters_max[i]);
6606         }
6607       }
6608       tty->cr();
6609     }
6610   }
6611 }
6612 
6613 void LinearScanStatistic::collect(LinearScan* allocator) {
6614   inc_counter(counter_method);
6615   if (allocator->has_fpu_registers()) {
6616     inc_counter(counter_fpu_method);
6617   }
6618   if (allocator->num_loops() > 0) {
6619     inc_counter(counter_loop_method);
6620   }
6621   inc_counter(counter_loop, allocator->num_loops());
6622   inc_counter(counter_spill_slots, allocator->max_spills());
6623 
6624   int i;
6625   for (i = 0; i < allocator->interval_count(); i++) {
6626     Interval* cur = allocator->interval_at(i);
6627 
6628     if (cur != NULL) {
6629       inc_counter(counter_interval);
6630       inc_counter(counter_use_pos, cur->num_use_positions());
6631       if (LinearScan::is_precolored_interval(cur)) {
6632         inc_counter(counter_fixed_interval);
6633         inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6634       }
6635 
6636       Range* range = cur->first();
6637       while (range != Range::end()) {
6638         inc_counter(counter_range);
6639         if (LinearScan::is_precolored_interval(cur)) {
6640           inc_counter(counter_fixed_range);
6641         }
6642         range = range->next();
6643       }
6644     }
6645   }
6646 
6647   bool has_xhandlers = false;
6648   // Note: only count blocks that are in code-emit order
6649   for (i = 0; i < allocator->ir()->code()->length(); i++) {
6650     BlockBegin* cur = allocator->ir()->code()->at(i);
6651 
6652     inc_counter(counter_block);
6653     if (cur->loop_depth() > 0) {
6654       inc_counter(counter_loop_block);
6655     }
6656     if (cur->is_set(BlockBegin::exception_entry_flag)) {
6657       inc_counter(counter_exception_block);
6658       has_xhandlers = true;
6659     }
6660 
6661     LIR_OpList* instructions = cur->lir()->instructions_list();
6662     for (int j = 0; j < instructions->length(); j++) {
6663       LIR_Op* op = instructions->at(j);
6664 
6665       inc_counter(counter_instruction);
6666 
6667       switch (op->code()) {
6668         case lir_label:           inc_counter(counter_label); break;
6669         case lir_std_entry:
6670         case lir_osr_entry:       inc_counter(counter_entry); break;
6671         case lir_return:          inc_counter(counter_return); break;
6672 
6673         case lir_rtcall:
6674         case lir_static_call:
6675         case lir_optvirtual_call: inc_counter(counter_call); break;
6676 
6677         case lir_move: {
6678           inc_counter(counter_move);
6679           inc_counter(counter_move_total);
6680 
6681           LIR_Opr in = op->as_Op1()->in_opr();
6682           LIR_Opr res = op->as_Op1()->result_opr();
6683           if (in->is_register()) {
6684             if (res->is_register()) {
6685               inc_counter(counter_move_reg_reg);
6686             } else if (res->is_stack()) {
6687               inc_counter(counter_move_reg_stack);
6688             } else if (res->is_address()) {
6689               inc_counter(counter_move_reg_mem);
6690             } else {
6691               ShouldNotReachHere();
6692             }
6693           } else if (in->is_stack()) {
6694             if (res->is_register()) {
6695               inc_counter(counter_move_stack_reg);
6696             } else {
6697               inc_counter(counter_move_stack_stack);
6698             }
6699           } else if (in->is_address()) {
6700             assert(res->is_register(), "must be");
6701             inc_counter(counter_move_mem_reg);
6702           } else if (in->is_constant()) {
6703             inc_counter(counter_move_const_any);
6704           } else {
6705             ShouldNotReachHere();
6706           }
6707           break;
6708         }
6709 
6710         case lir_cmp:             inc_counter(counter_cmp); break;
6711 
6712         case lir_branch:
6713         case lir_cond_float_branch: {
6714           LIR_OpBranch* branch = op->as_OpBranch();
6715           if (branch->block() == NULL) {
6716             inc_counter(counter_stub_branch);
6717           } else if (branch->cond() == lir_cond_always) {
6718             inc_counter(counter_uncond_branch);
6719           } else {
6720             inc_counter(counter_cond_branch);
6721           }
6722           break;
6723         }
6724 
6725         case lir_neg:
6726         case lir_add:
6727         case lir_sub:
6728         case lir_mul:
6729         case lir_div:
6730         case lir_rem:
6731         case lir_sqrt:
6732         case lir_abs:
6733         case lir_log10:
6734         case lir_logic_and:
6735         case lir_logic_or:
6736         case lir_logic_xor:
6737         case lir_shl:
6738         case lir_shr:
6739         case lir_ushr:            inc_counter(counter_alu); break;
6740 
6741         case lir_alloc_object:
6742         case lir_alloc_array:     inc_counter(counter_alloc); break;
6743 
6744         case lir_monaddr:
6745         case lir_lock:
6746         case lir_unlock:          inc_counter(counter_sync); break;
6747 
6748         case lir_throw:           inc_counter(counter_throw); break;
6749 
6750         case lir_unwind:          inc_counter(counter_unwind); break;
6751 
6752         case lir_null_check:
6753         case lir_leal:
6754         case lir_instanceof:
6755         case lir_checkcast:
6756         case lir_store_check:     inc_counter(counter_typecheck); break;
6757 
6758         case lir_fpop_raw:
6759         case lir_fxch:
6760         case lir_fld:             inc_counter(counter_fpu_stack); break;
6761 
6762         case lir_nop:
6763         case lir_push:
6764         case lir_pop:
6765         case lir_convert:
6766         case lir_roundfp:
6767         case lir_cmove:           inc_counter(counter_misc_inst); break;
6768 
6769         default:                  inc_counter(counter_other_inst); break;
6770       }
6771     }
6772   }
6773 
6774   if (has_xhandlers) {
6775     inc_counter(counter_exception_method);
6776   }
6777 }
6778 
6779 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6780   if (CountLinearScan || TraceLinearScanLevel > 0) {
6781 
6782     LinearScanStatistic local_statistic = LinearScanStatistic();
6783 
6784     local_statistic.collect(allocator);
6785     global_statistic.sum_up(local_statistic);
6786 
6787     if (TraceLinearScanLevel > 2) {
6788       local_statistic.print("current local statistic");
6789     }
6790   }
6791 }
6792 
6793 
6794 // Implementation of LinearTimers
6795 
6796 LinearScanTimers::LinearScanTimers() {
6797   for (int i = 0; i < number_of_timers; i++) {
6798     timer(i)->reset();
6799   }
6800 }
6801 
6802 const char* LinearScanTimers::timer_name(int idx) {
6803   switch (idx) {
6804     case timer_do_nothing:               return "Nothing (Time Check)";
6805     case timer_number_instructions:      return "Number Instructions";
6806     case timer_compute_local_live_sets:  return "Local Live Sets";
6807     case timer_compute_global_live_sets: return "Global Live Sets";
6808     case timer_build_intervals:          return "Build Intervals";
6809     case timer_sort_intervals_before:    return "Sort Intervals Before";
6810     case timer_allocate_registers:       return "Allocate Registers";
6811     case timer_resolve_data_flow:        return "Resolve Data Flow";
6812     case timer_sort_intervals_after:     return "Sort Intervals After";
6813     case timer_eliminate_spill_moves:    return "Spill optimization";
6814     case timer_assign_reg_num:           return "Assign Reg Num";
6815     case timer_allocate_fpu_stack:       return "Allocate FPU Stack";
6816     case timer_optimize_lir:             return "Optimize LIR";
6817     default: ShouldNotReachHere();       return "";
6818   }
6819 }
6820 
6821 void LinearScanTimers::begin_method() {
6822   if (TimeEachLinearScan) {
6823     // reset all timers to measure only current method
6824     for (int i = 0; i < number_of_timers; i++) {
6825       timer(i)->reset();
6826     }
6827   }
6828 }
6829 
6830 void LinearScanTimers::end_method(LinearScan* allocator) {
6831   if (TimeEachLinearScan) {
6832 
6833     double c = timer(timer_do_nothing)->seconds();
6834     double total = 0;
6835     for (int i = 1; i < number_of_timers; i++) {
6836       total += timer(i)->seconds() - c;
6837     }
6838 
6839     if (total >= 0.0005) {
6840       // print all information in one line for automatic processing
6841       tty->print("@"); allocator->compilation()->method()->print_name();
6842 
6843       tty->print("@ %d ", allocator->compilation()->method()->code_size());
6844       tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6845       tty->print("@ %d ", allocator->block_count());
6846       tty->print("@ %d ", allocator->num_virtual_regs());
6847       tty->print("@ %d ", allocator->interval_count());
6848       tty->print("@ %d ", allocator->_num_calls);
6849       tty->print("@ %d ", allocator->num_loops());
6850 
6851       tty->print("@ %6.6f ", total);
6852       for (int i = 1; i < number_of_timers; i++) {
6853         tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6854       }
6855       tty->cr();
6856     }
6857   }
6858 }
6859 
6860 void LinearScanTimers::print(double total_time) {
6861   if (TimeLinearScan) {
6862     // correction value: sum of dummy-timer that only measures the time that
6863     // is necesary to start and stop itself
6864     double c = timer(timer_do_nothing)->seconds();
6865 
6866     for (int i = 0; i < number_of_timers; i++) {
6867       double t = timer(i)->seconds();
6868       tty->print_cr("    %25s: %6.3f s (%4.1f%%)  corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6869     }
6870   }
6871 }
6872 
6873 #endif // #ifndef PRODUCT