89 }
90 PhiNode* has_phi() const; // returns an arbitrary phi user, or NULL
91 PhiNode* has_unique_phi() const; // returns the unique phi user, or NULL
92 // Is this region node unreachable from root?
93 bool is_unreachable_region(const PhaseGVN* phase);
94 #ifdef ASSERT
95 bool is_in_infinite_subgraph();
96 static bool are_all_nodes_in_infinite_subgraph(Unique_Node_List& worklist);
97 #endif //ASSERT
98 virtual int Opcode() const;
99 virtual uint size_of() const { return sizeof(*this); }
100 virtual bool pinned() const { return (const Node*)in(0) == this; }
101 virtual bool is_CFG() const { return true; }
102 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash
103 virtual bool depends_only_on_test() const { return false; }
104 virtual const Type* bottom_type() const { return Type::CONTROL; }
105 virtual const Type* Value(PhaseGVN* phase) const;
106 virtual Node* Identity(PhaseGVN* phase);
107 virtual Node* Ideal(PhaseGVN* phase, bool can_reshape);
108 virtual const RegMask &out_RegMask() const;
109 bool try_clean_mem_phi(PhaseGVN* phase);
110 bool optimize_trichotomy(PhaseIterGVN* igvn);
111 };
112
113 //------------------------------JProjNode--------------------------------------
114 // jump projection for node that produces multiple control-flow paths
115 class JProjNode : public ProjNode {
116 public:
117 JProjNode( Node* ctrl, uint idx ) : ProjNode(ctrl,idx) {}
118 virtual int Opcode() const;
119 virtual bool is_CFG() const { return true; }
120 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash
121 virtual const Node* is_block_proj() const { return in(0); }
122 virtual const RegMask& out_RegMask() const;
123 virtual uint ideal_reg() const { return 0; }
124 };
125
126 //------------------------------PhiNode----------------------------------------
127 // PhiNodes merge values from different Control paths. Slot 0 points to the
128 // controlling RegionNode. Other slots map 1-for-1 with incoming control flow
129 // paths to the RegionNode.
205 // Is it unsafe data loop? It becomes a dead loop if this phi node removed.
206 bool is_unsafe_data_reference(Node *in) const;
207 int is_diamond_phi(bool check_control_only = false) const;
208 virtual int Opcode() const;
209 virtual bool pinned() const { return in(0) != 0; }
210 virtual const TypePtr *adr_type() const { verify_adr_type(true); return _adr_type; }
211
212 void set_inst_mem_id(int inst_mem_id) { _inst_mem_id = inst_mem_id; }
213 const int inst_mem_id() const { return _inst_mem_id; }
214 const int inst_id() const { return _inst_id; }
215 const int inst_index() const { return _inst_index; }
216 const int inst_offset() const { return _inst_offset; }
217 bool is_same_inst_field(const Type* tp, int mem_id, int id, int index, int offset) {
218 return type()->basic_type() == tp->basic_type() &&
219 inst_mem_id() == mem_id &&
220 inst_id() == id &&
221 inst_index() == index &&
222 inst_offset() == offset &&
223 type()->higher_equal(tp);
224 }
225
226 virtual const Type* Value(PhaseGVN* phase) const;
227 virtual Node* Identity(PhaseGVN* phase);
228 virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
229 virtual const RegMask &out_RegMask() const;
230 virtual const RegMask &in_RegMask(uint) const;
231 #ifndef PRODUCT
232 virtual void dump_spec(outputStream *st) const;
233 #endif
234 #ifdef ASSERT
235 void verify_adr_type(VectorSet& visited, const TypePtr* at) const;
236 void verify_adr_type(bool recursive = false) const;
237 #else //ASSERT
238 void verify_adr_type(bool recursive = false) const {}
239 #endif //ASSERT
240 };
241
242 //------------------------------GotoNode---------------------------------------
243 // GotoNodes perform direct branches.
244 class GotoNode : public Node {
387 init_class_id(Class_If);
388 init_req(0,control);
389 init_req(1,b);
390 }
391 virtual int Opcode() const;
392 virtual bool pinned() const { return true; }
393 virtual const Type *bottom_type() const { return TypeTuple::IFBOTH; }
394 virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
395 virtual const Type* Value(PhaseGVN* phase) const;
396 virtual int required_outcnt() const { return 2; }
397 virtual const RegMask &out_RegMask() const;
398 Node* fold_compares(PhaseIterGVN* phase);
399 static Node* up_one_dom(Node* curr, bool linear_only = false);
400 Node* dominated_by(Node* prev_dom, PhaseIterGVN* igvn);
401
402 // Takes the type of val and filters it through the test represented
403 // by if_proj and returns a more refined type if one is produced.
404 // Returns NULL is it couldn't improve the type.
405 static const TypeInt* filtered_int_type(PhaseGVN* phase, Node* val, Node* if_proj);
406
407 #ifndef PRODUCT
408 virtual void dump_spec(outputStream *st) const;
409 #endif
410 };
411
412 class RangeCheckNode : public IfNode {
413 private:
414 int is_range_check(Node* &range, Node* &index, jint &offset);
415
416 public:
417 RangeCheckNode(Node* control, Node *b, float p, float fcnt)
418 : IfNode(control, b, p, fcnt) {
419 init_class_id(Class_RangeCheck);
420 }
421
422 virtual int Opcode() const;
423 virtual Node* Ideal(PhaseGVN *phase, bool can_reshape);
424 };
425
426 class IfProjNode : public CProjNode {
602 virtual int Opcode() const;
603 virtual bool pinned() const { return true; };
604 virtual const Type *bottom_type() const { return TypeTuple::IFBOTH; }
605 virtual const Type* Value(PhaseGVN* phase) const;
606 virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
607 virtual int required_outcnt() const { return 2; }
608 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { }
609 virtual uint size(PhaseRegAlloc *ra_) const { return 0; }
610 #ifndef PRODUCT
611 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
612 #endif
613 };
614
615 //------------------------------BlackholeNode----------------------------
616 // Blackhole all arguments. This node would survive through the compiler
617 // the effects on its arguments, and would be finally matched to nothing.
618 class BlackholeNode : public MultiNode {
619 public:
620 BlackholeNode(Node* ctrl) : MultiNode(1) {
621 init_req(TypeFunc::Control, ctrl);
622 }
623 virtual int Opcode() const;
624 virtual uint ideal_reg() const { return 0; } // not matched in the AD file
625 virtual const Type* bottom_type() const { return TypeTuple::MEMBAR; }
626
627 const RegMask &in_RegMask(uint idx) const {
628 // Fake the incoming arguments mask for blackholes: accept all registers
629 // and all stack slots. This would avoid any redundant register moves
630 // for blackhole inputs.
631 return RegMask::All;
632 }
633 #ifndef PRODUCT
634 virtual void format(PhaseRegAlloc* ra, outputStream* st) const;
635 #endif
636 };
637
638
639 #endif // SHARE_OPTO_CFGNODE_HPP
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89 }
90 PhiNode* has_phi() const; // returns an arbitrary phi user, or NULL
91 PhiNode* has_unique_phi() const; // returns the unique phi user, or NULL
92 // Is this region node unreachable from root?
93 bool is_unreachable_region(const PhaseGVN* phase);
94 #ifdef ASSERT
95 bool is_in_infinite_subgraph();
96 static bool are_all_nodes_in_infinite_subgraph(Unique_Node_List& worklist);
97 #endif //ASSERT
98 virtual int Opcode() const;
99 virtual uint size_of() const { return sizeof(*this); }
100 virtual bool pinned() const { return (const Node*)in(0) == this; }
101 virtual bool is_CFG() const { return true; }
102 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash
103 virtual bool depends_only_on_test() const { return false; }
104 virtual const Type* bottom_type() const { return Type::CONTROL; }
105 virtual const Type* Value(PhaseGVN* phase) const;
106 virtual Node* Identity(PhaseGVN* phase);
107 virtual Node* Ideal(PhaseGVN* phase, bool can_reshape);
108 virtual const RegMask &out_RegMask() const;
109 bool optimize_trichotomy(PhaseIterGVN* igvn);
110 };
111
112 //------------------------------JProjNode--------------------------------------
113 // jump projection for node that produces multiple control-flow paths
114 class JProjNode : public ProjNode {
115 public:
116 JProjNode( Node* ctrl, uint idx ) : ProjNode(ctrl,idx) {}
117 virtual int Opcode() const;
118 virtual bool is_CFG() const { return true; }
119 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash
120 virtual const Node* is_block_proj() const { return in(0); }
121 virtual const RegMask& out_RegMask() const;
122 virtual uint ideal_reg() const { return 0; }
123 };
124
125 //------------------------------PhiNode----------------------------------------
126 // PhiNodes merge values from different Control paths. Slot 0 points to the
127 // controlling RegionNode. Other slots map 1-for-1 with incoming control flow
128 // paths to the RegionNode.
204 // Is it unsafe data loop? It becomes a dead loop if this phi node removed.
205 bool is_unsafe_data_reference(Node *in) const;
206 int is_diamond_phi(bool check_control_only = false) const;
207 virtual int Opcode() const;
208 virtual bool pinned() const { return in(0) != 0; }
209 virtual const TypePtr *adr_type() const { verify_adr_type(true); return _adr_type; }
210
211 void set_inst_mem_id(int inst_mem_id) { _inst_mem_id = inst_mem_id; }
212 const int inst_mem_id() const { return _inst_mem_id; }
213 const int inst_id() const { return _inst_id; }
214 const int inst_index() const { return _inst_index; }
215 const int inst_offset() const { return _inst_offset; }
216 bool is_same_inst_field(const Type* tp, int mem_id, int id, int index, int offset) {
217 return type()->basic_type() == tp->basic_type() &&
218 inst_mem_id() == mem_id &&
219 inst_id() == id &&
220 inst_index() == index &&
221 inst_offset() == offset &&
222 type()->higher_equal(tp);
223 }
224 Node* try_clean_mem_phi(PhaseGVN *phase);
225
226 InlineTypeNode* push_inline_types_through(PhaseGVN* phase, bool can_reshape, ciInlineKlass* vk, bool is_init);
227
228 virtual const Type* Value(PhaseGVN* phase) const;
229 virtual Node* Identity(PhaseGVN* phase);
230 virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
231 virtual const RegMask &out_RegMask() const;
232 virtual const RegMask &in_RegMask(uint) const;
233 #ifndef PRODUCT
234 virtual void dump_spec(outputStream *st) const;
235 #endif
236 #ifdef ASSERT
237 void verify_adr_type(VectorSet& visited, const TypePtr* at) const;
238 void verify_adr_type(bool recursive = false) const;
239 #else //ASSERT
240 void verify_adr_type(bool recursive = false) const {}
241 #endif //ASSERT
242 };
243
244 //------------------------------GotoNode---------------------------------------
245 // GotoNodes perform direct branches.
246 class GotoNode : public Node {
389 init_class_id(Class_If);
390 init_req(0,control);
391 init_req(1,b);
392 }
393 virtual int Opcode() const;
394 virtual bool pinned() const { return true; }
395 virtual const Type *bottom_type() const { return TypeTuple::IFBOTH; }
396 virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
397 virtual const Type* Value(PhaseGVN* phase) const;
398 virtual int required_outcnt() const { return 2; }
399 virtual const RegMask &out_RegMask() const;
400 Node* fold_compares(PhaseIterGVN* phase);
401 static Node* up_one_dom(Node* curr, bool linear_only = false);
402 Node* dominated_by(Node* prev_dom, PhaseIterGVN* igvn);
403
404 // Takes the type of val and filters it through the test represented
405 // by if_proj and returns a more refined type if one is produced.
406 // Returns NULL is it couldn't improve the type.
407 static const TypeInt* filtered_int_type(PhaseGVN* phase, Node* val, Node* if_proj);
408
409 bool is_flat_array_check(PhaseTransform* phase, Node** array = NULL);
410
411 #ifndef PRODUCT
412 virtual void dump_spec(outputStream *st) const;
413 #endif
414 };
415
416 class RangeCheckNode : public IfNode {
417 private:
418 int is_range_check(Node* &range, Node* &index, jint &offset);
419
420 public:
421 RangeCheckNode(Node* control, Node *b, float p, float fcnt)
422 : IfNode(control, b, p, fcnt) {
423 init_class_id(Class_RangeCheck);
424 }
425
426 virtual int Opcode() const;
427 virtual Node* Ideal(PhaseGVN *phase, bool can_reshape);
428 };
429
430 class IfProjNode : public CProjNode {
606 virtual int Opcode() const;
607 virtual bool pinned() const { return true; };
608 virtual const Type *bottom_type() const { return TypeTuple::IFBOTH; }
609 virtual const Type* Value(PhaseGVN* phase) const;
610 virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
611 virtual int required_outcnt() const { return 2; }
612 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { }
613 virtual uint size(PhaseRegAlloc *ra_) const { return 0; }
614 #ifndef PRODUCT
615 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
616 #endif
617 };
618
619 //------------------------------BlackholeNode----------------------------
620 // Blackhole all arguments. This node would survive through the compiler
621 // the effects on its arguments, and would be finally matched to nothing.
622 class BlackholeNode : public MultiNode {
623 public:
624 BlackholeNode(Node* ctrl) : MultiNode(1) {
625 init_req(TypeFunc::Control, ctrl);
626 init_class_id(Class_Blackhole);
627 }
628 virtual int Opcode() const;
629 virtual uint ideal_reg() const { return 0; } // not matched in the AD file
630 virtual const Type* bottom_type() const { return TypeTuple::MEMBAR; }
631
632 const RegMask &in_RegMask(uint idx) const {
633 // Fake the incoming arguments mask for blackholes: accept all registers
634 // and all stack slots. This would avoid any redundant register moves
635 // for blackhole inputs.
636 return RegMask::All;
637 }
638 #ifndef PRODUCT
639 virtual void format(PhaseRegAlloc* ra, outputStream* st) const;
640 #endif
641 };
642
643
644 #endif // SHARE_OPTO_CFGNODE_HPP
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