115 #ifdef ASSERT
116 bool is_in_infinite_subgraph();
117 static bool are_all_nodes_in_infinite_subgraph(Unique_Node_List& worklist);
118 #endif //ASSERT
119 LoopStatus loop_status() const { return _loop_status; };
120 void set_loop_status(LoopStatus status);
121 DEBUG_ONLY(void verify_can_be_irreducible_entry() const;)
122
123 virtual int Opcode() const;
124 virtual uint size_of() const { return sizeof(*this); }
125 virtual bool pinned() const { return (const Node*)in(0) == this; }
126 virtual bool is_CFG() const { return true; }
127 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash
128 virtual bool depends_only_on_test() const { return false; }
129 virtual const Type* bottom_type() const { return Type::CONTROL; }
130 virtual const Type* Value(PhaseGVN* phase) const;
131 virtual Node* Identity(PhaseGVN* phase);
132 virtual Node* Ideal(PhaseGVN* phase, bool can_reshape);
133 void remove_unreachable_subgraph(PhaseIterGVN* igvn);
134 virtual const RegMask &out_RegMask() const;
135 bool try_clean_mem_phi(PhaseGVN* phase);
136 bool optimize_trichotomy(PhaseIterGVN* igvn);
137 NOT_PRODUCT(virtual void dump_spec(outputStream* st) const;)
138 };
139
140 //------------------------------JProjNode--------------------------------------
141 // jump projection for node that produces multiple control-flow paths
142 class JProjNode : public ProjNode {
143 public:
144 JProjNode( Node* ctrl, uint idx ) : ProjNode(ctrl,idx) {}
145 virtual int Opcode() const;
146 virtual bool is_CFG() const { return true; }
147 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash
148 virtual const Node* is_block_proj() const { return in(0); }
149 virtual const RegMask& out_RegMask() const;
150 virtual uint ideal_reg() const { return 0; }
151 };
152
153 //------------------------------PhiNode----------------------------------------
154 // PhiNodes merge values from different Control paths. Slot 0 points to the
155 // controlling RegionNode. Other slots map 1-for-1 with incoming control flow
234 // Is it unsafe data loop? It becomes a dead loop if this phi node removed.
235 bool is_unsafe_data_reference(Node *in) const;
236 int is_diamond_phi(bool check_control_only = false) const;
237 virtual int Opcode() const;
238 virtual bool pinned() const { return in(0) != 0; }
239 virtual const TypePtr *adr_type() const { verify_adr_type(true); return _adr_type; }
240
241 void set_inst_mem_id(int inst_mem_id) { _inst_mem_id = inst_mem_id; }
242 const int inst_mem_id() const { return _inst_mem_id; }
243 const int inst_id() const { return _inst_id; }
244 const int inst_index() const { return _inst_index; }
245 const int inst_offset() const { return _inst_offset; }
246 bool is_same_inst_field(const Type* tp, int mem_id, int id, int index, int offset) {
247 return type()->basic_type() == tp->basic_type() &&
248 inst_mem_id() == mem_id &&
249 inst_id() == id &&
250 inst_index() == index &&
251 inst_offset() == offset &&
252 type()->higher_equal(tp);
253 }
254
255 virtual const Type* Value(PhaseGVN* phase) const;
256 virtual Node* Identity(PhaseGVN* phase);
257 virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
258 virtual const RegMask &out_RegMask() const;
259 virtual const RegMask &in_RegMask(uint) const;
260 #ifndef PRODUCT
261 virtual void dump_spec(outputStream *st) const;
262 #endif
263 #ifdef ASSERT
264 void verify_adr_type(VectorSet& visited, const TypePtr* at) const;
265 void verify_adr_type(bool recursive = false) const;
266 #else //ASSERT
267 void verify_adr_type(bool recursive = false) const {}
268 #endif //ASSERT
269 };
270
271 //------------------------------GotoNode---------------------------------------
272 // GotoNodes perform direct branches.
273 class GotoNode : public Node {
416 init_class_id(Class_If);
417 init_req(0,control);
418 init_req(1,b);
419 }
420 virtual int Opcode() const;
421 virtual bool pinned() const { return true; }
422 virtual const Type *bottom_type() const { return TypeTuple::IFBOTH; }
423 virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
424 virtual const Type* Value(PhaseGVN* phase) const;
425 virtual int required_outcnt() const { return 2; }
426 virtual const RegMask &out_RegMask() const;
427 Node* fold_compares(PhaseIterGVN* phase);
428 static Node* up_one_dom(Node* curr, bool linear_only = false);
429 Node* dominated_by(Node* prev_dom, PhaseIterGVN* igvn);
430
431 // Takes the type of val and filters it through the test represented
432 // by if_proj and returns a more refined type if one is produced.
433 // Returns null is it couldn't improve the type.
434 static const TypeInt* filtered_int_type(PhaseGVN* phase, Node* val, Node* if_proj);
435
436 #ifndef PRODUCT
437 virtual void dump_spec(outputStream *st) const;
438 #endif
439 };
440
441 class RangeCheckNode : public IfNode {
442 private:
443 int is_range_check(Node* &range, Node* &index, jint &offset);
444
445 public:
446 RangeCheckNode(Node* control, Node *b, float p, float fcnt)
447 : IfNode(control, b, p, fcnt) {
448 init_class_id(Class_RangeCheck);
449 }
450
451 virtual int Opcode() const;
452 virtual Node* Ideal(PhaseGVN *phase, bool can_reshape);
453 };
454
455 class IfProjNode : public CProjNode {
631 virtual int Opcode() const;
632 virtual bool pinned() const { return true; };
633 virtual const Type *bottom_type() const { return TypeTuple::IFBOTH; }
634 virtual const Type* Value(PhaseGVN* phase) const;
635 virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
636 virtual int required_outcnt() const { return 2; }
637 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { }
638 virtual uint size(PhaseRegAlloc *ra_) const { return 0; }
639 #ifndef PRODUCT
640 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
641 #endif
642 };
643
644 //------------------------------BlackholeNode----------------------------
645 // Blackhole all arguments. This node would survive through the compiler
646 // the effects on its arguments, and would be finally matched to nothing.
647 class BlackholeNode : public MultiNode {
648 public:
649 BlackholeNode(Node* ctrl) : MultiNode(1) {
650 init_req(TypeFunc::Control, ctrl);
651 }
652 virtual int Opcode() const;
653 virtual uint ideal_reg() const { return 0; } // not matched in the AD file
654 virtual const Type* bottom_type() const { return TypeTuple::MEMBAR; }
655
656 const RegMask &in_RegMask(uint idx) const {
657 // Fake the incoming arguments mask for blackholes: accept all registers
658 // and all stack slots. This would avoid any redundant register moves
659 // for blackhole inputs.
660 return RegMask::All;
661 }
662 #ifndef PRODUCT
663 virtual void format(PhaseRegAlloc* ra, outputStream* st) const;
664 #endif
665 };
666
667
668 #endif // SHARE_OPTO_CFGNODE_HPP
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115 #ifdef ASSERT
116 bool is_in_infinite_subgraph();
117 static bool are_all_nodes_in_infinite_subgraph(Unique_Node_List& worklist);
118 #endif //ASSERT
119 LoopStatus loop_status() const { return _loop_status; };
120 void set_loop_status(LoopStatus status);
121 DEBUG_ONLY(void verify_can_be_irreducible_entry() const;)
122
123 virtual int Opcode() const;
124 virtual uint size_of() const { return sizeof(*this); }
125 virtual bool pinned() const { return (const Node*)in(0) == this; }
126 virtual bool is_CFG() const { return true; }
127 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash
128 virtual bool depends_only_on_test() const { return false; }
129 virtual const Type* bottom_type() const { return Type::CONTROL; }
130 virtual const Type* Value(PhaseGVN* phase) const;
131 virtual Node* Identity(PhaseGVN* phase);
132 virtual Node* Ideal(PhaseGVN* phase, bool can_reshape);
133 void remove_unreachable_subgraph(PhaseIterGVN* igvn);
134 virtual const RegMask &out_RegMask() const;
135 bool optimize_trichotomy(PhaseIterGVN* igvn);
136 NOT_PRODUCT(virtual void dump_spec(outputStream* st) const;)
137 };
138
139 //------------------------------JProjNode--------------------------------------
140 // jump projection for node that produces multiple control-flow paths
141 class JProjNode : public ProjNode {
142 public:
143 JProjNode( Node* ctrl, uint idx ) : ProjNode(ctrl,idx) {}
144 virtual int Opcode() const;
145 virtual bool is_CFG() const { return true; }
146 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash
147 virtual const Node* is_block_proj() const { return in(0); }
148 virtual const RegMask& out_RegMask() const;
149 virtual uint ideal_reg() const { return 0; }
150 };
151
152 //------------------------------PhiNode----------------------------------------
153 // PhiNodes merge values from different Control paths. Slot 0 points to the
154 // controlling RegionNode. Other slots map 1-for-1 with incoming control flow
233 // Is it unsafe data loop? It becomes a dead loop if this phi node removed.
234 bool is_unsafe_data_reference(Node *in) const;
235 int is_diamond_phi(bool check_control_only = false) const;
236 virtual int Opcode() const;
237 virtual bool pinned() const { return in(0) != 0; }
238 virtual const TypePtr *adr_type() const { verify_adr_type(true); return _adr_type; }
239
240 void set_inst_mem_id(int inst_mem_id) { _inst_mem_id = inst_mem_id; }
241 const int inst_mem_id() const { return _inst_mem_id; }
242 const int inst_id() const { return _inst_id; }
243 const int inst_index() const { return _inst_index; }
244 const int inst_offset() const { return _inst_offset; }
245 bool is_same_inst_field(const Type* tp, int mem_id, int id, int index, int offset) {
246 return type()->basic_type() == tp->basic_type() &&
247 inst_mem_id() == mem_id &&
248 inst_id() == id &&
249 inst_index() == index &&
250 inst_offset() == offset &&
251 type()->higher_equal(tp);
252 }
253 Node* try_clean_mem_phi(PhaseGVN *phase);
254
255 InlineTypeNode* push_inline_types_through(PhaseGVN* phase, bool can_reshape, ciInlineKlass* vk, bool is_init);
256
257 virtual const Type* Value(PhaseGVN* phase) const;
258 virtual Node* Identity(PhaseGVN* phase);
259 virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
260 virtual const RegMask &out_RegMask() const;
261 virtual const RegMask &in_RegMask(uint) const;
262 #ifndef PRODUCT
263 virtual void dump_spec(outputStream *st) const;
264 #endif
265 #ifdef ASSERT
266 void verify_adr_type(VectorSet& visited, const TypePtr* at) const;
267 void verify_adr_type(bool recursive = false) const;
268 #else //ASSERT
269 void verify_adr_type(bool recursive = false) const {}
270 #endif //ASSERT
271 };
272
273 //------------------------------GotoNode---------------------------------------
274 // GotoNodes perform direct branches.
275 class GotoNode : public Node {
418 init_class_id(Class_If);
419 init_req(0,control);
420 init_req(1,b);
421 }
422 virtual int Opcode() const;
423 virtual bool pinned() const { return true; }
424 virtual const Type *bottom_type() const { return TypeTuple::IFBOTH; }
425 virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
426 virtual const Type* Value(PhaseGVN* phase) const;
427 virtual int required_outcnt() const { return 2; }
428 virtual const RegMask &out_RegMask() const;
429 Node* fold_compares(PhaseIterGVN* phase);
430 static Node* up_one_dom(Node* curr, bool linear_only = false);
431 Node* dominated_by(Node* prev_dom, PhaseIterGVN* igvn);
432
433 // Takes the type of val and filters it through the test represented
434 // by if_proj and returns a more refined type if one is produced.
435 // Returns null is it couldn't improve the type.
436 static const TypeInt* filtered_int_type(PhaseGVN* phase, Node* val, Node* if_proj);
437
438 bool is_flat_array_check(PhaseTransform* phase, Node** array = NULL);
439
440 #ifndef PRODUCT
441 virtual void dump_spec(outputStream *st) const;
442 #endif
443 };
444
445 class RangeCheckNode : public IfNode {
446 private:
447 int is_range_check(Node* &range, Node* &index, jint &offset);
448
449 public:
450 RangeCheckNode(Node* control, Node *b, float p, float fcnt)
451 : IfNode(control, b, p, fcnt) {
452 init_class_id(Class_RangeCheck);
453 }
454
455 virtual int Opcode() const;
456 virtual Node* Ideal(PhaseGVN *phase, bool can_reshape);
457 };
458
459 class IfProjNode : public CProjNode {
635 virtual int Opcode() const;
636 virtual bool pinned() const { return true; };
637 virtual const Type *bottom_type() const { return TypeTuple::IFBOTH; }
638 virtual const Type* Value(PhaseGVN* phase) const;
639 virtual Node *Ideal(PhaseGVN *phase, bool can_reshape);
640 virtual int required_outcnt() const { return 2; }
641 virtual void emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { }
642 virtual uint size(PhaseRegAlloc *ra_) const { return 0; }
643 #ifndef PRODUCT
644 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
645 #endif
646 };
647
648 //------------------------------BlackholeNode----------------------------
649 // Blackhole all arguments. This node would survive through the compiler
650 // the effects on its arguments, and would be finally matched to nothing.
651 class BlackholeNode : public MultiNode {
652 public:
653 BlackholeNode(Node* ctrl) : MultiNode(1) {
654 init_req(TypeFunc::Control, ctrl);
655 init_class_id(Class_Blackhole);
656 }
657 virtual int Opcode() const;
658 virtual uint ideal_reg() const { return 0; } // not matched in the AD file
659 virtual const Type* bottom_type() const { return TypeTuple::MEMBAR; }
660
661 const RegMask &in_RegMask(uint idx) const {
662 // Fake the incoming arguments mask for blackholes: accept all registers
663 // and all stack slots. This would avoid any redundant register moves
664 // for blackhole inputs.
665 return RegMask::All;
666 }
667 #ifndef PRODUCT
668 virtual void format(PhaseRegAlloc* ra, outputStream* st) const;
669 #endif
670 };
671
672
673 #endif // SHARE_OPTO_CFGNODE_HPP
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