1 /*
2 * Copyright (c) 1998, 2026, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #include "asm/macroAssembler.inline.hpp"
26 #include "gc/shared/gc_globals.hpp"
27 #include "memory/allocation.inline.hpp"
28 #include "oops/compressedOops.hpp"
29 #include "opto/ad.hpp"
30 #include "opto/block.hpp"
31 #include "opto/c2compiler.hpp"
32 #include "opto/callnode.hpp"
33 #include "opto/cfgnode.hpp"
34 #include "opto/chaitin.hpp"
35 #include "opto/machnode.hpp"
36 #include "opto/runtime.hpp"
37 #include "runtime/os.inline.hpp"
38 #include "runtime/sharedRuntime.hpp"
39
40 // Optimization - Graph Style
41
42 // Check whether val is not-null-decoded compressed oop,
43 // i.e. will grab into the base of the heap if it represents null.
44 static bool accesses_heap_base_zone(Node *val) {
45 if (CompressedOops::base() != nullptr) { // Implies UseCompressedOops.
46 if (val && val->is_Mach()) {
47 if (val->as_Mach()->ideal_Opcode() == Op_DecodeN) {
48 // This assumes all Decodes with TypePtr::NotNull are matched to nodes that
49 // decode null to point to the heap base (Decode_NN).
50 if (val->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull) {
51 return true;
52 }
53 }
54 // Must recognize load operation with Decode matched in memory operand.
55 // We should not reach here except for PPC/AIX, as os::zero_page_read_protected()
56 // returns true everywhere else. On PPC, no such memory operands
57 // exist, therefore we did not yet implement a check for such operands.
58 NOT_AIX(Unimplemented());
59 }
60 }
61 return false;
62 }
63
64 static bool needs_explicit_null_check_for_read(Node *val) {
65 // On some OSes (AIX) the page at address 0 is only write protected.
66 // If so, only Store operations will trap.
67 if (os::zero_page_read_protected()) {
68 return false; // Implicit null check will work.
69 }
70 // Also a read accessing the base of a heap-based compressed heap will trap.
71 if (accesses_heap_base_zone(val) && // Hits the base zone page.
72 CompressedOops::use_implicit_null_checks()) { // Base zone page is protected.
73 return false;
74 }
75
76 return true;
77 }
78
79 void PhaseCFG::move_node_and_its_projections_to_block(Node* n, Block* b) {
80 assert(!is_CFG(n), "cannot move CFG node");
81 Block* old = get_block_for_node(n);
82 old->find_remove(n);
83 b->add_inst(n);
84 map_node_to_block(n, b);
85 // Check for Mach projections that also need to be moved.
86 for (DUIterator_Fast imax, i = n->fast_outs(imax); i < imax; i++) {
87 Node* out = n->fast_out(i);
88 if (!out->is_MachProj()) {
89 continue;
90 }
91 assert(!n->is_MachProj(), "nested projections are not allowed");
92 move_node_and_its_projections_to_block(out, b);
93 }
94 }
95
96 void PhaseCFG::ensure_node_is_at_block_or_above(Node* n, Block* b) {
97 assert(!is_CFG(n), "cannot move CFG node");
98 Block* current = get_block_for_node(n);
99 if (current->dominates(b)) {
100 return; // n is already placed above b, do nothing.
101 }
102 // We only expect nodes without further inputs, like MachTemp or load Base.
103 assert(n->req() == 0 || (n->req() == 1 && n->in(0) == (Node*)C->root()),
104 "need for recursive hoisting not expected");
105 assert(b->dominates(current), "precondition: can only move n to b if b dominates n");
106 move_node_and_its_projections_to_block(n, b);
107 }
108
109 //------------------------------implicit_null_check----------------------------
110 // Detect implicit-null-check opportunities. Basically, find null checks
111 // with suitable memory ops nearby. Use the memory op to do the null check.
112 // I can generate a memory op if there is not one nearby.
113 // The proj is the control projection for the not-null case.
114 // The val is the pointer being checked for nullness or
115 // decodeHeapOop_not_null node if it did not fold into address.
116 void PhaseCFG::implicit_null_check(Block* block, Node *proj, Node *val, int allowed_reasons) {
117 // Assume if null check need for 0 offset then always needed
118 // Intel solaris doesn't support any null checks yet and no
119 // mechanism exists (yet) to set the switches at an os_cpu level
120 if( !ImplicitNullChecks || MacroAssembler::needs_explicit_null_check(0)) return;
121
122 // Make sure the ptr-is-null path appears to be uncommon!
123 float f = block->end()->as_MachIf()->_prob;
124 if( proj->Opcode() == Op_IfTrue ) f = 1.0f - f;
125 if( f > PROB_UNLIKELY_MAG(4) ) return;
126
127 uint bidx = 0; // Capture index of value into memop
128 bool was_store; // Memory op is a store op
129
130 // Get the successor block for if the test ptr is non-null
131 Block* not_null_block; // this one goes with the proj
132 Block* null_block;
133 if (block->get_node(block->number_of_nodes()-1) == proj) {
134 null_block = block->_succs[0];
135 not_null_block = block->_succs[1];
136 } else {
137 assert(block->get_node(block->number_of_nodes()-2) == proj, "proj is one or the other");
138 not_null_block = block->_succs[0];
139 null_block = block->_succs[1];
140 }
141 while (null_block->is_Empty() == Block::empty_with_goto) {
142 null_block = null_block->_succs[0];
143 }
144
145 // Search the exception block for an uncommon trap.
146 // (See Parse::do_if and Parse::do_ifnull for the reason
147 // we need an uncommon trap. Briefly, we need a way to
148 // detect failure of this optimization, as in 6366351.)
149 {
150 bool found_trap = false;
151 for (uint i1 = 0; i1 < null_block->number_of_nodes(); i1++) {
152 Node* nn = null_block->get_node(i1);
153 if (nn->is_MachCall() &&
154 nn->as_MachCall()->entry_point() == OptoRuntime::uncommon_trap_blob()->entry_point()) {
155 const Type* trtype = nn->in(TypeFunc::Parms)->bottom_type();
156 if (trtype->isa_int() && trtype->is_int()->is_con()) {
157 jint tr_con = trtype->is_int()->get_con();
158 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
159 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
160 assert((int)reason < (int)BitsPerInt, "recode bit map");
161 if (is_set_nth_bit(allowed_reasons, (int) reason)
162 && action != Deoptimization::Action_none) {
163 // This uncommon trap is sure to recompile, eventually.
164 // When that happens, C->too_many_traps will prevent
165 // this transformation from happening again.
166 found_trap = true;
167 }
168 }
169 break;
170 }
171 }
172 if (!found_trap) {
173 // We did not find an uncommon trap.
174 return;
175 }
176 }
177
178 // Check for decodeHeapOop_not_null node which did not fold into address
179 bool is_decoden = ((intptr_t)val) & 1;
180 val = (Node*)(((intptr_t)val) & ~1);
181
182 assert(!is_decoden ||
183 ((val->in(0) == nullptr) && val->is_Mach() &&
184 (val->as_Mach()->ideal_Opcode() == Op_DecodeN)), "sanity");
185
186 // Search the successor block for a load or store who's base value is also
187 // the tested value. There may be several.
188 MachNode *best = nullptr; // Best found so far
189 for (DUIterator i = val->outs(); val->has_out(i); i++) {
190 Node *m = val->out(i);
191 if( !m->is_Mach() ) continue;
192 MachNode *mach = m->as_Mach();
193 if (mach->barrier_data() != 0 &&
194 !mach->is_late_expanded_null_check_candidate()) {
195 // Using memory accesses with barriers to perform implicit null checks is
196 // only supported if these are explicit marked as emitting a candidate
197 // memory access instruction at their initial address. If not marked as
198 // such, barrier-tagged operations might expand into one or several memory
199 // access instructions located at arbitrary offsets from the initial
200 // address, which would invalidate the implicit null exception table.
201 continue;
202 }
203 was_store = false;
204 int iop = mach->ideal_Opcode();
205 switch( iop ) {
206 case Op_LoadB:
207 case Op_LoadUB:
208 case Op_LoadUS:
209 case Op_LoadD:
210 case Op_LoadF:
211 case Op_LoadI:
212 case Op_LoadL:
213 case Op_LoadP:
214 case Op_LoadN:
215 case Op_LoadS:
216 case Op_LoadKlass:
217 case Op_LoadNKlass:
218 case Op_LoadRange:
219 case Op_LoadD_unaligned:
220 case Op_LoadL_unaligned:
221 assert(mach->in(2) == val, "should be address");
222 break;
223 case Op_StoreB:
224 case Op_StoreC:
225 case Op_StoreD:
226 case Op_StoreF:
227 case Op_StoreI:
228 case Op_StoreL:
229 case Op_StoreLSpecial:
230 case Op_StoreP:
231 case Op_StoreN:
232 case Op_StoreNKlass:
233 was_store = true; // Memory op is a store op
234 // Stores will have their address in slot 2 (memory in slot 1).
235 // If the value being nul-checked is in another slot, it means we
236 // are storing the checked value, which does NOT check the value!
237 if( mach->in(2) != val ) continue;
238 break; // Found a memory op?
239 case Op_StrComp:
240 case Op_StrEquals:
241 case Op_StrIndexOf:
242 case Op_StrIndexOfChar:
243 case Op_AryEq:
244 case Op_VectorizedHashCode:
245 case Op_StrInflatedCopy:
246 case Op_StrCompressedCopy:
247 case Op_EncodeISOArray:
248 case Op_CountPositives:
249 // Not a legit memory op for implicit null check regardless of
250 // embedded loads
251 continue;
252 default: // Also check for embedded loads
253 if( !mach->needs_anti_dependence_check() )
254 continue; // Not an memory op; skip it
255 if( must_clone[iop] ) {
256 // Do not move nodes which produce flags because
257 // RA will try to clone it to place near branch and
258 // it will cause recompilation, see clone_node().
259 continue;
260 }
261 {
262 // Check that value is used in memory address in
263 // instructions with embedded load (CmpP val1,(val2+off)).
264 Node* base;
265 Node* index;
266 const MachOper* oper = mach->memory_inputs(base, index);
267 if (oper == nullptr || oper == (MachOper*)-1) {
268 continue; // Not an memory op; skip it
269 }
270 if (val == base ||
271 (val == index && val->bottom_type()->isa_narrowoop())) {
272 break; // Found it
273 } else {
274 continue; // Skip it
275 }
276 }
277 break;
278 }
279
280 // On some OSes (AIX) the page at address 0 is only write protected.
281 // If so, only Store operations will trap.
282 // But a read accessing the base of a heap-based compressed heap will trap.
283 if (!was_store && needs_explicit_null_check_for_read(val)) {
284 continue;
285 }
286
287 // Check that node's control edge is not-null block's head or dominates it,
288 // otherwise we can't hoist it because there are other control dependencies.
289 Node* ctrl = mach->in(0);
290 if (ctrl != nullptr && !(ctrl == not_null_block->head() ||
291 get_block_for_node(ctrl)->dominates(not_null_block))) {
292 continue;
293 }
294
295 // check if the offset is not too high for implicit exception
296 {
297 intptr_t offset = 0;
298 const TypePtr *adr_type = nullptr; // Do not need this return value here
299 const Node* base = mach->get_base_and_disp(offset, adr_type);
300 if (base == nullptr || base == NodeSentinel) {
301 // Narrow oop address doesn't have base, only index.
302 // Give up if offset is beyond page size or if heap base is not protected.
303 if (val->bottom_type()->isa_narrowoop() &&
304 (MacroAssembler::needs_explicit_null_check(offset) ||
305 !CompressedOops::use_implicit_null_checks()))
306 continue;
307 // cannot reason about it; is probably not implicit null exception
308 } else {
309 const TypePtr* tptr;
310 if ((UseCompressedOops && CompressedOops::shift() == 0) || CompressedKlassPointers::shift() == 0) {
311 // 32-bits narrow oop can be the base of address expressions
312 tptr = base->get_ptr_type();
313 } else {
314 // only regular oops are expected here
315 tptr = base->bottom_type()->is_ptr();
316 }
317 // Give up if offset is not a compile-time constant.
318 if (offset == Type::OffsetBot || tptr->offset() == Type::OffsetBot)
319 continue;
320 offset += tptr->offset(); // correct if base is offsetted
321 // Give up if reference is beyond page size.
322 if (MacroAssembler::needs_explicit_null_check(offset))
323 continue;
324 // Give up if base is a decode node and the heap base is not protected.
325 if (base->is_Mach() && base->as_Mach()->ideal_Opcode() == Op_DecodeN &&
326 !CompressedOops::use_implicit_null_checks())
327 continue;
328 }
329 }
330
331 // Check ctrl input to see if the null-check dominates the memory op
332 Block *cb = get_block_for_node(mach);
333 cb = cb->_idom; // Always hoist at least 1 block
334 if( !was_store ) { // Stores can be hoisted only one block
335 while( cb->_dom_depth > (block->_dom_depth + 1))
336 cb = cb->_idom; // Hoist loads as far as we want
337 // The non-null-block should dominate the memory op, too. Live
338 // range spilling will insert a spill in the non-null-block if it is
339 // needs to spill the memory op for an implicit null check.
340 if (cb->_dom_depth == (block->_dom_depth + 1)) {
341 if (cb != not_null_block) continue;
342 cb = cb->_idom;
343 }
344 }
345 if( cb != block ) continue;
346
347 // Found a memory user; see if it can be hoisted to check-block
348 uint vidx = 0; // Capture index of value into memop
349 uint j;
350 for( j = mach->req()-1; j > 0; j-- ) {
351 if( mach->in(j) == val ) {
352 vidx = j;
353 // Ignore DecodeN val which could be hoisted to where needed.
354 if( is_decoden ) continue;
355 }
356 if (mach->in(j)->is_MachTemp()) {
357 assert(mach->in(j)->outcnt() == 1, "MachTemp nodes should not be shared");
358 // Ignore MachTemp inputs, they can be safely hoisted with the candidate.
359 // MachTemp nodes have no inputs themselves and are only used to reserve
360 // a scratch register for the implementation of the node (e.g. in
361 // late-expanded GC barriers).
362 continue;
363 }
364 // Block of memory-op input
365 Block* inb = get_block_for_node(mach->in(j));
366 if (mach->in(j)->is_Con() && mach->in(j)->req() == 1 && inb == get_block_for_node(mach)) {
367 // Ignore constant loads scheduled in the same block (we can simply hoist them as well)
368 continue;
369 }
370 Block *b = block; // Start from nul check
371 while( b != inb && b->_dom_depth > inb->_dom_depth )
372 b = b->_idom; // search upwards for input
373 // See if input dominates null check
374 if( b != inb )
375 break;
376 }
377 if( j > 0 )
378 continue;
379 Block *mb = get_block_for_node(mach);
380 // Hoisting stores requires more checks for the anti-dependence case.
381 // Give up hoisting if we have to move the store past any load.
382 if (was_store) {
383 // Make sure control does not do a merge (would have to check allpaths)
384 if (mb->num_preds() != 2) {
385 continue;
386 }
387 // mach is a store, hence block is the immediate dominator of mb.
388 // Due to the null-check shape of block (where its successors cannot re-join),
389 // block must be the direct predecessor of mb.
390 assert(get_block_for_node(mb->pred(1)) == block, "Unexpected predecessor block");
391 uint k;
392 uint num_nodes = mb->number_of_nodes();
393 for (k = 1; k < num_nodes; k++) {
394 Node *n = mb->get_node(k);
395 if (n->needs_anti_dependence_check() &&
396 n->in(LoadNode::Memory) == mach->in(StoreNode::Memory)) {
397 break; // Found anti-dependent load
398 }
399 }
400 if (k < num_nodes) {
401 continue; // Found anti-dependent load
402 }
403 }
404
405 // Make sure this memory op is not already being used for a NullCheck
406 Node *e = mb->end();
407 if( e->is_MachNullCheck() && e->in(1) == mach )
408 continue; // Already being used as a null check
409
410 // Found a candidate! Pick one with least dom depth - the highest
411 // in the dom tree should be closest to the null check.
412 if (best == nullptr || get_block_for_node(mach)->_dom_depth < get_block_for_node(best)->_dom_depth) {
413 best = mach;
414 bidx = vidx;
415 }
416 }
417 // No candidate!
418 if (best == nullptr) {
419 return;
420 }
421
422 // ---- Found an implicit null check
423 #ifndef PRODUCT
424 extern uint implicit_null_checks;
425 implicit_null_checks++;
426 #endif
427
428 if( is_decoden ) {
429 // Check if we need to hoist decodeHeapOop_not_null first.
430 Block *valb = get_block_for_node(val);
431 if( block != valb && block->_dom_depth < valb->_dom_depth ) {
432 // Hoist it up to the end of the test block together with its inputs if they exist.
433 for (uint i = 2; i < val->req(); i++) {
434 // DecodeN has 2 regular inputs + optional MachTemp or load Base inputs.
435 // Inputs of val may already be early enough, but if not move them together with val.
436 ensure_node_is_at_block_or_above(val->in(i), block);
437 }
438 move_node_and_its_projections_to_block(val, block);
439 }
440 }
441
442 // Hoist constant load inputs as well.
443 for (uint i = 1; i < best->req(); ++i) {
444 Node* n = best->in(i);
445 if (n->is_Con() && get_block_for_node(n) == get_block_for_node(best)) {
446 get_block_for_node(n)->find_remove(n);
447 block->add_inst(n);
448 map_node_to_block(n, block);
449 // Constant loads may kill flags (for example, when XORing a register).
450 // Check for flag-killing projections that also need to be hoisted.
451 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) {
452 Node* proj = n->fast_out(j);
453 if (proj->is_MachProj()) {
454 get_block_for_node(proj)->find_remove(proj);
455 block->add_inst(proj);
456 map_node_to_block(proj, block);
457 }
458 }
459 }
460 }
461
462
463 // Move any MachTemp inputs to the end of the test block.
464 for (uint i = 0; i < best->req(); i++) {
465 Node* n = best->in(i);
466 if (n == nullptr || !n->is_MachTemp()) {
467 continue;
468 }
469 ensure_node_is_at_block_or_above(n, block);
470 }
471
472 // Hoist the memory candidate up to the end of the test block.
473 move_node_and_its_projections_to_block(best, block);
474
475 // Move the control dependence if it is pinned to not-null block.
476 // Don't change it in other cases: null or dominating control.
477 Node* ctrl = best->in(0);
478 if (ctrl != nullptr && get_block_for_node(ctrl) == not_null_block) {
479 // Set it to control edge of null check.
480 best->set_req(0, proj->in(0)->in(0));
481 }
482
483 // proj==Op_True --> ne test; proj==Op_False --> eq test.
484 // One of two graph shapes got matched:
485 // (IfTrue (If (Bool NE (CmpP ptr null))))
486 // (IfFalse (If (Bool EQ (CmpP ptr null))))
487 // null checks are always branch-if-eq. If we see a IfTrue projection
488 // then we are replacing a 'ne' test with a 'eq' null check test.
489 // We need to flip the projections to keep the same semantics.
490 if( proj->Opcode() == Op_IfTrue ) {
491 // Swap order of projections in basic block to swap branch targets
492 Node *tmp1 = block->get_node(block->end_idx()+1);
493 Node *tmp2 = block->get_node(block->end_idx()+2);
494 block->map_node(tmp2, block->end_idx()+1);
495 block->map_node(tmp1, block->end_idx()+2);
496 Node *tmp = new Node(C->top()); // Use not null input
497 tmp1->replace_by(tmp);
498 tmp2->replace_by(tmp1);
499 tmp->replace_by(tmp2);
500 tmp->destruct(nullptr);
501 }
502
503 // Remove the existing null check; use a new implicit null check instead.
504 // Since schedule-local needs precise def-use info, we need to correct
505 // it as well.
506 Node *old_tst = proj->in(0);
507 MachNode *nul_chk = new MachNullCheckNode(old_tst->in(0),best,bidx);
508 block->map_node(nul_chk, block->end_idx());
509 map_node_to_block(nul_chk, block);
510 // Redirect users of old_test to nul_chk
511 for (DUIterator_Last i2min, i2 = old_tst->last_outs(i2min); i2 >= i2min; --i2)
512 old_tst->last_out(i2)->set_req(0, nul_chk);
513 // Clean-up any dead code
514 for (uint i3 = 0; i3 < old_tst->req(); i3++) {
515 Node* in = old_tst->in(i3);
516 old_tst->set_req(i3, nullptr);
517 if (in->outcnt() == 0) {
518 // Remove dead input node
519 in->disconnect_inputs(C);
520 block->find_remove(in);
521 }
522 }
523
524 latency_from_uses(nul_chk);
525 latency_from_uses(best);
526
527 // insert anti-dependences to defs in this block
528 if (! best->needs_anti_dependence_check()) {
529 for (uint k = 1; k < block->number_of_nodes(); k++) {
530 Node *n = block->get_node(k);
531 if (n->needs_anti_dependence_check() &&
532 n->in(LoadNode::Memory) == best->in(StoreNode::Memory)) {
533 // Found anti-dependent load
534 raise_above_anti_dependences(block, n);
535 if (C->failing()) {
536 return;
537 }
538 }
539 }
540 }
541 }
542
543
544 //------------------------------select-----------------------------------------
545 // Select a nice fellow from the worklist to schedule next. If there is only one
546 // choice, then use it. CreateEx nodes that are initially ready must start their
547 // blocks and are given the highest priority, by being placed at the beginning
548 // of the worklist. Next after initially-ready CreateEx nodes are projections,
549 // which must follow their parents, and CreateEx nodes with local input
550 // dependencies. Next are constants and CheckCastPP nodes. There are a number of
551 // other special cases, for instructions that consume condition codes, et al.
552 // These are chosen immediately. Some instructions are required to immediately
553 // precede the last instruction in the block, and these are taken last. Of the
554 // remaining cases (most), choose the instruction with the greatest latency
555 // (that is, the most number of pseudo-cycles required to the end of the
556 // routine). If there is a tie, choose the instruction with the most inputs.
557 Node* PhaseCFG::select(
558 Block* block,
559 Node_List &worklist,
560 GrowableArray<int> &ready_cnt,
561 VectorSet &next_call,
562 uint sched_slot,
563 intptr_t* recalc_pressure_nodes) {
564
565 // If only a single entry on the stack, use it
566 uint cnt = worklist.size();
567 if (cnt == 1) {
568 Node *n = worklist[0];
569 worklist.map(0,worklist.pop());
570 return n;
571 }
572
573 uint choice = 0; // Bigger is most important
574 uint latency = 0; // Bigger is scheduled first
575 uint score = 0; // Bigger is better
576 int idx = -1; // Index in worklist
577 int cand_cnt = 0; // Candidate count
578 bool block_size_threshold_ok = (recalc_pressure_nodes != nullptr) && (block->number_of_nodes() > 10);
579
580 for( uint i=0; i<cnt; i++ ) { // Inspect entire worklist
581 // Order in worklist is used to break ties.
582 // See caller for how this is used to delay scheduling
583 // of induction variable increments to after the other
584 // uses of the phi are scheduled.
585 Node *n = worklist[i]; // Get Node on worklist
586
587 int iop = n->is_Mach() ? n->as_Mach()->ideal_Opcode() : 0;
588 if (iop == Op_CreateEx || n->is_Proj()) {
589 // CreateEx nodes that are initially ready must start the block (after Phi
590 // and Parm nodes which are pre-scheduled) and get top priority. This is
591 // currently enforced by placing them at the beginning of the initial
592 // worklist and selecting them eagerly here. After these, projections and
593 // other CreateEx nodes are selected with equal priority.
594 worklist.map(i,worklist.pop());
595 return n;
596 }
597
598 if (n->Opcode() == Op_Con || iop == Op_CheckCastPP) {
599 // Constants and CheckCastPP nodes have higher priority than the rest of
600 // the nodes tested below. Record as current winner, but keep looking for
601 // higher-priority nodes in the worklist.
602 choice = 4;
603 // Latency and score are only used to break ties among low-priority nodes.
604 latency = 0;
605 score = 0;
606 idx = i;
607 continue;
608 }
609
610 // Final call in a block must be adjacent to 'catch'
611 Node *e = block->end();
612 if( e->is_Catch() && e->in(0)->in(0) == n )
613 continue;
614
615 // Memory op for an implicit null check has to be at the end of the block
616 if( e->is_MachNullCheck() && e->in(1) == n )
617 continue;
618
619 // Schedule IV increment last.
620 if (e->is_Mach() && e->as_Mach()->ideal_Opcode() == Op_CountedLoopEnd) {
621 // Cmp might be matched into CountedLoopEnd node.
622 Node *cmp = (e->in(1)->ideal_reg() == Op_RegFlags) ? e->in(1) : e;
623 if (cmp->req() > 1 && cmp->in(1) == n && n->is_iteratively_computed()) {
624 continue;
625 }
626 }
627
628 uint n_choice = 2;
629
630 // See if this instruction is consumed by a branch. If so, then (as the
631 // branch is the last instruction in the basic block) force it to the
632 // end of the basic block
633 if ( must_clone[iop] ) {
634 // See if any use is a branch
635 bool found_machif = false;
636
637 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) {
638 Node* use = n->fast_out(j);
639
640 // The use is a conditional branch, make them adjacent
641 if (use->is_MachIf() && get_block_for_node(use) == block) {
642 found_machif = true;
643 break;
644 }
645
646 // More than this instruction pending for successor to be ready,
647 // don't choose this if other opportunities are ready
648 if (ready_cnt.at(use->_idx) > 1)
649 n_choice = 1;
650 }
651
652 // loop terminated, prefer not to use this instruction
653 if (found_machif)
654 continue;
655 }
656
657 // See if this has a predecessor that is "must_clone", i.e. sets the
658 // condition code. If so, choose this first
659 for (uint j = 0; j < n->req() ; j++) {
660 Node *inn = n->in(j);
661 if (inn) {
662 if (inn->is_Mach() && must_clone[inn->as_Mach()->ideal_Opcode()] ) {
663 n_choice = 3;
664 break;
665 }
666 }
667 }
668
669 // MachTemps should be scheduled last so they are near their uses
670 if (n->is_MachTemp()) {
671 n_choice = 1;
672 }
673
674 uint n_latency = get_latency_for_node(n);
675 uint n_score = n->req(); // Many inputs get high score to break ties
676
677 if (OptoRegScheduling && block_size_threshold_ok) {
678 if (recalc_pressure_nodes[n->_idx] == 0x7fff7fff) {
679 _regalloc->_scratch_int_pressure.init(_regalloc->_sched_int_pressure.high_pressure_limit());
680 _regalloc->_scratch_float_pressure.init(_regalloc->_sched_float_pressure.high_pressure_limit());
681 // simulate the notion that we just picked this node to schedule
682 n->add_flag(Node::Flag_is_scheduled);
683 // now calculate its effect upon the graph if we did
684 adjust_register_pressure(n, block, recalc_pressure_nodes, false);
685 // return its state for finalize in case somebody else wins
686 n->remove_flag(Node::Flag_is_scheduled);
687 // now save the two final pressure components of register pressure, limiting pressure calcs to short size
688 short int_pressure = (short)_regalloc->_scratch_int_pressure.current_pressure();
689 short float_pressure = (short)_regalloc->_scratch_float_pressure.current_pressure();
690 recalc_pressure_nodes[n->_idx] = int_pressure;
691 recalc_pressure_nodes[n->_idx] |= (float_pressure << 16);
692 }
693
694 if (_scheduling_for_pressure) {
695 latency = n_latency;
696 if (n_choice != 3) {
697 // Now evaluate each register pressure component based on threshold in the score.
698 // In general the defining register type will dominate the score, ergo we will not see register pressure grow on both banks
699 // on a single instruction, but we might see it shrink on both banks.
700 // For each use of register that has a register class that is over the high pressure limit, we build n_score up for
701 // live ranges that terminate on this instruction.
702 if (_regalloc->_sched_int_pressure.current_pressure() > _regalloc->_sched_int_pressure.high_pressure_limit()) {
703 short int_pressure = (short)recalc_pressure_nodes[n->_idx];
704 n_score = (int_pressure < 0) ? ((score + n_score) - int_pressure) : (int_pressure > 0) ? 1 : n_score;
705 }
706 if (_regalloc->_sched_float_pressure.current_pressure() > _regalloc->_sched_float_pressure.high_pressure_limit()) {
707 short float_pressure = (short)(recalc_pressure_nodes[n->_idx] >> 16);
708 n_score = (float_pressure < 0) ? ((score + n_score) - float_pressure) : (float_pressure > 0) ? 1 : n_score;
709 }
710 } else {
711 // make sure we choose these candidates
712 score = 0;
713 }
714 }
715 }
716
717 // Keep best latency found
718 cand_cnt++;
719 if (choice < n_choice ||
720 (choice == n_choice &&
721 ((StressLCM && C->randomized_select(cand_cnt)) ||
722 (!StressLCM &&
723 (latency < n_latency ||
724 (latency == n_latency &&
725 (score < n_score))))))) {
726 choice = n_choice;
727 latency = n_latency;
728 score = n_score;
729 idx = i; // Also keep index in worklist
730 }
731 } // End of for all ready nodes in worklist
732
733 guarantee(idx >= 0, "index should be set");
734 Node *n = worklist[(uint)idx]; // Get the winner
735
736 worklist.map((uint)idx, worklist.pop()); // Compress worklist
737 return n;
738 }
739
740 //-------------------------adjust_register_pressure----------------------------
741 void PhaseCFG::adjust_register_pressure(Node* n, Block* block, intptr_t* recalc_pressure_nodes, bool finalize_mode) {
742 PhaseLive* liveinfo = _regalloc->get_live();
743 IndexSet* liveout = liveinfo->live(block);
744 // first adjust the register pressure for the sources
745 for (uint i = 1; i < n->req(); i++) {
746 bool lrg_ends = false;
747 Node *src_n = n->in(i);
748 if (src_n == nullptr) continue;
749 if (!src_n->is_Mach()) continue;
750 uint src = _regalloc->_lrg_map.find(src_n);
751 if (src == 0) continue;
752 LRG& lrg_src = _regalloc->lrgs(src);
753 // detect if the live range ends or not
754 if (liveout->member(src) == false) {
755 lrg_ends = true;
756 for (DUIterator_Fast jmax, j = src_n->fast_outs(jmax); j < jmax; j++) {
757 Node* m = src_n->fast_out(j); // Get user
758 if (m == n) continue;
759 if (!m->is_Mach()) continue;
760 MachNode *mach = m->as_Mach();
761 bool src_matches = false;
762 int iop = mach->ideal_Opcode();
763
764 switch (iop) {
765 case Op_StoreB:
766 case Op_StoreC:
767 case Op_StoreD:
768 case Op_StoreF:
769 case Op_StoreI:
770 case Op_StoreL:
771 case Op_StoreLSpecial:
772 case Op_StoreP:
773 case Op_StoreN:
774 case Op_StoreVector:
775 case Op_StoreVectorMasked:
776 case Op_StoreVectorScatter:
777 case Op_StoreVectorScatterMasked:
778 case Op_StoreNKlass:
779 for (uint k = 1; k < m->req(); k++) {
780 Node *in = m->in(k);
781 if (in == src_n) {
782 src_matches = true;
783 break;
784 }
785 }
786 break;
787
788 default:
789 src_matches = true;
790 break;
791 }
792
793 // If we have a store as our use, ignore the non source operands
794 if (src_matches == false) continue;
795
796 // Mark every unscheduled use which is not n with a recalculation
797 if ((get_block_for_node(m) == block) && (!m->is_scheduled())) {
798 if (finalize_mode && !m->is_Phi()) {
799 recalc_pressure_nodes[m->_idx] = 0x7fff7fff;
800 }
801 lrg_ends = false;
802 }
803 }
804 }
805 // if none, this live range ends and we can adjust register pressure
806 if (lrg_ends) {
807 if (finalize_mode) {
808 _regalloc->lower_pressure(block, 0, lrg_src, nullptr, _regalloc->_sched_int_pressure, _regalloc->_sched_float_pressure);
809 } else {
810 _regalloc->lower_pressure(block, 0, lrg_src, nullptr, _regalloc->_scratch_int_pressure, _regalloc->_scratch_float_pressure);
811 }
812 }
813 }
814
815 // now add the register pressure from the dest and evaluate which heuristic we should use:
816 // 1.) The default, latency scheduling
817 // 2.) Register pressure scheduling based on the high pressure limit threshold for int or float register stacks
818 uint dst = _regalloc->_lrg_map.find(n);
819 if (dst != 0) {
820 LRG& lrg_dst = _regalloc->lrgs(dst);
821 if (finalize_mode) {
822 _regalloc->raise_pressure(block, lrg_dst, _regalloc->_sched_int_pressure, _regalloc->_sched_float_pressure);
823 // check to see if we fall over the register pressure cliff here
824 if (_regalloc->_sched_int_pressure.current_pressure() > _regalloc->_sched_int_pressure.high_pressure_limit()) {
825 _scheduling_for_pressure = true;
826 } else if (_regalloc->_sched_float_pressure.current_pressure() > _regalloc->_sched_float_pressure.high_pressure_limit()) {
827 _scheduling_for_pressure = true;
828 } else {
829 // restore latency scheduling mode
830 _scheduling_for_pressure = false;
831 }
832 } else {
833 _regalloc->raise_pressure(block, lrg_dst, _regalloc->_scratch_int_pressure, _regalloc->_scratch_float_pressure);
834 }
835 }
836 }
837
838 //------------------------------set_next_call----------------------------------
839 void PhaseCFG::set_next_call(const Block* block, Node* init, VectorSet& next_call) const {
840 Node_List worklist;
841 worklist.push(init);
842
843 while (worklist.size() > 0) {
844 Node* n = worklist.pop();
845 if (next_call.test_set(n->_idx)) continue;
846 for (uint i = 0; i < n->len(); i++) {
847 Node* m = n->in(i);
848 if (m == nullptr) continue; // must see all nodes in block that precede call
849 if (get_block_for_node(m) == block) {
850 worklist.push(m);
851 }
852 }
853 }
854 }
855
856 //------------------------------needed_for_next_call---------------------------
857 // Set the flag 'next_call' for each Node that is needed for the next call to
858 // be scheduled. This flag lets me bias scheduling so Nodes needed for the
859 // next subroutine call get priority - basically it moves things NOT needed
860 // for the next call till after the call. This prevents me from trying to
861 // carry lots of stuff live across a call.
862 void PhaseCFG::needed_for_next_call(Block* block, Node* this_call, VectorSet& next_call) {
863 // Find the next control-defining Node in this block
864 Node* call = nullptr;
865 for (DUIterator_Fast imax, i = this_call->fast_outs(imax); i < imax; i++) {
866 Node* m = this_call->fast_out(i);
867 if (get_block_for_node(m) == block && // Local-block user
868 m != this_call && // Not self-start node
869 m->is_MachCall()) {
870 call = m;
871 break;
872 }
873 }
874 if (call == nullptr) return; // No next call (e.g., block end is near)
875 // Set next-call for all inputs to this call
876 set_next_call(block, call, next_call);
877 }
878
879 //------------------------------add_call_kills-------------------------------------
880 // helper function that adds caller save registers to MachProjNode
881 static void add_call_kills(MachProjNode *proj, RegMask& regs, const char* save_policy, bool exclude_soe) {
882 // Fill in the kill mask for the call
883 for( OptoReg::Name r = OptoReg::Name(0); r < _last_Mach_Reg; r=OptoReg::add(r,1) ) {
884 if (!regs.member(r)) { // Not already defined by the call
885 // Save-on-call register?
886 if ((save_policy[r] == 'C') ||
887 (save_policy[r] == 'A') ||
888 ((save_policy[r] == 'E') && exclude_soe)) {
889 proj->_rout.insert(r);
890 }
891 }
892 }
893 }
894
895
896 //------------------------------sched_call-------------------------------------
897 uint PhaseCFG::sched_call(Block* block, uint node_cnt, Node_List& worklist, GrowableArray<int>& ready_cnt, MachCallNode* mcall, VectorSet& next_call) {
898 ResourceMark rm(C->regmask_arena());
899 RegMask regs(C->regmask_arena());
900
901 // Schedule all the users of the call right now. All the users are
902 // projection Nodes, so they must be scheduled next to the call.
903 // Collect all the defined registers.
904 for (DUIterator_Fast imax, i = mcall->fast_outs(imax); i < imax; i++) {
905 Node* n = mcall->fast_out(i);
906 assert( n->is_MachProj(), "" );
907 int n_cnt = ready_cnt.at(n->_idx)-1;
908 ready_cnt.at_put(n->_idx, n_cnt);
909 assert( n_cnt == 0, "" );
910 // Schedule next to call
911 block->map_node(n, node_cnt++);
912 // Collect defined registers
913 regs.or_with(n->out_RegMask());
914 // Check for scheduling the next control-definer
915 if( n->bottom_type() == Type::CONTROL )
916 // Warm up next pile of heuristic bits
917 needed_for_next_call(block, n, next_call);
918
919 // Children of projections are now all ready
920 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) {
921 Node* m = n->fast_out(j); // Get user
922 if(get_block_for_node(m) != block) {
923 continue;
924 }
925 if( m->is_Phi() ) continue;
926 int m_cnt = ready_cnt.at(m->_idx) - 1;
927 ready_cnt.at_put(m->_idx, m_cnt);
928 if( m_cnt == 0 )
929 worklist.push(m);
930 }
931
932 }
933
934 // Act as if the call defines the Frame Pointer.
935 // Certainly the FP is alive and well after the call.
936 regs.insert(_matcher.c_frame_pointer());
937
938 // Set all registers killed and not already defined by the call.
939 uint r_cnt = mcall->tf()->range_cc()->cnt();
940 int op = mcall->ideal_Opcode();
941 MachProjNode* proj = new MachProjNode(mcall, r_cnt + 1, RegMask::EMPTY, MachProjNode::fat_proj);
942 map_node_to_block(proj, block);
943 block->insert_node(proj, node_cnt++);
944
945 // Select the right register save policy.
946 const char *save_policy = nullptr;
947 switch (op) {
948 case Op_CallRuntime:
949 case Op_CallLeaf:
950 case Op_CallLeafNoFP:
951 case Op_CallLeafVector:
952 // Calling C code so use C calling convention
953 save_policy = _matcher._c_reg_save_policy;
954 break;
955
956 case Op_CallStaticJava:
957 case Op_CallDynamicJava:
958 // Calling Java code so use Java calling convention
959 save_policy = _matcher._register_save_policy;
960 break;
961
962 default:
963 ShouldNotReachHere();
964 }
965
966 // When using CallRuntime mark SOE registers as killed by the call
967 // so values that could show up in the RegisterMap aren't live in a
968 // callee saved register since the register wouldn't know where to
969 // find them. CallLeaf and CallLeafNoFP are ok because they can't
970 // have debug info on them. Strictly speaking this only needs to be
971 // done for oops since idealreg2debugmask takes care of debug info
972 // references but there no way to handle oops differently than other
973 // pointers as far as the kill mask goes.
974 bool exclude_soe = op == Op_CallRuntime;
975 add_call_kills(proj, regs, save_policy, exclude_soe);
976
977 return node_cnt;
978 }
979
980
981 //------------------------------schedule_local---------------------------------
982 // Topological sort within a block. Someday become a real scheduler.
983 bool PhaseCFG::schedule_local(Block* block, GrowableArray<int>& ready_cnt, VectorSet& next_call, intptr_t *recalc_pressure_nodes) {
984 // Already "sorted" are the block start Node (as the first entry), and
985 // the block-ending Node and any trailing control projections. We leave
986 // these alone. PhiNodes and ParmNodes are made to follow the block start
987 // Node. Everything else gets topo-sorted.
988
989 #ifndef PRODUCT
990 if (trace_opto_pipelining()) {
991 tty->print_cr("# --- schedule_local B%d, before: ---", block->_pre_order);
992 for (uint i = 0;i < block->number_of_nodes(); i++) {
993 tty->print("# ");
994 block->get_node(i)->dump();
995 }
996 tty->print_cr("#");
997 }
998 #endif
999
1000 // RootNode is already sorted
1001 if (block->number_of_nodes() == 1) {
1002 return true;
1003 }
1004
1005 bool block_size_threshold_ok = (recalc_pressure_nodes != nullptr) && (block->number_of_nodes() > 10);
1006
1007 // We track the uses of local definitions as input dependences so that
1008 // we know when a given instruction is available to be scheduled.
1009 uint i;
1010 if (OptoRegScheduling && block_size_threshold_ok) {
1011 for (i = 1; i < block->number_of_nodes(); i++) { // setup nodes for pressure calc
1012 Node *n = block->get_node(i);
1013 n->remove_flag(Node::Flag_is_scheduled);
1014 if (!n->is_Phi()) {
1015 recalc_pressure_nodes[n->_idx] = 0x7fff7fff;
1016 }
1017 }
1018 }
1019
1020 // Move PhiNodes and ParmNodes from 1 to cnt up to the start
1021 uint node_cnt = block->end_idx();
1022 uint phi_cnt = 1;
1023 for( i = 1; i<node_cnt; i++ ) { // Scan for Phi
1024 Node *n = block->get_node(i);
1025 if( n->is_Phi() || // Found a PhiNode or ParmNode
1026 (n->is_Proj() && n->in(0) == block->head()) ) {
1027 // Move guy at 'phi_cnt' to the end; makes a hole at phi_cnt
1028 block->map_node(block->get_node(phi_cnt), i);
1029 block->map_node(n, phi_cnt++); // swap Phi/Parm up front
1030 if (OptoRegScheduling && block_size_threshold_ok) {
1031 // mark n as scheduled
1032 n->add_flag(Node::Flag_is_scheduled);
1033 }
1034 } else { // All others
1035 // Count block-local inputs to 'n'
1036 uint cnt = n->len(); // Input count
1037 uint local = 0;
1038 for( uint j=0; j<cnt; j++ ) {
1039 Node *m = n->in(j);
1040 if( m && get_block_for_node(m) == block && !m->is_top() )
1041 local++; // One more block-local input
1042 }
1043 ready_cnt.at_put(n->_idx, local); // Count em up
1044 // A few node types require changing a required edge to a precedence edge
1045 // before allocation.
1046 if( n->is_Mach() && n->req() > TypeFunc::Parms &&
1047 (n->as_Mach()->ideal_Opcode() == Op_MemBarAcquire ||
1048 n->as_Mach()->ideal_Opcode() == Op_MemBarVolatile) ) {
1049 // MemBarAcquire could be created without Precedent edge.
1050 // del_req() replaces the specified edge with the last input edge
1051 // and then removes the last edge. If the specified edge > number of
1052 // edges the last edge will be moved outside of the input edges array
1053 // and the edge will be lost. This is why this code should be
1054 // executed only when Precedent (== TypeFunc::Parms) edge is present.
1055 Node *x = n->in(TypeFunc::Parms);
1056 if (x != nullptr && get_block_for_node(x) == block && n->find_prec_edge(x) != -1) {
1057 // Old edge to node within same block will get removed, but no precedence
1058 // edge will get added because it already exists. Update ready count.
1059 int cnt = ready_cnt.at(n->_idx);
1060 assert(cnt > 1, "MemBar node %d must not get ready here", n->_idx);
1061 ready_cnt.at_put(n->_idx, cnt-1);
1062 }
1063 n->del_req(TypeFunc::Parms);
1064 n->add_prec(x);
1065 }
1066 }
1067 }
1068 for(uint i2=i; i2< block->number_of_nodes(); i2++ ) // Trailing guys get zapped count
1069 ready_cnt.at_put(block->get_node(i2)->_idx, 0);
1070
1071 // All the prescheduled guys do not hold back internal nodes
1072 uint i3;
1073 for (i3 = 0; i3 < phi_cnt; i3++) { // For all pre-scheduled
1074 Node *n = block->get_node(i3); // Get pre-scheduled
1075 for (DUIterator_Fast jmax, j = n->fast_outs(jmax); j < jmax; j++) {
1076 Node* m = n->fast_out(j);
1077 if (get_block_for_node(m) == block) { // Local-block user
1078 int m_cnt = ready_cnt.at(m->_idx)-1;
1079 if (OptoRegScheduling && block_size_threshold_ok) {
1080 // mark m as scheduled
1081 if (m_cnt < 0) {
1082 m->add_flag(Node::Flag_is_scheduled);
1083 }
1084 }
1085 ready_cnt.at_put(m->_idx, m_cnt); // Fix ready count
1086 }
1087 }
1088 }
1089
1090 Node_List delay;
1091 // Make a worklist
1092 Node_List worklist;
1093 for(uint i4=i3; i4<node_cnt; i4++ ) { // Put ready guys on worklist
1094 Node *m = block->get_node(i4);
1095 if( !ready_cnt.at(m->_idx) ) { // Zero ready count?
1096 if (m->is_iteratively_computed()) {
1097 // Push induction variable increments last to allow other uses
1098 // of the phi to be scheduled first. The select() method breaks
1099 // ties in scheduling by worklist order.
1100 delay.push(m);
1101 } else if (m->is_Mach() && m->as_Mach()->ideal_Opcode() == Op_CreateEx) {
1102 // Place CreateEx nodes that are initially ready at the beginning of the
1103 // worklist so they are selected first and scheduled at the block start.
1104 worklist.insert(0, m);
1105 } else {
1106 worklist.push(m); // Then on to worklist!
1107 }
1108 }
1109 }
1110 while (delay.size()) {
1111 Node* d = delay.pop();
1112 worklist.push(d);
1113 }
1114
1115 if (OptoRegScheduling && block_size_threshold_ok) {
1116 // To stage register pressure calculations we need to examine the live set variables
1117 // breaking them up by register class to compartmentalize the calculations.
1118 _regalloc->_sched_int_pressure.init(Matcher::int_pressure_limit());
1119 _regalloc->_sched_float_pressure.init(Matcher::float_pressure_limit());
1120 _regalloc->_scratch_int_pressure.init(Matcher::int_pressure_limit());
1121 _regalloc->_scratch_float_pressure.init(Matcher::float_pressure_limit());
1122
1123 _regalloc->compute_entry_block_pressure(block);
1124 }
1125
1126 // Warm up the 'next_call' heuristic bits
1127 needed_for_next_call(block, block->head(), next_call);
1128
1129 #ifndef PRODUCT
1130 if (trace_opto_pipelining()) {
1131 for (uint j=0; j< block->number_of_nodes(); j++) {
1132 Node *n = block->get_node(j);
1133 int idx = n->_idx;
1134 tty->print("# ready cnt:%3d ", ready_cnt.at(idx));
1135 tty->print("latency:%3d ", get_latency_for_node(n));
1136 tty->print("%4d: %s\n", idx, n->Name());
1137 }
1138 }
1139 #endif
1140
1141 uint max_idx = (uint)ready_cnt.length();
1142 // Pull from worklist and schedule
1143 while( worklist.size() ) { // Worklist is not ready
1144
1145 #ifndef PRODUCT
1146 if (trace_opto_pipelining()) {
1147 tty->print("# ready list:");
1148 for( uint i=0; i<worklist.size(); i++ ) { // Inspect entire worklist
1149 Node *n = worklist[i]; // Get Node on worklist
1150 tty->print(" %d", n->_idx);
1151 }
1152 tty->cr();
1153 }
1154 #endif
1155
1156 // Select and pop a ready guy from worklist
1157 Node* n = select(block, worklist, ready_cnt, next_call, phi_cnt, recalc_pressure_nodes);
1158 block->map_node(n, phi_cnt++); // Schedule him next
1159
1160 if (OptoRegScheduling && block_size_threshold_ok) {
1161 n->add_flag(Node::Flag_is_scheduled);
1162
1163 // Now adjust the resister pressure with the node we selected
1164 if (!n->is_Phi()) {
1165 adjust_register_pressure(n, block, recalc_pressure_nodes, true);
1166 }
1167 }
1168
1169 #ifndef PRODUCT
1170 if (trace_opto_pipelining()) {
1171 tty->print("# select %d: %s", n->_idx, n->Name());
1172 tty->print(", latency:%d", get_latency_for_node(n));
1173 n->dump();
1174 if (Verbose) {
1175 tty->print("# ready list:");
1176 for( uint i=0; i<worklist.size(); i++ ) { // Inspect entire worklist
1177 Node *n = worklist[i]; // Get Node on worklist
1178 tty->print(" %d", n->_idx);
1179 }
1180 tty->cr();
1181 }
1182 }
1183
1184 #endif
1185 if( n->is_MachCall() ) {
1186 MachCallNode *mcall = n->as_MachCall();
1187 phi_cnt = sched_call(block, phi_cnt, worklist, ready_cnt, mcall, next_call);
1188 continue;
1189 }
1190
1191 if (n->is_Mach() && n->as_Mach()->has_call()) {
1192 RegMask regs;
1193 regs.insert(_matcher.c_frame_pointer());
1194 regs.or_with(n->out_RegMask());
1195
1196 MachProjNode* proj = new MachProjNode(n, 1, RegMask::EMPTY, MachProjNode::fat_proj);
1197 map_node_to_block(proj, block);
1198 block->insert_node(proj, phi_cnt++);
1199
1200 add_call_kills(proj, regs, _matcher._c_reg_save_policy, false);
1201 }
1202
1203 // Children are now all ready
1204 for (DUIterator_Fast i5max, i5 = n->fast_outs(i5max); i5 < i5max; i5++) {
1205 Node* m = n->fast_out(i5); // Get user
1206 if (get_block_for_node(m) != block) {
1207 continue;
1208 }
1209 if( m->is_Phi() ) continue;
1210 if (m->_idx >= max_idx) { // new node, skip it
1211 assert(m->is_MachProj() && n->is_Mach() && n->as_Mach()->has_call(), "unexpected node types");
1212 continue;
1213 }
1214 int m_cnt = ready_cnt.at(m->_idx) - 1;
1215 ready_cnt.at_put(m->_idx, m_cnt);
1216 if( m_cnt == 0 )
1217 worklist.push(m);
1218 }
1219 }
1220
1221 if( phi_cnt != block->end_idx() ) {
1222 // did not schedule all. Retry, Bailout, or Die
1223 if (C->subsume_loads() == true && !C->failing()) {
1224 // Retry with subsume_loads == false
1225 // If this is the first failure, the sentinel string will "stick"
1226 // to the Compile object, and the C2Compiler will see it and retry.
1227 C->record_failure(C2Compiler::retry_no_subsuming_loads());
1228 } else {
1229 assert(C->failure_is_artificial(), "graph should be schedulable");
1230 }
1231 // assert( phi_cnt == end_idx(), "did not schedule all" );
1232 return false;
1233 }
1234
1235 if (OptoRegScheduling && block_size_threshold_ok) {
1236 _regalloc->compute_exit_block_pressure(block);
1237 block->_reg_pressure = _regalloc->_sched_int_pressure.final_pressure();
1238 block->_freg_pressure = _regalloc->_sched_float_pressure.final_pressure();
1239 }
1240
1241 #ifndef PRODUCT
1242 if (trace_opto_pipelining()) {
1243 tty->print_cr("#");
1244 tty->print_cr("# after schedule_local");
1245 for (uint i = 0;i < block->number_of_nodes();i++) {
1246 tty->print("# ");
1247 block->get_node(i)->dump();
1248 }
1249 tty->print_cr("# ");
1250
1251 if (OptoRegScheduling && block_size_threshold_ok) {
1252 tty->print_cr("# pressure info : %d", block->_pre_order);
1253 _regalloc->print_pressure_info(_regalloc->_sched_int_pressure, "int register info");
1254 _regalloc->print_pressure_info(_regalloc->_sched_float_pressure, "float register info");
1255 }
1256 tty->cr();
1257 }
1258 #endif
1259
1260 return true;
1261 }
1262
1263 //--------------------------catch_cleanup_fix_all_inputs-----------------------
1264 static void catch_cleanup_fix_all_inputs(Node *use, Node *old_def, Node *new_def) {
1265 for (uint l = 0; l < use->len(); l++) {
1266 if (use->in(l) == old_def) {
1267 if (l < use->req()) {
1268 use->set_req(l, new_def);
1269 } else {
1270 use->rm_prec(l);
1271 use->add_prec(new_def);
1272 l--;
1273 }
1274 }
1275 }
1276 }
1277
1278 //------------------------------catch_cleanup_find_cloned_def------------------
1279 Node* PhaseCFG::catch_cleanup_find_cloned_def(Block *use_blk, Node *def, Block *def_blk, int n_clone_idx) {
1280 assert( use_blk != def_blk, "Inter-block cleanup only");
1281
1282 // The use is some block below the Catch. Find and return the clone of the def
1283 // that dominates the use. If there is no clone in a dominating block, then
1284 // create a phi for the def in a dominating block.
1285
1286 // Find which successor block dominates this use. The successor
1287 // blocks must all be single-entry (from the Catch only; I will have
1288 // split blocks to make this so), hence they all dominate.
1289 while( use_blk->_dom_depth > def_blk->_dom_depth+1 )
1290 use_blk = use_blk->_idom;
1291
1292 // Find the successor
1293 Node *fixup = nullptr;
1294
1295 uint j;
1296 for( j = 0; j < def_blk->_num_succs; j++ )
1297 if( use_blk == def_blk->_succs[j] )
1298 break;
1299
1300 if( j == def_blk->_num_succs ) {
1301 // Block at same level in dom-tree is not a successor. It needs a
1302 // PhiNode, the PhiNode uses from the def and IT's uses need fixup.
1303 Node_Array inputs;
1304 for(uint k = 1; k < use_blk->num_preds(); k++) {
1305 Block* block = get_block_for_node(use_blk->pred(k));
1306 inputs.map(k, catch_cleanup_find_cloned_def(block, def, def_blk, n_clone_idx));
1307 }
1308
1309 // Check to see if the use_blk already has an identical phi inserted.
1310 // If it exists, it will be at the first position since all uses of a
1311 // def are processed together.
1312 Node *phi = use_blk->get_node(1);
1313 if( phi->is_Phi() ) {
1314 fixup = phi;
1315 for (uint k = 1; k < use_blk->num_preds(); k++) {
1316 if (phi->in(k) != inputs[k]) {
1317 // Not a match
1318 fixup = nullptr;
1319 break;
1320 }
1321 }
1322 }
1323
1324 // If an existing PhiNode was not found, make a new one.
1325 if (fixup == nullptr) {
1326 Node *new_phi = PhiNode::make(use_blk->head(), def);
1327 use_blk->insert_node(new_phi, 1);
1328 map_node_to_block(new_phi, use_blk);
1329 for (uint k = 1; k < use_blk->num_preds(); k++) {
1330 new_phi->set_req(k, inputs[k]);
1331 }
1332 fixup = new_phi;
1333 }
1334
1335 } else {
1336 // Found the use just below the Catch. Make it use the clone.
1337 fixup = use_blk->get_node(n_clone_idx);
1338 }
1339
1340 return fixup;
1341 }
1342
1343 //--------------------------catch_cleanup_intra_block--------------------------
1344 // Fix all input edges in use that reference "def". The use is in the same
1345 // block as the def and both have been cloned in each successor block.
1346 static void catch_cleanup_intra_block(Node *use, Node *def, Block *blk, int beg, int n_clone_idx) {
1347
1348 // Both the use and def have been cloned. For each successor block,
1349 // get the clone of the use, and make its input the clone of the def
1350 // found in that block.
1351
1352 uint use_idx = blk->find_node(use);
1353 uint offset_idx = use_idx - beg;
1354 for( uint k = 0; k < blk->_num_succs; k++ ) {
1355 // Get clone in each successor block
1356 Block *sb = blk->_succs[k];
1357 Node *clone = sb->get_node(offset_idx+1);
1358 assert( clone->Opcode() == use->Opcode(), "" );
1359
1360 // Make use-clone reference the def-clone
1361 catch_cleanup_fix_all_inputs(clone, def, sb->get_node(n_clone_idx));
1362 }
1363 }
1364
1365 //------------------------------catch_cleanup_inter_block---------------------
1366 // Fix all input edges in use that reference "def". The use is in a different
1367 // block than the def.
1368 void PhaseCFG::catch_cleanup_inter_block(Node *use, Block *use_blk, Node *def, Block *def_blk, int n_clone_idx) {
1369 if( !use_blk ) return; // Can happen if the use is a precedence edge
1370
1371 Node *new_def = catch_cleanup_find_cloned_def(use_blk, def, def_blk, n_clone_idx);
1372 catch_cleanup_fix_all_inputs(use, def, new_def);
1373 }
1374
1375 //------------------------------call_catch_cleanup-----------------------------
1376 // If we inserted any instructions between a Call and his CatchNode,
1377 // clone the instructions on all paths below the Catch.
1378 void PhaseCFG::call_catch_cleanup(Block* block) {
1379
1380 // End of region to clone
1381 uint end = block->end_idx();
1382 if( !block->get_node(end)->is_Catch() ) return;
1383 // Start of region to clone
1384 uint beg = end;
1385 while(!block->get_node(beg-1)->is_MachProj() ||
1386 !block->get_node(beg-1)->in(0)->is_MachCall() ) {
1387 beg--;
1388 assert(beg > 0,"Catch cleanup walking beyond block boundary");
1389 }
1390 // Range of inserted instructions is [beg, end)
1391 if( beg == end ) return;
1392
1393 // Clone along all Catch output paths. Clone area between the 'beg' and
1394 // 'end' indices.
1395 for( uint i = 0; i < block->_num_succs; i++ ) {
1396 Block *sb = block->_succs[i];
1397 // Clone the entire area; ignoring the edge fixup for now.
1398 for( uint j = end; j > beg; j-- ) {
1399 Node *clone = block->get_node(j-1)->clone();
1400 sb->insert_node(clone, 1);
1401 map_node_to_block(clone, sb);
1402 if (clone->needs_anti_dependence_check()) {
1403 raise_above_anti_dependences(sb, clone);
1404 if (C->failing()) {
1405 return;
1406 }
1407 }
1408 }
1409 }
1410
1411
1412 // Fixup edges. Check the def-use info per cloned Node
1413 for(uint i2 = beg; i2 < end; i2++ ) {
1414 uint n_clone_idx = i2-beg+1; // Index of clone of n in each successor block
1415 Node *n = block->get_node(i2); // Node that got cloned
1416 // Need DU safe iterator because of edge manipulation in calls.
1417 Unique_Node_List* out = new Unique_Node_List();
1418 for (DUIterator_Fast j1max, j1 = n->fast_outs(j1max); j1 < j1max; j1++) {
1419 out->push(n->fast_out(j1));
1420 }
1421 uint max = out->size();
1422 for (uint j = 0; j < max; j++) {// For all users
1423 Node *use = out->pop();
1424 Block *buse = get_block_for_node(use);
1425 if( use->is_Phi() ) {
1426 for( uint k = 1; k < use->req(); k++ )
1427 if( use->in(k) == n ) {
1428 Block* b = get_block_for_node(buse->pred(k));
1429 Node *fixup = catch_cleanup_find_cloned_def(b, n, block, n_clone_idx);
1430 use->set_req(k, fixup);
1431 }
1432 } else {
1433 if (block == buse) {
1434 catch_cleanup_intra_block(use, n, block, beg, n_clone_idx);
1435 } else {
1436 catch_cleanup_inter_block(use, buse, n, block, n_clone_idx);
1437 }
1438 }
1439 } // End for all users
1440
1441 } // End of for all Nodes in cloned area
1442
1443 // Remove the now-dead cloned ops
1444 for(uint i3 = beg; i3 < end; i3++ ) {
1445 block->get_node(beg)->disconnect_inputs(C);
1446 block->remove_node(beg);
1447 }
1448
1449 // If the successor blocks have a CreateEx node, move it back to the top
1450 for (uint i4 = 0; i4 < block->_num_succs; i4++) {
1451 Block *sb = block->_succs[i4];
1452 uint new_cnt = end - beg;
1453 // Remove any newly created, but dead, nodes by traversing their schedule
1454 // backwards. Here, a dead node is a node whose only outputs (if any) are
1455 // unused projections.
1456 for (uint j = new_cnt; j > 0; j--) {
1457 Node *n = sb->get_node(j);
1458 // Individual projections are examined together with all siblings when
1459 // their parent is visited.
1460 if (n->is_Proj()) {
1461 continue;
1462 }
1463 bool dead = true;
1464 for (DUIterator_Fast imax, i = n->fast_outs(imax); i < imax; i++) {
1465 Node* out = n->fast_out(i);
1466 // n is live if it has a non-projection output or a used projection.
1467 if (!out->is_Proj() || out->outcnt() > 0) {
1468 dead = false;
1469 break;
1470 }
1471 }
1472 if (dead) {
1473 // n's only outputs (if any) are unused projections scheduled next to n
1474 // (see PhaseCFG::select()). Remove these projections backwards.
1475 for (uint k = j + n->outcnt(); k > j; k--) {
1476 Node* proj = sb->get_node(k);
1477 assert(proj->is_Proj() && proj->in(0) == n,
1478 "projection should correspond to dead node");
1479 proj->disconnect_inputs(C);
1480 sb->remove_node(k);
1481 new_cnt--;
1482 }
1483 // Now remove the node itself.
1484 n->disconnect_inputs(C);
1485 sb->remove_node(j);
1486 new_cnt--;
1487 }
1488 }
1489 // If any newly created nodes remain, move the CreateEx node to the top
1490 if (new_cnt > 0) {
1491 Node *cex = sb->get_node(1+new_cnt);
1492 if( cex->is_Mach() && cex->as_Mach()->ideal_Opcode() == Op_CreateEx ) {
1493 sb->remove_node(1+new_cnt);
1494 sb->insert_node(cex, 1);
1495 }
1496 }
1497 }
1498 }