1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "gc/shared/barrierSet.hpp"
26 #include "gc/shared/c2/barrierSetC2.hpp"
27 #include "gc/shared/collectedHeap.hpp"
28 #include "memory/universe.hpp"
29 #include "oops/compressedOops.hpp"
30 #include "opto/machnode.hpp"
31 #include "opto/output.hpp"
32 #include "opto/regalloc.hpp"
33 #include "utilities/vmError.hpp"
34
35 //=============================================================================
36 // Return the value requested
37 // result register lookup, corresponding to int_format
38 int MachOper::reg(PhaseRegAlloc *ra_, const Node *node) const {
39 return (int)ra_->get_encode(node);
40 }
41 // input register lookup, corresponding to ext_format
42 int MachOper::reg(PhaseRegAlloc *ra_, const Node *node, int idx) const {
43 return (int)(ra_->get_encode(node->in(idx)));
44 }
45 intptr_t MachOper::constant() const { return 0x00; }
46 relocInfo::relocType MachOper::constant_reloc() const { return relocInfo::none; }
47 jdouble MachOper::constantD() const { ShouldNotReachHere(); }
48 jfloat MachOper::constantF() const { ShouldNotReachHere(); }
49 jshort MachOper::constantH() const { ShouldNotReachHere(); }
50 jlong MachOper::constantL() const { ShouldNotReachHere(); }
51 TypeOopPtr *MachOper::oop() const { return nullptr; }
52 int MachOper::ccode() const { return 0x00; }
53 // A zero, default, indicates this value is not needed.
54 // May need to lookup the base register, as done in int_ and ext_format
55 int MachOper::base (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
56 int MachOper::index(PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
57 int MachOper::scale() const { return 0x00; }
58 int MachOper::disp (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
59 int MachOper::constant_disp() const { return 0; }
60 int MachOper::base_position() const { return -1; } // no base input
61 int MachOper::index_position() const { return -1; } // no index input
62 // Check for PC-Relative displacement
63 relocInfo::relocType MachOper::disp_reloc() const { return relocInfo::none; }
64 // Return the label
65 Label* MachOper::label() const { ShouldNotReachHere(); }
66 intptr_t MachOper::method() const { ShouldNotReachHere(); }
67
68
69 //------------------------------negate-----------------------------------------
70 // Negate conditional branches. Error for non-branch operands
71 void MachOper::negate() {
72 ShouldNotCallThis();
73 }
74
75 //-----------------------------type--------------------------------------------
76 const Type *MachOper::type() const {
77 return Type::BOTTOM;
78 }
79
80 //------------------------------in_RegMask-------------------------------------
81 const RegMask *MachOper::in_RegMask(int index) const {
82 ShouldNotReachHere();
83 }
84
85 //------------------------------dump_spec--------------------------------------
86 // Print any per-operand special info
87 #ifndef PRODUCT
88 void MachOper::dump_spec(outputStream *st) const { }
89 #endif
90
91 //------------------------------hash-------------------------------------------
92 // Print any per-operand special info
93 uint MachOper::hash() const {
94 ShouldNotCallThis();
95 }
96
97 //------------------------------cmp--------------------------------------------
98 // Print any per-operand special info
99 bool MachOper::cmp( const MachOper &oper ) const {
100 ShouldNotCallThis();
101 }
102
103 //------------------------------hash-------------------------------------------
104 // Print any per-operand special info
105 uint labelOper::hash() const {
106 return _block_num;
107 }
108
109 //------------------------------cmp--------------------------------------------
110 // Print any per-operand special info
111 bool labelOper::cmp( const MachOper &oper ) const {
112 return (opcode() == oper.opcode()) && (_label == oper.label());
113 }
114
115 //------------------------------hash-------------------------------------------
116 // Print any per-operand special info
117 uint methodOper::hash() const {
118 return (uint)_method;
119 }
120
121 //------------------------------cmp--------------------------------------------
122 // Print any per-operand special info
123 bool methodOper::cmp( const MachOper &oper ) const {
124 return (opcode() == oper.opcode()) && (_method == oper.method());
125 }
126
127
128 //=============================================================================
129 //------------------------------MachNode---------------------------------------
130
131 //------------------------------emit-------------------------------------------
132 void MachNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
133 #ifdef ASSERT
134 tty->print("missing MachNode emit function: ");
135 dump();
136 #endif
137 ShouldNotCallThis();
138 }
139
140 //---------------------------postalloc_expand----------------------------------
141 // Expand node after register allocation.
142 void MachNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {}
143
144 //------------------------------size-------------------------------------------
145 // Size of instruction in bytes
146 uint MachNode::size(PhaseRegAlloc *ra_) const {
147 // If a virtual was not defined for this specific instruction,
148 // Call the helper which finds the size by emitting the bits.
149 return MachNode::emit_size(ra_);
150 }
151
152 //------------------------------size-------------------------------------------
153 // Helper function that computes size by emitting code
154 uint MachNode::emit_size(PhaseRegAlloc *ra_) const {
155 // Emit into a trash buffer and count bytes emitted.
156 assert(ra_ == ra_->C->regalloc(), "sanity");
157 return ra_->C->output()->scratch_emit_size(this);
158 }
159
160
161
162 //------------------------------hash-------------------------------------------
163 uint MachNode::hash() const {
164 uint no = num_opnds();
165 uint sum = rule();
166 for( uint i=0; i<no; i++ )
167 sum += _opnds[i]->hash();
168 return sum+Node::hash();
169 }
170
171 //-----------------------------cmp---------------------------------------------
172 bool MachNode::cmp( const Node &node ) const {
173 MachNode& n = *((Node&)node).as_Mach();
174 uint no = num_opnds();
175 if( no != n.num_opnds() ) return false;
176 if( rule() != n.rule() ) return false;
177 for( uint i=0; i<no; i++ ) // All operands must match
178 if( !_opnds[i]->cmp( *n._opnds[i] ) )
179 return false; // mis-matched operands
180 return true; // match
181 }
182
183 void MachNode::fill_new_machnode(MachNode* node) const {
184 // New node must use same node index
185 node->set_idx(_idx);
186 // Copy machine-independent inputs
187 for (uint j = 0; j < req(); j++) {
188 node->add_req(in(j));
189 }
190 // Copy my operands, except for cisc position
191 int nopnds = num_opnds();
192 assert(node->num_opnds() == (uint)nopnds, "Must have same number of operands");
193 MachOper** to = node->_opnds;
194 for (int i = 0; i < nopnds; i++) {
195 if (i != cisc_operand()) {
196 to[i] = _opnds[i]->clone();
197 }
198 }
199 // Do not increment node index counter, since node reuses my index
200 Compile* C = Compile::current();
201 C->set_unique(C->unique() - 1);
202 }
203
204 // Return an equivalent instruction using memory for cisc_operand position
205 MachNode *MachNode::cisc_version(int offset) {
206 ShouldNotCallThis();
207 }
208
209 void MachNode::use_cisc_RegMask() {
210 ShouldNotReachHere();
211 }
212
213
214 //-----------------------------in_RegMask--------------------------------------
215 const RegMask &MachNode::in_RegMask( uint idx ) const {
216 uint numopnds = num_opnds(); // Virtual call for number of operands
217 uint skipped = oper_input_base(); // Sum of leaves skipped so far
218 if( idx < skipped ) {
219 assert( ideal_Opcode() == Op_AddP, "expected base ptr here" );
220 assert( idx == 1, "expected base ptr here" );
221 // debug info can be anywhere
222 return *Compile::current()->matcher()->idealreg2spillmask[Op_RegP];
223 }
224 uint opcnt = 1; // First operand
225 uint num_edges = _opnds[1]->num_edges(); // leaves for first operand
226 while( idx >= skipped+num_edges ) {
227 skipped += num_edges;
228 opcnt++; // Bump operand count
229 assert( opcnt < numopnds, "Accessing non-existent operand" );
230 num_edges = _opnds[opcnt]->num_edges(); // leaves for next operand
231 }
232
233 const RegMask *rm = cisc_RegMask();
234 if( rm == nullptr || (int)opcnt != cisc_operand() ) {
235 rm = _opnds[opcnt]->in_RegMask(idx-skipped);
236 }
237 return *rm;
238 }
239
240 //-----------------------------memory_inputs--------------------------------
241 const MachOper* MachNode::memory_inputs(Node* &base, Node* &index) const {
242 const MachOper* oper = memory_operand();
243
244 if (oper == (MachOper*)-1) {
245 base = NodeSentinel;
246 index = NodeSentinel;
247 } else {
248 base = nullptr;
249 index = nullptr;
250 if (oper != nullptr) {
251 // It has a unique memory operand. Find its index.
252 int oper_idx = num_opnds();
253 while (--oper_idx >= 0) {
254 if (_opnds[oper_idx] == oper) break;
255 }
256 int oper_pos = operand_index(oper_idx);
257 int base_pos = oper->base_position();
258 if (base_pos >= 0) {
259 base = _in[oper_pos+base_pos];
260 }
261 int index_pos = oper->index_position();
262 if (index_pos >= 0) {
263 index = _in[oper_pos+index_pos];
264 }
265 }
266 }
267
268 return oper;
269 }
270
271 //-----------------------------get_base_and_disp----------------------------
272 const Node* MachNode::get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const {
273
274 // Find the memory inputs using our helper function
275 Node* base;
276 Node* index;
277 const MachOper* oper = memory_inputs(base, index);
278
279 if (oper == nullptr) {
280 // Base has been set to null
281 offset = 0;
282 } else if (oper == (MachOper*)-1) {
283 // Base has been set to NodeSentinel
284 // There is not a unique memory use here. We will fall to AliasIdxBot.
285 offset = Type::OffsetBot;
286 } else {
287 // Base may be null, even if offset turns out to be != 0
288
289 intptr_t disp = oper->constant_disp();
290 int scale = oper->scale();
291 // Now we have collected every part of the ADLC MEMORY_INTER.
292 // See if it adds up to a base + offset.
293 if (index != nullptr) {
294 const Type* t_index = index->bottom_type();
295 if (t_index->isa_narrowoop() || t_index->isa_narrowklass()) { // EncodeN, LoadN, LoadConN, LoadNKlass,
296 // EncodeNKlass, LoadConNklass.
297 // Memory references through narrow oops have a
298 // funny base so grab the type from the index:
299 // [R12 + narrow_oop_reg<<3 + offset]
300 assert(base == nullptr, "Memory references through narrow oops have no base");
301 offset = disp;
302 adr_type = t_index->make_ptr()->add_offset(offset);
303 return nullptr;
304 } else if (!index->is_Con()) {
305 disp = Type::OffsetBot;
306 } else if (disp != Type::OffsetBot) {
307 const TypeX* ti = t_index->isa_intptr_t();
308 if (ti == nullptr) {
309 disp = Type::OffsetBot; // a random constant??
310 } else {
311 disp += ti->get_con() << scale;
312 }
313 }
314 }
315 offset = disp;
316
317 // In x86_32.ad, indOffset32X uses base==RegI and disp==RegP,
318 // this will prevent alias analysis without the following support:
319 // Lookup the TypePtr used by indOffset32X, a compile-time constant oop,
320 // Add the offset determined by the "base", or use Type::OffsetBot.
321 if( adr_type == TYPE_PTR_SENTINAL ) {
322 const TypePtr *t_disp = oper->disp_as_type(); // only not null for indOffset32X
323 if (t_disp != nullptr) {
324 offset = Type::OffsetBot;
325 const Type* t_base = base->bottom_type();
326 if (t_base->isa_intptr_t()) {
327 const TypeX *t_offset = t_base->is_intptr_t();
328 if( t_offset->is_con() ) {
329 offset = t_offset->get_con();
330 }
331 }
332 adr_type = t_disp->add_offset(offset);
333 } else if( base == nullptr && offset != 0 && offset != Type::OffsetBot ) {
334 // Use ideal type if it is oop ptr.
335 const TypePtr *tp = oper->type()->isa_ptr();
336 if( tp != nullptr) {
337 adr_type = tp;
338 }
339 }
340 }
341
342 }
343 return base;
344 }
345
346
347 //---------------------------------adr_type---------------------------------
348 const class TypePtr *MachNode::adr_type() const {
349 intptr_t offset = 0;
350 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // attempt computing adr_type
351 const Node *base = get_base_and_disp(offset, adr_type);
352 if( adr_type != TYPE_PTR_SENTINAL ) {
353 return adr_type; // get_base_and_disp has the answer
354 }
355
356 #ifdef ASSERT
357 if (base != nullptr && base->is_Mach() && base->as_Mach()->ideal_Opcode() == Op_VerifyVectorAlignment) {
358 // For VerifyVectorAlignment we just pass the type through
359 return base->bottom_type()->is_ptr();
360 }
361 #endif
362
363 // Direct addressing modes have no base node, simply an indirect
364 // offset, which is always to raw memory.
365 // %%%%% Someday we'd like to allow constant oop offsets which
366 // would let Intel load from static globals in 1 instruction.
367 // Currently Intel requires 2 instructions and a register temp.
368 if (base == nullptr) {
369 // null base, zero offset means no memory at all (a null pointer!)
370 if (offset == 0) {
371 return nullptr;
372 }
373 // null base, any offset means any pointer whatever
374 if (offset == Type::OffsetBot) {
375 return TypePtr::BOTTOM;
376 }
377 // %%% make offset be intptr_t
378 assert(!Universe::heap()->is_in(cast_to_oop(offset)), "must be a raw ptr");
379 return TypeRawPtr::BOTTOM;
380 }
381
382 // base of -1 with no particular offset means all of memory
383 if (base == NodeSentinel) return TypePtr::BOTTOM;
384
385 const Type* t = base->bottom_type();
386 if (t->isa_narrowoop() && CompressedOops::shift() == 0) {
387 // 32-bit unscaled narrow oop can be the base of any address expression
388 t = t->make_ptr();
389 }
390 if (t->isa_narrowklass() && CompressedKlassPointers::shift() == 0) {
391 // 32-bit unscaled narrow oop can be the base of any address expression
392 t = t->make_ptr();
393 }
394
395 if (t->isa_intptr_t() &&
396 #if !defined(AARCH64)
397 // AArch64 supports the addressing mode:
398 // [base, 0], in which [base] is converted from a long value
399 offset != 0 &&
400 #endif
401 offset != Type::OffsetBot) {
402 // We cannot assert that the offset does not look oop-ish here.
403 // Depending on the heap layout the cardmark base could land
404 // inside some oopish region. It definitely does for Win2K.
405 // The sum of cardmark-base plus shift-by-9-oop lands outside
406 // the oop-ish area but we can't assert for that statically.
407 return TypeRawPtr::BOTTOM;
408 }
409
410 const TypePtr *tp = t->isa_ptr();
411
412 // be conservative if we do not recognize the type
413 if (tp == nullptr) {
414 assert(false, "this path may produce not optimal code");
415 return TypePtr::BOTTOM;
416 }
417 assert(tp->base() != Type::AnyPtr, "not a bare pointer");
418
419 if (tp->isa_aryptr()) {
420 // In the case of a flat inline type array, each field has its
421 // own slice so we need to extract the field being accessed from
422 // the address computation
423 if (offset == Type::OffsetBot) {
424 Node* base;
425 Node* index;
426 const MachOper* oper = memory_inputs(base, index);
427 if (oper != (MachOper*)-1) {
428 offset = oper->constant_disp();
429 return tp->is_aryptr()->add_field_offset_and_offset(offset)->add_offset(Type::OffsetBot);
430 }
431 }
432 return tp->is_aryptr()->add_field_offset_and_offset(offset);
433 }
434
435 return tp->add_offset(offset);
436 }
437
438
439 //-----------------------------operand_index---------------------------------
440 int MachNode::operand_index(uint operand) const {
441 if (operand < 1) return -1;
442 assert(operand < num_opnds(), "oob");
443 if (_opnds[operand]->num_edges() == 0) return -1;
444
445 uint skipped = oper_input_base(); // Sum of leaves skipped so far
446 for (uint opcnt = 1; opcnt < operand; opcnt++) {
447 uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
448 skipped += num_edges;
449 }
450 return skipped;
451 }
452
453 int MachNode::operand_index(const MachOper *oper) const {
454 uint skipped = oper_input_base(); // Sum of leaves skipped so far
455 uint opcnt;
456 for (opcnt = 1; opcnt < num_opnds(); opcnt++) {
457 if (_opnds[opcnt] == oper) break;
458 uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
459 skipped += num_edges;
460 }
461 if (_opnds[opcnt] != oper) return -1;
462 return skipped;
463 }
464
465 int MachNode::operand_index(Node* def) const {
466 uint skipped = oper_input_base(); // Sum of leaves skipped so far
467 for (uint opcnt = 1; opcnt < num_opnds(); opcnt++) {
468 uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
469 for (uint i = 0; i < num_edges; i++) {
470 if (in(skipped + i) == def) {
471 return opcnt;
472 }
473 }
474 skipped += num_edges;
475 }
476 return -1;
477 }
478
479 //------------------------------peephole---------------------------------------
480 // Apply peephole rule(s) to this instruction
481 int MachNode::peephole(Block *block, int block_index, PhaseCFG* cfg_, PhaseRegAlloc *ra_) {
482 return -1;
483 }
484
485 //------------------------------add_case_label---------------------------------
486 // Adds the label for the case
487 void MachNode::add_case_label( int index_num, Label* blockLabel) {
488 ShouldNotCallThis();
489 }
490
491 //------------------------------method_set-------------------------------------
492 // Set the absolute address of a method
493 void MachNode::method_set( intptr_t addr ) {
494 ShouldNotCallThis();
495 }
496
497 //------------------------------rematerialize----------------------------------
498 bool MachNode::rematerialize() const {
499 // Never rematerialize CastI2N because it might "hide" narrow oops from a safepoint
500 if (ideal_Opcode() == Op_CastI2N) {
501 return false;
502 }
503
504 // Temps are always rematerializable
505 if (is_MachTemp()) return true;
506
507 uint r = rule(); // Match rule
508 if (r < Matcher::_begin_rematerialize ||
509 r >= Matcher::_end_rematerialize) {
510 return false;
511 }
512
513 // For 2-address instructions, the input live range is also the output
514 // live range. Remateralizing does not make progress on the that live range.
515 if (two_adr()) return false;
516
517 // Check for rematerializing float constants, or not
518 if (!Matcher::rematerialize_float_constants) {
519 int op = ideal_Opcode();
520 if (op == Op_ConF || op == Op_ConD) {
521 return false;
522 }
523 }
524
525 // Defining flags - can't spill these! Must remateralize.
526 if (ideal_reg() == Op_RegFlags) {
527 return true;
528 }
529
530 // Stretching lots of inputs - don't do it.
531 // A MachContant has the last input being the constant base
532 if (req() > (is_MachConstant() ? 3U : 2U)) {
533 return false;
534 }
535
536 if (req() >= 2 && in(1) && in(1)->ideal_reg() == Op_RegFlags) {
537 // In(1) will be rematerialized, too.
538 // Stretching lots of inputs - don't do it.
539 if (in(1)->req() > (in(1)->is_MachConstant() ? 3U : 2U)) {
540 return false;
541 }
542 }
543
544 // Don't remateralize somebody with bound inputs - it stretches a
545 // fixed register lifetime.
546 uint idx = oper_input_base();
547 if (req() > idx) {
548 const RegMask &rm = in_RegMask(idx);
549 if (rm.is_NotEmpty() && rm.is_bound(ideal_reg())) {
550 return false;
551 }
552 }
553
554 return true;
555 }
556
557 #ifndef PRODUCT
558 //------------------------------dump_spec--------------------------------------
559 // Print any per-operand special info
560 void MachNode::dump_spec(outputStream *st) const {
561 uint cnt = num_opnds();
562 for( uint i=0; i<cnt; i++ ) {
563 if (_opnds[i] != nullptr) {
564 _opnds[i]->dump_spec(st);
565 } else {
566 st->print(" _");
567 }
568 }
569 const TypePtr *t = adr_type();
570 if( t ) {
571 Compile* C = Compile::current();
572 if( C->alias_type(t)->is_volatile() )
573 st->print(" Volatile!");
574 }
575 if (barrier_data() != 0) {
576 st->print(" barrier(");
577 BarrierSet::barrier_set()->barrier_set_c2()->dump_barrier_data(this, st);
578 st->print(") ");
579 }
580 }
581
582 //------------------------------dump_format------------------------------------
583 // access to virtual
584 void MachNode::dump_format(PhaseRegAlloc *ra, outputStream *st) const {
585 format(ra, st); // access to virtual
586 }
587 #endif
588
589 //=============================================================================
590 #ifndef PRODUCT
591 void MachTypeNode::dump_spec(outputStream *st) const {
592 MachNode::dump_spec(st);
593 if (_bottom_type != nullptr) {
594 _bottom_type->dump_on(st);
595 } else {
596 st->print(" null");
597 }
598 }
599 #endif
600
601
602 //=============================================================================
603 int MachConstantNode::constant_offset() {
604 // Bind the offset lazily.
605 if (_constant.offset() == -1) {
606 ConstantTable& constant_table = Compile::current()->output()->constant_table();
607 int offset = constant_table.find_offset(_constant);
608 // If called from Compile::scratch_emit_size return the
609 // pre-calculated offset.
610 // NOTE: If the AD file does some table base offset optimizations
611 // later the AD file needs to take care of this fact.
612 if (Compile::current()->output()->in_scratch_emit_size()) {
613 return constant_table.calculate_table_base_offset() + offset;
614 }
615 _constant.set_offset(constant_table.table_base_offset() + offset);
616 }
617 return _constant.offset();
618 }
619
620 int MachConstantNode::constant_offset_unchecked() const {
621 return _constant.offset();
622 }
623
624 //=============================================================================
625 #ifndef PRODUCT
626 void MachNullCheckNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
627 int reg = ra_->get_reg_first(in(1)->in(_vidx));
628 st->print("%s %s", Name(), Matcher::regName[reg]);
629 }
630 #endif
631
632 void MachNullCheckNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
633 // only emits entries in the null-pointer exception handler table
634 }
635 void MachNullCheckNode::label_set(Label* label, uint block_num) {
636 // Nothing to emit
637 }
638 void MachNullCheckNode::save_label( Label** label, uint* block_num ) {
639 // Nothing to emit
640 }
641
642 const RegMask &MachNullCheckNode::in_RegMask( uint idx ) const {
643 if( idx == 0 ) return RegMask::Empty;
644 else return in(1)->as_Mach()->out_RegMask();
645 }
646
647 //=============================================================================
648 const Type *MachProjNode::bottom_type() const {
649 if( _ideal_reg == fat_proj ) return Type::BOTTOM;
650 // Try the normal mechanism first
651 const Type *t = in(0)->bottom_type();
652 if( t->base() == Type::Tuple ) {
653 const TypeTuple *tt = t->is_tuple();
654 if (_con < tt->cnt())
655 return tt->field_at(_con);
656 }
657 // Else use generic type from ideal register set
658 assert((uint)_ideal_reg < (uint)_last_machine_leaf && Type::mreg2type[_ideal_reg], "in bounds");
659 return Type::mreg2type[_ideal_reg];
660 }
661
662 const TypePtr *MachProjNode::adr_type() const {
663 if (bottom_type() == Type::MEMORY) {
664 // in(0) might be a narrow MemBar; otherwise we will report TypePtr::BOTTOM
665 Node* ctrl = in(0);
666 if (ctrl == nullptr) return nullptr; // node is dead
667 const TypePtr* adr_type = ctrl->adr_type();
668 #ifdef ASSERT
669 if (!VMError::is_error_reported() && !Node::in_dump())
670 assert(adr_type != nullptr, "source must have adr_type");
671 #endif
672 return adr_type;
673 }
674 assert(bottom_type()->base() != Type::Memory, "no other memories?");
675 return nullptr;
676 }
677
678 #ifndef PRODUCT
679 void MachProjNode::dump_spec(outputStream *st) const {
680 ProjNode::dump_spec(st);
681 switch (_ideal_reg) {
682 case unmatched_proj: st->print("/unmatched"); break;
683 case fat_proj: st->print("/fat"); if (WizardMode) _rout.dump(st); break;
684 }
685 }
686 #endif
687
688 //=============================================================================
689 #ifndef PRODUCT
690 void MachIfNode::dump_spec(outputStream *st) const {
691 st->print("P=%f, C=%f",_prob, _fcnt);
692 }
693 #endif
694
695 //=============================================================================
696 uint MachReturnNode::size_of() const { return sizeof(*this); }
697
698 //------------------------------Registers--------------------------------------
699 const RegMask &MachReturnNode::in_RegMask( uint idx ) const {
700 return _in_rms[idx];
701 }
702
703 const TypePtr *MachReturnNode::adr_type() const {
704 // most returns and calls are assumed to consume & modify all of memory
705 // the matcher will copy non-wide adr_types from ideal originals
706 return _adr_type;
707 }
708
709 //=============================================================================
710 const Type *MachSafePointNode::bottom_type() const { return TypeTuple::MEMBAR; }
711
712 //------------------------------Registers--------------------------------------
713 const RegMask &MachSafePointNode::in_RegMask( uint idx ) const {
714 // Values in the domain use the users calling convention, embodied in the
715 // _in_rms array of RegMasks.
716 if( idx < TypeFunc::Parms ) return _in_rms[idx];
717
718 if (idx == TypeFunc::Parms &&
719 ideal_Opcode() == Op_SafePoint) {
720 return MachNode::in_RegMask(idx);
721 }
722
723 // Values outside the domain represent debug info
724 assert(in(idx)->ideal_reg() != Op_RegFlags, "flags register is not spillable");
725 return *Compile::current()->matcher()->idealreg2spillmask[in(idx)->ideal_reg()];
726 }
727
728
729 //=============================================================================
730
731 bool MachCallNode::cmp( const Node &n ) const
732 { return _tf == ((MachCallNode&)n)._tf; }
733 const Type *MachCallNode::bottom_type() const { return tf()->range_cc(); }
734 const Type* MachCallNode::Value(PhaseGVN* phase) const { return tf()->range_cc(); }
735
736 #ifndef PRODUCT
737 void MachCallNode::dump_spec(outputStream *st) const {
738 st->print("# ");
739 if (tf() != nullptr) tf()->dump_on(st);
740 if (_cnt != COUNT_UNKNOWN) st->print(" C=%f",_cnt);
741 if (jvms() != nullptr) jvms()->dump_spec(st);
742 }
743 #endif
744
745 bool MachCallNode::return_value_is_used() const {
746 if (tf()->range_sig()->cnt() == TypeFunc::Parms) {
747 // void return
748 return false;
749 }
750
751 // find the projection corresponding to the return value
752 for (DUIterator_Fast imax, i = fast_outs(imax); i < imax; i++) {
753 Node *use = fast_out(i);
754 if (!use->is_Proj()) continue;
755 if (use->as_Proj()->_con == TypeFunc::Parms) {
756 return true;
757 }
758 }
759 return false;
760 }
761
762 // Similar to cousin class CallNode::returns_pointer
763 // Because this is used in deoptimization, we want the type info, not the data
764 // flow info; the interpreter will "use" things that are dead to the optimizer.
765 bool MachCallNode::returns_pointer() const {
766 const TypeTuple *r = tf()->range_sig();
767 return (r->cnt() > TypeFunc::Parms &&
768 r->field_at(TypeFunc::Parms)->isa_ptr());
769 }
770
771 bool MachCallNode::returns_scalarized() const {
772 return tf()->returns_inline_type_as_fields();
773 }
774
775 //------------------------------Registers--------------------------------------
776 const RegMask &MachCallNode::in_RegMask(uint idx) const {
777 // Values in the domain use the users calling convention, embodied in the
778 // _in_rms array of RegMasks.
779 if (entry_point() == nullptr && idx == TypeFunc::Parms) {
780 // Null entry point is a special cast where the target of the call
781 // is in a register.
782 return MachNode::in_RegMask(idx);
783 }
784 if (idx < tf()->domain_sig()->cnt()) {
785 return _in_rms[idx];
786 }
787 if (idx == mach_constant_base_node_input()) {
788 return MachConstantBaseNode::static_out_RegMask();
789 }
790 // Values outside the domain represent debug info
791 return *Compile::current()->matcher()->idealreg2debugmask[in(idx)->ideal_reg()];
792 }
793
794 //=============================================================================
795 uint MachCallJavaNode::size_of() const { return sizeof(*this); }
796 bool MachCallJavaNode::cmp( const Node &n ) const {
797 MachCallJavaNode &call = (MachCallJavaNode&)n;
798 return MachCallNode::cmp(call) && _method->equals(call._method) &&
799 _override_symbolic_info == call._override_symbolic_info;
800 }
801 #ifndef PRODUCT
802 void MachCallJavaNode::dump_spec(outputStream *st) const {
803 if (_method_handle_invoke)
804 st->print("MethodHandle ");
805 if (_method) {
806 _method->print_short_name(st);
807 st->print(" ");
808 }
809 MachCallNode::dump_spec(st);
810 }
811 #endif
812
813 //------------------------------Registers--------------------------------------
814 const RegMask &MachCallJavaNode::in_RegMask(uint idx) const {
815 // Values in the domain use the users calling convention, embodied in the
816 // _in_rms array of RegMasks.
817 if (idx < tf()->domain_cc()->cnt()) {
818 return _in_rms[idx];
819 }
820 if (idx == mach_constant_base_node_input()) {
821 return MachConstantBaseNode::static_out_RegMask();
822 }
823 // Values outside the domain represent debug info
824 Matcher* m = Compile::current()->matcher();
825 // If this call is a MethodHandle invoke we have to use a different
826 // debugmask which does not include the register we use to save the
827 // SP over MH invokes.
828 RegMask** debugmask = _method_handle_invoke ? m->idealreg2mhdebugmask : m->idealreg2debugmask;
829 return *debugmask[in(idx)->ideal_reg()];
830 }
831
832 //=============================================================================
833 uint MachCallStaticJavaNode::size_of() const { return sizeof(*this); }
834 bool MachCallStaticJavaNode::cmp( const Node &n ) const {
835 MachCallStaticJavaNode &call = (MachCallStaticJavaNode&)n;
836 return MachCallJavaNode::cmp(call) && _name == call._name;
837 }
838
839 //----------------------------uncommon_trap_request----------------------------
840 // If this is an uncommon trap, return the request code, else zero.
841 int MachCallStaticJavaNode::uncommon_trap_request() const {
842 if (_name != nullptr && !strcmp(_name, "uncommon_trap")) {
843 return CallStaticJavaNode::extract_uncommon_trap_request(this);
844 }
845 return 0;
846 }
847
848 #ifndef PRODUCT
849 // Helper for summarizing uncommon_trap arguments.
850 void MachCallStaticJavaNode::dump_trap_args(outputStream *st) const {
851 int trap_req = uncommon_trap_request();
852 if (trap_req != 0) {
853 char buf[100];
854 st->print("(%s)",
855 Deoptimization::format_trap_request(buf, sizeof(buf),
856 trap_req));
857 }
858 }
859
860 void MachCallStaticJavaNode::dump_spec(outputStream *st) const {
861 st->print("Static ");
862 if (_name != nullptr) {
863 st->print("wrapper for: %s", _name );
864 dump_trap_args(st);
865 st->print(" ");
866 }
867 MachCallJavaNode::dump_spec(st);
868 }
869 #endif
870
871 //=============================================================================
872 #ifndef PRODUCT
873 void MachCallDynamicJavaNode::dump_spec(outputStream *st) const {
874 st->print("Dynamic ");
875 MachCallJavaNode::dump_spec(st);
876 }
877 #endif
878 //=============================================================================
879 uint MachCallRuntimeNode::size_of() const { return sizeof(*this); }
880 bool MachCallRuntimeNode::cmp( const Node &n ) const {
881 MachCallRuntimeNode &call = (MachCallRuntimeNode&)n;
882 return MachCallNode::cmp(call) && !strcmp(_name,call._name);
883 }
884 #ifndef PRODUCT
885 void MachCallRuntimeNode::dump_spec(outputStream *st) const {
886 st->print("%s ",_name);
887 MachCallNode::dump_spec(st);
888 }
889 #endif
890 //=============================================================================
891 // A shared JVMState for all HaltNodes. Indicates the start of debug info
892 // is at TypeFunc::Parms. Only required for SOE register spill handling -
893 // to indicate where the stack-slot-only debug info inputs begin.
894 // There is no other JVM state needed here.
895 JVMState jvms_for_throw(0);
896 JVMState *MachHaltNode::jvms() const {
897 return &jvms_for_throw;
898 }
899
900 uint MachMemBarNode::size_of() const { return sizeof(*this); }
901
902 const TypePtr *MachMemBarNode::adr_type() const {
903 return _adr_type;
904 }
905
906
907 //=============================================================================
908 #ifndef PRODUCT
909 void labelOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
910 st->print("B%d", _block_num);
911 }
912 #endif // PRODUCT
913
914 //=============================================================================
915 #ifndef PRODUCT
916 void methodOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
917 st->print(INTPTR_FORMAT, _method);
918 }
919 #endif // PRODUCT