1 /*
2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "gc/shared/barrierSet.hpp"
27 #include "gc/shared/c2/barrierSetC2.hpp"
28 #include "gc/shared/collectedHeap.hpp"
29 #include "memory/universe.hpp"
30 #include "oops/compressedOops.hpp"
31 #include "opto/machnode.hpp"
32 #include "opto/output.hpp"
33 #include "opto/regalloc.hpp"
34 #include "utilities/vmError.hpp"
35
36 //=============================================================================
37 // Return the value requested
38 // result register lookup, corresponding to int_format
39 int MachOper::reg(PhaseRegAlloc *ra_, const Node *node) const {
40 return (int)ra_->get_encode(node);
41 }
42 // input register lookup, corresponding to ext_format
43 int MachOper::reg(PhaseRegAlloc *ra_, const Node *node, int idx) const {
44 return (int)(ra_->get_encode(node->in(idx)));
45 }
46 intptr_t MachOper::constant() const { return 0x00; }
47 relocInfo::relocType MachOper::constant_reloc() const { return relocInfo::none; }
48 jdouble MachOper::constantD() const { ShouldNotReachHere(); return 0.0; }
49 jfloat MachOper::constantF() const { ShouldNotReachHere(); return 0.0; }
50 jlong MachOper::constantL() const { ShouldNotReachHere(); return CONST64(0) ; }
51 TypeOopPtr *MachOper::oop() const { return nullptr; }
52 int MachOper::ccode() const { return 0x00; }
53 // A zero, default, indicates this value is not needed.
54 // May need to lookup the base register, as done in int_ and ext_format
55 int MachOper::base (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
56 int MachOper::index(PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
57 int MachOper::scale() const { return 0x00; }
58 int MachOper::disp (PhaseRegAlloc *ra_, const Node *node, int idx) const { return 0x00; }
59 int MachOper::constant_disp() const { return 0; }
60 int MachOper::base_position() const { return -1; } // no base input
61 int MachOper::index_position() const { return -1; } // no index input
62 // Check for PC-Relative displacement
63 relocInfo::relocType MachOper::disp_reloc() const { return relocInfo::none; }
64 // Return the label
65 Label* MachOper::label() const { ShouldNotReachHere(); return 0; }
66 intptr_t MachOper::method() const { ShouldNotReachHere(); return 0; }
67
68
69 //------------------------------negate-----------------------------------------
70 // Negate conditional branches. Error for non-branch operands
71 void MachOper::negate() {
72 ShouldNotCallThis();
73 }
74
75 //-----------------------------type--------------------------------------------
76 const Type *MachOper::type() const {
77 return Type::BOTTOM;
78 }
79
80 //------------------------------in_RegMask-------------------------------------
81 const RegMask *MachOper::in_RegMask(int index) const {
82 ShouldNotReachHere();
83 return nullptr;
84 }
85
86 //------------------------------dump_spec--------------------------------------
87 // Print any per-operand special info
88 #ifndef PRODUCT
89 void MachOper::dump_spec(outputStream *st) const { }
90 #endif
91
92 //------------------------------hash-------------------------------------------
93 // Print any per-operand special info
94 uint MachOper::hash() const {
95 ShouldNotCallThis();
96 return 5;
97 }
98
99 //------------------------------cmp--------------------------------------------
100 // Print any per-operand special info
101 bool MachOper::cmp( const MachOper &oper ) const {
102 ShouldNotCallThis();
103 return opcode() == oper.opcode();
104 }
105
106 //------------------------------hash-------------------------------------------
107 // Print any per-operand special info
108 uint labelOper::hash() const {
109 return _block_num;
110 }
111
112 //------------------------------cmp--------------------------------------------
113 // Print any per-operand special info
114 bool labelOper::cmp( const MachOper &oper ) const {
115 return (opcode() == oper.opcode()) && (_label == oper.label());
116 }
117
118 //------------------------------hash-------------------------------------------
119 // Print any per-operand special info
120 uint methodOper::hash() const {
121 return (uint)_method;
122 }
123
124 //------------------------------cmp--------------------------------------------
125 // Print any per-operand special info
126 bool methodOper::cmp( const MachOper &oper ) const {
127 return (opcode() == oper.opcode()) && (_method == oper.method());
128 }
129
130
131 //=============================================================================
132 //------------------------------MachNode---------------------------------------
133
134 //------------------------------emit-------------------------------------------
135 void MachNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
136 #ifdef ASSERT
137 tty->print("missing MachNode emit function: ");
138 dump();
139 #endif
140 ShouldNotCallThis();
141 }
142
143 //---------------------------postalloc_expand----------------------------------
144 // Expand node after register allocation.
145 void MachNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {}
146
147 //------------------------------size-------------------------------------------
148 // Size of instruction in bytes
149 uint MachNode::size(PhaseRegAlloc *ra_) const {
150 // If a virtual was not defined for this specific instruction,
151 // Call the helper which finds the size by emitting the bits.
152 return MachNode::emit_size(ra_);
153 }
154
155 //------------------------------size-------------------------------------------
156 // Helper function that computes size by emitting code
157 uint MachNode::emit_size(PhaseRegAlloc *ra_) const {
158 // Emit into a trash buffer and count bytes emitted.
159 assert(ra_ == ra_->C->regalloc(), "sanity");
160 return ra_->C->output()->scratch_emit_size(this);
161 }
162
163
164
165 //------------------------------hash-------------------------------------------
166 uint MachNode::hash() const {
167 uint no = num_opnds();
168 uint sum = rule();
169 for( uint i=0; i<no; i++ )
170 sum += _opnds[i]->hash();
171 return sum+Node::hash();
172 }
173
174 //-----------------------------cmp---------------------------------------------
175 bool MachNode::cmp( const Node &node ) const {
176 MachNode& n = *((Node&)node).as_Mach();
177 uint no = num_opnds();
178 if( no != n.num_opnds() ) return false;
179 if( rule() != n.rule() ) return false;
180 for( uint i=0; i<no; i++ ) // All operands must match
181 if( !_opnds[i]->cmp( *n._opnds[i] ) )
182 return false; // mis-matched operands
183 return true; // match
184 }
185
186 void MachNode::fill_new_machnode(MachNode* node) const {
187 // New node must use same node index
188 node->set_idx(_idx);
189 // Copy machine-independent inputs
190 for (uint j = 0; j < req(); j++) {
191 node->add_req(in(j));
192 }
193 // Copy my operands, except for cisc position
194 int nopnds = num_opnds();
195 assert(node->num_opnds() == (uint)nopnds, "Must have same number of operands");
196 MachOper** to = node->_opnds;
197 for (int i = 0; i < nopnds; i++) {
198 if (i != cisc_operand()) {
199 to[i] = _opnds[i]->clone();
200 }
201 }
202 // Do not increment node index counter, since node reuses my index
203 Compile* C = Compile::current();
204 C->set_unique(C->unique() - 1);
205 }
206
207 // Return an equivalent instruction using memory for cisc_operand position
208 MachNode *MachNode::cisc_version(int offset) {
209 ShouldNotCallThis();
210 return nullptr;
211 }
212
213 void MachNode::use_cisc_RegMask() {
214 ShouldNotReachHere();
215 }
216
217
218 //-----------------------------in_RegMask--------------------------------------
219 const RegMask &MachNode::in_RegMask( uint idx ) const {
220 uint numopnds = num_opnds(); // Virtual call for number of operands
221 uint skipped = oper_input_base(); // Sum of leaves skipped so far
222 if( idx < skipped ) {
223 assert( ideal_Opcode() == Op_AddP, "expected base ptr here" );
224 assert( idx == 1, "expected base ptr here" );
225 // debug info can be anywhere
226 return *Compile::current()->matcher()->idealreg2spillmask[Op_RegP];
227 }
228 uint opcnt = 1; // First operand
229 uint num_edges = _opnds[1]->num_edges(); // leaves for first operand
230 while( idx >= skipped+num_edges ) {
231 skipped += num_edges;
232 opcnt++; // Bump operand count
233 assert( opcnt < numopnds, "Accessing non-existent operand" );
234 num_edges = _opnds[opcnt]->num_edges(); // leaves for next operand
235 }
236
237 const RegMask *rm = cisc_RegMask();
238 if( rm == nullptr || (int)opcnt != cisc_operand() ) {
239 rm = _opnds[opcnt]->in_RegMask(idx-skipped);
240 }
241 return *rm;
242 }
243
244 //-----------------------------memory_inputs--------------------------------
245 const MachOper* MachNode::memory_inputs(Node* &base, Node* &index) const {
246 const MachOper* oper = memory_operand();
247
248 if (oper == (MachOper*)-1) {
249 base = NodeSentinel;
250 index = NodeSentinel;
251 } else {
252 base = nullptr;
253 index = nullptr;
254 if (oper != nullptr) {
255 // It has a unique memory operand. Find its index.
256 int oper_idx = num_opnds();
257 while (--oper_idx >= 0) {
258 if (_opnds[oper_idx] == oper) break;
259 }
260 int oper_pos = operand_index(oper_idx);
261 int base_pos = oper->base_position();
262 if (base_pos >= 0) {
263 base = _in[oper_pos+base_pos];
264 }
265 int index_pos = oper->index_position();
266 if (index_pos >= 0) {
267 index = _in[oper_pos+index_pos];
268 }
269 }
270 }
271
272 return oper;
273 }
274
275 //-----------------------------get_base_and_disp----------------------------
276 const Node* MachNode::get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const {
277
278 // Find the memory inputs using our helper function
279 Node* base;
280 Node* index;
281 const MachOper* oper = memory_inputs(base, index);
282
283 if (oper == nullptr) {
284 // Base has been set to null
285 offset = 0;
286 } else if (oper == (MachOper*)-1) {
287 // Base has been set to NodeSentinel
288 // There is not a unique memory use here. We will fall to AliasIdxBot.
289 offset = Type::OffsetBot;
290 } else {
291 // Base may be null, even if offset turns out to be != 0
292
293 intptr_t disp = oper->constant_disp();
294 int scale = oper->scale();
295 // Now we have collected every part of the ADLC MEMORY_INTER.
296 // See if it adds up to a base + offset.
297 if (index != nullptr) {
298 const Type* t_index = index->bottom_type();
299 if (t_index->isa_narrowoop() || t_index->isa_narrowklass()) { // EncodeN, LoadN, LoadConN, LoadNKlass,
300 // EncodeNKlass, LoadConNklass.
301 // Memory references through narrow oops have a
302 // funny base so grab the type from the index:
303 // [R12 + narrow_oop_reg<<3 + offset]
304 assert(base == nullptr, "Memory references through narrow oops have no base");
305 offset = disp;
306 adr_type = t_index->make_ptr()->add_offset(offset);
307 return nullptr;
308 } else if (!index->is_Con()) {
309 disp = Type::OffsetBot;
310 } else if (disp != Type::OffsetBot) {
311 const TypeX* ti = t_index->isa_intptr_t();
312 if (ti == nullptr) {
313 disp = Type::OffsetBot; // a random constant??
314 } else {
315 disp += ti->get_con() << scale;
316 }
317 }
318 }
319 offset = disp;
320
321 // In x86_32.ad, indOffset32X uses base==RegI and disp==RegP,
322 // this will prevent alias analysis without the following support:
323 // Lookup the TypePtr used by indOffset32X, a compile-time constant oop,
324 // Add the offset determined by the "base", or use Type::OffsetBot.
325 if( adr_type == TYPE_PTR_SENTINAL ) {
326 const TypePtr *t_disp = oper->disp_as_type(); // only not null for indOffset32X
327 if (t_disp != nullptr) {
328 offset = Type::OffsetBot;
329 const Type* t_base = base->bottom_type();
330 if (t_base->isa_intptr_t()) {
331 const TypeX *t_offset = t_base->is_intptr_t();
332 if( t_offset->is_con() ) {
333 offset = t_offset->get_con();
334 }
335 }
336 adr_type = t_disp->add_offset(offset);
337 } else if( base == nullptr && offset != 0 && offset != Type::OffsetBot ) {
338 // Use ideal type if it is oop ptr.
339 const TypePtr *tp = oper->type()->isa_ptr();
340 if( tp != nullptr) {
341 adr_type = tp;
342 }
343 }
344 }
345
346 }
347 return base;
348 }
349
350
351 //---------------------------------adr_type---------------------------------
352 const class TypePtr *MachNode::adr_type() const {
353 intptr_t offset = 0;
354 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // attempt computing adr_type
355 const Node *base = get_base_and_disp(offset, adr_type);
356 if( adr_type != TYPE_PTR_SENTINAL ) {
357 return adr_type; // get_base_and_disp has the answer
358 }
359
360 // Direct addressing modes have no base node, simply an indirect
361 // offset, which is always to raw memory.
362 // %%%%% Someday we'd like to allow constant oop offsets which
363 // would let Intel load from static globals in 1 instruction.
364 // Currently Intel requires 2 instructions and a register temp.
365 if (base == nullptr) {
366 // null base, zero offset means no memory at all (a null pointer!)
367 if (offset == 0) {
368 return nullptr;
369 }
370 // null base, any offset means any pointer whatever
371 if (offset == Type::OffsetBot) {
372 return TypePtr::BOTTOM;
373 }
374 // %%% make offset be intptr_t
375 assert(!Universe::heap()->is_in(cast_to_oop(offset)), "must be a raw ptr");
376 return TypeRawPtr::BOTTOM;
377 }
378
379 // base of -1 with no particular offset means all of memory
380 if (base == NodeSentinel) return TypePtr::BOTTOM;
381
382 const Type* t = base->bottom_type();
383 if (t->isa_narrowoop() && CompressedOops::shift() == 0) {
384 // 32-bit unscaled narrow oop can be the base of any address expression
385 t = t->make_ptr();
386 }
387 if (t->isa_narrowklass() && CompressedKlassPointers::shift() == 0) {
388 // 32-bit unscaled narrow oop can be the base of any address expression
389 t = t->make_ptr();
390 }
391 if (t->isa_intptr_t() && offset != 0 && offset != Type::OffsetBot) {
392 // We cannot assert that the offset does not look oop-ish here.
393 // Depending on the heap layout the cardmark base could land
394 // inside some oopish region. It definitely does for Win2K.
395 // The sum of cardmark-base plus shift-by-9-oop lands outside
396 // the oop-ish area but we can't assert for that statically.
397 return TypeRawPtr::BOTTOM;
398 }
399
400 const TypePtr *tp = t->isa_ptr();
401
402 // be conservative if we do not recognize the type
403 if (tp == nullptr) {
404 assert(false, "this path may produce not optimal code");
405 return TypePtr::BOTTOM;
406 }
407 assert(tp->base() != Type::AnyPtr, "not a bare pointer");
408
409 if (tp->isa_aryptr()) {
410 // In the case of a flat inline type array, each field has its
411 // own slice so we need to extract the field being accessed from
412 // the address computation
413 if (offset == Type::OffsetBot) {
414 Node* base;
415 Node* index;
416 const MachOper* oper = memory_inputs(base, index);
417 if (oper != (MachOper*)-1) {
418 offset = oper->constant_disp();
419 return tp->is_aryptr()->add_field_offset_and_offset(offset)->add_offset(Type::OffsetBot);
420 }
421 }
422 return tp->is_aryptr()->add_field_offset_and_offset(offset);
423 }
424
425 return tp->add_offset(offset);
426 }
427
428
429 //-----------------------------operand_index---------------------------------
430 int MachNode::operand_index(uint operand) const {
431 if (operand < 1) return -1;
432 assert(operand < num_opnds(), "oob");
433 if (_opnds[operand]->num_edges() == 0) return -1;
434
435 uint skipped = oper_input_base(); // Sum of leaves skipped so far
436 for (uint opcnt = 1; opcnt < operand; opcnt++) {
437 uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
438 skipped += num_edges;
439 }
440 return skipped;
441 }
442
443 int MachNode::operand_index(const MachOper *oper) const {
444 uint skipped = oper_input_base(); // Sum of leaves skipped so far
445 uint opcnt;
446 for (opcnt = 1; opcnt < num_opnds(); opcnt++) {
447 if (_opnds[opcnt] == oper) break;
448 uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
449 skipped += num_edges;
450 }
451 if (_opnds[opcnt] != oper) return -1;
452 return skipped;
453 }
454
455 int MachNode::operand_index(Node* def) const {
456 uint skipped = oper_input_base(); // Sum of leaves skipped so far
457 for (uint opcnt = 1; opcnt < num_opnds(); opcnt++) {
458 uint num_edges = _opnds[opcnt]->num_edges(); // leaves for operand
459 for (uint i = 0; i < num_edges; i++) {
460 if (in(skipped + i) == def) {
461 return opcnt;
462 }
463 }
464 skipped += num_edges;
465 }
466 return -1;
467 }
468
469 //------------------------------peephole---------------------------------------
470 // Apply peephole rule(s) to this instruction
471 int MachNode::peephole(Block *block, int block_index, PhaseCFG* cfg_, PhaseRegAlloc *ra_) {
472 return -1;
473 }
474
475 //------------------------------add_case_label---------------------------------
476 // Adds the label for the case
477 void MachNode::add_case_label( int index_num, Label* blockLabel) {
478 ShouldNotCallThis();
479 }
480
481 //------------------------------method_set-------------------------------------
482 // Set the absolute address of a method
483 void MachNode::method_set( intptr_t addr ) {
484 ShouldNotCallThis();
485 }
486
487 //------------------------------rematerialize----------------------------------
488 bool MachNode::rematerialize() const {
489 // Temps are always rematerializable
490 if (is_MachTemp()) return true;
491
492 uint r = rule(); // Match rule
493 if (r < Matcher::_begin_rematerialize ||
494 r >= Matcher::_end_rematerialize) {
495 return false;
496 }
497
498 // For 2-address instructions, the input live range is also the output
499 // live range. Remateralizing does not make progress on the that live range.
500 if (two_adr()) return false;
501
502 // Check for rematerializing float constants, or not
503 if (!Matcher::rematerialize_float_constants) {
504 int op = ideal_Opcode();
505 if (op == Op_ConF || op == Op_ConD) {
506 return false;
507 }
508 }
509
510 // Defining flags - can't spill these! Must remateralize.
511 if (ideal_reg() == Op_RegFlags) {
512 return true;
513 }
514
515 // Stretching lots of inputs - don't do it.
516 // A MachContant has the last input being the constant base
517 if (req() > (is_MachConstant() ? 3U : 2U)) {
518 return false;
519 }
520
521 if (req() >= 2 && in(1) && in(1)->ideal_reg() == Op_RegFlags) {
522 // In(1) will be rematerialized, too.
523 // Stretching lots of inputs - don't do it.
524 if (in(1)->req() > (in(1)->is_MachConstant() ? 3U : 2U)) {
525 return false;
526 }
527 }
528
529 // Don't remateralize somebody with bound inputs - it stretches a
530 // fixed register lifetime.
531 uint idx = oper_input_base();
532 if (req() > idx) {
533 const RegMask &rm = in_RegMask(idx);
534 if (rm.is_NotEmpty() && rm.is_bound(ideal_reg())) {
535 return false;
536 }
537 }
538
539 return true;
540 }
541
542 #ifndef PRODUCT
543 //------------------------------dump_spec--------------------------------------
544 // Print any per-operand special info
545 void MachNode::dump_spec(outputStream *st) const {
546 uint cnt = num_opnds();
547 for( uint i=0; i<cnt; i++ ) {
548 if (_opnds[i] != nullptr) {
549 _opnds[i]->dump_spec(st);
550 } else {
551 st->print(" _");
552 }
553 }
554 const TypePtr *t = adr_type();
555 if( t ) {
556 Compile* C = Compile::current();
557 if( C->alias_type(t)->is_volatile() )
558 st->print(" Volatile!");
559 }
560 }
561
562 //------------------------------dump_format------------------------------------
563 // access to virtual
564 void MachNode::dump_format(PhaseRegAlloc *ra, outputStream *st) const {
565 format(ra, st); // access to virtual
566 }
567 #endif
568
569 //=============================================================================
570 #ifndef PRODUCT
571 void MachTypeNode::dump_spec(outputStream *st) const {
572 if (_bottom_type != nullptr) {
573 _bottom_type->dump_on(st);
574 } else {
575 st->print(" null");
576 }
577 if (barrier_data() != 0) {
578 st->print(" barrier(");
579 BarrierSet::barrier_set()->barrier_set_c2()->dump_barrier_data(this, st);
580 st->print(")");
581 }
582 }
583 #endif
584
585
586 //=============================================================================
587 int MachConstantNode::constant_offset() {
588 // Bind the offset lazily.
589 if (_constant.offset() == -1) {
590 ConstantTable& constant_table = Compile::current()->output()->constant_table();
591 int offset = constant_table.find_offset(_constant);
592 // If called from Compile::scratch_emit_size return the
593 // pre-calculated offset.
594 // NOTE: If the AD file does some table base offset optimizations
595 // later the AD file needs to take care of this fact.
596 if (Compile::current()->output()->in_scratch_emit_size()) {
597 return constant_table.calculate_table_base_offset() + offset;
598 }
599 _constant.set_offset(constant_table.table_base_offset() + offset);
600 }
601 return _constant.offset();
602 }
603
604 int MachConstantNode::constant_offset_unchecked() const {
605 return _constant.offset();
606 }
607
608 //=============================================================================
609 #ifndef PRODUCT
610 void MachNullCheckNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
611 int reg = ra_->get_reg_first(in(1)->in(_vidx));
612 st->print("%s %s", Name(), Matcher::regName[reg]);
613 }
614 #endif
615
616 void MachNullCheckNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
617 // only emits entries in the null-pointer exception handler table
618 }
619 void MachNullCheckNode::label_set(Label* label, uint block_num) {
620 // Nothing to emit
621 }
622 void MachNullCheckNode::save_label( Label** label, uint* block_num ) {
623 // Nothing to emit
624 }
625
626 const RegMask &MachNullCheckNode::in_RegMask( uint idx ) const {
627 if( idx == 0 ) return RegMask::Empty;
628 else return in(1)->as_Mach()->out_RegMask();
629 }
630
631 //=============================================================================
632 const Type *MachProjNode::bottom_type() const {
633 if( _ideal_reg == fat_proj ) return Type::BOTTOM;
634 // Try the normal mechanism first
635 const Type *t = in(0)->bottom_type();
636 if( t->base() == Type::Tuple ) {
637 const TypeTuple *tt = t->is_tuple();
638 if (_con < tt->cnt())
639 return tt->field_at(_con);
640 }
641 // Else use generic type from ideal register set
642 assert((uint)_ideal_reg < (uint)_last_machine_leaf && Type::mreg2type[_ideal_reg], "in bounds");
643 return Type::mreg2type[_ideal_reg];
644 }
645
646 const TypePtr *MachProjNode::adr_type() const {
647 if (bottom_type() == Type::MEMORY) {
648 // in(0) might be a narrow MemBar; otherwise we will report TypePtr::BOTTOM
649 Node* ctrl = in(0);
650 if (ctrl == nullptr) return nullptr; // node is dead
651 const TypePtr* adr_type = ctrl->adr_type();
652 #ifdef ASSERT
653 if (!VMError::is_error_reported() && !Node::in_dump())
654 assert(adr_type != nullptr, "source must have adr_type");
655 #endif
656 return adr_type;
657 }
658 assert(bottom_type()->base() != Type::Memory, "no other memories?");
659 return nullptr;
660 }
661
662 #ifndef PRODUCT
663 void MachProjNode::dump_spec(outputStream *st) const {
664 ProjNode::dump_spec(st);
665 switch (_ideal_reg) {
666 case unmatched_proj: st->print("/unmatched"); break;
667 case fat_proj: st->print("/fat"); if (WizardMode) _rout.dump(st); break;
668 }
669 }
670 #endif
671
672 //=============================================================================
673 #ifndef PRODUCT
674 void MachIfNode::dump_spec(outputStream *st) const {
675 st->print("P=%f, C=%f",_prob, _fcnt);
676 }
677 #endif
678
679 //=============================================================================
680 uint MachReturnNode::size_of() const { return sizeof(*this); }
681
682 //------------------------------Registers--------------------------------------
683 const RegMask &MachReturnNode::in_RegMask( uint idx ) const {
684 return _in_rms[idx];
685 }
686
687 const TypePtr *MachReturnNode::adr_type() const {
688 // most returns and calls are assumed to consume & modify all of memory
689 // the matcher will copy non-wide adr_types from ideal originals
690 return _adr_type;
691 }
692
693 //=============================================================================
694 const Type *MachSafePointNode::bottom_type() const { return TypeTuple::MEMBAR; }
695
696 //------------------------------Registers--------------------------------------
697 const RegMask &MachSafePointNode::in_RegMask( uint idx ) const {
698 // Values in the domain use the users calling convention, embodied in the
699 // _in_rms array of RegMasks.
700 if( idx < TypeFunc::Parms ) return _in_rms[idx];
701
702 if (idx == TypeFunc::Parms &&
703 ideal_Opcode() == Op_SafePoint) {
704 return MachNode::in_RegMask(idx);
705 }
706
707 // Values outside the domain represent debug info
708 assert(in(idx)->ideal_reg() != Op_RegFlags, "flags register is not spillable");
709 return *Compile::current()->matcher()->idealreg2spillmask[in(idx)->ideal_reg()];
710 }
711
712
713 //=============================================================================
714
715 bool MachCallNode::cmp( const Node &n ) const
716 { return _tf == ((MachCallNode&)n)._tf; }
717 const Type *MachCallNode::bottom_type() const { return tf()->range_cc(); }
718 const Type* MachCallNode::Value(PhaseGVN* phase) const { return tf()->range_cc(); }
719
720 #ifndef PRODUCT
721 void MachCallNode::dump_spec(outputStream *st) const {
722 st->print("# ");
723 if (tf() != nullptr) tf()->dump_on(st);
724 if (_cnt != COUNT_UNKNOWN) st->print(" C=%f",_cnt);
725 if (jvms() != nullptr) jvms()->dump_spec(st);
726 }
727 #endif
728
729 bool MachCallNode::return_value_is_used() const {
730 if (tf()->range_sig()->cnt() == TypeFunc::Parms) {
731 // void return
732 return false;
733 }
734
735 // find the projection corresponding to the return value
736 for (DUIterator_Fast imax, i = fast_outs(imax); i < imax; i++) {
737 Node *use = fast_out(i);
738 if (!use->is_Proj()) continue;
739 if (use->as_Proj()->_con == TypeFunc::Parms) {
740 return true;
741 }
742 }
743 return false;
744 }
745
746 // Similar to cousin class CallNode::returns_pointer
747 // Because this is used in deoptimization, we want the type info, not the data
748 // flow info; the interpreter will "use" things that are dead to the optimizer.
749 bool MachCallNode::returns_pointer() const {
750 const TypeTuple *r = tf()->range_sig();
751 return (r->cnt() > TypeFunc::Parms &&
752 r->field_at(TypeFunc::Parms)->isa_ptr());
753 }
754
755 bool MachCallNode::returns_scalarized() const {
756 return tf()->returns_inline_type_as_fields();
757 }
758
759 //------------------------------Registers--------------------------------------
760 const RegMask &MachCallNode::in_RegMask(uint idx) const {
761 // Values in the domain use the users calling convention, embodied in the
762 // _in_rms array of RegMasks.
763 if (entry_point() == nullptr && idx == TypeFunc::Parms) {
764 // Null entry point is a special cast where the target of the call
765 // is in a register.
766 return MachNode::in_RegMask(idx);
767 }
768 if (idx < tf()->domain_sig()->cnt()) {
769 return _in_rms[idx];
770 }
771 if (idx == mach_constant_base_node_input()) {
772 return MachConstantBaseNode::static_out_RegMask();
773 }
774 // Values outside the domain represent debug info
775 return *Compile::current()->matcher()->idealreg2debugmask[in(idx)->ideal_reg()];
776 }
777
778 //=============================================================================
779 uint MachCallJavaNode::size_of() const { return sizeof(*this); }
780 bool MachCallJavaNode::cmp( const Node &n ) const {
781 MachCallJavaNode &call = (MachCallJavaNode&)n;
782 return MachCallNode::cmp(call) && _method->equals(call._method) &&
783 _override_symbolic_info == call._override_symbolic_info;
784 }
785 #ifndef PRODUCT
786 void MachCallJavaNode::dump_spec(outputStream *st) const {
787 if (_method_handle_invoke)
788 st->print("MethodHandle ");
789 if (_method) {
790 _method->print_short_name(st);
791 st->print(" ");
792 }
793 MachCallNode::dump_spec(st);
794 }
795 #endif
796
797 //------------------------------Registers--------------------------------------
798 const RegMask &MachCallJavaNode::in_RegMask(uint idx) const {
799 // Values in the domain use the users calling convention, embodied in the
800 // _in_rms array of RegMasks.
801 if (idx < tf()->domain_cc()->cnt()) {
802 return _in_rms[idx];
803 }
804 if (idx == mach_constant_base_node_input()) {
805 return MachConstantBaseNode::static_out_RegMask();
806 }
807 // Values outside the domain represent debug info
808 Matcher* m = Compile::current()->matcher();
809 // If this call is a MethodHandle invoke we have to use a different
810 // debugmask which does not include the register we use to save the
811 // SP over MH invokes.
812 RegMask** debugmask = _method_handle_invoke ? m->idealreg2mhdebugmask : m->idealreg2debugmask;
813 return *debugmask[in(idx)->ideal_reg()];
814 }
815
816 //=============================================================================
817 uint MachCallStaticJavaNode::size_of() const { return sizeof(*this); }
818 bool MachCallStaticJavaNode::cmp( const Node &n ) const {
819 MachCallStaticJavaNode &call = (MachCallStaticJavaNode&)n;
820 return MachCallJavaNode::cmp(call) && _name == call._name;
821 }
822
823 //----------------------------uncommon_trap_request----------------------------
824 // If this is an uncommon trap, return the request code, else zero.
825 int MachCallStaticJavaNode::uncommon_trap_request() const {
826 if (_name != nullptr && !strcmp(_name, "uncommon_trap")) {
827 return CallStaticJavaNode::extract_uncommon_trap_request(this);
828 }
829 return 0;
830 }
831
832 #ifndef PRODUCT
833 // Helper for summarizing uncommon_trap arguments.
834 void MachCallStaticJavaNode::dump_trap_args(outputStream *st) const {
835 int trap_req = uncommon_trap_request();
836 if (trap_req != 0) {
837 char buf[100];
838 st->print("(%s)",
839 Deoptimization::format_trap_request(buf, sizeof(buf),
840 trap_req));
841 }
842 }
843
844 void MachCallStaticJavaNode::dump_spec(outputStream *st) const {
845 st->print("Static ");
846 if (_name != nullptr) {
847 st->print("wrapper for: %s", _name );
848 dump_trap_args(st);
849 st->print(" ");
850 }
851 MachCallJavaNode::dump_spec(st);
852 }
853 #endif
854
855 //=============================================================================
856 #ifndef PRODUCT
857 void MachCallDynamicJavaNode::dump_spec(outputStream *st) const {
858 st->print("Dynamic ");
859 MachCallJavaNode::dump_spec(st);
860 }
861 #endif
862 //=============================================================================
863 uint MachCallRuntimeNode::size_of() const { return sizeof(*this); }
864 bool MachCallRuntimeNode::cmp( const Node &n ) const {
865 MachCallRuntimeNode &call = (MachCallRuntimeNode&)n;
866 return MachCallNode::cmp(call) && !strcmp(_name,call._name);
867 }
868 #ifndef PRODUCT
869 void MachCallRuntimeNode::dump_spec(outputStream *st) const {
870 st->print("%s ",_name);
871 MachCallNode::dump_spec(st);
872 }
873 #endif
874 //=============================================================================
875 // A shared JVMState for all HaltNodes. Indicates the start of debug info
876 // is at TypeFunc::Parms. Only required for SOE register spill handling -
877 // to indicate where the stack-slot-only debug info inputs begin.
878 // There is no other JVM state needed here.
879 JVMState jvms_for_throw(0);
880 JVMState *MachHaltNode::jvms() const {
881 return &jvms_for_throw;
882 }
883
884 uint MachMemBarNode::size_of() const { return sizeof(*this); }
885
886 const TypePtr *MachMemBarNode::adr_type() const {
887 return _adr_type;
888 }
889
890
891 //=============================================================================
892 #ifndef PRODUCT
893 void labelOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
894 st->print("B%d", _block_num);
895 }
896 #endif // PRODUCT
897
898 //=============================================================================
899 #ifndef PRODUCT
900 void methodOper::int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const {
901 st->print(INTPTR_FORMAT, _method);
902 }
903 #endif // PRODUCT