1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef SHARE_OPTO_MACHNODE_HPP
26 #define SHARE_OPTO_MACHNODE_HPP
27
28 #include "opto/c2_MacroAssembler.hpp"
29 #include "opto/callnode.hpp"
30 #include "opto/constantTable.hpp"
31 #include "opto/matcher.hpp"
32 #include "opto/multnode.hpp"
33 #include "opto/node.hpp"
34 #include "opto/regmask.hpp"
35 #include "utilities/growableArray.hpp"
36
37 class BufferBlob;
38 class JVMState;
39 class MachCallDynamicJavaNode;
40 class MachCallJavaNode;
41 class MachCallLeafNode;
42 class MachCallNode;
43 class MachCallRuntimeNode;
44 class MachCallStaticJavaNode;
45 class MachEpilogNode;
46 class MachIfNode;
47 class MachNullCheckNode;
48 class MachOper;
49 class MachProjNode;
50 class MachPrologNode;
51 class MachReturnNode;
52 class MachSafePointNode;
53 class MachSpillCopyNode;
54 class Matcher;
55 class PhaseRegAlloc;
56 class RegMask;
57 class State;
58
59 //---------------------------MachOper------------------------------------------
60 class MachOper : public ResourceObj {
61 public:
62 // Allocate right next to the MachNodes in the same arena
63 void *operator new(size_t x) throw() {
64 Compile* C = Compile::current();
65 return C->node_arena()->AmallocWords(x);
66 }
67
68 // Opcode
69 virtual uint opcode() const = 0;
70
71 // Number of input edges.
72 // Generally at least 1
73 virtual uint num_edges() const { return 1; }
74 // Array of Register masks
75 virtual const RegMask *in_RegMask(int index) const;
76
77 // Methods to output the encoding of the operand
78
79 // Negate conditional branches. Error for non-branch Nodes
80 virtual void negate();
81
82 // Return the value requested
83 // result register lookup, corresponding to int_format
84 virtual int reg(PhaseRegAlloc *ra_, const Node *node) const;
85 // input register lookup, corresponding to ext_format
86 virtual int reg(PhaseRegAlloc *ra_, const Node *node, int idx) const;
87
88 // helpers for MacroAssembler generation from ADLC
89 Register as_Register(PhaseRegAlloc *ra_, const Node *node) const {
90 return ::as_Register(reg(ra_, node));
91 }
92 Register as_Register(PhaseRegAlloc *ra_, const Node *node, int idx) const {
93 return ::as_Register(reg(ra_, node, idx));
94 }
95 FloatRegister as_FloatRegister(PhaseRegAlloc *ra_, const Node *node) const {
96 return ::as_FloatRegister(reg(ra_, node));
97 }
98 FloatRegister as_FloatRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
99 return ::as_FloatRegister(reg(ra_, node, idx));
100 }
101
102 #if defined(AMD64)
103 KRegister as_KRegister(PhaseRegAlloc *ra_, const Node *node) const {
104 return ::as_KRegister(reg(ra_, node));
105 }
106 KRegister as_KRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
107 return ::as_KRegister(reg(ra_, node, idx));
108 }
109 XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node) const {
110 return ::as_XMMRegister(reg(ra_, node));
111 }
112 XMMRegister as_XMMRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
113 return ::as_XMMRegister(reg(ra_, node, idx));
114 }
115 #endif
116 // CondRegister reg converter
117 #if defined(PPC64)
118 ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node) const {
119 return ::as_ConditionRegister(reg(ra_, node));
120 }
121 ConditionRegister as_ConditionRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
122 return ::as_ConditionRegister(reg(ra_, node, idx));
123 }
124 VectorRegister as_VectorRegister(PhaseRegAlloc *ra_, const Node *node) const {
125 return ::as_VectorRegister(reg(ra_, node));
126 }
127 VectorRegister as_VectorRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
128 return ::as_VectorRegister(reg(ra_, node, idx));
129 }
130 VectorSRegister as_VectorSRegister(PhaseRegAlloc *ra_, const Node *node) const {
131 return ::as_VectorSRegister(reg(ra_, node));
132 }
133 VectorSRegister as_VectorSRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
134 return ::as_VectorSRegister(reg(ra_, node, idx));
135 }
136 #endif
137 #if defined(S390)
138 VectorRegister as_VectorRegister(PhaseRegAlloc *ra_, const Node *node) const {
139 return ::as_VectorRegister(reg(ra_, node));
140 }
141 VectorRegister as_VectorRegister(PhaseRegAlloc *ra_, const Node *node, int idx) const {
142 return ::as_VectorRegister(reg(ra_, node, idx));
143 }
144 #endif
145 #if defined(AARCH64)
146 PRegister as_PRegister(PhaseRegAlloc* ra_, const Node* node) const {
147 return ::as_PRegister(reg(ra_, node));
148 }
149 PRegister as_PRegister(PhaseRegAlloc* ra_, const Node* node, int idx) const {
150 return ::as_PRegister(reg(ra_, node, idx));
151 }
152 #endif
153
154 virtual intptr_t constant() const;
155 virtual relocInfo::relocType constant_reloc() const;
156 virtual jdouble constantD() const;
157 virtual jfloat constantF() const;
158 virtual jlong constantL() const;
159 virtual jshort constantH() const;
160 virtual TypeOopPtr *oop() const;
161 virtual int ccode() const;
162 // A zero, default, indicates this value is not needed.
163 // May need to lookup the base register, as done in int_ and ext_format
164 virtual int base (PhaseRegAlloc *ra_, const Node *node, int idx) const;
165 virtual int index(PhaseRegAlloc *ra_, const Node *node, int idx) const;
166 virtual int scale() const;
167 // Parameters needed to support MEMORY_INTERFACE access to stackSlot
168 virtual int disp (PhaseRegAlloc *ra_, const Node *node, int idx) const;
169 // Check for PC-Relative displacement
170 virtual relocInfo::relocType disp_reloc() const;
171 virtual int constant_disp() const; // usu. 0, may return Type::OffsetBot
172 virtual int base_position() const; // base edge position, or -1
173 virtual int index_position() const; // index edge position, or -1
174
175 // Access the TypeKlassPtr of operands with a base==RegI and disp==RegP
176 // Only returns non-null value for x86_32.ad's indOffset32X
177 virtual const TypePtr *disp_as_type() const { return nullptr; }
178
179 // Return the label
180 virtual Label *label() const;
181
182 // Return the method's address
183 virtual intptr_t method() const;
184
185 // Hash and compare over operands are currently identical
186 virtual uint hash() const;
187 virtual bool cmp( const MachOper &oper ) const;
188
189 // Virtual clone, since I do not know how big the MachOper is.
190 virtual MachOper *clone() const = 0;
191
192 // Return ideal Type from simple operands. Fail for complex operands.
193 virtual const Type *type() const;
194
195 // Set an integer offset if we have one, or error otherwise
196 virtual void set_con( jint c0 ) { ShouldNotReachHere(); }
197
198 #ifndef PRODUCT
199 // Return name of operand
200 virtual const char *Name() const { return "???";}
201
202 // Methods to output the text version of the operand
203 virtual void int_format(PhaseRegAlloc *,const MachNode *node, outputStream *st) const = 0;
204 virtual void ext_format(PhaseRegAlloc *,const MachNode *node,int idx, outputStream *st) const=0;
205
206 virtual void dump_spec(outputStream *st) const; // Print per-operand info
207
208 // Check whether o is a valid oper.
209 static bool notAnOper(const MachOper *o) {
210 if (o == nullptr) return true;
211 if (((intptr_t)o & 1) != 0) return true;
212 if (*(address*)o == badAddress) return true; // kill by Node::destruct
213 return false;
214 }
215 #endif // !PRODUCT
216 };
217
218 //------------------------------MachNode---------------------------------------
219 // Base type for all machine specific nodes. All node classes generated by the
220 // ADLC inherit from this class.
221 class MachNode : public Node {
222 public:
223 MachNode() : Node((uint)0), _barrier(0), _num_opnds(0), _opnds(nullptr) {
224 init_class_id(Class_Mach);
225 }
226 // Required boilerplate
227 virtual uint size_of() const { return sizeof(MachNode); }
228 virtual int Opcode() const; // Always equal to MachNode
229 virtual uint rule() const = 0; // Machine-specific opcode
230 // Number of inputs which come before the first operand.
231 // Generally at least 1, to skip the Control input
232 virtual uint oper_input_base() const { return 1; }
233 // Position of constant base node in node's inputs. -1 if
234 // no constant base node input.
235 virtual uint mach_constant_base_node_input() const { return (uint)-1; }
236
237 uint8_t barrier_data() const { return _barrier; }
238 void set_barrier_data(uint8_t data) { _barrier = data; }
239
240 // Copy index, inputs, and operands to a new version of the instruction.
241 // Called from cisc_version() and short_branch_version().
242 void fill_new_machnode(MachNode *n) const;
243
244 // Return an equivalent instruction using memory for cisc_operand position
245 virtual MachNode *cisc_version(int offset);
246 // Modify this instruction's register mask to use stack version for cisc_operand
247 virtual void use_cisc_RegMask();
248
249 // Support for short branches
250 bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; }
251
252 // Avoid back to back some instructions on some CPUs.
253 enum AvoidBackToBackFlag { AVOID_NONE = 0,
254 AVOID_BEFORE = Flag_avoid_back_to_back_before,
255 AVOID_AFTER = Flag_avoid_back_to_back_after,
256 AVOID_BEFORE_AND_AFTER = AVOID_BEFORE | AVOID_AFTER };
257
258 bool avoid_back_to_back(AvoidBackToBackFlag flag_value) const {
259 return (flags() & flag_value) == flag_value;
260 }
261
262 // instruction implemented with a call
263 bool has_call() const { return (flags() & Flag_has_call) != 0; }
264
265 // First index in _in[] corresponding to operand, or -1 if there is none
266 int operand_index(uint operand) const;
267 int operand_index(const MachOper *oper) const;
268 int operand_index(Node* m) const;
269 int operand_num_edges(uint operand) const;
270
271 // Register class input is expected in
272 virtual const RegMask &in_RegMask(uint) const;
273
274 // cisc-spillable instructions redefine for use by in_RegMask
275 virtual const RegMask *cisc_RegMask() const { return nullptr; }
276
277 // If this instruction is a 2-address instruction, then return the
278 // index of the input which must match the output. Not necessary
279 // for instructions which bind the input and output register to the
280 // same singleton register (e.g., Intel IDIV which binds AX to be
281 // both an input and an output). It is necessary when the input and
282 // output have choices - but they must use the same choice.
283 virtual uint two_adr( ) const { return 0; }
284
285 // The GC might require some barrier metadata for machine code emission.
286 uint8_t _barrier;
287
288 // Array of complex operand pointers. Each corresponds to zero or
289 // more leafs. Must be set by MachNode constructor to point to an
290 // internal array of MachOpers. The MachOper array is sized by
291 // specific MachNodes described in the ADL.
292 uint16_t _num_opnds;
293 MachOper **_opnds;
294 uint16_t num_opnds() const { return _num_opnds; }
295
296 // Emit bytes using C2_MacroAssembler
297 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
298 // Expand node after register allocation.
299 // Node is replaced by several nodes in the postalloc expand phase.
300 // Corresponding methods are generated for nodes if they specify
301 // postalloc_expand. See block.cpp for more documentation.
302 virtual bool requires_postalloc_expand() const { return false; }
303 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
304 // Size of instruction in bytes
305 virtual uint size(PhaseRegAlloc *ra_) const;
306 // Helper function that computes size by emitting code
307 virtual uint emit_size(PhaseRegAlloc *ra_) const;
308
309 // Return the alignment required (in units of relocInfo::addr_unit())
310 // for this instruction (must be a power of 2)
311 int pd_alignment_required() const;
312 virtual int alignment_required() const { return pd_alignment_required(); }
313
314 // Return the padding (in bytes) to be emitted before this
315 // instruction to properly align it.
316 virtual int compute_padding(int current_offset) const;
317
318 // Return number of relocatable values contained in this instruction
319 virtual int reloc() const { return 0; }
320
321 // Return number of words used for double constants in this instruction
322 virtual int ins_num_consts() const { return 0; }
323
324 // Hash and compare over operands. Used to do GVN on machine Nodes.
325 virtual uint hash() const;
326 virtual bool cmp( const Node &n ) const;
327
328 // Expand method for MachNode, replaces nodes representing pseudo
329 // instructions with a set of nodes which represent real machine
330 // instructions and compute the same value.
331 virtual MachNode *Expand( State *, Node_List &proj_list, Node* mem ) { return this; }
332
333 // Bottom_type call; value comes from operand0
334 virtual const class Type *bottom_type() const { return _opnds[0]->type(); }
335 virtual uint ideal_reg() const {
336 const Type *t = _opnds[0]->type();
337 if (t == TypeInt::CC) {
338 return Op_RegFlags;
339 } else {
340 return t->ideal_reg();
341 }
342 }
343
344 // If this is a memory op, return the base pointer and fixed offset.
345 // If there are no such, return null. If there are multiple addresses
346 // or the address is indeterminate (rare cases) then return (Node*)-1,
347 // which serves as node bottom.
348 // If the offset is not statically determined, set it to Type::OffsetBot.
349 // This method is free to ignore stack slots if that helps.
350 #define TYPE_PTR_SENTINAL ((const TypePtr*)-1)
351 // Passing TYPE_PTR_SENTINAL as adr_type asks for computation of the adr_type if possible
352 const Node* get_base_and_disp(intptr_t &offset, const TypePtr* &adr_type) const;
353
354 // Helper for get_base_and_disp: find the base and index input nodes.
355 // Returns the MachOper as determined by memory_operand(), for use, if
356 // needed by the caller. If (MachOper *)-1 is returned, base and index
357 // are set to NodeSentinel. If null is returned, base and
358 // index are set to null.
359 const MachOper* memory_inputs(Node* &base, Node* &index) const;
360
361 // Helper for memory_inputs: Which operand carries the necessary info?
362 // By default, returns null, which means there is no such operand.
363 // If it returns (MachOper*)-1, this means there are multiple memories.
364 virtual const MachOper* memory_operand() const { return nullptr; }
365
366 // Call "get_base_and_disp" to decide which category of memory is used here.
367 virtual const class TypePtr *adr_type() const;
368
369 // Apply peephole rule(s) to this instruction
370 virtual int peephole(Block *block, int block_index, PhaseCFG* cfg_, PhaseRegAlloc *ra_);
371
372 // Top-level ideal Opcode matched
373 virtual int ideal_Opcode() const { return Op_Node; }
374
375 // Adds the label for the case
376 virtual void add_case_label( int switch_val, Label* blockLabel);
377
378 // Set the absolute address for methods
379 virtual void method_set( intptr_t addr );
380
381 // Should we clone rather than spill this instruction?
382 bool rematerialize() const;
383
384 // Get the pipeline info
385 static const Pipeline *pipeline_class();
386 virtual const Pipeline *pipeline() const;
387
388 // Returns true if this node is a check that can be implemented with a trap.
389 virtual bool is_TrapBasedCheckNode() const { return false; }
390
391 // Whether this node is expanded during code emission into a sequence of
392 // instructions and the first instruction can perform an implicit null check.
393 virtual bool is_late_expanded_null_check_candidate() const {
394 return false;
395 }
396
397 void set_removed() { add_flag(Flag_is_removed_by_peephole); }
398 bool get_removed() { return (flags() & Flag_is_removed_by_peephole) != 0; }
399
400 #ifndef PRODUCT
401 virtual const char *Name() const = 0; // Machine-specific name
402 virtual void dump_spec(outputStream *st) const; // Print per-node info
403 void dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual
404 #endif
405 };
406
407 //------------------------------MachIdealNode----------------------------
408 // Machine specific versions of nodes that must be defined by user.
409 // These are not converted by matcher from ideal nodes to machine nodes
410 // but are inserted into the code by the compiler.
411 class MachIdealNode : public MachNode {
412 public:
413 MachIdealNode( ) {}
414
415 // Define the following defaults for non-matched machine nodes
416 virtual uint oper_input_base() const { return 0; }
417 virtual uint rule() const { return 9999999; }
418 virtual const class Type *bottom_type() const { return _opnds == nullptr ? Type::CONTROL : MachNode::bottom_type(); }
419 };
420
421 //------------------------------MachTypeNode----------------------------
422 // Machine Nodes that need to retain a known Type.
423 class MachTypeNode : public MachNode {
424 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
425 public:
426 MachTypeNode( ) {}
427 const Type *_bottom_type;
428
429 virtual const class Type *bottom_type() const { return _bottom_type; }
430 #ifndef PRODUCT
431 virtual void dump_spec(outputStream *st) const;
432 #endif
433 };
434
435 //------------------------------MachBreakpointNode----------------------------
436 // Machine breakpoint or interrupt Node
437 class MachBreakpointNode : public MachIdealNode {
438 public:
439 MachBreakpointNode( ) {}
440 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
441 virtual uint size(PhaseRegAlloc *ra_) const;
442
443 #ifndef PRODUCT
444 virtual const char *Name() const { return "Breakpoint"; }
445 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
446 #endif
447 };
448
449 //------------------------------MachConstantBaseNode--------------------------
450 // Machine node that represents the base address of the constant table.
451 class MachConstantBaseNode : public MachIdealNode {
452 public:
453 static const RegMask& _out_RegMask; // We need the out_RegMask statically in MachConstantNode::in_RegMask().
454
455 public:
456 MachConstantBaseNode() : MachIdealNode() {
457 init_class_id(Class_MachConstantBase);
458 }
459 virtual const class Type* bottom_type() const { return TypeRawPtr::NOTNULL; }
460 virtual uint ideal_reg() const { return Op_RegP; }
461 virtual uint oper_input_base() const { return 1; }
462
463 virtual bool requires_postalloc_expand() const;
464 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
465
466 virtual void emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const;
467 virtual uint size(PhaseRegAlloc* ra_) const;
468
469 static const RegMask& static_out_RegMask() { return _out_RegMask; }
470 virtual const RegMask& out_RegMask() const { return static_out_RegMask(); }
471
472 #ifndef PRODUCT
473 virtual const char* Name() const { return "MachConstantBaseNode"; }
474 virtual void format(PhaseRegAlloc*, outputStream* st) const;
475 #endif
476 };
477
478 //------------------------------MachConstantNode-------------------------------
479 // Machine node that holds a constant which is stored in the constant table.
480 class MachConstantNode : public MachTypeNode {
481 protected:
482 ConstantTable::Constant _constant; // This node's constant.
483
484 public:
485 MachConstantNode() : MachTypeNode() {
486 init_class_id(Class_MachConstant);
487 }
488
489 virtual void eval_constant(Compile* C) {
490 #ifdef ASSERT
491 tty->print("missing MachConstantNode eval_constant function: ");
492 dump();
493 #endif
494 ShouldNotCallThis();
495 }
496
497 virtual const RegMask &in_RegMask(uint idx) const {
498 if (idx == mach_constant_base_node_input())
499 return MachConstantBaseNode::static_out_RegMask();
500 return MachNode::in_RegMask(idx);
501 }
502
503 // Input edge of MachConstantBaseNode.
504 virtual uint mach_constant_base_node_input() const { return req() - 1; }
505
506 int constant_offset();
507 int constant_offset() const { return ((MachConstantNode*) this)->constant_offset(); }
508 // Unchecked version to avoid assertions in debug output.
509 int constant_offset_unchecked() const;
510 virtual uint size_of() const { return sizeof(MachConstantNode); }
511 };
512
513 //------------------------------MachUEPNode-----------------------------------
514 // Machine Unvalidated Entry Point Node
515 class MachUEPNode : public MachIdealNode {
516 public:
517 MachUEPNode( ) {}
518 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
519 virtual uint size(PhaseRegAlloc *ra_) const;
520
521 #ifndef PRODUCT
522 virtual const char *Name() const { return "Unvalidated-Entry-Point"; }
523 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
524 #endif
525 };
526
527 //------------------------------MachPrologNode--------------------------------
528 // Machine function Prolog Node
529 class MachPrologNode : public MachIdealNode {
530 public:
531 MachPrologNode( ) {}
532 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
533 virtual uint size(PhaseRegAlloc *ra_) const;
534 virtual int reloc() const;
535
536 #ifndef PRODUCT
537 virtual const char *Name() const { return "Prolog"; }
538 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
539 #endif
540 };
541
542 //------------------------------MachEpilogNode--------------------------------
543 // Machine function Epilog Node
544 class MachEpilogNode : public MachIdealNode {
545 private:
546 bool _do_polling;
547 public:
548 MachEpilogNode(bool do_poll = false) : _do_polling(do_poll) {}
549 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
550 virtual uint size(PhaseRegAlloc *ra_) const;
551 virtual int reloc() const;
552 virtual const Pipeline *pipeline() const;
553 virtual uint size_of() const { return sizeof(MachEpilogNode); }
554 bool do_polling() const { return _do_polling; }
555
556 #ifndef PRODUCT
557 virtual const char *Name() const { return "Epilog"; }
558 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
559 #endif
560 };
561
562 //------------------------------MachNopNode-----------------------------------
563 // Machine function Nop Node
564 class MachNopNode : public MachIdealNode {
565 private:
566 int _count;
567 public:
568 MachNopNode( ) : _count(1) {}
569 MachNopNode( int count ) : _count(count) {}
570 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
571 virtual uint size(PhaseRegAlloc *ra_) const;
572
573 virtual const class Type *bottom_type() const { return Type::CONTROL; }
574
575 virtual int ideal_Opcode() const { return Op_Con; } // bogus; see output.cpp
576 virtual const Pipeline *pipeline() const;
577 virtual uint size_of() const { return sizeof(MachNopNode); }
578 #ifndef PRODUCT
579 virtual const char *Name() const { return "Nop"; }
580 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
581 virtual void dump_spec(outputStream *st) const { } // No per-operand info
582 #endif
583 };
584
585 //------------------------------MachSpillCopyNode------------------------------
586 // Machine SpillCopy Node. Copies 1 or 2 words from any location to any
587 // location (stack or register).
588 class MachSpillCopyNode : public MachIdealNode {
589 public:
590 enum SpillType {
591 TwoAddress, // Inserted when coalescing of a two-address-instruction node and its input fails
592 PhiInput, // Inserted when coalescing of a phi node and its input fails
593 DebugUse, // Inserted as debug info spills to safepoints in non-frequent blocks
594 LoopPhiInput, // Pre-split compares of loop-phis
595 Definition, // An lrg marked as spilled will be spilled to memory right after its definition,
596 // if in high pressure region or the lrg is bound
597 RegToReg, // A register to register move
598 RegToMem, // A register to memory move
599 MemToReg, // A memory to register move
600 PhiLocationDifferToInputLocation, // When coalescing phi nodes in PhaseChaitin::Split(), a move spill is inserted if
601 // the phi and its input resides at different locations (i.e. reg or mem)
602 BasePointerToMem, // Spill base pointer to memory at safepoint
603 InputToRematerialization, // When rematerializing a node we stretch the inputs live ranges, and they might be
604 // stretched beyond a new definition point, therefore we split out new copies instead
605 CallUse, // Spill use at a call
606 Bound // An lrg marked as spill that is bound and needs to be spilled at a use
607 };
608 private:
609 const RegMask *_in; // RegMask for input
610 const RegMask *_out; // RegMask for output
611 const Type *_type;
612 const SpillType _spill_type;
613 public:
614 MachSpillCopyNode(SpillType spill_type, Node *n, const RegMask &in, const RegMask &out ) :
615 MachIdealNode(), _in(&in), _out(&out), _type(n->bottom_type()), _spill_type(spill_type) {
616 init_class_id(Class_MachSpillCopy);
617 init_flags(Flag_is_Copy);
618 add_req(nullptr);
619 add_req(n);
620 }
621 virtual uint size_of() const { return sizeof(*this); }
622 void set_out_RegMask(const RegMask &out) { _out = &out; }
623 void set_in_RegMask(const RegMask &in) { _in = ∈ }
624 virtual const RegMask &out_RegMask() const { return *_out; }
625 virtual const RegMask &in_RegMask(uint) const { return *_in; }
626 virtual const class Type *bottom_type() const { return _type; }
627 virtual uint ideal_reg() const { return _type->ideal_reg(); }
628 virtual uint oper_input_base() const { return 1; }
629 uint implementation( C2_MacroAssembler *masm, PhaseRegAlloc *ra_, bool do_size, outputStream* st ) const;
630
631 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
632 virtual uint size(PhaseRegAlloc *ra_) const;
633
634
635 #ifndef PRODUCT
636 static const char *spill_type(SpillType st) {
637 switch (st) {
638 case TwoAddress:
639 return "TwoAddressSpillCopy";
640 case PhiInput:
641 return "PhiInputSpillCopy";
642 case DebugUse:
643 return "DebugUseSpillCopy";
644 case LoopPhiInput:
645 return "LoopPhiInputSpillCopy";
646 case Definition:
647 return "DefinitionSpillCopy";
648 case RegToReg:
649 return "RegToRegSpillCopy";
650 case RegToMem:
651 return "RegToMemSpillCopy";
652 case MemToReg:
653 return "MemToRegSpillCopy";
654 case PhiLocationDifferToInputLocation:
655 return "PhiLocationDifferToInputLocationSpillCopy";
656 case BasePointerToMem:
657 return "BasePointerToMemSpillCopy";
658 case InputToRematerialization:
659 return "InputToRematerializationSpillCopy";
660 case CallUse:
661 return "CallUseSpillCopy";
662 case Bound:
663 return "BoundSpillCopy";
664 default:
665 assert(false, "Must have valid spill type");
666 return "MachSpillCopy";
667 }
668 }
669
670 virtual const char *Name() const {
671 return spill_type(_spill_type);
672 }
673
674 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
675 #endif
676 };
677
678 // MachMergeNode is similar to a PhiNode in a sense it merges multiple values,
679 // however it doesn't have a control input and is more like a MergeMem.
680 // It is inserted after the register allocation is done to ensure that nodes use single
681 // definition of a multidef lrg in a block.
682 class MachMergeNode : public MachIdealNode {
683 public:
684 MachMergeNode(Node *n1) {
685 init_class_id(Class_MachMerge);
686 add_req(nullptr);
687 add_req(n1);
688 }
689 virtual const RegMask &out_RegMask() const { return in(1)->out_RegMask(); }
690 virtual const RegMask &in_RegMask(uint idx) const { return in(1)->in_RegMask(idx); }
691 virtual const class Type *bottom_type() const { return in(1)->bottom_type(); }
692 virtual uint ideal_reg() const { return bottom_type()->ideal_reg(); }
693 virtual uint oper_input_base() const { return 1; }
694 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const { }
695 virtual uint size(PhaseRegAlloc *ra_) const { return 0; }
696 #ifndef PRODUCT
697 virtual const char *Name() const { return "MachMerge"; }
698 #endif
699 };
700
701 //------------------------------MachBranchNode--------------------------------
702 // Abstract machine branch Node
703 class MachBranchNode : public MachIdealNode {
704 public:
705 MachBranchNode() : MachIdealNode() {
706 init_class_id(Class_MachBranch);
707 }
708 virtual void label_set(Label* label, uint block_num) = 0;
709 virtual void save_label(Label** label, uint* block_num) = 0;
710
711 // Support for short branches
712 virtual MachNode *short_branch_version() { return nullptr; }
713
714 virtual bool pinned() const { return true; };
715 };
716
717 //------------------------------MachNullChkNode--------------------------------
718 // Machine-dependent null-pointer-check Node. Points a real MachNode that is
719 // also some kind of memory op. Turns the indicated MachNode into a
720 // conditional branch with good latency on the ptr-not-null path and awful
721 // latency on the pointer-is-null path.
722
723 class MachNullCheckNode : public MachBranchNode {
724 public:
725 const uint _vidx; // Index of memop being tested
726 MachNullCheckNode( Node *ctrl, Node *memop, uint vidx ) : MachBranchNode(), _vidx(vidx) {
727 init_class_id(Class_MachNullCheck);
728 add_req(ctrl);
729 add_req(memop);
730 }
731 virtual int Opcode() const;
732 virtual uint size_of() const { return sizeof(*this); }
733
734 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
735 virtual void label_set(Label* label, uint block_num);
736 virtual void save_label(Label** label, uint* block_num);
737 virtual void negate() { }
738 virtual const class Type *bottom_type() const { return TypeTuple::IFBOTH; }
739 virtual uint ideal_reg() const { return NotAMachineReg; }
740 virtual const RegMask &in_RegMask(uint) const;
741 virtual const RegMask& out_RegMask() const { return RegMask::EMPTY; }
742 #ifndef PRODUCT
743 virtual const char *Name() const { return "NullCheck"; }
744 virtual void format( PhaseRegAlloc *, outputStream *st ) const;
745 #endif
746 };
747
748 //------------------------------MachProjNode----------------------------------
749 // Machine-dependent Ideal projections (how is that for an oxymoron). Really
750 // just MachNodes made by the Ideal world that replicate simple projections
751 // but with machine-dependent input & output register masks. Generally
752 // produced as part of calling conventions. Normally I make MachNodes as part
753 // of the Matcher process, but the Matcher is ill suited to issues involving
754 // frame handling, so frame handling is all done in the Ideal world with
755 // occasional callbacks to the machine model for important info.
756 class MachProjNode : public ProjNode {
757 public:
758 MachProjNode(Node* multi, uint con, const RegMask& out, uint ideal_reg)
759 : ProjNode(multi, con),
760 _rout(out, Compile::current()->comp_arena()),
761 _ideal_reg(ideal_reg) {
762 init_class_id(Class_MachProj);
763 }
764 RegMask _rout;
765 const uint _ideal_reg;
766 enum projType {
767 unmatched_proj = 0, // Projs for Control, I/O, memory not matched
768 fat_proj = 999 // Projs killing many regs, defined by _rout
769 };
770 virtual int Opcode() const;
771 virtual const Type *bottom_type() const;
772 virtual const TypePtr *adr_type() const;
773 virtual const RegMask& in_RegMask(uint) const { return RegMask::EMPTY; }
774 virtual const RegMask &out_RegMask() const { return _rout; }
775 virtual uint ideal_reg() const { return _ideal_reg; }
776 // Need size_of() for virtual ProjNode::clone()
777 virtual uint size_of() const { return sizeof(MachProjNode); }
778 #ifndef PRODUCT
779 virtual void dump_spec(outputStream *st) const;
780 #endif
781 };
782
783 //------------------------------MachIfNode-------------------------------------
784 // Machine-specific versions of IfNodes
785 class MachIfNode : public MachBranchNode {
786 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
787 public:
788 float _prob; // Probability branch goes either way
789 float _fcnt; // Frequency counter
790 MachIfNode() : MachBranchNode() {
791 init_class_id(Class_MachIf);
792 }
793 // Negate conditional branches.
794 virtual void negate() = 0;
795 #ifndef PRODUCT
796 virtual void dump_spec(outputStream *st) const;
797 #endif
798 };
799
800 //------------------------------MachJumpNode-----------------------------------
801 // Machine-specific versions of JumpNodes
802 class MachJumpNode : public MachConstantNode {
803 public:
804 float* _probs;
805 MachJumpNode() : MachConstantNode() {
806 init_class_id(Class_MachJump);
807 }
808 virtual uint size_of() const { return sizeof(MachJumpNode); }
809 };
810
811 //------------------------------MachGotoNode-----------------------------------
812 // Machine-specific versions of GotoNodes
813 class MachGotoNode : public MachBranchNode {
814 public:
815 MachGotoNode() : MachBranchNode() {
816 init_class_id(Class_MachGoto);
817 }
818 };
819
820 //------------------------------MachFastLockNode-------------------------------------
821 // Machine-specific versions of FastLockNodes
822 class MachFastLockNode : public MachNode {
823 virtual uint size_of() const { return sizeof(*this); } // Size is bigger
824 public:
825 MachFastLockNode() : MachNode() {}
826 };
827
828 //------------------------------MachReturnNode--------------------------------
829 // Machine-specific versions of subroutine returns
830 class MachReturnNode : public MachNode {
831 virtual uint size_of() const; // Size is bigger
832 public:
833 RegMask *_in_rms; // Input register masks, set during allocation
834 ReallocMark _nesting; // assertion check for reallocations
835 const TypePtr* _adr_type; // memory effects of call or return
836 MachReturnNode() : MachNode() {
837 init_class_id(Class_MachReturn);
838 _adr_type = TypePtr::BOTTOM; // the default: all of memory
839 }
840
841 void set_adr_type(const TypePtr* atp) { _adr_type = atp; }
842
843 virtual const RegMask &in_RegMask(uint) const;
844 virtual bool pinned() const { return true; };
845 virtual const TypePtr *adr_type() const;
846 };
847
848 //------------------------------MachSafePointNode-----------------------------
849 // Machine-specific versions of safepoints
850 class MachSafePointNode : public MachReturnNode {
851 public:
852 OopMap* _oop_map; // Array of OopMap info (8-bit char) for GC
853 JVMState* _jvms; // Pointer to list of JVM State Objects
854 uint _jvmadj; // Extra delta to jvms indexes (mach. args)
855 bool _has_ea_local_in_scope; // NoEscape or ArgEscape objects in JVM States
856 OopMap* oop_map() const { return _oop_map; }
857 void set_oop_map(OopMap* om) { _oop_map = om; }
858
859 MachSafePointNode() : MachReturnNode(), _oop_map(nullptr), _jvms(nullptr), _jvmadj(0), _has_ea_local_in_scope(false) {
860 init_class_id(Class_MachSafePoint);
861 }
862
863 virtual JVMState* jvms() const { return _jvms; }
864 void set_jvms(JVMState* s) {
865 _jvms = s;
866 }
867 virtual const Type *bottom_type() const;
868
869 virtual const RegMask &in_RegMask(uint) const;
870
871 // Functionality from old debug nodes
872 Node *returnadr() const { return in(TypeFunc::ReturnAdr); }
873 Node *frameptr () const { return in(TypeFunc::FramePtr); }
874
875 Node *local(const JVMState* jvms, uint idx) const {
876 assert(verify_jvms(jvms), "jvms must match");
877 return in(_jvmadj + jvms->locoff() + idx);
878 }
879 Node *stack(const JVMState* jvms, uint idx) const {
880 assert(verify_jvms(jvms), "jvms must match");
881 return in(_jvmadj + jvms->stkoff() + idx);
882 }
883 Node *monitor_obj(const JVMState* jvms, uint idx) const {
884 assert(verify_jvms(jvms), "jvms must match");
885 return in(_jvmadj + jvms->monitor_obj_offset(idx));
886 }
887 Node *monitor_box(const JVMState* jvms, uint idx) const {
888 assert(verify_jvms(jvms), "jvms must match");
889 return in(_jvmadj + jvms->monitor_box_offset(idx));
890 }
891 Node* scalarized_obj(const JVMState* jvms, uint idx) const {
892 assert(verify_jvms(jvms), "jvms must match");
893 return in(_jvmadj + jvms->scloff() + idx);
894 }
895 void set_local(const JVMState* jvms, uint idx, Node *c) {
896 assert(verify_jvms(jvms), "jvms must match");
897 set_req(_jvmadj + jvms->locoff() + idx, c);
898 }
899 void set_stack(const JVMState* jvms, uint idx, Node *c) {
900 assert(verify_jvms(jvms), "jvms must match");
901 set_req(_jvmadj + jvms->stkoff() + idx, c);
902 }
903 void set_monitor(const JVMState* jvms, uint idx, Node *c) {
904 assert(verify_jvms(jvms), "jvms must match");
905 set_req(_jvmadj + jvms->monoff() + idx, c);
906 }
907 virtual uint size_of() const { return sizeof(MachSafePointNode); }
908 };
909
910 //------------------------------MachCallNode----------------------------------
911 // Machine-specific versions of subroutine calls
912 class MachCallNode : public MachSafePointNode {
913 protected:
914 virtual uint hash() const { return NO_HASH; } // CFG nodes do not hash
915 virtual bool cmp( const Node &n ) const;
916 virtual uint size_of() const = 0; // Size is bigger
917 public:
918 const TypeFunc *_tf; // Function type
919 address _entry_point; // Address of the method being called
920 float _cnt; // Estimate of number of times called
921 bool _guaranteed_safepoint; // Do we need to observe safepoint?
922
923 const TypeFunc* tf() const { return _tf; }
924 address entry_point() const { return _entry_point; }
925 float cnt() const { return _cnt; }
926
927 void set_tf(const TypeFunc* tf) { _tf = tf; }
928 void set_entry_point(address p) { _entry_point = p; }
929 void set_cnt(float c) { _cnt = c; }
930 void set_guaranteed_safepoint(bool b) { _guaranteed_safepoint = b; }
931
932 MachCallNode() : MachSafePointNode() {
933 init_class_id(Class_MachCall);
934 }
935
936 virtual const Type *bottom_type() const;
937 virtual bool pinned() const { return false; }
938 virtual const Type* Value(PhaseGVN* phase) const;
939 virtual const RegMask &in_RegMask(uint) const;
940 virtual int ret_addr_offset() { return 0; }
941
942 NOT_LP64(bool return_value_is_used() const;)
943
944 // Similar to cousin class CallNode::returns_pointer
945 bool returns_pointer() const;
946
947 bool guaranteed_safepoint() const { return _guaranteed_safepoint; }
948
949 #ifndef PRODUCT
950 virtual void dump_spec(outputStream *st) const;
951 #endif
952 };
953
954 //------------------------------MachCallJavaNode------------------------------
955 // "Base" class for machine-specific versions of subroutine calls
956 class MachCallJavaNode : public MachCallNode {
957 protected:
958 virtual bool cmp( const Node &n ) const;
959 virtual uint size_of() const; // Size is bigger
960 public:
961 ciMethod* _method; // Method being direct called
962 bool _override_symbolic_info; // Override symbolic call site info from bytecode
963 bool _optimized_virtual; // Tells if node is a static call or an optimized virtual
964 bool _arg_escape; // ArgEscape in parameter list
965 MachCallJavaNode() : MachCallNode(), _override_symbolic_info(false) {
966 init_class_id(Class_MachCallJava);
967 }
968
969 virtual const RegMask &in_RegMask(uint) const;
970
971 int resolved_method_index(C2_MacroAssembler *masm) const {
972 if (_override_symbolic_info) {
973 // Attach corresponding Method* to the call site, so VM can use it during resolution
974 // instead of querying symbolic info from bytecode.
975 assert(_method != nullptr, "method should be set");
976 assert(_method->constant_encoding()->is_method(), "should point to a Method");
977 return masm->code()->oop_recorder()->find_index(_method->constant_encoding());
978 }
979 return 0; // Use symbolic info from bytecode (resolved_method is null).
980 }
981
982 #ifndef PRODUCT
983 virtual void dump_spec(outputStream *st) const;
984 #endif
985 };
986
987 //------------------------------MachCallStaticJavaNode------------------------
988 // Machine-specific versions of monomorphic subroutine calls
989 class MachCallStaticJavaNode : public MachCallJavaNode {
990 virtual bool cmp( const Node &n ) const;
991 virtual uint size_of() const; // Size is bigger
992 public:
993 const char *_name; // Runtime wrapper name
994 MachCallStaticJavaNode() : MachCallJavaNode() {
995 init_class_id(Class_MachCallStaticJava);
996 }
997
998 // If this is an uncommon trap, return the request code, else zero.
999 int uncommon_trap_request() const;
1000
1001 virtual int ret_addr_offset();
1002 #ifndef PRODUCT
1003 virtual void dump_spec(outputStream *st) const;
1004 void dump_trap_args(outputStream *st) const;
1005 #endif
1006 };
1007
1008 //------------------------------MachCallDynamicJavaNode------------------------
1009 // Machine-specific versions of possibly megamorphic subroutine calls
1010 class MachCallDynamicJavaNode : public MachCallJavaNode {
1011 public:
1012 int _vtable_index;
1013 MachCallDynamicJavaNode() : MachCallJavaNode() {
1014 init_class_id(Class_MachCallDynamicJava);
1015 DEBUG_ONLY(_vtable_index = -99); // throw an assert if uninitialized
1016 }
1017 virtual int ret_addr_offset();
1018 #ifndef PRODUCT
1019 virtual void dump_spec(outputStream *st) const;
1020 #endif
1021 virtual uint size_of() const { return sizeof(MachCallDynamicJavaNode); }
1022 };
1023
1024 //------------------------------MachCallRuntimeNode----------------------------
1025 // Machine-specific versions of subroutine calls
1026 class MachCallRuntimeNode : public MachCallNode {
1027 virtual bool cmp( const Node &n ) const;
1028 virtual uint size_of() const; // Size is bigger
1029 public:
1030 const char *_name; // Printable name, if _method is null
1031 bool _leaf_no_fp; // Is this CallLeafNoFP?
1032 MachCallRuntimeNode() : MachCallNode() {
1033 init_class_id(Class_MachCallRuntime);
1034 }
1035 virtual int ret_addr_offset();
1036 #ifndef PRODUCT
1037 virtual void dump_spec(outputStream *st) const;
1038 #endif
1039 };
1040
1041 class MachCallLeafNode: public MachCallRuntimeNode {
1042 public:
1043 MachCallLeafNode() : MachCallRuntimeNode() {
1044 init_class_id(Class_MachCallLeaf);
1045 }
1046 };
1047
1048 //------------------------------MachHaltNode-----------------------------------
1049 // Machine-specific versions of halt nodes
1050 class MachHaltNode : public MachReturnNode {
1051 public:
1052 bool _reachable;
1053 const char* _halt_reason;
1054 virtual JVMState* jvms() const;
1055 virtual uint size_of() const { return sizeof(MachHaltNode); }
1056 bool is_reachable() const {
1057 return _reachable;
1058 }
1059 };
1060
1061 class MachMemBarNode : public MachNode {
1062 virtual uint size_of() const; // Size is bigger
1063 public:
1064 const TypePtr* _adr_type; // memory effects
1065 MachMemBarNode() : MachNode() {
1066 init_class_id(Class_MachMemBar);
1067 _adr_type = TypePtr::BOTTOM; // the default: all of memory
1068 }
1069
1070 void set_adr_type(const TypePtr* atp) { _adr_type = atp; }
1071 virtual const TypePtr *adr_type() const;
1072 };
1073
1074
1075 //------------------------------MachTempNode-----------------------------------
1076 // Node used by the adlc to construct inputs to represent temporary registers
1077 class MachTempNode : public MachNode {
1078 private:
1079 MachOper *_opnd_array[1];
1080
1081 public:
1082 virtual const RegMask &out_RegMask() const { return *_opnds[0]->in_RegMask(0); }
1083 virtual uint rule() const { return 9999999; }
1084 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {}
1085
1086 MachTempNode(MachOper* oper) {
1087 init_class_id(Class_MachTemp);
1088 _num_opnds = 1;
1089 _opnds = _opnd_array;
1090 add_req(nullptr);
1091 _opnds[0] = oper;
1092 }
1093 virtual uint size_of() const { return sizeof(MachTempNode); }
1094
1095 #ifndef PRODUCT
1096 virtual void format(PhaseRegAlloc *, outputStream *st ) const {}
1097 virtual const char *Name() const { return "MachTemp";}
1098 #endif
1099 };
1100
1101
1102
1103 //------------------------------labelOper--------------------------------------
1104 // Machine-independent version of label operand
1105 class labelOper : public MachOper {
1106 private:
1107 virtual uint num_edges() const { return 0; }
1108 public:
1109 // Supported for fixed size branches
1110 Label* _label; // Label for branch(es)
1111
1112 uint _block_num;
1113
1114 labelOper() : _label(nullptr), _block_num(0) {}
1115
1116 labelOper(Label* label, uint block_num) : _label(label), _block_num(block_num) {}
1117
1118 labelOper(labelOper* l) : _label(l->_label) , _block_num(l->_block_num) {}
1119
1120 virtual MachOper *clone() const;
1121
1122 virtual Label *label() const { assert(_label != nullptr, "need Label"); return _label; }
1123
1124 virtual uint opcode() const;
1125
1126 virtual uint hash() const;
1127 virtual bool cmp( const MachOper &oper ) const;
1128 #ifndef PRODUCT
1129 virtual const char *Name() const { return "Label";}
1130
1131 virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const;
1132 virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { int_format( ra, node, st ); }
1133 #endif
1134 };
1135
1136
1137 //------------------------------methodOper--------------------------------------
1138 // Machine-independent version of method operand
1139 class methodOper : public MachOper {
1140 private:
1141 virtual uint num_edges() const { return 0; }
1142 public:
1143 intptr_t _method; // Address of method
1144 methodOper() : _method(0) {}
1145 methodOper(intptr_t method) : _method(method) {}
1146
1147 virtual MachOper *clone() const;
1148
1149 virtual intptr_t method() const { return _method; }
1150
1151 virtual uint opcode() const;
1152
1153 virtual uint hash() const;
1154 virtual bool cmp( const MachOper &oper ) const;
1155 #ifndef PRODUCT
1156 virtual const char *Name() const { return "Method";}
1157
1158 virtual void int_format(PhaseRegAlloc *ra, const MachNode *node, outputStream *st) const;
1159 virtual void ext_format(PhaseRegAlloc *ra, const MachNode *node, int idx, outputStream *st) const { int_format( ra, node, st ); }
1160 #endif
1161 };
1162
1163 #endif // SHARE_OPTO_MACHNODE_HPP