1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #include "precompiled.hpp"
26 #include "gc/shared/barrierSet.hpp"
27 #include "gc/shared/c2/barrierSetC2.hpp"
28 #include "memory/allocation.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "oops/compressedOops.hpp"
31 #include "opto/ad.hpp"
32 #include "opto/addnode.hpp"
33 #include "opto/callnode.hpp"
34 #include "opto/idealGraphPrinter.hpp"
35 #include "opto/matcher.hpp"
36 #include "opto/memnode.hpp"
37 #include "opto/movenode.hpp"
38 #include "opto/opcodes.hpp"
39 #include "opto/regmask.hpp"
40 #include "opto/rootnode.hpp"
41 #include "opto/runtime.hpp"
42 #include "opto/type.hpp"
43 #include "opto/vectornode.hpp"
44 #include "runtime/os.inline.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "utilities/align.hpp"
47
48 OptoReg::Name OptoReg::c_frame_pointer;
49
50 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
51 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
52 RegMask Matcher::caller_save_regmask;
53 RegMask Matcher::caller_save_regmask_exclude_soe;
54 RegMask Matcher::mh_caller_save_regmask;
55 RegMask Matcher::mh_caller_save_regmask_exclude_soe;
56 RegMask Matcher::STACK_ONLY_mask;
57 RegMask Matcher::c_frame_ptr_mask;
58 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
59 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
60
61 //---------------------------Matcher-------------------------------------------
62 Matcher::Matcher()
63 : PhaseTransform( Phase::Ins_Select ),
64 _states_arena(Chunk::medium_size, mtCompiler),
65 _new_nodes(C->comp_arena()),
66 _visited(&_states_arena),
67 _shared(&_states_arena),
68 _dontcare(&_states_arena),
69 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
70 _swallowed(swallowed),
71 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
72 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
73 _must_clone(must_clone),
74 _shared_nodes(C->comp_arena()),
75 #ifndef PRODUCT
76 _old2new_map(C->comp_arena()),
77 _new2old_map(C->comp_arena()),
78 _reused(C->comp_arena()),
79 #endif // !PRODUCT
80 _allocation_started(false),
81 _ruleName(ruleName),
82 _register_save_policy(register_save_policy),
83 _c_reg_save_policy(c_reg_save_policy),
84 _register_save_type(register_save_type) {
85 C->set_matcher(this);
86
87 idealreg2spillmask [Op_RegI] = nullptr;
88 idealreg2spillmask [Op_RegN] = nullptr;
89 idealreg2spillmask [Op_RegL] = nullptr;
90 idealreg2spillmask [Op_RegF] = nullptr;
91 idealreg2spillmask [Op_RegD] = nullptr;
92 idealreg2spillmask [Op_RegP] = nullptr;
93 idealreg2spillmask [Op_VecA] = nullptr;
94 idealreg2spillmask [Op_VecS] = nullptr;
95 idealreg2spillmask [Op_VecD] = nullptr;
96 idealreg2spillmask [Op_VecX] = nullptr;
97 idealreg2spillmask [Op_VecY] = nullptr;
98 idealreg2spillmask [Op_VecZ] = nullptr;
99 idealreg2spillmask [Op_RegFlags] = nullptr;
100 idealreg2spillmask [Op_RegVectMask] = nullptr;
101
102 idealreg2debugmask [Op_RegI] = nullptr;
103 idealreg2debugmask [Op_RegN] = nullptr;
104 idealreg2debugmask [Op_RegL] = nullptr;
105 idealreg2debugmask [Op_RegF] = nullptr;
106 idealreg2debugmask [Op_RegD] = nullptr;
107 idealreg2debugmask [Op_RegP] = nullptr;
108 idealreg2debugmask [Op_VecA] = nullptr;
109 idealreg2debugmask [Op_VecS] = nullptr;
110 idealreg2debugmask [Op_VecD] = nullptr;
111 idealreg2debugmask [Op_VecX] = nullptr;
112 idealreg2debugmask [Op_VecY] = nullptr;
113 idealreg2debugmask [Op_VecZ] = nullptr;
114 idealreg2debugmask [Op_RegFlags] = nullptr;
115 idealreg2debugmask [Op_RegVectMask] = nullptr;
116
117 idealreg2mhdebugmask[Op_RegI] = nullptr;
118 idealreg2mhdebugmask[Op_RegN] = nullptr;
119 idealreg2mhdebugmask[Op_RegL] = nullptr;
120 idealreg2mhdebugmask[Op_RegF] = nullptr;
121 idealreg2mhdebugmask[Op_RegD] = nullptr;
122 idealreg2mhdebugmask[Op_RegP] = nullptr;
123 idealreg2mhdebugmask[Op_VecA] = nullptr;
124 idealreg2mhdebugmask[Op_VecS] = nullptr;
125 idealreg2mhdebugmask[Op_VecD] = nullptr;
126 idealreg2mhdebugmask[Op_VecX] = nullptr;
127 idealreg2mhdebugmask[Op_VecY] = nullptr;
128 idealreg2mhdebugmask[Op_VecZ] = nullptr;
129 idealreg2mhdebugmask[Op_RegFlags] = nullptr;
130 idealreg2mhdebugmask[Op_RegVectMask] = nullptr;
131
132 debug_only(_mem_node = nullptr;) // Ideal memory node consumed by mach node
133 }
134
135 //------------------------------warp_incoming_stk_arg------------------------
136 // This warps a VMReg into an OptoReg::Name
137 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
138 OptoReg::Name warped;
139 if( reg->is_stack() ) { // Stack slot argument?
140 warped = OptoReg::add(_old_SP, reg->reg2stack() );
141 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
142 if( warped >= _in_arg_limit )
143 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
144 if (!RegMask::can_represent_arg(warped)) {
145 // the compiler cannot represent this method's calling sequence
146 // Bailout. We do not have space to represent all arguments.
147 C->record_method_not_compilable("unsupported incoming calling sequence");
148 return OptoReg::Bad;
149 }
150 return warped;
151 }
152 return OptoReg::as_OptoReg(reg);
153 }
154
155 //---------------------------compute_old_SP------------------------------------
156 OptoReg::Name Compile::compute_old_SP() {
157 int fixed = fixed_slots();
158 int preserve = in_preserve_stack_slots();
159 return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots()));
160 }
161
162
163
164 #ifdef ASSERT
165 void Matcher::verify_new_nodes_only(Node* xroot) {
166 // Make sure that the new graph only references new nodes
167 ResourceMark rm;
168 Unique_Node_List worklist;
169 VectorSet visited;
170 worklist.push(xroot);
171 while (worklist.size() > 0) {
172 Node* n = worklist.pop();
173 visited.set(n->_idx);
174 assert(C->node_arena()->contains(n), "dead node");
175 for (uint j = 0; j < n->req(); j++) {
176 Node* in = n->in(j);
177 if (in != nullptr) {
178 assert(C->node_arena()->contains(in), "dead node");
179 if (!visited.test(in->_idx)) {
180 worklist.push(in);
181 }
182 }
183 }
184 }
185 }
186 #endif
187
188
189 //---------------------------match---------------------------------------------
190 void Matcher::match( ) {
191 if( MaxLabelRootDepth < 100 ) { // Too small?
192 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
193 MaxLabelRootDepth = 100;
194 }
195 // One-time initialization of some register masks.
196 init_spill_mask( C->root()->in(1) );
197 _return_addr_mask = return_addr();
198 #ifdef _LP64
199 // Pointers take 2 slots in 64-bit land
200 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
201 #endif
202
203 // Map a Java-signature return type into return register-value
204 // machine registers for 0, 1 and 2 returned values.
205 const TypeTuple *range = C->tf()->range();
206 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
207 // Get ideal-register return type
208 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
209 // Get machine return register
210 uint sop = C->start()->Opcode();
211 OptoRegPair regs = return_value(ireg);
212
213 // And mask for same
214 _return_value_mask = RegMask(regs.first());
215 if( OptoReg::is_valid(regs.second()) )
216 _return_value_mask.Insert(regs.second());
217 }
218
219 // ---------------
220 // Frame Layout
221
222 // Need the method signature to determine the incoming argument types,
223 // because the types determine which registers the incoming arguments are
224 // in, and this affects the matched code.
225 const TypeTuple *domain = C->tf()->domain();
226 uint argcnt = domain->cnt() - TypeFunc::Parms;
227 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
228 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
229 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
230 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
231 uint i;
232 for( i = 0; i<argcnt; i++ ) {
233 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
234 }
235
236 // Pass array of ideal registers and length to USER code (from the AD file)
237 // that will convert this to an array of register numbers.
238 const StartNode *start = C->start();
239 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
240 #ifdef ASSERT
241 // Sanity check users' calling convention. Real handy while trying to
242 // get the initial port correct.
243 { for (uint i = 0; i<argcnt; i++) {
244 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
245 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
246 _parm_regs[i].set_bad();
247 continue;
248 }
249 VMReg parm_reg = vm_parm_regs[i].first();
250 assert(parm_reg->is_valid(), "invalid arg?");
251 if (parm_reg->is_reg()) {
252 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
253 assert(can_be_java_arg(opto_parm_reg) ||
254 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
255 opto_parm_reg == inline_cache_reg(),
256 "parameters in register must be preserved by runtime stubs");
257 }
258 for (uint j = 0; j < i; j++) {
259 assert(parm_reg != vm_parm_regs[j].first(),
260 "calling conv. must produce distinct regs");
261 }
262 }
263 }
264 #endif
265
266 // Do some initial frame layout.
267
268 // Compute the old incoming SP (may be called FP) as
269 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
270 _old_SP = C->compute_old_SP();
271 assert( is_even(_old_SP), "must be even" );
272
273 // Compute highest incoming stack argument as
274 // _old_SP + out_preserve_stack_slots + incoming argument size.
275 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
276 assert( is_even(_in_arg_limit), "out_preserve must be even" );
277 for( i = 0; i < argcnt; i++ ) {
278 // Permit args to have no register
279 _calling_convention_mask[i].Clear();
280 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
281 _parm_regs[i].set_bad();
282 continue;
283 }
284 // calling_convention returns stack arguments as a count of
285 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
286 // the allocators point of view, taking into account all the
287 // preserve area, locks & pad2.
288
289 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
290 if( OptoReg::is_valid(reg1))
291 _calling_convention_mask[i].Insert(reg1);
292
293 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
294 if( OptoReg::is_valid(reg2))
295 _calling_convention_mask[i].Insert(reg2);
296
297 // Saved biased stack-slot register number
298 _parm_regs[i].set_pair(reg2, reg1);
299 }
300
301 // Finally, make sure the incoming arguments take up an even number of
302 // words, in case the arguments or locals need to contain doubleword stack
303 // slots. The rest of the system assumes that stack slot pairs (in
304 // particular, in the spill area) which look aligned will in fact be
305 // aligned relative to the stack pointer in the target machine. Double
306 // stack slots will always be allocated aligned.
307 _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong));
308
309 // Compute highest outgoing stack argument as
310 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
311 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
312 assert( is_even(_out_arg_limit), "out_preserve must be even" );
313
314 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
315 // the compiler cannot represent this method's calling sequence
316 // Bailout. We do not have space to represent all arguments.
317 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
318 }
319
320 if (C->failing()) return; // bailed out on incoming arg failure
321
322 // ---------------
323 // Collect roots of matcher trees. Every node for which
324 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
325 // can be a valid interior of some tree.
326 find_shared( C->root() );
327 find_shared( C->top() );
328
329 C->print_method(PHASE_BEFORE_MATCHING, 1);
330
331 // Create new ideal node ConP #null even if it does exist in old space
332 // to avoid false sharing if the corresponding mach node is not used.
333 // The corresponding mach node is only used in rare cases for derived
334 // pointers.
335 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
336
337 // Swap out to old-space; emptying new-space
338 Arena* old = C->swap_old_and_new();
339
340 // Save debug and profile information for nodes in old space:
341 _old_node_note_array = C->node_note_array();
342 if (_old_node_note_array != nullptr) {
343 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
344 (C->comp_arena(), _old_node_note_array->length(),
345 0, nullptr));
346 }
347
348 // Pre-size the new_node table to avoid the need for range checks.
349 grow_new_node_array(C->unique());
350
351 // Reset node counter so MachNodes start with _idx at 0
352 int live_nodes = C->live_nodes();
353 C->set_unique(0);
354 C->reset_dead_node_list();
355
356 // Recursively match trees from old space into new space.
357 // Correct leaves of new-space Nodes; they point to old-space.
358 _visited.clear();
359 Node* const n = xform(C->top(), live_nodes);
360 if (C->failing()) return;
361 C->set_cached_top_node(n);
362 if (!C->failing()) {
363 Node* xroot = xform( C->root(), 1 );
364 if (C->failing()) return;
365 if (xroot == nullptr) {
366 Matcher::soft_match_failure(); // recursive matching process failed
367 assert(false, "instruction match failed");
368 C->record_method_not_compilable("instruction match failed");
369 } else {
370 // During matching shared constants were attached to C->root()
371 // because xroot wasn't available yet, so transfer the uses to
372 // the xroot.
373 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
374 Node* n = C->root()->fast_out(j);
375 if (C->node_arena()->contains(n)) {
376 assert(n->in(0) == C->root(), "should be control user");
377 n->set_req(0, xroot);
378 --j;
379 --jmax;
380 }
381 }
382
383 // Generate new mach node for ConP #null
384 assert(new_ideal_null != nullptr, "sanity");
385 _mach_null = match_tree(new_ideal_null);
386 // Don't set control, it will confuse GCM since there are no uses.
387 // The control will be set when this node is used first time
388 // in find_base_for_derived().
389 assert(_mach_null != nullptr, "");
390
391 C->set_root(xroot->is_Root() ? xroot->as_Root() : nullptr);
392
393 #ifdef ASSERT
394 verify_new_nodes_only(xroot);
395 #endif
396 }
397 }
398 if (C->top() == nullptr || C->root() == nullptr) {
399 // New graph lost. This is due to a compilation failure we encountered earlier.
400 stringStream ss;
401 if (C->failure_reason() != nullptr) {
402 ss.print("graph lost: %s", C->failure_reason());
403 } else {
404 assert(C->failure_reason() != nullptr, "graph lost: reason unknown");
405 ss.print("graph lost: reason unknown");
406 }
407 C->record_method_not_compilable(ss.as_string());
408 }
409 if (C->failing()) {
410 // delete old;
411 old->destruct_contents();
412 return;
413 }
414 assert( C->top(), "" );
415 assert( C->root(), "" );
416 validate_null_checks();
417
418 // Now smoke old-space
419 NOT_DEBUG( old->destruct_contents() );
420
421 // ------------------------
422 // Set up save-on-entry registers.
423 Fixup_Save_On_Entry( );
424
425 { // Cleanup mach IR after selection phase is over.
426 Compile::TracePhase tp("postselect_cleanup", &timers[_t_postselect_cleanup]);
427 do_postselect_cleanup();
428 if (C->failing()) return;
429 assert(verify_after_postselect_cleanup(), "");
430 }
431 }
432
433 //------------------------------Fixup_Save_On_Entry----------------------------
434 // The stated purpose of this routine is to take care of save-on-entry
435 // registers. However, the overall goal of the Match phase is to convert into
436 // machine-specific instructions which have RegMasks to guide allocation.
437 // So what this procedure really does is put a valid RegMask on each input
438 // to the machine-specific variations of all Return, TailCall and Halt
439 // instructions. It also adds edgs to define the save-on-entry values (and of
440 // course gives them a mask).
441
442 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
443 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
444 // Do all the pre-defined register masks
445 rms[TypeFunc::Control ] = RegMask::Empty;
446 rms[TypeFunc::I_O ] = RegMask::Empty;
447 rms[TypeFunc::Memory ] = RegMask::Empty;
448 rms[TypeFunc::ReturnAdr] = ret_adr;
449 rms[TypeFunc::FramePtr ] = fp;
450 return rms;
451 }
452
453 int Matcher::scalable_predicate_reg_slots() {
454 assert(Matcher::has_predicated_vectors() && Matcher::supports_scalable_vector(),
455 "scalable predicate vector should be supported");
456 int vector_reg_bit_size = Matcher::scalable_vector_reg_size(T_BYTE) << LogBitsPerByte;
457 // We assume each predicate register is one-eighth of the size of
458 // scalable vector register, one mask bit per vector byte.
459 int predicate_reg_bit_size = vector_reg_bit_size >> 3;
460 // Compute number of slots which is required when scalable predicate
461 // register is spilled. E.g. if scalable vector register is 640 bits,
462 // predicate register is 80 bits, which is 2.5 * slots.
463 // We will round up the slot number to power of 2, which is required
464 // by find_first_set().
465 int slots = predicate_reg_bit_size & (BitsPerInt - 1)
466 ? (predicate_reg_bit_size >> LogBitsPerInt) + 1
467 : predicate_reg_bit_size >> LogBitsPerInt;
468 return round_up_power_of_2(slots);
469 }
470
471 #define NOF_STACK_MASKS (3*13)
472
473 // Create the initial stack mask used by values spilling to the stack.
474 // Disallow any debug info in outgoing argument areas by setting the
475 // initial mask accordingly.
476 void Matcher::init_first_stack_mask() {
477
478 // Allocate storage for spill masks as masks for the appropriate load type.
479 RegMask *rms = (RegMask*)C->comp_arena()->AmallocWords(sizeof(RegMask) * NOF_STACK_MASKS);
480
481 // Initialize empty placeholder masks into the newly allocated arena
482 for (int i = 0; i < NOF_STACK_MASKS; i++) {
483 new (rms + i) RegMask();
484 }
485
486 idealreg2spillmask [Op_RegN] = &rms[0];
487 idealreg2spillmask [Op_RegI] = &rms[1];
488 idealreg2spillmask [Op_RegL] = &rms[2];
489 idealreg2spillmask [Op_RegF] = &rms[3];
490 idealreg2spillmask [Op_RegD] = &rms[4];
491 idealreg2spillmask [Op_RegP] = &rms[5];
492
493 idealreg2debugmask [Op_RegN] = &rms[6];
494 idealreg2debugmask [Op_RegI] = &rms[7];
495 idealreg2debugmask [Op_RegL] = &rms[8];
496 idealreg2debugmask [Op_RegF] = &rms[9];
497 idealreg2debugmask [Op_RegD] = &rms[10];
498 idealreg2debugmask [Op_RegP] = &rms[11];
499
500 idealreg2mhdebugmask[Op_RegN] = &rms[12];
501 idealreg2mhdebugmask[Op_RegI] = &rms[13];
502 idealreg2mhdebugmask[Op_RegL] = &rms[14];
503 idealreg2mhdebugmask[Op_RegF] = &rms[15];
504 idealreg2mhdebugmask[Op_RegD] = &rms[16];
505 idealreg2mhdebugmask[Op_RegP] = &rms[17];
506
507 idealreg2spillmask [Op_VecA] = &rms[18];
508 idealreg2spillmask [Op_VecS] = &rms[19];
509 idealreg2spillmask [Op_VecD] = &rms[20];
510 idealreg2spillmask [Op_VecX] = &rms[21];
511 idealreg2spillmask [Op_VecY] = &rms[22];
512 idealreg2spillmask [Op_VecZ] = &rms[23];
513
514 idealreg2debugmask [Op_VecA] = &rms[24];
515 idealreg2debugmask [Op_VecS] = &rms[25];
516 idealreg2debugmask [Op_VecD] = &rms[26];
517 idealreg2debugmask [Op_VecX] = &rms[27];
518 idealreg2debugmask [Op_VecY] = &rms[28];
519 idealreg2debugmask [Op_VecZ] = &rms[29];
520
521 idealreg2mhdebugmask[Op_VecA] = &rms[30];
522 idealreg2mhdebugmask[Op_VecS] = &rms[31];
523 idealreg2mhdebugmask[Op_VecD] = &rms[32];
524 idealreg2mhdebugmask[Op_VecX] = &rms[33];
525 idealreg2mhdebugmask[Op_VecY] = &rms[34];
526 idealreg2mhdebugmask[Op_VecZ] = &rms[35];
527
528 idealreg2spillmask [Op_RegVectMask] = &rms[36];
529 idealreg2debugmask [Op_RegVectMask] = &rms[37];
530 idealreg2mhdebugmask[Op_RegVectMask] = &rms[38];
531
532 OptoReg::Name i;
533
534 // At first, start with the empty mask
535 C->FIRST_STACK_mask().Clear();
536
537 // Add in the incoming argument area
538 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
539 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
540 C->FIRST_STACK_mask().Insert(i);
541 }
542 // Add in all bits past the outgoing argument area
543 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
544 "must be able to represent all call arguments in reg mask");
545 OptoReg::Name init = _out_arg_limit;
546 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
547 C->FIRST_STACK_mask().Insert(i);
548 }
549 // Finally, set the "infinite stack" bit.
550 C->FIRST_STACK_mask().set_AllStack();
551
552 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
553 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
554 // Keep spill masks aligned.
555 aligned_stack_mask.clear_to_pairs();
556 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
557 RegMask scalable_stack_mask = aligned_stack_mask;
558
559 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
560 #ifdef _LP64
561 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
562 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
563 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
564 #else
565 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
566 #endif
567 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
568 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
569 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
570 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
571 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
572 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
573 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
574 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
575
576 if (Matcher::has_predicated_vectors()) {
577 *idealreg2spillmask[Op_RegVectMask] = *idealreg2regmask[Op_RegVectMask];
578 idealreg2spillmask[Op_RegVectMask]->OR(aligned_stack_mask);
579 } else {
580 *idealreg2spillmask[Op_RegVectMask] = RegMask::Empty;
581 }
582
583 if (Matcher::vector_size_supported(T_BYTE,4)) {
584 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
585 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
586 } else {
587 *idealreg2spillmask[Op_VecS] = RegMask::Empty;
588 }
589
590 if (Matcher::vector_size_supported(T_FLOAT,2)) {
591 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
592 // RA guarantees such alignment since it is needed for Double and Long values.
593 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
594 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
595 } else {
596 *idealreg2spillmask[Op_VecD] = RegMask::Empty;
597 }
598
599 if (Matcher::vector_size_supported(T_FLOAT,4)) {
600 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
601 //
602 // RA can use input arguments stack slots for spills but until RA
603 // we don't know frame size and offset of input arg stack slots.
604 //
605 // Exclude last input arg stack slots to avoid spilling vectors there
606 // otherwise vector spills could stomp over stack slots in caller frame.
607 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
608 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
609 aligned_stack_mask.Remove(in);
610 in = OptoReg::add(in, -1);
611 }
612 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
613 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
614 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
615 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
616 } else {
617 *idealreg2spillmask[Op_VecX] = RegMask::Empty;
618 }
619
620 if (Matcher::vector_size_supported(T_FLOAT,8)) {
621 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
622 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
623 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
624 aligned_stack_mask.Remove(in);
625 in = OptoReg::add(in, -1);
626 }
627 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
628 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
629 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
630 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
631 } else {
632 *idealreg2spillmask[Op_VecY] = RegMask::Empty;
633 }
634
635 if (Matcher::vector_size_supported(T_FLOAT,16)) {
636 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
637 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
638 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
639 aligned_stack_mask.Remove(in);
640 in = OptoReg::add(in, -1);
641 }
642 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
643 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
644 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
645 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
646 } else {
647 *idealreg2spillmask[Op_VecZ] = RegMask::Empty;
648 }
649
650 if (Matcher::supports_scalable_vector()) {
651 int k = 1;
652 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
653 if (Matcher::has_predicated_vectors()) {
654 // Exclude last input arg stack slots to avoid spilling vector register there,
655 // otherwise RegVectMask spills could stomp over stack slots in caller frame.
656 for (; (in >= init_in) && (k < scalable_predicate_reg_slots()); k++) {
657 scalable_stack_mask.Remove(in);
658 in = OptoReg::add(in, -1);
659 }
660
661 // For RegVectMask
662 scalable_stack_mask.clear_to_sets(scalable_predicate_reg_slots());
663 assert(scalable_stack_mask.is_AllStack(), "should be infinite stack");
664 *idealreg2spillmask[Op_RegVectMask] = *idealreg2regmask[Op_RegVectMask];
665 idealreg2spillmask[Op_RegVectMask]->OR(scalable_stack_mask);
666 }
667
668 // Exclude last input arg stack slots to avoid spilling vector register there,
669 // otherwise vector spills could stomp over stack slots in caller frame.
670 for (; (in >= init_in) && (k < scalable_vector_reg_size(T_FLOAT)); k++) {
671 scalable_stack_mask.Remove(in);
672 in = OptoReg::add(in, -1);
673 }
674
675 // For VecA
676 scalable_stack_mask.clear_to_sets(RegMask::SlotsPerVecA);
677 assert(scalable_stack_mask.is_AllStack(), "should be infinite stack");
678 *idealreg2spillmask[Op_VecA] = *idealreg2regmask[Op_VecA];
679 idealreg2spillmask[Op_VecA]->OR(scalable_stack_mask);
680 } else {
681 *idealreg2spillmask[Op_VecA] = RegMask::Empty;
682 }
683
684 if (UseFPUForSpilling) {
685 // This mask logic assumes that the spill operations are
686 // symmetric and that the registers involved are the same size.
687 // On sparc for instance we may have to use 64 bit moves will
688 // kill 2 registers when used with F0-F31.
689 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
690 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
691 #ifdef _LP64
692 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
693 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
694 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
695 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
696 #else
697 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
698 #ifdef ARM
699 // ARM has support for moving 64bit values between a pair of
700 // integer registers and a double register
701 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
702 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
703 #endif
704 #endif
705 }
706
707 // Make up debug masks. Any spill slot plus callee-save (SOE) registers.
708 // Caller-save (SOC, AS) registers are assumed to be trashable by the various
709 // inline-cache fixup routines.
710 *idealreg2debugmask [Op_RegN] = *idealreg2spillmask[Op_RegN];
711 *idealreg2debugmask [Op_RegI] = *idealreg2spillmask[Op_RegI];
712 *idealreg2debugmask [Op_RegL] = *idealreg2spillmask[Op_RegL];
713 *idealreg2debugmask [Op_RegF] = *idealreg2spillmask[Op_RegF];
714 *idealreg2debugmask [Op_RegD] = *idealreg2spillmask[Op_RegD];
715 *idealreg2debugmask [Op_RegP] = *idealreg2spillmask[Op_RegP];
716 *idealreg2debugmask [Op_RegVectMask] = *idealreg2spillmask[Op_RegVectMask];
717
718 *idealreg2debugmask [Op_VecA] = *idealreg2spillmask[Op_VecA];
719 *idealreg2debugmask [Op_VecS] = *idealreg2spillmask[Op_VecS];
720 *idealreg2debugmask [Op_VecD] = *idealreg2spillmask[Op_VecD];
721 *idealreg2debugmask [Op_VecX] = *idealreg2spillmask[Op_VecX];
722 *idealreg2debugmask [Op_VecY] = *idealreg2spillmask[Op_VecY];
723 *idealreg2debugmask [Op_VecZ] = *idealreg2spillmask[Op_VecZ];
724
725 *idealreg2mhdebugmask[Op_RegN] = *idealreg2spillmask[Op_RegN];
726 *idealreg2mhdebugmask[Op_RegI] = *idealreg2spillmask[Op_RegI];
727 *idealreg2mhdebugmask[Op_RegL] = *idealreg2spillmask[Op_RegL];
728 *idealreg2mhdebugmask[Op_RegF] = *idealreg2spillmask[Op_RegF];
729 *idealreg2mhdebugmask[Op_RegD] = *idealreg2spillmask[Op_RegD];
730 *idealreg2mhdebugmask[Op_RegP] = *idealreg2spillmask[Op_RegP];
731 *idealreg2mhdebugmask[Op_RegVectMask] = *idealreg2spillmask[Op_RegVectMask];
732
733 *idealreg2mhdebugmask[Op_VecA] = *idealreg2spillmask[Op_VecA];
734 *idealreg2mhdebugmask[Op_VecS] = *idealreg2spillmask[Op_VecS];
735 *idealreg2mhdebugmask[Op_VecD] = *idealreg2spillmask[Op_VecD];
736 *idealreg2mhdebugmask[Op_VecX] = *idealreg2spillmask[Op_VecX];
737 *idealreg2mhdebugmask[Op_VecY] = *idealreg2spillmask[Op_VecY];
738 *idealreg2mhdebugmask[Op_VecZ] = *idealreg2spillmask[Op_VecZ];
739
740 // Prevent stub compilations from attempting to reference
741 // callee-saved (SOE) registers from debug info
742 bool exclude_soe = !Compile::current()->is_method_compilation();
743 RegMask* caller_save_mask = exclude_soe ? &caller_save_regmask_exclude_soe : &caller_save_regmask;
744 RegMask* mh_caller_save_mask = exclude_soe ? &mh_caller_save_regmask_exclude_soe : &mh_caller_save_regmask;
745
746 idealreg2debugmask[Op_RegN]->SUBTRACT(*caller_save_mask);
747 idealreg2debugmask[Op_RegI]->SUBTRACT(*caller_save_mask);
748 idealreg2debugmask[Op_RegL]->SUBTRACT(*caller_save_mask);
749 idealreg2debugmask[Op_RegF]->SUBTRACT(*caller_save_mask);
750 idealreg2debugmask[Op_RegD]->SUBTRACT(*caller_save_mask);
751 idealreg2debugmask[Op_RegP]->SUBTRACT(*caller_save_mask);
752 idealreg2debugmask[Op_RegVectMask]->SUBTRACT(*caller_save_mask);
753
754 idealreg2debugmask[Op_VecA]->SUBTRACT(*caller_save_mask);
755 idealreg2debugmask[Op_VecS]->SUBTRACT(*caller_save_mask);
756 idealreg2debugmask[Op_VecD]->SUBTRACT(*caller_save_mask);
757 idealreg2debugmask[Op_VecX]->SUBTRACT(*caller_save_mask);
758 idealreg2debugmask[Op_VecY]->SUBTRACT(*caller_save_mask);
759 idealreg2debugmask[Op_VecZ]->SUBTRACT(*caller_save_mask);
760
761 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(*mh_caller_save_mask);
762 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(*mh_caller_save_mask);
763 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(*mh_caller_save_mask);
764 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(*mh_caller_save_mask);
765 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(*mh_caller_save_mask);
766 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(*mh_caller_save_mask);
767 idealreg2mhdebugmask[Op_RegVectMask]->SUBTRACT(*mh_caller_save_mask);
768
769 idealreg2mhdebugmask[Op_VecA]->SUBTRACT(*mh_caller_save_mask);
770 idealreg2mhdebugmask[Op_VecS]->SUBTRACT(*mh_caller_save_mask);
771 idealreg2mhdebugmask[Op_VecD]->SUBTRACT(*mh_caller_save_mask);
772 idealreg2mhdebugmask[Op_VecX]->SUBTRACT(*mh_caller_save_mask);
773 idealreg2mhdebugmask[Op_VecY]->SUBTRACT(*mh_caller_save_mask);
774 idealreg2mhdebugmask[Op_VecZ]->SUBTRACT(*mh_caller_save_mask);
775 }
776
777 //---------------------------is_save_on_entry----------------------------------
778 bool Matcher::is_save_on_entry(int reg) {
779 return
780 _register_save_policy[reg] == 'E' ||
781 _register_save_policy[reg] == 'A'; // Save-on-entry register?
782 }
783
784 //---------------------------Fixup_Save_On_Entry-------------------------------
785 void Matcher::Fixup_Save_On_Entry( ) {
786 init_first_stack_mask();
787
788 Node *root = C->root(); // Short name for root
789 // Count number of save-on-entry registers.
790 uint soe_cnt = number_of_saved_registers();
791 uint i;
792
793 // Find the procedure Start Node
794 StartNode *start = C->start();
795 assert( start, "Expect a start node" );
796
797 // Input RegMask array shared by all Returns.
798 // The type for doubles and longs has a count of 2, but
799 // there is only 1 returned value
800 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
801 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
802 // Returns have 0 or 1 returned values depending on call signature.
803 // Return register is specified by return_value in the AD file.
804 if (ret_edge_cnt > TypeFunc::Parms)
805 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
806
807 // Input RegMask array shared by all ForwardExceptions
808 uint forw_exc_edge_cnt = TypeFunc::Parms;
809 RegMask* forw_exc_rms = init_input_masks( forw_exc_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
810
811 // Input RegMask array shared by all Rethrows.
812 uint reth_edge_cnt = TypeFunc::Parms+1;
813 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
814 // Rethrow takes exception oop only, but in the argument 0 slot.
815 OptoReg::Name reg = find_receiver();
816 if (reg >= 0) {
817 reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
818 #ifdef _LP64
819 // Need two slots for ptrs in 64-bit land
820 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
821 #endif
822 }
823
824 // Input RegMask array shared by all TailCalls
825 uint tail_call_edge_cnt = TypeFunc::Parms+2;
826 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
827
828 // Input RegMask array shared by all TailJumps
829 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
830 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
831
832 // TailCalls have 2 returned values (target & moop), whose masks come
833 // from the usual MachNode/MachOper mechanism. Find a sample
834 // TailCall to extract these masks and put the correct masks into
835 // the tail_call_rms array.
836 for( i=1; i < root->req(); i++ ) {
837 MachReturnNode *m = root->in(i)->as_MachReturn();
838 if( m->ideal_Opcode() == Op_TailCall ) {
839 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
840 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
841 break;
842 }
843 }
844
845 // TailJumps have 2 returned values (target & ex_oop), whose masks come
846 // from the usual MachNode/MachOper mechanism. Find a sample
847 // TailJump to extract these masks and put the correct masks into
848 // the tail_jump_rms array.
849 for( i=1; i < root->req(); i++ ) {
850 MachReturnNode *m = root->in(i)->as_MachReturn();
851 if( m->ideal_Opcode() == Op_TailJump ) {
852 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
853 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
854 break;
855 }
856 }
857
858 // Input RegMask array shared by all Halts
859 uint halt_edge_cnt = TypeFunc::Parms;
860 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
861
862 // Capture the return input masks into each exit flavor
863 for( i=1; i < root->req(); i++ ) {
864 MachReturnNode *exit = root->in(i)->as_MachReturn();
865 switch( exit->ideal_Opcode() ) {
866 case Op_Return : exit->_in_rms = ret_rms; break;
867 case Op_Rethrow : exit->_in_rms = reth_rms; break;
868 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
869 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
870 case Op_ForwardException: exit->_in_rms = forw_exc_rms; break;
871 case Op_Halt : exit->_in_rms = halt_rms; break;
872 default : ShouldNotReachHere();
873 }
874 }
875
876 // Next unused projection number from Start.
877 int proj_cnt = C->tf()->domain()->cnt();
878
879 // Do all the save-on-entry registers. Make projections from Start for
880 // them, and give them a use at the exit points. To the allocator, they
881 // look like incoming register arguments.
882 for( i = 0; i < _last_Mach_Reg; i++ ) {
883 if( is_save_on_entry(i) ) {
884
885 // Add the save-on-entry to the mask array
886 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
887 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
888 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
889 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
890 forw_exc_rms [ forw_exc_edge_cnt] = mreg2regmask[i];
891 // Halts need the SOE registers, but only in the stack as debug info.
892 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
893 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
894
895 Node *mproj;
896
897 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
898 // into a single RegD.
899 if( (i&1) == 0 &&
900 _register_save_type[i ] == Op_RegF &&
901 _register_save_type[i+1] == Op_RegF &&
902 is_save_on_entry(i+1) ) {
903 // Add other bit for double
904 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
905 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
906 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
907 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
908 forw_exc_rms [ forw_exc_edge_cnt].Insert(OptoReg::Name(i+1));
909 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
910 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
911 proj_cnt += 2; // Skip 2 for doubles
912 }
913 else if( (i&1) == 1 && // Else check for high half of double
914 _register_save_type[i-1] == Op_RegF &&
915 _register_save_type[i ] == Op_RegF &&
916 is_save_on_entry(i-1) ) {
917 ret_rms [ ret_edge_cnt] = RegMask::Empty;
918 reth_rms [ reth_edge_cnt] = RegMask::Empty;
919 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
920 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
921 forw_exc_rms [ forw_exc_edge_cnt] = RegMask::Empty;
922 halt_rms [ halt_edge_cnt] = RegMask::Empty;
923 mproj = C->top();
924 }
925 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
926 // into a single RegL.
927 else if( (i&1) == 0 &&
928 _register_save_type[i ] == Op_RegI &&
929 _register_save_type[i+1] == Op_RegI &&
930 is_save_on_entry(i+1) ) {
931 // Add other bit for long
932 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
933 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
934 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
935 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
936 forw_exc_rms [ forw_exc_edge_cnt].Insert(OptoReg::Name(i+1));
937 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
938 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
939 proj_cnt += 2; // Skip 2 for longs
940 }
941 else if( (i&1) == 1 && // Else check for high half of long
942 _register_save_type[i-1] == Op_RegI &&
943 _register_save_type[i ] == Op_RegI &&
944 is_save_on_entry(i-1) ) {
945 ret_rms [ ret_edge_cnt] = RegMask::Empty;
946 reth_rms [ reth_edge_cnt] = RegMask::Empty;
947 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
948 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
949 forw_exc_rms [ forw_exc_edge_cnt] = RegMask::Empty;
950 halt_rms [ halt_edge_cnt] = RegMask::Empty;
951 mproj = C->top();
952 } else {
953 // Make a projection for it off the Start
954 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
955 }
956
957 ret_edge_cnt ++;
958 reth_edge_cnt ++;
959 tail_call_edge_cnt ++;
960 tail_jump_edge_cnt ++;
961 forw_exc_edge_cnt++;
962 halt_edge_cnt ++;
963
964 // Add a use of the SOE register to all exit paths
965 for (uint j=1; j < root->req(); j++) {
966 root->in(j)->add_req(mproj);
967 }
968 } // End of if a save-on-entry register
969 } // End of for all machine registers
970 }
971
972 //------------------------------init_spill_mask--------------------------------
973 void Matcher::init_spill_mask( Node *ret ) {
974 if( idealreg2regmask[Op_RegI] ) return; // One time only init
975
976 OptoReg::c_frame_pointer = c_frame_pointer();
977 c_frame_ptr_mask = c_frame_pointer();
978 #ifdef _LP64
979 // pointers are twice as big
980 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
981 #endif
982
983 // Start at OptoReg::stack0()
984 STACK_ONLY_mask.Clear();
985 OptoReg::Name init = OptoReg::stack2reg(0);
986 // STACK_ONLY_mask is all stack bits
987 OptoReg::Name i;
988 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
989 STACK_ONLY_mask.Insert(i);
990 // Also set the "infinite stack" bit.
991 STACK_ONLY_mask.set_AllStack();
992
993 for (i = OptoReg::Name(0); i < OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i, 1)) {
994 // Copy the register names over into the shared world.
995 // SharedInfo::regName[i] = regName[i];
996 // Handy RegMasks per machine register
997 mreg2regmask[i].Insert(i);
998
999 // Set up regmasks used to exclude save-on-call (and always-save) registers from debug masks.
1000 if (_register_save_policy[i] == 'C' ||
1001 _register_save_policy[i] == 'A') {
1002 caller_save_regmask.Insert(i);
1003 mh_caller_save_regmask.Insert(i);
1004 }
1005 // Exclude save-on-entry registers from debug masks for stub compilations.
1006 if (_register_save_policy[i] == 'C' ||
1007 _register_save_policy[i] == 'A' ||
1008 _register_save_policy[i] == 'E') {
1009 caller_save_regmask_exclude_soe.Insert(i);
1010 mh_caller_save_regmask_exclude_soe.Insert(i);
1011 }
1012 }
1013
1014 // Also exclude the register we use to save the SP for MethodHandle
1015 // invokes to from the corresponding MH debug masks
1016 const RegMask sp_save_mask = method_handle_invoke_SP_save_mask();
1017 mh_caller_save_regmask.OR(sp_save_mask);
1018 mh_caller_save_regmask_exclude_soe.OR(sp_save_mask);
1019
1020 // Grab the Frame Pointer
1021 Node *fp = ret->in(TypeFunc::FramePtr);
1022 // Share frame pointer while making spill ops
1023 set_shared(fp);
1024
1025 // Get the ADLC notion of the right regmask, for each basic type.
1026 #ifdef _LP64
1027 idealreg2regmask[Op_RegN] = regmask_for_ideal_register(Op_RegN, ret);
1028 #endif
1029 idealreg2regmask[Op_RegI] = regmask_for_ideal_register(Op_RegI, ret);
1030 idealreg2regmask[Op_RegP] = regmask_for_ideal_register(Op_RegP, ret);
1031 idealreg2regmask[Op_RegF] = regmask_for_ideal_register(Op_RegF, ret);
1032 idealreg2regmask[Op_RegD] = regmask_for_ideal_register(Op_RegD, ret);
1033 idealreg2regmask[Op_RegL] = regmask_for_ideal_register(Op_RegL, ret);
1034 idealreg2regmask[Op_VecA] = regmask_for_ideal_register(Op_VecA, ret);
1035 idealreg2regmask[Op_VecS] = regmask_for_ideal_register(Op_VecS, ret);
1036 idealreg2regmask[Op_VecD] = regmask_for_ideal_register(Op_VecD, ret);
1037 idealreg2regmask[Op_VecX] = regmask_for_ideal_register(Op_VecX, ret);
1038 idealreg2regmask[Op_VecY] = regmask_for_ideal_register(Op_VecY, ret);
1039 idealreg2regmask[Op_VecZ] = regmask_for_ideal_register(Op_VecZ, ret);
1040 idealreg2regmask[Op_RegVectMask] = regmask_for_ideal_register(Op_RegVectMask, ret);
1041 }
1042
1043 #ifdef ASSERT
1044 static void match_alias_type(Compile* C, Node* n, Node* m) {
1045 if (!VerifyAliases) return; // do not go looking for trouble by default
1046 const TypePtr* nat = n->adr_type();
1047 const TypePtr* mat = m->adr_type();
1048 int nidx = C->get_alias_index(nat);
1049 int midx = C->get_alias_index(mat);
1050 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
1051 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
1052 for (uint i = 1; i < n->req(); i++) {
1053 Node* n1 = n->in(i);
1054 const TypePtr* n1at = n1->adr_type();
1055 if (n1at != nullptr) {
1056 nat = n1at;
1057 nidx = C->get_alias_index(n1at);
1058 }
1059 }
1060 }
1061 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
1062 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
1063 switch (n->Opcode()) {
1064 case Op_PrefetchAllocation:
1065 nidx = Compile::AliasIdxRaw;
1066 nat = TypeRawPtr::BOTTOM;
1067 break;
1068 }
1069 }
1070 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
1071 switch (n->Opcode()) {
1072 case Op_ClearArray:
1073 midx = Compile::AliasIdxRaw;
1074 mat = TypeRawPtr::BOTTOM;
1075 break;
1076 }
1077 }
1078 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
1079 switch (n->Opcode()) {
1080 case Op_Return:
1081 case Op_Rethrow:
1082 case Op_Halt:
1083 case Op_TailCall:
1084 case Op_TailJump:
1085 case Op_ForwardException:
1086 nidx = Compile::AliasIdxBot;
1087 nat = TypePtr::BOTTOM;
1088 break;
1089 }
1090 }
1091 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
1092 switch (n->Opcode()) {
1093 case Op_StrComp:
1094 case Op_StrEquals:
1095 case Op_StrIndexOf:
1096 case Op_StrIndexOfChar:
1097 case Op_AryEq:
1098 case Op_VectorizedHashCode:
1099 case Op_CountPositives:
1100 case Op_MemBarVolatile:
1101 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
1102 case Op_StrInflatedCopy:
1103 case Op_StrCompressedCopy:
1104 case Op_OnSpinWait:
1105 case Op_EncodeISOArray:
1106 nidx = Compile::AliasIdxTop;
1107 nat = nullptr;
1108 break;
1109 }
1110 }
1111 if (nidx != midx) {
1112 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
1113 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
1114 n->dump();
1115 m->dump();
1116 }
1117 assert(C->subsume_loads() && C->must_alias(nat, midx),
1118 "must not lose alias info when matching");
1119 }
1120 }
1121 #endif
1122
1123 //------------------------------xform------------------------------------------
1124 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1125 // Node in new-space. Given a new-space Node, recursively walk his children.
1126 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1127 Node *Matcher::xform( Node *n, int max_stack ) {
1128 // Use one stack to keep both: child's node/state and parent's node/index
1129 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1130 mstack.push(n, Visit, nullptr, -1); // set null as parent to indicate root
1131 while (mstack.is_nonempty()) {
1132 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1133 if (C->failing()) return nullptr;
1134 n = mstack.node(); // Leave node on stack
1135 Node_State nstate = mstack.state();
1136 if (nstate == Visit) {
1137 mstack.set_state(Post_Visit);
1138 Node *oldn = n;
1139 // Old-space or new-space check
1140 if (!C->node_arena()->contains(n)) {
1141 // Old space!
1142 Node* m;
1143 if (has_new_node(n)) { // Not yet Label/Reduced
1144 m = new_node(n);
1145 } else {
1146 if (!is_dontcare(n)) { // Matcher can match this guy
1147 // Calls match special. They match alone with no children.
1148 // Their children, the incoming arguments, match normally.
1149 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1150 if (C->failing()) return nullptr;
1151 if (m == nullptr) { Matcher::soft_match_failure(); return nullptr; }
1152 if (n->is_MemBar()) {
1153 m->as_MachMemBar()->set_adr_type(n->adr_type());
1154 }
1155 } else { // Nothing the matcher cares about
1156 if (n->is_Proj() && n->in(0) != nullptr && n->in(0)->is_Multi()) { // Projections?
1157 // Convert to machine-dependent projection
1158 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1159 NOT_PRODUCT(record_new2old(m, n);)
1160 if (m->in(0) != nullptr) // m might be top
1161 collect_null_checks(m, n);
1162 } else { // Else just a regular 'ol guy
1163 m = n->clone(); // So just clone into new-space
1164 NOT_PRODUCT(record_new2old(m, n);)
1165 // Def-Use edges will be added incrementally as Uses
1166 // of this node are matched.
1167 assert(m->outcnt() == 0, "no Uses of this clone yet");
1168 }
1169 }
1170
1171 set_new_node(n, m); // Map old to new
1172 if (_old_node_note_array != nullptr) {
1173 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1174 n->_idx);
1175 C->set_node_notes_at(m->_idx, nn);
1176 }
1177 debug_only(match_alias_type(C, n, m));
1178 }
1179 n = m; // n is now a new-space node
1180 mstack.set_node(n);
1181 }
1182
1183 // New space!
1184 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1185
1186 int i;
1187 // Put precedence edges on stack first (match them last).
1188 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1189 Node *m = oldn->in(i);
1190 if (m == nullptr) break;
1191 // set -1 to call add_prec() instead of set_req() during Step1
1192 mstack.push(m, Visit, n, -1);
1193 }
1194
1195 // Handle precedence edges for interior nodes
1196 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1197 Node *m = n->in(i);
1198 if (m == nullptr || C->node_arena()->contains(m)) continue;
1199 n->rm_prec(i);
1200 // set -1 to call add_prec() instead of set_req() during Step1
1201 mstack.push(m, Visit, n, -1);
1202 }
1203
1204 // For constant debug info, I'd rather have unmatched constants.
1205 int cnt = n->req();
1206 JVMState* jvms = n->jvms();
1207 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1208
1209 // Now do only debug info. Clone constants rather than matching.
1210 // Constants are represented directly in the debug info without
1211 // the need for executable machine instructions.
1212 // Monitor boxes are also represented directly.
1213 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1214 Node *m = n->in(i); // Get input
1215 int op = m->Opcode();
1216 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1217 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1218 op == Op_ConF || op == Op_ConD || op == Op_ConL
1219 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1220 ) {
1221 m = m->clone();
1222 NOT_PRODUCT(record_new2old(m, n));
1223 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1224 mstack.push(m->in(0), Visit, m, 0);
1225 } else {
1226 mstack.push(m, Visit, n, i);
1227 }
1228 }
1229
1230 // And now walk his children, and convert his inputs to new-space.
1231 for( ; i >= 0; --i ) { // For all normal inputs do
1232 Node *m = n->in(i); // Get input
1233 if(m != nullptr)
1234 mstack.push(m, Visit, n, i);
1235 }
1236
1237 }
1238 else if (nstate == Post_Visit) {
1239 // Set xformed input
1240 Node *p = mstack.parent();
1241 if (p != nullptr) { // root doesn't have parent
1242 int i = (int)mstack.index();
1243 if (i >= 0)
1244 p->set_req(i, n); // required input
1245 else if (i == -1)
1246 p->add_prec(n); // precedence input
1247 else
1248 ShouldNotReachHere();
1249 }
1250 mstack.pop(); // remove processed node from stack
1251 }
1252 else {
1253 ShouldNotReachHere();
1254 }
1255 } // while (mstack.is_nonempty())
1256 return n; // Return new-space Node
1257 }
1258
1259 //------------------------------warp_outgoing_stk_arg------------------------
1260 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1261 // Convert outgoing argument location to a pre-biased stack offset
1262 if (reg->is_stack()) {
1263 OptoReg::Name warped = reg->reg2stack();
1264 // Adjust the stack slot offset to be the register number used
1265 // by the allocator.
1266 warped = OptoReg::add(begin_out_arg_area, warped);
1267 // Keep track of the largest numbered stack slot used for an arg.
1268 // Largest used slot per call-site indicates the amount of stack
1269 // that is killed by the call.
1270 if( warped >= out_arg_limit_per_call )
1271 out_arg_limit_per_call = OptoReg::add(warped,1);
1272 if (!RegMask::can_represent_arg(warped)) {
1273 // Bailout. For example not enough space on stack for all arguments. Happens for methods with too many arguments.
1274 C->record_method_not_compilable("unsupported calling sequence");
1275 return OptoReg::Bad;
1276 }
1277 return warped;
1278 }
1279 return OptoReg::as_OptoReg(reg);
1280 }
1281
1282
1283 //------------------------------match_sfpt-------------------------------------
1284 // Helper function to match call instructions. Calls match special.
1285 // They match alone with no children. Their children, the incoming
1286 // arguments, match normally.
1287 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1288 MachSafePointNode *msfpt = nullptr;
1289 MachCallNode *mcall = nullptr;
1290 uint cnt;
1291 // Split out case for SafePoint vs Call
1292 CallNode *call;
1293 const TypeTuple *domain;
1294 ciMethod* method = nullptr;
1295 bool is_method_handle_invoke = false; // for special kill effects
1296 if( sfpt->is_Call() ) {
1297 call = sfpt->as_Call();
1298 domain = call->tf()->domain();
1299 cnt = domain->cnt();
1300
1301 // Match just the call, nothing else
1302 MachNode *m = match_tree(call);
1303 if (C->failing()) return nullptr;
1304 if( m == nullptr ) { Matcher::soft_match_failure(); return nullptr; }
1305
1306 // Copy data from the Ideal SafePoint to the machine version
1307 mcall = m->as_MachCall();
1308
1309 mcall->set_tf( call->tf());
1310 mcall->set_entry_point( call->entry_point());
1311 mcall->set_cnt( call->cnt());
1312 mcall->set_guaranteed_safepoint(call->guaranteed_safepoint());
1313
1314 if( mcall->is_MachCallJava() ) {
1315 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1316 const CallJavaNode *call_java = call->as_CallJava();
1317 assert(call_java->validate_symbolic_info(), "inconsistent info");
1318 method = call_java->method();
1319 mcall_java->_method = method;
1320 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1321 is_method_handle_invoke = call_java->is_method_handle_invoke();
1322 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1323 mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1324 mcall_java->_arg_escape = call_java->arg_escape();
1325 if (is_method_handle_invoke) {
1326 C->set_has_method_handle_invokes(true);
1327 }
1328 if( mcall_java->is_MachCallStaticJava() )
1329 mcall_java->as_MachCallStaticJava()->_name =
1330 call_java->as_CallStaticJava()->_name;
1331 if( mcall_java->is_MachCallDynamicJava() )
1332 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1333 call_java->as_CallDynamicJava()->_vtable_index;
1334 }
1335 else if( mcall->is_MachCallRuntime() ) {
1336 MachCallRuntimeNode* mach_call_rt = mcall->as_MachCallRuntime();
1337 mach_call_rt->_name = call->as_CallRuntime()->_name;
1338 mach_call_rt->_leaf_no_fp = call->is_CallLeafNoFP();
1339 }
1340 msfpt = mcall;
1341 }
1342 // This is a non-call safepoint
1343 else {
1344 call = nullptr;
1345 domain = nullptr;
1346 MachNode *mn = match_tree(sfpt);
1347 if (C->failing()) return nullptr;
1348 msfpt = mn->as_MachSafePoint();
1349 cnt = TypeFunc::Parms;
1350 }
1351 msfpt->_has_ea_local_in_scope = sfpt->has_ea_local_in_scope();
1352
1353 // Advertise the correct memory effects (for anti-dependence computation).
1354 msfpt->set_adr_type(sfpt->adr_type());
1355
1356 // Allocate a private array of RegMasks. These RegMasks are not shared.
1357 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1358 // Empty them all.
1359 for (uint i = 0; i < cnt; i++) ::new (&(msfpt->_in_rms[i])) RegMask();
1360
1361 // Do all the pre-defined non-Empty register masks
1362 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1363 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1364
1365 // Place first outgoing argument can possibly be put.
1366 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1367 assert( is_even(begin_out_arg_area), "" );
1368 // Compute max outgoing register number per call site.
1369 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1370 // Calls to C may hammer extra stack slots above and beyond any arguments.
1371 // These are usually backing store for register arguments for varargs.
1372 if( call != nullptr && call->is_CallRuntime() )
1373 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1374
1375
1376 // Do the normal argument list (parameters) register masks
1377 int argcnt = cnt - TypeFunc::Parms;
1378 if( argcnt > 0 ) { // Skip it all if we have no args
1379 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1380 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1381 int i;
1382 for( i = 0; i < argcnt; i++ ) {
1383 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1384 }
1385 // V-call to pick proper calling convention
1386 call->calling_convention( sig_bt, parm_regs, argcnt );
1387
1388 #ifdef ASSERT
1389 // Sanity check users' calling convention. Really handy during
1390 // the initial porting effort. Fairly expensive otherwise.
1391 { for (int i = 0; i<argcnt; i++) {
1392 if( !parm_regs[i].first()->is_valid() &&
1393 !parm_regs[i].second()->is_valid() ) continue;
1394 VMReg reg1 = parm_regs[i].first();
1395 VMReg reg2 = parm_regs[i].second();
1396 for (int j = 0; j < i; j++) {
1397 if( !parm_regs[j].first()->is_valid() &&
1398 !parm_regs[j].second()->is_valid() ) continue;
1399 VMReg reg3 = parm_regs[j].first();
1400 VMReg reg4 = parm_regs[j].second();
1401 if( !reg1->is_valid() ) {
1402 assert( !reg2->is_valid(), "valid halvsies" );
1403 } else if( !reg3->is_valid() ) {
1404 assert( !reg4->is_valid(), "valid halvsies" );
1405 } else {
1406 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1407 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1408 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1409 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1410 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1411 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1412 }
1413 }
1414 }
1415 }
1416 #endif
1417
1418 // Visit each argument. Compute its outgoing register mask.
1419 // Return results now can have 2 bits returned.
1420 // Compute max over all outgoing arguments both per call-site
1421 // and over the entire method.
1422 for( i = 0; i < argcnt; i++ ) {
1423 // Address of incoming argument mask to fill in
1424 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1425 VMReg first = parm_regs[i].first();
1426 VMReg second = parm_regs[i].second();
1427 if(!first->is_valid() &&
1428 !second->is_valid()) {
1429 continue; // Avoid Halves
1430 }
1431 // Handle case where arguments are in vector registers.
1432 if(call->in(TypeFunc::Parms + i)->bottom_type()->isa_vect()) {
1433 OptoReg::Name reg_fst = OptoReg::as_OptoReg(first);
1434 OptoReg::Name reg_snd = OptoReg::as_OptoReg(second);
1435 assert (reg_fst <= reg_snd, "fst=%d snd=%d", reg_fst, reg_snd);
1436 for (OptoReg::Name r = reg_fst; r <= reg_snd; r++) {
1437 rm->Insert(r);
1438 }
1439 }
1440 // Grab first register, adjust stack slots and insert in mask.
1441 OptoReg::Name reg1 = warp_outgoing_stk_arg(first, begin_out_arg_area, out_arg_limit_per_call );
1442 if (OptoReg::is_valid(reg1))
1443 rm->Insert( reg1 );
1444 // Grab second register (if any), adjust stack slots and insert in mask.
1445 OptoReg::Name reg2 = warp_outgoing_stk_arg(second, begin_out_arg_area, out_arg_limit_per_call );
1446 if (OptoReg::is_valid(reg2))
1447 rm->Insert( reg2 );
1448 } // End of for all arguments
1449 }
1450
1451 // Compute the max stack slot killed by any call. These will not be
1452 // available for debug info, and will be used to adjust FIRST_STACK_mask
1453 // after all call sites have been visited.
1454 if( _out_arg_limit < out_arg_limit_per_call)
1455 _out_arg_limit = out_arg_limit_per_call;
1456
1457 if (mcall) {
1458 // Kill the outgoing argument area, including any non-argument holes and
1459 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1460 // Since the max-per-method covers the max-per-call-site and debug info
1461 // is excluded on the max-per-method basis, debug info cannot land in
1462 // this killed area.
1463 uint r_cnt = mcall->tf()->range()->cnt();
1464 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1465 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1466 // Bailout. We do not have space to represent all arguments.
1467 C->record_method_not_compilable("unsupported outgoing calling sequence");
1468 } else {
1469 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1470 proj->_rout.Insert(OptoReg::Name(i));
1471 }
1472 if (proj->_rout.is_NotEmpty()) {
1473 push_projection(proj);
1474 }
1475 }
1476 // Transfer the safepoint information from the call to the mcall
1477 // Move the JVMState list
1478 msfpt->set_jvms(sfpt->jvms());
1479 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1480 jvms->set_map(sfpt);
1481 }
1482
1483 // Debug inputs begin just after the last incoming parameter
1484 assert((mcall == nullptr) || (mcall->jvms() == nullptr) ||
1485 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1486
1487 // Add additional edges.
1488 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1489 // For these calls we can not add MachConstantBase in expand(), as the
1490 // ins are not complete then.
1491 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1492 if (msfpt->jvms() &&
1493 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1494 // We added an edge before jvms, so we must adapt the position of the ins.
1495 msfpt->jvms()->adapt_position(+1);
1496 }
1497 }
1498
1499 // Registers killed by the call are set in the local scheduling pass
1500 // of Global Code Motion.
1501 return msfpt;
1502 }
1503
1504 //---------------------------match_tree----------------------------------------
1505 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1506 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1507 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1508 // a Load's result RegMask for memoization in idealreg2regmask[]
1509 MachNode *Matcher::match_tree( const Node *n ) {
1510 assert( n->Opcode() != Op_Phi, "cannot match" );
1511 assert( !n->is_block_start(), "cannot match" );
1512 // Set the mark for all locally allocated State objects.
1513 // When this call returns, the _states_arena arena will be reset
1514 // freeing all State objects.
1515 ResourceMark rm( &_states_arena );
1516
1517 LabelRootDepth = 0;
1518
1519 // StoreNodes require their Memory input to match any LoadNodes
1520 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1521 #ifdef ASSERT
1522 Node* save_mem_node = _mem_node;
1523 _mem_node = n->is_Store() ? (Node*)n : nullptr;
1524 #endif
1525 // State object for root node of match tree
1526 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1527 State *s = new (&_states_arena) State;
1528 s->_kids[0] = nullptr;
1529 s->_kids[1] = nullptr;
1530 s->_leaf = (Node*)n;
1531 // Label the input tree, allocating labels from top-level arena
1532 Node* root_mem = mem;
1533 Label_Root(n, s, n->in(0), root_mem);
1534 if (C->failing()) return nullptr;
1535
1536 // The minimum cost match for the whole tree is found at the root State
1537 uint mincost = max_juint;
1538 uint cost = max_juint;
1539 uint i;
1540 for (i = 0; i < NUM_OPERANDS; i++) {
1541 if (s->valid(i) && // valid entry and
1542 s->cost(i) < cost && // low cost and
1543 s->rule(i) >= NUM_OPERANDS) {// not an operand
1544 mincost = i;
1545 cost = s->cost(i);
1546 }
1547 }
1548 if (mincost == max_juint) {
1549 #ifndef PRODUCT
1550 tty->print("No matching rule for:");
1551 s->dump();
1552 #endif
1553 Matcher::soft_match_failure();
1554 return nullptr;
1555 }
1556 // Reduce input tree based upon the state labels to machine Nodes
1557 MachNode *m = ReduceInst(s, s->rule(mincost), mem);
1558 // New-to-old mapping is done in ReduceInst, to cover complex instructions.
1559 NOT_PRODUCT(_old2new_map.map(n->_idx, m);)
1560
1561 // Add any Matcher-ignored edges
1562 uint cnt = n->req();
1563 uint start = 1;
1564 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1565 if( n->is_AddP() ) {
1566 assert( mem == (Node*)1, "" );
1567 start = AddPNode::Base+1;
1568 }
1569 for( i = start; i < cnt; i++ ) {
1570 if( !n->match_edge(i) ) {
1571 if( i < m->req() )
1572 m->ins_req( i, n->in(i) );
1573 else
1574 m->add_req( n->in(i) );
1575 }
1576 }
1577
1578 debug_only( _mem_node = save_mem_node; )
1579 return m;
1580 }
1581
1582
1583 //------------------------------match_into_reg---------------------------------
1584 // Choose to either match this Node in a register or part of the current
1585 // match tree. Return true for requiring a register and false for matching
1586 // as part of the current match tree.
1587 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1588
1589 const Type *t = m->bottom_type();
1590
1591 if (t->singleton()) {
1592 // Never force constants into registers. Allow them to match as
1593 // constants or registers. Copies of the same value will share
1594 // the same register. See find_shared_node.
1595 return false;
1596 } else { // Not a constant
1597 // Stop recursion if they have different Controls.
1598 Node* m_control = m->in(0);
1599 // Control of load's memory can post-dominates load's control.
1600 // So use it since load can't float above its memory.
1601 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : nullptr;
1602 if (control && m_control && control != m_control && control != mem_control) {
1603
1604 // Actually, we can live with the most conservative control we
1605 // find, if it post-dominates the others. This allows us to
1606 // pick up load/op/store trees where the load can float a little
1607 // above the store.
1608 Node *x = control;
1609 const uint max_scan = 6; // Arbitrary scan cutoff
1610 uint j;
1611 for (j=0; j<max_scan; j++) {
1612 if (x->is_Region()) // Bail out at merge points
1613 return true;
1614 x = x->in(0);
1615 if (x == m_control) // Does 'control' post-dominate
1616 break; // m->in(0)? If so, we can use it
1617 if (x == mem_control) // Does 'control' post-dominate
1618 break; // mem_control? If so, we can use it
1619 }
1620 if (j == max_scan) // No post-domination before scan end?
1621 return true; // Then break the match tree up
1622 }
1623 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1624 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1625 // These are commonly used in address expressions and can
1626 // efficiently fold into them on X64 in some cases.
1627 return false;
1628 }
1629 }
1630
1631 // Not forceable cloning. If shared, put it into a register.
1632 return shared;
1633 }
1634
1635
1636 //------------------------------Instruction Selection--------------------------
1637 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1638 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1639 // things the Matcher does not match (e.g., Memory), and things with different
1640 // Controls (hence forced into different blocks). We pass in the Control
1641 // selected for this entire State tree.
1642
1643 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1644 // Store and the Load must have identical Memories (as well as identical
1645 // pointers). Since the Matcher does not have anything for Memory (and
1646 // does not handle DAGs), I have to match the Memory input myself. If the
1647 // Tree root is a Store or if there are multiple Loads in the tree, I require
1648 // all Loads to have the identical memory.
1649 Node* Matcher::Label_Root(const Node* n, State* svec, Node* control, Node*& mem) {
1650 // Since Label_Root is a recursive function, its possible that we might run
1651 // out of stack space. See bugs 6272980 & 6227033 for more info.
1652 LabelRootDepth++;
1653 if (LabelRootDepth > MaxLabelRootDepth) {
1654 // Bailout. Can for example be hit with a deep chain of operations.
1655 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1656 return nullptr;
1657 }
1658 uint care = 0; // Edges matcher cares about
1659 uint cnt = n->req();
1660 uint i = 0;
1661
1662 // Examine children for memory state
1663 // Can only subsume a child into your match-tree if that child's memory state
1664 // is not modified along the path to another input.
1665 // It is unsafe even if the other inputs are separate roots.
1666 Node *input_mem = nullptr;
1667 for( i = 1; i < cnt; i++ ) {
1668 if( !n->match_edge(i) ) continue;
1669 Node *m = n->in(i); // Get ith input
1670 assert( m, "expect non-null children" );
1671 if( m->is_Load() ) {
1672 if( input_mem == nullptr ) {
1673 input_mem = m->in(MemNode::Memory);
1674 if (mem == (Node*)1) {
1675 // Save this memory to bail out if there's another memory access
1676 // to a different memory location in the same tree.
1677 mem = input_mem;
1678 }
1679 } else if( input_mem != m->in(MemNode::Memory) ) {
1680 input_mem = NodeSentinel;
1681 }
1682 }
1683 }
1684
1685 for( i = 1; i < cnt; i++ ){// For my children
1686 if( !n->match_edge(i) ) continue;
1687 Node *m = n->in(i); // Get ith input
1688 // Allocate states out of a private arena
1689 State *s = new (&_states_arena) State;
1690 svec->_kids[care++] = s;
1691 assert( care <= 2, "binary only for now" );
1692
1693 // Recursively label the State tree.
1694 s->_kids[0] = nullptr;
1695 s->_kids[1] = nullptr;
1696 s->_leaf = m;
1697
1698 // Check for leaves of the State Tree; things that cannot be a part of
1699 // the current tree. If it finds any, that value is matched as a
1700 // register operand. If not, then the normal matching is used.
1701 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1702 // Stop recursion if this is a LoadNode and there is another memory access
1703 // to a different memory location in the same tree (for example, a StoreNode
1704 // at the root of this tree or another LoadNode in one of the children).
1705 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1706 // Can NOT include the match of a subtree when its memory state
1707 // is used by any of the other subtrees
1708 (input_mem == NodeSentinel) ) {
1709 // Print when we exclude matching due to different memory states at input-loads
1710 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1711 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1712 tty->print_cr("invalid input_mem");
1713 }
1714 // Switch to a register-only opcode; this value must be in a register
1715 // and cannot be subsumed as part of a larger instruction.
1716 s->DFA( m->ideal_reg(), m );
1717
1718 } else {
1719 // If match tree has no control and we do, adopt it for entire tree
1720 if( control == nullptr && m->in(0) != nullptr && m->req() > 1 )
1721 control = m->in(0); // Pick up control
1722 // Else match as a normal part of the match tree.
1723 control = Label_Root(m, s, control, mem);
1724 if (C->failing()) return nullptr;
1725 }
1726 }
1727
1728 // Call DFA to match this node, and return
1729 svec->DFA( n->Opcode(), n );
1730
1731 #ifdef ASSERT
1732 uint x;
1733 for( x = 0; x < _LAST_MACH_OPER; x++ )
1734 if( svec->valid(x) )
1735 break;
1736
1737 if (x >= _LAST_MACH_OPER) {
1738 n->dump();
1739 svec->dump();
1740 assert( false, "bad AD file" );
1741 }
1742 #endif
1743 return control;
1744 }
1745
1746
1747 // Con nodes reduced using the same rule can share their MachNode
1748 // which reduces the number of copies of a constant in the final
1749 // program. The register allocator is free to split uses later to
1750 // split live ranges.
1751 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1752 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return nullptr;
1753
1754 // See if this Con has already been reduced using this rule.
1755 if (_shared_nodes.max() <= leaf->_idx) return nullptr;
1756 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1757 if (last != nullptr && rule == last->rule()) {
1758 // Don't expect control change for DecodeN
1759 if (leaf->is_DecodeNarrowPtr())
1760 return last;
1761 // Get the new space root.
1762 Node* xroot = new_node(C->root());
1763 if (xroot == nullptr) {
1764 // This shouldn't happen give the order of matching.
1765 return nullptr;
1766 }
1767
1768 // Shared constants need to have their control be root so they
1769 // can be scheduled properly.
1770 Node* control = last->in(0);
1771 if (control != xroot) {
1772 if (control == nullptr || control == C->root()) {
1773 last->set_req(0, xroot);
1774 } else {
1775 assert(false, "unexpected control");
1776 return nullptr;
1777 }
1778 }
1779 return last;
1780 }
1781 return nullptr;
1782 }
1783
1784
1785 //------------------------------ReduceInst-------------------------------------
1786 // Reduce a State tree (with given Control) into a tree of MachNodes.
1787 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1788 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1789 // Each MachNode has a number of complicated MachOper operands; each
1790 // MachOper also covers a further tree of Ideal Nodes.
1791
1792 // The root of the Ideal match tree is always an instruction, so we enter
1793 // the recursion here. After building the MachNode, we need to recurse
1794 // the tree checking for these cases:
1795 // (1) Child is an instruction -
1796 // Build the instruction (recursively), add it as an edge.
1797 // Build a simple operand (register) to hold the result of the instruction.
1798 // (2) Child is an interior part of an instruction -
1799 // Skip over it (do nothing)
1800 // (3) Child is the start of a operand -
1801 // Build the operand, place it inside the instruction
1802 // Call ReduceOper.
1803 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1804 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1805
1806 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1807 if (shared_node != nullptr) {
1808 return shared_node;
1809 }
1810
1811 // Build the object to represent this state & prepare for recursive calls
1812 MachNode *mach = s->MachNodeGenerator(rule);
1813 guarantee(mach != nullptr, "Missing MachNode");
1814 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1815 assert( mach->_opnds[0] != nullptr, "Missing result operand" );
1816 Node *leaf = s->_leaf;
1817 NOT_PRODUCT(record_new2old(mach, leaf);)
1818 // Check for instruction or instruction chain rule
1819 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1820 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1821 "duplicating node that's already been matched");
1822 // Instruction
1823 mach->add_req( leaf->in(0) ); // Set initial control
1824 // Reduce interior of complex instruction
1825 ReduceInst_Interior( s, rule, mem, mach, 1 );
1826 } else {
1827 // Instruction chain rules are data-dependent on their inputs
1828 mach->add_req(nullptr); // Set initial control to none
1829 ReduceInst_Chain_Rule( s, rule, mem, mach );
1830 }
1831
1832 // If a Memory was used, insert a Memory edge
1833 if( mem != (Node*)1 ) {
1834 mach->ins_req(MemNode::Memory,mem);
1835 #ifdef ASSERT
1836 // Verify adr type after matching memory operation
1837 const MachOper* oper = mach->memory_operand();
1838 if (oper != nullptr && oper != (MachOper*)-1) {
1839 // It has a unique memory operand. Find corresponding ideal mem node.
1840 Node* m = nullptr;
1841 if (leaf->is_Mem()) {
1842 m = leaf;
1843 } else {
1844 m = _mem_node;
1845 assert(m != nullptr && m->is_Mem(), "expecting memory node");
1846 }
1847 const Type* mach_at = mach->adr_type();
1848 // DecodeN node consumed by an address may have different type
1849 // than its input. Don't compare types for such case.
1850 if (m->adr_type() != mach_at &&
1851 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1852 (m->in(MemNode::Address)->is_AddP() &&
1853 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) ||
1854 (m->in(MemNode::Address)->is_AddP() &&
1855 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1856 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) {
1857 mach_at = m->adr_type();
1858 }
1859 if (m->adr_type() != mach_at) {
1860 m->dump();
1861 tty->print_cr("mach:");
1862 mach->dump(1);
1863 }
1864 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1865 }
1866 #endif
1867 }
1868
1869 // If the _leaf is an AddP, insert the base edge
1870 if (leaf->is_AddP()) {
1871 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1872 }
1873
1874 uint number_of_projections_prior = number_of_projections();
1875
1876 // Perform any 1-to-many expansions required
1877 MachNode *ex = mach->Expand(s, _projection_list, mem);
1878 if (ex != mach) {
1879 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1880 if( ex->in(1)->is_Con() )
1881 ex->in(1)->set_req(0, C->root());
1882 // Remove old node from the graph
1883 for( uint i=0; i<mach->req(); i++ ) {
1884 mach->set_req(i,nullptr);
1885 }
1886 NOT_PRODUCT(record_new2old(ex, s->_leaf);)
1887 }
1888
1889 // PhaseChaitin::fixup_spills will sometimes generate spill code
1890 // via the matcher. By the time, nodes have been wired into the CFG,
1891 // and any further nodes generated by expand rules will be left hanging
1892 // in space, and will not get emitted as output code. Catch this.
1893 // Also, catch any new register allocation constraints ("projections")
1894 // generated belatedly during spill code generation.
1895 if (_allocation_started) {
1896 guarantee(ex == mach, "no expand rules during spill generation");
1897 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1898 }
1899
1900 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1901 // Record the con for sharing
1902 _shared_nodes.map(leaf->_idx, ex);
1903 }
1904
1905 // Have mach nodes inherit GC barrier data
1906 mach->set_barrier_data(MemNode::barrier_data(leaf));
1907
1908 return ex;
1909 }
1910
1911 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1912 for (uint i = n->req(); i < n->len(); i++) {
1913 if (n->in(i) != nullptr) {
1914 mach->add_prec(n->in(i));
1915 }
1916 }
1917 }
1918
1919 void Matcher::ReduceInst_Chain_Rule(State* s, int rule, Node* &mem, MachNode* mach) {
1920 // 'op' is what I am expecting to receive
1921 int op = _leftOp[rule];
1922 // Operand type to catch childs result
1923 // This is what my child will give me.
1924 unsigned int opnd_class_instance = s->rule(op);
1925 // Choose between operand class or not.
1926 // This is what I will receive.
1927 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1928 // New rule for child. Chase operand classes to get the actual rule.
1929 unsigned int newrule = s->rule(catch_op);
1930
1931 if (newrule < NUM_OPERANDS) {
1932 // Chain from operand or operand class, may be output of shared node
1933 assert(opnd_class_instance < NUM_OPERANDS, "Bad AD file: Instruction chain rule must chain from operand");
1934 // Insert operand into array of operands for this instruction
1935 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1936
1937 ReduceOper(s, newrule, mem, mach);
1938 } else {
1939 // Chain from the result of an instruction
1940 assert(newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1941 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1942 Node *mem1 = (Node*)1;
1943 debug_only(Node *save_mem_node = _mem_node;)
1944 mach->add_req( ReduceInst(s, newrule, mem1) );
1945 debug_only(_mem_node = save_mem_node;)
1946 }
1947 return;
1948 }
1949
1950
1951 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1952 handle_precedence_edges(s->_leaf, mach);
1953
1954 if( s->_leaf->is_Load() ) {
1955 Node *mem2 = s->_leaf->in(MemNode::Memory);
1956 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1957 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1958 mem = mem2;
1959 }
1960 if( s->_leaf->in(0) != nullptr && s->_leaf->req() > 1) {
1961 if( mach->in(0) == nullptr )
1962 mach->set_req(0, s->_leaf->in(0));
1963 }
1964
1965 // Now recursively walk the state tree & add operand list.
1966 for( uint i=0; i<2; i++ ) { // binary tree
1967 State *newstate = s->_kids[i];
1968 if( newstate == nullptr ) break; // Might only have 1 child
1969 // 'op' is what I am expecting to receive
1970 int op;
1971 if( i == 0 ) {
1972 op = _leftOp[rule];
1973 } else {
1974 op = _rightOp[rule];
1975 }
1976 // Operand type to catch childs result
1977 // This is what my child will give me.
1978 int opnd_class_instance = newstate->rule(op);
1979 // Choose between operand class or not.
1980 // This is what I will receive.
1981 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1982 // New rule for child. Chase operand classes to get the actual rule.
1983 int newrule = newstate->rule(catch_op);
1984
1985 if (newrule < NUM_OPERANDS) { // Operand/operandClass or internalOp/instruction?
1986 // Operand/operandClass
1987 // Insert operand into array of operands for this instruction
1988 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1989 ReduceOper(newstate, newrule, mem, mach);
1990
1991 } else { // Child is internal operand or new instruction
1992 if (newrule < _LAST_MACH_OPER) { // internal operand or instruction?
1993 // internal operand --> call ReduceInst_Interior
1994 // Interior of complex instruction. Do nothing but recurse.
1995 num_opnds = ReduceInst_Interior(newstate, newrule, mem, mach, num_opnds);
1996 } else {
1997 // instruction --> call build operand( ) to catch result
1998 // --> ReduceInst( newrule )
1999 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
2000 Node *mem1 = (Node*)1;
2001 debug_only(Node *save_mem_node = _mem_node;)
2002 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
2003 debug_only(_mem_node = save_mem_node;)
2004 }
2005 }
2006 assert( mach->_opnds[num_opnds-1], "" );
2007 }
2008 return num_opnds;
2009 }
2010
2011 // This routine walks the interior of possible complex operands.
2012 // At each point we check our children in the match tree:
2013 // (1) No children -
2014 // We are a leaf; add _leaf field as an input to the MachNode
2015 // (2) Child is an internal operand -
2016 // Skip over it ( do nothing )
2017 // (3) Child is an instruction -
2018 // Call ReduceInst recursively and
2019 // and instruction as an input to the MachNode
2020 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
2021 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
2022 State *kid = s->_kids[0];
2023 assert( kid == nullptr || s->_leaf->in(0) == nullptr, "internal operands have no control" );
2024
2025 // Leaf? And not subsumed?
2026 if( kid == nullptr && !_swallowed[rule] ) {
2027 mach->add_req( s->_leaf ); // Add leaf pointer
2028 return; // Bail out
2029 }
2030
2031 if( s->_leaf->is_Load() ) {
2032 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
2033 mem = s->_leaf->in(MemNode::Memory);
2034 debug_only(_mem_node = s->_leaf;)
2035 }
2036
2037 handle_precedence_edges(s->_leaf, mach);
2038
2039 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
2040 if( !mach->in(0) )
2041 mach->set_req(0,s->_leaf->in(0));
2042 else {
2043 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
2044 }
2045 }
2046
2047 for (uint i = 0; kid != nullptr && i < 2; kid = s->_kids[1], i++) { // binary tree
2048 int newrule;
2049 if( i == 0) {
2050 newrule = kid->rule(_leftOp[rule]);
2051 } else {
2052 newrule = kid->rule(_rightOp[rule]);
2053 }
2054
2055 if (newrule < _LAST_MACH_OPER) { // Operand or instruction?
2056 // Internal operand; recurse but do nothing else
2057 ReduceOper(kid, newrule, mem, mach);
2058
2059 } else { // Child is a new instruction
2060 // Reduce the instruction, and add a direct pointer from this
2061 // machine instruction to the newly reduced one.
2062 Node *mem1 = (Node*)1;
2063 debug_only(Node *save_mem_node = _mem_node;)
2064 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
2065 debug_only(_mem_node = save_mem_node;)
2066 }
2067 }
2068 }
2069
2070
2071 // -------------------------------------------------------------------------
2072 // Java-Java calling convention
2073 // (what you use when Java calls Java)
2074
2075 //------------------------------find_receiver----------------------------------
2076 // For a given signature, return the OptoReg for parameter 0.
2077 OptoReg::Name Matcher::find_receiver() {
2078 VMRegPair regs;
2079 BasicType sig_bt = T_OBJECT;
2080 SharedRuntime::java_calling_convention(&sig_bt, ®s, 1);
2081 // Return argument 0 register. In the LP64 build pointers
2082 // take 2 registers, but the VM wants only the 'main' name.
2083 return OptoReg::as_OptoReg(regs.first());
2084 }
2085
2086 bool Matcher::is_vshift_con_pattern(Node* n, Node* m) {
2087 if (n != nullptr && m != nullptr) {
2088 return VectorNode::is_vector_shift(n) &&
2089 VectorNode::is_vector_shift_count(m) && m->in(1)->is_Con();
2090 }
2091 return false;
2092 }
2093
2094 bool Matcher::clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2095 // Must clone all producers of flags, or we will not match correctly.
2096 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2097 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2098 // are also there, so we may match a float-branch to int-flags and
2099 // expect the allocator to haul the flags from the int-side to the
2100 // fp-side. No can do.
2101 if (_must_clone[m->Opcode()]) {
2102 mstack.push(m, Visit);
2103 return true;
2104 }
2105 return pd_clone_node(n, m, mstack);
2106 }
2107
2108 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2109 Node *off = m->in(AddPNode::Offset);
2110 if (off->is_Con()) {
2111 address_visited.test_set(m->_idx); // Flag as address_visited
2112 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2113 // Clone X+offset as it also folds into most addressing expressions
2114 mstack.push(off, Visit);
2115 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2116 return true;
2117 }
2118 return false;
2119 }
2120
2121 // A method-klass-holder may be passed in the inline_cache_reg
2122 // and then expanded into the inline_cache_reg and a method_ptr register
2123 // defined in ad_<arch>.cpp
2124
2125 //------------------------------find_shared------------------------------------
2126 // Set bits if Node is shared or otherwise a root
2127 void Matcher::find_shared(Node* n) {
2128 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2129 MStack mstack(C->live_nodes() * 2);
2130 // Mark nodes as address_visited if they are inputs to an address expression
2131 VectorSet address_visited;
2132 mstack.push(n, Visit); // Don't need to pre-visit root node
2133 while (mstack.is_nonempty()) {
2134 n = mstack.node(); // Leave node on stack
2135 Node_State nstate = mstack.state();
2136 uint nop = n->Opcode();
2137 if (nstate == Pre_Visit) {
2138 if (address_visited.test(n->_idx)) { // Visited in address already?
2139 // Flag as visited and shared now.
2140 set_visited(n);
2141 }
2142 if (is_visited(n)) { // Visited already?
2143 // Node is shared and has no reason to clone. Flag it as shared.
2144 // This causes it to match into a register for the sharing.
2145 set_shared(n); // Flag as shared and
2146 if (n->is_DecodeNarrowPtr()) {
2147 // Oop field/array element loads must be shared but since
2148 // they are shared through a DecodeN they may appear to have
2149 // a single use so force sharing here.
2150 set_shared(n->in(1));
2151 }
2152 mstack.pop(); // remove node from stack
2153 continue;
2154 }
2155 nstate = Visit; // Not already visited; so visit now
2156 }
2157 if (nstate == Visit) {
2158 mstack.set_state(Post_Visit);
2159 set_visited(n); // Flag as visited now
2160 bool mem_op = false;
2161 int mem_addr_idx = MemNode::Address;
2162 if (find_shared_visit(mstack, n, nop, mem_op, mem_addr_idx)) {
2163 continue;
2164 }
2165 for (int i = n->req() - 1; i >= 0; --i) { // For my children
2166 Node* m = n->in(i); // Get ith input
2167 if (m == nullptr) {
2168 continue; // Ignore nulls
2169 }
2170 if (clone_node(n, m, mstack)) {
2171 continue;
2172 }
2173
2174 // Clone addressing expressions as they are "free" in memory access instructions
2175 if (mem_op && i == mem_addr_idx && m->is_AddP() &&
2176 // When there are other uses besides address expressions
2177 // put it on stack and mark as shared.
2178 !is_visited(m)) {
2179 // Some inputs for address expression are not put on stack
2180 // to avoid marking them as shared and forcing them into register
2181 // if they are used only in address expressions.
2182 // But they should be marked as shared if there are other uses
2183 // besides address expressions.
2184
2185 if (pd_clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2186 continue;
2187 }
2188 } // if( mem_op &&
2189 mstack.push(m, Pre_Visit);
2190 } // for(int i = ...)
2191 }
2192 else if (nstate == Alt_Post_Visit) {
2193 mstack.pop(); // Remove node from stack
2194 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2195 // shared and all users of the Bool need to move the Cmp in parallel.
2196 // This leaves both the Bool and the If pointing at the Cmp. To
2197 // prevent the Matcher from trying to Match the Cmp along both paths
2198 // BoolNode::match_edge always returns a zero.
2199
2200 // We reorder the Op_If in a pre-order manner, so we can visit without
2201 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2202 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2203 }
2204 else if (nstate == Post_Visit) {
2205 mstack.pop(); // Remove node from stack
2206
2207 // Now hack a few special opcodes
2208 uint opcode = n->Opcode();
2209 bool gc_handled = BarrierSet::barrier_set()->barrier_set_c2()->matcher_find_shared_post_visit(this, n, opcode);
2210 if (!gc_handled) {
2211 find_shared_post_visit(n, opcode);
2212 }
2213 }
2214 else {
2215 ShouldNotReachHere();
2216 }
2217 } // end of while (mstack.is_nonempty())
2218 }
2219
2220 bool Matcher::find_shared_visit(MStack& mstack, Node* n, uint opcode, bool& mem_op, int& mem_addr_idx) {
2221 switch(opcode) { // Handle some opcodes special
2222 case Op_Phi: // Treat Phis as shared roots
2223 case Op_Parm:
2224 case Op_Proj: // All handled specially during matching
2225 case Op_SafePointScalarObject:
2226 set_shared(n);
2227 set_dontcare(n);
2228 break;
2229 case Op_If:
2230 case Op_CountedLoopEnd:
2231 mstack.set_state(Alt_Post_Visit); // Alternative way
2232 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2233 // with matching cmp/branch in 1 instruction. The Matcher needs the
2234 // Bool and CmpX side-by-side, because it can only get at constants
2235 // that are at the leaves of Match trees, and the Bool's condition acts
2236 // as a constant here.
2237 mstack.push(n->in(1), Visit); // Clone the Bool
2238 mstack.push(n->in(0), Pre_Visit); // Visit control input
2239 return true; // while (mstack.is_nonempty())
2240 case Op_ConvI2D: // These forms efficiently match with a prior
2241 case Op_ConvI2F: // Load but not a following Store
2242 if( n->in(1)->is_Load() && // Prior load
2243 n->outcnt() == 1 && // Not already shared
2244 n->unique_out()->is_Store() ) // Following store
2245 set_shared(n); // Force it to be a root
2246 break;
2247 case Op_ReverseBytesI:
2248 case Op_ReverseBytesL:
2249 if( n->in(1)->is_Load() && // Prior load
2250 n->outcnt() == 1 ) // Not already shared
2251 set_shared(n); // Force it to be a root
2252 break;
2253 case Op_BoxLock: // Can't match until we get stack-regs in ADLC
2254 case Op_IfFalse:
2255 case Op_IfTrue:
2256 case Op_MachProj:
2257 case Op_MergeMem:
2258 case Op_Catch:
2259 case Op_CatchProj:
2260 case Op_CProj:
2261 case Op_JumpProj:
2262 case Op_JProj:
2263 case Op_NeverBranch:
2264 set_dontcare(n);
2265 break;
2266 case Op_Jump:
2267 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2268 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2269 return true; // while (mstack.is_nonempty())
2270 case Op_StrComp:
2271 case Op_StrEquals:
2272 case Op_StrIndexOf:
2273 case Op_StrIndexOfChar:
2274 case Op_AryEq:
2275 case Op_VectorizedHashCode:
2276 case Op_CountPositives:
2277 case Op_StrInflatedCopy:
2278 case Op_StrCompressedCopy:
2279 case Op_EncodeISOArray:
2280 case Op_FmaD:
2281 case Op_FmaF:
2282 case Op_FmaVD:
2283 case Op_FmaVF:
2284 case Op_MacroLogicV:
2285 case Op_VectorCmpMasked:
2286 case Op_CompressV:
2287 case Op_CompressM:
2288 case Op_ExpandV:
2289 case Op_VectorLoadMask:
2290 set_shared(n); // Force result into register (it will be anyways)
2291 break;
2292 case Op_ConP: { // Convert pointers above the centerline to NUL
2293 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2294 const TypePtr* tp = tn->type()->is_ptr();
2295 if (tp->_ptr == TypePtr::AnyNull) {
2296 tn->set_type(TypePtr::NULL_PTR);
2297 }
2298 break;
2299 }
2300 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2301 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2302 const TypePtr* tp = tn->type()->make_ptr();
2303 if (tp && tp->_ptr == TypePtr::AnyNull) {
2304 tn->set_type(TypeNarrowOop::NULL_PTR);
2305 }
2306 break;
2307 }
2308 case Op_Binary: // These are introduced in the Post_Visit state.
2309 ShouldNotReachHere();
2310 break;
2311 case Op_ClearArray:
2312 case Op_SafePoint:
2313 mem_op = true;
2314 break;
2315 default:
2316 if( n->is_Store() ) {
2317 // Do match stores, despite no ideal reg
2318 mem_op = true;
2319 break;
2320 }
2321 if( n->is_Mem() ) { // Loads and LoadStores
2322 mem_op = true;
2323 // Loads must be root of match tree due to prior load conflict
2324 if( C->subsume_loads() == false )
2325 set_shared(n);
2326 }
2327 // Fall into default case
2328 if( !n->ideal_reg() )
2329 set_dontcare(n); // Unmatchable Nodes
2330 } // end_switch
2331 return false;
2332 }
2333
2334 void Matcher::find_shared_post_visit(Node* n, uint opcode) {
2335 if (n->is_predicated_vector()) {
2336 // Restructure into binary trees for Matching.
2337 if (n->req() == 4) {
2338 n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2339 n->set_req(2, n->in(3));
2340 n->del_req(3);
2341 } else if (n->req() == 5) {
2342 n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2343 n->set_req(2, new BinaryNode(n->in(3), n->in(4)));
2344 n->del_req(4);
2345 n->del_req(3);
2346 } else if (n->req() == 6) {
2347 Node* b3 = new BinaryNode(n->in(4), n->in(5));
2348 Node* b2 = new BinaryNode(n->in(3), b3);
2349 Node* b1 = new BinaryNode(n->in(2), b2);
2350 n->set_req(2, b1);
2351 n->del_req(5);
2352 n->del_req(4);
2353 n->del_req(3);
2354 }
2355 return;
2356 }
2357
2358 switch(opcode) { // Handle some opcodes special
2359 case Op_CompareAndExchangeB:
2360 case Op_CompareAndExchangeS:
2361 case Op_CompareAndExchangeI:
2362 case Op_CompareAndExchangeL:
2363 case Op_CompareAndExchangeP:
2364 case Op_CompareAndExchangeN:
2365 case Op_WeakCompareAndSwapB:
2366 case Op_WeakCompareAndSwapS:
2367 case Op_WeakCompareAndSwapI:
2368 case Op_WeakCompareAndSwapL:
2369 case Op_WeakCompareAndSwapP:
2370 case Op_WeakCompareAndSwapN:
2371 case Op_CompareAndSwapB:
2372 case Op_CompareAndSwapS:
2373 case Op_CompareAndSwapI:
2374 case Op_CompareAndSwapL:
2375 case Op_CompareAndSwapP:
2376 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2377 Node* newval = n->in(MemNode::ValueIn);
2378 Node* oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2379 Node* pair = new BinaryNode(oldval, newval);
2380 n->set_req(MemNode::ValueIn, pair);
2381 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2382 break;
2383 }
2384 case Op_CMoveD: // Convert trinary to binary-tree
2385 case Op_CMoveF:
2386 case Op_CMoveI:
2387 case Op_CMoveL:
2388 case Op_CMoveN:
2389 case Op_CMoveP: {
2390 // Restructure into a binary tree for Matching. It's possible that
2391 // we could move this code up next to the graph reshaping for IfNodes
2392 // or vice-versa, but I do not want to debug this for Ladybird.
2393 // 10/2/2000 CNC.
2394 Node* pair1 = new BinaryNode(n->in(1), n->in(1)->in(1));
2395 n->set_req(1, pair1);
2396 Node* pair2 = new BinaryNode(n->in(2), n->in(3));
2397 n->set_req(2, pair2);
2398 n->del_req(3);
2399 break;
2400 }
2401 case Op_MacroLogicV: {
2402 Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2403 Node* pair2 = new BinaryNode(n->in(3), n->in(4));
2404 n->set_req(1, pair1);
2405 n->set_req(2, pair2);
2406 n->del_req(4);
2407 n->del_req(3);
2408 break;
2409 }
2410 case Op_StoreVectorMasked: {
2411 Node* pair = new BinaryNode(n->in(3), n->in(4));
2412 n->set_req(3, pair);
2413 n->del_req(4);
2414 break;
2415 }
2416 case Op_LoopLimit: {
2417 Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2418 n->set_req(1, pair1);
2419 n->set_req(2, n->in(3));
2420 n->del_req(3);
2421 break;
2422 }
2423 case Op_StrEquals:
2424 case Op_StrIndexOfChar: {
2425 Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2426 n->set_req(2, pair1);
2427 n->set_req(3, n->in(4));
2428 n->del_req(4);
2429 break;
2430 }
2431 case Op_StrComp:
2432 case Op_StrIndexOf:
2433 case Op_VectorizedHashCode: {
2434 Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2435 n->set_req(2, pair1);
2436 Node* pair2 = new BinaryNode(n->in(4),n->in(5));
2437 n->set_req(3, pair2);
2438 n->del_req(5);
2439 n->del_req(4);
2440 break;
2441 }
2442 case Op_EncodeISOArray:
2443 case Op_StrCompressedCopy:
2444 case Op_StrInflatedCopy: {
2445 // Restructure into a binary tree for Matching.
2446 Node* pair = new BinaryNode(n->in(3), n->in(4));
2447 n->set_req(3, pair);
2448 n->del_req(4);
2449 break;
2450 }
2451 case Op_FmaD:
2452 case Op_FmaF:
2453 case Op_FmaVD:
2454 case Op_FmaVF: {
2455 // Restructure into a binary tree for Matching.
2456 Node* pair = new BinaryNode(n->in(1), n->in(2));
2457 n->set_req(2, pair);
2458 n->set_req(1, n->in(3));
2459 n->del_req(3);
2460 break;
2461 }
2462 case Op_MulAddS2I: {
2463 Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2464 Node* pair2 = new BinaryNode(n->in(3), n->in(4));
2465 n->set_req(1, pair1);
2466 n->set_req(2, pair2);
2467 n->del_req(4);
2468 n->del_req(3);
2469 break;
2470 }
2471 case Op_VectorCmpMasked:
2472 case Op_CopySignD:
2473 case Op_SignumVF:
2474 case Op_SignumVD:
2475 case Op_SignumF:
2476 case Op_SignumD: {
2477 Node* pair = new BinaryNode(n->in(2), n->in(3));
2478 n->set_req(2, pair);
2479 n->del_req(3);
2480 break;
2481 }
2482 case Op_VectorBlend:
2483 case Op_VectorInsert: {
2484 Node* pair = new BinaryNode(n->in(1), n->in(2));
2485 n->set_req(1, pair);
2486 n->set_req(2, n->in(3));
2487 n->del_req(3);
2488 break;
2489 }
2490 case Op_LoadVectorGather:
2491 if (is_subword_type(n->bottom_type()->is_vect()->element_basic_type())) {
2492 Node* pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2493 n->set_req(MemNode::ValueIn, pair);
2494 n->del_req(MemNode::ValueIn+1);
2495 }
2496 break;
2497 case Op_LoadVectorGatherMasked:
2498 if (is_subword_type(n->bottom_type()->is_vect()->element_basic_type())) {
2499 Node* pair2 = new BinaryNode(n->in(MemNode::ValueIn + 1), n->in(MemNode::ValueIn + 2));
2500 Node* pair1 = new BinaryNode(n->in(MemNode::ValueIn), pair2);
2501 n->set_req(MemNode::ValueIn, pair1);
2502 n->del_req(MemNode::ValueIn+2);
2503 n->del_req(MemNode::ValueIn+1);
2504 break;
2505 } // fall-through
2506 case Op_StoreVectorScatter: {
2507 Node* pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2508 n->set_req(MemNode::ValueIn, pair);
2509 n->del_req(MemNode::ValueIn+1);
2510 break;
2511 }
2512 case Op_StoreVectorScatterMasked: {
2513 Node* pair = new BinaryNode(n->in(MemNode::ValueIn+1), n->in(MemNode::ValueIn+2));
2514 n->set_req(MemNode::ValueIn+1, pair);
2515 n->del_req(MemNode::ValueIn+2);
2516 pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2517 n->set_req(MemNode::ValueIn, pair);
2518 n->del_req(MemNode::ValueIn+1);
2519 break;
2520 }
2521 case Op_VectorMaskCmp: {
2522 n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2523 n->set_req(2, n->in(3));
2524 n->del_req(3);
2525 break;
2526 }
2527 case Op_PartialSubtypeCheck: {
2528 if (UseSecondarySupersTable && n->in(2)->is_Con()) {
2529 // PartialSubtypeCheck uses both constant and register operands for superclass input.
2530 n->set_req(2, new BinaryNode(n->in(2), n->in(2)));
2531 break;
2532 }
2533 break;
2534 }
2535 default:
2536 break;
2537 }
2538 }
2539
2540 #ifndef PRODUCT
2541 void Matcher::record_new2old(Node* newn, Node* old) {
2542 _new2old_map.map(newn->_idx, old);
2543 if (!_reused.test_set(old->_igv_idx)) {
2544 // Reuse the Ideal-level IGV identifier so that the node can be tracked
2545 // across matching. If there are multiple machine nodes expanded from the
2546 // same Ideal node, only one will reuse its IGV identifier.
2547 newn->_igv_idx = old->_igv_idx;
2548 }
2549 }
2550
2551 // machine-independent root to machine-dependent root
2552 void Matcher::dump_old2new_map() {
2553 _old2new_map.dump();
2554 }
2555 #endif // !PRODUCT
2556
2557 //---------------------------collect_null_checks-------------------------------
2558 // Find null checks in the ideal graph; write a machine-specific node for
2559 // it. Used by later implicit-null-check handling. Actually collects
2560 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2561 // value being tested.
2562 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2563 Node *iff = proj->in(0);
2564 if( iff->Opcode() == Op_If ) {
2565 // During matching If's have Bool & Cmp side-by-side
2566 BoolNode *b = iff->in(1)->as_Bool();
2567 Node *cmp = iff->in(2);
2568 int opc = cmp->Opcode();
2569 if (opc != Op_CmpP && opc != Op_CmpN) return;
2570
2571 const Type* ct = cmp->in(2)->bottom_type();
2572 if (ct == TypePtr::NULL_PTR ||
2573 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2574
2575 bool push_it = false;
2576 if( proj->Opcode() == Op_IfTrue ) {
2577 #ifndef PRODUCT
2578 extern uint all_null_checks_found;
2579 all_null_checks_found++;
2580 #endif
2581 if( b->_test._test == BoolTest::ne ) {
2582 push_it = true;
2583 }
2584 } else {
2585 assert( proj->Opcode() == Op_IfFalse, "" );
2586 if( b->_test._test == BoolTest::eq ) {
2587 push_it = true;
2588 }
2589 }
2590 if( push_it ) {
2591 _null_check_tests.push(proj);
2592 Node* val = cmp->in(1);
2593 #ifdef _LP64
2594 if (val->bottom_type()->isa_narrowoop() &&
2595 !Matcher::narrow_oop_use_complex_address()) {
2596 //
2597 // Look for DecodeN node which should be pinned to orig_proj.
2598 // On platforms (Sparc) which can not handle 2 adds
2599 // in addressing mode we have to keep a DecodeN node and
2600 // use it to do implicit null check in address.
2601 //
2602 // DecodeN node was pinned to non-null path (orig_proj) during
2603 // CastPP transformation in final_graph_reshaping_impl().
2604 //
2605 uint cnt = orig_proj->outcnt();
2606 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2607 Node* d = orig_proj->raw_out(i);
2608 if (d->is_DecodeN() && d->in(1) == val) {
2609 val = d;
2610 val->set_req(0, nullptr); // Unpin now.
2611 // Mark this as special case to distinguish from
2612 // a regular case: CmpP(DecodeN, null).
2613 val = (Node*)(((intptr_t)val) | 1);
2614 break;
2615 }
2616 }
2617 }
2618 #endif
2619 _null_check_tests.push(val);
2620 }
2621 }
2622 }
2623 }
2624
2625 //---------------------------validate_null_checks------------------------------
2626 // Its possible that the value being null checked is not the root of a match
2627 // tree. If so, I cannot use the value in an implicit null check.
2628 void Matcher::validate_null_checks( ) {
2629 uint cnt = _null_check_tests.size();
2630 for( uint i=0; i < cnt; i+=2 ) {
2631 Node *test = _null_check_tests[i];
2632 Node *val = _null_check_tests[i+1];
2633 bool is_decoden = ((intptr_t)val) & 1;
2634 val = (Node*)(((intptr_t)val) & ~1);
2635 if (has_new_node(val)) {
2636 Node* new_val = new_node(val);
2637 if (is_decoden) {
2638 assert(val->is_DecodeNarrowPtr() && val->in(0) == nullptr, "sanity");
2639 // Note: new_val may have a control edge if
2640 // the original ideal node DecodeN was matched before
2641 // it was unpinned in Matcher::collect_null_checks().
2642 // Unpin the mach node and mark it.
2643 new_val->set_req(0, nullptr);
2644 new_val = (Node*)(((intptr_t)new_val) | 1);
2645 }
2646 // Is a match-tree root, so replace with the matched value
2647 _null_check_tests.map(i+1, new_val);
2648 } else {
2649 // Yank from candidate list
2650 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2651 _null_check_tests.map(i,_null_check_tests[--cnt]);
2652 _null_check_tests.pop();
2653 _null_check_tests.pop();
2654 i-=2;
2655 }
2656 }
2657 }
2658
2659 bool Matcher::gen_narrow_oop_implicit_null_checks() {
2660 // Advice matcher to perform null checks on the narrow oop side.
2661 // Implicit checks are not possible on the uncompressed oop side anyway
2662 // (at least not for read accesses).
2663 // Performs significantly better (especially on Power 6).
2664 if (!os::zero_page_read_protected()) {
2665 return true;
2666 }
2667 return CompressedOops::use_implicit_null_checks() &&
2668 (narrow_oop_use_complex_address() ||
2669 CompressedOops::base() != nullptr);
2670 }
2671
2672 // Compute RegMask for an ideal register.
2673 const RegMask* Matcher::regmask_for_ideal_register(uint ideal_reg, Node* ret) {
2674 const Type* t = Type::mreg2type[ideal_reg];
2675 if (t == nullptr) {
2676 assert(ideal_reg >= Op_VecA && ideal_reg <= Op_VecZ, "not a vector: %d", ideal_reg);
2677 return nullptr; // not supported
2678 }
2679 Node* fp = ret->in(TypeFunc::FramePtr);
2680 Node* mem = ret->in(TypeFunc::Memory);
2681 const TypePtr* atp = TypePtr::BOTTOM;
2682 MemNode::MemOrd mo = MemNode::unordered;
2683
2684 Node* spill;
2685 switch (ideal_reg) {
2686 case Op_RegN: spill = new LoadNNode(nullptr, mem, fp, atp, t->is_narrowoop(), mo); break;
2687 case Op_RegI: spill = new LoadINode(nullptr, mem, fp, atp, t->is_int(), mo); break;
2688 case Op_RegP: spill = new LoadPNode(nullptr, mem, fp, atp, t->is_ptr(), mo); break;
2689 case Op_RegF: spill = new LoadFNode(nullptr, mem, fp, atp, t, mo); break;
2690 case Op_RegD: spill = new LoadDNode(nullptr, mem, fp, atp, t, mo); break;
2691 case Op_RegL: spill = new LoadLNode(nullptr, mem, fp, atp, t->is_long(), mo); break;
2692
2693 case Op_VecA: // fall-through
2694 case Op_VecS: // fall-through
2695 case Op_VecD: // fall-through
2696 case Op_VecX: // fall-through
2697 case Op_VecY: // fall-through
2698 case Op_VecZ: spill = new LoadVectorNode(nullptr, mem, fp, atp, t->is_vect()); break;
2699 case Op_RegVectMask: return Matcher::predicate_reg_mask();
2700
2701 default: ShouldNotReachHere();
2702 }
2703 MachNode* mspill = match_tree(spill);
2704 assert(mspill != nullptr, "matching failed: %d", ideal_reg);
2705 // Handle generic vector operand case
2706 if (Matcher::supports_generic_vector_operands && t->isa_vect()) {
2707 specialize_mach_node(mspill);
2708 }
2709 return &mspill->out_RegMask();
2710 }
2711
2712 // Process Mach IR right after selection phase is over.
2713 void Matcher::do_postselect_cleanup() {
2714 if (supports_generic_vector_operands) {
2715 specialize_generic_vector_operands();
2716 if (C->failing()) return;
2717 }
2718 }
2719
2720 //----------------------------------------------------------------------
2721 // Generic machine operands elision.
2722 //----------------------------------------------------------------------
2723
2724 // Compute concrete vector operand for a generic TEMP vector mach node based on its user info.
2725 void Matcher::specialize_temp_node(MachTempNode* tmp, MachNode* use, uint idx) {
2726 assert(use->in(idx) == tmp, "not a user");
2727 assert(!Matcher::is_generic_vector(use->_opnds[0]), "use not processed yet");
2728
2729 if ((uint)idx == use->two_adr()) { // DEF_TEMP case
2730 tmp->_opnds[0] = use->_opnds[0]->clone();
2731 } else {
2732 uint ideal_vreg = vector_ideal_reg(C->max_vector_size());
2733 tmp->_opnds[0] = Matcher::pd_specialize_generic_vector_operand(tmp->_opnds[0], ideal_vreg, true /*is_temp*/);
2734 }
2735 }
2736
2737 // Compute concrete vector operand for a generic DEF/USE vector operand (of mach node m at index idx).
2738 MachOper* Matcher::specialize_vector_operand(MachNode* m, uint opnd_idx) {
2739 assert(Matcher::is_generic_vector(m->_opnds[opnd_idx]), "repeated updates");
2740 Node* def = nullptr;
2741 if (opnd_idx == 0) { // DEF
2742 def = m; // use mach node itself to compute vector operand type
2743 } else {
2744 int base_idx = m->operand_index(opnd_idx);
2745 def = m->in(base_idx);
2746 if (def->is_Mach()) {
2747 if (def->is_MachTemp() && Matcher::is_generic_vector(def->as_Mach()->_opnds[0])) {
2748 specialize_temp_node(def->as_MachTemp(), m, base_idx); // MachTemp node use site
2749 } else if (is_reg2reg_move(def->as_Mach())) {
2750 def = def->in(1); // skip over generic reg-to-reg moves
2751 }
2752 }
2753 }
2754 assert(def->bottom_type()->isa_vect(), "not a vector");
2755 uint ideal_vreg = def->bottom_type()->ideal_reg();
2756 return Matcher::pd_specialize_generic_vector_operand(m->_opnds[opnd_idx], ideal_vreg, false /*is_temp*/);
2757 }
2758
2759 void Matcher::specialize_mach_node(MachNode* m) {
2760 assert(!m->is_MachTemp(), "processed along with its user");
2761 // For generic use operands pull specific register class operands from
2762 // its def instruction's output operand (def operand).
2763 for (uint i = 0; i < m->num_opnds(); i++) {
2764 if (Matcher::is_generic_vector(m->_opnds[i])) {
2765 m->_opnds[i] = specialize_vector_operand(m, i);
2766 }
2767 }
2768 }
2769
2770 // Replace generic vector operands with concrete vector operands and eliminate generic reg-to-reg moves from the graph.
2771 void Matcher::specialize_generic_vector_operands() {
2772 assert(supports_generic_vector_operands, "sanity");
2773 ResourceMark rm;
2774
2775 // Replace generic vector operands (vec/legVec) with concrete ones (vec[SDXYZ]/legVec[SDXYZ])
2776 // and remove reg-to-reg vector moves (MoveVec2Leg and MoveLeg2Vec).
2777 Unique_Node_List live_nodes;
2778 C->identify_useful_nodes(live_nodes);
2779
2780 while (live_nodes.size() > 0) {
2781 MachNode* m = live_nodes.pop()->isa_Mach();
2782 if (m != nullptr) {
2783 if (Matcher::is_reg2reg_move(m)) {
2784 // Register allocator properly handles vec <=> leg moves using register masks.
2785 int opnd_idx = m->operand_index(1);
2786 Node* def = m->in(opnd_idx);
2787 m->subsume_by(def, C);
2788 } else if (m->is_MachTemp()) {
2789 // process MachTemp nodes at use site (see Matcher::specialize_vector_operand)
2790 } else {
2791 specialize_mach_node(m);
2792 }
2793 }
2794 }
2795 }
2796
2797 uint Matcher::vector_length(const Node* n) {
2798 const TypeVect* vt = n->bottom_type()->is_vect();
2799 return vt->length();
2800 }
2801
2802 uint Matcher::vector_length(const MachNode* use, const MachOper* opnd) {
2803 int def_idx = use->operand_index(opnd);
2804 Node* def = use->in(def_idx);
2805 return def->bottom_type()->is_vect()->length();
2806 }
2807
2808 uint Matcher::vector_length_in_bytes(const Node* n) {
2809 const TypeVect* vt = n->bottom_type()->is_vect();
2810 return vt->length_in_bytes();
2811 }
2812
2813 uint Matcher::vector_length_in_bytes(const MachNode* use, const MachOper* opnd) {
2814 uint def_idx = use->operand_index(opnd);
2815 Node* def = use->in(def_idx);
2816 return def->bottom_type()->is_vect()->length_in_bytes();
2817 }
2818
2819 BasicType Matcher::vector_element_basic_type(const Node* n) {
2820 const TypeVect* vt = n->bottom_type()->is_vect();
2821 return vt->element_basic_type();
2822 }
2823
2824 BasicType Matcher::vector_element_basic_type(const MachNode* use, const MachOper* opnd) {
2825 int def_idx = use->operand_index(opnd);
2826 Node* def = use->in(def_idx);
2827 return def->bottom_type()->is_vect()->element_basic_type();
2828 }
2829
2830 bool Matcher::is_non_long_integral_vector(const Node* n) {
2831 BasicType bt = vector_element_basic_type(n);
2832 assert(bt != T_CHAR, "char is not allowed in vector");
2833 return is_subword_type(bt) || bt == T_INT;
2834 }
2835
2836 #ifdef ASSERT
2837 bool Matcher::verify_after_postselect_cleanup() {
2838 assert(!C->failing(), "sanity");
2839 if (supports_generic_vector_operands) {
2840 Unique_Node_List useful;
2841 C->identify_useful_nodes(useful);
2842 for (uint i = 0; i < useful.size(); i++) {
2843 MachNode* m = useful.at(i)->isa_Mach();
2844 if (m != nullptr) {
2845 assert(!Matcher::is_reg2reg_move(m), "no MoveVec nodes allowed");
2846 for (uint j = 0; j < m->num_opnds(); j++) {
2847 assert(!Matcher::is_generic_vector(m->_opnds[j]), "no generic vector operands allowed");
2848 }
2849 }
2850 }
2851 }
2852 return true;
2853 }
2854 #endif // ASSERT
2855
2856 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2857 // atomic instruction acting as a store_load barrier without any
2858 // intervening volatile load, and thus we don't need a barrier here.
2859 // We retain the Node to act as a compiler ordering barrier.
2860 bool Matcher::post_store_load_barrier(const Node* vmb) {
2861 Compile* C = Compile::current();
2862 assert(vmb->is_MemBar(), "");
2863 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2864 const MemBarNode* membar = vmb->as_MemBar();
2865
2866 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2867 Node* ctrl = nullptr;
2868 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2869 Node* p = membar->fast_out(i);
2870 assert(p->is_Proj(), "only projections here");
2871 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2872 !C->node_arena()->contains(p)) { // Unmatched old-space only
2873 ctrl = p;
2874 break;
2875 }
2876 }
2877 assert((ctrl != nullptr), "missing control projection");
2878
2879 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2880 Node *x = ctrl->fast_out(j);
2881 int xop = x->Opcode();
2882
2883 // We don't need current barrier if we see another or a lock
2884 // before seeing volatile load.
2885 //
2886 // Op_Fastunlock previously appeared in the Op_* list below.
2887 // With the advent of 1-0 lock operations we're no longer guaranteed
2888 // that a monitor exit operation contains a serializing instruction.
2889
2890 if (xop == Op_MemBarVolatile ||
2891 xop == Op_CompareAndExchangeB ||
2892 xop == Op_CompareAndExchangeS ||
2893 xop == Op_CompareAndExchangeI ||
2894 xop == Op_CompareAndExchangeL ||
2895 xop == Op_CompareAndExchangeP ||
2896 xop == Op_CompareAndExchangeN ||
2897 xop == Op_WeakCompareAndSwapB ||
2898 xop == Op_WeakCompareAndSwapS ||
2899 xop == Op_WeakCompareAndSwapL ||
2900 xop == Op_WeakCompareAndSwapP ||
2901 xop == Op_WeakCompareAndSwapN ||
2902 xop == Op_WeakCompareAndSwapI ||
2903 xop == Op_CompareAndSwapB ||
2904 xop == Op_CompareAndSwapS ||
2905 xop == Op_CompareAndSwapL ||
2906 xop == Op_CompareAndSwapP ||
2907 xop == Op_CompareAndSwapN ||
2908 xop == Op_CompareAndSwapI ||
2909 BarrierSet::barrier_set()->barrier_set_c2()->matcher_is_store_load_barrier(x, xop)) {
2910 return true;
2911 }
2912
2913 // Op_FastLock previously appeared in the Op_* list above.
2914 if (xop == Op_FastLock) {
2915 return true;
2916 }
2917
2918 if (x->is_MemBar()) {
2919 // We must retain this membar if there is an upcoming volatile
2920 // load, which will be followed by acquire membar.
2921 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2922 return false;
2923 } else {
2924 // For other kinds of barriers, check by pretending we
2925 // are them, and seeing if we can be removed.
2926 return post_store_load_barrier(x->as_MemBar());
2927 }
2928 }
2929
2930 // probably not necessary to check for these
2931 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2932 return false;
2933 }
2934 }
2935 return false;
2936 }
2937
2938 // Check whether node n is a branch to an uncommon trap that we could
2939 // optimize as test with very high branch costs in case of going to
2940 // the uncommon trap. The code must be able to be recompiled to use
2941 // a cheaper test.
2942 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2943 // Don't do it for natives, adapters, or runtime stubs
2944 Compile *C = Compile::current();
2945 if (!C->is_method_compilation()) return false;
2946
2947 assert(n->is_If(), "You should only call this on if nodes.");
2948 IfNode *ifn = n->as_If();
2949
2950 Node *ifFalse = nullptr;
2951 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2952 if (ifn->fast_out(i)->is_IfFalse()) {
2953 ifFalse = ifn->fast_out(i);
2954 break;
2955 }
2956 }
2957 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2958
2959 Node *reg = ifFalse;
2960 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2961 // Alternatively use visited set? Seems too expensive.
2962 while (reg != nullptr && cnt > 0) {
2963 CallNode *call = nullptr;
2964 RegionNode *nxt_reg = nullptr;
2965 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2966 Node *o = reg->fast_out(i);
2967 if (o->is_Call()) {
2968 call = o->as_Call();
2969 }
2970 if (o->is_Region()) {
2971 nxt_reg = o->as_Region();
2972 }
2973 }
2974
2975 if (call &&
2976 call->entry_point() == OptoRuntime::uncommon_trap_blob()->entry_point()) {
2977 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2978 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2979 jint tr_con = trtype->is_int()->get_con();
2980 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2981 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2982 assert((int)reason < (int)BitsPerInt, "recode bit map");
2983
2984 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2985 && action != Deoptimization::Action_none) {
2986 // This uncommon trap is sure to recompile, eventually.
2987 // When that happens, C->too_many_traps will prevent
2988 // this transformation from happening again.
2989 return true;
2990 }
2991 }
2992 }
2993
2994 reg = nxt_reg;
2995 cnt--;
2996 }
2997
2998 return false;
2999 }
3000
3001 //=============================================================================
3002 //---------------------------State---------------------------------------------
3003 State::State(void) : _rule() {
3004 #ifdef ASSERT
3005 _id = 0;
3006 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
3007 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
3008 #endif
3009 }
3010
3011 #ifdef ASSERT
3012 State::~State() {
3013 _id = 99;
3014 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
3015 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
3016 memset(_cost, -3, sizeof(_cost));
3017 memset(_rule, -3, sizeof(_rule));
3018 }
3019 #endif
3020
3021 #ifndef PRODUCT
3022 //---------------------------dump----------------------------------------------
3023 void State::dump() {
3024 tty->print("\n");
3025 dump(0);
3026 }
3027
3028 void State::dump(int depth) {
3029 for (int j = 0; j < depth; j++) {
3030 tty->print(" ");
3031 }
3032 tty->print("--N: ");
3033 _leaf->dump();
3034 uint i;
3035 for (i = 0; i < _LAST_MACH_OPER; i++) {
3036 // Check for valid entry
3037 if (valid(i)) {
3038 for (int j = 0; j < depth; j++) {
3039 tty->print(" ");
3040 }
3041 assert(cost(i) != max_juint, "cost must be a valid value");
3042 assert(rule(i) < _last_Mach_Node, "rule[i] must be valid rule");
3043 tty->print_cr("%s %d %s",
3044 ruleName[i], cost(i), ruleName[rule(i)] );
3045 }
3046 }
3047 tty->cr();
3048
3049 for (i = 0; i < 2; i++) {
3050 if (_kids[i]) {
3051 _kids[i]->dump(depth + 1);
3052 }
3053 }
3054 }
3055 #endif