1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #include "precompiled.hpp"
26 #include "gc/shared/barrierSet.hpp"
27 #include "gc/shared/c2/barrierSetC2.hpp"
28 #include "memory/allocation.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "oops/compressedOops.hpp"
31 #include "opto/ad.hpp"
32 #include "opto/addnode.hpp"
33 #include "opto/callnode.hpp"
34 #include "opto/idealGraphPrinter.hpp"
35 #include "opto/matcher.hpp"
36 #include "opto/memnode.hpp"
37 #include "opto/movenode.hpp"
38 #include "opto/opcodes.hpp"
39 #include "opto/regmask.hpp"
40 #include "opto/rootnode.hpp"
41 #include "opto/runtime.hpp"
42 #include "opto/type.hpp"
43 #include "opto/vectornode.hpp"
44 #include "runtime/os.inline.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "utilities/align.hpp"
47
48 OptoReg::Name OptoReg::c_frame_pointer;
49
50 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
51 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
52 RegMask Matcher::caller_save_regmask;
53 RegMask Matcher::caller_save_regmask_exclude_soe;
54 RegMask Matcher::mh_caller_save_regmask;
55 RegMask Matcher::mh_caller_save_regmask_exclude_soe;
56 RegMask Matcher::STACK_ONLY_mask;
57 RegMask Matcher::c_frame_ptr_mask;
58 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
59 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
60
61 //---------------------------Matcher-------------------------------------------
62 Matcher::Matcher()
63 : PhaseTransform( Phase::Ins_Select ),
64 _states_arena(Chunk::medium_size, mtCompiler),
65 _new_nodes(C->comp_arena()),
66 _visited(&_states_arena),
67 _shared(&_states_arena),
68 _dontcare(&_states_arena),
69 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
70 _swallowed(swallowed),
71 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
72 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
73 _must_clone(must_clone),
74 _shared_nodes(C->comp_arena()),
75 #ifndef PRODUCT
76 _old2new_map(C->comp_arena()),
77 _new2old_map(C->comp_arena()),
78 _reused(C->comp_arena()),
79 #endif // !PRODUCT
80 _allocation_started(false),
81 _ruleName(ruleName),
82 _register_save_policy(register_save_policy),
83 _c_reg_save_policy(c_reg_save_policy),
84 _register_save_type(register_save_type) {
85 C->set_matcher(this);
86
87 idealreg2spillmask [Op_RegI] = nullptr;
88 idealreg2spillmask [Op_RegN] = nullptr;
89 idealreg2spillmask [Op_RegL] = nullptr;
90 idealreg2spillmask [Op_RegF] = nullptr;
91 idealreg2spillmask [Op_RegD] = nullptr;
92 idealreg2spillmask [Op_RegP] = nullptr;
93 idealreg2spillmask [Op_VecA] = nullptr;
94 idealreg2spillmask [Op_VecS] = nullptr;
95 idealreg2spillmask [Op_VecD] = nullptr;
96 idealreg2spillmask [Op_VecX] = nullptr;
97 idealreg2spillmask [Op_VecY] = nullptr;
98 idealreg2spillmask [Op_VecZ] = nullptr;
99 idealreg2spillmask [Op_RegFlags] = nullptr;
100 idealreg2spillmask [Op_RegVectMask] = nullptr;
101
102 idealreg2debugmask [Op_RegI] = nullptr;
103 idealreg2debugmask [Op_RegN] = nullptr;
104 idealreg2debugmask [Op_RegL] = nullptr;
105 idealreg2debugmask [Op_RegF] = nullptr;
106 idealreg2debugmask [Op_RegD] = nullptr;
107 idealreg2debugmask [Op_RegP] = nullptr;
108 idealreg2debugmask [Op_VecA] = nullptr;
109 idealreg2debugmask [Op_VecS] = nullptr;
110 idealreg2debugmask [Op_VecD] = nullptr;
111 idealreg2debugmask [Op_VecX] = nullptr;
112 idealreg2debugmask [Op_VecY] = nullptr;
113 idealreg2debugmask [Op_VecZ] = nullptr;
114 idealreg2debugmask [Op_RegFlags] = nullptr;
115 idealreg2debugmask [Op_RegVectMask] = nullptr;
116
117 idealreg2mhdebugmask[Op_RegI] = nullptr;
118 idealreg2mhdebugmask[Op_RegN] = nullptr;
119 idealreg2mhdebugmask[Op_RegL] = nullptr;
120 idealreg2mhdebugmask[Op_RegF] = nullptr;
121 idealreg2mhdebugmask[Op_RegD] = nullptr;
122 idealreg2mhdebugmask[Op_RegP] = nullptr;
123 idealreg2mhdebugmask[Op_VecA] = nullptr;
124 idealreg2mhdebugmask[Op_VecS] = nullptr;
125 idealreg2mhdebugmask[Op_VecD] = nullptr;
126 idealreg2mhdebugmask[Op_VecX] = nullptr;
127 idealreg2mhdebugmask[Op_VecY] = nullptr;
128 idealreg2mhdebugmask[Op_VecZ] = nullptr;
129 idealreg2mhdebugmask[Op_RegFlags] = nullptr;
130 idealreg2mhdebugmask[Op_RegVectMask] = nullptr;
131
132 debug_only(_mem_node = nullptr;) // Ideal memory node consumed by mach node
133 }
134
135 //------------------------------warp_incoming_stk_arg------------------------
136 // This warps a VMReg into an OptoReg::Name
137 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
138 OptoReg::Name warped;
139 if( reg->is_stack() ) { // Stack slot argument?
140 warped = OptoReg::add(_old_SP, reg->reg2stack() );
141 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
142 if( warped >= _in_arg_limit )
143 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
144 if (!RegMask::can_represent_arg(warped)) {
145 // the compiler cannot represent this method's calling sequence
146 // Bailout. We do not have space to represent all arguments.
147 C->record_method_not_compilable("unsupported incoming calling sequence");
148 return OptoReg::Bad;
149 }
150 return warped;
151 }
152 return OptoReg::as_OptoReg(reg);
153 }
154
155 //---------------------------compute_old_SP------------------------------------
156 OptoReg::Name Compile::compute_old_SP() {
157 int fixed = fixed_slots();
158 int preserve = in_preserve_stack_slots();
159 return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots()));
160 }
161
162
163
164 #ifdef ASSERT
165 void Matcher::verify_new_nodes_only(Node* xroot) {
166 // Make sure that the new graph only references new nodes
167 ResourceMark rm;
168 Unique_Node_List worklist;
169 VectorSet visited;
170 worklist.push(xroot);
171 while (worklist.size() > 0) {
172 Node* n = worklist.pop();
173 visited.set(n->_idx);
174 assert(C->node_arena()->contains(n), "dead node");
175 for (uint j = 0; j < n->req(); j++) {
176 Node* in = n->in(j);
177 if (in != nullptr) {
178 assert(C->node_arena()->contains(in), "dead node");
179 if (!visited.test(in->_idx)) {
180 worklist.push(in);
181 }
182 }
183 }
184 }
185 }
186 #endif
187
188
189 //---------------------------match---------------------------------------------
190 void Matcher::match( ) {
191 if( MaxLabelRootDepth < 100 ) { // Too small?
192 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
193 MaxLabelRootDepth = 100;
194 }
195 // One-time initialization of some register masks.
196 init_spill_mask( C->root()->in(1) );
197 if (C->failing()) {
198 return;
199 }
200 _return_addr_mask = return_addr();
201 #ifdef _LP64
202 // Pointers take 2 slots in 64-bit land
203 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
204 #endif
205
206 // Map a Java-signature return type into return register-value
207 // machine registers for 0, 1 and 2 returned values.
208 const TypeTuple *range = C->tf()->range();
209 if( range->cnt() > TypeFunc::Parms ) { // If not a void function
210 // Get ideal-register return type
211 uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
212 // Get machine return register
213 uint sop = C->start()->Opcode();
214 OptoRegPair regs = return_value(ireg);
215
216 // And mask for same
217 _return_value_mask = RegMask(regs.first());
218 if( OptoReg::is_valid(regs.second()) )
219 _return_value_mask.Insert(regs.second());
220 }
221
222 // ---------------
223 // Frame Layout
224
225 // Need the method signature to determine the incoming argument types,
226 // because the types determine which registers the incoming arguments are
227 // in, and this affects the matched code.
228 const TypeTuple *domain = C->tf()->domain();
229 uint argcnt = domain->cnt() - TypeFunc::Parms;
230 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
231 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
232 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
233 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
234 uint i;
235 for( i = 0; i<argcnt; i++ ) {
236 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
237 }
238
239 // Pass array of ideal registers and length to USER code (from the AD file)
240 // that will convert this to an array of register numbers.
241 const StartNode *start = C->start();
242 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
243 #ifdef ASSERT
244 // Sanity check users' calling convention. Real handy while trying to
245 // get the initial port correct.
246 { for (uint i = 0; i<argcnt; i++) {
247 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
248 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
249 _parm_regs[i].set_bad();
250 continue;
251 }
252 VMReg parm_reg = vm_parm_regs[i].first();
253 assert(parm_reg->is_valid(), "invalid arg?");
254 if (parm_reg->is_reg()) {
255 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
256 assert(can_be_java_arg(opto_parm_reg) ||
257 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
258 opto_parm_reg == inline_cache_reg(),
259 "parameters in register must be preserved by runtime stubs");
260 }
261 for (uint j = 0; j < i; j++) {
262 assert(parm_reg != vm_parm_regs[j].first(),
263 "calling conv. must produce distinct regs");
264 }
265 }
266 }
267 #endif
268
269 // Do some initial frame layout.
270
271 // Compute the old incoming SP (may be called FP) as
272 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
273 _old_SP = C->compute_old_SP();
274 assert( is_even(_old_SP), "must be even" );
275
276 // Compute highest incoming stack argument as
277 // _old_SP + out_preserve_stack_slots + incoming argument size.
278 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
279 assert( is_even(_in_arg_limit), "out_preserve must be even" );
280 for( i = 0; i < argcnt; i++ ) {
281 // Permit args to have no register
282 _calling_convention_mask[i].Clear();
283 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
284 _parm_regs[i].set_bad();
285 continue;
286 }
287 // calling_convention returns stack arguments as a count of
288 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
289 // the allocators point of view, taking into account all the
290 // preserve area, locks & pad2.
291
292 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
293 if (C->failing()) {
294 return;
295 }
296 if( OptoReg::is_valid(reg1))
297 _calling_convention_mask[i].Insert(reg1);
298
299 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
300 if (C->failing()) {
301 return;
302 }
303 if( OptoReg::is_valid(reg2))
304 _calling_convention_mask[i].Insert(reg2);
305
306 // Saved biased stack-slot register number
307 _parm_regs[i].set_pair(reg2, reg1);
308 }
309
310 // Finally, make sure the incoming arguments take up an even number of
311 // words, in case the arguments or locals need to contain doubleword stack
312 // slots. The rest of the system assumes that stack slot pairs (in
313 // particular, in the spill area) which look aligned will in fact be
314 // aligned relative to the stack pointer in the target machine. Double
315 // stack slots will always be allocated aligned.
316 _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong));
317
318 // Compute highest outgoing stack argument as
319 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
320 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
321 assert( is_even(_out_arg_limit), "out_preserve must be even" );
322
323 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
324 // the compiler cannot represent this method's calling sequence
325 // Bailout. We do not have space to represent all arguments.
326 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
327 }
328
329 if (C->failing()) return; // bailed out on incoming arg failure
330
331 // ---------------
332 // Collect roots of matcher trees. Every node for which
333 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
334 // can be a valid interior of some tree.
335 find_shared( C->root() );
336 find_shared( C->top() );
337
338 C->print_method(PHASE_BEFORE_MATCHING, 1);
339
340 // Create new ideal node ConP #null even if it does exist in old space
341 // to avoid false sharing if the corresponding mach node is not used.
342 // The corresponding mach node is only used in rare cases for derived
343 // pointers.
344 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
345
346 // Swap out to old-space; emptying new-space
347 Arena* old = C->swap_old_and_new();
348
349 // Save debug and profile information for nodes in old space:
350 _old_node_note_array = C->node_note_array();
351 if (_old_node_note_array != nullptr) {
352 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
353 (C->comp_arena(), _old_node_note_array->length(),
354 0, nullptr));
355 }
356
357 // Pre-size the new_node table to avoid the need for range checks.
358 grow_new_node_array(C->unique());
359
360 // Reset node counter so MachNodes start with _idx at 0
361 int live_nodes = C->live_nodes();
362 C->set_unique(0);
363 C->reset_dead_node_list();
364
365 // Recursively match trees from old space into new space.
366 // Correct leaves of new-space Nodes; they point to old-space.
367 _visited.clear();
368 Node* const n = xform(C->top(), live_nodes);
369 if (C->failing()) return;
370 C->set_cached_top_node(n);
371 if (!C->failing()) {
372 Node* xroot = xform( C->root(), 1 );
373 if (C->failing()) return;
374 if (xroot == nullptr) {
375 Matcher::soft_match_failure(); // recursive matching process failed
376 assert(false, "instruction match failed");
377 C->record_method_not_compilable("instruction match failed");
378 } else {
379 // During matching shared constants were attached to C->root()
380 // because xroot wasn't available yet, so transfer the uses to
381 // the xroot.
382 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
383 Node* n = C->root()->fast_out(j);
384 if (C->node_arena()->contains(n)) {
385 assert(n->in(0) == C->root(), "should be control user");
386 n->set_req(0, xroot);
387 --j;
388 --jmax;
389 }
390 }
391
392 // Generate new mach node for ConP #null
393 assert(new_ideal_null != nullptr, "sanity");
394 _mach_null = match_tree(new_ideal_null);
395 // Don't set control, it will confuse GCM since there are no uses.
396 // The control will be set when this node is used first time
397 // in find_base_for_derived().
398 assert(_mach_null != nullptr || C->failure_is_artificial(), ""); // bailouts are handled below.
399
400 C->set_root(xroot->is_Root() ? xroot->as_Root() : nullptr);
401
402 #ifdef ASSERT
403 verify_new_nodes_only(xroot);
404 #endif
405 }
406 }
407 if (C->top() == nullptr || C->root() == nullptr) {
408 // New graph lost. This is due to a compilation failure we encountered earlier.
409 stringStream ss;
410 if (C->failure_reason() != nullptr) {
411 ss.print("graph lost: %s", C->failure_reason());
412 } else {
413 assert(C->failure_reason() != nullptr, "graph lost: reason unknown");
414 ss.print("graph lost: reason unknown");
415 }
416 C->record_method_not_compilable(ss.as_string() DEBUG_ONLY(COMMA true));
417 }
418 if (C->failing()) {
419 // delete old;
420 old->destruct_contents();
421 return;
422 }
423 assert( C->top(), "" );
424 assert( C->root(), "" );
425 validate_null_checks();
426
427 // Now smoke old-space
428 NOT_DEBUG( old->destruct_contents() );
429
430 // ------------------------
431 // Set up save-on-entry registers.
432 Fixup_Save_On_Entry( );
433
434 { // Cleanup mach IR after selection phase is over.
435 Compile::TracePhase tp("postselect_cleanup", &timers[_t_postselect_cleanup]);
436 do_postselect_cleanup();
437 if (C->failing()) return;
438 assert(verify_after_postselect_cleanup(), "");
439 }
440 }
441
442 //------------------------------Fixup_Save_On_Entry----------------------------
443 // The stated purpose of this routine is to take care of save-on-entry
444 // registers. However, the overall goal of the Match phase is to convert into
445 // machine-specific instructions which have RegMasks to guide allocation.
446 // So what this procedure really does is put a valid RegMask on each input
447 // to the machine-specific variations of all Return, TailCall and Halt
448 // instructions. It also adds edgs to define the save-on-entry values (and of
449 // course gives them a mask).
450
451 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
452 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
453 // Do all the pre-defined register masks
454 rms[TypeFunc::Control ] = RegMask::Empty;
455 rms[TypeFunc::I_O ] = RegMask::Empty;
456 rms[TypeFunc::Memory ] = RegMask::Empty;
457 rms[TypeFunc::ReturnAdr] = ret_adr;
458 rms[TypeFunc::FramePtr ] = fp;
459 return rms;
460 }
461
462 int Matcher::scalable_predicate_reg_slots() {
463 assert(Matcher::has_predicated_vectors() && Matcher::supports_scalable_vector(),
464 "scalable predicate vector should be supported");
465 int vector_reg_bit_size = Matcher::scalable_vector_reg_size(T_BYTE) << LogBitsPerByte;
466 // We assume each predicate register is one-eighth of the size of
467 // scalable vector register, one mask bit per vector byte.
468 int predicate_reg_bit_size = vector_reg_bit_size >> 3;
469 // Compute number of slots which is required when scalable predicate
470 // register is spilled. E.g. if scalable vector register is 640 bits,
471 // predicate register is 80 bits, which is 2.5 * slots.
472 // We will round up the slot number to power of 2, which is required
473 // by find_first_set().
474 int slots = predicate_reg_bit_size & (BitsPerInt - 1)
475 ? (predicate_reg_bit_size >> LogBitsPerInt) + 1
476 : predicate_reg_bit_size >> LogBitsPerInt;
477 return round_up_power_of_2(slots);
478 }
479
480 #define NOF_STACK_MASKS (3*13)
481
482 // Create the initial stack mask used by values spilling to the stack.
483 // Disallow any debug info in outgoing argument areas by setting the
484 // initial mask accordingly.
485 void Matcher::init_first_stack_mask() {
486
487 // Allocate storage for spill masks as masks for the appropriate load type.
488 RegMask *rms = (RegMask*)C->comp_arena()->AmallocWords(sizeof(RegMask) * NOF_STACK_MASKS);
489
490 // Initialize empty placeholder masks into the newly allocated arena
491 for (int i = 0; i < NOF_STACK_MASKS; i++) {
492 new (rms + i) RegMask();
493 }
494
495 idealreg2spillmask [Op_RegN] = &rms[0];
496 idealreg2spillmask [Op_RegI] = &rms[1];
497 idealreg2spillmask [Op_RegL] = &rms[2];
498 idealreg2spillmask [Op_RegF] = &rms[3];
499 idealreg2spillmask [Op_RegD] = &rms[4];
500 idealreg2spillmask [Op_RegP] = &rms[5];
501
502 idealreg2debugmask [Op_RegN] = &rms[6];
503 idealreg2debugmask [Op_RegI] = &rms[7];
504 idealreg2debugmask [Op_RegL] = &rms[8];
505 idealreg2debugmask [Op_RegF] = &rms[9];
506 idealreg2debugmask [Op_RegD] = &rms[10];
507 idealreg2debugmask [Op_RegP] = &rms[11];
508
509 idealreg2mhdebugmask[Op_RegN] = &rms[12];
510 idealreg2mhdebugmask[Op_RegI] = &rms[13];
511 idealreg2mhdebugmask[Op_RegL] = &rms[14];
512 idealreg2mhdebugmask[Op_RegF] = &rms[15];
513 idealreg2mhdebugmask[Op_RegD] = &rms[16];
514 idealreg2mhdebugmask[Op_RegP] = &rms[17];
515
516 idealreg2spillmask [Op_VecA] = &rms[18];
517 idealreg2spillmask [Op_VecS] = &rms[19];
518 idealreg2spillmask [Op_VecD] = &rms[20];
519 idealreg2spillmask [Op_VecX] = &rms[21];
520 idealreg2spillmask [Op_VecY] = &rms[22];
521 idealreg2spillmask [Op_VecZ] = &rms[23];
522
523 idealreg2debugmask [Op_VecA] = &rms[24];
524 idealreg2debugmask [Op_VecS] = &rms[25];
525 idealreg2debugmask [Op_VecD] = &rms[26];
526 idealreg2debugmask [Op_VecX] = &rms[27];
527 idealreg2debugmask [Op_VecY] = &rms[28];
528 idealreg2debugmask [Op_VecZ] = &rms[29];
529
530 idealreg2mhdebugmask[Op_VecA] = &rms[30];
531 idealreg2mhdebugmask[Op_VecS] = &rms[31];
532 idealreg2mhdebugmask[Op_VecD] = &rms[32];
533 idealreg2mhdebugmask[Op_VecX] = &rms[33];
534 idealreg2mhdebugmask[Op_VecY] = &rms[34];
535 idealreg2mhdebugmask[Op_VecZ] = &rms[35];
536
537 idealreg2spillmask [Op_RegVectMask] = &rms[36];
538 idealreg2debugmask [Op_RegVectMask] = &rms[37];
539 idealreg2mhdebugmask[Op_RegVectMask] = &rms[38];
540
541 OptoReg::Name i;
542
543 // At first, start with the empty mask
544 C->FIRST_STACK_mask().Clear();
545
546 // Add in the incoming argument area
547 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
548 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
549 C->FIRST_STACK_mask().Insert(i);
550 }
551 // Add in all bits past the outgoing argument area
552 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
553 "must be able to represent all call arguments in reg mask");
554 OptoReg::Name init = _out_arg_limit;
555 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
556 C->FIRST_STACK_mask().Insert(i);
557 }
558 // Finally, set the "infinite stack" bit.
559 C->FIRST_STACK_mask().set_AllStack();
560
561 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
562 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
563 // Keep spill masks aligned.
564 aligned_stack_mask.clear_to_pairs();
565 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
566 RegMask scalable_stack_mask = aligned_stack_mask;
567
568 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
569 #ifdef _LP64
570 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
571 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
572 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
573 #else
574 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
575 #endif
576 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
577 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
578 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
579 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
580 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
581 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
582 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
583 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
584
585 if (Matcher::has_predicated_vectors()) {
586 *idealreg2spillmask[Op_RegVectMask] = *idealreg2regmask[Op_RegVectMask];
587 idealreg2spillmask[Op_RegVectMask]->OR(aligned_stack_mask);
588 } else {
589 *idealreg2spillmask[Op_RegVectMask] = RegMask::Empty;
590 }
591
592 if (Matcher::vector_size_supported(T_BYTE,4)) {
593 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
594 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
595 } else {
596 *idealreg2spillmask[Op_VecS] = RegMask::Empty;
597 }
598
599 if (Matcher::vector_size_supported(T_FLOAT,2)) {
600 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
601 // RA guarantees such alignment since it is needed for Double and Long values.
602 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
603 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
604 } else {
605 *idealreg2spillmask[Op_VecD] = RegMask::Empty;
606 }
607
608 if (Matcher::vector_size_supported(T_FLOAT,4)) {
609 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
610 //
611 // RA can use input arguments stack slots for spills but until RA
612 // we don't know frame size and offset of input arg stack slots.
613 //
614 // Exclude last input arg stack slots to avoid spilling vectors there
615 // otherwise vector spills could stomp over stack slots in caller frame.
616 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
617 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
618 aligned_stack_mask.Remove(in);
619 in = OptoReg::add(in, -1);
620 }
621 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
622 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
623 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
624 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
625 } else {
626 *idealreg2spillmask[Op_VecX] = RegMask::Empty;
627 }
628
629 if (Matcher::vector_size_supported(T_FLOAT,8)) {
630 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
631 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
632 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
633 aligned_stack_mask.Remove(in);
634 in = OptoReg::add(in, -1);
635 }
636 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
637 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
638 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
639 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
640 } else {
641 *idealreg2spillmask[Op_VecY] = RegMask::Empty;
642 }
643
644 if (Matcher::vector_size_supported(T_FLOAT,16)) {
645 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
646 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
647 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
648 aligned_stack_mask.Remove(in);
649 in = OptoReg::add(in, -1);
650 }
651 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
652 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
653 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
654 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
655 } else {
656 *idealreg2spillmask[Op_VecZ] = RegMask::Empty;
657 }
658
659 if (Matcher::supports_scalable_vector()) {
660 int k = 1;
661 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
662 if (Matcher::has_predicated_vectors()) {
663 // Exclude last input arg stack slots to avoid spilling vector register there,
664 // otherwise RegVectMask spills could stomp over stack slots in caller frame.
665 for (; (in >= init_in) && (k < scalable_predicate_reg_slots()); k++) {
666 scalable_stack_mask.Remove(in);
667 in = OptoReg::add(in, -1);
668 }
669
670 // For RegVectMask
671 scalable_stack_mask.clear_to_sets(scalable_predicate_reg_slots());
672 assert(scalable_stack_mask.is_AllStack(), "should be infinite stack");
673 *idealreg2spillmask[Op_RegVectMask] = *idealreg2regmask[Op_RegVectMask];
674 idealreg2spillmask[Op_RegVectMask]->OR(scalable_stack_mask);
675 }
676
677 // Exclude last input arg stack slots to avoid spilling vector register there,
678 // otherwise vector spills could stomp over stack slots in caller frame.
679 for (; (in >= init_in) && (k < scalable_vector_reg_size(T_FLOAT)); k++) {
680 scalable_stack_mask.Remove(in);
681 in = OptoReg::add(in, -1);
682 }
683
684 // For VecA
685 scalable_stack_mask.clear_to_sets(RegMask::SlotsPerVecA);
686 assert(scalable_stack_mask.is_AllStack(), "should be infinite stack");
687 *idealreg2spillmask[Op_VecA] = *idealreg2regmask[Op_VecA];
688 idealreg2spillmask[Op_VecA]->OR(scalable_stack_mask);
689 } else {
690 *idealreg2spillmask[Op_VecA] = RegMask::Empty;
691 }
692
693 if (UseFPUForSpilling) {
694 // This mask logic assumes that the spill operations are
695 // symmetric and that the registers involved are the same size.
696 // On sparc for instance we may have to use 64 bit moves will
697 // kill 2 registers when used with F0-F31.
698 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
699 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
700 #ifdef _LP64
701 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
702 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
703 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
704 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
705 #else
706 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
707 #ifdef ARM
708 // ARM has support for moving 64bit values between a pair of
709 // integer registers and a double register
710 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
711 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
712 #endif
713 #endif
714 }
715
716 // Make up debug masks. Any spill slot plus callee-save (SOE) registers.
717 // Caller-save (SOC, AS) registers are assumed to be trashable by the various
718 // inline-cache fixup routines.
719 *idealreg2debugmask [Op_RegN] = *idealreg2spillmask[Op_RegN];
720 *idealreg2debugmask [Op_RegI] = *idealreg2spillmask[Op_RegI];
721 *idealreg2debugmask [Op_RegL] = *idealreg2spillmask[Op_RegL];
722 *idealreg2debugmask [Op_RegF] = *idealreg2spillmask[Op_RegF];
723 *idealreg2debugmask [Op_RegD] = *idealreg2spillmask[Op_RegD];
724 *idealreg2debugmask [Op_RegP] = *idealreg2spillmask[Op_RegP];
725 *idealreg2debugmask [Op_RegVectMask] = *idealreg2spillmask[Op_RegVectMask];
726
727 *idealreg2debugmask [Op_VecA] = *idealreg2spillmask[Op_VecA];
728 *idealreg2debugmask [Op_VecS] = *idealreg2spillmask[Op_VecS];
729 *idealreg2debugmask [Op_VecD] = *idealreg2spillmask[Op_VecD];
730 *idealreg2debugmask [Op_VecX] = *idealreg2spillmask[Op_VecX];
731 *idealreg2debugmask [Op_VecY] = *idealreg2spillmask[Op_VecY];
732 *idealreg2debugmask [Op_VecZ] = *idealreg2spillmask[Op_VecZ];
733
734 *idealreg2mhdebugmask[Op_RegN] = *idealreg2spillmask[Op_RegN];
735 *idealreg2mhdebugmask[Op_RegI] = *idealreg2spillmask[Op_RegI];
736 *idealreg2mhdebugmask[Op_RegL] = *idealreg2spillmask[Op_RegL];
737 *idealreg2mhdebugmask[Op_RegF] = *idealreg2spillmask[Op_RegF];
738 *idealreg2mhdebugmask[Op_RegD] = *idealreg2spillmask[Op_RegD];
739 *idealreg2mhdebugmask[Op_RegP] = *idealreg2spillmask[Op_RegP];
740 *idealreg2mhdebugmask[Op_RegVectMask] = *idealreg2spillmask[Op_RegVectMask];
741
742 *idealreg2mhdebugmask[Op_VecA] = *idealreg2spillmask[Op_VecA];
743 *idealreg2mhdebugmask[Op_VecS] = *idealreg2spillmask[Op_VecS];
744 *idealreg2mhdebugmask[Op_VecD] = *idealreg2spillmask[Op_VecD];
745 *idealreg2mhdebugmask[Op_VecX] = *idealreg2spillmask[Op_VecX];
746 *idealreg2mhdebugmask[Op_VecY] = *idealreg2spillmask[Op_VecY];
747 *idealreg2mhdebugmask[Op_VecZ] = *idealreg2spillmask[Op_VecZ];
748
749 // Prevent stub compilations from attempting to reference
750 // callee-saved (SOE) registers from debug info
751 bool exclude_soe = !Compile::current()->is_method_compilation();
752 RegMask* caller_save_mask = exclude_soe ? &caller_save_regmask_exclude_soe : &caller_save_regmask;
753 RegMask* mh_caller_save_mask = exclude_soe ? &mh_caller_save_regmask_exclude_soe : &mh_caller_save_regmask;
754
755 idealreg2debugmask[Op_RegN]->SUBTRACT(*caller_save_mask);
756 idealreg2debugmask[Op_RegI]->SUBTRACT(*caller_save_mask);
757 idealreg2debugmask[Op_RegL]->SUBTRACT(*caller_save_mask);
758 idealreg2debugmask[Op_RegF]->SUBTRACT(*caller_save_mask);
759 idealreg2debugmask[Op_RegD]->SUBTRACT(*caller_save_mask);
760 idealreg2debugmask[Op_RegP]->SUBTRACT(*caller_save_mask);
761 idealreg2debugmask[Op_RegVectMask]->SUBTRACT(*caller_save_mask);
762
763 idealreg2debugmask[Op_VecA]->SUBTRACT(*caller_save_mask);
764 idealreg2debugmask[Op_VecS]->SUBTRACT(*caller_save_mask);
765 idealreg2debugmask[Op_VecD]->SUBTRACT(*caller_save_mask);
766 idealreg2debugmask[Op_VecX]->SUBTRACT(*caller_save_mask);
767 idealreg2debugmask[Op_VecY]->SUBTRACT(*caller_save_mask);
768 idealreg2debugmask[Op_VecZ]->SUBTRACT(*caller_save_mask);
769
770 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(*mh_caller_save_mask);
771 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(*mh_caller_save_mask);
772 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(*mh_caller_save_mask);
773 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(*mh_caller_save_mask);
774 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(*mh_caller_save_mask);
775 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(*mh_caller_save_mask);
776 idealreg2mhdebugmask[Op_RegVectMask]->SUBTRACT(*mh_caller_save_mask);
777
778 idealreg2mhdebugmask[Op_VecA]->SUBTRACT(*mh_caller_save_mask);
779 idealreg2mhdebugmask[Op_VecS]->SUBTRACT(*mh_caller_save_mask);
780 idealreg2mhdebugmask[Op_VecD]->SUBTRACT(*mh_caller_save_mask);
781 idealreg2mhdebugmask[Op_VecX]->SUBTRACT(*mh_caller_save_mask);
782 idealreg2mhdebugmask[Op_VecY]->SUBTRACT(*mh_caller_save_mask);
783 idealreg2mhdebugmask[Op_VecZ]->SUBTRACT(*mh_caller_save_mask);
784 }
785
786 //---------------------------is_save_on_entry----------------------------------
787 bool Matcher::is_save_on_entry(int reg) {
788 return
789 _register_save_policy[reg] == 'E' ||
790 _register_save_policy[reg] == 'A'; // Save-on-entry register?
791 }
792
793 //---------------------------Fixup_Save_On_Entry-------------------------------
794 void Matcher::Fixup_Save_On_Entry( ) {
795 init_first_stack_mask();
796
797 Node *root = C->root(); // Short name for root
798 // Count number of save-on-entry registers.
799 uint soe_cnt = number_of_saved_registers();
800 uint i;
801
802 // Find the procedure Start Node
803 StartNode *start = C->start();
804 assert( start, "Expect a start node" );
805
806 // Input RegMask array shared by all Returns.
807 // The type for doubles and longs has a count of 2, but
808 // there is only 1 returned value
809 uint ret_edge_cnt = TypeFunc::Parms + ((C->tf()->range()->cnt() == TypeFunc::Parms) ? 0 : 1);
810 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
811 // Returns have 0 or 1 returned values depending on call signature.
812 // Return register is specified by return_value in the AD file.
813 if (ret_edge_cnt > TypeFunc::Parms)
814 ret_rms[TypeFunc::Parms+0] = _return_value_mask;
815
816 // Input RegMask array shared by all ForwardExceptions
817 uint forw_exc_edge_cnt = TypeFunc::Parms;
818 RegMask* forw_exc_rms = init_input_masks( forw_exc_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
819
820 // Input RegMask array shared by all Rethrows.
821 uint reth_edge_cnt = TypeFunc::Parms+1;
822 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
823 // Rethrow takes exception oop only, but in the argument 0 slot.
824 OptoReg::Name reg = find_receiver();
825 if (reg >= 0) {
826 reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
827 #ifdef _LP64
828 // Need two slots for ptrs in 64-bit land
829 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
830 #endif
831 }
832
833 // Input RegMask array shared by all TailCalls
834 uint tail_call_edge_cnt = TypeFunc::Parms+2;
835 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
836
837 // Input RegMask array shared by all TailJumps
838 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
839 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
840
841 // TailCalls have 2 returned values (target & moop), whose masks come
842 // from the usual MachNode/MachOper mechanism. Find a sample
843 // TailCall to extract these masks and put the correct masks into
844 // the tail_call_rms array.
845 for( i=1; i < root->req(); i++ ) {
846 MachReturnNode *m = root->in(i)->as_MachReturn();
847 if( m->ideal_Opcode() == Op_TailCall ) {
848 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
849 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
850 break;
851 }
852 }
853
854 // TailJumps have 2 returned values (target & ex_oop), whose masks come
855 // from the usual MachNode/MachOper mechanism. Find a sample
856 // TailJump to extract these masks and put the correct masks into
857 // the tail_jump_rms array.
858 for( i=1; i < root->req(); i++ ) {
859 MachReturnNode *m = root->in(i)->as_MachReturn();
860 if( m->ideal_Opcode() == Op_TailJump ) {
861 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
862 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
863 break;
864 }
865 }
866
867 // Input RegMask array shared by all Halts
868 uint halt_edge_cnt = TypeFunc::Parms;
869 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
870
871 // Capture the return input masks into each exit flavor
872 for( i=1; i < root->req(); i++ ) {
873 MachReturnNode *exit = root->in(i)->as_MachReturn();
874 switch( exit->ideal_Opcode() ) {
875 case Op_Return : exit->_in_rms = ret_rms; break;
876 case Op_Rethrow : exit->_in_rms = reth_rms; break;
877 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
878 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
879 case Op_ForwardException: exit->_in_rms = forw_exc_rms; break;
880 case Op_Halt : exit->_in_rms = halt_rms; break;
881 default : ShouldNotReachHere();
882 }
883 }
884
885 // Next unused projection number from Start.
886 int proj_cnt = C->tf()->domain()->cnt();
887
888 // Do all the save-on-entry registers. Make projections from Start for
889 // them, and give them a use at the exit points. To the allocator, they
890 // look like incoming register arguments.
891 for( i = 0; i < _last_Mach_Reg; i++ ) {
892 if( is_save_on_entry(i) ) {
893
894 // Add the save-on-entry to the mask array
895 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
896 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
897 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
898 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
899 forw_exc_rms [ forw_exc_edge_cnt] = mreg2regmask[i];
900 // Halts need the SOE registers, but only in the stack as debug info.
901 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
902 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
903
904 Node *mproj;
905
906 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
907 // into a single RegD.
908 if( (i&1) == 0 &&
909 _register_save_type[i ] == Op_RegF &&
910 _register_save_type[i+1] == Op_RegF &&
911 is_save_on_entry(i+1) ) {
912 // Add other bit for double
913 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
914 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
915 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
916 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
917 forw_exc_rms [ forw_exc_edge_cnt].Insert(OptoReg::Name(i+1));
918 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
919 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
920 proj_cnt += 2; // Skip 2 for doubles
921 }
922 else if( (i&1) == 1 && // Else check for high half of double
923 _register_save_type[i-1] == Op_RegF &&
924 _register_save_type[i ] == Op_RegF &&
925 is_save_on_entry(i-1) ) {
926 ret_rms [ ret_edge_cnt] = RegMask::Empty;
927 reth_rms [ reth_edge_cnt] = RegMask::Empty;
928 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
929 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
930 forw_exc_rms [ forw_exc_edge_cnt] = RegMask::Empty;
931 halt_rms [ halt_edge_cnt] = RegMask::Empty;
932 mproj = C->top();
933 }
934 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
935 // into a single RegL.
936 else if( (i&1) == 0 &&
937 _register_save_type[i ] == Op_RegI &&
938 _register_save_type[i+1] == Op_RegI &&
939 is_save_on_entry(i+1) ) {
940 // Add other bit for long
941 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
942 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
943 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
944 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
945 forw_exc_rms [ forw_exc_edge_cnt].Insert(OptoReg::Name(i+1));
946 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
947 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
948 proj_cnt += 2; // Skip 2 for longs
949 }
950 else if( (i&1) == 1 && // Else check for high half of long
951 _register_save_type[i-1] == Op_RegI &&
952 _register_save_type[i ] == Op_RegI &&
953 is_save_on_entry(i-1) ) {
954 ret_rms [ ret_edge_cnt] = RegMask::Empty;
955 reth_rms [ reth_edge_cnt] = RegMask::Empty;
956 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
957 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
958 forw_exc_rms [ forw_exc_edge_cnt] = RegMask::Empty;
959 halt_rms [ halt_edge_cnt] = RegMask::Empty;
960 mproj = C->top();
961 } else {
962 // Make a projection for it off the Start
963 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
964 }
965
966 ret_edge_cnt ++;
967 reth_edge_cnt ++;
968 tail_call_edge_cnt ++;
969 tail_jump_edge_cnt ++;
970 forw_exc_edge_cnt++;
971 halt_edge_cnt ++;
972
973 // Add a use of the SOE register to all exit paths
974 for (uint j=1; j < root->req(); j++) {
975 root->in(j)->add_req(mproj);
976 }
977 } // End of if a save-on-entry register
978 } // End of for all machine registers
979 }
980
981 //------------------------------init_spill_mask--------------------------------
982 void Matcher::init_spill_mask( Node *ret ) {
983 if( idealreg2regmask[Op_RegI] ) return; // One time only init
984
985 OptoReg::c_frame_pointer = c_frame_pointer();
986 c_frame_ptr_mask = c_frame_pointer();
987 #ifdef _LP64
988 // pointers are twice as big
989 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
990 #endif
991
992 // Start at OptoReg::stack0()
993 STACK_ONLY_mask.Clear();
994 OptoReg::Name init = OptoReg::stack2reg(0);
995 // STACK_ONLY_mask is all stack bits
996 OptoReg::Name i;
997 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
998 STACK_ONLY_mask.Insert(i);
999 // Also set the "infinite stack" bit.
1000 STACK_ONLY_mask.set_AllStack();
1001
1002 for (i = OptoReg::Name(0); i < OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i, 1)) {
1003 // Copy the register names over into the shared world.
1004 // SharedInfo::regName[i] = regName[i];
1005 // Handy RegMasks per machine register
1006 mreg2regmask[i].Insert(i);
1007
1008 // Set up regmasks used to exclude save-on-call (and always-save) registers from debug masks.
1009 if (_register_save_policy[i] == 'C' ||
1010 _register_save_policy[i] == 'A') {
1011 caller_save_regmask.Insert(i);
1012 mh_caller_save_regmask.Insert(i);
1013 }
1014 // Exclude save-on-entry registers from debug masks for stub compilations.
1015 if (_register_save_policy[i] == 'C' ||
1016 _register_save_policy[i] == 'A' ||
1017 _register_save_policy[i] == 'E') {
1018 caller_save_regmask_exclude_soe.Insert(i);
1019 mh_caller_save_regmask_exclude_soe.Insert(i);
1020 }
1021 }
1022
1023 // Also exclude the register we use to save the SP for MethodHandle
1024 // invokes to from the corresponding MH debug masks
1025 const RegMask sp_save_mask = method_handle_invoke_SP_save_mask();
1026 mh_caller_save_regmask.OR(sp_save_mask);
1027 mh_caller_save_regmask_exclude_soe.OR(sp_save_mask);
1028
1029 // Grab the Frame Pointer
1030 Node *fp = ret->in(TypeFunc::FramePtr);
1031 // Share frame pointer while making spill ops
1032 set_shared(fp);
1033
1034 // Get the ADLC notion of the right regmask, for each basic type.
1035 #ifdef _LP64
1036 idealreg2regmask[Op_RegN] = regmask_for_ideal_register(Op_RegN, ret);
1037 #endif
1038 idealreg2regmask[Op_RegI] = regmask_for_ideal_register(Op_RegI, ret);
1039 idealreg2regmask[Op_RegP] = regmask_for_ideal_register(Op_RegP, ret);
1040 idealreg2regmask[Op_RegF] = regmask_for_ideal_register(Op_RegF, ret);
1041 idealreg2regmask[Op_RegD] = regmask_for_ideal_register(Op_RegD, ret);
1042 idealreg2regmask[Op_RegL] = regmask_for_ideal_register(Op_RegL, ret);
1043 idealreg2regmask[Op_VecA] = regmask_for_ideal_register(Op_VecA, ret);
1044 idealreg2regmask[Op_VecS] = regmask_for_ideal_register(Op_VecS, ret);
1045 idealreg2regmask[Op_VecD] = regmask_for_ideal_register(Op_VecD, ret);
1046 idealreg2regmask[Op_VecX] = regmask_for_ideal_register(Op_VecX, ret);
1047 idealreg2regmask[Op_VecY] = regmask_for_ideal_register(Op_VecY, ret);
1048 idealreg2regmask[Op_VecZ] = regmask_for_ideal_register(Op_VecZ, ret);
1049 idealreg2regmask[Op_RegVectMask] = regmask_for_ideal_register(Op_RegVectMask, ret);
1050 }
1051
1052 #ifdef ASSERT
1053 static void match_alias_type(Compile* C, Node* n, Node* m) {
1054 if (!VerifyAliases) return; // do not go looking for trouble by default
1055 const TypePtr* nat = n->adr_type();
1056 const TypePtr* mat = m->adr_type();
1057 int nidx = C->get_alias_index(nat);
1058 int midx = C->get_alias_index(mat);
1059 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
1060 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
1061 for (uint i = 1; i < n->req(); i++) {
1062 Node* n1 = n->in(i);
1063 const TypePtr* n1at = n1->adr_type();
1064 if (n1at != nullptr) {
1065 nat = n1at;
1066 nidx = C->get_alias_index(n1at);
1067 }
1068 }
1069 }
1070 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
1071 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
1072 switch (n->Opcode()) {
1073 case Op_PrefetchAllocation:
1074 nidx = Compile::AliasIdxRaw;
1075 nat = TypeRawPtr::BOTTOM;
1076 break;
1077 }
1078 }
1079 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
1080 switch (n->Opcode()) {
1081 case Op_ClearArray:
1082 midx = Compile::AliasIdxRaw;
1083 mat = TypeRawPtr::BOTTOM;
1084 break;
1085 }
1086 }
1087 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
1088 switch (n->Opcode()) {
1089 case Op_Return:
1090 case Op_Rethrow:
1091 case Op_Halt:
1092 case Op_TailCall:
1093 case Op_TailJump:
1094 case Op_ForwardException:
1095 nidx = Compile::AliasIdxBot;
1096 nat = TypePtr::BOTTOM;
1097 break;
1098 }
1099 }
1100 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
1101 switch (n->Opcode()) {
1102 case Op_StrComp:
1103 case Op_StrEquals:
1104 case Op_StrIndexOf:
1105 case Op_StrIndexOfChar:
1106 case Op_AryEq:
1107 case Op_VectorizedHashCode:
1108 case Op_CountPositives:
1109 case Op_MemBarVolatile:
1110 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
1111 case Op_StrInflatedCopy:
1112 case Op_StrCompressedCopy:
1113 case Op_OnSpinWait:
1114 case Op_EncodeISOArray:
1115 nidx = Compile::AliasIdxTop;
1116 nat = nullptr;
1117 break;
1118 }
1119 }
1120 if (nidx != midx) {
1121 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
1122 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
1123 n->dump();
1124 m->dump();
1125 }
1126 assert(C->subsume_loads() && C->must_alias(nat, midx),
1127 "must not lose alias info when matching");
1128 }
1129 }
1130 #endif
1131
1132 //------------------------------xform------------------------------------------
1133 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1134 // Node in new-space. Given a new-space Node, recursively walk his children.
1135 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1136 Node *Matcher::xform( Node *n, int max_stack ) {
1137 // Use one stack to keep both: child's node/state and parent's node/index
1138 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1139 mstack.push(n, Visit, nullptr, -1); // set null as parent to indicate root
1140 while (mstack.is_nonempty()) {
1141 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1142 if (C->failing()) return nullptr;
1143 n = mstack.node(); // Leave node on stack
1144 Node_State nstate = mstack.state();
1145 if (nstate == Visit) {
1146 mstack.set_state(Post_Visit);
1147 Node *oldn = n;
1148 // Old-space or new-space check
1149 if (!C->node_arena()->contains(n)) {
1150 // Old space!
1151 Node* m;
1152 if (has_new_node(n)) { // Not yet Label/Reduced
1153 m = new_node(n);
1154 } else {
1155 if (!is_dontcare(n)) { // Matcher can match this guy
1156 // Calls match special. They match alone with no children.
1157 // Their children, the incoming arguments, match normally.
1158 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1159 if (C->failing()) return nullptr;
1160 if (m == nullptr) { Matcher::soft_match_failure(); return nullptr; }
1161 if (n->is_MemBar()) {
1162 m->as_MachMemBar()->set_adr_type(n->adr_type());
1163 }
1164 } else { // Nothing the matcher cares about
1165 if (n->is_Proj() && n->in(0) != nullptr && n->in(0)->is_Multi()) { // Projections?
1166 // Convert to machine-dependent projection
1167 m = n->in(0)->as_Multi()->match( n->as_Proj(), this );
1168 NOT_PRODUCT(record_new2old(m, n);)
1169 if (m->in(0) != nullptr) // m might be top
1170 collect_null_checks(m, n);
1171 } else { // Else just a regular 'ol guy
1172 m = n->clone(); // So just clone into new-space
1173 NOT_PRODUCT(record_new2old(m, n);)
1174 // Def-Use edges will be added incrementally as Uses
1175 // of this node are matched.
1176 assert(m->outcnt() == 0, "no Uses of this clone yet");
1177 }
1178 }
1179
1180 set_new_node(n, m); // Map old to new
1181 if (_old_node_note_array != nullptr) {
1182 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1183 n->_idx);
1184 C->set_node_notes_at(m->_idx, nn);
1185 }
1186 debug_only(match_alias_type(C, n, m));
1187 }
1188 n = m; // n is now a new-space node
1189 mstack.set_node(n);
1190 }
1191
1192 // New space!
1193 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1194
1195 int i;
1196 // Put precedence edges on stack first (match them last).
1197 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1198 Node *m = oldn->in(i);
1199 if (m == nullptr) break;
1200 // set -1 to call add_prec() instead of set_req() during Step1
1201 mstack.push(m, Visit, n, -1);
1202 }
1203
1204 // Handle precedence edges for interior nodes
1205 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1206 Node *m = n->in(i);
1207 if (m == nullptr || C->node_arena()->contains(m)) continue;
1208 n->rm_prec(i);
1209 // set -1 to call add_prec() instead of set_req() during Step1
1210 mstack.push(m, Visit, n, -1);
1211 }
1212
1213 // For constant debug info, I'd rather have unmatched constants.
1214 int cnt = n->req();
1215 JVMState* jvms = n->jvms();
1216 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1217
1218 // Now do only debug info. Clone constants rather than matching.
1219 // Constants are represented directly in the debug info without
1220 // the need for executable machine instructions.
1221 // Monitor boxes are also represented directly.
1222 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1223 Node *m = n->in(i); // Get input
1224 int op = m->Opcode();
1225 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1226 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1227 op == Op_ConF || op == Op_ConD || op == Op_ConL
1228 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1229 ) {
1230 m = m->clone();
1231 NOT_PRODUCT(record_new2old(m, n));
1232 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1233 mstack.push(m->in(0), Visit, m, 0);
1234 } else {
1235 mstack.push(m, Visit, n, i);
1236 }
1237 }
1238
1239 // And now walk his children, and convert his inputs to new-space.
1240 for( ; i >= 0; --i ) { // For all normal inputs do
1241 Node *m = n->in(i); // Get input
1242 if(m != nullptr)
1243 mstack.push(m, Visit, n, i);
1244 }
1245
1246 }
1247 else if (nstate == Post_Visit) {
1248 // Set xformed input
1249 Node *p = mstack.parent();
1250 if (p != nullptr) { // root doesn't have parent
1251 int i = (int)mstack.index();
1252 if (i >= 0)
1253 p->set_req(i, n); // required input
1254 else if (i == -1)
1255 p->add_prec(n); // precedence input
1256 else
1257 ShouldNotReachHere();
1258 }
1259 mstack.pop(); // remove processed node from stack
1260 }
1261 else {
1262 ShouldNotReachHere();
1263 }
1264 } // while (mstack.is_nonempty())
1265 return n; // Return new-space Node
1266 }
1267
1268 //------------------------------warp_outgoing_stk_arg------------------------
1269 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1270 // Convert outgoing argument location to a pre-biased stack offset
1271 if (reg->is_stack()) {
1272 OptoReg::Name warped = reg->reg2stack();
1273 // Adjust the stack slot offset to be the register number used
1274 // by the allocator.
1275 warped = OptoReg::add(begin_out_arg_area, warped);
1276 // Keep track of the largest numbered stack slot used for an arg.
1277 // Largest used slot per call-site indicates the amount of stack
1278 // that is killed by the call.
1279 if( warped >= out_arg_limit_per_call )
1280 out_arg_limit_per_call = OptoReg::add(warped,1);
1281 if (!RegMask::can_represent_arg(warped)) {
1282 // Bailout. For example not enough space on stack for all arguments. Happens for methods with too many arguments.
1283 C->record_method_not_compilable("unsupported calling sequence");
1284 return OptoReg::Bad;
1285 }
1286 return warped;
1287 }
1288 return OptoReg::as_OptoReg(reg);
1289 }
1290
1291
1292 //------------------------------match_sfpt-------------------------------------
1293 // Helper function to match call instructions. Calls match special.
1294 // They match alone with no children. Their children, the incoming
1295 // arguments, match normally.
1296 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1297 MachSafePointNode *msfpt = nullptr;
1298 MachCallNode *mcall = nullptr;
1299 uint cnt;
1300 // Split out case for SafePoint vs Call
1301 CallNode *call;
1302 const TypeTuple *domain;
1303 ciMethod* method = nullptr;
1304 bool is_method_handle_invoke = false; // for special kill effects
1305 if( sfpt->is_Call() ) {
1306 call = sfpt->as_Call();
1307 domain = call->tf()->domain();
1308 cnt = domain->cnt();
1309
1310 // Match just the call, nothing else
1311 MachNode *m = match_tree(call);
1312 if (C->failing()) return nullptr;
1313 if( m == nullptr ) { Matcher::soft_match_failure(); return nullptr; }
1314
1315 // Copy data from the Ideal SafePoint to the machine version
1316 mcall = m->as_MachCall();
1317
1318 mcall->set_tf( call->tf());
1319 mcall->set_entry_point( call->entry_point());
1320 mcall->set_cnt( call->cnt());
1321 mcall->set_guaranteed_safepoint(call->guaranteed_safepoint());
1322
1323 if( mcall->is_MachCallJava() ) {
1324 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1325 const CallJavaNode *call_java = call->as_CallJava();
1326 assert(call_java->validate_symbolic_info(), "inconsistent info");
1327 method = call_java->method();
1328 mcall_java->_method = method;
1329 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1330 is_method_handle_invoke = call_java->is_method_handle_invoke();
1331 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1332 mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1333 mcall_java->_arg_escape = call_java->arg_escape();
1334 if (is_method_handle_invoke) {
1335 C->set_has_method_handle_invokes(true);
1336 }
1337 if( mcall_java->is_MachCallStaticJava() )
1338 mcall_java->as_MachCallStaticJava()->_name =
1339 call_java->as_CallStaticJava()->_name;
1340 if( mcall_java->is_MachCallDynamicJava() )
1341 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1342 call_java->as_CallDynamicJava()->_vtable_index;
1343 }
1344 else if( mcall->is_MachCallRuntime() ) {
1345 MachCallRuntimeNode* mach_call_rt = mcall->as_MachCallRuntime();
1346 mach_call_rt->_name = call->as_CallRuntime()->_name;
1347 mach_call_rt->_leaf_no_fp = call->is_CallLeafNoFP();
1348 }
1349 msfpt = mcall;
1350 }
1351 // This is a non-call safepoint
1352 else {
1353 call = nullptr;
1354 domain = nullptr;
1355 MachNode *mn = match_tree(sfpt);
1356 if (C->failing()) return nullptr;
1357 msfpt = mn->as_MachSafePoint();
1358 cnt = TypeFunc::Parms;
1359 }
1360 msfpt->_has_ea_local_in_scope = sfpt->has_ea_local_in_scope();
1361
1362 // Advertise the correct memory effects (for anti-dependence computation).
1363 msfpt->set_adr_type(sfpt->adr_type());
1364
1365 // Allocate a private array of RegMasks. These RegMasks are not shared.
1366 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1367 // Empty them all.
1368 for (uint i = 0; i < cnt; i++) ::new (&(msfpt->_in_rms[i])) RegMask();
1369
1370 // Do all the pre-defined non-Empty register masks
1371 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1372 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1373
1374 // Place first outgoing argument can possibly be put.
1375 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1376 assert( is_even(begin_out_arg_area), "" );
1377 // Compute max outgoing register number per call site.
1378 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1379 // Calls to C may hammer extra stack slots above and beyond any arguments.
1380 // These are usually backing store for register arguments for varargs.
1381 if( call != nullptr && call->is_CallRuntime() )
1382 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1383
1384
1385 // Do the normal argument list (parameters) register masks
1386 int argcnt = cnt - TypeFunc::Parms;
1387 if( argcnt > 0 ) { // Skip it all if we have no args
1388 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1389 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1390 int i;
1391 for( i = 0; i < argcnt; i++ ) {
1392 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
1393 }
1394 // V-call to pick proper calling convention
1395 call->calling_convention( sig_bt, parm_regs, argcnt );
1396
1397 #ifdef ASSERT
1398 // Sanity check users' calling convention. Really handy during
1399 // the initial porting effort. Fairly expensive otherwise.
1400 { for (int i = 0; i<argcnt; i++) {
1401 if( !parm_regs[i].first()->is_valid() &&
1402 !parm_regs[i].second()->is_valid() ) continue;
1403 VMReg reg1 = parm_regs[i].first();
1404 VMReg reg2 = parm_regs[i].second();
1405 for (int j = 0; j < i; j++) {
1406 if( !parm_regs[j].first()->is_valid() &&
1407 !parm_regs[j].second()->is_valid() ) continue;
1408 VMReg reg3 = parm_regs[j].first();
1409 VMReg reg4 = parm_regs[j].second();
1410 if( !reg1->is_valid() ) {
1411 assert( !reg2->is_valid(), "valid halvsies" );
1412 } else if( !reg3->is_valid() ) {
1413 assert( !reg4->is_valid(), "valid halvsies" );
1414 } else {
1415 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1416 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1417 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1418 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1419 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1420 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1421 }
1422 }
1423 }
1424 }
1425 #endif
1426
1427 // Visit each argument. Compute its outgoing register mask.
1428 // Return results now can have 2 bits returned.
1429 // Compute max over all outgoing arguments both per call-site
1430 // and over the entire method.
1431 for( i = 0; i < argcnt; i++ ) {
1432 // Address of incoming argument mask to fill in
1433 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms];
1434 VMReg first = parm_regs[i].first();
1435 VMReg second = parm_regs[i].second();
1436 if(!first->is_valid() &&
1437 !second->is_valid()) {
1438 continue; // Avoid Halves
1439 }
1440 // Handle case where arguments are in vector registers.
1441 if(call->in(TypeFunc::Parms + i)->bottom_type()->isa_vect()) {
1442 OptoReg::Name reg_fst = OptoReg::as_OptoReg(first);
1443 OptoReg::Name reg_snd = OptoReg::as_OptoReg(second);
1444 assert (reg_fst <= reg_snd, "fst=%d snd=%d", reg_fst, reg_snd);
1445 for (OptoReg::Name r = reg_fst; r <= reg_snd; r++) {
1446 rm->Insert(r);
1447 }
1448 }
1449 // Grab first register, adjust stack slots and insert in mask.
1450 OptoReg::Name reg1 = warp_outgoing_stk_arg(first, begin_out_arg_area, out_arg_limit_per_call );
1451 if (C->failing()) {
1452 return nullptr;
1453 }
1454 if (OptoReg::is_valid(reg1))
1455 rm->Insert( reg1 );
1456 // Grab second register (if any), adjust stack slots and insert in mask.
1457 OptoReg::Name reg2 = warp_outgoing_stk_arg(second, begin_out_arg_area, out_arg_limit_per_call );
1458 if (C->failing()) {
1459 return nullptr;
1460 }
1461 if (OptoReg::is_valid(reg2))
1462 rm->Insert( reg2 );
1463 } // End of for all arguments
1464 }
1465
1466 // Compute the max stack slot killed by any call. These will not be
1467 // available for debug info, and will be used to adjust FIRST_STACK_mask
1468 // after all call sites have been visited.
1469 if( _out_arg_limit < out_arg_limit_per_call)
1470 _out_arg_limit = out_arg_limit_per_call;
1471
1472 if (mcall) {
1473 // Kill the outgoing argument area, including any non-argument holes and
1474 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1475 // Since the max-per-method covers the max-per-call-site and debug info
1476 // is excluded on the max-per-method basis, debug info cannot land in
1477 // this killed area.
1478 uint r_cnt = mcall->tf()->range()->cnt();
1479 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1480 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1481 // Bailout. We do not have space to represent all arguments.
1482 C->record_method_not_compilable("unsupported outgoing calling sequence");
1483 } else {
1484 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1485 proj->_rout.Insert(OptoReg::Name(i));
1486 }
1487 if (proj->_rout.is_NotEmpty()) {
1488 push_projection(proj);
1489 }
1490 }
1491 // Transfer the safepoint information from the call to the mcall
1492 // Move the JVMState list
1493 msfpt->set_jvms(sfpt->jvms());
1494 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1495 jvms->set_map(sfpt);
1496 }
1497
1498 // Debug inputs begin just after the last incoming parameter
1499 assert((mcall == nullptr) || (mcall->jvms() == nullptr) ||
1500 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain()->cnt()), "");
1501
1502 // Add additional edges.
1503 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1504 // For these calls we can not add MachConstantBase in expand(), as the
1505 // ins are not complete then.
1506 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1507 if (msfpt->jvms() &&
1508 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1509 // We added an edge before jvms, so we must adapt the position of the ins.
1510 msfpt->jvms()->adapt_position(+1);
1511 }
1512 }
1513
1514 // Registers killed by the call are set in the local scheduling pass
1515 // of Global Code Motion.
1516 return msfpt;
1517 }
1518
1519 //---------------------------match_tree----------------------------------------
1520 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1521 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1522 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1523 // a Load's result RegMask for memoization in idealreg2regmask[]
1524 MachNode *Matcher::match_tree( const Node *n ) {
1525 assert( n->Opcode() != Op_Phi, "cannot match" );
1526 assert( !n->is_block_start(), "cannot match" );
1527 // Set the mark for all locally allocated State objects.
1528 // When this call returns, the _states_arena arena will be reset
1529 // freeing all State objects.
1530 ResourceMark rm( &_states_arena );
1531
1532 LabelRootDepth = 0;
1533
1534 // StoreNodes require their Memory input to match any LoadNodes
1535 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1536 #ifdef ASSERT
1537 Node* save_mem_node = _mem_node;
1538 _mem_node = n->is_Store() ? (Node*)n : nullptr;
1539 #endif
1540 // State object for root node of match tree
1541 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1542 State *s = new (&_states_arena) State;
1543 s->_kids[0] = nullptr;
1544 s->_kids[1] = nullptr;
1545 s->_leaf = (Node*)n;
1546 // Label the input tree, allocating labels from top-level arena
1547 Node* root_mem = mem;
1548 Label_Root(n, s, n->in(0), root_mem);
1549 if (C->failing()) return nullptr;
1550
1551 // The minimum cost match for the whole tree is found at the root State
1552 uint mincost = max_juint;
1553 uint cost = max_juint;
1554 uint i;
1555 for (i = 0; i < NUM_OPERANDS; i++) {
1556 if (s->valid(i) && // valid entry and
1557 s->cost(i) < cost && // low cost and
1558 s->rule(i) >= NUM_OPERANDS) {// not an operand
1559 mincost = i;
1560 cost = s->cost(i);
1561 }
1562 }
1563 if (mincost == max_juint) {
1564 #ifndef PRODUCT
1565 tty->print("No matching rule for:");
1566 s->dump();
1567 #endif
1568 Matcher::soft_match_failure();
1569 return nullptr;
1570 }
1571 // Reduce input tree based upon the state labels to machine Nodes
1572 MachNode *m = ReduceInst(s, s->rule(mincost), mem);
1573 // New-to-old mapping is done in ReduceInst, to cover complex instructions.
1574 NOT_PRODUCT(_old2new_map.map(n->_idx, m);)
1575
1576 // Add any Matcher-ignored edges
1577 uint cnt = n->req();
1578 uint start = 1;
1579 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1580 if( n->is_AddP() ) {
1581 assert( mem == (Node*)1, "" );
1582 start = AddPNode::Base+1;
1583 }
1584 for( i = start; i < cnt; i++ ) {
1585 if( !n->match_edge(i) ) {
1586 if( i < m->req() )
1587 m->ins_req( i, n->in(i) );
1588 else
1589 m->add_req( n->in(i) );
1590 }
1591 }
1592
1593 debug_only( _mem_node = save_mem_node; )
1594 return m;
1595 }
1596
1597
1598 //------------------------------match_into_reg---------------------------------
1599 // Choose to either match this Node in a register or part of the current
1600 // match tree. Return true for requiring a register and false for matching
1601 // as part of the current match tree.
1602 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1603
1604 const Type *t = m->bottom_type();
1605
1606 if (t->singleton()) {
1607 // Never force constants into registers. Allow them to match as
1608 // constants or registers. Copies of the same value will share
1609 // the same register. See find_shared_node.
1610 return false;
1611 } else { // Not a constant
1612 if (!shared && Matcher::is_encode_and_store_pattern(n, m)) {
1613 // Make it possible to match "encode and store" patterns with non-shared
1614 // encode operations that are pinned to a control node (e.g. by CastPP
1615 // node removal in final graph reshaping). The matched instruction cannot
1616 // float above the encode's control node because it is pinned to the
1617 // store's control node.
1618 return false;
1619 }
1620 // Stop recursion if they have different Controls.
1621 Node* m_control = m->in(0);
1622 // Control of load's memory can post-dominates load's control.
1623 // So use it since load can't float above its memory.
1624 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : nullptr;
1625 if (control && m_control && control != m_control && control != mem_control) {
1626
1627 // Actually, we can live with the most conservative control we
1628 // find, if it post-dominates the others. This allows us to
1629 // pick up load/op/store trees where the load can float a little
1630 // above the store.
1631 Node *x = control;
1632 const uint max_scan = 6; // Arbitrary scan cutoff
1633 uint j;
1634 for (j=0; j<max_scan; j++) {
1635 if (x->is_Region()) // Bail out at merge points
1636 return true;
1637 x = x->in(0);
1638 if (x == m_control) // Does 'control' post-dominate
1639 break; // m->in(0)? If so, we can use it
1640 if (x == mem_control) // Does 'control' post-dominate
1641 break; // mem_control? If so, we can use it
1642 }
1643 if (j == max_scan) // No post-domination before scan end?
1644 return true; // Then break the match tree up
1645 }
1646 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1647 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1648 // These are commonly used in address expressions and can
1649 // efficiently fold into them on X64 in some cases.
1650 return false;
1651 }
1652 }
1653
1654 // Not forceable cloning. If shared, put it into a register.
1655 return shared;
1656 }
1657
1658
1659 //------------------------------Instruction Selection--------------------------
1660 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1661 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1662 // things the Matcher does not match (e.g., Memory), and things with different
1663 // Controls (hence forced into different blocks). We pass in the Control
1664 // selected for this entire State tree.
1665
1666 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1667 // Store and the Load must have identical Memories (as well as identical
1668 // pointers). Since the Matcher does not have anything for Memory (and
1669 // does not handle DAGs), I have to match the Memory input myself. If the
1670 // Tree root is a Store or if there are multiple Loads in the tree, I require
1671 // all Loads to have the identical memory.
1672 Node* Matcher::Label_Root(const Node* n, State* svec, Node* control, Node*& mem) {
1673 // Since Label_Root is a recursive function, its possible that we might run
1674 // out of stack space. See bugs 6272980 & 6227033 for more info.
1675 LabelRootDepth++;
1676 if (LabelRootDepth > MaxLabelRootDepth) {
1677 // Bailout. Can for example be hit with a deep chain of operations.
1678 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1679 return nullptr;
1680 }
1681 uint care = 0; // Edges matcher cares about
1682 uint cnt = n->req();
1683 uint i = 0;
1684
1685 // Examine children for memory state
1686 // Can only subsume a child into your match-tree if that child's memory state
1687 // is not modified along the path to another input.
1688 // It is unsafe even if the other inputs are separate roots.
1689 Node *input_mem = nullptr;
1690 for( i = 1; i < cnt; i++ ) {
1691 if( !n->match_edge(i) ) continue;
1692 Node *m = n->in(i); // Get ith input
1693 assert( m, "expect non-null children" );
1694 if( m->is_Load() ) {
1695 if( input_mem == nullptr ) {
1696 input_mem = m->in(MemNode::Memory);
1697 if (mem == (Node*)1) {
1698 // Save this memory to bail out if there's another memory access
1699 // to a different memory location in the same tree.
1700 mem = input_mem;
1701 }
1702 } else if( input_mem != m->in(MemNode::Memory) ) {
1703 input_mem = NodeSentinel;
1704 }
1705 }
1706 }
1707
1708 for( i = 1; i < cnt; i++ ){// For my children
1709 if( !n->match_edge(i) ) continue;
1710 Node *m = n->in(i); // Get ith input
1711 // Allocate states out of a private arena
1712 State *s = new (&_states_arena) State;
1713 svec->_kids[care++] = s;
1714 assert( care <= 2, "binary only for now" );
1715
1716 // Recursively label the State tree.
1717 s->_kids[0] = nullptr;
1718 s->_kids[1] = nullptr;
1719 s->_leaf = m;
1720
1721 // Check for leaves of the State Tree; things that cannot be a part of
1722 // the current tree. If it finds any, that value is matched as a
1723 // register operand. If not, then the normal matching is used.
1724 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1725 // Stop recursion if this is a LoadNode and there is another memory access
1726 // to a different memory location in the same tree (for example, a StoreNode
1727 // at the root of this tree or another LoadNode in one of the children).
1728 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1729 // Can NOT include the match of a subtree when its memory state
1730 // is used by any of the other subtrees
1731 (input_mem == NodeSentinel) ) {
1732 // Print when we exclude matching due to different memory states at input-loads
1733 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1734 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1735 tty->print_cr("invalid input_mem");
1736 }
1737 // Switch to a register-only opcode; this value must be in a register
1738 // and cannot be subsumed as part of a larger instruction.
1739 s->DFA( m->ideal_reg(), m );
1740
1741 } else {
1742 // If match tree has no control and we do, adopt it for entire tree
1743 if( control == nullptr && m->in(0) != nullptr && m->req() > 1 )
1744 control = m->in(0); // Pick up control
1745 // Else match as a normal part of the match tree.
1746 control = Label_Root(m, s, control, mem);
1747 if (C->failing()) return nullptr;
1748 }
1749 }
1750
1751 // Call DFA to match this node, and return
1752 svec->DFA( n->Opcode(), n );
1753
1754 #ifdef ASSERT
1755 uint x;
1756 for( x = 0; x < _LAST_MACH_OPER; x++ )
1757 if( svec->valid(x) )
1758 break;
1759
1760 if (x >= _LAST_MACH_OPER) {
1761 n->dump();
1762 svec->dump();
1763 assert( false, "bad AD file" );
1764 }
1765 #endif
1766 return control;
1767 }
1768
1769
1770 // Con nodes reduced using the same rule can share their MachNode
1771 // which reduces the number of copies of a constant in the final
1772 // program. The register allocator is free to split uses later to
1773 // split live ranges.
1774 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1775 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return nullptr;
1776
1777 // See if this Con has already been reduced using this rule.
1778 if (_shared_nodes.max() <= leaf->_idx) return nullptr;
1779 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1780 if (last != nullptr && rule == last->rule()) {
1781 // Don't expect control change for DecodeN
1782 if (leaf->is_DecodeNarrowPtr())
1783 return last;
1784 // Get the new space root.
1785 Node* xroot = new_node(C->root());
1786 if (xroot == nullptr) {
1787 // This shouldn't happen give the order of matching.
1788 return nullptr;
1789 }
1790
1791 // Shared constants need to have their control be root so they
1792 // can be scheduled properly.
1793 Node* control = last->in(0);
1794 if (control != xroot) {
1795 if (control == nullptr || control == C->root()) {
1796 last->set_req(0, xroot);
1797 } else {
1798 assert(false, "unexpected control");
1799 return nullptr;
1800 }
1801 }
1802 return last;
1803 }
1804 return nullptr;
1805 }
1806
1807
1808 //------------------------------ReduceInst-------------------------------------
1809 // Reduce a State tree (with given Control) into a tree of MachNodes.
1810 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1811 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1812 // Each MachNode has a number of complicated MachOper operands; each
1813 // MachOper also covers a further tree of Ideal Nodes.
1814
1815 // The root of the Ideal match tree is always an instruction, so we enter
1816 // the recursion here. After building the MachNode, we need to recurse
1817 // the tree checking for these cases:
1818 // (1) Child is an instruction -
1819 // Build the instruction (recursively), add it as an edge.
1820 // Build a simple operand (register) to hold the result of the instruction.
1821 // (2) Child is an interior part of an instruction -
1822 // Skip over it (do nothing)
1823 // (3) Child is the start of a operand -
1824 // Build the operand, place it inside the instruction
1825 // Call ReduceOper.
1826 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1827 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1828
1829 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1830 if (shared_node != nullptr) {
1831 return shared_node;
1832 }
1833
1834 // Build the object to represent this state & prepare for recursive calls
1835 MachNode *mach = s->MachNodeGenerator(rule);
1836 guarantee(mach != nullptr, "Missing MachNode");
1837 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1838 assert( mach->_opnds[0] != nullptr, "Missing result operand" );
1839 Node *leaf = s->_leaf;
1840 NOT_PRODUCT(record_new2old(mach, leaf);)
1841 // Check for instruction or instruction chain rule
1842 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1843 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1844 "duplicating node that's already been matched");
1845 // Instruction
1846 mach->add_req( leaf->in(0) ); // Set initial control
1847 // Reduce interior of complex instruction
1848 ReduceInst_Interior( s, rule, mem, mach, 1 );
1849 } else {
1850 // Instruction chain rules are data-dependent on their inputs
1851 mach->add_req(nullptr); // Set initial control to none
1852 ReduceInst_Chain_Rule( s, rule, mem, mach );
1853 }
1854
1855 // If a Memory was used, insert a Memory edge
1856 if( mem != (Node*)1 ) {
1857 mach->ins_req(MemNode::Memory,mem);
1858 #ifdef ASSERT
1859 // Verify adr type after matching memory operation
1860 const MachOper* oper = mach->memory_operand();
1861 if (oper != nullptr && oper != (MachOper*)-1) {
1862 // It has a unique memory operand. Find corresponding ideal mem node.
1863 Node* m = nullptr;
1864 if (leaf->is_Mem()) {
1865 m = leaf;
1866 } else {
1867 m = _mem_node;
1868 assert(m != nullptr && m->is_Mem(), "expecting memory node");
1869 }
1870 const Type* mach_at = mach->adr_type();
1871 // DecodeN node consumed by an address may have different type
1872 // than its input. Don't compare types for such case.
1873 if (m->adr_type() != mach_at &&
1874 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1875 (m->in(MemNode::Address)->is_AddP() &&
1876 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) ||
1877 (m->in(MemNode::Address)->is_AddP() &&
1878 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1879 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) {
1880 mach_at = m->adr_type();
1881 }
1882 if (m->adr_type() != mach_at) {
1883 m->dump();
1884 tty->print_cr("mach:");
1885 mach->dump(1);
1886 }
1887 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1888 }
1889 #endif
1890 }
1891
1892 // If the _leaf is an AddP, insert the base edge
1893 if (leaf->is_AddP()) {
1894 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1895 }
1896
1897 uint number_of_projections_prior = number_of_projections();
1898
1899 // Perform any 1-to-many expansions required
1900 MachNode *ex = mach->Expand(s, _projection_list, mem);
1901 if (ex != mach) {
1902 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1903 if( ex->in(1)->is_Con() )
1904 ex->in(1)->set_req(0, C->root());
1905 // Remove old node from the graph
1906 for( uint i=0; i<mach->req(); i++ ) {
1907 mach->set_req(i,nullptr);
1908 }
1909 NOT_PRODUCT(record_new2old(ex, s->_leaf);)
1910 }
1911
1912 // PhaseChaitin::fixup_spills will sometimes generate spill code
1913 // via the matcher. By the time, nodes have been wired into the CFG,
1914 // and any further nodes generated by expand rules will be left hanging
1915 // in space, and will not get emitted as output code. Catch this.
1916 // Also, catch any new register allocation constraints ("projections")
1917 // generated belatedly during spill code generation.
1918 if (_allocation_started) {
1919 guarantee(ex == mach, "no expand rules during spill generation");
1920 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1921 }
1922
1923 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1924 // Record the con for sharing
1925 _shared_nodes.map(leaf->_idx, ex);
1926 }
1927
1928 // Have mach nodes inherit GC barrier data
1929 mach->set_barrier_data(MemNode::barrier_data(leaf));
1930
1931 return ex;
1932 }
1933
1934 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1935 for (uint i = n->req(); i < n->len(); i++) {
1936 if (n->in(i) != nullptr) {
1937 mach->add_prec(n->in(i));
1938 }
1939 }
1940 }
1941
1942 void Matcher::ReduceInst_Chain_Rule(State* s, int rule, Node* &mem, MachNode* mach) {
1943 // 'op' is what I am expecting to receive
1944 int op = _leftOp[rule];
1945 // Operand type to catch childs result
1946 // This is what my child will give me.
1947 unsigned int opnd_class_instance = s->rule(op);
1948 // Choose between operand class or not.
1949 // This is what I will receive.
1950 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1951 // New rule for child. Chase operand classes to get the actual rule.
1952 unsigned int newrule = s->rule(catch_op);
1953
1954 if (newrule < NUM_OPERANDS) {
1955 // Chain from operand or operand class, may be output of shared node
1956 assert(opnd_class_instance < NUM_OPERANDS, "Bad AD file: Instruction chain rule must chain from operand");
1957 // Insert operand into array of operands for this instruction
1958 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1959
1960 ReduceOper(s, newrule, mem, mach);
1961 } else {
1962 // Chain from the result of an instruction
1963 assert(newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1964 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1965 Node *mem1 = (Node*)1;
1966 debug_only(Node *save_mem_node = _mem_node;)
1967 mach->add_req( ReduceInst(s, newrule, mem1) );
1968 debug_only(_mem_node = save_mem_node;)
1969 }
1970 return;
1971 }
1972
1973
1974 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1975 handle_precedence_edges(s->_leaf, mach);
1976
1977 if( s->_leaf->is_Load() ) {
1978 Node *mem2 = s->_leaf->in(MemNode::Memory);
1979 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1980 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1981 mem = mem2;
1982 }
1983 if( s->_leaf->in(0) != nullptr && s->_leaf->req() > 1) {
1984 if( mach->in(0) == nullptr )
1985 mach->set_req(0, s->_leaf->in(0));
1986 }
1987
1988 // Now recursively walk the state tree & add operand list.
1989 for( uint i=0; i<2; i++ ) { // binary tree
1990 State *newstate = s->_kids[i];
1991 if( newstate == nullptr ) break; // Might only have 1 child
1992 // 'op' is what I am expecting to receive
1993 int op;
1994 if( i == 0 ) {
1995 op = _leftOp[rule];
1996 } else {
1997 op = _rightOp[rule];
1998 }
1999 // Operand type to catch childs result
2000 // This is what my child will give me.
2001 int opnd_class_instance = newstate->rule(op);
2002 // Choose between operand class or not.
2003 // This is what I will receive.
2004 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
2005 // New rule for child. Chase operand classes to get the actual rule.
2006 int newrule = newstate->rule(catch_op);
2007
2008 if (newrule < NUM_OPERANDS) { // Operand/operandClass or internalOp/instruction?
2009 // Operand/operandClass
2010 // Insert operand into array of operands for this instruction
2011 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
2012 ReduceOper(newstate, newrule, mem, mach);
2013
2014 } else { // Child is internal operand or new instruction
2015 if (newrule < _LAST_MACH_OPER) { // internal operand or instruction?
2016 // internal operand --> call ReduceInst_Interior
2017 // Interior of complex instruction. Do nothing but recurse.
2018 num_opnds = ReduceInst_Interior(newstate, newrule, mem, mach, num_opnds);
2019 } else {
2020 // instruction --> call build operand( ) to catch result
2021 // --> ReduceInst( newrule )
2022 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
2023 Node *mem1 = (Node*)1;
2024 debug_only(Node *save_mem_node = _mem_node;)
2025 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
2026 debug_only(_mem_node = save_mem_node;)
2027 }
2028 }
2029 assert( mach->_opnds[num_opnds-1], "" );
2030 }
2031 return num_opnds;
2032 }
2033
2034 // This routine walks the interior of possible complex operands.
2035 // At each point we check our children in the match tree:
2036 // (1) No children -
2037 // We are a leaf; add _leaf field as an input to the MachNode
2038 // (2) Child is an internal operand -
2039 // Skip over it ( do nothing )
2040 // (3) Child is an instruction -
2041 // Call ReduceInst recursively and
2042 // and instruction as an input to the MachNode
2043 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
2044 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
2045 State *kid = s->_kids[0];
2046 assert( kid == nullptr || s->_leaf->in(0) == nullptr, "internal operands have no control" );
2047
2048 // Leaf? And not subsumed?
2049 if( kid == nullptr && !_swallowed[rule] ) {
2050 mach->add_req( s->_leaf ); // Add leaf pointer
2051 return; // Bail out
2052 }
2053
2054 if( s->_leaf->is_Load() ) {
2055 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
2056 mem = s->_leaf->in(MemNode::Memory);
2057 debug_only(_mem_node = s->_leaf;)
2058 }
2059
2060 handle_precedence_edges(s->_leaf, mach);
2061
2062 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
2063 if( !mach->in(0) )
2064 mach->set_req(0,s->_leaf->in(0));
2065 else {
2066 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
2067 }
2068 }
2069
2070 for (uint i = 0; kid != nullptr && i < 2; kid = s->_kids[1], i++) { // binary tree
2071 int newrule;
2072 if( i == 0) {
2073 newrule = kid->rule(_leftOp[rule]);
2074 } else {
2075 newrule = kid->rule(_rightOp[rule]);
2076 }
2077
2078 if (newrule < _LAST_MACH_OPER) { // Operand or instruction?
2079 // Internal operand; recurse but do nothing else
2080 ReduceOper(kid, newrule, mem, mach);
2081
2082 } else { // Child is a new instruction
2083 // Reduce the instruction, and add a direct pointer from this
2084 // machine instruction to the newly reduced one.
2085 Node *mem1 = (Node*)1;
2086 debug_only(Node *save_mem_node = _mem_node;)
2087 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
2088 debug_only(_mem_node = save_mem_node;)
2089 }
2090 }
2091 }
2092
2093
2094 // -------------------------------------------------------------------------
2095 // Java-Java calling convention
2096 // (what you use when Java calls Java)
2097
2098 //------------------------------find_receiver----------------------------------
2099 // For a given signature, return the OptoReg for parameter 0.
2100 OptoReg::Name Matcher::find_receiver() {
2101 VMRegPair regs;
2102 BasicType sig_bt = T_OBJECT;
2103 SharedRuntime::java_calling_convention(&sig_bt, ®s, 1);
2104 // Return argument 0 register. In the LP64 build pointers
2105 // take 2 registers, but the VM wants only the 'main' name.
2106 return OptoReg::as_OptoReg(regs.first());
2107 }
2108
2109 bool Matcher::is_vshift_con_pattern(Node* n, Node* m) {
2110 if (n != nullptr && m != nullptr) {
2111 return VectorNode::is_vector_shift(n) &&
2112 VectorNode::is_vector_shift_count(m) && m->in(1)->is_Con();
2113 }
2114 return false;
2115 }
2116
2117 bool Matcher::clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2118 // Must clone all producers of flags, or we will not match correctly.
2119 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2120 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2121 // are also there, so we may match a float-branch to int-flags and
2122 // expect the allocator to haul the flags from the int-side to the
2123 // fp-side. No can do.
2124 if (_must_clone[m->Opcode()]) {
2125 mstack.push(m, Visit);
2126 return true;
2127 }
2128 return pd_clone_node(n, m, mstack);
2129 }
2130
2131 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2132 Node *off = m->in(AddPNode::Offset);
2133 if (off->is_Con()) {
2134 address_visited.test_set(m->_idx); // Flag as address_visited
2135 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2136 // Clone X+offset as it also folds into most addressing expressions
2137 mstack.push(off, Visit);
2138 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2139 return true;
2140 }
2141 return false;
2142 }
2143
2144 // A method-klass-holder may be passed in the inline_cache_reg
2145 // and then expanded into the inline_cache_reg and a method_ptr register
2146 // defined in ad_<arch>.cpp
2147
2148 //------------------------------find_shared------------------------------------
2149 // Set bits if Node is shared or otherwise a root
2150 void Matcher::find_shared(Node* n) {
2151 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2152 MStack mstack(C->live_nodes() * 2);
2153 // Mark nodes as address_visited if they are inputs to an address expression
2154 VectorSet address_visited;
2155 mstack.push(n, Visit); // Don't need to pre-visit root node
2156 while (mstack.is_nonempty()) {
2157 n = mstack.node(); // Leave node on stack
2158 Node_State nstate = mstack.state();
2159 uint nop = n->Opcode();
2160 if (nstate == Pre_Visit) {
2161 if (address_visited.test(n->_idx)) { // Visited in address already?
2162 // Flag as visited and shared now.
2163 set_visited(n);
2164 }
2165 if (is_visited(n)) { // Visited already?
2166 // Node is shared and has no reason to clone. Flag it as shared.
2167 // This causes it to match into a register for the sharing.
2168 set_shared(n); // Flag as shared and
2169 if (n->is_DecodeNarrowPtr()) {
2170 // Oop field/array element loads must be shared but since
2171 // they are shared through a DecodeN they may appear to have
2172 // a single use so force sharing here.
2173 set_shared(n->in(1));
2174 }
2175 mstack.pop(); // remove node from stack
2176 continue;
2177 }
2178 nstate = Visit; // Not already visited; so visit now
2179 }
2180 if (nstate == Visit) {
2181 mstack.set_state(Post_Visit);
2182 set_visited(n); // Flag as visited now
2183 bool mem_op = false;
2184 int mem_addr_idx = MemNode::Address;
2185 if (find_shared_visit(mstack, n, nop, mem_op, mem_addr_idx)) {
2186 continue;
2187 }
2188 for (int i = n->req() - 1; i >= 0; --i) { // For my children
2189 Node* m = n->in(i); // Get ith input
2190 if (m == nullptr) {
2191 continue; // Ignore nulls
2192 }
2193 if (clone_node(n, m, mstack)) {
2194 continue;
2195 }
2196
2197 // Clone addressing expressions as they are "free" in memory access instructions
2198 if (mem_op && i == mem_addr_idx && m->is_AddP() &&
2199 // When there are other uses besides address expressions
2200 // put it on stack and mark as shared.
2201 !is_visited(m)) {
2202 // Some inputs for address expression are not put on stack
2203 // to avoid marking them as shared and forcing them into register
2204 // if they are used only in address expressions.
2205 // But they should be marked as shared if there are other uses
2206 // besides address expressions.
2207
2208 if (pd_clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2209 continue;
2210 }
2211 } // if( mem_op &&
2212 mstack.push(m, Pre_Visit);
2213 } // for(int i = ...)
2214 }
2215 else if (nstate == Alt_Post_Visit) {
2216 mstack.pop(); // Remove node from stack
2217 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2218 // shared and all users of the Bool need to move the Cmp in parallel.
2219 // This leaves both the Bool and the If pointing at the Cmp. To
2220 // prevent the Matcher from trying to Match the Cmp along both paths
2221 // BoolNode::match_edge always returns a zero.
2222
2223 // We reorder the Op_If in a pre-order manner, so we can visit without
2224 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2225 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2226 }
2227 else if (nstate == Post_Visit) {
2228 mstack.pop(); // Remove node from stack
2229
2230 // Now hack a few special opcodes
2231 uint opcode = n->Opcode();
2232 bool gc_handled = BarrierSet::barrier_set()->barrier_set_c2()->matcher_find_shared_post_visit(this, n, opcode);
2233 if (!gc_handled) {
2234 find_shared_post_visit(n, opcode);
2235 }
2236 }
2237 else {
2238 ShouldNotReachHere();
2239 }
2240 } // end of while (mstack.is_nonempty())
2241 }
2242
2243 bool Matcher::find_shared_visit(MStack& mstack, Node* n, uint opcode, bool& mem_op, int& mem_addr_idx) {
2244 switch(opcode) { // Handle some opcodes special
2245 case Op_Phi: // Treat Phis as shared roots
2246 case Op_Parm:
2247 case Op_Proj: // All handled specially during matching
2248 case Op_SafePointScalarObject:
2249 set_shared(n);
2250 set_dontcare(n);
2251 break;
2252 case Op_If:
2253 case Op_CountedLoopEnd:
2254 mstack.set_state(Alt_Post_Visit); // Alternative way
2255 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2256 // with matching cmp/branch in 1 instruction. The Matcher needs the
2257 // Bool and CmpX side-by-side, because it can only get at constants
2258 // that are at the leaves of Match trees, and the Bool's condition acts
2259 // as a constant here.
2260 mstack.push(n->in(1), Visit); // Clone the Bool
2261 mstack.push(n->in(0), Pre_Visit); // Visit control input
2262 return true; // while (mstack.is_nonempty())
2263 case Op_ConvI2D: // These forms efficiently match with a prior
2264 case Op_ConvI2F: // Load but not a following Store
2265 if( n->in(1)->is_Load() && // Prior load
2266 n->outcnt() == 1 && // Not already shared
2267 n->unique_out()->is_Store() ) // Following store
2268 set_shared(n); // Force it to be a root
2269 break;
2270 case Op_ReverseBytesI:
2271 case Op_ReverseBytesL:
2272 if( n->in(1)->is_Load() && // Prior load
2273 n->outcnt() == 1 ) // Not already shared
2274 set_shared(n); // Force it to be a root
2275 break;
2276 case Op_BoxLock: // Can't match until we get stack-regs in ADLC
2277 case Op_IfFalse:
2278 case Op_IfTrue:
2279 case Op_MachProj:
2280 case Op_MergeMem:
2281 case Op_Catch:
2282 case Op_CatchProj:
2283 case Op_CProj:
2284 case Op_JumpProj:
2285 case Op_JProj:
2286 case Op_NeverBranch:
2287 set_dontcare(n);
2288 break;
2289 case Op_Jump:
2290 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2291 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2292 return true; // while (mstack.is_nonempty())
2293 case Op_StrComp:
2294 case Op_StrEquals:
2295 case Op_StrIndexOf:
2296 case Op_StrIndexOfChar:
2297 case Op_AryEq:
2298 case Op_VectorizedHashCode:
2299 case Op_CountPositives:
2300 case Op_StrInflatedCopy:
2301 case Op_StrCompressedCopy:
2302 case Op_EncodeISOArray:
2303 case Op_FmaD:
2304 case Op_FmaF:
2305 case Op_FmaVD:
2306 case Op_FmaVF:
2307 case Op_MacroLogicV:
2308 case Op_VectorCmpMasked:
2309 case Op_CompressV:
2310 case Op_CompressM:
2311 case Op_ExpandV:
2312 case Op_VectorLoadMask:
2313 set_shared(n); // Force result into register (it will be anyways)
2314 break;
2315 case Op_ConP: { // Convert pointers above the centerline to NUL
2316 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2317 const TypePtr* tp = tn->type()->is_ptr();
2318 if (tp->_ptr == TypePtr::AnyNull) {
2319 tn->set_type(TypePtr::NULL_PTR);
2320 }
2321 break;
2322 }
2323 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2324 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2325 const TypePtr* tp = tn->type()->make_ptr();
2326 if (tp && tp->_ptr == TypePtr::AnyNull) {
2327 tn->set_type(TypeNarrowOop::NULL_PTR);
2328 }
2329 break;
2330 }
2331 case Op_Binary: // These are introduced in the Post_Visit state.
2332 ShouldNotReachHere();
2333 break;
2334 case Op_ClearArray:
2335 case Op_SafePoint:
2336 mem_op = true;
2337 break;
2338 default:
2339 if( n->is_Store() ) {
2340 // Do match stores, despite no ideal reg
2341 mem_op = true;
2342 break;
2343 }
2344 if( n->is_Mem() ) { // Loads and LoadStores
2345 mem_op = true;
2346 // Loads must be root of match tree due to prior load conflict
2347 if( C->subsume_loads() == false )
2348 set_shared(n);
2349 }
2350 // Fall into default case
2351 if( !n->ideal_reg() )
2352 set_dontcare(n); // Unmatchable Nodes
2353 } // end_switch
2354 return false;
2355 }
2356
2357 void Matcher::find_shared_post_visit(Node* n, uint opcode) {
2358 if (n->is_predicated_vector()) {
2359 // Restructure into binary trees for Matching.
2360 if (n->req() == 4) {
2361 n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2362 n->set_req(2, n->in(3));
2363 n->del_req(3);
2364 } else if (n->req() == 5) {
2365 n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2366 n->set_req(2, new BinaryNode(n->in(3), n->in(4)));
2367 n->del_req(4);
2368 n->del_req(3);
2369 } else if (n->req() == 6) {
2370 Node* b3 = new BinaryNode(n->in(4), n->in(5));
2371 Node* b2 = new BinaryNode(n->in(3), b3);
2372 Node* b1 = new BinaryNode(n->in(2), b2);
2373 n->set_req(2, b1);
2374 n->del_req(5);
2375 n->del_req(4);
2376 n->del_req(3);
2377 }
2378 return;
2379 }
2380
2381 switch(opcode) { // Handle some opcodes special
2382 case Op_CompareAndExchangeB:
2383 case Op_CompareAndExchangeS:
2384 case Op_CompareAndExchangeI:
2385 case Op_CompareAndExchangeL:
2386 case Op_CompareAndExchangeP:
2387 case Op_CompareAndExchangeN:
2388 case Op_WeakCompareAndSwapB:
2389 case Op_WeakCompareAndSwapS:
2390 case Op_WeakCompareAndSwapI:
2391 case Op_WeakCompareAndSwapL:
2392 case Op_WeakCompareAndSwapP:
2393 case Op_WeakCompareAndSwapN:
2394 case Op_CompareAndSwapB:
2395 case Op_CompareAndSwapS:
2396 case Op_CompareAndSwapI:
2397 case Op_CompareAndSwapL:
2398 case Op_CompareAndSwapP:
2399 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2400 Node* newval = n->in(MemNode::ValueIn);
2401 Node* oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2402 Node* pair = new BinaryNode(oldval, newval);
2403 n->set_req(MemNode::ValueIn, pair);
2404 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2405 break;
2406 }
2407 case Op_CMoveD: // Convert trinary to binary-tree
2408 case Op_CMoveF:
2409 case Op_CMoveI:
2410 case Op_CMoveL:
2411 case Op_CMoveN:
2412 case Op_CMoveP: {
2413 // Restructure into a binary tree for Matching. It's possible that
2414 // we could move this code up next to the graph reshaping for IfNodes
2415 // or vice-versa, but I do not want to debug this for Ladybird.
2416 // 10/2/2000 CNC.
2417 Node* pair1 = new BinaryNode(n->in(1), n->in(1)->in(1));
2418 n->set_req(1, pair1);
2419 Node* pair2 = new BinaryNode(n->in(2), n->in(3));
2420 n->set_req(2, pair2);
2421 n->del_req(3);
2422 break;
2423 }
2424 case Op_MacroLogicV: {
2425 Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2426 Node* pair2 = new BinaryNode(n->in(3), n->in(4));
2427 n->set_req(1, pair1);
2428 n->set_req(2, pair2);
2429 n->del_req(4);
2430 n->del_req(3);
2431 break;
2432 }
2433 case Op_StoreVectorMasked: {
2434 Node* pair = new BinaryNode(n->in(3), n->in(4));
2435 n->set_req(3, pair);
2436 n->del_req(4);
2437 break;
2438 }
2439 case Op_SelectFromTwoVector:
2440 case Op_LoopLimit: {
2441 Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2442 n->set_req(1, pair1);
2443 n->set_req(2, n->in(3));
2444 n->del_req(3);
2445 break;
2446 }
2447 case Op_StrEquals:
2448 case Op_StrIndexOfChar: {
2449 Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2450 n->set_req(2, pair1);
2451 n->set_req(3, n->in(4));
2452 n->del_req(4);
2453 break;
2454 }
2455 case Op_StrComp:
2456 case Op_StrIndexOf:
2457 case Op_VectorizedHashCode: {
2458 Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2459 n->set_req(2, pair1);
2460 Node* pair2 = new BinaryNode(n->in(4),n->in(5));
2461 n->set_req(3, pair2);
2462 n->del_req(5);
2463 n->del_req(4);
2464 break;
2465 }
2466 case Op_EncodeISOArray:
2467 case Op_StrCompressedCopy:
2468 case Op_StrInflatedCopy: {
2469 // Restructure into a binary tree for Matching.
2470 Node* pair = new BinaryNode(n->in(3), n->in(4));
2471 n->set_req(3, pair);
2472 n->del_req(4);
2473 break;
2474 }
2475 case Op_FmaD:
2476 case Op_FmaF:
2477 case Op_FmaVD:
2478 case Op_FmaVF: {
2479 // Restructure into a binary tree for Matching.
2480 Node* pair = new BinaryNode(n->in(1), n->in(2));
2481 n->set_req(2, pair);
2482 n->set_req(1, n->in(3));
2483 n->del_req(3);
2484 break;
2485 }
2486 case Op_MulAddS2I: {
2487 Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2488 Node* pair2 = new BinaryNode(n->in(3), n->in(4));
2489 n->set_req(1, pair1);
2490 n->set_req(2, pair2);
2491 n->del_req(4);
2492 n->del_req(3);
2493 break;
2494 }
2495 case Op_VectorCmpMasked:
2496 case Op_CopySignD:
2497 case Op_SignumVF:
2498 case Op_SignumVD:
2499 case Op_SignumF:
2500 case Op_SignumD: {
2501 Node* pair = new BinaryNode(n->in(2), n->in(3));
2502 n->set_req(2, pair);
2503 n->del_req(3);
2504 break;
2505 }
2506 case Op_VectorBlend:
2507 case Op_VectorInsert: {
2508 Node* pair = new BinaryNode(n->in(1), n->in(2));
2509 n->set_req(1, pair);
2510 n->set_req(2, n->in(3));
2511 n->del_req(3);
2512 break;
2513 }
2514 case Op_LoadVectorGather:
2515 if (is_subword_type(n->bottom_type()->is_vect()->element_basic_type())) {
2516 Node* pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2517 n->set_req(MemNode::ValueIn, pair);
2518 n->del_req(MemNode::ValueIn+1);
2519 }
2520 break;
2521 case Op_LoadVectorGatherMasked:
2522 if (is_subword_type(n->bottom_type()->is_vect()->element_basic_type())) {
2523 Node* pair2 = new BinaryNode(n->in(MemNode::ValueIn + 1), n->in(MemNode::ValueIn + 2));
2524 Node* pair1 = new BinaryNode(n->in(MemNode::ValueIn), pair2);
2525 n->set_req(MemNode::ValueIn, pair1);
2526 n->del_req(MemNode::ValueIn+2);
2527 n->del_req(MemNode::ValueIn+1);
2528 break;
2529 } // fall-through
2530 case Op_StoreVectorScatter: {
2531 Node* pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2532 n->set_req(MemNode::ValueIn, pair);
2533 n->del_req(MemNode::ValueIn+1);
2534 break;
2535 }
2536 case Op_StoreVectorScatterMasked: {
2537 Node* pair = new BinaryNode(n->in(MemNode::ValueIn+1), n->in(MemNode::ValueIn+2));
2538 n->set_req(MemNode::ValueIn+1, pair);
2539 n->del_req(MemNode::ValueIn+2);
2540 pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2541 n->set_req(MemNode::ValueIn, pair);
2542 n->del_req(MemNode::ValueIn+1);
2543 break;
2544 }
2545 case Op_VectorMaskCmp: {
2546 n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2547 n->set_req(2, n->in(3));
2548 n->del_req(3);
2549 break;
2550 }
2551 case Op_PartialSubtypeCheck: {
2552 if (UseSecondarySupersTable && n->in(2)->is_Con()) {
2553 // PartialSubtypeCheck uses both constant and register operands for superclass input.
2554 n->set_req(2, new BinaryNode(n->in(2), n->in(2)));
2555 break;
2556 }
2557 break;
2558 }
2559 default:
2560 break;
2561 }
2562 }
2563
2564 #ifndef PRODUCT
2565 void Matcher::record_new2old(Node* newn, Node* old) {
2566 _new2old_map.map(newn->_idx, old);
2567 if (!_reused.test_set(old->_igv_idx)) {
2568 // Reuse the Ideal-level IGV identifier so that the node can be tracked
2569 // across matching. If there are multiple machine nodes expanded from the
2570 // same Ideal node, only one will reuse its IGV identifier.
2571 newn->_igv_idx = old->_igv_idx;
2572 }
2573 }
2574
2575 // machine-independent root to machine-dependent root
2576 void Matcher::dump_old2new_map() {
2577 _old2new_map.dump();
2578 }
2579 #endif // !PRODUCT
2580
2581 //---------------------------collect_null_checks-------------------------------
2582 // Find null checks in the ideal graph; write a machine-specific node for
2583 // it. Used by later implicit-null-check handling. Actually collects
2584 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2585 // value being tested.
2586 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2587 Node *iff = proj->in(0);
2588 if( iff->Opcode() == Op_If ) {
2589 // During matching If's have Bool & Cmp side-by-side
2590 BoolNode *b = iff->in(1)->as_Bool();
2591 Node *cmp = iff->in(2);
2592 int opc = cmp->Opcode();
2593 if (opc != Op_CmpP && opc != Op_CmpN) return;
2594
2595 const Type* ct = cmp->in(2)->bottom_type();
2596 if (ct == TypePtr::NULL_PTR ||
2597 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2598
2599 bool push_it = false;
2600 if( proj->Opcode() == Op_IfTrue ) {
2601 #ifndef PRODUCT
2602 extern uint all_null_checks_found;
2603 all_null_checks_found++;
2604 #endif
2605 if( b->_test._test == BoolTest::ne ) {
2606 push_it = true;
2607 }
2608 } else {
2609 assert( proj->Opcode() == Op_IfFalse, "" );
2610 if( b->_test._test == BoolTest::eq ) {
2611 push_it = true;
2612 }
2613 }
2614 if( push_it ) {
2615 _null_check_tests.push(proj);
2616 Node* val = cmp->in(1);
2617 #ifdef _LP64
2618 if (val->bottom_type()->isa_narrowoop() &&
2619 !Matcher::narrow_oop_use_complex_address()) {
2620 //
2621 // Look for DecodeN node which should be pinned to orig_proj.
2622 // On platforms (Sparc) which can not handle 2 adds
2623 // in addressing mode we have to keep a DecodeN node and
2624 // use it to do implicit null check in address.
2625 //
2626 // DecodeN node was pinned to non-null path (orig_proj) during
2627 // CastPP transformation in final_graph_reshaping_impl().
2628 //
2629 uint cnt = orig_proj->outcnt();
2630 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2631 Node* d = orig_proj->raw_out(i);
2632 if (d->is_DecodeN() && d->in(1) == val) {
2633 val = d;
2634 val->set_req(0, nullptr); // Unpin now.
2635 // Mark this as special case to distinguish from
2636 // a regular case: CmpP(DecodeN, null).
2637 val = (Node*)(((intptr_t)val) | 1);
2638 break;
2639 }
2640 }
2641 }
2642 #endif
2643 _null_check_tests.push(val);
2644 }
2645 }
2646 }
2647 }
2648
2649 //---------------------------validate_null_checks------------------------------
2650 // Its possible that the value being null checked is not the root of a match
2651 // tree. If so, I cannot use the value in an implicit null check.
2652 void Matcher::validate_null_checks( ) {
2653 uint cnt = _null_check_tests.size();
2654 for( uint i=0; i < cnt; i+=2 ) {
2655 Node *test = _null_check_tests[i];
2656 Node *val = _null_check_tests[i+1];
2657 bool is_decoden = ((intptr_t)val) & 1;
2658 val = (Node*)(((intptr_t)val) & ~1);
2659 if (has_new_node(val)) {
2660 Node* new_val = new_node(val);
2661 if (is_decoden) {
2662 assert(val->is_DecodeNarrowPtr() && val->in(0) == nullptr, "sanity");
2663 // Note: new_val may have a control edge if
2664 // the original ideal node DecodeN was matched before
2665 // it was unpinned in Matcher::collect_null_checks().
2666 // Unpin the mach node and mark it.
2667 new_val->set_req(0, nullptr);
2668 new_val = (Node*)(((intptr_t)new_val) | 1);
2669 }
2670 // Is a match-tree root, so replace with the matched value
2671 _null_check_tests.map(i+1, new_val);
2672 } else {
2673 // Yank from candidate list
2674 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2675 _null_check_tests.map(i,_null_check_tests[--cnt]);
2676 _null_check_tests.pop();
2677 _null_check_tests.pop();
2678 i-=2;
2679 }
2680 }
2681 }
2682
2683 bool Matcher::gen_narrow_oop_implicit_null_checks() {
2684 // Advice matcher to perform null checks on the narrow oop side.
2685 // Implicit checks are not possible on the uncompressed oop side anyway
2686 // (at least not for read accesses).
2687 // Performs significantly better (especially on Power 6).
2688 if (!os::zero_page_read_protected()) {
2689 return true;
2690 }
2691 return CompressedOops::use_implicit_null_checks() &&
2692 (narrow_oop_use_complex_address() ||
2693 CompressedOops::base() != nullptr);
2694 }
2695
2696 // Compute RegMask for an ideal register.
2697 const RegMask* Matcher::regmask_for_ideal_register(uint ideal_reg, Node* ret) {
2698 assert(!C->failing_internal() || C->failure_is_artificial(), "already failing.");
2699 if (C->failing()) {
2700 return nullptr;
2701 }
2702 const Type* t = Type::mreg2type[ideal_reg];
2703 if (t == nullptr) {
2704 assert(ideal_reg >= Op_VecA && ideal_reg <= Op_VecZ, "not a vector: %d", ideal_reg);
2705 return nullptr; // not supported
2706 }
2707 Node* fp = ret->in(TypeFunc::FramePtr);
2708 Node* mem = ret->in(TypeFunc::Memory);
2709 const TypePtr* atp = TypePtr::BOTTOM;
2710 MemNode::MemOrd mo = MemNode::unordered;
2711
2712 Node* spill;
2713 switch (ideal_reg) {
2714 case Op_RegN: spill = new LoadNNode(nullptr, mem, fp, atp, t->is_narrowoop(), mo); break;
2715 case Op_RegI: spill = new LoadINode(nullptr, mem, fp, atp, t->is_int(), mo); break;
2716 case Op_RegP: spill = new LoadPNode(nullptr, mem, fp, atp, t->is_ptr(), mo); break;
2717 case Op_RegF: spill = new LoadFNode(nullptr, mem, fp, atp, t, mo); break;
2718 case Op_RegD: spill = new LoadDNode(nullptr, mem, fp, atp, t, mo); break;
2719 case Op_RegL: spill = new LoadLNode(nullptr, mem, fp, atp, t->is_long(), mo); break;
2720
2721 case Op_VecA: // fall-through
2722 case Op_VecS: // fall-through
2723 case Op_VecD: // fall-through
2724 case Op_VecX: // fall-through
2725 case Op_VecY: // fall-through
2726 case Op_VecZ: spill = new LoadVectorNode(nullptr, mem, fp, atp, t->is_vect()); break;
2727 case Op_RegVectMask: return Matcher::predicate_reg_mask();
2728
2729 default: ShouldNotReachHere();
2730 }
2731 MachNode* mspill = match_tree(spill);
2732 assert(mspill != nullptr || C->failure_is_artificial(), "matching failed: %d", ideal_reg);
2733 if (C->failing()) {
2734 return nullptr;
2735 }
2736 // Handle generic vector operand case
2737 if (Matcher::supports_generic_vector_operands && t->isa_vect()) {
2738 specialize_mach_node(mspill);
2739 }
2740 return &mspill->out_RegMask();
2741 }
2742
2743 // Process Mach IR right after selection phase is over.
2744 void Matcher::do_postselect_cleanup() {
2745 if (supports_generic_vector_operands) {
2746 specialize_generic_vector_operands();
2747 if (C->failing()) return;
2748 }
2749 }
2750
2751 //----------------------------------------------------------------------
2752 // Generic machine operands elision.
2753 //----------------------------------------------------------------------
2754
2755 // Compute concrete vector operand for a generic TEMP vector mach node based on its user info.
2756 void Matcher::specialize_temp_node(MachTempNode* tmp, MachNode* use, uint idx) {
2757 assert(use->in(idx) == tmp, "not a user");
2758 assert(!Matcher::is_generic_vector(use->_opnds[0]), "use not processed yet");
2759
2760 if ((uint)idx == use->two_adr()) { // DEF_TEMP case
2761 tmp->_opnds[0] = use->_opnds[0]->clone();
2762 } else {
2763 uint ideal_vreg = vector_ideal_reg(C->max_vector_size());
2764 tmp->_opnds[0] = Matcher::pd_specialize_generic_vector_operand(tmp->_opnds[0], ideal_vreg, true /*is_temp*/);
2765 }
2766 }
2767
2768 // Compute concrete vector operand for a generic DEF/USE vector operand (of mach node m at index idx).
2769 MachOper* Matcher::specialize_vector_operand(MachNode* m, uint opnd_idx) {
2770 assert(Matcher::is_generic_vector(m->_opnds[opnd_idx]), "repeated updates");
2771 Node* def = nullptr;
2772 if (opnd_idx == 0) { // DEF
2773 def = m; // use mach node itself to compute vector operand type
2774 } else {
2775 int base_idx = m->operand_index(opnd_idx);
2776 def = m->in(base_idx);
2777 if (def->is_Mach()) {
2778 if (def->is_MachTemp() && Matcher::is_generic_vector(def->as_Mach()->_opnds[0])) {
2779 specialize_temp_node(def->as_MachTemp(), m, base_idx); // MachTemp node use site
2780 } else if (is_reg2reg_move(def->as_Mach())) {
2781 def = def->in(1); // skip over generic reg-to-reg moves
2782 }
2783 }
2784 }
2785 assert(def->bottom_type()->isa_vect(), "not a vector");
2786 uint ideal_vreg = def->bottom_type()->ideal_reg();
2787 return Matcher::pd_specialize_generic_vector_operand(m->_opnds[opnd_idx], ideal_vreg, false /*is_temp*/);
2788 }
2789
2790 void Matcher::specialize_mach_node(MachNode* m) {
2791 assert(!m->is_MachTemp(), "processed along with its user");
2792 // For generic use operands pull specific register class operands from
2793 // its def instruction's output operand (def operand).
2794 for (uint i = 0; i < m->num_opnds(); i++) {
2795 if (Matcher::is_generic_vector(m->_opnds[i])) {
2796 m->_opnds[i] = specialize_vector_operand(m, i);
2797 }
2798 }
2799 }
2800
2801 // Replace generic vector operands with concrete vector operands and eliminate generic reg-to-reg moves from the graph.
2802 void Matcher::specialize_generic_vector_operands() {
2803 assert(supports_generic_vector_operands, "sanity");
2804 ResourceMark rm;
2805
2806 // Replace generic vector operands (vec/legVec) with concrete ones (vec[SDXYZ]/legVec[SDXYZ])
2807 // and remove reg-to-reg vector moves (MoveVec2Leg and MoveLeg2Vec).
2808 Unique_Node_List live_nodes;
2809 C->identify_useful_nodes(live_nodes);
2810
2811 while (live_nodes.size() > 0) {
2812 MachNode* m = live_nodes.pop()->isa_Mach();
2813 if (m != nullptr) {
2814 if (Matcher::is_reg2reg_move(m)) {
2815 // Register allocator properly handles vec <=> leg moves using register masks.
2816 int opnd_idx = m->operand_index(1);
2817 Node* def = m->in(opnd_idx);
2818 m->subsume_by(def, C);
2819 } else if (m->is_MachTemp()) {
2820 // process MachTemp nodes at use site (see Matcher::specialize_vector_operand)
2821 } else {
2822 specialize_mach_node(m);
2823 }
2824 }
2825 }
2826 }
2827
2828 uint Matcher::vector_length(const Node* n) {
2829 const TypeVect* vt = n->bottom_type()->is_vect();
2830 return vt->length();
2831 }
2832
2833 uint Matcher::vector_length(const MachNode* use, const MachOper* opnd) {
2834 int def_idx = use->operand_index(opnd);
2835 Node* def = use->in(def_idx);
2836 return def->bottom_type()->is_vect()->length();
2837 }
2838
2839 uint Matcher::vector_length_in_bytes(const Node* n) {
2840 const TypeVect* vt = n->bottom_type()->is_vect();
2841 return vt->length_in_bytes();
2842 }
2843
2844 uint Matcher::vector_length_in_bytes(const MachNode* use, const MachOper* opnd) {
2845 uint def_idx = use->operand_index(opnd);
2846 Node* def = use->in(def_idx);
2847 return def->bottom_type()->is_vect()->length_in_bytes();
2848 }
2849
2850 BasicType Matcher::vector_element_basic_type(const Node* n) {
2851 const TypeVect* vt = n->bottom_type()->is_vect();
2852 return vt->element_basic_type();
2853 }
2854
2855 BasicType Matcher::vector_element_basic_type(const MachNode* use, const MachOper* opnd) {
2856 int def_idx = use->operand_index(opnd);
2857 Node* def = use->in(def_idx);
2858 return def->bottom_type()->is_vect()->element_basic_type();
2859 }
2860
2861 bool Matcher::is_non_long_integral_vector(const Node* n) {
2862 BasicType bt = vector_element_basic_type(n);
2863 assert(bt != T_CHAR, "char is not allowed in vector");
2864 return is_subword_type(bt) || bt == T_INT;
2865 }
2866
2867 bool Matcher::is_encode_and_store_pattern(const Node* n, const Node* m) {
2868 if (n == nullptr ||
2869 m == nullptr ||
2870 n->Opcode() != Op_StoreN ||
2871 !m->is_EncodeP() ||
2872 n->as_Store()->barrier_data() == 0) {
2873 return false;
2874 }
2875 assert(m == n->in(MemNode::ValueIn), "m should be input to n");
2876 return true;
2877 }
2878
2879 #ifdef ASSERT
2880 bool Matcher::verify_after_postselect_cleanup() {
2881 assert(!C->failing_internal() || C->failure_is_artificial(), "sanity");
2882 if (supports_generic_vector_operands) {
2883 Unique_Node_List useful;
2884 C->identify_useful_nodes(useful);
2885 for (uint i = 0; i < useful.size(); i++) {
2886 MachNode* m = useful.at(i)->isa_Mach();
2887 if (m != nullptr) {
2888 assert(!Matcher::is_reg2reg_move(m), "no MoveVec nodes allowed");
2889 for (uint j = 0; j < m->num_opnds(); j++) {
2890 assert(!Matcher::is_generic_vector(m->_opnds[j]), "no generic vector operands allowed");
2891 }
2892 }
2893 }
2894 }
2895 return true;
2896 }
2897 #endif // ASSERT
2898
2899 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2900 // atomic instruction acting as a store_load barrier without any
2901 // intervening volatile load, and thus we don't need a barrier here.
2902 // We retain the Node to act as a compiler ordering barrier.
2903 bool Matcher::post_store_load_barrier(const Node* vmb) {
2904 Compile* C = Compile::current();
2905 assert(vmb->is_MemBar(), "");
2906 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2907 const MemBarNode* membar = vmb->as_MemBar();
2908
2909 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2910 Node* ctrl = nullptr;
2911 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2912 Node* p = membar->fast_out(i);
2913 assert(p->is_Proj(), "only projections here");
2914 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2915 !C->node_arena()->contains(p)) { // Unmatched old-space only
2916 ctrl = p;
2917 break;
2918 }
2919 }
2920 assert((ctrl != nullptr), "missing control projection");
2921
2922 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2923 Node *x = ctrl->fast_out(j);
2924 int xop = x->Opcode();
2925
2926 // We don't need current barrier if we see another or a lock
2927 // before seeing volatile load.
2928 //
2929 // Op_Fastunlock previously appeared in the Op_* list below.
2930 // With the advent of 1-0 lock operations we're no longer guaranteed
2931 // that a monitor exit operation contains a serializing instruction.
2932
2933 if (xop == Op_MemBarVolatile ||
2934 xop == Op_CompareAndExchangeB ||
2935 xop == Op_CompareAndExchangeS ||
2936 xop == Op_CompareAndExchangeI ||
2937 xop == Op_CompareAndExchangeL ||
2938 xop == Op_CompareAndExchangeP ||
2939 xop == Op_CompareAndExchangeN ||
2940 xop == Op_WeakCompareAndSwapB ||
2941 xop == Op_WeakCompareAndSwapS ||
2942 xop == Op_WeakCompareAndSwapL ||
2943 xop == Op_WeakCompareAndSwapP ||
2944 xop == Op_WeakCompareAndSwapN ||
2945 xop == Op_WeakCompareAndSwapI ||
2946 xop == Op_CompareAndSwapB ||
2947 xop == Op_CompareAndSwapS ||
2948 xop == Op_CompareAndSwapL ||
2949 xop == Op_CompareAndSwapP ||
2950 xop == Op_CompareAndSwapN ||
2951 xop == Op_CompareAndSwapI ||
2952 BarrierSet::barrier_set()->barrier_set_c2()->matcher_is_store_load_barrier(x, xop)) {
2953 return true;
2954 }
2955
2956 // Op_FastLock previously appeared in the Op_* list above.
2957 if (xop == Op_FastLock) {
2958 return true;
2959 }
2960
2961 if (x->is_MemBar()) {
2962 // We must retain this membar if there is an upcoming volatile
2963 // load, which will be followed by acquire membar.
2964 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2965 return false;
2966 } else {
2967 // For other kinds of barriers, check by pretending we
2968 // are them, and seeing if we can be removed.
2969 return post_store_load_barrier(x->as_MemBar());
2970 }
2971 }
2972
2973 // probably not necessary to check for these
2974 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2975 return false;
2976 }
2977 }
2978 return false;
2979 }
2980
2981 // Check whether node n is a branch to an uncommon trap that we could
2982 // optimize as test with very high branch costs in case of going to
2983 // the uncommon trap. The code must be able to be recompiled to use
2984 // a cheaper test.
2985 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2986 // Don't do it for natives, adapters, or runtime stubs
2987 Compile *C = Compile::current();
2988 if (!C->is_method_compilation()) return false;
2989
2990 assert(n->is_If(), "You should only call this on if nodes.");
2991 IfNode *ifn = n->as_If();
2992
2993 Node *ifFalse = nullptr;
2994 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2995 if (ifn->fast_out(i)->is_IfFalse()) {
2996 ifFalse = ifn->fast_out(i);
2997 break;
2998 }
2999 }
3000 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
3001
3002 Node *reg = ifFalse;
3003 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
3004 // Alternatively use visited set? Seems too expensive.
3005 while (reg != nullptr && cnt > 0) {
3006 CallNode *call = nullptr;
3007 RegionNode *nxt_reg = nullptr;
3008 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
3009 Node *o = reg->fast_out(i);
3010 if (o->is_Call()) {
3011 call = o->as_Call();
3012 }
3013 if (o->is_Region()) {
3014 nxt_reg = o->as_Region();
3015 }
3016 }
3017
3018 if (call &&
3019 call->entry_point() == OptoRuntime::uncommon_trap_blob()->entry_point()) {
3020 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
3021 if (trtype->isa_int() && trtype->is_int()->is_con()) {
3022 jint tr_con = trtype->is_int()->get_con();
3023 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
3024 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
3025 assert((int)reason < (int)BitsPerInt, "recode bit map");
3026
3027 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
3028 && action != Deoptimization::Action_none) {
3029 // This uncommon trap is sure to recompile, eventually.
3030 // When that happens, C->too_many_traps will prevent
3031 // this transformation from happening again.
3032 return true;
3033 }
3034 }
3035 }
3036
3037 reg = nxt_reg;
3038 cnt--;
3039 }
3040
3041 return false;
3042 }
3043
3044 //=============================================================================
3045 //---------------------------State---------------------------------------------
3046 State::State(void) : _rule() {
3047 #ifdef ASSERT
3048 _id = 0;
3049 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
3050 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
3051 #endif
3052 }
3053
3054 #ifdef ASSERT
3055 State::~State() {
3056 _id = 99;
3057 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
3058 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
3059 memset(_cost, -3, sizeof(_cost));
3060 memset(_rule, -3, sizeof(_rule));
3061 }
3062 #endif
3063
3064 #ifndef PRODUCT
3065 //---------------------------dump----------------------------------------------
3066 void State::dump() {
3067 tty->print("\n");
3068 dump(0);
3069 }
3070
3071 void State::dump(int depth) {
3072 for (int j = 0; j < depth; j++) {
3073 tty->print(" ");
3074 }
3075 tty->print("--N: ");
3076 _leaf->dump();
3077 uint i;
3078 for (i = 0; i < _LAST_MACH_OPER; i++) {
3079 // Check for valid entry
3080 if (valid(i)) {
3081 for (int j = 0; j < depth; j++) {
3082 tty->print(" ");
3083 }
3084 assert(cost(i) != max_juint, "cost must be a valid value");
3085 assert(rule(i) < _last_Mach_Node, "rule[i] must be valid rule");
3086 tty->print_cr("%s %d %s",
3087 ruleName[i], cost(i), ruleName[rule(i)] );
3088 }
3089 }
3090 tty->cr();
3091
3092 for (i = 0; i < 2; i++) {
3093 if (_kids[i]) {
3094 _kids[i]->dump(depth + 1);
3095 }
3096 }
3097 }
3098 #endif