1 /* 2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "gc/shared/barrierSet.hpp" 27 #include "gc/shared/c2/barrierSetC2.hpp" 28 #include "memory/allocation.inline.hpp" 29 #include "memory/resourceArea.hpp" 30 #include "oops/compressedOops.hpp" 31 #include "opto/ad.hpp" 32 #include "opto/addnode.hpp" 33 #include "opto/callnode.hpp" 34 #include "opto/idealGraphPrinter.hpp" 35 #include "opto/matcher.hpp" 36 #include "opto/memnode.hpp" 37 #include "opto/movenode.hpp" 38 #include "opto/opcodes.hpp" 39 #include "opto/regmask.hpp" 40 #include "opto/rootnode.hpp" 41 #include "opto/runtime.hpp" 42 #include "opto/type.hpp" 43 #include "opto/vectornode.hpp" 44 #include "runtime/os.inline.hpp" 45 #include "runtime/sharedRuntime.hpp" 46 #include "utilities/align.hpp" 47 48 OptoReg::Name OptoReg::c_frame_pointer; 49 50 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf]; 51 RegMask Matcher::mreg2regmask[_last_Mach_Reg]; 52 RegMask Matcher::caller_save_regmask; 53 RegMask Matcher::caller_save_regmask_exclude_soe; 54 RegMask Matcher::mh_caller_save_regmask; 55 RegMask Matcher::mh_caller_save_regmask_exclude_soe; 56 RegMask Matcher::STACK_ONLY_mask; 57 RegMask Matcher::c_frame_ptr_mask; 58 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE; 59 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE; 60 61 //---------------------------Matcher------------------------------------------- 62 Matcher::Matcher() 63 : PhaseTransform( Phase::Ins_Select ), 64 _states_arena(Chunk::medium_size, mtCompiler), 65 _new_nodes(C->comp_arena()), 66 _visited(&_states_arena), 67 _shared(&_states_arena), 68 _dontcare(&_states_arena), 69 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp), 70 _swallowed(swallowed), 71 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE), 72 _end_inst_chain_rule(_END_INST_CHAIN_RULE), 73 _must_clone(must_clone), 74 _shared_nodes(C->comp_arena()), 75 #ifndef PRODUCT 76 _old2new_map(C->comp_arena()), 77 _new2old_map(C->comp_arena()), 78 _reused(C->comp_arena()), 79 #endif // !PRODUCT 80 _allocation_started(false), 81 _ruleName(ruleName), 82 _register_save_policy(register_save_policy), 83 _c_reg_save_policy(c_reg_save_policy), 84 _register_save_type(register_save_type) { 85 C->set_matcher(this); 86 87 idealreg2spillmask [Op_RegI] = nullptr; 88 idealreg2spillmask [Op_RegN] = nullptr; 89 idealreg2spillmask [Op_RegL] = nullptr; 90 idealreg2spillmask [Op_RegF] = nullptr; 91 idealreg2spillmask [Op_RegD] = nullptr; 92 idealreg2spillmask [Op_RegP] = nullptr; 93 idealreg2spillmask [Op_VecA] = nullptr; 94 idealreg2spillmask [Op_VecS] = nullptr; 95 idealreg2spillmask [Op_VecD] = nullptr; 96 idealreg2spillmask [Op_VecX] = nullptr; 97 idealreg2spillmask [Op_VecY] = nullptr; 98 idealreg2spillmask [Op_VecZ] = nullptr; 99 idealreg2spillmask [Op_RegFlags] = nullptr; 100 idealreg2spillmask [Op_RegVectMask] = nullptr; 101 102 idealreg2debugmask [Op_RegI] = nullptr; 103 idealreg2debugmask [Op_RegN] = nullptr; 104 idealreg2debugmask [Op_RegL] = nullptr; 105 idealreg2debugmask [Op_RegF] = nullptr; 106 idealreg2debugmask [Op_RegD] = nullptr; 107 idealreg2debugmask [Op_RegP] = nullptr; 108 idealreg2debugmask [Op_VecA] = nullptr; 109 idealreg2debugmask [Op_VecS] = nullptr; 110 idealreg2debugmask [Op_VecD] = nullptr; 111 idealreg2debugmask [Op_VecX] = nullptr; 112 idealreg2debugmask [Op_VecY] = nullptr; 113 idealreg2debugmask [Op_VecZ] = nullptr; 114 idealreg2debugmask [Op_RegFlags] = nullptr; 115 idealreg2debugmask [Op_RegVectMask] = nullptr; 116 117 idealreg2mhdebugmask[Op_RegI] = nullptr; 118 idealreg2mhdebugmask[Op_RegN] = nullptr; 119 idealreg2mhdebugmask[Op_RegL] = nullptr; 120 idealreg2mhdebugmask[Op_RegF] = nullptr; 121 idealreg2mhdebugmask[Op_RegD] = nullptr; 122 idealreg2mhdebugmask[Op_RegP] = nullptr; 123 idealreg2mhdebugmask[Op_VecA] = nullptr; 124 idealreg2mhdebugmask[Op_VecS] = nullptr; 125 idealreg2mhdebugmask[Op_VecD] = nullptr; 126 idealreg2mhdebugmask[Op_VecX] = nullptr; 127 idealreg2mhdebugmask[Op_VecY] = nullptr; 128 idealreg2mhdebugmask[Op_VecZ] = nullptr; 129 idealreg2mhdebugmask[Op_RegFlags] = nullptr; 130 idealreg2mhdebugmask[Op_RegVectMask] = nullptr; 131 132 debug_only(_mem_node = nullptr;) // Ideal memory node consumed by mach node 133 } 134 135 //------------------------------warp_incoming_stk_arg------------------------ 136 // This warps a VMReg into an OptoReg::Name 137 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) { 138 OptoReg::Name warped; 139 if( reg->is_stack() ) { // Stack slot argument? 140 warped = OptoReg::add(_old_SP, reg->reg2stack() ); 141 warped = OptoReg::add(warped, C->out_preserve_stack_slots()); 142 if( warped >= _in_arg_limit ) 143 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen 144 if (!RegMask::can_represent_arg(warped)) { 145 // the compiler cannot represent this method's calling sequence 146 // Bailout. We do not have space to represent all arguments. 147 C->record_method_not_compilable("unsupported incoming calling sequence"); 148 return OptoReg::Bad; 149 } 150 return warped; 151 } 152 return OptoReg::as_OptoReg(reg); 153 } 154 155 //---------------------------compute_old_SP------------------------------------ 156 OptoReg::Name Compile::compute_old_SP() { 157 int fixed = fixed_slots(); 158 int preserve = in_preserve_stack_slots(); 159 return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots())); 160 } 161 162 163 164 #ifdef ASSERT 165 void Matcher::verify_new_nodes_only(Node* xroot) { 166 // Make sure that the new graph only references new nodes 167 ResourceMark rm; 168 Unique_Node_List worklist; 169 VectorSet visited; 170 worklist.push(xroot); 171 while (worklist.size() > 0) { 172 Node* n = worklist.pop(); 173 visited.set(n->_idx); 174 assert(C->node_arena()->contains(n), "dead node"); 175 for (uint j = 0; j < n->req(); j++) { 176 Node* in = n->in(j); 177 if (in != nullptr) { 178 assert(C->node_arena()->contains(in), "dead node"); 179 if (!visited.test(in->_idx)) { 180 worklist.push(in); 181 } 182 } 183 } 184 } 185 } 186 #endif 187 188 // Array of RegMask, one per returned values (inline type instances can 189 // be returned as multiple return values, one per field) 190 RegMask* Matcher::return_values_mask(const TypeFunc* tf) { 191 const TypeTuple* range = tf->range_cc(); 192 uint cnt = range->cnt() - TypeFunc::Parms; 193 if (cnt == 0) { 194 return nullptr; 195 } 196 RegMask* mask = NEW_RESOURCE_ARRAY(RegMask, cnt); 197 BasicType* sig_bt = NEW_RESOURCE_ARRAY(BasicType, cnt); 198 VMRegPair* vm_parm_regs = NEW_RESOURCE_ARRAY(VMRegPair, cnt); 199 for (uint i = 0; i < cnt; i++) { 200 sig_bt[i] = range->field_at(i+TypeFunc::Parms)->basic_type(); 201 } 202 203 int regs = SharedRuntime::java_return_convention(sig_bt, vm_parm_regs, cnt); 204 if (regs <= 0) { 205 // We ran out of registers to store the IsInit information for a nullable inline type return. 206 // Since it is only set in the 'call_epilog', we can simply put it on the stack. 207 assert(tf->returns_inline_type_as_fields(), "should have been tested during graph construction"); 208 // TODO 8284443 Can we teach the register allocator to reserve a stack slot instead? 209 // mask[--cnt] = STACK_ONLY_mask does not work (test with -XX:+StressGCM) 210 int slot = C->fixed_slots() - 2; 211 if (C->needs_stack_repair()) { 212 slot -= 2; // Account for stack increment value 213 } 214 mask[--cnt].Clear(); 215 mask[cnt].Insert(OptoReg::stack2reg(slot)); 216 } 217 for (uint i = 0; i < cnt; i++) { 218 mask[i].Clear(); 219 220 OptoReg::Name reg1 = OptoReg::as_OptoReg(vm_parm_regs[i].first()); 221 if (OptoReg::is_valid(reg1)) { 222 mask[i].Insert(reg1); 223 } 224 OptoReg::Name reg2 = OptoReg::as_OptoReg(vm_parm_regs[i].second()); 225 if (OptoReg::is_valid(reg2)) { 226 mask[i].Insert(reg2); 227 } 228 } 229 230 return mask; 231 } 232 233 //---------------------------match--------------------------------------------- 234 void Matcher::match( ) { 235 if( MaxLabelRootDepth < 100 ) { // Too small? 236 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum"); 237 MaxLabelRootDepth = 100; 238 } 239 // One-time initialization of some register masks. 240 init_spill_mask( C->root()->in(1) ); 241 _return_addr_mask = return_addr(); 242 #ifdef _LP64 243 // Pointers take 2 slots in 64-bit land 244 _return_addr_mask.Insert(OptoReg::add(return_addr(),1)); 245 #endif 246 247 // Map Java-signature return types into return register-value 248 // machine registers. 249 _return_values_mask = return_values_mask(C->tf()); 250 251 // --------------- 252 // Frame Layout 253 254 // Need the method signature to determine the incoming argument types, 255 // because the types determine which registers the incoming arguments are 256 // in, and this affects the matched code. 257 const TypeTuple *domain = C->tf()->domain_cc(); 258 uint argcnt = domain->cnt() - TypeFunc::Parms; 259 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 260 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 261 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt ); 262 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt ); 263 uint i; 264 for( i = 0; i<argcnt; i++ ) { 265 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type(); 266 } 267 268 // Pass array of ideal registers and length to USER code (from the AD file) 269 // that will convert this to an array of register numbers. 270 const StartNode *start = C->start(); 271 start->calling_convention( sig_bt, vm_parm_regs, argcnt ); 272 #ifdef ASSERT 273 // Sanity check users' calling convention. Real handy while trying to 274 // get the initial port correct. 275 { for (uint i = 0; i<argcnt; i++) { 276 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 277 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" ); 278 _parm_regs[i].set_bad(); 279 continue; 280 } 281 VMReg parm_reg = vm_parm_regs[i].first(); 282 assert(parm_reg->is_valid(), "invalid arg?"); 283 if (parm_reg->is_reg()) { 284 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg); 285 assert(can_be_java_arg(opto_parm_reg) || 286 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) || 287 opto_parm_reg == inline_cache_reg(), 288 "parameters in register must be preserved by runtime stubs"); 289 } 290 for (uint j = 0; j < i; j++) { 291 assert(parm_reg != vm_parm_regs[j].first(), 292 "calling conv. must produce distinct regs"); 293 } 294 } 295 } 296 #endif 297 298 // Do some initial frame layout. 299 300 // Compute the old incoming SP (may be called FP) as 301 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2. 302 _old_SP = C->compute_old_SP(); 303 assert( is_even(_old_SP), "must be even" ); 304 305 // Compute highest incoming stack argument as 306 // _old_SP + out_preserve_stack_slots + incoming argument size. 307 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 308 assert( is_even(_in_arg_limit), "out_preserve must be even" ); 309 for( i = 0; i < argcnt; i++ ) { 310 // Permit args to have no register 311 _calling_convention_mask[i].Clear(); 312 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) { 313 _parm_regs[i].set_bad(); 314 continue; 315 } 316 // calling_convention returns stack arguments as a count of 317 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to 318 // the allocators point of view, taking into account all the 319 // preserve area, locks & pad2. 320 321 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first()); 322 if( OptoReg::is_valid(reg1)) 323 _calling_convention_mask[i].Insert(reg1); 324 325 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second()); 326 if( OptoReg::is_valid(reg2)) 327 _calling_convention_mask[i].Insert(reg2); 328 329 // Saved biased stack-slot register number 330 _parm_regs[i].set_pair(reg2, reg1); 331 } 332 333 // Finally, make sure the incoming arguments take up an even number of 334 // words, in case the arguments or locals need to contain doubleword stack 335 // slots. The rest of the system assumes that stack slot pairs (in 336 // particular, in the spill area) which look aligned will in fact be 337 // aligned relative to the stack pointer in the target machine. Double 338 // stack slots will always be allocated aligned. 339 _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong)); 340 341 // Compute highest outgoing stack argument as 342 // _new_SP + out_preserve_stack_slots + max(outgoing argument size). 343 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 344 assert( is_even(_out_arg_limit), "out_preserve must be even" ); 345 346 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) { 347 // the compiler cannot represent this method's calling sequence 348 // Bailout. We do not have space to represent all arguments. 349 C->record_method_not_compilable("must be able to represent all call arguments in reg mask"); 350 } 351 352 if (C->failing()) return; // bailed out on incoming arg failure 353 354 // --------------- 355 // Collect roots of matcher trees. Every node for which 356 // _shared[_idx] is cleared is guaranteed to not be shared, and thus 357 // can be a valid interior of some tree. 358 find_shared( C->root() ); 359 find_shared( C->top() ); 360 361 C->print_method(PHASE_BEFORE_MATCHING, 1); 362 363 // Create new ideal node ConP #null even if it does exist in old space 364 // to avoid false sharing if the corresponding mach node is not used. 365 // The corresponding mach node is only used in rare cases for derived 366 // pointers. 367 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR); 368 369 // Swap out to old-space; emptying new-space 370 Arena* old = C->swap_old_and_new(); 371 372 // Save debug and profile information for nodes in old space: 373 _old_node_note_array = C->node_note_array(); 374 if (_old_node_note_array != nullptr) { 375 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*> 376 (C->comp_arena(), _old_node_note_array->length(), 377 0, nullptr)); 378 } 379 380 // Pre-size the new_node table to avoid the need for range checks. 381 grow_new_node_array(C->unique()); 382 383 // Reset node counter so MachNodes start with _idx at 0 384 int live_nodes = C->live_nodes(); 385 C->set_unique(0); 386 C->reset_dead_node_list(); 387 388 // Recursively match trees from old space into new space. 389 // Correct leaves of new-space Nodes; they point to old-space. 390 _visited.clear(); 391 Node* const n = xform(C->top(), live_nodes); 392 if (C->failing()) return; 393 C->set_cached_top_node(n); 394 if (!C->failing()) { 395 Node* xroot = xform( C->root(), 1 ); 396 if (C->failing()) return; 397 if (xroot == nullptr) { 398 Matcher::soft_match_failure(); // recursive matching process failed 399 assert(false, "instruction match failed"); 400 C->record_method_not_compilable("instruction match failed"); 401 } else { 402 // During matching shared constants were attached to C->root() 403 // because xroot wasn't available yet, so transfer the uses to 404 // the xroot. 405 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) { 406 Node* n = C->root()->fast_out(j); 407 if (C->node_arena()->contains(n)) { 408 assert(n->in(0) == C->root(), "should be control user"); 409 n->set_req(0, xroot); 410 --j; 411 --jmax; 412 } 413 } 414 415 // Generate new mach node for ConP #null 416 assert(new_ideal_null != nullptr, "sanity"); 417 _mach_null = match_tree(new_ideal_null); 418 // Don't set control, it will confuse GCM since there are no uses. 419 // The control will be set when this node is used first time 420 // in find_base_for_derived(). 421 assert(_mach_null != nullptr, ""); 422 423 C->set_root(xroot->is_Root() ? xroot->as_Root() : nullptr); 424 425 #ifdef ASSERT 426 verify_new_nodes_only(xroot); 427 #endif 428 } 429 } 430 if (C->top() == nullptr || C->root() == nullptr) { 431 // New graph lost. This is due to a compilation failure we encountered earlier. 432 stringStream ss; 433 if (C->failure_reason() != nullptr) { 434 ss.print("graph lost: %s", C->failure_reason()); 435 } else { 436 assert(C->failure_reason() != nullptr, "graph lost: reason unknown"); 437 ss.print("graph lost: reason unknown"); 438 } 439 C->record_method_not_compilable(ss.as_string()); 440 } 441 if (C->failing()) { 442 // delete old; 443 old->destruct_contents(); 444 return; 445 } 446 assert( C->top(), "" ); 447 assert( C->root(), "" ); 448 validate_null_checks(); 449 450 // Now smoke old-space 451 NOT_DEBUG( old->destruct_contents() ); 452 453 // ------------------------ 454 // Set up save-on-entry registers. 455 Fixup_Save_On_Entry( ); 456 457 { // Cleanup mach IR after selection phase is over. 458 Compile::TracePhase tp("postselect_cleanup", &timers[_t_postselect_cleanup]); 459 do_postselect_cleanup(); 460 if (C->failing()) return; 461 assert(verify_after_postselect_cleanup(), ""); 462 } 463 } 464 465 //------------------------------Fixup_Save_On_Entry---------------------------- 466 // The stated purpose of this routine is to take care of save-on-entry 467 // registers. However, the overall goal of the Match phase is to convert into 468 // machine-specific instructions which have RegMasks to guide allocation. 469 // So what this procedure really does is put a valid RegMask on each input 470 // to the machine-specific variations of all Return, TailCall and Halt 471 // instructions. It also adds edgs to define the save-on-entry values (and of 472 // course gives them a mask). 473 474 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) { 475 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size ); 476 // Do all the pre-defined register masks 477 rms[TypeFunc::Control ] = RegMask::Empty; 478 rms[TypeFunc::I_O ] = RegMask::Empty; 479 rms[TypeFunc::Memory ] = RegMask::Empty; 480 rms[TypeFunc::ReturnAdr] = ret_adr; 481 rms[TypeFunc::FramePtr ] = fp; 482 return rms; 483 } 484 485 int Matcher::scalable_predicate_reg_slots() { 486 assert(Matcher::has_predicated_vectors() && Matcher::supports_scalable_vector(), 487 "scalable predicate vector should be supported"); 488 int vector_reg_bit_size = Matcher::scalable_vector_reg_size(T_BYTE) << LogBitsPerByte; 489 // We assume each predicate register is one-eighth of the size of 490 // scalable vector register, one mask bit per vector byte. 491 int predicate_reg_bit_size = vector_reg_bit_size >> 3; 492 // Compute number of slots which is required when scalable predicate 493 // register is spilled. E.g. if scalable vector register is 640 bits, 494 // predicate register is 80 bits, which is 2.5 * slots. 495 // We will round up the slot number to power of 2, which is required 496 // by find_first_set(). 497 int slots = predicate_reg_bit_size & (BitsPerInt - 1) 498 ? (predicate_reg_bit_size >> LogBitsPerInt) + 1 499 : predicate_reg_bit_size >> LogBitsPerInt; 500 return round_up_power_of_2(slots); 501 } 502 503 #define NOF_STACK_MASKS (3*13) 504 505 // Create the initial stack mask used by values spilling to the stack. 506 // Disallow any debug info in outgoing argument areas by setting the 507 // initial mask accordingly. 508 void Matcher::init_first_stack_mask() { 509 510 // Allocate storage for spill masks as masks for the appropriate load type. 511 RegMask *rms = (RegMask*)C->comp_arena()->AmallocWords(sizeof(RegMask) * NOF_STACK_MASKS); 512 513 // Initialize empty placeholder masks into the newly allocated arena 514 for (int i = 0; i < NOF_STACK_MASKS; i++) { 515 new (rms + i) RegMask(); 516 } 517 518 idealreg2spillmask [Op_RegN] = &rms[0]; 519 idealreg2spillmask [Op_RegI] = &rms[1]; 520 idealreg2spillmask [Op_RegL] = &rms[2]; 521 idealreg2spillmask [Op_RegF] = &rms[3]; 522 idealreg2spillmask [Op_RegD] = &rms[4]; 523 idealreg2spillmask [Op_RegP] = &rms[5]; 524 525 idealreg2debugmask [Op_RegN] = &rms[6]; 526 idealreg2debugmask [Op_RegI] = &rms[7]; 527 idealreg2debugmask [Op_RegL] = &rms[8]; 528 idealreg2debugmask [Op_RegF] = &rms[9]; 529 idealreg2debugmask [Op_RegD] = &rms[10]; 530 idealreg2debugmask [Op_RegP] = &rms[11]; 531 532 idealreg2mhdebugmask[Op_RegN] = &rms[12]; 533 idealreg2mhdebugmask[Op_RegI] = &rms[13]; 534 idealreg2mhdebugmask[Op_RegL] = &rms[14]; 535 idealreg2mhdebugmask[Op_RegF] = &rms[15]; 536 idealreg2mhdebugmask[Op_RegD] = &rms[16]; 537 idealreg2mhdebugmask[Op_RegP] = &rms[17]; 538 539 idealreg2spillmask [Op_VecA] = &rms[18]; 540 idealreg2spillmask [Op_VecS] = &rms[19]; 541 idealreg2spillmask [Op_VecD] = &rms[20]; 542 idealreg2spillmask [Op_VecX] = &rms[21]; 543 idealreg2spillmask [Op_VecY] = &rms[22]; 544 idealreg2spillmask [Op_VecZ] = &rms[23]; 545 546 idealreg2debugmask [Op_VecA] = &rms[24]; 547 idealreg2debugmask [Op_VecS] = &rms[25]; 548 idealreg2debugmask [Op_VecD] = &rms[26]; 549 idealreg2debugmask [Op_VecX] = &rms[27]; 550 idealreg2debugmask [Op_VecY] = &rms[28]; 551 idealreg2debugmask [Op_VecZ] = &rms[29]; 552 553 idealreg2mhdebugmask[Op_VecA] = &rms[30]; 554 idealreg2mhdebugmask[Op_VecS] = &rms[31]; 555 idealreg2mhdebugmask[Op_VecD] = &rms[32]; 556 idealreg2mhdebugmask[Op_VecX] = &rms[33]; 557 idealreg2mhdebugmask[Op_VecY] = &rms[34]; 558 idealreg2mhdebugmask[Op_VecZ] = &rms[35]; 559 560 idealreg2spillmask [Op_RegVectMask] = &rms[36]; 561 idealreg2debugmask [Op_RegVectMask] = &rms[37]; 562 idealreg2mhdebugmask[Op_RegVectMask] = &rms[38]; 563 564 OptoReg::Name i; 565 566 // At first, start with the empty mask 567 C->FIRST_STACK_mask().Clear(); 568 569 // Add in the incoming argument area 570 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots()); 571 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) { 572 C->FIRST_STACK_mask().Insert(i); 573 } 574 575 // Add in all bits past the outgoing argument area 576 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)), 577 "must be able to represent all call arguments in reg mask"); 578 OptoReg::Name init = _out_arg_limit; 579 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) { 580 C->FIRST_STACK_mask().Insert(i); 581 } 582 // Finally, set the "infinite stack" bit. 583 C->FIRST_STACK_mask().set_AllStack(); 584 585 // Make spill masks. Registers for their class, plus FIRST_STACK_mask. 586 RegMask aligned_stack_mask = C->FIRST_STACK_mask(); 587 // Keep spill masks aligned. 588 aligned_stack_mask.clear_to_pairs(); 589 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 590 RegMask scalable_stack_mask = aligned_stack_mask; 591 592 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP]; 593 #ifdef _LP64 594 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN]; 595 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask()); 596 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask); 597 #else 598 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask()); 599 #endif 600 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI]; 601 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask()); 602 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL]; 603 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask); 604 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF]; 605 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask()); 606 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD]; 607 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask); 608 609 if (Matcher::has_predicated_vectors()) { 610 *idealreg2spillmask[Op_RegVectMask] = *idealreg2regmask[Op_RegVectMask]; 611 idealreg2spillmask[Op_RegVectMask]->OR(aligned_stack_mask); 612 } else { 613 *idealreg2spillmask[Op_RegVectMask] = RegMask::Empty; 614 } 615 616 if (Matcher::vector_size_supported(T_BYTE,4)) { 617 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS]; 618 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask()); 619 } else { 620 *idealreg2spillmask[Op_VecS] = RegMask::Empty; 621 } 622 623 if (Matcher::vector_size_supported(T_FLOAT,2)) { 624 // For VecD we need dual alignment and 8 bytes (2 slots) for spills. 625 // RA guarantees such alignment since it is needed for Double and Long values. 626 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD]; 627 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask); 628 } else { 629 *idealreg2spillmask[Op_VecD] = RegMask::Empty; 630 } 631 632 if (Matcher::vector_size_supported(T_FLOAT,4)) { 633 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills. 634 // 635 // RA can use input arguments stack slots for spills but until RA 636 // we don't know frame size and offset of input arg stack slots. 637 // 638 // Exclude last input arg stack slots to avoid spilling vectors there 639 // otherwise vector spills could stomp over stack slots in caller frame. 640 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 641 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) { 642 aligned_stack_mask.Remove(in); 643 in = OptoReg::add(in, -1); 644 } 645 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX); 646 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 647 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX]; 648 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask); 649 } else { 650 *idealreg2spillmask[Op_VecX] = RegMask::Empty; 651 } 652 653 if (Matcher::vector_size_supported(T_FLOAT,8)) { 654 // For VecY we need octo alignment and 32 bytes (8 slots) for spills. 655 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 656 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) { 657 aligned_stack_mask.Remove(in); 658 in = OptoReg::add(in, -1); 659 } 660 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY); 661 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 662 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY]; 663 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask); 664 } else { 665 *idealreg2spillmask[Op_VecY] = RegMask::Empty; 666 } 667 668 if (Matcher::vector_size_supported(T_FLOAT,16)) { 669 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills. 670 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 671 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) { 672 aligned_stack_mask.Remove(in); 673 in = OptoReg::add(in, -1); 674 } 675 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ); 676 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack"); 677 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ]; 678 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask); 679 } else { 680 *idealreg2spillmask[Op_VecZ] = RegMask::Empty; 681 } 682 683 if (Matcher::supports_scalable_vector()) { 684 int k = 1; 685 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1); 686 if (Matcher::has_predicated_vectors()) { 687 // Exclude last input arg stack slots to avoid spilling vector register there, 688 // otherwise RegVectMask spills could stomp over stack slots in caller frame. 689 for (; (in >= init_in) && (k < scalable_predicate_reg_slots()); k++) { 690 scalable_stack_mask.Remove(in); 691 in = OptoReg::add(in, -1); 692 } 693 694 // For RegVectMask 695 scalable_stack_mask.clear_to_sets(scalable_predicate_reg_slots()); 696 assert(scalable_stack_mask.is_AllStack(), "should be infinite stack"); 697 *idealreg2spillmask[Op_RegVectMask] = *idealreg2regmask[Op_RegVectMask]; 698 idealreg2spillmask[Op_RegVectMask]->OR(scalable_stack_mask); 699 } 700 701 // Exclude last input arg stack slots to avoid spilling vector register there, 702 // otherwise vector spills could stomp over stack slots in caller frame. 703 for (; (in >= init_in) && (k < scalable_vector_reg_size(T_FLOAT)); k++) { 704 scalable_stack_mask.Remove(in); 705 in = OptoReg::add(in, -1); 706 } 707 708 // For VecA 709 scalable_stack_mask.clear_to_sets(RegMask::SlotsPerVecA); 710 assert(scalable_stack_mask.is_AllStack(), "should be infinite stack"); 711 *idealreg2spillmask[Op_VecA] = *idealreg2regmask[Op_VecA]; 712 idealreg2spillmask[Op_VecA]->OR(scalable_stack_mask); 713 } else { 714 *idealreg2spillmask[Op_VecA] = RegMask::Empty; 715 } 716 717 if (UseFPUForSpilling) { 718 // This mask logic assumes that the spill operations are 719 // symmetric and that the registers involved are the same size. 720 // On sparc for instance we may have to use 64 bit moves will 721 // kill 2 registers when used with F0-F31. 722 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]); 723 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]); 724 #ifdef _LP64 725 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]); 726 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 727 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 728 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]); 729 #else 730 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]); 731 #ifdef ARM 732 // ARM has support for moving 64bit values between a pair of 733 // integer registers and a double register 734 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]); 735 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]); 736 #endif 737 #endif 738 } 739 740 // Make up debug masks. Any spill slot plus callee-save (SOE) registers. 741 // Caller-save (SOC, AS) registers are assumed to be trashable by the various 742 // inline-cache fixup routines. 743 *idealreg2debugmask [Op_RegN] = *idealreg2spillmask[Op_RegN]; 744 *idealreg2debugmask [Op_RegI] = *idealreg2spillmask[Op_RegI]; 745 *idealreg2debugmask [Op_RegL] = *idealreg2spillmask[Op_RegL]; 746 *idealreg2debugmask [Op_RegF] = *idealreg2spillmask[Op_RegF]; 747 *idealreg2debugmask [Op_RegD] = *idealreg2spillmask[Op_RegD]; 748 *idealreg2debugmask [Op_RegP] = *idealreg2spillmask[Op_RegP]; 749 *idealreg2debugmask [Op_RegVectMask] = *idealreg2spillmask[Op_RegVectMask]; 750 751 *idealreg2debugmask [Op_VecA] = *idealreg2spillmask[Op_VecA]; 752 *idealreg2debugmask [Op_VecS] = *idealreg2spillmask[Op_VecS]; 753 *idealreg2debugmask [Op_VecD] = *idealreg2spillmask[Op_VecD]; 754 *idealreg2debugmask [Op_VecX] = *idealreg2spillmask[Op_VecX]; 755 *idealreg2debugmask [Op_VecY] = *idealreg2spillmask[Op_VecY]; 756 *idealreg2debugmask [Op_VecZ] = *idealreg2spillmask[Op_VecZ]; 757 758 *idealreg2mhdebugmask[Op_RegN] = *idealreg2spillmask[Op_RegN]; 759 *idealreg2mhdebugmask[Op_RegI] = *idealreg2spillmask[Op_RegI]; 760 *idealreg2mhdebugmask[Op_RegL] = *idealreg2spillmask[Op_RegL]; 761 *idealreg2mhdebugmask[Op_RegF] = *idealreg2spillmask[Op_RegF]; 762 *idealreg2mhdebugmask[Op_RegD] = *idealreg2spillmask[Op_RegD]; 763 *idealreg2mhdebugmask[Op_RegP] = *idealreg2spillmask[Op_RegP]; 764 *idealreg2mhdebugmask[Op_RegVectMask] = *idealreg2spillmask[Op_RegVectMask]; 765 766 *idealreg2mhdebugmask[Op_VecA] = *idealreg2spillmask[Op_VecA]; 767 *idealreg2mhdebugmask[Op_VecS] = *idealreg2spillmask[Op_VecS]; 768 *idealreg2mhdebugmask[Op_VecD] = *idealreg2spillmask[Op_VecD]; 769 *idealreg2mhdebugmask[Op_VecX] = *idealreg2spillmask[Op_VecX]; 770 *idealreg2mhdebugmask[Op_VecY] = *idealreg2spillmask[Op_VecY]; 771 *idealreg2mhdebugmask[Op_VecZ] = *idealreg2spillmask[Op_VecZ]; 772 773 // Prevent stub compilations from attempting to reference 774 // callee-saved (SOE) registers from debug info 775 bool exclude_soe = !Compile::current()->is_method_compilation(); 776 RegMask* caller_save_mask = exclude_soe ? &caller_save_regmask_exclude_soe : &caller_save_regmask; 777 RegMask* mh_caller_save_mask = exclude_soe ? &mh_caller_save_regmask_exclude_soe : &mh_caller_save_regmask; 778 779 idealreg2debugmask[Op_RegN]->SUBTRACT(*caller_save_mask); 780 idealreg2debugmask[Op_RegI]->SUBTRACT(*caller_save_mask); 781 idealreg2debugmask[Op_RegL]->SUBTRACT(*caller_save_mask); 782 idealreg2debugmask[Op_RegF]->SUBTRACT(*caller_save_mask); 783 idealreg2debugmask[Op_RegD]->SUBTRACT(*caller_save_mask); 784 idealreg2debugmask[Op_RegP]->SUBTRACT(*caller_save_mask); 785 idealreg2debugmask[Op_RegVectMask]->SUBTRACT(*caller_save_mask); 786 787 idealreg2debugmask[Op_VecA]->SUBTRACT(*caller_save_mask); 788 idealreg2debugmask[Op_VecS]->SUBTRACT(*caller_save_mask); 789 idealreg2debugmask[Op_VecD]->SUBTRACT(*caller_save_mask); 790 idealreg2debugmask[Op_VecX]->SUBTRACT(*caller_save_mask); 791 idealreg2debugmask[Op_VecY]->SUBTRACT(*caller_save_mask); 792 idealreg2debugmask[Op_VecZ]->SUBTRACT(*caller_save_mask); 793 794 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(*mh_caller_save_mask); 795 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(*mh_caller_save_mask); 796 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(*mh_caller_save_mask); 797 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(*mh_caller_save_mask); 798 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(*mh_caller_save_mask); 799 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(*mh_caller_save_mask); 800 idealreg2mhdebugmask[Op_RegVectMask]->SUBTRACT(*mh_caller_save_mask); 801 802 idealreg2mhdebugmask[Op_VecA]->SUBTRACT(*mh_caller_save_mask); 803 idealreg2mhdebugmask[Op_VecS]->SUBTRACT(*mh_caller_save_mask); 804 idealreg2mhdebugmask[Op_VecD]->SUBTRACT(*mh_caller_save_mask); 805 idealreg2mhdebugmask[Op_VecX]->SUBTRACT(*mh_caller_save_mask); 806 idealreg2mhdebugmask[Op_VecY]->SUBTRACT(*mh_caller_save_mask); 807 idealreg2mhdebugmask[Op_VecZ]->SUBTRACT(*mh_caller_save_mask); 808 } 809 810 //---------------------------is_save_on_entry---------------------------------- 811 bool Matcher::is_save_on_entry(int reg) { 812 return 813 _register_save_policy[reg] == 'E' || 814 _register_save_policy[reg] == 'A'; // Save-on-entry register? 815 } 816 817 //---------------------------Fixup_Save_On_Entry------------------------------- 818 void Matcher::Fixup_Save_On_Entry( ) { 819 init_first_stack_mask(); 820 821 Node *root = C->root(); // Short name for root 822 // Count number of save-on-entry registers. 823 uint soe_cnt = number_of_saved_registers(); 824 uint i; 825 826 // Find the procedure Start Node 827 StartNode *start = C->start(); 828 assert( start, "Expect a start node" ); 829 830 // Input RegMask array shared by all Returns. 831 // The type for doubles and longs has a count of 2, but 832 // there is only 1 returned value 833 uint ret_edge_cnt = C->tf()->range_cc()->cnt(); 834 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 835 for (i = TypeFunc::Parms; i < ret_edge_cnt; i++) { 836 ret_rms[i] = _return_values_mask[i-TypeFunc::Parms]; 837 } 838 839 // Input RegMask array shared by all Rethrows. 840 uint reth_edge_cnt = TypeFunc::Parms+1; 841 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 842 // Rethrow takes exception oop only, but in the argument 0 slot. 843 OptoReg::Name reg = find_receiver(); 844 if (reg >= 0) { 845 reth_rms[TypeFunc::Parms] = mreg2regmask[reg]; 846 #ifdef _LP64 847 // Need two slots for ptrs in 64-bit land 848 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1)); 849 #endif 850 } 851 852 // Input RegMask array shared by all TailCalls 853 uint tail_call_edge_cnt = TypeFunc::Parms+2; 854 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 855 856 // Input RegMask array shared by all TailJumps 857 uint tail_jump_edge_cnt = TypeFunc::Parms+2; 858 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 859 860 // TailCalls have 2 returned values (target & moop), whose masks come 861 // from the usual MachNode/MachOper mechanism. Find a sample 862 // TailCall to extract these masks and put the correct masks into 863 // the tail_call_rms array. 864 for( i=1; i < root->req(); i++ ) { 865 MachReturnNode *m = root->in(i)->as_MachReturn(); 866 if( m->ideal_Opcode() == Op_TailCall ) { 867 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 868 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 869 break; 870 } 871 } 872 873 // TailJumps have 2 returned values (target & ex_oop), whose masks come 874 // from the usual MachNode/MachOper mechanism. Find a sample 875 // TailJump to extract these masks and put the correct masks into 876 // the tail_jump_rms array. 877 for( i=1; i < root->req(); i++ ) { 878 MachReturnNode *m = root->in(i)->as_MachReturn(); 879 if( m->ideal_Opcode() == Op_TailJump ) { 880 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0); 881 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1); 882 break; 883 } 884 } 885 886 // Input RegMask array shared by all Halts 887 uint halt_edge_cnt = TypeFunc::Parms; 888 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask ); 889 890 // Capture the return input masks into each exit flavor 891 for( i=1; i < root->req(); i++ ) { 892 MachReturnNode *exit = root->in(i)->as_MachReturn(); 893 switch( exit->ideal_Opcode() ) { 894 case Op_Return : exit->_in_rms = ret_rms; break; 895 case Op_Rethrow : exit->_in_rms = reth_rms; break; 896 case Op_TailCall : exit->_in_rms = tail_call_rms; break; 897 case Op_TailJump : exit->_in_rms = tail_jump_rms; break; 898 case Op_Halt : exit->_in_rms = halt_rms; break; 899 default : ShouldNotReachHere(); 900 } 901 } 902 903 // Next unused projection number from Start. 904 int proj_cnt = C->tf()->domain_cc()->cnt(); 905 906 // Do all the save-on-entry registers. Make projections from Start for 907 // them, and give them a use at the exit points. To the allocator, they 908 // look like incoming register arguments. 909 for( i = 0; i < _last_Mach_Reg; i++ ) { 910 if( is_save_on_entry(i) ) { 911 912 // Add the save-on-entry to the mask array 913 ret_rms [ ret_edge_cnt] = mreg2regmask[i]; 914 reth_rms [ reth_edge_cnt] = mreg2regmask[i]; 915 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i]; 916 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i]; 917 // Halts need the SOE registers, but only in the stack as debug info. 918 // A just-prior uncommon-trap or deoptimization will use the SOE regs. 919 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]]; 920 921 Node *mproj; 922 923 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's 924 // into a single RegD. 925 if( (i&1) == 0 && 926 _register_save_type[i ] == Op_RegF && 927 _register_save_type[i+1] == Op_RegF && 928 is_save_on_entry(i+1) ) { 929 // Add other bit for double 930 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 931 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 932 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 933 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 934 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 935 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD ); 936 proj_cnt += 2; // Skip 2 for doubles 937 } 938 else if( (i&1) == 1 && // Else check for high half of double 939 _register_save_type[i-1] == Op_RegF && 940 _register_save_type[i ] == Op_RegF && 941 is_save_on_entry(i-1) ) { 942 ret_rms [ ret_edge_cnt] = RegMask::Empty; 943 reth_rms [ reth_edge_cnt] = RegMask::Empty; 944 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 945 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 946 halt_rms [ halt_edge_cnt] = RegMask::Empty; 947 mproj = C->top(); 948 } 949 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's 950 // into a single RegL. 951 else if( (i&1) == 0 && 952 _register_save_type[i ] == Op_RegI && 953 _register_save_type[i+1] == Op_RegI && 954 is_save_on_entry(i+1) ) { 955 // Add other bit for long 956 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1)); 957 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1)); 958 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1)); 959 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1)); 960 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1)); 961 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL ); 962 proj_cnt += 2; // Skip 2 for longs 963 } 964 else if( (i&1) == 1 && // Else check for high half of long 965 _register_save_type[i-1] == Op_RegI && 966 _register_save_type[i ] == Op_RegI && 967 is_save_on_entry(i-1) ) { 968 ret_rms [ ret_edge_cnt] = RegMask::Empty; 969 reth_rms [ reth_edge_cnt] = RegMask::Empty; 970 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty; 971 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty; 972 halt_rms [ halt_edge_cnt] = RegMask::Empty; 973 mproj = C->top(); 974 } else { 975 // Make a projection for it off the Start 976 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] ); 977 } 978 979 ret_edge_cnt ++; 980 reth_edge_cnt ++; 981 tail_call_edge_cnt ++; 982 tail_jump_edge_cnt ++; 983 halt_edge_cnt ++; 984 985 // Add a use of the SOE register to all exit paths 986 for( uint j=1; j < root->req(); j++ ) 987 root->in(j)->add_req(mproj); 988 } // End of if a save-on-entry register 989 } // End of for all machine registers 990 } 991 992 //------------------------------init_spill_mask-------------------------------- 993 void Matcher::init_spill_mask( Node *ret ) { 994 if( idealreg2regmask[Op_RegI] ) return; // One time only init 995 996 OptoReg::c_frame_pointer = c_frame_pointer(); 997 c_frame_ptr_mask = c_frame_pointer(); 998 #ifdef _LP64 999 // pointers are twice as big 1000 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1)); 1001 #endif 1002 1003 // Start at OptoReg::stack0() 1004 STACK_ONLY_mask.Clear(); 1005 OptoReg::Name init = OptoReg::stack2reg(0); 1006 // STACK_ONLY_mask is all stack bits 1007 OptoReg::Name i; 1008 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) 1009 STACK_ONLY_mask.Insert(i); 1010 // Also set the "infinite stack" bit. 1011 STACK_ONLY_mask.set_AllStack(); 1012 1013 for (i = OptoReg::Name(0); i < OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i, 1)) { 1014 // Copy the register names over into the shared world. 1015 // SharedInfo::regName[i] = regName[i]; 1016 // Handy RegMasks per machine register 1017 mreg2regmask[i].Insert(i); 1018 1019 // Set up regmasks used to exclude save-on-call (and always-save) registers from debug masks. 1020 if (_register_save_policy[i] == 'C' || 1021 _register_save_policy[i] == 'A') { 1022 caller_save_regmask.Insert(i); 1023 mh_caller_save_regmask.Insert(i); 1024 } 1025 // Exclude save-on-entry registers from debug masks for stub compilations. 1026 if (_register_save_policy[i] == 'C' || 1027 _register_save_policy[i] == 'A' || 1028 _register_save_policy[i] == 'E') { 1029 caller_save_regmask_exclude_soe.Insert(i); 1030 mh_caller_save_regmask_exclude_soe.Insert(i); 1031 } 1032 } 1033 1034 // Also exclude the register we use to save the SP for MethodHandle 1035 // invokes to from the corresponding MH debug masks 1036 const RegMask sp_save_mask = method_handle_invoke_SP_save_mask(); 1037 mh_caller_save_regmask.OR(sp_save_mask); 1038 mh_caller_save_regmask_exclude_soe.OR(sp_save_mask); 1039 1040 // Grab the Frame Pointer 1041 Node *fp = ret->in(TypeFunc::FramePtr); 1042 // Share frame pointer while making spill ops 1043 set_shared(fp); 1044 1045 // Get the ADLC notion of the right regmask, for each basic type. 1046 #ifdef _LP64 1047 idealreg2regmask[Op_RegN] = regmask_for_ideal_register(Op_RegN, ret); 1048 #endif 1049 idealreg2regmask[Op_RegI] = regmask_for_ideal_register(Op_RegI, ret); 1050 idealreg2regmask[Op_RegP] = regmask_for_ideal_register(Op_RegP, ret); 1051 idealreg2regmask[Op_RegF] = regmask_for_ideal_register(Op_RegF, ret); 1052 idealreg2regmask[Op_RegD] = regmask_for_ideal_register(Op_RegD, ret); 1053 idealreg2regmask[Op_RegL] = regmask_for_ideal_register(Op_RegL, ret); 1054 idealreg2regmask[Op_VecA] = regmask_for_ideal_register(Op_VecA, ret); 1055 idealreg2regmask[Op_VecS] = regmask_for_ideal_register(Op_VecS, ret); 1056 idealreg2regmask[Op_VecD] = regmask_for_ideal_register(Op_VecD, ret); 1057 idealreg2regmask[Op_VecX] = regmask_for_ideal_register(Op_VecX, ret); 1058 idealreg2regmask[Op_VecY] = regmask_for_ideal_register(Op_VecY, ret); 1059 idealreg2regmask[Op_VecZ] = regmask_for_ideal_register(Op_VecZ, ret); 1060 idealreg2regmask[Op_RegVectMask] = regmask_for_ideal_register(Op_RegVectMask, ret); 1061 } 1062 1063 #ifdef ASSERT 1064 static void match_alias_type(Compile* C, Node* n, Node* m) { 1065 if (!VerifyAliases) return; // do not go looking for trouble by default 1066 const TypePtr* nat = n->adr_type(); 1067 const TypePtr* mat = m->adr_type(); 1068 int nidx = C->get_alias_index(nat); 1069 int midx = C->get_alias_index(mat); 1070 // Detune the assert for cases like (AndI 0xFF (LoadB p)). 1071 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) { 1072 for (uint i = 1; i < n->req(); i++) { 1073 Node* n1 = n->in(i); 1074 const TypePtr* n1at = n1->adr_type(); 1075 if (n1at != nullptr) { 1076 nat = n1at; 1077 nidx = C->get_alias_index(n1at); 1078 } 1079 } 1080 } 1081 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases: 1082 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) { 1083 switch (n->Opcode()) { 1084 case Op_PrefetchAllocation: 1085 nidx = Compile::AliasIdxRaw; 1086 nat = TypeRawPtr::BOTTOM; 1087 break; 1088 } 1089 } 1090 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) { 1091 switch (n->Opcode()) { 1092 case Op_ClearArray: 1093 midx = Compile::AliasIdxRaw; 1094 mat = TypeRawPtr::BOTTOM; 1095 break; 1096 } 1097 } 1098 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) { 1099 switch (n->Opcode()) { 1100 case Op_Return: 1101 case Op_Rethrow: 1102 case Op_Halt: 1103 case Op_TailCall: 1104 case Op_TailJump: 1105 nidx = Compile::AliasIdxBot; 1106 nat = TypePtr::BOTTOM; 1107 break; 1108 } 1109 } 1110 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) { 1111 switch (n->Opcode()) { 1112 case Op_StrComp: 1113 case Op_StrEquals: 1114 case Op_StrIndexOf: 1115 case Op_StrIndexOfChar: 1116 case Op_AryEq: 1117 case Op_VectorizedHashCode: 1118 case Op_CountPositives: 1119 case Op_MemBarVolatile: 1120 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type? 1121 case Op_StrInflatedCopy: 1122 case Op_StrCompressedCopy: 1123 case Op_OnSpinWait: 1124 case Op_EncodeISOArray: 1125 nidx = Compile::AliasIdxTop; 1126 nat = nullptr; 1127 break; 1128 } 1129 } 1130 if (nidx != midx) { 1131 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) { 1132 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx); 1133 n->dump(); 1134 m->dump(); 1135 } 1136 assert(C->subsume_loads() && C->must_alias(nat, midx), 1137 "must not lose alias info when matching"); 1138 } 1139 } 1140 #endif 1141 1142 //------------------------------xform------------------------------------------ 1143 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine 1144 // Node in new-space. Given a new-space Node, recursively walk his children. 1145 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; } 1146 Node *Matcher::xform( Node *n, int max_stack ) { 1147 // Use one stack to keep both: child's node/state and parent's node/index 1148 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2 1149 mstack.push(n, Visit, nullptr, -1); // set null as parent to indicate root 1150 while (mstack.is_nonempty()) { 1151 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions"); 1152 if (C->failing()) return nullptr; 1153 n = mstack.node(); // Leave node on stack 1154 Node_State nstate = mstack.state(); 1155 if (nstate == Visit) { 1156 mstack.set_state(Post_Visit); 1157 Node *oldn = n; 1158 // Old-space or new-space check 1159 if (!C->node_arena()->contains(n)) { 1160 // Old space! 1161 Node* m; 1162 if (has_new_node(n)) { // Not yet Label/Reduced 1163 m = new_node(n); 1164 } else { 1165 if (!is_dontcare(n)) { // Matcher can match this guy 1166 // Calls match special. They match alone with no children. 1167 // Their children, the incoming arguments, match normally. 1168 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n); 1169 if (C->failing()) return nullptr; 1170 if (m == nullptr) { Matcher::soft_match_failure(); return nullptr; } 1171 if (n->is_MemBar()) { 1172 m->as_MachMemBar()->set_adr_type(n->adr_type()); 1173 } 1174 } else { // Nothing the matcher cares about 1175 if (n->is_Proj() && n->in(0) != nullptr && n->in(0)->is_Multi()) { // Projections? 1176 // Convert to machine-dependent projection 1177 RegMask* mask = nullptr; 1178 if (n->in(0)->is_Call() && n->in(0)->as_Call()->tf()->returns_inline_type_as_fields()) { 1179 mask = return_values_mask(n->in(0)->as_Call()->tf()); 1180 } 1181 m = n->in(0)->as_Multi()->match(n->as_Proj(), this, mask); 1182 NOT_PRODUCT(record_new2old(m, n);) 1183 if (m->in(0) != nullptr) // m might be top 1184 collect_null_checks(m, n); 1185 } else { // Else just a regular 'ol guy 1186 m = n->clone(); // So just clone into new-space 1187 NOT_PRODUCT(record_new2old(m, n);) 1188 // Def-Use edges will be added incrementally as Uses 1189 // of this node are matched. 1190 assert(m->outcnt() == 0, "no Uses of this clone yet"); 1191 } 1192 } 1193 1194 set_new_node(n, m); // Map old to new 1195 if (_old_node_note_array != nullptr) { 1196 Node_Notes* nn = C->locate_node_notes(_old_node_note_array, 1197 n->_idx); 1198 C->set_node_notes_at(m->_idx, nn); 1199 } 1200 debug_only(match_alias_type(C, n, m)); 1201 } 1202 n = m; // n is now a new-space node 1203 mstack.set_node(n); 1204 } 1205 1206 // New space! 1207 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty()) 1208 1209 int i; 1210 // Put precedence edges on stack first (match them last). 1211 for (i = oldn->req(); (uint)i < oldn->len(); i++) { 1212 Node *m = oldn->in(i); 1213 if (m == nullptr) break; 1214 // set -1 to call add_prec() instead of set_req() during Step1 1215 mstack.push(m, Visit, n, -1); 1216 } 1217 1218 // Handle precedence edges for interior nodes 1219 for (i = n->len()-1; (uint)i >= n->req(); i--) { 1220 Node *m = n->in(i); 1221 if (m == nullptr || C->node_arena()->contains(m)) continue; 1222 n->rm_prec(i); 1223 // set -1 to call add_prec() instead of set_req() during Step1 1224 mstack.push(m, Visit, n, -1); 1225 } 1226 1227 // For constant debug info, I'd rather have unmatched constants. 1228 int cnt = n->req(); 1229 JVMState* jvms = n->jvms(); 1230 int debug_cnt = jvms ? jvms->debug_start() : cnt; 1231 1232 // Now do only debug info. Clone constants rather than matching. 1233 // Constants are represented directly in the debug info without 1234 // the need for executable machine instructions. 1235 // Monitor boxes are also represented directly. 1236 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do 1237 Node *m = n->in(i); // Get input 1238 int op = m->Opcode(); 1239 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites"); 1240 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass || 1241 op == Op_ConF || op == Op_ConD || op == Op_ConL 1242 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp 1243 ) { 1244 m = m->clone(); 1245 NOT_PRODUCT(record_new2old(m, n)); 1246 mstack.push(m, Post_Visit, n, i); // Don't need to visit 1247 mstack.push(m->in(0), Visit, m, 0); 1248 } else { 1249 mstack.push(m, Visit, n, i); 1250 } 1251 } 1252 1253 // And now walk his children, and convert his inputs to new-space. 1254 for( ; i >= 0; --i ) { // For all normal inputs do 1255 Node *m = n->in(i); // Get input 1256 if(m != nullptr) 1257 mstack.push(m, Visit, n, i); 1258 } 1259 1260 } 1261 else if (nstate == Post_Visit) { 1262 // Set xformed input 1263 Node *p = mstack.parent(); 1264 if (p != nullptr) { // root doesn't have parent 1265 int i = (int)mstack.index(); 1266 if (i >= 0) 1267 p->set_req(i, n); // required input 1268 else if (i == -1) 1269 p->add_prec(n); // precedence input 1270 else 1271 ShouldNotReachHere(); 1272 } 1273 mstack.pop(); // remove processed node from stack 1274 } 1275 else { 1276 ShouldNotReachHere(); 1277 } 1278 } // while (mstack.is_nonempty()) 1279 return n; // Return new-space Node 1280 } 1281 1282 //------------------------------warp_outgoing_stk_arg------------------------ 1283 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) { 1284 // Convert outgoing argument location to a pre-biased stack offset 1285 if (reg->is_stack()) { 1286 OptoReg::Name warped = reg->reg2stack(); 1287 // Adjust the stack slot offset to be the register number used 1288 // by the allocator. 1289 warped = OptoReg::add(begin_out_arg_area, warped); 1290 // Keep track of the largest numbered stack slot used for an arg. 1291 // Largest used slot per call-site indicates the amount of stack 1292 // that is killed by the call. 1293 if( warped >= out_arg_limit_per_call ) 1294 out_arg_limit_per_call = OptoReg::add(warped,1); 1295 if (!RegMask::can_represent_arg(warped)) { 1296 // Bailout. For example not enough space on stack for all arguments. Happens for methods with too many arguments. 1297 C->record_method_not_compilable("unsupported calling sequence"); 1298 return OptoReg::Bad; 1299 } 1300 return warped; 1301 } 1302 return OptoReg::as_OptoReg(reg); 1303 } 1304 1305 1306 //------------------------------match_sfpt------------------------------------- 1307 // Helper function to match call instructions. Calls match special. 1308 // They match alone with no children. Their children, the incoming 1309 // arguments, match normally. 1310 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) { 1311 MachSafePointNode *msfpt = nullptr; 1312 MachCallNode *mcall = nullptr; 1313 uint cnt; 1314 // Split out case for SafePoint vs Call 1315 CallNode *call; 1316 const TypeTuple *domain; 1317 ciMethod* method = nullptr; 1318 bool is_method_handle_invoke = false; // for special kill effects 1319 if( sfpt->is_Call() ) { 1320 call = sfpt->as_Call(); 1321 domain = call->tf()->domain_cc(); 1322 cnt = domain->cnt(); 1323 1324 // Match just the call, nothing else 1325 MachNode *m = match_tree(call); 1326 if (C->failing()) return nullptr; 1327 if( m == nullptr ) { Matcher::soft_match_failure(); return nullptr; } 1328 1329 // Copy data from the Ideal SafePoint to the machine version 1330 mcall = m->as_MachCall(); 1331 1332 mcall->set_tf( call->tf()); 1333 mcall->set_entry_point( call->entry_point()); 1334 mcall->set_cnt( call->cnt()); 1335 mcall->set_guaranteed_safepoint(call->guaranteed_safepoint()); 1336 1337 if( mcall->is_MachCallJava() ) { 1338 MachCallJavaNode *mcall_java = mcall->as_MachCallJava(); 1339 const CallJavaNode *call_java = call->as_CallJava(); 1340 assert(call_java->validate_symbolic_info(), "inconsistent info"); 1341 method = call_java->method(); 1342 mcall_java->_method = method; 1343 mcall_java->_optimized_virtual = call_java->is_optimized_virtual(); 1344 is_method_handle_invoke = call_java->is_method_handle_invoke(); 1345 mcall_java->_method_handle_invoke = is_method_handle_invoke; 1346 mcall_java->_override_symbolic_info = call_java->override_symbolic_info(); 1347 mcall_java->_arg_escape = call_java->arg_escape(); 1348 if (is_method_handle_invoke) { 1349 C->set_has_method_handle_invokes(true); 1350 } 1351 if( mcall_java->is_MachCallStaticJava() ) 1352 mcall_java->as_MachCallStaticJava()->_name = 1353 call_java->as_CallStaticJava()->_name; 1354 if( mcall_java->is_MachCallDynamicJava() ) 1355 mcall_java->as_MachCallDynamicJava()->_vtable_index = 1356 call_java->as_CallDynamicJava()->_vtable_index; 1357 } 1358 else if( mcall->is_MachCallRuntime() ) { 1359 MachCallRuntimeNode* mach_call_rt = mcall->as_MachCallRuntime(); 1360 mach_call_rt->_name = call->as_CallRuntime()->_name; 1361 mach_call_rt->_leaf_no_fp = call->is_CallLeafNoFP(); 1362 } 1363 msfpt = mcall; 1364 } 1365 // This is a non-call safepoint 1366 else { 1367 call = nullptr; 1368 domain = nullptr; 1369 MachNode *mn = match_tree(sfpt); 1370 if (C->failing()) return nullptr; 1371 msfpt = mn->as_MachSafePoint(); 1372 cnt = TypeFunc::Parms; 1373 } 1374 msfpt->_has_ea_local_in_scope = sfpt->has_ea_local_in_scope(); 1375 1376 // Advertise the correct memory effects (for anti-dependence computation). 1377 msfpt->set_adr_type(sfpt->adr_type()); 1378 1379 // Allocate a private array of RegMasks. These RegMasks are not shared. 1380 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt ); 1381 // Empty them all. 1382 for (uint i = 0; i < cnt; i++) ::new (&(msfpt->_in_rms[i])) RegMask(); 1383 1384 // Do all the pre-defined non-Empty register masks 1385 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask; 1386 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask; 1387 1388 // Place first outgoing argument can possibly be put. 1389 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots()); 1390 assert( is_even(begin_out_arg_area), "" ); 1391 // Compute max outgoing register number per call site. 1392 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area; 1393 // Calls to C may hammer extra stack slots above and beyond any arguments. 1394 // These are usually backing store for register arguments for varargs. 1395 if( call != nullptr && call->is_CallRuntime() ) 1396 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed()); 1397 1398 1399 // Do the normal argument list (parameters) register masks 1400 // Null entry point is a special cast where the target of the call 1401 // is in a register. 1402 int adj = (call != nullptr && call->entry_point() == nullptr) ? 1 : 0; 1403 int argcnt = cnt - TypeFunc::Parms - adj; 1404 if( argcnt > 0 ) { // Skip it all if we have no args 1405 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt ); 1406 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt ); 1407 int i; 1408 for( i = 0; i < argcnt; i++ ) { 1409 sig_bt[i] = domain->field_at(i+TypeFunc::Parms+adj)->basic_type(); 1410 } 1411 // V-call to pick proper calling convention 1412 call->calling_convention( sig_bt, parm_regs, argcnt ); 1413 1414 #ifdef ASSERT 1415 // Sanity check users' calling convention. Really handy during 1416 // the initial porting effort. Fairly expensive otherwise. 1417 { for (int i = 0; i<argcnt; i++) { 1418 if( !parm_regs[i].first()->is_valid() && 1419 !parm_regs[i].second()->is_valid() ) continue; 1420 VMReg reg1 = parm_regs[i].first(); 1421 VMReg reg2 = parm_regs[i].second(); 1422 for (int j = 0; j < i; j++) { 1423 if( !parm_regs[j].first()->is_valid() && 1424 !parm_regs[j].second()->is_valid() ) continue; 1425 VMReg reg3 = parm_regs[j].first(); 1426 VMReg reg4 = parm_regs[j].second(); 1427 if( !reg1->is_valid() ) { 1428 assert( !reg2->is_valid(), "valid halvsies" ); 1429 } else if( !reg3->is_valid() ) { 1430 assert( !reg4->is_valid(), "valid halvsies" ); 1431 } else { 1432 assert( reg1 != reg2, "calling conv. must produce distinct regs"); 1433 assert( reg1 != reg3, "calling conv. must produce distinct regs"); 1434 assert( reg1 != reg4, "calling conv. must produce distinct regs"); 1435 assert( reg2 != reg3, "calling conv. must produce distinct regs"); 1436 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs"); 1437 assert( reg3 != reg4, "calling conv. must produce distinct regs"); 1438 } 1439 } 1440 } 1441 } 1442 #endif 1443 1444 // Visit each argument. Compute its outgoing register mask. 1445 // Return results now can have 2 bits returned. 1446 // Compute max over all outgoing arguments both per call-site 1447 // and over the entire method. 1448 for( i = 0; i < argcnt; i++ ) { 1449 // Address of incoming argument mask to fill in 1450 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms+adj]; 1451 VMReg first = parm_regs[i].first(); 1452 VMReg second = parm_regs[i].second(); 1453 if(!first->is_valid() && 1454 !second->is_valid()) { 1455 continue; // Avoid Halves 1456 } 1457 // Handle case where arguments are in vector registers. 1458 if(call->in(TypeFunc::Parms + i)->bottom_type()->isa_vect()) { 1459 OptoReg::Name reg_fst = OptoReg::as_OptoReg(first); 1460 OptoReg::Name reg_snd = OptoReg::as_OptoReg(second); 1461 assert (reg_fst <= reg_snd, "fst=%d snd=%d", reg_fst, reg_snd); 1462 for (OptoReg::Name r = reg_fst; r <= reg_snd; r++) { 1463 rm->Insert(r); 1464 } 1465 } 1466 // Grab first register, adjust stack slots and insert in mask. 1467 OptoReg::Name reg1 = warp_outgoing_stk_arg(first, begin_out_arg_area, out_arg_limit_per_call ); 1468 if (OptoReg::is_valid(reg1)) { 1469 rm->Insert( reg1 ); 1470 } 1471 // Grab second register (if any), adjust stack slots and insert in mask. 1472 OptoReg::Name reg2 = warp_outgoing_stk_arg(second, begin_out_arg_area, out_arg_limit_per_call ); 1473 if (OptoReg::is_valid(reg2)) { 1474 rm->Insert( reg2 ); 1475 } 1476 } // End of for all arguments 1477 } 1478 1479 // Compute the max stack slot killed by any call. These will not be 1480 // available for debug info, and will be used to adjust FIRST_STACK_mask 1481 // after all call sites have been visited. 1482 if( _out_arg_limit < out_arg_limit_per_call) 1483 _out_arg_limit = out_arg_limit_per_call; 1484 1485 if (mcall) { 1486 // Kill the outgoing argument area, including any non-argument holes and 1487 // any legacy C-killed slots. Use Fat-Projections to do the killing. 1488 // Since the max-per-method covers the max-per-call-site and debug info 1489 // is excluded on the max-per-method basis, debug info cannot land in 1490 // this killed area. 1491 uint r_cnt = mcall->tf()->range_sig()->cnt(); 1492 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj ); 1493 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) { 1494 // Bailout. We do not have space to represent all arguments. 1495 C->record_method_not_compilable("unsupported outgoing calling sequence"); 1496 } else { 1497 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++) 1498 proj->_rout.Insert(OptoReg::Name(i)); 1499 } 1500 if (proj->_rout.is_NotEmpty()) { 1501 push_projection(proj); 1502 } 1503 } 1504 // Transfer the safepoint information from the call to the mcall 1505 // Move the JVMState list 1506 msfpt->set_jvms(sfpt->jvms()); 1507 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) { 1508 jvms->set_map(sfpt); 1509 } 1510 1511 // Debug inputs begin just after the last incoming parameter 1512 assert((mcall == nullptr) || (mcall->jvms() == nullptr) || 1513 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain_cc()->cnt()), ""); 1514 1515 // Add additional edges. 1516 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) { 1517 // For these calls we can not add MachConstantBase in expand(), as the 1518 // ins are not complete then. 1519 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node()); 1520 if (msfpt->jvms() && 1521 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) { 1522 // We added an edge before jvms, so we must adapt the position of the ins. 1523 msfpt->jvms()->adapt_position(+1); 1524 } 1525 } 1526 1527 // Registers killed by the call are set in the local scheduling pass 1528 // of Global Code Motion. 1529 return msfpt; 1530 } 1531 1532 //---------------------------match_tree---------------------------------------- 1533 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part 1534 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for 1535 // making GotoNodes while building the CFG and in init_spill_mask() to identify 1536 // a Load's result RegMask for memoization in idealreg2regmask[] 1537 MachNode *Matcher::match_tree( const Node *n ) { 1538 assert( n->Opcode() != Op_Phi, "cannot match" ); 1539 assert( !n->is_block_start(), "cannot match" ); 1540 // Set the mark for all locally allocated State objects. 1541 // When this call returns, the _states_arena arena will be reset 1542 // freeing all State objects. 1543 ResourceMark rm( &_states_arena ); 1544 1545 LabelRootDepth = 0; 1546 1547 // StoreNodes require their Memory input to match any LoadNodes 1548 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ; 1549 #ifdef ASSERT 1550 Node* save_mem_node = _mem_node; 1551 _mem_node = n->is_Store() ? (Node*)n : nullptr; 1552 #endif 1553 // State object for root node of match tree 1554 // Allocate it on _states_arena - stack allocation can cause stack overflow. 1555 State *s = new (&_states_arena) State; 1556 s->_kids[0] = nullptr; 1557 s->_kids[1] = nullptr; 1558 s->_leaf = (Node*)n; 1559 // Label the input tree, allocating labels from top-level arena 1560 Node* root_mem = mem; 1561 Label_Root(n, s, n->in(0), root_mem); 1562 if (C->failing()) return nullptr; 1563 1564 // The minimum cost match for the whole tree is found at the root State 1565 uint mincost = max_juint; 1566 uint cost = max_juint; 1567 uint i; 1568 for (i = 0; i < NUM_OPERANDS; i++) { 1569 if (s->valid(i) && // valid entry and 1570 s->cost(i) < cost && // low cost and 1571 s->rule(i) >= NUM_OPERANDS) {// not an operand 1572 mincost = i; 1573 cost = s->cost(i); 1574 } 1575 } 1576 if (mincost == max_juint) { 1577 #ifndef PRODUCT 1578 tty->print("No matching rule for:"); 1579 s->dump(); 1580 #endif 1581 Matcher::soft_match_failure(); 1582 return nullptr; 1583 } 1584 // Reduce input tree based upon the state labels to machine Nodes 1585 MachNode *m = ReduceInst(s, s->rule(mincost), mem); 1586 // New-to-old mapping is done in ReduceInst, to cover complex instructions. 1587 NOT_PRODUCT(_old2new_map.map(n->_idx, m);) 1588 1589 // Add any Matcher-ignored edges 1590 uint cnt = n->req(); 1591 uint start = 1; 1592 if( mem != (Node*)1 ) start = MemNode::Memory+1; 1593 if( n->is_AddP() ) { 1594 assert( mem == (Node*)1, "" ); 1595 start = AddPNode::Base+1; 1596 } 1597 for( i = start; i < cnt; i++ ) { 1598 if( !n->match_edge(i) ) { 1599 if( i < m->req() ) 1600 m->ins_req( i, n->in(i) ); 1601 else 1602 m->add_req( n->in(i) ); 1603 } 1604 } 1605 1606 debug_only( _mem_node = save_mem_node; ) 1607 return m; 1608 } 1609 1610 1611 //------------------------------match_into_reg--------------------------------- 1612 // Choose to either match this Node in a register or part of the current 1613 // match tree. Return true for requiring a register and false for matching 1614 // as part of the current match tree. 1615 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) { 1616 1617 const Type *t = m->bottom_type(); 1618 1619 if (t->singleton()) { 1620 // Never force constants into registers. Allow them to match as 1621 // constants or registers. Copies of the same value will share 1622 // the same register. See find_shared_node. 1623 return false; 1624 } else { // Not a constant 1625 // Stop recursion if they have different Controls. 1626 Node* m_control = m->in(0); 1627 // Control of load's memory can post-dominates load's control. 1628 // So use it since load can't float above its memory. 1629 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : nullptr; 1630 if (control && m_control && control != m_control && control != mem_control) { 1631 1632 // Actually, we can live with the most conservative control we 1633 // find, if it post-dominates the others. This allows us to 1634 // pick up load/op/store trees where the load can float a little 1635 // above the store. 1636 Node *x = control; 1637 const uint max_scan = 6; // Arbitrary scan cutoff 1638 uint j; 1639 for (j=0; j<max_scan; j++) { 1640 if (x->is_Region()) // Bail out at merge points 1641 return true; 1642 x = x->in(0); 1643 if (x == m_control) // Does 'control' post-dominate 1644 break; // m->in(0)? If so, we can use it 1645 if (x == mem_control) // Does 'control' post-dominate 1646 break; // mem_control? If so, we can use it 1647 } 1648 if (j == max_scan) // No post-domination before scan end? 1649 return true; // Then break the match tree up 1650 } 1651 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) || 1652 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) { 1653 // These are commonly used in address expressions and can 1654 // efficiently fold into them on X64 in some cases. 1655 return false; 1656 } 1657 } 1658 1659 // Not forceable cloning. If shared, put it into a register. 1660 return shared; 1661 } 1662 1663 1664 //------------------------------Instruction Selection-------------------------- 1665 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match 1666 // ideal nodes to machine instructions. Trees are delimited by shared Nodes, 1667 // things the Matcher does not match (e.g., Memory), and things with different 1668 // Controls (hence forced into different blocks). We pass in the Control 1669 // selected for this entire State tree. 1670 1671 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the 1672 // Store and the Load must have identical Memories (as well as identical 1673 // pointers). Since the Matcher does not have anything for Memory (and 1674 // does not handle DAGs), I have to match the Memory input myself. If the 1675 // Tree root is a Store or if there are multiple Loads in the tree, I require 1676 // all Loads to have the identical memory. 1677 Node* Matcher::Label_Root(const Node* n, State* svec, Node* control, Node*& mem) { 1678 // Since Label_Root is a recursive function, its possible that we might run 1679 // out of stack space. See bugs 6272980 & 6227033 for more info. 1680 LabelRootDepth++; 1681 if (LabelRootDepth > MaxLabelRootDepth) { 1682 // Bailout. Can for example be hit with a deep chain of operations. 1683 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth"); 1684 return nullptr; 1685 } 1686 uint care = 0; // Edges matcher cares about 1687 uint cnt = n->req(); 1688 uint i = 0; 1689 1690 // Examine children for memory state 1691 // Can only subsume a child into your match-tree if that child's memory state 1692 // is not modified along the path to another input. 1693 // It is unsafe even if the other inputs are separate roots. 1694 Node *input_mem = nullptr; 1695 for( i = 1; i < cnt; i++ ) { 1696 if( !n->match_edge(i) ) continue; 1697 Node *m = n->in(i); // Get ith input 1698 assert( m, "expect non-null children" ); 1699 if( m->is_Load() ) { 1700 if( input_mem == nullptr ) { 1701 input_mem = m->in(MemNode::Memory); 1702 if (mem == (Node*)1) { 1703 // Save this memory to bail out if there's another memory access 1704 // to a different memory location in the same tree. 1705 mem = input_mem; 1706 } 1707 } else if( input_mem != m->in(MemNode::Memory) ) { 1708 input_mem = NodeSentinel; 1709 } 1710 } 1711 } 1712 1713 for( i = 1; i < cnt; i++ ){// For my children 1714 if( !n->match_edge(i) ) continue; 1715 Node *m = n->in(i); // Get ith input 1716 // Allocate states out of a private arena 1717 State *s = new (&_states_arena) State; 1718 svec->_kids[care++] = s; 1719 assert( care <= 2, "binary only for now" ); 1720 1721 // Recursively label the State tree. 1722 s->_kids[0] = nullptr; 1723 s->_kids[1] = nullptr; 1724 s->_leaf = m; 1725 1726 // Check for leaves of the State Tree; things that cannot be a part of 1727 // the current tree. If it finds any, that value is matched as a 1728 // register operand. If not, then the normal matching is used. 1729 if( match_into_reg(n, m, control, i, is_shared(m)) || 1730 // Stop recursion if this is a LoadNode and there is another memory access 1731 // to a different memory location in the same tree (for example, a StoreNode 1732 // at the root of this tree or another LoadNode in one of the children). 1733 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) || 1734 // Can NOT include the match of a subtree when its memory state 1735 // is used by any of the other subtrees 1736 (input_mem == NodeSentinel) ) { 1737 // Print when we exclude matching due to different memory states at input-loads 1738 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel) 1739 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) { 1740 tty->print_cr("invalid input_mem"); 1741 } 1742 // Switch to a register-only opcode; this value must be in a register 1743 // and cannot be subsumed as part of a larger instruction. 1744 s->DFA( m->ideal_reg(), m ); 1745 1746 } else { 1747 // If match tree has no control and we do, adopt it for entire tree 1748 if( control == nullptr && m->in(0) != nullptr && m->req() > 1 ) 1749 control = m->in(0); // Pick up control 1750 // Else match as a normal part of the match tree. 1751 control = Label_Root(m, s, control, mem); 1752 if (C->failing()) return nullptr; 1753 } 1754 } 1755 1756 // Call DFA to match this node, and return 1757 svec->DFA( n->Opcode(), n ); 1758 1759 #ifdef ASSERT 1760 uint x; 1761 for( x = 0; x < _LAST_MACH_OPER; x++ ) 1762 if( svec->valid(x) ) 1763 break; 1764 1765 if (x >= _LAST_MACH_OPER) { 1766 n->dump(); 1767 svec->dump(); 1768 assert( false, "bad AD file" ); 1769 } 1770 #endif 1771 return control; 1772 } 1773 1774 1775 // Con nodes reduced using the same rule can share their MachNode 1776 // which reduces the number of copies of a constant in the final 1777 // program. The register allocator is free to split uses later to 1778 // split live ranges. 1779 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) { 1780 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return nullptr; 1781 1782 // See if this Con has already been reduced using this rule. 1783 if (_shared_nodes.max() <= leaf->_idx) return nullptr; 1784 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx); 1785 if (last != nullptr && rule == last->rule()) { 1786 // Don't expect control change for DecodeN 1787 if (leaf->is_DecodeNarrowPtr()) 1788 return last; 1789 // Get the new space root. 1790 Node* xroot = new_node(C->root()); 1791 if (xroot == nullptr) { 1792 // This shouldn't happen give the order of matching. 1793 return nullptr; 1794 } 1795 1796 // Shared constants need to have their control be root so they 1797 // can be scheduled properly. 1798 Node* control = last->in(0); 1799 if (control != xroot) { 1800 if (control == nullptr || control == C->root()) { 1801 last->set_req(0, xroot); 1802 } else { 1803 assert(false, "unexpected control"); 1804 return nullptr; 1805 } 1806 } 1807 return last; 1808 } 1809 return nullptr; 1810 } 1811 1812 1813 //------------------------------ReduceInst------------------------------------- 1814 // Reduce a State tree (with given Control) into a tree of MachNodes. 1815 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into 1816 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes. 1817 // Each MachNode has a number of complicated MachOper operands; each 1818 // MachOper also covers a further tree of Ideal Nodes. 1819 1820 // The root of the Ideal match tree is always an instruction, so we enter 1821 // the recursion here. After building the MachNode, we need to recurse 1822 // the tree checking for these cases: 1823 // (1) Child is an instruction - 1824 // Build the instruction (recursively), add it as an edge. 1825 // Build a simple operand (register) to hold the result of the instruction. 1826 // (2) Child is an interior part of an instruction - 1827 // Skip over it (do nothing) 1828 // (3) Child is the start of a operand - 1829 // Build the operand, place it inside the instruction 1830 // Call ReduceOper. 1831 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) { 1832 assert( rule >= NUM_OPERANDS, "called with operand rule" ); 1833 1834 MachNode* shared_node = find_shared_node(s->_leaf, rule); 1835 if (shared_node != nullptr) { 1836 return shared_node; 1837 } 1838 1839 // Build the object to represent this state & prepare for recursive calls 1840 MachNode *mach = s->MachNodeGenerator(rule); 1841 guarantee(mach != nullptr, "Missing MachNode"); 1842 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]); 1843 assert( mach->_opnds[0] != nullptr, "Missing result operand" ); 1844 Node *leaf = s->_leaf; 1845 NOT_PRODUCT(record_new2old(mach, leaf);) 1846 // Check for instruction or instruction chain rule 1847 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) { 1848 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf), 1849 "duplicating node that's already been matched"); 1850 // Instruction 1851 mach->add_req( leaf->in(0) ); // Set initial control 1852 // Reduce interior of complex instruction 1853 ReduceInst_Interior( s, rule, mem, mach, 1 ); 1854 } else { 1855 // Instruction chain rules are data-dependent on their inputs 1856 mach->add_req(0); // Set initial control to none 1857 ReduceInst_Chain_Rule( s, rule, mem, mach ); 1858 } 1859 1860 // If a Memory was used, insert a Memory edge 1861 if( mem != (Node*)1 ) { 1862 mach->ins_req(MemNode::Memory,mem); 1863 #ifdef ASSERT 1864 // Verify adr type after matching memory operation 1865 const MachOper* oper = mach->memory_operand(); 1866 if (oper != nullptr && oper != (MachOper*)-1) { 1867 // It has a unique memory operand. Find corresponding ideal mem node. 1868 Node* m = nullptr; 1869 if (leaf->is_Mem()) { 1870 m = leaf; 1871 } else { 1872 m = _mem_node; 1873 assert(m != nullptr && m->is_Mem(), "expecting memory node"); 1874 } 1875 const Type* mach_at = mach->adr_type(); 1876 // DecodeN node consumed by an address may have different type 1877 // than its input. Don't compare types for such case. 1878 if (m->adr_type() != mach_at && 1879 (m->in(MemNode::Address)->is_DecodeNarrowPtr() || 1880 (m->in(MemNode::Address)->is_AddP() && 1881 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) || 1882 (m->in(MemNode::Address)->is_AddP() && 1883 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() && 1884 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) { 1885 mach_at = m->adr_type(); 1886 } 1887 if (m->adr_type() != mach_at) { 1888 m->dump(); 1889 tty->print_cr("mach:"); 1890 mach->dump(1); 1891 } 1892 assert(m->adr_type() == mach_at, "matcher should not change adr type"); 1893 } 1894 #endif 1895 } 1896 1897 // If the _leaf is an AddP, insert the base edge 1898 if (leaf->is_AddP()) { 1899 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base)); 1900 } 1901 1902 uint number_of_projections_prior = number_of_projections(); 1903 1904 // Perform any 1-to-many expansions required 1905 MachNode *ex = mach->Expand(s, _projection_list, mem); 1906 if (ex != mach) { 1907 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match"); 1908 if( ex->in(1)->is_Con() ) 1909 ex->in(1)->set_req(0, C->root()); 1910 // Remove old node from the graph 1911 for( uint i=0; i<mach->req(); i++ ) { 1912 mach->set_req(i,nullptr); 1913 } 1914 NOT_PRODUCT(record_new2old(ex, s->_leaf);) 1915 } 1916 1917 // PhaseChaitin::fixup_spills will sometimes generate spill code 1918 // via the matcher. By the time, nodes have been wired into the CFG, 1919 // and any further nodes generated by expand rules will be left hanging 1920 // in space, and will not get emitted as output code. Catch this. 1921 // Also, catch any new register allocation constraints ("projections") 1922 // generated belatedly during spill code generation. 1923 if (_allocation_started) { 1924 guarantee(ex == mach, "no expand rules during spill generation"); 1925 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation"); 1926 } 1927 1928 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) { 1929 // Record the con for sharing 1930 _shared_nodes.map(leaf->_idx, ex); 1931 } 1932 1933 // Have mach nodes inherit GC barrier data 1934 if (leaf->is_LoadStore()) { 1935 mach->set_barrier_data(leaf->as_LoadStore()->barrier_data()); 1936 } else if (leaf->is_Mem()) { 1937 mach->set_barrier_data(leaf->as_Mem()->barrier_data()); 1938 } 1939 1940 return ex; 1941 } 1942 1943 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) { 1944 for (uint i = n->req(); i < n->len(); i++) { 1945 if (n->in(i) != nullptr) { 1946 mach->add_prec(n->in(i)); 1947 } 1948 } 1949 } 1950 1951 void Matcher::ReduceInst_Chain_Rule(State* s, int rule, Node* &mem, MachNode* mach) { 1952 // 'op' is what I am expecting to receive 1953 int op = _leftOp[rule]; 1954 // Operand type to catch childs result 1955 // This is what my child will give me. 1956 unsigned int opnd_class_instance = s->rule(op); 1957 // Choose between operand class or not. 1958 // This is what I will receive. 1959 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op; 1960 // New rule for child. Chase operand classes to get the actual rule. 1961 unsigned int newrule = s->rule(catch_op); 1962 1963 if (newrule < NUM_OPERANDS) { 1964 // Chain from operand or operand class, may be output of shared node 1965 assert(opnd_class_instance < NUM_OPERANDS, "Bad AD file: Instruction chain rule must chain from operand"); 1966 // Insert operand into array of operands for this instruction 1967 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance); 1968 1969 ReduceOper(s, newrule, mem, mach); 1970 } else { 1971 // Chain from the result of an instruction 1972 assert(newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand"); 1973 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]); 1974 Node *mem1 = (Node*)1; 1975 debug_only(Node *save_mem_node = _mem_node;) 1976 mach->add_req( ReduceInst(s, newrule, mem1) ); 1977 debug_only(_mem_node = save_mem_node;) 1978 } 1979 return; 1980 } 1981 1982 1983 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) { 1984 handle_precedence_edges(s->_leaf, mach); 1985 1986 if( s->_leaf->is_Load() ) { 1987 Node *mem2 = s->_leaf->in(MemNode::Memory); 1988 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" ); 1989 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;) 1990 mem = mem2; 1991 } 1992 if( s->_leaf->in(0) != nullptr && s->_leaf->req() > 1) { 1993 if( mach->in(0) == nullptr ) 1994 mach->set_req(0, s->_leaf->in(0)); 1995 } 1996 1997 // Now recursively walk the state tree & add operand list. 1998 for( uint i=0; i<2; i++ ) { // binary tree 1999 State *newstate = s->_kids[i]; 2000 if( newstate == nullptr ) break; // Might only have 1 child 2001 // 'op' is what I am expecting to receive 2002 int op; 2003 if( i == 0 ) { 2004 op = _leftOp[rule]; 2005 } else { 2006 op = _rightOp[rule]; 2007 } 2008 // Operand type to catch childs result 2009 // This is what my child will give me. 2010 int opnd_class_instance = newstate->rule(op); 2011 // Choose between operand class or not. 2012 // This is what I will receive. 2013 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op; 2014 // New rule for child. Chase operand classes to get the actual rule. 2015 int newrule = newstate->rule(catch_op); 2016 2017 if (newrule < NUM_OPERANDS) { // Operand/operandClass or internalOp/instruction? 2018 // Operand/operandClass 2019 // Insert operand into array of operands for this instruction 2020 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance); 2021 ReduceOper(newstate, newrule, mem, mach); 2022 2023 } else { // Child is internal operand or new instruction 2024 if (newrule < _LAST_MACH_OPER) { // internal operand or instruction? 2025 // internal operand --> call ReduceInst_Interior 2026 // Interior of complex instruction. Do nothing but recurse. 2027 num_opnds = ReduceInst_Interior(newstate, newrule, mem, mach, num_opnds); 2028 } else { 2029 // instruction --> call build operand( ) to catch result 2030 // --> ReduceInst( newrule ) 2031 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]); 2032 Node *mem1 = (Node*)1; 2033 debug_only(Node *save_mem_node = _mem_node;) 2034 mach->add_req( ReduceInst( newstate, newrule, mem1 ) ); 2035 debug_only(_mem_node = save_mem_node;) 2036 } 2037 } 2038 assert( mach->_opnds[num_opnds-1], "" ); 2039 } 2040 return num_opnds; 2041 } 2042 2043 // This routine walks the interior of possible complex operands. 2044 // At each point we check our children in the match tree: 2045 // (1) No children - 2046 // We are a leaf; add _leaf field as an input to the MachNode 2047 // (2) Child is an internal operand - 2048 // Skip over it ( do nothing ) 2049 // (3) Child is an instruction - 2050 // Call ReduceInst recursively and 2051 // and instruction as an input to the MachNode 2052 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) { 2053 assert( rule < _LAST_MACH_OPER, "called with operand rule" ); 2054 State *kid = s->_kids[0]; 2055 assert( kid == nullptr || s->_leaf->in(0) == nullptr, "internal operands have no control" ); 2056 2057 // Leaf? And not subsumed? 2058 if( kid == nullptr && !_swallowed[rule] ) { 2059 mach->add_req( s->_leaf ); // Add leaf pointer 2060 return; // Bail out 2061 } 2062 2063 if( s->_leaf->is_Load() ) { 2064 assert( mem == (Node*)1, "multiple Memories being matched at once?" ); 2065 mem = s->_leaf->in(MemNode::Memory); 2066 debug_only(_mem_node = s->_leaf;) 2067 } 2068 2069 handle_precedence_edges(s->_leaf, mach); 2070 2071 if( s->_leaf->in(0) && s->_leaf->req() > 1) { 2072 if( !mach->in(0) ) 2073 mach->set_req(0,s->_leaf->in(0)); 2074 else { 2075 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" ); 2076 } 2077 } 2078 2079 for (uint i = 0; kid != nullptr && i < 2; kid = s->_kids[1], i++) { // binary tree 2080 int newrule; 2081 if( i == 0) { 2082 newrule = kid->rule(_leftOp[rule]); 2083 } else { 2084 newrule = kid->rule(_rightOp[rule]); 2085 } 2086 2087 if (newrule < _LAST_MACH_OPER) { // Operand or instruction? 2088 // Internal operand; recurse but do nothing else 2089 ReduceOper(kid, newrule, mem, mach); 2090 2091 } else { // Child is a new instruction 2092 // Reduce the instruction, and add a direct pointer from this 2093 // machine instruction to the newly reduced one. 2094 Node *mem1 = (Node*)1; 2095 debug_only(Node *save_mem_node = _mem_node;) 2096 mach->add_req( ReduceInst( kid, newrule, mem1 ) ); 2097 debug_only(_mem_node = save_mem_node;) 2098 } 2099 } 2100 } 2101 2102 2103 // ------------------------------------------------------------------------- 2104 // Java-Java calling convention 2105 // (what you use when Java calls Java) 2106 2107 //------------------------------find_receiver---------------------------------- 2108 // For a given signature, return the OptoReg for parameter 0. 2109 OptoReg::Name Matcher::find_receiver() { 2110 VMRegPair regs; 2111 BasicType sig_bt = T_OBJECT; 2112 SharedRuntime::java_calling_convention(&sig_bt, ®s, 1); 2113 // Return argument 0 register. In the LP64 build pointers 2114 // take 2 registers, but the VM wants only the 'main' name. 2115 return OptoReg::as_OptoReg(regs.first()); 2116 } 2117 2118 bool Matcher::is_vshift_con_pattern(Node* n, Node* m) { 2119 if (n != nullptr && m != nullptr) { 2120 return VectorNode::is_vector_shift(n) && 2121 VectorNode::is_vector_shift_count(m) && m->in(1)->is_Con(); 2122 } 2123 return false; 2124 } 2125 2126 bool Matcher::clone_node(Node* n, Node* m, Matcher::MStack& mstack) { 2127 // Must clone all producers of flags, or we will not match correctly. 2128 // Suppose a compare setting int-flags is shared (e.g., a switch-tree) 2129 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags 2130 // are also there, so we may match a float-branch to int-flags and 2131 // expect the allocator to haul the flags from the int-side to the 2132 // fp-side. No can do. 2133 if (_must_clone[m->Opcode()]) { 2134 mstack.push(m, Visit); 2135 return true; 2136 } 2137 return pd_clone_node(n, m, mstack); 2138 } 2139 2140 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) { 2141 Node *off = m->in(AddPNode::Offset); 2142 if (off->is_Con()) { 2143 address_visited.test_set(m->_idx); // Flag as address_visited 2144 mstack.push(m->in(AddPNode::Address), Pre_Visit); 2145 // Clone X+offset as it also folds into most addressing expressions 2146 mstack.push(off, Visit); 2147 mstack.push(m->in(AddPNode::Base), Pre_Visit); 2148 return true; 2149 } 2150 return false; 2151 } 2152 2153 // A method-klass-holder may be passed in the inline_cache_reg 2154 // and then expanded into the inline_cache_reg and a method_ptr register 2155 // defined in ad_<arch>.cpp 2156 2157 //------------------------------find_shared------------------------------------ 2158 // Set bits if Node is shared or otherwise a root 2159 void Matcher::find_shared(Node* n) { 2160 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc 2161 MStack mstack(C->live_nodes() * 2); 2162 // Mark nodes as address_visited if they are inputs to an address expression 2163 VectorSet address_visited; 2164 mstack.push(n, Visit); // Don't need to pre-visit root node 2165 while (mstack.is_nonempty()) { 2166 n = mstack.node(); // Leave node on stack 2167 Node_State nstate = mstack.state(); 2168 uint nop = n->Opcode(); 2169 if (nstate == Pre_Visit) { 2170 if (address_visited.test(n->_idx)) { // Visited in address already? 2171 // Flag as visited and shared now. 2172 set_visited(n); 2173 } 2174 if (is_visited(n)) { // Visited already? 2175 // Node is shared and has no reason to clone. Flag it as shared. 2176 // This causes it to match into a register for the sharing. 2177 set_shared(n); // Flag as shared and 2178 if (n->is_DecodeNarrowPtr()) { 2179 // Oop field/array element loads must be shared but since 2180 // they are shared through a DecodeN they may appear to have 2181 // a single use so force sharing here. 2182 set_shared(n->in(1)); 2183 } 2184 mstack.pop(); // remove node from stack 2185 continue; 2186 } 2187 nstate = Visit; // Not already visited; so visit now 2188 } 2189 if (nstate == Visit) { 2190 mstack.set_state(Post_Visit); 2191 set_visited(n); // Flag as visited now 2192 bool mem_op = false; 2193 int mem_addr_idx = MemNode::Address; 2194 if (find_shared_visit(mstack, n, nop, mem_op, mem_addr_idx)) { 2195 continue; 2196 } 2197 for (int i = n->len() - 1; i >= 0; --i) { // For my children 2198 Node* m = n->in(i); // Get ith input 2199 if (m == nullptr) { 2200 continue; // Ignore nulls 2201 } 2202 if (clone_node(n, m, mstack)) { 2203 continue; 2204 } 2205 2206 // Clone addressing expressions as they are "free" in memory access instructions 2207 if (mem_op && i == mem_addr_idx && m->is_AddP() && 2208 // When there are other uses besides address expressions 2209 // put it on stack and mark as shared. 2210 !is_visited(m)) { 2211 // Some inputs for address expression are not put on stack 2212 // to avoid marking them as shared and forcing them into register 2213 // if they are used only in address expressions. 2214 // But they should be marked as shared if there are other uses 2215 // besides address expressions. 2216 2217 if (pd_clone_address_expressions(m->as_AddP(), mstack, address_visited)) { 2218 continue; 2219 } 2220 } // if( mem_op && 2221 mstack.push(m, Pre_Visit); 2222 } // for(int i = ...) 2223 } 2224 else if (nstate == Alt_Post_Visit) { 2225 mstack.pop(); // Remove node from stack 2226 // We cannot remove the Cmp input from the Bool here, as the Bool may be 2227 // shared and all users of the Bool need to move the Cmp in parallel. 2228 // This leaves both the Bool and the If pointing at the Cmp. To 2229 // prevent the Matcher from trying to Match the Cmp along both paths 2230 // BoolNode::match_edge always returns a zero. 2231 2232 // We reorder the Op_If in a pre-order manner, so we can visit without 2233 // accidentally sharing the Cmp (the Bool and the If make 2 users). 2234 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool 2235 } 2236 else if (nstate == Post_Visit) { 2237 mstack.pop(); // Remove node from stack 2238 2239 // Now hack a few special opcodes 2240 uint opcode = n->Opcode(); 2241 bool gc_handled = BarrierSet::barrier_set()->barrier_set_c2()->matcher_find_shared_post_visit(this, n, opcode); 2242 if (!gc_handled) { 2243 find_shared_post_visit(n, opcode); 2244 } 2245 } 2246 else { 2247 ShouldNotReachHere(); 2248 } 2249 } // end of while (mstack.is_nonempty()) 2250 } 2251 2252 bool Matcher::find_shared_visit(MStack& mstack, Node* n, uint opcode, bool& mem_op, int& mem_addr_idx) { 2253 switch(opcode) { // Handle some opcodes special 2254 case Op_Phi: // Treat Phis as shared roots 2255 case Op_Parm: 2256 case Op_Proj: // All handled specially during matching 2257 case Op_SafePointScalarObject: 2258 set_shared(n); 2259 set_dontcare(n); 2260 break; 2261 case Op_If: 2262 case Op_CountedLoopEnd: 2263 mstack.set_state(Alt_Post_Visit); // Alternative way 2264 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps 2265 // with matching cmp/branch in 1 instruction. The Matcher needs the 2266 // Bool and CmpX side-by-side, because it can only get at constants 2267 // that are at the leaves of Match trees, and the Bool's condition acts 2268 // as a constant here. 2269 mstack.push(n->in(1), Visit); // Clone the Bool 2270 mstack.push(n->in(0), Pre_Visit); // Visit control input 2271 return true; // while (mstack.is_nonempty()) 2272 case Op_ConvI2D: // These forms efficiently match with a prior 2273 case Op_ConvI2F: // Load but not a following Store 2274 if( n->in(1)->is_Load() && // Prior load 2275 n->outcnt() == 1 && // Not already shared 2276 n->unique_out()->is_Store() ) // Following store 2277 set_shared(n); // Force it to be a root 2278 break; 2279 case Op_ReverseBytesI: 2280 case Op_ReverseBytesL: 2281 if( n->in(1)->is_Load() && // Prior load 2282 n->outcnt() == 1 ) // Not already shared 2283 set_shared(n); // Force it to be a root 2284 break; 2285 case Op_BoxLock: // Can't match until we get stack-regs in ADLC 2286 case Op_IfFalse: 2287 case Op_IfTrue: 2288 case Op_MachProj: 2289 case Op_MergeMem: 2290 case Op_Catch: 2291 case Op_CatchProj: 2292 case Op_CProj: 2293 case Op_JumpProj: 2294 case Op_JProj: 2295 case Op_NeverBranch: 2296 set_dontcare(n); 2297 break; 2298 case Op_Jump: 2299 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared) 2300 mstack.push(n->in(0), Pre_Visit); // Visit Control input 2301 return true; // while (mstack.is_nonempty()) 2302 case Op_StrComp: 2303 case Op_StrEquals: 2304 case Op_StrIndexOf: 2305 case Op_StrIndexOfChar: 2306 case Op_AryEq: 2307 case Op_VectorizedHashCode: 2308 case Op_CountPositives: 2309 case Op_StrInflatedCopy: 2310 case Op_StrCompressedCopy: 2311 case Op_EncodeISOArray: 2312 case Op_FmaD: 2313 case Op_FmaF: 2314 case Op_FmaVD: 2315 case Op_FmaVF: 2316 case Op_MacroLogicV: 2317 case Op_VectorCmpMasked: 2318 case Op_CompressV: 2319 case Op_CompressM: 2320 case Op_ExpandV: 2321 case Op_VectorLoadMask: 2322 set_shared(n); // Force result into register (it will be anyways) 2323 break; 2324 case Op_ConP: { // Convert pointers above the centerline to NUL 2325 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 2326 const TypePtr* tp = tn->type()->is_ptr(); 2327 if (tp->_ptr == TypePtr::AnyNull) { 2328 tn->set_type(TypePtr::NULL_PTR); 2329 } 2330 break; 2331 } 2332 case Op_ConN: { // Convert narrow pointers above the centerline to NUL 2333 TypeNode *tn = n->as_Type(); // Constants derive from type nodes 2334 const TypePtr* tp = tn->type()->make_ptr(); 2335 if (tp && tp->_ptr == TypePtr::AnyNull) { 2336 tn->set_type(TypeNarrowOop::NULL_PTR); 2337 } 2338 break; 2339 } 2340 case Op_Binary: // These are introduced in the Post_Visit state. 2341 ShouldNotReachHere(); 2342 break; 2343 case Op_ClearArray: 2344 case Op_SafePoint: 2345 mem_op = true; 2346 break; 2347 default: 2348 if( n->is_Store() ) { 2349 // Do match stores, despite no ideal reg 2350 mem_op = true; 2351 break; 2352 } 2353 if( n->is_Mem() ) { // Loads and LoadStores 2354 mem_op = true; 2355 // Loads must be root of match tree due to prior load conflict 2356 if( C->subsume_loads() == false ) 2357 set_shared(n); 2358 } 2359 // Fall into default case 2360 if( !n->ideal_reg() ) 2361 set_dontcare(n); // Unmatchable Nodes 2362 } // end_switch 2363 return false; 2364 } 2365 2366 void Matcher::find_shared_post_visit(Node* n, uint opcode) { 2367 if (n->is_predicated_vector()) { 2368 // Restructure into binary trees for Matching. 2369 if (n->req() == 4) { 2370 n->set_req(1, new BinaryNode(n->in(1), n->in(2))); 2371 n->set_req(2, n->in(3)); 2372 n->del_req(3); 2373 } else if (n->req() == 5) { 2374 n->set_req(1, new BinaryNode(n->in(1), n->in(2))); 2375 n->set_req(2, new BinaryNode(n->in(3), n->in(4))); 2376 n->del_req(4); 2377 n->del_req(3); 2378 } else if (n->req() == 6) { 2379 Node* b3 = new BinaryNode(n->in(4), n->in(5)); 2380 Node* b2 = new BinaryNode(n->in(3), b3); 2381 Node* b1 = new BinaryNode(n->in(2), b2); 2382 n->set_req(2, b1); 2383 n->del_req(5); 2384 n->del_req(4); 2385 n->del_req(3); 2386 } 2387 return; 2388 } 2389 2390 switch(opcode) { // Handle some opcodes special 2391 case Op_CompareAndExchangeB: 2392 case Op_CompareAndExchangeS: 2393 case Op_CompareAndExchangeI: 2394 case Op_CompareAndExchangeL: 2395 case Op_CompareAndExchangeP: 2396 case Op_CompareAndExchangeN: 2397 case Op_WeakCompareAndSwapB: 2398 case Op_WeakCompareAndSwapS: 2399 case Op_WeakCompareAndSwapI: 2400 case Op_WeakCompareAndSwapL: 2401 case Op_WeakCompareAndSwapP: 2402 case Op_WeakCompareAndSwapN: 2403 case Op_CompareAndSwapB: 2404 case Op_CompareAndSwapS: 2405 case Op_CompareAndSwapI: 2406 case Op_CompareAndSwapL: 2407 case Op_CompareAndSwapP: 2408 case Op_CompareAndSwapN: { // Convert trinary to binary-tree 2409 Node* newval = n->in(MemNode::ValueIn); 2410 Node* oldval = n->in(LoadStoreConditionalNode::ExpectedIn); 2411 Node* pair = new BinaryNode(oldval, newval); 2412 n->set_req(MemNode::ValueIn, pair); 2413 n->del_req(LoadStoreConditionalNode::ExpectedIn); 2414 break; 2415 } 2416 case Op_CMoveD: // Convert trinary to binary-tree 2417 case Op_CMoveF: 2418 case Op_CMoveI: 2419 case Op_CMoveL: 2420 case Op_CMoveN: 2421 case Op_CMoveP: { 2422 // Restructure into a binary tree for Matching. It's possible that 2423 // we could move this code up next to the graph reshaping for IfNodes 2424 // or vice-versa, but I do not want to debug this for Ladybird. 2425 // 10/2/2000 CNC. 2426 Node* pair1 = new BinaryNode(n->in(1), n->in(1)->in(1)); 2427 n->set_req(1, pair1); 2428 Node* pair2 = new BinaryNode(n->in(2), n->in(3)); 2429 n->set_req(2, pair2); 2430 n->del_req(3); 2431 break; 2432 } 2433 case Op_MacroLogicV: { 2434 Node* pair1 = new BinaryNode(n->in(1), n->in(2)); 2435 Node* pair2 = new BinaryNode(n->in(3), n->in(4)); 2436 n->set_req(1, pair1); 2437 n->set_req(2, pair2); 2438 n->del_req(4); 2439 n->del_req(3); 2440 break; 2441 } 2442 case Op_StoreVectorMasked: { 2443 Node* pair = new BinaryNode(n->in(3), n->in(4)); 2444 n->set_req(3, pair); 2445 n->del_req(4); 2446 break; 2447 } 2448 case Op_LoopLimit: { 2449 Node* pair1 = new BinaryNode(n->in(1), n->in(2)); 2450 n->set_req(1, pair1); 2451 n->set_req(2, n->in(3)); 2452 n->del_req(3); 2453 break; 2454 } 2455 case Op_StrEquals: 2456 case Op_StrIndexOfChar: { 2457 Node* pair1 = new BinaryNode(n->in(2), n->in(3)); 2458 n->set_req(2, pair1); 2459 n->set_req(3, n->in(4)); 2460 n->del_req(4); 2461 break; 2462 } 2463 case Op_StrComp: 2464 case Op_StrIndexOf: 2465 case Op_VectorizedHashCode: { 2466 Node* pair1 = new BinaryNode(n->in(2), n->in(3)); 2467 n->set_req(2, pair1); 2468 Node* pair2 = new BinaryNode(n->in(4),n->in(5)); 2469 n->set_req(3, pair2); 2470 n->del_req(5); 2471 n->del_req(4); 2472 break; 2473 } 2474 case Op_EncodeISOArray: 2475 case Op_StrCompressedCopy: 2476 case Op_StrInflatedCopy: { 2477 // Restructure into a binary tree for Matching. 2478 Node* pair = new BinaryNode(n->in(3), n->in(4)); 2479 n->set_req(3, pair); 2480 n->del_req(4); 2481 break; 2482 } 2483 case Op_FmaD: 2484 case Op_FmaF: 2485 case Op_FmaVD: 2486 case Op_FmaVF: { 2487 // Restructure into a binary tree for Matching. 2488 Node* pair = new BinaryNode(n->in(1), n->in(2)); 2489 n->set_req(2, pair); 2490 n->set_req(1, n->in(3)); 2491 n->del_req(3); 2492 break; 2493 } 2494 case Op_MulAddS2I: { 2495 Node* pair1 = new BinaryNode(n->in(1), n->in(2)); 2496 Node* pair2 = new BinaryNode(n->in(3), n->in(4)); 2497 n->set_req(1, pair1); 2498 n->set_req(2, pair2); 2499 n->del_req(4); 2500 n->del_req(3); 2501 break; 2502 } 2503 case Op_ClearArray: { 2504 Node* pair = new BinaryNode(n->in(2), n->in(3)); 2505 n->set_req(2, pair); 2506 n->set_req(3, n->in(4)); 2507 n->del_req(4); 2508 break; 2509 } 2510 case Op_VectorCmpMasked: 2511 case Op_CopySignD: 2512 case Op_SignumVF: 2513 case Op_SignumVD: 2514 case Op_SignumF: 2515 case Op_SignumD: { 2516 Node* pair = new BinaryNode(n->in(2), n->in(3)); 2517 n->set_req(2, pair); 2518 n->del_req(3); 2519 break; 2520 } 2521 case Op_VectorBlend: 2522 case Op_VectorInsert: { 2523 Node* pair = new BinaryNode(n->in(1), n->in(2)); 2524 n->set_req(1, pair); 2525 n->set_req(2, n->in(3)); 2526 n->del_req(3); 2527 break; 2528 } 2529 case Op_LoadVectorGatherMasked: 2530 case Op_StoreVectorScatter: { 2531 Node* pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1)); 2532 n->set_req(MemNode::ValueIn, pair); 2533 n->del_req(MemNode::ValueIn+1); 2534 break; 2535 } 2536 case Op_StoreVectorScatterMasked: { 2537 Node* pair = new BinaryNode(n->in(MemNode::ValueIn+1), n->in(MemNode::ValueIn+2)); 2538 n->set_req(MemNode::ValueIn+1, pair); 2539 n->del_req(MemNode::ValueIn+2); 2540 pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1)); 2541 n->set_req(MemNode::ValueIn, pair); 2542 n->del_req(MemNode::ValueIn+1); 2543 break; 2544 } 2545 case Op_VectorMaskCmp: { 2546 n->set_req(1, new BinaryNode(n->in(1), n->in(2))); 2547 n->set_req(2, n->in(3)); 2548 n->del_req(3); 2549 break; 2550 } 2551 default: 2552 break; 2553 } 2554 } 2555 2556 #ifndef PRODUCT 2557 void Matcher::record_new2old(Node* newn, Node* old) { 2558 _new2old_map.map(newn->_idx, old); 2559 if (!_reused.test_set(old->_igv_idx)) { 2560 // Reuse the Ideal-level IGV identifier so that the node can be tracked 2561 // across matching. If there are multiple machine nodes expanded from the 2562 // same Ideal node, only one will reuse its IGV identifier. 2563 newn->_igv_idx = old->_igv_idx; 2564 } 2565 } 2566 2567 // machine-independent root to machine-dependent root 2568 void Matcher::dump_old2new_map() { 2569 _old2new_map.dump(); 2570 } 2571 #endif // !PRODUCT 2572 2573 //---------------------------collect_null_checks------------------------------- 2574 // Find null checks in the ideal graph; write a machine-specific node for 2575 // it. Used by later implicit-null-check handling. Actually collects 2576 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal 2577 // value being tested. 2578 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) { 2579 Node *iff = proj->in(0); 2580 if( iff->Opcode() == Op_If ) { 2581 // During matching If's have Bool & Cmp side-by-side 2582 BoolNode *b = iff->in(1)->as_Bool(); 2583 Node *cmp = iff->in(2); 2584 int opc = cmp->Opcode(); 2585 if (opc != Op_CmpP && opc != Op_CmpN) return; 2586 2587 const Type* ct = cmp->in(2)->bottom_type(); 2588 if (ct == TypePtr::NULL_PTR || 2589 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) { 2590 2591 bool push_it = false; 2592 if( proj->Opcode() == Op_IfTrue ) { 2593 #ifndef PRODUCT 2594 extern uint all_null_checks_found; 2595 all_null_checks_found++; 2596 #endif 2597 if( b->_test._test == BoolTest::ne ) { 2598 push_it = true; 2599 } 2600 } else { 2601 assert( proj->Opcode() == Op_IfFalse, "" ); 2602 if( b->_test._test == BoolTest::eq ) { 2603 push_it = true; 2604 } 2605 } 2606 if( push_it ) { 2607 _null_check_tests.push(proj); 2608 Node* val = cmp->in(1); 2609 #ifdef _LP64 2610 if (val->bottom_type()->isa_narrowoop() && 2611 !Matcher::narrow_oop_use_complex_address()) { 2612 // 2613 // Look for DecodeN node which should be pinned to orig_proj. 2614 // On platforms (Sparc) which can not handle 2 adds 2615 // in addressing mode we have to keep a DecodeN node and 2616 // use it to do implicit null check in address. 2617 // 2618 // DecodeN node was pinned to non-null path (orig_proj) during 2619 // CastPP transformation in final_graph_reshaping_impl(). 2620 // 2621 uint cnt = orig_proj->outcnt(); 2622 for (uint i = 0; i < orig_proj->outcnt(); i++) { 2623 Node* d = orig_proj->raw_out(i); 2624 if (d->is_DecodeN() && d->in(1) == val) { 2625 val = d; 2626 val->set_req(0, nullptr); // Unpin now. 2627 // Mark this as special case to distinguish from 2628 // a regular case: CmpP(DecodeN, null). 2629 val = (Node*)(((intptr_t)val) | 1); 2630 break; 2631 } 2632 } 2633 } 2634 #endif 2635 _null_check_tests.push(val); 2636 } 2637 } 2638 } 2639 } 2640 2641 //---------------------------validate_null_checks------------------------------ 2642 // Its possible that the value being null checked is not the root of a match 2643 // tree. If so, I cannot use the value in an implicit null check. 2644 void Matcher::validate_null_checks( ) { 2645 uint cnt = _null_check_tests.size(); 2646 for( uint i=0; i < cnt; i+=2 ) { 2647 Node *test = _null_check_tests[i]; 2648 Node *val = _null_check_tests[i+1]; 2649 bool is_decoden = ((intptr_t)val) & 1; 2650 val = (Node*)(((intptr_t)val) & ~1); 2651 if (has_new_node(val)) { 2652 Node* new_val = new_node(val); 2653 if (is_decoden) { 2654 assert(val->is_DecodeNarrowPtr() && val->in(0) == nullptr, "sanity"); 2655 // Note: new_val may have a control edge if 2656 // the original ideal node DecodeN was matched before 2657 // it was unpinned in Matcher::collect_null_checks(). 2658 // Unpin the mach node and mark it. 2659 new_val->set_req(0, nullptr); 2660 new_val = (Node*)(((intptr_t)new_val) | 1); 2661 } 2662 // Is a match-tree root, so replace with the matched value 2663 _null_check_tests.map(i+1, new_val); 2664 } else { 2665 // Yank from candidate list 2666 _null_check_tests.map(i+1,_null_check_tests[--cnt]); 2667 _null_check_tests.map(i,_null_check_tests[--cnt]); 2668 _null_check_tests.pop(); 2669 _null_check_tests.pop(); 2670 i-=2; 2671 } 2672 } 2673 } 2674 2675 bool Matcher::gen_narrow_oop_implicit_null_checks() { 2676 // Advice matcher to perform null checks on the narrow oop side. 2677 // Implicit checks are not possible on the uncompressed oop side anyway 2678 // (at least not for read accesses). 2679 // Performs significantly better (especially on Power 6). 2680 if (!os::zero_page_read_protected()) { 2681 return true; 2682 } 2683 return CompressedOops::use_implicit_null_checks() && 2684 (narrow_oop_use_complex_address() || 2685 CompressedOops::base() != nullptr); 2686 } 2687 2688 // Compute RegMask for an ideal register. 2689 const RegMask* Matcher::regmask_for_ideal_register(uint ideal_reg, Node* ret) { 2690 const Type* t = Type::mreg2type[ideal_reg]; 2691 if (t == nullptr) { 2692 assert(ideal_reg >= Op_VecA && ideal_reg <= Op_VecZ, "not a vector: %d", ideal_reg); 2693 return nullptr; // not supported 2694 } 2695 Node* fp = ret->in(TypeFunc::FramePtr); 2696 Node* mem = ret->in(TypeFunc::Memory); 2697 const TypePtr* atp = TypePtr::BOTTOM; 2698 MemNode::MemOrd mo = MemNode::unordered; 2699 2700 Node* spill; 2701 switch (ideal_reg) { 2702 case Op_RegN: spill = new LoadNNode(nullptr, mem, fp, atp, t->is_narrowoop(), mo); break; 2703 case Op_RegI: spill = new LoadINode(nullptr, mem, fp, atp, t->is_int(), mo); break; 2704 case Op_RegP: spill = new LoadPNode(nullptr, mem, fp, atp, t->is_ptr(), mo); break; 2705 case Op_RegF: spill = new LoadFNode(nullptr, mem, fp, atp, t, mo); break; 2706 case Op_RegD: spill = new LoadDNode(nullptr, mem, fp, atp, t, mo); break; 2707 case Op_RegL: spill = new LoadLNode(nullptr, mem, fp, atp, t->is_long(), mo); break; 2708 2709 case Op_VecA: // fall-through 2710 case Op_VecS: // fall-through 2711 case Op_VecD: // fall-through 2712 case Op_VecX: // fall-through 2713 case Op_VecY: // fall-through 2714 case Op_VecZ: spill = new LoadVectorNode(nullptr, mem, fp, atp, t->is_vect()); break; 2715 case Op_RegVectMask: return Matcher::predicate_reg_mask(); 2716 2717 default: ShouldNotReachHere(); 2718 } 2719 MachNode* mspill = match_tree(spill); 2720 assert(mspill != nullptr, "matching failed: %d", ideal_reg); 2721 // Handle generic vector operand case 2722 if (Matcher::supports_generic_vector_operands && t->isa_vect()) { 2723 specialize_mach_node(mspill); 2724 } 2725 return &mspill->out_RegMask(); 2726 } 2727 2728 // Process Mach IR right after selection phase is over. 2729 void Matcher::do_postselect_cleanup() { 2730 if (supports_generic_vector_operands) { 2731 specialize_generic_vector_operands(); 2732 if (C->failing()) return; 2733 } 2734 } 2735 2736 //---------------------------------------------------------------------- 2737 // Generic machine operands elision. 2738 //---------------------------------------------------------------------- 2739 2740 // Compute concrete vector operand for a generic TEMP vector mach node based on its user info. 2741 void Matcher::specialize_temp_node(MachTempNode* tmp, MachNode* use, uint idx) { 2742 assert(use->in(idx) == tmp, "not a user"); 2743 assert(!Matcher::is_generic_vector(use->_opnds[0]), "use not processed yet"); 2744 2745 if ((uint)idx == use->two_adr()) { // DEF_TEMP case 2746 tmp->_opnds[0] = use->_opnds[0]->clone(); 2747 } else { 2748 uint ideal_vreg = vector_ideal_reg(C->max_vector_size()); 2749 tmp->_opnds[0] = Matcher::pd_specialize_generic_vector_operand(tmp->_opnds[0], ideal_vreg, true /*is_temp*/); 2750 } 2751 } 2752 2753 // Compute concrete vector operand for a generic DEF/USE vector operand (of mach node m at index idx). 2754 MachOper* Matcher::specialize_vector_operand(MachNode* m, uint opnd_idx) { 2755 assert(Matcher::is_generic_vector(m->_opnds[opnd_idx]), "repeated updates"); 2756 Node* def = nullptr; 2757 if (opnd_idx == 0) { // DEF 2758 def = m; // use mach node itself to compute vector operand type 2759 } else { 2760 int base_idx = m->operand_index(opnd_idx); 2761 def = m->in(base_idx); 2762 if (def->is_Mach()) { 2763 if (def->is_MachTemp() && Matcher::is_generic_vector(def->as_Mach()->_opnds[0])) { 2764 specialize_temp_node(def->as_MachTemp(), m, base_idx); // MachTemp node use site 2765 } else if (is_reg2reg_move(def->as_Mach())) { 2766 def = def->in(1); // skip over generic reg-to-reg moves 2767 } 2768 } 2769 } 2770 assert(def->bottom_type()->isa_vect(), "not a vector"); 2771 uint ideal_vreg = def->bottom_type()->ideal_reg(); 2772 return Matcher::pd_specialize_generic_vector_operand(m->_opnds[opnd_idx], ideal_vreg, false /*is_temp*/); 2773 } 2774 2775 void Matcher::specialize_mach_node(MachNode* m) { 2776 assert(!m->is_MachTemp(), "processed along with its user"); 2777 // For generic use operands pull specific register class operands from 2778 // its def instruction's output operand (def operand). 2779 for (uint i = 0; i < m->num_opnds(); i++) { 2780 if (Matcher::is_generic_vector(m->_opnds[i])) { 2781 m->_opnds[i] = specialize_vector_operand(m, i); 2782 } 2783 } 2784 } 2785 2786 // Replace generic vector operands with concrete vector operands and eliminate generic reg-to-reg moves from the graph. 2787 void Matcher::specialize_generic_vector_operands() { 2788 assert(supports_generic_vector_operands, "sanity"); 2789 ResourceMark rm; 2790 2791 // Replace generic vector operands (vec/legVec) with concrete ones (vec[SDXYZ]/legVec[SDXYZ]) 2792 // and remove reg-to-reg vector moves (MoveVec2Leg and MoveLeg2Vec). 2793 Unique_Node_List live_nodes; 2794 C->identify_useful_nodes(live_nodes); 2795 2796 while (live_nodes.size() > 0) { 2797 MachNode* m = live_nodes.pop()->isa_Mach(); 2798 if (m != nullptr) { 2799 if (Matcher::is_reg2reg_move(m)) { 2800 // Register allocator properly handles vec <=> leg moves using register masks. 2801 int opnd_idx = m->operand_index(1); 2802 Node* def = m->in(opnd_idx); 2803 m->subsume_by(def, C); 2804 } else if (m->is_MachTemp()) { 2805 // process MachTemp nodes at use site (see Matcher::specialize_vector_operand) 2806 } else { 2807 specialize_mach_node(m); 2808 } 2809 } 2810 } 2811 } 2812 2813 uint Matcher::vector_length(const Node* n) { 2814 const TypeVect* vt = n->bottom_type()->is_vect(); 2815 return vt->length(); 2816 } 2817 2818 uint Matcher::vector_length(const MachNode* use, const MachOper* opnd) { 2819 int def_idx = use->operand_index(opnd); 2820 Node* def = use->in(def_idx); 2821 return def->bottom_type()->is_vect()->length(); 2822 } 2823 2824 uint Matcher::vector_length_in_bytes(const Node* n) { 2825 const TypeVect* vt = n->bottom_type()->is_vect(); 2826 return vt->length_in_bytes(); 2827 } 2828 2829 uint Matcher::vector_length_in_bytes(const MachNode* use, const MachOper* opnd) { 2830 uint def_idx = use->operand_index(opnd); 2831 Node* def = use->in(def_idx); 2832 return def->bottom_type()->is_vect()->length_in_bytes(); 2833 } 2834 2835 BasicType Matcher::vector_element_basic_type(const Node* n) { 2836 const TypeVect* vt = n->bottom_type()->is_vect(); 2837 return vt->element_basic_type(); 2838 } 2839 2840 BasicType Matcher::vector_element_basic_type(const MachNode* use, const MachOper* opnd) { 2841 int def_idx = use->operand_index(opnd); 2842 Node* def = use->in(def_idx); 2843 return def->bottom_type()->is_vect()->element_basic_type(); 2844 } 2845 2846 bool Matcher::is_non_long_integral_vector(const Node* n) { 2847 BasicType bt = vector_element_basic_type(n); 2848 assert(bt != T_CHAR, "char is not allowed in vector"); 2849 return is_subword_type(bt) || bt == T_INT; 2850 } 2851 2852 #ifdef ASSERT 2853 bool Matcher::verify_after_postselect_cleanup() { 2854 assert(!C->failing(), "sanity"); 2855 if (supports_generic_vector_operands) { 2856 Unique_Node_List useful; 2857 C->identify_useful_nodes(useful); 2858 for (uint i = 0; i < useful.size(); i++) { 2859 MachNode* m = useful.at(i)->isa_Mach(); 2860 if (m != nullptr) { 2861 assert(!Matcher::is_reg2reg_move(m), "no MoveVec nodes allowed"); 2862 for (uint j = 0; j < m->num_opnds(); j++) { 2863 assert(!Matcher::is_generic_vector(m->_opnds[j]), "no generic vector operands allowed"); 2864 } 2865 } 2866 } 2867 } 2868 return true; 2869 } 2870 #endif // ASSERT 2871 2872 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or 2873 // atomic instruction acting as a store_load barrier without any 2874 // intervening volatile load, and thus we don't need a barrier here. 2875 // We retain the Node to act as a compiler ordering barrier. 2876 bool Matcher::post_store_load_barrier(const Node* vmb) { 2877 Compile* C = Compile::current(); 2878 assert(vmb->is_MemBar(), ""); 2879 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, ""); 2880 const MemBarNode* membar = vmb->as_MemBar(); 2881 2882 // Get the Ideal Proj node, ctrl, that can be used to iterate forward 2883 Node* ctrl = nullptr; 2884 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) { 2885 Node* p = membar->fast_out(i); 2886 assert(p->is_Proj(), "only projections here"); 2887 if ((p->as_Proj()->_con == TypeFunc::Control) && 2888 !C->node_arena()->contains(p)) { // Unmatched old-space only 2889 ctrl = p; 2890 break; 2891 } 2892 } 2893 assert((ctrl != nullptr), "missing control projection"); 2894 2895 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) { 2896 Node *x = ctrl->fast_out(j); 2897 int xop = x->Opcode(); 2898 2899 // We don't need current barrier if we see another or a lock 2900 // before seeing volatile load. 2901 // 2902 // Op_Fastunlock previously appeared in the Op_* list below. 2903 // With the advent of 1-0 lock operations we're no longer guaranteed 2904 // that a monitor exit operation contains a serializing instruction. 2905 2906 if (xop == Op_MemBarVolatile || 2907 xop == Op_CompareAndExchangeB || 2908 xop == Op_CompareAndExchangeS || 2909 xop == Op_CompareAndExchangeI || 2910 xop == Op_CompareAndExchangeL || 2911 xop == Op_CompareAndExchangeP || 2912 xop == Op_CompareAndExchangeN || 2913 xop == Op_WeakCompareAndSwapB || 2914 xop == Op_WeakCompareAndSwapS || 2915 xop == Op_WeakCompareAndSwapL || 2916 xop == Op_WeakCompareAndSwapP || 2917 xop == Op_WeakCompareAndSwapN || 2918 xop == Op_WeakCompareAndSwapI || 2919 xop == Op_CompareAndSwapB || 2920 xop == Op_CompareAndSwapS || 2921 xop == Op_CompareAndSwapL || 2922 xop == Op_CompareAndSwapP || 2923 xop == Op_CompareAndSwapN || 2924 xop == Op_CompareAndSwapI || 2925 BarrierSet::barrier_set()->barrier_set_c2()->matcher_is_store_load_barrier(x, xop)) { 2926 return true; 2927 } 2928 2929 // Op_FastLock previously appeared in the Op_* list above. 2930 if (xop == Op_FastLock) { 2931 return true; 2932 } 2933 2934 if (x->is_MemBar()) { 2935 // We must retain this membar if there is an upcoming volatile 2936 // load, which will be followed by acquire membar. 2937 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) { 2938 return false; 2939 } else { 2940 // For other kinds of barriers, check by pretending we 2941 // are them, and seeing if we can be removed. 2942 return post_store_load_barrier(x->as_MemBar()); 2943 } 2944 } 2945 2946 // probably not necessary to check for these 2947 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) { 2948 return false; 2949 } 2950 } 2951 return false; 2952 } 2953 2954 // Check whether node n is a branch to an uncommon trap that we could 2955 // optimize as test with very high branch costs in case of going to 2956 // the uncommon trap. The code must be able to be recompiled to use 2957 // a cheaper test. 2958 bool Matcher::branches_to_uncommon_trap(const Node *n) { 2959 // Don't do it for natives, adapters, or runtime stubs 2960 Compile *C = Compile::current(); 2961 if (!C->is_method_compilation()) return false; 2962 2963 assert(n->is_If(), "You should only call this on if nodes."); 2964 IfNode *ifn = n->as_If(); 2965 2966 Node *ifFalse = nullptr; 2967 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) { 2968 if (ifn->fast_out(i)->is_IfFalse()) { 2969 ifFalse = ifn->fast_out(i); 2970 break; 2971 } 2972 } 2973 assert(ifFalse, "An If should have an ifFalse. Graph is broken."); 2974 2975 Node *reg = ifFalse; 2976 int cnt = 4; // We must protect against cycles. Limit to 4 iterations. 2977 // Alternatively use visited set? Seems too expensive. 2978 while (reg != nullptr && cnt > 0) { 2979 CallNode *call = nullptr; 2980 RegionNode *nxt_reg = nullptr; 2981 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) { 2982 Node *o = reg->fast_out(i); 2983 if (o->is_Call()) { 2984 call = o->as_Call(); 2985 } 2986 if (o->is_Region()) { 2987 nxt_reg = o->as_Region(); 2988 } 2989 } 2990 2991 if (call && 2992 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) { 2993 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type(); 2994 if (trtype->isa_int() && trtype->is_int()->is_con()) { 2995 jint tr_con = trtype->is_int()->get_con(); 2996 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con); 2997 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con); 2998 assert((int)reason < (int)BitsPerInt, "recode bit map"); 2999 3000 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason) 3001 && action != Deoptimization::Action_none) { 3002 // This uncommon trap is sure to recompile, eventually. 3003 // When that happens, C->too_many_traps will prevent 3004 // this transformation from happening again. 3005 return true; 3006 } 3007 } 3008 } 3009 3010 reg = nxt_reg; 3011 cnt--; 3012 } 3013 3014 return false; 3015 } 3016 3017 //============================================================================= 3018 //---------------------------State--------------------------------------------- 3019 State::State(void) : _rule() { 3020 #ifdef ASSERT 3021 _id = 0; 3022 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 3023 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 3024 #endif 3025 } 3026 3027 #ifdef ASSERT 3028 State::~State() { 3029 _id = 99; 3030 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe); 3031 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d); 3032 memset(_cost, -3, sizeof(_cost)); 3033 memset(_rule, -3, sizeof(_rule)); 3034 } 3035 #endif 3036 3037 #ifndef PRODUCT 3038 //---------------------------dump---------------------------------------------- 3039 void State::dump() { 3040 tty->print("\n"); 3041 dump(0); 3042 } 3043 3044 void State::dump(int depth) { 3045 for (int j = 0; j < depth; j++) { 3046 tty->print(" "); 3047 } 3048 tty->print("--N: "); 3049 _leaf->dump(); 3050 uint i; 3051 for (i = 0; i < _LAST_MACH_OPER; i++) { 3052 // Check for valid entry 3053 if (valid(i)) { 3054 for (int j = 0; j < depth; j++) { 3055 tty->print(" "); 3056 } 3057 assert(cost(i) != max_juint, "cost must be a valid value"); 3058 assert(rule(i) < _last_Mach_Node, "rule[i] must be valid rule"); 3059 tty->print_cr("%s %d %s", 3060 ruleName[i], cost(i), ruleName[rule(i)] ); 3061 } 3062 } 3063 tty->cr(); 3064 3065 for (i = 0; i < 2; i++) { 3066 if (_kids[i]) { 3067 _kids[i]->dump(depth + 1); 3068 } 3069 } 3070 } 3071 #endif