1 /*
   2  * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "gc/shared/barrierSet.hpp"
  27 #include "gc/shared/c2/barrierSetC2.hpp"
  28 #include "memory/allocation.inline.hpp"
  29 #include "memory/resourceArea.hpp"
  30 #include "oops/compressedOops.hpp"
  31 #include "opto/ad.hpp"
  32 #include "opto/addnode.hpp"
  33 #include "opto/callnode.hpp"
  34 #include "opto/idealGraphPrinter.hpp"
  35 #include "opto/matcher.hpp"
  36 #include "opto/memnode.hpp"
  37 #include "opto/movenode.hpp"
  38 #include "opto/opcodes.hpp"
  39 #include "opto/regmask.hpp"
  40 #include "opto/rootnode.hpp"
  41 #include "opto/runtime.hpp"
  42 #include "opto/type.hpp"
  43 #include "opto/vectornode.hpp"
  44 #include "runtime/os.inline.hpp"
  45 #include "runtime/sharedRuntime.hpp"
  46 #include "utilities/align.hpp"
  47 
  48 OptoReg::Name OptoReg::c_frame_pointer;
  49 
  50 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
  51 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
  52 RegMask Matcher::caller_save_regmask;
  53 RegMask Matcher::caller_save_regmask_exclude_soe;
  54 RegMask Matcher::mh_caller_save_regmask;
  55 RegMask Matcher::mh_caller_save_regmask_exclude_soe;
  56 RegMask Matcher::STACK_ONLY_mask;
  57 RegMask Matcher::c_frame_ptr_mask;
  58 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
  59 const uint Matcher::_end_rematerialize   = _END_REMATERIALIZE;
  60 
  61 //---------------------------Matcher-------------------------------------------
  62 Matcher::Matcher()
  63 : PhaseTransform( Phase::Ins_Select ),
  64   _states_arena(Chunk::medium_size, mtCompiler),
  65   _visited(&_states_arena),
  66   _shared(&_states_arena),
  67   _dontcare(&_states_arena),
  68   _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
  69   _swallowed(swallowed),
  70   _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
  71   _end_inst_chain_rule(_END_INST_CHAIN_RULE),
  72   _must_clone(must_clone),
  73   _shared_nodes(C->comp_arena()),
  74 #ifndef PRODUCT
  75   _old2new_map(C->comp_arena()),
  76   _new2old_map(C->comp_arena()),
  77   _reused(C->comp_arena()),
  78 #endif // !PRODUCT
  79   _allocation_started(false),
  80   _ruleName(ruleName),
  81   _register_save_policy(register_save_policy),
  82   _c_reg_save_policy(c_reg_save_policy),
  83   _register_save_type(register_save_type) {
  84   C->set_matcher(this);
  85 
  86   idealreg2spillmask  [Op_RegI] = NULL;
  87   idealreg2spillmask  [Op_RegN] = NULL;
  88   idealreg2spillmask  [Op_RegL] = NULL;
  89   idealreg2spillmask  [Op_RegF] = NULL;
  90   idealreg2spillmask  [Op_RegD] = NULL;
  91   idealreg2spillmask  [Op_RegP] = NULL;
  92   idealreg2spillmask  [Op_VecA] = NULL;
  93   idealreg2spillmask  [Op_VecS] = NULL;
  94   idealreg2spillmask  [Op_VecD] = NULL;
  95   idealreg2spillmask  [Op_VecX] = NULL;
  96   idealreg2spillmask  [Op_VecY] = NULL;
  97   idealreg2spillmask  [Op_VecZ] = NULL;
  98   idealreg2spillmask  [Op_RegFlags] = NULL;
  99   idealreg2spillmask  [Op_RegVectMask] = NULL;
 100 
 101   idealreg2debugmask  [Op_RegI] = NULL;
 102   idealreg2debugmask  [Op_RegN] = NULL;
 103   idealreg2debugmask  [Op_RegL] = NULL;
 104   idealreg2debugmask  [Op_RegF] = NULL;
 105   idealreg2debugmask  [Op_RegD] = NULL;
 106   idealreg2debugmask  [Op_RegP] = NULL;
 107   idealreg2debugmask  [Op_VecA] = NULL;
 108   idealreg2debugmask  [Op_VecS] = NULL;
 109   idealreg2debugmask  [Op_VecD] = NULL;
 110   idealreg2debugmask  [Op_VecX] = NULL;
 111   idealreg2debugmask  [Op_VecY] = NULL;
 112   idealreg2debugmask  [Op_VecZ] = NULL;
 113   idealreg2debugmask  [Op_RegFlags] = NULL;
 114   idealreg2debugmask  [Op_RegVectMask] = NULL;
 115 
 116   idealreg2mhdebugmask[Op_RegI] = NULL;
 117   idealreg2mhdebugmask[Op_RegN] = NULL;
 118   idealreg2mhdebugmask[Op_RegL] = NULL;
 119   idealreg2mhdebugmask[Op_RegF] = NULL;
 120   idealreg2mhdebugmask[Op_RegD] = NULL;
 121   idealreg2mhdebugmask[Op_RegP] = NULL;
 122   idealreg2mhdebugmask[Op_VecA] = NULL;
 123   idealreg2mhdebugmask[Op_VecS] = NULL;
 124   idealreg2mhdebugmask[Op_VecD] = NULL;
 125   idealreg2mhdebugmask[Op_VecX] = NULL;
 126   idealreg2mhdebugmask[Op_VecY] = NULL;
 127   idealreg2mhdebugmask[Op_VecZ] = NULL;
 128   idealreg2mhdebugmask[Op_RegFlags] = NULL;
 129   idealreg2mhdebugmask[Op_RegVectMask] = NULL;
 130 
 131   debug_only(_mem_node = NULL;)   // Ideal memory node consumed by mach node
 132 }
 133 
 134 //------------------------------warp_incoming_stk_arg------------------------
 135 // This warps a VMReg into an OptoReg::Name
 136 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
 137   OptoReg::Name warped;
 138   if( reg->is_stack() ) {  // Stack slot argument?
 139     warped = OptoReg::add(_old_SP, reg->reg2stack() );
 140     warped = OptoReg::add(warped, C->out_preserve_stack_slots());
 141     if( warped >= _in_arg_limit )
 142       _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
 143     if (!RegMask::can_represent_arg(warped)) {
 144       // the compiler cannot represent this method's calling sequence
 145       C->record_method_not_compilable("unsupported incoming calling sequence");
 146       return OptoReg::Bad;
 147     }
 148     return warped;
 149   }
 150   return OptoReg::as_OptoReg(reg);
 151 }
 152 
 153 //---------------------------compute_old_SP------------------------------------
 154 OptoReg::Name Compile::compute_old_SP() {
 155   int fixed    = fixed_slots();
 156   int preserve = in_preserve_stack_slots();
 157   return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots()));
 158 }
 159 
 160 
 161 
 162 #ifdef ASSERT
 163 void Matcher::verify_new_nodes_only(Node* xroot) {
 164   // Make sure that the new graph only references new nodes
 165   ResourceMark rm;
 166   Unique_Node_List worklist;
 167   VectorSet visited;
 168   worklist.push(xroot);
 169   while (worklist.size() > 0) {
 170     Node* n = worklist.pop();
 171     visited.set(n->_idx);
 172     assert(C->node_arena()->contains(n), "dead node");
 173     for (uint j = 0; j < n->req(); j++) {
 174       Node* in = n->in(j);
 175       if (in != NULL) {
 176         assert(C->node_arena()->contains(in), "dead node");
 177         if (!visited.test(in->_idx)) {
 178           worklist.push(in);
 179         }
 180       }
 181     }
 182   }
 183 }
 184 #endif
 185 
 186 // Array of RegMask, one per returned values (inline type instances can
 187 // be returned as multiple return values, one per field)
 188 RegMask* Matcher::return_values_mask(const TypeFunc* tf) {
 189   const TypeTuple* range = tf->range_cc();
 190   uint cnt = range->cnt() - TypeFunc::Parms;
 191   if (cnt == 0) {
 192     return NULL;
 193   }
 194   RegMask* mask = NEW_RESOURCE_ARRAY(RegMask, cnt);
 195   BasicType* sig_bt = NEW_RESOURCE_ARRAY(BasicType, cnt);
 196   VMRegPair* vm_parm_regs = NEW_RESOURCE_ARRAY(VMRegPair, cnt);
 197   for (uint i = 0; i < cnt; i++) {
 198     sig_bt[i] = range->field_at(i+TypeFunc::Parms)->basic_type();
 199   }
 200 
 201   int regs = SharedRuntime::java_return_convention(sig_bt, vm_parm_regs, cnt);
 202   if (regs <= 0) {
 203     // We ran out of registers to store the IsInit information for a nullable inline type return.
 204     // Since it is only set in the 'call_epilog', we can simply put it on the stack.
 205     assert(tf->returns_inline_type_as_fields(), "should have been tested during graph construction");
 206     // TODO 8284443 Can we teach the register allocator to reserve a stack slot instead?
 207     // mask[--cnt] = STACK_ONLY_mask does not work (test with -XX:+StressGCM)
 208     int slot = C->fixed_slots() - 2;
 209     if (C->needs_stack_repair()) {
 210       slot -= 2; // Account for stack increment value
 211     }
 212     mask[--cnt].Clear();
 213     mask[cnt].Insert(OptoReg::stack2reg(slot));
 214   }
 215   for (uint i = 0; i < cnt; i++) {
 216     mask[i].Clear();
 217 
 218     OptoReg::Name reg1 = OptoReg::as_OptoReg(vm_parm_regs[i].first());
 219     if (OptoReg::is_valid(reg1)) {
 220       mask[i].Insert(reg1);
 221     }
 222     OptoReg::Name reg2 = OptoReg::as_OptoReg(vm_parm_regs[i].second());
 223     if (OptoReg::is_valid(reg2)) {
 224       mask[i].Insert(reg2);
 225     }
 226   }
 227 
 228   return mask;
 229 }
 230 
 231 //---------------------------match---------------------------------------------
 232 void Matcher::match( ) {
 233   if( MaxLabelRootDepth < 100 ) { // Too small?
 234     assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
 235     MaxLabelRootDepth = 100;
 236   }
 237   // One-time initialization of some register masks.
 238   init_spill_mask( C->root()->in(1) );
 239   _return_addr_mask = return_addr();
 240 #ifdef _LP64
 241   // Pointers take 2 slots in 64-bit land
 242   _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
 243 #endif
 244 
 245   // Map Java-signature return types into return register-value
 246   // machine registers.
 247   _return_values_mask = return_values_mask(C->tf());
 248 
 249   // ---------------
 250   // Frame Layout
 251 
 252   // Need the method signature to determine the incoming argument types,
 253   // because the types determine which registers the incoming arguments are
 254   // in, and this affects the matched code.
 255   const TypeTuple *domain = C->tf()->domain_cc();
 256   uint             argcnt = domain->cnt() - TypeFunc::Parms;
 257   BasicType *sig_bt        = NEW_RESOURCE_ARRAY( BasicType, argcnt );
 258   VMRegPair *vm_parm_regs  = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
 259   _parm_regs               = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
 260   _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
 261   uint i;
 262   for( i = 0; i<argcnt; i++ ) {
 263     sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
 264   }
 265 
 266   // Pass array of ideal registers and length to USER code (from the AD file)
 267   // that will convert this to an array of register numbers.
 268   const StartNode *start = C->start();
 269   start->calling_convention( sig_bt, vm_parm_regs, argcnt );
 270 #ifdef ASSERT
 271   // Sanity check users' calling convention.  Real handy while trying to
 272   // get the initial port correct.
 273   { for (uint i = 0; i<argcnt; i++) {
 274       if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
 275         assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
 276         _parm_regs[i].set_bad();
 277         continue;
 278       }
 279       VMReg parm_reg = vm_parm_regs[i].first();
 280       assert(parm_reg->is_valid(), "invalid arg?");
 281       if (parm_reg->is_reg()) {
 282         OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
 283         assert(can_be_java_arg(opto_parm_reg) ||
 284                C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
 285                opto_parm_reg == inline_cache_reg(),
 286                "parameters in register must be preserved by runtime stubs");
 287       }
 288       for (uint j = 0; j < i; j++) {
 289         assert(parm_reg != vm_parm_regs[j].first(),
 290                "calling conv. must produce distinct regs");
 291       }
 292     }
 293   }
 294 #endif
 295 
 296   // Do some initial frame layout.
 297 
 298   // Compute the old incoming SP (may be called FP) as
 299   //   OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
 300   _old_SP = C->compute_old_SP();
 301   assert( is_even(_old_SP), "must be even" );
 302 
 303   // Compute highest incoming stack argument as
 304   //   _old_SP + out_preserve_stack_slots + incoming argument size.
 305   _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
 306   assert( is_even(_in_arg_limit), "out_preserve must be even" );
 307   for( i = 0; i < argcnt; i++ ) {
 308     // Permit args to have no register
 309     _calling_convention_mask[i].Clear();
 310     if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
 311       continue;
 312     }
 313     // calling_convention returns stack arguments as a count of
 314     // slots beyond OptoReg::stack0()/VMRegImpl::stack0.  We need to convert this to
 315     // the allocators point of view, taking into account all the
 316     // preserve area, locks & pad2.
 317 
 318     OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
 319     if( OptoReg::is_valid(reg1))
 320       _calling_convention_mask[i].Insert(reg1);
 321 
 322     OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
 323     if( OptoReg::is_valid(reg2))
 324       _calling_convention_mask[i].Insert(reg2);
 325 
 326     // Saved biased stack-slot register number
 327     _parm_regs[i].set_pair(reg2, reg1);
 328   }
 329 
 330   // Finally, make sure the incoming arguments take up an even number of
 331   // words, in case the arguments or locals need to contain doubleword stack
 332   // slots.  The rest of the system assumes that stack slot pairs (in
 333   // particular, in the spill area) which look aligned will in fact be
 334   // aligned relative to the stack pointer in the target machine.  Double
 335   // stack slots will always be allocated aligned.
 336   _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong));
 337 
 338   // Compute highest outgoing stack argument as
 339   //   _new_SP + out_preserve_stack_slots + max(outgoing argument size).
 340   _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
 341   assert( is_even(_out_arg_limit), "out_preserve must be even" );
 342 
 343   if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
 344     // the compiler cannot represent this method's calling sequence
 345     C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
 346   }
 347 
 348   if (C->failing())  return;  // bailed out on incoming arg failure
 349 
 350   // ---------------
 351   // Collect roots of matcher trees.  Every node for which
 352   // _shared[_idx] is cleared is guaranteed to not be shared, and thus
 353   // can be a valid interior of some tree.
 354   find_shared( C->root() );
 355   find_shared( C->top() );
 356 
 357   C->print_method(PHASE_BEFORE_MATCHING, 1);
 358 
 359   // Create new ideal node ConP #NULL even if it does exist in old space
 360   // to avoid false sharing if the corresponding mach node is not used.
 361   // The corresponding mach node is only used in rare cases for derived
 362   // pointers.
 363   Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
 364 
 365   // Swap out to old-space; emptying new-space
 366   Arena *old = C->node_arena()->move_contents(C->old_arena());
 367 
 368   // Save debug and profile information for nodes in old space:
 369   _old_node_note_array = C->node_note_array();
 370   if (_old_node_note_array != NULL) {
 371     C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
 372                            (C->comp_arena(), _old_node_note_array->length(),
 373                             0, NULL));
 374   }
 375 
 376   // Pre-size the new_node table to avoid the need for range checks.
 377   grow_new_node_array(C->unique());
 378 
 379   // Reset node counter so MachNodes start with _idx at 0
 380   int live_nodes = C->live_nodes();
 381   C->set_unique(0);
 382   C->reset_dead_node_list();
 383 
 384   // Recursively match trees from old space into new space.
 385   // Correct leaves of new-space Nodes; they point to old-space.
 386   _visited.clear();
 387   C->set_cached_top_node(xform( C->top(), live_nodes ));
 388   if (!C->failing()) {
 389     Node* xroot =        xform( C->root(), 1 );
 390     if (xroot == NULL) {
 391       Matcher::soft_match_failure();  // recursive matching process failed
 392       C->record_method_not_compilable("instruction match failed");
 393     } else {
 394       // During matching shared constants were attached to C->root()
 395       // because xroot wasn't available yet, so transfer the uses to
 396       // the xroot.
 397       for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
 398         Node* n = C->root()->fast_out(j);
 399         if (C->node_arena()->contains(n)) {
 400           assert(n->in(0) == C->root(), "should be control user");
 401           n->set_req(0, xroot);
 402           --j;
 403           --jmax;
 404         }
 405       }
 406 
 407       // Generate new mach node for ConP #NULL
 408       assert(new_ideal_null != NULL, "sanity");
 409       _mach_null = match_tree(new_ideal_null);
 410       // Don't set control, it will confuse GCM since there are no uses.
 411       // The control will be set when this node is used first time
 412       // in find_base_for_derived().
 413       assert(_mach_null != NULL, "");
 414 
 415       C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
 416 
 417 #ifdef ASSERT
 418       verify_new_nodes_only(xroot);
 419 #endif
 420     }
 421   }
 422   if (C->top() == NULL || C->root() == NULL) {
 423     C->record_method_not_compilable("graph lost"); // %%% cannot happen?
 424   }
 425   if (C->failing()) {
 426     // delete old;
 427     old->destruct_contents();
 428     return;
 429   }
 430   assert( C->top(), "" );
 431   assert( C->root(), "" );
 432   validate_null_checks();
 433 
 434   // Now smoke old-space
 435   NOT_DEBUG( old->destruct_contents() );
 436 
 437   // ------------------------
 438   // Set up save-on-entry registers.
 439   Fixup_Save_On_Entry( );
 440 
 441   { // Cleanup mach IR after selection phase is over.
 442     Compile::TracePhase tp("postselect_cleanup", &timers[_t_postselect_cleanup]);
 443     do_postselect_cleanup();
 444     if (C->failing())  return;
 445     assert(verify_after_postselect_cleanup(), "");
 446   }
 447 }
 448 
 449 //------------------------------Fixup_Save_On_Entry----------------------------
 450 // The stated purpose of this routine is to take care of save-on-entry
 451 // registers.  However, the overall goal of the Match phase is to convert into
 452 // machine-specific instructions which have RegMasks to guide allocation.
 453 // So what this procedure really does is put a valid RegMask on each input
 454 // to the machine-specific variations of all Return, TailCall and Halt
 455 // instructions.  It also adds edgs to define the save-on-entry values (and of
 456 // course gives them a mask).
 457 
 458 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
 459   RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
 460   // Do all the pre-defined register masks
 461   rms[TypeFunc::Control  ] = RegMask::Empty;
 462   rms[TypeFunc::I_O      ] = RegMask::Empty;
 463   rms[TypeFunc::Memory   ] = RegMask::Empty;
 464   rms[TypeFunc::ReturnAdr] = ret_adr;
 465   rms[TypeFunc::FramePtr ] = fp;
 466   return rms;
 467 }
 468 
 469 const int Matcher::scalable_predicate_reg_slots() {
 470   assert(Matcher::has_predicated_vectors() && Matcher::supports_scalable_vector(),
 471         "scalable predicate vector should be supported");
 472   int vector_reg_bit_size = Matcher::scalable_vector_reg_size(T_BYTE) << LogBitsPerByte;
 473   // We assume each predicate register is one-eighth of the size of
 474   // scalable vector register, one mask bit per vector byte.
 475   int predicate_reg_bit_size = vector_reg_bit_size >> 3;
 476   // Compute number of slots which is required when scalable predicate
 477   // register is spilled. E.g. if scalable vector register is 640 bits,
 478   // predicate register is 80 bits, which is 2.5 * slots.
 479   // We will round up the slot number to power of 2, which is required
 480   // by find_first_set().
 481   int slots = predicate_reg_bit_size & (BitsPerInt - 1)
 482               ? (predicate_reg_bit_size >> LogBitsPerInt) + 1
 483               : predicate_reg_bit_size >> LogBitsPerInt;
 484   return round_up_power_of_2(slots);
 485 }
 486 
 487 #define NOF_STACK_MASKS (3*13)
 488 
 489 // Create the initial stack mask used by values spilling to the stack.
 490 // Disallow any debug info in outgoing argument areas by setting the
 491 // initial mask accordingly.
 492 void Matcher::init_first_stack_mask() {
 493 
 494   // Allocate storage for spill masks as masks for the appropriate load type.
 495   RegMask *rms = (RegMask*)C->comp_arena()->AmallocWords(sizeof(RegMask) * NOF_STACK_MASKS);
 496 
 497   // Initialize empty placeholder masks into the newly allocated arena
 498   for (int i = 0; i < NOF_STACK_MASKS; i++) {
 499     new (rms + i) RegMask();
 500   }
 501 
 502   idealreg2spillmask  [Op_RegN] = &rms[0];
 503   idealreg2spillmask  [Op_RegI] = &rms[1];
 504   idealreg2spillmask  [Op_RegL] = &rms[2];
 505   idealreg2spillmask  [Op_RegF] = &rms[3];
 506   idealreg2spillmask  [Op_RegD] = &rms[4];
 507   idealreg2spillmask  [Op_RegP] = &rms[5];
 508 
 509   idealreg2debugmask  [Op_RegN] = &rms[6];
 510   idealreg2debugmask  [Op_RegI] = &rms[7];
 511   idealreg2debugmask  [Op_RegL] = &rms[8];
 512   idealreg2debugmask  [Op_RegF] = &rms[9];
 513   idealreg2debugmask  [Op_RegD] = &rms[10];
 514   idealreg2debugmask  [Op_RegP] = &rms[11];
 515 
 516   idealreg2mhdebugmask[Op_RegN] = &rms[12];
 517   idealreg2mhdebugmask[Op_RegI] = &rms[13];
 518   idealreg2mhdebugmask[Op_RegL] = &rms[14];
 519   idealreg2mhdebugmask[Op_RegF] = &rms[15];
 520   idealreg2mhdebugmask[Op_RegD] = &rms[16];
 521   idealreg2mhdebugmask[Op_RegP] = &rms[17];
 522 
 523   idealreg2spillmask  [Op_VecA] = &rms[18];
 524   idealreg2spillmask  [Op_VecS] = &rms[19];
 525   idealreg2spillmask  [Op_VecD] = &rms[20];
 526   idealreg2spillmask  [Op_VecX] = &rms[21];
 527   idealreg2spillmask  [Op_VecY] = &rms[22];
 528   idealreg2spillmask  [Op_VecZ] = &rms[23];
 529 
 530   idealreg2debugmask  [Op_VecA] = &rms[24];
 531   idealreg2debugmask  [Op_VecS] = &rms[25];
 532   idealreg2debugmask  [Op_VecD] = &rms[26];
 533   idealreg2debugmask  [Op_VecX] = &rms[27];
 534   idealreg2debugmask  [Op_VecY] = &rms[28];
 535   idealreg2debugmask  [Op_VecZ] = &rms[29];
 536 
 537   idealreg2mhdebugmask[Op_VecA] = &rms[30];
 538   idealreg2mhdebugmask[Op_VecS] = &rms[31];
 539   idealreg2mhdebugmask[Op_VecD] = &rms[32];
 540   idealreg2mhdebugmask[Op_VecX] = &rms[33];
 541   idealreg2mhdebugmask[Op_VecY] = &rms[34];
 542   idealreg2mhdebugmask[Op_VecZ] = &rms[35];
 543 
 544   idealreg2spillmask  [Op_RegVectMask] = &rms[36];
 545   idealreg2debugmask  [Op_RegVectMask] = &rms[37];
 546   idealreg2mhdebugmask[Op_RegVectMask] = &rms[38];
 547 
 548   OptoReg::Name i;
 549 
 550   // At first, start with the empty mask
 551   C->FIRST_STACK_mask().Clear();
 552 
 553   // Add in the incoming argument area
 554   OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
 555   for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
 556     C->FIRST_STACK_mask().Insert(i);
 557   }
 558 
 559   // Add in all bits past the outgoing argument area
 560   guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
 561             "must be able to represent all call arguments in reg mask");
 562   OptoReg::Name init = _out_arg_limit;
 563   for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
 564     C->FIRST_STACK_mask().Insert(i);
 565   }
 566   // Finally, set the "infinite stack" bit.
 567   C->FIRST_STACK_mask().set_AllStack();
 568 
 569   // Make spill masks.  Registers for their class, plus FIRST_STACK_mask.
 570   RegMask aligned_stack_mask = C->FIRST_STACK_mask();
 571   // Keep spill masks aligned.
 572   aligned_stack_mask.clear_to_pairs();
 573   assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 574   RegMask scalable_stack_mask = aligned_stack_mask;
 575 
 576   *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
 577 #ifdef _LP64
 578   *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
 579    idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
 580    idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
 581 #else
 582    idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
 583 #endif
 584   *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
 585    idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
 586   *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
 587    idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
 588   *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
 589    idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
 590   *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
 591    idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
 592 
 593   if (Matcher::has_predicated_vectors()) {
 594     *idealreg2spillmask[Op_RegVectMask] = *idealreg2regmask[Op_RegVectMask];
 595      idealreg2spillmask[Op_RegVectMask]->OR(aligned_stack_mask);
 596   } else {
 597     *idealreg2spillmask[Op_RegVectMask] = RegMask::Empty;
 598   }
 599 
 600   if (Matcher::vector_size_supported(T_BYTE,4)) {
 601     *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
 602      idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
 603   } else {
 604     *idealreg2spillmask[Op_VecS] = RegMask::Empty;
 605   }
 606 
 607   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 608     // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
 609     // RA guarantees such alignment since it is needed for Double and Long values.
 610     *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
 611      idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
 612   } else {
 613     *idealreg2spillmask[Op_VecD] = RegMask::Empty;
 614   }
 615 
 616   if (Matcher::vector_size_supported(T_FLOAT,4)) {
 617     // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
 618     //
 619     // RA can use input arguments stack slots for spills but until RA
 620     // we don't know frame size and offset of input arg stack slots.
 621     //
 622     // Exclude last input arg stack slots to avoid spilling vectors there
 623     // otherwise vector spills could stomp over stack slots in caller frame.
 624     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 625     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
 626       aligned_stack_mask.Remove(in);
 627       in = OptoReg::add(in, -1);
 628     }
 629      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
 630      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 631     *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
 632      idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
 633   } else {
 634     *idealreg2spillmask[Op_VecX] = RegMask::Empty;
 635   }
 636 
 637   if (Matcher::vector_size_supported(T_FLOAT,8)) {
 638     // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
 639     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 640     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
 641       aligned_stack_mask.Remove(in);
 642       in = OptoReg::add(in, -1);
 643     }
 644      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
 645      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 646     *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
 647      idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
 648   } else {
 649     *idealreg2spillmask[Op_VecY] = RegMask::Empty;
 650   }
 651 
 652   if (Matcher::vector_size_supported(T_FLOAT,16)) {
 653     // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
 654     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 655     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
 656       aligned_stack_mask.Remove(in);
 657       in = OptoReg::add(in, -1);
 658     }
 659      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
 660      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 661     *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
 662      idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
 663   } else {
 664     *idealreg2spillmask[Op_VecZ] = RegMask::Empty;
 665   }
 666 
 667   if (Matcher::supports_scalable_vector()) {
 668     int k = 1;
 669     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 670     if (Matcher::has_predicated_vectors()) {
 671       // Exclude last input arg stack slots to avoid spilling vector register there,
 672       // otherwise RegVectMask spills could stomp over stack slots in caller frame.
 673       for (; (in >= init_in) && (k < scalable_predicate_reg_slots()); k++) {
 674         scalable_stack_mask.Remove(in);
 675         in = OptoReg::add(in, -1);
 676       }
 677 
 678       // For RegVectMask
 679       scalable_stack_mask.clear_to_sets(scalable_predicate_reg_slots());
 680       assert(scalable_stack_mask.is_AllStack(), "should be infinite stack");
 681       *idealreg2spillmask[Op_RegVectMask] = *idealreg2regmask[Op_RegVectMask];
 682       idealreg2spillmask[Op_RegVectMask]->OR(scalable_stack_mask);
 683     }
 684 
 685     // Exclude last input arg stack slots to avoid spilling vector register there,
 686     // otherwise vector spills could stomp over stack slots in caller frame.
 687     for (; (in >= init_in) && (k < scalable_vector_reg_size(T_FLOAT)); k++) {
 688       scalable_stack_mask.Remove(in);
 689       in = OptoReg::add(in, -1);
 690     }
 691 
 692     // For VecA
 693      scalable_stack_mask.clear_to_sets(RegMask::SlotsPerVecA);
 694      assert(scalable_stack_mask.is_AllStack(), "should be infinite stack");
 695     *idealreg2spillmask[Op_VecA] = *idealreg2regmask[Op_VecA];
 696      idealreg2spillmask[Op_VecA]->OR(scalable_stack_mask);
 697   } else {
 698     *idealreg2spillmask[Op_VecA] = RegMask::Empty;
 699   }
 700 
 701   if (UseFPUForSpilling) {
 702     // This mask logic assumes that the spill operations are
 703     // symmetric and that the registers involved are the same size.
 704     // On sparc for instance we may have to use 64 bit moves will
 705     // kill 2 registers when used with F0-F31.
 706     idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
 707     idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
 708 #ifdef _LP64
 709     idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
 710     idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
 711     idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
 712     idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
 713 #else
 714     idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
 715 #ifdef ARM
 716     // ARM has support for moving 64bit values between a pair of
 717     // integer registers and a double register
 718     idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
 719     idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
 720 #endif
 721 #endif
 722   }
 723 
 724   // Make up debug masks.  Any spill slot plus callee-save (SOE) registers.
 725   // Caller-save (SOC, AS) registers are assumed to be trashable by the various
 726   // inline-cache fixup routines.
 727   *idealreg2debugmask  [Op_RegN] = *idealreg2spillmask[Op_RegN];
 728   *idealreg2debugmask  [Op_RegI] = *idealreg2spillmask[Op_RegI];
 729   *idealreg2debugmask  [Op_RegL] = *idealreg2spillmask[Op_RegL];
 730   *idealreg2debugmask  [Op_RegF] = *idealreg2spillmask[Op_RegF];
 731   *idealreg2debugmask  [Op_RegD] = *idealreg2spillmask[Op_RegD];
 732   *idealreg2debugmask  [Op_RegP] = *idealreg2spillmask[Op_RegP];
 733   *idealreg2debugmask  [Op_RegVectMask] = *idealreg2spillmask[Op_RegVectMask];
 734 
 735   *idealreg2debugmask  [Op_VecA] = *idealreg2spillmask[Op_VecA];
 736   *idealreg2debugmask  [Op_VecS] = *idealreg2spillmask[Op_VecS];
 737   *idealreg2debugmask  [Op_VecD] = *idealreg2spillmask[Op_VecD];
 738   *idealreg2debugmask  [Op_VecX] = *idealreg2spillmask[Op_VecX];
 739   *idealreg2debugmask  [Op_VecY] = *idealreg2spillmask[Op_VecY];
 740   *idealreg2debugmask  [Op_VecZ] = *idealreg2spillmask[Op_VecZ];
 741 
 742   *idealreg2mhdebugmask[Op_RegN] = *idealreg2spillmask[Op_RegN];
 743   *idealreg2mhdebugmask[Op_RegI] = *idealreg2spillmask[Op_RegI];
 744   *idealreg2mhdebugmask[Op_RegL] = *idealreg2spillmask[Op_RegL];
 745   *idealreg2mhdebugmask[Op_RegF] = *idealreg2spillmask[Op_RegF];
 746   *idealreg2mhdebugmask[Op_RegD] = *idealreg2spillmask[Op_RegD];
 747   *idealreg2mhdebugmask[Op_RegP] = *idealreg2spillmask[Op_RegP];
 748   *idealreg2mhdebugmask[Op_RegVectMask] = *idealreg2spillmask[Op_RegVectMask];
 749 
 750   *idealreg2mhdebugmask[Op_VecA] = *idealreg2spillmask[Op_VecA];
 751   *idealreg2mhdebugmask[Op_VecS] = *idealreg2spillmask[Op_VecS];
 752   *idealreg2mhdebugmask[Op_VecD] = *idealreg2spillmask[Op_VecD];
 753   *idealreg2mhdebugmask[Op_VecX] = *idealreg2spillmask[Op_VecX];
 754   *idealreg2mhdebugmask[Op_VecY] = *idealreg2spillmask[Op_VecY];
 755   *idealreg2mhdebugmask[Op_VecZ] = *idealreg2spillmask[Op_VecZ];
 756 
 757   // Prevent stub compilations from attempting to reference
 758   // callee-saved (SOE) registers from debug info
 759   bool exclude_soe = !Compile::current()->is_method_compilation();
 760   RegMask* caller_save_mask = exclude_soe ? &caller_save_regmask_exclude_soe : &caller_save_regmask;
 761   RegMask* mh_caller_save_mask = exclude_soe ? &mh_caller_save_regmask_exclude_soe : &mh_caller_save_regmask;
 762 
 763   idealreg2debugmask[Op_RegN]->SUBTRACT(*caller_save_mask);
 764   idealreg2debugmask[Op_RegI]->SUBTRACT(*caller_save_mask);
 765   idealreg2debugmask[Op_RegL]->SUBTRACT(*caller_save_mask);
 766   idealreg2debugmask[Op_RegF]->SUBTRACT(*caller_save_mask);
 767   idealreg2debugmask[Op_RegD]->SUBTRACT(*caller_save_mask);
 768   idealreg2debugmask[Op_RegP]->SUBTRACT(*caller_save_mask);
 769   idealreg2debugmask[Op_RegVectMask]->SUBTRACT(*caller_save_mask);
 770 
 771   idealreg2debugmask[Op_VecA]->SUBTRACT(*caller_save_mask);
 772   idealreg2debugmask[Op_VecS]->SUBTRACT(*caller_save_mask);
 773   idealreg2debugmask[Op_VecD]->SUBTRACT(*caller_save_mask);
 774   idealreg2debugmask[Op_VecX]->SUBTRACT(*caller_save_mask);
 775   idealreg2debugmask[Op_VecY]->SUBTRACT(*caller_save_mask);
 776   idealreg2debugmask[Op_VecZ]->SUBTRACT(*caller_save_mask);
 777 
 778   idealreg2mhdebugmask[Op_RegN]->SUBTRACT(*mh_caller_save_mask);
 779   idealreg2mhdebugmask[Op_RegI]->SUBTRACT(*mh_caller_save_mask);
 780   idealreg2mhdebugmask[Op_RegL]->SUBTRACT(*mh_caller_save_mask);
 781   idealreg2mhdebugmask[Op_RegF]->SUBTRACT(*mh_caller_save_mask);
 782   idealreg2mhdebugmask[Op_RegD]->SUBTRACT(*mh_caller_save_mask);
 783   idealreg2mhdebugmask[Op_RegP]->SUBTRACT(*mh_caller_save_mask);
 784   idealreg2mhdebugmask[Op_RegVectMask]->SUBTRACT(*mh_caller_save_mask);
 785 
 786   idealreg2mhdebugmask[Op_VecA]->SUBTRACT(*mh_caller_save_mask);
 787   idealreg2mhdebugmask[Op_VecS]->SUBTRACT(*mh_caller_save_mask);
 788   idealreg2mhdebugmask[Op_VecD]->SUBTRACT(*mh_caller_save_mask);
 789   idealreg2mhdebugmask[Op_VecX]->SUBTRACT(*mh_caller_save_mask);
 790   idealreg2mhdebugmask[Op_VecY]->SUBTRACT(*mh_caller_save_mask);
 791   idealreg2mhdebugmask[Op_VecZ]->SUBTRACT(*mh_caller_save_mask);
 792 }
 793 
 794 //---------------------------is_save_on_entry----------------------------------
 795 bool Matcher::is_save_on_entry(int reg) {
 796   return
 797     _register_save_policy[reg] == 'E' ||
 798     _register_save_policy[reg] == 'A'; // Save-on-entry register?
 799 }
 800 
 801 //---------------------------Fixup_Save_On_Entry-------------------------------
 802 void Matcher::Fixup_Save_On_Entry( ) {
 803   init_first_stack_mask();
 804 
 805   Node *root = C->root();       // Short name for root
 806   // Count number of save-on-entry registers.
 807   uint soe_cnt = number_of_saved_registers();
 808   uint i;
 809 
 810   // Find the procedure Start Node
 811   StartNode *start = C->start();
 812   assert( start, "Expect a start node" );
 813 
 814   // Input RegMask array shared by all Returns.
 815   // The type for doubles and longs has a count of 2, but
 816   // there is only 1 returned value
 817   uint ret_edge_cnt = C->tf()->range_cc()->cnt();
 818   RegMask *ret_rms  = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 819   for (i = TypeFunc::Parms; i < ret_edge_cnt; i++) {
 820     ret_rms[i] = _return_values_mask[i-TypeFunc::Parms];
 821   }
 822 
 823   // Input RegMask array shared by all Rethrows.
 824   uint reth_edge_cnt = TypeFunc::Parms+1;
 825   RegMask *reth_rms  = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 826   // Rethrow takes exception oop only, but in the argument 0 slot.
 827   OptoReg::Name reg = find_receiver();
 828   if (reg >= 0) {
 829     reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
 830 #ifdef _LP64
 831     // Need two slots for ptrs in 64-bit land
 832     reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
 833 #endif
 834   }
 835 
 836   // Input RegMask array shared by all TailCalls
 837   uint tail_call_edge_cnt = TypeFunc::Parms+2;
 838   RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 839 
 840   // Input RegMask array shared by all TailJumps
 841   uint tail_jump_edge_cnt = TypeFunc::Parms+2;
 842   RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 843 
 844   // TailCalls have 2 returned values (target & moop), whose masks come
 845   // from the usual MachNode/MachOper mechanism.  Find a sample
 846   // TailCall to extract these masks and put the correct masks into
 847   // the tail_call_rms array.
 848   for( i=1; i < root->req(); i++ ) {
 849     MachReturnNode *m = root->in(i)->as_MachReturn();
 850     if( m->ideal_Opcode() == Op_TailCall ) {
 851       tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
 852       tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
 853       break;
 854     }
 855   }
 856 
 857   // TailJumps have 2 returned values (target & ex_oop), whose masks come
 858   // from the usual MachNode/MachOper mechanism.  Find a sample
 859   // TailJump to extract these masks and put the correct masks into
 860   // the tail_jump_rms array.
 861   for( i=1; i < root->req(); i++ ) {
 862     MachReturnNode *m = root->in(i)->as_MachReturn();
 863     if( m->ideal_Opcode() == Op_TailJump ) {
 864       tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
 865       tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
 866       break;
 867     }
 868   }
 869 
 870   // Input RegMask array shared by all Halts
 871   uint halt_edge_cnt = TypeFunc::Parms;
 872   RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 873 
 874   // Capture the return input masks into each exit flavor
 875   for( i=1; i < root->req(); i++ ) {
 876     MachReturnNode *exit = root->in(i)->as_MachReturn();
 877     switch( exit->ideal_Opcode() ) {
 878       case Op_Return   : exit->_in_rms = ret_rms;  break;
 879       case Op_Rethrow  : exit->_in_rms = reth_rms; break;
 880       case Op_TailCall : exit->_in_rms = tail_call_rms; break;
 881       case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
 882       case Op_Halt     : exit->_in_rms = halt_rms; break;
 883       default          : ShouldNotReachHere();
 884     }
 885   }
 886 
 887   // Next unused projection number from Start.
 888   int proj_cnt = C->tf()->domain_cc()->cnt();
 889 
 890   // Do all the save-on-entry registers.  Make projections from Start for
 891   // them, and give them a use at the exit points.  To the allocator, they
 892   // look like incoming register arguments.
 893   for( i = 0; i < _last_Mach_Reg; i++ ) {
 894     if( is_save_on_entry(i) ) {
 895 
 896       // Add the save-on-entry to the mask array
 897       ret_rms      [      ret_edge_cnt] = mreg2regmask[i];
 898       reth_rms     [     reth_edge_cnt] = mreg2regmask[i];
 899       tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
 900       tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
 901       // Halts need the SOE registers, but only in the stack as debug info.
 902       // A just-prior uncommon-trap or deoptimization will use the SOE regs.
 903       halt_rms     [     halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
 904 
 905       Node *mproj;
 906 
 907       // Is this a RegF low half of a RegD?  Double up 2 adjacent RegF's
 908       // into a single RegD.
 909       if( (i&1) == 0 &&
 910           _register_save_type[i  ] == Op_RegF &&
 911           _register_save_type[i+1] == Op_RegF &&
 912           is_save_on_entry(i+1) ) {
 913         // Add other bit for double
 914         ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
 915         reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
 916         tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
 917         tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
 918         halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
 919         mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
 920         proj_cnt += 2;          // Skip 2 for doubles
 921       }
 922       else if( (i&1) == 1 &&    // Else check for high half of double
 923                _register_save_type[i-1] == Op_RegF &&
 924                _register_save_type[i  ] == Op_RegF &&
 925                is_save_on_entry(i-1) ) {
 926         ret_rms      [      ret_edge_cnt] = RegMask::Empty;
 927         reth_rms     [     reth_edge_cnt] = RegMask::Empty;
 928         tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
 929         tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
 930         halt_rms     [     halt_edge_cnt] = RegMask::Empty;
 931         mproj = C->top();
 932       }
 933       // Is this a RegI low half of a RegL?  Double up 2 adjacent RegI's
 934       // into a single RegL.
 935       else if( (i&1) == 0 &&
 936           _register_save_type[i  ] == Op_RegI &&
 937           _register_save_type[i+1] == Op_RegI &&
 938         is_save_on_entry(i+1) ) {
 939         // Add other bit for long
 940         ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
 941         reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
 942         tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
 943         tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
 944         halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
 945         mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
 946         proj_cnt += 2;          // Skip 2 for longs
 947       }
 948       else if( (i&1) == 1 &&    // Else check for high half of long
 949                _register_save_type[i-1] == Op_RegI &&
 950                _register_save_type[i  ] == Op_RegI &&
 951                is_save_on_entry(i-1) ) {
 952         ret_rms      [      ret_edge_cnt] = RegMask::Empty;
 953         reth_rms     [     reth_edge_cnt] = RegMask::Empty;
 954         tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
 955         tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
 956         halt_rms     [     halt_edge_cnt] = RegMask::Empty;
 957         mproj = C->top();
 958       } else {
 959         // Make a projection for it off the Start
 960         mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
 961       }
 962 
 963       ret_edge_cnt ++;
 964       reth_edge_cnt ++;
 965       tail_call_edge_cnt ++;
 966       tail_jump_edge_cnt ++;
 967       halt_edge_cnt ++;
 968 
 969       // Add a use of the SOE register to all exit paths
 970       for( uint j=1; j < root->req(); j++ )
 971         root->in(j)->add_req(mproj);
 972     } // End of if a save-on-entry register
 973   } // End of for all machine registers
 974 }
 975 
 976 //------------------------------init_spill_mask--------------------------------
 977 void Matcher::init_spill_mask( Node *ret ) {
 978   if( idealreg2regmask[Op_RegI] ) return; // One time only init
 979 
 980   OptoReg::c_frame_pointer = c_frame_pointer();
 981   c_frame_ptr_mask = c_frame_pointer();
 982 #ifdef _LP64
 983   // pointers are twice as big
 984   c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
 985 #endif
 986 
 987   // Start at OptoReg::stack0()
 988   STACK_ONLY_mask.Clear();
 989   OptoReg::Name init = OptoReg::stack2reg(0);
 990   // STACK_ONLY_mask is all stack bits
 991   OptoReg::Name i;
 992   for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
 993     STACK_ONLY_mask.Insert(i);
 994   // Also set the "infinite stack" bit.
 995   STACK_ONLY_mask.set_AllStack();
 996 
 997   for (i = OptoReg::Name(0); i < OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i, 1)) {
 998     // Copy the register names over into the shared world.
 999     // SharedInfo::regName[i] = regName[i];
1000     // Handy RegMasks per machine register
1001     mreg2regmask[i].Insert(i);
1002 
1003     // Set up regmasks used to exclude save-on-call (and always-save) registers from debug masks.
1004     if (_register_save_policy[i] == 'C' ||
1005         _register_save_policy[i] == 'A') {
1006       caller_save_regmask.Insert(i);
1007       mh_caller_save_regmask.Insert(i);
1008     }
1009     // Exclude save-on-entry registers from debug masks for stub compilations.
1010     if (_register_save_policy[i] == 'C' ||
1011         _register_save_policy[i] == 'A' ||
1012         _register_save_policy[i] == 'E') {
1013       caller_save_regmask_exclude_soe.Insert(i);
1014       mh_caller_save_regmask_exclude_soe.Insert(i);
1015     }
1016   }
1017 
1018   // Also exclude the register we use to save the SP for MethodHandle
1019   // invokes to from the corresponding MH debug masks
1020   const RegMask sp_save_mask = method_handle_invoke_SP_save_mask();
1021   mh_caller_save_regmask.OR(sp_save_mask);
1022   mh_caller_save_regmask_exclude_soe.OR(sp_save_mask);
1023 
1024   // Grab the Frame Pointer
1025   Node *fp  = ret->in(TypeFunc::FramePtr);
1026   // Share frame pointer while making spill ops
1027   set_shared(fp);
1028 
1029 // Get the ADLC notion of the right regmask, for each basic type.
1030 #ifdef _LP64
1031   idealreg2regmask[Op_RegN] = regmask_for_ideal_register(Op_RegN, ret);
1032 #endif
1033   idealreg2regmask[Op_RegI] = regmask_for_ideal_register(Op_RegI, ret);
1034   idealreg2regmask[Op_RegP] = regmask_for_ideal_register(Op_RegP, ret);
1035   idealreg2regmask[Op_RegF] = regmask_for_ideal_register(Op_RegF, ret);
1036   idealreg2regmask[Op_RegD] = regmask_for_ideal_register(Op_RegD, ret);
1037   idealreg2regmask[Op_RegL] = regmask_for_ideal_register(Op_RegL, ret);
1038   idealreg2regmask[Op_VecA] = regmask_for_ideal_register(Op_VecA, ret);
1039   idealreg2regmask[Op_VecS] = regmask_for_ideal_register(Op_VecS, ret);
1040   idealreg2regmask[Op_VecD] = regmask_for_ideal_register(Op_VecD, ret);
1041   idealreg2regmask[Op_VecX] = regmask_for_ideal_register(Op_VecX, ret);
1042   idealreg2regmask[Op_VecY] = regmask_for_ideal_register(Op_VecY, ret);
1043   idealreg2regmask[Op_VecZ] = regmask_for_ideal_register(Op_VecZ, ret);
1044   idealreg2regmask[Op_RegVectMask] = regmask_for_ideal_register(Op_RegVectMask, ret);
1045 }
1046 
1047 #ifdef ASSERT
1048 static void match_alias_type(Compile* C, Node* n, Node* m) {
1049   if (!VerifyAliases)  return;  // do not go looking for trouble by default
1050   const TypePtr* nat = n->adr_type();
1051   const TypePtr* mat = m->adr_type();
1052   int nidx = C->get_alias_index(nat);
1053   int midx = C->get_alias_index(mat);
1054   // Detune the assert for cases like (AndI 0xFF (LoadB p)).
1055   if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
1056     for (uint i = 1; i < n->req(); i++) {
1057       Node* n1 = n->in(i);
1058       const TypePtr* n1at = n1->adr_type();
1059       if (n1at != NULL) {
1060         nat = n1at;
1061         nidx = C->get_alias_index(n1at);
1062       }
1063     }
1064   }
1065   // %%% Kludgery.  Instead, fix ideal adr_type methods for all these cases:
1066   if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
1067     switch (n->Opcode()) {
1068     case Op_PrefetchAllocation:
1069       nidx = Compile::AliasIdxRaw;
1070       nat = TypeRawPtr::BOTTOM;
1071       break;
1072     }
1073   }
1074   if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
1075     switch (n->Opcode()) {
1076     case Op_ClearArray:
1077       midx = Compile::AliasIdxRaw;
1078       mat = TypeRawPtr::BOTTOM;
1079       break;
1080     }
1081   }
1082   if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
1083     switch (n->Opcode()) {
1084     case Op_Return:
1085     case Op_Rethrow:
1086     case Op_Halt:
1087     case Op_TailCall:
1088     case Op_TailJump:
1089       nidx = Compile::AliasIdxBot;
1090       nat = TypePtr::BOTTOM;
1091       break;
1092     }
1093   }
1094   if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
1095     switch (n->Opcode()) {
1096     case Op_StrComp:
1097     case Op_StrEquals:
1098     case Op_StrIndexOf:
1099     case Op_StrIndexOfChar:
1100     case Op_AryEq:
1101     case Op_CountPositives:
1102     case Op_MemBarVolatile:
1103     case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
1104     case Op_StrInflatedCopy:
1105     case Op_StrCompressedCopy:
1106     case Op_OnSpinWait:
1107     case Op_EncodeISOArray:
1108       nidx = Compile::AliasIdxTop;
1109       nat = NULL;
1110       break;
1111     }
1112   }
1113   if (nidx != midx) {
1114     if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
1115       tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
1116       n->dump();
1117       m->dump();
1118     }
1119     assert(C->subsume_loads() && C->must_alias(nat, midx),
1120            "must not lose alias info when matching");
1121   }
1122 }
1123 #endif
1124 
1125 //------------------------------xform------------------------------------------
1126 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1127 // Node in new-space.  Given a new-space Node, recursively walk his children.
1128 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1129 Node *Matcher::xform( Node *n, int max_stack ) {
1130   // Use one stack to keep both: child's node/state and parent's node/index
1131   MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1132   mstack.push(n, Visit, NULL, -1);  // set NULL as parent to indicate root
1133   while (mstack.is_nonempty()) {
1134     C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1135     if (C->failing()) return NULL;
1136     n = mstack.node();          // Leave node on stack
1137     Node_State nstate = mstack.state();
1138     if (nstate == Visit) {
1139       mstack.set_state(Post_Visit);
1140       Node *oldn = n;
1141       // Old-space or new-space check
1142       if (!C->node_arena()->contains(n)) {
1143         // Old space!
1144         Node* m;
1145         if (has_new_node(n)) {  // Not yet Label/Reduced
1146           m = new_node(n);
1147         } else {
1148           if (!is_dontcare(n)) { // Matcher can match this guy
1149             // Calls match special.  They match alone with no children.
1150             // Their children, the incoming arguments, match normally.
1151             m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1152             if (C->failing())  return NULL;
1153             if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1154             if (n->is_MemBar()) {
1155               m->as_MachMemBar()->set_adr_type(n->adr_type());
1156             }
1157           } else {                  // Nothing the matcher cares about
1158             if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) {       // Projections?
1159               // Convert to machine-dependent projection
1160               RegMask* mask = NULL;
1161               if (n->in(0)->is_Call() && n->in(0)->as_Call()->tf()->returns_inline_type_as_fields()) {
1162                 mask = return_values_mask(n->in(0)->as_Call()->tf());
1163               }
1164               m = n->in(0)->as_Multi()->match(n->as_Proj(), this, mask);
1165               NOT_PRODUCT(record_new2old(m, n);)
1166               if (m->in(0) != NULL) // m might be top
1167                 collect_null_checks(m, n);
1168             } else {                // Else just a regular 'ol guy
1169               m = n->clone();       // So just clone into new-space
1170               NOT_PRODUCT(record_new2old(m, n);)
1171               // Def-Use edges will be added incrementally as Uses
1172               // of this node are matched.
1173               assert(m->outcnt() == 0, "no Uses of this clone yet");
1174             }
1175           }
1176 
1177           set_new_node(n, m);       // Map old to new
1178           if (_old_node_note_array != NULL) {
1179             Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1180                                                   n->_idx);
1181             C->set_node_notes_at(m->_idx, nn);
1182           }
1183           debug_only(match_alias_type(C, n, m));
1184         }
1185         n = m;    // n is now a new-space node
1186         mstack.set_node(n);
1187       }
1188 
1189       // New space!
1190       if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1191 
1192       int i;
1193       // Put precedence edges on stack first (match them last).
1194       for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1195         Node *m = oldn->in(i);
1196         if (m == NULL) break;
1197         // set -1 to call add_prec() instead of set_req() during Step1
1198         mstack.push(m, Visit, n, -1);
1199       }
1200 
1201       // Handle precedence edges for interior nodes
1202       for (i = n->len()-1; (uint)i >= n->req(); i--) {
1203         Node *m = n->in(i);
1204         if (m == NULL || C->node_arena()->contains(m)) continue;
1205         n->rm_prec(i);
1206         // set -1 to call add_prec() instead of set_req() during Step1
1207         mstack.push(m, Visit, n, -1);
1208       }
1209 
1210       // For constant debug info, I'd rather have unmatched constants.
1211       int cnt = n->req();
1212       JVMState* jvms = n->jvms();
1213       int debug_cnt = jvms ? jvms->debug_start() : cnt;
1214 
1215       // Now do only debug info.  Clone constants rather than matching.
1216       // Constants are represented directly in the debug info without
1217       // the need for executable machine instructions.
1218       // Monitor boxes are also represented directly.
1219       for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1220         Node *m = n->in(i);          // Get input
1221         int op = m->Opcode();
1222         assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1223         if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1224             op == Op_ConF || op == Op_ConD || op == Op_ConL
1225             // || op == Op_BoxLock  // %%%% enable this and remove (+++) in chaitin.cpp
1226             ) {
1227           m = m->clone();
1228           NOT_PRODUCT(record_new2old(m, n));
1229           mstack.push(m, Post_Visit, n, i); // Don't need to visit
1230           mstack.push(m->in(0), Visit, m, 0);
1231         } else {
1232           mstack.push(m, Visit, n, i);
1233         }
1234       }
1235 
1236       // And now walk his children, and convert his inputs to new-space.
1237       for( ; i >= 0; --i ) { // For all normal inputs do
1238         Node *m = n->in(i);  // Get input
1239         if(m != NULL)
1240           mstack.push(m, Visit, n, i);
1241       }
1242 
1243     }
1244     else if (nstate == Post_Visit) {
1245       // Set xformed input
1246       Node *p = mstack.parent();
1247       if (p != NULL) { // root doesn't have parent
1248         int i = (int)mstack.index();
1249         if (i >= 0)
1250           p->set_req(i, n); // required input
1251         else if (i == -1)
1252           p->add_prec(n);   // precedence input
1253         else
1254           ShouldNotReachHere();
1255       }
1256       mstack.pop(); // remove processed node from stack
1257     }
1258     else {
1259       ShouldNotReachHere();
1260     }
1261   } // while (mstack.is_nonempty())
1262   return n; // Return new-space Node
1263 }
1264 
1265 //------------------------------warp_outgoing_stk_arg------------------------
1266 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1267   // Convert outgoing argument location to a pre-biased stack offset
1268   if (reg->is_stack()) {
1269     OptoReg::Name warped = reg->reg2stack();
1270     // Adjust the stack slot offset to be the register number used
1271     // by the allocator.
1272     warped = OptoReg::add(begin_out_arg_area, warped);
1273     // Keep track of the largest numbered stack slot used for an arg.
1274     // Largest used slot per call-site indicates the amount of stack
1275     // that is killed by the call.
1276     if( warped >= out_arg_limit_per_call )
1277       out_arg_limit_per_call = OptoReg::add(warped,1);
1278     if (!RegMask::can_represent_arg(warped)) {
1279       C->record_method_not_compilable("unsupported calling sequence");
1280       return OptoReg::Bad;
1281     }
1282     return warped;
1283   }
1284   return OptoReg::as_OptoReg(reg);
1285 }
1286 
1287 
1288 //------------------------------match_sfpt-------------------------------------
1289 // Helper function to match call instructions.  Calls match special.
1290 // They match alone with no children.  Their children, the incoming
1291 // arguments, match normally.
1292 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1293   MachSafePointNode *msfpt = NULL;
1294   MachCallNode      *mcall = NULL;
1295   uint               cnt;
1296   // Split out case for SafePoint vs Call
1297   CallNode *call;
1298   const TypeTuple *domain;
1299   ciMethod*        method = NULL;
1300   bool             is_method_handle_invoke = false;  // for special kill effects
1301   if( sfpt->is_Call() ) {
1302     call = sfpt->as_Call();
1303     domain = call->tf()->domain_cc();
1304     cnt = domain->cnt();
1305 
1306     // Match just the call, nothing else
1307     MachNode *m = match_tree(call);
1308     if (C->failing())  return NULL;
1309     if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1310 
1311     // Copy data from the Ideal SafePoint to the machine version
1312     mcall = m->as_MachCall();
1313 
1314     mcall->set_tf(                  call->tf());
1315     mcall->set_entry_point(         call->entry_point());
1316     mcall->set_cnt(                 call->cnt());
1317     mcall->set_guaranteed_safepoint(call->guaranteed_safepoint());
1318 
1319     if( mcall->is_MachCallJava() ) {
1320       MachCallJavaNode *mcall_java  = mcall->as_MachCallJava();
1321       const CallJavaNode *call_java =  call->as_CallJava();
1322       assert(call_java->validate_symbolic_info(), "inconsistent info");
1323       method = call_java->method();
1324       mcall_java->_method = method;
1325       mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1326       is_method_handle_invoke = call_java->is_method_handle_invoke();
1327       mcall_java->_method_handle_invoke = is_method_handle_invoke;
1328       mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1329       mcall_java->_arg_escape = call_java->arg_escape();
1330       if (is_method_handle_invoke) {
1331         C->set_has_method_handle_invokes(true);
1332       }
1333       if( mcall_java->is_MachCallStaticJava() )
1334         mcall_java->as_MachCallStaticJava()->_name =
1335          call_java->as_CallStaticJava()->_name;
1336       if( mcall_java->is_MachCallDynamicJava() )
1337         mcall_java->as_MachCallDynamicJava()->_vtable_index =
1338          call_java->as_CallDynamicJava()->_vtable_index;
1339     }
1340     else if( mcall->is_MachCallRuntime() ) {
1341       MachCallRuntimeNode* mach_call_rt = mcall->as_MachCallRuntime();
1342       mach_call_rt->_name = call->as_CallRuntime()->_name;
1343       mach_call_rt->_leaf_no_fp = call->is_CallLeafNoFP();
1344     }
1345     msfpt = mcall;
1346   }
1347   // This is a non-call safepoint
1348   else {
1349     call = NULL;
1350     domain = NULL;
1351     MachNode *mn = match_tree(sfpt);
1352     if (C->failing())  return NULL;
1353     msfpt = mn->as_MachSafePoint();
1354     cnt = TypeFunc::Parms;
1355   }
1356   msfpt->_has_ea_local_in_scope = sfpt->has_ea_local_in_scope();
1357 
1358   // Advertise the correct memory effects (for anti-dependence computation).
1359   msfpt->set_adr_type(sfpt->adr_type());
1360 
1361   // Allocate a private array of RegMasks.  These RegMasks are not shared.
1362   msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1363   // Empty them all.
1364   for (uint i = 0; i < cnt; i++) ::new (&(msfpt->_in_rms[i])) RegMask();
1365 
1366   // Do all the pre-defined non-Empty register masks
1367   msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1368   msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1369 
1370   // Place first outgoing argument can possibly be put.
1371   OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1372   assert( is_even(begin_out_arg_area), "" );
1373   // Compute max outgoing register number per call site.
1374   OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1375   // Calls to C may hammer extra stack slots above and beyond any arguments.
1376   // These are usually backing store for register arguments for varargs.
1377   if( call != NULL && call->is_CallRuntime() )
1378     out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1379 
1380 
1381   // Do the normal argument list (parameters) register masks
1382   // Null entry point is a special cast where the target of the call
1383   // is in a register.
1384   int adj = (call != NULL && call->entry_point() == NULL) ? 1 : 0;
1385   int argcnt = cnt - TypeFunc::Parms - adj;
1386   if( argcnt > 0 ) {          // Skip it all if we have no args
1387     BasicType *sig_bt  = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1388     VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1389     int i;
1390     for( i = 0; i < argcnt; i++ ) {
1391       sig_bt[i] = domain->field_at(i+TypeFunc::Parms+adj)->basic_type();
1392     }
1393     // V-call to pick proper calling convention
1394     call->calling_convention( sig_bt, parm_regs, argcnt );
1395 
1396 #ifdef ASSERT
1397     // Sanity check users' calling convention.  Really handy during
1398     // the initial porting effort.  Fairly expensive otherwise.
1399     { for (int i = 0; i<argcnt; i++) {
1400       if( !parm_regs[i].first()->is_valid() &&
1401           !parm_regs[i].second()->is_valid() ) continue;
1402       VMReg reg1 = parm_regs[i].first();
1403       VMReg reg2 = parm_regs[i].second();
1404       for (int j = 0; j < i; j++) {
1405         if( !parm_regs[j].first()->is_valid() &&
1406             !parm_regs[j].second()->is_valid() ) continue;
1407         VMReg reg3 = parm_regs[j].first();
1408         VMReg reg4 = parm_regs[j].second();
1409         if( !reg1->is_valid() ) {
1410           assert( !reg2->is_valid(), "valid halvsies" );
1411         } else if( !reg3->is_valid() ) {
1412           assert( !reg4->is_valid(), "valid halvsies" );
1413         } else {
1414           assert( reg1 != reg2, "calling conv. must produce distinct regs");
1415           assert( reg1 != reg3, "calling conv. must produce distinct regs");
1416           assert( reg1 != reg4, "calling conv. must produce distinct regs");
1417           assert( reg2 != reg3, "calling conv. must produce distinct regs");
1418           assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1419           assert( reg3 != reg4, "calling conv. must produce distinct regs");
1420         }
1421       }
1422     }
1423     }
1424 #endif
1425 
1426     // Visit each argument.  Compute its outgoing register mask.
1427     // Return results now can have 2 bits returned.
1428     // Compute max over all outgoing arguments both per call-site
1429     // and over the entire method.
1430     for( i = 0; i < argcnt; i++ ) {
1431       // Address of incoming argument mask to fill in
1432       RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms+adj];
1433       VMReg first = parm_regs[i].first();
1434       VMReg second = parm_regs[i].second();
1435       if(!first->is_valid() &&
1436          !second->is_valid()) {
1437         continue;               // Avoid Halves
1438       }
1439       // Handle case where arguments are in vector registers.
1440       if(call->in(TypeFunc::Parms + i)->bottom_type()->isa_vect()) {
1441         OptoReg::Name reg_fst = OptoReg::as_OptoReg(first);
1442         OptoReg::Name reg_snd = OptoReg::as_OptoReg(second);
1443         assert (reg_fst <= reg_snd, "fst=%d snd=%d", reg_fst, reg_snd);
1444         for (OptoReg::Name r = reg_fst; r <= reg_snd; r++) {
1445           rm->Insert(r);
1446         }
1447       }
1448       // Grab first register, adjust stack slots and insert in mask.
1449       OptoReg::Name reg1 = warp_outgoing_stk_arg(first, begin_out_arg_area, out_arg_limit_per_call );
1450       if (OptoReg::is_valid(reg1)) {
1451         rm->Insert( reg1 );
1452       }
1453       // Grab second register (if any), adjust stack slots and insert in mask.
1454       OptoReg::Name reg2 = warp_outgoing_stk_arg(second, begin_out_arg_area, out_arg_limit_per_call );
1455       if (OptoReg::is_valid(reg2)) {
1456         rm->Insert( reg2 );
1457       }
1458     } // End of for all arguments
1459   }
1460 
1461   // Compute the max stack slot killed by any call.  These will not be
1462   // available for debug info, and will be used to adjust FIRST_STACK_mask
1463   // after all call sites have been visited.
1464   if( _out_arg_limit < out_arg_limit_per_call)
1465     _out_arg_limit = out_arg_limit_per_call;
1466 
1467   if (mcall) {
1468     // Kill the outgoing argument area, including any non-argument holes and
1469     // any legacy C-killed slots.  Use Fat-Projections to do the killing.
1470     // Since the max-per-method covers the max-per-call-site and debug info
1471     // is excluded on the max-per-method basis, debug info cannot land in
1472     // this killed area.
1473     uint r_cnt = mcall->tf()->range_sig()->cnt();
1474     MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1475     if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1476       C->record_method_not_compilable("unsupported outgoing calling sequence");
1477     } else {
1478       for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1479         proj->_rout.Insert(OptoReg::Name(i));
1480     }
1481     if (proj->_rout.is_NotEmpty()) {
1482       push_projection(proj);
1483     }
1484   }
1485   // Transfer the safepoint information from the call to the mcall
1486   // Move the JVMState list
1487   msfpt->set_jvms(sfpt->jvms());
1488   for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1489     jvms->set_map(sfpt);
1490   }
1491 
1492   // Debug inputs begin just after the last incoming parameter
1493   assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1494          (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain_cc()->cnt()), "");
1495 
1496   // Add additional edges.
1497   if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1498     // For these calls we can not add MachConstantBase in expand(), as the
1499     // ins are not complete then.
1500     msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1501     if (msfpt->jvms() &&
1502         msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1503       // We added an edge before jvms, so we must adapt the position of the ins.
1504       msfpt->jvms()->adapt_position(+1);
1505     }
1506   }
1507 
1508   // Registers killed by the call are set in the local scheduling pass
1509   // of Global Code Motion.
1510   return msfpt;
1511 }
1512 
1513 //---------------------------match_tree----------------------------------------
1514 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce.  Used as part
1515 // of the whole-sale conversion from Ideal to Mach Nodes.  Also used for
1516 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1517 // a Load's result RegMask for memoization in idealreg2regmask[]
1518 MachNode *Matcher::match_tree( const Node *n ) {
1519   assert( n->Opcode() != Op_Phi, "cannot match" );
1520   assert( !n->is_block_start(), "cannot match" );
1521   // Set the mark for all locally allocated State objects.
1522   // When this call returns, the _states_arena arena will be reset
1523   // freeing all State objects.
1524   ResourceMark rm( &_states_arena );
1525 
1526   LabelRootDepth = 0;
1527 
1528   // StoreNodes require their Memory input to match any LoadNodes
1529   Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1530 #ifdef ASSERT
1531   Node* save_mem_node = _mem_node;
1532   _mem_node = n->is_Store() ? (Node*)n : NULL;
1533 #endif
1534   // State object for root node of match tree
1535   // Allocate it on _states_arena - stack allocation can cause stack overflow.
1536   State *s = new (&_states_arena) State;
1537   s->_kids[0] = NULL;
1538   s->_kids[1] = NULL;
1539   s->_leaf = (Node*)n;
1540   // Label the input tree, allocating labels from top-level arena
1541   Node* root_mem = mem;
1542   Label_Root(n, s, n->in(0), root_mem);
1543   if (C->failing())  return NULL;
1544 
1545   // The minimum cost match for the whole tree is found at the root State
1546   uint mincost = max_juint;
1547   uint cost = max_juint;
1548   uint i;
1549   for (i = 0; i < NUM_OPERANDS; i++) {
1550     if (s->valid(i) &&               // valid entry and
1551         s->cost(i) < cost &&         // low cost and
1552         s->rule(i) >= NUM_OPERANDS) {// not an operand
1553       mincost = i;
1554       cost = s->cost(i);
1555     }
1556   }
1557   if (mincost == max_juint) {
1558 #ifndef PRODUCT
1559     tty->print("No matching rule for:");
1560     s->dump();
1561 #endif
1562     Matcher::soft_match_failure();
1563     return NULL;
1564   }
1565   // Reduce input tree based upon the state labels to machine Nodes
1566   MachNode *m = ReduceInst(s, s->rule(mincost), mem);
1567   // New-to-old mapping is done in ReduceInst, to cover complex instructions.
1568   NOT_PRODUCT(_old2new_map.map(n->_idx, m);)
1569 
1570   // Add any Matcher-ignored edges
1571   uint cnt = n->req();
1572   uint start = 1;
1573   if( mem != (Node*)1 ) start = MemNode::Memory+1;
1574   if( n->is_AddP() ) {
1575     assert( mem == (Node*)1, "" );
1576     start = AddPNode::Base+1;
1577   }
1578   for( i = start; i < cnt; i++ ) {
1579     if( !n->match_edge(i) ) {
1580       if( i < m->req() )
1581         m->ins_req( i, n->in(i) );
1582       else
1583         m->add_req( n->in(i) );
1584     }
1585   }
1586 
1587   debug_only( _mem_node = save_mem_node; )
1588   return m;
1589 }
1590 
1591 
1592 //------------------------------match_into_reg---------------------------------
1593 // Choose to either match this Node in a register or part of the current
1594 // match tree.  Return true for requiring a register and false for matching
1595 // as part of the current match tree.
1596 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1597 
1598   const Type *t = m->bottom_type();
1599 
1600   if (t->singleton()) {
1601     // Never force constants into registers.  Allow them to match as
1602     // constants or registers.  Copies of the same value will share
1603     // the same register.  See find_shared_node.
1604     return false;
1605   } else {                      // Not a constant
1606     // Stop recursion if they have different Controls.
1607     Node* m_control = m->in(0);
1608     // Control of load's memory can post-dominates load's control.
1609     // So use it since load can't float above its memory.
1610     Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1611     if (control && m_control && control != m_control && control != mem_control) {
1612 
1613       // Actually, we can live with the most conservative control we
1614       // find, if it post-dominates the others.  This allows us to
1615       // pick up load/op/store trees where the load can float a little
1616       // above the store.
1617       Node *x = control;
1618       const uint max_scan = 6;  // Arbitrary scan cutoff
1619       uint j;
1620       for (j=0; j<max_scan; j++) {
1621         if (x->is_Region())     // Bail out at merge points
1622           return true;
1623         x = x->in(0);
1624         if (x == m_control)     // Does 'control' post-dominate
1625           break;                // m->in(0)?  If so, we can use it
1626         if (x == mem_control)   // Does 'control' post-dominate
1627           break;                // mem_control?  If so, we can use it
1628       }
1629       if (j == max_scan)        // No post-domination before scan end?
1630         return true;            // Then break the match tree up
1631     }
1632     if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1633         (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1634       // These are commonly used in address expressions and can
1635       // efficiently fold into them on X64 in some cases.
1636       return false;
1637     }
1638   }
1639 
1640   // Not forceable cloning.  If shared, put it into a register.
1641   return shared;
1642 }
1643 
1644 
1645 //------------------------------Instruction Selection--------------------------
1646 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1647 // ideal nodes to machine instructions.  Trees are delimited by shared Nodes,
1648 // things the Matcher does not match (e.g., Memory), and things with different
1649 // Controls (hence forced into different blocks).  We pass in the Control
1650 // selected for this entire State tree.
1651 
1652 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1653 // Store and the Load must have identical Memories (as well as identical
1654 // pointers).  Since the Matcher does not have anything for Memory (and
1655 // does not handle DAGs), I have to match the Memory input myself.  If the
1656 // Tree root is a Store or if there are multiple Loads in the tree, I require
1657 // all Loads to have the identical memory.
1658 Node* Matcher::Label_Root(const Node* n, State* svec, Node* control, Node*& mem) {
1659   // Since Label_Root is a recursive function, its possible that we might run
1660   // out of stack space.  See bugs 6272980 & 6227033 for more info.
1661   LabelRootDepth++;
1662   if (LabelRootDepth > MaxLabelRootDepth) {
1663     C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1664     return NULL;
1665   }
1666   uint care = 0;                // Edges matcher cares about
1667   uint cnt = n->req();
1668   uint i = 0;
1669 
1670   // Examine children for memory state
1671   // Can only subsume a child into your match-tree if that child's memory state
1672   // is not modified along the path to another input.
1673   // It is unsafe even if the other inputs are separate roots.
1674   Node *input_mem = NULL;
1675   for( i = 1; i < cnt; i++ ) {
1676     if( !n->match_edge(i) ) continue;
1677     Node *m = n->in(i);         // Get ith input
1678     assert( m, "expect non-null children" );
1679     if( m->is_Load() ) {
1680       if( input_mem == NULL ) {
1681         input_mem = m->in(MemNode::Memory);
1682         if (mem == (Node*)1) {
1683           // Save this memory to bail out if there's another memory access
1684           // to a different memory location in the same tree.
1685           mem = input_mem;
1686         }
1687       } else if( input_mem != m->in(MemNode::Memory) ) {
1688         input_mem = NodeSentinel;
1689       }
1690     }
1691   }
1692 
1693   for( i = 1; i < cnt; i++ ){// For my children
1694     if( !n->match_edge(i) ) continue;
1695     Node *m = n->in(i);         // Get ith input
1696     // Allocate states out of a private arena
1697     State *s = new (&_states_arena) State;
1698     svec->_kids[care++] = s;
1699     assert( care <= 2, "binary only for now" );
1700 
1701     // Recursively label the State tree.
1702     s->_kids[0] = NULL;
1703     s->_kids[1] = NULL;
1704     s->_leaf = m;
1705 
1706     // Check for leaves of the State Tree; things that cannot be a part of
1707     // the current tree.  If it finds any, that value is matched as a
1708     // register operand.  If not, then the normal matching is used.
1709     if( match_into_reg(n, m, control, i, is_shared(m)) ||
1710         // Stop recursion if this is a LoadNode and there is another memory access
1711         // to a different memory location in the same tree (for example, a StoreNode
1712         // at the root of this tree or another LoadNode in one of the children).
1713         ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1714         // Can NOT include the match of a subtree when its memory state
1715         // is used by any of the other subtrees
1716         (input_mem == NodeSentinel) ) {
1717       // Print when we exclude matching due to different memory states at input-loads
1718       if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1719           && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1720         tty->print_cr("invalid input_mem");
1721       }
1722       // Switch to a register-only opcode; this value must be in a register
1723       // and cannot be subsumed as part of a larger instruction.
1724       s->DFA( m->ideal_reg(), m );
1725 
1726     } else {
1727       // If match tree has no control and we do, adopt it for entire tree
1728       if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1729         control = m->in(0);         // Pick up control
1730       // Else match as a normal part of the match tree.
1731       control = Label_Root(m, s, control, mem);
1732       if (C->failing()) return NULL;
1733     }
1734   }
1735 
1736   // Call DFA to match this node, and return
1737   svec->DFA( n->Opcode(), n );
1738 
1739 #ifdef ASSERT
1740   uint x;
1741   for( x = 0; x < _LAST_MACH_OPER; x++ )
1742     if( svec->valid(x) )
1743       break;
1744 
1745   if (x >= _LAST_MACH_OPER) {
1746     n->dump();
1747     svec->dump();
1748     assert( false, "bad AD file" );
1749   }
1750 #endif
1751   return control;
1752 }
1753 
1754 
1755 // Con nodes reduced using the same rule can share their MachNode
1756 // which reduces the number of copies of a constant in the final
1757 // program.  The register allocator is free to split uses later to
1758 // split live ranges.
1759 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1760   if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1761 
1762   // See if this Con has already been reduced using this rule.
1763   if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1764   MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1765   if (last != NULL && rule == last->rule()) {
1766     // Don't expect control change for DecodeN
1767     if (leaf->is_DecodeNarrowPtr())
1768       return last;
1769     // Get the new space root.
1770     Node* xroot = new_node(C->root());
1771     if (xroot == NULL) {
1772       // This shouldn't happen give the order of matching.
1773       return NULL;
1774     }
1775 
1776     // Shared constants need to have their control be root so they
1777     // can be scheduled properly.
1778     Node* control = last->in(0);
1779     if (control != xroot) {
1780       if (control == NULL || control == C->root()) {
1781         last->set_req(0, xroot);
1782       } else {
1783         assert(false, "unexpected control");
1784         return NULL;
1785       }
1786     }
1787     return last;
1788   }
1789   return NULL;
1790 }
1791 
1792 
1793 //------------------------------ReduceInst-------------------------------------
1794 // Reduce a State tree (with given Control) into a tree of MachNodes.
1795 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1796 // complicated machine Nodes.  Each MachNode covers some tree of Ideal Nodes.
1797 // Each MachNode has a number of complicated MachOper operands; each
1798 // MachOper also covers a further tree of Ideal Nodes.
1799 
1800 // The root of the Ideal match tree is always an instruction, so we enter
1801 // the recursion here.  After building the MachNode, we need to recurse
1802 // the tree checking for these cases:
1803 // (1) Child is an instruction -
1804 //     Build the instruction (recursively), add it as an edge.
1805 //     Build a simple operand (register) to hold the result of the instruction.
1806 // (2) Child is an interior part of an instruction -
1807 //     Skip over it (do nothing)
1808 // (3) Child is the start of a operand -
1809 //     Build the operand, place it inside the instruction
1810 //     Call ReduceOper.
1811 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1812   assert( rule >= NUM_OPERANDS, "called with operand rule" );
1813 
1814   MachNode* shared_node = find_shared_node(s->_leaf, rule);
1815   if (shared_node != NULL) {
1816     return shared_node;
1817   }
1818 
1819   // Build the object to represent this state & prepare for recursive calls
1820   MachNode *mach = s->MachNodeGenerator(rule);
1821   guarantee(mach != NULL, "Missing MachNode");
1822   mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1823   assert( mach->_opnds[0] != NULL, "Missing result operand" );
1824   Node *leaf = s->_leaf;
1825   NOT_PRODUCT(record_new2old(mach, leaf);)
1826   // Check for instruction or instruction chain rule
1827   if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1828     assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1829            "duplicating node that's already been matched");
1830     // Instruction
1831     mach->add_req( leaf->in(0) ); // Set initial control
1832     // Reduce interior of complex instruction
1833     ReduceInst_Interior( s, rule, mem, mach, 1 );
1834   } else {
1835     // Instruction chain rules are data-dependent on their inputs
1836     mach->add_req(0);             // Set initial control to none
1837     ReduceInst_Chain_Rule( s, rule, mem, mach );
1838   }
1839 
1840   // If a Memory was used, insert a Memory edge
1841   if( mem != (Node*)1 ) {
1842     mach->ins_req(MemNode::Memory,mem);
1843 #ifdef ASSERT
1844     // Verify adr type after matching memory operation
1845     const MachOper* oper = mach->memory_operand();
1846     if (oper != NULL && oper != (MachOper*)-1) {
1847       // It has a unique memory operand.  Find corresponding ideal mem node.
1848       Node* m = NULL;
1849       if (leaf->is_Mem()) {
1850         m = leaf;
1851       } else {
1852         m = _mem_node;
1853         assert(m != NULL && m->is_Mem(), "expecting memory node");
1854       }
1855       const Type* mach_at = mach->adr_type();
1856       // DecodeN node consumed by an address may have different type
1857       // than its input. Don't compare types for such case.
1858       if (m->adr_type() != mach_at &&
1859           (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1860            (m->in(MemNode::Address)->is_AddP() &&
1861             m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) ||
1862            (m->in(MemNode::Address)->is_AddP() &&
1863             m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1864             m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) {
1865         mach_at = m->adr_type();
1866       }
1867       if (m->adr_type() != mach_at) {
1868         m->dump();
1869         tty->print_cr("mach:");
1870         mach->dump(1);
1871       }
1872       assert(m->adr_type() == mach_at, "matcher should not change adr type");
1873     }
1874 #endif
1875   }
1876 
1877   // If the _leaf is an AddP, insert the base edge
1878   if (leaf->is_AddP()) {
1879     mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1880   }
1881 
1882   uint number_of_projections_prior = number_of_projections();
1883 
1884   // Perform any 1-to-many expansions required
1885   MachNode *ex = mach->Expand(s, _projection_list, mem);
1886   if (ex != mach) {
1887     assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1888     if( ex->in(1)->is_Con() )
1889       ex->in(1)->set_req(0, C->root());
1890     // Remove old node from the graph
1891     for( uint i=0; i<mach->req(); i++ ) {
1892       mach->set_req(i,NULL);
1893     }
1894     NOT_PRODUCT(record_new2old(ex, s->_leaf);)
1895   }
1896 
1897   // PhaseChaitin::fixup_spills will sometimes generate spill code
1898   // via the matcher.  By the time, nodes have been wired into the CFG,
1899   // and any further nodes generated by expand rules will be left hanging
1900   // in space, and will not get emitted as output code.  Catch this.
1901   // Also, catch any new register allocation constraints ("projections")
1902   // generated belatedly during spill code generation.
1903   if (_allocation_started) {
1904     guarantee(ex == mach, "no expand rules during spill generation");
1905     guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1906   }
1907 
1908   if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1909     // Record the con for sharing
1910     _shared_nodes.map(leaf->_idx, ex);
1911   }
1912 
1913   // Have mach nodes inherit GC barrier data
1914   if (leaf->is_LoadStore()) {
1915     mach->set_barrier_data(leaf->as_LoadStore()->barrier_data());
1916   } else if (leaf->is_Mem()) {
1917     mach->set_barrier_data(leaf->as_Mem()->barrier_data());
1918   }
1919 
1920   return ex;
1921 }
1922 
1923 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1924   for (uint i = n->req(); i < n->len(); i++) {
1925     if (n->in(i) != NULL) {
1926       mach->add_prec(n->in(i));
1927     }
1928   }
1929 }
1930 
1931 void Matcher::ReduceInst_Chain_Rule(State* s, int rule, Node* &mem, MachNode* mach) {
1932   // 'op' is what I am expecting to receive
1933   int op = _leftOp[rule];
1934   // Operand type to catch childs result
1935   // This is what my child will give me.
1936   unsigned int opnd_class_instance = s->rule(op);
1937   // Choose between operand class or not.
1938   // This is what I will receive.
1939   int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1940   // New rule for child.  Chase operand classes to get the actual rule.
1941   unsigned int newrule = s->rule(catch_op);
1942 
1943   if (newrule < NUM_OPERANDS) {
1944     // Chain from operand or operand class, may be output of shared node
1945     assert(opnd_class_instance < NUM_OPERANDS, "Bad AD file: Instruction chain rule must chain from operand");
1946     // Insert operand into array of operands for this instruction
1947     mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1948 
1949     ReduceOper(s, newrule, mem, mach);
1950   } else {
1951     // Chain from the result of an instruction
1952     assert(newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1953     mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1954     Node *mem1 = (Node*)1;
1955     debug_only(Node *save_mem_node = _mem_node;)
1956     mach->add_req( ReduceInst(s, newrule, mem1) );
1957     debug_only(_mem_node = save_mem_node;)
1958   }
1959   return;
1960 }
1961 
1962 
1963 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1964   handle_precedence_edges(s->_leaf, mach);
1965 
1966   if( s->_leaf->is_Load() ) {
1967     Node *mem2 = s->_leaf->in(MemNode::Memory);
1968     assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1969     debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1970     mem = mem2;
1971   }
1972   if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1973     if( mach->in(0) == NULL )
1974       mach->set_req(0, s->_leaf->in(0));
1975   }
1976 
1977   // Now recursively walk the state tree & add operand list.
1978   for( uint i=0; i<2; i++ ) {   // binary tree
1979     State *newstate = s->_kids[i];
1980     if( newstate == NULL ) break;      // Might only have 1 child
1981     // 'op' is what I am expecting to receive
1982     int op;
1983     if( i == 0 ) {
1984       op = _leftOp[rule];
1985     } else {
1986       op = _rightOp[rule];
1987     }
1988     // Operand type to catch childs result
1989     // This is what my child will give me.
1990     int opnd_class_instance = newstate->rule(op);
1991     // Choose between operand class or not.
1992     // This is what I will receive.
1993     int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1994     // New rule for child.  Chase operand classes to get the actual rule.
1995     int newrule = newstate->rule(catch_op);
1996 
1997     if (newrule < NUM_OPERANDS) { // Operand/operandClass or internalOp/instruction?
1998       // Operand/operandClass
1999       // Insert operand into array of operands for this instruction
2000       mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
2001       ReduceOper(newstate, newrule, mem, mach);
2002 
2003     } else {                    // Child is internal operand or new instruction
2004       if (newrule < _LAST_MACH_OPER) { // internal operand or instruction?
2005         // internal operand --> call ReduceInst_Interior
2006         // Interior of complex instruction.  Do nothing but recurse.
2007         num_opnds = ReduceInst_Interior(newstate, newrule, mem, mach, num_opnds);
2008       } else {
2009         // instruction --> call build operand(  ) to catch result
2010         //             --> ReduceInst( newrule )
2011         mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
2012         Node *mem1 = (Node*)1;
2013         debug_only(Node *save_mem_node = _mem_node;)
2014         mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
2015         debug_only(_mem_node = save_mem_node;)
2016       }
2017     }
2018     assert( mach->_opnds[num_opnds-1], "" );
2019   }
2020   return num_opnds;
2021 }
2022 
2023 // This routine walks the interior of possible complex operands.
2024 // At each point we check our children in the match tree:
2025 // (1) No children -
2026 //     We are a leaf; add _leaf field as an input to the MachNode
2027 // (2) Child is an internal operand -
2028 //     Skip over it ( do nothing )
2029 // (3) Child is an instruction -
2030 //     Call ReduceInst recursively and
2031 //     and instruction as an input to the MachNode
2032 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
2033   assert( rule < _LAST_MACH_OPER, "called with operand rule" );
2034   State *kid = s->_kids[0];
2035   assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
2036 
2037   // Leaf?  And not subsumed?
2038   if( kid == NULL && !_swallowed[rule] ) {
2039     mach->add_req( s->_leaf );  // Add leaf pointer
2040     return;                     // Bail out
2041   }
2042 
2043   if( s->_leaf->is_Load() ) {
2044     assert( mem == (Node*)1, "multiple Memories being matched at once?" );
2045     mem = s->_leaf->in(MemNode::Memory);
2046     debug_only(_mem_node = s->_leaf;)
2047   }
2048 
2049   handle_precedence_edges(s->_leaf, mach);
2050 
2051   if( s->_leaf->in(0) && s->_leaf->req() > 1) {
2052     if( !mach->in(0) )
2053       mach->set_req(0,s->_leaf->in(0));
2054     else {
2055       assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
2056     }
2057   }
2058 
2059   for (uint i = 0; kid != NULL && i < 2; kid = s->_kids[1], i++) {   // binary tree
2060     int newrule;
2061     if( i == 0) {
2062       newrule = kid->rule(_leftOp[rule]);
2063     } else {
2064       newrule = kid->rule(_rightOp[rule]);
2065     }
2066 
2067     if (newrule < _LAST_MACH_OPER) { // Operand or instruction?
2068       // Internal operand; recurse but do nothing else
2069       ReduceOper(kid, newrule, mem, mach);
2070 
2071     } else {                    // Child is a new instruction
2072       // Reduce the instruction, and add a direct pointer from this
2073       // machine instruction to the newly reduced one.
2074       Node *mem1 = (Node*)1;
2075       debug_only(Node *save_mem_node = _mem_node;)
2076       mach->add_req( ReduceInst( kid, newrule, mem1 ) );
2077       debug_only(_mem_node = save_mem_node;)
2078     }
2079   }
2080 }
2081 
2082 
2083 // -------------------------------------------------------------------------
2084 // Java-Java calling convention
2085 // (what you use when Java calls Java)
2086 
2087 //------------------------------find_receiver----------------------------------
2088 // For a given signature, return the OptoReg for parameter 0.
2089 OptoReg::Name Matcher::find_receiver() {
2090   VMRegPair regs;
2091   BasicType sig_bt = T_OBJECT;
2092   SharedRuntime::java_calling_convention(&sig_bt, &regs, 1);
2093   // Return argument 0 register.  In the LP64 build pointers
2094   // take 2 registers, but the VM wants only the 'main' name.
2095   return OptoReg::as_OptoReg(regs.first());
2096 }
2097 
2098 bool Matcher::is_vshift_con_pattern(Node* n, Node* m) {
2099   if (n != NULL && m != NULL) {
2100     return VectorNode::is_vector_shift(n) &&
2101            VectorNode::is_vector_shift_count(m) && m->in(1)->is_Con();
2102   }
2103   return false;
2104 }
2105 
2106 bool Matcher::clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2107   // Must clone all producers of flags, or we will not match correctly.
2108   // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2109   // then it will match into an ideal Op_RegFlags.  Alas, the fp-flags
2110   // are also there, so we may match a float-branch to int-flags and
2111   // expect the allocator to haul the flags from the int-side to the
2112   // fp-side.  No can do.
2113   if (_must_clone[m->Opcode()]) {
2114     mstack.push(m, Visit);
2115     return true;
2116   }
2117   return pd_clone_node(n, m, mstack);
2118 }
2119 
2120 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2121   Node *off = m->in(AddPNode::Offset);
2122   if (off->is_Con()) {
2123     address_visited.test_set(m->_idx); // Flag as address_visited
2124     mstack.push(m->in(AddPNode::Address), Pre_Visit);
2125     // Clone X+offset as it also folds into most addressing expressions
2126     mstack.push(off, Visit);
2127     mstack.push(m->in(AddPNode::Base), Pre_Visit);
2128     return true;
2129   }
2130   return false;
2131 }
2132 
2133 // A method-klass-holder may be passed in the inline_cache_reg
2134 // and then expanded into the inline_cache_reg and a method_ptr register
2135 //   defined in ad_<arch>.cpp
2136 
2137 //------------------------------find_shared------------------------------------
2138 // Set bits if Node is shared or otherwise a root
2139 void Matcher::find_shared(Node* n) {
2140   // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2141   MStack mstack(C->live_nodes() * 2);
2142   // Mark nodes as address_visited if they are inputs to an address expression
2143   VectorSet address_visited;
2144   mstack.push(n, Visit);     // Don't need to pre-visit root node
2145   while (mstack.is_nonempty()) {
2146     n = mstack.node();       // Leave node on stack
2147     Node_State nstate = mstack.state();
2148     uint nop = n->Opcode();
2149     if (nstate == Pre_Visit) {
2150       if (address_visited.test(n->_idx)) { // Visited in address already?
2151         // Flag as visited and shared now.
2152         set_visited(n);
2153       }
2154       if (is_visited(n)) {   // Visited already?
2155         // Node is shared and has no reason to clone.  Flag it as shared.
2156         // This causes it to match into a register for the sharing.
2157         set_shared(n);       // Flag as shared and
2158         if (n->is_DecodeNarrowPtr()) {
2159           // Oop field/array element loads must be shared but since
2160           // they are shared through a DecodeN they may appear to have
2161           // a single use so force sharing here.
2162           set_shared(n->in(1));
2163         }
2164         mstack.pop();        // remove node from stack
2165         continue;
2166       }
2167       nstate = Visit; // Not already visited; so visit now
2168     }
2169     if (nstate == Visit) {
2170       mstack.set_state(Post_Visit);
2171       set_visited(n);   // Flag as visited now
2172       bool mem_op = false;
2173       int mem_addr_idx = MemNode::Address;
2174       if (find_shared_visit(mstack, n, nop, mem_op, mem_addr_idx)) {
2175         continue;
2176       }
2177       for (int i = n->len() - 1; i >= 0; --i) { // For my children
2178         Node* m = n->in(i); // Get ith input
2179         if (m == NULL) {
2180           continue;  // Ignore NULLs
2181         }
2182         if (clone_node(n, m, mstack)) {
2183           continue;
2184         }
2185 
2186         // Clone addressing expressions as they are "free" in memory access instructions
2187         if (mem_op && i == mem_addr_idx && m->is_AddP() &&
2188             // When there are other uses besides address expressions
2189             // put it on stack and mark as shared.
2190             !is_visited(m)) {
2191           // Some inputs for address expression are not put on stack
2192           // to avoid marking them as shared and forcing them into register
2193           // if they are used only in address expressions.
2194           // But they should be marked as shared if there are other uses
2195           // besides address expressions.
2196 
2197           if (pd_clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2198             continue;
2199           }
2200         }   // if( mem_op &&
2201         mstack.push(m, Pre_Visit);
2202       }     // for(int i = ...)
2203     }
2204     else if (nstate == Alt_Post_Visit) {
2205       mstack.pop(); // Remove node from stack
2206       // We cannot remove the Cmp input from the Bool here, as the Bool may be
2207       // shared and all users of the Bool need to move the Cmp in parallel.
2208       // This leaves both the Bool and the If pointing at the Cmp.  To
2209       // prevent the Matcher from trying to Match the Cmp along both paths
2210       // BoolNode::match_edge always returns a zero.
2211 
2212       // We reorder the Op_If in a pre-order manner, so we can visit without
2213       // accidentally sharing the Cmp (the Bool and the If make 2 users).
2214       n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2215     }
2216     else if (nstate == Post_Visit) {
2217       mstack.pop(); // Remove node from stack
2218 
2219       // Now hack a few special opcodes
2220       uint opcode = n->Opcode();
2221       bool gc_handled = BarrierSet::barrier_set()->barrier_set_c2()->matcher_find_shared_post_visit(this, n, opcode);
2222       if (!gc_handled) {
2223         find_shared_post_visit(n, opcode);
2224       }
2225     }
2226     else {
2227       ShouldNotReachHere();
2228     }
2229   } // end of while (mstack.is_nonempty())
2230 }
2231 
2232 bool Matcher::find_shared_visit(MStack& mstack, Node* n, uint opcode, bool& mem_op, int& mem_addr_idx) {
2233   switch(opcode) {  // Handle some opcodes special
2234     case Op_Phi:             // Treat Phis as shared roots
2235     case Op_Parm:
2236     case Op_Proj:            // All handled specially during matching
2237     case Op_SafePointScalarObject:
2238       set_shared(n);
2239       set_dontcare(n);
2240       break;
2241     case Op_If:
2242     case Op_CountedLoopEnd:
2243       mstack.set_state(Alt_Post_Visit); // Alternative way
2244       // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)).  Helps
2245       // with matching cmp/branch in 1 instruction.  The Matcher needs the
2246       // Bool and CmpX side-by-side, because it can only get at constants
2247       // that are at the leaves of Match trees, and the Bool's condition acts
2248       // as a constant here.
2249       mstack.push(n->in(1), Visit);         // Clone the Bool
2250       mstack.push(n->in(0), Pre_Visit);     // Visit control input
2251       return true; // while (mstack.is_nonempty())
2252     case Op_ConvI2D:         // These forms efficiently match with a prior
2253     case Op_ConvI2F:         //   Load but not a following Store
2254       if( n->in(1)->is_Load() &&        // Prior load
2255           n->outcnt() == 1 &&           // Not already shared
2256           n->unique_out()->is_Store() ) // Following store
2257         set_shared(n);       // Force it to be a root
2258       break;
2259     case Op_ReverseBytesI:
2260     case Op_ReverseBytesL:
2261       if( n->in(1)->is_Load() &&        // Prior load
2262           n->outcnt() == 1 )            // Not already shared
2263         set_shared(n);                  // Force it to be a root
2264       break;
2265     case Op_BoxLock:         // Can't match until we get stack-regs in ADLC
2266     case Op_IfFalse:
2267     case Op_IfTrue:
2268     case Op_MachProj:
2269     case Op_MergeMem:
2270     case Op_Catch:
2271     case Op_CatchProj:
2272     case Op_CProj:
2273     case Op_JumpProj:
2274     case Op_JProj:
2275     case Op_NeverBranch:
2276       set_dontcare(n);
2277       break;
2278     case Op_Jump:
2279       mstack.push(n->in(1), Pre_Visit);     // Switch Value (could be shared)
2280       mstack.push(n->in(0), Pre_Visit);     // Visit Control input
2281       return true;                             // while (mstack.is_nonempty())
2282     case Op_StrComp:
2283     case Op_StrEquals:
2284     case Op_StrIndexOf:
2285     case Op_StrIndexOfChar:
2286     case Op_AryEq:
2287     case Op_CountPositives:
2288     case Op_StrInflatedCopy:
2289     case Op_StrCompressedCopy:
2290     case Op_EncodeISOArray:
2291     case Op_FmaD:
2292     case Op_FmaF:
2293     case Op_FmaVD:
2294     case Op_FmaVF:
2295     case Op_MacroLogicV:
2296     case Op_VectorCmpMasked:
2297     case Op_CompressV:
2298     case Op_CompressM:
2299     case Op_ExpandV:
2300     case Op_VectorLoadMask:
2301       set_shared(n); // Force result into register (it will be anyways)
2302       break;
2303     case Op_ConP: {  // Convert pointers above the centerline to NUL
2304       TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2305       const TypePtr* tp = tn->type()->is_ptr();
2306       if (tp->_ptr == TypePtr::AnyNull) {
2307         tn->set_type(TypePtr::NULL_PTR);
2308       }
2309       break;
2310     }
2311     case Op_ConN: {  // Convert narrow pointers above the centerline to NUL
2312       TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2313       const TypePtr* tp = tn->type()->make_ptr();
2314       if (tp && tp->_ptr == TypePtr::AnyNull) {
2315         tn->set_type(TypeNarrowOop::NULL_PTR);
2316       }
2317       break;
2318     }
2319     case Op_Binary:         // These are introduced in the Post_Visit state.
2320       ShouldNotReachHere();
2321       break;
2322     case Op_ClearArray:
2323     case Op_SafePoint:
2324       mem_op = true;
2325       break;
2326     default:
2327       if( n->is_Store() ) {
2328         // Do match stores, despite no ideal reg
2329         mem_op = true;
2330         break;
2331       }
2332       if( n->is_Mem() ) { // Loads and LoadStores
2333         mem_op = true;
2334         // Loads must be root of match tree due to prior load conflict
2335         if( C->subsume_loads() == false )
2336           set_shared(n);
2337       }
2338       // Fall into default case
2339       if( !n->ideal_reg() )
2340         set_dontcare(n);  // Unmatchable Nodes
2341   } // end_switch
2342   return false;
2343 }
2344 
2345 void Matcher::find_shared_post_visit(Node* n, uint opcode) {
2346   if (n->is_predicated_vector()) {
2347     // Restructure into binary trees for Matching.
2348     if (n->req() == 4) {
2349       n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2350       n->set_req(2, n->in(3));
2351       n->del_req(3);
2352     } else if (n->req() == 5) {
2353       n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2354       n->set_req(2, new BinaryNode(n->in(3), n->in(4)));
2355       n->del_req(4);
2356       n->del_req(3);
2357     } else if (n->req() == 6) {
2358       Node* b3 = new BinaryNode(n->in(4), n->in(5));
2359       Node* b2 = new BinaryNode(n->in(3), b3);
2360       Node* b1 = new BinaryNode(n->in(2), b2);
2361       n->set_req(2, b1);
2362       n->del_req(5);
2363       n->del_req(4);
2364       n->del_req(3);
2365     }
2366     return;
2367   }
2368 
2369   switch(opcode) {       // Handle some opcodes special
2370     case Op_CompareAndExchangeB:
2371     case Op_CompareAndExchangeS:
2372     case Op_CompareAndExchangeI:
2373     case Op_CompareAndExchangeL:
2374     case Op_CompareAndExchangeP:
2375     case Op_CompareAndExchangeN:
2376     case Op_WeakCompareAndSwapB:
2377     case Op_WeakCompareAndSwapS:
2378     case Op_WeakCompareAndSwapI:
2379     case Op_WeakCompareAndSwapL:
2380     case Op_WeakCompareAndSwapP:
2381     case Op_WeakCompareAndSwapN:
2382     case Op_CompareAndSwapB:
2383     case Op_CompareAndSwapS:
2384     case Op_CompareAndSwapI:
2385     case Op_CompareAndSwapL:
2386     case Op_CompareAndSwapP:
2387     case Op_CompareAndSwapN: {   // Convert trinary to binary-tree
2388       Node* newval = n->in(MemNode::ValueIn);
2389       Node* oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2390       Node* pair = new BinaryNode(oldval, newval);
2391       n->set_req(MemNode::ValueIn, pair);
2392       n->del_req(LoadStoreConditionalNode::ExpectedIn);
2393       break;
2394     }
2395     case Op_CMoveD:              // Convert trinary to binary-tree
2396     case Op_CMoveF:
2397     case Op_CMoveI:
2398     case Op_CMoveL:
2399     case Op_CMoveN:
2400     case Op_CMoveP: {
2401       // Restructure into a binary tree for Matching.  It's possible that
2402       // we could move this code up next to the graph reshaping for IfNodes
2403       // or vice-versa, but I do not want to debug this for Ladybird.
2404       // 10/2/2000 CNC.
2405       Node* pair1 = new BinaryNode(n->in(1), n->in(1)->in(1));
2406       n->set_req(1, pair1);
2407       Node* pair2 = new BinaryNode(n->in(2), n->in(3));
2408       n->set_req(2, pair2);
2409       n->del_req(3);
2410       break;
2411     }
2412     case Op_CMoveVF:
2413     case Op_CMoveVD: {
2414       // Restructure into a binary tree for Matching:
2415       // CMoveVF (Binary bool mask) (Binary src1 src2)
2416       Node* in_cc = n->in(1);
2417       assert(in_cc->is_Con(), "The condition input of cmove vector node must be a constant.");
2418       Node* bol = new BoolNode(in_cc, (BoolTest::mask)in_cc->get_int());
2419       Node* pair1 = new BinaryNode(bol, in_cc);
2420       n->set_req(1, pair1);
2421       Node* pair2 = new BinaryNode(n->in(2), n->in(3));
2422       n->set_req(2, pair2);
2423       n->del_req(3);
2424       break;
2425     }
2426     case Op_VectorCmpMasked: {
2427       Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2428       n->set_req(2, pair1);
2429       n->del_req(3);
2430       break;
2431     }
2432     case Op_MacroLogicV: {
2433       Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2434       Node* pair2 = new BinaryNode(n->in(3), n->in(4));
2435       n->set_req(1, pair1);
2436       n->set_req(2, pair2);
2437       n->del_req(4);
2438       n->del_req(3);
2439       break;
2440     }
2441     case Op_StoreVectorMasked: {
2442       Node* pair = new BinaryNode(n->in(3), n->in(4));
2443       n->set_req(3, pair);
2444       n->del_req(4);
2445       break;
2446     }
2447     case Op_LoopLimit: {
2448       Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2449       n->set_req(1, pair1);
2450       n->set_req(2, n->in(3));
2451       n->del_req(3);
2452       break;
2453     }
2454     case Op_StrEquals:
2455     case Op_StrIndexOfChar: {
2456       Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2457       n->set_req(2, pair1);
2458       n->set_req(3, n->in(4));
2459       n->del_req(4);
2460       break;
2461     }
2462     case Op_StrComp:
2463     case Op_StrIndexOf: {
2464       Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2465       n->set_req(2, pair1);
2466       Node* pair2 = new BinaryNode(n->in(4),n->in(5));
2467       n->set_req(3, pair2);
2468       n->del_req(5);
2469       n->del_req(4);
2470       break;
2471     }
2472     case Op_StrCompressedCopy:
2473     case Op_StrInflatedCopy:
2474     case Op_EncodeISOArray: {
2475       // Restructure into a binary tree for Matching.
2476       Node* pair = new BinaryNode(n->in(3), n->in(4));
2477       n->set_req(3, pair);
2478       n->del_req(4);
2479       break;
2480     }
2481     case Op_FmaD:
2482     case Op_FmaF:
2483     case Op_FmaVD:
2484     case Op_FmaVF: {
2485       // Restructure into a binary tree for Matching.
2486       Node* pair = new BinaryNode(n->in(1), n->in(2));
2487       n->set_req(2, pair);
2488       n->set_req(1, n->in(3));
2489       n->del_req(3);
2490       break;
2491     }
2492     case Op_MulAddS2I: {
2493       Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2494       Node* pair2 = new BinaryNode(n->in(3), n->in(4));
2495       n->set_req(1, pair1);
2496       n->set_req(2, pair2);
2497       n->del_req(4);
2498       n->del_req(3);
2499       break;
2500     }
2501     case Op_ClearArray: {
2502       Node* pair = new BinaryNode(n->in(2), n->in(3));
2503       n->set_req(2, pair);
2504       n->set_req(3, n->in(4));
2505       n->del_req(4);
2506       break;
2507     }
2508     case Op_CopySignD:
2509     case Op_SignumVF:
2510     case Op_SignumVD:
2511     case Op_SignumF:
2512     case Op_SignumD: {
2513       Node* pair = new BinaryNode(n->in(2), n->in(3));
2514       n->set_req(2, pair);
2515       n->del_req(3);
2516       break;
2517     }
2518     case Op_VectorBlend:
2519     case Op_VectorInsert: {
2520       Node* pair = new BinaryNode(n->in(1), n->in(2));
2521       n->set_req(1, pair);
2522       n->set_req(2, n->in(3));
2523       n->del_req(3);
2524       break;
2525     }
2526     case Op_LoadVectorGatherMasked:
2527     case Op_StoreVectorScatter: {
2528       Node* pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2529       n->set_req(MemNode::ValueIn, pair);
2530       n->del_req(MemNode::ValueIn+1);
2531       break;
2532     }
2533     case Op_StoreVectorScatterMasked: {
2534       Node* pair = new BinaryNode(n->in(MemNode::ValueIn+1), n->in(MemNode::ValueIn+2));
2535       n->set_req(MemNode::ValueIn+1, pair);
2536       n->del_req(MemNode::ValueIn+2);
2537       pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2538       n->set_req(MemNode::ValueIn, pair);
2539       n->del_req(MemNode::ValueIn+1);
2540       break;
2541     }
2542     case Op_VectorMaskCmp: {
2543       n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2544       n->set_req(2, n->in(3));
2545       n->del_req(3);
2546       break;
2547     }
2548     default:
2549       break;
2550   }
2551 }
2552 
2553 #ifndef PRODUCT
2554 void Matcher::record_new2old(Node* newn, Node* old) {
2555   _new2old_map.map(newn->_idx, old);
2556   if (!_reused.test_set(old->_igv_idx)) {
2557     // Reuse the Ideal-level IGV identifier so that the node can be tracked
2558     // across matching. If there are multiple machine nodes expanded from the
2559     // same Ideal node, only one will reuse its IGV identifier.
2560     newn->_igv_idx = old->_igv_idx;
2561   }
2562 }
2563 
2564 // machine-independent root to machine-dependent root
2565 void Matcher::dump_old2new_map() {
2566   _old2new_map.dump();
2567 }
2568 #endif // !PRODUCT
2569 
2570 //---------------------------collect_null_checks-------------------------------
2571 // Find null checks in the ideal graph; write a machine-specific node for
2572 // it.  Used by later implicit-null-check handling.  Actually collects
2573 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2574 // value being tested.
2575 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2576   Node *iff = proj->in(0);
2577   if( iff->Opcode() == Op_If ) {
2578     // During matching If's have Bool & Cmp side-by-side
2579     BoolNode *b = iff->in(1)->as_Bool();
2580     Node *cmp = iff->in(2);
2581     int opc = cmp->Opcode();
2582     if (opc != Op_CmpP && opc != Op_CmpN) return;
2583 
2584     const Type* ct = cmp->in(2)->bottom_type();
2585     if (ct == TypePtr::NULL_PTR ||
2586         (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2587 
2588       bool push_it = false;
2589       if( proj->Opcode() == Op_IfTrue ) {
2590 #ifndef PRODUCT
2591         extern int all_null_checks_found;
2592         all_null_checks_found++;
2593 #endif
2594         if( b->_test._test == BoolTest::ne ) {
2595           push_it = true;
2596         }
2597       } else {
2598         assert( proj->Opcode() == Op_IfFalse, "" );
2599         if( b->_test._test == BoolTest::eq ) {
2600           push_it = true;
2601         }
2602       }
2603       if( push_it ) {
2604         _null_check_tests.push(proj);
2605         Node* val = cmp->in(1);
2606 #ifdef _LP64
2607         if (val->bottom_type()->isa_narrowoop() &&
2608             !Matcher::narrow_oop_use_complex_address()) {
2609           //
2610           // Look for DecodeN node which should be pinned to orig_proj.
2611           // On platforms (Sparc) which can not handle 2 adds
2612           // in addressing mode we have to keep a DecodeN node and
2613           // use it to do implicit NULL check in address.
2614           //
2615           // DecodeN node was pinned to non-null path (orig_proj) during
2616           // CastPP transformation in final_graph_reshaping_impl().
2617           //
2618           uint cnt = orig_proj->outcnt();
2619           for (uint i = 0; i < orig_proj->outcnt(); i++) {
2620             Node* d = orig_proj->raw_out(i);
2621             if (d->is_DecodeN() && d->in(1) == val) {
2622               val = d;
2623               val->set_req(0, NULL); // Unpin now.
2624               // Mark this as special case to distinguish from
2625               // a regular case: CmpP(DecodeN, NULL).
2626               val = (Node*)(((intptr_t)val) | 1);
2627               break;
2628             }
2629           }
2630         }
2631 #endif
2632         _null_check_tests.push(val);
2633       }
2634     }
2635   }
2636 }
2637 
2638 //---------------------------validate_null_checks------------------------------
2639 // Its possible that the value being NULL checked is not the root of a match
2640 // tree.  If so, I cannot use the value in an implicit null check.
2641 void Matcher::validate_null_checks( ) {
2642   uint cnt = _null_check_tests.size();
2643   for( uint i=0; i < cnt; i+=2 ) {
2644     Node *test = _null_check_tests[i];
2645     Node *val = _null_check_tests[i+1];
2646     bool is_decoden = ((intptr_t)val) & 1;
2647     val = (Node*)(((intptr_t)val) & ~1);
2648     if (has_new_node(val)) {
2649       Node* new_val = new_node(val);
2650       if (is_decoden) {
2651         assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2652         // Note: new_val may have a control edge if
2653         // the original ideal node DecodeN was matched before
2654         // it was unpinned in Matcher::collect_null_checks().
2655         // Unpin the mach node and mark it.
2656         new_val->set_req(0, NULL);
2657         new_val = (Node*)(((intptr_t)new_val) | 1);
2658       }
2659       // Is a match-tree root, so replace with the matched value
2660       _null_check_tests.map(i+1, new_val);
2661     } else {
2662       // Yank from candidate list
2663       _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2664       _null_check_tests.map(i,_null_check_tests[--cnt]);
2665       _null_check_tests.pop();
2666       _null_check_tests.pop();
2667       i-=2;
2668     }
2669   }
2670 }
2671 
2672 bool Matcher::gen_narrow_oop_implicit_null_checks() {
2673   // Advice matcher to perform null checks on the narrow oop side.
2674   // Implicit checks are not possible on the uncompressed oop side anyway
2675   // (at least not for read accesses).
2676   // Performs significantly better (especially on Power 6).
2677   if (!os::zero_page_read_protected()) {
2678     return true;
2679   }
2680   return CompressedOops::use_implicit_null_checks() &&
2681          (narrow_oop_use_complex_address() ||
2682           CompressedOops::base() != NULL);
2683 }
2684 
2685 // Compute RegMask for an ideal register.
2686 const RegMask* Matcher::regmask_for_ideal_register(uint ideal_reg, Node* ret) {
2687   const Type* t = Type::mreg2type[ideal_reg];
2688   if (t == NULL) {
2689     assert(ideal_reg >= Op_VecA && ideal_reg <= Op_VecZ, "not a vector: %d", ideal_reg);
2690     return NULL; // not supported
2691   }
2692   Node* fp  = ret->in(TypeFunc::FramePtr);
2693   Node* mem = ret->in(TypeFunc::Memory);
2694   const TypePtr* atp = TypePtr::BOTTOM;
2695   MemNode::MemOrd mo = MemNode::unordered;
2696 
2697   Node* spill;
2698   switch (ideal_reg) {
2699     case Op_RegN: spill = new LoadNNode(NULL, mem, fp, atp, t->is_narrowoop(), mo); break;
2700     case Op_RegI: spill = new LoadINode(NULL, mem, fp, atp, t->is_int(),       mo); break;
2701     case Op_RegP: spill = new LoadPNode(NULL, mem, fp, atp, t->is_ptr(),       mo); break;
2702     case Op_RegF: spill = new LoadFNode(NULL, mem, fp, atp, t,                 mo); break;
2703     case Op_RegD: spill = new LoadDNode(NULL, mem, fp, atp, t,                 mo); break;
2704     case Op_RegL: spill = new LoadLNode(NULL, mem, fp, atp, t->is_long(),      mo); break;
2705 
2706     case Op_VecA: // fall-through
2707     case Op_VecS: // fall-through
2708     case Op_VecD: // fall-through
2709     case Op_VecX: // fall-through
2710     case Op_VecY: // fall-through
2711     case Op_VecZ: spill = new LoadVectorNode(NULL, mem, fp, atp, t->is_vect()); break;
2712     case Op_RegVectMask: return Matcher::predicate_reg_mask();
2713 
2714     default: ShouldNotReachHere();
2715   }
2716   MachNode* mspill = match_tree(spill);
2717   assert(mspill != NULL, "matching failed: %d", ideal_reg);
2718   // Handle generic vector operand case
2719   if (Matcher::supports_generic_vector_operands && t->isa_vect()) {
2720     specialize_mach_node(mspill);
2721   }
2722   return &mspill->out_RegMask();
2723 }
2724 
2725 // Process Mach IR right after selection phase is over.
2726 void Matcher::do_postselect_cleanup() {
2727   if (supports_generic_vector_operands) {
2728     specialize_generic_vector_operands();
2729     if (C->failing())  return;
2730   }
2731 }
2732 
2733 //----------------------------------------------------------------------
2734 // Generic machine operands elision.
2735 //----------------------------------------------------------------------
2736 
2737 // Compute concrete vector operand for a generic TEMP vector mach node based on its user info.
2738 void Matcher::specialize_temp_node(MachTempNode* tmp, MachNode* use, uint idx) {
2739   assert(use->in(idx) == tmp, "not a user");
2740   assert(!Matcher::is_generic_vector(use->_opnds[0]), "use not processed yet");
2741 
2742   if ((uint)idx == use->two_adr()) { // DEF_TEMP case
2743     tmp->_opnds[0] = use->_opnds[0]->clone();
2744   } else {
2745     uint ideal_vreg = vector_ideal_reg(C->max_vector_size());
2746     tmp->_opnds[0] = Matcher::pd_specialize_generic_vector_operand(tmp->_opnds[0], ideal_vreg, true /*is_temp*/);
2747   }
2748 }
2749 
2750 // Compute concrete vector operand for a generic DEF/USE vector operand (of mach node m at index idx).
2751 MachOper* Matcher::specialize_vector_operand(MachNode* m, uint opnd_idx) {
2752   assert(Matcher::is_generic_vector(m->_opnds[opnd_idx]), "repeated updates");
2753   Node* def = NULL;
2754   if (opnd_idx == 0) { // DEF
2755     def = m; // use mach node itself to compute vector operand type
2756   } else {
2757     int base_idx = m->operand_index(opnd_idx);
2758     def = m->in(base_idx);
2759     if (def->is_Mach()) {
2760       if (def->is_MachTemp() && Matcher::is_generic_vector(def->as_Mach()->_opnds[0])) {
2761         specialize_temp_node(def->as_MachTemp(), m, base_idx); // MachTemp node use site
2762       } else if (is_reg2reg_move(def->as_Mach())) {
2763         def = def->in(1); // skip over generic reg-to-reg moves
2764       }
2765     }
2766   }
2767   assert(def->bottom_type()->isa_vect(), "not a vector");
2768   uint ideal_vreg = def->bottom_type()->ideal_reg();
2769   return Matcher::pd_specialize_generic_vector_operand(m->_opnds[opnd_idx], ideal_vreg, false /*is_temp*/);
2770 }
2771 
2772 void Matcher::specialize_mach_node(MachNode* m) {
2773   assert(!m->is_MachTemp(), "processed along with its user");
2774   // For generic use operands pull specific register class operands from
2775   // its def instruction's output operand (def operand).
2776   for (uint i = 0; i < m->num_opnds(); i++) {
2777     if (Matcher::is_generic_vector(m->_opnds[i])) {
2778       m->_opnds[i] = specialize_vector_operand(m, i);
2779     }
2780   }
2781 }
2782 
2783 // Replace generic vector operands with concrete vector operands and eliminate generic reg-to-reg moves from the graph.
2784 void Matcher::specialize_generic_vector_operands() {
2785   assert(supports_generic_vector_operands, "sanity");
2786   ResourceMark rm;
2787 
2788   // Replace generic vector operands (vec/legVec) with concrete ones (vec[SDXYZ]/legVec[SDXYZ])
2789   // and remove reg-to-reg vector moves (MoveVec2Leg and MoveLeg2Vec).
2790   Unique_Node_List live_nodes;
2791   C->identify_useful_nodes(live_nodes);
2792 
2793   while (live_nodes.size() > 0) {
2794     MachNode* m = live_nodes.pop()->isa_Mach();
2795     if (m != NULL) {
2796       if (Matcher::is_reg2reg_move(m)) {
2797         // Register allocator properly handles vec <=> leg moves using register masks.
2798         int opnd_idx = m->operand_index(1);
2799         Node* def = m->in(opnd_idx);
2800         m->subsume_by(def, C);
2801       } else if (m->is_MachTemp()) {
2802         // process MachTemp nodes at use site (see Matcher::specialize_vector_operand)
2803       } else {
2804         specialize_mach_node(m);
2805       }
2806     }
2807   }
2808 }
2809 
2810 uint Matcher::vector_length(const Node* n) {
2811   const TypeVect* vt = n->bottom_type()->is_vect();
2812   return vt->length();
2813 }
2814 
2815 uint Matcher::vector_length(const MachNode* use, const MachOper* opnd) {
2816   int def_idx = use->operand_index(opnd);
2817   Node* def = use->in(def_idx);
2818   return def->bottom_type()->is_vect()->length();
2819 }
2820 
2821 uint Matcher::vector_length_in_bytes(const Node* n) {
2822   const TypeVect* vt = n->bottom_type()->is_vect();
2823   return vt->length_in_bytes();
2824 }
2825 
2826 uint Matcher::vector_length_in_bytes(const MachNode* use, const MachOper* opnd) {
2827   uint def_idx = use->operand_index(opnd);
2828   Node* def = use->in(def_idx);
2829   return def->bottom_type()->is_vect()->length_in_bytes();
2830 }
2831 
2832 BasicType Matcher::vector_element_basic_type(const Node* n) {
2833   const TypeVect* vt = n->bottom_type()->is_vect();
2834   return vt->element_basic_type();
2835 }
2836 
2837 BasicType Matcher::vector_element_basic_type(const MachNode* use, const MachOper* opnd) {
2838   int def_idx = use->operand_index(opnd);
2839   Node* def = use->in(def_idx);
2840   return def->bottom_type()->is_vect()->element_basic_type();
2841 }
2842 
2843 #ifdef ASSERT
2844 bool Matcher::verify_after_postselect_cleanup() {
2845   assert(!C->failing(), "sanity");
2846   if (supports_generic_vector_operands) {
2847     Unique_Node_List useful;
2848     C->identify_useful_nodes(useful);
2849     for (uint i = 0; i < useful.size(); i++) {
2850       MachNode* m = useful.at(i)->isa_Mach();
2851       if (m != NULL) {
2852         assert(!Matcher::is_reg2reg_move(m), "no MoveVec nodes allowed");
2853         for (uint j = 0; j < m->num_opnds(); j++) {
2854           assert(!Matcher::is_generic_vector(m->_opnds[j]), "no generic vector operands allowed");
2855         }
2856       }
2857     }
2858   }
2859   return true;
2860 }
2861 #endif // ASSERT
2862 
2863 // Used by the DFA in dfa_xxx.cpp.  Check for a following barrier or
2864 // atomic instruction acting as a store_load barrier without any
2865 // intervening volatile load, and thus we don't need a barrier here.
2866 // We retain the Node to act as a compiler ordering barrier.
2867 bool Matcher::post_store_load_barrier(const Node* vmb) {
2868   Compile* C = Compile::current();
2869   assert(vmb->is_MemBar(), "");
2870   assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2871   const MemBarNode* membar = vmb->as_MemBar();
2872 
2873   // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2874   Node* ctrl = NULL;
2875   for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2876     Node* p = membar->fast_out(i);
2877     assert(p->is_Proj(), "only projections here");
2878     if ((p->as_Proj()->_con == TypeFunc::Control) &&
2879         !C->node_arena()->contains(p)) { // Unmatched old-space only
2880       ctrl = p;
2881       break;
2882     }
2883   }
2884   assert((ctrl != NULL), "missing control projection");
2885 
2886   for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2887     Node *x = ctrl->fast_out(j);
2888     int xop = x->Opcode();
2889 
2890     // We don't need current barrier if we see another or a lock
2891     // before seeing volatile load.
2892     //
2893     // Op_Fastunlock previously appeared in the Op_* list below.
2894     // With the advent of 1-0 lock operations we're no longer guaranteed
2895     // that a monitor exit operation contains a serializing instruction.
2896 
2897     if (xop == Op_MemBarVolatile ||
2898         xop == Op_CompareAndExchangeB ||
2899         xop == Op_CompareAndExchangeS ||
2900         xop == Op_CompareAndExchangeI ||
2901         xop == Op_CompareAndExchangeL ||
2902         xop == Op_CompareAndExchangeP ||
2903         xop == Op_CompareAndExchangeN ||
2904         xop == Op_WeakCompareAndSwapB ||
2905         xop == Op_WeakCompareAndSwapS ||
2906         xop == Op_WeakCompareAndSwapL ||
2907         xop == Op_WeakCompareAndSwapP ||
2908         xop == Op_WeakCompareAndSwapN ||
2909         xop == Op_WeakCompareAndSwapI ||
2910         xop == Op_CompareAndSwapB ||
2911         xop == Op_CompareAndSwapS ||
2912         xop == Op_CompareAndSwapL ||
2913         xop == Op_CompareAndSwapP ||
2914         xop == Op_CompareAndSwapN ||
2915         xop == Op_CompareAndSwapI ||
2916         BarrierSet::barrier_set()->barrier_set_c2()->matcher_is_store_load_barrier(x, xop)) {
2917       return true;
2918     }
2919 
2920     // Op_FastLock previously appeared in the Op_* list above.
2921     if (xop == Op_FastLock) {
2922       return true;
2923     }
2924 
2925     if (x->is_MemBar()) {
2926       // We must retain this membar if there is an upcoming volatile
2927       // load, which will be followed by acquire membar.
2928       if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2929         return false;
2930       } else {
2931         // For other kinds of barriers, check by pretending we
2932         // are them, and seeing if we can be removed.
2933         return post_store_load_barrier(x->as_MemBar());
2934       }
2935     }
2936 
2937     // probably not necessary to check for these
2938     if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2939       return false;
2940     }
2941   }
2942   return false;
2943 }
2944 
2945 // Check whether node n is a branch to an uncommon trap that we could
2946 // optimize as test with very high branch costs in case of going to
2947 // the uncommon trap. The code must be able to be recompiled to use
2948 // a cheaper test.
2949 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2950   // Don't do it for natives, adapters, or runtime stubs
2951   Compile *C = Compile::current();
2952   if (!C->is_method_compilation()) return false;
2953 
2954   assert(n->is_If(), "You should only call this on if nodes.");
2955   IfNode *ifn = n->as_If();
2956 
2957   Node *ifFalse = NULL;
2958   for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2959     if (ifn->fast_out(i)->is_IfFalse()) {
2960       ifFalse = ifn->fast_out(i);
2961       break;
2962     }
2963   }
2964   assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2965 
2966   Node *reg = ifFalse;
2967   int cnt = 4; // We must protect against cycles.  Limit to 4 iterations.
2968                // Alternatively use visited set?  Seems too expensive.
2969   while (reg != NULL && cnt > 0) {
2970     CallNode *call = NULL;
2971     RegionNode *nxt_reg = NULL;
2972     for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2973       Node *o = reg->fast_out(i);
2974       if (o->is_Call()) {
2975         call = o->as_Call();
2976       }
2977       if (o->is_Region()) {
2978         nxt_reg = o->as_Region();
2979       }
2980     }
2981 
2982     if (call &&
2983         call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2984       const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2985       if (trtype->isa_int() && trtype->is_int()->is_con()) {
2986         jint tr_con = trtype->is_int()->get_con();
2987         Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2988         Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2989         assert((int)reason < (int)BitsPerInt, "recode bit map");
2990 
2991         if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2992             && action != Deoptimization::Action_none) {
2993           // This uncommon trap is sure to recompile, eventually.
2994           // When that happens, C->too_many_traps will prevent
2995           // this transformation from happening again.
2996           return true;
2997         }
2998       }
2999     }
3000 
3001     reg = nxt_reg;
3002     cnt--;
3003   }
3004 
3005   return false;
3006 }
3007 
3008 //=============================================================================
3009 //---------------------------State---------------------------------------------
3010 State::State(void) : _rule() {
3011 #ifdef ASSERT
3012   _id = 0;
3013   _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
3014   _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
3015 #endif
3016 }
3017 
3018 #ifdef ASSERT
3019 State::~State() {
3020   _id = 99;
3021   _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
3022   _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
3023   memset(_cost, -3, sizeof(_cost));
3024   memset(_rule, -3, sizeof(_rule));
3025 }
3026 #endif
3027 
3028 #ifndef PRODUCT
3029 //---------------------------dump----------------------------------------------
3030 void State::dump() {
3031   tty->print("\n");
3032   dump(0);
3033 }
3034 
3035 void State::dump(int depth) {
3036   for (int j = 0; j < depth; j++) {
3037     tty->print("   ");
3038   }
3039   tty->print("--N: ");
3040   _leaf->dump();
3041   uint i;
3042   for (i = 0; i < _LAST_MACH_OPER; i++) {
3043     // Check for valid entry
3044     if (valid(i)) {
3045       for (int j = 0; j < depth; j++) {
3046         tty->print("   ");
3047       }
3048       assert(cost(i) != max_juint, "cost must be a valid value");
3049       assert(rule(i) < _last_Mach_Node, "rule[i] must be valid rule");
3050       tty->print_cr("%s  %d  %s",
3051                     ruleName[i], cost(i), ruleName[rule(i)] );
3052     }
3053   }
3054   tty->cr();
3055 
3056   for (i = 0; i < 2; i++) {
3057     if (_kids[i]) {
3058       _kids[i]->dump(depth + 1);
3059     }
3060   }
3061 }
3062 #endif