1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #include "precompiled.hpp"
26 #include "gc/shared/barrierSet.hpp"
27 #include "gc/shared/c2/barrierSetC2.hpp"
28 #include "memory/allocation.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "oops/compressedOops.hpp"
31 #include "opto/ad.hpp"
32 #include "opto/addnode.hpp"
33 #include "opto/callnode.hpp"
34 #include "opto/idealGraphPrinter.hpp"
35 #include "opto/matcher.hpp"
36 #include "opto/memnode.hpp"
37 #include "opto/movenode.hpp"
38 #include "opto/opcodes.hpp"
39 #include "opto/regmask.hpp"
40 #include "opto/rootnode.hpp"
41 #include "opto/runtime.hpp"
42 #include "opto/type.hpp"
43 #include "opto/vectornode.hpp"
44 #include "runtime/os.inline.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "utilities/align.hpp"
47
48 OptoReg::Name OptoReg::c_frame_pointer;
49
50 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
51 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
52 RegMask Matcher::caller_save_regmask;
53 RegMask Matcher::caller_save_regmask_exclude_soe;
54 RegMask Matcher::mh_caller_save_regmask;
55 RegMask Matcher::mh_caller_save_regmask_exclude_soe;
56 RegMask Matcher::STACK_ONLY_mask;
57 RegMask Matcher::c_frame_ptr_mask;
58 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
59 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
60
61 //---------------------------Matcher-------------------------------------------
62 Matcher::Matcher()
63 : PhaseTransform( Phase::Ins_Select ),
64 _states_arena(Chunk::medium_size, mtCompiler),
65 _new_nodes(C->comp_arena()),
66 _visited(&_states_arena),
67 _shared(&_states_arena),
68 _dontcare(&_states_arena),
69 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
70 _swallowed(swallowed),
71 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
72 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
73 _must_clone(must_clone),
74 _shared_nodes(C->comp_arena()),
75 #ifndef PRODUCT
76 _old2new_map(C->comp_arena()),
77 _new2old_map(C->comp_arena()),
78 _reused(C->comp_arena()),
79 #endif // !PRODUCT
80 _allocation_started(false),
81 _ruleName(ruleName),
82 _register_save_policy(register_save_policy),
83 _c_reg_save_policy(c_reg_save_policy),
84 _register_save_type(register_save_type) {
85 C->set_matcher(this);
86
87 idealreg2spillmask [Op_RegI] = nullptr;
88 idealreg2spillmask [Op_RegN] = nullptr;
89 idealreg2spillmask [Op_RegL] = nullptr;
90 idealreg2spillmask [Op_RegF] = nullptr;
91 idealreg2spillmask [Op_RegD] = nullptr;
92 idealreg2spillmask [Op_RegP] = nullptr;
93 idealreg2spillmask [Op_VecA] = nullptr;
94 idealreg2spillmask [Op_VecS] = nullptr;
95 idealreg2spillmask [Op_VecD] = nullptr;
96 idealreg2spillmask [Op_VecX] = nullptr;
97 idealreg2spillmask [Op_VecY] = nullptr;
98 idealreg2spillmask [Op_VecZ] = nullptr;
99 idealreg2spillmask [Op_RegFlags] = nullptr;
100 idealreg2spillmask [Op_RegVectMask] = nullptr;
101
102 idealreg2debugmask [Op_RegI] = nullptr;
103 idealreg2debugmask [Op_RegN] = nullptr;
104 idealreg2debugmask [Op_RegL] = nullptr;
105 idealreg2debugmask [Op_RegF] = nullptr;
106 idealreg2debugmask [Op_RegD] = nullptr;
107 idealreg2debugmask [Op_RegP] = nullptr;
108 idealreg2debugmask [Op_VecA] = nullptr;
109 idealreg2debugmask [Op_VecS] = nullptr;
110 idealreg2debugmask [Op_VecD] = nullptr;
111 idealreg2debugmask [Op_VecX] = nullptr;
112 idealreg2debugmask [Op_VecY] = nullptr;
113 idealreg2debugmask [Op_VecZ] = nullptr;
114 idealreg2debugmask [Op_RegFlags] = nullptr;
115 idealreg2debugmask [Op_RegVectMask] = nullptr;
116
117 idealreg2mhdebugmask[Op_RegI] = nullptr;
118 idealreg2mhdebugmask[Op_RegN] = nullptr;
119 idealreg2mhdebugmask[Op_RegL] = nullptr;
120 idealreg2mhdebugmask[Op_RegF] = nullptr;
121 idealreg2mhdebugmask[Op_RegD] = nullptr;
122 idealreg2mhdebugmask[Op_RegP] = nullptr;
123 idealreg2mhdebugmask[Op_VecA] = nullptr;
124 idealreg2mhdebugmask[Op_VecS] = nullptr;
125 idealreg2mhdebugmask[Op_VecD] = nullptr;
126 idealreg2mhdebugmask[Op_VecX] = nullptr;
127 idealreg2mhdebugmask[Op_VecY] = nullptr;
128 idealreg2mhdebugmask[Op_VecZ] = nullptr;
129 idealreg2mhdebugmask[Op_RegFlags] = nullptr;
130 idealreg2mhdebugmask[Op_RegVectMask] = nullptr;
131
132 debug_only(_mem_node = nullptr;) // Ideal memory node consumed by mach node
133 }
134
135 //------------------------------warp_incoming_stk_arg------------------------
136 // This warps a VMReg into an OptoReg::Name
137 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
138 OptoReg::Name warped;
139 if( reg->is_stack() ) { // Stack slot argument?
140 warped = OptoReg::add(_old_SP, reg->reg2stack() );
141 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
142 if( warped >= _in_arg_limit )
143 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
144 if (!RegMask::can_represent_arg(warped)) {
145 // the compiler cannot represent this method's calling sequence
146 // Bailout. We do not have space to represent all arguments.
147 C->record_method_not_compilable("unsupported incoming calling sequence");
148 return OptoReg::Bad;
149 }
150 return warped;
151 }
152 return OptoReg::as_OptoReg(reg);
153 }
154
155 //---------------------------compute_old_SP------------------------------------
156 OptoReg::Name Compile::compute_old_SP() {
157 int fixed = fixed_slots();
158 int preserve = in_preserve_stack_slots();
159 return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots()));
160 }
161
162
163
164 #ifdef ASSERT
165 void Matcher::verify_new_nodes_only(Node* xroot) {
166 // Make sure that the new graph only references new nodes
167 ResourceMark rm;
168 Unique_Node_List worklist;
169 VectorSet visited;
170 worklist.push(xroot);
171 while (worklist.size() > 0) {
172 Node* n = worklist.pop();
173 visited.set(n->_idx);
174 assert(C->node_arena()->contains(n), "dead node");
175 for (uint j = 0; j < n->req(); j++) {
176 Node* in = n->in(j);
177 if (in != nullptr) {
178 assert(C->node_arena()->contains(in), "dead node");
179 if (!visited.test(in->_idx)) {
180 worklist.push(in);
181 }
182 }
183 }
184 }
185 }
186 #endif
187
188 // Array of RegMask, one per returned values (inline type instances can
189 // be returned as multiple return values, one per field)
190 RegMask* Matcher::return_values_mask(const TypeFunc* tf) {
191 const TypeTuple* range = tf->range_cc();
192 uint cnt = range->cnt() - TypeFunc::Parms;
193 if (cnt == 0) {
194 return nullptr;
195 }
196 RegMask* mask = NEW_RESOURCE_ARRAY(RegMask, cnt);
197 BasicType* sig_bt = NEW_RESOURCE_ARRAY(BasicType, cnt);
198 VMRegPair* vm_parm_regs = NEW_RESOURCE_ARRAY(VMRegPair, cnt);
199 for (uint i = 0; i < cnt; i++) {
200 sig_bt[i] = range->field_at(i+TypeFunc::Parms)->basic_type();
201 }
202
203 int regs = SharedRuntime::java_return_convention(sig_bt, vm_parm_regs, cnt);
204 if (regs <= 0) {
205 // We ran out of registers to store the IsInit information for a nullable inline type return.
206 // Since it is only set in the 'call_epilog', we can simply put it on the stack.
207 assert(tf->returns_inline_type_as_fields(), "should have been tested during graph construction");
208 // TODO 8284443 Can we teach the register allocator to reserve a stack slot instead?
209 // mask[--cnt] = STACK_ONLY_mask does not work (test with -XX:+StressGCM)
210 int slot = C->fixed_slots() - 2;
211 if (C->needs_stack_repair()) {
212 slot -= 2; // Account for stack increment value
213 }
214 mask[--cnt].Clear();
215 mask[cnt].Insert(OptoReg::stack2reg(slot));
216 }
217 for (uint i = 0; i < cnt; i++) {
218 mask[i].Clear();
219
220 OptoReg::Name reg1 = OptoReg::as_OptoReg(vm_parm_regs[i].first());
221 if (OptoReg::is_valid(reg1)) {
222 mask[i].Insert(reg1);
223 }
224 OptoReg::Name reg2 = OptoReg::as_OptoReg(vm_parm_regs[i].second());
225 if (OptoReg::is_valid(reg2)) {
226 mask[i].Insert(reg2);
227 }
228 }
229
230 return mask;
231 }
232
233 //---------------------------match---------------------------------------------
234 void Matcher::match( ) {
235 if( MaxLabelRootDepth < 100 ) { // Too small?
236 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
237 MaxLabelRootDepth = 100;
238 }
239 // One-time initialization of some register masks.
240 init_spill_mask( C->root()->in(1) );
241 _return_addr_mask = return_addr();
242 #ifdef _LP64
243 // Pointers take 2 slots in 64-bit land
244 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
245 #endif
246
247 // Map Java-signature return types into return register-value
248 // machine registers.
249 _return_values_mask = return_values_mask(C->tf());
250
251 // ---------------
252 // Frame Layout
253
254 // Need the method signature to determine the incoming argument types,
255 // because the types determine which registers the incoming arguments are
256 // in, and this affects the matched code.
257 const TypeTuple *domain = C->tf()->domain_cc();
258 uint argcnt = domain->cnt() - TypeFunc::Parms;
259 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
260 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
261 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
262 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
263 uint i;
264 for( i = 0; i<argcnt; i++ ) {
265 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
266 }
267
268 // Pass array of ideal registers and length to USER code (from the AD file)
269 // that will convert this to an array of register numbers.
270 const StartNode *start = C->start();
271 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
272 #ifdef ASSERT
273 // Sanity check users' calling convention. Real handy while trying to
274 // get the initial port correct.
275 { for (uint i = 0; i<argcnt; i++) {
276 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
277 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
278 _parm_regs[i].set_bad();
279 continue;
280 }
281 VMReg parm_reg = vm_parm_regs[i].first();
282 assert(parm_reg->is_valid(), "invalid arg?");
283 if (parm_reg->is_reg()) {
284 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
285 assert(can_be_java_arg(opto_parm_reg) ||
286 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
287 opto_parm_reg == inline_cache_reg(),
288 "parameters in register must be preserved by runtime stubs");
289 }
290 for (uint j = 0; j < i; j++) {
291 assert(parm_reg != vm_parm_regs[j].first(),
292 "calling conv. must produce distinct regs");
293 }
294 }
295 }
296 #endif
297
298 // Do some initial frame layout.
299
300 // Compute the old incoming SP (may be called FP) as
301 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
302 _old_SP = C->compute_old_SP();
303 assert( is_even(_old_SP), "must be even" );
304
305 // Compute highest incoming stack argument as
306 // _old_SP + out_preserve_stack_slots + incoming argument size.
307 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
308 assert( is_even(_in_arg_limit), "out_preserve must be even" );
309 for( i = 0; i < argcnt; i++ ) {
310 // Permit args to have no register
311 _calling_convention_mask[i].Clear();
312 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
313 _parm_regs[i].set_bad();
314 continue;
315 }
316 // calling_convention returns stack arguments as a count of
317 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
318 // the allocators point of view, taking into account all the
319 // preserve area, locks & pad2.
320
321 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
322 if( OptoReg::is_valid(reg1))
323 _calling_convention_mask[i].Insert(reg1);
324
325 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
326 if( OptoReg::is_valid(reg2))
327 _calling_convention_mask[i].Insert(reg2);
328
329 // Saved biased stack-slot register number
330 _parm_regs[i].set_pair(reg2, reg1);
331 }
332
333 // Finally, make sure the incoming arguments take up an even number of
334 // words, in case the arguments or locals need to contain doubleword stack
335 // slots. The rest of the system assumes that stack slot pairs (in
336 // particular, in the spill area) which look aligned will in fact be
337 // aligned relative to the stack pointer in the target machine. Double
338 // stack slots will always be allocated aligned.
339 _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong));
340
341 // Compute highest outgoing stack argument as
342 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
343 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
344 assert( is_even(_out_arg_limit), "out_preserve must be even" );
345
346 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
347 // the compiler cannot represent this method's calling sequence
348 // Bailout. We do not have space to represent all arguments.
349 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
350 }
351
352 if (C->failing()) return; // bailed out on incoming arg failure
353
354 // ---------------
355 // Collect roots of matcher trees. Every node for which
356 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
357 // can be a valid interior of some tree.
358 find_shared( C->root() );
359 find_shared( C->top() );
360
361 C->print_method(PHASE_BEFORE_MATCHING, 1);
362
363 // Create new ideal node ConP #null even if it does exist in old space
364 // to avoid false sharing if the corresponding mach node is not used.
365 // The corresponding mach node is only used in rare cases for derived
366 // pointers.
367 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
368
369 // Swap out to old-space; emptying new-space
370 Arena* old = C->swap_old_and_new();
371
372 // Save debug and profile information for nodes in old space:
373 _old_node_note_array = C->node_note_array();
374 if (_old_node_note_array != nullptr) {
375 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
376 (C->comp_arena(), _old_node_note_array->length(),
377 0, nullptr));
378 }
379
380 // Pre-size the new_node table to avoid the need for range checks.
381 grow_new_node_array(C->unique());
382
383 // Reset node counter so MachNodes start with _idx at 0
384 int live_nodes = C->live_nodes();
385 C->set_unique(0);
386 C->reset_dead_node_list();
387
388 // Recursively match trees from old space into new space.
389 // Correct leaves of new-space Nodes; they point to old-space.
390 _visited.clear();
391 Node* const n = xform(C->top(), live_nodes);
392 if (C->failing()) return;
393 C->set_cached_top_node(n);
394 if (!C->failing()) {
395 Node* xroot = xform( C->root(), 1 );
396 if (C->failing()) return;
397 if (xroot == nullptr) {
398 Matcher::soft_match_failure(); // recursive matching process failed
399 assert(false, "instruction match failed");
400 C->record_method_not_compilable("instruction match failed");
401 } else {
402 // During matching shared constants were attached to C->root()
403 // because xroot wasn't available yet, so transfer the uses to
404 // the xroot.
405 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
406 Node* n = C->root()->fast_out(j);
407 if (C->node_arena()->contains(n)) {
408 assert(n->in(0) == C->root(), "should be control user");
409 n->set_req(0, xroot);
410 --j;
411 --jmax;
412 }
413 }
414
415 // Generate new mach node for ConP #null
416 assert(new_ideal_null != nullptr, "sanity");
417 _mach_null = match_tree(new_ideal_null);
418 // Don't set control, it will confuse GCM since there are no uses.
419 // The control will be set when this node is used first time
420 // in find_base_for_derived().
421 assert(_mach_null != nullptr, "");
422
423 C->set_root(xroot->is_Root() ? xroot->as_Root() : nullptr);
424
425 #ifdef ASSERT
426 verify_new_nodes_only(xroot);
427 #endif
428 }
429 }
430 if (C->top() == nullptr || C->root() == nullptr) {
431 // New graph lost. This is due to a compilation failure we encountered earlier.
432 stringStream ss;
433 if (C->failure_reason() != nullptr) {
434 ss.print("graph lost: %s", C->failure_reason());
435 } else {
436 assert(C->failure_reason() != nullptr, "graph lost: reason unknown");
437 ss.print("graph lost: reason unknown");
438 }
439 C->record_method_not_compilable(ss.as_string());
440 }
441 if (C->failing()) {
442 // delete old;
443 old->destruct_contents();
444 return;
445 }
446 assert( C->top(), "" );
447 assert( C->root(), "" );
448 validate_null_checks();
449
450 // Now smoke old-space
451 NOT_DEBUG( old->destruct_contents() );
452
453 // ------------------------
454 // Set up save-on-entry registers.
455 Fixup_Save_On_Entry( );
456
457 { // Cleanup mach IR after selection phase is over.
458 Compile::TracePhase tp("postselect_cleanup", &timers[_t_postselect_cleanup]);
459 do_postselect_cleanup();
460 if (C->failing()) return;
461 assert(verify_after_postselect_cleanup(), "");
462 }
463 }
464
465 //------------------------------Fixup_Save_On_Entry----------------------------
466 // The stated purpose of this routine is to take care of save-on-entry
467 // registers. However, the overall goal of the Match phase is to convert into
468 // machine-specific instructions which have RegMasks to guide allocation.
469 // So what this procedure really does is put a valid RegMask on each input
470 // to the machine-specific variations of all Return, TailCall and Halt
471 // instructions. It also adds edgs to define the save-on-entry values (and of
472 // course gives them a mask).
473
474 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
475 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
476 // Do all the pre-defined register masks
477 rms[TypeFunc::Control ] = RegMask::Empty;
478 rms[TypeFunc::I_O ] = RegMask::Empty;
479 rms[TypeFunc::Memory ] = RegMask::Empty;
480 rms[TypeFunc::ReturnAdr] = ret_adr;
481 rms[TypeFunc::FramePtr ] = fp;
482 return rms;
483 }
484
485 int Matcher::scalable_predicate_reg_slots() {
486 assert(Matcher::has_predicated_vectors() && Matcher::supports_scalable_vector(),
487 "scalable predicate vector should be supported");
488 int vector_reg_bit_size = Matcher::scalable_vector_reg_size(T_BYTE) << LogBitsPerByte;
489 // We assume each predicate register is one-eighth of the size of
490 // scalable vector register, one mask bit per vector byte.
491 int predicate_reg_bit_size = vector_reg_bit_size >> 3;
492 // Compute number of slots which is required when scalable predicate
493 // register is spilled. E.g. if scalable vector register is 640 bits,
494 // predicate register is 80 bits, which is 2.5 * slots.
495 // We will round up the slot number to power of 2, which is required
496 // by find_first_set().
497 int slots = predicate_reg_bit_size & (BitsPerInt - 1)
498 ? (predicate_reg_bit_size >> LogBitsPerInt) + 1
499 : predicate_reg_bit_size >> LogBitsPerInt;
500 return round_up_power_of_2(slots);
501 }
502
503 #define NOF_STACK_MASKS (3*13)
504
505 // Create the initial stack mask used by values spilling to the stack.
506 // Disallow any debug info in outgoing argument areas by setting the
507 // initial mask accordingly.
508 void Matcher::init_first_stack_mask() {
509
510 // Allocate storage for spill masks as masks for the appropriate load type.
511 RegMask *rms = (RegMask*)C->comp_arena()->AmallocWords(sizeof(RegMask) * NOF_STACK_MASKS);
512
513 // Initialize empty placeholder masks into the newly allocated arena
514 for (int i = 0; i < NOF_STACK_MASKS; i++) {
515 new (rms + i) RegMask();
516 }
517
518 idealreg2spillmask [Op_RegN] = &rms[0];
519 idealreg2spillmask [Op_RegI] = &rms[1];
520 idealreg2spillmask [Op_RegL] = &rms[2];
521 idealreg2spillmask [Op_RegF] = &rms[3];
522 idealreg2spillmask [Op_RegD] = &rms[4];
523 idealreg2spillmask [Op_RegP] = &rms[5];
524
525 idealreg2debugmask [Op_RegN] = &rms[6];
526 idealreg2debugmask [Op_RegI] = &rms[7];
527 idealreg2debugmask [Op_RegL] = &rms[8];
528 idealreg2debugmask [Op_RegF] = &rms[9];
529 idealreg2debugmask [Op_RegD] = &rms[10];
530 idealreg2debugmask [Op_RegP] = &rms[11];
531
532 idealreg2mhdebugmask[Op_RegN] = &rms[12];
533 idealreg2mhdebugmask[Op_RegI] = &rms[13];
534 idealreg2mhdebugmask[Op_RegL] = &rms[14];
535 idealreg2mhdebugmask[Op_RegF] = &rms[15];
536 idealreg2mhdebugmask[Op_RegD] = &rms[16];
537 idealreg2mhdebugmask[Op_RegP] = &rms[17];
538
539 idealreg2spillmask [Op_VecA] = &rms[18];
540 idealreg2spillmask [Op_VecS] = &rms[19];
541 idealreg2spillmask [Op_VecD] = &rms[20];
542 idealreg2spillmask [Op_VecX] = &rms[21];
543 idealreg2spillmask [Op_VecY] = &rms[22];
544 idealreg2spillmask [Op_VecZ] = &rms[23];
545
546 idealreg2debugmask [Op_VecA] = &rms[24];
547 idealreg2debugmask [Op_VecS] = &rms[25];
548 idealreg2debugmask [Op_VecD] = &rms[26];
549 idealreg2debugmask [Op_VecX] = &rms[27];
550 idealreg2debugmask [Op_VecY] = &rms[28];
551 idealreg2debugmask [Op_VecZ] = &rms[29];
552
553 idealreg2mhdebugmask[Op_VecA] = &rms[30];
554 idealreg2mhdebugmask[Op_VecS] = &rms[31];
555 idealreg2mhdebugmask[Op_VecD] = &rms[32];
556 idealreg2mhdebugmask[Op_VecX] = &rms[33];
557 idealreg2mhdebugmask[Op_VecY] = &rms[34];
558 idealreg2mhdebugmask[Op_VecZ] = &rms[35];
559
560 idealreg2spillmask [Op_RegVectMask] = &rms[36];
561 idealreg2debugmask [Op_RegVectMask] = &rms[37];
562 idealreg2mhdebugmask[Op_RegVectMask] = &rms[38];
563
564 OptoReg::Name i;
565
566 // At first, start with the empty mask
567 C->FIRST_STACK_mask().Clear();
568
569 // Add in the incoming argument area
570 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
571 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
572 C->FIRST_STACK_mask().Insert(i);
573 }
574
575 // Add in all bits past the outgoing argument area
576 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
577 "must be able to represent all call arguments in reg mask");
578 OptoReg::Name init = _out_arg_limit;
579 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
580 C->FIRST_STACK_mask().Insert(i);
581 }
582 // Finally, set the "infinite stack" bit.
583 C->FIRST_STACK_mask().set_AllStack();
584
585 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
586 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
587 // Keep spill masks aligned.
588 aligned_stack_mask.clear_to_pairs();
589 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
590 RegMask scalable_stack_mask = aligned_stack_mask;
591
592 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
593 #ifdef _LP64
594 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
595 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
596 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
597 #else
598 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
599 #endif
600 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
601 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
602 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
603 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
604 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
605 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
606 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
607 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
608
609 if (Matcher::has_predicated_vectors()) {
610 *idealreg2spillmask[Op_RegVectMask] = *idealreg2regmask[Op_RegVectMask];
611 idealreg2spillmask[Op_RegVectMask]->OR(aligned_stack_mask);
612 } else {
613 *idealreg2spillmask[Op_RegVectMask] = RegMask::Empty;
614 }
615
616 if (Matcher::vector_size_supported(T_BYTE,4)) {
617 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
618 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
619 } else {
620 *idealreg2spillmask[Op_VecS] = RegMask::Empty;
621 }
622
623 if (Matcher::vector_size_supported(T_FLOAT,2)) {
624 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
625 // RA guarantees such alignment since it is needed for Double and Long values.
626 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
627 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
628 } else {
629 *idealreg2spillmask[Op_VecD] = RegMask::Empty;
630 }
631
632 if (Matcher::vector_size_supported(T_FLOAT,4)) {
633 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
634 //
635 // RA can use input arguments stack slots for spills but until RA
636 // we don't know frame size and offset of input arg stack slots.
637 //
638 // Exclude last input arg stack slots to avoid spilling vectors there
639 // otherwise vector spills could stomp over stack slots in caller frame.
640 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
641 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
642 aligned_stack_mask.Remove(in);
643 in = OptoReg::add(in, -1);
644 }
645 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
646 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
647 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
648 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
649 } else {
650 *idealreg2spillmask[Op_VecX] = RegMask::Empty;
651 }
652
653 if (Matcher::vector_size_supported(T_FLOAT,8)) {
654 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
655 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
656 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
657 aligned_stack_mask.Remove(in);
658 in = OptoReg::add(in, -1);
659 }
660 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
661 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
662 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
663 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
664 } else {
665 *idealreg2spillmask[Op_VecY] = RegMask::Empty;
666 }
667
668 if (Matcher::vector_size_supported(T_FLOAT,16)) {
669 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
670 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
671 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
672 aligned_stack_mask.Remove(in);
673 in = OptoReg::add(in, -1);
674 }
675 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
676 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
677 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
678 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
679 } else {
680 *idealreg2spillmask[Op_VecZ] = RegMask::Empty;
681 }
682
683 if (Matcher::supports_scalable_vector()) {
684 int k = 1;
685 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
686 if (Matcher::has_predicated_vectors()) {
687 // Exclude last input arg stack slots to avoid spilling vector register there,
688 // otherwise RegVectMask spills could stomp over stack slots in caller frame.
689 for (; (in >= init_in) && (k < scalable_predicate_reg_slots()); k++) {
690 scalable_stack_mask.Remove(in);
691 in = OptoReg::add(in, -1);
692 }
693
694 // For RegVectMask
695 scalable_stack_mask.clear_to_sets(scalable_predicate_reg_slots());
696 assert(scalable_stack_mask.is_AllStack(), "should be infinite stack");
697 *idealreg2spillmask[Op_RegVectMask] = *idealreg2regmask[Op_RegVectMask];
698 idealreg2spillmask[Op_RegVectMask]->OR(scalable_stack_mask);
699 }
700
701 // Exclude last input arg stack slots to avoid spilling vector register there,
702 // otherwise vector spills could stomp over stack slots in caller frame.
703 for (; (in >= init_in) && (k < scalable_vector_reg_size(T_FLOAT)); k++) {
704 scalable_stack_mask.Remove(in);
705 in = OptoReg::add(in, -1);
706 }
707
708 // For VecA
709 scalable_stack_mask.clear_to_sets(RegMask::SlotsPerVecA);
710 assert(scalable_stack_mask.is_AllStack(), "should be infinite stack");
711 *idealreg2spillmask[Op_VecA] = *idealreg2regmask[Op_VecA];
712 idealreg2spillmask[Op_VecA]->OR(scalable_stack_mask);
713 } else {
714 *idealreg2spillmask[Op_VecA] = RegMask::Empty;
715 }
716
717 if (UseFPUForSpilling) {
718 // This mask logic assumes that the spill operations are
719 // symmetric and that the registers involved are the same size.
720 // On sparc for instance we may have to use 64 bit moves will
721 // kill 2 registers when used with F0-F31.
722 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
723 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
724 #ifdef _LP64
725 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
726 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
727 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
728 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
729 #else
730 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
731 #ifdef ARM
732 // ARM has support for moving 64bit values between a pair of
733 // integer registers and a double register
734 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
735 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
736 #endif
737 #endif
738 }
739
740 // Make up debug masks. Any spill slot plus callee-save (SOE) registers.
741 // Caller-save (SOC, AS) registers are assumed to be trashable by the various
742 // inline-cache fixup routines.
743 *idealreg2debugmask [Op_RegN] = *idealreg2spillmask[Op_RegN];
744 *idealreg2debugmask [Op_RegI] = *idealreg2spillmask[Op_RegI];
745 *idealreg2debugmask [Op_RegL] = *idealreg2spillmask[Op_RegL];
746 *idealreg2debugmask [Op_RegF] = *idealreg2spillmask[Op_RegF];
747 *idealreg2debugmask [Op_RegD] = *idealreg2spillmask[Op_RegD];
748 *idealreg2debugmask [Op_RegP] = *idealreg2spillmask[Op_RegP];
749 *idealreg2debugmask [Op_RegVectMask] = *idealreg2spillmask[Op_RegVectMask];
750
751 *idealreg2debugmask [Op_VecA] = *idealreg2spillmask[Op_VecA];
752 *idealreg2debugmask [Op_VecS] = *idealreg2spillmask[Op_VecS];
753 *idealreg2debugmask [Op_VecD] = *idealreg2spillmask[Op_VecD];
754 *idealreg2debugmask [Op_VecX] = *idealreg2spillmask[Op_VecX];
755 *idealreg2debugmask [Op_VecY] = *idealreg2spillmask[Op_VecY];
756 *idealreg2debugmask [Op_VecZ] = *idealreg2spillmask[Op_VecZ];
757
758 *idealreg2mhdebugmask[Op_RegN] = *idealreg2spillmask[Op_RegN];
759 *idealreg2mhdebugmask[Op_RegI] = *idealreg2spillmask[Op_RegI];
760 *idealreg2mhdebugmask[Op_RegL] = *idealreg2spillmask[Op_RegL];
761 *idealreg2mhdebugmask[Op_RegF] = *idealreg2spillmask[Op_RegF];
762 *idealreg2mhdebugmask[Op_RegD] = *idealreg2spillmask[Op_RegD];
763 *idealreg2mhdebugmask[Op_RegP] = *idealreg2spillmask[Op_RegP];
764 *idealreg2mhdebugmask[Op_RegVectMask] = *idealreg2spillmask[Op_RegVectMask];
765
766 *idealreg2mhdebugmask[Op_VecA] = *idealreg2spillmask[Op_VecA];
767 *idealreg2mhdebugmask[Op_VecS] = *idealreg2spillmask[Op_VecS];
768 *idealreg2mhdebugmask[Op_VecD] = *idealreg2spillmask[Op_VecD];
769 *idealreg2mhdebugmask[Op_VecX] = *idealreg2spillmask[Op_VecX];
770 *idealreg2mhdebugmask[Op_VecY] = *idealreg2spillmask[Op_VecY];
771 *idealreg2mhdebugmask[Op_VecZ] = *idealreg2spillmask[Op_VecZ];
772
773 // Prevent stub compilations from attempting to reference
774 // callee-saved (SOE) registers from debug info
775 bool exclude_soe = !Compile::current()->is_method_compilation();
776 RegMask* caller_save_mask = exclude_soe ? &caller_save_regmask_exclude_soe : &caller_save_regmask;
777 RegMask* mh_caller_save_mask = exclude_soe ? &mh_caller_save_regmask_exclude_soe : &mh_caller_save_regmask;
778
779 idealreg2debugmask[Op_RegN]->SUBTRACT(*caller_save_mask);
780 idealreg2debugmask[Op_RegI]->SUBTRACT(*caller_save_mask);
781 idealreg2debugmask[Op_RegL]->SUBTRACT(*caller_save_mask);
782 idealreg2debugmask[Op_RegF]->SUBTRACT(*caller_save_mask);
783 idealreg2debugmask[Op_RegD]->SUBTRACT(*caller_save_mask);
784 idealreg2debugmask[Op_RegP]->SUBTRACT(*caller_save_mask);
785 idealreg2debugmask[Op_RegVectMask]->SUBTRACT(*caller_save_mask);
786
787 idealreg2debugmask[Op_VecA]->SUBTRACT(*caller_save_mask);
788 idealreg2debugmask[Op_VecS]->SUBTRACT(*caller_save_mask);
789 idealreg2debugmask[Op_VecD]->SUBTRACT(*caller_save_mask);
790 idealreg2debugmask[Op_VecX]->SUBTRACT(*caller_save_mask);
791 idealreg2debugmask[Op_VecY]->SUBTRACT(*caller_save_mask);
792 idealreg2debugmask[Op_VecZ]->SUBTRACT(*caller_save_mask);
793
794 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(*mh_caller_save_mask);
795 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(*mh_caller_save_mask);
796 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(*mh_caller_save_mask);
797 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(*mh_caller_save_mask);
798 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(*mh_caller_save_mask);
799 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(*mh_caller_save_mask);
800 idealreg2mhdebugmask[Op_RegVectMask]->SUBTRACT(*mh_caller_save_mask);
801
802 idealreg2mhdebugmask[Op_VecA]->SUBTRACT(*mh_caller_save_mask);
803 idealreg2mhdebugmask[Op_VecS]->SUBTRACT(*mh_caller_save_mask);
804 idealreg2mhdebugmask[Op_VecD]->SUBTRACT(*mh_caller_save_mask);
805 idealreg2mhdebugmask[Op_VecX]->SUBTRACT(*mh_caller_save_mask);
806 idealreg2mhdebugmask[Op_VecY]->SUBTRACT(*mh_caller_save_mask);
807 idealreg2mhdebugmask[Op_VecZ]->SUBTRACT(*mh_caller_save_mask);
808 }
809
810 //---------------------------is_save_on_entry----------------------------------
811 bool Matcher::is_save_on_entry(int reg) {
812 return
813 _register_save_policy[reg] == 'E' ||
814 _register_save_policy[reg] == 'A'; // Save-on-entry register?
815 }
816
817 //---------------------------Fixup_Save_On_Entry-------------------------------
818 void Matcher::Fixup_Save_On_Entry( ) {
819 init_first_stack_mask();
820
821 Node *root = C->root(); // Short name for root
822 // Count number of save-on-entry registers.
823 uint soe_cnt = number_of_saved_registers();
824 uint i;
825
826 // Find the procedure Start Node
827 StartNode *start = C->start();
828 assert( start, "Expect a start node" );
829
830 // Input RegMask array shared by all Returns.
831 // The type for doubles and longs has a count of 2, but
832 // there is only 1 returned value
833 uint ret_edge_cnt = C->tf()->range_cc()->cnt();
834 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
835 for (i = TypeFunc::Parms; i < ret_edge_cnt; i++) {
836 ret_rms[i] = _return_values_mask[i-TypeFunc::Parms];
837 }
838
839 // Input RegMask array shared by all ForwardExceptions
840 uint forw_exc_edge_cnt = TypeFunc::Parms;
841 RegMask* forw_exc_rms = init_input_masks( forw_exc_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
842
843 // Input RegMask array shared by all Rethrows.
844 uint reth_edge_cnt = TypeFunc::Parms+1;
845 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
846 // Rethrow takes exception oop only, but in the argument 0 slot.
847 OptoReg::Name reg = find_receiver();
848 if (reg >= 0) {
849 reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
850 #ifdef _LP64
851 // Need two slots for ptrs in 64-bit land
852 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
853 #endif
854 }
855
856 // Input RegMask array shared by all TailCalls
857 uint tail_call_edge_cnt = TypeFunc::Parms+2;
858 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
859
860 // Input RegMask array shared by all TailJumps
861 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
862 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
863
864 // TailCalls have 2 returned values (target & moop), whose masks come
865 // from the usual MachNode/MachOper mechanism. Find a sample
866 // TailCall to extract these masks and put the correct masks into
867 // the tail_call_rms array.
868 for( i=1; i < root->req(); i++ ) {
869 MachReturnNode *m = root->in(i)->as_MachReturn();
870 if( m->ideal_Opcode() == Op_TailCall ) {
871 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
872 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
873 break;
874 }
875 }
876
877 // TailJumps have 2 returned values (target & ex_oop), whose masks come
878 // from the usual MachNode/MachOper mechanism. Find a sample
879 // TailJump to extract these masks and put the correct masks into
880 // the tail_jump_rms array.
881 for( i=1; i < root->req(); i++ ) {
882 MachReturnNode *m = root->in(i)->as_MachReturn();
883 if( m->ideal_Opcode() == Op_TailJump ) {
884 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
885 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
886 break;
887 }
888 }
889
890 // Input RegMask array shared by all Halts
891 uint halt_edge_cnt = TypeFunc::Parms;
892 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
893
894 // Capture the return input masks into each exit flavor
895 for( i=1; i < root->req(); i++ ) {
896 MachReturnNode *exit = root->in(i)->as_MachReturn();
897 switch( exit->ideal_Opcode() ) {
898 case Op_Return : exit->_in_rms = ret_rms; break;
899 case Op_Rethrow : exit->_in_rms = reth_rms; break;
900 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
901 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
902 case Op_ForwardException: exit->_in_rms = forw_exc_rms; break;
903 case Op_Halt : exit->_in_rms = halt_rms; break;
904 default : ShouldNotReachHere();
905 }
906 }
907
908 // Next unused projection number from Start.
909 int proj_cnt = C->tf()->domain_cc()->cnt();
910
911 // Do all the save-on-entry registers. Make projections from Start for
912 // them, and give them a use at the exit points. To the allocator, they
913 // look like incoming register arguments.
914 for( i = 0; i < _last_Mach_Reg; i++ ) {
915 if( is_save_on_entry(i) ) {
916
917 // Add the save-on-entry to the mask array
918 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
919 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
920 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
921 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
922 forw_exc_rms [ forw_exc_edge_cnt] = mreg2regmask[i];
923 // Halts need the SOE registers, but only in the stack as debug info.
924 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
925 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
926
927 Node *mproj;
928
929 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
930 // into a single RegD.
931 if( (i&1) == 0 &&
932 _register_save_type[i ] == Op_RegF &&
933 _register_save_type[i+1] == Op_RegF &&
934 is_save_on_entry(i+1) ) {
935 // Add other bit for double
936 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
937 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
938 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
939 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
940 forw_exc_rms [ forw_exc_edge_cnt].Insert(OptoReg::Name(i+1));
941 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
942 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
943 proj_cnt += 2; // Skip 2 for doubles
944 }
945 else if( (i&1) == 1 && // Else check for high half of double
946 _register_save_type[i-1] == Op_RegF &&
947 _register_save_type[i ] == Op_RegF &&
948 is_save_on_entry(i-1) ) {
949 ret_rms [ ret_edge_cnt] = RegMask::Empty;
950 reth_rms [ reth_edge_cnt] = RegMask::Empty;
951 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
952 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
953 forw_exc_rms [ forw_exc_edge_cnt] = RegMask::Empty;
954 halt_rms [ halt_edge_cnt] = RegMask::Empty;
955 mproj = C->top();
956 }
957 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
958 // into a single RegL.
959 else if( (i&1) == 0 &&
960 _register_save_type[i ] == Op_RegI &&
961 _register_save_type[i+1] == Op_RegI &&
962 is_save_on_entry(i+1) ) {
963 // Add other bit for long
964 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
965 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
966 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
967 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
968 forw_exc_rms [ forw_exc_edge_cnt].Insert(OptoReg::Name(i+1));
969 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
970 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
971 proj_cnt += 2; // Skip 2 for longs
972 }
973 else if( (i&1) == 1 && // Else check for high half of long
974 _register_save_type[i-1] == Op_RegI &&
975 _register_save_type[i ] == Op_RegI &&
976 is_save_on_entry(i-1) ) {
977 ret_rms [ ret_edge_cnt] = RegMask::Empty;
978 reth_rms [ reth_edge_cnt] = RegMask::Empty;
979 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
980 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
981 forw_exc_rms [ forw_exc_edge_cnt] = RegMask::Empty;
982 halt_rms [ halt_edge_cnt] = RegMask::Empty;
983 mproj = C->top();
984 } else {
985 // Make a projection for it off the Start
986 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
987 }
988
989 ret_edge_cnt ++;
990 reth_edge_cnt ++;
991 tail_call_edge_cnt ++;
992 tail_jump_edge_cnt ++;
993 forw_exc_edge_cnt++;
994 halt_edge_cnt ++;
995
996 // Add a use of the SOE register to all exit paths
997 for (uint j=1; j < root->req(); j++) {
998 root->in(j)->add_req(mproj);
999 }
1000 } // End of if a save-on-entry register
1001 } // End of for all machine registers
1002 }
1003
1004 //------------------------------init_spill_mask--------------------------------
1005 void Matcher::init_spill_mask( Node *ret ) {
1006 if( idealreg2regmask[Op_RegI] ) return; // One time only init
1007
1008 OptoReg::c_frame_pointer = c_frame_pointer();
1009 c_frame_ptr_mask = c_frame_pointer();
1010 #ifdef _LP64
1011 // pointers are twice as big
1012 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
1013 #endif
1014
1015 // Start at OptoReg::stack0()
1016 STACK_ONLY_mask.Clear();
1017 OptoReg::Name init = OptoReg::stack2reg(0);
1018 // STACK_ONLY_mask is all stack bits
1019 OptoReg::Name i;
1020 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
1021 STACK_ONLY_mask.Insert(i);
1022 // Also set the "infinite stack" bit.
1023 STACK_ONLY_mask.set_AllStack();
1024
1025 for (i = OptoReg::Name(0); i < OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i, 1)) {
1026 // Copy the register names over into the shared world.
1027 // SharedInfo::regName[i] = regName[i];
1028 // Handy RegMasks per machine register
1029 mreg2regmask[i].Insert(i);
1030
1031 // Set up regmasks used to exclude save-on-call (and always-save) registers from debug masks.
1032 if (_register_save_policy[i] == 'C' ||
1033 _register_save_policy[i] == 'A') {
1034 caller_save_regmask.Insert(i);
1035 mh_caller_save_regmask.Insert(i);
1036 }
1037 // Exclude save-on-entry registers from debug masks for stub compilations.
1038 if (_register_save_policy[i] == 'C' ||
1039 _register_save_policy[i] == 'A' ||
1040 _register_save_policy[i] == 'E') {
1041 caller_save_regmask_exclude_soe.Insert(i);
1042 mh_caller_save_regmask_exclude_soe.Insert(i);
1043 }
1044 }
1045
1046 // Also exclude the register we use to save the SP for MethodHandle
1047 // invokes to from the corresponding MH debug masks
1048 const RegMask sp_save_mask = method_handle_invoke_SP_save_mask();
1049 mh_caller_save_regmask.OR(sp_save_mask);
1050 mh_caller_save_regmask_exclude_soe.OR(sp_save_mask);
1051
1052 // Grab the Frame Pointer
1053 Node *fp = ret->in(TypeFunc::FramePtr);
1054 // Share frame pointer while making spill ops
1055 set_shared(fp);
1056
1057 // Get the ADLC notion of the right regmask, for each basic type.
1058 #ifdef _LP64
1059 idealreg2regmask[Op_RegN] = regmask_for_ideal_register(Op_RegN, ret);
1060 #endif
1061 idealreg2regmask[Op_RegI] = regmask_for_ideal_register(Op_RegI, ret);
1062 idealreg2regmask[Op_RegP] = regmask_for_ideal_register(Op_RegP, ret);
1063 idealreg2regmask[Op_RegF] = regmask_for_ideal_register(Op_RegF, ret);
1064 idealreg2regmask[Op_RegD] = regmask_for_ideal_register(Op_RegD, ret);
1065 idealreg2regmask[Op_RegL] = regmask_for_ideal_register(Op_RegL, ret);
1066 idealreg2regmask[Op_VecA] = regmask_for_ideal_register(Op_VecA, ret);
1067 idealreg2regmask[Op_VecS] = regmask_for_ideal_register(Op_VecS, ret);
1068 idealreg2regmask[Op_VecD] = regmask_for_ideal_register(Op_VecD, ret);
1069 idealreg2regmask[Op_VecX] = regmask_for_ideal_register(Op_VecX, ret);
1070 idealreg2regmask[Op_VecY] = regmask_for_ideal_register(Op_VecY, ret);
1071 idealreg2regmask[Op_VecZ] = regmask_for_ideal_register(Op_VecZ, ret);
1072 idealreg2regmask[Op_RegVectMask] = regmask_for_ideal_register(Op_RegVectMask, ret);
1073 }
1074
1075 #ifdef ASSERT
1076 static void match_alias_type(Compile* C, Node* n, Node* m) {
1077 if (!VerifyAliases) return; // do not go looking for trouble by default
1078 const TypePtr* nat = n->adr_type();
1079 const TypePtr* mat = m->adr_type();
1080 int nidx = C->get_alias_index(nat);
1081 int midx = C->get_alias_index(mat);
1082 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
1083 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
1084 for (uint i = 1; i < n->req(); i++) {
1085 Node* n1 = n->in(i);
1086 const TypePtr* n1at = n1->adr_type();
1087 if (n1at != nullptr) {
1088 nat = n1at;
1089 nidx = C->get_alias_index(n1at);
1090 }
1091 }
1092 }
1093 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
1094 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
1095 switch (n->Opcode()) {
1096 case Op_PrefetchAllocation:
1097 nidx = Compile::AliasIdxRaw;
1098 nat = TypeRawPtr::BOTTOM;
1099 break;
1100 }
1101 }
1102 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
1103 switch (n->Opcode()) {
1104 case Op_ClearArray:
1105 midx = Compile::AliasIdxRaw;
1106 mat = TypeRawPtr::BOTTOM;
1107 break;
1108 }
1109 }
1110 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
1111 switch (n->Opcode()) {
1112 case Op_Return:
1113 case Op_Rethrow:
1114 case Op_Halt:
1115 case Op_TailCall:
1116 case Op_TailJump:
1117 case Op_ForwardException:
1118 nidx = Compile::AliasIdxBot;
1119 nat = TypePtr::BOTTOM;
1120 break;
1121 }
1122 }
1123 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
1124 switch (n->Opcode()) {
1125 case Op_StrComp:
1126 case Op_StrEquals:
1127 case Op_StrIndexOf:
1128 case Op_StrIndexOfChar:
1129 case Op_AryEq:
1130 case Op_VectorizedHashCode:
1131 case Op_CountPositives:
1132 case Op_MemBarVolatile:
1133 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
1134 case Op_StrInflatedCopy:
1135 case Op_StrCompressedCopy:
1136 case Op_OnSpinWait:
1137 case Op_EncodeISOArray:
1138 nidx = Compile::AliasIdxTop;
1139 nat = nullptr;
1140 break;
1141 }
1142 }
1143 if (nidx != midx) {
1144 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
1145 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
1146 n->dump();
1147 m->dump();
1148 }
1149 assert(C->subsume_loads() && C->must_alias(nat, midx),
1150 "must not lose alias info when matching");
1151 }
1152 }
1153 #endif
1154
1155 //------------------------------xform------------------------------------------
1156 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1157 // Node in new-space. Given a new-space Node, recursively walk his children.
1158 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1159 Node *Matcher::xform( Node *n, int max_stack ) {
1160 // Use one stack to keep both: child's node/state and parent's node/index
1161 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1162 mstack.push(n, Visit, nullptr, -1); // set null as parent to indicate root
1163 while (mstack.is_nonempty()) {
1164 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1165 if (C->failing()) return nullptr;
1166 n = mstack.node(); // Leave node on stack
1167 Node_State nstate = mstack.state();
1168 if (nstate == Visit) {
1169 mstack.set_state(Post_Visit);
1170 Node *oldn = n;
1171 // Old-space or new-space check
1172 if (!C->node_arena()->contains(n)) {
1173 // Old space!
1174 Node* m;
1175 if (has_new_node(n)) { // Not yet Label/Reduced
1176 m = new_node(n);
1177 } else {
1178 if (!is_dontcare(n)) { // Matcher can match this guy
1179 // Calls match special. They match alone with no children.
1180 // Their children, the incoming arguments, match normally.
1181 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1182 if (C->failing()) return nullptr;
1183 if (m == nullptr) { Matcher::soft_match_failure(); return nullptr; }
1184 if (n->is_MemBar()) {
1185 m->as_MachMemBar()->set_adr_type(n->adr_type());
1186 }
1187 } else { // Nothing the matcher cares about
1188 if (n->is_Proj() && n->in(0) != nullptr && n->in(0)->is_Multi()) { // Projections?
1189 // Convert to machine-dependent projection
1190 RegMask* mask = nullptr;
1191 if (n->in(0)->is_Call() && n->in(0)->as_Call()->tf()->returns_inline_type_as_fields()) {
1192 mask = return_values_mask(n->in(0)->as_Call()->tf());
1193 }
1194 m = n->in(0)->as_Multi()->match(n->as_Proj(), this, mask);
1195 NOT_PRODUCT(record_new2old(m, n);)
1196 if (m->in(0) != nullptr) // m might be top
1197 collect_null_checks(m, n);
1198 } else { // Else just a regular 'ol guy
1199 m = n->clone(); // So just clone into new-space
1200 NOT_PRODUCT(record_new2old(m, n);)
1201 // Def-Use edges will be added incrementally as Uses
1202 // of this node are matched.
1203 assert(m->outcnt() == 0, "no Uses of this clone yet");
1204 }
1205 }
1206
1207 set_new_node(n, m); // Map old to new
1208 if (_old_node_note_array != nullptr) {
1209 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1210 n->_idx);
1211 C->set_node_notes_at(m->_idx, nn);
1212 }
1213 debug_only(match_alias_type(C, n, m));
1214 }
1215 n = m; // n is now a new-space node
1216 mstack.set_node(n);
1217 }
1218
1219 // New space!
1220 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1221
1222 int i;
1223 // Put precedence edges on stack first (match them last).
1224 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1225 Node *m = oldn->in(i);
1226 if (m == nullptr) break;
1227 // set -1 to call add_prec() instead of set_req() during Step1
1228 mstack.push(m, Visit, n, -1);
1229 }
1230
1231 // Handle precedence edges for interior nodes
1232 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1233 Node *m = n->in(i);
1234 if (m == nullptr || C->node_arena()->contains(m)) continue;
1235 n->rm_prec(i);
1236 // set -1 to call add_prec() instead of set_req() during Step1
1237 mstack.push(m, Visit, n, -1);
1238 }
1239
1240 // For constant debug info, I'd rather have unmatched constants.
1241 int cnt = n->req();
1242 JVMState* jvms = n->jvms();
1243 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1244
1245 // Now do only debug info. Clone constants rather than matching.
1246 // Constants are represented directly in the debug info without
1247 // the need for executable machine instructions.
1248 // Monitor boxes are also represented directly.
1249 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1250 Node *m = n->in(i); // Get input
1251 int op = m->Opcode();
1252 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1253 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1254 op == Op_ConF || op == Op_ConD || op == Op_ConL
1255 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1256 ) {
1257 m = m->clone();
1258 NOT_PRODUCT(record_new2old(m, n));
1259 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1260 mstack.push(m->in(0), Visit, m, 0);
1261 } else {
1262 mstack.push(m, Visit, n, i);
1263 }
1264 }
1265
1266 // And now walk his children, and convert his inputs to new-space.
1267 for( ; i >= 0; --i ) { // For all normal inputs do
1268 Node *m = n->in(i); // Get input
1269 if(m != nullptr)
1270 mstack.push(m, Visit, n, i);
1271 }
1272
1273 }
1274 else if (nstate == Post_Visit) {
1275 // Set xformed input
1276 Node *p = mstack.parent();
1277 if (p != nullptr) { // root doesn't have parent
1278 int i = (int)mstack.index();
1279 if (i >= 0)
1280 p->set_req(i, n); // required input
1281 else if (i == -1)
1282 p->add_prec(n); // precedence input
1283 else
1284 ShouldNotReachHere();
1285 }
1286 mstack.pop(); // remove processed node from stack
1287 }
1288 else {
1289 ShouldNotReachHere();
1290 }
1291 } // while (mstack.is_nonempty())
1292 return n; // Return new-space Node
1293 }
1294
1295 //------------------------------warp_outgoing_stk_arg------------------------
1296 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1297 // Convert outgoing argument location to a pre-biased stack offset
1298 if (reg->is_stack()) {
1299 OptoReg::Name warped = reg->reg2stack();
1300 // Adjust the stack slot offset to be the register number used
1301 // by the allocator.
1302 warped = OptoReg::add(begin_out_arg_area, warped);
1303 // Keep track of the largest numbered stack slot used for an arg.
1304 // Largest used slot per call-site indicates the amount of stack
1305 // that is killed by the call.
1306 if( warped >= out_arg_limit_per_call )
1307 out_arg_limit_per_call = OptoReg::add(warped,1);
1308 if (!RegMask::can_represent_arg(warped)) {
1309 // Bailout. For example not enough space on stack for all arguments. Happens for methods with too many arguments.
1310 C->record_method_not_compilable("unsupported calling sequence");
1311 return OptoReg::Bad;
1312 }
1313 return warped;
1314 }
1315 return OptoReg::as_OptoReg(reg);
1316 }
1317
1318
1319 //------------------------------match_sfpt-------------------------------------
1320 // Helper function to match call instructions. Calls match special.
1321 // They match alone with no children. Their children, the incoming
1322 // arguments, match normally.
1323 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1324 MachSafePointNode *msfpt = nullptr;
1325 MachCallNode *mcall = nullptr;
1326 uint cnt;
1327 // Split out case for SafePoint vs Call
1328 CallNode *call;
1329 const TypeTuple *domain;
1330 ciMethod* method = nullptr;
1331 bool is_method_handle_invoke = false; // for special kill effects
1332 if( sfpt->is_Call() ) {
1333 call = sfpt->as_Call();
1334 domain = call->tf()->domain_cc();
1335 cnt = domain->cnt();
1336
1337 // Match just the call, nothing else
1338 MachNode *m = match_tree(call);
1339 if (C->failing()) return nullptr;
1340 if( m == nullptr ) { Matcher::soft_match_failure(); return nullptr; }
1341
1342 // Copy data from the Ideal SafePoint to the machine version
1343 mcall = m->as_MachCall();
1344
1345 mcall->set_tf( call->tf());
1346 mcall->set_entry_point( call->entry_point());
1347 mcall->set_cnt( call->cnt());
1348 mcall->set_guaranteed_safepoint(call->guaranteed_safepoint());
1349
1350 if( mcall->is_MachCallJava() ) {
1351 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1352 const CallJavaNode *call_java = call->as_CallJava();
1353 assert(call_java->validate_symbolic_info(), "inconsistent info");
1354 method = call_java->method();
1355 mcall_java->_method = method;
1356 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1357 is_method_handle_invoke = call_java->is_method_handle_invoke();
1358 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1359 mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1360 mcall_java->_arg_escape = call_java->arg_escape();
1361 if (is_method_handle_invoke) {
1362 C->set_has_method_handle_invokes(true);
1363 }
1364 if( mcall_java->is_MachCallStaticJava() )
1365 mcall_java->as_MachCallStaticJava()->_name =
1366 call_java->as_CallStaticJava()->_name;
1367 if( mcall_java->is_MachCallDynamicJava() )
1368 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1369 call_java->as_CallDynamicJava()->_vtable_index;
1370 }
1371 else if( mcall->is_MachCallRuntime() ) {
1372 MachCallRuntimeNode* mach_call_rt = mcall->as_MachCallRuntime();
1373 mach_call_rt->_name = call->as_CallRuntime()->_name;
1374 mach_call_rt->_leaf_no_fp = call->is_CallLeafNoFP();
1375 }
1376 msfpt = mcall;
1377 }
1378 // This is a non-call safepoint
1379 else {
1380 call = nullptr;
1381 domain = nullptr;
1382 MachNode *mn = match_tree(sfpt);
1383 if (C->failing()) return nullptr;
1384 msfpt = mn->as_MachSafePoint();
1385 cnt = TypeFunc::Parms;
1386 }
1387 msfpt->_has_ea_local_in_scope = sfpt->has_ea_local_in_scope();
1388
1389 // Advertise the correct memory effects (for anti-dependence computation).
1390 msfpt->set_adr_type(sfpt->adr_type());
1391
1392 // Allocate a private array of RegMasks. These RegMasks are not shared.
1393 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1394 // Empty them all.
1395 for (uint i = 0; i < cnt; i++) ::new (&(msfpt->_in_rms[i])) RegMask();
1396
1397 // Do all the pre-defined non-Empty register masks
1398 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1399 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1400
1401 // Place first outgoing argument can possibly be put.
1402 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1403 assert( is_even(begin_out_arg_area), "" );
1404 // Compute max outgoing register number per call site.
1405 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1406 // Calls to C may hammer extra stack slots above and beyond any arguments.
1407 // These are usually backing store for register arguments for varargs.
1408 if( call != nullptr && call->is_CallRuntime() )
1409 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1410
1411
1412 // Do the normal argument list (parameters) register masks
1413 // Null entry point is a special cast where the target of the call
1414 // is in a register.
1415 int adj = (call != nullptr && call->entry_point() == nullptr) ? 1 : 0;
1416 int argcnt = cnt - TypeFunc::Parms - adj;
1417 if( argcnt > 0 ) { // Skip it all if we have no args
1418 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1419 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1420 int i;
1421 for( i = 0; i < argcnt; i++ ) {
1422 sig_bt[i] = domain->field_at(i+TypeFunc::Parms+adj)->basic_type();
1423 }
1424 // V-call to pick proper calling convention
1425 call->calling_convention( sig_bt, parm_regs, argcnt );
1426
1427 #ifdef ASSERT
1428 // Sanity check users' calling convention. Really handy during
1429 // the initial porting effort. Fairly expensive otherwise.
1430 { for (int i = 0; i<argcnt; i++) {
1431 if( !parm_regs[i].first()->is_valid() &&
1432 !parm_regs[i].second()->is_valid() ) continue;
1433 VMReg reg1 = parm_regs[i].first();
1434 VMReg reg2 = parm_regs[i].second();
1435 for (int j = 0; j < i; j++) {
1436 if( !parm_regs[j].first()->is_valid() &&
1437 !parm_regs[j].second()->is_valid() ) continue;
1438 VMReg reg3 = parm_regs[j].first();
1439 VMReg reg4 = parm_regs[j].second();
1440 if( !reg1->is_valid() ) {
1441 assert( !reg2->is_valid(), "valid halvsies" );
1442 } else if( !reg3->is_valid() ) {
1443 assert( !reg4->is_valid(), "valid halvsies" );
1444 } else {
1445 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1446 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1447 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1448 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1449 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1450 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1451 }
1452 }
1453 }
1454 }
1455 #endif
1456
1457 // Visit each argument. Compute its outgoing register mask.
1458 // Return results now can have 2 bits returned.
1459 // Compute max over all outgoing arguments both per call-site
1460 // and over the entire method.
1461 for( i = 0; i < argcnt; i++ ) {
1462 // Address of incoming argument mask to fill in
1463 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms+adj];
1464 VMReg first = parm_regs[i].first();
1465 VMReg second = parm_regs[i].second();
1466 if(!first->is_valid() &&
1467 !second->is_valid()) {
1468 continue; // Avoid Halves
1469 }
1470 // Handle case where arguments are in vector registers.
1471 if(call->in(TypeFunc::Parms + i)->bottom_type()->isa_vect()) {
1472 OptoReg::Name reg_fst = OptoReg::as_OptoReg(first);
1473 OptoReg::Name reg_snd = OptoReg::as_OptoReg(second);
1474 assert (reg_fst <= reg_snd, "fst=%d snd=%d", reg_fst, reg_snd);
1475 for (OptoReg::Name r = reg_fst; r <= reg_snd; r++) {
1476 rm->Insert(r);
1477 }
1478 }
1479 // Grab first register, adjust stack slots and insert in mask.
1480 OptoReg::Name reg1 = warp_outgoing_stk_arg(first, begin_out_arg_area, out_arg_limit_per_call );
1481 if (OptoReg::is_valid(reg1)) {
1482 rm->Insert( reg1 );
1483 }
1484 // Grab second register (if any), adjust stack slots and insert in mask.
1485 OptoReg::Name reg2 = warp_outgoing_stk_arg(second, begin_out_arg_area, out_arg_limit_per_call );
1486 if (OptoReg::is_valid(reg2)) {
1487 rm->Insert( reg2 );
1488 }
1489 } // End of for all arguments
1490 }
1491
1492 // Compute the max stack slot killed by any call. These will not be
1493 // available for debug info, and will be used to adjust FIRST_STACK_mask
1494 // after all call sites have been visited.
1495 if( _out_arg_limit < out_arg_limit_per_call)
1496 _out_arg_limit = out_arg_limit_per_call;
1497
1498 if (mcall) {
1499 // Kill the outgoing argument area, including any non-argument holes and
1500 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1501 // Since the max-per-method covers the max-per-call-site and debug info
1502 // is excluded on the max-per-method basis, debug info cannot land in
1503 // this killed area.
1504 uint r_cnt = mcall->tf()->range_sig()->cnt();
1505 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1506 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1507 // Bailout. We do not have space to represent all arguments.
1508 C->record_method_not_compilable("unsupported outgoing calling sequence");
1509 } else {
1510 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1511 proj->_rout.Insert(OptoReg::Name(i));
1512 }
1513 if (proj->_rout.is_NotEmpty()) {
1514 push_projection(proj);
1515 }
1516 }
1517 // Transfer the safepoint information from the call to the mcall
1518 // Move the JVMState list
1519 msfpt->set_jvms(sfpt->jvms());
1520 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1521 jvms->set_map(sfpt);
1522 }
1523
1524 // Debug inputs begin just after the last incoming parameter
1525 assert((mcall == nullptr) || (mcall->jvms() == nullptr) ||
1526 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain_cc()->cnt()), "");
1527
1528 // Add additional edges.
1529 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1530 // For these calls we can not add MachConstantBase in expand(), as the
1531 // ins are not complete then.
1532 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1533 if (msfpt->jvms() &&
1534 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1535 // We added an edge before jvms, so we must adapt the position of the ins.
1536 msfpt->jvms()->adapt_position(+1);
1537 }
1538 }
1539
1540 // Registers killed by the call are set in the local scheduling pass
1541 // of Global Code Motion.
1542 return msfpt;
1543 }
1544
1545 //---------------------------match_tree----------------------------------------
1546 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1547 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1548 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1549 // a Load's result RegMask for memoization in idealreg2regmask[]
1550 MachNode *Matcher::match_tree( const Node *n ) {
1551 assert( n->Opcode() != Op_Phi, "cannot match" );
1552 assert( !n->is_block_start(), "cannot match" );
1553 // Set the mark for all locally allocated State objects.
1554 // When this call returns, the _states_arena arena will be reset
1555 // freeing all State objects.
1556 ResourceMark rm( &_states_arena );
1557
1558 LabelRootDepth = 0;
1559
1560 // StoreNodes require their Memory input to match any LoadNodes
1561 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1562 #ifdef ASSERT
1563 Node* save_mem_node = _mem_node;
1564 _mem_node = n->is_Store() ? (Node*)n : nullptr;
1565 #endif
1566 // State object for root node of match tree
1567 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1568 State *s = new (&_states_arena) State;
1569 s->_kids[0] = nullptr;
1570 s->_kids[1] = nullptr;
1571 s->_leaf = (Node*)n;
1572 // Label the input tree, allocating labels from top-level arena
1573 Node* root_mem = mem;
1574 Label_Root(n, s, n->in(0), root_mem);
1575 if (C->failing()) return nullptr;
1576
1577 // The minimum cost match for the whole tree is found at the root State
1578 uint mincost = max_juint;
1579 uint cost = max_juint;
1580 uint i;
1581 for (i = 0; i < NUM_OPERANDS; i++) {
1582 if (s->valid(i) && // valid entry and
1583 s->cost(i) < cost && // low cost and
1584 s->rule(i) >= NUM_OPERANDS) {// not an operand
1585 mincost = i;
1586 cost = s->cost(i);
1587 }
1588 }
1589 if (mincost == max_juint) {
1590 #ifndef PRODUCT
1591 tty->print("No matching rule for:");
1592 s->dump();
1593 #endif
1594 Matcher::soft_match_failure();
1595 return nullptr;
1596 }
1597 // Reduce input tree based upon the state labels to machine Nodes
1598 MachNode *m = ReduceInst(s, s->rule(mincost), mem);
1599 // New-to-old mapping is done in ReduceInst, to cover complex instructions.
1600 NOT_PRODUCT(_old2new_map.map(n->_idx, m);)
1601
1602 // Add any Matcher-ignored edges
1603 uint cnt = n->req();
1604 uint start = 1;
1605 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1606 if( n->is_AddP() ) {
1607 assert( mem == (Node*)1, "" );
1608 start = AddPNode::Base+1;
1609 }
1610 for( i = start; i < cnt; i++ ) {
1611 if( !n->match_edge(i) ) {
1612 if( i < m->req() )
1613 m->ins_req( i, n->in(i) );
1614 else
1615 m->add_req( n->in(i) );
1616 }
1617 }
1618
1619 debug_only( _mem_node = save_mem_node; )
1620 return m;
1621 }
1622
1623
1624 //------------------------------match_into_reg---------------------------------
1625 // Choose to either match this Node in a register or part of the current
1626 // match tree. Return true for requiring a register and false for matching
1627 // as part of the current match tree.
1628 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1629
1630 const Type *t = m->bottom_type();
1631
1632 if (t->singleton()) {
1633 // Never force constants into registers. Allow them to match as
1634 // constants or registers. Copies of the same value will share
1635 // the same register. See find_shared_node.
1636 return false;
1637 } else { // Not a constant
1638 // Stop recursion if they have different Controls.
1639 Node* m_control = m->in(0);
1640 // Control of load's memory can post-dominates load's control.
1641 // So use it since load can't float above its memory.
1642 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : nullptr;
1643 if (control && m_control && control != m_control && control != mem_control) {
1644
1645 // Actually, we can live with the most conservative control we
1646 // find, if it post-dominates the others. This allows us to
1647 // pick up load/op/store trees where the load can float a little
1648 // above the store.
1649 Node *x = control;
1650 const uint max_scan = 6; // Arbitrary scan cutoff
1651 uint j;
1652 for (j=0; j<max_scan; j++) {
1653 if (x->is_Region()) // Bail out at merge points
1654 return true;
1655 x = x->in(0);
1656 if (x == m_control) // Does 'control' post-dominate
1657 break; // m->in(0)? If so, we can use it
1658 if (x == mem_control) // Does 'control' post-dominate
1659 break; // mem_control? If so, we can use it
1660 }
1661 if (j == max_scan) // No post-domination before scan end?
1662 return true; // Then break the match tree up
1663 }
1664 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1665 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1666 // These are commonly used in address expressions and can
1667 // efficiently fold into them on X64 in some cases.
1668 return false;
1669 }
1670 }
1671
1672 // Not forceable cloning. If shared, put it into a register.
1673 return shared;
1674 }
1675
1676
1677 //------------------------------Instruction Selection--------------------------
1678 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1679 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1680 // things the Matcher does not match (e.g., Memory), and things with different
1681 // Controls (hence forced into different blocks). We pass in the Control
1682 // selected for this entire State tree.
1683
1684 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1685 // Store and the Load must have identical Memories (as well as identical
1686 // pointers). Since the Matcher does not have anything for Memory (and
1687 // does not handle DAGs), I have to match the Memory input myself. If the
1688 // Tree root is a Store or if there are multiple Loads in the tree, I require
1689 // all Loads to have the identical memory.
1690 Node* Matcher::Label_Root(const Node* n, State* svec, Node* control, Node*& mem) {
1691 // Since Label_Root is a recursive function, its possible that we might run
1692 // out of stack space. See bugs 6272980 & 6227033 for more info.
1693 LabelRootDepth++;
1694 if (LabelRootDepth > MaxLabelRootDepth) {
1695 // Bailout. Can for example be hit with a deep chain of operations.
1696 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1697 return nullptr;
1698 }
1699 uint care = 0; // Edges matcher cares about
1700 uint cnt = n->req();
1701 uint i = 0;
1702
1703 // Examine children for memory state
1704 // Can only subsume a child into your match-tree if that child's memory state
1705 // is not modified along the path to another input.
1706 // It is unsafe even if the other inputs are separate roots.
1707 Node *input_mem = nullptr;
1708 for( i = 1; i < cnt; i++ ) {
1709 if( !n->match_edge(i) ) continue;
1710 Node *m = n->in(i); // Get ith input
1711 assert( m, "expect non-null children" );
1712 if( m->is_Load() ) {
1713 if( input_mem == nullptr ) {
1714 input_mem = m->in(MemNode::Memory);
1715 if (mem == (Node*)1) {
1716 // Save this memory to bail out if there's another memory access
1717 // to a different memory location in the same tree.
1718 mem = input_mem;
1719 }
1720 } else if( input_mem != m->in(MemNode::Memory) ) {
1721 input_mem = NodeSentinel;
1722 }
1723 }
1724 }
1725
1726 for( i = 1; i < cnt; i++ ){// For my children
1727 if( !n->match_edge(i) ) continue;
1728 Node *m = n->in(i); // Get ith input
1729 // Allocate states out of a private arena
1730 State *s = new (&_states_arena) State;
1731 svec->_kids[care++] = s;
1732 assert( care <= 2, "binary only for now" );
1733
1734 // Recursively label the State tree.
1735 s->_kids[0] = nullptr;
1736 s->_kids[1] = nullptr;
1737 s->_leaf = m;
1738
1739 // Check for leaves of the State Tree; things that cannot be a part of
1740 // the current tree. If it finds any, that value is matched as a
1741 // register operand. If not, then the normal matching is used.
1742 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1743 // Stop recursion if this is a LoadNode and there is another memory access
1744 // to a different memory location in the same tree (for example, a StoreNode
1745 // at the root of this tree or another LoadNode in one of the children).
1746 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1747 // Can NOT include the match of a subtree when its memory state
1748 // is used by any of the other subtrees
1749 (input_mem == NodeSentinel) ) {
1750 // Print when we exclude matching due to different memory states at input-loads
1751 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1752 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1753 tty->print_cr("invalid input_mem");
1754 }
1755 // Switch to a register-only opcode; this value must be in a register
1756 // and cannot be subsumed as part of a larger instruction.
1757 s->DFA( m->ideal_reg(), m );
1758
1759 } else {
1760 // If match tree has no control and we do, adopt it for entire tree
1761 if( control == nullptr && m->in(0) != nullptr && m->req() > 1 )
1762 control = m->in(0); // Pick up control
1763 // Else match as a normal part of the match tree.
1764 control = Label_Root(m, s, control, mem);
1765 if (C->failing()) return nullptr;
1766 }
1767 }
1768
1769 // Call DFA to match this node, and return
1770 svec->DFA( n->Opcode(), n );
1771
1772 #ifdef ASSERT
1773 uint x;
1774 for( x = 0; x < _LAST_MACH_OPER; x++ )
1775 if( svec->valid(x) )
1776 break;
1777
1778 if (x >= _LAST_MACH_OPER) {
1779 n->dump();
1780 svec->dump();
1781 assert( false, "bad AD file" );
1782 }
1783 #endif
1784 return control;
1785 }
1786
1787
1788 // Con nodes reduced using the same rule can share their MachNode
1789 // which reduces the number of copies of a constant in the final
1790 // program. The register allocator is free to split uses later to
1791 // split live ranges.
1792 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1793 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return nullptr;
1794
1795 // See if this Con has already been reduced using this rule.
1796 if (_shared_nodes.max() <= leaf->_idx) return nullptr;
1797 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1798 if (last != nullptr && rule == last->rule()) {
1799 // Don't expect control change for DecodeN
1800 if (leaf->is_DecodeNarrowPtr())
1801 return last;
1802 // Get the new space root.
1803 Node* xroot = new_node(C->root());
1804 if (xroot == nullptr) {
1805 // This shouldn't happen give the order of matching.
1806 return nullptr;
1807 }
1808
1809 // Shared constants need to have their control be root so they
1810 // can be scheduled properly.
1811 Node* control = last->in(0);
1812 if (control != xroot) {
1813 if (control == nullptr || control == C->root()) {
1814 last->set_req(0, xroot);
1815 } else {
1816 assert(false, "unexpected control");
1817 return nullptr;
1818 }
1819 }
1820 return last;
1821 }
1822 return nullptr;
1823 }
1824
1825
1826 //------------------------------ReduceInst-------------------------------------
1827 // Reduce a State tree (with given Control) into a tree of MachNodes.
1828 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1829 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1830 // Each MachNode has a number of complicated MachOper operands; each
1831 // MachOper also covers a further tree of Ideal Nodes.
1832
1833 // The root of the Ideal match tree is always an instruction, so we enter
1834 // the recursion here. After building the MachNode, we need to recurse
1835 // the tree checking for these cases:
1836 // (1) Child is an instruction -
1837 // Build the instruction (recursively), add it as an edge.
1838 // Build a simple operand (register) to hold the result of the instruction.
1839 // (2) Child is an interior part of an instruction -
1840 // Skip over it (do nothing)
1841 // (3) Child is the start of a operand -
1842 // Build the operand, place it inside the instruction
1843 // Call ReduceOper.
1844 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1845 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1846
1847 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1848 if (shared_node != nullptr) {
1849 return shared_node;
1850 }
1851
1852 // Build the object to represent this state & prepare for recursive calls
1853 MachNode *mach = s->MachNodeGenerator(rule);
1854 guarantee(mach != nullptr, "Missing MachNode");
1855 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1856 assert( mach->_opnds[0] != nullptr, "Missing result operand" );
1857 Node *leaf = s->_leaf;
1858 NOT_PRODUCT(record_new2old(mach, leaf);)
1859 // Check for instruction or instruction chain rule
1860 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1861 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1862 "duplicating node that's already been matched");
1863 // Instruction
1864 mach->add_req( leaf->in(0) ); // Set initial control
1865 // Reduce interior of complex instruction
1866 ReduceInst_Interior( s, rule, mem, mach, 1 );
1867 } else {
1868 // Instruction chain rules are data-dependent on their inputs
1869 mach->add_req(nullptr); // Set initial control to none
1870 ReduceInst_Chain_Rule( s, rule, mem, mach );
1871 }
1872
1873 // If a Memory was used, insert a Memory edge
1874 if( mem != (Node*)1 ) {
1875 mach->ins_req(MemNode::Memory,mem);
1876 #ifdef ASSERT
1877 // Verify adr type after matching memory operation
1878 const MachOper* oper = mach->memory_operand();
1879 if (oper != nullptr && oper != (MachOper*)-1) {
1880 // It has a unique memory operand. Find corresponding ideal mem node.
1881 Node* m = nullptr;
1882 if (leaf->is_Mem()) {
1883 m = leaf;
1884 } else {
1885 m = _mem_node;
1886 assert(m != nullptr && m->is_Mem(), "expecting memory node");
1887 }
1888 const Type* mach_at = mach->adr_type();
1889 // DecodeN node consumed by an address may have different type
1890 // than its input. Don't compare types for such case.
1891 if (m->adr_type() != mach_at &&
1892 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1893 (m->in(MemNode::Address)->is_AddP() &&
1894 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) ||
1895 (m->in(MemNode::Address)->is_AddP() &&
1896 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1897 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) {
1898 mach_at = m->adr_type();
1899 }
1900 if (m->adr_type() != mach_at) {
1901 m->dump();
1902 tty->print_cr("mach:");
1903 mach->dump(1);
1904 }
1905 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1906 }
1907 #endif
1908 }
1909
1910 // If the _leaf is an AddP, insert the base edge
1911 if (leaf->is_AddP()) {
1912 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1913 }
1914
1915 uint number_of_projections_prior = number_of_projections();
1916
1917 // Perform any 1-to-many expansions required
1918 MachNode *ex = mach->Expand(s, _projection_list, mem);
1919 if (ex != mach) {
1920 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1921 if( ex->in(1)->is_Con() )
1922 ex->in(1)->set_req(0, C->root());
1923 // Remove old node from the graph
1924 for( uint i=0; i<mach->req(); i++ ) {
1925 mach->set_req(i,nullptr);
1926 }
1927 NOT_PRODUCT(record_new2old(ex, s->_leaf);)
1928 }
1929
1930 // PhaseChaitin::fixup_spills will sometimes generate spill code
1931 // via the matcher. By the time, nodes have been wired into the CFG,
1932 // and any further nodes generated by expand rules will be left hanging
1933 // in space, and will not get emitted as output code. Catch this.
1934 // Also, catch any new register allocation constraints ("projections")
1935 // generated belatedly during spill code generation.
1936 if (_allocation_started) {
1937 guarantee(ex == mach, "no expand rules during spill generation");
1938 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1939 }
1940
1941 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1942 // Record the con for sharing
1943 _shared_nodes.map(leaf->_idx, ex);
1944 }
1945
1946 // Have mach nodes inherit GC barrier data
1947 mach->set_barrier_data(MemNode::barrier_data(leaf));
1948
1949 return ex;
1950 }
1951
1952 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1953 for (uint i = n->req(); i < n->len(); i++) {
1954 if (n->in(i) != nullptr) {
1955 mach->add_prec(n->in(i));
1956 }
1957 }
1958 }
1959
1960 void Matcher::ReduceInst_Chain_Rule(State* s, int rule, Node* &mem, MachNode* mach) {
1961 // 'op' is what I am expecting to receive
1962 int op = _leftOp[rule];
1963 // Operand type to catch childs result
1964 // This is what my child will give me.
1965 unsigned int opnd_class_instance = s->rule(op);
1966 // Choose between operand class or not.
1967 // This is what I will receive.
1968 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1969 // New rule for child. Chase operand classes to get the actual rule.
1970 unsigned int newrule = s->rule(catch_op);
1971
1972 if (newrule < NUM_OPERANDS) {
1973 // Chain from operand or operand class, may be output of shared node
1974 assert(opnd_class_instance < NUM_OPERANDS, "Bad AD file: Instruction chain rule must chain from operand");
1975 // Insert operand into array of operands for this instruction
1976 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1977
1978 ReduceOper(s, newrule, mem, mach);
1979 } else {
1980 // Chain from the result of an instruction
1981 assert(newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1982 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1983 Node *mem1 = (Node*)1;
1984 debug_only(Node *save_mem_node = _mem_node;)
1985 mach->add_req( ReduceInst(s, newrule, mem1) );
1986 debug_only(_mem_node = save_mem_node;)
1987 }
1988 return;
1989 }
1990
1991
1992 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1993 handle_precedence_edges(s->_leaf, mach);
1994
1995 if( s->_leaf->is_Load() ) {
1996 Node *mem2 = s->_leaf->in(MemNode::Memory);
1997 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1998 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1999 mem = mem2;
2000 }
2001 if( s->_leaf->in(0) != nullptr && s->_leaf->req() > 1) {
2002 if( mach->in(0) == nullptr )
2003 mach->set_req(0, s->_leaf->in(0));
2004 }
2005
2006 // Now recursively walk the state tree & add operand list.
2007 for( uint i=0; i<2; i++ ) { // binary tree
2008 State *newstate = s->_kids[i];
2009 if( newstate == nullptr ) break; // Might only have 1 child
2010 // 'op' is what I am expecting to receive
2011 int op;
2012 if( i == 0 ) {
2013 op = _leftOp[rule];
2014 } else {
2015 op = _rightOp[rule];
2016 }
2017 // Operand type to catch childs result
2018 // This is what my child will give me.
2019 int opnd_class_instance = newstate->rule(op);
2020 // Choose between operand class or not.
2021 // This is what I will receive.
2022 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
2023 // New rule for child. Chase operand classes to get the actual rule.
2024 int newrule = newstate->rule(catch_op);
2025
2026 if (newrule < NUM_OPERANDS) { // Operand/operandClass or internalOp/instruction?
2027 // Operand/operandClass
2028 // Insert operand into array of operands for this instruction
2029 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
2030 ReduceOper(newstate, newrule, mem, mach);
2031
2032 } else { // Child is internal operand or new instruction
2033 if (newrule < _LAST_MACH_OPER) { // internal operand or instruction?
2034 // internal operand --> call ReduceInst_Interior
2035 // Interior of complex instruction. Do nothing but recurse.
2036 num_opnds = ReduceInst_Interior(newstate, newrule, mem, mach, num_opnds);
2037 } else {
2038 // instruction --> call build operand( ) to catch result
2039 // --> ReduceInst( newrule )
2040 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
2041 Node *mem1 = (Node*)1;
2042 debug_only(Node *save_mem_node = _mem_node;)
2043 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
2044 debug_only(_mem_node = save_mem_node;)
2045 }
2046 }
2047 assert( mach->_opnds[num_opnds-1], "" );
2048 }
2049 return num_opnds;
2050 }
2051
2052 // This routine walks the interior of possible complex operands.
2053 // At each point we check our children in the match tree:
2054 // (1) No children -
2055 // We are a leaf; add _leaf field as an input to the MachNode
2056 // (2) Child is an internal operand -
2057 // Skip over it ( do nothing )
2058 // (3) Child is an instruction -
2059 // Call ReduceInst recursively and
2060 // and instruction as an input to the MachNode
2061 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
2062 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
2063 State *kid = s->_kids[0];
2064 assert( kid == nullptr || s->_leaf->in(0) == nullptr, "internal operands have no control" );
2065
2066 // Leaf? And not subsumed?
2067 if( kid == nullptr && !_swallowed[rule] ) {
2068 mach->add_req( s->_leaf ); // Add leaf pointer
2069 return; // Bail out
2070 }
2071
2072 if( s->_leaf->is_Load() ) {
2073 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
2074 mem = s->_leaf->in(MemNode::Memory);
2075 debug_only(_mem_node = s->_leaf;)
2076 }
2077
2078 handle_precedence_edges(s->_leaf, mach);
2079
2080 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
2081 if( !mach->in(0) )
2082 mach->set_req(0,s->_leaf->in(0));
2083 else {
2084 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
2085 }
2086 }
2087
2088 for (uint i = 0; kid != nullptr && i < 2; kid = s->_kids[1], i++) { // binary tree
2089 int newrule;
2090 if( i == 0) {
2091 newrule = kid->rule(_leftOp[rule]);
2092 } else {
2093 newrule = kid->rule(_rightOp[rule]);
2094 }
2095
2096 if (newrule < _LAST_MACH_OPER) { // Operand or instruction?
2097 // Internal operand; recurse but do nothing else
2098 ReduceOper(kid, newrule, mem, mach);
2099
2100 } else { // Child is a new instruction
2101 // Reduce the instruction, and add a direct pointer from this
2102 // machine instruction to the newly reduced one.
2103 Node *mem1 = (Node*)1;
2104 debug_only(Node *save_mem_node = _mem_node;)
2105 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
2106 debug_only(_mem_node = save_mem_node;)
2107 }
2108 }
2109 }
2110
2111
2112 // -------------------------------------------------------------------------
2113 // Java-Java calling convention
2114 // (what you use when Java calls Java)
2115
2116 //------------------------------find_receiver----------------------------------
2117 // For a given signature, return the OptoReg for parameter 0.
2118 OptoReg::Name Matcher::find_receiver() {
2119 VMRegPair regs;
2120 BasicType sig_bt = T_OBJECT;
2121 SharedRuntime::java_calling_convention(&sig_bt, ®s, 1);
2122 // Return argument 0 register. In the LP64 build pointers
2123 // take 2 registers, but the VM wants only the 'main' name.
2124 return OptoReg::as_OptoReg(regs.first());
2125 }
2126
2127 bool Matcher::is_vshift_con_pattern(Node* n, Node* m) {
2128 if (n != nullptr && m != nullptr) {
2129 return VectorNode::is_vector_shift(n) &&
2130 VectorNode::is_vector_shift_count(m) && m->in(1)->is_Con();
2131 }
2132 return false;
2133 }
2134
2135 bool Matcher::clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2136 // Must clone all producers of flags, or we will not match correctly.
2137 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2138 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2139 // are also there, so we may match a float-branch to int-flags and
2140 // expect the allocator to haul the flags from the int-side to the
2141 // fp-side. No can do.
2142 if (_must_clone[m->Opcode()]) {
2143 mstack.push(m, Visit);
2144 return true;
2145 }
2146 return pd_clone_node(n, m, mstack);
2147 }
2148
2149 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2150 Node *off = m->in(AddPNode::Offset);
2151 if (off->is_Con()) {
2152 address_visited.test_set(m->_idx); // Flag as address_visited
2153 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2154 // Clone X+offset as it also folds into most addressing expressions
2155 mstack.push(off, Visit);
2156 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2157 return true;
2158 }
2159 return false;
2160 }
2161
2162 // A method-klass-holder may be passed in the inline_cache_reg
2163 // and then expanded into the inline_cache_reg and a method_ptr register
2164 // defined in ad_<arch>.cpp
2165
2166 //------------------------------find_shared------------------------------------
2167 // Set bits if Node is shared or otherwise a root
2168 void Matcher::find_shared(Node* n) {
2169 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2170 MStack mstack(C->live_nodes() * 2);
2171 // Mark nodes as address_visited if they are inputs to an address expression
2172 VectorSet address_visited;
2173 mstack.push(n, Visit); // Don't need to pre-visit root node
2174 while (mstack.is_nonempty()) {
2175 n = mstack.node(); // Leave node on stack
2176 Node_State nstate = mstack.state();
2177 uint nop = n->Opcode();
2178 if (nstate == Pre_Visit) {
2179 if (address_visited.test(n->_idx)) { // Visited in address already?
2180 // Flag as visited and shared now.
2181 set_visited(n);
2182 }
2183 if (is_visited(n)) { // Visited already?
2184 // Node is shared and has no reason to clone. Flag it as shared.
2185 // This causes it to match into a register for the sharing.
2186 set_shared(n); // Flag as shared and
2187 if (n->is_DecodeNarrowPtr()) {
2188 // Oop field/array element loads must be shared but since
2189 // they are shared through a DecodeN they may appear to have
2190 // a single use so force sharing here.
2191 set_shared(n->in(1));
2192 }
2193 mstack.pop(); // remove node from stack
2194 continue;
2195 }
2196 nstate = Visit; // Not already visited; so visit now
2197 }
2198 if (nstate == Visit) {
2199 mstack.set_state(Post_Visit);
2200 set_visited(n); // Flag as visited now
2201 bool mem_op = false;
2202 int mem_addr_idx = MemNode::Address;
2203 if (find_shared_visit(mstack, n, nop, mem_op, mem_addr_idx)) {
2204 continue;
2205 }
2206 for (int i = n->len() - 1; i >= 0; --i) { // For my children
2207 Node* m = n->in(i); // Get ith input
2208 if (m == nullptr) {
2209 continue; // Ignore nulls
2210 }
2211 if (clone_node(n, m, mstack)) {
2212 continue;
2213 }
2214
2215 // Clone addressing expressions as they are "free" in memory access instructions
2216 if (mem_op && i == mem_addr_idx && m->is_AddP() &&
2217 // When there are other uses besides address expressions
2218 // put it on stack and mark as shared.
2219 !is_visited(m)) {
2220 // Some inputs for address expression are not put on stack
2221 // to avoid marking them as shared and forcing them into register
2222 // if they are used only in address expressions.
2223 // But they should be marked as shared if there are other uses
2224 // besides address expressions.
2225
2226 if (pd_clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2227 continue;
2228 }
2229 } // if( mem_op &&
2230 mstack.push(m, Pre_Visit);
2231 } // for(int i = ...)
2232 }
2233 else if (nstate == Alt_Post_Visit) {
2234 mstack.pop(); // Remove node from stack
2235 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2236 // shared and all users of the Bool need to move the Cmp in parallel.
2237 // This leaves both the Bool and the If pointing at the Cmp. To
2238 // prevent the Matcher from trying to Match the Cmp along both paths
2239 // BoolNode::match_edge always returns a zero.
2240
2241 // We reorder the Op_If in a pre-order manner, so we can visit without
2242 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2243 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2244 }
2245 else if (nstate == Post_Visit) {
2246 mstack.pop(); // Remove node from stack
2247
2248 // Now hack a few special opcodes
2249 uint opcode = n->Opcode();
2250 bool gc_handled = BarrierSet::barrier_set()->barrier_set_c2()->matcher_find_shared_post_visit(this, n, opcode);
2251 if (!gc_handled) {
2252 find_shared_post_visit(n, opcode);
2253 }
2254 }
2255 else {
2256 ShouldNotReachHere();
2257 }
2258 } // end of while (mstack.is_nonempty())
2259 }
2260
2261 bool Matcher::find_shared_visit(MStack& mstack, Node* n, uint opcode, bool& mem_op, int& mem_addr_idx) {
2262 switch(opcode) { // Handle some opcodes special
2263 case Op_Phi: // Treat Phis as shared roots
2264 case Op_Parm:
2265 case Op_Proj: // All handled specially during matching
2266 case Op_SafePointScalarObject:
2267 set_shared(n);
2268 set_dontcare(n);
2269 break;
2270 case Op_If:
2271 case Op_CountedLoopEnd:
2272 mstack.set_state(Alt_Post_Visit); // Alternative way
2273 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2274 // with matching cmp/branch in 1 instruction. The Matcher needs the
2275 // Bool and CmpX side-by-side, because it can only get at constants
2276 // that are at the leaves of Match trees, and the Bool's condition acts
2277 // as a constant here.
2278 mstack.push(n->in(1), Visit); // Clone the Bool
2279 mstack.push(n->in(0), Pre_Visit); // Visit control input
2280 return true; // while (mstack.is_nonempty())
2281 case Op_ConvI2D: // These forms efficiently match with a prior
2282 case Op_ConvI2F: // Load but not a following Store
2283 if( n->in(1)->is_Load() && // Prior load
2284 n->outcnt() == 1 && // Not already shared
2285 n->unique_out()->is_Store() ) // Following store
2286 set_shared(n); // Force it to be a root
2287 break;
2288 case Op_ReverseBytesI:
2289 case Op_ReverseBytesL:
2290 if( n->in(1)->is_Load() && // Prior load
2291 n->outcnt() == 1 ) // Not already shared
2292 set_shared(n); // Force it to be a root
2293 break;
2294 case Op_BoxLock: // Can't match until we get stack-regs in ADLC
2295 case Op_IfFalse:
2296 case Op_IfTrue:
2297 case Op_MachProj:
2298 case Op_MergeMem:
2299 case Op_Catch:
2300 case Op_CatchProj:
2301 case Op_CProj:
2302 case Op_JumpProj:
2303 case Op_JProj:
2304 case Op_NeverBranch:
2305 set_dontcare(n);
2306 break;
2307 case Op_Jump:
2308 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2309 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2310 return true; // while (mstack.is_nonempty())
2311 case Op_StrComp:
2312 case Op_StrEquals:
2313 case Op_StrIndexOf:
2314 case Op_StrIndexOfChar:
2315 case Op_AryEq:
2316 case Op_VectorizedHashCode:
2317 case Op_CountPositives:
2318 case Op_StrInflatedCopy:
2319 case Op_StrCompressedCopy:
2320 case Op_EncodeISOArray:
2321 case Op_FmaD:
2322 case Op_FmaF:
2323 case Op_FmaVD:
2324 case Op_FmaVF:
2325 case Op_MacroLogicV:
2326 case Op_VectorCmpMasked:
2327 case Op_CompressV:
2328 case Op_CompressM:
2329 case Op_ExpandV:
2330 case Op_VectorLoadMask:
2331 set_shared(n); // Force result into register (it will be anyways)
2332 break;
2333 case Op_ConP: { // Convert pointers above the centerline to NUL
2334 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2335 const TypePtr* tp = tn->type()->is_ptr();
2336 if (tp->_ptr == TypePtr::AnyNull) {
2337 tn->set_type(TypePtr::NULL_PTR);
2338 }
2339 break;
2340 }
2341 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2342 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2343 const TypePtr* tp = tn->type()->make_ptr();
2344 if (tp && tp->_ptr == TypePtr::AnyNull) {
2345 tn->set_type(TypeNarrowOop::NULL_PTR);
2346 }
2347 break;
2348 }
2349 case Op_Binary: // These are introduced in the Post_Visit state.
2350 ShouldNotReachHere();
2351 break;
2352 case Op_ClearArray:
2353 case Op_SafePoint:
2354 mem_op = true;
2355 break;
2356 default:
2357 if( n->is_Store() ) {
2358 // Do match stores, despite no ideal reg
2359 mem_op = true;
2360 break;
2361 }
2362 if( n->is_Mem() ) { // Loads and LoadStores
2363 mem_op = true;
2364 // Loads must be root of match tree due to prior load conflict
2365 if( C->subsume_loads() == false )
2366 set_shared(n);
2367 }
2368 // Fall into default case
2369 if( !n->ideal_reg() )
2370 set_dontcare(n); // Unmatchable Nodes
2371 } // end_switch
2372 return false;
2373 }
2374
2375 void Matcher::find_shared_post_visit(Node* n, uint opcode) {
2376 if (n->is_predicated_vector()) {
2377 // Restructure into binary trees for Matching.
2378 if (n->req() == 4) {
2379 n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2380 n->set_req(2, n->in(3));
2381 n->del_req(3);
2382 } else if (n->req() == 5) {
2383 n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2384 n->set_req(2, new BinaryNode(n->in(3), n->in(4)));
2385 n->del_req(4);
2386 n->del_req(3);
2387 } else if (n->req() == 6) {
2388 Node* b3 = new BinaryNode(n->in(4), n->in(5));
2389 Node* b2 = new BinaryNode(n->in(3), b3);
2390 Node* b1 = new BinaryNode(n->in(2), b2);
2391 n->set_req(2, b1);
2392 n->del_req(5);
2393 n->del_req(4);
2394 n->del_req(3);
2395 }
2396 return;
2397 }
2398
2399 switch(opcode) { // Handle some opcodes special
2400 case Op_CompareAndExchangeB:
2401 case Op_CompareAndExchangeS:
2402 case Op_CompareAndExchangeI:
2403 case Op_CompareAndExchangeL:
2404 case Op_CompareAndExchangeP:
2405 case Op_CompareAndExchangeN:
2406 case Op_WeakCompareAndSwapB:
2407 case Op_WeakCompareAndSwapS:
2408 case Op_WeakCompareAndSwapI:
2409 case Op_WeakCompareAndSwapL:
2410 case Op_WeakCompareAndSwapP:
2411 case Op_WeakCompareAndSwapN:
2412 case Op_CompareAndSwapB:
2413 case Op_CompareAndSwapS:
2414 case Op_CompareAndSwapI:
2415 case Op_CompareAndSwapL:
2416 case Op_CompareAndSwapP:
2417 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2418 Node* newval = n->in(MemNode::ValueIn);
2419 Node* oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2420 Node* pair = new BinaryNode(oldval, newval);
2421 n->set_req(MemNode::ValueIn, pair);
2422 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2423 break;
2424 }
2425 case Op_CMoveD: // Convert trinary to binary-tree
2426 case Op_CMoveF:
2427 case Op_CMoveI:
2428 case Op_CMoveL:
2429 case Op_CMoveN:
2430 case Op_CMoveP: {
2431 // Restructure into a binary tree for Matching. It's possible that
2432 // we could move this code up next to the graph reshaping for IfNodes
2433 // or vice-versa, but I do not want to debug this for Ladybird.
2434 // 10/2/2000 CNC.
2435 Node* pair1 = new BinaryNode(n->in(1), n->in(1)->in(1));
2436 n->set_req(1, pair1);
2437 Node* pair2 = new BinaryNode(n->in(2), n->in(3));
2438 n->set_req(2, pair2);
2439 n->del_req(3);
2440 break;
2441 }
2442 case Op_MacroLogicV: {
2443 Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2444 Node* pair2 = new BinaryNode(n->in(3), n->in(4));
2445 n->set_req(1, pair1);
2446 n->set_req(2, pair2);
2447 n->del_req(4);
2448 n->del_req(3);
2449 break;
2450 }
2451 case Op_StoreVectorMasked: {
2452 Node* pair = new BinaryNode(n->in(3), n->in(4));
2453 n->set_req(3, pair);
2454 n->del_req(4);
2455 break;
2456 }
2457 case Op_LoopLimit: {
2458 Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2459 n->set_req(1, pair1);
2460 n->set_req(2, n->in(3));
2461 n->del_req(3);
2462 break;
2463 }
2464 case Op_StrEquals:
2465 case Op_StrIndexOfChar: {
2466 Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2467 n->set_req(2, pair1);
2468 n->set_req(3, n->in(4));
2469 n->del_req(4);
2470 break;
2471 }
2472 case Op_StrComp:
2473 case Op_StrIndexOf:
2474 case Op_VectorizedHashCode: {
2475 Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2476 n->set_req(2, pair1);
2477 Node* pair2 = new BinaryNode(n->in(4),n->in(5));
2478 n->set_req(3, pair2);
2479 n->del_req(5);
2480 n->del_req(4);
2481 break;
2482 }
2483 case Op_EncodeISOArray:
2484 case Op_StrCompressedCopy:
2485 case Op_StrInflatedCopy: {
2486 // Restructure into a binary tree for Matching.
2487 Node* pair = new BinaryNode(n->in(3), n->in(4));
2488 n->set_req(3, pair);
2489 n->del_req(4);
2490 break;
2491 }
2492 case Op_FmaD:
2493 case Op_FmaF:
2494 case Op_FmaVD:
2495 case Op_FmaVF: {
2496 // Restructure into a binary tree for Matching.
2497 Node* pair = new BinaryNode(n->in(1), n->in(2));
2498 n->set_req(2, pair);
2499 n->set_req(1, n->in(3));
2500 n->del_req(3);
2501 break;
2502 }
2503 case Op_MulAddS2I: {
2504 Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2505 Node* pair2 = new BinaryNode(n->in(3), n->in(4));
2506 n->set_req(1, pair1);
2507 n->set_req(2, pair2);
2508 n->del_req(4);
2509 n->del_req(3);
2510 break;
2511 }
2512 case Op_ClearArray: {
2513 Node* pair = new BinaryNode(n->in(2), n->in(3));
2514 n->set_req(2, pair);
2515 n->set_req(3, n->in(4));
2516 n->del_req(4);
2517 break;
2518 }
2519 case Op_VectorCmpMasked:
2520 case Op_CopySignD:
2521 case Op_SignumVF:
2522 case Op_SignumVD:
2523 case Op_SignumF:
2524 case Op_SignumD: {
2525 Node* pair = new BinaryNode(n->in(2), n->in(3));
2526 n->set_req(2, pair);
2527 n->del_req(3);
2528 break;
2529 }
2530 case Op_VectorBlend:
2531 case Op_VectorInsert: {
2532 Node* pair = new BinaryNode(n->in(1), n->in(2));
2533 n->set_req(1, pair);
2534 n->set_req(2, n->in(3));
2535 n->del_req(3);
2536 break;
2537 }
2538 case Op_LoadVectorGather:
2539 if (is_subword_type(n->bottom_type()->is_vect()->element_basic_type())) {
2540 Node* pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2541 n->set_req(MemNode::ValueIn, pair);
2542 n->del_req(MemNode::ValueIn+1);
2543 }
2544 break;
2545 case Op_LoadVectorGatherMasked:
2546 if (is_subword_type(n->bottom_type()->is_vect()->element_basic_type())) {
2547 Node* pair2 = new BinaryNode(n->in(MemNode::ValueIn + 1), n->in(MemNode::ValueIn + 2));
2548 Node* pair1 = new BinaryNode(n->in(MemNode::ValueIn), pair2);
2549 n->set_req(MemNode::ValueIn, pair1);
2550 n->del_req(MemNode::ValueIn+2);
2551 n->del_req(MemNode::ValueIn+1);
2552 break;
2553 } // fall-through
2554 case Op_StoreVectorScatter: {
2555 Node* pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2556 n->set_req(MemNode::ValueIn, pair);
2557 n->del_req(MemNode::ValueIn+1);
2558 break;
2559 }
2560 case Op_StoreVectorScatterMasked: {
2561 Node* pair = new BinaryNode(n->in(MemNode::ValueIn+1), n->in(MemNode::ValueIn+2));
2562 n->set_req(MemNode::ValueIn+1, pair);
2563 n->del_req(MemNode::ValueIn+2);
2564 pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2565 n->set_req(MemNode::ValueIn, pair);
2566 n->del_req(MemNode::ValueIn+1);
2567 break;
2568 }
2569 case Op_VectorMaskCmp: {
2570 n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2571 n->set_req(2, n->in(3));
2572 n->del_req(3);
2573 break;
2574 }
2575 case Op_PartialSubtypeCheck: {
2576 if (UseSecondarySupersTable && n->in(2)->is_Con()) {
2577 // PartialSubtypeCheck uses both constant and register operands for superclass input.
2578 n->set_req(2, new BinaryNode(n->in(2), n->in(2)));
2579 break;
2580 }
2581 break;
2582 }
2583 default:
2584 break;
2585 }
2586 }
2587
2588 #ifndef PRODUCT
2589 void Matcher::record_new2old(Node* newn, Node* old) {
2590 _new2old_map.map(newn->_idx, old);
2591 if (!_reused.test_set(old->_igv_idx)) {
2592 // Reuse the Ideal-level IGV identifier so that the node can be tracked
2593 // across matching. If there are multiple machine nodes expanded from the
2594 // same Ideal node, only one will reuse its IGV identifier.
2595 newn->_igv_idx = old->_igv_idx;
2596 }
2597 }
2598
2599 // machine-independent root to machine-dependent root
2600 void Matcher::dump_old2new_map() {
2601 _old2new_map.dump();
2602 }
2603 #endif // !PRODUCT
2604
2605 //---------------------------collect_null_checks-------------------------------
2606 // Find null checks in the ideal graph; write a machine-specific node for
2607 // it. Used by later implicit-null-check handling. Actually collects
2608 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2609 // value being tested.
2610 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2611 Node *iff = proj->in(0);
2612 if( iff->Opcode() == Op_If ) {
2613 // During matching If's have Bool & Cmp side-by-side
2614 BoolNode *b = iff->in(1)->as_Bool();
2615 Node *cmp = iff->in(2);
2616 int opc = cmp->Opcode();
2617 if (opc != Op_CmpP && opc != Op_CmpN) return;
2618
2619 const Type* ct = cmp->in(2)->bottom_type();
2620 if (ct == TypePtr::NULL_PTR ||
2621 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2622
2623 bool push_it = false;
2624 if( proj->Opcode() == Op_IfTrue ) {
2625 #ifndef PRODUCT
2626 extern uint all_null_checks_found;
2627 all_null_checks_found++;
2628 #endif
2629 if( b->_test._test == BoolTest::ne ) {
2630 push_it = true;
2631 }
2632 } else {
2633 assert( proj->Opcode() == Op_IfFalse, "" );
2634 if( b->_test._test == BoolTest::eq ) {
2635 push_it = true;
2636 }
2637 }
2638 if( push_it ) {
2639 _null_check_tests.push(proj);
2640 Node* val = cmp->in(1);
2641 #ifdef _LP64
2642 if (val->bottom_type()->isa_narrowoop() &&
2643 !Matcher::narrow_oop_use_complex_address()) {
2644 //
2645 // Look for DecodeN node which should be pinned to orig_proj.
2646 // On platforms (Sparc) which can not handle 2 adds
2647 // in addressing mode we have to keep a DecodeN node and
2648 // use it to do implicit null check in address.
2649 //
2650 // DecodeN node was pinned to non-null path (orig_proj) during
2651 // CastPP transformation in final_graph_reshaping_impl().
2652 //
2653 uint cnt = orig_proj->outcnt();
2654 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2655 Node* d = orig_proj->raw_out(i);
2656 if (d->is_DecodeN() && d->in(1) == val) {
2657 val = d;
2658 val->set_req(0, nullptr); // Unpin now.
2659 // Mark this as special case to distinguish from
2660 // a regular case: CmpP(DecodeN, null).
2661 val = (Node*)(((intptr_t)val) | 1);
2662 break;
2663 }
2664 }
2665 }
2666 #endif
2667 _null_check_tests.push(val);
2668 }
2669 }
2670 }
2671 }
2672
2673 //---------------------------validate_null_checks------------------------------
2674 // Its possible that the value being null checked is not the root of a match
2675 // tree. If so, I cannot use the value in an implicit null check.
2676 void Matcher::validate_null_checks( ) {
2677 uint cnt = _null_check_tests.size();
2678 for( uint i=0; i < cnt; i+=2 ) {
2679 Node *test = _null_check_tests[i];
2680 Node *val = _null_check_tests[i+1];
2681 bool is_decoden = ((intptr_t)val) & 1;
2682 val = (Node*)(((intptr_t)val) & ~1);
2683 if (has_new_node(val)) {
2684 Node* new_val = new_node(val);
2685 if (is_decoden) {
2686 assert(val->is_DecodeNarrowPtr() && val->in(0) == nullptr, "sanity");
2687 // Note: new_val may have a control edge if
2688 // the original ideal node DecodeN was matched before
2689 // it was unpinned in Matcher::collect_null_checks().
2690 // Unpin the mach node and mark it.
2691 new_val->set_req(0, nullptr);
2692 new_val = (Node*)(((intptr_t)new_val) | 1);
2693 }
2694 // Is a match-tree root, so replace with the matched value
2695 _null_check_tests.map(i+1, new_val);
2696 } else {
2697 // Yank from candidate list
2698 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2699 _null_check_tests.map(i,_null_check_tests[--cnt]);
2700 _null_check_tests.pop();
2701 _null_check_tests.pop();
2702 i-=2;
2703 }
2704 }
2705 }
2706
2707 bool Matcher::gen_narrow_oop_implicit_null_checks() {
2708 // Advice matcher to perform null checks on the narrow oop side.
2709 // Implicit checks are not possible on the uncompressed oop side anyway
2710 // (at least not for read accesses).
2711 // Performs significantly better (especially on Power 6).
2712 if (!os::zero_page_read_protected()) {
2713 return true;
2714 }
2715 return CompressedOops::use_implicit_null_checks() &&
2716 (narrow_oop_use_complex_address() ||
2717 CompressedOops::base() != nullptr);
2718 }
2719
2720 // Compute RegMask for an ideal register.
2721 const RegMask* Matcher::regmask_for_ideal_register(uint ideal_reg, Node* ret) {
2722 const Type* t = Type::mreg2type[ideal_reg];
2723 if (t == nullptr) {
2724 assert(ideal_reg >= Op_VecA && ideal_reg <= Op_VecZ, "not a vector: %d", ideal_reg);
2725 return nullptr; // not supported
2726 }
2727 Node* fp = ret->in(TypeFunc::FramePtr);
2728 Node* mem = ret->in(TypeFunc::Memory);
2729 const TypePtr* atp = TypePtr::BOTTOM;
2730 MemNode::MemOrd mo = MemNode::unordered;
2731
2732 Node* spill;
2733 switch (ideal_reg) {
2734 case Op_RegN: spill = new LoadNNode(nullptr, mem, fp, atp, t->is_narrowoop(), mo); break;
2735 case Op_RegI: spill = new LoadINode(nullptr, mem, fp, atp, t->is_int(), mo); break;
2736 case Op_RegP: spill = new LoadPNode(nullptr, mem, fp, atp, t->is_ptr(), mo); break;
2737 case Op_RegF: spill = new LoadFNode(nullptr, mem, fp, atp, t, mo); break;
2738 case Op_RegD: spill = new LoadDNode(nullptr, mem, fp, atp, t, mo); break;
2739 case Op_RegL: spill = new LoadLNode(nullptr, mem, fp, atp, t->is_long(), mo); break;
2740
2741 case Op_VecA: // fall-through
2742 case Op_VecS: // fall-through
2743 case Op_VecD: // fall-through
2744 case Op_VecX: // fall-through
2745 case Op_VecY: // fall-through
2746 case Op_VecZ: spill = new LoadVectorNode(nullptr, mem, fp, atp, t->is_vect()); break;
2747 case Op_RegVectMask: return Matcher::predicate_reg_mask();
2748
2749 default: ShouldNotReachHere();
2750 }
2751 MachNode* mspill = match_tree(spill);
2752 assert(mspill != nullptr, "matching failed: %d", ideal_reg);
2753 // Handle generic vector operand case
2754 if (Matcher::supports_generic_vector_operands && t->isa_vect()) {
2755 specialize_mach_node(mspill);
2756 }
2757 return &mspill->out_RegMask();
2758 }
2759
2760 // Process Mach IR right after selection phase is over.
2761 void Matcher::do_postselect_cleanup() {
2762 if (supports_generic_vector_operands) {
2763 specialize_generic_vector_operands();
2764 if (C->failing()) return;
2765 }
2766 }
2767
2768 //----------------------------------------------------------------------
2769 // Generic machine operands elision.
2770 //----------------------------------------------------------------------
2771
2772 // Compute concrete vector operand for a generic TEMP vector mach node based on its user info.
2773 void Matcher::specialize_temp_node(MachTempNode* tmp, MachNode* use, uint idx) {
2774 assert(use->in(idx) == tmp, "not a user");
2775 assert(!Matcher::is_generic_vector(use->_opnds[0]), "use not processed yet");
2776
2777 if ((uint)idx == use->two_adr()) { // DEF_TEMP case
2778 tmp->_opnds[0] = use->_opnds[0]->clone();
2779 } else {
2780 uint ideal_vreg = vector_ideal_reg(C->max_vector_size());
2781 tmp->_opnds[0] = Matcher::pd_specialize_generic_vector_operand(tmp->_opnds[0], ideal_vreg, true /*is_temp*/);
2782 }
2783 }
2784
2785 // Compute concrete vector operand for a generic DEF/USE vector operand (of mach node m at index idx).
2786 MachOper* Matcher::specialize_vector_operand(MachNode* m, uint opnd_idx) {
2787 assert(Matcher::is_generic_vector(m->_opnds[opnd_idx]), "repeated updates");
2788 Node* def = nullptr;
2789 if (opnd_idx == 0) { // DEF
2790 def = m; // use mach node itself to compute vector operand type
2791 } else {
2792 int base_idx = m->operand_index(opnd_idx);
2793 def = m->in(base_idx);
2794 if (def->is_Mach()) {
2795 if (def->is_MachTemp() && Matcher::is_generic_vector(def->as_Mach()->_opnds[0])) {
2796 specialize_temp_node(def->as_MachTemp(), m, base_idx); // MachTemp node use site
2797 } else if (is_reg2reg_move(def->as_Mach())) {
2798 def = def->in(1); // skip over generic reg-to-reg moves
2799 }
2800 }
2801 }
2802 assert(def->bottom_type()->isa_vect(), "not a vector");
2803 uint ideal_vreg = def->bottom_type()->ideal_reg();
2804 return Matcher::pd_specialize_generic_vector_operand(m->_opnds[opnd_idx], ideal_vreg, false /*is_temp*/);
2805 }
2806
2807 void Matcher::specialize_mach_node(MachNode* m) {
2808 assert(!m->is_MachTemp(), "processed along with its user");
2809 // For generic use operands pull specific register class operands from
2810 // its def instruction's output operand (def operand).
2811 for (uint i = 0; i < m->num_opnds(); i++) {
2812 if (Matcher::is_generic_vector(m->_opnds[i])) {
2813 m->_opnds[i] = specialize_vector_operand(m, i);
2814 }
2815 }
2816 }
2817
2818 // Replace generic vector operands with concrete vector operands and eliminate generic reg-to-reg moves from the graph.
2819 void Matcher::specialize_generic_vector_operands() {
2820 assert(supports_generic_vector_operands, "sanity");
2821 ResourceMark rm;
2822
2823 // Replace generic vector operands (vec/legVec) with concrete ones (vec[SDXYZ]/legVec[SDXYZ])
2824 // and remove reg-to-reg vector moves (MoveVec2Leg and MoveLeg2Vec).
2825 Unique_Node_List live_nodes;
2826 C->identify_useful_nodes(live_nodes);
2827
2828 while (live_nodes.size() > 0) {
2829 MachNode* m = live_nodes.pop()->isa_Mach();
2830 if (m != nullptr) {
2831 if (Matcher::is_reg2reg_move(m)) {
2832 // Register allocator properly handles vec <=> leg moves using register masks.
2833 int opnd_idx = m->operand_index(1);
2834 Node* def = m->in(opnd_idx);
2835 m->subsume_by(def, C);
2836 } else if (m->is_MachTemp()) {
2837 // process MachTemp nodes at use site (see Matcher::specialize_vector_operand)
2838 } else {
2839 specialize_mach_node(m);
2840 }
2841 }
2842 }
2843 }
2844
2845 uint Matcher::vector_length(const Node* n) {
2846 const TypeVect* vt = n->bottom_type()->is_vect();
2847 return vt->length();
2848 }
2849
2850 uint Matcher::vector_length(const MachNode* use, const MachOper* opnd) {
2851 int def_idx = use->operand_index(opnd);
2852 Node* def = use->in(def_idx);
2853 return def->bottom_type()->is_vect()->length();
2854 }
2855
2856 uint Matcher::vector_length_in_bytes(const Node* n) {
2857 const TypeVect* vt = n->bottom_type()->is_vect();
2858 return vt->length_in_bytes();
2859 }
2860
2861 uint Matcher::vector_length_in_bytes(const MachNode* use, const MachOper* opnd) {
2862 uint def_idx = use->operand_index(opnd);
2863 Node* def = use->in(def_idx);
2864 return def->bottom_type()->is_vect()->length_in_bytes();
2865 }
2866
2867 BasicType Matcher::vector_element_basic_type(const Node* n) {
2868 const TypeVect* vt = n->bottom_type()->is_vect();
2869 return vt->element_basic_type();
2870 }
2871
2872 BasicType Matcher::vector_element_basic_type(const MachNode* use, const MachOper* opnd) {
2873 int def_idx = use->operand_index(opnd);
2874 Node* def = use->in(def_idx);
2875 return def->bottom_type()->is_vect()->element_basic_type();
2876 }
2877
2878 bool Matcher::is_non_long_integral_vector(const Node* n) {
2879 BasicType bt = vector_element_basic_type(n);
2880 assert(bt != T_CHAR, "char is not allowed in vector");
2881 return is_subword_type(bt) || bt == T_INT;
2882 }
2883
2884 #ifdef ASSERT
2885 bool Matcher::verify_after_postselect_cleanup() {
2886 assert(!C->failing(), "sanity");
2887 if (supports_generic_vector_operands) {
2888 Unique_Node_List useful;
2889 C->identify_useful_nodes(useful);
2890 for (uint i = 0; i < useful.size(); i++) {
2891 MachNode* m = useful.at(i)->isa_Mach();
2892 if (m != nullptr) {
2893 assert(!Matcher::is_reg2reg_move(m), "no MoveVec nodes allowed");
2894 for (uint j = 0; j < m->num_opnds(); j++) {
2895 assert(!Matcher::is_generic_vector(m->_opnds[j]), "no generic vector operands allowed");
2896 }
2897 }
2898 }
2899 }
2900 return true;
2901 }
2902 #endif // ASSERT
2903
2904 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2905 // atomic instruction acting as a store_load barrier without any
2906 // intervening volatile load, and thus we don't need a barrier here.
2907 // We retain the Node to act as a compiler ordering barrier.
2908 bool Matcher::post_store_load_barrier(const Node* vmb) {
2909 Compile* C = Compile::current();
2910 assert(vmb->is_MemBar(), "");
2911 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2912 const MemBarNode* membar = vmb->as_MemBar();
2913
2914 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2915 Node* ctrl = nullptr;
2916 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2917 Node* p = membar->fast_out(i);
2918 assert(p->is_Proj(), "only projections here");
2919 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2920 !C->node_arena()->contains(p)) { // Unmatched old-space only
2921 ctrl = p;
2922 break;
2923 }
2924 }
2925 assert((ctrl != nullptr), "missing control projection");
2926
2927 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2928 Node *x = ctrl->fast_out(j);
2929 int xop = x->Opcode();
2930
2931 // We don't need current barrier if we see another or a lock
2932 // before seeing volatile load.
2933 //
2934 // Op_Fastunlock previously appeared in the Op_* list below.
2935 // With the advent of 1-0 lock operations we're no longer guaranteed
2936 // that a monitor exit operation contains a serializing instruction.
2937
2938 if (xop == Op_MemBarVolatile ||
2939 xop == Op_CompareAndExchangeB ||
2940 xop == Op_CompareAndExchangeS ||
2941 xop == Op_CompareAndExchangeI ||
2942 xop == Op_CompareAndExchangeL ||
2943 xop == Op_CompareAndExchangeP ||
2944 xop == Op_CompareAndExchangeN ||
2945 xop == Op_WeakCompareAndSwapB ||
2946 xop == Op_WeakCompareAndSwapS ||
2947 xop == Op_WeakCompareAndSwapL ||
2948 xop == Op_WeakCompareAndSwapP ||
2949 xop == Op_WeakCompareAndSwapN ||
2950 xop == Op_WeakCompareAndSwapI ||
2951 xop == Op_CompareAndSwapB ||
2952 xop == Op_CompareAndSwapS ||
2953 xop == Op_CompareAndSwapL ||
2954 xop == Op_CompareAndSwapP ||
2955 xop == Op_CompareAndSwapN ||
2956 xop == Op_CompareAndSwapI ||
2957 BarrierSet::barrier_set()->barrier_set_c2()->matcher_is_store_load_barrier(x, xop)) {
2958 return true;
2959 }
2960
2961 // Op_FastLock previously appeared in the Op_* list above.
2962 if (xop == Op_FastLock) {
2963 return true;
2964 }
2965
2966 if (x->is_MemBar()) {
2967 // We must retain this membar if there is an upcoming volatile
2968 // load, which will be followed by acquire membar.
2969 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2970 return false;
2971 } else {
2972 // For other kinds of barriers, check by pretending we
2973 // are them, and seeing if we can be removed.
2974 return post_store_load_barrier(x->as_MemBar());
2975 }
2976 }
2977
2978 // probably not necessary to check for these
2979 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2980 return false;
2981 }
2982 }
2983 return false;
2984 }
2985
2986 // Check whether node n is a branch to an uncommon trap that we could
2987 // optimize as test with very high branch costs in case of going to
2988 // the uncommon trap. The code must be able to be recompiled to use
2989 // a cheaper test.
2990 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2991 // Don't do it for natives, adapters, or runtime stubs
2992 Compile *C = Compile::current();
2993 if (!C->is_method_compilation()) return false;
2994
2995 assert(n->is_If(), "You should only call this on if nodes.");
2996 IfNode *ifn = n->as_If();
2997
2998 Node *ifFalse = nullptr;
2999 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
3000 if (ifn->fast_out(i)->is_IfFalse()) {
3001 ifFalse = ifn->fast_out(i);
3002 break;
3003 }
3004 }
3005 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
3006
3007 Node *reg = ifFalse;
3008 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
3009 // Alternatively use visited set? Seems too expensive.
3010 while (reg != nullptr && cnt > 0) {
3011 CallNode *call = nullptr;
3012 RegionNode *nxt_reg = nullptr;
3013 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
3014 Node *o = reg->fast_out(i);
3015 if (o->is_Call()) {
3016 call = o->as_Call();
3017 }
3018 if (o->is_Region()) {
3019 nxt_reg = o->as_Region();
3020 }
3021 }
3022
3023 if (call &&
3024 call->entry_point() == OptoRuntime::uncommon_trap_blob()->entry_point()) {
3025 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
3026 if (trtype->isa_int() && trtype->is_int()->is_con()) {
3027 jint tr_con = trtype->is_int()->get_con();
3028 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
3029 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
3030 assert((int)reason < (int)BitsPerInt, "recode bit map");
3031
3032 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
3033 && action != Deoptimization::Action_none) {
3034 // This uncommon trap is sure to recompile, eventually.
3035 // When that happens, C->too_many_traps will prevent
3036 // this transformation from happening again.
3037 return true;
3038 }
3039 }
3040 }
3041
3042 reg = nxt_reg;
3043 cnt--;
3044 }
3045
3046 return false;
3047 }
3048
3049 //=============================================================================
3050 //---------------------------State---------------------------------------------
3051 State::State(void) : _rule() {
3052 #ifdef ASSERT
3053 _id = 0;
3054 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
3055 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
3056 #endif
3057 }
3058
3059 #ifdef ASSERT
3060 State::~State() {
3061 _id = 99;
3062 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
3063 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
3064 memset(_cost, -3, sizeof(_cost));
3065 memset(_rule, -3, sizeof(_rule));
3066 }
3067 #endif
3068
3069 #ifndef PRODUCT
3070 //---------------------------dump----------------------------------------------
3071 void State::dump() {
3072 tty->print("\n");
3073 dump(0);
3074 }
3075
3076 void State::dump(int depth) {
3077 for (int j = 0; j < depth; j++) {
3078 tty->print(" ");
3079 }
3080 tty->print("--N: ");
3081 _leaf->dump();
3082 uint i;
3083 for (i = 0; i < _LAST_MACH_OPER; i++) {
3084 // Check for valid entry
3085 if (valid(i)) {
3086 for (int j = 0; j < depth; j++) {
3087 tty->print(" ");
3088 }
3089 assert(cost(i) != max_juint, "cost must be a valid value");
3090 assert(rule(i) < _last_Mach_Node, "rule[i] must be valid rule");
3091 tty->print_cr("%s %d %s",
3092 ruleName[i], cost(i), ruleName[rule(i)] );
3093 }
3094 }
3095 tty->cr();
3096
3097 for (i = 0; i < 2; i++) {
3098 if (_kids[i]) {
3099 _kids[i]->dump(depth + 1);
3100 }
3101 }
3102 }
3103 #endif