1 /*
2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #include "precompiled.hpp"
26 #include "gc/shared/barrierSet.hpp"
27 #include "gc/shared/c2/barrierSetC2.hpp"
28 #include "memory/allocation.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "oops/compressedOops.hpp"
31 #include "opto/ad.hpp"
32 #include "opto/addnode.hpp"
33 #include "opto/callnode.hpp"
34 #include "opto/idealGraphPrinter.hpp"
35 #include "opto/matcher.hpp"
36 #include "opto/memnode.hpp"
37 #include "opto/movenode.hpp"
38 #include "opto/opcodes.hpp"
39 #include "opto/regmask.hpp"
40 #include "opto/rootnode.hpp"
41 #include "opto/runtime.hpp"
42 #include "opto/type.hpp"
43 #include "opto/vectornode.hpp"
44 #include "runtime/os.inline.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "utilities/align.hpp"
47
48 OptoReg::Name OptoReg::c_frame_pointer;
49
50 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
51 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
52 RegMask Matcher::caller_save_regmask;
53 RegMask Matcher::caller_save_regmask_exclude_soe;
54 RegMask Matcher::mh_caller_save_regmask;
55 RegMask Matcher::mh_caller_save_regmask_exclude_soe;
56 RegMask Matcher::STACK_ONLY_mask;
57 RegMask Matcher::c_frame_ptr_mask;
58 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
59 const uint Matcher::_end_rematerialize = _END_REMATERIALIZE;
60
61 //---------------------------Matcher-------------------------------------------
62 Matcher::Matcher()
63 : PhaseTransform( Phase::Ins_Select ),
64 _states_arena(Chunk::medium_size, mtCompiler),
65 _new_nodes(C->comp_arena()),
66 _visited(&_states_arena),
67 _shared(&_states_arena),
68 _dontcare(&_states_arena),
69 _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
70 _swallowed(swallowed),
71 _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
72 _end_inst_chain_rule(_END_INST_CHAIN_RULE),
73 _must_clone(must_clone),
74 _shared_nodes(C->comp_arena()),
75 #ifndef PRODUCT
76 _old2new_map(C->comp_arena()),
77 _new2old_map(C->comp_arena()),
78 _reused(C->comp_arena()),
79 #endif // !PRODUCT
80 _allocation_started(false),
81 _ruleName(ruleName),
82 _register_save_policy(register_save_policy),
83 _c_reg_save_policy(c_reg_save_policy),
84 _register_save_type(register_save_type) {
85 C->set_matcher(this);
86
87 idealreg2spillmask [Op_RegI] = nullptr;
88 idealreg2spillmask [Op_RegN] = nullptr;
89 idealreg2spillmask [Op_RegL] = nullptr;
90 idealreg2spillmask [Op_RegF] = nullptr;
91 idealreg2spillmask [Op_RegD] = nullptr;
92 idealreg2spillmask [Op_RegP] = nullptr;
93 idealreg2spillmask [Op_VecA] = nullptr;
94 idealreg2spillmask [Op_VecS] = nullptr;
95 idealreg2spillmask [Op_VecD] = nullptr;
96 idealreg2spillmask [Op_VecX] = nullptr;
97 idealreg2spillmask [Op_VecY] = nullptr;
98 idealreg2spillmask [Op_VecZ] = nullptr;
99 idealreg2spillmask [Op_RegFlags] = nullptr;
100 idealreg2spillmask [Op_RegVectMask] = nullptr;
101
102 idealreg2debugmask [Op_RegI] = nullptr;
103 idealreg2debugmask [Op_RegN] = nullptr;
104 idealreg2debugmask [Op_RegL] = nullptr;
105 idealreg2debugmask [Op_RegF] = nullptr;
106 idealreg2debugmask [Op_RegD] = nullptr;
107 idealreg2debugmask [Op_RegP] = nullptr;
108 idealreg2debugmask [Op_VecA] = nullptr;
109 idealreg2debugmask [Op_VecS] = nullptr;
110 idealreg2debugmask [Op_VecD] = nullptr;
111 idealreg2debugmask [Op_VecX] = nullptr;
112 idealreg2debugmask [Op_VecY] = nullptr;
113 idealreg2debugmask [Op_VecZ] = nullptr;
114 idealreg2debugmask [Op_RegFlags] = nullptr;
115 idealreg2debugmask [Op_RegVectMask] = nullptr;
116
117 idealreg2mhdebugmask[Op_RegI] = nullptr;
118 idealreg2mhdebugmask[Op_RegN] = nullptr;
119 idealreg2mhdebugmask[Op_RegL] = nullptr;
120 idealreg2mhdebugmask[Op_RegF] = nullptr;
121 idealreg2mhdebugmask[Op_RegD] = nullptr;
122 idealreg2mhdebugmask[Op_RegP] = nullptr;
123 idealreg2mhdebugmask[Op_VecA] = nullptr;
124 idealreg2mhdebugmask[Op_VecS] = nullptr;
125 idealreg2mhdebugmask[Op_VecD] = nullptr;
126 idealreg2mhdebugmask[Op_VecX] = nullptr;
127 idealreg2mhdebugmask[Op_VecY] = nullptr;
128 idealreg2mhdebugmask[Op_VecZ] = nullptr;
129 idealreg2mhdebugmask[Op_RegFlags] = nullptr;
130 idealreg2mhdebugmask[Op_RegVectMask] = nullptr;
131
132 debug_only(_mem_node = nullptr;) // Ideal memory node consumed by mach node
133 }
134
135 //------------------------------warp_incoming_stk_arg------------------------
136 // This warps a VMReg into an OptoReg::Name
137 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
138 OptoReg::Name warped;
139 if( reg->is_stack() ) { // Stack slot argument?
140 warped = OptoReg::add(_old_SP, reg->reg2stack() );
141 warped = OptoReg::add(warped, C->out_preserve_stack_slots());
142 if( warped >= _in_arg_limit )
143 _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
144 if (!RegMask::can_represent_arg(warped)) {
145 // the compiler cannot represent this method's calling sequence
146 // Bailout. We do not have space to represent all arguments.
147 C->record_method_not_compilable("unsupported incoming calling sequence");
148 return OptoReg::Bad;
149 }
150 return warped;
151 }
152 return OptoReg::as_OptoReg(reg);
153 }
154
155 //---------------------------compute_old_SP------------------------------------
156 OptoReg::Name Compile::compute_old_SP() {
157 int fixed = fixed_slots();
158 int preserve = in_preserve_stack_slots();
159 return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots()));
160 }
161
162
163
164 #ifdef ASSERT
165 void Matcher::verify_new_nodes_only(Node* xroot) {
166 // Make sure that the new graph only references new nodes
167 ResourceMark rm;
168 Unique_Node_List worklist;
169 VectorSet visited;
170 worklist.push(xroot);
171 while (worklist.size() > 0) {
172 Node* n = worklist.pop();
173 visited.set(n->_idx);
174 assert(C->node_arena()->contains(n), "dead node");
175 for (uint j = 0; j < n->req(); j++) {
176 Node* in = n->in(j);
177 if (in != nullptr) {
178 assert(C->node_arena()->contains(in), "dead node");
179 if (!visited.test(in->_idx)) {
180 worklist.push(in);
181 }
182 }
183 }
184 }
185 }
186 #endif
187
188 // Array of RegMask, one per returned values (inline type instances can
189 // be returned as multiple return values, one per field)
190 RegMask* Matcher::return_values_mask(const TypeFunc* tf) {
191 const TypeTuple* range = tf->range_cc();
192 uint cnt = range->cnt() - TypeFunc::Parms;
193 if (cnt == 0) {
194 return nullptr;
195 }
196 RegMask* mask = NEW_RESOURCE_ARRAY(RegMask, cnt);
197 BasicType* sig_bt = NEW_RESOURCE_ARRAY(BasicType, cnt);
198 VMRegPair* vm_parm_regs = NEW_RESOURCE_ARRAY(VMRegPair, cnt);
199 for (uint i = 0; i < cnt; i++) {
200 sig_bt[i] = range->field_at(i+TypeFunc::Parms)->basic_type();
201 }
202
203 int regs = SharedRuntime::java_return_convention(sig_bt, vm_parm_regs, cnt);
204 if (regs <= 0) {
205 // We ran out of registers to store the IsInit information for a nullable inline type return.
206 // Since it is only set in the 'call_epilog', we can simply put it on the stack.
207 assert(tf->returns_inline_type_as_fields(), "should have been tested during graph construction");
208 // TODO 8284443 Can we teach the register allocator to reserve a stack slot instead?
209 // mask[--cnt] = STACK_ONLY_mask does not work (test with -XX:+StressGCM)
210 int slot = C->fixed_slots() - 2;
211 if (C->needs_stack_repair()) {
212 slot -= 2; // Account for stack increment value
213 }
214 mask[--cnt].Clear();
215 mask[cnt].Insert(OptoReg::stack2reg(slot));
216 }
217 for (uint i = 0; i < cnt; i++) {
218 mask[i].Clear();
219
220 OptoReg::Name reg1 = OptoReg::as_OptoReg(vm_parm_regs[i].first());
221 if (OptoReg::is_valid(reg1)) {
222 mask[i].Insert(reg1);
223 }
224 OptoReg::Name reg2 = OptoReg::as_OptoReg(vm_parm_regs[i].second());
225 if (OptoReg::is_valid(reg2)) {
226 mask[i].Insert(reg2);
227 }
228 }
229
230 return mask;
231 }
232
233 //---------------------------match---------------------------------------------
234 void Matcher::match( ) {
235 if( MaxLabelRootDepth < 100 ) { // Too small?
236 assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
237 MaxLabelRootDepth = 100;
238 }
239 // One-time initialization of some register masks.
240 init_spill_mask( C->root()->in(1) );
241 _return_addr_mask = return_addr();
242 #ifdef _LP64
243 // Pointers take 2 slots in 64-bit land
244 _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
245 #endif
246
247 // Map Java-signature return types into return register-value
248 // machine registers.
249 _return_values_mask = return_values_mask(C->tf());
250
251 // ---------------
252 // Frame Layout
253
254 // Need the method signature to determine the incoming argument types,
255 // because the types determine which registers the incoming arguments are
256 // in, and this affects the matched code.
257 const TypeTuple *domain = C->tf()->domain_cc();
258 uint argcnt = domain->cnt() - TypeFunc::Parms;
259 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
260 VMRegPair *vm_parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
261 _parm_regs = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
262 _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
263 uint i;
264 for( i = 0; i<argcnt; i++ ) {
265 sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
266 }
267
268 // Pass array of ideal registers and length to USER code (from the AD file)
269 // that will convert this to an array of register numbers.
270 const StartNode *start = C->start();
271 start->calling_convention( sig_bt, vm_parm_regs, argcnt );
272 #ifdef ASSERT
273 // Sanity check users' calling convention. Real handy while trying to
274 // get the initial port correct.
275 { for (uint i = 0; i<argcnt; i++) {
276 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
277 assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
278 _parm_regs[i].set_bad();
279 continue;
280 }
281 VMReg parm_reg = vm_parm_regs[i].first();
282 assert(parm_reg->is_valid(), "invalid arg?");
283 if (parm_reg->is_reg()) {
284 OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
285 assert(can_be_java_arg(opto_parm_reg) ||
286 C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
287 opto_parm_reg == inline_cache_reg(),
288 "parameters in register must be preserved by runtime stubs");
289 }
290 for (uint j = 0; j < i; j++) {
291 assert(parm_reg != vm_parm_regs[j].first(),
292 "calling conv. must produce distinct regs");
293 }
294 }
295 }
296 #endif
297
298 // Do some initial frame layout.
299
300 // Compute the old incoming SP (may be called FP) as
301 // OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
302 _old_SP = C->compute_old_SP();
303 assert( is_even(_old_SP), "must be even" );
304
305 // Compute highest incoming stack argument as
306 // _old_SP + out_preserve_stack_slots + incoming argument size.
307 _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
308 assert( is_even(_in_arg_limit), "out_preserve must be even" );
309 for( i = 0; i < argcnt; i++ ) {
310 // Permit args to have no register
311 _calling_convention_mask[i].Clear();
312 if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
313 _parm_regs[i].set_bad();
314 continue;
315 }
316 // calling_convention returns stack arguments as a count of
317 // slots beyond OptoReg::stack0()/VMRegImpl::stack0. We need to convert this to
318 // the allocators point of view, taking into account all the
319 // preserve area, locks & pad2.
320
321 OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
322 if( OptoReg::is_valid(reg1))
323 _calling_convention_mask[i].Insert(reg1);
324
325 OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
326 if( OptoReg::is_valid(reg2))
327 _calling_convention_mask[i].Insert(reg2);
328
329 // Saved biased stack-slot register number
330 _parm_regs[i].set_pair(reg2, reg1);
331 }
332
333 // Finally, make sure the incoming arguments take up an even number of
334 // words, in case the arguments or locals need to contain doubleword stack
335 // slots. The rest of the system assumes that stack slot pairs (in
336 // particular, in the spill area) which look aligned will in fact be
337 // aligned relative to the stack pointer in the target machine. Double
338 // stack slots will always be allocated aligned.
339 _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong));
340
341 // Compute highest outgoing stack argument as
342 // _new_SP + out_preserve_stack_slots + max(outgoing argument size).
343 _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
344 assert( is_even(_out_arg_limit), "out_preserve must be even" );
345
346 if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
347 // the compiler cannot represent this method's calling sequence
348 // Bailout. We do not have space to represent all arguments.
349 C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
350 }
351
352 if (C->failing()) return; // bailed out on incoming arg failure
353
354 // ---------------
355 // Collect roots of matcher trees. Every node for which
356 // _shared[_idx] is cleared is guaranteed to not be shared, and thus
357 // can be a valid interior of some tree.
358 find_shared( C->root() );
359 find_shared( C->top() );
360
361 C->print_method(PHASE_BEFORE_MATCHING, 1);
362
363 // Create new ideal node ConP #null even if it does exist in old space
364 // to avoid false sharing if the corresponding mach node is not used.
365 // The corresponding mach node is only used in rare cases for derived
366 // pointers.
367 Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
368
369 // Swap out to old-space; emptying new-space
370 Arena* old = C->swap_old_and_new();
371
372 // Save debug and profile information for nodes in old space:
373 _old_node_note_array = C->node_note_array();
374 if (_old_node_note_array != nullptr) {
375 C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
376 (C->comp_arena(), _old_node_note_array->length(),
377 0, nullptr));
378 }
379
380 // Pre-size the new_node table to avoid the need for range checks.
381 grow_new_node_array(C->unique());
382
383 // Reset node counter so MachNodes start with _idx at 0
384 int live_nodes = C->live_nodes();
385 C->set_unique(0);
386 C->reset_dead_node_list();
387
388 // Recursively match trees from old space into new space.
389 // Correct leaves of new-space Nodes; they point to old-space.
390 _visited.clear();
391 C->set_cached_top_node(xform( C->top(), live_nodes ));
392 if (!C->failing()) {
393 Node* xroot = xform( C->root(), 1 );
394 if (xroot == nullptr) {
395 Matcher::soft_match_failure(); // recursive matching process failed
396 assert(false, "instruction match failed");
397 C->record_method_not_compilable("instruction match failed");
398 } else {
399 // During matching shared constants were attached to C->root()
400 // because xroot wasn't available yet, so transfer the uses to
401 // the xroot.
402 for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
403 Node* n = C->root()->fast_out(j);
404 if (C->node_arena()->contains(n)) {
405 assert(n->in(0) == C->root(), "should be control user");
406 n->set_req(0, xroot);
407 --j;
408 --jmax;
409 }
410 }
411
412 // Generate new mach node for ConP #null
413 assert(new_ideal_null != nullptr, "sanity");
414 _mach_null = match_tree(new_ideal_null);
415 // Don't set control, it will confuse GCM since there are no uses.
416 // The control will be set when this node is used first time
417 // in find_base_for_derived().
418 assert(_mach_null != nullptr, "");
419
420 C->set_root(xroot->is_Root() ? xroot->as_Root() : nullptr);
421
422 #ifdef ASSERT
423 verify_new_nodes_only(xroot);
424 #endif
425 }
426 }
427 if (C->top() == nullptr || C->root() == nullptr) {
428 // New graph lost. This is due to a compilation failure we encountered earlier.
429 stringStream ss;
430 if (C->failure_reason() != nullptr) {
431 ss.print("graph lost: %s", C->failure_reason());
432 } else {
433 assert(C->failure_reason() != nullptr, "graph lost: reason unknown");
434 ss.print("graph lost: reason unknown");
435 }
436 C->record_method_not_compilable(ss.as_string());
437 }
438 if (C->failing()) {
439 // delete old;
440 old->destruct_contents();
441 return;
442 }
443 assert( C->top(), "" );
444 assert( C->root(), "" );
445 validate_null_checks();
446
447 // Now smoke old-space
448 NOT_DEBUG( old->destruct_contents() );
449
450 // ------------------------
451 // Set up save-on-entry registers.
452 Fixup_Save_On_Entry( );
453
454 { // Cleanup mach IR after selection phase is over.
455 Compile::TracePhase tp("postselect_cleanup", &timers[_t_postselect_cleanup]);
456 do_postselect_cleanup();
457 if (C->failing()) return;
458 assert(verify_after_postselect_cleanup(), "");
459 }
460 }
461
462 //------------------------------Fixup_Save_On_Entry----------------------------
463 // The stated purpose of this routine is to take care of save-on-entry
464 // registers. However, the overall goal of the Match phase is to convert into
465 // machine-specific instructions which have RegMasks to guide allocation.
466 // So what this procedure really does is put a valid RegMask on each input
467 // to the machine-specific variations of all Return, TailCall and Halt
468 // instructions. It also adds edgs to define the save-on-entry values (and of
469 // course gives them a mask).
470
471 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
472 RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
473 // Do all the pre-defined register masks
474 rms[TypeFunc::Control ] = RegMask::Empty;
475 rms[TypeFunc::I_O ] = RegMask::Empty;
476 rms[TypeFunc::Memory ] = RegMask::Empty;
477 rms[TypeFunc::ReturnAdr] = ret_adr;
478 rms[TypeFunc::FramePtr ] = fp;
479 return rms;
480 }
481
482 int Matcher::scalable_predicate_reg_slots() {
483 assert(Matcher::has_predicated_vectors() && Matcher::supports_scalable_vector(),
484 "scalable predicate vector should be supported");
485 int vector_reg_bit_size = Matcher::scalable_vector_reg_size(T_BYTE) << LogBitsPerByte;
486 // We assume each predicate register is one-eighth of the size of
487 // scalable vector register, one mask bit per vector byte.
488 int predicate_reg_bit_size = vector_reg_bit_size >> 3;
489 // Compute number of slots which is required when scalable predicate
490 // register is spilled. E.g. if scalable vector register is 640 bits,
491 // predicate register is 80 bits, which is 2.5 * slots.
492 // We will round up the slot number to power of 2, which is required
493 // by find_first_set().
494 int slots = predicate_reg_bit_size & (BitsPerInt - 1)
495 ? (predicate_reg_bit_size >> LogBitsPerInt) + 1
496 : predicate_reg_bit_size >> LogBitsPerInt;
497 return round_up_power_of_2(slots);
498 }
499
500 #define NOF_STACK_MASKS (3*13)
501
502 // Create the initial stack mask used by values spilling to the stack.
503 // Disallow any debug info in outgoing argument areas by setting the
504 // initial mask accordingly.
505 void Matcher::init_first_stack_mask() {
506
507 // Allocate storage for spill masks as masks for the appropriate load type.
508 RegMask *rms = (RegMask*)C->comp_arena()->AmallocWords(sizeof(RegMask) * NOF_STACK_MASKS);
509
510 // Initialize empty placeholder masks into the newly allocated arena
511 for (int i = 0; i < NOF_STACK_MASKS; i++) {
512 new (rms + i) RegMask();
513 }
514
515 idealreg2spillmask [Op_RegN] = &rms[0];
516 idealreg2spillmask [Op_RegI] = &rms[1];
517 idealreg2spillmask [Op_RegL] = &rms[2];
518 idealreg2spillmask [Op_RegF] = &rms[3];
519 idealreg2spillmask [Op_RegD] = &rms[4];
520 idealreg2spillmask [Op_RegP] = &rms[5];
521
522 idealreg2debugmask [Op_RegN] = &rms[6];
523 idealreg2debugmask [Op_RegI] = &rms[7];
524 idealreg2debugmask [Op_RegL] = &rms[8];
525 idealreg2debugmask [Op_RegF] = &rms[9];
526 idealreg2debugmask [Op_RegD] = &rms[10];
527 idealreg2debugmask [Op_RegP] = &rms[11];
528
529 idealreg2mhdebugmask[Op_RegN] = &rms[12];
530 idealreg2mhdebugmask[Op_RegI] = &rms[13];
531 idealreg2mhdebugmask[Op_RegL] = &rms[14];
532 idealreg2mhdebugmask[Op_RegF] = &rms[15];
533 idealreg2mhdebugmask[Op_RegD] = &rms[16];
534 idealreg2mhdebugmask[Op_RegP] = &rms[17];
535
536 idealreg2spillmask [Op_VecA] = &rms[18];
537 idealreg2spillmask [Op_VecS] = &rms[19];
538 idealreg2spillmask [Op_VecD] = &rms[20];
539 idealreg2spillmask [Op_VecX] = &rms[21];
540 idealreg2spillmask [Op_VecY] = &rms[22];
541 idealreg2spillmask [Op_VecZ] = &rms[23];
542
543 idealreg2debugmask [Op_VecA] = &rms[24];
544 idealreg2debugmask [Op_VecS] = &rms[25];
545 idealreg2debugmask [Op_VecD] = &rms[26];
546 idealreg2debugmask [Op_VecX] = &rms[27];
547 idealreg2debugmask [Op_VecY] = &rms[28];
548 idealreg2debugmask [Op_VecZ] = &rms[29];
549
550 idealreg2mhdebugmask[Op_VecA] = &rms[30];
551 idealreg2mhdebugmask[Op_VecS] = &rms[31];
552 idealreg2mhdebugmask[Op_VecD] = &rms[32];
553 idealreg2mhdebugmask[Op_VecX] = &rms[33];
554 idealreg2mhdebugmask[Op_VecY] = &rms[34];
555 idealreg2mhdebugmask[Op_VecZ] = &rms[35];
556
557 idealreg2spillmask [Op_RegVectMask] = &rms[36];
558 idealreg2debugmask [Op_RegVectMask] = &rms[37];
559 idealreg2mhdebugmask[Op_RegVectMask] = &rms[38];
560
561 OptoReg::Name i;
562
563 // At first, start with the empty mask
564 C->FIRST_STACK_mask().Clear();
565
566 // Add in the incoming argument area
567 OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
568 for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
569 C->FIRST_STACK_mask().Insert(i);
570 }
571
572 // Add in all bits past the outgoing argument area
573 guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
574 "must be able to represent all call arguments in reg mask");
575 OptoReg::Name init = _out_arg_limit;
576 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
577 C->FIRST_STACK_mask().Insert(i);
578 }
579 // Finally, set the "infinite stack" bit.
580 C->FIRST_STACK_mask().set_AllStack();
581
582 // Make spill masks. Registers for their class, plus FIRST_STACK_mask.
583 RegMask aligned_stack_mask = C->FIRST_STACK_mask();
584 // Keep spill masks aligned.
585 aligned_stack_mask.clear_to_pairs();
586 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
587 RegMask scalable_stack_mask = aligned_stack_mask;
588
589 *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
590 #ifdef _LP64
591 *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
592 idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
593 idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
594 #else
595 idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
596 #endif
597 *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
598 idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
599 *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
600 idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
601 *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
602 idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
603 *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
604 idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
605
606 if (Matcher::has_predicated_vectors()) {
607 *idealreg2spillmask[Op_RegVectMask] = *idealreg2regmask[Op_RegVectMask];
608 idealreg2spillmask[Op_RegVectMask]->OR(aligned_stack_mask);
609 } else {
610 *idealreg2spillmask[Op_RegVectMask] = RegMask::Empty;
611 }
612
613 if (Matcher::vector_size_supported(T_BYTE,4)) {
614 *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
615 idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
616 } else {
617 *idealreg2spillmask[Op_VecS] = RegMask::Empty;
618 }
619
620 if (Matcher::vector_size_supported(T_FLOAT,2)) {
621 // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
622 // RA guarantees such alignment since it is needed for Double and Long values.
623 *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
624 idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
625 } else {
626 *idealreg2spillmask[Op_VecD] = RegMask::Empty;
627 }
628
629 if (Matcher::vector_size_supported(T_FLOAT,4)) {
630 // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
631 //
632 // RA can use input arguments stack slots for spills but until RA
633 // we don't know frame size and offset of input arg stack slots.
634 //
635 // Exclude last input arg stack slots to avoid spilling vectors there
636 // otherwise vector spills could stomp over stack slots in caller frame.
637 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
638 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
639 aligned_stack_mask.Remove(in);
640 in = OptoReg::add(in, -1);
641 }
642 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
643 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
644 *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
645 idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
646 } else {
647 *idealreg2spillmask[Op_VecX] = RegMask::Empty;
648 }
649
650 if (Matcher::vector_size_supported(T_FLOAT,8)) {
651 // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
652 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
653 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
654 aligned_stack_mask.Remove(in);
655 in = OptoReg::add(in, -1);
656 }
657 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
658 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
659 *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
660 idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
661 } else {
662 *idealreg2spillmask[Op_VecY] = RegMask::Empty;
663 }
664
665 if (Matcher::vector_size_supported(T_FLOAT,16)) {
666 // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
667 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
668 for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
669 aligned_stack_mask.Remove(in);
670 in = OptoReg::add(in, -1);
671 }
672 aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
673 assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
674 *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
675 idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
676 } else {
677 *idealreg2spillmask[Op_VecZ] = RegMask::Empty;
678 }
679
680 if (Matcher::supports_scalable_vector()) {
681 int k = 1;
682 OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
683 if (Matcher::has_predicated_vectors()) {
684 // Exclude last input arg stack slots to avoid spilling vector register there,
685 // otherwise RegVectMask spills could stomp over stack slots in caller frame.
686 for (; (in >= init_in) && (k < scalable_predicate_reg_slots()); k++) {
687 scalable_stack_mask.Remove(in);
688 in = OptoReg::add(in, -1);
689 }
690
691 // For RegVectMask
692 scalable_stack_mask.clear_to_sets(scalable_predicate_reg_slots());
693 assert(scalable_stack_mask.is_AllStack(), "should be infinite stack");
694 *idealreg2spillmask[Op_RegVectMask] = *idealreg2regmask[Op_RegVectMask];
695 idealreg2spillmask[Op_RegVectMask]->OR(scalable_stack_mask);
696 }
697
698 // Exclude last input arg stack slots to avoid spilling vector register there,
699 // otherwise vector spills could stomp over stack slots in caller frame.
700 for (; (in >= init_in) && (k < scalable_vector_reg_size(T_FLOAT)); k++) {
701 scalable_stack_mask.Remove(in);
702 in = OptoReg::add(in, -1);
703 }
704
705 // For VecA
706 scalable_stack_mask.clear_to_sets(RegMask::SlotsPerVecA);
707 assert(scalable_stack_mask.is_AllStack(), "should be infinite stack");
708 *idealreg2spillmask[Op_VecA] = *idealreg2regmask[Op_VecA];
709 idealreg2spillmask[Op_VecA]->OR(scalable_stack_mask);
710 } else {
711 *idealreg2spillmask[Op_VecA] = RegMask::Empty;
712 }
713
714 if (UseFPUForSpilling) {
715 // This mask logic assumes that the spill operations are
716 // symmetric and that the registers involved are the same size.
717 // On sparc for instance we may have to use 64 bit moves will
718 // kill 2 registers when used with F0-F31.
719 idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
720 idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
721 #ifdef _LP64
722 idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
723 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
724 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
725 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
726 #else
727 idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
728 #ifdef ARM
729 // ARM has support for moving 64bit values between a pair of
730 // integer registers and a double register
731 idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
732 idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
733 #endif
734 #endif
735 }
736
737 // Make up debug masks. Any spill slot plus callee-save (SOE) registers.
738 // Caller-save (SOC, AS) registers are assumed to be trashable by the various
739 // inline-cache fixup routines.
740 *idealreg2debugmask [Op_RegN] = *idealreg2spillmask[Op_RegN];
741 *idealreg2debugmask [Op_RegI] = *idealreg2spillmask[Op_RegI];
742 *idealreg2debugmask [Op_RegL] = *idealreg2spillmask[Op_RegL];
743 *idealreg2debugmask [Op_RegF] = *idealreg2spillmask[Op_RegF];
744 *idealreg2debugmask [Op_RegD] = *idealreg2spillmask[Op_RegD];
745 *idealreg2debugmask [Op_RegP] = *idealreg2spillmask[Op_RegP];
746 *idealreg2debugmask [Op_RegVectMask] = *idealreg2spillmask[Op_RegVectMask];
747
748 *idealreg2debugmask [Op_VecA] = *idealreg2spillmask[Op_VecA];
749 *idealreg2debugmask [Op_VecS] = *idealreg2spillmask[Op_VecS];
750 *idealreg2debugmask [Op_VecD] = *idealreg2spillmask[Op_VecD];
751 *idealreg2debugmask [Op_VecX] = *idealreg2spillmask[Op_VecX];
752 *idealreg2debugmask [Op_VecY] = *idealreg2spillmask[Op_VecY];
753 *idealreg2debugmask [Op_VecZ] = *idealreg2spillmask[Op_VecZ];
754
755 *idealreg2mhdebugmask[Op_RegN] = *idealreg2spillmask[Op_RegN];
756 *idealreg2mhdebugmask[Op_RegI] = *idealreg2spillmask[Op_RegI];
757 *idealreg2mhdebugmask[Op_RegL] = *idealreg2spillmask[Op_RegL];
758 *idealreg2mhdebugmask[Op_RegF] = *idealreg2spillmask[Op_RegF];
759 *idealreg2mhdebugmask[Op_RegD] = *idealreg2spillmask[Op_RegD];
760 *idealreg2mhdebugmask[Op_RegP] = *idealreg2spillmask[Op_RegP];
761 *idealreg2mhdebugmask[Op_RegVectMask] = *idealreg2spillmask[Op_RegVectMask];
762
763 *idealreg2mhdebugmask[Op_VecA] = *idealreg2spillmask[Op_VecA];
764 *idealreg2mhdebugmask[Op_VecS] = *idealreg2spillmask[Op_VecS];
765 *idealreg2mhdebugmask[Op_VecD] = *idealreg2spillmask[Op_VecD];
766 *idealreg2mhdebugmask[Op_VecX] = *idealreg2spillmask[Op_VecX];
767 *idealreg2mhdebugmask[Op_VecY] = *idealreg2spillmask[Op_VecY];
768 *idealreg2mhdebugmask[Op_VecZ] = *idealreg2spillmask[Op_VecZ];
769
770 // Prevent stub compilations from attempting to reference
771 // callee-saved (SOE) registers from debug info
772 bool exclude_soe = !Compile::current()->is_method_compilation();
773 RegMask* caller_save_mask = exclude_soe ? &caller_save_regmask_exclude_soe : &caller_save_regmask;
774 RegMask* mh_caller_save_mask = exclude_soe ? &mh_caller_save_regmask_exclude_soe : &mh_caller_save_regmask;
775
776 idealreg2debugmask[Op_RegN]->SUBTRACT(*caller_save_mask);
777 idealreg2debugmask[Op_RegI]->SUBTRACT(*caller_save_mask);
778 idealreg2debugmask[Op_RegL]->SUBTRACT(*caller_save_mask);
779 idealreg2debugmask[Op_RegF]->SUBTRACT(*caller_save_mask);
780 idealreg2debugmask[Op_RegD]->SUBTRACT(*caller_save_mask);
781 idealreg2debugmask[Op_RegP]->SUBTRACT(*caller_save_mask);
782 idealreg2debugmask[Op_RegVectMask]->SUBTRACT(*caller_save_mask);
783
784 idealreg2debugmask[Op_VecA]->SUBTRACT(*caller_save_mask);
785 idealreg2debugmask[Op_VecS]->SUBTRACT(*caller_save_mask);
786 idealreg2debugmask[Op_VecD]->SUBTRACT(*caller_save_mask);
787 idealreg2debugmask[Op_VecX]->SUBTRACT(*caller_save_mask);
788 idealreg2debugmask[Op_VecY]->SUBTRACT(*caller_save_mask);
789 idealreg2debugmask[Op_VecZ]->SUBTRACT(*caller_save_mask);
790
791 idealreg2mhdebugmask[Op_RegN]->SUBTRACT(*mh_caller_save_mask);
792 idealreg2mhdebugmask[Op_RegI]->SUBTRACT(*mh_caller_save_mask);
793 idealreg2mhdebugmask[Op_RegL]->SUBTRACT(*mh_caller_save_mask);
794 idealreg2mhdebugmask[Op_RegF]->SUBTRACT(*mh_caller_save_mask);
795 idealreg2mhdebugmask[Op_RegD]->SUBTRACT(*mh_caller_save_mask);
796 idealreg2mhdebugmask[Op_RegP]->SUBTRACT(*mh_caller_save_mask);
797 idealreg2mhdebugmask[Op_RegVectMask]->SUBTRACT(*mh_caller_save_mask);
798
799 idealreg2mhdebugmask[Op_VecA]->SUBTRACT(*mh_caller_save_mask);
800 idealreg2mhdebugmask[Op_VecS]->SUBTRACT(*mh_caller_save_mask);
801 idealreg2mhdebugmask[Op_VecD]->SUBTRACT(*mh_caller_save_mask);
802 idealreg2mhdebugmask[Op_VecX]->SUBTRACT(*mh_caller_save_mask);
803 idealreg2mhdebugmask[Op_VecY]->SUBTRACT(*mh_caller_save_mask);
804 idealreg2mhdebugmask[Op_VecZ]->SUBTRACT(*mh_caller_save_mask);
805 }
806
807 //---------------------------is_save_on_entry----------------------------------
808 bool Matcher::is_save_on_entry(int reg) {
809 return
810 _register_save_policy[reg] == 'E' ||
811 _register_save_policy[reg] == 'A'; // Save-on-entry register?
812 }
813
814 //---------------------------Fixup_Save_On_Entry-------------------------------
815 void Matcher::Fixup_Save_On_Entry( ) {
816 init_first_stack_mask();
817
818 Node *root = C->root(); // Short name for root
819 // Count number of save-on-entry registers.
820 uint soe_cnt = number_of_saved_registers();
821 uint i;
822
823 // Find the procedure Start Node
824 StartNode *start = C->start();
825 assert( start, "Expect a start node" );
826
827 // Input RegMask array shared by all Returns.
828 // The type for doubles and longs has a count of 2, but
829 // there is only 1 returned value
830 uint ret_edge_cnt = C->tf()->range_cc()->cnt();
831 RegMask *ret_rms = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
832 for (i = TypeFunc::Parms; i < ret_edge_cnt; i++) {
833 ret_rms[i] = _return_values_mask[i-TypeFunc::Parms];
834 }
835
836 // Input RegMask array shared by all Rethrows.
837 uint reth_edge_cnt = TypeFunc::Parms+1;
838 RegMask *reth_rms = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
839 // Rethrow takes exception oop only, but in the argument 0 slot.
840 OptoReg::Name reg = find_receiver();
841 if (reg >= 0) {
842 reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
843 #ifdef _LP64
844 // Need two slots for ptrs in 64-bit land
845 reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
846 #endif
847 }
848
849 // Input RegMask array shared by all TailCalls
850 uint tail_call_edge_cnt = TypeFunc::Parms+2;
851 RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
852
853 // Input RegMask array shared by all TailJumps
854 uint tail_jump_edge_cnt = TypeFunc::Parms+2;
855 RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
856
857 // TailCalls have 2 returned values (target & moop), whose masks come
858 // from the usual MachNode/MachOper mechanism. Find a sample
859 // TailCall to extract these masks and put the correct masks into
860 // the tail_call_rms array.
861 for( i=1; i < root->req(); i++ ) {
862 MachReturnNode *m = root->in(i)->as_MachReturn();
863 if( m->ideal_Opcode() == Op_TailCall ) {
864 tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
865 tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
866 break;
867 }
868 }
869
870 // TailJumps have 2 returned values (target & ex_oop), whose masks come
871 // from the usual MachNode/MachOper mechanism. Find a sample
872 // TailJump to extract these masks and put the correct masks into
873 // the tail_jump_rms array.
874 for( i=1; i < root->req(); i++ ) {
875 MachReturnNode *m = root->in(i)->as_MachReturn();
876 if( m->ideal_Opcode() == Op_TailJump ) {
877 tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
878 tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
879 break;
880 }
881 }
882
883 // Input RegMask array shared by all Halts
884 uint halt_edge_cnt = TypeFunc::Parms;
885 RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
886
887 // Capture the return input masks into each exit flavor
888 for( i=1; i < root->req(); i++ ) {
889 MachReturnNode *exit = root->in(i)->as_MachReturn();
890 switch( exit->ideal_Opcode() ) {
891 case Op_Return : exit->_in_rms = ret_rms; break;
892 case Op_Rethrow : exit->_in_rms = reth_rms; break;
893 case Op_TailCall : exit->_in_rms = tail_call_rms; break;
894 case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
895 case Op_Halt : exit->_in_rms = halt_rms; break;
896 default : ShouldNotReachHere();
897 }
898 }
899
900 // Next unused projection number from Start.
901 int proj_cnt = C->tf()->domain_cc()->cnt();
902
903 // Do all the save-on-entry registers. Make projections from Start for
904 // them, and give them a use at the exit points. To the allocator, they
905 // look like incoming register arguments.
906 for( i = 0; i < _last_Mach_Reg; i++ ) {
907 if( is_save_on_entry(i) ) {
908
909 // Add the save-on-entry to the mask array
910 ret_rms [ ret_edge_cnt] = mreg2regmask[i];
911 reth_rms [ reth_edge_cnt] = mreg2regmask[i];
912 tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
913 tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
914 // Halts need the SOE registers, but only in the stack as debug info.
915 // A just-prior uncommon-trap or deoptimization will use the SOE regs.
916 halt_rms [ halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
917
918 Node *mproj;
919
920 // Is this a RegF low half of a RegD? Double up 2 adjacent RegF's
921 // into a single RegD.
922 if( (i&1) == 0 &&
923 _register_save_type[i ] == Op_RegF &&
924 _register_save_type[i+1] == Op_RegF &&
925 is_save_on_entry(i+1) ) {
926 // Add other bit for double
927 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
928 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
929 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
930 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
931 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
932 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
933 proj_cnt += 2; // Skip 2 for doubles
934 }
935 else if( (i&1) == 1 && // Else check for high half of double
936 _register_save_type[i-1] == Op_RegF &&
937 _register_save_type[i ] == Op_RegF &&
938 is_save_on_entry(i-1) ) {
939 ret_rms [ ret_edge_cnt] = RegMask::Empty;
940 reth_rms [ reth_edge_cnt] = RegMask::Empty;
941 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
942 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
943 halt_rms [ halt_edge_cnt] = RegMask::Empty;
944 mproj = C->top();
945 }
946 // Is this a RegI low half of a RegL? Double up 2 adjacent RegI's
947 // into a single RegL.
948 else if( (i&1) == 0 &&
949 _register_save_type[i ] == Op_RegI &&
950 _register_save_type[i+1] == Op_RegI &&
951 is_save_on_entry(i+1) ) {
952 // Add other bit for long
953 ret_rms [ ret_edge_cnt].Insert(OptoReg::Name(i+1));
954 reth_rms [ reth_edge_cnt].Insert(OptoReg::Name(i+1));
955 tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
956 tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
957 halt_rms [ halt_edge_cnt].Insert(OptoReg::Name(i+1));
958 mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
959 proj_cnt += 2; // Skip 2 for longs
960 }
961 else if( (i&1) == 1 && // Else check for high half of long
962 _register_save_type[i-1] == Op_RegI &&
963 _register_save_type[i ] == Op_RegI &&
964 is_save_on_entry(i-1) ) {
965 ret_rms [ ret_edge_cnt] = RegMask::Empty;
966 reth_rms [ reth_edge_cnt] = RegMask::Empty;
967 tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
968 tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
969 halt_rms [ halt_edge_cnt] = RegMask::Empty;
970 mproj = C->top();
971 } else {
972 // Make a projection for it off the Start
973 mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
974 }
975
976 ret_edge_cnt ++;
977 reth_edge_cnt ++;
978 tail_call_edge_cnt ++;
979 tail_jump_edge_cnt ++;
980 halt_edge_cnt ++;
981
982 // Add a use of the SOE register to all exit paths
983 for( uint j=1; j < root->req(); j++ )
984 root->in(j)->add_req(mproj);
985 } // End of if a save-on-entry register
986 } // End of for all machine registers
987 }
988
989 //------------------------------init_spill_mask--------------------------------
990 void Matcher::init_spill_mask( Node *ret ) {
991 if( idealreg2regmask[Op_RegI] ) return; // One time only init
992
993 OptoReg::c_frame_pointer = c_frame_pointer();
994 c_frame_ptr_mask = c_frame_pointer();
995 #ifdef _LP64
996 // pointers are twice as big
997 c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
998 #endif
999
1000 // Start at OptoReg::stack0()
1001 STACK_ONLY_mask.Clear();
1002 OptoReg::Name init = OptoReg::stack2reg(0);
1003 // STACK_ONLY_mask is all stack bits
1004 OptoReg::Name i;
1005 for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
1006 STACK_ONLY_mask.Insert(i);
1007 // Also set the "infinite stack" bit.
1008 STACK_ONLY_mask.set_AllStack();
1009
1010 for (i = OptoReg::Name(0); i < OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i, 1)) {
1011 // Copy the register names over into the shared world.
1012 // SharedInfo::regName[i] = regName[i];
1013 // Handy RegMasks per machine register
1014 mreg2regmask[i].Insert(i);
1015
1016 // Set up regmasks used to exclude save-on-call (and always-save) registers from debug masks.
1017 if (_register_save_policy[i] == 'C' ||
1018 _register_save_policy[i] == 'A') {
1019 caller_save_regmask.Insert(i);
1020 mh_caller_save_regmask.Insert(i);
1021 }
1022 // Exclude save-on-entry registers from debug masks for stub compilations.
1023 if (_register_save_policy[i] == 'C' ||
1024 _register_save_policy[i] == 'A' ||
1025 _register_save_policy[i] == 'E') {
1026 caller_save_regmask_exclude_soe.Insert(i);
1027 mh_caller_save_regmask_exclude_soe.Insert(i);
1028 }
1029 }
1030
1031 // Also exclude the register we use to save the SP for MethodHandle
1032 // invokes to from the corresponding MH debug masks
1033 const RegMask sp_save_mask = method_handle_invoke_SP_save_mask();
1034 mh_caller_save_regmask.OR(sp_save_mask);
1035 mh_caller_save_regmask_exclude_soe.OR(sp_save_mask);
1036
1037 // Grab the Frame Pointer
1038 Node *fp = ret->in(TypeFunc::FramePtr);
1039 // Share frame pointer while making spill ops
1040 set_shared(fp);
1041
1042 // Get the ADLC notion of the right regmask, for each basic type.
1043 #ifdef _LP64
1044 idealreg2regmask[Op_RegN] = regmask_for_ideal_register(Op_RegN, ret);
1045 #endif
1046 idealreg2regmask[Op_RegI] = regmask_for_ideal_register(Op_RegI, ret);
1047 idealreg2regmask[Op_RegP] = regmask_for_ideal_register(Op_RegP, ret);
1048 idealreg2regmask[Op_RegF] = regmask_for_ideal_register(Op_RegF, ret);
1049 idealreg2regmask[Op_RegD] = regmask_for_ideal_register(Op_RegD, ret);
1050 idealreg2regmask[Op_RegL] = regmask_for_ideal_register(Op_RegL, ret);
1051 idealreg2regmask[Op_VecA] = regmask_for_ideal_register(Op_VecA, ret);
1052 idealreg2regmask[Op_VecS] = regmask_for_ideal_register(Op_VecS, ret);
1053 idealreg2regmask[Op_VecD] = regmask_for_ideal_register(Op_VecD, ret);
1054 idealreg2regmask[Op_VecX] = regmask_for_ideal_register(Op_VecX, ret);
1055 idealreg2regmask[Op_VecY] = regmask_for_ideal_register(Op_VecY, ret);
1056 idealreg2regmask[Op_VecZ] = regmask_for_ideal_register(Op_VecZ, ret);
1057 idealreg2regmask[Op_RegVectMask] = regmask_for_ideal_register(Op_RegVectMask, ret);
1058 }
1059
1060 #ifdef ASSERT
1061 static void match_alias_type(Compile* C, Node* n, Node* m) {
1062 if (!VerifyAliases) return; // do not go looking for trouble by default
1063 const TypePtr* nat = n->adr_type();
1064 const TypePtr* mat = m->adr_type();
1065 int nidx = C->get_alias_index(nat);
1066 int midx = C->get_alias_index(mat);
1067 // Detune the assert for cases like (AndI 0xFF (LoadB p)).
1068 if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
1069 for (uint i = 1; i < n->req(); i++) {
1070 Node* n1 = n->in(i);
1071 const TypePtr* n1at = n1->adr_type();
1072 if (n1at != nullptr) {
1073 nat = n1at;
1074 nidx = C->get_alias_index(n1at);
1075 }
1076 }
1077 }
1078 // %%% Kludgery. Instead, fix ideal adr_type methods for all these cases:
1079 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
1080 switch (n->Opcode()) {
1081 case Op_PrefetchAllocation:
1082 nidx = Compile::AliasIdxRaw;
1083 nat = TypeRawPtr::BOTTOM;
1084 break;
1085 }
1086 }
1087 if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
1088 switch (n->Opcode()) {
1089 case Op_ClearArray:
1090 midx = Compile::AliasIdxRaw;
1091 mat = TypeRawPtr::BOTTOM;
1092 break;
1093 }
1094 }
1095 if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
1096 switch (n->Opcode()) {
1097 case Op_Return:
1098 case Op_Rethrow:
1099 case Op_Halt:
1100 case Op_TailCall:
1101 case Op_TailJump:
1102 nidx = Compile::AliasIdxBot;
1103 nat = TypePtr::BOTTOM;
1104 break;
1105 }
1106 }
1107 if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
1108 switch (n->Opcode()) {
1109 case Op_StrComp:
1110 case Op_StrEquals:
1111 case Op_StrIndexOf:
1112 case Op_StrIndexOfChar:
1113 case Op_AryEq:
1114 case Op_VectorizedHashCode:
1115 case Op_CountPositives:
1116 case Op_MemBarVolatile:
1117 case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
1118 case Op_StrInflatedCopy:
1119 case Op_StrCompressedCopy:
1120 case Op_OnSpinWait:
1121 case Op_EncodeISOArray:
1122 nidx = Compile::AliasIdxTop;
1123 nat = nullptr;
1124 break;
1125 }
1126 }
1127 if (nidx != midx) {
1128 if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
1129 tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
1130 n->dump();
1131 m->dump();
1132 }
1133 assert(C->subsume_loads() && C->must_alias(nat, midx),
1134 "must not lose alias info when matching");
1135 }
1136 }
1137 #endif
1138
1139 //------------------------------xform------------------------------------------
1140 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1141 // Node in new-space. Given a new-space Node, recursively walk his children.
1142 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1143 Node *Matcher::xform( Node *n, int max_stack ) {
1144 // Use one stack to keep both: child's node/state and parent's node/index
1145 MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1146 mstack.push(n, Visit, nullptr, -1); // set null as parent to indicate root
1147 while (mstack.is_nonempty()) {
1148 C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1149 if (C->failing()) return nullptr;
1150 n = mstack.node(); // Leave node on stack
1151 Node_State nstate = mstack.state();
1152 if (nstate == Visit) {
1153 mstack.set_state(Post_Visit);
1154 Node *oldn = n;
1155 // Old-space or new-space check
1156 if (!C->node_arena()->contains(n)) {
1157 // Old space!
1158 Node* m;
1159 if (has_new_node(n)) { // Not yet Label/Reduced
1160 m = new_node(n);
1161 } else {
1162 if (!is_dontcare(n)) { // Matcher can match this guy
1163 // Calls match special. They match alone with no children.
1164 // Their children, the incoming arguments, match normally.
1165 m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1166 if (C->failing()) return nullptr;
1167 if (m == nullptr) { Matcher::soft_match_failure(); return nullptr; }
1168 if (n->is_MemBar()) {
1169 m->as_MachMemBar()->set_adr_type(n->adr_type());
1170 }
1171 } else { // Nothing the matcher cares about
1172 if (n->is_Proj() && n->in(0) != nullptr && n->in(0)->is_Multi()) { // Projections?
1173 // Convert to machine-dependent projection
1174 RegMask* mask = nullptr;
1175 if (n->in(0)->is_Call() && n->in(0)->as_Call()->tf()->returns_inline_type_as_fields()) {
1176 mask = return_values_mask(n->in(0)->as_Call()->tf());
1177 }
1178 m = n->in(0)->as_Multi()->match(n->as_Proj(), this, mask);
1179 NOT_PRODUCT(record_new2old(m, n);)
1180 if (m->in(0) != nullptr) // m might be top
1181 collect_null_checks(m, n);
1182 } else { // Else just a regular 'ol guy
1183 m = n->clone(); // So just clone into new-space
1184 NOT_PRODUCT(record_new2old(m, n);)
1185 // Def-Use edges will be added incrementally as Uses
1186 // of this node are matched.
1187 assert(m->outcnt() == 0, "no Uses of this clone yet");
1188 }
1189 }
1190
1191 set_new_node(n, m); // Map old to new
1192 if (_old_node_note_array != nullptr) {
1193 Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1194 n->_idx);
1195 C->set_node_notes_at(m->_idx, nn);
1196 }
1197 debug_only(match_alias_type(C, n, m));
1198 }
1199 n = m; // n is now a new-space node
1200 mstack.set_node(n);
1201 }
1202
1203 // New space!
1204 if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1205
1206 int i;
1207 // Put precedence edges on stack first (match them last).
1208 for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1209 Node *m = oldn->in(i);
1210 if (m == nullptr) break;
1211 // set -1 to call add_prec() instead of set_req() during Step1
1212 mstack.push(m, Visit, n, -1);
1213 }
1214
1215 // Handle precedence edges for interior nodes
1216 for (i = n->len()-1; (uint)i >= n->req(); i--) {
1217 Node *m = n->in(i);
1218 if (m == nullptr || C->node_arena()->contains(m)) continue;
1219 n->rm_prec(i);
1220 // set -1 to call add_prec() instead of set_req() during Step1
1221 mstack.push(m, Visit, n, -1);
1222 }
1223
1224 // For constant debug info, I'd rather have unmatched constants.
1225 int cnt = n->req();
1226 JVMState* jvms = n->jvms();
1227 int debug_cnt = jvms ? jvms->debug_start() : cnt;
1228
1229 // Now do only debug info. Clone constants rather than matching.
1230 // Constants are represented directly in the debug info without
1231 // the need for executable machine instructions.
1232 // Monitor boxes are also represented directly.
1233 for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1234 Node *m = n->in(i); // Get input
1235 int op = m->Opcode();
1236 assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1237 if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1238 op == Op_ConF || op == Op_ConD || op == Op_ConL
1239 // || op == Op_BoxLock // %%%% enable this and remove (+++) in chaitin.cpp
1240 ) {
1241 m = m->clone();
1242 NOT_PRODUCT(record_new2old(m, n));
1243 mstack.push(m, Post_Visit, n, i); // Don't need to visit
1244 mstack.push(m->in(0), Visit, m, 0);
1245 } else {
1246 mstack.push(m, Visit, n, i);
1247 }
1248 }
1249
1250 // And now walk his children, and convert his inputs to new-space.
1251 for( ; i >= 0; --i ) { // For all normal inputs do
1252 Node *m = n->in(i); // Get input
1253 if(m != nullptr)
1254 mstack.push(m, Visit, n, i);
1255 }
1256
1257 }
1258 else if (nstate == Post_Visit) {
1259 // Set xformed input
1260 Node *p = mstack.parent();
1261 if (p != nullptr) { // root doesn't have parent
1262 int i = (int)mstack.index();
1263 if (i >= 0)
1264 p->set_req(i, n); // required input
1265 else if (i == -1)
1266 p->add_prec(n); // precedence input
1267 else
1268 ShouldNotReachHere();
1269 }
1270 mstack.pop(); // remove processed node from stack
1271 }
1272 else {
1273 ShouldNotReachHere();
1274 }
1275 } // while (mstack.is_nonempty())
1276 return n; // Return new-space Node
1277 }
1278
1279 //------------------------------warp_outgoing_stk_arg------------------------
1280 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1281 // Convert outgoing argument location to a pre-biased stack offset
1282 if (reg->is_stack()) {
1283 OptoReg::Name warped = reg->reg2stack();
1284 // Adjust the stack slot offset to be the register number used
1285 // by the allocator.
1286 warped = OptoReg::add(begin_out_arg_area, warped);
1287 // Keep track of the largest numbered stack slot used for an arg.
1288 // Largest used slot per call-site indicates the amount of stack
1289 // that is killed by the call.
1290 if( warped >= out_arg_limit_per_call )
1291 out_arg_limit_per_call = OptoReg::add(warped,1);
1292 if (!RegMask::can_represent_arg(warped)) {
1293 // Bailout. For example not enough space on stack for all arguments. Happens for methods with too many arguments.
1294 C->record_method_not_compilable("unsupported calling sequence");
1295 return OptoReg::Bad;
1296 }
1297 return warped;
1298 }
1299 return OptoReg::as_OptoReg(reg);
1300 }
1301
1302
1303 //------------------------------match_sfpt-------------------------------------
1304 // Helper function to match call instructions. Calls match special.
1305 // They match alone with no children. Their children, the incoming
1306 // arguments, match normally.
1307 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1308 MachSafePointNode *msfpt = nullptr;
1309 MachCallNode *mcall = nullptr;
1310 uint cnt;
1311 // Split out case for SafePoint vs Call
1312 CallNode *call;
1313 const TypeTuple *domain;
1314 ciMethod* method = nullptr;
1315 bool is_method_handle_invoke = false; // for special kill effects
1316 if( sfpt->is_Call() ) {
1317 call = sfpt->as_Call();
1318 domain = call->tf()->domain_cc();
1319 cnt = domain->cnt();
1320
1321 // Match just the call, nothing else
1322 MachNode *m = match_tree(call);
1323 if (C->failing()) return nullptr;
1324 if( m == nullptr ) { Matcher::soft_match_failure(); return nullptr; }
1325
1326 // Copy data from the Ideal SafePoint to the machine version
1327 mcall = m->as_MachCall();
1328
1329 mcall->set_tf( call->tf());
1330 mcall->set_entry_point( call->entry_point());
1331 mcall->set_cnt( call->cnt());
1332 mcall->set_guaranteed_safepoint(call->guaranteed_safepoint());
1333
1334 if( mcall->is_MachCallJava() ) {
1335 MachCallJavaNode *mcall_java = mcall->as_MachCallJava();
1336 const CallJavaNode *call_java = call->as_CallJava();
1337 assert(call_java->validate_symbolic_info(), "inconsistent info");
1338 method = call_java->method();
1339 mcall_java->_method = method;
1340 mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1341 is_method_handle_invoke = call_java->is_method_handle_invoke();
1342 mcall_java->_method_handle_invoke = is_method_handle_invoke;
1343 mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1344 mcall_java->_arg_escape = call_java->arg_escape();
1345 if (is_method_handle_invoke) {
1346 C->set_has_method_handle_invokes(true);
1347 }
1348 if( mcall_java->is_MachCallStaticJava() )
1349 mcall_java->as_MachCallStaticJava()->_name =
1350 call_java->as_CallStaticJava()->_name;
1351 if( mcall_java->is_MachCallDynamicJava() )
1352 mcall_java->as_MachCallDynamicJava()->_vtable_index =
1353 call_java->as_CallDynamicJava()->_vtable_index;
1354 }
1355 else if( mcall->is_MachCallRuntime() ) {
1356 MachCallRuntimeNode* mach_call_rt = mcall->as_MachCallRuntime();
1357 mach_call_rt->_name = call->as_CallRuntime()->_name;
1358 mach_call_rt->_leaf_no_fp = call->is_CallLeafNoFP();
1359 }
1360 msfpt = mcall;
1361 }
1362 // This is a non-call safepoint
1363 else {
1364 call = nullptr;
1365 domain = nullptr;
1366 MachNode *mn = match_tree(sfpt);
1367 if (C->failing()) return nullptr;
1368 msfpt = mn->as_MachSafePoint();
1369 cnt = TypeFunc::Parms;
1370 }
1371 msfpt->_has_ea_local_in_scope = sfpt->has_ea_local_in_scope();
1372
1373 // Advertise the correct memory effects (for anti-dependence computation).
1374 msfpt->set_adr_type(sfpt->adr_type());
1375
1376 // Allocate a private array of RegMasks. These RegMasks are not shared.
1377 msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1378 // Empty them all.
1379 for (uint i = 0; i < cnt; i++) ::new (&(msfpt->_in_rms[i])) RegMask();
1380
1381 // Do all the pre-defined non-Empty register masks
1382 msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1383 msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1384
1385 // Place first outgoing argument can possibly be put.
1386 OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1387 assert( is_even(begin_out_arg_area), "" );
1388 // Compute max outgoing register number per call site.
1389 OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1390 // Calls to C may hammer extra stack slots above and beyond any arguments.
1391 // These are usually backing store for register arguments for varargs.
1392 if( call != nullptr && call->is_CallRuntime() )
1393 out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1394
1395
1396 // Do the normal argument list (parameters) register masks
1397 // Null entry point is a special cast where the target of the call
1398 // is in a register.
1399 int adj = (call != nullptr && call->entry_point() == nullptr) ? 1 : 0;
1400 int argcnt = cnt - TypeFunc::Parms - adj;
1401 if( argcnt > 0 ) { // Skip it all if we have no args
1402 BasicType *sig_bt = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1403 VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1404 int i;
1405 for( i = 0; i < argcnt; i++ ) {
1406 sig_bt[i] = domain->field_at(i+TypeFunc::Parms+adj)->basic_type();
1407 }
1408 // V-call to pick proper calling convention
1409 call->calling_convention( sig_bt, parm_regs, argcnt );
1410
1411 #ifdef ASSERT
1412 // Sanity check users' calling convention. Really handy during
1413 // the initial porting effort. Fairly expensive otherwise.
1414 { for (int i = 0; i<argcnt; i++) {
1415 if( !parm_regs[i].first()->is_valid() &&
1416 !parm_regs[i].second()->is_valid() ) continue;
1417 VMReg reg1 = parm_regs[i].first();
1418 VMReg reg2 = parm_regs[i].second();
1419 for (int j = 0; j < i; j++) {
1420 if( !parm_regs[j].first()->is_valid() &&
1421 !parm_regs[j].second()->is_valid() ) continue;
1422 VMReg reg3 = parm_regs[j].first();
1423 VMReg reg4 = parm_regs[j].second();
1424 if( !reg1->is_valid() ) {
1425 assert( !reg2->is_valid(), "valid halvsies" );
1426 } else if( !reg3->is_valid() ) {
1427 assert( !reg4->is_valid(), "valid halvsies" );
1428 } else {
1429 assert( reg1 != reg2, "calling conv. must produce distinct regs");
1430 assert( reg1 != reg3, "calling conv. must produce distinct regs");
1431 assert( reg1 != reg4, "calling conv. must produce distinct regs");
1432 assert( reg2 != reg3, "calling conv. must produce distinct regs");
1433 assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1434 assert( reg3 != reg4, "calling conv. must produce distinct regs");
1435 }
1436 }
1437 }
1438 }
1439 #endif
1440
1441 // Visit each argument. Compute its outgoing register mask.
1442 // Return results now can have 2 bits returned.
1443 // Compute max over all outgoing arguments both per call-site
1444 // and over the entire method.
1445 for( i = 0; i < argcnt; i++ ) {
1446 // Address of incoming argument mask to fill in
1447 RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms+adj];
1448 VMReg first = parm_regs[i].first();
1449 VMReg second = parm_regs[i].second();
1450 if(!first->is_valid() &&
1451 !second->is_valid()) {
1452 continue; // Avoid Halves
1453 }
1454 // Handle case where arguments are in vector registers.
1455 if(call->in(TypeFunc::Parms + i)->bottom_type()->isa_vect()) {
1456 OptoReg::Name reg_fst = OptoReg::as_OptoReg(first);
1457 OptoReg::Name reg_snd = OptoReg::as_OptoReg(second);
1458 assert (reg_fst <= reg_snd, "fst=%d snd=%d", reg_fst, reg_snd);
1459 for (OptoReg::Name r = reg_fst; r <= reg_snd; r++) {
1460 rm->Insert(r);
1461 }
1462 }
1463 // Grab first register, adjust stack slots and insert in mask.
1464 OptoReg::Name reg1 = warp_outgoing_stk_arg(first, begin_out_arg_area, out_arg_limit_per_call );
1465 if (OptoReg::is_valid(reg1)) {
1466 rm->Insert( reg1 );
1467 }
1468 // Grab second register (if any), adjust stack slots and insert in mask.
1469 OptoReg::Name reg2 = warp_outgoing_stk_arg(second, begin_out_arg_area, out_arg_limit_per_call );
1470 if (OptoReg::is_valid(reg2)) {
1471 rm->Insert( reg2 );
1472 }
1473 } // End of for all arguments
1474 }
1475
1476 // Compute the max stack slot killed by any call. These will not be
1477 // available for debug info, and will be used to adjust FIRST_STACK_mask
1478 // after all call sites have been visited.
1479 if( _out_arg_limit < out_arg_limit_per_call)
1480 _out_arg_limit = out_arg_limit_per_call;
1481
1482 if (mcall) {
1483 // Kill the outgoing argument area, including any non-argument holes and
1484 // any legacy C-killed slots. Use Fat-Projections to do the killing.
1485 // Since the max-per-method covers the max-per-call-site and debug info
1486 // is excluded on the max-per-method basis, debug info cannot land in
1487 // this killed area.
1488 uint r_cnt = mcall->tf()->range_sig()->cnt();
1489 MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1490 if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1491 // Bailout. We do not have space to represent all arguments.
1492 C->record_method_not_compilable("unsupported outgoing calling sequence");
1493 } else {
1494 for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1495 proj->_rout.Insert(OptoReg::Name(i));
1496 }
1497 if (proj->_rout.is_NotEmpty()) {
1498 push_projection(proj);
1499 }
1500 }
1501 // Transfer the safepoint information from the call to the mcall
1502 // Move the JVMState list
1503 msfpt->set_jvms(sfpt->jvms());
1504 for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1505 jvms->set_map(sfpt);
1506 }
1507
1508 // Debug inputs begin just after the last incoming parameter
1509 assert((mcall == nullptr) || (mcall->jvms() == nullptr) ||
1510 (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain_cc()->cnt()), "");
1511
1512 // Add additional edges.
1513 if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1514 // For these calls we can not add MachConstantBase in expand(), as the
1515 // ins are not complete then.
1516 msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1517 if (msfpt->jvms() &&
1518 msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1519 // We added an edge before jvms, so we must adapt the position of the ins.
1520 msfpt->jvms()->adapt_position(+1);
1521 }
1522 }
1523
1524 // Registers killed by the call are set in the local scheduling pass
1525 // of Global Code Motion.
1526 return msfpt;
1527 }
1528
1529 //---------------------------match_tree----------------------------------------
1530 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce. Used as part
1531 // of the whole-sale conversion from Ideal to Mach Nodes. Also used for
1532 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1533 // a Load's result RegMask for memoization in idealreg2regmask[]
1534 MachNode *Matcher::match_tree( const Node *n ) {
1535 assert( n->Opcode() != Op_Phi, "cannot match" );
1536 assert( !n->is_block_start(), "cannot match" );
1537 // Set the mark for all locally allocated State objects.
1538 // When this call returns, the _states_arena arena will be reset
1539 // freeing all State objects.
1540 ResourceMark rm( &_states_arena );
1541
1542 LabelRootDepth = 0;
1543
1544 // StoreNodes require their Memory input to match any LoadNodes
1545 Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1546 #ifdef ASSERT
1547 Node* save_mem_node = _mem_node;
1548 _mem_node = n->is_Store() ? (Node*)n : nullptr;
1549 #endif
1550 // State object for root node of match tree
1551 // Allocate it on _states_arena - stack allocation can cause stack overflow.
1552 State *s = new (&_states_arena) State;
1553 s->_kids[0] = nullptr;
1554 s->_kids[1] = nullptr;
1555 s->_leaf = (Node*)n;
1556 // Label the input tree, allocating labels from top-level arena
1557 Node* root_mem = mem;
1558 Label_Root(n, s, n->in(0), root_mem);
1559 if (C->failing()) return nullptr;
1560
1561 // The minimum cost match for the whole tree is found at the root State
1562 uint mincost = max_juint;
1563 uint cost = max_juint;
1564 uint i;
1565 for (i = 0; i < NUM_OPERANDS; i++) {
1566 if (s->valid(i) && // valid entry and
1567 s->cost(i) < cost && // low cost and
1568 s->rule(i) >= NUM_OPERANDS) {// not an operand
1569 mincost = i;
1570 cost = s->cost(i);
1571 }
1572 }
1573 if (mincost == max_juint) {
1574 #ifndef PRODUCT
1575 tty->print("No matching rule for:");
1576 s->dump();
1577 #endif
1578 Matcher::soft_match_failure();
1579 return nullptr;
1580 }
1581 // Reduce input tree based upon the state labels to machine Nodes
1582 MachNode *m = ReduceInst(s, s->rule(mincost), mem);
1583 // New-to-old mapping is done in ReduceInst, to cover complex instructions.
1584 NOT_PRODUCT(_old2new_map.map(n->_idx, m);)
1585
1586 // Add any Matcher-ignored edges
1587 uint cnt = n->req();
1588 uint start = 1;
1589 if( mem != (Node*)1 ) start = MemNode::Memory+1;
1590 if( n->is_AddP() ) {
1591 assert( mem == (Node*)1, "" );
1592 start = AddPNode::Base+1;
1593 }
1594 for( i = start; i < cnt; i++ ) {
1595 if( !n->match_edge(i) ) {
1596 if( i < m->req() )
1597 m->ins_req( i, n->in(i) );
1598 else
1599 m->add_req( n->in(i) );
1600 }
1601 }
1602
1603 debug_only( _mem_node = save_mem_node; )
1604 return m;
1605 }
1606
1607
1608 //------------------------------match_into_reg---------------------------------
1609 // Choose to either match this Node in a register or part of the current
1610 // match tree. Return true for requiring a register and false for matching
1611 // as part of the current match tree.
1612 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1613
1614 const Type *t = m->bottom_type();
1615
1616 if (t->singleton()) {
1617 // Never force constants into registers. Allow them to match as
1618 // constants or registers. Copies of the same value will share
1619 // the same register. See find_shared_node.
1620 return false;
1621 } else { // Not a constant
1622 // Stop recursion if they have different Controls.
1623 Node* m_control = m->in(0);
1624 // Control of load's memory can post-dominates load's control.
1625 // So use it since load can't float above its memory.
1626 Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : nullptr;
1627 if (control && m_control && control != m_control && control != mem_control) {
1628
1629 // Actually, we can live with the most conservative control we
1630 // find, if it post-dominates the others. This allows us to
1631 // pick up load/op/store trees where the load can float a little
1632 // above the store.
1633 Node *x = control;
1634 const uint max_scan = 6; // Arbitrary scan cutoff
1635 uint j;
1636 for (j=0; j<max_scan; j++) {
1637 if (x->is_Region()) // Bail out at merge points
1638 return true;
1639 x = x->in(0);
1640 if (x == m_control) // Does 'control' post-dominate
1641 break; // m->in(0)? If so, we can use it
1642 if (x == mem_control) // Does 'control' post-dominate
1643 break; // mem_control? If so, we can use it
1644 }
1645 if (j == max_scan) // No post-domination before scan end?
1646 return true; // Then break the match tree up
1647 }
1648 if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1649 (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1650 // These are commonly used in address expressions and can
1651 // efficiently fold into them on X64 in some cases.
1652 return false;
1653 }
1654 }
1655
1656 // Not forceable cloning. If shared, put it into a register.
1657 return shared;
1658 }
1659
1660
1661 //------------------------------Instruction Selection--------------------------
1662 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1663 // ideal nodes to machine instructions. Trees are delimited by shared Nodes,
1664 // things the Matcher does not match (e.g., Memory), and things with different
1665 // Controls (hence forced into different blocks). We pass in the Control
1666 // selected for this entire State tree.
1667
1668 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1669 // Store and the Load must have identical Memories (as well as identical
1670 // pointers). Since the Matcher does not have anything for Memory (and
1671 // does not handle DAGs), I have to match the Memory input myself. If the
1672 // Tree root is a Store or if there are multiple Loads in the tree, I require
1673 // all Loads to have the identical memory.
1674 Node* Matcher::Label_Root(const Node* n, State* svec, Node* control, Node*& mem) {
1675 // Since Label_Root is a recursive function, its possible that we might run
1676 // out of stack space. See bugs 6272980 & 6227033 for more info.
1677 LabelRootDepth++;
1678 if (LabelRootDepth > MaxLabelRootDepth) {
1679 // Bailout. Can for example be hit with a deep chain of operations.
1680 C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1681 return nullptr;
1682 }
1683 uint care = 0; // Edges matcher cares about
1684 uint cnt = n->req();
1685 uint i = 0;
1686
1687 // Examine children for memory state
1688 // Can only subsume a child into your match-tree if that child's memory state
1689 // is not modified along the path to another input.
1690 // It is unsafe even if the other inputs are separate roots.
1691 Node *input_mem = nullptr;
1692 for( i = 1; i < cnt; i++ ) {
1693 if( !n->match_edge(i) ) continue;
1694 Node *m = n->in(i); // Get ith input
1695 assert( m, "expect non-null children" );
1696 if( m->is_Load() ) {
1697 if( input_mem == nullptr ) {
1698 input_mem = m->in(MemNode::Memory);
1699 if (mem == (Node*)1) {
1700 // Save this memory to bail out if there's another memory access
1701 // to a different memory location in the same tree.
1702 mem = input_mem;
1703 }
1704 } else if( input_mem != m->in(MemNode::Memory) ) {
1705 input_mem = NodeSentinel;
1706 }
1707 }
1708 }
1709
1710 for( i = 1; i < cnt; i++ ){// For my children
1711 if( !n->match_edge(i) ) continue;
1712 Node *m = n->in(i); // Get ith input
1713 // Allocate states out of a private arena
1714 State *s = new (&_states_arena) State;
1715 svec->_kids[care++] = s;
1716 assert( care <= 2, "binary only for now" );
1717
1718 // Recursively label the State tree.
1719 s->_kids[0] = nullptr;
1720 s->_kids[1] = nullptr;
1721 s->_leaf = m;
1722
1723 // Check for leaves of the State Tree; things that cannot be a part of
1724 // the current tree. If it finds any, that value is matched as a
1725 // register operand. If not, then the normal matching is used.
1726 if( match_into_reg(n, m, control, i, is_shared(m)) ||
1727 // Stop recursion if this is a LoadNode and there is another memory access
1728 // to a different memory location in the same tree (for example, a StoreNode
1729 // at the root of this tree or another LoadNode in one of the children).
1730 ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1731 // Can NOT include the match of a subtree when its memory state
1732 // is used by any of the other subtrees
1733 (input_mem == NodeSentinel) ) {
1734 // Print when we exclude matching due to different memory states at input-loads
1735 if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1736 && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1737 tty->print_cr("invalid input_mem");
1738 }
1739 // Switch to a register-only opcode; this value must be in a register
1740 // and cannot be subsumed as part of a larger instruction.
1741 s->DFA( m->ideal_reg(), m );
1742
1743 } else {
1744 // If match tree has no control and we do, adopt it for entire tree
1745 if( control == nullptr && m->in(0) != nullptr && m->req() > 1 )
1746 control = m->in(0); // Pick up control
1747 // Else match as a normal part of the match tree.
1748 control = Label_Root(m, s, control, mem);
1749 if (C->failing()) return nullptr;
1750 }
1751 }
1752
1753 // Call DFA to match this node, and return
1754 svec->DFA( n->Opcode(), n );
1755
1756 #ifdef ASSERT
1757 uint x;
1758 for( x = 0; x < _LAST_MACH_OPER; x++ )
1759 if( svec->valid(x) )
1760 break;
1761
1762 if (x >= _LAST_MACH_OPER) {
1763 n->dump();
1764 svec->dump();
1765 assert( false, "bad AD file" );
1766 }
1767 #endif
1768 return control;
1769 }
1770
1771
1772 // Con nodes reduced using the same rule can share their MachNode
1773 // which reduces the number of copies of a constant in the final
1774 // program. The register allocator is free to split uses later to
1775 // split live ranges.
1776 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1777 if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return nullptr;
1778
1779 // See if this Con has already been reduced using this rule.
1780 if (_shared_nodes.max() <= leaf->_idx) return nullptr;
1781 MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1782 if (last != nullptr && rule == last->rule()) {
1783 // Don't expect control change for DecodeN
1784 if (leaf->is_DecodeNarrowPtr())
1785 return last;
1786 // Get the new space root.
1787 Node* xroot = new_node(C->root());
1788 if (xroot == nullptr) {
1789 // This shouldn't happen give the order of matching.
1790 return nullptr;
1791 }
1792
1793 // Shared constants need to have their control be root so they
1794 // can be scheduled properly.
1795 Node* control = last->in(0);
1796 if (control != xroot) {
1797 if (control == nullptr || control == C->root()) {
1798 last->set_req(0, xroot);
1799 } else {
1800 assert(false, "unexpected control");
1801 return nullptr;
1802 }
1803 }
1804 return last;
1805 }
1806 return nullptr;
1807 }
1808
1809
1810 //------------------------------ReduceInst-------------------------------------
1811 // Reduce a State tree (with given Control) into a tree of MachNodes.
1812 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1813 // complicated machine Nodes. Each MachNode covers some tree of Ideal Nodes.
1814 // Each MachNode has a number of complicated MachOper operands; each
1815 // MachOper also covers a further tree of Ideal Nodes.
1816
1817 // The root of the Ideal match tree is always an instruction, so we enter
1818 // the recursion here. After building the MachNode, we need to recurse
1819 // the tree checking for these cases:
1820 // (1) Child is an instruction -
1821 // Build the instruction (recursively), add it as an edge.
1822 // Build a simple operand (register) to hold the result of the instruction.
1823 // (2) Child is an interior part of an instruction -
1824 // Skip over it (do nothing)
1825 // (3) Child is the start of a operand -
1826 // Build the operand, place it inside the instruction
1827 // Call ReduceOper.
1828 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1829 assert( rule >= NUM_OPERANDS, "called with operand rule" );
1830
1831 MachNode* shared_node = find_shared_node(s->_leaf, rule);
1832 if (shared_node != nullptr) {
1833 return shared_node;
1834 }
1835
1836 // Build the object to represent this state & prepare for recursive calls
1837 MachNode *mach = s->MachNodeGenerator(rule);
1838 guarantee(mach != nullptr, "Missing MachNode");
1839 mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1840 assert( mach->_opnds[0] != nullptr, "Missing result operand" );
1841 Node *leaf = s->_leaf;
1842 NOT_PRODUCT(record_new2old(mach, leaf);)
1843 // Check for instruction or instruction chain rule
1844 if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1845 assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1846 "duplicating node that's already been matched");
1847 // Instruction
1848 mach->add_req( leaf->in(0) ); // Set initial control
1849 // Reduce interior of complex instruction
1850 ReduceInst_Interior( s, rule, mem, mach, 1 );
1851 } else {
1852 // Instruction chain rules are data-dependent on their inputs
1853 mach->add_req(0); // Set initial control to none
1854 ReduceInst_Chain_Rule( s, rule, mem, mach );
1855 }
1856
1857 // If a Memory was used, insert a Memory edge
1858 if( mem != (Node*)1 ) {
1859 mach->ins_req(MemNode::Memory,mem);
1860 #ifdef ASSERT
1861 // Verify adr type after matching memory operation
1862 const MachOper* oper = mach->memory_operand();
1863 if (oper != nullptr && oper != (MachOper*)-1) {
1864 // It has a unique memory operand. Find corresponding ideal mem node.
1865 Node* m = nullptr;
1866 if (leaf->is_Mem()) {
1867 m = leaf;
1868 } else {
1869 m = _mem_node;
1870 assert(m != nullptr && m->is_Mem(), "expecting memory node");
1871 }
1872 const Type* mach_at = mach->adr_type();
1873 // DecodeN node consumed by an address may have different type
1874 // than its input. Don't compare types for such case.
1875 if (m->adr_type() != mach_at &&
1876 (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1877 (m->in(MemNode::Address)->is_AddP() &&
1878 m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) ||
1879 (m->in(MemNode::Address)->is_AddP() &&
1880 m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1881 m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) {
1882 mach_at = m->adr_type();
1883 }
1884 if (m->adr_type() != mach_at) {
1885 m->dump();
1886 tty->print_cr("mach:");
1887 mach->dump(1);
1888 }
1889 assert(m->adr_type() == mach_at, "matcher should not change adr type");
1890 }
1891 #endif
1892 }
1893
1894 // If the _leaf is an AddP, insert the base edge
1895 if (leaf->is_AddP()) {
1896 mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1897 }
1898
1899 uint number_of_projections_prior = number_of_projections();
1900
1901 // Perform any 1-to-many expansions required
1902 MachNode *ex = mach->Expand(s, _projection_list, mem);
1903 if (ex != mach) {
1904 assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1905 if( ex->in(1)->is_Con() )
1906 ex->in(1)->set_req(0, C->root());
1907 // Remove old node from the graph
1908 for( uint i=0; i<mach->req(); i++ ) {
1909 mach->set_req(i,nullptr);
1910 }
1911 NOT_PRODUCT(record_new2old(ex, s->_leaf);)
1912 }
1913
1914 // PhaseChaitin::fixup_spills will sometimes generate spill code
1915 // via the matcher. By the time, nodes have been wired into the CFG,
1916 // and any further nodes generated by expand rules will be left hanging
1917 // in space, and will not get emitted as output code. Catch this.
1918 // Also, catch any new register allocation constraints ("projections")
1919 // generated belatedly during spill code generation.
1920 if (_allocation_started) {
1921 guarantee(ex == mach, "no expand rules during spill generation");
1922 guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1923 }
1924
1925 if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1926 // Record the con for sharing
1927 _shared_nodes.map(leaf->_idx, ex);
1928 }
1929
1930 // Have mach nodes inherit GC barrier data
1931 if (leaf->is_LoadStore()) {
1932 mach->set_barrier_data(leaf->as_LoadStore()->barrier_data());
1933 } else if (leaf->is_Mem()) {
1934 mach->set_barrier_data(leaf->as_Mem()->barrier_data());
1935 }
1936
1937 return ex;
1938 }
1939
1940 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1941 for (uint i = n->req(); i < n->len(); i++) {
1942 if (n->in(i) != nullptr) {
1943 mach->add_prec(n->in(i));
1944 }
1945 }
1946 }
1947
1948 void Matcher::ReduceInst_Chain_Rule(State* s, int rule, Node* &mem, MachNode* mach) {
1949 // 'op' is what I am expecting to receive
1950 int op = _leftOp[rule];
1951 // Operand type to catch childs result
1952 // This is what my child will give me.
1953 unsigned int opnd_class_instance = s->rule(op);
1954 // Choose between operand class or not.
1955 // This is what I will receive.
1956 int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1957 // New rule for child. Chase operand classes to get the actual rule.
1958 unsigned int newrule = s->rule(catch_op);
1959
1960 if (newrule < NUM_OPERANDS) {
1961 // Chain from operand or operand class, may be output of shared node
1962 assert(opnd_class_instance < NUM_OPERANDS, "Bad AD file: Instruction chain rule must chain from operand");
1963 // Insert operand into array of operands for this instruction
1964 mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1965
1966 ReduceOper(s, newrule, mem, mach);
1967 } else {
1968 // Chain from the result of an instruction
1969 assert(newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1970 mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1971 Node *mem1 = (Node*)1;
1972 debug_only(Node *save_mem_node = _mem_node;)
1973 mach->add_req( ReduceInst(s, newrule, mem1) );
1974 debug_only(_mem_node = save_mem_node;)
1975 }
1976 return;
1977 }
1978
1979
1980 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1981 handle_precedence_edges(s->_leaf, mach);
1982
1983 if( s->_leaf->is_Load() ) {
1984 Node *mem2 = s->_leaf->in(MemNode::Memory);
1985 assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1986 debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1987 mem = mem2;
1988 }
1989 if( s->_leaf->in(0) != nullptr && s->_leaf->req() > 1) {
1990 if( mach->in(0) == nullptr )
1991 mach->set_req(0, s->_leaf->in(0));
1992 }
1993
1994 // Now recursively walk the state tree & add operand list.
1995 for( uint i=0; i<2; i++ ) { // binary tree
1996 State *newstate = s->_kids[i];
1997 if( newstate == nullptr ) break; // Might only have 1 child
1998 // 'op' is what I am expecting to receive
1999 int op;
2000 if( i == 0 ) {
2001 op = _leftOp[rule];
2002 } else {
2003 op = _rightOp[rule];
2004 }
2005 // Operand type to catch childs result
2006 // This is what my child will give me.
2007 int opnd_class_instance = newstate->rule(op);
2008 // Choose between operand class or not.
2009 // This is what I will receive.
2010 int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
2011 // New rule for child. Chase operand classes to get the actual rule.
2012 int newrule = newstate->rule(catch_op);
2013
2014 if (newrule < NUM_OPERANDS) { // Operand/operandClass or internalOp/instruction?
2015 // Operand/operandClass
2016 // Insert operand into array of operands for this instruction
2017 mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
2018 ReduceOper(newstate, newrule, mem, mach);
2019
2020 } else { // Child is internal operand or new instruction
2021 if (newrule < _LAST_MACH_OPER) { // internal operand or instruction?
2022 // internal operand --> call ReduceInst_Interior
2023 // Interior of complex instruction. Do nothing but recurse.
2024 num_opnds = ReduceInst_Interior(newstate, newrule, mem, mach, num_opnds);
2025 } else {
2026 // instruction --> call build operand( ) to catch result
2027 // --> ReduceInst( newrule )
2028 mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
2029 Node *mem1 = (Node*)1;
2030 debug_only(Node *save_mem_node = _mem_node;)
2031 mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
2032 debug_only(_mem_node = save_mem_node;)
2033 }
2034 }
2035 assert( mach->_opnds[num_opnds-1], "" );
2036 }
2037 return num_opnds;
2038 }
2039
2040 // This routine walks the interior of possible complex operands.
2041 // At each point we check our children in the match tree:
2042 // (1) No children -
2043 // We are a leaf; add _leaf field as an input to the MachNode
2044 // (2) Child is an internal operand -
2045 // Skip over it ( do nothing )
2046 // (3) Child is an instruction -
2047 // Call ReduceInst recursively and
2048 // and instruction as an input to the MachNode
2049 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
2050 assert( rule < _LAST_MACH_OPER, "called with operand rule" );
2051 State *kid = s->_kids[0];
2052 assert( kid == nullptr || s->_leaf->in(0) == nullptr, "internal operands have no control" );
2053
2054 // Leaf? And not subsumed?
2055 if( kid == nullptr && !_swallowed[rule] ) {
2056 mach->add_req( s->_leaf ); // Add leaf pointer
2057 return; // Bail out
2058 }
2059
2060 if( s->_leaf->is_Load() ) {
2061 assert( mem == (Node*)1, "multiple Memories being matched at once?" );
2062 mem = s->_leaf->in(MemNode::Memory);
2063 debug_only(_mem_node = s->_leaf;)
2064 }
2065
2066 handle_precedence_edges(s->_leaf, mach);
2067
2068 if( s->_leaf->in(0) && s->_leaf->req() > 1) {
2069 if( !mach->in(0) )
2070 mach->set_req(0,s->_leaf->in(0));
2071 else {
2072 assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
2073 }
2074 }
2075
2076 for (uint i = 0; kid != nullptr && i < 2; kid = s->_kids[1], i++) { // binary tree
2077 int newrule;
2078 if( i == 0) {
2079 newrule = kid->rule(_leftOp[rule]);
2080 } else {
2081 newrule = kid->rule(_rightOp[rule]);
2082 }
2083
2084 if (newrule < _LAST_MACH_OPER) { // Operand or instruction?
2085 // Internal operand; recurse but do nothing else
2086 ReduceOper(kid, newrule, mem, mach);
2087
2088 } else { // Child is a new instruction
2089 // Reduce the instruction, and add a direct pointer from this
2090 // machine instruction to the newly reduced one.
2091 Node *mem1 = (Node*)1;
2092 debug_only(Node *save_mem_node = _mem_node;)
2093 mach->add_req( ReduceInst( kid, newrule, mem1 ) );
2094 debug_only(_mem_node = save_mem_node;)
2095 }
2096 }
2097 }
2098
2099
2100 // -------------------------------------------------------------------------
2101 // Java-Java calling convention
2102 // (what you use when Java calls Java)
2103
2104 //------------------------------find_receiver----------------------------------
2105 // For a given signature, return the OptoReg for parameter 0.
2106 OptoReg::Name Matcher::find_receiver() {
2107 VMRegPair regs;
2108 BasicType sig_bt = T_OBJECT;
2109 SharedRuntime::java_calling_convention(&sig_bt, ®s, 1);
2110 // Return argument 0 register. In the LP64 build pointers
2111 // take 2 registers, but the VM wants only the 'main' name.
2112 return OptoReg::as_OptoReg(regs.first());
2113 }
2114
2115 bool Matcher::is_vshift_con_pattern(Node* n, Node* m) {
2116 if (n != nullptr && m != nullptr) {
2117 return VectorNode::is_vector_shift(n) &&
2118 VectorNode::is_vector_shift_count(m) && m->in(1)->is_Con();
2119 }
2120 return false;
2121 }
2122
2123 bool Matcher::clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
2124 // Must clone all producers of flags, or we will not match correctly.
2125 // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2126 // then it will match into an ideal Op_RegFlags. Alas, the fp-flags
2127 // are also there, so we may match a float-branch to int-flags and
2128 // expect the allocator to haul the flags from the int-side to the
2129 // fp-side. No can do.
2130 if (_must_clone[m->Opcode()]) {
2131 mstack.push(m, Visit);
2132 return true;
2133 }
2134 return pd_clone_node(n, m, mstack);
2135 }
2136
2137 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2138 Node *off = m->in(AddPNode::Offset);
2139 if (off->is_Con()) {
2140 address_visited.test_set(m->_idx); // Flag as address_visited
2141 mstack.push(m->in(AddPNode::Address), Pre_Visit);
2142 // Clone X+offset as it also folds into most addressing expressions
2143 mstack.push(off, Visit);
2144 mstack.push(m->in(AddPNode::Base), Pre_Visit);
2145 return true;
2146 }
2147 return false;
2148 }
2149
2150 // A method-klass-holder may be passed in the inline_cache_reg
2151 // and then expanded into the inline_cache_reg and a method_ptr register
2152 // defined in ad_<arch>.cpp
2153
2154 //------------------------------find_shared------------------------------------
2155 // Set bits if Node is shared or otherwise a root
2156 void Matcher::find_shared(Node* n) {
2157 // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2158 MStack mstack(C->live_nodes() * 2);
2159 // Mark nodes as address_visited if they are inputs to an address expression
2160 VectorSet address_visited;
2161 mstack.push(n, Visit); // Don't need to pre-visit root node
2162 while (mstack.is_nonempty()) {
2163 n = mstack.node(); // Leave node on stack
2164 Node_State nstate = mstack.state();
2165 uint nop = n->Opcode();
2166 if (nstate == Pre_Visit) {
2167 if (address_visited.test(n->_idx)) { // Visited in address already?
2168 // Flag as visited and shared now.
2169 set_visited(n);
2170 }
2171 if (is_visited(n)) { // Visited already?
2172 // Node is shared and has no reason to clone. Flag it as shared.
2173 // This causes it to match into a register for the sharing.
2174 set_shared(n); // Flag as shared and
2175 if (n->is_DecodeNarrowPtr()) {
2176 // Oop field/array element loads must be shared but since
2177 // they are shared through a DecodeN they may appear to have
2178 // a single use so force sharing here.
2179 set_shared(n->in(1));
2180 }
2181 mstack.pop(); // remove node from stack
2182 continue;
2183 }
2184 nstate = Visit; // Not already visited; so visit now
2185 }
2186 if (nstate == Visit) {
2187 mstack.set_state(Post_Visit);
2188 set_visited(n); // Flag as visited now
2189 bool mem_op = false;
2190 int mem_addr_idx = MemNode::Address;
2191 if (find_shared_visit(mstack, n, nop, mem_op, mem_addr_idx)) {
2192 continue;
2193 }
2194 for (int i = n->len() - 1; i >= 0; --i) { // For my children
2195 Node* m = n->in(i); // Get ith input
2196 if (m == nullptr) {
2197 continue; // Ignore nulls
2198 }
2199 if (clone_node(n, m, mstack)) {
2200 continue;
2201 }
2202
2203 // Clone addressing expressions as they are "free" in memory access instructions
2204 if (mem_op && i == mem_addr_idx && m->is_AddP() &&
2205 // When there are other uses besides address expressions
2206 // put it on stack and mark as shared.
2207 !is_visited(m)) {
2208 // Some inputs for address expression are not put on stack
2209 // to avoid marking them as shared and forcing them into register
2210 // if they are used only in address expressions.
2211 // But they should be marked as shared if there are other uses
2212 // besides address expressions.
2213
2214 if (pd_clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2215 continue;
2216 }
2217 } // if( mem_op &&
2218 mstack.push(m, Pre_Visit);
2219 } // for(int i = ...)
2220 }
2221 else if (nstate == Alt_Post_Visit) {
2222 mstack.pop(); // Remove node from stack
2223 // We cannot remove the Cmp input from the Bool here, as the Bool may be
2224 // shared and all users of the Bool need to move the Cmp in parallel.
2225 // This leaves both the Bool and the If pointing at the Cmp. To
2226 // prevent the Matcher from trying to Match the Cmp along both paths
2227 // BoolNode::match_edge always returns a zero.
2228
2229 // We reorder the Op_If in a pre-order manner, so we can visit without
2230 // accidentally sharing the Cmp (the Bool and the If make 2 users).
2231 n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2232 }
2233 else if (nstate == Post_Visit) {
2234 mstack.pop(); // Remove node from stack
2235
2236 // Now hack a few special opcodes
2237 uint opcode = n->Opcode();
2238 bool gc_handled = BarrierSet::barrier_set()->barrier_set_c2()->matcher_find_shared_post_visit(this, n, opcode);
2239 if (!gc_handled) {
2240 find_shared_post_visit(n, opcode);
2241 }
2242 }
2243 else {
2244 ShouldNotReachHere();
2245 }
2246 } // end of while (mstack.is_nonempty())
2247 }
2248
2249 bool Matcher::find_shared_visit(MStack& mstack, Node* n, uint opcode, bool& mem_op, int& mem_addr_idx) {
2250 switch(opcode) { // Handle some opcodes special
2251 case Op_Phi: // Treat Phis as shared roots
2252 case Op_Parm:
2253 case Op_Proj: // All handled specially during matching
2254 case Op_SafePointScalarObject:
2255 set_shared(n);
2256 set_dontcare(n);
2257 break;
2258 case Op_If:
2259 case Op_CountedLoopEnd:
2260 mstack.set_state(Alt_Post_Visit); // Alternative way
2261 // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)). Helps
2262 // with matching cmp/branch in 1 instruction. The Matcher needs the
2263 // Bool and CmpX side-by-side, because it can only get at constants
2264 // that are at the leaves of Match trees, and the Bool's condition acts
2265 // as a constant here.
2266 mstack.push(n->in(1), Visit); // Clone the Bool
2267 mstack.push(n->in(0), Pre_Visit); // Visit control input
2268 return true; // while (mstack.is_nonempty())
2269 case Op_ConvI2D: // These forms efficiently match with a prior
2270 case Op_ConvI2F: // Load but not a following Store
2271 if( n->in(1)->is_Load() && // Prior load
2272 n->outcnt() == 1 && // Not already shared
2273 n->unique_out()->is_Store() ) // Following store
2274 set_shared(n); // Force it to be a root
2275 break;
2276 case Op_ReverseBytesI:
2277 case Op_ReverseBytesL:
2278 if( n->in(1)->is_Load() && // Prior load
2279 n->outcnt() == 1 ) // Not already shared
2280 set_shared(n); // Force it to be a root
2281 break;
2282 case Op_BoxLock: // Can't match until we get stack-regs in ADLC
2283 case Op_IfFalse:
2284 case Op_IfTrue:
2285 case Op_MachProj:
2286 case Op_MergeMem:
2287 case Op_Catch:
2288 case Op_CatchProj:
2289 case Op_CProj:
2290 case Op_JumpProj:
2291 case Op_JProj:
2292 case Op_NeverBranch:
2293 set_dontcare(n);
2294 break;
2295 case Op_Jump:
2296 mstack.push(n->in(1), Pre_Visit); // Switch Value (could be shared)
2297 mstack.push(n->in(0), Pre_Visit); // Visit Control input
2298 return true; // while (mstack.is_nonempty())
2299 case Op_StrComp:
2300 case Op_StrEquals:
2301 case Op_StrIndexOf:
2302 case Op_StrIndexOfChar:
2303 case Op_AryEq:
2304 case Op_VectorizedHashCode:
2305 case Op_CountPositives:
2306 case Op_StrInflatedCopy:
2307 case Op_StrCompressedCopy:
2308 case Op_EncodeISOArray:
2309 case Op_FmaD:
2310 case Op_FmaF:
2311 case Op_FmaVD:
2312 case Op_FmaVF:
2313 case Op_MacroLogicV:
2314 case Op_VectorCmpMasked:
2315 case Op_CompressV:
2316 case Op_CompressM:
2317 case Op_ExpandV:
2318 case Op_VectorLoadMask:
2319 set_shared(n); // Force result into register (it will be anyways)
2320 break;
2321 case Op_ConP: { // Convert pointers above the centerline to NUL
2322 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2323 const TypePtr* tp = tn->type()->is_ptr();
2324 if (tp->_ptr == TypePtr::AnyNull) {
2325 tn->set_type(TypePtr::NULL_PTR);
2326 }
2327 break;
2328 }
2329 case Op_ConN: { // Convert narrow pointers above the centerline to NUL
2330 TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2331 const TypePtr* tp = tn->type()->make_ptr();
2332 if (tp && tp->_ptr == TypePtr::AnyNull) {
2333 tn->set_type(TypeNarrowOop::NULL_PTR);
2334 }
2335 break;
2336 }
2337 case Op_Binary: // These are introduced in the Post_Visit state.
2338 ShouldNotReachHere();
2339 break;
2340 case Op_ClearArray:
2341 case Op_SafePoint:
2342 mem_op = true;
2343 break;
2344 default:
2345 if( n->is_Store() ) {
2346 // Do match stores, despite no ideal reg
2347 mem_op = true;
2348 break;
2349 }
2350 if( n->is_Mem() ) { // Loads and LoadStores
2351 mem_op = true;
2352 // Loads must be root of match tree due to prior load conflict
2353 if( C->subsume_loads() == false )
2354 set_shared(n);
2355 }
2356 // Fall into default case
2357 if( !n->ideal_reg() )
2358 set_dontcare(n); // Unmatchable Nodes
2359 } // end_switch
2360 return false;
2361 }
2362
2363 void Matcher::find_shared_post_visit(Node* n, uint opcode) {
2364 if (n->is_predicated_vector()) {
2365 // Restructure into binary trees for Matching.
2366 if (n->req() == 4) {
2367 n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2368 n->set_req(2, n->in(3));
2369 n->del_req(3);
2370 } else if (n->req() == 5) {
2371 n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2372 n->set_req(2, new BinaryNode(n->in(3), n->in(4)));
2373 n->del_req(4);
2374 n->del_req(3);
2375 } else if (n->req() == 6) {
2376 Node* b3 = new BinaryNode(n->in(4), n->in(5));
2377 Node* b2 = new BinaryNode(n->in(3), b3);
2378 Node* b1 = new BinaryNode(n->in(2), b2);
2379 n->set_req(2, b1);
2380 n->del_req(5);
2381 n->del_req(4);
2382 n->del_req(3);
2383 }
2384 return;
2385 }
2386
2387 switch(opcode) { // Handle some opcodes special
2388 case Op_CompareAndExchangeB:
2389 case Op_CompareAndExchangeS:
2390 case Op_CompareAndExchangeI:
2391 case Op_CompareAndExchangeL:
2392 case Op_CompareAndExchangeP:
2393 case Op_CompareAndExchangeN:
2394 case Op_WeakCompareAndSwapB:
2395 case Op_WeakCompareAndSwapS:
2396 case Op_WeakCompareAndSwapI:
2397 case Op_WeakCompareAndSwapL:
2398 case Op_WeakCompareAndSwapP:
2399 case Op_WeakCompareAndSwapN:
2400 case Op_CompareAndSwapB:
2401 case Op_CompareAndSwapS:
2402 case Op_CompareAndSwapI:
2403 case Op_CompareAndSwapL:
2404 case Op_CompareAndSwapP:
2405 case Op_CompareAndSwapN: { // Convert trinary to binary-tree
2406 Node* newval = n->in(MemNode::ValueIn);
2407 Node* oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2408 Node* pair = new BinaryNode(oldval, newval);
2409 n->set_req(MemNode::ValueIn, pair);
2410 n->del_req(LoadStoreConditionalNode::ExpectedIn);
2411 break;
2412 }
2413 case Op_CMoveD: // Convert trinary to binary-tree
2414 case Op_CMoveF:
2415 case Op_CMoveI:
2416 case Op_CMoveL:
2417 case Op_CMoveN:
2418 case Op_CMoveP: {
2419 // Restructure into a binary tree for Matching. It's possible that
2420 // we could move this code up next to the graph reshaping for IfNodes
2421 // or vice-versa, but I do not want to debug this for Ladybird.
2422 // 10/2/2000 CNC.
2423 Node* pair1 = new BinaryNode(n->in(1), n->in(1)->in(1));
2424 n->set_req(1, pair1);
2425 Node* pair2 = new BinaryNode(n->in(2), n->in(3));
2426 n->set_req(2, pair2);
2427 n->del_req(3);
2428 break;
2429 }
2430 case Op_MacroLogicV: {
2431 Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2432 Node* pair2 = new BinaryNode(n->in(3), n->in(4));
2433 n->set_req(1, pair1);
2434 n->set_req(2, pair2);
2435 n->del_req(4);
2436 n->del_req(3);
2437 break;
2438 }
2439 case Op_StoreVectorMasked: {
2440 Node* pair = new BinaryNode(n->in(3), n->in(4));
2441 n->set_req(3, pair);
2442 n->del_req(4);
2443 break;
2444 }
2445 case Op_LoopLimit: {
2446 Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2447 n->set_req(1, pair1);
2448 n->set_req(2, n->in(3));
2449 n->del_req(3);
2450 break;
2451 }
2452 case Op_StrEquals:
2453 case Op_StrIndexOfChar: {
2454 Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2455 n->set_req(2, pair1);
2456 n->set_req(3, n->in(4));
2457 n->del_req(4);
2458 break;
2459 }
2460 case Op_StrComp:
2461 case Op_StrIndexOf:
2462 case Op_VectorizedHashCode: {
2463 Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2464 n->set_req(2, pair1);
2465 Node* pair2 = new BinaryNode(n->in(4),n->in(5));
2466 n->set_req(3, pair2);
2467 n->del_req(5);
2468 n->del_req(4);
2469 break;
2470 }
2471 case Op_EncodeISOArray:
2472 case Op_StrCompressedCopy:
2473 case Op_StrInflatedCopy: {
2474 // Restructure into a binary tree for Matching.
2475 Node* pair = new BinaryNode(n->in(3), n->in(4));
2476 n->set_req(3, pair);
2477 n->del_req(4);
2478 break;
2479 }
2480 case Op_FmaD:
2481 case Op_FmaF:
2482 case Op_FmaVD:
2483 case Op_FmaVF: {
2484 // Restructure into a binary tree for Matching.
2485 Node* pair = new BinaryNode(n->in(1), n->in(2));
2486 n->set_req(2, pair);
2487 n->set_req(1, n->in(3));
2488 n->del_req(3);
2489 break;
2490 }
2491 case Op_MulAddS2I: {
2492 Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2493 Node* pair2 = new BinaryNode(n->in(3), n->in(4));
2494 n->set_req(1, pair1);
2495 n->set_req(2, pair2);
2496 n->del_req(4);
2497 n->del_req(3);
2498 break;
2499 }
2500 case Op_ClearArray: {
2501 Node* pair = new BinaryNode(n->in(2), n->in(3));
2502 n->set_req(2, pair);
2503 n->set_req(3, n->in(4));
2504 n->del_req(4);
2505 break;
2506 }
2507 case Op_VectorCmpMasked:
2508 case Op_CopySignD:
2509 case Op_SignumVF:
2510 case Op_SignumVD:
2511 case Op_SignumF:
2512 case Op_SignumD: {
2513 Node* pair = new BinaryNode(n->in(2), n->in(3));
2514 n->set_req(2, pair);
2515 n->del_req(3);
2516 break;
2517 }
2518 case Op_VectorBlend:
2519 case Op_VectorInsert: {
2520 Node* pair = new BinaryNode(n->in(1), n->in(2));
2521 n->set_req(1, pair);
2522 n->set_req(2, n->in(3));
2523 n->del_req(3);
2524 break;
2525 }
2526 case Op_LoadVectorGatherMasked:
2527 case Op_StoreVectorScatter: {
2528 Node* pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2529 n->set_req(MemNode::ValueIn, pair);
2530 n->del_req(MemNode::ValueIn+1);
2531 break;
2532 }
2533 case Op_StoreVectorScatterMasked: {
2534 Node* pair = new BinaryNode(n->in(MemNode::ValueIn+1), n->in(MemNode::ValueIn+2));
2535 n->set_req(MemNode::ValueIn+1, pair);
2536 n->del_req(MemNode::ValueIn+2);
2537 pair = new BinaryNode(n->in(MemNode::ValueIn), n->in(MemNode::ValueIn+1));
2538 n->set_req(MemNode::ValueIn, pair);
2539 n->del_req(MemNode::ValueIn+1);
2540 break;
2541 }
2542 case Op_VectorMaskCmp: {
2543 n->set_req(1, new BinaryNode(n->in(1), n->in(2)));
2544 n->set_req(2, n->in(3));
2545 n->del_req(3);
2546 break;
2547 }
2548 default:
2549 break;
2550 }
2551 }
2552
2553 #ifndef PRODUCT
2554 void Matcher::record_new2old(Node* newn, Node* old) {
2555 _new2old_map.map(newn->_idx, old);
2556 if (!_reused.test_set(old->_igv_idx)) {
2557 // Reuse the Ideal-level IGV identifier so that the node can be tracked
2558 // across matching. If there are multiple machine nodes expanded from the
2559 // same Ideal node, only one will reuse its IGV identifier.
2560 newn->_igv_idx = old->_igv_idx;
2561 }
2562 }
2563
2564 // machine-independent root to machine-dependent root
2565 void Matcher::dump_old2new_map() {
2566 _old2new_map.dump();
2567 }
2568 #endif // !PRODUCT
2569
2570 //---------------------------collect_null_checks-------------------------------
2571 // Find null checks in the ideal graph; write a machine-specific node for
2572 // it. Used by later implicit-null-check handling. Actually collects
2573 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2574 // value being tested.
2575 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2576 Node *iff = proj->in(0);
2577 if( iff->Opcode() == Op_If ) {
2578 // During matching If's have Bool & Cmp side-by-side
2579 BoolNode *b = iff->in(1)->as_Bool();
2580 Node *cmp = iff->in(2);
2581 int opc = cmp->Opcode();
2582 if (opc != Op_CmpP && opc != Op_CmpN) return;
2583
2584 const Type* ct = cmp->in(2)->bottom_type();
2585 if (ct == TypePtr::NULL_PTR ||
2586 (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2587
2588 bool push_it = false;
2589 if( proj->Opcode() == Op_IfTrue ) {
2590 #ifndef PRODUCT
2591 extern uint all_null_checks_found;
2592 all_null_checks_found++;
2593 #endif
2594 if( b->_test._test == BoolTest::ne ) {
2595 push_it = true;
2596 }
2597 } else {
2598 assert( proj->Opcode() == Op_IfFalse, "" );
2599 if( b->_test._test == BoolTest::eq ) {
2600 push_it = true;
2601 }
2602 }
2603 if( push_it ) {
2604 _null_check_tests.push(proj);
2605 Node* val = cmp->in(1);
2606 #ifdef _LP64
2607 if (val->bottom_type()->isa_narrowoop() &&
2608 !Matcher::narrow_oop_use_complex_address()) {
2609 //
2610 // Look for DecodeN node which should be pinned to orig_proj.
2611 // On platforms (Sparc) which can not handle 2 adds
2612 // in addressing mode we have to keep a DecodeN node and
2613 // use it to do implicit null check in address.
2614 //
2615 // DecodeN node was pinned to non-null path (orig_proj) during
2616 // CastPP transformation in final_graph_reshaping_impl().
2617 //
2618 uint cnt = orig_proj->outcnt();
2619 for (uint i = 0; i < orig_proj->outcnt(); i++) {
2620 Node* d = orig_proj->raw_out(i);
2621 if (d->is_DecodeN() && d->in(1) == val) {
2622 val = d;
2623 val->set_req(0, nullptr); // Unpin now.
2624 // Mark this as special case to distinguish from
2625 // a regular case: CmpP(DecodeN, null).
2626 val = (Node*)(((intptr_t)val) | 1);
2627 break;
2628 }
2629 }
2630 }
2631 #endif
2632 _null_check_tests.push(val);
2633 }
2634 }
2635 }
2636 }
2637
2638 //---------------------------validate_null_checks------------------------------
2639 // Its possible that the value being null checked is not the root of a match
2640 // tree. If so, I cannot use the value in an implicit null check.
2641 void Matcher::validate_null_checks( ) {
2642 uint cnt = _null_check_tests.size();
2643 for( uint i=0; i < cnt; i+=2 ) {
2644 Node *test = _null_check_tests[i];
2645 Node *val = _null_check_tests[i+1];
2646 bool is_decoden = ((intptr_t)val) & 1;
2647 val = (Node*)(((intptr_t)val) & ~1);
2648 if (has_new_node(val)) {
2649 Node* new_val = new_node(val);
2650 if (is_decoden) {
2651 assert(val->is_DecodeNarrowPtr() && val->in(0) == nullptr, "sanity");
2652 // Note: new_val may have a control edge if
2653 // the original ideal node DecodeN was matched before
2654 // it was unpinned in Matcher::collect_null_checks().
2655 // Unpin the mach node and mark it.
2656 new_val->set_req(0, nullptr);
2657 new_val = (Node*)(((intptr_t)new_val) | 1);
2658 }
2659 // Is a match-tree root, so replace with the matched value
2660 _null_check_tests.map(i+1, new_val);
2661 } else {
2662 // Yank from candidate list
2663 _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2664 _null_check_tests.map(i,_null_check_tests[--cnt]);
2665 _null_check_tests.pop();
2666 _null_check_tests.pop();
2667 i-=2;
2668 }
2669 }
2670 }
2671
2672 bool Matcher::gen_narrow_oop_implicit_null_checks() {
2673 // Advice matcher to perform null checks on the narrow oop side.
2674 // Implicit checks are not possible on the uncompressed oop side anyway
2675 // (at least not for read accesses).
2676 // Performs significantly better (especially on Power 6).
2677 if (!os::zero_page_read_protected()) {
2678 return true;
2679 }
2680 return CompressedOops::use_implicit_null_checks() &&
2681 (narrow_oop_use_complex_address() ||
2682 CompressedOops::base() != nullptr);
2683 }
2684
2685 // Compute RegMask for an ideal register.
2686 const RegMask* Matcher::regmask_for_ideal_register(uint ideal_reg, Node* ret) {
2687 const Type* t = Type::mreg2type[ideal_reg];
2688 if (t == nullptr) {
2689 assert(ideal_reg >= Op_VecA && ideal_reg <= Op_VecZ, "not a vector: %d", ideal_reg);
2690 return nullptr; // not supported
2691 }
2692 Node* fp = ret->in(TypeFunc::FramePtr);
2693 Node* mem = ret->in(TypeFunc::Memory);
2694 const TypePtr* atp = TypePtr::BOTTOM;
2695 MemNode::MemOrd mo = MemNode::unordered;
2696
2697 Node* spill;
2698 switch (ideal_reg) {
2699 case Op_RegN: spill = new LoadNNode(nullptr, mem, fp, atp, t->is_narrowoop(), mo); break;
2700 case Op_RegI: spill = new LoadINode(nullptr, mem, fp, atp, t->is_int(), mo); break;
2701 case Op_RegP: spill = new LoadPNode(nullptr, mem, fp, atp, t->is_ptr(), mo); break;
2702 case Op_RegF: spill = new LoadFNode(nullptr, mem, fp, atp, t, mo); break;
2703 case Op_RegD: spill = new LoadDNode(nullptr, mem, fp, atp, t, mo); break;
2704 case Op_RegL: spill = new LoadLNode(nullptr, mem, fp, atp, t->is_long(), mo); break;
2705
2706 case Op_VecA: // fall-through
2707 case Op_VecS: // fall-through
2708 case Op_VecD: // fall-through
2709 case Op_VecX: // fall-through
2710 case Op_VecY: // fall-through
2711 case Op_VecZ: spill = new LoadVectorNode(nullptr, mem, fp, atp, t->is_vect()); break;
2712 case Op_RegVectMask: return Matcher::predicate_reg_mask();
2713
2714 default: ShouldNotReachHere();
2715 }
2716 MachNode* mspill = match_tree(spill);
2717 assert(mspill != nullptr, "matching failed: %d", ideal_reg);
2718 // Handle generic vector operand case
2719 if (Matcher::supports_generic_vector_operands && t->isa_vect()) {
2720 specialize_mach_node(mspill);
2721 }
2722 return &mspill->out_RegMask();
2723 }
2724
2725 // Process Mach IR right after selection phase is over.
2726 void Matcher::do_postselect_cleanup() {
2727 if (supports_generic_vector_operands) {
2728 specialize_generic_vector_operands();
2729 if (C->failing()) return;
2730 }
2731 }
2732
2733 //----------------------------------------------------------------------
2734 // Generic machine operands elision.
2735 //----------------------------------------------------------------------
2736
2737 // Compute concrete vector operand for a generic TEMP vector mach node based on its user info.
2738 void Matcher::specialize_temp_node(MachTempNode* tmp, MachNode* use, uint idx) {
2739 assert(use->in(idx) == tmp, "not a user");
2740 assert(!Matcher::is_generic_vector(use->_opnds[0]), "use not processed yet");
2741
2742 if ((uint)idx == use->two_adr()) { // DEF_TEMP case
2743 tmp->_opnds[0] = use->_opnds[0]->clone();
2744 } else {
2745 uint ideal_vreg = vector_ideal_reg(C->max_vector_size());
2746 tmp->_opnds[0] = Matcher::pd_specialize_generic_vector_operand(tmp->_opnds[0], ideal_vreg, true /*is_temp*/);
2747 }
2748 }
2749
2750 // Compute concrete vector operand for a generic DEF/USE vector operand (of mach node m at index idx).
2751 MachOper* Matcher::specialize_vector_operand(MachNode* m, uint opnd_idx) {
2752 assert(Matcher::is_generic_vector(m->_opnds[opnd_idx]), "repeated updates");
2753 Node* def = nullptr;
2754 if (opnd_idx == 0) { // DEF
2755 def = m; // use mach node itself to compute vector operand type
2756 } else {
2757 int base_idx = m->operand_index(opnd_idx);
2758 def = m->in(base_idx);
2759 if (def->is_Mach()) {
2760 if (def->is_MachTemp() && Matcher::is_generic_vector(def->as_Mach()->_opnds[0])) {
2761 specialize_temp_node(def->as_MachTemp(), m, base_idx); // MachTemp node use site
2762 } else if (is_reg2reg_move(def->as_Mach())) {
2763 def = def->in(1); // skip over generic reg-to-reg moves
2764 }
2765 }
2766 }
2767 assert(def->bottom_type()->isa_vect(), "not a vector");
2768 uint ideal_vreg = def->bottom_type()->ideal_reg();
2769 return Matcher::pd_specialize_generic_vector_operand(m->_opnds[opnd_idx], ideal_vreg, false /*is_temp*/);
2770 }
2771
2772 void Matcher::specialize_mach_node(MachNode* m) {
2773 assert(!m->is_MachTemp(), "processed along with its user");
2774 // For generic use operands pull specific register class operands from
2775 // its def instruction's output operand (def operand).
2776 for (uint i = 0; i < m->num_opnds(); i++) {
2777 if (Matcher::is_generic_vector(m->_opnds[i])) {
2778 m->_opnds[i] = specialize_vector_operand(m, i);
2779 }
2780 }
2781 }
2782
2783 // Replace generic vector operands with concrete vector operands and eliminate generic reg-to-reg moves from the graph.
2784 void Matcher::specialize_generic_vector_operands() {
2785 assert(supports_generic_vector_operands, "sanity");
2786 ResourceMark rm;
2787
2788 // Replace generic vector operands (vec/legVec) with concrete ones (vec[SDXYZ]/legVec[SDXYZ])
2789 // and remove reg-to-reg vector moves (MoveVec2Leg and MoveLeg2Vec).
2790 Unique_Node_List live_nodes;
2791 C->identify_useful_nodes(live_nodes);
2792
2793 while (live_nodes.size() > 0) {
2794 MachNode* m = live_nodes.pop()->isa_Mach();
2795 if (m != nullptr) {
2796 if (Matcher::is_reg2reg_move(m)) {
2797 // Register allocator properly handles vec <=> leg moves using register masks.
2798 int opnd_idx = m->operand_index(1);
2799 Node* def = m->in(opnd_idx);
2800 m->subsume_by(def, C);
2801 } else if (m->is_MachTemp()) {
2802 // process MachTemp nodes at use site (see Matcher::specialize_vector_operand)
2803 } else {
2804 specialize_mach_node(m);
2805 }
2806 }
2807 }
2808 }
2809
2810 uint Matcher::vector_length(const Node* n) {
2811 const TypeVect* vt = n->bottom_type()->is_vect();
2812 return vt->length();
2813 }
2814
2815 uint Matcher::vector_length(const MachNode* use, const MachOper* opnd) {
2816 int def_idx = use->operand_index(opnd);
2817 Node* def = use->in(def_idx);
2818 return def->bottom_type()->is_vect()->length();
2819 }
2820
2821 uint Matcher::vector_length_in_bytes(const Node* n) {
2822 const TypeVect* vt = n->bottom_type()->is_vect();
2823 return vt->length_in_bytes();
2824 }
2825
2826 uint Matcher::vector_length_in_bytes(const MachNode* use, const MachOper* opnd) {
2827 uint def_idx = use->operand_index(opnd);
2828 Node* def = use->in(def_idx);
2829 return def->bottom_type()->is_vect()->length_in_bytes();
2830 }
2831
2832 BasicType Matcher::vector_element_basic_type(const Node* n) {
2833 const TypeVect* vt = n->bottom_type()->is_vect();
2834 return vt->element_basic_type();
2835 }
2836
2837 BasicType Matcher::vector_element_basic_type(const MachNode* use, const MachOper* opnd) {
2838 int def_idx = use->operand_index(opnd);
2839 Node* def = use->in(def_idx);
2840 return def->bottom_type()->is_vect()->element_basic_type();
2841 }
2842
2843 #ifdef ASSERT
2844 bool Matcher::verify_after_postselect_cleanup() {
2845 assert(!C->failing(), "sanity");
2846 if (supports_generic_vector_operands) {
2847 Unique_Node_List useful;
2848 C->identify_useful_nodes(useful);
2849 for (uint i = 0; i < useful.size(); i++) {
2850 MachNode* m = useful.at(i)->isa_Mach();
2851 if (m != nullptr) {
2852 assert(!Matcher::is_reg2reg_move(m), "no MoveVec nodes allowed");
2853 for (uint j = 0; j < m->num_opnds(); j++) {
2854 assert(!Matcher::is_generic_vector(m->_opnds[j]), "no generic vector operands allowed");
2855 }
2856 }
2857 }
2858 }
2859 return true;
2860 }
2861 #endif // ASSERT
2862
2863 // Used by the DFA in dfa_xxx.cpp. Check for a following barrier or
2864 // atomic instruction acting as a store_load barrier without any
2865 // intervening volatile load, and thus we don't need a barrier here.
2866 // We retain the Node to act as a compiler ordering barrier.
2867 bool Matcher::post_store_load_barrier(const Node* vmb) {
2868 Compile* C = Compile::current();
2869 assert(vmb->is_MemBar(), "");
2870 assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2871 const MemBarNode* membar = vmb->as_MemBar();
2872
2873 // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2874 Node* ctrl = nullptr;
2875 for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2876 Node* p = membar->fast_out(i);
2877 assert(p->is_Proj(), "only projections here");
2878 if ((p->as_Proj()->_con == TypeFunc::Control) &&
2879 !C->node_arena()->contains(p)) { // Unmatched old-space only
2880 ctrl = p;
2881 break;
2882 }
2883 }
2884 assert((ctrl != nullptr), "missing control projection");
2885
2886 for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2887 Node *x = ctrl->fast_out(j);
2888 int xop = x->Opcode();
2889
2890 // We don't need current barrier if we see another or a lock
2891 // before seeing volatile load.
2892 //
2893 // Op_Fastunlock previously appeared in the Op_* list below.
2894 // With the advent of 1-0 lock operations we're no longer guaranteed
2895 // that a monitor exit operation contains a serializing instruction.
2896
2897 if (xop == Op_MemBarVolatile ||
2898 xop == Op_CompareAndExchangeB ||
2899 xop == Op_CompareAndExchangeS ||
2900 xop == Op_CompareAndExchangeI ||
2901 xop == Op_CompareAndExchangeL ||
2902 xop == Op_CompareAndExchangeP ||
2903 xop == Op_CompareAndExchangeN ||
2904 xop == Op_WeakCompareAndSwapB ||
2905 xop == Op_WeakCompareAndSwapS ||
2906 xop == Op_WeakCompareAndSwapL ||
2907 xop == Op_WeakCompareAndSwapP ||
2908 xop == Op_WeakCompareAndSwapN ||
2909 xop == Op_WeakCompareAndSwapI ||
2910 xop == Op_CompareAndSwapB ||
2911 xop == Op_CompareAndSwapS ||
2912 xop == Op_CompareAndSwapL ||
2913 xop == Op_CompareAndSwapP ||
2914 xop == Op_CompareAndSwapN ||
2915 xop == Op_CompareAndSwapI ||
2916 BarrierSet::barrier_set()->barrier_set_c2()->matcher_is_store_load_barrier(x, xop)) {
2917 return true;
2918 }
2919
2920 // Op_FastLock previously appeared in the Op_* list above.
2921 if (xop == Op_FastLock) {
2922 return true;
2923 }
2924
2925 if (x->is_MemBar()) {
2926 // We must retain this membar if there is an upcoming volatile
2927 // load, which will be followed by acquire membar.
2928 if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2929 return false;
2930 } else {
2931 // For other kinds of barriers, check by pretending we
2932 // are them, and seeing if we can be removed.
2933 return post_store_load_barrier(x->as_MemBar());
2934 }
2935 }
2936
2937 // probably not necessary to check for these
2938 if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2939 return false;
2940 }
2941 }
2942 return false;
2943 }
2944
2945 // Check whether node n is a branch to an uncommon trap that we could
2946 // optimize as test with very high branch costs in case of going to
2947 // the uncommon trap. The code must be able to be recompiled to use
2948 // a cheaper test.
2949 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2950 // Don't do it for natives, adapters, or runtime stubs
2951 Compile *C = Compile::current();
2952 if (!C->is_method_compilation()) return false;
2953
2954 assert(n->is_If(), "You should only call this on if nodes.");
2955 IfNode *ifn = n->as_If();
2956
2957 Node *ifFalse = nullptr;
2958 for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2959 if (ifn->fast_out(i)->is_IfFalse()) {
2960 ifFalse = ifn->fast_out(i);
2961 break;
2962 }
2963 }
2964 assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2965
2966 Node *reg = ifFalse;
2967 int cnt = 4; // We must protect against cycles. Limit to 4 iterations.
2968 // Alternatively use visited set? Seems too expensive.
2969 while (reg != nullptr && cnt > 0) {
2970 CallNode *call = nullptr;
2971 RegionNode *nxt_reg = nullptr;
2972 for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2973 Node *o = reg->fast_out(i);
2974 if (o->is_Call()) {
2975 call = o->as_Call();
2976 }
2977 if (o->is_Region()) {
2978 nxt_reg = o->as_Region();
2979 }
2980 }
2981
2982 if (call &&
2983 call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2984 const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2985 if (trtype->isa_int() && trtype->is_int()->is_con()) {
2986 jint tr_con = trtype->is_int()->get_con();
2987 Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2988 Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2989 assert((int)reason < (int)BitsPerInt, "recode bit map");
2990
2991 if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2992 && action != Deoptimization::Action_none) {
2993 // This uncommon trap is sure to recompile, eventually.
2994 // When that happens, C->too_many_traps will prevent
2995 // this transformation from happening again.
2996 return true;
2997 }
2998 }
2999 }
3000
3001 reg = nxt_reg;
3002 cnt--;
3003 }
3004
3005 return false;
3006 }
3007
3008 //=============================================================================
3009 //---------------------------State---------------------------------------------
3010 State::State(void) : _rule() {
3011 #ifdef ASSERT
3012 _id = 0;
3013 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
3014 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
3015 #endif
3016 }
3017
3018 #ifdef ASSERT
3019 State::~State() {
3020 _id = 99;
3021 _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
3022 _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
3023 memset(_cost, -3, sizeof(_cost));
3024 memset(_rule, -3, sizeof(_rule));
3025 }
3026 #endif
3027
3028 #ifndef PRODUCT
3029 //---------------------------dump----------------------------------------------
3030 void State::dump() {
3031 tty->print("\n");
3032 dump(0);
3033 }
3034
3035 void State::dump(int depth) {
3036 for (int j = 0; j < depth; j++) {
3037 tty->print(" ");
3038 }
3039 tty->print("--N: ");
3040 _leaf->dump();
3041 uint i;
3042 for (i = 0; i < _LAST_MACH_OPER; i++) {
3043 // Check for valid entry
3044 if (valid(i)) {
3045 for (int j = 0; j < depth; j++) {
3046 tty->print(" ");
3047 }
3048 assert(cost(i) != max_juint, "cost must be a valid value");
3049 assert(rule(i) < _last_Mach_Node, "rule[i] must be valid rule");
3050 tty->print_cr("%s %d %s",
3051 ruleName[i], cost(i), ruleName[rule(i)] );
3052 }
3053 }
3054 tty->cr();
3055
3056 for (i = 0; i < 2; i++) {
3057 if (_kids[i]) {
3058 _kids[i]->dump(depth + 1);
3059 }
3060 }
3061 }
3062 #endif