1 /*
   2  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "gc/shared/barrierSet.hpp"
  27 #include "gc/shared/c2/barrierSetC2.hpp"
  28 #include "memory/allocation.inline.hpp"
  29 #include "memory/resourceArea.hpp"
  30 #include "oops/compressedOops.hpp"
  31 #include "opto/ad.hpp"
  32 #include "opto/addnode.hpp"
  33 #include "opto/callnode.hpp"
  34 #include "opto/idealGraphPrinter.hpp"
  35 #include "opto/matcher.hpp"
  36 #include "opto/memnode.hpp"
  37 #include "opto/movenode.hpp"
  38 #include "opto/opcodes.hpp"
  39 #include "opto/regmask.hpp"
  40 #include "opto/rootnode.hpp"
  41 #include "opto/runtime.hpp"
  42 #include "opto/type.hpp"
  43 #include "opto/vectornode.hpp"
  44 #include "runtime/os.hpp"
  45 #include "runtime/sharedRuntime.hpp"
  46 #include "utilities/align.hpp"
  47 
  48 OptoReg::Name OptoReg::c_frame_pointer;
  49 
  50 const RegMask *Matcher::idealreg2regmask[_last_machine_leaf];
  51 RegMask Matcher::mreg2regmask[_last_Mach_Reg];
  52 RegMask Matcher::STACK_ONLY_mask;
  53 RegMask Matcher::c_frame_ptr_mask;
  54 const uint Matcher::_begin_rematerialize = _BEGIN_REMATERIALIZE;
  55 const uint Matcher::_end_rematerialize   = _END_REMATERIALIZE;
  56 
  57 //---------------------------Matcher-------------------------------------------
  58 Matcher::Matcher()
  59 : PhaseTransform( Phase::Ins_Select ),
  60   _states_arena(Chunk::medium_size, mtCompiler),
  61   _visited(&_states_arena),
  62   _shared(&_states_arena),
  63   _dontcare(&_states_arena),
  64   _reduceOp(reduceOp), _leftOp(leftOp), _rightOp(rightOp),
  65   _swallowed(swallowed),
  66   _begin_inst_chain_rule(_BEGIN_INST_CHAIN_RULE),
  67   _end_inst_chain_rule(_END_INST_CHAIN_RULE),
  68   _must_clone(must_clone),
  69   _shared_nodes(C->comp_arena()),
  70 #ifdef ASSERT
  71   _old2new_map(C->comp_arena()),
  72   _new2old_map(C->comp_arena()),
  73 #endif
  74   _allocation_started(false),
  75   _ruleName(ruleName),
  76   _register_save_policy(register_save_policy),
  77   _c_reg_save_policy(c_reg_save_policy),
  78   _register_save_type(register_save_type) {
  79   C->set_matcher(this);
  80 
  81   idealreg2spillmask  [Op_RegI] = NULL;
  82   idealreg2spillmask  [Op_RegN] = NULL;
  83   idealreg2spillmask  [Op_RegL] = NULL;
  84   idealreg2spillmask  [Op_RegF] = NULL;
  85   idealreg2spillmask  [Op_RegD] = NULL;
  86   idealreg2spillmask  [Op_RegP] = NULL;
  87   idealreg2spillmask  [Op_VecS] = NULL;
  88   idealreg2spillmask  [Op_VecD] = NULL;
  89   idealreg2spillmask  [Op_VecX] = NULL;
  90   idealreg2spillmask  [Op_VecY] = NULL;
  91   idealreg2spillmask  [Op_VecZ] = NULL;
  92   idealreg2spillmask  [Op_RegFlags] = NULL;
  93 
  94   idealreg2debugmask  [Op_RegI] = NULL;
  95   idealreg2debugmask  [Op_RegN] = NULL;
  96   idealreg2debugmask  [Op_RegL] = NULL;
  97   idealreg2debugmask  [Op_RegF] = NULL;
  98   idealreg2debugmask  [Op_RegD] = NULL;
  99   idealreg2debugmask  [Op_RegP] = NULL;
 100   idealreg2debugmask  [Op_VecS] = NULL;
 101   idealreg2debugmask  [Op_VecD] = NULL;
 102   idealreg2debugmask  [Op_VecX] = NULL;
 103   idealreg2debugmask  [Op_VecY] = NULL;
 104   idealreg2debugmask  [Op_VecZ] = NULL;
 105   idealreg2debugmask  [Op_RegFlags] = NULL;
 106 
 107   idealreg2mhdebugmask[Op_RegI] = NULL;
 108   idealreg2mhdebugmask[Op_RegN] = NULL;
 109   idealreg2mhdebugmask[Op_RegL] = NULL;
 110   idealreg2mhdebugmask[Op_RegF] = NULL;
 111   idealreg2mhdebugmask[Op_RegD] = NULL;
 112   idealreg2mhdebugmask[Op_RegP] = NULL;
 113   idealreg2mhdebugmask[Op_VecS] = NULL;
 114   idealreg2mhdebugmask[Op_VecD] = NULL;
 115   idealreg2mhdebugmask[Op_VecX] = NULL;
 116   idealreg2mhdebugmask[Op_VecY] = NULL;
 117   idealreg2mhdebugmask[Op_VecZ] = NULL;
 118   idealreg2mhdebugmask[Op_RegFlags] = NULL;
 119 
 120   debug_only(_mem_node = NULL;)   // Ideal memory node consumed by mach node
 121 }
 122 
 123 //------------------------------warp_incoming_stk_arg------------------------
 124 // This warps a VMReg into an OptoReg::Name
 125 OptoReg::Name Matcher::warp_incoming_stk_arg( VMReg reg ) {
 126   OptoReg::Name warped;
 127   if( reg->is_stack() ) {  // Stack slot argument?
 128     warped = OptoReg::add(_old_SP, reg->reg2stack() );
 129     warped = OptoReg::add(warped, C->out_preserve_stack_slots());
 130     if( warped >= _in_arg_limit )
 131       _in_arg_limit = OptoReg::add(warped, 1); // Bump max stack slot seen
 132     if (!RegMask::can_represent_arg(warped)) {
 133       // the compiler cannot represent this method's calling sequence
 134       C->record_method_not_compilable("unsupported incoming calling sequence");
 135       return OptoReg::Bad;
 136     }
 137     return warped;
 138   }
 139   return OptoReg::as_OptoReg(reg);
 140 }
 141 
 142 //---------------------------compute_old_SP------------------------------------
 143 OptoReg::Name Compile::compute_old_SP() {
 144   int fixed    = fixed_slots();
 145   int preserve = in_preserve_stack_slots();
 146   return OptoReg::stack2reg(align_up(fixed + preserve, (int)Matcher::stack_alignment_in_slots()));
 147 }
 148 
 149 
 150 
 151 #ifdef ASSERT
 152 void Matcher::verify_new_nodes_only(Node* xroot) {
 153   // Make sure that the new graph only references new nodes
 154   ResourceMark rm;
 155   Unique_Node_List worklist;
 156   VectorSet visited(Thread::current()->resource_area());
 157   worklist.push(xroot);
 158   while (worklist.size() > 0) {
 159     Node* n = worklist.pop();
 160     visited <<= n->_idx;
 161     assert(C->node_arena()->contains(n), "dead node");
 162     for (uint j = 0; j < n->req(); j++) {
 163       Node* in = n->in(j);
 164       if (in != NULL) {
 165         assert(C->node_arena()->contains(in), "dead node");
 166         if (!visited.test(in->_idx)) {
 167           worklist.push(in);
 168         }
 169       }
 170     }
 171   }
 172 }
 173 #endif
 174 
 175 // Array of RegMask, one per returned values (value type instances can
 176 // be returned as multiple return values, one per field)
 177 RegMask* Matcher::return_values_mask(const TypeTuple *range) {
 178   uint cnt = range->cnt() - TypeFunc::Parms;
 179   if (cnt == 0) {
 180     return NULL;
 181   }
 182   RegMask* mask = NEW_RESOURCE_ARRAY(RegMask, cnt);
 183 
 184   if (!ValueTypeReturnedAsFields) {
 185     // Get ideal-register return type
 186     uint ireg = range->field_at(TypeFunc::Parms)->ideal_reg();
 187     // Get machine return register
 188     OptoRegPair regs = return_value(ireg, false);
 189 
 190     // And mask for same
 191     mask[0].Clear();
 192     mask[0].Insert(regs.first());
 193     if (OptoReg::is_valid(regs.second())) {
 194       mask[0].Insert(regs.second());
 195     }
 196   } else {
 197     BasicType* sig_bt = NEW_RESOURCE_ARRAY(BasicType, cnt);
 198     VMRegPair* vm_parm_regs = NEW_RESOURCE_ARRAY(VMRegPair, cnt);
 199 
 200     for (uint i = 0; i < cnt; i++) {
 201       sig_bt[i] = range->field_at(i+TypeFunc::Parms)->basic_type();
 202     }
 203 
 204     int regs = SharedRuntime::java_return_convention(sig_bt, vm_parm_regs, cnt);
 205     assert(regs > 0, "should have been tested during graph construction");
 206     for (uint i = 0; i < cnt; i++) {
 207       mask[i].Clear();
 208 
 209       OptoReg::Name reg1 = OptoReg::as_OptoReg(vm_parm_regs[i].first());
 210       if (OptoReg::is_valid(reg1)) {
 211         mask[i].Insert(reg1);
 212       }
 213       OptoReg::Name reg2 = OptoReg::as_OptoReg(vm_parm_regs[i].second());
 214       if (OptoReg::is_valid(reg2)) {
 215         mask[i].Insert(reg2);
 216       }
 217     }
 218   }
 219   return mask;
 220 }
 221 
 222 //---------------------------match---------------------------------------------
 223 void Matcher::match( ) {
 224   if( MaxLabelRootDepth < 100 ) { // Too small?
 225     assert(false, "invalid MaxLabelRootDepth, increase it to 100 minimum");
 226     MaxLabelRootDepth = 100;
 227   }
 228   // One-time initialization of some register masks.
 229   init_spill_mask( C->root()->in(1) );
 230   _return_addr_mask = return_addr();
 231 #ifdef _LP64
 232   // Pointers take 2 slots in 64-bit land
 233   _return_addr_mask.Insert(OptoReg::add(return_addr(),1));
 234 #endif
 235 
 236   // Map Java-signature return types into return register-value
 237   // machine registers.
 238   const TypeTuple *range = C->tf()->range_cc();
 239   _return_values_mask = return_values_mask(range);
 240 
 241   // ---------------
 242   // Frame Layout
 243 
 244   // Need the method signature to determine the incoming argument types,
 245   // because the types determine which registers the incoming arguments are
 246   // in, and this affects the matched code.
 247   const TypeTuple *domain = C->tf()->domain_cc();
 248   uint             argcnt = domain->cnt() - TypeFunc::Parms;
 249   BasicType *sig_bt        = NEW_RESOURCE_ARRAY( BasicType, argcnt );
 250   VMRegPair *vm_parm_regs  = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
 251   _parm_regs               = NEW_RESOURCE_ARRAY( OptoRegPair, argcnt );
 252   _calling_convention_mask = NEW_RESOURCE_ARRAY( RegMask, argcnt );
 253   uint i;
 254   for( i = 0; i<argcnt; i++ ) {
 255     sig_bt[i] = domain->field_at(i+TypeFunc::Parms)->basic_type();
 256   }
 257 
 258   // Pass array of ideal registers and length to USER code (from the AD file)
 259   // that will convert this to an array of register numbers.
 260   const StartNode *start = C->start();
 261   start->calling_convention( sig_bt, vm_parm_regs, argcnt );
 262 #ifdef ASSERT
 263   // Sanity check users' calling convention.  Real handy while trying to
 264   // get the initial port correct.
 265   { for (uint i = 0; i<argcnt; i++) {
 266       if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
 267         assert(domain->field_at(i+TypeFunc::Parms)==Type::HALF, "only allowed on halve" );
 268         _parm_regs[i].set_bad();
 269         continue;
 270       }
 271       VMReg parm_reg = vm_parm_regs[i].first();
 272       assert(parm_reg->is_valid(), "invalid arg?");
 273       if (parm_reg->is_reg()) {
 274         OptoReg::Name opto_parm_reg = OptoReg::as_OptoReg(parm_reg);
 275         assert(can_be_java_arg(opto_parm_reg) ||
 276                C->stub_function() == CAST_FROM_FN_PTR(address, OptoRuntime::rethrow_C) ||
 277                opto_parm_reg == inline_cache_reg(),
 278                "parameters in register must be preserved by runtime stubs");
 279       }
 280       for (uint j = 0; j < i; j++) {
 281         assert(parm_reg != vm_parm_regs[j].first(),
 282                "calling conv. must produce distinct regs");
 283       }
 284     }
 285   }
 286 #endif
 287 
 288   // Do some initial frame layout.
 289 
 290   // Compute the old incoming SP (may be called FP) as
 291   //   OptoReg::stack0() + locks + in_preserve_stack_slots + pad2.
 292   _old_SP = C->compute_old_SP();
 293   assert( is_even(_old_SP), "must be even" );
 294 
 295   // Compute highest incoming stack argument as
 296   //   _old_SP + out_preserve_stack_slots + incoming argument size.
 297   _in_arg_limit = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
 298   assert( is_even(_in_arg_limit), "out_preserve must be even" );
 299   for( i = 0; i < argcnt; i++ ) {
 300     // Permit args to have no register
 301     _calling_convention_mask[i].Clear();
 302     if( !vm_parm_regs[i].first()->is_valid() && !vm_parm_regs[i].second()->is_valid() ) {
 303       continue;
 304     }
 305     // calling_convention returns stack arguments as a count of
 306     // slots beyond OptoReg::stack0()/VMRegImpl::stack0.  We need to convert this to
 307     // the allocators point of view, taking into account all the
 308     // preserve area, locks & pad2.
 309 
 310     OptoReg::Name reg1 = warp_incoming_stk_arg(vm_parm_regs[i].first());
 311     if( OptoReg::is_valid(reg1))
 312       _calling_convention_mask[i].Insert(reg1);
 313 
 314     OptoReg::Name reg2 = warp_incoming_stk_arg(vm_parm_regs[i].second());
 315     if( OptoReg::is_valid(reg2))
 316       _calling_convention_mask[i].Insert(reg2);
 317 
 318     // Saved biased stack-slot register number
 319     _parm_regs[i].set_pair(reg2, reg1);
 320   }
 321 
 322   // Finally, make sure the incoming arguments take up an even number of
 323   // words, in case the arguments or locals need to contain doubleword stack
 324   // slots.  The rest of the system assumes that stack slot pairs (in
 325   // particular, in the spill area) which look aligned will in fact be
 326   // aligned relative to the stack pointer in the target machine.  Double
 327   // stack slots will always be allocated aligned.
 328   _new_SP = OptoReg::Name(align_up(_in_arg_limit, (int)RegMask::SlotsPerLong));
 329 
 330   // Compute highest outgoing stack argument as
 331   //   _new_SP + out_preserve_stack_slots + max(outgoing argument size).
 332   _out_arg_limit = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
 333   assert( is_even(_out_arg_limit), "out_preserve must be even" );
 334 
 335   if (!RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1))) {
 336     // the compiler cannot represent this method's calling sequence
 337     C->record_method_not_compilable("must be able to represent all call arguments in reg mask");
 338   }
 339 
 340   if (C->failing())  return;  // bailed out on incoming arg failure
 341 
 342   // ---------------
 343   // Collect roots of matcher trees.  Every node for which
 344   // _shared[_idx] is cleared is guaranteed to not be shared, and thus
 345   // can be a valid interior of some tree.
 346   find_shared( C->root() );
 347   find_shared( C->top() );
 348 
 349   C->print_method(PHASE_BEFORE_MATCHING);
 350 
 351   // Create new ideal node ConP #NULL even if it does exist in old space
 352   // to avoid false sharing if the corresponding mach node is not used.
 353   // The corresponding mach node is only used in rare cases for derived
 354   // pointers.
 355   Node* new_ideal_null = ConNode::make(TypePtr::NULL_PTR);
 356 
 357   // Swap out to old-space; emptying new-space
 358   Arena *old = C->node_arena()->move_contents(C->old_arena());
 359 
 360   // Save debug and profile information for nodes in old space:
 361   _old_node_note_array = C->node_note_array();
 362   if (_old_node_note_array != NULL) {
 363     C->set_node_note_array(new(C->comp_arena()) GrowableArray<Node_Notes*>
 364                            (C->comp_arena(), _old_node_note_array->length(),
 365                             0, NULL));
 366   }
 367 
 368   // Pre-size the new_node table to avoid the need for range checks.
 369   grow_new_node_array(C->unique());
 370 
 371   // Reset node counter so MachNodes start with _idx at 0
 372   int live_nodes = C->live_nodes();
 373   C->set_unique(0);
 374   C->reset_dead_node_list();
 375 
 376   // Recursively match trees from old space into new space.
 377   // Correct leaves of new-space Nodes; they point to old-space.
 378   _visited.Clear();             // Clear visit bits for xform call
 379   C->set_cached_top_node(xform( C->top(), live_nodes ));
 380   if (!C->failing()) {
 381     Node* xroot =        xform( C->root(), 1 );
 382     if (xroot == NULL) {
 383       Matcher::soft_match_failure();  // recursive matching process failed
 384       C->record_method_not_compilable("instruction match failed");
 385     } else {
 386       // During matching shared constants were attached to C->root()
 387       // because xroot wasn't available yet, so transfer the uses to
 388       // the xroot.
 389       for( DUIterator_Fast jmax, j = C->root()->fast_outs(jmax); j < jmax; j++ ) {
 390         Node* n = C->root()->fast_out(j);
 391         if (C->node_arena()->contains(n)) {
 392           assert(n->in(0) == C->root(), "should be control user");
 393           n->set_req(0, xroot);
 394           --j;
 395           --jmax;
 396         }
 397       }
 398 
 399       // Generate new mach node for ConP #NULL
 400       assert(new_ideal_null != NULL, "sanity");
 401       _mach_null = match_tree(new_ideal_null);
 402       // Don't set control, it will confuse GCM since there are no uses.
 403       // The control will be set when this node is used first time
 404       // in find_base_for_derived().
 405       assert(_mach_null != NULL, "");
 406 
 407       C->set_root(xroot->is_Root() ? xroot->as_Root() : NULL);
 408 
 409 #ifdef ASSERT
 410       verify_new_nodes_only(xroot);
 411 #endif
 412     }
 413   }
 414   if (C->top() == NULL || C->root() == NULL) {
 415     C->record_method_not_compilable("graph lost"); // %%% cannot happen?
 416   }
 417   if (C->failing()) {
 418     // delete old;
 419     old->destruct_contents();
 420     return;
 421   }
 422   assert( C->top(), "" );
 423   assert( C->root(), "" );
 424   validate_null_checks();
 425 
 426   // Now smoke old-space
 427   NOT_DEBUG( old->destruct_contents() );
 428 
 429   // ------------------------
 430   // Set up save-on-entry registers
 431   Fixup_Save_On_Entry( );
 432 }
 433 
 434 
 435 //------------------------------Fixup_Save_On_Entry----------------------------
 436 // The stated purpose of this routine is to take care of save-on-entry
 437 // registers.  However, the overall goal of the Match phase is to convert into
 438 // machine-specific instructions which have RegMasks to guide allocation.
 439 // So what this procedure really does is put a valid RegMask on each input
 440 // to the machine-specific variations of all Return, TailCall and Halt
 441 // instructions.  It also adds edgs to define the save-on-entry values (and of
 442 // course gives them a mask).
 443 
 444 static RegMask *init_input_masks( uint size, RegMask &ret_adr, RegMask &fp ) {
 445   RegMask *rms = NEW_RESOURCE_ARRAY( RegMask, size );
 446   // Do all the pre-defined register masks
 447   rms[TypeFunc::Control  ] = RegMask::Empty;
 448   rms[TypeFunc::I_O      ] = RegMask::Empty;
 449   rms[TypeFunc::Memory   ] = RegMask::Empty;
 450   rms[TypeFunc::ReturnAdr] = ret_adr;
 451   rms[TypeFunc::FramePtr ] = fp;
 452   return rms;
 453 }
 454 
 455 #define NOF_STACK_MASKS (3*6+5)
 456 
 457 // Create the initial stack mask used by values spilling to the stack.
 458 // Disallow any debug info in outgoing argument areas by setting the
 459 // initial mask accordingly.
 460 void Matcher::init_first_stack_mask() {
 461 
 462   // Allocate storage for spill masks as masks for the appropriate load type.
 463   RegMask *rms = (RegMask*)C->comp_arena()->Amalloc_D(sizeof(RegMask) * NOF_STACK_MASKS);
 464 
 465   // Initialize empty placeholder masks into the newly allocated arena
 466   for (int i = 0; i < NOF_STACK_MASKS; i++) {
 467     new (rms + i) RegMask();
 468   }
 469 
 470   idealreg2spillmask  [Op_RegN] = &rms[0];
 471   idealreg2spillmask  [Op_RegI] = &rms[1];
 472   idealreg2spillmask  [Op_RegL] = &rms[2];
 473   idealreg2spillmask  [Op_RegF] = &rms[3];
 474   idealreg2spillmask  [Op_RegD] = &rms[4];
 475   idealreg2spillmask  [Op_RegP] = &rms[5];
 476 
 477   idealreg2debugmask  [Op_RegN] = &rms[6];
 478   idealreg2debugmask  [Op_RegI] = &rms[7];
 479   idealreg2debugmask  [Op_RegL] = &rms[8];
 480   idealreg2debugmask  [Op_RegF] = &rms[9];
 481   idealreg2debugmask  [Op_RegD] = &rms[10];
 482   idealreg2debugmask  [Op_RegP] = &rms[11];
 483 
 484   idealreg2mhdebugmask[Op_RegN] = &rms[12];
 485   idealreg2mhdebugmask[Op_RegI] = &rms[13];
 486   idealreg2mhdebugmask[Op_RegL] = &rms[14];
 487   idealreg2mhdebugmask[Op_RegF] = &rms[15];
 488   idealreg2mhdebugmask[Op_RegD] = &rms[16];
 489   idealreg2mhdebugmask[Op_RegP] = &rms[17];
 490 
 491   idealreg2spillmask  [Op_VecS] = &rms[18];
 492   idealreg2spillmask  [Op_VecD] = &rms[19];
 493   idealreg2spillmask  [Op_VecX] = &rms[20];
 494   idealreg2spillmask  [Op_VecY] = &rms[21];
 495   idealreg2spillmask  [Op_VecZ] = &rms[22];
 496 
 497   OptoReg::Name i;
 498 
 499   // At first, start with the empty mask
 500   C->FIRST_STACK_mask().Clear();
 501 
 502   // Add in the incoming argument area
 503   OptoReg::Name init_in = OptoReg::add(_old_SP, C->out_preserve_stack_slots());
 504   for (i = init_in; i < _in_arg_limit; i = OptoReg::add(i,1)) {
 505     C->FIRST_STACK_mask().Insert(i);
 506   }
 507 
 508   // Check if the method has a reserved entry in the argument stack area that
 509   // should not be used for spilling because it may hold the return address.
 510   if (C->method() != NULL && C->method()->has_scalarized_args()) {
 511     ExtendedSignature sig_cc = ExtendedSignature(C->method()->get_sig_cc(), SigEntryFilter());
 512     for (int off = 0; !sig_cc.at_end(); ) {
 513       BasicType bt = (*sig_cc)._bt;
 514       off += type2size[bt];
 515       while (SigEntry::next_is_reserved(sig_cc, bt)) {
 516         // Remove reserved stack slot from mask to avoid spilling
 517         OptoRegPair reg = _parm_regs[off];
 518         assert(OptoReg::is_valid(reg.first()), "invalid reserved register");
 519         C->FIRST_STACK_mask().Remove(reg.first());
 520         C->FIRST_STACK_mask().Remove(reg.first()+1); // Always occupies two stack slots
 521         off += type2size[bt];
 522       }
 523     }
 524   }
 525 
 526   // Add in all bits past the outgoing argument area
 527   guarantee(RegMask::can_represent_arg(OptoReg::add(_out_arg_limit,-1)),
 528             "must be able to represent all call arguments in reg mask");
 529   OptoReg::Name init = _out_arg_limit;
 530   for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1)) {
 531     C->FIRST_STACK_mask().Insert(i);
 532   }
 533   // Finally, set the "infinite stack" bit.
 534   C->FIRST_STACK_mask().set_AllStack();
 535 
 536   // Make spill masks.  Registers for their class, plus FIRST_STACK_mask.
 537   RegMask aligned_stack_mask = C->FIRST_STACK_mask();
 538   // Keep spill masks aligned.
 539   aligned_stack_mask.clear_to_pairs();
 540   assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 541 
 542   *idealreg2spillmask[Op_RegP] = *idealreg2regmask[Op_RegP];
 543 #ifdef _LP64
 544   *idealreg2spillmask[Op_RegN] = *idealreg2regmask[Op_RegN];
 545    idealreg2spillmask[Op_RegN]->OR(C->FIRST_STACK_mask());
 546    idealreg2spillmask[Op_RegP]->OR(aligned_stack_mask);
 547 #else
 548    idealreg2spillmask[Op_RegP]->OR(C->FIRST_STACK_mask());
 549 #endif
 550   *idealreg2spillmask[Op_RegI] = *idealreg2regmask[Op_RegI];
 551    idealreg2spillmask[Op_RegI]->OR(C->FIRST_STACK_mask());
 552   *idealreg2spillmask[Op_RegL] = *idealreg2regmask[Op_RegL];
 553    idealreg2spillmask[Op_RegL]->OR(aligned_stack_mask);
 554   *idealreg2spillmask[Op_RegF] = *idealreg2regmask[Op_RegF];
 555    idealreg2spillmask[Op_RegF]->OR(C->FIRST_STACK_mask());
 556   *idealreg2spillmask[Op_RegD] = *idealreg2regmask[Op_RegD];
 557    idealreg2spillmask[Op_RegD]->OR(aligned_stack_mask);
 558 
 559   if (Matcher::vector_size_supported(T_BYTE,4)) {
 560     *idealreg2spillmask[Op_VecS] = *idealreg2regmask[Op_VecS];
 561      idealreg2spillmask[Op_VecS]->OR(C->FIRST_STACK_mask());
 562   }
 563   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 564     // For VecD we need dual alignment and 8 bytes (2 slots) for spills.
 565     // RA guarantees such alignment since it is needed for Double and Long values.
 566     *idealreg2spillmask[Op_VecD] = *idealreg2regmask[Op_VecD];
 567      idealreg2spillmask[Op_VecD]->OR(aligned_stack_mask);
 568   }
 569   if (Matcher::vector_size_supported(T_FLOAT,4)) {
 570     // For VecX we need quadro alignment and 16 bytes (4 slots) for spills.
 571     //
 572     // RA can use input arguments stack slots for spills but until RA
 573     // we don't know frame size and offset of input arg stack slots.
 574     //
 575     // Exclude last input arg stack slots to avoid spilling vectors there
 576     // otherwise vector spills could stomp over stack slots in caller frame.
 577     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 578     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecX); k++) {
 579       aligned_stack_mask.Remove(in);
 580       in = OptoReg::add(in, -1);
 581     }
 582      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecX);
 583      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 584     *idealreg2spillmask[Op_VecX] = *idealreg2regmask[Op_VecX];
 585      idealreg2spillmask[Op_VecX]->OR(aligned_stack_mask);
 586   }
 587   if (Matcher::vector_size_supported(T_FLOAT,8)) {
 588     // For VecY we need octo alignment and 32 bytes (8 slots) for spills.
 589     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 590     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecY); k++) {
 591       aligned_stack_mask.Remove(in);
 592       in = OptoReg::add(in, -1);
 593     }
 594      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecY);
 595      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 596     *idealreg2spillmask[Op_VecY] = *idealreg2regmask[Op_VecY];
 597      idealreg2spillmask[Op_VecY]->OR(aligned_stack_mask);
 598   }
 599   if (Matcher::vector_size_supported(T_FLOAT,16)) {
 600     // For VecZ we need enough alignment and 64 bytes (16 slots) for spills.
 601     OptoReg::Name in = OptoReg::add(_in_arg_limit, -1);
 602     for (int k = 1; (in >= init_in) && (k < RegMask::SlotsPerVecZ); k++) {
 603       aligned_stack_mask.Remove(in);
 604       in = OptoReg::add(in, -1);
 605     }
 606      aligned_stack_mask.clear_to_sets(RegMask::SlotsPerVecZ);
 607      assert(aligned_stack_mask.is_AllStack(), "should be infinite stack");
 608     *idealreg2spillmask[Op_VecZ] = *idealreg2regmask[Op_VecZ];
 609      idealreg2spillmask[Op_VecZ]->OR(aligned_stack_mask);
 610   }
 611    if (UseFPUForSpilling) {
 612      // This mask logic assumes that the spill operations are
 613      // symmetric and that the registers involved are the same size.
 614      // On sparc for instance we may have to use 64 bit moves will
 615      // kill 2 registers when used with F0-F31.
 616      idealreg2spillmask[Op_RegI]->OR(*idealreg2regmask[Op_RegF]);
 617      idealreg2spillmask[Op_RegF]->OR(*idealreg2regmask[Op_RegI]);
 618 #ifdef _LP64
 619      idealreg2spillmask[Op_RegN]->OR(*idealreg2regmask[Op_RegF]);
 620      idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
 621      idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
 622      idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegD]);
 623 #else
 624      idealreg2spillmask[Op_RegP]->OR(*idealreg2regmask[Op_RegF]);
 625 #ifdef ARM
 626      // ARM has support for moving 64bit values between a pair of
 627      // integer registers and a double register
 628      idealreg2spillmask[Op_RegL]->OR(*idealreg2regmask[Op_RegD]);
 629      idealreg2spillmask[Op_RegD]->OR(*idealreg2regmask[Op_RegL]);
 630 #endif
 631 #endif
 632    }
 633 
 634   // Make up debug masks.  Any spill slot plus callee-save registers.
 635   // Caller-save registers are assumed to be trashable by the various
 636   // inline-cache fixup routines.
 637   *idealreg2debugmask  [Op_RegN]= *idealreg2spillmask[Op_RegN];
 638   *idealreg2debugmask  [Op_RegI]= *idealreg2spillmask[Op_RegI];
 639   *idealreg2debugmask  [Op_RegL]= *idealreg2spillmask[Op_RegL];
 640   *idealreg2debugmask  [Op_RegF]= *idealreg2spillmask[Op_RegF];
 641   *idealreg2debugmask  [Op_RegD]= *idealreg2spillmask[Op_RegD];
 642   *idealreg2debugmask  [Op_RegP]= *idealreg2spillmask[Op_RegP];
 643 
 644   *idealreg2mhdebugmask[Op_RegN]= *idealreg2spillmask[Op_RegN];
 645   *idealreg2mhdebugmask[Op_RegI]= *idealreg2spillmask[Op_RegI];
 646   *idealreg2mhdebugmask[Op_RegL]= *idealreg2spillmask[Op_RegL];
 647   *idealreg2mhdebugmask[Op_RegF]= *idealreg2spillmask[Op_RegF];
 648   *idealreg2mhdebugmask[Op_RegD]= *idealreg2spillmask[Op_RegD];
 649   *idealreg2mhdebugmask[Op_RegP]= *idealreg2spillmask[Op_RegP];
 650 
 651   // Prevent stub compilations from attempting to reference
 652   // callee-saved registers from debug info
 653   bool exclude_soe = !Compile::current()->is_method_compilation();
 654 
 655   for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
 656     // registers the caller has to save do not work
 657     if( _register_save_policy[i] == 'C' ||
 658         _register_save_policy[i] == 'A' ||
 659         (_register_save_policy[i] == 'E' && exclude_soe) ) {
 660       idealreg2debugmask  [Op_RegN]->Remove(i);
 661       idealreg2debugmask  [Op_RegI]->Remove(i); // Exclude save-on-call
 662       idealreg2debugmask  [Op_RegL]->Remove(i); // registers from debug
 663       idealreg2debugmask  [Op_RegF]->Remove(i); // masks
 664       idealreg2debugmask  [Op_RegD]->Remove(i);
 665       idealreg2debugmask  [Op_RegP]->Remove(i);
 666 
 667       idealreg2mhdebugmask[Op_RegN]->Remove(i);
 668       idealreg2mhdebugmask[Op_RegI]->Remove(i);
 669       idealreg2mhdebugmask[Op_RegL]->Remove(i);
 670       idealreg2mhdebugmask[Op_RegF]->Remove(i);
 671       idealreg2mhdebugmask[Op_RegD]->Remove(i);
 672       idealreg2mhdebugmask[Op_RegP]->Remove(i);
 673     }
 674   }
 675 
 676   // Subtract the register we use to save the SP for MethodHandle
 677   // invokes to from the debug mask.
 678   const RegMask save_mask = method_handle_invoke_SP_save_mask();
 679   idealreg2mhdebugmask[Op_RegN]->SUBTRACT(save_mask);
 680   idealreg2mhdebugmask[Op_RegI]->SUBTRACT(save_mask);
 681   idealreg2mhdebugmask[Op_RegL]->SUBTRACT(save_mask);
 682   idealreg2mhdebugmask[Op_RegF]->SUBTRACT(save_mask);
 683   idealreg2mhdebugmask[Op_RegD]->SUBTRACT(save_mask);
 684   idealreg2mhdebugmask[Op_RegP]->SUBTRACT(save_mask);
 685 }
 686 
 687 //---------------------------is_save_on_entry----------------------------------
 688 bool Matcher::is_save_on_entry( int reg ) {
 689   return
 690     _register_save_policy[reg] == 'E' ||
 691     _register_save_policy[reg] == 'A' || // Save-on-entry register?
 692     // Also save argument registers in the trampolining stubs
 693     (C->save_argument_registers() && is_spillable_arg(reg));
 694 }
 695 
 696 //---------------------------Fixup_Save_On_Entry-------------------------------
 697 void Matcher::Fixup_Save_On_Entry( ) {
 698   init_first_stack_mask();
 699 
 700   Node *root = C->root();       // Short name for root
 701   // Count number of save-on-entry registers.
 702   uint soe_cnt = number_of_saved_registers();
 703   uint i;
 704 
 705   // Find the procedure Start Node
 706   StartNode *start = C->start();
 707   assert( start, "Expect a start node" );
 708 
 709   // Save argument registers in the trampolining stubs
 710   if( C->save_argument_registers() )
 711     for( i = 0; i < _last_Mach_Reg; i++ )
 712       if( is_spillable_arg(i) )
 713         soe_cnt++;
 714 
 715   // Input RegMask array shared by all Returns.
 716   // The type for doubles and longs has a count of 2, but
 717   // there is only 1 returned value
 718   uint ret_edge_cnt = C->tf()->range_cc()->cnt();
 719   RegMask *ret_rms  = init_input_masks( ret_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 720   for (i = TypeFunc::Parms; i < ret_edge_cnt; i++) {
 721     ret_rms[i] = _return_values_mask[i-TypeFunc::Parms];
 722   }
 723 
 724   // Input RegMask array shared by all Rethrows.
 725   uint reth_edge_cnt = TypeFunc::Parms+1;
 726   RegMask *reth_rms  = init_input_masks( reth_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 727   // Rethrow takes exception oop only, but in the argument 0 slot.
 728   OptoReg::Name reg = find_receiver(false);
 729   if (reg >= 0) {
 730     reth_rms[TypeFunc::Parms] = mreg2regmask[reg];
 731 #ifdef _LP64
 732     // Need two slots for ptrs in 64-bit land
 733     reth_rms[TypeFunc::Parms].Insert(OptoReg::add(OptoReg::Name(reg), 1));
 734 #endif
 735   }
 736 
 737   // Input RegMask array shared by all TailCalls
 738   uint tail_call_edge_cnt = TypeFunc::Parms+2;
 739   RegMask *tail_call_rms = init_input_masks( tail_call_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 740 
 741   // Input RegMask array shared by all TailJumps
 742   uint tail_jump_edge_cnt = TypeFunc::Parms+2;
 743   RegMask *tail_jump_rms = init_input_masks( tail_jump_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 744 
 745   // TailCalls have 2 returned values (target & moop), whose masks come
 746   // from the usual MachNode/MachOper mechanism.  Find a sample
 747   // TailCall to extract these masks and put the correct masks into
 748   // the tail_call_rms array.
 749   for( i=1; i < root->req(); i++ ) {
 750     MachReturnNode *m = root->in(i)->as_MachReturn();
 751     if( m->ideal_Opcode() == Op_TailCall ) {
 752       tail_call_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
 753       tail_call_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
 754       break;
 755     }
 756   }
 757 
 758   // TailJumps have 2 returned values (target & ex_oop), whose masks come
 759   // from the usual MachNode/MachOper mechanism.  Find a sample
 760   // TailJump to extract these masks and put the correct masks into
 761   // the tail_jump_rms array.
 762   for( i=1; i < root->req(); i++ ) {
 763     MachReturnNode *m = root->in(i)->as_MachReturn();
 764     if( m->ideal_Opcode() == Op_TailJump ) {
 765       tail_jump_rms[TypeFunc::Parms+0] = m->MachNode::in_RegMask(TypeFunc::Parms+0);
 766       tail_jump_rms[TypeFunc::Parms+1] = m->MachNode::in_RegMask(TypeFunc::Parms+1);
 767       break;
 768     }
 769   }
 770 
 771   // Input RegMask array shared by all Halts
 772   uint halt_edge_cnt = TypeFunc::Parms;
 773   RegMask *halt_rms = init_input_masks( halt_edge_cnt + soe_cnt, _return_addr_mask, c_frame_ptr_mask );
 774 
 775   // Capture the return input masks into each exit flavor
 776   for( i=1; i < root->req(); i++ ) {
 777     MachReturnNode *exit = root->in(i)->as_MachReturn();
 778     switch( exit->ideal_Opcode() ) {
 779       case Op_Return   : exit->_in_rms = ret_rms;  break;
 780       case Op_Rethrow  : exit->_in_rms = reth_rms; break;
 781       case Op_TailCall : exit->_in_rms = tail_call_rms; break;
 782       case Op_TailJump : exit->_in_rms = tail_jump_rms; break;
 783       case Op_Halt     : exit->_in_rms = halt_rms; break;
 784       default          : ShouldNotReachHere();
 785     }
 786   }
 787 
 788   // Next unused projection number from Start.
 789   int proj_cnt = C->tf()->domain_cc()->cnt();
 790 
 791   // Do all the save-on-entry registers.  Make projections from Start for
 792   // them, and give them a use at the exit points.  To the allocator, they
 793   // look like incoming register arguments.
 794   for( i = 0; i < _last_Mach_Reg; i++ ) {
 795     if( is_save_on_entry(i) ) {
 796 
 797       // Add the save-on-entry to the mask array
 798       ret_rms      [      ret_edge_cnt] = mreg2regmask[i];
 799       reth_rms     [     reth_edge_cnt] = mreg2regmask[i];
 800       tail_call_rms[tail_call_edge_cnt] = mreg2regmask[i];
 801       tail_jump_rms[tail_jump_edge_cnt] = mreg2regmask[i];
 802       // Halts need the SOE registers, but only in the stack as debug info.
 803       // A just-prior uncommon-trap or deoptimization will use the SOE regs.
 804       halt_rms     [     halt_edge_cnt] = *idealreg2spillmask[_register_save_type[i]];
 805 
 806       Node *mproj;
 807 
 808       // Is this a RegF low half of a RegD?  Double up 2 adjacent RegF's
 809       // into a single RegD.
 810       if( (i&1) == 0 &&
 811           _register_save_type[i  ] == Op_RegF &&
 812           _register_save_type[i+1] == Op_RegF &&
 813           is_save_on_entry(i+1) ) {
 814         // Add other bit for double
 815         ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
 816         reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
 817         tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
 818         tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
 819         halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
 820         mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegD );
 821         proj_cnt += 2;          // Skip 2 for doubles
 822       }
 823       else if( (i&1) == 1 &&    // Else check for high half of double
 824                _register_save_type[i-1] == Op_RegF &&
 825                _register_save_type[i  ] == Op_RegF &&
 826                is_save_on_entry(i-1) ) {
 827         ret_rms      [      ret_edge_cnt] = RegMask::Empty;
 828         reth_rms     [     reth_edge_cnt] = RegMask::Empty;
 829         tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
 830         tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
 831         halt_rms     [     halt_edge_cnt] = RegMask::Empty;
 832         mproj = C->top();
 833       }
 834       // Is this a RegI low half of a RegL?  Double up 2 adjacent RegI's
 835       // into a single RegL.
 836       else if( (i&1) == 0 &&
 837           _register_save_type[i  ] == Op_RegI &&
 838           _register_save_type[i+1] == Op_RegI &&
 839         is_save_on_entry(i+1) ) {
 840         // Add other bit for long
 841         ret_rms      [      ret_edge_cnt].Insert(OptoReg::Name(i+1));
 842         reth_rms     [     reth_edge_cnt].Insert(OptoReg::Name(i+1));
 843         tail_call_rms[tail_call_edge_cnt].Insert(OptoReg::Name(i+1));
 844         tail_jump_rms[tail_jump_edge_cnt].Insert(OptoReg::Name(i+1));
 845         halt_rms     [     halt_edge_cnt].Insert(OptoReg::Name(i+1));
 846         mproj = new MachProjNode( start, proj_cnt, ret_rms[ret_edge_cnt], Op_RegL );
 847         proj_cnt += 2;          // Skip 2 for longs
 848       }
 849       else if( (i&1) == 1 &&    // Else check for high half of long
 850                _register_save_type[i-1] == Op_RegI &&
 851                _register_save_type[i  ] == Op_RegI &&
 852                is_save_on_entry(i-1) ) {
 853         ret_rms      [      ret_edge_cnt] = RegMask::Empty;
 854         reth_rms     [     reth_edge_cnt] = RegMask::Empty;
 855         tail_call_rms[tail_call_edge_cnt] = RegMask::Empty;
 856         tail_jump_rms[tail_jump_edge_cnt] = RegMask::Empty;
 857         halt_rms     [     halt_edge_cnt] = RegMask::Empty;
 858         mproj = C->top();
 859       } else {
 860         // Make a projection for it off the Start
 861         mproj = new MachProjNode( start, proj_cnt++, ret_rms[ret_edge_cnt], _register_save_type[i] );
 862       }
 863 
 864       ret_edge_cnt ++;
 865       reth_edge_cnt ++;
 866       tail_call_edge_cnt ++;
 867       tail_jump_edge_cnt ++;
 868       halt_edge_cnt ++;
 869 
 870       // Add a use of the SOE register to all exit paths
 871       for( uint j=1; j < root->req(); j++ )
 872         root->in(j)->add_req(mproj);
 873     } // End of if a save-on-entry register
 874   } // End of for all machine registers
 875 }
 876 
 877 //------------------------------init_spill_mask--------------------------------
 878 void Matcher::init_spill_mask( Node *ret ) {
 879   if( idealreg2regmask[Op_RegI] ) return; // One time only init
 880 
 881   OptoReg::c_frame_pointer = c_frame_pointer();
 882   c_frame_ptr_mask = c_frame_pointer();
 883 #ifdef _LP64
 884   // pointers are twice as big
 885   c_frame_ptr_mask.Insert(OptoReg::add(c_frame_pointer(),1));
 886 #endif
 887 
 888   // Start at OptoReg::stack0()
 889   STACK_ONLY_mask.Clear();
 890   OptoReg::Name init = OptoReg::stack2reg(0);
 891   // STACK_ONLY_mask is all stack bits
 892   OptoReg::Name i;
 893   for (i = init; RegMask::can_represent(i); i = OptoReg::add(i,1))
 894     STACK_ONLY_mask.Insert(i);
 895   // Also set the "infinite stack" bit.
 896   STACK_ONLY_mask.set_AllStack();
 897 
 898   // Copy the register names over into the shared world
 899   for( i=OptoReg::Name(0); i<OptoReg::Name(_last_Mach_Reg); i = OptoReg::add(i,1) ) {
 900     // SharedInfo::regName[i] = regName[i];
 901     // Handy RegMasks per machine register
 902     mreg2regmask[i].Insert(i);
 903   }
 904 
 905   // Grab the Frame Pointer
 906   Node *fp  = ret->in(TypeFunc::FramePtr);
 907   Node *mem = ret->in(TypeFunc::Memory);
 908   const TypePtr* atp = TypePtr::BOTTOM;
 909   // Share frame pointer while making spill ops
 910   set_shared(fp);
 911 
 912   // Compute generic short-offset Loads
 913 #ifdef _LP64
 914   MachNode *spillCP = match_tree(new LoadNNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
 915 #endif
 916   MachNode *spillI  = match_tree(new LoadINode(NULL,mem,fp,atp,TypeInt::INT,MemNode::unordered));
 917   MachNode *spillL  = match_tree(new LoadLNode(NULL,mem,fp,atp,TypeLong::LONG,MemNode::unordered, LoadNode::DependsOnlyOnTest, false));
 918   MachNode *spillF  = match_tree(new LoadFNode(NULL,mem,fp,atp,Type::FLOAT,MemNode::unordered));
 919   MachNode *spillD  = match_tree(new LoadDNode(NULL,mem,fp,atp,Type::DOUBLE,MemNode::unordered));
 920   MachNode *spillP  = match_tree(new LoadPNode(NULL,mem,fp,atp,TypeInstPtr::BOTTOM,MemNode::unordered));
 921   assert(spillI != NULL && spillL != NULL && spillF != NULL &&
 922          spillD != NULL && spillP != NULL, "");
 923   // Get the ADLC notion of the right regmask, for each basic type.
 924 #ifdef _LP64
 925   idealreg2regmask[Op_RegN] = &spillCP->out_RegMask();
 926 #endif
 927   idealreg2regmask[Op_RegI] = &spillI->out_RegMask();
 928   idealreg2regmask[Op_RegL] = &spillL->out_RegMask();
 929   idealreg2regmask[Op_RegF] = &spillF->out_RegMask();
 930   idealreg2regmask[Op_RegD] = &spillD->out_RegMask();
 931   idealreg2regmask[Op_RegP] = &spillP->out_RegMask();
 932 
 933   // Vector regmasks.
 934   if (Matcher::vector_size_supported(T_BYTE,4)) {
 935     TypeVect::VECTS = TypeVect::make(T_BYTE, 4);
 936     MachNode *spillVectS = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTS));
 937     idealreg2regmask[Op_VecS] = &spillVectS->out_RegMask();
 938   }
 939   if (Matcher::vector_size_supported(T_FLOAT,2)) {
 940     MachNode *spillVectD = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTD));
 941     idealreg2regmask[Op_VecD] = &spillVectD->out_RegMask();
 942   }
 943   if (Matcher::vector_size_supported(T_FLOAT,4)) {
 944     MachNode *spillVectX = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTX));
 945     idealreg2regmask[Op_VecX] = &spillVectX->out_RegMask();
 946   }
 947   if (Matcher::vector_size_supported(T_FLOAT,8)) {
 948     MachNode *spillVectY = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTY));
 949     idealreg2regmask[Op_VecY] = &spillVectY->out_RegMask();
 950   }
 951   if (Matcher::vector_size_supported(T_FLOAT,16)) {
 952     MachNode *spillVectZ = match_tree(new LoadVectorNode(NULL,mem,fp,atp,TypeVect::VECTZ));
 953     idealreg2regmask[Op_VecZ] = &spillVectZ->out_RegMask();
 954   }
 955 }
 956 
 957 #ifdef ASSERT
 958 static void match_alias_type(Compile* C, Node* n, Node* m) {
 959   if (!VerifyAliases)  return;  // do not go looking for trouble by default
 960   const TypePtr* nat = n->adr_type();
 961   const TypePtr* mat = m->adr_type();
 962   int nidx = C->get_alias_index(nat);
 963   int midx = C->get_alias_index(mat);
 964   // Detune the assert for cases like (AndI 0xFF (LoadB p)).
 965   if (nidx == Compile::AliasIdxTop && midx >= Compile::AliasIdxRaw) {
 966     for (uint i = 1; i < n->req(); i++) {
 967       Node* n1 = n->in(i);
 968       const TypePtr* n1at = n1->adr_type();
 969       if (n1at != NULL) {
 970         nat = n1at;
 971         nidx = C->get_alias_index(n1at);
 972       }
 973     }
 974   }
 975   // %%% Kludgery.  Instead, fix ideal adr_type methods for all these cases:
 976   if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxRaw) {
 977     switch (n->Opcode()) {
 978     case Op_PrefetchAllocation:
 979       nidx = Compile::AliasIdxRaw;
 980       nat = TypeRawPtr::BOTTOM;
 981       break;
 982     }
 983   }
 984   if (nidx == Compile::AliasIdxRaw && midx == Compile::AliasIdxTop) {
 985     switch (n->Opcode()) {
 986     case Op_ClearArray:
 987       midx = Compile::AliasIdxRaw;
 988       mat = TypeRawPtr::BOTTOM;
 989       break;
 990     }
 991   }
 992   if (nidx == Compile::AliasIdxTop && midx == Compile::AliasIdxBot) {
 993     switch (n->Opcode()) {
 994     case Op_Return:
 995     case Op_Rethrow:
 996     case Op_Halt:
 997     case Op_TailCall:
 998     case Op_TailJump:
 999       nidx = Compile::AliasIdxBot;
1000       nat = TypePtr::BOTTOM;
1001       break;
1002     }
1003   }
1004   if (nidx == Compile::AliasIdxBot && midx == Compile::AliasIdxTop) {
1005     switch (n->Opcode()) {
1006     case Op_StrComp:
1007     case Op_StrEquals:
1008     case Op_StrIndexOf:
1009     case Op_StrIndexOfChar:
1010     case Op_AryEq:
1011     case Op_HasNegatives:
1012     case Op_MemBarVolatile:
1013     case Op_MemBarCPUOrder: // %%% these ideals should have narrower adr_type?
1014     case Op_StrInflatedCopy:
1015     case Op_StrCompressedCopy:
1016     case Op_OnSpinWait:
1017     case Op_EncodeISOArray:
1018       nidx = Compile::AliasIdxTop;
1019       nat = NULL;
1020       break;
1021     }
1022   }
1023   if (nidx != midx) {
1024     if (PrintOpto || (PrintMiscellaneous && (WizardMode || Verbose))) {
1025       tty->print_cr("==== Matcher alias shift %d => %d", nidx, midx);
1026       n->dump();
1027       m->dump();
1028     }
1029     assert(C->subsume_loads() && C->must_alias(nat, midx),
1030            "must not lose alias info when matching");
1031   }
1032 }
1033 #endif
1034 
1035 //------------------------------xform------------------------------------------
1036 // Given a Node in old-space, Match him (Label/Reduce) to produce a machine
1037 // Node in new-space.  Given a new-space Node, recursively walk his children.
1038 Node *Matcher::transform( Node *n ) { ShouldNotCallThis(); return n; }
1039 Node *Matcher::xform( Node *n, int max_stack ) {
1040   // Use one stack to keep both: child's node/state and parent's node/index
1041   MStack mstack(max_stack * 2 * 2); // usually: C->live_nodes() * 2 * 2
1042   mstack.push(n, Visit, NULL, -1);  // set NULL as parent to indicate root
1043   while (mstack.is_nonempty()) {
1044     C->check_node_count(NodeLimitFudgeFactor, "too many nodes matching instructions");
1045     if (C->failing()) return NULL;
1046     n = mstack.node();          // Leave node on stack
1047     Node_State nstate = mstack.state();
1048     if (nstate == Visit) {
1049       mstack.set_state(Post_Visit);
1050       Node *oldn = n;
1051       // Old-space or new-space check
1052       if (!C->node_arena()->contains(n)) {
1053         // Old space!
1054         Node* m;
1055         if (has_new_node(n)) {  // Not yet Label/Reduced
1056           m = new_node(n);
1057         } else {
1058           if (!is_dontcare(n)) { // Matcher can match this guy
1059             // Calls match special.  They match alone with no children.
1060             // Their children, the incoming arguments, match normally.
1061             m = n->is_SafePoint() ? match_sfpt(n->as_SafePoint()):match_tree(n);
1062             if (C->failing())  return NULL;
1063             if (m == NULL) { Matcher::soft_match_failure(); return NULL; }
1064             if (n->is_MemBar()) {
1065               m->as_MachMemBar()->set_adr_type(n->adr_type());
1066             }
1067           } else {                  // Nothing the matcher cares about
1068             if (n->is_Proj() && n->in(0) != NULL && n->in(0)->is_Multi()) {       // Projections?
1069               // Convert to machine-dependent projection
1070               RegMask* mask = NULL;
1071               if (n->in(0)->is_Call()) {
1072                 mask = return_values_mask(n->in(0)->as_Call()->tf()->range_cc());
1073               }
1074               m = n->in(0)->as_Multi()->match(n->as_Proj(), this, mask);
1075 #ifdef ASSERT
1076               _new2old_map.map(m->_idx, n);
1077 #endif
1078               if (m->in(0) != NULL) // m might be top
1079                 collect_null_checks(m, n);
1080             } else {                // Else just a regular 'ol guy
1081               m = n->clone();       // So just clone into new-space
1082 #ifdef ASSERT
1083               _new2old_map.map(m->_idx, n);
1084 #endif
1085               // Def-Use edges will be added incrementally as Uses
1086               // of this node are matched.
1087               assert(m->outcnt() == 0, "no Uses of this clone yet");
1088             }
1089           }
1090 
1091           set_new_node(n, m);       // Map old to new
1092           if (_old_node_note_array != NULL) {
1093             Node_Notes* nn = C->locate_node_notes(_old_node_note_array,
1094                                                   n->_idx);
1095             C->set_node_notes_at(m->_idx, nn);
1096           }
1097           debug_only(match_alias_type(C, n, m));
1098         }
1099         n = m;    // n is now a new-space node
1100         mstack.set_node(n);
1101       }
1102 
1103       // New space!
1104       if (_visited.test_set(n->_idx)) continue; // while(mstack.is_nonempty())
1105 
1106       int i;
1107       // Put precedence edges on stack first (match them last).
1108       for (i = oldn->req(); (uint)i < oldn->len(); i++) {
1109         Node *m = oldn->in(i);
1110         if (m == NULL) break;
1111         // set -1 to call add_prec() instead of set_req() during Step1
1112         mstack.push(m, Visit, n, -1);
1113       }
1114 
1115       // Handle precedence edges for interior nodes
1116       for (i = n->len()-1; (uint)i >= n->req(); i--) {
1117         Node *m = n->in(i);
1118         if (m == NULL || C->node_arena()->contains(m)) continue;
1119         n->rm_prec(i);
1120         // set -1 to call add_prec() instead of set_req() during Step1
1121         mstack.push(m, Visit, n, -1);
1122       }
1123 
1124       // For constant debug info, I'd rather have unmatched constants.
1125       int cnt = n->req();
1126       JVMState* jvms = n->jvms();
1127       int debug_cnt = jvms ? jvms->debug_start() : cnt;
1128 
1129       // Now do only debug info.  Clone constants rather than matching.
1130       // Constants are represented directly in the debug info without
1131       // the need for executable machine instructions.
1132       // Monitor boxes are also represented directly.
1133       for (i = cnt - 1; i >= debug_cnt; --i) { // For all debug inputs do
1134         Node *m = n->in(i);          // Get input
1135         int op = m->Opcode();
1136         assert((op == Op_BoxLock) == jvms->is_monitor_use(i), "boxes only at monitor sites");
1137         if( op == Op_ConI || op == Op_ConP || op == Op_ConN || op == Op_ConNKlass ||
1138             op == Op_ConF || op == Op_ConD || op == Op_ConL
1139             // || op == Op_BoxLock  // %%%% enable this and remove (+++) in chaitin.cpp
1140             ) {
1141           m = m->clone();
1142 #ifdef ASSERT
1143           _new2old_map.map(m->_idx, n);
1144 #endif
1145           mstack.push(m, Post_Visit, n, i); // Don't need to visit
1146           mstack.push(m->in(0), Visit, m, 0);
1147         } else {
1148           mstack.push(m, Visit, n, i);
1149         }
1150       }
1151 
1152       // And now walk his children, and convert his inputs to new-space.
1153       for( ; i >= 0; --i ) { // For all normal inputs do
1154         Node *m = n->in(i);  // Get input
1155         if(m != NULL)
1156           mstack.push(m, Visit, n, i);
1157       }
1158 
1159     }
1160     else if (nstate == Post_Visit) {
1161       // Set xformed input
1162       Node *p = mstack.parent();
1163       if (p != NULL) { // root doesn't have parent
1164         int i = (int)mstack.index();
1165         if (i >= 0)
1166           p->set_req(i, n); // required input
1167         else if (i == -1)
1168           p->add_prec(n);   // precedence input
1169         else
1170           ShouldNotReachHere();
1171       }
1172       mstack.pop(); // remove processed node from stack
1173     }
1174     else {
1175       ShouldNotReachHere();
1176     }
1177   } // while (mstack.is_nonempty())
1178   return n; // Return new-space Node
1179 }
1180 
1181 //------------------------------warp_outgoing_stk_arg------------------------
1182 OptoReg::Name Matcher::warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ) {
1183   // Convert outgoing argument location to a pre-biased stack offset
1184   if (reg->is_stack()) {
1185     OptoReg::Name warped = reg->reg2stack();
1186     // Adjust the stack slot offset to be the register number used
1187     // by the allocator.
1188     warped = OptoReg::add(begin_out_arg_area, warped);
1189     // Keep track of the largest numbered stack slot used for an arg.
1190     // Largest used slot per call-site indicates the amount of stack
1191     // that is killed by the call.
1192     if( warped >= out_arg_limit_per_call )
1193       out_arg_limit_per_call = OptoReg::add(warped,1);
1194     if (!RegMask::can_represent_arg(warped)) {
1195       C->record_method_not_compilable("unsupported calling sequence");
1196       return OptoReg::Bad;
1197     }
1198     return warped;
1199   }
1200   return OptoReg::as_OptoReg(reg);
1201 }
1202 
1203 
1204 //------------------------------match_sfpt-------------------------------------
1205 // Helper function to match call instructions.  Calls match special.
1206 // They match alone with no children.  Their children, the incoming
1207 // arguments, match normally.
1208 MachNode *Matcher::match_sfpt( SafePointNode *sfpt ) {
1209   MachSafePointNode *msfpt = NULL;
1210   MachCallNode      *mcall = NULL;
1211   uint               cnt;
1212   // Split out case for SafePoint vs Call
1213   CallNode *call;
1214   const TypeTuple *domain;
1215   ciMethod*        method = NULL;
1216   bool             is_method_handle_invoke = false;  // for special kill effects
1217   if( sfpt->is_Call() ) {
1218     call = sfpt->as_Call();
1219     domain = call->tf()->domain_cc();
1220     cnt = domain->cnt();
1221 
1222     // Match just the call, nothing else
1223     MachNode *m = match_tree(call);
1224     if (C->failing())  return NULL;
1225     if( m == NULL ) { Matcher::soft_match_failure(); return NULL; }
1226 
1227     // Copy data from the Ideal SafePoint to the machine version
1228     mcall = m->as_MachCall();
1229 
1230     mcall->set_tf(         call->tf());
1231     mcall->set_entry_point(call->entry_point());
1232     mcall->set_cnt(        call->cnt());
1233 
1234     if( mcall->is_MachCallJava() ) {
1235       MachCallJavaNode *mcall_java  = mcall->as_MachCallJava();
1236       const CallJavaNode *call_java =  call->as_CallJava();
1237       assert(call_java->validate_symbolic_info(), "inconsistent info");
1238       method = call_java->method();
1239       mcall_java->_method = method;
1240       mcall_java->_bci = call_java->_bci;
1241       mcall_java->_optimized_virtual = call_java->is_optimized_virtual();
1242       is_method_handle_invoke = call_java->is_method_handle_invoke();
1243       mcall_java->_method_handle_invoke = is_method_handle_invoke;
1244       mcall_java->_override_symbolic_info = call_java->override_symbolic_info();
1245       if (is_method_handle_invoke) {
1246         C->set_has_method_handle_invokes(true);
1247       }
1248       if( mcall_java->is_MachCallStaticJava() )
1249         mcall_java->as_MachCallStaticJava()->_name =
1250          call_java->as_CallStaticJava()->_name;
1251       if( mcall_java->is_MachCallDynamicJava() )
1252         mcall_java->as_MachCallDynamicJava()->_vtable_index =
1253          call_java->as_CallDynamicJava()->_vtable_index;
1254     }
1255     else if( mcall->is_MachCallRuntime() ) {
1256       mcall->as_MachCallRuntime()->_name = call->as_CallRuntime()->_name;
1257     }
1258     msfpt = mcall;
1259   }
1260   // This is a non-call safepoint
1261   else {
1262     call = NULL;
1263     domain = NULL;
1264     MachNode *mn = match_tree(sfpt);
1265     if (C->failing())  return NULL;
1266     msfpt = mn->as_MachSafePoint();
1267     cnt = TypeFunc::Parms;
1268   }
1269 
1270   // Advertise the correct memory effects (for anti-dependence computation).
1271   msfpt->set_adr_type(sfpt->adr_type());
1272 
1273   // Allocate a private array of RegMasks.  These RegMasks are not shared.
1274   msfpt->_in_rms = NEW_RESOURCE_ARRAY( RegMask, cnt );
1275   // Empty them all.
1276   for (uint i = 0; i < cnt; i++) ::new (&(msfpt->_in_rms[i])) RegMask();
1277 
1278   // Do all the pre-defined non-Empty register masks
1279   msfpt->_in_rms[TypeFunc::ReturnAdr] = _return_addr_mask;
1280   msfpt->_in_rms[TypeFunc::FramePtr ] = c_frame_ptr_mask;
1281 
1282   // Place first outgoing argument can possibly be put.
1283   OptoReg::Name begin_out_arg_area = OptoReg::add(_new_SP, C->out_preserve_stack_slots());
1284   assert( is_even(begin_out_arg_area), "" );
1285   // Compute max outgoing register number per call site.
1286   OptoReg::Name out_arg_limit_per_call = begin_out_arg_area;
1287   // Calls to C may hammer extra stack slots above and beyond any arguments.
1288   // These are usually backing store for register arguments for varargs.
1289   if( call != NULL && call->is_CallRuntime() )
1290     out_arg_limit_per_call = OptoReg::add(out_arg_limit_per_call,C->varargs_C_out_slots_killed());
1291 
1292 
1293   // Do the normal argument list (parameters) register masks
1294   // Null entry point is a special cast where the target of the call
1295   // is in a register.
1296   int adj = (call != NULL && call->entry_point() == NULL) ? 1 : 0;
1297   int argcnt = cnt - TypeFunc::Parms - adj;
1298   if( argcnt > 0 ) {          // Skip it all if we have no args
1299     BasicType *sig_bt  = NEW_RESOURCE_ARRAY( BasicType, argcnt );
1300     VMRegPair *parm_regs = NEW_RESOURCE_ARRAY( VMRegPair, argcnt );
1301     int i;
1302     for( i = 0; i < argcnt; i++ ) {
1303       sig_bt[i] = domain->field_at(i+TypeFunc::Parms+adj)->basic_type();
1304     }
1305     // V-call to pick proper calling convention
1306     call->calling_convention( sig_bt, parm_regs, argcnt );
1307 
1308 #ifdef ASSERT
1309     // Sanity check users' calling convention.  Really handy during
1310     // the initial porting effort.  Fairly expensive otherwise.
1311     { for (int i = 0; i<argcnt; i++) {
1312       if( !parm_regs[i].first()->is_valid() &&
1313           !parm_regs[i].second()->is_valid() ) continue;
1314       VMReg reg1 = parm_regs[i].first();
1315       VMReg reg2 = parm_regs[i].second();
1316       for (int j = 0; j < i; j++) {
1317         if( !parm_regs[j].first()->is_valid() &&
1318             !parm_regs[j].second()->is_valid() ) continue;
1319         VMReg reg3 = parm_regs[j].first();
1320         VMReg reg4 = parm_regs[j].second();
1321         if( !reg1->is_valid() ) {
1322           assert( !reg2->is_valid(), "valid halvsies" );
1323         } else if( !reg3->is_valid() ) {
1324           assert( !reg4->is_valid(), "valid halvsies" );
1325         } else {
1326           assert( reg1 != reg2, "calling conv. must produce distinct regs");
1327           assert( reg1 != reg3, "calling conv. must produce distinct regs");
1328           assert( reg1 != reg4, "calling conv. must produce distinct regs");
1329           assert( reg2 != reg3, "calling conv. must produce distinct regs");
1330           assert( reg2 != reg4 || !reg2->is_valid(), "calling conv. must produce distinct regs");
1331           assert( reg3 != reg4, "calling conv. must produce distinct regs");
1332         }
1333       }
1334     }
1335     }
1336 #endif
1337 
1338     // Visit each argument.  Compute its outgoing register mask.
1339     // Return results now can have 2 bits returned.
1340     // Compute max over all outgoing arguments both per call-site
1341     // and over the entire method.
1342     for( i = 0; i < argcnt; i++ ) {
1343       // Address of incoming argument mask to fill in
1344       RegMask *rm = &mcall->_in_rms[i+TypeFunc::Parms+adj];
1345       if( !parm_regs[i].first()->is_valid() &&
1346           !parm_regs[i].second()->is_valid() ) {
1347         continue;               // Avoid Halves
1348       }
1349       // Grab first register, adjust stack slots and insert in mask.
1350       OptoReg::Name reg1 = warp_outgoing_stk_arg(parm_regs[i].first(), begin_out_arg_area, out_arg_limit_per_call );
1351       if (OptoReg::is_valid(reg1)) {
1352         rm->Insert( reg1 );
1353       }
1354       // Grab second register (if any), adjust stack slots and insert in mask.
1355       OptoReg::Name reg2 = warp_outgoing_stk_arg(parm_regs[i].second(), begin_out_arg_area, out_arg_limit_per_call );
1356       if (OptoReg::is_valid(reg2)) {
1357         rm->Insert( reg2 );
1358       }
1359     } // End of for all arguments
1360 
1361     // Compute number of stack slots needed to restore stack in case of
1362     // Pascal-style argument popping.
1363     mcall->_argsize = out_arg_limit_per_call - begin_out_arg_area;
1364   }
1365 
1366   // Compute the max stack slot killed by any call.  These will not be
1367   // available for debug info, and will be used to adjust FIRST_STACK_mask
1368   // after all call sites have been visited.
1369   if( _out_arg_limit < out_arg_limit_per_call)
1370     _out_arg_limit = out_arg_limit_per_call;
1371 
1372   if (mcall) {
1373     // Kill the outgoing argument area, including any non-argument holes and
1374     // any legacy C-killed slots.  Use Fat-Projections to do the killing.
1375     // Since the max-per-method covers the max-per-call-site and debug info
1376     // is excluded on the max-per-method basis, debug info cannot land in
1377     // this killed area.
1378     uint r_cnt = mcall->tf()->range_sig()->cnt();
1379     MachProjNode *proj = new MachProjNode( mcall, r_cnt+10000, RegMask::Empty, MachProjNode::fat_proj );
1380     if (!RegMask::can_represent_arg(OptoReg::Name(out_arg_limit_per_call-1))) {
1381       C->record_method_not_compilable("unsupported outgoing calling sequence");
1382     } else {
1383       for (int i = begin_out_arg_area; i < out_arg_limit_per_call; i++)
1384         proj->_rout.Insert(OptoReg::Name(i));
1385     }
1386     if (proj->_rout.is_NotEmpty()) {
1387       push_projection(proj);
1388     }
1389   }
1390   // Transfer the safepoint information from the call to the mcall
1391   // Move the JVMState list
1392   msfpt->set_jvms(sfpt->jvms());
1393   for (JVMState* jvms = msfpt->jvms(); jvms; jvms = jvms->caller()) {
1394     jvms->set_map(sfpt);
1395   }
1396 
1397   // Debug inputs begin just after the last incoming parameter
1398   assert((mcall == NULL) || (mcall->jvms() == NULL) ||
1399          (mcall->jvms()->debug_start() + mcall->_jvmadj == mcall->tf()->domain_cc()->cnt()), "");
1400 
1401   // Move the OopMap
1402   msfpt->_oop_map = sfpt->_oop_map;
1403 
1404   // Add additional edges.
1405   if (msfpt->mach_constant_base_node_input() != (uint)-1 && !msfpt->is_MachCallLeaf()) {
1406     // For these calls we can not add MachConstantBase in expand(), as the
1407     // ins are not complete then.
1408     msfpt->ins_req(msfpt->mach_constant_base_node_input(), C->mach_constant_base_node());
1409     if (msfpt->jvms() &&
1410         msfpt->mach_constant_base_node_input() <= msfpt->jvms()->debug_start() + msfpt->_jvmadj) {
1411       // We added an edge before jvms, so we must adapt the position of the ins.
1412       msfpt->jvms()->adapt_position(+1);
1413     }
1414   }
1415 
1416   // Registers killed by the call are set in the local scheduling pass
1417   // of Global Code Motion.
1418   return msfpt;
1419 }
1420 
1421 //---------------------------match_tree----------------------------------------
1422 // Match a Ideal Node DAG - turn it into a tree; Label & Reduce.  Used as part
1423 // of the whole-sale conversion from Ideal to Mach Nodes.  Also used for
1424 // making GotoNodes while building the CFG and in init_spill_mask() to identify
1425 // a Load's result RegMask for memoization in idealreg2regmask[]
1426 MachNode *Matcher::match_tree( const Node *n ) {
1427   assert( n->Opcode() != Op_Phi, "cannot match" );
1428   assert( !n->is_block_start(), "cannot match" );
1429   // Set the mark for all locally allocated State objects.
1430   // When this call returns, the _states_arena arena will be reset
1431   // freeing all State objects.
1432   ResourceMark rm( &_states_arena );
1433 
1434   LabelRootDepth = 0;
1435 
1436   // StoreNodes require their Memory input to match any LoadNodes
1437   Node *mem = n->is_Store() ? n->in(MemNode::Memory) : (Node*)1 ;
1438 #ifdef ASSERT
1439   Node* save_mem_node = _mem_node;
1440   _mem_node = n->is_Store() ? (Node*)n : NULL;
1441 #endif
1442   // State object for root node of match tree
1443   // Allocate it on _states_arena - stack allocation can cause stack overflow.
1444   State *s = new (&_states_arena) State;
1445   s->_kids[0] = NULL;
1446   s->_kids[1] = NULL;
1447   s->_leaf = (Node*)n;
1448   // Label the input tree, allocating labels from top-level arena
1449   Label_Root( n, s, n->in(0), mem );
1450   if (C->failing())  return NULL;
1451 
1452   // The minimum cost match for the whole tree is found at the root State
1453   uint mincost = max_juint;
1454   uint cost = max_juint;
1455   uint i;
1456   for( i = 0; i < NUM_OPERANDS; i++ ) {
1457     if( s->valid(i) &&                // valid entry and
1458         s->_cost[i] < cost &&         // low cost and
1459         s->_rule[i] >= NUM_OPERANDS ) // not an operand
1460       cost = s->_cost[mincost=i];
1461   }
1462   if (mincost == max_juint) {
1463 #ifndef PRODUCT
1464     tty->print("No matching rule for:");
1465     s->dump();
1466 #endif
1467     Matcher::soft_match_failure();
1468     return NULL;
1469   }
1470   // Reduce input tree based upon the state labels to machine Nodes
1471   MachNode *m = ReduceInst( s, s->_rule[mincost], mem );
1472 #ifdef ASSERT
1473   _old2new_map.map(n->_idx, m);
1474   _new2old_map.map(m->_idx, (Node*)n);
1475 #endif
1476 
1477   // Add any Matcher-ignored edges
1478   uint cnt = n->req();
1479   uint start = 1;
1480   if( mem != (Node*)1 ) start = MemNode::Memory+1;
1481   if( n->is_AddP() ) {
1482     assert( mem == (Node*)1, "" );
1483     start = AddPNode::Base+1;
1484   }
1485   for( i = start; i < cnt; i++ ) {
1486     if( !n->match_edge(i) ) {
1487       if( i < m->req() )
1488         m->ins_req( i, n->in(i) );
1489       else
1490         m->add_req( n->in(i) );
1491     }
1492   }
1493 
1494   debug_only( _mem_node = save_mem_node; )
1495   return m;
1496 }
1497 
1498 
1499 //------------------------------match_into_reg---------------------------------
1500 // Choose to either match this Node in a register or part of the current
1501 // match tree.  Return true for requiring a register and false for matching
1502 // as part of the current match tree.
1503 static bool match_into_reg( const Node *n, Node *m, Node *control, int i, bool shared ) {
1504 
1505   const Type *t = m->bottom_type();
1506 
1507   if (t->singleton()) {
1508     // Never force constants into registers.  Allow them to match as
1509     // constants or registers.  Copies of the same value will share
1510     // the same register.  See find_shared_node.
1511     return false;
1512   } else {                      // Not a constant
1513     // Stop recursion if they have different Controls.
1514     Node* m_control = m->in(0);
1515     // Control of load's memory can post-dominates load's control.
1516     // So use it since load can't float above its memory.
1517     Node* mem_control = (m->is_Load()) ? m->in(MemNode::Memory)->in(0) : NULL;
1518     if (control && m_control && control != m_control && control != mem_control) {
1519 
1520       // Actually, we can live with the most conservative control we
1521       // find, if it post-dominates the others.  This allows us to
1522       // pick up load/op/store trees where the load can float a little
1523       // above the store.
1524       Node *x = control;
1525       const uint max_scan = 6;  // Arbitrary scan cutoff
1526       uint j;
1527       for (j=0; j<max_scan; j++) {
1528         if (x->is_Region())     // Bail out at merge points
1529           return true;
1530         x = x->in(0);
1531         if (x == m_control)     // Does 'control' post-dominate
1532           break;                // m->in(0)?  If so, we can use it
1533         if (x == mem_control)   // Does 'control' post-dominate
1534           break;                // mem_control?  If so, we can use it
1535       }
1536       if (j == max_scan)        // No post-domination before scan end?
1537         return true;            // Then break the match tree up
1538     }
1539     if ((m->is_DecodeN() && Matcher::narrow_oop_use_complex_address()) ||
1540         (m->is_DecodeNKlass() && Matcher::narrow_klass_use_complex_address())) {
1541       // These are commonly used in address expressions and can
1542       // efficiently fold into them on X64 in some cases.
1543       return false;
1544     }
1545   }
1546 
1547   // Not forceable cloning.  If shared, put it into a register.
1548   return shared;
1549 }
1550 
1551 
1552 //------------------------------Instruction Selection--------------------------
1553 // Label method walks a "tree" of nodes, using the ADLC generated DFA to match
1554 // ideal nodes to machine instructions.  Trees are delimited by shared Nodes,
1555 // things the Matcher does not match (e.g., Memory), and things with different
1556 // Controls (hence forced into different blocks).  We pass in the Control
1557 // selected for this entire State tree.
1558 
1559 // The Matcher works on Trees, but an Intel add-to-memory requires a DAG: the
1560 // Store and the Load must have identical Memories (as well as identical
1561 // pointers).  Since the Matcher does not have anything for Memory (and
1562 // does not handle DAGs), I have to match the Memory input myself.  If the
1563 // Tree root is a Store, I require all Loads to have the identical memory.
1564 Node *Matcher::Label_Root( const Node *n, State *svec, Node *control, const Node *mem){
1565   // Since Label_Root is a recursive function, its possible that we might run
1566   // out of stack space.  See bugs 6272980 & 6227033 for more info.
1567   LabelRootDepth++;
1568   if (LabelRootDepth > MaxLabelRootDepth) {
1569     C->record_method_not_compilable("Out of stack space, increase MaxLabelRootDepth");
1570     return NULL;
1571   }
1572   uint care = 0;                // Edges matcher cares about
1573   uint cnt = n->req();
1574   uint i = 0;
1575 
1576   // Examine children for memory state
1577   // Can only subsume a child into your match-tree if that child's memory state
1578   // is not modified along the path to another input.
1579   // It is unsafe even if the other inputs are separate roots.
1580   Node *input_mem = NULL;
1581   for( i = 1; i < cnt; i++ ) {
1582     if( !n->match_edge(i) ) continue;
1583     Node *m = n->in(i);         // Get ith input
1584     assert( m, "expect non-null children" );
1585     if( m->is_Load() ) {
1586       if( input_mem == NULL ) {
1587         input_mem = m->in(MemNode::Memory);
1588       } else if( input_mem != m->in(MemNode::Memory) ) {
1589         input_mem = NodeSentinel;
1590       }
1591     }
1592   }
1593 
1594   for( i = 1; i < cnt; i++ ){// For my children
1595     if( !n->match_edge(i) ) continue;
1596     Node *m = n->in(i);         // Get ith input
1597     // Allocate states out of a private arena
1598     State *s = new (&_states_arena) State;
1599     svec->_kids[care++] = s;
1600     assert( care <= 2, "binary only for now" );
1601 
1602     // Recursively label the State tree.
1603     s->_kids[0] = NULL;
1604     s->_kids[1] = NULL;
1605     s->_leaf = m;
1606 
1607     // Check for leaves of the State Tree; things that cannot be a part of
1608     // the current tree.  If it finds any, that value is matched as a
1609     // register operand.  If not, then the normal matching is used.
1610     if( match_into_reg(n, m, control, i, is_shared(m)) ||
1611         //
1612         // Stop recursion if this is LoadNode and the root of this tree is a
1613         // StoreNode and the load & store have different memories.
1614         ((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem) ||
1615         // Can NOT include the match of a subtree when its memory state
1616         // is used by any of the other subtrees
1617         (input_mem == NodeSentinel) ) {
1618       // Print when we exclude matching due to different memory states at input-loads
1619       if (PrintOpto && (Verbose && WizardMode) && (input_mem == NodeSentinel)
1620         && !((mem!=(Node*)1) && m->is_Load() && m->in(MemNode::Memory) != mem)) {
1621         tty->print_cr("invalid input_mem");
1622       }
1623       // Switch to a register-only opcode; this value must be in a register
1624       // and cannot be subsumed as part of a larger instruction.
1625       s->DFA( m->ideal_reg(), m );
1626 
1627     } else {
1628       // If match tree has no control and we do, adopt it for entire tree
1629       if( control == NULL && m->in(0) != NULL && m->req() > 1 )
1630         control = m->in(0);         // Pick up control
1631       // Else match as a normal part of the match tree.
1632       control = Label_Root(m,s,control,mem);
1633       if (C->failing()) return NULL;
1634     }
1635   }
1636 
1637 
1638   // Call DFA to match this node, and return
1639   svec->DFA( n->Opcode(), n );
1640 
1641 #ifdef ASSERT
1642   uint x;
1643   for( x = 0; x < _LAST_MACH_OPER; x++ )
1644     if( svec->valid(x) )
1645       break;
1646 
1647   if (x >= _LAST_MACH_OPER) {
1648     n->dump();
1649     svec->dump();
1650     assert( false, "bad AD file" );
1651   }
1652 #endif
1653   return control;
1654 }
1655 
1656 
1657 // Con nodes reduced using the same rule can share their MachNode
1658 // which reduces the number of copies of a constant in the final
1659 // program.  The register allocator is free to split uses later to
1660 // split live ranges.
1661 MachNode* Matcher::find_shared_node(Node* leaf, uint rule) {
1662   if (!leaf->is_Con() && !leaf->is_DecodeNarrowPtr()) return NULL;
1663 
1664   // See if this Con has already been reduced using this rule.
1665   if (_shared_nodes.Size() <= leaf->_idx) return NULL;
1666   MachNode* last = (MachNode*)_shared_nodes.at(leaf->_idx);
1667   if (last != NULL && rule == last->rule()) {
1668     // Don't expect control change for DecodeN
1669     if (leaf->is_DecodeNarrowPtr())
1670       return last;
1671     // Get the new space root.
1672     Node* xroot = new_node(C->root());
1673     if (xroot == NULL) {
1674       // This shouldn't happen give the order of matching.
1675       return NULL;
1676     }
1677 
1678     // Shared constants need to have their control be root so they
1679     // can be scheduled properly.
1680     Node* control = last->in(0);
1681     if (control != xroot) {
1682       if (control == NULL || control == C->root()) {
1683         last->set_req(0, xroot);
1684       } else {
1685         assert(false, "unexpected control");
1686         return NULL;
1687       }
1688     }
1689     return last;
1690   }
1691   return NULL;
1692 }
1693 
1694 
1695 //------------------------------ReduceInst-------------------------------------
1696 // Reduce a State tree (with given Control) into a tree of MachNodes.
1697 // This routine (and it's cohort ReduceOper) convert Ideal Nodes into
1698 // complicated machine Nodes.  Each MachNode covers some tree of Ideal Nodes.
1699 // Each MachNode has a number of complicated MachOper operands; each
1700 // MachOper also covers a further tree of Ideal Nodes.
1701 
1702 // The root of the Ideal match tree is always an instruction, so we enter
1703 // the recursion here.  After building the MachNode, we need to recurse
1704 // the tree checking for these cases:
1705 // (1) Child is an instruction -
1706 //     Build the instruction (recursively), add it as an edge.
1707 //     Build a simple operand (register) to hold the result of the instruction.
1708 // (2) Child is an interior part of an instruction -
1709 //     Skip over it (do nothing)
1710 // (3) Child is the start of a operand -
1711 //     Build the operand, place it inside the instruction
1712 //     Call ReduceOper.
1713 MachNode *Matcher::ReduceInst( State *s, int rule, Node *&mem ) {
1714   assert( rule >= NUM_OPERANDS, "called with operand rule" );
1715 
1716   MachNode* shared_node = find_shared_node(s->_leaf, rule);
1717   if (shared_node != NULL) {
1718     return shared_node;
1719   }
1720 
1721   // Build the object to represent this state & prepare for recursive calls
1722   MachNode *mach = s->MachNodeGenerator(rule);
1723   guarantee(mach != NULL, "Missing MachNode");
1724   mach->_opnds[0] = s->MachOperGenerator(_reduceOp[rule]);
1725   assert( mach->_opnds[0] != NULL, "Missing result operand" );
1726   Node *leaf = s->_leaf;
1727   // Check for instruction or instruction chain rule
1728   if( rule >= _END_INST_CHAIN_RULE || rule < _BEGIN_INST_CHAIN_RULE ) {
1729     assert(C->node_arena()->contains(s->_leaf) || !has_new_node(s->_leaf),
1730            "duplicating node that's already been matched");
1731     // Instruction
1732     mach->add_req( leaf->in(0) ); // Set initial control
1733     // Reduce interior of complex instruction
1734     ReduceInst_Interior( s, rule, mem, mach, 1 );
1735   } else {
1736     // Instruction chain rules are data-dependent on their inputs
1737     mach->add_req(0);             // Set initial control to none
1738     ReduceInst_Chain_Rule( s, rule, mem, mach );
1739   }
1740 
1741   // If a Memory was used, insert a Memory edge
1742   if( mem != (Node*)1 ) {
1743     mach->ins_req(MemNode::Memory,mem);
1744 #ifdef ASSERT
1745     // Verify adr type after matching memory operation
1746     const MachOper* oper = mach->memory_operand();
1747     if (oper != NULL && oper != (MachOper*)-1) {
1748       // It has a unique memory operand.  Find corresponding ideal mem node.
1749       Node* m = NULL;
1750       if (leaf->is_Mem()) {
1751         m = leaf;
1752       } else {
1753         m = _mem_node;
1754         assert(m != NULL && m->is_Mem(), "expecting memory node");
1755       }
1756       const Type* mach_at = mach->adr_type();
1757       // DecodeN node consumed by an address may have different type
1758       // than its input. Don't compare types for such case.
1759       if (m->adr_type() != mach_at &&
1760           (m->in(MemNode::Address)->is_DecodeNarrowPtr() ||
1761            (m->in(MemNode::Address)->is_AddP() &&
1762             m->in(MemNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()) ||
1763            (m->in(MemNode::Address)->is_AddP() &&
1764             m->in(MemNode::Address)->in(AddPNode::Address)->is_AddP() &&
1765             m->in(MemNode::Address)->in(AddPNode::Address)->in(AddPNode::Address)->is_DecodeNarrowPtr()))) {
1766         mach_at = m->adr_type();
1767       }
1768       if (m->adr_type() != mach_at) {
1769         m->dump();
1770         tty->print_cr("mach:");
1771         mach->dump(1);
1772       }
1773       assert(m->adr_type() == mach_at, "matcher should not change adr type");
1774     }
1775 #endif
1776   }
1777 
1778   // If the _leaf is an AddP, insert the base edge
1779   if (leaf->is_AddP()) {
1780     mach->ins_req(AddPNode::Base,leaf->in(AddPNode::Base));
1781   }
1782 
1783   uint number_of_projections_prior = number_of_projections();
1784 
1785   // Perform any 1-to-many expansions required
1786   MachNode *ex = mach->Expand(s, _projection_list, mem);
1787   if (ex != mach) {
1788     assert(ex->ideal_reg() == mach->ideal_reg(), "ideal types should match");
1789     if( ex->in(1)->is_Con() )
1790       ex->in(1)->set_req(0, C->root());
1791     // Remove old node from the graph
1792     for( uint i=0; i<mach->req(); i++ ) {
1793       mach->set_req(i,NULL);
1794     }
1795 #ifdef ASSERT
1796     _new2old_map.map(ex->_idx, s->_leaf);
1797 #endif
1798   }
1799 
1800   // PhaseChaitin::fixup_spills will sometimes generate spill code
1801   // via the matcher.  By the time, nodes have been wired into the CFG,
1802   // and any further nodes generated by expand rules will be left hanging
1803   // in space, and will not get emitted as output code.  Catch this.
1804   // Also, catch any new register allocation constraints ("projections")
1805   // generated belatedly during spill code generation.
1806   if (_allocation_started) {
1807     guarantee(ex == mach, "no expand rules during spill generation");
1808     guarantee(number_of_projections_prior == number_of_projections(), "no allocation during spill generation");
1809   }
1810 
1811   if (leaf->is_Con() || leaf->is_DecodeNarrowPtr()) {
1812     // Record the con for sharing
1813     _shared_nodes.map(leaf->_idx, ex);
1814   }
1815 
1816   return ex;
1817 }
1818 
1819 void Matcher::handle_precedence_edges(Node* n, MachNode *mach) {
1820   for (uint i = n->req(); i < n->len(); i++) {
1821     if (n->in(i) != NULL) {
1822       mach->add_prec(n->in(i));
1823     }
1824   }
1825 }
1826 
1827 void Matcher::ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach ) {
1828   // 'op' is what I am expecting to receive
1829   int op = _leftOp[rule];
1830   // Operand type to catch childs result
1831   // This is what my child will give me.
1832   int opnd_class_instance = s->_rule[op];
1833   // Choose between operand class or not.
1834   // This is what I will receive.
1835   int catch_op = (FIRST_OPERAND_CLASS <= op && op < NUM_OPERANDS) ? opnd_class_instance : op;
1836   // New rule for child.  Chase operand classes to get the actual rule.
1837   int newrule = s->_rule[catch_op];
1838 
1839   if( newrule < NUM_OPERANDS ) {
1840     // Chain from operand or operand class, may be output of shared node
1841     assert( 0 <= opnd_class_instance && opnd_class_instance < NUM_OPERANDS,
1842             "Bad AD file: Instruction chain rule must chain from operand");
1843     // Insert operand into array of operands for this instruction
1844     mach->_opnds[1] = s->MachOperGenerator(opnd_class_instance);
1845 
1846     ReduceOper( s, newrule, mem, mach );
1847   } else {
1848     // Chain from the result of an instruction
1849     assert( newrule >= _LAST_MACH_OPER, "Do NOT chain from internal operand");
1850     mach->_opnds[1] = s->MachOperGenerator(_reduceOp[catch_op]);
1851     Node *mem1 = (Node*)1;
1852     debug_only(Node *save_mem_node = _mem_node;)
1853     mach->add_req( ReduceInst(s, newrule, mem1) );
1854     debug_only(_mem_node = save_mem_node;)
1855   }
1856   return;
1857 }
1858 
1859 
1860 uint Matcher::ReduceInst_Interior( State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds ) {
1861   handle_precedence_edges(s->_leaf, mach);
1862 
1863   if( s->_leaf->is_Load() ) {
1864     Node *mem2 = s->_leaf->in(MemNode::Memory);
1865     assert( mem == (Node*)1 || mem == mem2, "multiple Memories being matched at once?" );
1866     debug_only( if( mem == (Node*)1 ) _mem_node = s->_leaf;)
1867     mem = mem2;
1868   }
1869   if( s->_leaf->in(0) != NULL && s->_leaf->req() > 1) {
1870     if( mach->in(0) == NULL )
1871       mach->set_req(0, s->_leaf->in(0));
1872   }
1873 
1874   // Now recursively walk the state tree & add operand list.
1875   for( uint i=0; i<2; i++ ) {   // binary tree
1876     State *newstate = s->_kids[i];
1877     if( newstate == NULL ) break;      // Might only have 1 child
1878     // 'op' is what I am expecting to receive
1879     int op;
1880     if( i == 0 ) {
1881       op = _leftOp[rule];
1882     } else {
1883       op = _rightOp[rule];
1884     }
1885     // Operand type to catch childs result
1886     // This is what my child will give me.
1887     int opnd_class_instance = newstate->_rule[op];
1888     // Choose between operand class or not.
1889     // This is what I will receive.
1890     int catch_op = (op >= FIRST_OPERAND_CLASS && op < NUM_OPERANDS) ? opnd_class_instance : op;
1891     // New rule for child.  Chase operand classes to get the actual rule.
1892     int newrule = newstate->_rule[catch_op];
1893 
1894     if( newrule < NUM_OPERANDS ) { // Operand/operandClass or internalOp/instruction?
1895       // Operand/operandClass
1896       // Insert operand into array of operands for this instruction
1897       mach->_opnds[num_opnds++] = newstate->MachOperGenerator(opnd_class_instance);
1898       ReduceOper( newstate, newrule, mem, mach );
1899 
1900     } else {                    // Child is internal operand or new instruction
1901       if( newrule < _LAST_MACH_OPER ) { // internal operand or instruction?
1902         // internal operand --> call ReduceInst_Interior
1903         // Interior of complex instruction.  Do nothing but recurse.
1904         num_opnds = ReduceInst_Interior( newstate, newrule, mem, mach, num_opnds );
1905       } else {
1906         // instruction --> call build operand(  ) to catch result
1907         //             --> ReduceInst( newrule )
1908         mach->_opnds[num_opnds++] = s->MachOperGenerator(_reduceOp[catch_op]);
1909         Node *mem1 = (Node*)1;
1910         debug_only(Node *save_mem_node = _mem_node;)
1911         mach->add_req( ReduceInst( newstate, newrule, mem1 ) );
1912         debug_only(_mem_node = save_mem_node;)
1913       }
1914     }
1915     assert( mach->_opnds[num_opnds-1], "" );
1916   }
1917   return num_opnds;
1918 }
1919 
1920 // This routine walks the interior of possible complex operands.
1921 // At each point we check our children in the match tree:
1922 // (1) No children -
1923 //     We are a leaf; add _leaf field as an input to the MachNode
1924 // (2) Child is an internal operand -
1925 //     Skip over it ( do nothing )
1926 // (3) Child is an instruction -
1927 //     Call ReduceInst recursively and
1928 //     and instruction as an input to the MachNode
1929 void Matcher::ReduceOper( State *s, int rule, Node *&mem, MachNode *mach ) {
1930   assert( rule < _LAST_MACH_OPER, "called with operand rule" );
1931   State *kid = s->_kids[0];
1932   assert( kid == NULL || s->_leaf->in(0) == NULL, "internal operands have no control" );
1933 
1934   // Leaf?  And not subsumed?
1935   if( kid == NULL && !_swallowed[rule] ) {
1936     mach->add_req( s->_leaf );  // Add leaf pointer
1937     return;                     // Bail out
1938   }
1939 
1940   if( s->_leaf->is_Load() ) {
1941     assert( mem == (Node*)1, "multiple Memories being matched at once?" );
1942     mem = s->_leaf->in(MemNode::Memory);
1943     debug_only(_mem_node = s->_leaf;)
1944   }
1945 
1946   handle_precedence_edges(s->_leaf, mach);
1947 
1948   if( s->_leaf->in(0) && s->_leaf->req() > 1) {
1949     if( !mach->in(0) )
1950       mach->set_req(0,s->_leaf->in(0));
1951     else {
1952       assert( s->_leaf->in(0) == mach->in(0), "same instruction, differing controls?" );
1953     }
1954   }
1955 
1956   for( uint i=0; kid != NULL && i<2; kid = s->_kids[1], i++ ) {   // binary tree
1957     int newrule;
1958     if( i == 0)
1959       newrule = kid->_rule[_leftOp[rule]];
1960     else
1961       newrule = kid->_rule[_rightOp[rule]];
1962 
1963     if( newrule < _LAST_MACH_OPER ) { // Operand or instruction?
1964       // Internal operand; recurse but do nothing else
1965       ReduceOper( kid, newrule, mem, mach );
1966 
1967     } else {                    // Child is a new instruction
1968       // Reduce the instruction, and add a direct pointer from this
1969       // machine instruction to the newly reduced one.
1970       Node *mem1 = (Node*)1;
1971       debug_only(Node *save_mem_node = _mem_node;)
1972       mach->add_req( ReduceInst( kid, newrule, mem1 ) );
1973       debug_only(_mem_node = save_mem_node;)
1974     }
1975   }
1976 }
1977 
1978 
1979 // -------------------------------------------------------------------------
1980 // Java-Java calling convention
1981 // (what you use when Java calls Java)
1982 
1983 //------------------------------find_receiver----------------------------------
1984 // For a given signature, return the OptoReg for parameter 0.
1985 OptoReg::Name Matcher::find_receiver( bool is_outgoing ) {
1986   VMRegPair regs;
1987   BasicType sig_bt = T_OBJECT;
1988   calling_convention(&sig_bt, &regs, 1, is_outgoing);
1989   // Return argument 0 register.  In the LP64 build pointers
1990   // take 2 registers, but the VM wants only the 'main' name.
1991   return OptoReg::as_OptoReg(regs.first());
1992 }
1993 
1994 // This function identifies sub-graphs in which a 'load' node is
1995 // input to two different nodes, and such that it can be matched
1996 // with BMI instructions like blsi, blsr, etc.
1997 // Example : for b = -a[i] & a[i] can be matched to blsi r32, m32.
1998 // The graph is (AndL (SubL Con0 LoadL*) LoadL*), where LoadL*
1999 // refers to the same node.
2000 #ifdef X86
2001 // Match the generic fused operations pattern (op1 (op2 Con{ConType} mop) mop)
2002 // This is a temporary solution until we make DAGs expressible in ADL.
2003 template<typename ConType>
2004 class FusedPatternMatcher {
2005   Node* _op1_node;
2006   Node* _mop_node;
2007   int _con_op;
2008 
2009   static int match_next(Node* n, int next_op, int next_op_idx) {
2010     if (n->in(1) == NULL || n->in(2) == NULL) {
2011       return -1;
2012     }
2013 
2014     if (next_op_idx == -1) { // n is commutative, try rotations
2015       if (n->in(1)->Opcode() == next_op) {
2016         return 1;
2017       } else if (n->in(2)->Opcode() == next_op) {
2018         return 2;
2019       }
2020     } else {
2021       assert(next_op_idx > 0 && next_op_idx <= 2, "Bad argument index");
2022       if (n->in(next_op_idx)->Opcode() == next_op) {
2023         return next_op_idx;
2024       }
2025     }
2026     return -1;
2027   }
2028 public:
2029   FusedPatternMatcher(Node* op1_node, Node *mop_node, int con_op) :
2030     _op1_node(op1_node), _mop_node(mop_node), _con_op(con_op) { }
2031 
2032   bool match(int op1, int op1_op2_idx,  // op1 and the index of the op1->op2 edge, -1 if op1 is commutative
2033              int op2, int op2_con_idx,  // op2 and the index of the op2->con edge, -1 if op2 is commutative
2034              typename ConType::NativeType con_value) {
2035     if (_op1_node->Opcode() != op1) {
2036       return false;
2037     }
2038     if (_mop_node->outcnt() > 2) {
2039       return false;
2040     }
2041     op1_op2_idx = match_next(_op1_node, op2, op1_op2_idx);
2042     if (op1_op2_idx == -1) {
2043       return false;
2044     }
2045     // Memory operation must be the other edge
2046     int op1_mop_idx = (op1_op2_idx & 1) + 1;
2047 
2048     // Check that the mop node is really what we want
2049     if (_op1_node->in(op1_mop_idx) == _mop_node) {
2050       Node *op2_node = _op1_node->in(op1_op2_idx);
2051       if (op2_node->outcnt() > 1) {
2052         return false;
2053       }
2054       assert(op2_node->Opcode() == op2, "Should be");
2055       op2_con_idx = match_next(op2_node, _con_op, op2_con_idx);
2056       if (op2_con_idx == -1) {
2057         return false;
2058       }
2059       // Memory operation must be the other edge
2060       int op2_mop_idx = (op2_con_idx & 1) + 1;
2061       // Check that the memory operation is the same node
2062       if (op2_node->in(op2_mop_idx) == _mop_node) {
2063         // Now check the constant
2064         const Type* con_type = op2_node->in(op2_con_idx)->bottom_type();
2065         if (con_type != Type::TOP && ConType::as_self(con_type)->get_con() == con_value) {
2066           return true;
2067         }
2068       }
2069     }
2070     return false;
2071   }
2072 };
2073 
2074 
2075 bool Matcher::is_bmi_pattern(Node *n, Node *m) {
2076   if (n != NULL && m != NULL) {
2077     if (m->Opcode() == Op_LoadI) {
2078       FusedPatternMatcher<TypeInt> bmii(n, m, Op_ConI);
2079       return bmii.match(Op_AndI, -1, Op_SubI,  1,  0)  ||
2080              bmii.match(Op_AndI, -1, Op_AddI, -1, -1)  ||
2081              bmii.match(Op_XorI, -1, Op_AddI, -1, -1);
2082     } else if (m->Opcode() == Op_LoadL) {
2083       FusedPatternMatcher<TypeLong> bmil(n, m, Op_ConL);
2084       return bmil.match(Op_AndL, -1, Op_SubL,  1,  0) ||
2085              bmil.match(Op_AndL, -1, Op_AddL, -1, -1) ||
2086              bmil.match(Op_XorL, -1, Op_AddL, -1, -1);
2087     }
2088   }
2089   return false;
2090 }
2091 #endif // X86
2092 
2093 bool Matcher::clone_base_plus_offset_address(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
2094   Node *off = m->in(AddPNode::Offset);
2095   if (off->is_Con()) {
2096     address_visited.test_set(m->_idx); // Flag as address_visited
2097     mstack.push(m->in(AddPNode::Address), Pre_Visit);
2098     // Clone X+offset as it also folds into most addressing expressions
2099     mstack.push(off, Visit);
2100     mstack.push(m->in(AddPNode::Base), Pre_Visit);
2101     return true;
2102   }
2103   return false;
2104 }
2105 
2106 // A method-klass-holder may be passed in the inline_cache_reg
2107 // and then expanded into the inline_cache_reg and a method_oop register
2108 //   defined in ad_<arch>.cpp
2109 
2110 //------------------------------find_shared------------------------------------
2111 // Set bits if Node is shared or otherwise a root
2112 void Matcher::find_shared( Node *n ) {
2113   // Allocate stack of size C->live_nodes() * 2 to avoid frequent realloc
2114   MStack mstack(C->live_nodes() * 2);
2115   // Mark nodes as address_visited if they are inputs to an address expression
2116   VectorSet address_visited(Thread::current()->resource_area());
2117   mstack.push(n, Visit);     // Don't need to pre-visit root node
2118   while (mstack.is_nonempty()) {
2119     n = mstack.node();       // Leave node on stack
2120     Node_State nstate = mstack.state();
2121     uint nop = n->Opcode();
2122     if (nstate == Pre_Visit) {
2123       if (address_visited.test(n->_idx)) { // Visited in address already?
2124         // Flag as visited and shared now.
2125         set_visited(n);
2126       }
2127       if (is_visited(n)) {   // Visited already?
2128         // Node is shared and has no reason to clone.  Flag it as shared.
2129         // This causes it to match into a register for the sharing.
2130         set_shared(n);       // Flag as shared and
2131         if (n->is_DecodeNarrowPtr()) {
2132           // Oop field/array element loads must be shared but since
2133           // they are shared through a DecodeN they may appear to have
2134           // a single use so force sharing here.
2135           set_shared(n->in(1));
2136         }
2137         mstack.pop();        // remove node from stack
2138         continue;
2139       }
2140       nstate = Visit; // Not already visited; so visit now
2141     }
2142     if (nstate == Visit) {
2143       mstack.set_state(Post_Visit);
2144       set_visited(n);   // Flag as visited now
2145       bool mem_op = false;
2146       int mem_addr_idx = MemNode::Address;
2147       bool gc_handled = BarrierSet::barrier_set()->barrier_set_c2()->matcher_find_shared_visit(this, mstack, n, nop, mem_op, mem_addr_idx);
2148       if (!gc_handled) {
2149         if (find_shared_visit(mstack, n, nop, mem_op, mem_addr_idx)) {
2150           continue;
2151         }
2152       }
2153       for(int i = n->req() - 1; i >= 0; --i) { // For my children
2154         Node *m = n->in(i); // Get ith input
2155         if (m == NULL) continue;  // Ignore NULLs
2156         uint mop = m->Opcode();
2157 
2158         // Must clone all producers of flags, or we will not match correctly.
2159         // Suppose a compare setting int-flags is shared (e.g., a switch-tree)
2160         // then it will match into an ideal Op_RegFlags.  Alas, the fp-flags
2161         // are also there, so we may match a float-branch to int-flags and
2162         // expect the allocator to haul the flags from the int-side to the
2163         // fp-side.  No can do.
2164         if( _must_clone[mop] ) {
2165           mstack.push(m, Visit);
2166           continue; // for(int i = ...)
2167         }
2168 
2169         // if 'n' and 'm' are part of a graph for BMI instruction, clone this node.
2170 #ifdef X86
2171         if (UseBMI1Instructions && is_bmi_pattern(n, m)) {
2172           mstack.push(m, Visit);
2173           continue;
2174         }
2175 #endif
2176 
2177         // Clone addressing expressions as they are "free" in memory access instructions
2178         if (mem_op && i == mem_addr_idx && mop == Op_AddP &&
2179             // When there are other uses besides address expressions
2180             // put it on stack and mark as shared.
2181             !is_visited(m)) {
2182           // Some inputs for address expression are not put on stack
2183           // to avoid marking them as shared and forcing them into register
2184           // if they are used only in address expressions.
2185           // But they should be marked as shared if there are other uses
2186           // besides address expressions.
2187 
2188           if (clone_address_expressions(m->as_AddP(), mstack, address_visited)) {
2189             continue;
2190           }
2191         }   // if( mem_op &&
2192         mstack.push(m, Pre_Visit);
2193       }     // for(int i = ...)
2194     }
2195     else if (nstate == Alt_Post_Visit) {
2196       mstack.pop(); // Remove node from stack
2197       // We cannot remove the Cmp input from the Bool here, as the Bool may be
2198       // shared and all users of the Bool need to move the Cmp in parallel.
2199       // This leaves both the Bool and the If pointing at the Cmp.  To
2200       // prevent the Matcher from trying to Match the Cmp along both paths
2201       // BoolNode::match_edge always returns a zero.
2202 
2203       // We reorder the Op_If in a pre-order manner, so we can visit without
2204       // accidentally sharing the Cmp (the Bool and the If make 2 users).
2205       n->add_req( n->in(1)->in(1) ); // Add the Cmp next to the Bool
2206     }
2207     else if (nstate == Post_Visit) {
2208       mstack.pop(); // Remove node from stack
2209 
2210       // Now hack a few special opcodes
2211       uint opcode = n->Opcode();
2212       bool gc_handled = BarrierSet::barrier_set()->barrier_set_c2()->matcher_find_shared_post_visit(this, n, opcode);
2213       if (!gc_handled) {
2214         find_shared_post_visit(n, opcode);
2215       }
2216     }
2217     else {
2218       ShouldNotReachHere();
2219     }
2220   } // end of while (mstack.is_nonempty())
2221 }
2222 
2223 bool Matcher::find_shared_visit(MStack& mstack, Node* n, uint opcode, bool& mem_op, int& mem_addr_idx) {
2224   switch(opcode) {  // Handle some opcodes special
2225     case Op_Phi:             // Treat Phis as shared roots
2226     case Op_Parm:
2227     case Op_Proj:            // All handled specially during matching
2228     case Op_SafePointScalarObject:
2229       set_shared(n);
2230       set_dontcare(n);
2231       break;
2232     case Op_If:
2233     case Op_CountedLoopEnd:
2234       mstack.set_state(Alt_Post_Visit); // Alternative way
2235       // Convert (If (Bool (CmpX A B))) into (If (Bool) (CmpX A B)).  Helps
2236       // with matching cmp/branch in 1 instruction.  The Matcher needs the
2237       // Bool and CmpX side-by-side, because it can only get at constants
2238       // that are at the leaves of Match trees, and the Bool's condition acts
2239       // as a constant here.
2240       mstack.push(n->in(1), Visit);         // Clone the Bool
2241       mstack.push(n->in(0), Pre_Visit);     // Visit control input
2242       return true; // while (mstack.is_nonempty())
2243     case Op_ConvI2D:         // These forms efficiently match with a prior
2244     case Op_ConvI2F:         //   Load but not a following Store
2245       if( n->in(1)->is_Load() &&        // Prior load
2246           n->outcnt() == 1 &&           // Not already shared
2247           n->unique_out()->is_Store() ) // Following store
2248         set_shared(n);       // Force it to be a root
2249       break;
2250     case Op_ReverseBytesI:
2251     case Op_ReverseBytesL:
2252       if( n->in(1)->is_Load() &&        // Prior load
2253           n->outcnt() == 1 )            // Not already shared
2254         set_shared(n);                  // Force it to be a root
2255       break;
2256     case Op_BoxLock:         // Cant match until we get stack-regs in ADLC
2257     case Op_IfFalse:
2258     case Op_IfTrue:
2259     case Op_MachProj:
2260     case Op_MergeMem:
2261     case Op_Catch:
2262     case Op_CatchProj:
2263     case Op_CProj:
2264     case Op_JumpProj:
2265     case Op_JProj:
2266     case Op_NeverBranch:
2267       set_dontcare(n);
2268       break;
2269     case Op_Jump:
2270       mstack.push(n->in(1), Pre_Visit);     // Switch Value (could be shared)
2271       mstack.push(n->in(0), Pre_Visit);     // Visit Control input
2272       return true;                             // while (mstack.is_nonempty())
2273     case Op_StrComp:
2274     case Op_StrEquals:
2275     case Op_StrIndexOf:
2276     case Op_StrIndexOfChar:
2277     case Op_AryEq:
2278     case Op_HasNegatives:
2279     case Op_StrInflatedCopy:
2280     case Op_StrCompressedCopy:
2281     case Op_EncodeISOArray:
2282     case Op_FmaD:
2283     case Op_FmaF:
2284     case Op_FmaVD:
2285     case Op_FmaVF:
2286       set_shared(n); // Force result into register (it will be anyways)
2287       break;
2288     case Op_ConP: {  // Convert pointers above the centerline to NUL
2289       TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2290       const TypePtr* tp = tn->type()->is_ptr();
2291       if (tp->_ptr == TypePtr::AnyNull) {
2292         tn->set_type(TypePtr::NULL_PTR);
2293       }
2294       break;
2295     }
2296     case Op_ConN: {  // Convert narrow pointers above the centerline to NUL
2297       TypeNode *tn = n->as_Type(); // Constants derive from type nodes
2298       const TypePtr* tp = tn->type()->make_ptr();
2299       if (tp && tp->_ptr == TypePtr::AnyNull) {
2300         tn->set_type(TypeNarrowOop::NULL_PTR);
2301       }
2302       break;
2303     }
2304     case Op_Binary:         // These are introduced in the Post_Visit state.
2305       ShouldNotReachHere();
2306       break;
2307     case Op_ClearArray:
2308     case Op_SafePoint:
2309       mem_op = true;
2310       break;
2311     default:
2312       if( n->is_Store() ) {
2313         // Do match stores, despite no ideal reg
2314         mem_op = true;
2315         break;
2316       }
2317       if( n->is_Mem() ) { // Loads and LoadStores
2318         mem_op = true;
2319         // Loads must be root of match tree due to prior load conflict
2320         if( C->subsume_loads() == false )
2321           set_shared(n);
2322       }
2323       // Fall into default case
2324       if( !n->ideal_reg() )
2325         set_dontcare(n);  // Unmatchable Nodes
2326   } // end_switch
2327   return false;
2328 }
2329 
2330 void Matcher::find_shared_post_visit(Node* n, uint opcode) {
2331   switch(opcode) {       // Handle some opcodes special
2332     case Op_StorePConditional:
2333     case Op_StoreIConditional:
2334     case Op_StoreLConditional:
2335     case Op_CompareAndExchangeB:
2336     case Op_CompareAndExchangeS:
2337     case Op_CompareAndExchangeI:
2338     case Op_CompareAndExchangeL:
2339     case Op_CompareAndExchangeP:
2340     case Op_CompareAndExchangeN:
2341     case Op_WeakCompareAndSwapB:
2342     case Op_WeakCompareAndSwapS:
2343     case Op_WeakCompareAndSwapI:
2344     case Op_WeakCompareAndSwapL:
2345     case Op_WeakCompareAndSwapP:
2346     case Op_WeakCompareAndSwapN:
2347     case Op_CompareAndSwapB:
2348     case Op_CompareAndSwapS:
2349     case Op_CompareAndSwapI:
2350     case Op_CompareAndSwapL:
2351     case Op_CompareAndSwapP:
2352     case Op_CompareAndSwapN: {   // Convert trinary to binary-tree
2353       Node* newval = n->in(MemNode::ValueIn);
2354       Node* oldval = n->in(LoadStoreConditionalNode::ExpectedIn);
2355       Node* pair = new BinaryNode(oldval, newval);
2356       n->set_req(MemNode::ValueIn, pair);
2357       n->del_req(LoadStoreConditionalNode::ExpectedIn);
2358       break;
2359     }
2360     case Op_CMoveD:              // Convert trinary to binary-tree
2361     case Op_CMoveF:
2362     case Op_CMoveI:
2363     case Op_CMoveL:
2364     case Op_CMoveN:
2365     case Op_CMoveP:
2366     case Op_CMoveVF:
2367     case Op_CMoveVD:  {
2368       // Restructure into a binary tree for Matching.  It's possible that
2369       // we could move this code up next to the graph reshaping for IfNodes
2370       // or vice-versa, but I do not want to debug this for Ladybird.
2371       // 10/2/2000 CNC.
2372       Node* pair1 = new BinaryNode(n->in(1), n->in(1)->in(1));
2373       n->set_req(1, pair1);
2374       Node* pair2 = new BinaryNode(n->in(2), n->in(3));
2375       n->set_req(2, pair2);
2376       n->del_req(3);
2377       break;
2378     }
2379     case Op_LoopLimit: {
2380       Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2381       n->set_req(1, pair1);
2382       n->set_req(2, n->in(3));
2383       n->del_req(3);
2384       break;
2385     }
2386     case Op_StrEquals:
2387     case Op_StrIndexOfChar: {
2388       Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2389       n->set_req(2, pair1);
2390       n->set_req(3, n->in(4));
2391       n->del_req(4);
2392       break;
2393     }
2394     case Op_StrComp:
2395     case Op_StrIndexOf: {
2396       Node* pair1 = new BinaryNode(n->in(2), n->in(3));
2397       n->set_req(2, pair1);
2398       Node* pair2 = new BinaryNode(n->in(4),n->in(5));
2399       n->set_req(3, pair2);
2400       n->del_req(5);
2401       n->del_req(4);
2402       break;
2403     }
2404     case Op_StrCompressedCopy:
2405     case Op_StrInflatedCopy:
2406     case Op_EncodeISOArray: {
2407       // Restructure into a binary tree for Matching.
2408       Node* pair = new BinaryNode(n->in(3), n->in(4));
2409       n->set_req(3, pair);
2410       n->del_req(4);
2411       break;
2412     }
2413     case Op_FmaD:
2414     case Op_FmaF:
2415     case Op_FmaVD:
2416     case Op_FmaVF: {
2417       // Restructure into a binary tree for Matching.
2418       Node* pair = new BinaryNode(n->in(1), n->in(2));
2419       n->set_req(2, pair);
2420       n->set_req(1, n->in(3));
2421       n->del_req(3);
2422       break;
2423     }
2424     case Op_MulAddS2I: {
2425       Node* pair1 = new BinaryNode(n->in(1), n->in(2));
2426       Node* pair2 = new BinaryNode(n->in(3), n->in(4));
2427       n->set_req(1, pair1);
2428       n->set_req(2, pair2);
2429       n->del_req(4);
2430       n->del_req(3);
2431       break;
2432     }
2433     case Op_ClearArray: {
2434       Node* pair = new BinaryNode(n->in(2), n->in(3));
2435       n->set_req(2, pair);
2436       n->set_req(3, n->in(4));
2437       n->del_req(4);
2438       break;
2439     }
2440     default:
2441       break;
2442   }
2443 }
2444 
2445 #ifdef ASSERT
2446 // machine-independent root to machine-dependent root
2447 void Matcher::dump_old2new_map() {
2448   _old2new_map.dump();
2449 }
2450 #endif
2451 
2452 //---------------------------collect_null_checks-------------------------------
2453 // Find null checks in the ideal graph; write a machine-specific node for
2454 // it.  Used by later implicit-null-check handling.  Actually collects
2455 // either an IfTrue or IfFalse for the common NOT-null path, AND the ideal
2456 // value being tested.
2457 void Matcher::collect_null_checks( Node *proj, Node *orig_proj ) {
2458   Node *iff = proj->in(0);
2459   if( iff->Opcode() == Op_If ) {
2460     // During matching If's have Bool & Cmp side-by-side
2461     BoolNode *b = iff->in(1)->as_Bool();
2462     Node *cmp = iff->in(2);
2463     int opc = cmp->Opcode();
2464     if (opc != Op_CmpP && opc != Op_CmpN) return;
2465 
2466     const Type* ct = cmp->in(2)->bottom_type();
2467     if (ct == TypePtr::NULL_PTR ||
2468         (opc == Op_CmpN && ct == TypeNarrowOop::NULL_PTR)) {
2469 
2470       bool push_it = false;
2471       if( proj->Opcode() == Op_IfTrue ) {
2472 #ifndef PRODUCT
2473         extern int all_null_checks_found;
2474         all_null_checks_found++;
2475 #endif
2476         if( b->_test._test == BoolTest::ne ) {
2477           push_it = true;
2478         }
2479       } else {
2480         assert( proj->Opcode() == Op_IfFalse, "" );
2481         if( b->_test._test == BoolTest::eq ) {
2482           push_it = true;
2483         }
2484       }
2485       if( push_it ) {
2486         _null_check_tests.push(proj);
2487         Node* val = cmp->in(1);
2488 #ifdef _LP64
2489         if (val->bottom_type()->isa_narrowoop() &&
2490             !Matcher::narrow_oop_use_complex_address()) {
2491           //
2492           // Look for DecodeN node which should be pinned to orig_proj.
2493           // On platforms (Sparc) which can not handle 2 adds
2494           // in addressing mode we have to keep a DecodeN node and
2495           // use it to do implicit NULL check in address.
2496           //
2497           // DecodeN node was pinned to non-null path (orig_proj) during
2498           // CastPP transformation in final_graph_reshaping_impl().
2499           //
2500           uint cnt = orig_proj->outcnt();
2501           for (uint i = 0; i < orig_proj->outcnt(); i++) {
2502             Node* d = orig_proj->raw_out(i);
2503             if (d->is_DecodeN() && d->in(1) == val) {
2504               val = d;
2505               val->set_req(0, NULL); // Unpin now.
2506               // Mark this as special case to distinguish from
2507               // a regular case: CmpP(DecodeN, NULL).
2508               val = (Node*)(((intptr_t)val) | 1);
2509               break;
2510             }
2511           }
2512         }
2513 #endif
2514         _null_check_tests.push(val);
2515       }
2516     }
2517   }
2518 }
2519 
2520 //---------------------------validate_null_checks------------------------------
2521 // Its possible that the value being NULL checked is not the root of a match
2522 // tree.  If so, I cannot use the value in an implicit null check.
2523 void Matcher::validate_null_checks( ) {
2524   uint cnt = _null_check_tests.size();
2525   for( uint i=0; i < cnt; i+=2 ) {
2526     Node *test = _null_check_tests[i];
2527     Node *val = _null_check_tests[i+1];
2528     bool is_decoden = ((intptr_t)val) & 1;
2529     val = (Node*)(((intptr_t)val) & ~1);
2530     if (has_new_node(val)) {
2531       Node* new_val = new_node(val);
2532       if (is_decoden) {
2533         assert(val->is_DecodeNarrowPtr() && val->in(0) == NULL, "sanity");
2534         // Note: new_val may have a control edge if
2535         // the original ideal node DecodeN was matched before
2536         // it was unpinned in Matcher::collect_null_checks().
2537         // Unpin the mach node and mark it.
2538         new_val->set_req(0, NULL);
2539         new_val = (Node*)(((intptr_t)new_val) | 1);
2540       }
2541       // Is a match-tree root, so replace with the matched value
2542       _null_check_tests.map(i+1, new_val);
2543     } else {
2544       // Yank from candidate list
2545       _null_check_tests.map(i+1,_null_check_tests[--cnt]);
2546       _null_check_tests.map(i,_null_check_tests[--cnt]);
2547       _null_check_tests.pop();
2548       _null_check_tests.pop();
2549       i-=2;
2550     }
2551   }
2552 }
2553 
2554 bool Matcher::gen_narrow_oop_implicit_null_checks() {
2555   // Advice matcher to perform null checks on the narrow oop side.
2556   // Implicit checks are not possible on the uncompressed oop side anyway
2557   // (at least not for read accesses).
2558   // Performs significantly better (especially on Power 6).
2559   if (!os::zero_page_read_protected()) {
2560     return true;
2561   }
2562   return CompressedOops::use_implicit_null_checks() &&
2563          (narrow_oop_use_complex_address() ||
2564           CompressedOops::base() != NULL);
2565 }
2566 
2567 // Used by the DFA in dfa_xxx.cpp.  Check for a following barrier or
2568 // atomic instruction acting as a store_load barrier without any
2569 // intervening volatile load, and thus we don't need a barrier here.
2570 // We retain the Node to act as a compiler ordering barrier.
2571 bool Matcher::post_store_load_barrier(const Node* vmb) {
2572   Compile* C = Compile::current();
2573   assert(vmb->is_MemBar(), "");
2574   assert(vmb->Opcode() != Op_MemBarAcquire && vmb->Opcode() != Op_LoadFence, "");
2575   const MemBarNode* membar = vmb->as_MemBar();
2576 
2577   // Get the Ideal Proj node, ctrl, that can be used to iterate forward
2578   Node* ctrl = NULL;
2579   for (DUIterator_Fast imax, i = membar->fast_outs(imax); i < imax; i++) {
2580     Node* p = membar->fast_out(i);
2581     assert(p->is_Proj(), "only projections here");
2582     if ((p->as_Proj()->_con == TypeFunc::Control) &&
2583         !C->node_arena()->contains(p)) { // Unmatched old-space only
2584       ctrl = p;
2585       break;
2586     }
2587   }
2588   assert((ctrl != NULL), "missing control projection");
2589 
2590   for (DUIterator_Fast jmax, j = ctrl->fast_outs(jmax); j < jmax; j++) {
2591     Node *x = ctrl->fast_out(j);
2592     int xop = x->Opcode();
2593 
2594     // We don't need current barrier if we see another or a lock
2595     // before seeing volatile load.
2596     //
2597     // Op_Fastunlock previously appeared in the Op_* list below.
2598     // With the advent of 1-0 lock operations we're no longer guaranteed
2599     // that a monitor exit operation contains a serializing instruction.
2600 
2601     if (xop == Op_MemBarVolatile ||
2602         xop == Op_CompareAndExchangeB ||
2603         xop == Op_CompareAndExchangeS ||
2604         xop == Op_CompareAndExchangeI ||
2605         xop == Op_CompareAndExchangeL ||
2606         xop == Op_CompareAndExchangeP ||
2607         xop == Op_CompareAndExchangeN ||
2608         xop == Op_WeakCompareAndSwapB ||
2609         xop == Op_WeakCompareAndSwapS ||
2610         xop == Op_WeakCompareAndSwapL ||
2611         xop == Op_WeakCompareAndSwapP ||
2612         xop == Op_WeakCompareAndSwapN ||
2613         xop == Op_WeakCompareAndSwapI ||
2614         xop == Op_CompareAndSwapB ||
2615         xop == Op_CompareAndSwapS ||
2616         xop == Op_CompareAndSwapL ||
2617         xop == Op_CompareAndSwapP ||
2618         xop == Op_CompareAndSwapN ||
2619         xop == Op_CompareAndSwapI ||
2620         BarrierSet::barrier_set()->barrier_set_c2()->matcher_is_store_load_barrier(x, xop)) {
2621       return true;
2622     }
2623 
2624     // Op_FastLock previously appeared in the Op_* list above.
2625     // With biased locking we're no longer guaranteed that a monitor
2626     // enter operation contains a serializing instruction.
2627     if ((xop == Op_FastLock) && !UseBiasedLocking) {
2628       return true;
2629     }
2630 
2631     if (x->is_MemBar()) {
2632       // We must retain this membar if there is an upcoming volatile
2633       // load, which will be followed by acquire membar.
2634       if (xop == Op_MemBarAcquire || xop == Op_LoadFence) {
2635         return false;
2636       } else {
2637         // For other kinds of barriers, check by pretending we
2638         // are them, and seeing if we can be removed.
2639         return post_store_load_barrier(x->as_MemBar());
2640       }
2641     }
2642 
2643     // probably not necessary to check for these
2644     if (x->is_Call() || x->is_SafePoint() || x->is_block_proj()) {
2645       return false;
2646     }
2647   }
2648   return false;
2649 }
2650 
2651 // Check whether node n is a branch to an uncommon trap that we could
2652 // optimize as test with very high branch costs in case of going to
2653 // the uncommon trap. The code must be able to be recompiled to use
2654 // a cheaper test.
2655 bool Matcher::branches_to_uncommon_trap(const Node *n) {
2656   // Don't do it for natives, adapters, or runtime stubs
2657   Compile *C = Compile::current();
2658   if (!C->is_method_compilation()) return false;
2659 
2660   assert(n->is_If(), "You should only call this on if nodes.");
2661   IfNode *ifn = n->as_If();
2662 
2663   Node *ifFalse = NULL;
2664   for (DUIterator_Fast imax, i = ifn->fast_outs(imax); i < imax; i++) {
2665     if (ifn->fast_out(i)->is_IfFalse()) {
2666       ifFalse = ifn->fast_out(i);
2667       break;
2668     }
2669   }
2670   assert(ifFalse, "An If should have an ifFalse. Graph is broken.");
2671 
2672   Node *reg = ifFalse;
2673   int cnt = 4; // We must protect against cycles.  Limit to 4 iterations.
2674                // Alternatively use visited set?  Seems too expensive.
2675   while (reg != NULL && cnt > 0) {
2676     CallNode *call = NULL;
2677     RegionNode *nxt_reg = NULL;
2678     for (DUIterator_Fast imax, i = reg->fast_outs(imax); i < imax; i++) {
2679       Node *o = reg->fast_out(i);
2680       if (o->is_Call()) {
2681         call = o->as_Call();
2682       }
2683       if (o->is_Region()) {
2684         nxt_reg = o->as_Region();
2685       }
2686     }
2687 
2688     if (call &&
2689         call->entry_point() == SharedRuntime::uncommon_trap_blob()->entry_point()) {
2690       const Type* trtype = call->in(TypeFunc::Parms)->bottom_type();
2691       if (trtype->isa_int() && trtype->is_int()->is_con()) {
2692         jint tr_con = trtype->is_int()->get_con();
2693         Deoptimization::DeoptReason reason = Deoptimization::trap_request_reason(tr_con);
2694         Deoptimization::DeoptAction action = Deoptimization::trap_request_action(tr_con);
2695         assert((int)reason < (int)BitsPerInt, "recode bit map");
2696 
2697         if (is_set_nth_bit(C->allowed_deopt_reasons(), (int)reason)
2698             && action != Deoptimization::Action_none) {
2699           // This uncommon trap is sure to recompile, eventually.
2700           // When that happens, C->too_many_traps will prevent
2701           // this transformation from happening again.
2702           return true;
2703         }
2704       }
2705     }
2706 
2707     reg = nxt_reg;
2708     cnt--;
2709   }
2710 
2711   return false;
2712 }
2713 
2714 //=============================================================================
2715 //---------------------------State---------------------------------------------
2716 State::State(void) {
2717 #ifdef ASSERT
2718   _id = 0;
2719   _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2720   _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2721   //memset(_cost, -1, sizeof(_cost));
2722   //memset(_rule, -1, sizeof(_rule));
2723 #endif
2724   memset(_valid, 0, sizeof(_valid));
2725 }
2726 
2727 #ifdef ASSERT
2728 State::~State() {
2729   _id = 99;
2730   _kids[0] = _kids[1] = (State*)(intptr_t) CONST64(0xcafebabecafebabe);
2731   _leaf = (Node*)(intptr_t) CONST64(0xbaadf00dbaadf00d);
2732   memset(_cost, -3, sizeof(_cost));
2733   memset(_rule, -3, sizeof(_rule));
2734 }
2735 #endif
2736 
2737 #ifndef PRODUCT
2738 //---------------------------dump----------------------------------------------
2739 void State::dump() {
2740   tty->print("\n");
2741   dump(0);
2742 }
2743 
2744 void State::dump(int depth) {
2745   for( int j = 0; j < depth; j++ )
2746     tty->print("   ");
2747   tty->print("--N: ");
2748   _leaf->dump();
2749   uint i;
2750   for( i = 0; i < _LAST_MACH_OPER; i++ )
2751     // Check for valid entry
2752     if( valid(i) ) {
2753       for( int j = 0; j < depth; j++ )
2754         tty->print("   ");
2755         assert(_cost[i] != max_juint, "cost must be a valid value");
2756         assert(_rule[i] < _last_Mach_Node, "rule[i] must be valid rule");
2757         tty->print_cr("%s  %d  %s",
2758                       ruleName[i], _cost[i], ruleName[_rule[i]] );
2759       }
2760   tty->cr();
2761 
2762   for( i=0; i<2; i++ )
2763     if( _kids[i] )
2764       _kids[i]->dump(depth+1);
2765 }
2766 #endif