1 /* 2 * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef SHARE_OPTO_MATCHER_HPP 26 #define SHARE_OPTO_MATCHER_HPP 27 28 #include "libadt/vectset.hpp" 29 #include "memory/resourceArea.hpp" 30 #include "oops/compressedOops.hpp" 31 #include "opto/node.hpp" 32 #include "opto/phaseX.hpp" 33 #include "opto/regmask.hpp" 34 #include "runtime/vm_version.hpp" 35 36 class Compile; 37 class Node; 38 class MachNode; 39 class MachTypeNode; 40 class MachOper; 41 42 //---------------------------Matcher------------------------------------------- 43 class Matcher : public PhaseTransform { 44 friend class VMStructs; 45 46 public: 47 48 // Machine-dependent definitions 49 #include CPU_HEADER(matcher) 50 51 // State and MStack class used in xform() and find_shared() iterative methods. 52 enum Node_State { Pre_Visit, // node has to be pre-visited 53 Visit, // visit node 54 Post_Visit, // post-visit node 55 Alt_Post_Visit // alternative post-visit path 56 }; 57 58 class MStack: public Node_Stack { 59 public: 60 MStack(int size) : Node_Stack(size) { } 61 62 void push(Node *n, Node_State ns) { 63 Node_Stack::push(n, (uint)ns); 64 } 65 void push(Node *n, Node_State ns, Node *parent, int indx) { 66 ++_inode_top; 67 if ((_inode_top + 1) >= _inode_max) grow(); 68 _inode_top->node = parent; 69 _inode_top->indx = (uint)indx; 70 ++_inode_top; 71 _inode_top->node = n; 72 _inode_top->indx = (uint)ns; 73 } 74 Node *parent() { 75 pop(); 76 return node(); 77 } 78 Node_State state() const { 79 return (Node_State)index(); 80 } 81 void set_state(Node_State ns) { 82 set_index((uint)ns); 83 } 84 }; 85 86 private: 87 // Private arena of State objects 88 ResourceArea _states_arena; 89 90 VectorSet _visited; // Visit bits 91 92 // Used to control the Label pass 93 VectorSet _shared; // Shared Ideal Node 94 VectorSet _dontcare; // Nothing the matcher cares about 95 96 // Private methods which perform the actual matching and reduction 97 // Walks the label tree, generating machine nodes 98 MachNode *ReduceInst( State *s, int rule, Node *&mem); 99 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach); 100 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds); 101 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach ); 102 103 // If this node already matched using "rule", return the MachNode for it. 104 MachNode* find_shared_node(Node* n, uint rule); 105 106 // Convert a dense opcode number to an expanded rule number 107 const int *_reduceOp; 108 const int *_leftOp; 109 const int *_rightOp; 110 111 // Map dense opcode number to info on when rule is swallowed constant. 112 const bool *_swallowed; 113 114 // Map dense rule number to determine if this is an instruction chain rule 115 const uint _begin_inst_chain_rule; 116 const uint _end_inst_chain_rule; 117 118 // We want to clone constants and possible CmpI-variants. 119 // If we do not clone CmpI, then we can have many instances of 120 // condition codes alive at once. This is OK on some chips and 121 // bad on others. Hence the machine-dependent table lookup. 122 const char *_must_clone; 123 124 // Find shared Nodes, or Nodes that otherwise are Matcher roots 125 void find_shared( Node *n ); 126 bool find_shared_visit(MStack& mstack, Node* n, uint opcode, bool& mem_op, int& mem_addr_idx); 127 void find_shared_post_visit(Node* n, uint opcode); 128 129 bool is_vshift_con_pattern(Node* n, Node* m); 130 131 // Debug and profile information for nodes in old space: 132 GrowableArray<Node_Notes*>* _old_node_note_array; 133 134 // Node labeling iterator for instruction selection 135 Node* Label_Root(const Node* n, State* svec, Node* control, Node*& mem); 136 137 Node *transform( Node *dummy ); 138 139 Node_List _projection_list; // For Machine nodes killing many values 140 141 Node_Array _shared_nodes; 142 143 #ifndef PRODUCT 144 Node_Array _old2new_map; // Map roots of ideal-trees to machine-roots 145 Node_Array _new2old_map; // Maps machine nodes back to ideal 146 VectorSet _reused; // Ideal IGV identifiers reused by machine nodes 147 #endif // !PRODUCT 148 149 // Accessors for the inherited field PhaseTransform::_nodes: 150 void grow_new_node_array(uint idx_limit) { 151 _nodes.map(idx_limit-1, NULL); 152 } 153 bool has_new_node(const Node* n) const { 154 return _nodes.at(n->_idx) != NULL; 155 } 156 Node* new_node(const Node* n) const { 157 assert(has_new_node(n), "set before get"); 158 return _nodes.at(n->_idx); 159 } 160 void set_new_node(const Node* n, Node *nn) { 161 assert(!has_new_node(n), "set only once"); 162 _nodes.map(n->_idx, nn); 163 } 164 165 #ifdef ASSERT 166 // Make sure only new nodes are reachable from this node 167 void verify_new_nodes_only(Node* root); 168 169 Node* _mem_node; // Ideal memory node consumed by mach node 170 #endif 171 172 // Mach node for ConP #NULL 173 MachNode* _mach_null; 174 175 void handle_precedence_edges(Node* n, MachNode *mach); 176 177 public: 178 int LabelRootDepth; 179 // Convert ideal machine register to a register mask for spill-loads 180 static const RegMask *idealreg2regmask[]; 181 RegMask *idealreg2spillmask [_last_machine_leaf]; 182 RegMask *idealreg2debugmask [_last_machine_leaf]; 183 RegMask *idealreg2mhdebugmask[_last_machine_leaf]; 184 void init_spill_mask( Node *ret ); 185 // Convert machine register number to register mask 186 static uint mreg2regmask_max; 187 static RegMask mreg2regmask[]; 188 static RegMask STACK_ONLY_mask; 189 static RegMask caller_save_regmask; 190 static RegMask caller_save_regmask_exclude_soe; 191 static RegMask mh_caller_save_regmask; 192 static RegMask mh_caller_save_regmask_exclude_soe; 193 194 MachNode* mach_null() const { return _mach_null; } 195 196 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; } 197 void set_shared( Node *n ) { _shared.set(n->_idx); } 198 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; } 199 void set_visited( Node *n ) { _visited.set(n->_idx); } 200 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; } 201 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); } 202 203 // Mode bit to tell DFA and expand rules whether we are running after 204 // (or during) register selection. Usually, the matcher runs before, 205 // but it will also get called to generate post-allocation spill code. 206 // In this situation, it is a deadly error to attempt to allocate more 207 // temporary registers. 208 bool _allocation_started; 209 210 // Machine register names 211 static const char *regName[]; 212 // Machine register encodings 213 static const unsigned char _regEncode[]; 214 // Machine Node names 215 const char **_ruleName; 216 // Rules that are cheaper to rematerialize than to spill 217 static const uint _begin_rematerialize; 218 static const uint _end_rematerialize; 219 220 // An array of chars, from 0 to _last_Mach_Reg. 221 // No Save = 'N' (for register windows) 222 // Save on Entry = 'E' 223 // Save on Call = 'C' 224 // Always Save = 'A' (same as SOE + SOC) 225 const char *_register_save_policy; 226 const char *_c_reg_save_policy; 227 // Convert a machine register to a machine register type, so-as to 228 // properly match spill code. 229 const int *_register_save_type; 230 // Maps from machine register to boolean; true if machine register can 231 // be holding a call argument in some signature. 232 static bool can_be_java_arg( int reg ); 233 // Maps from machine register to boolean; true if machine register holds 234 // a spillable argument. 235 static bool is_spillable_arg( int reg ); 236 // Number of integer live ranges that constitute high register pressure 237 static uint int_pressure_limit(); 238 // Number of float live ranges that constitute high register pressure 239 static uint float_pressure_limit(); 240 241 // List of IfFalse or IfTrue Nodes that indicate a taken null test. 242 // List is valid in the post-matching space. 243 Node_List _null_check_tests; 244 void collect_null_checks( Node *proj, Node *orig_proj ); 245 void validate_null_checks( ); 246 247 Matcher(); 248 249 // Get a projection node at position pos 250 Node* get_projection(uint pos) { 251 return _projection_list[pos]; 252 } 253 254 // Push a projection node onto the projection list 255 void push_projection(Node* node) { 256 _projection_list.push(node); 257 } 258 259 Node* pop_projection() { 260 return _projection_list.pop(); 261 } 262 263 // Number of nodes in the projection list 264 uint number_of_projections() const { 265 return _projection_list.size(); 266 } 267 268 // Select instructions for entire method 269 void match(); 270 271 // Helper for match 272 OptoReg::Name warp_incoming_stk_arg( VMReg reg ); 273 274 RegMask* return_values_mask(const TypeFunc* tf); 275 276 // Transform, then walk. Does implicit DCE while walking. 277 // Name changed from "transform" to avoid it being virtual. 278 Node *xform( Node *old_space_node, int Nodes ); 279 280 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce. 281 MachNode *match_tree( const Node *n ); 282 MachNode *match_sfpt( SafePointNode *sfpt ); 283 // Helper for match_sfpt 284 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call ); 285 286 // Initialize first stack mask and related masks. 287 void init_first_stack_mask(); 288 289 // If we should save-on-entry this register 290 bool is_save_on_entry( int reg ); 291 292 // Fixup the save-on-entry registers 293 void Fixup_Save_On_Entry( ); 294 295 // --- Frame handling --- 296 297 // Register number of the stack slot corresponding to the incoming SP. 298 // Per the Big Picture in the AD file, it is: 299 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2. 300 OptoReg::Name _old_SP; 301 302 // Register number of the stack slot corresponding to the highest incoming 303 // argument on the stack. Per the Big Picture in the AD file, it is: 304 // _old_SP + out_preserve_stack_slots + incoming argument size. 305 OptoReg::Name _in_arg_limit; 306 307 // Register number of the stack slot corresponding to the new SP. 308 // Per the Big Picture in the AD file, it is: 309 // _in_arg_limit + pad0 310 OptoReg::Name _new_SP; 311 312 // Register number of the stack slot corresponding to the highest outgoing 313 // argument on the stack. Per the Big Picture in the AD file, it is: 314 // _new_SP + max outgoing arguments of all calls 315 OptoReg::Name _out_arg_limit; 316 317 OptoRegPair *_parm_regs; // Array of machine registers per argument 318 RegMask *_calling_convention_mask; // Array of RegMasks per argument 319 320 // Does matcher have a match rule for this ideal node? 321 static const bool has_match_rule(int opcode); 322 static const bool _hasMatchRule[_last_opcode]; 323 324 // Does matcher have a match rule for this ideal node and is the 325 // predicate (if there is one) true? 326 // NOTE: If this function is used more commonly in the future, ADLC 327 // should generate this one. 328 static const bool match_rule_supported(int opcode); 329 330 // identify extra cases that we might want to provide match rules for 331 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen 332 static const bool match_rule_supported_vector(int opcode, int vlen, BasicType bt); 333 334 static const bool match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt); 335 336 static const RegMask* predicate_reg_mask(void); 337 static const TypeVectMask* predicate_reg_type(const Type* elemTy, int length); 338 339 // Vector width in bytes 340 static const int vector_width_in_bytes(BasicType bt); 341 342 // Limits on vector size (number of elements). 343 static const int max_vector_size(const BasicType bt); 344 static const int min_vector_size(const BasicType bt); 345 static const bool vector_size_supported(const BasicType bt, int size) { 346 return (Matcher::max_vector_size(bt) >= size && 347 Matcher::min_vector_size(bt) <= size); 348 } 349 350 // Actual max scalable vector register length. 351 static const int scalable_vector_reg_size(const BasicType bt); 352 // Actual max scalable predicate register length. 353 static const int scalable_predicate_reg_slots(); 354 355 // Vector ideal reg 356 static const uint vector_ideal_reg(int len); 357 358 // Vector length 359 static uint vector_length(const Node* n); 360 static uint vector_length(const MachNode* use, const MachOper* opnd); 361 362 // Vector length in bytes 363 static uint vector_length_in_bytes(const Node* n); 364 static uint vector_length_in_bytes(const MachNode* use, const MachOper* opnd); 365 366 // Vector element basic type 367 static BasicType vector_element_basic_type(const Node* n); 368 static BasicType vector_element_basic_type(const MachNode* use, const MachOper* opnd); 369 370 // These calls are all generated by the ADLC 371 372 // Java-Java calling convention 373 // (what you use when Java calls Java) 374 375 // Alignment of stack in bytes, standard Intel word alignment is 4. 376 // Sparc probably wants at least double-word (8). 377 static uint stack_alignment_in_bytes(); 378 // Alignment of stack, measured in stack slots. 379 // The size of stack slots is defined by VMRegImpl::stack_slot_size. 380 static uint stack_alignment_in_slots() { 381 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size); 382 } 383 384 // Convert a sig into a calling convention register layout 385 // and find interesting things about it. 386 static OptoReg::Name find_receiver(); 387 // Return address register. On Intel it is a stack-slot. On PowerPC 388 // it is the Link register. On Sparc it is r31? 389 virtual OptoReg::Name return_addr() const; 390 RegMask _return_addr_mask; 391 // Return value register. On Intel it is EAX. 392 static OptoRegPair return_value(uint ideal_reg); 393 static OptoRegPair c_return_value(uint ideal_reg); 394 RegMask* _return_values_mask; 395 // Inline Cache Register 396 static OptoReg::Name inline_cache_reg(); 397 static int inline_cache_reg_encode(); 398 399 // Register for DIVI projection of divmodI 400 static RegMask divI_proj_mask(); 401 // Register for MODI projection of divmodI 402 static RegMask modI_proj_mask(); 403 404 // Register for DIVL projection of divmodL 405 static RegMask divL_proj_mask(); 406 // Register for MODL projection of divmodL 407 static RegMask modL_proj_mask(); 408 409 // Use hardware DIV instruction when it is faster than 410 // a code which use multiply for division by constant. 411 static bool use_asm_for_ldiv_by_con( jlong divisor ); 412 413 static const RegMask method_handle_invoke_SP_save_mask(); 414 415 // Java-Interpreter calling convention 416 // (what you use when calling between compiled-Java and Interpreted-Java 417 418 // Number of callee-save + always-save registers 419 // Ignores frame pointer and "special" registers 420 static int number_of_saved_registers(); 421 422 // The Method-klass-holder may be passed in the inline_cache_reg 423 // and then expanded into the inline_cache_reg and a method_ptr register 424 425 // Interpreter's Frame Pointer Register 426 static OptoReg::Name interpreter_frame_pointer_reg(); 427 428 // Java-Native calling convention 429 // (what you use when intercalling between Java and C++ code) 430 431 // Frame pointer. The frame pointer is kept at the base of the stack 432 // and so is probably the stack pointer for most machines. On Intel 433 // it is ESP. On the PowerPC it is R1. On Sparc it is SP. 434 OptoReg::Name c_frame_pointer() const; 435 static RegMask c_frame_ptr_mask; 436 437 // Java-Native vector calling convention 438 static const bool supports_vector_calling_convention(); 439 static OptoRegPair vector_return_value(uint ideal_reg); 440 441 // Is this branch offset small enough to be addressed by a short branch? 442 bool is_short_branch_offset(int rule, int br_size, int offset); 443 444 // Should the input 'm' of node 'n' be cloned during matching? 445 // Reports back whether the node was cloned or not. 446 bool clone_node(Node* n, Node* m, Matcher::MStack& mstack); 447 bool pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack); 448 449 // Should the Matcher clone shifts on addressing modes, expecting them to 450 // be subsumed into complex addressing expressions or compute them into 451 // registers? True for Intel but false for most RISCs 452 bool pd_clone_address_expressions(AddPNode* m, MStack& mstack, VectorSet& address_visited); 453 // Clone base + offset address expression 454 bool clone_base_plus_offset_address(AddPNode* m, MStack& mstack, VectorSet& address_visited); 455 456 // Generate implicit null check for narrow oops if it can fold 457 // into address expression (x64). 458 // 459 // [R12 + narrow_oop_reg<<3 + offset] // fold into address expression 460 // NullCheck narrow_oop_reg 461 // 462 // When narrow oops can't fold into address expression (Sparc) and 463 // base is not null use decode_not_null and normal implicit null check. 464 // Note, decode_not_null node can be used here since it is referenced 465 // only on non null path but it requires special handling, see 466 // collect_null_checks(): 467 // 468 // decode_not_null narrow_oop_reg, oop_reg // 'shift' and 'add base' 469 // [oop_reg + offset] 470 // NullCheck oop_reg 471 // 472 // With Zero base and when narrow oops can not fold into address 473 // expression use normal implicit null check since only shift 474 // is needed to decode narrow oop. 475 // 476 // decode narrow_oop_reg, oop_reg // only 'shift' 477 // [oop_reg + offset] 478 // NullCheck oop_reg 479 // 480 static bool gen_narrow_oop_implicit_null_checks(); 481 482 private: 483 void do_postselect_cleanup(); 484 485 void specialize_generic_vector_operands(); 486 void specialize_mach_node(MachNode* m); 487 void specialize_temp_node(MachTempNode* tmp, MachNode* use, uint idx); 488 MachOper* specialize_vector_operand(MachNode* m, uint opnd_idx); 489 490 static MachOper* pd_specialize_generic_vector_operand(MachOper* generic_opnd, uint ideal_reg, bool is_temp); 491 static bool is_reg2reg_move(MachNode* m); 492 static bool is_generic_vector(MachOper* opnd); 493 494 const RegMask* regmask_for_ideal_register(uint ideal_reg, Node* ret); 495 496 // Graph verification code 497 DEBUG_ONLY( bool verify_after_postselect_cleanup(); ) 498 499 public: 500 // This routine is run whenever a graph fails to match. 501 // If it returns, the compiler should bailout to interpreter without error. 502 // In non-product mode, SoftMatchFailure is false to detect non-canonical 503 // graphs. Print a message and exit. 504 static void soft_match_failure() { 505 if( SoftMatchFailure ) return; 506 else { fatal("SoftMatchFailure is not allowed except in product"); } 507 } 508 509 // Check for a following volatile memory barrier without an 510 // intervening load and thus we don't need a barrier here. We 511 // retain the Node to act as a compiler ordering barrier. 512 static bool post_store_load_barrier(const Node* mb); 513 514 // Does n lead to an uncommon trap that can cause deoptimization? 515 static bool branches_to_uncommon_trap(const Node *n); 516 517 #ifndef PRODUCT 518 // Record mach-to-Ideal mapping, reusing the Ideal IGV identifier if possible. 519 void record_new2old(Node* newn, Node* old); 520 521 void dump_old2new_map(); // machine-independent to machine-dependent 522 523 Node* find_old_node(Node* new_node) { 524 return _new2old_map[new_node->_idx]; 525 } 526 #endif // !PRODUCT 527 }; 528 529 #endif // SHARE_OPTO_MATCHER_HPP