1 /*
2 * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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5 * This code is free software; you can redistribute it and/or modify it
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7 * published by the Free Software Foundation.
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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13 * accompanied this code).
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23 */
24
25 #ifndef SHARE_OPTO_MATCHER_HPP
26 #define SHARE_OPTO_MATCHER_HPP
27
28 #include "libadt/vectset.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "oops/compressedOops.hpp"
31 #include "opto/node.hpp"
32 #include "opto/phaseX.hpp"
33 #include "opto/regmask.hpp"
34 #include "opto/subnode.hpp"
35 #include "runtime/vm_version.hpp"
36
37 class Compile;
38 class Node;
39 class MachNode;
40 class MachTypeNode;
41 class MachOper;
42
43 //---------------------------Matcher-------------------------------------------
44 class Matcher : public PhaseTransform {
45 friend class VMStructs;
46
47 public:
48
49 // Machine-dependent definitions
50 #include CPU_HEADER(matcher)
51
52 // State and MStack class used in xform() and find_shared() iterative methods.
53 enum Node_State { Pre_Visit, // node has to be pre-visited
54 Visit, // visit node
55 Post_Visit, // post-visit node
56 Alt_Post_Visit // alternative post-visit path
57 };
58
59 class MStack: public Node_Stack {
60 public:
61 MStack(int size) : Node_Stack(size) { }
62
63 void push(Node *n, Node_State ns) {
64 Node_Stack::push(n, (uint)ns);
65 }
66 void push(Node *n, Node_State ns, Node *parent, int indx) {
67 ++_inode_top;
68 if ((_inode_top + 1) >= _inode_max) grow();
69 _inode_top->node = parent;
70 _inode_top->indx = (uint)indx;
71 ++_inode_top;
72 _inode_top->node = n;
73 _inode_top->indx = (uint)ns;
74 }
75 Node *parent() {
76 pop();
77 return node();
78 }
79 Node_State state() const {
80 return (Node_State)index();
81 }
82 void set_state(Node_State ns) {
83 set_index((uint)ns);
84 }
85 };
86
87 private:
88 // Private arena of State objects
89 ResourceArea _states_arena;
90
91 VectorSet _visited; // Visit bits
92
93 // Used to control the Label pass
94 VectorSet _shared; // Shared Ideal Node
95 VectorSet _dontcare; // Nothing the matcher cares about
96
97 // Private methods which perform the actual matching and reduction
98 // Walks the label tree, generating machine nodes
99 MachNode *ReduceInst( State *s, int rule, Node *&mem);
100 void ReduceInst_Chain_Rule( State *s, int rule, Node *&mem, MachNode *mach);
101 uint ReduceInst_Interior(State *s, int rule, Node *&mem, MachNode *mach, uint num_opnds);
102 void ReduceOper( State *s, int newrule, Node *&mem, MachNode *mach );
103
104 // If this node already matched using "rule", return the MachNode for it.
105 MachNode* find_shared_node(Node* n, uint rule);
106
107 // Convert a dense opcode number to an expanded rule number
108 const int *_reduceOp;
109 const int *_leftOp;
110 const int *_rightOp;
111
112 // Map dense opcode number to info on when rule is swallowed constant.
113 const bool *_swallowed;
114
115 // Map dense rule number to determine if this is an instruction chain rule
116 const uint _begin_inst_chain_rule;
117 const uint _end_inst_chain_rule;
118
119 // We want to clone constants and possible CmpI-variants.
120 // If we do not clone CmpI, then we can have many instances of
121 // condition codes alive at once. This is OK on some chips and
122 // bad on others. Hence the machine-dependent table lookup.
123 const char *_must_clone;
124
125 // Find shared Nodes, or Nodes that otherwise are Matcher roots
126 void find_shared( Node *n );
127 bool find_shared_visit(MStack& mstack, Node* n, uint opcode, bool& mem_op, int& mem_addr_idx);
128 void find_shared_post_visit(Node* n, uint opcode);
129
130 bool is_vshift_con_pattern(Node* n, Node* m);
131
132 // Debug and profile information for nodes in old space:
133 GrowableArray<Node_Notes*>* _old_node_note_array;
134
135 // Node labeling iterator for instruction selection
136 Node* Label_Root(const Node* n, State* svec, Node* control, Node*& mem);
137
138 Node *transform( Node *dummy );
139
140 Node_List _projection_list; // For Machine nodes killing many values
141
142 Node_Array _shared_nodes;
143
144 #ifndef PRODUCT
145 Node_Array _old2new_map; // Map roots of ideal-trees to machine-roots
146 Node_Array _new2old_map; // Maps machine nodes back to ideal
147 VectorSet _reused; // Ideal IGV identifiers reused by machine nodes
148 #endif // !PRODUCT
149
150 // Accessors for the inherited field PhaseTransform::_nodes:
151 void grow_new_node_array(uint idx_limit) {
152 _nodes.map(idx_limit-1, NULL);
153 }
154 bool has_new_node(const Node* n) const {
155 return _nodes.at(n->_idx) != NULL;
156 }
157 Node* new_node(const Node* n) const {
158 assert(has_new_node(n), "set before get");
159 return _nodes.at(n->_idx);
160 }
161 void set_new_node(const Node* n, Node *nn) {
162 assert(!has_new_node(n), "set only once");
163 _nodes.map(n->_idx, nn);
164 }
165
166 #ifdef ASSERT
167 // Make sure only new nodes are reachable from this node
168 void verify_new_nodes_only(Node* root);
169
170 Node* _mem_node; // Ideal memory node consumed by mach node
171 #endif
172
173 // Mach node for ConP #NULL
174 MachNode* _mach_null;
175
176 void handle_precedence_edges(Node* n, MachNode *mach);
177
178 public:
179 int LabelRootDepth;
180 // Convert ideal machine register to a register mask for spill-loads
181 static const RegMask *idealreg2regmask[];
182 RegMask *idealreg2spillmask [_last_machine_leaf];
183 RegMask *idealreg2debugmask [_last_machine_leaf];
184 RegMask *idealreg2mhdebugmask[_last_machine_leaf];
185 void init_spill_mask( Node *ret );
186 // Convert machine register number to register mask
187 static uint mreg2regmask_max;
188 static RegMask mreg2regmask[];
189 static RegMask STACK_ONLY_mask;
190 static RegMask caller_save_regmask;
191 static RegMask caller_save_regmask_exclude_soe;
192 static RegMask mh_caller_save_regmask;
193 static RegMask mh_caller_save_regmask_exclude_soe;
194
195 MachNode* mach_null() const { return _mach_null; }
196
197 bool is_shared( Node *n ) { return _shared.test(n->_idx) != 0; }
198 void set_shared( Node *n ) { _shared.set(n->_idx); }
199 bool is_visited( Node *n ) { return _visited.test(n->_idx) != 0; }
200 void set_visited( Node *n ) { _visited.set(n->_idx); }
201 bool is_dontcare( Node *n ) { return _dontcare.test(n->_idx) != 0; }
202 void set_dontcare( Node *n ) { _dontcare.set(n->_idx); }
203
204 // Mode bit to tell DFA and expand rules whether we are running after
205 // (or during) register selection. Usually, the matcher runs before,
206 // but it will also get called to generate post-allocation spill code.
207 // In this situation, it is a deadly error to attempt to allocate more
208 // temporary registers.
209 bool _allocation_started;
210
211 // Machine register names
212 static const char *regName[];
213 // Machine register encodings
214 static const unsigned char _regEncode[];
215 // Machine Node names
216 const char **_ruleName;
217 // Rules that are cheaper to rematerialize than to spill
218 static const uint _begin_rematerialize;
219 static const uint _end_rematerialize;
220
221 // An array of chars, from 0 to _last_Mach_Reg.
222 // No Save = 'N' (for register windows)
223 // Save on Entry = 'E'
224 // Save on Call = 'C'
225 // Always Save = 'A' (same as SOE + SOC)
226 const char *_register_save_policy;
227 const char *_c_reg_save_policy;
228 // Convert a machine register to a machine register type, so-as to
229 // properly match spill code.
230 const int *_register_save_type;
231 // Maps from machine register to boolean; true if machine register can
232 // be holding a call argument in some signature.
233 static bool can_be_java_arg( int reg );
234 // Maps from machine register to boolean; true if machine register holds
235 // a spillable argument.
236 static bool is_spillable_arg( int reg );
237 // Number of integer live ranges that constitute high register pressure
238 static uint int_pressure_limit();
239 // Number of float live ranges that constitute high register pressure
240 static uint float_pressure_limit();
241
242 // List of IfFalse or IfTrue Nodes that indicate a taken null test.
243 // List is valid in the post-matching space.
244 Node_List _null_check_tests;
245 void collect_null_checks( Node *proj, Node *orig_proj );
246 void validate_null_checks( );
247
248 Matcher();
249
250 // Get a projection node at position pos
251 Node* get_projection(uint pos) {
252 return _projection_list[pos];
253 }
254
255 // Push a projection node onto the projection list
256 void push_projection(Node* node) {
257 _projection_list.push(node);
258 }
259
260 Node* pop_projection() {
261 return _projection_list.pop();
262 }
263
264 // Number of nodes in the projection list
265 uint number_of_projections() const {
266 return _projection_list.size();
267 }
268
269 // Select instructions for entire method
270 void match();
271
272 // Helper for match
273 OptoReg::Name warp_incoming_stk_arg( VMReg reg );
274
275 RegMask* return_values_mask(const TypeFunc* tf);
276
277 // Transform, then walk. Does implicit DCE while walking.
278 // Name changed from "transform" to avoid it being virtual.
279 Node *xform( Node *old_space_node, int Nodes );
280
281 // Match a single Ideal Node - turn it into a 1-Node tree; Label & Reduce.
282 MachNode *match_tree( const Node *n );
283 MachNode *match_sfpt( SafePointNode *sfpt );
284 // Helper for match_sfpt
285 OptoReg::Name warp_outgoing_stk_arg( VMReg reg, OptoReg::Name begin_out_arg_area, OptoReg::Name &out_arg_limit_per_call );
286
287 // Initialize first stack mask and related masks.
288 void init_first_stack_mask();
289
290 // If we should save-on-entry this register
291 bool is_save_on_entry( int reg );
292
293 // Fixup the save-on-entry registers
294 void Fixup_Save_On_Entry( );
295
296 // --- Frame handling ---
297
298 // Register number of the stack slot corresponding to the incoming SP.
299 // Per the Big Picture in the AD file, it is:
300 // SharedInfo::stack0 + locks + in_preserve_stack_slots + pad2.
301 OptoReg::Name _old_SP;
302
303 // Register number of the stack slot corresponding to the highest incoming
304 // argument on the stack. Per the Big Picture in the AD file, it is:
305 // _old_SP + out_preserve_stack_slots + incoming argument size.
306 OptoReg::Name _in_arg_limit;
307
308 // Register number of the stack slot corresponding to the new SP.
309 // Per the Big Picture in the AD file, it is:
310 // _in_arg_limit + pad0
311 OptoReg::Name _new_SP;
312
313 // Register number of the stack slot corresponding to the highest outgoing
314 // argument on the stack. Per the Big Picture in the AD file, it is:
315 // _new_SP + max outgoing arguments of all calls
316 OptoReg::Name _out_arg_limit;
317
318 OptoRegPair *_parm_regs; // Array of machine registers per argument
319 RegMask *_calling_convention_mask; // Array of RegMasks per argument
320
321 // Does matcher have a match rule for this ideal node?
322 static const bool has_match_rule(int opcode);
323 static const bool _hasMatchRule[_last_opcode];
324
325 // Does matcher have a match rule for this ideal node and is the
326 // predicate (if there is one) true?
327 // NOTE: If this function is used more commonly in the future, ADLC
328 // should generate this one.
329 static const bool match_rule_supported(int opcode);
330
331 // Identify extra cases that we might want to vectorize automatically
332 // And exclude cases which are not profitable to auto-vectorize.
333 static const bool match_rule_supported_superword(int opcode, int vlen, BasicType bt);
334
335 // identify extra cases that we might want to provide match rules for
336 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
337 static const bool match_rule_supported_vector(int opcode, int vlen, BasicType bt);
338
339 static const bool match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt);
340
341 static const bool vector_needs_partial_operations(Node* node, const TypeVect* vt);
342
343 static const RegMask* predicate_reg_mask(void);
344 static const TypeVectMask* predicate_reg_type(const Type* elemTy, int length);
345
346 // Vector width in bytes
347 static const int vector_width_in_bytes(BasicType bt);
348
349 // Limits on vector size (number of elements).
350 static const int max_vector_size(const BasicType bt);
351 static const int min_vector_size(const BasicType bt);
352 static const bool vector_size_supported(const BasicType bt, int size) {
353 return (Matcher::max_vector_size(bt) >= size &&
354 Matcher::min_vector_size(bt) <= size);
355 }
356
357 // Actual max scalable vector register length.
358 static const int scalable_vector_reg_size(const BasicType bt);
359 // Actual max scalable predicate register length.
360 static const int scalable_predicate_reg_slots();
361
362 // Vector ideal reg
363 static const uint vector_ideal_reg(int len);
364
365 // Vector length
366 static uint vector_length(const Node* n);
367 static uint vector_length(const MachNode* use, const MachOper* opnd);
368
369 // Vector length in bytes
370 static uint vector_length_in_bytes(const Node* n);
371 static uint vector_length_in_bytes(const MachNode* use, const MachOper* opnd);
372
373 // Vector element basic type
374 static BasicType vector_element_basic_type(const Node* n);
375 static BasicType vector_element_basic_type(const MachNode* use, const MachOper* opnd);
376
377 // These calls are all generated by the ADLC
378
379 // Java-Java calling convention
380 // (what you use when Java calls Java)
381
382 // Alignment of stack in bytes, standard Intel word alignment is 4.
383 // Sparc probably wants at least double-word (8).
384 static uint stack_alignment_in_bytes();
385 // Alignment of stack, measured in stack slots.
386 // The size of stack slots is defined by VMRegImpl::stack_slot_size.
387 static uint stack_alignment_in_slots() {
388 return stack_alignment_in_bytes() / (VMRegImpl::stack_slot_size);
389 }
390
391 // Convert a sig into a calling convention register layout
392 // and find interesting things about it.
393 static OptoReg::Name find_receiver();
394 // Return address register. On Intel it is a stack-slot. On PowerPC
395 // it is the Link register. On Sparc it is r31?
396 virtual OptoReg::Name return_addr() const;
397 RegMask _return_addr_mask;
398 // Return value register. On Intel it is EAX.
399 static OptoRegPair return_value(uint ideal_reg);
400 static OptoRegPair c_return_value(uint ideal_reg);
401 RegMask* _return_values_mask;
402 // Inline Cache Register
403 static OptoReg::Name inline_cache_reg();
404 static int inline_cache_reg_encode();
405
406 // Register for DIVI projection of divmodI
407 static RegMask divI_proj_mask();
408 // Register for MODI projection of divmodI
409 static RegMask modI_proj_mask();
410
411 // Register for DIVL projection of divmodL
412 static RegMask divL_proj_mask();
413 // Register for MODL projection of divmodL
414 static RegMask modL_proj_mask();
415
416 // Use hardware DIV instruction when it is faster than
417 // a code which use multiply for division by constant.
418 static bool use_asm_for_ldiv_by_con( jlong divisor );
419
420 static const RegMask method_handle_invoke_SP_save_mask();
421
422 // Java-Interpreter calling convention
423 // (what you use when calling between compiled-Java and Interpreted-Java
424
425 // Number of callee-save + always-save registers
426 // Ignores frame pointer and "special" registers
427 static int number_of_saved_registers();
428
429 // The Method-klass-holder may be passed in the inline_cache_reg
430 // and then expanded into the inline_cache_reg and a method_ptr register
431
432 // Interpreter's Frame Pointer Register
433 static OptoReg::Name interpreter_frame_pointer_reg();
434
435 // Java-Native calling convention
436 // (what you use when intercalling between Java and C++ code)
437
438 // Frame pointer. The frame pointer is kept at the base of the stack
439 // and so is probably the stack pointer for most machines. On Intel
440 // it is ESP. On the PowerPC it is R1. On Sparc it is SP.
441 OptoReg::Name c_frame_pointer() const;
442 static RegMask c_frame_ptr_mask;
443
444 // Java-Native vector calling convention
445 static const bool supports_vector_calling_convention();
446 static OptoRegPair vector_return_value(uint ideal_reg);
447
448 // Is this branch offset small enough to be addressed by a short branch?
449 bool is_short_branch_offset(int rule, int br_size, int offset);
450
451 // Should the input 'm' of node 'n' be cloned during matching?
452 // Reports back whether the node was cloned or not.
453 bool clone_node(Node* n, Node* m, Matcher::MStack& mstack);
454 bool pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack);
455
456 // Should the Matcher clone shifts on addressing modes, expecting them to
457 // be subsumed into complex addressing expressions or compute them into
458 // registers? True for Intel but false for most RISCs
459 bool pd_clone_address_expressions(AddPNode* m, MStack& mstack, VectorSet& address_visited);
460 // Clone base + offset address expression
461 bool clone_base_plus_offset_address(AddPNode* m, MStack& mstack, VectorSet& address_visited);
462
463 // Generate implicit null check for narrow oops if it can fold
464 // into address expression (x64).
465 //
466 // [R12 + narrow_oop_reg<<3 + offset] // fold into address expression
467 // NullCheck narrow_oop_reg
468 //
469 // When narrow oops can't fold into address expression (Sparc) and
470 // base is not null use decode_not_null and normal implicit null check.
471 // Note, decode_not_null node can be used here since it is referenced
472 // only on non null path but it requires special handling, see
473 // collect_null_checks():
474 //
475 // decode_not_null narrow_oop_reg, oop_reg // 'shift' and 'add base'
476 // [oop_reg + offset]
477 // NullCheck oop_reg
478 //
479 // With Zero base and when narrow oops can not fold into address
480 // expression use normal implicit null check since only shift
481 // is needed to decode narrow oop.
482 //
483 // decode narrow_oop_reg, oop_reg // only 'shift'
484 // [oop_reg + offset]
485 // NullCheck oop_reg
486 //
487 static bool gen_narrow_oop_implicit_null_checks();
488
489 private:
490 void do_postselect_cleanup();
491
492 void specialize_generic_vector_operands();
493 void specialize_mach_node(MachNode* m);
494 void specialize_temp_node(MachTempNode* tmp, MachNode* use, uint idx);
495 MachOper* specialize_vector_operand(MachNode* m, uint opnd_idx);
496
497 static MachOper* pd_specialize_generic_vector_operand(MachOper* generic_opnd, uint ideal_reg, bool is_temp);
498 static bool is_reg2reg_move(MachNode* m);
499 static bool is_generic_vector(MachOper* opnd);
500
501 const RegMask* regmask_for_ideal_register(uint ideal_reg, Node* ret);
502
503 // Graph verification code
504 DEBUG_ONLY( bool verify_after_postselect_cleanup(); )
505
506 public:
507 // This routine is run whenever a graph fails to match.
508 // If it returns, the compiler should bailout to interpreter without error.
509 // In non-product mode, SoftMatchFailure is false to detect non-canonical
510 // graphs. Print a message and exit.
511 static void soft_match_failure() {
512 if( SoftMatchFailure ) return;
513 else { fatal("SoftMatchFailure is not allowed except in product"); }
514 }
515
516 // Check for a following volatile memory barrier without an
517 // intervening load and thus we don't need a barrier here. We
518 // retain the Node to act as a compiler ordering barrier.
519 static bool post_store_load_barrier(const Node* mb);
520
521 // Does n lead to an uncommon trap that can cause deoptimization?
522 static bool branches_to_uncommon_trap(const Node *n);
523
524 #ifndef PRODUCT
525 // Record mach-to-Ideal mapping, reusing the Ideal IGV identifier if possible.
526 void record_new2old(Node* newn, Node* old);
527
528 void dump_old2new_map(); // machine-independent to machine-dependent
529
530 Node* find_old_node(const Node* new_node) {
531 return _new2old_map[new_node->_idx];
532 }
533 #endif // !PRODUCT
534 };
535
536 #endif // SHARE_OPTO_MATCHER_HPP