1119     f(op2, 7, 5);
1120     // reading to zr is a mistake
1121     rf(rt, 0);
1122   }
1123 
1124   enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1125                 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1126 
1127   void dsb(barrier imm) {
1128     system(0b00, 0b011, 0b00011, imm, 0b100);
1129   }
1130 
1131   void dmb(barrier imm) {
1132     system(0b00, 0b011, 0b00011, imm, 0b101);
1133   }
1134 
1135   void isb() {
1136     system(0b00, 0b011, 0b00011, SY, 0b110);
1137   }
1138 




1139   void sys(int op1, int CRn, int CRm, int op2,
1140            Register rt = as_Register(0b11111)) {
1141     system(0b01, op1, CRn, CRm, op2, rt);
1142   }
1143 
1144   // Only implement operations accessible from EL0 or higher, i.e.,
1145   //            op1    CRn    CRm    op2
1146   // IC IVAU     3      7      5      1
1147   // DC CVAC     3      7      10     1
1148   // DC CVAP     3      7      12     1
1149   // DC CVAU     3      7      11     1
1150   // DC CIVAC    3      7      14     1
1151   // DC ZVA      3      7      4      1
1152   // So only deal with the CRm field.
1153   enum icache_maintenance {IVAU = 0b0101};
1154   enum dcache_maintenance {CVAC = 0b1010, CVAP = 0b1100, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1155 
1156   void dc(dcache_maintenance cm, Register Rt) {
1157     sys(0b011, 0b0111, cm, 0b001, Rt);
1158   }

1119     f(op2, 7, 5);
1120     // reading to zr is a mistake
1121     rf(rt, 0);
1122   }
1123 
1124   enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1125                 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1126 
1127   void dsb(barrier imm) {
1128     system(0b00, 0b011, 0b00011, imm, 0b100);
1129   }
1130 
1131   void dmb(barrier imm) {
1132     system(0b00, 0b011, 0b00011, imm, 0b101);
1133   }
1134 
1135   void isb() {
1136     system(0b00, 0b011, 0b00011, SY, 0b110);
1137   }
1138 
1139   void sb() {
1140     system(0b00, 0b011, 0b00011, 0b0000, 0b111);
1141   }
1142 
1143   void sys(int op1, int CRn, int CRm, int op2,
1144            Register rt = as_Register(0b11111)) {
1145     system(0b01, op1, CRn, CRm, op2, rt);
1146   }
1147 
1148   // Only implement operations accessible from EL0 or higher, i.e.,
1149   //            op1    CRn    CRm    op2
1150   // IC IVAU     3      7      5      1
1151   // DC CVAC     3      7      10     1
1152   // DC CVAP     3      7      12     1
1153   // DC CVAU     3      7      11     1
1154   // DC CIVAC    3      7      14     1
1155   // DC ZVA      3      7      4      1
1156   // So only deal with the CRm field.
1157   enum icache_maintenance {IVAU = 0b0101};
1158   enum dcache_maintenance {CVAC = 0b1010, CVAP = 0b1100, CVAU = 0b1011, CIVAC = 0b1110, ZVA = 0b100};
1159 
1160   void dc(dcache_maintenance cm, Register Rt) {
1161     sys(0b011, 0b0111, cm, 0b001, Rt);
1162   }