15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "pauth_aarch64.hpp"
27 #include "register_aarch64.hpp"
28 #include "runtime/arguments.hpp"
29 #include "runtime/globals_extension.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/os.inline.hpp"
32 #include "runtime/vm_version.hpp"
33 #include "utilities/formatBuffer.hpp"
34 #include "utilities/macros.hpp"
35
36 int VM_Version::_cpu;
37 int VM_Version::_model;
38 int VM_Version::_model2;
39 int VM_Version::_variant;
40 int VM_Version::_revision;
41 int VM_Version::_stepping;
42
43 int VM_Version::_zva_length;
44 int VM_Version::_dcache_line_size;
45 int VM_Version::_icache_line_size;
46 int VM_Version::_initial_sve_vector_length;
47 int VM_Version::_max_supported_sve_vector_length;
48 bool VM_Version::_rop_protection;
49 uintptr_t VM_Version::_pac_mask;
50
51 SpinWait VM_Version::_spin_wait;
52
53 static SpinWait get_spin_wait_desc() {
54 if (strcmp(OnSpinWaitInst, "nop") == 0) {
55 return SpinWait(SpinWait::NOP, OnSpinWaitInstCount);
56 } else if (strcmp(OnSpinWaitInst, "isb") == 0) {
57 return SpinWait(SpinWait::ISB, OnSpinWaitInstCount);
58 } else if (strcmp(OnSpinWaitInst, "yield") == 0) {
59 return SpinWait(SpinWait::YIELD, OnSpinWaitInstCount);
60 } else if (strcmp(OnSpinWaitInst, "none") != 0) {
61 vm_exit_during_initialization("The options for OnSpinWaitInst are nop, isb, yield, and none", OnSpinWaitInst);
62 }
63
64 if (!FLAG_IS_DEFAULT(OnSpinWaitInstCount) && OnSpinWaitInstCount > 0) {
65 vm_exit_during_initialization("OnSpinWaitInstCount cannot be used for OnSpinWaitInst 'none'");
66 }
67
68 return SpinWait{};
69 }
70
71 void VM_Version::initialize() {
72 _supports_atomic_getset4 = true;
73 _supports_atomic_getadd4 = true;
74 _supports_atomic_getset8 = true;
75 _supports_atomic_getadd8 = true;
76
77 get_os_cpu_info();
78
79 int dcache_line = VM_Version::dcache_line_size();
80
81 // Limit AllocatePrefetchDistance so that it does not exceed the
82 // static constraint of 512 defined in runtime/globals.hpp.
83 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
84 FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
85
86 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
87 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
88 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
89 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
90 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
91 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
186 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
187 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
188 }
189 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
190 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
191 }
192 }
193
194 // HiSilicon TSV110
195 if (_cpu == CPU_HISILICON && _model == 0xd01) {
196 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
197 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
198 }
199 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
200 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
201 }
202 }
203
204 // Cortex A53
205 if (_cpu == CPU_ARM && model_is(0xd03)) {
206 _features |= CPU_A53MAC;
207 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
208 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
209 }
210 }
211
212 // Cortex A73
213 if (_cpu == CPU_ARM && model_is(0xd09)) {
214 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
215 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
216 }
217 // A73 is faster with short-and-easy-for-speculative-execution-loop
218 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
219 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
220 }
221 }
222
223 // Neoverse
224 // N1: 0xd0c
225 // N2: 0xd49
226 // V1: 0xd40
227 // V2: 0xd4f
228 if (_cpu == CPU_ARM && (model_is(0xd0c) || model_is(0xd49) ||
229 model_is(0xd40) || model_is(0xd4f))) {
230 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
231 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
232 }
233
234 if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
235 FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
236 }
237
238 if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
239 FLAG_SET_DEFAULT(OnSpinWaitInstCount, 1);
240 }
241 if (FLAG_IS_DEFAULT(AlwaysMergeDMB)) {
242 FLAG_SET_DEFAULT(AlwaysMergeDMB, false);
243 }
244 }
245
246 if (_features & (CPU_FP | CPU_ASIMD)) {
247 if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
248 FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
249 }
250 }
251
252 if (FLAG_IS_DEFAULT(UseCRC32)) {
253 UseCRC32 = VM_Version::supports_crc32();
254 }
255
256 if (UseCRC32 && !VM_Version::supports_crc32()) {
257 warning("UseCRC32 specified, but not supported on this CPU");
258 FLAG_SET_DEFAULT(UseCRC32, false);
259 }
260
261 // Neoverse
262 // V1: 0xd40
263 // V2: 0xd4f
264 if (_cpu == CPU_ARM && (model_is(0xd40) || model_is(0xd4f))) {
265 if (FLAG_IS_DEFAULT(UseCryptoPmullForCRC32)) {
266 FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, true);
389 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
390 }
391 } else if (UseSHA512Intrinsics) {
392 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
393 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
394 }
395
396 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA3Intrinsics || UseSHA512Intrinsics)) {
397 FLAG_SET_DEFAULT(UseSHA, false);
398 }
399
400 if (VM_Version::supports_pmull()) {
401 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
402 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
403 }
404 } else if (UseGHASHIntrinsics) {
405 warning("GHASH intrinsics are not available on this CPU");
406 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
407 }
408
409 if (_features & CPU_ASIMD) {
410 if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
411 UseChaCha20Intrinsics = true;
412 }
413 } else if (UseChaCha20Intrinsics) {
414 if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
415 warning("ChaCha20 intrinsic requires ASIMD instructions");
416 }
417 FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
418 }
419
420 if (_features & CPU_ASIMD) {
421 if (FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
422 UseKyberIntrinsics = true;
423 }
424 } else if (UseKyberIntrinsics) {
425 if (!FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
426 warning("Kyber intrinsics require ASIMD instructions");
427 }
428 FLAG_SET_DEFAULT(UseKyberIntrinsics, false);
429 }
430
431 if (_features & CPU_ASIMD) {
432 if (FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
433 UseDilithiumIntrinsics = true;
434 }
435 } else if (UseDilithiumIntrinsics) {
436 if (!FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
437 warning("Dilithium intrinsics require ASIMD instructions");
438 }
439 FLAG_SET_DEFAULT(UseDilithiumIntrinsics, false);
440 }
441
442 if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
443 UseBASE64Intrinsics = true;
444 }
445
446 if (is_zva_enabled()) {
447 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
448 FLAG_SET_DEFAULT(UseBlockZeroing, true);
449 }
450 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
451 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
612
613 if (FLAG_IS_DEFAULT(AlignVector)) {
614 AlignVector = AvoidUnalignedAccesses;
615 }
616
617 if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
618 FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
619 }
620
621 if (FLAG_IS_DEFAULT(UseVectorizedHashCodeIntrinsic)) {
622 FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, true);
623 }
624 #endif
625
626 _spin_wait = get_spin_wait_desc();
627
628 check_virtualizations();
629
630 // Sync SVE related CPU features with flags
631 if (UseSVE < 2) {
632 _features &= ~CPU_SVE2;
633 _features &= ~CPU_SVEBITPERM;
634 }
635 if (UseSVE < 1) {
636 _features &= ~CPU_SVE;
637 }
638
639 // Construct the "features" string
640 char buf[512];
641 int buf_used_len = os::snprintf_checked(buf, sizeof(buf), "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
642 if (_model2) {
643 os::snprintf_checked(buf + buf_used_len, sizeof(buf) - buf_used_len, "(0x%03x)", _model2);
644 }
645 size_t features_offset = strnlen(buf, sizeof(buf));
646 #define ADD_FEATURE_IF_SUPPORTED(id, name, bit) \
647 do { \
648 if (VM_Version::supports_##name()) strcat(buf, ", " #name); \
649 } while(0);
650 CPU_FEATURE_FLAGS(ADD_FEATURE_IF_SUPPORTED)
651 #undef ADD_FEATURE_IF_SUPPORTED
652
653 _cpu_info_string = os::strdup(buf);
654
655 _features_string = extract_features_string(_cpu_info_string,
656 strnlen(_cpu_info_string, sizeof(buf)),
657 features_offset);
658 }
659
660 #if defined(LINUX)
661 static bool check_info_file(const char* fpath,
662 const char* virt1, VirtualizationType vt1,
663 const char* virt2, VirtualizationType vt2) {
664 char line[500];
665 FILE* fp = os::fopen(fpath, "r");
666 if (fp == nullptr) {
667 return false;
668 }
669 while (fgets(line, sizeof(line), fp) != nullptr) {
670 if (strcasestr(line, virt1) != nullptr) {
671 Abstract_VM_Version::_detected_virtualization = vt1;
672 fclose(fp);
673 return true;
674 }
675 if (virt2 != nullptr && strcasestr(line, virt2) != nullptr) {
676 Abstract_VM_Version::_detected_virtualization = vt2;
677 fclose(fp);
708 }
709
710 void VM_Version::initialize_cpu_information(void) {
711 // do nothing if cpu info has been initialized
712 if (_initialized) {
713 return;
714 }
715
716 _no_of_cores = os::processor_count();
717 _no_of_threads = _no_of_cores;
718 _no_of_sockets = _no_of_cores;
719 snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "AArch64");
720
721 int desc_len = snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "AArch64 ");
722 get_compatible_board(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len);
723 desc_len = (int)strlen(_cpu_desc);
724 snprintf(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len, " %s", _cpu_info_string);
725
726 _initialized = true;
727 }
|
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "pauth_aarch64.hpp"
27 #include "register_aarch64.hpp"
28 #include "runtime/arguments.hpp"
29 #include "runtime/globals_extension.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/os.inline.hpp"
32 #include "runtime/vm_version.hpp"
33 #include "utilities/formatBuffer.hpp"
34 #include "utilities/macros.hpp"
35 #include "utilities/ostream.hpp"
36
37 int VM_Version::_cpu;
38 int VM_Version::_model;
39 int VM_Version::_model2;
40 int VM_Version::_variant;
41 int VM_Version::_revision;
42 int VM_Version::_stepping;
43
44 int VM_Version::_zva_length;
45 int VM_Version::_dcache_line_size;
46 int VM_Version::_icache_line_size;
47 int VM_Version::_initial_sve_vector_length;
48 int VM_Version::_max_supported_sve_vector_length;
49 bool VM_Version::_rop_protection;
50 uintptr_t VM_Version::_pac_mask;
51
52 const char* VM_Version::_features_names[MAX_CPU_FEATURES] = { nullptr };
53
54 SpinWait VM_Version::_spin_wait;
55
56 static SpinWait get_spin_wait_desc() {
57 if (strcmp(OnSpinWaitInst, "nop") == 0) {
58 return SpinWait(SpinWait::NOP, OnSpinWaitInstCount);
59 } else if (strcmp(OnSpinWaitInst, "isb") == 0) {
60 return SpinWait(SpinWait::ISB, OnSpinWaitInstCount);
61 } else if (strcmp(OnSpinWaitInst, "yield") == 0) {
62 return SpinWait(SpinWait::YIELD, OnSpinWaitInstCount);
63 } else if (strcmp(OnSpinWaitInst, "none") != 0) {
64 vm_exit_during_initialization("The options for OnSpinWaitInst are nop, isb, yield, and none", OnSpinWaitInst);
65 }
66
67 if (!FLAG_IS_DEFAULT(OnSpinWaitInstCount) && OnSpinWaitInstCount > 0) {
68 vm_exit_during_initialization("OnSpinWaitInstCount cannot be used for OnSpinWaitInst 'none'");
69 }
70
71 return SpinWait{};
72 }
73
74 void VM_Version::initialize() {
75 #define SET_CPU_FEATURE_NAME(id, name, bit) \
76 _features_names[bit] = XSTR(name);
77 CPU_FEATURE_FLAGS(SET_CPU_FEATURE_NAME)
78 #undef SET_CPU_FEATURE_NAME
79
80 _supports_atomic_getset4 = true;
81 _supports_atomic_getadd4 = true;
82 _supports_atomic_getset8 = true;
83 _supports_atomic_getadd8 = true;
84
85 get_os_cpu_info();
86
87 int dcache_line = VM_Version::dcache_line_size();
88
89 // Limit AllocatePrefetchDistance so that it does not exceed the
90 // static constraint of 512 defined in runtime/globals.hpp.
91 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
92 FLAG_SET_DEFAULT(AllocatePrefetchDistance, MIN2(512, 3*dcache_line));
93
94 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
95 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
96 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
97 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
98 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
99 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
194 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
195 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
196 }
197 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
198 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
199 }
200 }
201
202 // HiSilicon TSV110
203 if (_cpu == CPU_HISILICON && _model == 0xd01) {
204 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
205 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
206 }
207 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
208 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
209 }
210 }
211
212 // Cortex A53
213 if (_cpu == CPU_ARM && model_is(0xd03)) {
214 set_feature(CPU_A53MAC);
215 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
216 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
217 }
218 }
219
220 // Cortex A73
221 if (_cpu == CPU_ARM && model_is(0xd09)) {
222 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
223 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
224 }
225 // A73 is faster with short-and-easy-for-speculative-execution-loop
226 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
227 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
228 }
229 }
230
231 // Neoverse
232 // N1: 0xd0c
233 // N2: 0xd49
234 // V1: 0xd40
235 // V2: 0xd4f
236 if (_cpu == CPU_ARM && (model_is(0xd0c) || model_is(0xd49) ||
237 model_is(0xd40) || model_is(0xd4f))) {
238 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
239 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
240 }
241
242 if (FLAG_IS_DEFAULT(OnSpinWaitInst)) {
243 FLAG_SET_DEFAULT(OnSpinWaitInst, "isb");
244 }
245
246 if (FLAG_IS_DEFAULT(OnSpinWaitInstCount)) {
247 FLAG_SET_DEFAULT(OnSpinWaitInstCount, 1);
248 }
249 if (FLAG_IS_DEFAULT(AlwaysMergeDMB)) {
250 FLAG_SET_DEFAULT(AlwaysMergeDMB, false);
251 }
252 }
253
254 if (supports_feature(CPU_FP) || supports_feature(CPU_ASIMD)) {
255 if (FLAG_IS_DEFAULT(UseSignumIntrinsic)) {
256 FLAG_SET_DEFAULT(UseSignumIntrinsic, true);
257 }
258 }
259
260 if (FLAG_IS_DEFAULT(UseCRC32)) {
261 UseCRC32 = VM_Version::supports_crc32();
262 }
263
264 if (UseCRC32 && !VM_Version::supports_crc32()) {
265 warning("UseCRC32 specified, but not supported on this CPU");
266 FLAG_SET_DEFAULT(UseCRC32, false);
267 }
268
269 // Neoverse
270 // V1: 0xd40
271 // V2: 0xd4f
272 if (_cpu == CPU_ARM && (model_is(0xd40) || model_is(0xd4f))) {
273 if (FLAG_IS_DEFAULT(UseCryptoPmullForCRC32)) {
274 FLAG_SET_DEFAULT(UseCryptoPmullForCRC32, true);
397 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
398 }
399 } else if (UseSHA512Intrinsics) {
400 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
401 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
402 }
403
404 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA3Intrinsics || UseSHA512Intrinsics)) {
405 FLAG_SET_DEFAULT(UseSHA, false);
406 }
407
408 if (VM_Version::supports_pmull()) {
409 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
410 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
411 }
412 } else if (UseGHASHIntrinsics) {
413 warning("GHASH intrinsics are not available on this CPU");
414 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
415 }
416
417 if (supports_feature(CPU_ASIMD)) {
418 if (FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
419 UseChaCha20Intrinsics = true;
420 }
421 } else if (UseChaCha20Intrinsics) {
422 if (!FLAG_IS_DEFAULT(UseChaCha20Intrinsics)) {
423 warning("ChaCha20 intrinsic requires ASIMD instructions");
424 }
425 FLAG_SET_DEFAULT(UseChaCha20Intrinsics, false);
426 }
427
428 if (supports_feature(CPU_ASIMD)) {
429 if (FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
430 UseKyberIntrinsics = true;
431 }
432 } else if (UseKyberIntrinsics) {
433 if (!FLAG_IS_DEFAULT(UseKyberIntrinsics)) {
434 warning("Kyber intrinsics require ASIMD instructions");
435 }
436 FLAG_SET_DEFAULT(UseKyberIntrinsics, false);
437 }
438
439 if (supports_feature(CPU_ASIMD)) {
440 if (FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
441 UseDilithiumIntrinsics = true;
442 }
443 } else if (UseDilithiumIntrinsics) {
444 if (!FLAG_IS_DEFAULT(UseDilithiumIntrinsics)) {
445 warning("Dilithium intrinsics require ASIMD instructions");
446 }
447 FLAG_SET_DEFAULT(UseDilithiumIntrinsics, false);
448 }
449
450 if (FLAG_IS_DEFAULT(UseBASE64Intrinsics)) {
451 UseBASE64Intrinsics = true;
452 }
453
454 if (is_zva_enabled()) {
455 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
456 FLAG_SET_DEFAULT(UseBlockZeroing, true);
457 }
458 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
459 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
620
621 if (FLAG_IS_DEFAULT(AlignVector)) {
622 AlignVector = AvoidUnalignedAccesses;
623 }
624
625 if (FLAG_IS_DEFAULT(UsePoly1305Intrinsics)) {
626 FLAG_SET_DEFAULT(UsePoly1305Intrinsics, true);
627 }
628
629 if (FLAG_IS_DEFAULT(UseVectorizedHashCodeIntrinsic)) {
630 FLAG_SET_DEFAULT(UseVectorizedHashCodeIntrinsic, true);
631 }
632 #endif
633
634 _spin_wait = get_spin_wait_desc();
635
636 check_virtualizations();
637
638 // Sync SVE related CPU features with flags
639 if (UseSVE < 2) {
640 clear_feature(CPU_SVE2);
641 clear_feature(CPU_SVEBITPERM);
642 }
643 if (UseSVE < 1) {
644 clear_feature(CPU_SVE);
645 }
646
647 // Construct the "features" string
648 stringStream ss(512);
649 ss.print("0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
650 if (_model2) {
651 ss.print("(0x%03x)", _model2);
652 }
653 ss.print(", ");
654 int features_offset = (int)ss.size();
655 insert_features_names(_features, ss);
656
657 _cpu_info_string = ss.as_string(true);
658 _features_string = _cpu_info_string + features_offset;
659 }
660
661 #if defined(LINUX)
662 static bool check_info_file(const char* fpath,
663 const char* virt1, VirtualizationType vt1,
664 const char* virt2, VirtualizationType vt2) {
665 char line[500];
666 FILE* fp = os::fopen(fpath, "r");
667 if (fp == nullptr) {
668 return false;
669 }
670 while (fgets(line, sizeof(line), fp) != nullptr) {
671 if (strcasestr(line, virt1) != nullptr) {
672 Abstract_VM_Version::_detected_virtualization = vt1;
673 fclose(fp);
674 return true;
675 }
676 if (virt2 != nullptr && strcasestr(line, virt2) != nullptr) {
677 Abstract_VM_Version::_detected_virtualization = vt2;
678 fclose(fp);
709 }
710
711 void VM_Version::initialize_cpu_information(void) {
712 // do nothing if cpu info has been initialized
713 if (_initialized) {
714 return;
715 }
716
717 _no_of_cores = os::processor_count();
718 _no_of_threads = _no_of_cores;
719 _no_of_sockets = _no_of_cores;
720 snprintf(_cpu_name, CPU_TYPE_DESC_BUF_SIZE - 1, "AArch64");
721
722 int desc_len = snprintf(_cpu_desc, CPU_DETAILED_DESC_BUF_SIZE, "AArch64 ");
723 get_compatible_board(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len);
724 desc_len = (int)strlen(_cpu_desc);
725 snprintf(_cpu_desc + desc_len, CPU_DETAILED_DESC_BUF_SIZE - desc_len, " %s", _cpu_info_string);
726
727 _initialized = true;
728 }
729
730 void VM_Version::insert_features_names(uint64_t features, stringStream& ss) {
731 int i = 0;
732 ss.join([&]() {
733 const char* str = nullptr;
734 while ((i < MAX_CPU_FEATURES) && (str == nullptr)) {
735 if (supports_feature((VM_Version::Feature_Flag)i)) {
736 str = _features_names[i];
737 }
738 i += 1;
739 }
740 return str;
741 }, ", ");
742 }
743
744 void VM_Version::get_cpu_features_name(void* features_buffer, stringStream& ss) {
745 uint64_t features = *(uint64_t*)features_buffer;
746 insert_features_names(features, ss);
747 }
748
749 void VM_Version::get_missing_features_name(void* features_buffer, stringStream& ss) {
750 uint64_t features_to_test = *(uint64_t*)features_buffer;
751 int i = 0;
752 ss.join([&]() {
753 const char* str = nullptr;
754 while ((i < MAX_CPU_FEATURES) && (str == nullptr)) {
755 Feature_Flag flag = (Feature_Flag)i;
756 if (supports_feature(features_to_test, flag) && !supports_feature(flag)) {
757 str = _features_names[i];
758 }
759 i += 1;
760 }
761 return str;
762 }, ", ");
763 }
764
765 int VM_Version::cpu_features_size() {
766 return sizeof(_features);
767 }
768
769 void VM_Version::store_cpu_features(void* buf) {
770 *(uint64_t*)buf = _features;
771 }
772
773 bool VM_Version::supports_features(void* features_buffer) {
774 uint64_t features_to_test = *(uint64_t*)features_buffer;
775 return (_features & features_to_test) == features_to_test;
776 }
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