48
49 static int _zva_length;
50 static int _dcache_line_size;
51 static int _icache_line_size;
52 static int _initial_sve_vector_length;
53 static int _max_supported_sve_vector_length;
54 static bool _rop_protection;
55 static uintptr_t _pac_mask;
56
57 static SpinWait _spin_wait;
58
59 // Read additional info using OS-specific interfaces
60 static void get_os_cpu_info();
61
62 // Sets the SVE length and returns a new actual value or negative on error.
63 // If the len is larger than the system largest supported SVE vector length,
64 // the function sets the largest supported value.
65 static int set_and_get_current_sve_vector_length(int len);
66 static int get_current_sve_vector_length();
67
68 public:
69 // Initialization
70 static void initialize();
71 static void check_virtualizations();
72
73 static void insert_features_names(uint64_t features, stringStream& ss);
74
75 static void print_platform_virtualization_info(outputStream*);
76
77 // Asserts
78 static void assert_is_initialized() {
79 }
80
81 static bool expensive_load(int ld_size, int scale) {
82 if (cpu_family() == CPU_ARM) {
83 // Half-word load with index shift by 1 (aka scale is 2) has
84 // extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1].
85 if (ld_size == 2 && scale == 2) {
86 return true;
87 }
88 }
89 return false;
90 }
91
92 // The CPU implementer codes can be found in
93 // ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
94 // https://developer.arm.com/docs/ddi0487/latest
153
154 STATIC_ASSERT(sizeof(_features) * BitsPerByte >= MAX_CPU_FEATURES);
155
156 static const char* _features_names[MAX_CPU_FEATURES];
157
158 // Feature identification
159 #define CPU_FEATURE_DETECTION(id, name, bit) \
160 static bool supports_##name() { return supports_feature(CPU_##id); }
161 CPU_FEATURE_FLAGS(CPU_FEATURE_DETECTION)
162 #undef CPU_FEATURE_DETECTION
163
164 static void set_feature(Feature_Flag flag) {
165 _features |= BIT_MASK(flag);
166 }
167 static void clear_feature(Feature_Flag flag) {
168 _features &= (~BIT_MASK(flag));
169 }
170 static bool supports_feature(Feature_Flag flag) {
171 return (_features & BIT_MASK(flag)) != 0;
172 }
173
174 static int cpu_family() { return _cpu; }
175 static int cpu_model() { return _model; }
176 static int cpu_model2() { return _model2; }
177 static int cpu_variant() { return _variant; }
178 static int cpu_revision() { return _revision; }
179
180 static bool model_is(int cpu_model) {
181 return _model == cpu_model || _model2 == cpu_model;
182 }
183
184 static bool is_zva_enabled() { return 0 <= _zva_length; }
185 static int zva_length() {
186 assert(is_zva_enabled(), "ZVA not available");
187 return _zva_length;
188 }
189
190 static int icache_line_size() { return _icache_line_size; }
191 static int dcache_line_size() { return _dcache_line_size; }
192 static int get_initial_sve_vector_length() { return _initial_sve_vector_length; };
204 static const SpinWait& spin_wait_desc() { return _spin_wait; }
205
206 static bool supports_on_spin_wait() { return _spin_wait.inst() != SpinWait::NONE; }
207
208 static bool supports_float16() { return true; }
209
210 #ifdef __APPLE__
211 // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
212 static bool is_cpu_emulated();
213 #endif
214
215 static void initialize_cpu_information(void);
216
217 static bool use_rop_protection() { return _rop_protection; }
218
219 // For common 64/128-bit unpredicated vector operations, we may prefer
220 // emitting NEON instructions rather than the corresponding SVE instructions.
221 static bool use_neon_for_vector(int vector_length_in_bytes) {
222 return vector_length_in_bytes <= 16;
223 }
224 };
225
226 #endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP
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48
49 static int _zva_length;
50 static int _dcache_line_size;
51 static int _icache_line_size;
52 static int _initial_sve_vector_length;
53 static int _max_supported_sve_vector_length;
54 static bool _rop_protection;
55 static uintptr_t _pac_mask;
56
57 static SpinWait _spin_wait;
58
59 // Read additional info using OS-specific interfaces
60 static void get_os_cpu_info();
61
62 // Sets the SVE length and returns a new actual value or negative on error.
63 // If the len is larger than the system largest supported SVE vector length,
64 // the function sets the largest supported value.
65 static int set_and_get_current_sve_vector_length(int len);
66 static int get_current_sve_vector_length();
67
68 static void insert_features_names(uint64_t features, stringStream& ss);
69
70 public:
71 // Initialization
72 static void initialize();
73 static void check_virtualizations();
74
75 static void print_platform_virtualization_info(outputStream*);
76
77 // Asserts
78 static void assert_is_initialized() {
79 }
80
81 static bool expensive_load(int ld_size, int scale) {
82 if (cpu_family() == CPU_ARM) {
83 // Half-word load with index shift by 1 (aka scale is 2) has
84 // extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1].
85 if (ld_size == 2 && scale == 2) {
86 return true;
87 }
88 }
89 return false;
90 }
91
92 // The CPU implementer codes can be found in
93 // ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
94 // https://developer.arm.com/docs/ddi0487/latest
153
154 STATIC_ASSERT(sizeof(_features) * BitsPerByte >= MAX_CPU_FEATURES);
155
156 static const char* _features_names[MAX_CPU_FEATURES];
157
158 // Feature identification
159 #define CPU_FEATURE_DETECTION(id, name, bit) \
160 static bool supports_##name() { return supports_feature(CPU_##id); }
161 CPU_FEATURE_FLAGS(CPU_FEATURE_DETECTION)
162 #undef CPU_FEATURE_DETECTION
163
164 static void set_feature(Feature_Flag flag) {
165 _features |= BIT_MASK(flag);
166 }
167 static void clear_feature(Feature_Flag flag) {
168 _features &= (~BIT_MASK(flag));
169 }
170 static bool supports_feature(Feature_Flag flag) {
171 return (_features & BIT_MASK(flag)) != 0;
172 }
173 static bool supports_feature(uint64_t features, Feature_Flag flag) {
174 return (features & BIT_MASK(flag)) != 0;
175 }
176
177 static int cpu_family() { return _cpu; }
178 static int cpu_model() { return _model; }
179 static int cpu_model2() { return _model2; }
180 static int cpu_variant() { return _variant; }
181 static int cpu_revision() { return _revision; }
182
183 static bool model_is(int cpu_model) {
184 return _model == cpu_model || _model2 == cpu_model;
185 }
186
187 static bool is_zva_enabled() { return 0 <= _zva_length; }
188 static int zva_length() {
189 assert(is_zva_enabled(), "ZVA not available");
190 return _zva_length;
191 }
192
193 static int icache_line_size() { return _icache_line_size; }
194 static int dcache_line_size() { return _dcache_line_size; }
195 static int get_initial_sve_vector_length() { return _initial_sve_vector_length; };
207 static const SpinWait& spin_wait_desc() { return _spin_wait; }
208
209 static bool supports_on_spin_wait() { return _spin_wait.inst() != SpinWait::NONE; }
210
211 static bool supports_float16() { return true; }
212
213 #ifdef __APPLE__
214 // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
215 static bool is_cpu_emulated();
216 #endif
217
218 static void initialize_cpu_information(void);
219
220 static bool use_rop_protection() { return _rop_protection; }
221
222 // For common 64/128-bit unpredicated vector operations, we may prefer
223 // emitting NEON instructions rather than the corresponding SVE instructions.
224 static bool use_neon_for_vector(int vector_length_in_bytes) {
225 return vector_length_in_bytes <= 16;
226 }
227
228 static void get_cpu_features_name(void* features_buffer, stringStream& ss);
229 static void get_missing_features_name(void* features_buffer, stringStream& ss);
230
231 // Returns number of bytes required to store cpu features representation
232 static int cpu_features_size();
233
234 // Stores cpu features representation in the provided buffer. This representation is arch dependent.
235 // Size of the buffer must be same as returned by cpu_features_size()
236 static void store_cpu_features(void* buf);
237
238 static bool supports_features(void* features_to_test);
239 };
240
241 #endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP
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