352
353 protected:
354 static int _cpu;
355 static int _model;
356 static int _stepping;
357
358 static bool _has_intel_jcc_erratum;
359
360 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
361 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
362 static address _cpuinfo_segv_addr_apx; // address of instruction which causes APX specific SEGV
363 static address _cpuinfo_cont_addr_apx; // address of instruction after the one which causes APX specific SEGV
364
365 /*
366 * Update following files when declaring new flags:
367 * test/lib-test/jdk/test/whitebox/CPUInfoTest.java
368 * src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/amd64/AMD64.java
369 */
370 enum Feature_Flag {
371 #define CPU_FEATURE_FLAGS(decl) \
372 decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \
373 decl(CMOV, "cmov", 1) \
374 decl(FXSR, "fxsr", 2) \
375 decl(HT, "ht", 3) \
376 \
377 decl(MMX, "mmx", 4) \
378 decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
379 /* may not necessarily support other 3dnow instructions */ \
380 decl(SSE, "sse", 6) \
381 decl(SSE2, "sse2", 7) \
382 \
383 decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
384 decl(SSSE3, "ssse3", 9 ) \
385 decl(SSE4A, "sse4a", 10) \
386 decl(SSE4_1, "sse4.1", 11) \
387 \
388 decl(SSE4_2, "sse4.2", 12) \
389 decl(POPCNT, "popcnt", 13) \
390 decl(LZCNT, "lzcnt", 14) \
391 decl(TSC, "tsc", 15) \
392 \
393 decl(TSCINV_BIT, "tscinvbit", 16) \
394 decl(TSCINV, "tscinv", 17) \
395 decl(AVX, "avx", 18) \
396 decl(AVX2, "avx2", 19) \
397 \
398 decl(AES, "aes", 20) \
399 decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \
400 decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \
401 decl(BMI1, "bmi1", 23) \
402 \
403 decl(BMI2, "bmi2", 24) \
404 decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \
405 decl(ADX, "adx", 26) \
406 decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \
407 \
408 decl(AVX512DQ, "avx512dq", 28) \
409 decl(AVX512PF, "avx512pf", 29) \
410 decl(AVX512ER, "avx512er", 30) \
411 decl(AVX512CD, "avx512cd", 31) \
412 \
413 decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \
414 decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \
415 decl(SHA, "sha", 34) /* SHA instructions */ \
416 decl(FMA, "fma", 35) /* FMA instructions */ \
417 \
418 decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \
419 decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \
420 decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
421 decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \
422 \
423 decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \
424 decl(FLUSH, "clflush", 41) /* flush instruction */ \
425 decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \
426 decl(CLWB, "clwb", 43) /* clwb instruction */ \
427 \
428 decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \
429 decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \
430 decl(HV, "hv", 46) /* Hypervisor instructions */ \
431 decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \
432 decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \
433 decl(RDPID, "rdpid", 49) /* RDPID instruction */ \
434 decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \
435 decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \
436 decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\
437 decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \
438 decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \
439 decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \
440 decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
441 decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \
442 decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \
443 decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
444 decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \
445 decl(SHA512, "sha512", 61) /* SHA512 instructions*/ \
446 decl(AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \
447 decl(AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \
448 decl(AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/ \
449 decl(HYBRID, "hybrid", 65) /* Hybrid architecture */
450
451 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),
452 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
453 #undef DECLARE_CPU_FEATURE_FLAG
454 MAX_CPU_FEATURES
455 };
456
457 class VM_Features {
458 friend class VMStructs;
459 friend class JVMCIVMStructs;
460
461 private:
462 uint64_t _features_bitmap[(MAX_CPU_FEATURES / BitsPerLong) + 1];
463
464 STATIC_ASSERT(sizeof(_features_bitmap) * BitsPerByte >= MAX_CPU_FEATURES);
465
466 // Number of 8-byte elements in _bitmap.
467 constexpr static int features_bitmap_element_count() {
468 return sizeof(_features_bitmap) / sizeof(uint64_t);
469 }
470
471 constexpr static int features_bitmap_element_shift_count() {
472 return LogBitsPerLong;
473 }
474
475 constexpr static uint64_t features_bitmap_element_mask() {
476 return (1ULL << features_bitmap_element_shift_count()) - 1;
477 }
478
479 static int index(Feature_Flag feature) {
480 int idx = feature >> features_bitmap_element_shift_count();
481 assert(idx < features_bitmap_element_count(), "Features array index out of bounds");
482 return idx;
483 }
484
485 static uint64_t bit_mask(Feature_Flag feature) {
486 return (1ULL << (feature & features_bitmap_element_mask()));
487 }
488
489 static int _features_bitmap_size; // for JVMCI purposes
490 public:
491 VM_Features() {
492 for (int i = 0; i < features_bitmap_element_count(); i++) {
493 _features_bitmap[i] = 0;
494 }
495 }
496
497 void set_feature(Feature_Flag feature) {
498 int idx = index(feature);
499 _features_bitmap[idx] |= bit_mask(feature);
500 }
501
502 void clear_feature(VM_Version::Feature_Flag feature) {
503 int idx = index(feature);
504 _features_bitmap[idx] &= ~bit_mask(feature);
505 }
506
507 bool supports_feature(VM_Version::Feature_Flag feature) {
508 int idx = index(feature);
509 return (_features_bitmap[idx] & bit_mask(feature)) != 0;
510 }
511 };
512
513 // CPU feature flags vector, can be affected by VM settings.
514 static VM_Features _features;
515
516 // Original CPU feature flags vector, not affected by VM settings.
517 static VM_Features _cpu_features;
518
519 static const char* _features_names[];
520
521 static void clear_cpu_features() {
522 _features = VM_Features();
523 _cpu_features = VM_Features();
524 }
525
526 enum Extended_Family {
527 // AMD
528 CPU_FAMILY_AMD_11H = 0x11,
529 CPU_FAMILY_AMD_17H = 0x17, /* Zen1 & Zen2 */
530 CPU_FAMILY_AMD_19H = 0x19, /* Zen3 & Zen4 */
1061 // Offsets for cpuid asm stub brand string
1062 static ByteSize proc_name_0_offset() { return byte_offset_of(CpuidInfo, proc_name_0); }
1063 static ByteSize proc_name_1_offset() { return byte_offset_of(CpuidInfo, proc_name_1); }
1064 static ByteSize proc_name_2_offset() { return byte_offset_of(CpuidInfo, proc_name_2); }
1065 static ByteSize proc_name_3_offset() { return byte_offset_of(CpuidInfo, proc_name_3); }
1066 static ByteSize proc_name_4_offset() { return byte_offset_of(CpuidInfo, proc_name_4); }
1067 static ByteSize proc_name_5_offset() { return byte_offset_of(CpuidInfo, proc_name_5); }
1068 static ByteSize proc_name_6_offset() { return byte_offset_of(CpuidInfo, proc_name_6); }
1069 static ByteSize proc_name_7_offset() { return byte_offset_of(CpuidInfo, proc_name_7); }
1070 static ByteSize proc_name_8_offset() { return byte_offset_of(CpuidInfo, proc_name_8); }
1071 static ByteSize proc_name_9_offset() { return byte_offset_of(CpuidInfo, proc_name_9); }
1072 static ByteSize proc_name_10_offset() { return byte_offset_of(CpuidInfo, proc_name_10); }
1073 static ByteSize proc_name_11_offset() { return byte_offset_of(CpuidInfo, proc_name_11); }
1074
1075 static int64_t maximum_qualified_cpu_frequency(void);
1076
1077 static bool supports_tscinv_ext(void);
1078
1079 static void initialize_tsc();
1080 static void initialize_cpu_information(void);
1081 };
1082
1083 #endif // CPU_X86_VM_VERSION_X86_HPP
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352
353 protected:
354 static int _cpu;
355 static int _model;
356 static int _stepping;
357
358 static bool _has_intel_jcc_erratum;
359
360 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
361 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
362 static address _cpuinfo_segv_addr_apx; // address of instruction which causes APX specific SEGV
363 static address _cpuinfo_cont_addr_apx; // address of instruction after the one which causes APX specific SEGV
364
365 /*
366 * Update following files when declaring new flags:
367 * test/lib-test/jdk/test/whitebox/CPUInfoTest.java
368 * src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/amd64/AMD64.java
369 */
370 enum Feature_Flag {
371 #define CPU_FEATURE_FLAGS(decl) \
372 decl(CX8, cx8, 0) /* next bits are from cpuid 1 (EDX) */ \
373 decl(CMOV, cmov, 1) \
374 decl(FXSR, fxsr, 2) \
375 decl(HT, ht, 3) \
376 \
377 decl(MMX, mmx, 4) \
378 decl(3DNOW_PREFETCH, 3dnowpref, 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
379 /* may not necessarily support other 3dnow instructions */ \
380 decl(SSE, sse, 6) \
381 decl(SSE2, sse2, 7) \
382 \
383 decl(SSE3, sse3, 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
384 decl(SSSE3, ssse3, 9 ) \
385 decl(SSE4A, sse4a, 10) \
386 decl(SSE4_1, sse4.1, 11) \
387 \
388 decl(SSE4_2, sse4.2, 12) \
389 decl(POPCNT, popcnt, 13) \
390 decl(LZCNT, lzcnt, 14) \
391 decl(TSC, tsc, 15) \
392 \
393 decl(TSCINV_BIT, tscinvbit, 16) \
394 decl(TSCINV, tscinv, 17) \
395 decl(AVX, avx, 18) \
396 decl(AVX2, avx2, 19) \
397 \
398 decl(AES, aes, 20) \
399 decl(ERMS, erms, 21) /* enhanced 'rep movsb/stosb' instructions */ \
400 decl(CLMUL, clmul, 22) /* carryless multiply for CRC */ \
401 decl(BMI1, bmi1, 23) \
402 \
403 decl(BMI2, bmi2, 24) \
404 decl(RTM, rtm, 25) /* Restricted Transactional Memory instructions */ \
405 decl(ADX, adx, 26) \
406 decl(AVX512F, avx512f, 27) /* AVX 512bit foundation instructions */ \
407 \
408 decl(AVX512DQ, avx512dq, 28) \
409 decl(AVX512PF, avx512pf, 29) \
410 decl(AVX512ER, avx512er, 30) \
411 decl(AVX512CD, avx512cd, 31) \
412 \
413 decl(AVX512BW, avx512bw, 32) /* Byte and word vector instructions */ \
414 decl(AVX512VL, avx512vl, 33) /* EVEX instructions with smaller vector length */ \
415 decl(SHA, sha, 34) /* SHA instructions */ \
416 decl(FMA, fma, 35) /* FMA instructions */ \
417 \
418 decl(VZEROUPPER, vzeroupper, 36) /* Vzeroupper instruction */ \
419 decl(AVX512_VPOPCNTDQ, avx512_vpopcntdq, 37) /* Vector popcount */ \
420 decl(AVX512_VPCLMULQDQ, avx512_vpclmulqdq, 38) /* Vector carryless multiplication */ \
421 decl(AVX512_VAES, avx512_vaes, 39) /* Vector AES instruction */ \
422 \
423 decl(AVX512_VNNI, avx512_vnni, 40) /* Vector Neural Network Instructions */ \
424 decl(FLUSH, clflush, 41) /* flush instruction */ \
425 decl(FLUSHOPT, clflushopt, 42) /* flusopth instruction */ \
426 decl(CLWB, clwb, 43) /* clwb instruction */ \
427 \
428 decl(AVX512_VBMI2, avx512_vbmi2, 44) /* VBMI2 shift left double instructions */ \
429 decl(AVX512_VBMI, avx512_vbmi, 45) /* Vector BMI instructions */ \
430 decl(HV, hv, 46) /* Hypervisor instructions */ \
431 decl(SERIALIZE, serialize, 47) /* CPU SERIALIZE */ \
432 decl(RDTSCP, rdtscp, 48) /* RDTSCP instruction */ \
433 decl(RDPID, rdpid, 49) /* RDPID instruction */ \
434 decl(FSRM, fsrm, 50) /* Fast Short REP MOV */ \
435 decl(GFNI, gfni, 51) /* Vector GFNI instructions */ \
436 decl(AVX512_BITALG, avx512_bitalg, 52) /* Vector sub-word popcount and bit gather instructions */\
437 decl(F16C, f16c, 53) /* Half-precision and single precision FP conversion instructions*/ \
438 decl(PKU, pku, 54) /* Protection keys for user-mode pages */ \
439 decl(OSPKE, ospke, 55) /* OS enables protection keys */ \
440 decl(CET_IBT, cet_ibt, 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
441 decl(CET_SS, cet_ss, 57) /* Control Flow Enforcement - Shadow Stack */ \
442 decl(AVX512_IFMA, avx512_ifma, 58) /* Integer Vector FMA instructions*/ \
443 decl(AVX_IFMA, avx_ifma, 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
444 decl(APX_F, apx_f, 60) /* Intel Advanced Performance Extensions*/ \
445 decl(SHA512, sha512, 61) /* SHA512 instructions*/ \
446 decl(AVX512_FP16, avx512_fp16, 62) /* AVX512 FP16 ISA support*/ \
447 decl(AVX10_1, avx10_1, 63) /* AVX10 512 bit vector ISA Version 1 support*/ \
448 decl(AVX10_2, avx10_2, 64) /* AVX10 512 bit vector ISA Version 2 support*/ \
449 decl(HYBRID, hybrid, 65) /* Hybrid architecture */
450
451 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),
452 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
453 #undef DECLARE_CPU_FEATURE_FLAG
454 MAX_CPU_FEATURES
455 };
456
457 class VM_Features {
458 friend class VMStructs;
459 friend class JVMCIVMStructs;
460
461 private:
462 uint64_t _features_bitmap[(MAX_CPU_FEATURES / BitsPerLong) + 1];
463
464 STATIC_ASSERT(sizeof(_features_bitmap) * BitsPerByte >= MAX_CPU_FEATURES);
465
466 // Number of 8-byte elements in _bitmap.
467 constexpr static int features_bitmap_element_count() {
468 return sizeof(_features_bitmap) / sizeof(uint64_t);
469 }
470
471 constexpr static int features_bitmap_element_shift_count() {
472 return LogBitsPerLong;
473 }
474
475 constexpr static uint64_t features_bitmap_element_mask() {
476 return (1ULL << features_bitmap_element_shift_count()) - 1;
477 }
478
479 static int index(Feature_Flag feature) {
480 int idx = feature >> features_bitmap_element_shift_count();
481 assert(idx < features_bitmap_element_count(), "Features array index out of bounds");
482 return idx;
483 }
484
485 static uint64_t bit_mask(Feature_Flag feature) {
486 return (1ULL << (feature & features_bitmap_element_mask()));
487 }
488
489 static int _features_bitmap_size; // for JVMCI purposes
490
491 public:
492 VM_Features() {
493 for (int i = 0; i < features_bitmap_element_count(); i++) {
494 _features_bitmap[i] = 0;
495 }
496 }
497
498 void set_feature(Feature_Flag feature) {
499 int idx = index(feature);
500 _features_bitmap[idx] |= bit_mask(feature);
501 }
502
503 void clear_feature(VM_Version::Feature_Flag feature) {
504 int idx = index(feature);
505 _features_bitmap[idx] &= ~bit_mask(feature);
506 }
507
508 bool supports_feature(VM_Version::Feature_Flag feature) {
509 int idx = index(feature);
510 return (_features_bitmap[idx] & bit_mask(feature)) != 0;
511 }
512
513 bool supports_features(VM_Features* features_to_test) {
514 for (int i = 0; i < features_bitmap_element_count(); i++) {
515 if ((_features_bitmap[i] & features_to_test->_features_bitmap[i]) != features_to_test->_features_bitmap[i]) {
516 return false;
517 }
518 }
519 return true;
520 }
521 };
522
523 // CPU feature flags vector, can be affected by VM settings.
524 static VM_Features _features;
525
526 // Original CPU feature flags vector, not affected by VM settings.
527 static VM_Features _cpu_features;
528
529 static const char* _features_names[];
530
531 static void clear_cpu_features() {
532 _features = VM_Features();
533 _cpu_features = VM_Features();
534 }
535
536 enum Extended_Family {
537 // AMD
538 CPU_FAMILY_AMD_11H = 0x11,
539 CPU_FAMILY_AMD_17H = 0x17, /* Zen1 & Zen2 */
540 CPU_FAMILY_AMD_19H = 0x19, /* Zen3 & Zen4 */
1071 // Offsets for cpuid asm stub brand string
1072 static ByteSize proc_name_0_offset() { return byte_offset_of(CpuidInfo, proc_name_0); }
1073 static ByteSize proc_name_1_offset() { return byte_offset_of(CpuidInfo, proc_name_1); }
1074 static ByteSize proc_name_2_offset() { return byte_offset_of(CpuidInfo, proc_name_2); }
1075 static ByteSize proc_name_3_offset() { return byte_offset_of(CpuidInfo, proc_name_3); }
1076 static ByteSize proc_name_4_offset() { return byte_offset_of(CpuidInfo, proc_name_4); }
1077 static ByteSize proc_name_5_offset() { return byte_offset_of(CpuidInfo, proc_name_5); }
1078 static ByteSize proc_name_6_offset() { return byte_offset_of(CpuidInfo, proc_name_6); }
1079 static ByteSize proc_name_7_offset() { return byte_offset_of(CpuidInfo, proc_name_7); }
1080 static ByteSize proc_name_8_offset() { return byte_offset_of(CpuidInfo, proc_name_8); }
1081 static ByteSize proc_name_9_offset() { return byte_offset_of(CpuidInfo, proc_name_9); }
1082 static ByteSize proc_name_10_offset() { return byte_offset_of(CpuidInfo, proc_name_10); }
1083 static ByteSize proc_name_11_offset() { return byte_offset_of(CpuidInfo, proc_name_11); }
1084
1085 static int64_t maximum_qualified_cpu_frequency(void);
1086
1087 static bool supports_tscinv_ext(void);
1088
1089 static void initialize_tsc();
1090 static void initialize_cpu_information(void);
1091
1092 static void get_cpu_features_name(void* features_buffer, stringStream& ss);
1093 static void get_missing_features_name(void* features_buffer, stringStream& ss);
1094
1095 // Returns number of bytes required to store cpu features representation
1096 static int cpu_features_size();
1097
1098 // Stores cpu features representation in the provided buffer. This representation is arch dependent.
1099 // Size of the buffer must be same as returned by cpu_features_size()
1100 static void store_cpu_features(void* buf);
1101
1102 static bool supports_features(void* features_to_test);
1103 };
1104
1105 #endif // CPU_X86_VM_VERSION_X86_HPP
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