13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VERSION_X86_HPP
27
28 #include "runtime/abstract_vm_version.hpp"
29 #include "utilities/debug.hpp"
30 #include "utilities/macros.hpp"
31 #include "utilities/sizes.hpp"
32
33 class VM_Version : public Abstract_VM_Version {
34 friend class VMStructs;
35 friend class JVMCIVMStructs;
36
37 public:
38 // cpuid result register layouts. These are all unions of a uint32_t
39 // (in case anyone wants access to the register as a whole) and a bitfield.
40
41 union StdCpuid1Eax {
42 uint32_t value;
43 struct {
44 uint32_t stepping : 4,
45 model : 4,
46 family : 4,
47 proc_type : 2,
48 : 2,
49 ext_model : 4,
50 ext_family : 8,
51 : 4;
52 } bits;
349
350 protected:
351 static int _cpu;
352 static int _model;
353 static int _stepping;
354
355 static bool _has_intel_jcc_erratum;
356
357 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
358 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
359 static address _cpuinfo_segv_addr_apx; // address of instruction which causes APX specific SEGV
360 static address _cpuinfo_cont_addr_apx; // address of instruction after the one which causes APX specific SEGV
361
362 /*
363 * Update following files when declaring new flags:
364 * test/lib-test/jdk/test/whitebox/CPUInfoTest.java
365 * src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/amd64/AMD64.java
366 */
367 enum Feature_Flag {
368 #define CPU_FEATURE_FLAGS(decl) \
369 decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \
370 decl(CMOV, "cmov", 1) \
371 decl(FXSR, "fxsr", 2) \
372 decl(HT, "ht", 3) \
373 \
374 decl(MMX, "mmx", 4) \
375 decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
376 /* may not necessarily support other 3dnow instructions */ \
377 decl(SSE, "sse", 6) \
378 decl(SSE2, "sse2", 7) \
379 \
380 decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
381 decl(SSSE3, "ssse3", 9 ) \
382 decl(SSE4A, "sse4a", 10) \
383 decl(SSE4_1, "sse4.1", 11) \
384 \
385 decl(SSE4_2, "sse4.2", 12) \
386 decl(POPCNT, "popcnt", 13) \
387 decl(LZCNT, "lzcnt", 14) \
388 decl(TSC, "tsc", 15) \
389 \
390 decl(TSCINV_BIT, "tscinvbit", 16) \
391 decl(TSCINV, "tscinv", 17) \
392 decl(AVX, "avx", 18) \
393 decl(AVX2, "avx2", 19) \
394 \
395 decl(AES, "aes", 20) \
396 decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \
397 decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \
398 decl(BMI1, "bmi1", 23) \
399 \
400 decl(BMI2, "bmi2", 24) \
401 decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \
402 decl(ADX, "adx", 26) \
403 decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \
404 \
405 decl(AVX512DQ, "avx512dq", 28) \
406 decl(AVX512PF, "avx512pf", 29) \
407 decl(AVX512ER, "avx512er", 30) \
408 decl(AVX512CD, "avx512cd", 31) \
409 \
410 decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \
411 decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \
412 decl(SHA, "sha", 34) /* SHA instructions */ \
413 decl(FMA, "fma", 35) /* FMA instructions */ \
414 \
415 decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \
416 decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \
417 decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
418 decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \
419 \
420 decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \
421 decl(FLUSH, "clflush", 41) /* flush instruction */ \
422 decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \
423 decl(CLWB, "clwb", 43) /* clwb instruction */ \
424 \
425 decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \
426 decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \
427 decl(HV, "hv", 46) /* Hypervisor instructions */ \
428 decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \
429 decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \
430 decl(RDPID, "rdpid", 49) /* RDPID instruction */ \
431 decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \
432 decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \
433 decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\
434 decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \
435 decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \
436 decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \
437 decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
438 decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \
439 decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \
440 decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
441 decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \
442 decl(SHA512, "sha512", 61) /* SHA512 instructions*/ \
443 decl(AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \
444 decl(AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \
445 decl(AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/
446
447 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),
448 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
449 #undef DECLARE_CPU_FEATURE_FLAG
450 MAX_CPU_FEATURES
451 };
452
453 class VM_Features {
454 friend class VMStructs;
455 friend class JVMCIVMStructs;
456
457 private:
458 uint64_t _features_bitmap[(MAX_CPU_FEATURES / BitsPerLong) + 1];
459
460 STATIC_ASSERT(sizeof(_features_bitmap) * BitsPerByte >= MAX_CPU_FEATURES);
461
462 // Number of 8-byte elements in _bitmap.
463 constexpr static int features_bitmap_element_count() {
464 return sizeof(_features_bitmap) / sizeof(uint64_t);
465 }
466
467 constexpr static int features_bitmap_element_shift_count() {
468 return LogBitsPerLong;
469 }
470
471 constexpr static uint64_t features_bitmap_element_mask() {
472 return (1ULL << features_bitmap_element_shift_count()) - 1;
473 }
474
475 static int index(Feature_Flag feature) {
476 int idx = feature >> features_bitmap_element_shift_count();
477 assert(idx < features_bitmap_element_count(), "Features array index out of bounds");
478 return idx;
479 }
480
481 static uint64_t bit_mask(Feature_Flag feature) {
482 return (1ULL << (feature & features_bitmap_element_mask()));
483 }
484
485 static int _features_bitmap_size; // for JVMCI purposes
486 public:
487 VM_Features() {
488 for (int i = 0; i < features_bitmap_element_count(); i++) {
489 _features_bitmap[i] = 0;
490 }
491 }
492
493 void set_feature(Feature_Flag feature) {
494 int idx = index(feature);
495 _features_bitmap[idx] |= bit_mask(feature);
496 }
497
498 void clear_feature(VM_Version::Feature_Flag feature) {
499 int idx = index(feature);
500 _features_bitmap[idx] &= ~bit_mask(feature);
501 }
502
503 bool supports_feature(VM_Version::Feature_Flag feature) {
504 int idx = index(feature);
505 return (_features_bitmap[idx] & bit_mask(feature)) != 0;
506 }
507 };
508
509 // CPU feature flags vector, can be affected by VM settings.
510 static VM_Features _features;
511
512 // Original CPU feature flags vector, not affected by VM settings.
513 static VM_Features _cpu_features;
514
515 static const char* _features_names[];
516
517 static void clear_cpu_features() {
518 _features = VM_Features();
519 _cpu_features = VM_Features();
520 }
521
522 enum Extended_Family {
523 // AMD
524 CPU_FAMILY_AMD_11H = 0x11,
525 CPU_FAMILY_AMD_17H = 0x17, /* Zen1 & Zen2 */
526 CPU_FAMILY_AMD_19H = 0x19, /* Zen3 & Zen4 */
904 }
905
906 // Intel features
907 static bool is_intel_family_core() { return is_intel() &&
908 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
909
910 static bool is_intel_skylake() { return is_intel_family_core() &&
911 extended_cpu_model() == CPU_MODEL_SKYLAKE; }
912
913 #ifdef COMPILER2
914 // Determine if it's running on Cascade Lake using default options.
915 static bool is_default_intel_cascade_lake();
916 #endif
917
918 static bool is_intel_cascade_lake();
919
920 static int avx3_threshold();
921
922 static bool is_intel_tsc_synched_at_init();
923
924 static void insert_features_names(VM_Version::VM_Features features, char* buf, size_t buflen);
925
926 // This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102)
927 // that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode
928 // mitigation causes regressions when jumps or fused conditional branches cross or end at
929 // 32 byte boundaries.
930 static bool has_intel_jcc_erratum() { return _has_intel_jcc_erratum; }
931
932 // AMD features
933 static bool supports_3dnow_prefetch() { return _features.supports_feature(CPU_3DNOW_PREFETCH); }
934 static bool supports_lzcnt() { return _features.supports_feature(CPU_LZCNT); }
935 static bool supports_sse4a() { return _features.supports_feature(CPU_SSE4A); }
936
937 static bool is_amd_Barcelona() { return is_amd() &&
938 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
939
940 // Intel and AMD newer cores support fast timestamps well
941 static bool supports_tscinv_bit() {
942 return _features.supports_feature(CPU_TSCINV_BIT);
943 }
944 static bool supports_tscinv() {
1055 // Offsets for cpuid asm stub brand string
1056 static ByteSize proc_name_0_offset() { return byte_offset_of(CpuidInfo, proc_name_0); }
1057 static ByteSize proc_name_1_offset() { return byte_offset_of(CpuidInfo, proc_name_1); }
1058 static ByteSize proc_name_2_offset() { return byte_offset_of(CpuidInfo, proc_name_2); }
1059 static ByteSize proc_name_3_offset() { return byte_offset_of(CpuidInfo, proc_name_3); }
1060 static ByteSize proc_name_4_offset() { return byte_offset_of(CpuidInfo, proc_name_4); }
1061 static ByteSize proc_name_5_offset() { return byte_offset_of(CpuidInfo, proc_name_5); }
1062 static ByteSize proc_name_6_offset() { return byte_offset_of(CpuidInfo, proc_name_6); }
1063 static ByteSize proc_name_7_offset() { return byte_offset_of(CpuidInfo, proc_name_7); }
1064 static ByteSize proc_name_8_offset() { return byte_offset_of(CpuidInfo, proc_name_8); }
1065 static ByteSize proc_name_9_offset() { return byte_offset_of(CpuidInfo, proc_name_9); }
1066 static ByteSize proc_name_10_offset() { return byte_offset_of(CpuidInfo, proc_name_10); }
1067 static ByteSize proc_name_11_offset() { return byte_offset_of(CpuidInfo, proc_name_11); }
1068
1069 static int64_t maximum_qualified_cpu_frequency(void);
1070
1071 static bool supports_tscinv_ext(void);
1072
1073 static void initialize_tsc();
1074 static void initialize_cpu_information(void);
1075 };
1076
1077 #endif // CPU_X86_VM_VERSION_X86_HPP
|
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VERSION_X86_HPP
27
28 #include "runtime/abstract_vm_version.hpp"
29 #include "utilities/debug.hpp"
30 #include "utilities/macros.hpp"
31 #include "utilities/sizes.hpp"
32
33 class stringStream;
34
35 class VM_Version : public Abstract_VM_Version {
36 friend class VMStructs;
37 friend class JVMCIVMStructs;
38
39 public:
40 // cpuid result register layouts. These are all unions of a uint32_t
41 // (in case anyone wants access to the register as a whole) and a bitfield.
42
43 union StdCpuid1Eax {
44 uint32_t value;
45 struct {
46 uint32_t stepping : 4,
47 model : 4,
48 family : 4,
49 proc_type : 2,
50 : 2,
51 ext_model : 4,
52 ext_family : 8,
53 : 4;
54 } bits;
351
352 protected:
353 static int _cpu;
354 static int _model;
355 static int _stepping;
356
357 static bool _has_intel_jcc_erratum;
358
359 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
360 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
361 static address _cpuinfo_segv_addr_apx; // address of instruction which causes APX specific SEGV
362 static address _cpuinfo_cont_addr_apx; // address of instruction after the one which causes APX specific SEGV
363
364 /*
365 * Update following files when declaring new flags:
366 * test/lib-test/jdk/test/whitebox/CPUInfoTest.java
367 * src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/amd64/AMD64.java
368 */
369 enum Feature_Flag {
370 #define CPU_FEATURE_FLAGS(decl) \
371 decl(CX8, cx8, 0) /* next bits are from cpuid 1 (EDX) */ \
372 decl(CMOV, cmov, 1) \
373 decl(FXSR, fxsr, 2) \
374 decl(HT, ht, 3) \
375 \
376 decl(MMX, mmx, 4) \
377 decl(3DNOW_PREFETCH, 3dnowpref, 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
378 /* may not necessarily support other 3dnow instructions */ \
379 decl(SSE, sse, 6) \
380 decl(SSE2, sse2, 7) \
381 \
382 decl(SSE3, sse3, 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
383 decl(SSSE3, ssse3, 9 ) \
384 decl(SSE4A, sse4a, 10) \
385 decl(SSE4_1, sse4.1, 11) \
386 \
387 decl(SSE4_2, sse4.2, 12) \
388 decl(POPCNT, popcnt, 13) \
389 decl(LZCNT, lzcnt, 14) \
390 decl(TSC, tsc, 15) \
391 \
392 decl(TSCINV_BIT, tscinvbit, 16) \
393 decl(TSCINV, tscinv, 17) \
394 decl(AVX, avx, 18) \
395 decl(AVX2, avx2, 19) \
396 \
397 decl(AES, aes, 20) \
398 decl(ERMS, erms, 21) /* enhanced 'rep movsb/stosb' instructions */ \
399 decl(CLMUL, clmul, 22) /* carryless multiply for CRC */ \
400 decl(BMI1, bmi1, 23) \
401 \
402 decl(BMI2, bmi2, 24) \
403 decl(RTM, rtm, 25) /* Restricted Transactional Memory instructions */ \
404 decl(ADX, adx, 26) \
405 decl(AVX512F, avx512f, 27) /* AVX 512bit foundation instructions */ \
406 \
407 decl(AVX512DQ, avx512dq, 28) \
408 decl(AVX512PF, avx512pf, 29) \
409 decl(AVX512ER, avx512er, 30) \
410 decl(AVX512CD, avx512cd, 31) \
411 \
412 decl(AVX512BW, avx512bw, 32) /* Byte and word vector instructions */ \
413 decl(AVX512VL, avx512vl, 33) /* EVEX instructions with smaller vector length */ \
414 decl(SHA, sha, 34) /* SHA instructions */ \
415 decl(FMA, fma, 35) /* FMA instructions */ \
416 \
417 decl(VZEROUPPER, vzeroupper, 36) /* Vzeroupper instruction */ \
418 decl(AVX512_VPOPCNTDQ, avx512_vpopcntdq, 37) /* Vector popcount */ \
419 decl(AVX512_VPCLMULQDQ, avx512_vpclmulqdq, 38) /* Vector carryless multiplication */ \
420 decl(AVX512_VAES, avx512_vaes, 39) /* Vector AES instruction */ \
421 \
422 decl(AVX512_VNNI, avx512_vnni, 40) /* Vector Neural Network Instructions */ \
423 decl(FLUSH, clflush, 41) /* flush instruction */ \
424 decl(FLUSHOPT, clflushopt, 42) /* flusopth instruction */ \
425 decl(CLWB, clwb, 43) /* clwb instruction */ \
426 \
427 decl(AVX512_VBMI2, avx512_vbmi2, 44) /* VBMI2 shift left double instructions */ \
428 decl(AVX512_VBMI, avx512_vbmi, 45) /* Vector BMI instructions */ \
429 decl(HV, hv, 46) /* Hypervisor instructions */ \
430 decl(SERIALIZE, serialize, 47) /* CPU SERIALIZE */ \
431 decl(RDTSCP, rdtscp, 48) /* RDTSCP instruction */ \
432 decl(RDPID, rdpid, 49) /* RDPID instruction */ \
433 decl(FSRM, fsrm, 50) /* Fast Short REP MOV */ \
434 decl(GFNI, gfni, 51) /* Vector GFNI instructions */ \
435 decl(AVX512_BITALG, avx512_bitalg, 52) /* Vector sub-word popcount and bit gather instructions */\
436 decl(F16C, f16c, 53) /* Half-precision and single precision FP conversion instructions*/ \
437 decl(PKU, pku, 54) /* Protection keys for user-mode pages */ \
438 decl(OSPKE, ospke, 55) /* OS enables protection keys */ \
439 decl(CET_IBT, cet_ibt, 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
440 decl(CET_SS, cet_ss, 57) /* Control Flow Enforcement - Shadow Stack */ \
441 decl(AVX512_IFMA, avx512_ifma, 58) /* Integer Vector FMA instructions*/ \
442 decl(AVX_IFMA, avx_ifma, 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
443 decl(APX_F, apx_f, 60) /* Intel Advanced Performance Extensions*/ \
444 decl(SHA512, sha512, 61) /* SHA512 instructions*/ \
445 decl(AVX512_FP16, avx512_fp16, 62) /* AVX512 FP16 ISA support*/ \
446 decl(AVX10_1, avx10_1, 63) /* AVX10 512 bit vector ISA Version 1 support*/ \
447 decl(AVX10_2, avx10_2, 64) /* AVX10 512 bit vector ISA Version 2 support*/
448
449 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),
450 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
451 #undef DECLARE_CPU_FEATURE_FLAG
452 MAX_CPU_FEATURES
453 };
454
455 class VM_Features {
456 friend class VMStructs;
457 friend class JVMCIVMStructs;
458
459 private:
460 uint64_t _features_bitmap[(MAX_CPU_FEATURES / BitsPerLong) + 1];
461
462 STATIC_ASSERT(sizeof(_features_bitmap) * BitsPerByte >= MAX_CPU_FEATURES);
463
464 // Number of 8-byte elements in _bitmap.
465 constexpr static int features_bitmap_element_count() {
466 return sizeof(_features_bitmap) / sizeof(uint64_t);
467 }
468
469 constexpr static int features_bitmap_element_shift_count() {
470 return LogBitsPerLong;
471 }
472
473 constexpr static uint64_t features_bitmap_element_mask() {
474 return (1ULL << features_bitmap_element_shift_count()) - 1;
475 }
476
477 static int index(Feature_Flag feature) {
478 int idx = feature >> features_bitmap_element_shift_count();
479 assert(idx < features_bitmap_element_count(), "Features array index out of bounds");
480 return idx;
481 }
482
483 static uint64_t bit_mask(Feature_Flag feature) {
484 return (1ULL << (feature & features_bitmap_element_mask()));
485 }
486
487 static int _features_bitmap_size; // for JVMCI purposes
488
489 public:
490 VM_Features() {
491 for (int i = 0; i < features_bitmap_element_count(); i++) {
492 _features_bitmap[i] = 0;
493 }
494 }
495
496 void set_feature(Feature_Flag feature) {
497 int idx = index(feature);
498 _features_bitmap[idx] |= bit_mask(feature);
499 }
500
501 void clear_feature(VM_Version::Feature_Flag feature) {
502 int idx = index(feature);
503 _features_bitmap[idx] &= ~bit_mask(feature);
504 }
505
506 bool supports_feature(VM_Version::Feature_Flag feature) {
507 int idx = index(feature);
508 return (_features_bitmap[idx] & bit_mask(feature)) != 0;
509 }
510
511 bool supports_features(VM_Features* features_to_test) {
512 for (int i = 0; i < features_bitmap_element_count(); i++) {
513 if ((_features_bitmap[i] & features_to_test->_features_bitmap[i]) != features_to_test->_features_bitmap[i]) {
514 return false;
515 }
516 }
517 return true;
518 }
519 };
520
521 // CPU feature flags vector, can be affected by VM settings.
522 static VM_Features _features;
523
524 // Original CPU feature flags vector, not affected by VM settings.
525 static VM_Features _cpu_features;
526
527 static const char* _features_names[];
528
529 static void clear_cpu_features() {
530 _features = VM_Features();
531 _cpu_features = VM_Features();
532 }
533
534 enum Extended_Family {
535 // AMD
536 CPU_FAMILY_AMD_11H = 0x11,
537 CPU_FAMILY_AMD_17H = 0x17, /* Zen1 & Zen2 */
538 CPU_FAMILY_AMD_19H = 0x19, /* Zen3 & Zen4 */
916 }
917
918 // Intel features
919 static bool is_intel_family_core() { return is_intel() &&
920 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
921
922 static bool is_intel_skylake() { return is_intel_family_core() &&
923 extended_cpu_model() == CPU_MODEL_SKYLAKE; }
924
925 #ifdef COMPILER2
926 // Determine if it's running on Cascade Lake using default options.
927 static bool is_default_intel_cascade_lake();
928 #endif
929
930 static bool is_intel_cascade_lake();
931
932 static int avx3_threshold();
933
934 static bool is_intel_tsc_synched_at_init();
935
936 static void insert_features_names(VM_Version::VM_Features features, stringStream& ss);
937
938 // This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102)
939 // that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode
940 // mitigation causes regressions when jumps or fused conditional branches cross or end at
941 // 32 byte boundaries.
942 static bool has_intel_jcc_erratum() { return _has_intel_jcc_erratum; }
943
944 // AMD features
945 static bool supports_3dnow_prefetch() { return _features.supports_feature(CPU_3DNOW_PREFETCH); }
946 static bool supports_lzcnt() { return _features.supports_feature(CPU_LZCNT); }
947 static bool supports_sse4a() { return _features.supports_feature(CPU_SSE4A); }
948
949 static bool is_amd_Barcelona() { return is_amd() &&
950 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
951
952 // Intel and AMD newer cores support fast timestamps well
953 static bool supports_tscinv_bit() {
954 return _features.supports_feature(CPU_TSCINV_BIT);
955 }
956 static bool supports_tscinv() {
1067 // Offsets for cpuid asm stub brand string
1068 static ByteSize proc_name_0_offset() { return byte_offset_of(CpuidInfo, proc_name_0); }
1069 static ByteSize proc_name_1_offset() { return byte_offset_of(CpuidInfo, proc_name_1); }
1070 static ByteSize proc_name_2_offset() { return byte_offset_of(CpuidInfo, proc_name_2); }
1071 static ByteSize proc_name_3_offset() { return byte_offset_of(CpuidInfo, proc_name_3); }
1072 static ByteSize proc_name_4_offset() { return byte_offset_of(CpuidInfo, proc_name_4); }
1073 static ByteSize proc_name_5_offset() { return byte_offset_of(CpuidInfo, proc_name_5); }
1074 static ByteSize proc_name_6_offset() { return byte_offset_of(CpuidInfo, proc_name_6); }
1075 static ByteSize proc_name_7_offset() { return byte_offset_of(CpuidInfo, proc_name_7); }
1076 static ByteSize proc_name_8_offset() { return byte_offset_of(CpuidInfo, proc_name_8); }
1077 static ByteSize proc_name_9_offset() { return byte_offset_of(CpuidInfo, proc_name_9); }
1078 static ByteSize proc_name_10_offset() { return byte_offset_of(CpuidInfo, proc_name_10); }
1079 static ByteSize proc_name_11_offset() { return byte_offset_of(CpuidInfo, proc_name_11); }
1080
1081 static int64_t maximum_qualified_cpu_frequency(void);
1082
1083 static bool supports_tscinv_ext(void);
1084
1085 static void initialize_tsc();
1086 static void initialize_cpu_information(void);
1087
1088 static void get_cpu_features_name(void* features_buffer, stringStream& ss);
1089 static void get_missing_features_name(void* features_buffer, stringStream& ss);
1090
1091 // Returns number of bytes required to store cpu features representation
1092 static int cpu_features_size();
1093
1094 // Stores cpu features representation in the provided buffer. This representation is arch dependent.
1095 // Size of the buffer must be same as returned by cpu_features_size()
1096 static void store_cpu_features(void* buf);
1097
1098 static bool supports_features(void* features_to_test);
1099 };
1100
1101 #endif // CPU_X86_VM_VERSION_X86_HPP
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