360
361 protected:
362 static int _cpu;
363 static int _model;
364 static int _stepping;
365
366 static bool _has_intel_jcc_erratum;
367
368 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
369 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
370 static address _cpuinfo_segv_addr_apx; // address of instruction which causes APX specific SEGV
371 static address _cpuinfo_cont_addr_apx; // address of instruction after the one which causes APX specific SEGV
372
373 /*
374 * Update following files when declaring new flags:
375 * test/lib-test/jdk/test/whitebox/CPUInfoTest.java
376 * src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/amd64/AMD64.java
377 */
378 enum Feature_Flag {
379 #define CPU_FEATURE_FLAGS(decl) \
380 decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \
381 decl(CMOV, "cmov", 1) \
382 decl(FXSR, "fxsr", 2) \
383 decl(HT, "ht", 3) \
384 \
385 decl(MMX, "mmx", 4) \
386 decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
387 /* may not necessarily support other 3dnow instructions */ \
388 decl(SSE, "sse", 6) \
389 decl(SSE2, "sse2", 7) \
390 \
391 decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
392 decl(SSSE3, "ssse3", 9 ) \
393 decl(SSE4A, "sse4a", 10) \
394 decl(SSE4_1, "sse4.1", 11) \
395 \
396 decl(SSE4_2, "sse4.2", 12) \
397 decl(POPCNT, "popcnt", 13) \
398 decl(LZCNT, "lzcnt", 14) \
399 decl(TSC, "tsc", 15) \
400 \
401 decl(TSCINV_BIT, "tscinvbit", 16) \
402 decl(TSCINV, "tscinv", 17) \
403 decl(AVX, "avx", 18) \
404 decl(AVX2, "avx2", 19) \
405 \
406 decl(AES, "aes", 20) \
407 decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \
408 decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \
409 decl(BMI1, "bmi1", 23) \
410 \
411 decl(BMI2, "bmi2", 24) \
412 decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \
413 decl(ADX, "adx", 26) \
414 decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \
415 \
416 decl(AVX512DQ, "avx512dq", 28) \
417 decl(AVX512PF, "avx512pf", 29) \
418 decl(AVX512ER, "avx512er", 30) \
419 decl(AVX512CD, "avx512cd", 31) \
420 \
421 decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \
422 decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \
423 decl(SHA, "sha", 34) /* SHA instructions */ \
424 decl(FMA, "fma", 35) /* FMA instructions */ \
425 \
426 decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \
427 decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \
428 decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
429 decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \
430 \
431 decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \
432 decl(FLUSH, "clflush", 41) /* flush instruction */ \
433 decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \
434 decl(CLWB, "clwb", 43) /* clwb instruction */ \
435 \
436 decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \
437 decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \
438 decl(HV, "hv", 46) /* Hypervisor instructions */ \
439 decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \
440 decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \
441 decl(RDPID, "rdpid", 49) /* RDPID instruction */ \
442 decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \
443 decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \
444 decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\
445 decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \
446 decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \
447 decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \
448 decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
449 decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \
450 decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \
451 decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
452 decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/ \
453 decl(SHA512, "sha512", 61) /* SHA512 instructions*/ \
454 decl(AVX512_FP16, "avx512_fp16", 62) /* AVX512 FP16 ISA support*/ \
455 decl(AVX10_1, "avx10_1", 63) /* AVX10 512 bit vector ISA Version 1 support*/ \
456 decl(AVX10_2, "avx10_2", 64) /* AVX10 512 bit vector ISA Version 2 support*/ \
457 decl(HYBRID, "hybrid", 65) /* Hybrid architecture */
458
459 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),
460 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
461 #undef DECLARE_CPU_FEATURE_FLAG
462 MAX_CPU_FEATURES
463 };
464
465 class VM_Features {
466 friend class VMStructs;
467 friend class JVMCIVMStructs;
468
469 private:
470 uint64_t _features_bitmap[(MAX_CPU_FEATURES / BitsPerLong) + 1];
471
472 STATIC_ASSERT(sizeof(_features_bitmap) * BitsPerByte >= MAX_CPU_FEATURES);
473
474 // Number of 8-byte elements in _bitmap.
475 constexpr static int features_bitmap_element_count() {
476 return sizeof(_features_bitmap) / sizeof(uint64_t);
477 }
478
479 constexpr static int features_bitmap_element_shift_count() {
480 return LogBitsPerLong;
481 }
482
483 constexpr static uint64_t features_bitmap_element_mask() {
484 return (1ULL << features_bitmap_element_shift_count()) - 1;
485 }
486
487 static int index(Feature_Flag feature) {
488 int idx = feature >> features_bitmap_element_shift_count();
489 assert(idx < features_bitmap_element_count(), "Features array index out of bounds");
490 return idx;
491 }
492
493 static uint64_t bit_mask(Feature_Flag feature) {
494 return (1ULL << (feature & features_bitmap_element_mask()));
495 }
496
497 static int _features_bitmap_size; // for JVMCI purposes
498 public:
499 VM_Features() {
500 for (int i = 0; i < features_bitmap_element_count(); i++) {
501 _features_bitmap[i] = 0;
502 }
503 }
504
505 void set_feature(Feature_Flag feature) {
506 int idx = index(feature);
507 _features_bitmap[idx] |= bit_mask(feature);
508 }
509
510 void clear_feature(VM_Version::Feature_Flag feature) {
511 int idx = index(feature);
512 _features_bitmap[idx] &= ~bit_mask(feature);
513 }
514
515 bool supports_feature(VM_Version::Feature_Flag feature) {
516 int idx = index(feature);
517 return (_features_bitmap[idx] & bit_mask(feature)) != 0;
518 }
519 };
520
521 // CPU feature flags vector, can be affected by VM settings.
522 static VM_Features _features;
523
524 // Original CPU feature flags vector, not affected by VM settings.
525 static VM_Features _cpu_features;
526
527 static const char* _features_names[];
528
529 static void clear_cpu_features() {
530 _features = VM_Features();
531 _cpu_features = VM_Features();
532 }
533
534 enum Extended_Family {
535 // AMD
536 CPU_FAMILY_AMD_11H = 0x11,
537 CPU_FAMILY_AMD_17H = 0x17, /* Zen1 & Zen2 */
538 CPU_FAMILY_AMD_19H = 0x19, /* Zen3 & Zen4 */
1077 public:
1078 // Offsets for cpuid asm stub brand string
1079 static ByteSize proc_name_0_offset() { return byte_offset_of(CpuidInfo, proc_name_0); }
1080 static ByteSize proc_name_1_offset() { return byte_offset_of(CpuidInfo, proc_name_1); }
1081 static ByteSize proc_name_2_offset() { return byte_offset_of(CpuidInfo, proc_name_2); }
1082 static ByteSize proc_name_3_offset() { return byte_offset_of(CpuidInfo, proc_name_3); }
1083 static ByteSize proc_name_4_offset() { return byte_offset_of(CpuidInfo, proc_name_4); }
1084 static ByteSize proc_name_5_offset() { return byte_offset_of(CpuidInfo, proc_name_5); }
1085 static ByteSize proc_name_6_offset() { return byte_offset_of(CpuidInfo, proc_name_6); }
1086 static ByteSize proc_name_7_offset() { return byte_offset_of(CpuidInfo, proc_name_7); }
1087 static ByteSize proc_name_8_offset() { return byte_offset_of(CpuidInfo, proc_name_8); }
1088 static ByteSize proc_name_9_offset() { return byte_offset_of(CpuidInfo, proc_name_9); }
1089 static ByteSize proc_name_10_offset() { return byte_offset_of(CpuidInfo, proc_name_10); }
1090 static ByteSize proc_name_11_offset() { return byte_offset_of(CpuidInfo, proc_name_11); }
1091
1092 static int64_t maximum_qualified_cpu_frequency(void);
1093
1094 static bool supports_tscinv_ext(void);
1095
1096 static void initialize_cpu_information(void);
1097 };
1098
1099 #endif // CPU_X86_VM_VERSION_X86_HPP
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360
361 protected:
362 static int _cpu;
363 static int _model;
364 static int _stepping;
365
366 static bool _has_intel_jcc_erratum;
367
368 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
369 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
370 static address _cpuinfo_segv_addr_apx; // address of instruction which causes APX specific SEGV
371 static address _cpuinfo_cont_addr_apx; // address of instruction after the one which causes APX specific SEGV
372
373 /*
374 * Update following files when declaring new flags:
375 * test/lib-test/jdk/test/whitebox/CPUInfoTest.java
376 * src/jdk.internal.vm.ci/share/classes/jdk/vm/ci/amd64/AMD64.java
377 */
378 enum Feature_Flag {
379 #define CPU_FEATURE_FLAGS(decl) \
380 decl(CX8, cx8, 0) /* next bits are from cpuid 1 (EDX) */ \
381 decl(CMOV, cmov, 1) \
382 decl(FXSR, fxsr, 2) \
383 decl(HT, ht, 3) \
384 \
385 decl(MMX, mmx, 4) \
386 decl(3DNOW_PREFETCH, 3dnowpref, 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
387 /* may not necessarily support other 3dnow instructions */ \
388 decl(SSE, sse, 6) \
389 decl(SSE2, sse2, 7) \
390 \
391 decl(SSE3, sse3, 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
392 decl(SSSE3, ssse3, 9 ) \
393 decl(SSE4A, sse4a, 10) \
394 decl(SSE4_1, sse4.1, 11) \
395 \
396 decl(SSE4_2, sse4.2, 12) \
397 decl(POPCNT, popcnt, 13) \
398 decl(LZCNT, lzcnt, 14) \
399 decl(TSC, tsc, 15) \
400 \
401 decl(TSCINV_BIT, tscinvbit, 16) \
402 decl(TSCINV, tscinv, 17) \
403 decl(AVX, avx, 18) \
404 decl(AVX2, avx2, 19) \
405 \
406 decl(AES, aes, 20) \
407 decl(ERMS, erms, 21) /* enhanced 'rep movsb/stosb' instructions */ \
408 decl(CLMUL, clmul, 22) /* carryless multiply for CRC */ \
409 decl(BMI1, bmi1, 23) \
410 \
411 decl(BMI2, bmi2, 24) \
412 decl(RTM, rtm, 25) /* Restricted Transactional Memory instructions */ \
413 decl(ADX, adx, 26) \
414 decl(AVX512F, avx512f, 27) /* AVX 512bit foundation instructions */ \
415 \
416 decl(AVX512DQ, avx512dq, 28) \
417 decl(AVX512PF, avx512pf, 29) \
418 decl(AVX512ER, avx512er, 30) \
419 decl(AVX512CD, avx512cd, 31) \
420 \
421 decl(AVX512BW, avx512bw, 32) /* Byte and word vector instructions */ \
422 decl(AVX512VL, avx512vl, 33) /* EVEX instructions with smaller vector length */ \
423 decl(SHA, sha, 34) /* SHA instructions */ \
424 decl(FMA, fma, 35) /* FMA instructions */ \
425 \
426 decl(VZEROUPPER, vzeroupper, 36) /* Vzeroupper instruction */ \
427 decl(AVX512_VPOPCNTDQ, avx512_vpopcntdq, 37) /* Vector popcount */ \
428 decl(AVX512_VPCLMULQDQ, avx512_vpclmulqdq, 38) /* Vector carryless multiplication */ \
429 decl(AVX512_VAES, avx512_vaes, 39) /* Vector AES instruction */ \
430 \
431 decl(AVX512_VNNI, avx512_vnni, 40) /* Vector Neural Network Instructions */ \
432 decl(FLUSH, clflush, 41) /* flush instruction */ \
433 decl(FLUSHOPT, clflushopt, 42) /* flusopth instruction */ \
434 decl(CLWB, clwb, 43) /* clwb instruction */ \
435 \
436 decl(AVX512_VBMI2, avx512_vbmi2, 44) /* VBMI2 shift left double instructions */ \
437 decl(AVX512_VBMI, avx512_vbmi, 45) /* Vector BMI instructions */ \
438 decl(HV, hv, 46) /* Hypervisor instructions */ \
439 decl(SERIALIZE, serialize, 47) /* CPU SERIALIZE */ \
440 decl(RDTSCP, rdtscp, 48) /* RDTSCP instruction */ \
441 decl(RDPID, rdpid, 49) /* RDPID instruction */ \
442 decl(FSRM, fsrm, 50) /* Fast Short REP MOV */ \
443 decl(GFNI, gfni, 51) /* Vector GFNI instructions */ \
444 decl(AVX512_BITALG, avx512_bitalg, 52) /* Vector sub-word popcount and bit gather instructions */\
445 decl(F16C, f16c, 53) /* Half-precision and single precision FP conversion instructions*/ \
446 decl(PKU, pku, 54) /* Protection keys for user-mode pages */ \
447 decl(OSPKE, ospke, 55) /* OS enables protection keys */ \
448 decl(CET_IBT, cet_ibt, 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
449 decl(CET_SS, cet_ss, 57) /* Control Flow Enforcement - Shadow Stack */ \
450 decl(AVX512_IFMA, avx512_ifma, 58) /* Integer Vector FMA instructions*/ \
451 decl(AVX_IFMA, avx_ifma, 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
452 decl(APX_F, apx_f, 60) /* Intel Advanced Performance Extensions*/ \
453 decl(SHA512, sha512, 61) /* SHA512 instructions*/ \
454 decl(AVX512_FP16, avx512_fp16, 62) /* AVX512 FP16 ISA support*/ \
455 decl(AVX10_1, avx10_1, 63) /* AVX10 512 bit vector ISA Version 1 support*/ \
456 decl(AVX10_2, avx10_2, 64) /* AVX10 512 bit vector ISA Version 2 support*/ \
457 decl(HYBRID, hybrid, 65) /* Hybrid architecture */
458
459 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (bit),
460 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
461 #undef DECLARE_CPU_FEATURE_FLAG
462 MAX_CPU_FEATURES
463 };
464
465 class VM_Features {
466 friend class VMStructs;
467 friend class JVMCIVMStructs;
468
469 private:
470 uint64_t _features_bitmap[(MAX_CPU_FEATURES / BitsPerLong) + 1];
471
472 STATIC_ASSERT(sizeof(_features_bitmap) * BitsPerByte >= MAX_CPU_FEATURES);
473
474 // Number of 8-byte elements in _bitmap.
475 constexpr static int features_bitmap_element_count() {
476 return sizeof(_features_bitmap) / sizeof(uint64_t);
477 }
478
479 constexpr static int features_bitmap_element_shift_count() {
480 return LogBitsPerLong;
481 }
482
483 constexpr static uint64_t features_bitmap_element_mask() {
484 return (1ULL << features_bitmap_element_shift_count()) - 1;
485 }
486
487 static int index(Feature_Flag feature) {
488 int idx = feature >> features_bitmap_element_shift_count();
489 assert(idx < features_bitmap_element_count(), "Features array index out of bounds");
490 return idx;
491 }
492
493 static uint64_t bit_mask(Feature_Flag feature) {
494 return (1ULL << (feature & features_bitmap_element_mask()));
495 }
496
497 static int _features_bitmap_size; // for JVMCI purposes
498
499 public:
500 VM_Features() {
501 for (int i = 0; i < features_bitmap_element_count(); i++) {
502 _features_bitmap[i] = 0;
503 }
504 }
505
506 void set_feature(Feature_Flag feature) {
507 int idx = index(feature);
508 _features_bitmap[idx] |= bit_mask(feature);
509 }
510
511 void clear_feature(VM_Version::Feature_Flag feature) {
512 int idx = index(feature);
513 _features_bitmap[idx] &= ~bit_mask(feature);
514 }
515
516 bool supports_feature(VM_Version::Feature_Flag feature) {
517 int idx = index(feature);
518 return (_features_bitmap[idx] & bit_mask(feature)) != 0;
519 }
520
521 bool supports_features(VM_Features* features_to_test) {
522 for (int i = 0; i < features_bitmap_element_count(); i++) {
523 if ((_features_bitmap[i] & features_to_test->_features_bitmap[i]) != features_to_test->_features_bitmap[i]) {
524 return false;
525 }
526 }
527 return true;
528 }
529 };
530
531 // CPU feature flags vector, can be affected by VM settings.
532 static VM_Features _features;
533
534 // Original CPU feature flags vector, not affected by VM settings.
535 static VM_Features _cpu_features;
536
537 static const char* _features_names[];
538
539 static void clear_cpu_features() {
540 _features = VM_Features();
541 _cpu_features = VM_Features();
542 }
543
544 enum Extended_Family {
545 // AMD
546 CPU_FAMILY_AMD_11H = 0x11,
547 CPU_FAMILY_AMD_17H = 0x17, /* Zen1 & Zen2 */
548 CPU_FAMILY_AMD_19H = 0x19, /* Zen3 & Zen4 */
1087 public:
1088 // Offsets for cpuid asm stub brand string
1089 static ByteSize proc_name_0_offset() { return byte_offset_of(CpuidInfo, proc_name_0); }
1090 static ByteSize proc_name_1_offset() { return byte_offset_of(CpuidInfo, proc_name_1); }
1091 static ByteSize proc_name_2_offset() { return byte_offset_of(CpuidInfo, proc_name_2); }
1092 static ByteSize proc_name_3_offset() { return byte_offset_of(CpuidInfo, proc_name_3); }
1093 static ByteSize proc_name_4_offset() { return byte_offset_of(CpuidInfo, proc_name_4); }
1094 static ByteSize proc_name_5_offset() { return byte_offset_of(CpuidInfo, proc_name_5); }
1095 static ByteSize proc_name_6_offset() { return byte_offset_of(CpuidInfo, proc_name_6); }
1096 static ByteSize proc_name_7_offset() { return byte_offset_of(CpuidInfo, proc_name_7); }
1097 static ByteSize proc_name_8_offset() { return byte_offset_of(CpuidInfo, proc_name_8); }
1098 static ByteSize proc_name_9_offset() { return byte_offset_of(CpuidInfo, proc_name_9); }
1099 static ByteSize proc_name_10_offset() { return byte_offset_of(CpuidInfo, proc_name_10); }
1100 static ByteSize proc_name_11_offset() { return byte_offset_of(CpuidInfo, proc_name_11); }
1101
1102 static int64_t maximum_qualified_cpu_frequency(void);
1103
1104 static bool supports_tscinv_ext(void);
1105
1106 static void initialize_cpu_information(void);
1107
1108 static void get_cpu_features_name(void* features_buffer, stringStream& ss);
1109 static void get_missing_features_name(void* features_buffer, stringStream& ss);
1110
1111 // Returns number of bytes required to store cpu features representation
1112 static int cpu_features_size();
1113
1114 // Stores cpu features representation in the provided buffer. This representation is arch dependent.
1115 // Size of the buffer must be same as returned by cpu_features_size()
1116 static void store_cpu_features(void* buf);
1117
1118 static bool supports_features(void* features_to_test);
1119 };
1120
1121 #endif // CPU_X86_VM_VERSION_X86_HPP
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