421 source_hpp %{
422
423 #include "peephole_x86_64.hpp"
424
425 bool castLL_is_imm32(const Node* n);
426
427 %}
428
429 source %{
430
431 bool castLL_is_imm32(const Node* n) {
432 assert(n->is_CastLL(), "must be a CastLL");
433 const TypeLong* t = n->bottom_type()->is_long();
434 return (t->_lo == min_jlong || Assembler::is_simm32(t->_lo)) && (t->_hi == max_jlong || Assembler::is_simm32(t->_hi));
435 }
436
437 %}
438
439 // Register masks
440 source_hpp %{
441
442 extern RegMask _ANY_REG_mask;
443 extern RegMask _PTR_REG_mask;
444 extern RegMask _PTR_REG_NO_RBP_mask;
445 extern RegMask _PTR_NO_RAX_REG_mask;
446 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
447 extern RegMask _LONG_REG_mask;
448 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
449 extern RegMask _LONG_NO_RCX_REG_mask;
450 extern RegMask _LONG_NO_RBP_R13_REG_mask;
451 extern RegMask _INT_REG_mask;
452 extern RegMask _INT_NO_RAX_RDX_REG_mask;
453 extern RegMask _INT_NO_RCX_REG_mask;
454 extern RegMask _INT_NO_RBP_R13_REG_mask;
455 extern RegMask _FLOAT_REG_mask;
456
457 extern RegMask _STACK_OR_PTR_REG_mask;
458 extern RegMask _STACK_OR_LONG_REG_mask;
459 extern RegMask _STACK_OR_INT_REG_mask;
460
461 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
834 st->print("\n\t");
835 st->print("cmpl [r15_thread + #disarmed_guard_value_offset], #disarmed_guard_value\t");
836 st->print("\n\t");
837 st->print("je fast_entry\t");
838 st->print("\n\t");
839 st->print("call #nmethod_entry_barrier_stub\t");
840 st->print("\n\tfast_entry:");
841 }
842 st->cr();
843 }
844 #endif
845
846 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
847 Compile* C = ra_->C;
848
849 int framesize = C->output()->frame_size_in_bytes();
850 int bangsize = C->output()->bang_size_in_bytes();
851
852 if (C->clinit_barrier_on_entry()) {
853 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
854 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
855
856 Label L_skip_barrier;
857 Register klass = rscratch1;
858
859 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
860 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
861
862 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
863
864 __ bind(L_skip_barrier);
865 }
866
867 __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != nullptr);
868
869 C->output()->set_frame_complete(__ offset());
870
871 if (C->has_mach_constant_base_node()) {
872 // NOTE: We set the table base offset here because users might be
873 // emitted before MachConstantBaseNode.
874 ConstantTable& constant_table = C->output()->constant_table();
2468 // Constant for byte-wide masking
2469 operand immL_255()
2470 %{
2471 predicate(n->get_long() == 255);
2472 match(ConL);
2473
2474 format %{ %}
2475 interface(CONST_INTER);
2476 %}
2477
2478 // Constant for short-wide masking
2479 operand immL_65535()
2480 %{
2481 predicate(n->get_long() == 65535);
2482 match(ConL);
2483
2484 format %{ %}
2485 interface(CONST_INTER);
2486 %}
2487
2488 operand kReg()
2489 %{
2490 constraint(ALLOC_IN_RC(vectmask_reg));
2491 match(RegVectMask);
2492 format %{%}
2493 interface(REG_INTER);
2494 %}
2495
2496 // Register Operands
2497 // Integer Register
2498 operand rRegI()
2499 %{
2500 constraint(ALLOC_IN_RC(int_reg));
2501 match(RegI);
2502
2503 match(rax_RegI);
2504 match(rbx_RegI);
2505 match(rcx_RegI);
2506 match(rdx_RegI);
2507 match(rdi_RegI);
4425 format %{ "movlpd $dst, $mem\t# double" %}
4426 ins_encode %{
4427 __ movdbl($dst$$XMMRegister, $mem$$Address);
4428 %}
4429 ins_pipe(pipe_slow); // XXX
4430 %}
4431
4432 instruct loadD(regD dst, memory mem)
4433 %{
4434 predicate(UseXmmLoadAndClearUpper);
4435 match(Set dst (LoadD mem));
4436
4437 ins_cost(145); // XXX
4438 format %{ "movsd $dst, $mem\t# double" %}
4439 ins_encode %{
4440 __ movdbl($dst$$XMMRegister, $mem$$Address);
4441 %}
4442 ins_pipe(pipe_slow); // XXX
4443 %}
4444
4445 // max = java.lang.Math.max(float a, float b)
4446 instruct maxF_avx10_reg(regF dst, regF a, regF b) %{
4447 predicate(VM_Version::supports_avx10_2());
4448 match(Set dst (MaxF a b));
4449 format %{ "maxF $dst, $a, $b" %}
4450 ins_encode %{
4451 __ eminmaxss($dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, AVX10_MINMAX_MAX_COMPARE_SIGN);
4452 %}
4453 ins_pipe( pipe_slow );
4454 %}
4455
4456 // max = java.lang.Math.max(float a, float b)
4457 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4458 predicate(!VM_Version::supports_avx10_2() && UseAVX > 0 && !VLoopReductions::is_reduction(n));
4459 match(Set dst (MaxF a b));
4460 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4461 format %{ "maxF $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4462 ins_encode %{
4463 __ vminmax_fp(Op_MaxV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4464 %}
|
421 source_hpp %{
422
423 #include "peephole_x86_64.hpp"
424
425 bool castLL_is_imm32(const Node* n);
426
427 %}
428
429 source %{
430
431 bool castLL_is_imm32(const Node* n) {
432 assert(n->is_CastLL(), "must be a CastLL");
433 const TypeLong* t = n->bottom_type()->is_long();
434 return (t->_lo == min_jlong || Assembler::is_simm32(t->_lo)) && (t->_hi == max_jlong || Assembler::is_simm32(t->_hi));
435 }
436
437 %}
438
439 // Register masks
440 source_hpp %{
441 extern RegMask _ANY_REG_mask;
442 extern RegMask _PTR_REG_mask;
443 extern RegMask _PTR_REG_NO_RBP_mask;
444 extern RegMask _PTR_NO_RAX_REG_mask;
445 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
446 extern RegMask _LONG_REG_mask;
447 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
448 extern RegMask _LONG_NO_RCX_REG_mask;
449 extern RegMask _LONG_NO_RBP_R13_REG_mask;
450 extern RegMask _INT_REG_mask;
451 extern RegMask _INT_NO_RAX_RDX_REG_mask;
452 extern RegMask _INT_NO_RCX_REG_mask;
453 extern RegMask _INT_NO_RBP_R13_REG_mask;
454 extern RegMask _FLOAT_REG_mask;
455
456 extern RegMask _STACK_OR_PTR_REG_mask;
457 extern RegMask _STACK_OR_LONG_REG_mask;
458 extern RegMask _STACK_OR_INT_REG_mask;
459
460 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
833 st->print("\n\t");
834 st->print("cmpl [r15_thread + #disarmed_guard_value_offset], #disarmed_guard_value\t");
835 st->print("\n\t");
836 st->print("je fast_entry\t");
837 st->print("\n\t");
838 st->print("call #nmethod_entry_barrier_stub\t");
839 st->print("\n\tfast_entry:");
840 }
841 st->cr();
842 }
843 #endif
844
845 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
846 Compile* C = ra_->C;
847
848 int framesize = C->output()->frame_size_in_bytes();
849 int bangsize = C->output()->bang_size_in_bytes();
850
851 if (C->clinit_barrier_on_entry()) {
852 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
853 assert(!C->method()->holder()->is_not_initialized() || C->do_clinit_barriers(), "initialization should have been started");
854
855 Label L_skip_barrier;
856 Register klass = rscratch1;
857
858 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
859 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
860
861 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
862
863 __ bind(L_skip_barrier);
864 }
865
866 __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != nullptr);
867
868 C->output()->set_frame_complete(__ offset());
869
870 if (C->has_mach_constant_base_node()) {
871 // NOTE: We set the table base offset here because users might be
872 // emitted before MachConstantBaseNode.
873 ConstantTable& constant_table = C->output()->constant_table();
2467 // Constant for byte-wide masking
2468 operand immL_255()
2469 %{
2470 predicate(n->get_long() == 255);
2471 match(ConL);
2472
2473 format %{ %}
2474 interface(CONST_INTER);
2475 %}
2476
2477 // Constant for short-wide masking
2478 operand immL_65535()
2479 %{
2480 predicate(n->get_long() == 65535);
2481 match(ConL);
2482
2483 format %{ %}
2484 interface(CONST_INTER);
2485 %}
2486
2487 // AOT Runtime Constants Address
2488 operand immAOTRuntimeConstantsAddress()
2489 %{
2490 // Check if the address is in the range of AOT Runtime Constants
2491 predicate(AOTRuntimeConstants::contains((address)(n->get_ptr())));
2492 match(ConP);
2493
2494 op_cost(0);
2495 format %{ %}
2496 interface(CONST_INTER);
2497 %}
2498
2499 operand kReg()
2500 %{
2501 constraint(ALLOC_IN_RC(vectmask_reg));
2502 match(RegVectMask);
2503 format %{%}
2504 interface(REG_INTER);
2505 %}
2506
2507 // Register Operands
2508 // Integer Register
2509 operand rRegI()
2510 %{
2511 constraint(ALLOC_IN_RC(int_reg));
2512 match(RegI);
2513
2514 match(rax_RegI);
2515 match(rbx_RegI);
2516 match(rcx_RegI);
2517 match(rdx_RegI);
2518 match(rdi_RegI);
4436 format %{ "movlpd $dst, $mem\t# double" %}
4437 ins_encode %{
4438 __ movdbl($dst$$XMMRegister, $mem$$Address);
4439 %}
4440 ins_pipe(pipe_slow); // XXX
4441 %}
4442
4443 instruct loadD(regD dst, memory mem)
4444 %{
4445 predicate(UseXmmLoadAndClearUpper);
4446 match(Set dst (LoadD mem));
4447
4448 ins_cost(145); // XXX
4449 format %{ "movsd $dst, $mem\t# double" %}
4450 ins_encode %{
4451 __ movdbl($dst$$XMMRegister, $mem$$Address);
4452 %}
4453 ins_pipe(pipe_slow); // XXX
4454 %}
4455
4456 instruct loadAOTRCAddress(rRegP dst, immAOTRuntimeConstantsAddress con)
4457 %{
4458 match(Set dst con);
4459
4460 format %{ "leaq $dst, $con\t# AOT Runtime Constants Address" %}
4461
4462 ins_encode %{
4463 __ load_aotrc_address($dst$$Register, (address)$con$$constant);
4464 %}
4465
4466 ins_pipe(ialu_reg_fat);
4467 %}
4468
4469 // max = java.lang.Math.max(float a, float b)
4470 instruct maxF_avx10_reg(regF dst, regF a, regF b) %{
4471 predicate(VM_Version::supports_avx10_2());
4472 match(Set dst (MaxF a b));
4473 format %{ "maxF $dst, $a, $b" %}
4474 ins_encode %{
4475 __ eminmaxss($dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, AVX10_MINMAX_MAX_COMPARE_SIGN);
4476 %}
4477 ins_pipe( pipe_slow );
4478 %}
4479
4480 // max = java.lang.Math.max(float a, float b)
4481 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4482 predicate(!VM_Version::supports_avx10_2() && UseAVX > 0 && !VLoopReductions::is_reduction(n));
4483 match(Set dst (MaxF a b));
4484 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4485 format %{ "maxF $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4486 ins_encode %{
4487 __ vminmax_fp(Op_MaxV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4488 %}
|