421 source_hpp %{
422
423 #include "peephole_x86_64.hpp"
424
425 bool castLL_is_imm32(const Node* n);
426
427 %}
428
429 source %{
430
431 bool castLL_is_imm32(const Node* n) {
432 assert(n->is_CastLL(), "must be a CastLL");
433 const TypeLong* t = n->bottom_type()->is_long();
434 return (t->_lo == min_jlong || Assembler::is_simm32(t->_lo)) && (t->_hi == max_jlong || Assembler::is_simm32(t->_hi));
435 }
436
437 %}
438
439 // Register masks
440 source_hpp %{
441
442 extern RegMask _ANY_REG_mask;
443 extern RegMask _PTR_REG_mask;
444 extern RegMask _PTR_REG_NO_RBP_mask;
445 extern RegMask _PTR_NO_RAX_REG_mask;
446 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
447 extern RegMask _LONG_REG_mask;
448 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
449 extern RegMask _LONG_NO_RCX_REG_mask;
450 extern RegMask _LONG_NO_RBP_R13_REG_mask;
451 extern RegMask _INT_REG_mask;
452 extern RegMask _INT_NO_RAX_RDX_REG_mask;
453 extern RegMask _INT_NO_RCX_REG_mask;
454 extern RegMask _INT_NO_RBP_R13_REG_mask;
455 extern RegMask _FLOAT_REG_mask;
456
457 extern RegMask _STACK_OR_PTR_REG_mask;
458 extern RegMask _STACK_OR_LONG_REG_mask;
459 extern RegMask _STACK_OR_INT_REG_mask;
460
461 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
834 st->print("\n\t");
835 st->print("cmpl [r15_thread + #disarmed_guard_value_offset], #disarmed_guard_value\t");
836 st->print("\n\t");
837 st->print("je fast_entry\t");
838 st->print("\n\t");
839 st->print("call #nmethod_entry_barrier_stub\t");
840 st->print("\n\tfast_entry:");
841 }
842 st->cr();
843 }
844 #endif
845
846 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
847 Compile* C = ra_->C;
848
849 int framesize = C->output()->frame_size_in_bytes();
850 int bangsize = C->output()->bang_size_in_bytes();
851
852 if (C->clinit_barrier_on_entry()) {
853 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
854 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
855
856 Label L_skip_barrier;
857 Register klass = rscratch1;
858
859 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
860 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
861
862 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
863
864 __ bind(L_skip_barrier);
865 }
866
867 __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != nullptr);
868
869 C->output()->set_frame_complete(__ offset());
870
871 if (C->has_mach_constant_base_node()) {
872 // NOTE: We set the table base offset here because users might be
873 // emitted before MachConstantBaseNode.
874 ConstantTable& constant_table = C->output()->constant_table();
2473 // Constant for byte-wide masking
2474 operand immL_255()
2475 %{
2476 predicate(n->get_long() == 255);
2477 match(ConL);
2478
2479 format %{ %}
2480 interface(CONST_INTER);
2481 %}
2482
2483 // Constant for short-wide masking
2484 operand immL_65535()
2485 %{
2486 predicate(n->get_long() == 65535);
2487 match(ConL);
2488
2489 format %{ %}
2490 interface(CONST_INTER);
2491 %}
2492
2493 operand kReg()
2494 %{
2495 constraint(ALLOC_IN_RC(vectmask_reg));
2496 match(RegVectMask);
2497 format %{%}
2498 interface(REG_INTER);
2499 %}
2500
2501 // Register Operands
2502 // Integer Register
2503 operand rRegI()
2504 %{
2505 constraint(ALLOC_IN_RC(int_reg));
2506 match(RegI);
2507
2508 match(rax_RegI);
2509 match(rbx_RegI);
2510 match(rcx_RegI);
2511 match(rdx_RegI);
2512 match(rdi_RegI);
4433 format %{ "movlpd $dst, $mem\t# double" %}
4434 ins_encode %{
4435 __ movdbl($dst$$XMMRegister, $mem$$Address);
4436 %}
4437 ins_pipe(pipe_slow); // XXX
4438 %}
4439
4440 instruct loadD(regD dst, memory mem)
4441 %{
4442 predicate(UseXmmLoadAndClearUpper);
4443 match(Set dst (LoadD mem));
4444
4445 ins_cost(145); // XXX
4446 format %{ "movsd $dst, $mem\t# double" %}
4447 ins_encode %{
4448 __ movdbl($dst$$XMMRegister, $mem$$Address);
4449 %}
4450 ins_pipe(pipe_slow); // XXX
4451 %}
4452
4453 // max = java.lang.Math.max(float a, float b)
4454 instruct maxF_avx10_reg(regF dst, regF a, regF b) %{
4455 predicate(VM_Version::supports_avx10_2());
4456 match(Set dst (MaxF a b));
4457 format %{ "maxF $dst, $a, $b" %}
4458 ins_encode %{
4459 __ eminmaxss($dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, AVX10_MINMAX_MAX_COMPARE_SIGN);
4460 %}
4461 ins_pipe( pipe_slow );
4462 %}
4463
4464 // max = java.lang.Math.max(float a, float b)
4465 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4466 predicate(!VM_Version::supports_avx10_2() && UseAVX > 0 && !VLoopReductions::is_reduction(n));
4467 match(Set dst (MaxF a b));
4468 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4469 format %{ "maxF $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4470 ins_encode %{
4471 __ vminmax_fp(Op_MaxV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4472 %}
|
421 source_hpp %{
422
423 #include "peephole_x86_64.hpp"
424
425 bool castLL_is_imm32(const Node* n);
426
427 %}
428
429 source %{
430
431 bool castLL_is_imm32(const Node* n) {
432 assert(n->is_CastLL(), "must be a CastLL");
433 const TypeLong* t = n->bottom_type()->is_long();
434 return (t->_lo == min_jlong || Assembler::is_simm32(t->_lo)) && (t->_hi == max_jlong || Assembler::is_simm32(t->_hi));
435 }
436
437 %}
438
439 // Register masks
440 source_hpp %{
441 extern RegMask _ANY_REG_mask;
442 extern RegMask _PTR_REG_mask;
443 extern RegMask _PTR_REG_NO_RBP_mask;
444 extern RegMask _PTR_NO_RAX_REG_mask;
445 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
446 extern RegMask _LONG_REG_mask;
447 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
448 extern RegMask _LONG_NO_RCX_REG_mask;
449 extern RegMask _LONG_NO_RBP_R13_REG_mask;
450 extern RegMask _INT_REG_mask;
451 extern RegMask _INT_NO_RAX_RDX_REG_mask;
452 extern RegMask _INT_NO_RCX_REG_mask;
453 extern RegMask _INT_NO_RBP_R13_REG_mask;
454 extern RegMask _FLOAT_REG_mask;
455
456 extern RegMask _STACK_OR_PTR_REG_mask;
457 extern RegMask _STACK_OR_LONG_REG_mask;
458 extern RegMask _STACK_OR_INT_REG_mask;
459
460 inline const RegMask& STACK_OR_PTR_REG_mask() { return _STACK_OR_PTR_REG_mask; }
833 st->print("\n\t");
834 st->print("cmpl [r15_thread + #disarmed_guard_value_offset], #disarmed_guard_value\t");
835 st->print("\n\t");
836 st->print("je fast_entry\t");
837 st->print("\n\t");
838 st->print("call #nmethod_entry_barrier_stub\t");
839 st->print("\n\tfast_entry:");
840 }
841 st->cr();
842 }
843 #endif
844
845 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
846 Compile* C = ra_->C;
847
848 int framesize = C->output()->frame_size_in_bytes();
849 int bangsize = C->output()->bang_size_in_bytes();
850
851 if (C->clinit_barrier_on_entry()) {
852 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
853 assert(!C->method()->holder()->is_not_initialized() || C->do_clinit_barriers(), "initialization should have been started");
854
855 Label L_skip_barrier;
856 Register klass = rscratch1;
857
858 __ mov_metadata(klass, C->method()->holder()->constant_encoding());
859 __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
860
861 __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
862
863 __ bind(L_skip_barrier);
864 }
865
866 __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != nullptr);
867
868 C->output()->set_frame_complete(__ offset());
869
870 if (C->has_mach_constant_base_node()) {
871 // NOTE: We set the table base offset here because users might be
872 // emitted before MachConstantBaseNode.
873 ConstantTable& constant_table = C->output()->constant_table();
2472 // Constant for byte-wide masking
2473 operand immL_255()
2474 %{
2475 predicate(n->get_long() == 255);
2476 match(ConL);
2477
2478 format %{ %}
2479 interface(CONST_INTER);
2480 %}
2481
2482 // Constant for short-wide masking
2483 operand immL_65535()
2484 %{
2485 predicate(n->get_long() == 65535);
2486 match(ConL);
2487
2488 format %{ %}
2489 interface(CONST_INTER);
2490 %}
2491
2492 // AOT Runtime Constants Address
2493 operand immAOTRuntimeConstantsAddress()
2494 %{
2495 // Check if the address is in the range of AOT Runtime Constants
2496 predicate(AOTRuntimeConstants::contains((address)(n->get_ptr())));
2497 match(ConP);
2498
2499 op_cost(0);
2500 format %{ %}
2501 interface(CONST_INTER);
2502 %}
2503
2504 operand kReg()
2505 %{
2506 constraint(ALLOC_IN_RC(vectmask_reg));
2507 match(RegVectMask);
2508 format %{%}
2509 interface(REG_INTER);
2510 %}
2511
2512 // Register Operands
2513 // Integer Register
2514 operand rRegI()
2515 %{
2516 constraint(ALLOC_IN_RC(int_reg));
2517 match(RegI);
2518
2519 match(rax_RegI);
2520 match(rbx_RegI);
2521 match(rcx_RegI);
2522 match(rdx_RegI);
2523 match(rdi_RegI);
4444 format %{ "movlpd $dst, $mem\t# double" %}
4445 ins_encode %{
4446 __ movdbl($dst$$XMMRegister, $mem$$Address);
4447 %}
4448 ins_pipe(pipe_slow); // XXX
4449 %}
4450
4451 instruct loadD(regD dst, memory mem)
4452 %{
4453 predicate(UseXmmLoadAndClearUpper);
4454 match(Set dst (LoadD mem));
4455
4456 ins_cost(145); // XXX
4457 format %{ "movsd $dst, $mem\t# double" %}
4458 ins_encode %{
4459 __ movdbl($dst$$XMMRegister, $mem$$Address);
4460 %}
4461 ins_pipe(pipe_slow); // XXX
4462 %}
4463
4464 instruct loadAOTRCAddress(rRegP dst, immAOTRuntimeConstantsAddress con)
4465 %{
4466 match(Set dst con);
4467
4468 format %{ "leaq $dst, $con\t# AOT Runtime Constants Address" %}
4469
4470 ins_encode %{
4471 __ load_aotrc_address($dst$$Register, (address)$con$$constant);
4472 %}
4473
4474 ins_pipe(ialu_reg_fat);
4475 %}
4476
4477 // max = java.lang.Math.max(float a, float b)
4478 instruct maxF_avx10_reg(regF dst, regF a, regF b) %{
4479 predicate(VM_Version::supports_avx10_2());
4480 match(Set dst (MaxF a b));
4481 format %{ "maxF $dst, $a, $b" %}
4482 ins_encode %{
4483 __ eminmaxss($dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, AVX10_MINMAX_MAX_COMPARE_SIGN);
4484 %}
4485 ins_pipe( pipe_slow );
4486 %}
4487
4488 // max = java.lang.Math.max(float a, float b)
4489 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
4490 predicate(!VM_Version::supports_avx10_2() && UseAVX > 0 && !VLoopReductions::is_reduction(n));
4491 match(Set dst (MaxF a b));
4492 effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
4493 format %{ "maxF $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
4494 ins_encode %{
4495 __ vminmax_fp(Op_MaxV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
4496 %}
|