1 /*
2 * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
993 return 512; // Pentium 4
994 }
995 } else {
996 return 128; // Pentium 3 (and all other old CPUs)
997 }
998 }
999 }
1000
1001 // SSE2 and later processors implement a 'pause' instruction
1002 // that can be used for efficient implementation of
1003 // the intrinsic for java.lang.Thread.onSpinWait()
1004 static bool supports_on_spin_wait() { return supports_sse2(); }
1005
1006 // x86_64 supports fast class initialization checks for static methods.
1007 static bool supports_fast_class_init_checks() {
1008 return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
1009 }
1010
1011 constexpr static bool supports_stack_watermark_barrier() {
1012 return true;
1013 }
1014
1015 // there are several insns to force cache line sync to memory which
1016 // we can use to ensure mapped non-volatile memory is up to date with
1017 // pending in-cache changes.
1018 //
1019 // 64 bit cpus always support clflush which writes back and evicts
1020 // on 32 bit cpus support is recorded via a feature flag
1021 //
1022 // clflushopt is optional and acts like clflush except it does
1023 // not synchronize with other memory ops. it needs a preceding
1024 // and trailing StoreStore fence
1025 //
1026 // clwb is an optional intel-specific instruction which
1027 // writes back without evicting the line. it also does not
1028 // synchronize with other memory ops. so, it needs preceding
1029 // and trailing StoreStore fences.
1030
1031 #ifdef _LP64
1032 static bool supports_clflush() {
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1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
993 return 512; // Pentium 4
994 }
995 } else {
996 return 128; // Pentium 3 (and all other old CPUs)
997 }
998 }
999 }
1000
1001 // SSE2 and later processors implement a 'pause' instruction
1002 // that can be used for efficient implementation of
1003 // the intrinsic for java.lang.Thread.onSpinWait()
1004 static bool supports_on_spin_wait() { return supports_sse2(); }
1005
1006 // x86_64 supports fast class initialization checks for static methods.
1007 static bool supports_fast_class_init_checks() {
1008 return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
1009 }
1010
1011 constexpr static bool supports_stack_watermark_barrier() {
1012 return true;
1013 }
1014
1015 constexpr static bool supports_recursive_lightweight_locking() {
1016 return true;
1017 }
1018
1019 // there are several insns to force cache line sync to memory which
1020 // we can use to ensure mapped non-volatile memory is up to date with
1021 // pending in-cache changes.
1022 //
1023 // 64 bit cpus always support clflush which writes back and evicts
1024 // on 32 bit cpus support is recorded via a feature flag
1025 //
1026 // clflushopt is optional and acts like clflush except it does
1027 // not synchronize with other memory ops. it needs a preceding
1028 // and trailing StoreStore fence
1029 //
1030 // clwb is an optional intel-specific instruction which
1031 // writes back without evicting the line. it also does not
1032 // synchronize with other memory ops. so, it needs preceding
1033 // and trailing StoreStore fences.
1034
1035 #ifdef _LP64
1036 static bool supports_clflush() {
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