220 // ADLC inherit from this class.
221 class MachNode : public Node {
222 public:
223 MachNode() : Node((uint)0), _barrier(0), _num_opnds(0), _opnds(nullptr) {
224 init_class_id(Class_Mach);
225 }
226 // Required boilerplate
227 virtual uint size_of() const { return sizeof(MachNode); }
228 virtual int Opcode() const; // Always equal to MachNode
229 virtual uint rule() const = 0; // Machine-specific opcode
230 // Number of inputs which come before the first operand.
231 // Generally at least 1, to skip the Control input
232 virtual uint oper_input_base() const { return 1; }
233 // Position of constant base node in node's inputs. -1 if
234 // no constant base node input.
235 virtual uint mach_constant_base_node_input() const { return (uint)-1; }
236
237 uint8_t barrier_data() const { return _barrier; }
238 void set_barrier_data(uint8_t data) { _barrier = data; }
239
240 // Copy index, inputs, and operands to a new version of the instruction.
241 // Called from cisc_version() and short_branch_version().
242 void fill_new_machnode(MachNode *n) const;
243
244 // Return an equivalent instruction using memory for cisc_operand position
245 virtual MachNode *cisc_version(int offset);
246 // Modify this instruction's register mask to use stack version for cisc_operand
247 virtual void use_cisc_RegMask();
248
249 // Support for short branches
250 bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; }
251
252 // Avoid back to back some instructions on some CPUs.
253 enum AvoidBackToBackFlag { AVOID_NONE = 0,
254 AVOID_BEFORE = Flag_avoid_back_to_back_before,
255 AVOID_AFTER = Flag_avoid_back_to_back_after,
256 AVOID_BEFORE_AND_AFTER = AVOID_BEFORE | AVOID_AFTER };
257
258 bool avoid_back_to_back(AvoidBackToBackFlag flag_value) const {
259 return (flags() & flag_value) == flag_value;
268 int operand_index(Node* m) const;
269 int operand_num_edges(uint operand) const;
270
271 // Register class input is expected in
272 virtual const RegMask &in_RegMask(uint) const;
273
274 // cisc-spillable instructions redefine for use by in_RegMask
275 virtual const RegMask *cisc_RegMask() const { return nullptr; }
276
277 // If this instruction is a 2-address instruction, then return the
278 // index of the input which must match the output. Not necessary
279 // for instructions which bind the input and output register to the
280 // same singleton register (e.g., Intel IDIV which binds AX to be
281 // both an input and an output). It is necessary when the input and
282 // output have choices - but they must use the same choice.
283 virtual uint two_adr( ) const { return 0; }
284
285 // The GC might require some barrier metadata for machine code emission.
286 uint8_t _barrier;
287
288 // Array of complex operand pointers. Each corresponds to zero or
289 // more leafs. Must be set by MachNode constructor to point to an
290 // internal array of MachOpers. The MachOper array is sized by
291 // specific MachNodes described in the ADL.
292 uint16_t _num_opnds;
293 MachOper **_opnds;
294 uint16_t num_opnds() const { return _num_opnds; }
295
296 // Emit bytes using C2_MacroAssembler
297 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
298 // Expand node after register allocation.
299 // Node is replaced by several nodes in the postalloc expand phase.
300 // Corresponding methods are generated for nodes if they specify
301 // postalloc_expand. See block.cpp for more documentation.
302 virtual bool requires_postalloc_expand() const { return false; }
303 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
304 // Size of instruction in bytes
305 virtual uint size(PhaseRegAlloc *ra_) const;
306 // Helper function that computes size by emitting code
307 virtual uint emit_size(PhaseRegAlloc *ra_) const;
364 virtual const MachOper* memory_operand() const { return nullptr; }
365
366 // Call "get_base_and_disp" to decide which category of memory is used here.
367 virtual const class TypePtr *adr_type() const;
368
369 // Apply peephole rule(s) to this instruction
370 virtual int peephole(Block *block, int block_index, PhaseCFG* cfg_, PhaseRegAlloc *ra_);
371
372 // Top-level ideal Opcode matched
373 virtual int ideal_Opcode() const { return Op_Node; }
374
375 // Adds the label for the case
376 virtual void add_case_label( int switch_val, Label* blockLabel);
377
378 // Set the absolute address for methods
379 virtual void method_set( intptr_t addr );
380
381 // Should we clone rather than spill this instruction?
382 bool rematerialize() const;
383
384 // Get the pipeline info
385 static const Pipeline *pipeline_class();
386 virtual const Pipeline *pipeline() const;
387
388 // Returns true if this node is a check that can be implemented with a trap.
389 virtual bool is_TrapBasedCheckNode() const { return false; }
390
391 // Whether this node is expanded during code emission into a sequence of
392 // instructions and the first instruction can perform an implicit null check.
393 virtual bool is_late_expanded_null_check_candidate() const {
394 return false;
395 }
396
397 void set_removed() { add_flag(Flag_is_removed_by_peephole); }
398 bool get_removed() { return (flags() & Flag_is_removed_by_peephole) != 0; }
399
400 #ifndef PRODUCT
401 virtual const char *Name() const = 0; // Machine-specific name
402 virtual void dump_spec(outputStream *st) const; // Print per-node info
403 void dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual
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220 // ADLC inherit from this class.
221 class MachNode : public Node {
222 public:
223 MachNode() : Node((uint)0), _barrier(0), _num_opnds(0), _opnds(nullptr) {
224 init_class_id(Class_Mach);
225 }
226 // Required boilerplate
227 virtual uint size_of() const { return sizeof(MachNode); }
228 virtual int Opcode() const; // Always equal to MachNode
229 virtual uint rule() const = 0; // Machine-specific opcode
230 // Number of inputs which come before the first operand.
231 // Generally at least 1, to skip the Control input
232 virtual uint oper_input_base() const { return 1; }
233 // Position of constant base node in node's inputs. -1 if
234 // no constant base node input.
235 virtual uint mach_constant_base_node_input() const { return (uint)-1; }
236
237 uint8_t barrier_data() const { return _barrier; }
238 void set_barrier_data(uint8_t data) { _barrier = data; }
239
240 void set_memory_order(MemNode::MemOrd mo) { _mo = mo; }
241 MemNode::MemOrd memory_order() const { return _mo; }
242
243 void set_trailing_membar(Node* n) {
244 if (n->is_Store()) {
245 _has_trailing_membar = n->as_Store()->trailing_membar() != nullptr;
246 } else if (n->is_LoadStore()) {
247 _has_trailing_membar = n->as_LoadStore()->trailing_membar() != nullptr;
248 } else {
249 _has_trailing_membar = false;
250 }
251 }
252
253 bool has_trailing_membar() const { return _has_trailing_membar; }
254
255 // Copy index, inputs, and operands to a new version of the instruction.
256 // Called from cisc_version() and short_branch_version().
257 void fill_new_machnode(MachNode *n) const;
258
259 // Return an equivalent instruction using memory for cisc_operand position
260 virtual MachNode *cisc_version(int offset);
261 // Modify this instruction's register mask to use stack version for cisc_operand
262 virtual void use_cisc_RegMask();
263
264 // Support for short branches
265 bool may_be_short_branch() const { return (flags() & Flag_may_be_short_branch) != 0; }
266
267 // Avoid back to back some instructions on some CPUs.
268 enum AvoidBackToBackFlag { AVOID_NONE = 0,
269 AVOID_BEFORE = Flag_avoid_back_to_back_before,
270 AVOID_AFTER = Flag_avoid_back_to_back_after,
271 AVOID_BEFORE_AND_AFTER = AVOID_BEFORE | AVOID_AFTER };
272
273 bool avoid_back_to_back(AvoidBackToBackFlag flag_value) const {
274 return (flags() & flag_value) == flag_value;
283 int operand_index(Node* m) const;
284 int operand_num_edges(uint operand) const;
285
286 // Register class input is expected in
287 virtual const RegMask &in_RegMask(uint) const;
288
289 // cisc-spillable instructions redefine for use by in_RegMask
290 virtual const RegMask *cisc_RegMask() const { return nullptr; }
291
292 // If this instruction is a 2-address instruction, then return the
293 // index of the input which must match the output. Not necessary
294 // for instructions which bind the input and output register to the
295 // same singleton register (e.g., Intel IDIV which binds AX to be
296 // both an input and an output). It is necessary when the input and
297 // output have choices - but they must use the same choice.
298 virtual uint two_adr( ) const { return 0; }
299
300 // The GC might require some barrier metadata for machine code emission.
301 uint8_t _barrier;
302
303 MemNode::MemOrd _mo;
304
305 bool _has_trailing_membar;
306
307
308 // Array of complex operand pointers. Each corresponds to zero or
309 // more leafs. Must be set by MachNode constructor to point to an
310 // internal array of MachOpers. The MachOper array is sized by
311 // specific MachNodes described in the ADL.
312 uint16_t _num_opnds;
313 MachOper **_opnds;
314 uint16_t num_opnds() const { return _num_opnds; }
315
316 // Emit bytes using C2_MacroAssembler
317 virtual void emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const;
318 // Expand node after register allocation.
319 // Node is replaced by several nodes in the postalloc expand phase.
320 // Corresponding methods are generated for nodes if they specify
321 // postalloc_expand. See block.cpp for more documentation.
322 virtual bool requires_postalloc_expand() const { return false; }
323 virtual void postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_);
324 // Size of instruction in bytes
325 virtual uint size(PhaseRegAlloc *ra_) const;
326 // Helper function that computes size by emitting code
327 virtual uint emit_size(PhaseRegAlloc *ra_) const;
384 virtual const MachOper* memory_operand() const { return nullptr; }
385
386 // Call "get_base_and_disp" to decide which category of memory is used here.
387 virtual const class TypePtr *adr_type() const;
388
389 // Apply peephole rule(s) to this instruction
390 virtual int peephole(Block *block, int block_index, PhaseCFG* cfg_, PhaseRegAlloc *ra_);
391
392 // Top-level ideal Opcode matched
393 virtual int ideal_Opcode() const { return Op_Node; }
394
395 // Adds the label for the case
396 virtual void add_case_label( int switch_val, Label* blockLabel);
397
398 // Set the absolute address for methods
399 virtual void method_set( intptr_t addr );
400
401 // Should we clone rather than spill this instruction?
402 bool rematerialize() const;
403
404 bool is_CAS(bool maybe_volatile) const;
405
406 // Get the pipeline info
407 static const Pipeline *pipeline_class();
408 virtual const Pipeline *pipeline() const;
409
410 // Returns true if this node is a check that can be implemented with a trap.
411 virtual bool is_TrapBasedCheckNode() const { return false; }
412
413 // Whether this node is expanded during code emission into a sequence of
414 // instructions and the first instruction can perform an implicit null check.
415 virtual bool is_late_expanded_null_check_candidate() const {
416 return false;
417 }
418
419 void set_removed() { add_flag(Flag_is_removed_by_peephole); }
420 bool get_removed() { return (flags() & Flag_is_removed_by_peephole) != 0; }
421
422 #ifndef PRODUCT
423 virtual const char *Name() const = 0; // Machine-specific name
424 virtual void dump_spec(outputStream *st) const; // Print per-node info
425 void dump_format(PhaseRegAlloc *ra, outputStream *st) const; // access to virtual
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