16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInstance.hpp"
37 #include "code/compiledIC.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/gc_globals.hpp"
40 #include "nativeInst_aarch64.hpp"
41 #include "oops/objArrayKlass.hpp"
42 #include "runtime/frame.inline.hpp"
43 #include "runtime/sharedRuntime.hpp"
44 #include "runtime/stubRoutines.hpp"
45 #include "utilities/powerOfTwo.hpp"
46 #include "vmreg_aarch64.inline.hpp"
47
48
49 #ifndef PRODUCT
50 #define COMMENT(x) do { __ block_comment(x); } while (0)
51 #else
52 #define COMMENT(x)
53 #endif
54
55 NEEDS_CLEANUP // remove this definitions ?
56 const Register IC_Klass = rscratch2; // where the IC klass is cached
57 const Register SYNC_header = r0; // synchronization header
58 const Register SHIFT_count = r0; // where count for shift operations must be
59
60 #define __ _masm->
61
434 if (LockingMode == LM_MONITOR) {
435 __ b(*stub->entry());
436 } else {
437 __ unlock_object(r5, r4, r0, r6, *stub->entry());
438 }
439 __ bind(*stub->continuation());
440 }
441
442 if (compilation()->env()->dtrace_method_probes()) {
443 __ mov(c_rarg0, rthread);
444 __ mov_metadata(c_rarg1, method()->constant_encoding());
445 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
446 }
447
448 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
449 __ mov(r0, r19); // Restore the exception
450 }
451
452 // remove the activation and dispatch to the unwind handler
453 __ block_comment("remove_frame and dispatch to the unwind handler");
454 __ remove_frame(initial_frame_size_in_bytes());
455 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
456
457 // Emit the slow path assembly
458 if (stub != nullptr) {
459 stub->emit_code(this);
460 }
461
462 return offset;
463 }
464
465
466 int LIR_Assembler::emit_deopt_handler() {
467 // generate code for exception handler
468 address handler_base = __ start_a_stub(deopt_handler_size());
469 if (handler_base == nullptr) {
470 // not enough space left for the handler
471 bailout("deopt handler overflow");
472 return -1;
473 }
474
478 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
479 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
480 __ end_a_stub();
481
482 return offset;
483 }
484
485 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
486 _masm->code_section()->relocate(adr, relocInfo::poll_type);
487 int pc_offset = code_offset();
488 flush_debug_info(pc_offset);
489 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
490 if (info->exception_handlers() != nullptr) {
491 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
492 }
493 }
494
495 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
496 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
497
498 // Pop the stack before the safepoint code
499 __ remove_frame(initial_frame_size_in_bytes());
500
501 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
502 __ reserved_stack_check();
503 }
504
505 code_stub->set_safepoint_offset(__ offset());
506 __ relocate(relocInfo::poll_return_type);
507 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
508 __ ret(lr);
509 }
510
511 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
512 guarantee(info != nullptr, "Shouldn't be null");
513 __ get_polling_page(rscratch1, relocInfo::poll_type);
514 add_debug_info_for_branch(info); // This isn't just debug info:
515 // it's the oop map
516 __ read_polling_page(rscratch1, relocInfo::poll_type);
517 return __ offset();
518 }
519
520
521 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
522 if (from_reg == r31_sp)
523 from_reg = sp;
524 if (to_reg == r31_sp)
525 to_reg = sp;
526 __ mov(to_reg, from_reg);
527 }
528
529 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
530
537 switch (c->type()) {
538 case T_INT: {
539 assert(patch_code == lir_patch_none, "no patching handled here");
540 __ movw(dest->as_register(), c->as_jint());
541 break;
542 }
543
544 case T_ADDRESS: {
545 assert(patch_code == lir_patch_none, "no patching handled here");
546 __ mov(dest->as_register(), c->as_jint());
547 break;
548 }
549
550 case T_LONG: {
551 assert(patch_code == lir_patch_none, "no patching handled here");
552 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
553 break;
554 }
555
556 case T_OBJECT: {
557 if (patch_code == lir_patch_none) {
558 jobject2reg(c->as_jobject(), dest->as_register());
559 } else {
560 jobject2reg_with_patching(dest->as_register(), info);
561 }
562 break;
563 }
564
565 case T_METADATA: {
566 if (patch_code != lir_patch_none) {
567 klass2reg_with_patching(dest->as_register(), info);
568 } else {
569 __ mov_metadata(dest->as_register(), c->as_metadata());
570 }
571 break;
572 }
573
574 case T_FLOAT: {
575 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
576 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
577 } else {
578 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
579 __ ldrs(dest->as_float_reg(), Address(rscratch1));
580 }
650 LIR_Const* c = src->as_constant_ptr();
651 LIR_Address* to_addr = dest->as_address_ptr();
652
653 void (Assembler::* insn)(Register Rt, const Address &adr);
654
655 switch (type) {
656 case T_ADDRESS:
657 assert(c->as_jint() == 0, "should be");
658 insn = &Assembler::str;
659 break;
660 case T_LONG:
661 assert(c->as_jlong() == 0, "should be");
662 insn = &Assembler::str;
663 break;
664 case T_INT:
665 assert(c->as_jint() == 0, "should be");
666 insn = &Assembler::strw;
667 break;
668 case T_OBJECT:
669 case T_ARRAY:
670 assert(c->as_jobject() == 0, "should be");
671 if (UseCompressedOops && !wide) {
672 insn = &Assembler::strw;
673 } else {
674 insn = &Assembler::str;
675 }
676 break;
677 case T_CHAR:
678 case T_SHORT:
679 assert(c->as_jint() == 0, "should be");
680 insn = &Assembler::strh;
681 break;
682 case T_BOOLEAN:
683 case T_BYTE:
684 assert(c->as_jint() == 0, "should be");
685 insn = &Assembler::strb;
686 break;
687 default:
688 ShouldNotReachHere();
689 insn = &Assembler::str; // unreachable
1000 case T_SHORT:
1001 __ ldrsh(dest->as_register(), as_Address(from_addr));
1002 break;
1003
1004 default:
1005 ShouldNotReachHere();
1006 }
1007
1008 if (is_reference_type(type)) {
1009 if (UseCompressedOops && !wide) {
1010 __ decode_heap_oop(dest->as_register());
1011 }
1012
1013 if (!(UseZGC && !ZGenerational)) {
1014 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1015 __ verify_oop(dest->as_register());
1016 }
1017 }
1018 }
1019
1020
1021 int LIR_Assembler::array_element_size(BasicType type) const {
1022 int elem_size = type2aelembytes(type);
1023 return exact_log2(elem_size);
1024 }
1025
1026
1027 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1028 switch (op->code()) {
1029 case lir_idiv:
1030 case lir_irem:
1031 arithmetic_idiv(op->code(),
1032 op->in_opr1(),
1033 op->in_opr2(),
1034 op->in_opr3(),
1035 op->result_opr(),
1036 op->info());
1037 break;
1038 case lir_fmad:
1039 __ fmaddd(op->result_opr()->as_double_reg(),
1191 __ ldrb(rscratch1, Address(op->klass()->as_register(),
1192 InstanceKlass::init_state_offset()));
1193 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1194 add_debug_info_for_null_check_here(op->stub()->info());
1195 __ br(Assembler::NE, *op->stub()->entry());
1196 }
1197 __ allocate_object(op->obj()->as_register(),
1198 op->tmp1()->as_register(),
1199 op->tmp2()->as_register(),
1200 op->header_size(),
1201 op->object_size(),
1202 op->klass()->as_register(),
1203 *op->stub()->entry());
1204 __ bind(*op->stub()->continuation());
1205 }
1206
1207 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1208 Register len = op->len()->as_register();
1209 __ uxtw(len, len);
1210
1211 if (UseSlowPath ||
1212 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1213 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1214 __ b(*op->stub()->entry());
1215 } else {
1216 Register tmp1 = op->tmp1()->as_register();
1217 Register tmp2 = op->tmp2()->as_register();
1218 Register tmp3 = op->tmp3()->as_register();
1219 if (len == tmp1) {
1220 tmp1 = tmp3;
1221 } else if (len == tmp2) {
1222 tmp2 = tmp3;
1223 } else if (len == tmp3) {
1224 // everything is ok
1225 } else {
1226 __ mov(tmp3, len);
1227 }
1228 __ allocate_array(op->obj()->as_register(),
1229 len,
1230 tmp1,
1231 tmp2,
1296 assert(data != nullptr, "need data for type check");
1297 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1298 }
1299 Label* success_target = success;
1300 Label* failure_target = failure;
1301
1302 if (obj == k_RInfo) {
1303 k_RInfo = dst;
1304 } else if (obj == klass_RInfo) {
1305 klass_RInfo = dst;
1306 }
1307 if (k->is_loaded() && !UseCompressedClassPointers) {
1308 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1309 } else {
1310 Rtmp1 = op->tmp3()->as_register();
1311 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1312 }
1313
1314 assert_different_registers(obj, k_RInfo, klass_RInfo);
1315
1316 if (should_profile) {
1317 Register mdo = klass_RInfo;
1318 __ mov_metadata(mdo, md->constant_encoding());
1319 Label not_null;
1320 __ cbnz(obj, not_null);
1321 // Object is null; update MDO and exit
1322 Address data_addr
1323 = __ form_address(rscratch2, mdo,
1324 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1325 0);
1326 __ ldrb(rscratch1, data_addr);
1327 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1328 __ strb(rscratch1, data_addr);
1329 __ b(*obj_is_null);
1330 __ bind(not_null);
1331
1332 Label update_done;
1333 Register recv = k_RInfo;
1334 __ load_klass(recv, obj);
1335 type_profile_helper(mdo, md, data, recv, &update_done);
1336 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1337 __ addptr(counter_addr, DataLayout::counter_increment);
1338
1339 __ bind(update_done);
1340 } else {
1341 __ cbz(obj, *obj_is_null);
1342 }
1343
1344 if (!k->is_loaded()) {
1345 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1346 } else {
1347 __ mov_metadata(k_RInfo, k->constant_encoding());
1348 }
1349 __ verify_oop(obj);
1350
1351 if (op->fast_check()) {
1352 // get object class
1353 // not a safepoint as obj null check happens earlier
1354 __ load_klass(rscratch1, obj);
1355 __ cmp( rscratch1, k_RInfo);
1356
1357 __ br(Assembler::NE, *failure_target);
1358 // successful cast, fall through to profile or jump
1359 } else {
1360 // get object class
1361 // not a safepoint as obj null check happens earlier
1480 __ bind(success);
1481 if (dst != obj) {
1482 __ mov(dst, obj);
1483 }
1484 } else if (code == lir_instanceof) {
1485 Register obj = op->object()->as_register();
1486 Register dst = op->result_opr()->as_register();
1487 Label success, failure, done;
1488 emit_typecheck_helper(op, &success, &failure, &failure);
1489 __ bind(failure);
1490 __ mov(dst, zr);
1491 __ b(done);
1492 __ bind(success);
1493 __ mov(dst, 1);
1494 __ bind(done);
1495 } else {
1496 ShouldNotReachHere();
1497 }
1498 }
1499
1500 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1501 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1502 __ cset(rscratch1, Assembler::NE);
1503 __ membar(__ AnyAny);
1504 }
1505
1506 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1507 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1508 __ cset(rscratch1, Assembler::NE);
1509 __ membar(__ AnyAny);
1510 }
1511
1512
1513 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1514 Register addr;
1515 if (op->addr()->is_register()) {
1516 addr = as_reg(op->addr());
1517 } else {
1518 assert(op->addr()->is_address(), "what else?");
1519 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1996 __ cmp(left->as_register_lo(), right->as_register_lo());
1997 __ mov(dst->as_register(), (uint64_t)-1L);
1998 __ br(Assembler::LT, done);
1999 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2000 __ bind(done);
2001 } else {
2002 ShouldNotReachHere();
2003 }
2004 }
2005
2006
2007 void LIR_Assembler::align_call(LIR_Code code) { }
2008
2009
2010 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2011 address call = __ trampoline_call(Address(op->addr(), rtype));
2012 if (call == nullptr) {
2013 bailout("trampoline stub overflow");
2014 return;
2015 }
2016 add_call_info(code_offset(), op->info());
2017 __ post_call_nop();
2018 }
2019
2020
2021 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2022 address call = __ ic_call(op->addr());
2023 if (call == nullptr) {
2024 bailout("trampoline stub overflow");
2025 return;
2026 }
2027 add_call_info(code_offset(), op->info());
2028 __ post_call_nop();
2029 }
2030
2031 void LIR_Assembler::emit_static_call_stub() {
2032 address call_pc = __ pc();
2033 address stub = __ start_a_stub(call_stub_size());
2034 if (stub == nullptr) {
2035 bailout("static call stub overflow");
2036 return;
2037 }
2038
2039 int start = __ offset();
2040
2041 __ relocate(static_stub_Relocation::spec(call_pc));
2042 __ emit_static_call_stub();
2043
2044 assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2045 <= call_stub_size(), "stub too big");
2046 __ end_a_stub();
2047 }
2170
2171
2172 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2173 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2174 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2175 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2176 __ mov (rscratch1, c);
2177 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2178 }
2179
2180
2181 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2182 ShouldNotReachHere();
2183 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2184 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2185 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2186 __ lea(rscratch1, __ constant_oop_address(o));
2187 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2188 }
2189
2190
2191 // This code replaces a call to arraycopy; no exception may
2192 // be thrown in this code, they must be thrown in the System.arraycopy
2193 // activation frame; we could save some checks if this would not be the case
2194 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2195 ciArrayKlass* default_type = op->expected_type();
2196 Register src = op->src()->as_register();
2197 Register dst = op->dst()->as_register();
2198 Register src_pos = op->src_pos()->as_register();
2199 Register dst_pos = op->dst_pos()->as_register();
2200 Register length = op->length()->as_register();
2201 Register tmp = op->tmp()->as_register();
2202
2203 CodeStub* stub = op->stub();
2204 int flags = op->flags();
2205 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2206 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2207
2208 // if we don't know anything, just go through the generic arraycopy
2209 if (default_type == nullptr // || basic_type == T_OBJECT
2210 ) {
2211 Label done;
2212 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2213
2214 // Save the arguments in case the generic arraycopy fails and we
2215 // have to fall back to the JNI stub
2216 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2217 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2218 __ str(src, Address(sp, 4*BytesPerWord));
2219
2220 address copyfunc_addr = StubRoutines::generic_arraycopy();
2221 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2222
2223 // The arguments are in java calling convention so we shift them
2224 // to C convention
2225 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2226 __ mov(c_rarg0, j_rarg0);
2227 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2241 __ cbz(r0, *stub->continuation());
2242
2243 // Reload values from the stack so they are where the stub
2244 // expects them.
2245 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2246 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2247 __ ldr(src, Address(sp, 4*BytesPerWord));
2248
2249 // r0 is -1^K where K == partial copied count
2250 __ eonw(rscratch1, r0, zr);
2251 // adjust length down and src/end pos up by partial copied count
2252 __ subw(length, length, rscratch1);
2253 __ addw(src_pos, src_pos, rscratch1);
2254 __ addw(dst_pos, dst_pos, rscratch1);
2255 __ b(*stub->entry());
2256
2257 __ bind(*stub->continuation());
2258 return;
2259 }
2260
2261 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2262
2263 int elem_size = type2aelembytes(basic_type);
2264 int scale = exact_log2(elem_size);
2265
2266 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2267 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2268 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2269 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2270
2271 // test for null
2272 if (flags & LIR_OpArrayCopy::src_null_check) {
2273 __ cbz(src, *stub->entry());
2274 }
2275 if (flags & LIR_OpArrayCopy::dst_null_check) {
2276 __ cbz(dst, *stub->entry());
2277 }
2278
2279 // If the compiler was not able to prove that exact type of the source or the destination
2280 // of the arraycopy is an array type, check at runtime if the source or the destination is
2828 __ verify_klass_ptr(tmp);
2829 #endif
2830 } else {
2831 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
2832 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2833
2834 __ ldr(tmp, mdo_addr);
2835 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2836
2837 __ orr(tmp, tmp, TypeEntries::type_unknown);
2838 __ str(tmp, mdo_addr);
2839 // FIXME: Write barrier needed here?
2840 }
2841 }
2842
2843 __ bind(next);
2844 }
2845 COMMENT("} emit_profile_type");
2846 }
2847
2848
2849 void LIR_Assembler::align_backward_branch_target() {
2850 }
2851
2852
2853 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2854 // tmp must be unused
2855 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2856
2857 if (left->is_single_cpu()) {
2858 assert(dest->is_single_cpu(), "expect single result reg");
2859 __ negw(dest->as_register(), left->as_register());
2860 } else if (left->is_double_cpu()) {
2861 assert(dest->is_double_cpu(), "expect double result reg");
2862 __ neg(dest->as_register_lo(), left->as_register_lo());
2863 } else if (left->is_single_fpu()) {
2864 assert(dest->is_single_fpu(), "expect single float result reg");
2865 __ fnegs(dest->as_float_reg(), left->as_float_reg());
2866 } else {
2867 assert(left->is_double_fpu(), "expect double float operand reg");
2968 void LIR_Assembler::membar_loadload() {
2969 __ membar(Assembler::LoadLoad);
2970 }
2971
2972 void LIR_Assembler::membar_storestore() {
2973 __ membar(MacroAssembler::StoreStore);
2974 }
2975
2976 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2977
2978 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
2979
2980 void LIR_Assembler::on_spin_wait() {
2981 __ spin_wait();
2982 }
2983
2984 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
2985 __ mov(result_reg->as_register(), rthread);
2986 }
2987
2988
2989 void LIR_Assembler::peephole(LIR_List *lir) {
2990 #if 0
2991 if (tableswitch_count >= max_tableswitches)
2992 return;
2993
2994 /*
2995 This finite-state automaton recognizes sequences of compare-and-
2996 branch instructions. We will turn them into a tableswitch. You
2997 could argue that C1 really shouldn't be doing this sort of
2998 optimization, but without it the code is really horrible.
2999 */
3000
3001 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3002 int first_key, last_key = -2147483648;
3003 int next_key = 0;
3004 int start_insn = -1;
3005 int last_insn = -1;
3006 Register reg = noreg;
3007 LIR_Opr reg_opr;
|
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.inline.hpp"
28 #include "asm/assembler.hpp"
29 #include "c1/c1_CodeStubs.hpp"
30 #include "c1/c1_Compilation.hpp"
31 #include "c1/c1_LIRAssembler.hpp"
32 #include "c1/c1_MacroAssembler.hpp"
33 #include "c1/c1_Runtime1.hpp"
34 #include "c1/c1_ValueStack.hpp"
35 #include "ci/ciArrayKlass.hpp"
36 #include "ci/ciInlineKlass.hpp"
37 #include "ci/ciInstance.hpp"
38 #include "code/compiledIC.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/gc_globals.hpp"
41 #include "nativeInst_aarch64.hpp"
42 #include "oops/objArrayKlass.hpp"
43 #include "oops/oop.inline.hpp"
44 #include "runtime/frame.inline.hpp"
45 #include "runtime/sharedRuntime.hpp"
46 #include "runtime/stubRoutines.hpp"
47 #include "utilities/powerOfTwo.hpp"
48 #include "vmreg_aarch64.inline.hpp"
49
50
51 #ifndef PRODUCT
52 #define COMMENT(x) do { __ block_comment(x); } while (0)
53 #else
54 #define COMMENT(x)
55 #endif
56
57 NEEDS_CLEANUP // remove this definitions ?
58 const Register IC_Klass = rscratch2; // where the IC klass is cached
59 const Register SYNC_header = r0; // synchronization header
60 const Register SHIFT_count = r0; // where count for shift operations must be
61
62 #define __ _masm->
63
436 if (LockingMode == LM_MONITOR) {
437 __ b(*stub->entry());
438 } else {
439 __ unlock_object(r5, r4, r0, r6, *stub->entry());
440 }
441 __ bind(*stub->continuation());
442 }
443
444 if (compilation()->env()->dtrace_method_probes()) {
445 __ mov(c_rarg0, rthread);
446 __ mov_metadata(c_rarg1, method()->constant_encoding());
447 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
448 }
449
450 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
451 __ mov(r0, r19); // Restore the exception
452 }
453
454 // remove the activation and dispatch to the unwind handler
455 __ block_comment("remove_frame and dispatch to the unwind handler");
456 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
457 __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
458
459 // Emit the slow path assembly
460 if (stub != nullptr) {
461 stub->emit_code(this);
462 }
463
464 return offset;
465 }
466
467
468 int LIR_Assembler::emit_deopt_handler() {
469 // generate code for exception handler
470 address handler_base = __ start_a_stub(deopt_handler_size());
471 if (handler_base == nullptr) {
472 // not enough space left for the handler
473 bailout("deopt handler overflow");
474 return -1;
475 }
476
480 __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
481 guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
482 __ end_a_stub();
483
484 return offset;
485 }
486
487 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
488 _masm->code_section()->relocate(adr, relocInfo::poll_type);
489 int pc_offset = code_offset();
490 flush_debug_info(pc_offset);
491 info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
492 if (info->exception_handlers() != nullptr) {
493 compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
494 }
495 }
496
497 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
498 assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
499
500 if (InlineTypeReturnedAsFields) {
501 // Check if we are returning an non-null inline type and load its fields into registers
502 ciType* return_type = compilation()->method()->return_type();
503 if (return_type->is_inlinetype()) {
504 ciInlineKlass* vk = return_type->as_inline_klass();
505 if (vk->can_be_returned_as_fields()) {
506 address unpack_handler = vk->unpack_handler();
507 assert(unpack_handler != nullptr, "must be");
508 __ far_call(RuntimeAddress(unpack_handler));
509 }
510 } else if (return_type->is_instance_klass() && (!return_type->is_loaded() || StressCallingConvention)) {
511 Label skip;
512 __ test_oop_is_not_inline_type(r0, rscratch2, skip);
513
514 // Load fields from a buffered value with an inline class specific handler
515 __ load_klass(rscratch1 /*dst*/, r0 /*src*/);
516 __ ldr(rscratch1, Address(rscratch1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
517 __ ldr(rscratch1, Address(rscratch1, InlineKlass::unpack_handler_offset()));
518 // Unpack handler can be null if inline type is not scalarizable in returns
519 __ cbz(rscratch1, skip);
520 __ blr(rscratch1);
521
522 __ bind(skip);
523 }
524 // At this point, r0 points to the value object (for interpreter or C1 caller).
525 // The fields of the object are copied into registers (for C2 caller).
526 }
527
528 // Pop the stack before the safepoint code
529 __ remove_frame(initial_frame_size_in_bytes(), needs_stack_repair());
530
531 if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
532 __ reserved_stack_check();
533 }
534
535 code_stub->set_safepoint_offset(__ offset());
536 __ relocate(relocInfo::poll_return_type);
537 __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
538 __ ret(lr);
539 }
540
541 int LIR_Assembler::store_inline_type_fields_to_buf(ciInlineKlass* vk) {
542 return (__ store_inline_type_fields_to_buf(vk, false));
543 }
544
545 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
546 guarantee(info != nullptr, "Shouldn't be null");
547 __ get_polling_page(rscratch1, relocInfo::poll_type);
548 add_debug_info_for_branch(info); // This isn't just debug info:
549 // it's the oop map
550 __ read_polling_page(rscratch1, relocInfo::poll_type);
551 return __ offset();
552 }
553
554
555 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
556 if (from_reg == r31_sp)
557 from_reg = sp;
558 if (to_reg == r31_sp)
559 to_reg = sp;
560 __ mov(to_reg, from_reg);
561 }
562
563 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
564
571 switch (c->type()) {
572 case T_INT: {
573 assert(patch_code == lir_patch_none, "no patching handled here");
574 __ movw(dest->as_register(), c->as_jint());
575 break;
576 }
577
578 case T_ADDRESS: {
579 assert(patch_code == lir_patch_none, "no patching handled here");
580 __ mov(dest->as_register(), c->as_jint());
581 break;
582 }
583
584 case T_LONG: {
585 assert(patch_code == lir_patch_none, "no patching handled here");
586 __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
587 break;
588 }
589
590 case T_OBJECT: {
591 if (patch_code != lir_patch_none) {
592 jobject2reg_with_patching(dest->as_register(), info);
593 } else {
594 jobject2reg(c->as_jobject(), dest->as_register());
595 }
596 break;
597 }
598
599 case T_METADATA: {
600 if (patch_code != lir_patch_none) {
601 klass2reg_with_patching(dest->as_register(), info);
602 } else {
603 __ mov_metadata(dest->as_register(), c->as_metadata());
604 }
605 break;
606 }
607
608 case T_FLOAT: {
609 if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
610 __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
611 } else {
612 __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
613 __ ldrs(dest->as_float_reg(), Address(rscratch1));
614 }
684 LIR_Const* c = src->as_constant_ptr();
685 LIR_Address* to_addr = dest->as_address_ptr();
686
687 void (Assembler::* insn)(Register Rt, const Address &adr);
688
689 switch (type) {
690 case T_ADDRESS:
691 assert(c->as_jint() == 0, "should be");
692 insn = &Assembler::str;
693 break;
694 case T_LONG:
695 assert(c->as_jlong() == 0, "should be");
696 insn = &Assembler::str;
697 break;
698 case T_INT:
699 assert(c->as_jint() == 0, "should be");
700 insn = &Assembler::strw;
701 break;
702 case T_OBJECT:
703 case T_ARRAY:
704 // Non-null case is not handled on aarch64 but handled on x86
705 // FIXME: do we need to add it here?
706 assert(c->as_jobject() == 0, "should be");
707 if (UseCompressedOops && !wide) {
708 insn = &Assembler::strw;
709 } else {
710 insn = &Assembler::str;
711 }
712 break;
713 case T_CHAR:
714 case T_SHORT:
715 assert(c->as_jint() == 0, "should be");
716 insn = &Assembler::strh;
717 break;
718 case T_BOOLEAN:
719 case T_BYTE:
720 assert(c->as_jint() == 0, "should be");
721 insn = &Assembler::strb;
722 break;
723 default:
724 ShouldNotReachHere();
725 insn = &Assembler::str; // unreachable
1036 case T_SHORT:
1037 __ ldrsh(dest->as_register(), as_Address(from_addr));
1038 break;
1039
1040 default:
1041 ShouldNotReachHere();
1042 }
1043
1044 if (is_reference_type(type)) {
1045 if (UseCompressedOops && !wide) {
1046 __ decode_heap_oop(dest->as_register());
1047 }
1048
1049 if (!(UseZGC && !ZGenerational)) {
1050 // Load barrier has not yet been applied, so ZGC can't verify the oop here
1051 __ verify_oop(dest->as_register());
1052 }
1053 }
1054 }
1055
1056 void LIR_Assembler::move(LIR_Opr src, LIR_Opr dst) {
1057 assert(dst->is_cpu_register(), "must be");
1058 assert(dst->type() == src->type(), "must be");
1059
1060 if (src->is_cpu_register()) {
1061 reg2reg(src, dst);
1062 } else if (src->is_stack()) {
1063 stack2reg(src, dst, dst->type());
1064 } else if (src->is_constant()) {
1065 const2reg(src, dst, lir_patch_none, nullptr);
1066 } else {
1067 ShouldNotReachHere();
1068 }
1069 }
1070
1071 int LIR_Assembler::array_element_size(BasicType type) const {
1072 int elem_size = type2aelembytes(type);
1073 return exact_log2(elem_size);
1074 }
1075
1076
1077 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1078 switch (op->code()) {
1079 case lir_idiv:
1080 case lir_irem:
1081 arithmetic_idiv(op->code(),
1082 op->in_opr1(),
1083 op->in_opr2(),
1084 op->in_opr3(),
1085 op->result_opr(),
1086 op->info());
1087 break;
1088 case lir_fmad:
1089 __ fmaddd(op->result_opr()->as_double_reg(),
1241 __ ldrb(rscratch1, Address(op->klass()->as_register(),
1242 InstanceKlass::init_state_offset()));
1243 __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1244 add_debug_info_for_null_check_here(op->stub()->info());
1245 __ br(Assembler::NE, *op->stub()->entry());
1246 }
1247 __ allocate_object(op->obj()->as_register(),
1248 op->tmp1()->as_register(),
1249 op->tmp2()->as_register(),
1250 op->header_size(),
1251 op->object_size(),
1252 op->klass()->as_register(),
1253 *op->stub()->entry());
1254 __ bind(*op->stub()->continuation());
1255 }
1256
1257 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1258 Register len = op->len()->as_register();
1259 __ uxtw(len, len);
1260
1261 if (UseSlowPath || op->is_null_free() ||
1262 (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1263 (!UseFastNewTypeArray && !is_reference_type(op->type()))) {
1264 __ b(*op->stub()->entry());
1265 } else {
1266 Register tmp1 = op->tmp1()->as_register();
1267 Register tmp2 = op->tmp2()->as_register();
1268 Register tmp3 = op->tmp3()->as_register();
1269 if (len == tmp1) {
1270 tmp1 = tmp3;
1271 } else if (len == tmp2) {
1272 tmp2 = tmp3;
1273 } else if (len == tmp3) {
1274 // everything is ok
1275 } else {
1276 __ mov(tmp3, len);
1277 }
1278 __ allocate_array(op->obj()->as_register(),
1279 len,
1280 tmp1,
1281 tmp2,
1346 assert(data != nullptr, "need data for type check");
1347 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1348 }
1349 Label* success_target = success;
1350 Label* failure_target = failure;
1351
1352 if (obj == k_RInfo) {
1353 k_RInfo = dst;
1354 } else if (obj == klass_RInfo) {
1355 klass_RInfo = dst;
1356 }
1357 if (k->is_loaded() && !UseCompressedClassPointers) {
1358 select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1359 } else {
1360 Rtmp1 = op->tmp3()->as_register();
1361 select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1362 }
1363
1364 assert_different_registers(obj, k_RInfo, klass_RInfo);
1365
1366 if (op->need_null_check()) {
1367 if (should_profile) {
1368 Register mdo = klass_RInfo;
1369 __ mov_metadata(mdo, md->constant_encoding());
1370 Label not_null;
1371 __ cbnz(obj, not_null);
1372 // Object is null; update MDO and exit
1373 Address data_addr
1374 = __ form_address(rscratch2, mdo,
1375 md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1376 0);
1377 __ ldrb(rscratch1, data_addr);
1378 __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1379 __ strb(rscratch1, data_addr);
1380 __ b(*obj_is_null);
1381 __ bind(not_null);
1382
1383 Label update_done;
1384 Register recv = k_RInfo;
1385 __ load_klass(recv, obj);
1386 type_profile_helper(mdo, md, data, recv, &update_done);
1387 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1388 __ addptr(counter_addr, DataLayout::counter_increment);
1389
1390 __ bind(update_done);
1391 } else {
1392 __ cbz(obj, *obj_is_null);
1393 }
1394 }
1395
1396 if (!k->is_loaded()) {
1397 klass2reg_with_patching(k_RInfo, op->info_for_patch());
1398 } else {
1399 __ mov_metadata(k_RInfo, k->constant_encoding());
1400 }
1401 __ verify_oop(obj);
1402
1403 if (op->fast_check()) {
1404 // get object class
1405 // not a safepoint as obj null check happens earlier
1406 __ load_klass(rscratch1, obj);
1407 __ cmp( rscratch1, k_RInfo);
1408
1409 __ br(Assembler::NE, *failure_target);
1410 // successful cast, fall through to profile or jump
1411 } else {
1412 // get object class
1413 // not a safepoint as obj null check happens earlier
1532 __ bind(success);
1533 if (dst != obj) {
1534 __ mov(dst, obj);
1535 }
1536 } else if (code == lir_instanceof) {
1537 Register obj = op->object()->as_register();
1538 Register dst = op->result_opr()->as_register();
1539 Label success, failure, done;
1540 emit_typecheck_helper(op, &success, &failure, &failure);
1541 __ bind(failure);
1542 __ mov(dst, zr);
1543 __ b(done);
1544 __ bind(success);
1545 __ mov(dst, 1);
1546 __ bind(done);
1547 } else {
1548 ShouldNotReachHere();
1549 }
1550 }
1551
1552 void LIR_Assembler::emit_opFlattenedArrayCheck(LIR_OpFlattenedArrayCheck* op) {
1553 // We are loading/storing from/to an array that *may* be a flat array (the
1554 // declared type is Object[], abstract[], interface[] or VT.ref[]).
1555 // If this array is a flat array, take the slow path.
1556
1557 Register klass = op->tmp()->as_register();
1558 if (UseArrayMarkWordCheck) {
1559 __ test_flat_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1560 } else {
1561 __ load_klass(klass, op->array()->as_register());
1562 __ ldrw(klass, Address(klass, Klass::layout_helper_offset()));
1563 __ tst(klass, Klass::_lh_array_tag_flat_value_bit_inplace);
1564 __ br(Assembler::NE, *op->stub()->entry());
1565 }
1566 if (!op->value()->is_illegal()) {
1567 // The array is not a flat array, but it might be null-free. If we are storing
1568 // a null into a null-free array, take the slow path (which will throw NPE).
1569 Label skip;
1570 __ cbnz(op->value()->as_register(), skip);
1571 if (UseArrayMarkWordCheck) {
1572 __ test_null_free_array_oop(op->array()->as_register(), op->tmp()->as_register(), *op->stub()->entry());
1573 } else {
1574 __ tst(klass, Klass::_lh_null_free_array_bit_inplace);
1575 __ br(Assembler::NE, *op->stub()->entry());
1576 }
1577 __ bind(skip);
1578 }
1579 }
1580
1581 void LIR_Assembler::emit_opNullFreeArrayCheck(LIR_OpNullFreeArrayCheck* op) {
1582 // We are storing into an array that *may* be null-free (the declared type is
1583 // Object[], abstract[], interface[] or VT.ref[]).
1584 if (UseArrayMarkWordCheck) {
1585 Label test_mark_word;
1586 Register tmp = op->tmp()->as_register();
1587 __ ldr(tmp, Address(op->array()->as_register(), oopDesc::mark_offset_in_bytes()));
1588 __ tst(tmp, markWord::unlocked_value);
1589 __ br(Assembler::NE, test_mark_word);
1590 __ load_prototype_header(tmp, op->array()->as_register());
1591 __ bind(test_mark_word);
1592 __ tst(tmp, markWord::null_free_array_bit_in_place);
1593 } else {
1594 Register klass = op->tmp()->as_register();
1595 __ load_klass(klass, op->array()->as_register());
1596 __ ldr(klass, Address(klass, Klass::layout_helper_offset()));
1597 __ tst(klass, Klass::_lh_null_free_array_bit_inplace);
1598 }
1599 }
1600
1601 void LIR_Assembler::emit_opSubstitutabilityCheck(LIR_OpSubstitutabilityCheck* op) {
1602 Label L_oops_equal;
1603 Label L_oops_not_equal;
1604 Label L_end;
1605
1606 Register left = op->left()->as_register();
1607 Register right = op->right()->as_register();
1608
1609 __ cmp(left, right);
1610 __ br(Assembler::EQ, L_oops_equal);
1611
1612 // (1) Null check -- if one of the operands is null, the other must not be null (because
1613 // the two references are not equal), so they are not substitutable,
1614 // FIXME: do null check only if the operand is nullable
1615 {
1616 __ cbz(left, L_oops_not_equal);
1617 __ cbz(right, L_oops_not_equal);
1618 }
1619
1620 ciKlass* left_klass = op->left_klass();
1621 ciKlass* right_klass = op->right_klass();
1622
1623 // (2) Inline type check -- if either of the operands is not a inline type,
1624 // they are not substitutable. We do this only if we are not sure that the
1625 // operands are inline type
1626 if ((left_klass == nullptr || right_klass == nullptr) ||// The klass is still unloaded, or came from a Phi node.
1627 !left_klass->is_inlinetype() || !right_klass->is_inlinetype()) {
1628 Register tmp1 = op->tmp1()->as_register();
1629 __ mov(tmp1, markWord::inline_type_pattern);
1630 __ ldr(rscratch1, Address(left, oopDesc::mark_offset_in_bytes()));
1631 __ andr(tmp1, tmp1, rscratch1);
1632 __ ldr(rscratch1, Address(right, oopDesc::mark_offset_in_bytes()));
1633 __ andr(tmp1, tmp1, rscratch1);
1634 __ cmp(tmp1, (u1)markWord::inline_type_pattern);
1635 __ br(Assembler::NE, L_oops_not_equal);
1636 }
1637
1638 // (3) Same klass check: if the operands are of different klasses, they are not substitutable.
1639 if (left_klass != nullptr && left_klass->is_inlinetype() && left_klass == right_klass) {
1640 // No need to load klass -- the operands are statically known to be the same inline klass.
1641 __ b(*op->stub()->entry());
1642 } else {
1643 Register left_klass_op = op->left_klass_op()->as_register();
1644 Register right_klass_op = op->right_klass_op()->as_register();
1645
1646 if (UseCompressedClassPointers) {
1647 __ ldrw(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1648 __ ldrw(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1649 __ cmpw(left_klass_op, right_klass_op);
1650 } else {
1651 __ ldr(left_klass_op, Address(left, oopDesc::klass_offset_in_bytes()));
1652 __ ldr(right_klass_op, Address(right, oopDesc::klass_offset_in_bytes()));
1653 __ cmp(left_klass_op, right_klass_op);
1654 }
1655
1656 __ br(Assembler::EQ, *op->stub()->entry()); // same klass -> do slow check
1657 // fall through to L_oops_not_equal
1658 }
1659
1660 __ bind(L_oops_not_equal);
1661 move(op->not_equal_result(), op->result_opr());
1662 __ b(L_end);
1663
1664 __ bind(L_oops_equal);
1665 move(op->equal_result(), op->result_opr());
1666 __ b(L_end);
1667
1668 // We've returned from the stub. R0 contains 0x0 IFF the two
1669 // operands are not substitutable. (Don't compare against 0x1 in case the
1670 // C compiler is naughty)
1671 __ bind(*op->stub()->continuation());
1672 __ cbz(r0, L_oops_not_equal); // (call_stub() == 0x0) -> not_equal
1673 move(op->equal_result(), op->result_opr()); // (call_stub() != 0x0) -> equal
1674 // fall-through
1675 __ bind(L_end);
1676 }
1677
1678
1679 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1680 __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1681 __ cset(rscratch1, Assembler::NE);
1682 __ membar(__ AnyAny);
1683 }
1684
1685 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1686 __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1687 __ cset(rscratch1, Assembler::NE);
1688 __ membar(__ AnyAny);
1689 }
1690
1691
1692 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1693 Register addr;
1694 if (op->addr()->is_register()) {
1695 addr = as_reg(op->addr());
1696 } else {
1697 assert(op->addr()->is_address(), "what else?");
1698 LIR_Address* addr_ptr = op->addr()->as_address_ptr();
2175 __ cmp(left->as_register_lo(), right->as_register_lo());
2176 __ mov(dst->as_register(), (uint64_t)-1L);
2177 __ br(Assembler::LT, done);
2178 __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2179 __ bind(done);
2180 } else {
2181 ShouldNotReachHere();
2182 }
2183 }
2184
2185
2186 void LIR_Assembler::align_call(LIR_Code code) { }
2187
2188
2189 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2190 address call = __ trampoline_call(Address(op->addr(), rtype));
2191 if (call == nullptr) {
2192 bailout("trampoline stub overflow");
2193 return;
2194 }
2195 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2196 __ post_call_nop();
2197 }
2198
2199
2200 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2201 address call = __ ic_call(op->addr());
2202 if (call == nullptr) {
2203 bailout("trampoline stub overflow");
2204 return;
2205 }
2206 add_call_info(code_offset(), op->info(), op->maybe_return_as_fields());
2207 __ post_call_nop();
2208 }
2209
2210 void LIR_Assembler::emit_static_call_stub() {
2211 address call_pc = __ pc();
2212 address stub = __ start_a_stub(call_stub_size());
2213 if (stub == nullptr) {
2214 bailout("static call stub overflow");
2215 return;
2216 }
2217
2218 int start = __ offset();
2219
2220 __ relocate(static_stub_Relocation::spec(call_pc));
2221 __ emit_static_call_stub();
2222
2223 assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2224 <= call_stub_size(), "stub too big");
2225 __ end_a_stub();
2226 }
2349
2350
2351 void LIR_Assembler::store_parameter(jint c, int offset_from_rsp_in_words) {
2352 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2353 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2354 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2355 __ mov (rscratch1, c);
2356 __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2357 }
2358
2359
2360 void LIR_Assembler::store_parameter(jobject o, int offset_from_rsp_in_words) {
2361 ShouldNotReachHere();
2362 assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2363 int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2364 assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2365 __ lea(rscratch1, __ constant_oop_address(o));
2366 __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2367 }
2368
2369 void LIR_Assembler::arraycopy_inlinetype_check(Register obj, Register tmp, CodeStub* slow_path, bool is_dest, bool null_check) {
2370 if (null_check) {
2371 __ cbz(obj, *slow_path->entry());
2372 }
2373 if (UseArrayMarkWordCheck) {
2374 if (is_dest) {
2375 __ test_null_free_array_oop(obj, tmp, *slow_path->entry());
2376 } else {
2377 __ test_flat_array_oop(obj, tmp, *slow_path->entry());
2378 }
2379 } else {
2380 __ load_klass(tmp, obj);
2381 __ ldr(tmp, Address(tmp, Klass::layout_helper_offset()));
2382 if (is_dest) {
2383 // Take the slow path if it's a null_free destination array, in case the source array contains nulls.
2384 __ tst(tmp, Klass::_lh_null_free_array_bit_inplace);
2385 } else {
2386 __ tst(tmp, Klass::_lh_array_tag_flat_value_bit_inplace);
2387 }
2388 __ br(Assembler::NE, *slow_path->entry());
2389 }
2390 }
2391
2392 // This code replaces a call to arraycopy; no exception may
2393 // be thrown in this code, they must be thrown in the System.arraycopy
2394 // activation frame; we could save some checks if this would not be the case
2395 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2396 ciArrayKlass* default_type = op->expected_type();
2397 Register src = op->src()->as_register();
2398 Register dst = op->dst()->as_register();
2399 Register src_pos = op->src_pos()->as_register();
2400 Register dst_pos = op->dst_pos()->as_register();
2401 Register length = op->length()->as_register();
2402 Register tmp = op->tmp()->as_register();
2403
2404 CodeStub* stub = op->stub();
2405 int flags = op->flags();
2406 BasicType basic_type = default_type != nullptr ? default_type->element_type()->basic_type() : T_ILLEGAL;
2407 if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2408
2409 if (flags & LIR_OpArrayCopy::always_slow_path) {
2410 __ b(*stub->entry());
2411 __ bind(*stub->continuation());
2412 return;
2413 }
2414
2415 // if we don't know anything, just go through the generic arraycopy
2416 if (default_type == nullptr // || basic_type == T_OBJECT
2417 ) {
2418 Label done;
2419 assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2420
2421 // Save the arguments in case the generic arraycopy fails and we
2422 // have to fall back to the JNI stub
2423 __ stp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2424 __ stp(length, src_pos, Address(sp, 2*BytesPerWord));
2425 __ str(src, Address(sp, 4*BytesPerWord));
2426
2427 address copyfunc_addr = StubRoutines::generic_arraycopy();
2428 assert(copyfunc_addr != nullptr, "generic arraycopy stub required");
2429
2430 // The arguments are in java calling convention so we shift them
2431 // to C convention
2432 assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2433 __ mov(c_rarg0, j_rarg0);
2434 assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2448 __ cbz(r0, *stub->continuation());
2449
2450 // Reload values from the stack so they are where the stub
2451 // expects them.
2452 __ ldp(dst, dst_pos, Address(sp, 0*BytesPerWord));
2453 __ ldp(length, src_pos, Address(sp, 2*BytesPerWord));
2454 __ ldr(src, Address(sp, 4*BytesPerWord));
2455
2456 // r0 is -1^K where K == partial copied count
2457 __ eonw(rscratch1, r0, zr);
2458 // adjust length down and src/end pos up by partial copied count
2459 __ subw(length, length, rscratch1);
2460 __ addw(src_pos, src_pos, rscratch1);
2461 __ addw(dst_pos, dst_pos, rscratch1);
2462 __ b(*stub->entry());
2463
2464 __ bind(*stub->continuation());
2465 return;
2466 }
2467
2468 // Handle inline type arrays
2469 if (flags & LIR_OpArrayCopy::src_inlinetype_check) {
2470 arraycopy_inlinetype_check(src, tmp, stub, false, (flags & LIR_OpArrayCopy::src_null_check));
2471 }
2472
2473 if (flags & LIR_OpArrayCopy::dst_inlinetype_check) {
2474 arraycopy_inlinetype_check(dst, tmp, stub, true, (flags & LIR_OpArrayCopy::dst_null_check));
2475 }
2476
2477 assert(default_type != nullptr && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2478
2479 int elem_size = type2aelembytes(basic_type);
2480 int scale = exact_log2(elem_size);
2481
2482 Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2483 Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2484 Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2485 Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2486
2487 // test for null
2488 if (flags & LIR_OpArrayCopy::src_null_check) {
2489 __ cbz(src, *stub->entry());
2490 }
2491 if (flags & LIR_OpArrayCopy::dst_null_check) {
2492 __ cbz(dst, *stub->entry());
2493 }
2494
2495 // If the compiler was not able to prove that exact type of the source or the destination
2496 // of the arraycopy is an array type, check at runtime if the source or the destination is
3044 __ verify_klass_ptr(tmp);
3045 #endif
3046 } else {
3047 assert(ciTypeEntries::valid_ciklass(current_klass) != nullptr &&
3048 ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3049
3050 __ ldr(tmp, mdo_addr);
3051 __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
3052
3053 __ orr(tmp, tmp, TypeEntries::type_unknown);
3054 __ str(tmp, mdo_addr);
3055 // FIXME: Write barrier needed here?
3056 }
3057 }
3058
3059 __ bind(next);
3060 }
3061 COMMENT("} emit_profile_type");
3062 }
3063
3064 void LIR_Assembler::emit_profile_inline_type(LIR_OpProfileInlineType* op) {
3065 Register obj = op->obj()->as_register();
3066 Register tmp = op->tmp()->as_pointer_register();
3067 bool not_null = op->not_null();
3068 int flag = op->flag();
3069
3070 Label not_inline_type;
3071 if (!not_null) {
3072 __ cbz(obj, not_inline_type);
3073 }
3074
3075 __ test_oop_is_not_inline_type(obj, tmp, not_inline_type);
3076
3077 Address mdo_addr = as_Address(op->mdp()->as_address_ptr(), rscratch2);
3078 __ ldrb(rscratch1, mdo_addr);
3079 __ orr(rscratch1, rscratch1, flag);
3080 __ strb(rscratch1, mdo_addr);
3081
3082 __ bind(not_inline_type);
3083 }
3084
3085 void LIR_Assembler::align_backward_branch_target() {
3086 }
3087
3088
3089 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3090 // tmp must be unused
3091 assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
3092
3093 if (left->is_single_cpu()) {
3094 assert(dest->is_single_cpu(), "expect single result reg");
3095 __ negw(dest->as_register(), left->as_register());
3096 } else if (left->is_double_cpu()) {
3097 assert(dest->is_double_cpu(), "expect double result reg");
3098 __ neg(dest->as_register_lo(), left->as_register_lo());
3099 } else if (left->is_single_fpu()) {
3100 assert(dest->is_single_fpu(), "expect single float result reg");
3101 __ fnegs(dest->as_float_reg(), left->as_float_reg());
3102 } else {
3103 assert(left->is_double_fpu(), "expect double float operand reg");
3204 void LIR_Assembler::membar_loadload() {
3205 __ membar(Assembler::LoadLoad);
3206 }
3207
3208 void LIR_Assembler::membar_storestore() {
3209 __ membar(MacroAssembler::StoreStore);
3210 }
3211
3212 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
3213
3214 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3215
3216 void LIR_Assembler::on_spin_wait() {
3217 __ spin_wait();
3218 }
3219
3220 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3221 __ mov(result_reg->as_register(), rthread);
3222 }
3223
3224 void LIR_Assembler::check_orig_pc() {
3225 __ ldr(rscratch2, frame_map()->address_for_orig_pc_addr());
3226 __ cmp(rscratch2, (u1)NULL_WORD);
3227 }
3228
3229 void LIR_Assembler::peephole(LIR_List *lir) {
3230 #if 0
3231 if (tableswitch_count >= max_tableswitches)
3232 return;
3233
3234 /*
3235 This finite-state automaton recognizes sequences of compare-and-
3236 branch instructions. We will turn them into a tableswitch. You
3237 could argue that C1 really shouldn't be doing this sort of
3238 optimization, but without it the code is really horrible.
3239 */
3240
3241 enum { start_s, cmp1_s, beq_s, cmp_s } state;
3242 int first_key, last_key = -2147483648;
3243 int next_key = 0;
3244 int start_insn = -1;
3245 int last_insn = -1;
3246 Register reg = noreg;
3247 LIR_Opr reg_opr;
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