56 g1_asm->g1_write_barrier_pre_c2(masm, obj, pre_val, rthread, tmp1, tmp2, stub);
57 }
58
59 static void write_barrier_post(MacroAssembler* masm,
60 const MachNode* node,
61 Register store_addr,
62 Register new_val,
63 Register tmp1,
64 Register tmp2) {
65 if (!G1BarrierStubC2::needs_post_barrier(node)) {
66 return;
67 }
68 Assembler::InlineSkippedInstructionsCounter skip_counter(masm);
69 G1BarrierSetAssembler* g1_asm = static_cast<G1BarrierSetAssembler*>(BarrierSet::barrier_set()->barrier_set_assembler());
70 bool new_val_may_be_null = G1BarrierStubC2::post_new_val_may_be_null(node);
71 g1_asm->g1_write_barrier_post_c2(masm, store_addr, new_val, rthread, tmp1, tmp2, new_val_may_be_null);
72 }
73
74 %}
75
76 // BEGIN This section of the file is automatically generated. Do not edit --------------
77
78 // This section is generated from g1_aarch64.m4
79
80
81 // This pattern is generated automatically from g1_aarch64.m4.
82 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
83 instruct g1StoreP(indirect mem, iRegP src, iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, rFlagsReg cr)
84 %{
85 predicate(UseG1GC && !needs_releasing_store(n) && n->as_Store()->barrier_data() != 0);
86 match(Set mem (StoreP mem src));
87 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
88 ins_cost(INSN_COST);
89 format %{ "str $src, $mem\t# ptr" %}
90 ins_encode %{
91 write_barrier_pre(masm, this,
92 $mem$$Register /* obj */,
93 $tmp1$$Register /* pre_val */,
94 $tmp2$$Register /* tmp1 */,
95 $tmp3$$Register /* tmp2 */,
|
56 g1_asm->g1_write_barrier_pre_c2(masm, obj, pre_val, rthread, tmp1, tmp2, stub);
57 }
58
59 static void write_barrier_post(MacroAssembler* masm,
60 const MachNode* node,
61 Register store_addr,
62 Register new_val,
63 Register tmp1,
64 Register tmp2) {
65 if (!G1BarrierStubC2::needs_post_barrier(node)) {
66 return;
67 }
68 Assembler::InlineSkippedInstructionsCounter skip_counter(masm);
69 G1BarrierSetAssembler* g1_asm = static_cast<G1BarrierSetAssembler*>(BarrierSet::barrier_set()->barrier_set_assembler());
70 bool new_val_may_be_null = G1BarrierStubC2::post_new_val_may_be_null(node);
71 g1_asm->g1_write_barrier_post_c2(masm, store_addr, new_val, rthread, tmp1, tmp2, new_val_may_be_null);
72 }
73
74 %}
75
76 // TODO 8350865 (same applies to g1StoreLSpecialTwoOops)
77 // - Can we use an unbound register for src?
78 // - Do no set/overwrite barrier data here, also handle G1C2BarrierPostNotNull
79 // - Is the zero-extend really required in all the places?
80 // - Move this into the .m4?
81 instruct g1StoreLSpecialOneOop(indirect mem, iRegL_R11 src, immI off, iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4, rFlagsReg cr)
82 %{
83 predicate(UseG1GC);
84 match(Set mem (StoreLSpecial mem (Binary src off)));
85 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, KILL cr);
86 ins_cost(INSN_COST);
87 format %{ "str $src, $mem\t# g1StoreLSpecialOneOop" %}
88 ins_encode %{
89 ((MachNode*)this)->set_barrier_data(G1C2BarrierPre | G1C2BarrierPost);
90
91 // Adjust address to point to narrow oop
92 __ add($tmp4$$Register, $mem$$Register, $off$$constant);
93 write_barrier_pre(masm, this,
94 $tmp4$$Register /* obj */,
95 $tmp1$$Register /* pre_val */,
96 $tmp2$$Register /* tmp1 */,
97 $tmp3$$Register /* tmp2 */);
98
99 __ str($src$$Register, $mem$$Register);
100
101 // Shift long value to extract the narrow oop field value and zero-extend it
102 __ lsr($src$$Register, $src$$Register, $off$$constant << LogBitsPerByte);
103 __ ubfm($src$$Register, $src$$Register, 0, 31);
104
105 write_barrier_post(masm, this,
106 $tmp4$$Register /* store_addr */,
107 $src$$Register /* new_val */,
108 $tmp2$$Register /* tmp1 */,
109 $tmp3$$Register /* tmp2 */);
110 %}
111 ins_pipe(istore_reg_mem);
112 %}
113
114 instruct g1StoreLSpecialTwoOops(indirect mem, iRegL_R11 src, iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, iRegPNoSp tmp4, rFlagsReg cr)
115 %{
116 predicate(UseG1GC);
117 match(Set mem (StoreLSpecial mem src));
118 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, KILL cr);
119 ins_cost(INSN_COST);
120 format %{ "str $src, $mem\t# g1StoreLSpecialTwoOops" %}
121 ins_encode %{
122 ((MachNode*)this)->set_barrier_data(G1C2BarrierPre | G1C2BarrierPost);
123
124 write_barrier_pre(masm, this,
125 $mem$$Register /* obj */,
126 $tmp1$$Register /* pre_val */,
127 $tmp2$$Register /* tmp1 */,
128 $tmp3$$Register /* tmp2 */,
129 RegSet::of($mem$$Register, $src$$Register) /* preserve */);
130 // Adjust address to point to the second narrow oop in the long value
131 __ add($tmp4$$Register, $mem$$Register, 4);
132 write_barrier_pre(masm, this,
133 $tmp4$$Register /* obj */,
134 $tmp1$$Register /* pre_val */,
135 $tmp2$$Register /* tmp1 */,
136 $tmp3$$Register /* tmp2 */,
137 RegSet::of($mem$$Register, $src$$Register, $tmp4$$Register) /* preserve */);
138
139 __ str($src$$Register, $mem$$Register);
140
141 // Zero-extend first narrow oop to long
142 __ ubfm($tmp1$$Register, $src$$Register, 0, 31);
143
144 // Shift long value to extract the second narrow oop field value
145 __ lsr($src$$Register, $src$$Register, 32);
146 write_barrier_post(masm, this,
147 $mem$$Register /* store_addr */,
148 $tmp1$$Register /* new_val */,
149 $tmp2$$Register /* tmp1 */,
150 $tmp3$$Register /* tmp2 */);
151 write_barrier_post(masm, this,
152 $tmp4$$Register /* store_addr */,
153 $src$$Register /* new_val */,
154 $tmp2$$Register /* tmp1 */,
155 $tmp3$$Register /* tmp2 */);
156 %}
157 ins_pipe(istore_reg_mem);
158 %}
159
160
161 // BEGIN This section of the file is automatically generated. Do not edit --------------
162
163 // This section is generated from g1_aarch64.m4
164
165
166 // This pattern is generated automatically from g1_aarch64.m4.
167 // DO NOT EDIT ANYTHING IN THIS SECTION OF THE FILE
168 instruct g1StoreP(indirect mem, iRegP src, iRegPNoSp tmp1, iRegPNoSp tmp2, iRegPNoSp tmp3, rFlagsReg cr)
169 %{
170 predicate(UseG1GC && !needs_releasing_store(n) && n->as_Store()->barrier_data() != 0);
171 match(Set mem (StoreP mem src));
172 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, KILL cr);
173 ins_cost(INSN_COST);
174 format %{ "str $src, $mem\t# ptr" %}
175 ins_encode %{
176 write_barrier_pre(masm, this,
177 $mem$$Register /* obj */,
178 $tmp1$$Register /* pre_val */,
179 $tmp2$$Register /* tmp1 */,
180 $tmp3$$Register /* tmp2 */,
|