12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "asm/assembler.hpp"
30 #include "asm/assembler.inline.hpp"
31 #include "ci/ciEnv.hpp"
32 #include "compiler/compileTask.hpp"
33 #include "compiler/disassembler.hpp"
34 #include "compiler/oopMap.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/barrierSetAssembler.hpp"
37 #include "gc/shared/cardTableBarrierSet.hpp"
38 #include "gc/shared/cardTable.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/tlab_globals.hpp"
41 #include "interpreter/bytecodeHistogram.hpp"
42 #include "interpreter/interpreter.hpp"
43 #include "jvm.h"
44 #include "memory/resourceArea.hpp"
45 #include "memory/universe.hpp"
46 #include "nativeInst_aarch64.hpp"
47 #include "oops/accessDecorators.hpp"
48 #include "oops/compressedOops.inline.hpp"
49 #include "oops/klass.inline.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/icache.hpp"
52 #include "runtime/interfaceSupport.inline.hpp"
53 #include "runtime/javaThread.hpp"
54 #include "runtime/jniHandles.inline.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/powerOfTwo.hpp"
58 #ifdef COMPILER1
59 #include "c1/c1_LIRAssembler.hpp"
60 #endif
61 #ifdef COMPILER2
62 #include "oops/oop.hpp"
63 #include "opto/compile.hpp"
64 #include "opto/node.hpp"
65 #include "opto/output.hpp"
66 #endif
67
68 #ifdef PRODUCT
69 #define BLOCK_COMMENT(str) /* nothing */
70 #else
71 #define BLOCK_COMMENT(str) block_comment(str)
72 #endif
73 #define STOP(str) stop(str);
74 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
75
76 #ifdef ASSERT
77 extern "C" void disnm(intptr_t p);
1095 while (offset() % modulus != 0) nop();
1096 }
1097
1098 void MacroAssembler::post_call_nop() {
1099 if (!Continuations::enabled()) {
1100 return;
1101 }
1102 InstructionMark im(this);
1103 relocate(post_call_nop_Relocation::spec());
1104 nop();
1105 movk(zr, 0);
1106 movk(zr, 0);
1107 }
1108
1109 // these are no-ops overridden by InterpreterMacroAssembler
1110
1111 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1112
1113 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1114
1115 // Look up the method for a megamorphic invokeinterface call.
1116 // The target method is determined by <intf_klass, itable_index>.
1117 // The receiver klass is in recv_klass.
1118 // On success, the result will be in method_result, and execution falls through.
1119 // On failure, execution transfers to the given label.
1120 void MacroAssembler::lookup_interface_method(Register recv_klass,
1121 Register intf_klass,
1122 RegisterOrConstant itable_index,
1123 Register method_result,
1124 Register scan_temp,
1125 Label& L_no_such_interface,
1126 bool return_method) {
1127 assert_different_registers(recv_klass, intf_klass, scan_temp);
1128 assert_different_registers(method_result, intf_klass, scan_temp);
1129 assert(recv_klass != method_result || !return_method,
1130 "recv_klass can be destroyed when method isn't needed");
1131 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1132 "caller must use same register for non-constant itable index as for method");
1133
1134 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1445 ldrb(scratch, Address(klass, InstanceKlass::init_state_offset()));
1446 subs(zr, scratch, InstanceKlass::fully_initialized);
1447 br(Assembler::EQ, *L_fast_path);
1448
1449 // Fast path check: current thread is initializer thread
1450 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
1451 cmp(rthread, scratch);
1452
1453 if (L_slow_path == &L_fallthrough) {
1454 br(Assembler::EQ, *L_fast_path);
1455 bind(*L_slow_path);
1456 } else if (L_fast_path == &L_fallthrough) {
1457 br(Assembler::NE, *L_slow_path);
1458 bind(*L_fast_path);
1459 } else {
1460 Unimplemented();
1461 }
1462 }
1463
1464 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
1465 if (!VerifyOops) return;
1466
1467 // Pass register number to verify_oop_subroutine
1468 const char* b = NULL;
1469 {
1470 ResourceMark rm;
1471 stringStream ss;
1472 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
1473 b = code_string(ss.as_string());
1474 }
1475 BLOCK_COMMENT("verify_oop {");
1476
1477 strip_return_address(); // This might happen within a stack frame.
1478 protect_return_address();
1479 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1480 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1481
1482 mov(r0, reg);
1483 movptr(rscratch1, (uintptr_t)(address)b);
1484
1485 // call indirectly to solve generation ordering problem
1486 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1487 ldr(rscratch2, Address(rscratch2));
1488 blr(rscratch2);
1489
1490 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1491 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1492 authenticate_return_address();
1493
1494 BLOCK_COMMENT("} verify_oop");
1495 }
1496
1497 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
1498 if (!VerifyOops) return;
1499
1500 const char* b = NULL;
1501 {
1502 ResourceMark rm;
1503 stringStream ss;
1504 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
1505 b = code_string(ss.as_string());
1506 }
1507 BLOCK_COMMENT("verify_oop_addr {");
1508
1509 strip_return_address(); // This might happen within a stack frame.
1510 protect_return_address();
1511 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1512 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1513
1514 // addr may contain sp so we will have to adjust it based on the
1515 // pushes that we just did.
1516 if (addr.uses(sp)) {
1517 lea(r0, addr);
1518 ldr(r0, Address(r0, 4 * wordSize));
1560 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1561
1562 mov(rscratch1, entry_point);
1563 blr(rscratch1);
1564 if (retaddr)
1565 bind(*retaddr);
1566
1567 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1568 }
1569
1570 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1571 call_VM_leaf_base(entry_point, number_of_arguments);
1572 }
1573
1574 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1575 pass_arg0(this, arg_0);
1576 call_VM_leaf_base(entry_point, 1);
1577 }
1578
1579 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1580 pass_arg0(this, arg_0);
1581 pass_arg1(this, arg_1);
1582 call_VM_leaf_base(entry_point, 2);
1583 }
1584
1585 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1586 Register arg_1, Register arg_2) {
1587 pass_arg0(this, arg_0);
1588 pass_arg1(this, arg_1);
1589 pass_arg2(this, arg_2);
1590 call_VM_leaf_base(entry_point, 3);
1591 }
1592
1593 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1594 pass_arg0(this, arg_0);
1595 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1596 }
1597
1598 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1599
1600 assert(arg_0 != c_rarg1, "smashed arg");
1601 pass_arg1(this, arg_1);
1602 pass_arg0(this, arg_0);
1603 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1604 }
1605
1606 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1607 assert(arg_0 != c_rarg2, "smashed arg");
1608 assert(arg_1 != c_rarg2, "smashed arg");
1609 pass_arg2(this, arg_2);
1610 assert(arg_0 != c_rarg1, "smashed arg");
1611 pass_arg1(this, arg_1);
1612 pass_arg0(this, arg_0);
1622 assert(arg_1 != c_rarg2, "smashed arg");
1623 pass_arg2(this, arg_2);
1624 assert(arg_0 != c_rarg1, "smashed arg");
1625 pass_arg1(this, arg_1);
1626 pass_arg0(this, arg_0);
1627 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1628 }
1629
1630 void MacroAssembler::null_check(Register reg, int offset) {
1631 if (needs_explicit_null_check(offset)) {
1632 // provoke OS NULL exception if reg = NULL by
1633 // accessing M[reg] w/o changing any registers
1634 // NOTE: this is plenty to provoke a segv
1635 ldr(zr, Address(reg));
1636 } else {
1637 // nothing to do, (later) access of M[reg + offset]
1638 // will provoke OS NULL exception if reg = NULL
1639 }
1640 }
1641
1642 // MacroAssembler protected routines needed to implement
1643 // public methods
1644
1645 void MacroAssembler::mov(Register r, Address dest) {
1646 code_section()->relocate(pc(), dest.rspec());
1647 uint64_t imm64 = (uint64_t)dest.target();
1648 movptr(r, imm64);
1649 }
1650
1651 // Move a constant pointer into r. In AArch64 mode the virtual
1652 // address space is 48 bits in size, so we only need three
1653 // instructions to create a patchable instruction sequence that can
1654 // reach anywhere.
1655 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1656 #ifndef PRODUCT
1657 {
1658 char buffer[64];
1659 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
1660 block_comment(buffer);
1661 }
4010 adrp(rscratch1, src2, offset);
4011 ldr(rscratch1, Address(rscratch1, offset));
4012 cmp(src1, rscratch1);
4013 }
4014
4015 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4016 cmp(obj1, obj2);
4017 }
4018
4019 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4020 load_method_holder(rresult, rmethod);
4021 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4022 }
4023
4024 void MacroAssembler::load_method_holder(Register holder, Register method) {
4025 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
4026 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
4027 ldr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
4028 }
4029
4030 void MacroAssembler::load_klass(Register dst, Register src) {
4031 if (UseCompressedClassPointers) {
4032 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4033 decode_klass_not_null(dst);
4034 } else {
4035 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4036 }
4037 }
4038
4039 // ((OopHandle)result).resolve();
4040 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
4041 // OopHandle::resolve is an indirection.
4042 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
4043 }
4044
4045 // ((WeakHandle)result).resolve();
4046 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
4047 assert_different_registers(result, tmp1, tmp2);
4048 Label resolved;
4049
4068
4069 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
4070 if (UseCompressedClassPointers) {
4071 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4072 if (CompressedKlassPointers::base() == NULL) {
4073 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
4074 return;
4075 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
4076 && CompressedKlassPointers::shift() == 0) {
4077 // Only the bottom 32 bits matter
4078 cmpw(trial_klass, tmp);
4079 return;
4080 }
4081 decode_klass_not_null(tmp);
4082 } else {
4083 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4084 }
4085 cmp(trial_klass, tmp);
4086 }
4087
4088 void MacroAssembler::store_klass(Register dst, Register src) {
4089 // FIXME: Should this be a store release? concurrent gcs assumes
4090 // klass length is valid if klass field is not null.
4091 if (UseCompressedClassPointers) {
4092 encode_klass_not_null(src);
4093 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4094 } else {
4095 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4096 }
4097 }
4098
4099 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4100 if (UseCompressedClassPointers) {
4101 // Store to klass gap in destination
4102 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
4103 }
4104 }
4105
4106 // Algorithm must match CompressedOops::encode.
4107 void MacroAssembler::encode_heap_oop(Register d, Register s) {
4392 if (as_raw) {
4393 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
4394 } else {
4395 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
4396 }
4397 }
4398
4399 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
4400 Address dst, Register val,
4401 Register tmp1, Register tmp2, Register tmp3) {
4402 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4403 decorators = AccessInternal::decorator_fixup(decorators, type);
4404 bool as_raw = (decorators & AS_RAW) != 0;
4405 if (as_raw) {
4406 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
4407 } else {
4408 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
4409 }
4410 }
4411
4412 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
4413 Register tmp2, DecoratorSet decorators) {
4414 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
4415 }
4416
4417 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4418 Register tmp2, DecoratorSet decorators) {
4419 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
4420 }
4421
4422 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
4423 Register tmp2, Register tmp3, DecoratorSet decorators) {
4424 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
4425 }
4426
4427 // Used for storing NULLs.
4428 void MacroAssembler::store_heap_oop_null(Address dst) {
4429 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
4430 }
4431
4468 oop_index = oop_recorder()->allocate_metadata_index(obj);
4469 } else {
4470 oop_index = oop_recorder()->find_index(obj);
4471 }
4472 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
4473 mov(dst, Address((address)obj, rspec));
4474 }
4475
4476 Address MacroAssembler::constant_oop_address(jobject obj) {
4477 #ifdef ASSERT
4478 {
4479 ThreadInVMfromUnknown tiv;
4480 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
4481 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
4482 }
4483 #endif
4484 int oop_index = oop_recorder()->find_index(obj);
4485 return Address((address)obj, oop_Relocation::spec(oop_index));
4486 }
4487
4488 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4489 void MacroAssembler::tlab_allocate(Register obj,
4490 Register var_size_in_bytes,
4491 int con_size_in_bytes,
4492 Register t1,
4493 Register t2,
4494 Label& slow_case) {
4495 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4496 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4497 }
4498
4499 void MacroAssembler::verify_tlab() {
4500 #ifdef ASSERT
4501 if (UseTLAB && VerifyOops) {
4502 Label next, ok;
4503
4504 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
4505
4506 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4507 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
4508 cmp(rscratch2, rscratch1);
4509 br(Assembler::HS, next);
4510 STOP("assert(top >= start)");
4511 should_not_reach_here();
4512
4513 bind(next);
4514 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
4515 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4516 cmp(rscratch2, rscratch1);
4517 br(Assembler::HS, ok);
4518 STOP("assert(top <= end)");
4519 should_not_reach_here();
4520
4521 bind(ok);
4522 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
4523 }
4524 #endif
4525 }
4526
4527 // Writes to stack successive pages until offset reached to check for
4528 // stack overflow + shadow pages. This clobbers tmp.
4529 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
4530 assert_different_registers(tmp, size, rscratch1);
4531 mov(tmp, sp);
4532 // Bang stack for total size given plus shadow page size.
4533 // Bang one page at a time because large size can bang beyond yellow and
4534 // red zones.
4535 Label loop;
4536 mov(rscratch1, os::vm_page_size());
4537 bind(loop);
4538 lea(tmp, Address(tmp, -os::vm_page_size()));
4539 subsw(size, size, rscratch1);
4540 str(size, Address(tmp));
4541 br(Assembler::GT, loop);
4542
4543 // Bang down shadow pages too.
4544 // At this point, (tmp-0) is the last address touched, so don't
4545 // touch it again. (It was touched as (tmp-pagesize) but then tmp
4546 // was post-decremented.) Skip this address by starting at i=1, and
4632 }
4633
4634 void MacroAssembler::remove_frame(int framesize) {
4635 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
4636 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
4637 if (framesize < ((1 << 9) + 2 * wordSize)) {
4638 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4639 add(sp, sp, framesize);
4640 } else {
4641 if (framesize < ((1 << 12) + 2 * wordSize))
4642 add(sp, sp, framesize - 2 * wordSize);
4643 else {
4644 mov(rscratch1, framesize - 2 * wordSize);
4645 add(sp, sp, rscratch1);
4646 }
4647 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
4648 }
4649 authenticate_return_address();
4650 }
4651
4652
4653 // This method counts leading positive bytes (highest bit not set) in provided byte array
4654 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
4655 // Simple and most common case of aligned small array which is not at the
4656 // end of memory page is placed here. All other cases are in stub.
4657 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
4658 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
4659 assert_different_registers(ary1, len, result);
4660
4661 mov(result, len);
4662 cmpw(len, 0);
4663 br(LE, DONE);
4664 cmpw(len, 4 * wordSize);
4665 br(GE, STUB_LONG); // size > 32 then go to stub
4666
4667 int shift = 64 - exact_log2(os::vm_page_size());
4668 lsl(rscratch1, ary1, shift);
4669 mov(rscratch2, (size_t)(4 * wordSize) << shift);
4670 adds(rscratch2, rscratch1, rscratch2); // At end of page?
4671 br(CS, STUB); // at the end of page then go to stub
5540 // On other systems, the helper is a usual C function.
5541 //
5542 void MacroAssembler::get_thread(Register dst) {
5543 RegSet saved_regs =
5544 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
5545 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
5546
5547 protect_return_address();
5548 push(saved_regs, sp);
5549
5550 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
5551 blr(lr);
5552 if (dst != c_rarg0) {
5553 mov(dst, c_rarg0);
5554 }
5555
5556 pop(saved_regs, sp);
5557 authenticate_return_address();
5558 }
5559
5560 void MacroAssembler::cache_wb(Address line) {
5561 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
5562 assert(line.index() == noreg, "index should be noreg");
5563 assert(line.offset() == 0, "offset should be 0");
5564 // would like to assert this
5565 // assert(line._ext.shift == 0, "shift should be zero");
5566 if (VM_Version::supports_dcpop()) {
5567 // writeback using clear virtual address to point of persistence
5568 dc(Assembler::CVAP, line.base());
5569 } else {
5570 // no need to generate anything as Unsafe.writebackMemory should
5571 // never invoke this stub
5572 }
5573 }
5574
5575 void MacroAssembler::cache_wbsync(bool is_pre) {
5576 // we only need a barrier post sync
5577 if (!is_pre) {
5578 membar(Assembler::AnyAny);
5579 }
|
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "asm/assembler.hpp"
30 #include "asm/assembler.inline.hpp"
31 #include "ci/ciEnv.hpp"
32 #include "ci/ciInlineKlass.hpp"
33 #include "compiler/compileTask.hpp"
34 #include "compiler/disassembler.hpp"
35 #include "compiler/oopMap.hpp"
36 #include "gc/shared/barrierSet.hpp"
37 #include "gc/shared/barrierSetAssembler.hpp"
38 #include "gc/shared/cardTableBarrierSet.hpp"
39 #include "gc/shared/cardTable.hpp"
40 #include "gc/shared/collectedHeap.hpp"
41 #include "gc/shared/tlab_globals.hpp"
42 #include "interpreter/bytecodeHistogram.hpp"
43 #include "interpreter/interpreter.hpp"
44 #include "jvm.h"
45 #include "memory/resourceArea.hpp"
46 #include "memory/universe.hpp"
47 #include "nativeInst_aarch64.hpp"
48 #include "oops/accessDecorators.hpp"
49 #include "oops/compressedOops.inline.hpp"
50 #include "oops/klass.inline.hpp"
51 #include "runtime/continuation.hpp"
52 #include "runtime/icache.hpp"
53 #include "runtime/interfaceSupport.inline.hpp"
54 #include "runtime/javaThread.hpp"
55 #include "runtime/jniHandles.inline.hpp"
56 #include "runtime/sharedRuntime.hpp"
57 #include "runtime/signature_cc.hpp"
58 #include "runtime/stubRoutines.hpp"
59 #include "utilities/powerOfTwo.hpp"
60 #include "vmreg_aarch64.inline.hpp"
61 #ifdef COMPILER1
62 #include "c1/c1_LIRAssembler.hpp"
63 #endif
64 #ifdef COMPILER2
65 #include "oops/oop.hpp"
66 #include "opto/compile.hpp"
67 #include "opto/node.hpp"
68 #include "opto/output.hpp"
69 #endif
70
71 #ifdef PRODUCT
72 #define BLOCK_COMMENT(str) /* nothing */
73 #else
74 #define BLOCK_COMMENT(str) block_comment(str)
75 #endif
76 #define STOP(str) stop(str);
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
79 #ifdef ASSERT
80 extern "C" void disnm(intptr_t p);
1098 while (offset() % modulus != 0) nop();
1099 }
1100
1101 void MacroAssembler::post_call_nop() {
1102 if (!Continuations::enabled()) {
1103 return;
1104 }
1105 InstructionMark im(this);
1106 relocate(post_call_nop_Relocation::spec());
1107 nop();
1108 movk(zr, 0);
1109 movk(zr, 0);
1110 }
1111
1112 // these are no-ops overridden by InterpreterMacroAssembler
1113
1114 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1115
1116 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1117
1118 void MacroAssembler::get_default_value_oop(Register inline_klass, Register temp_reg, Register obj) {
1119 #ifdef ASSERT
1120 {
1121 Label done_check;
1122 test_klass_is_inline_type(inline_klass, temp_reg, done_check);
1123 stop("get_default_value_oop from non inline type klass");
1124 bind(done_check);
1125 }
1126 #endif
1127 Register offset = temp_reg;
1128 // Getting the offset of the pre-allocated default value
1129 ldr(offset, Address(inline_klass, in_bytes(InstanceKlass::adr_inlineklass_fixed_block_offset())));
1130 ldr(offset, Address(offset, in_bytes(InlineKlass::default_value_offset_offset())));
1131
1132 // Getting the mirror
1133 ldr(obj, Address(inline_klass, in_bytes(Klass::java_mirror_offset())));
1134 resolve_oop_handle(obj, inline_klass, temp_reg);
1135
1136 // Getting the pre-allocated default value from the mirror
1137 Address field(obj, offset);
1138 load_heap_oop(obj, field, temp_reg, rscratch2);
1139 }
1140
1141 void MacroAssembler::get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj) {
1142 #ifdef ASSERT
1143 {
1144 Label done_check;
1145 test_klass_is_empty_inline_type(inline_klass, temp_reg, done_check);
1146 stop("get_empty_value from non-empty inline klass");
1147 bind(done_check);
1148 }
1149 #endif
1150 get_default_value_oop(inline_klass, temp_reg, obj);
1151 }
1152
1153 // Look up the method for a megamorphic invokeinterface call.
1154 // The target method is determined by <intf_klass, itable_index>.
1155 // The receiver klass is in recv_klass.
1156 // On success, the result will be in method_result, and execution falls through.
1157 // On failure, execution transfers to the given label.
1158 void MacroAssembler::lookup_interface_method(Register recv_klass,
1159 Register intf_klass,
1160 RegisterOrConstant itable_index,
1161 Register method_result,
1162 Register scan_temp,
1163 Label& L_no_such_interface,
1164 bool return_method) {
1165 assert_different_registers(recv_klass, intf_klass, scan_temp);
1166 assert_different_registers(method_result, intf_klass, scan_temp);
1167 assert(recv_klass != method_result || !return_method,
1168 "recv_klass can be destroyed when method isn't needed");
1169 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1170 "caller must use same register for non-constant itable index as for method");
1171
1172 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1483 ldrb(scratch, Address(klass, InstanceKlass::init_state_offset()));
1484 subs(zr, scratch, InstanceKlass::fully_initialized);
1485 br(Assembler::EQ, *L_fast_path);
1486
1487 // Fast path check: current thread is initializer thread
1488 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
1489 cmp(rthread, scratch);
1490
1491 if (L_slow_path == &L_fallthrough) {
1492 br(Assembler::EQ, *L_fast_path);
1493 bind(*L_slow_path);
1494 } else if (L_fast_path == &L_fallthrough) {
1495 br(Assembler::NE, *L_slow_path);
1496 bind(*L_fast_path);
1497 } else {
1498 Unimplemented();
1499 }
1500 }
1501
1502 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
1503 if (!VerifyOops || VerifyAdapterSharing) {
1504 // Below address of the code string confuses VerifyAdapterSharing
1505 // because it may differ between otherwise equivalent adapters.
1506 return;
1507 }
1508
1509 // Pass register number to verify_oop_subroutine
1510 const char* b = NULL;
1511 {
1512 ResourceMark rm;
1513 stringStream ss;
1514 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
1515 b = code_string(ss.as_string());
1516 }
1517 BLOCK_COMMENT("verify_oop {");
1518
1519 strip_return_address(); // This might happen within a stack frame.
1520 protect_return_address();
1521 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1522 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1523
1524 mov(r0, reg);
1525 movptr(rscratch1, (uintptr_t)(address)b);
1526
1527 // call indirectly to solve generation ordering problem
1528 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1529 ldr(rscratch2, Address(rscratch2));
1530 blr(rscratch2);
1531
1532 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1533 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1534 authenticate_return_address();
1535
1536 BLOCK_COMMENT("} verify_oop");
1537 }
1538
1539 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
1540 if (!VerifyOops || VerifyAdapterSharing) {
1541 // Below address of the code string confuses VerifyAdapterSharing
1542 // because it may differ between otherwise equivalent adapters.
1543 return;
1544 }
1545
1546 const char* b = NULL;
1547 {
1548 ResourceMark rm;
1549 stringStream ss;
1550 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
1551 b = code_string(ss.as_string());
1552 }
1553 BLOCK_COMMENT("verify_oop_addr {");
1554
1555 strip_return_address(); // This might happen within a stack frame.
1556 protect_return_address();
1557 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1558 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1559
1560 // addr may contain sp so we will have to adjust it based on the
1561 // pushes that we just did.
1562 if (addr.uses(sp)) {
1563 lea(r0, addr);
1564 ldr(r0, Address(r0, 4 * wordSize));
1606 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1607
1608 mov(rscratch1, entry_point);
1609 blr(rscratch1);
1610 if (retaddr)
1611 bind(*retaddr);
1612
1613 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1614 }
1615
1616 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1617 call_VM_leaf_base(entry_point, number_of_arguments);
1618 }
1619
1620 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1621 pass_arg0(this, arg_0);
1622 call_VM_leaf_base(entry_point, 1);
1623 }
1624
1625 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1626 assert_different_registers(arg_1, c_rarg0);
1627 pass_arg0(this, arg_0);
1628 pass_arg1(this, arg_1);
1629 call_VM_leaf_base(entry_point, 2);
1630 }
1631
1632 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1633 Register arg_1, Register arg_2) {
1634 assert_different_registers(arg_1, c_rarg0);
1635 assert_different_registers(arg_2, c_rarg0, c_rarg1);
1636 pass_arg0(this, arg_0);
1637 pass_arg1(this, arg_1);
1638 pass_arg2(this, arg_2);
1639 call_VM_leaf_base(entry_point, 3);
1640 }
1641
1642 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1643 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1644 }
1645
1646 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1647 pass_arg0(this, arg_0);
1648 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1649 }
1650
1651 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1652
1653 assert(arg_0 != c_rarg1, "smashed arg");
1654 pass_arg1(this, arg_1);
1655 pass_arg0(this, arg_0);
1656 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1657 }
1658
1659 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1660 assert(arg_0 != c_rarg2, "smashed arg");
1661 assert(arg_1 != c_rarg2, "smashed arg");
1662 pass_arg2(this, arg_2);
1663 assert(arg_0 != c_rarg1, "smashed arg");
1664 pass_arg1(this, arg_1);
1665 pass_arg0(this, arg_0);
1675 assert(arg_1 != c_rarg2, "smashed arg");
1676 pass_arg2(this, arg_2);
1677 assert(arg_0 != c_rarg1, "smashed arg");
1678 pass_arg1(this, arg_1);
1679 pass_arg0(this, arg_0);
1680 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1681 }
1682
1683 void MacroAssembler::null_check(Register reg, int offset) {
1684 if (needs_explicit_null_check(offset)) {
1685 // provoke OS NULL exception if reg = NULL by
1686 // accessing M[reg] w/o changing any registers
1687 // NOTE: this is plenty to provoke a segv
1688 ldr(zr, Address(reg));
1689 } else {
1690 // nothing to do, (later) access of M[reg + offset]
1691 // will provoke OS NULL exception if reg = NULL
1692 }
1693 }
1694
1695 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
1696 assert_different_registers(markword, rscratch2);
1697 andr(markword, markword, markWord::inline_type_mask_in_place);
1698 mov(rscratch2, markWord::inline_type_pattern);
1699 cmp(markword, rscratch2);
1700 br(Assembler::EQ, is_inline_type);
1701 }
1702
1703 void MacroAssembler::test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type) {
1704 ldrw(temp_reg, Address(klass, Klass::access_flags_offset()));
1705 andr(temp_reg, temp_reg, JVM_ACC_VALUE);
1706 cbnz(temp_reg, is_inline_type);
1707 }
1708
1709 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type) {
1710 assert_different_registers(tmp, rscratch1);
1711 cbz(object, not_inline_type);
1712 const int is_inline_type_mask = markWord::inline_type_pattern;
1713 ldr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
1714 mov(rscratch1, is_inline_type_mask);
1715 andr(tmp, tmp, rscratch1);
1716 cmp(tmp, rscratch1);
1717 br(Assembler::NE, not_inline_type);
1718 }
1719
1720 void MacroAssembler::test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type) {
1721 #ifdef ASSERT
1722 {
1723 Label done_check;
1724 test_klass_is_inline_type(klass, temp_reg, done_check);
1725 stop("test_klass_is_empty_inline_type with non inline type klass");
1726 bind(done_check);
1727 }
1728 #endif
1729 ldrw(temp_reg, Address(klass, InstanceKlass::misc_status_offset()));
1730 andr(temp_reg, temp_reg, InstanceKlassMiscStatus::is_empty_inline_type_value());
1731 cbnz(temp_reg, is_empty_inline_type);
1732 }
1733
1734 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
1735 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
1736 tbnz(flags, ConstantPoolCacheEntry::is_null_free_inline_type_shift, is_null_free_inline_type);
1737 }
1738
1739 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
1740 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
1741 tbz(flags, ConstantPoolCacheEntry::is_null_free_inline_type_shift, not_null_free_inline_type);
1742 }
1743
1744 void MacroAssembler::test_field_is_inlined(Register flags, Register temp_reg, Label& is_flattened) {
1745 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
1746 tbnz(flags, ConstantPoolCacheEntry::is_inlined_shift, is_flattened);
1747 }
1748
1749 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
1750 Label test_mark_word;
1751 // load mark word
1752 ldr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
1753 // check displaced
1754 tst(temp_reg, markWord::unlocked_value);
1755 br(Assembler::NE, test_mark_word);
1756 // slow path use klass prototype
1757 load_prototype_header(temp_reg, oop);
1758
1759 bind(test_mark_word);
1760 andr(temp_reg, temp_reg, test_bit);
1761 if (jmp_set) {
1762 cbnz(temp_reg, jmp_label);
1763 } else {
1764 cbz(temp_reg, jmp_label);
1765 }
1766 }
1767
1768 void MacroAssembler::test_flattened_array_oop(Register oop, Register temp_reg, Label& is_flattened_array) {
1769 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flattened_array);
1770 }
1771
1772 void MacroAssembler::test_non_flattened_array_oop(Register oop, Register temp_reg,
1773 Label&is_non_flattened_array) {
1774 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flattened_array);
1775 }
1776
1777 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array) {
1778 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
1779 }
1780
1781 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
1782 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
1783 }
1784
1785 void MacroAssembler::test_flattened_array_layout(Register lh, Label& is_flattened_array) {
1786 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
1787 br(Assembler::NE, is_flattened_array);
1788 }
1789
1790 void MacroAssembler::test_non_flattened_array_layout(Register lh, Label& is_non_flattened_array) {
1791 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
1792 br(Assembler::EQ, is_non_flattened_array);
1793 }
1794
1795 void MacroAssembler::test_null_free_array_layout(Register lh, Label& is_null_free_array) {
1796 tst(lh, Klass::_lh_null_free_array_bit_inplace);
1797 br(Assembler::NE, is_null_free_array);
1798 }
1799
1800 void MacroAssembler::test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array) {
1801 tst(lh, Klass::_lh_null_free_array_bit_inplace);
1802 br(Assembler::EQ, is_non_null_free_array);
1803 }
1804
1805 // MacroAssembler protected routines needed to implement
1806 // public methods
1807
1808 void MacroAssembler::mov(Register r, Address dest) {
1809 code_section()->relocate(pc(), dest.rspec());
1810 uint64_t imm64 = (uint64_t)dest.target();
1811 movptr(r, imm64);
1812 }
1813
1814 // Move a constant pointer into r. In AArch64 mode the virtual
1815 // address space is 48 bits in size, so we only need three
1816 // instructions to create a patchable instruction sequence that can
1817 // reach anywhere.
1818 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1819 #ifndef PRODUCT
1820 {
1821 char buffer[64];
1822 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
1823 block_comment(buffer);
1824 }
4173 adrp(rscratch1, src2, offset);
4174 ldr(rscratch1, Address(rscratch1, offset));
4175 cmp(src1, rscratch1);
4176 }
4177
4178 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4179 cmp(obj1, obj2);
4180 }
4181
4182 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4183 load_method_holder(rresult, rmethod);
4184 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4185 }
4186
4187 void MacroAssembler::load_method_holder(Register holder, Register method) {
4188 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
4189 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
4190 ldr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
4191 }
4192
4193 void MacroAssembler::load_metadata(Register dst, Register src) {
4194 if (UseCompressedClassPointers) {
4195 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4196 } else {
4197 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4198 }
4199 }
4200
4201 void MacroAssembler::load_klass(Register dst, Register src) {
4202 if (UseCompressedClassPointers) {
4203 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4204 decode_klass_not_null(dst);
4205 } else {
4206 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4207 }
4208 }
4209
4210 // ((OopHandle)result).resolve();
4211 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
4212 // OopHandle::resolve is an indirection.
4213 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
4214 }
4215
4216 // ((WeakHandle)result).resolve();
4217 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
4218 assert_different_registers(result, tmp1, tmp2);
4219 Label resolved;
4220
4239
4240 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
4241 if (UseCompressedClassPointers) {
4242 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4243 if (CompressedKlassPointers::base() == NULL) {
4244 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
4245 return;
4246 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
4247 && CompressedKlassPointers::shift() == 0) {
4248 // Only the bottom 32 bits matter
4249 cmpw(trial_klass, tmp);
4250 return;
4251 }
4252 decode_klass_not_null(tmp);
4253 } else {
4254 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4255 }
4256 cmp(trial_klass, tmp);
4257 }
4258
4259 void MacroAssembler::load_prototype_header(Register dst, Register src) {
4260 load_klass(dst, src);
4261 ldr(dst, Address(dst, Klass::prototype_header_offset()));
4262 }
4263
4264 void MacroAssembler::store_klass(Register dst, Register src) {
4265 // FIXME: Should this be a store release? concurrent gcs assumes
4266 // klass length is valid if klass field is not null.
4267 if (UseCompressedClassPointers) {
4268 encode_klass_not_null(src);
4269 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4270 } else {
4271 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4272 }
4273 }
4274
4275 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4276 if (UseCompressedClassPointers) {
4277 // Store to klass gap in destination
4278 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
4279 }
4280 }
4281
4282 // Algorithm must match CompressedOops::encode.
4283 void MacroAssembler::encode_heap_oop(Register d, Register s) {
4568 if (as_raw) {
4569 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
4570 } else {
4571 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
4572 }
4573 }
4574
4575 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
4576 Address dst, Register val,
4577 Register tmp1, Register tmp2, Register tmp3) {
4578 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4579 decorators = AccessInternal::decorator_fixup(decorators, type);
4580 bool as_raw = (decorators & AS_RAW) != 0;
4581 if (as_raw) {
4582 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
4583 } else {
4584 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
4585 }
4586 }
4587
4588 void MacroAssembler::access_value_copy(DecoratorSet decorators, Register src, Register dst,
4589 Register inline_klass) {
4590 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4591 bs->value_copy(this, decorators, src, dst, inline_klass);
4592 }
4593
4594 void MacroAssembler::first_field_offset(Register inline_klass, Register offset) {
4595 ldr(offset, Address(inline_klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
4596 ldrw(offset, Address(offset, InlineKlass::first_field_offset_offset()));
4597 }
4598
4599 void MacroAssembler::data_for_oop(Register oop, Register data, Register inline_klass) {
4600 // ((address) (void*) o) + vk->first_field_offset();
4601 Register offset = (data == oop) ? rscratch1 : data;
4602 first_field_offset(inline_klass, offset);
4603 if (data == oop) {
4604 add(data, data, offset);
4605 } else {
4606 lea(data, Address(oop, offset));
4607 }
4608 }
4609
4610 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
4611 Register index, Register data) {
4612 assert_different_registers(array, array_klass, index);
4613 assert_different_registers(rscratch1, array, index);
4614
4615 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
4616 ldrw(rscratch1, Address(array_klass, Klass::layout_helper_offset()));
4617
4618 // Klass::layout_helper_log2_element_size(lh)
4619 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
4620 lsr(rscratch1, rscratch1, Klass::_lh_log2_element_size_shift);
4621 andr(rscratch1, rscratch1, Klass::_lh_log2_element_size_mask);
4622 lslv(index, index, rscratch1);
4623
4624 add(data, array, index);
4625 add(data, data, arrayOopDesc::base_offset_in_bytes(T_PRIMITIVE_OBJECT));
4626 }
4627
4628 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
4629 Register tmp2, DecoratorSet decorators) {
4630 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
4631 }
4632
4633 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4634 Register tmp2, DecoratorSet decorators) {
4635 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
4636 }
4637
4638 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
4639 Register tmp2, Register tmp3, DecoratorSet decorators) {
4640 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
4641 }
4642
4643 // Used for storing NULLs.
4644 void MacroAssembler::store_heap_oop_null(Address dst) {
4645 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
4646 }
4647
4684 oop_index = oop_recorder()->allocate_metadata_index(obj);
4685 } else {
4686 oop_index = oop_recorder()->find_index(obj);
4687 }
4688 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
4689 mov(dst, Address((address)obj, rspec));
4690 }
4691
4692 Address MacroAssembler::constant_oop_address(jobject obj) {
4693 #ifdef ASSERT
4694 {
4695 ThreadInVMfromUnknown tiv;
4696 assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
4697 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
4698 }
4699 #endif
4700 int oop_index = oop_recorder()->find_index(obj);
4701 return Address((address)obj, oop_Relocation::spec(oop_index));
4702 }
4703
4704 // Object / value buffer allocation...
4705 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
4706 Register t1, Register t2,
4707 bool clear_fields, Label& alloc_failed)
4708 {
4709 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
4710 Register layout_size = t1;
4711 assert(new_obj == r0, "needs to be r0");
4712 assert_different_registers(klass, new_obj, t1, t2);
4713
4714 // get instance_size in InstanceKlass (scaled to a count of bytes)
4715 ldrw(layout_size, Address(klass, Klass::layout_helper_offset()));
4716 // test to see if it has a finalizer or is malformed in some way
4717 tst(layout_size, Klass::_lh_instance_slow_path_bit);
4718 br(Assembler::NE, slow_case_no_pop);
4719
4720 // Allocate the instance:
4721 // If TLAB is enabled:
4722 // Try to allocate in the TLAB.
4723 // If fails, go to the slow path.
4724 // Initialize the allocation.
4725 // Exit.
4726 //
4727 // Go to slow path.
4728
4729 if (UseTLAB) {
4730 push(klass);
4731 tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case);
4732 if (ZeroTLAB || (!clear_fields)) {
4733 // the fields have been already cleared
4734 b(initialize_header);
4735 } else {
4736 // initialize both the header and fields
4737 b(initialize_object);
4738 }
4739
4740 if (clear_fields) {
4741 // The object is initialized before the header. If the object size is
4742 // zero, go directly to the header initialization.
4743 bind(initialize_object);
4744 subs(layout_size, layout_size, sizeof(oopDesc));
4745 br(Assembler::EQ, initialize_header);
4746
4747 // Initialize topmost object field, divide size by 8, check if odd and
4748 // test if zero.
4749
4750 #ifdef ASSERT
4751 // make sure instance_size was multiple of 8
4752 Label L;
4753 tst(layout_size, 7);
4754 br(Assembler::EQ, L);
4755 stop("object size is not multiple of 8 - adjust this code");
4756 bind(L);
4757 // must be > 0, no extra check needed here
4758 #endif
4759
4760 lsr(layout_size, layout_size, LogBytesPerLong);
4761
4762 // initialize remaining object fields: instance_size was a multiple of 8
4763 {
4764 Label loop;
4765 Register base = t2;
4766
4767 bind(loop);
4768 add(rscratch1, new_obj, layout_size, Assembler::LSL, LogBytesPerLong);
4769 str(zr, Address(rscratch1, sizeof(oopDesc) - 1*oopSize));
4770 subs(layout_size, layout_size, 1);
4771 br(Assembler::NE, loop);
4772 }
4773 } // clear_fields
4774
4775 // initialize object header only.
4776 bind(initialize_header);
4777 pop(klass);
4778 Register mark_word = t2;
4779 ldr(mark_word, Address(klass, Klass::prototype_header_offset()));
4780 str(mark_word, Address(new_obj, oopDesc::mark_offset_in_bytes ()));
4781 store_klass_gap(new_obj, zr); // zero klass gap for compressed oops
4782 mov(t2, klass); // preserve klass
4783 store_klass(new_obj, t2); // src klass reg is potentially compressed
4784
4785 // TODO: Valhalla removed SharedRuntime::dtrace_object_alloc from here ?
4786
4787 b(done);
4788 }
4789
4790 if (UseTLAB) {
4791 bind(slow_case);
4792 pop(klass);
4793 }
4794 bind(slow_case_no_pop);
4795 b(alloc_failed);
4796
4797 bind(done);
4798 }
4799
4800 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4801 void MacroAssembler::tlab_allocate(Register obj,
4802 Register var_size_in_bytes,
4803 int con_size_in_bytes,
4804 Register t1,
4805 Register t2,
4806 Label& slow_case) {
4807 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4808 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4809 }
4810
4811 void MacroAssembler::verify_tlab() {
4812 #ifdef ASSERT
4813 if (UseTLAB && VerifyOops) {
4814 Label next, ok;
4815
4816 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
4817
4818 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4819 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
4820 cmp(rscratch2, rscratch1);
4821 br(Assembler::HS, next);
4822 STOP("assert(top >= start)");
4823 should_not_reach_here();
4824
4825 bind(next);
4826 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
4827 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4828 cmp(rscratch2, rscratch1);
4829 br(Assembler::HS, ok);
4830 STOP("assert(top <= end)");
4831 should_not_reach_here();
4832
4833 bind(ok);
4834 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
4835 }
4836 #endif
4837 }
4838
4839 void MacroAssembler::get_inline_type_field_klass(Register klass, Register index, Register inline_klass) {
4840 ldr(inline_klass, Address(klass, InstanceKlass::inline_type_field_klasses_offset()));
4841 #ifdef ASSERT
4842 {
4843 Label done;
4844 cbnz(inline_klass, done);
4845 stop("get_inline_type_field_klass contains no inline klass");
4846 bind(done);
4847 }
4848 #endif
4849 ldr(inline_klass, Address(inline_klass, index, Address::lsl(3)));
4850 }
4851
4852 // Writes to stack successive pages until offset reached to check for
4853 // stack overflow + shadow pages. This clobbers tmp.
4854 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
4855 assert_different_registers(tmp, size, rscratch1);
4856 mov(tmp, sp);
4857 // Bang stack for total size given plus shadow page size.
4858 // Bang one page at a time because large size can bang beyond yellow and
4859 // red zones.
4860 Label loop;
4861 mov(rscratch1, os::vm_page_size());
4862 bind(loop);
4863 lea(tmp, Address(tmp, -os::vm_page_size()));
4864 subsw(size, size, rscratch1);
4865 str(size, Address(tmp));
4866 br(Assembler::GT, loop);
4867
4868 // Bang down shadow pages too.
4869 // At this point, (tmp-0) is the last address touched, so don't
4870 // touch it again. (It was touched as (tmp-pagesize) but then tmp
4871 // was post-decremented.) Skip this address by starting at i=1, and
4957 }
4958
4959 void MacroAssembler::remove_frame(int framesize) {
4960 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
4961 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
4962 if (framesize < ((1 << 9) + 2 * wordSize)) {
4963 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4964 add(sp, sp, framesize);
4965 } else {
4966 if (framesize < ((1 << 12) + 2 * wordSize))
4967 add(sp, sp, framesize - 2 * wordSize);
4968 else {
4969 mov(rscratch1, framesize - 2 * wordSize);
4970 add(sp, sp, rscratch1);
4971 }
4972 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
4973 }
4974 authenticate_return_address();
4975 }
4976
4977 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
4978 if (needs_stack_repair) {
4979 // Remove the extension of the caller's frame used for inline type unpacking
4980 //
4981 // Right now the stack looks like this:
4982 //
4983 // | Arguments from caller |
4984 // |---------------------------| <-- caller's SP
4985 // | Saved LR #1 |
4986 // | Saved FP #1 |
4987 // |---------------------------|
4988 // | Extension space for |
4989 // | inline arg (un)packing |
4990 // |---------------------------| <-- start of this method's frame
4991 // | Saved LR #2 |
4992 // | Saved FP #2 |
4993 // |---------------------------| <-- FP
4994 // | sp_inc |
4995 // | method locals |
4996 // |---------------------------| <-- SP
4997 //
4998 // There are two copies of FP and LR on the stack. They will be identical
4999 // unless the caller has been deoptimized, in which case LR #1 will be patched
5000 // to point at the deopt blob, and LR #2 will still point into the old method.
5001 //
5002 // The sp_inc stack slot holds the total size of the frame including the
5003 // extension space minus two words for the saved FP and LR.
5004
5005 int sp_inc_offset = initial_framesize - 3 * wordSize; // Immediately below saved LR and FP
5006
5007 ldr(rscratch1, Address(sp, sp_inc_offset));
5008 add(sp, sp, rscratch1);
5009 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5010 } else {
5011 remove_frame(initial_framesize);
5012 }
5013 }
5014
5015 void MacroAssembler::save_stack_increment(int sp_inc, int frame_size) {
5016 int real_frame_size = frame_size + sp_inc;
5017 assert(sp_inc == 0 || sp_inc > 2*wordSize, "invalid sp_inc value");
5018 assert(real_frame_size >= 2*wordSize, "frame size must include FP/LR space");
5019 assert((real_frame_size & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5020
5021 int sp_inc_offset = frame_size - 3 * wordSize; // Immediately below saved LR and FP
5022
5023 // Subtract two words for the saved FP and LR as these will be popped
5024 // separately. See remove_frame above.
5025 mov(rscratch1, real_frame_size - 2*wordSize);
5026 str(rscratch1, Address(sp, sp_inc_offset));
5027 }
5028
5029 // This method counts leading positive bytes (highest bit not set) in provided byte array
5030 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5031 // Simple and most common case of aligned small array which is not at the
5032 // end of memory page is placed here. All other cases are in stub.
5033 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5034 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5035 assert_different_registers(ary1, len, result);
5036
5037 mov(result, len);
5038 cmpw(len, 0);
5039 br(LE, DONE);
5040 cmpw(len, 4 * wordSize);
5041 br(GE, STUB_LONG); // size > 32 then go to stub
5042
5043 int shift = 64 - exact_log2(os::vm_page_size());
5044 lsl(rscratch1, ary1, shift);
5045 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5046 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5047 br(CS, STUB); // at the end of page then go to stub
5916 // On other systems, the helper is a usual C function.
5917 //
5918 void MacroAssembler::get_thread(Register dst) {
5919 RegSet saved_regs =
5920 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
5921 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
5922
5923 protect_return_address();
5924 push(saved_regs, sp);
5925
5926 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
5927 blr(lr);
5928 if (dst != c_rarg0) {
5929 mov(dst, c_rarg0);
5930 }
5931
5932 pop(saved_regs, sp);
5933 authenticate_return_address();
5934 }
5935
5936 #ifdef COMPILER2
5937 // C2 compiled method's prolog code
5938 // Moved here from aarch64.ad to support Valhalla code belows
5939 void MacroAssembler::verified_entry(Compile* C, int sp_inc) {
5940 if (C->clinit_barrier_on_entry()) {
5941 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
5942
5943 Label L_skip_barrier;
5944
5945 mov_metadata(rscratch2, C->method()->holder()->constant_encoding());
5946 clinit_barrier(rscratch2, rscratch1, &L_skip_barrier);
5947 far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
5948 bind(L_skip_barrier);
5949 }
5950
5951 if (C->max_vector_size() > 0) {
5952 reinitialize_ptrue();
5953 }
5954
5955 int bangsize = C->output()->bang_size_in_bytes();
5956 if (C->output()->need_stack_bang(bangsize))
5957 generate_stack_overflow_check(bangsize);
5958
5959 // n.b. frame size includes space for return pc and rfp
5960 const long framesize = C->output()->frame_size_in_bytes();
5961 build_frame(framesize);
5962
5963 if (C->needs_stack_repair()) {
5964 save_stack_increment(sp_inc, framesize);
5965 }
5966
5967 if (VerifyStackAtCalls) {
5968 Unimplemented();
5969 }
5970 }
5971 #endif // COMPILER2
5972
5973 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
5974 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
5975 // An inline type might be returned. If fields are in registers we
5976 // need to allocate an inline type instance and initialize it with
5977 // the value of the fields.
5978 Label skip;
5979 // We only need a new buffered inline type if a new one is not returned
5980 tbz(r0, 0, skip);
5981 int call_offset = -1;
5982
5983 // Be careful not to clobber r1-7 which hold returned fields
5984 // Also do not use callee-saved registers as these may be live in the interpreter
5985 Register tmp1 = r13, tmp2 = r14, klass = r15, r0_preserved = r12;
5986
5987 // The following code is similar to allocate_instance but has some slight differences,
5988 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
5989 // allocating is not necessary if vk != NULL, etc. allocate_instance is not aware of these.
5990 Label slow_case;
5991 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
5992 mov(r0_preserved, r0); // save r0 for slow_case since *_allocate may corrupt it when allocation failed
5993
5994 if (vk != NULL) {
5995 // Called from C1, where the return type is statically known.
5996 movptr(klass, (intptr_t)vk->get_InlineKlass());
5997 jint obj_size = vk->layout_helper();
5998 assert(obj_size != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
5999 if (UseTLAB) {
6000 tlab_allocate(r0, noreg, obj_size, tmp1, tmp2, slow_case);
6001 } else {
6002 b(slow_case);
6003 }
6004 } else {
6005 // Call from interpreter. R0 contains ((the InlineKlass* of the return type) | 0x01)
6006 andr(klass, r0, -2);
6007 ldrw(tmp2, Address(klass, Klass::layout_helper_offset()));
6008 if (UseTLAB) {
6009 tlab_allocate(r0, tmp2, 0, tmp1, tmp2, slow_case);
6010 } else {
6011 b(slow_case);
6012 }
6013 }
6014 if (UseTLAB) {
6015 // 2. Initialize buffered inline instance header
6016 Register buffer_obj = r0;
6017 mov(rscratch1, (intptr_t)markWord::inline_type_prototype().value());
6018 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes()));
6019 store_klass_gap(buffer_obj, zr);
6020 if (vk == NULL) {
6021 // store_klass corrupts klass, so save it for later use (interpreter case only).
6022 mov(tmp1, klass);
6023 }
6024 store_klass(buffer_obj, klass);
6025 // 3. Initialize its fields with an inline class specific handler
6026 if (vk != NULL) {
6027 far_call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6028 } else {
6029 // tmp1 holds klass preserved above
6030 ldr(tmp1, Address(tmp1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
6031 ldr(tmp1, Address(tmp1, InlineKlass::pack_handler_offset()));
6032 blr(tmp1);
6033 }
6034
6035 membar(Assembler::StoreStore);
6036 b(skip);
6037 } else {
6038 // Must have already branched to slow_case above.
6039 DEBUG_ONLY(should_not_reach_here());
6040 }
6041 bind(slow_case);
6042 // We failed to allocate a new inline type, fall back to a runtime
6043 // call. Some oop field may be live in some registers but we can't
6044 // tell. That runtime call will take care of preserving them
6045 // across a GC if there's one.
6046 mov(r0, r0_preserved);
6047
6048 if (from_interpreter) {
6049 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6050 } else {
6051 far_call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6052 call_offset = offset();
6053 }
6054 membar(Assembler::StoreStore);
6055
6056 bind(skip);
6057 return call_offset;
6058 }
6059
6060 // Move a value between registers/stack slots and update the reg_state
6061 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6062 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6063 if (reg_state[to->value()] == reg_written) {
6064 return true; // Already written
6065 }
6066
6067 if (from != to && bt != T_VOID) {
6068 if (reg_state[to->value()] == reg_readonly) {
6069 return false; // Not yet writable
6070 }
6071 if (from->is_reg()) {
6072 if (to->is_reg()) {
6073 if (from->is_Register() && to->is_Register()) {
6074 mov(to->as_Register(), from->as_Register());
6075 } else if (from->is_FloatRegister() && to->is_FloatRegister()) {
6076 fmovd(to->as_FloatRegister(), from->as_FloatRegister());
6077 } else {
6078 ShouldNotReachHere();
6079 }
6080 } else {
6081 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
6082 Address to_addr = Address(sp, st_off);
6083 if (from->is_FloatRegister()) {
6084 if (bt == T_DOUBLE) {
6085 strd(from->as_FloatRegister(), to_addr);
6086 } else {
6087 assert(bt == T_FLOAT, "must be float");
6088 strs(from->as_FloatRegister(), to_addr);
6089 }
6090 } else {
6091 str(from->as_Register(), to_addr);
6092 }
6093 }
6094 } else {
6095 Address from_addr = Address(sp, from->reg2stack() * VMRegImpl::stack_slot_size);
6096 if (to->is_reg()) {
6097 if (to->is_FloatRegister()) {
6098 if (bt == T_DOUBLE) {
6099 ldrd(to->as_FloatRegister(), from_addr);
6100 } else {
6101 assert(bt == T_FLOAT, "must be float");
6102 ldrs(to->as_FloatRegister(), from_addr);
6103 }
6104 } else {
6105 ldr(to->as_Register(), from_addr);
6106 }
6107 } else {
6108 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
6109 ldr(rscratch1, from_addr);
6110 str(rscratch1, Address(sp, st_off));
6111 }
6112 }
6113 }
6114
6115 // Update register states
6116 reg_state[from->value()] = reg_writable;
6117 reg_state[to->value()] = reg_written;
6118 return true;
6119 }
6120
6121 // Calculate the extra stack space required for packing or unpacking inline
6122 // args and adjust the stack pointer
6123 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6124 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
6125 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6126 assert(sp_inc > 0, "sanity");
6127
6128 // Save a copy of the FP and LR here for deoptimization patching and frame walking
6129 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6130
6131 // Adjust the stack pointer. This will be repaired on return by MacroAssembler::remove_frame
6132 if (sp_inc < (1 << 9)) {
6133 sub(sp, sp, sp_inc); // Fits in an immediate
6134 } else {
6135 mov(rscratch1, sp_inc);
6136 sub(sp, sp, rscratch1);
6137 }
6138
6139 return sp_inc + 2 * wordSize; // Account for the FP/LR space
6140 }
6141
6142 // Read all fields from an inline type oop and store the values in registers/stack slots
6143 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6144 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6145 RegState reg_state[]) {
6146 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6147 assert(from->is_valid(), "source must be valid");
6148 bool progress = false;
6149 #ifdef ASSERT
6150 const int start_offset = offset();
6151 #endif
6152
6153 Label L_null, L_notNull;
6154 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6155 Register tmp1 = r10;
6156 Register tmp2 = r11;
6157 Register fromReg = noreg;
6158 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
6159 bool done = true;
6160 bool mark_done = true;
6161 VMReg toReg;
6162 BasicType bt;
6163 // Check if argument requires a null check
6164 bool null_check = false;
6165 VMReg nullCheckReg;
6166 while (stream.next(nullCheckReg, bt)) {
6167 if (sig->at(stream.sig_index())._offset == -1) {
6168 null_check = true;
6169 break;
6170 }
6171 }
6172 stream.reset(sig_index, to_index);
6173 while (stream.next(toReg, bt)) {
6174 assert(toReg->is_valid(), "destination must be valid");
6175 int idx = (int)toReg->value();
6176 if (reg_state[idx] == reg_readonly) {
6177 if (idx != from->value()) {
6178 mark_done = false;
6179 }
6180 done = false;
6181 continue;
6182 } else if (reg_state[idx] == reg_written) {
6183 continue;
6184 }
6185 assert(reg_state[idx] == reg_writable, "must be writable");
6186 reg_state[idx] = reg_written;
6187 progress = true;
6188
6189 if (fromReg == noreg) {
6190 if (from->is_reg()) {
6191 fromReg = from->as_Register();
6192 } else {
6193 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size;
6194 ldr(tmp1, Address(sp, st_off));
6195 fromReg = tmp1;
6196 }
6197 if (null_check) {
6198 // Nullable inline type argument, emit null check
6199 cbz(fromReg, L_null);
6200 }
6201 }
6202 int off = sig->at(stream.sig_index())._offset;
6203 if (off == -1) {
6204 assert(null_check, "Missing null check at");
6205 if (toReg->is_stack()) {
6206 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
6207 mov(tmp2, 1);
6208 str(tmp2, Address(sp, st_off));
6209 } else {
6210 mov(toReg->as_Register(), 1);
6211 }
6212 continue;
6213 }
6214 assert(off > 0, "offset in object should be positive");
6215 Address fromAddr = Address(fromReg, off);
6216 if (!toReg->is_FloatRegister()) {
6217 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
6218 if (is_reference_type(bt)) {
6219 load_heap_oop(dst, fromAddr, rscratch1, rscratch2);
6220 } else {
6221 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
6222 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
6223 }
6224 if (toReg->is_stack()) {
6225 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
6226 str(dst, Address(sp, st_off));
6227 }
6228 } else if (bt == T_DOUBLE) {
6229 ldrd(toReg->as_FloatRegister(), fromAddr);
6230 } else {
6231 assert(bt == T_FLOAT, "must be float");
6232 ldrs(toReg->as_FloatRegister(), fromAddr);
6233 }
6234 }
6235 if (progress && null_check) {
6236 if (done) {
6237 b(L_notNull);
6238 bind(L_null);
6239 // Set IsInit field to zero to signal that the argument is null.
6240 // Also set all oop fields to zero to make the GC happy.
6241 stream.reset(sig_index, to_index);
6242 while (stream.next(toReg, bt)) {
6243 if (sig->at(stream.sig_index())._offset == -1 ||
6244 bt == T_OBJECT || bt == T_ARRAY) {
6245 if (toReg->is_stack()) {
6246 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
6247 str(zr, Address(sp, st_off));
6248 } else {
6249 mov(toReg->as_Register(), zr);
6250 }
6251 }
6252 }
6253 bind(L_notNull);
6254 } else {
6255 bind(L_null);
6256 }
6257 }
6258
6259 sig_index = stream.sig_index();
6260 to_index = stream.regs_index();
6261
6262 if (mark_done && reg_state[from->value()] != reg_written) {
6263 // This is okay because no one else will write to that slot
6264 reg_state[from->value()] = reg_writable;
6265 }
6266 from_index--;
6267 assert(progress || (start_offset == offset()), "should not emit code");
6268 return done;
6269 }
6270
6271 // Pack fields back into an inline type oop
6272 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
6273 VMRegPair* from, int from_count, int& from_index, VMReg to,
6274 RegState reg_state[], Register val_array) {
6275 assert(sig->at(sig_index)._bt == T_PRIMITIVE_OBJECT, "should be at end delimiter");
6276 assert(to->is_valid(), "destination must be valid");
6277
6278 if (reg_state[to->value()] == reg_written) {
6279 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6280 return true; // Already written
6281 }
6282
6283 // The GC barrier expanded by store_heap_oop below may call into the
6284 // runtime so use callee-saved registers for any values that need to be
6285 // preserved. The GC barrier assembler should take care of saving the
6286 // Java argument registers.
6287 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
6288 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
6289 Register val_obj_tmp = r21;
6290 Register from_reg_tmp = r22;
6291 Register tmp1 = r14;
6292 Register tmp2 = r13;
6293 Register tmp3 = r12;
6294 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
6295
6296 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
6297
6298 if (reg_state[to->value()] == reg_readonly) {
6299 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
6300 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6301 return false; // Not yet writable
6302 }
6303 val_obj = val_obj_tmp;
6304 }
6305
6306 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_PRIMITIVE_OBJECT);
6307 load_heap_oop(val_obj, Address(val_array, index), tmp1, tmp2);
6308
6309 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
6310 VMReg fromReg;
6311 BasicType bt;
6312 Label L_null;
6313 while (stream.next(fromReg, bt)) {
6314 assert(fromReg->is_valid(), "source must be valid");
6315 reg_state[fromReg->value()] = reg_writable;
6316
6317 int off = sig->at(stream.sig_index())._offset;
6318 if (off == -1) {
6319 // Nullable inline type argument, emit null check
6320 Label L_notNull;
6321 if (fromReg->is_stack()) {
6322 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
6323 ldr(tmp2, Address(sp, ld_off));
6324 cbnz(tmp2, L_notNull);
6325 } else {
6326 cbnz(fromReg->as_Register(), L_notNull);
6327 }
6328 mov(val_obj, 0);
6329 b(L_null);
6330 bind(L_notNull);
6331 continue;
6332 }
6333
6334 assert(off > 0, "offset in object should be positive");
6335 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
6336
6337 // Pack the scalarized field into the value object.
6338 Address dst(val_obj, off);
6339
6340 if (!fromReg->is_FloatRegister()) {
6341 Register src;
6342 if (fromReg->is_stack()) {
6343 src = from_reg_tmp;
6344 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
6345 load_sized_value(src, Address(sp, ld_off), size_in_bytes, /* is_signed */ false);
6346 } else {
6347 src = fromReg->as_Register();
6348 }
6349 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
6350 if (is_reference_type(bt)) {
6351 store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
6352 } else {
6353 store_sized_value(dst, src, size_in_bytes);
6354 }
6355 } else if (bt == T_DOUBLE) {
6356 strd(fromReg->as_FloatRegister(), dst);
6357 } else {
6358 assert(bt == T_FLOAT, "must be float");
6359 strs(fromReg->as_FloatRegister(), dst);
6360 }
6361 }
6362 bind(L_null);
6363 sig_index = stream.sig_index();
6364 from_index = stream.regs_index();
6365
6366 assert(reg_state[to->value()] == reg_writable, "must have already been read");
6367 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6368 assert(success, "to register must be writeable");
6369
6370 return true;
6371 }
6372
6373 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6374 return (reg->is_FloatRegister()) ? v0->as_VMReg() : r14->as_VMReg();
6375 }
6376
6377 void MacroAssembler::cache_wb(Address line) {
6378 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6379 assert(line.index() == noreg, "index should be noreg");
6380 assert(line.offset() == 0, "offset should be 0");
6381 // would like to assert this
6382 // assert(line._ext.shift == 0, "shift should be zero");
6383 if (VM_Version::supports_dcpop()) {
6384 // writeback using clear virtual address to point of persistence
6385 dc(Assembler::CVAP, line.base());
6386 } else {
6387 // no need to generate anything as Unsafe.writebackMemory should
6388 // never invoke this stub
6389 }
6390 }
6391
6392 void MacroAssembler::cache_wbsync(bool is_pre) {
6393 // we only need a barrier post sync
6394 if (!is_pre) {
6395 membar(Assembler::AnyAny);
6396 }
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