1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "ci/ciEnv.hpp"
30 #include "code/compiledIC.hpp"
31 #include "compiler/compileTask.hpp"
32 #include "compiler/disassembler.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "gc/shared/barrierSet.hpp"
35 #include "gc/shared/barrierSetAssembler.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/cardTable.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/tlab_globals.hpp"
40 #include "interpreter/bytecodeHistogram.hpp"
41 #include "interpreter/interpreter.hpp"
42 #include "jvm.h"
43 #include "memory/resourceArea.hpp"
44 #include "memory/universe.hpp"
45 #include "nativeInst_aarch64.hpp"
46 #include "oops/accessDecorators.hpp"
47 #include "oops/compressedKlass.inline.hpp"
48 #include "oops/compressedOops.inline.hpp"
49 #include "oops/klass.inline.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/icache.hpp"
52 #include "runtime/interfaceSupport.inline.hpp"
53 #include "runtime/javaThread.hpp"
54 #include "runtime/jniHandles.inline.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/globalDefinitions.hpp"
58 #include "utilities/powerOfTwo.hpp"
59 #ifdef COMPILER1
60 #include "c1/c1_LIRAssembler.hpp"
61 #endif
62 #ifdef COMPILER2
63 #include "oops/oop.hpp"
64 #include "opto/compile.hpp"
65 #include "opto/node.hpp"
66 #include "opto/output.hpp"
67 #endif
68
69 #include <sys/types.h>
70
71 #ifdef PRODUCT
72 #define BLOCK_COMMENT(str) /* nothing */
73 #else
74 #define BLOCK_COMMENT(str) block_comment(str)
75 #endif
76 #define STOP(str) stop(str);
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
1154 }
1155
1156 void MacroAssembler::post_call_nop() {
1157 if (!Continuations::enabled()) {
1158 return;
1159 }
1160 InstructionMark im(this);
1161 relocate(post_call_nop_Relocation::spec());
1162 InlineSkippedInstructionsCounter skipCounter(this);
1163 nop();
1164 movk(zr, 0);
1165 movk(zr, 0);
1166 }
1167
1168 // these are no-ops overridden by InterpreterMacroAssembler
1169
1170 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1171
1172 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1173
1174 // Look up the method for a megamorphic invokeinterface call.
1175 // The target method is determined by <intf_klass, itable_index>.
1176 // The receiver klass is in recv_klass.
1177 // On success, the result will be in method_result, and execution falls through.
1178 // On failure, execution transfers to the given label.
1179 void MacroAssembler::lookup_interface_method(Register recv_klass,
1180 Register intf_klass,
1181 RegisterOrConstant itable_index,
1182 Register method_result,
1183 Register scan_temp,
1184 Label& L_no_such_interface,
1185 bool return_method) {
1186 assert_different_registers(recv_klass, intf_klass, scan_temp);
1187 assert_different_registers(method_result, intf_klass, scan_temp);
1188 assert(recv_klass != method_result || !return_method,
1189 "recv_klass can be destroyed when method isn't needed");
1190 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1191 "caller must use same register for non-constant itable index as for method");
1192
1193 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
2029 ldarb(scratch, scratch);
2030 subs(zr, scratch, InstanceKlass::fully_initialized);
2031 br(Assembler::EQ, *L_fast_path);
2032
2033 // Fast path check: current thread is initializer thread
2034 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2035 cmp(rthread, scratch);
2036
2037 if (L_slow_path == &L_fallthrough) {
2038 br(Assembler::EQ, *L_fast_path);
2039 bind(*L_slow_path);
2040 } else if (L_fast_path == &L_fallthrough) {
2041 br(Assembler::NE, *L_slow_path);
2042 bind(*L_fast_path);
2043 } else {
2044 Unimplemented();
2045 }
2046 }
2047
2048 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2049 if (!VerifyOops) return;
2050
2051 // Pass register number to verify_oop_subroutine
2052 const char* b = nullptr;
2053 {
2054 ResourceMark rm;
2055 stringStream ss;
2056 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2057 b = code_string(ss.as_string());
2058 }
2059 BLOCK_COMMENT("verify_oop {");
2060
2061 strip_return_address(); // This might happen within a stack frame.
2062 protect_return_address();
2063 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2064 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2065
2066 mov(r0, reg);
2067 movptr(rscratch1, (uintptr_t)(address)b);
2068
2069 // call indirectly to solve generation ordering problem
2070 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2071 ldr(rscratch2, Address(rscratch2));
2072 blr(rscratch2);
2073
2074 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2075 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2076 authenticate_return_address();
2077
2078 BLOCK_COMMENT("} verify_oop");
2079 }
2080
2081 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2082 if (!VerifyOops) return;
2083
2084 const char* b = nullptr;
2085 {
2086 ResourceMark rm;
2087 stringStream ss;
2088 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2089 b = code_string(ss.as_string());
2090 }
2091 BLOCK_COMMENT("verify_oop_addr {");
2092
2093 strip_return_address(); // This might happen within a stack frame.
2094 protect_return_address();
2095 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2096 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2097
2098 // addr may contain sp so we will have to adjust it based on the
2099 // pushes that we just did.
2100 if (addr.uses(sp)) {
2101 lea(r0, addr);
2102 ldr(r0, Address(r0, 4 * wordSize));
2160 call_VM_leaf_base(entry_point, 1);
2161 }
2162
2163 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2164 assert_different_registers(arg_1, c_rarg0);
2165 pass_arg0(this, arg_0);
2166 pass_arg1(this, arg_1);
2167 call_VM_leaf_base(entry_point, 2);
2168 }
2169
2170 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2171 Register arg_1, Register arg_2) {
2172 assert_different_registers(arg_1, c_rarg0);
2173 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2174 pass_arg0(this, arg_0);
2175 pass_arg1(this, arg_1);
2176 pass_arg2(this, arg_2);
2177 call_VM_leaf_base(entry_point, 3);
2178 }
2179
2180 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2181 pass_arg0(this, arg_0);
2182 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2183 }
2184
2185 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2186
2187 assert_different_registers(arg_0, c_rarg1);
2188 pass_arg1(this, arg_1);
2189 pass_arg0(this, arg_0);
2190 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2191 }
2192
2193 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2194 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2195 assert_different_registers(arg_1, c_rarg2);
2196 pass_arg2(this, arg_2);
2197 pass_arg1(this, arg_1);
2198 pass_arg0(this, arg_0);
2199 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2205 assert_different_registers(arg_2, c_rarg3);
2206 pass_arg3(this, arg_3);
2207 pass_arg2(this, arg_2);
2208 pass_arg1(this, arg_1);
2209 pass_arg0(this, arg_0);
2210 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2211 }
2212
2213 void MacroAssembler::null_check(Register reg, int offset) {
2214 if (needs_explicit_null_check(offset)) {
2215 // provoke OS null exception if reg is null by
2216 // accessing M[reg] w/o changing any registers
2217 // NOTE: this is plenty to provoke a segv
2218 ldr(zr, Address(reg));
2219 } else {
2220 // nothing to do, (later) access of M[reg + offset]
2221 // will provoke OS null exception if reg is null
2222 }
2223 }
2224
2225 // MacroAssembler protected routines needed to implement
2226 // public methods
2227
2228 void MacroAssembler::mov(Register r, Address dest) {
2229 code_section()->relocate(pc(), dest.rspec());
2230 uint64_t imm64 = (uint64_t)dest.target();
2231 movptr(r, imm64);
2232 }
2233
2234 // Move a constant pointer into r. In AArch64 mode the virtual
2235 // address space is 48 bits in size, so we only need three
2236 // instructions to create a patchable instruction sequence that can
2237 // reach anywhere.
2238 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2239 #ifndef PRODUCT
2240 {
2241 char buffer[64];
2242 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2243 block_comment(buffer);
2244 }
4992 adrp(rscratch1, src2, offset);
4993 ldr(rscratch1, Address(rscratch1, offset));
4994 cmp(src1, rscratch1);
4995 }
4996
4997 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4998 cmp(obj1, obj2);
4999 }
5000
5001 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5002 load_method_holder(rresult, rmethod);
5003 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5004 }
5005
5006 void MacroAssembler::load_method_holder(Register holder, Register method) {
5007 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
5008 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5009 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5010 }
5011
5012 void MacroAssembler::load_klass(Register dst, Register src) {
5013 if (UseCompressedClassPointers) {
5014 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5015 decode_klass_not_null(dst);
5016 } else {
5017 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5018 }
5019 }
5020
5021 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5022 if (RestoreMXCSROnJNICalls) {
5023 Label OK;
5024 get_fpcr(tmp1);
5025 mov(tmp2, tmp1);
5026 // Set FPCR to the state we need. We do want Round to Nearest. We
5027 // don't want non-IEEE rounding modes or floating-point traps.
5028 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5029 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5030 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5031 eor(tmp2, tmp1, tmp2);
5067
5068 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
5069 if (UseCompressedClassPointers) {
5070 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
5071 if (CompressedKlassPointers::base() == nullptr) {
5072 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
5073 return;
5074 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5075 && CompressedKlassPointers::shift() == 0) {
5076 // Only the bottom 32 bits matter
5077 cmpw(trial_klass, tmp);
5078 return;
5079 }
5080 decode_klass_not_null(tmp);
5081 } else {
5082 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
5083 }
5084 cmp(trial_klass, tmp);
5085 }
5086
5087 void MacroAssembler::store_klass(Register dst, Register src) {
5088 // FIXME: Should this be a store release? concurrent gcs assumes
5089 // klass length is valid if klass field is not null.
5090 if (UseCompressedClassPointers) {
5091 encode_klass_not_null(src);
5092 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5093 } else {
5094 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5095 }
5096 }
5097
5098 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5099 if (UseCompressedClassPointers) {
5100 // Store to klass gap in destination
5101 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5102 }
5103 }
5104
5105 // Algorithm must match CompressedOops::encode.
5106 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5393 if (as_raw) {
5394 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5395 } else {
5396 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5397 }
5398 }
5399
5400 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5401 Address dst, Register val,
5402 Register tmp1, Register tmp2, Register tmp3) {
5403 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5404 decorators = AccessInternal::decorator_fixup(decorators, type);
5405 bool as_raw = (decorators & AS_RAW) != 0;
5406 if (as_raw) {
5407 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5408 } else {
5409 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5410 }
5411 }
5412
5413 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5414 Register tmp2, DecoratorSet decorators) {
5415 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5416 }
5417
5418 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5419 Register tmp2, DecoratorSet decorators) {
5420 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5421 }
5422
5423 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5424 Register tmp2, Register tmp3, DecoratorSet decorators) {
5425 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5426 }
5427
5428 // Used for storing nulls.
5429 void MacroAssembler::store_heap_oop_null(Address dst) {
5430 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5431 }
5432
5469 oop_index = oop_recorder()->allocate_metadata_index(obj);
5470 } else {
5471 oop_index = oop_recorder()->find_index(obj);
5472 }
5473 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5474 mov(dst, Address((address)obj, rspec));
5475 }
5476
5477 Address MacroAssembler::constant_oop_address(jobject obj) {
5478 #ifdef ASSERT
5479 {
5480 ThreadInVMfromUnknown tiv;
5481 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5482 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5483 }
5484 #endif
5485 int oop_index = oop_recorder()->find_index(obj);
5486 return Address((address)obj, oop_Relocation::spec(oop_index));
5487 }
5488
5489 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5490 void MacroAssembler::tlab_allocate(Register obj,
5491 Register var_size_in_bytes,
5492 int con_size_in_bytes,
5493 Register t1,
5494 Register t2,
5495 Label& slow_case) {
5496 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5497 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5498 }
5499
5500 void MacroAssembler::verify_tlab() {
5501 #ifdef ASSERT
5502 if (UseTLAB && VerifyOops) {
5503 Label next, ok;
5504
5505 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5506
5507 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5508 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5509 cmp(rscratch2, rscratch1);
5510 br(Assembler::HS, next);
5511 STOP("assert(top >= start)");
5512 should_not_reach_here();
5513
5514 bind(next);
5515 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5516 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5517 cmp(rscratch2, rscratch1);
5518 br(Assembler::HS, ok);
5519 STOP("assert(top <= end)");
5520 should_not_reach_here();
5521
5522 bind(ok);
5523 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5524 }
5525 #endif
5526 }
5527
5528 // Writes to stack successive pages until offset reached to check for
5529 // stack overflow + shadow pages. This clobbers tmp.
5530 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5531 assert_different_registers(tmp, size, rscratch1);
5532 mov(tmp, sp);
5533 // Bang stack for total size given plus shadow page size.
5534 // Bang one page at a time because large size can bang beyond yellow and
5535 // red zones.
5536 Label loop;
5537 mov(rscratch1, (int)os::vm_page_size());
5538 bind(loop);
5539 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5540 subsw(size, size, rscratch1);
5541 str(size, Address(tmp));
5542 br(Assembler::GT, loop);
5543
5544 // Bang down shadow pages too.
5545 // At this point, (tmp-0) is the last address touched, so don't
5546 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5547 // was post-decremented.) Skip this address by starting at i=1, and
5633 }
5634
5635 void MacroAssembler::remove_frame(int framesize) {
5636 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5637 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5638 if (framesize < ((1 << 9) + 2 * wordSize)) {
5639 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5640 add(sp, sp, framesize);
5641 } else {
5642 if (framesize < ((1 << 12) + 2 * wordSize))
5643 add(sp, sp, framesize - 2 * wordSize);
5644 else {
5645 mov(rscratch1, framesize - 2 * wordSize);
5646 add(sp, sp, rscratch1);
5647 }
5648 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5649 }
5650 authenticate_return_address();
5651 }
5652
5653
5654 // This method counts leading positive bytes (highest bit not set) in provided byte array
5655 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5656 // Simple and most common case of aligned small array which is not at the
5657 // end of memory page is placed here. All other cases are in stub.
5658 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5659 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5660 assert_different_registers(ary1, len, result);
5661
5662 mov(result, len);
5663 cmpw(len, 0);
5664 br(LE, DONE);
5665 cmpw(len, 4 * wordSize);
5666 br(GE, STUB_LONG); // size > 32 then go to stub
5667
5668 int shift = 64 - exact_log2(os::vm_page_size());
5669 lsl(rscratch1, ary1, shift);
5670 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5671 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5672 br(CS, STUB); // at the end of page then go to stub
6546 // On other systems, the helper is a usual C function.
6547 //
6548 void MacroAssembler::get_thread(Register dst) {
6549 RegSet saved_regs =
6550 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6551 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6552
6553 protect_return_address();
6554 push(saved_regs, sp);
6555
6556 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
6557 blr(lr);
6558 if (dst != c_rarg0) {
6559 mov(dst, c_rarg0);
6560 }
6561
6562 pop(saved_regs, sp);
6563 authenticate_return_address();
6564 }
6565
6566 void MacroAssembler::cache_wb(Address line) {
6567 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6568 assert(line.index() == noreg, "index should be noreg");
6569 assert(line.offset() == 0, "offset should be 0");
6570 // would like to assert this
6571 // assert(line._ext.shift == 0, "shift should be zero");
6572 if (VM_Version::supports_dcpop()) {
6573 // writeback using clear virtual address to point of persistence
6574 dc(Assembler::CVAP, line.base());
6575 } else {
6576 // no need to generate anything as Unsafe.writebackMemory should
6577 // never invoke this stub
6578 }
6579 }
6580
6581 void MacroAssembler::cache_wbsync(bool is_pre) {
6582 // we only need a barrier post sync
6583 if (!is_pre) {
6584 membar(Assembler::AnyAny);
6585 }
6944 }
6945
6946 // Check if the lock-stack is full.
6947 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6948 cmpw(top, (unsigned)LockStack::end_offset());
6949 br(Assembler::GE, slow);
6950
6951 // Check for recursion.
6952 subw(t, top, oopSize);
6953 ldr(t, Address(rthread, t));
6954 cmp(obj, t);
6955 br(Assembler::EQ, push);
6956
6957 // Check header for monitor (0b10).
6958 tst(mark, markWord::monitor_value);
6959 br(Assembler::NE, slow);
6960
6961 // Try to lock. Transition lock bits 0b01 => 0b00
6962 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
6963 orr(mark, mark, markWord::unlocked_value);
6964 eor(t, mark, markWord::unlocked_value);
6965 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
6966 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
6967 br(Assembler::NE, slow);
6968
6969 bind(push);
6970 // After successful lock, push object on lock-stack.
6971 str(obj, Address(rthread, top));
6972 addw(top, top, oopSize);
6973 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6974 }
6975
6976 // Implements lightweight-unlocking.
6977 //
6978 // - obj: the object to be unlocked
6979 // - t1, t2, t3: temporary registers
6980 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
6981 void MacroAssembler::lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
6982 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
6983 // cmpxchg clobbers rscratch1.
|
1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "ci/ciEnv.hpp"
30 #include "ci/ciInlineKlass.hpp"
31 #include "code/compiledIC.hpp"
32 #include "compiler/compileTask.hpp"
33 #include "compiler/disassembler.hpp"
34 #include "compiler/oopMap.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/barrierSetAssembler.hpp"
37 #include "gc/shared/cardTableBarrierSet.hpp"
38 #include "gc/shared/cardTable.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/tlab_globals.hpp"
41 #include "interpreter/bytecodeHistogram.hpp"
42 #include "interpreter/interpreter.hpp"
43 #include "jvm.h"
44 #include "memory/resourceArea.hpp"
45 #include "memory/universe.hpp"
46 #include "nativeInst_aarch64.hpp"
47 #include "oops/accessDecorators.hpp"
48 #include "oops/compressedKlass.inline.hpp"
49 #include "oops/compressedOops.inline.hpp"
50 #include "oops/klass.inline.hpp"
51 #include "oops/resolvedFieldEntry.hpp"
52 #include "runtime/continuation.hpp"
53 #include "runtime/icache.hpp"
54 #include "runtime/interfaceSupport.inline.hpp"
55 #include "runtime/javaThread.hpp"
56 #include "runtime/jniHandles.inline.hpp"
57 #include "runtime/sharedRuntime.hpp"
58 #include "runtime/signature_cc.hpp"
59 #include "runtime/stubRoutines.hpp"
60 #include "utilities/globalDefinitions.hpp"
61 #include "utilities/powerOfTwo.hpp"
62 #include "vmreg_aarch64.inline.hpp"
63 #ifdef COMPILER1
64 #include "c1/c1_LIRAssembler.hpp"
65 #endif
66 #ifdef COMPILER2
67 #include "oops/oop.hpp"
68 #include "opto/compile.hpp"
69 #include "opto/node.hpp"
70 #include "opto/output.hpp"
71 #endif
72
73 #include <sys/types.h>
74
75 #ifdef PRODUCT
76 #define BLOCK_COMMENT(str) /* nothing */
77 #else
78 #define BLOCK_COMMENT(str) block_comment(str)
79 #endif
80 #define STOP(str) stop(str);
81 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
82
1158 }
1159
1160 void MacroAssembler::post_call_nop() {
1161 if (!Continuations::enabled()) {
1162 return;
1163 }
1164 InstructionMark im(this);
1165 relocate(post_call_nop_Relocation::spec());
1166 InlineSkippedInstructionsCounter skipCounter(this);
1167 nop();
1168 movk(zr, 0);
1169 movk(zr, 0);
1170 }
1171
1172 // these are no-ops overridden by InterpreterMacroAssembler
1173
1174 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1175
1176 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1177
1178 void MacroAssembler::get_default_value_oop(Register inline_klass, Register temp_reg, Register obj) {
1179 assert_different_registers(inline_klass, temp_reg, obj, rscratch2);
1180 #ifdef ASSERT
1181 {
1182 Label done_check;
1183 test_klass_is_inline_type(inline_klass, temp_reg, done_check);
1184 stop("get_default_value_oop from non inline type klass");
1185 bind(done_check);
1186 }
1187 #endif
1188 Register offset = temp_reg;
1189 // Getting the offset of the pre-allocated default value
1190 ldr(offset, Address(inline_klass, in_bytes(InstanceKlass::adr_inlineklass_fixed_block_offset())));
1191 load_sized_value(offset, Address(offset, in_bytes(InlineKlass::default_value_offset_offset())), sizeof(int), true /*is_signed*/);
1192
1193 // Getting the mirror
1194 ldr(obj, Address(inline_klass, in_bytes(Klass::java_mirror_offset())));
1195 resolve_oop_handle(obj, inline_klass, rscratch2);
1196
1197 // Getting the pre-allocated default value from the mirror
1198 Address field(obj, offset);
1199 load_heap_oop(obj, field, inline_klass, rscratch2);
1200 }
1201
1202 void MacroAssembler::get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj) {
1203 #ifdef ASSERT
1204 {
1205 Label done_check;
1206 test_klass_is_empty_inline_type(inline_klass, temp_reg, done_check);
1207 stop("get_empty_value from non-empty inline klass");
1208 bind(done_check);
1209 }
1210 #endif
1211 get_default_value_oop(inline_klass, temp_reg, obj);
1212 }
1213
1214 // Look up the method for a megamorphic invokeinterface call.
1215 // The target method is determined by <intf_klass, itable_index>.
1216 // The receiver klass is in recv_klass.
1217 // On success, the result will be in method_result, and execution falls through.
1218 // On failure, execution transfers to the given label.
1219 void MacroAssembler::lookup_interface_method(Register recv_klass,
1220 Register intf_klass,
1221 RegisterOrConstant itable_index,
1222 Register method_result,
1223 Register scan_temp,
1224 Label& L_no_such_interface,
1225 bool return_method) {
1226 assert_different_registers(recv_klass, intf_klass, scan_temp);
1227 assert_different_registers(method_result, intf_klass, scan_temp);
1228 assert(recv_klass != method_result || !return_method,
1229 "recv_klass can be destroyed when method isn't needed");
1230 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1231 "caller must use same register for non-constant itable index as for method");
1232
1233 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
2069 ldarb(scratch, scratch);
2070 subs(zr, scratch, InstanceKlass::fully_initialized);
2071 br(Assembler::EQ, *L_fast_path);
2072
2073 // Fast path check: current thread is initializer thread
2074 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2075 cmp(rthread, scratch);
2076
2077 if (L_slow_path == &L_fallthrough) {
2078 br(Assembler::EQ, *L_fast_path);
2079 bind(*L_slow_path);
2080 } else if (L_fast_path == &L_fallthrough) {
2081 br(Assembler::NE, *L_slow_path);
2082 bind(*L_fast_path);
2083 } else {
2084 Unimplemented();
2085 }
2086 }
2087
2088 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2089 if (!VerifyOops || VerifyAdapterSharing) {
2090 // Below address of the code string confuses VerifyAdapterSharing
2091 // because it may differ between otherwise equivalent adapters.
2092 return;
2093 }
2094
2095 // Pass register number to verify_oop_subroutine
2096 const char* b = nullptr;
2097 {
2098 ResourceMark rm;
2099 stringStream ss;
2100 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2101 b = code_string(ss.as_string());
2102 }
2103 BLOCK_COMMENT("verify_oop {");
2104
2105 strip_return_address(); // This might happen within a stack frame.
2106 protect_return_address();
2107 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2108 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2109
2110 mov(r0, reg);
2111 movptr(rscratch1, (uintptr_t)(address)b);
2112
2113 // call indirectly to solve generation ordering problem
2114 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2115 ldr(rscratch2, Address(rscratch2));
2116 blr(rscratch2);
2117
2118 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2119 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2120 authenticate_return_address();
2121
2122 BLOCK_COMMENT("} verify_oop");
2123 }
2124
2125 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2126 if (!VerifyOops || VerifyAdapterSharing) {
2127 // Below address of the code string confuses VerifyAdapterSharing
2128 // because it may differ between otherwise equivalent adapters.
2129 return;
2130 }
2131
2132 const char* b = nullptr;
2133 {
2134 ResourceMark rm;
2135 stringStream ss;
2136 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2137 b = code_string(ss.as_string());
2138 }
2139 BLOCK_COMMENT("verify_oop_addr {");
2140
2141 strip_return_address(); // This might happen within a stack frame.
2142 protect_return_address();
2143 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2144 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2145
2146 // addr may contain sp so we will have to adjust it based on the
2147 // pushes that we just did.
2148 if (addr.uses(sp)) {
2149 lea(r0, addr);
2150 ldr(r0, Address(r0, 4 * wordSize));
2208 call_VM_leaf_base(entry_point, 1);
2209 }
2210
2211 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2212 assert_different_registers(arg_1, c_rarg0);
2213 pass_arg0(this, arg_0);
2214 pass_arg1(this, arg_1);
2215 call_VM_leaf_base(entry_point, 2);
2216 }
2217
2218 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2219 Register arg_1, Register arg_2) {
2220 assert_different_registers(arg_1, c_rarg0);
2221 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2222 pass_arg0(this, arg_0);
2223 pass_arg1(this, arg_1);
2224 pass_arg2(this, arg_2);
2225 call_VM_leaf_base(entry_point, 3);
2226 }
2227
2228 void MacroAssembler::super_call_VM_leaf(address entry_point) {
2229 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2230 }
2231
2232 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2233 pass_arg0(this, arg_0);
2234 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2235 }
2236
2237 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2238
2239 assert_different_registers(arg_0, c_rarg1);
2240 pass_arg1(this, arg_1);
2241 pass_arg0(this, arg_0);
2242 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2243 }
2244
2245 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2246 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2247 assert_different_registers(arg_1, c_rarg2);
2248 pass_arg2(this, arg_2);
2249 pass_arg1(this, arg_1);
2250 pass_arg0(this, arg_0);
2251 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2257 assert_different_registers(arg_2, c_rarg3);
2258 pass_arg3(this, arg_3);
2259 pass_arg2(this, arg_2);
2260 pass_arg1(this, arg_1);
2261 pass_arg0(this, arg_0);
2262 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2263 }
2264
2265 void MacroAssembler::null_check(Register reg, int offset) {
2266 if (needs_explicit_null_check(offset)) {
2267 // provoke OS null exception if reg is null by
2268 // accessing M[reg] w/o changing any registers
2269 // NOTE: this is plenty to provoke a segv
2270 ldr(zr, Address(reg));
2271 } else {
2272 // nothing to do, (later) access of M[reg + offset]
2273 // will provoke OS null exception if reg is null
2274 }
2275 }
2276
2277 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2278 assert_different_registers(markword, rscratch2);
2279 andr(markword, markword, markWord::inline_type_mask_in_place);
2280 mov(rscratch2, markWord::inline_type_pattern);
2281 cmp(markword, rscratch2);
2282 br(Assembler::EQ, is_inline_type);
2283 }
2284
2285 void MacroAssembler::test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type) {
2286 ldrw(temp_reg, Address(klass, Klass::access_flags_offset()));
2287 andr(temp_reg, temp_reg, JVM_ACC_IDENTITY);
2288 cbz(temp_reg, is_inline_type);
2289 }
2290
2291 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type) {
2292 assert_different_registers(tmp, rscratch1);
2293 cbz(object, not_inline_type);
2294 const int is_inline_type_mask = markWord::inline_type_pattern;
2295 ldr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2296 mov(rscratch1, is_inline_type_mask);
2297 andr(tmp, tmp, rscratch1);
2298 cmp(tmp, rscratch1);
2299 br(Assembler::NE, not_inline_type);
2300 }
2301
2302 void MacroAssembler::test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type) {
2303 #ifdef ASSERT
2304 {
2305 Label done_check;
2306 test_klass_is_inline_type(klass, temp_reg, done_check);
2307 stop("test_klass_is_empty_inline_type with non inline type klass");
2308 bind(done_check);
2309 }
2310 #endif
2311 ldrw(temp_reg, Address(klass, InstanceKlass::misc_flags_offset()));
2312 andr(temp_reg, temp_reg, InstanceKlassFlags::is_empty_inline_type_value());
2313 cbnz(temp_reg, is_empty_inline_type);
2314 }
2315
2316 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2317 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2318 tbnz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, is_null_free_inline_type);
2319 }
2320
2321 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2322 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2323 tbz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, not_null_free_inline_type);
2324 }
2325
2326 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2327 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2328 tbnz(flags, ResolvedFieldEntry::is_flat_shift, is_flat);
2329 }
2330
2331 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2332 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2333 tbnz(flags, ResolvedFieldEntry::has_null_marker_shift, has_null_marker);
2334 }
2335
2336 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2337 Label test_mark_word;
2338 // load mark word
2339 ldr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2340 // check displaced
2341 tst(temp_reg, markWord::unlocked_value);
2342 br(Assembler::NE, test_mark_word);
2343 // slow path use klass prototype
2344 load_prototype_header(temp_reg, oop);
2345
2346 bind(test_mark_word);
2347 andr(temp_reg, temp_reg, test_bit);
2348 if (jmp_set) {
2349 cbnz(temp_reg, jmp_label);
2350 } else {
2351 cbz(temp_reg, jmp_label);
2352 }
2353 }
2354
2355 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array) {
2356 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2357 }
2358
2359 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2360 Label&is_non_flat_array) {
2361 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2362 }
2363
2364 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array) {
2365 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2366 }
2367
2368 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2369 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2370 }
2371
2372 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2373 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2374 br(Assembler::NE, is_flat_array);
2375 }
2376
2377 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
2378 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2379 br(Assembler::EQ, is_non_flat_array);
2380 }
2381
2382 // MacroAssembler protected routines needed to implement
2383 // public methods
2384
2385 void MacroAssembler::mov(Register r, Address dest) {
2386 code_section()->relocate(pc(), dest.rspec());
2387 uint64_t imm64 = (uint64_t)dest.target();
2388 movptr(r, imm64);
2389 }
2390
2391 // Move a constant pointer into r. In AArch64 mode the virtual
2392 // address space is 48 bits in size, so we only need three
2393 // instructions to create a patchable instruction sequence that can
2394 // reach anywhere.
2395 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2396 #ifndef PRODUCT
2397 {
2398 char buffer[64];
2399 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2400 block_comment(buffer);
2401 }
5149 adrp(rscratch1, src2, offset);
5150 ldr(rscratch1, Address(rscratch1, offset));
5151 cmp(src1, rscratch1);
5152 }
5153
5154 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
5155 cmp(obj1, obj2);
5156 }
5157
5158 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5159 load_method_holder(rresult, rmethod);
5160 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5161 }
5162
5163 void MacroAssembler::load_method_holder(Register holder, Register method) {
5164 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
5165 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5166 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5167 }
5168
5169 void MacroAssembler::load_metadata(Register dst, Register src) {
5170 if (UseCompressedClassPointers) {
5171 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5172 } else {
5173 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5174 }
5175 }
5176
5177 void MacroAssembler::load_klass(Register dst, Register src) {
5178 if (UseCompressedClassPointers) {
5179 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5180 decode_klass_not_null(dst);
5181 } else {
5182 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5183 }
5184 }
5185
5186 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5187 if (RestoreMXCSROnJNICalls) {
5188 Label OK;
5189 get_fpcr(tmp1);
5190 mov(tmp2, tmp1);
5191 // Set FPCR to the state we need. We do want Round to Nearest. We
5192 // don't want non-IEEE rounding modes or floating-point traps.
5193 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5194 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5195 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5196 eor(tmp2, tmp1, tmp2);
5232
5233 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
5234 if (UseCompressedClassPointers) {
5235 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
5236 if (CompressedKlassPointers::base() == nullptr) {
5237 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
5238 return;
5239 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5240 && CompressedKlassPointers::shift() == 0) {
5241 // Only the bottom 32 bits matter
5242 cmpw(trial_klass, tmp);
5243 return;
5244 }
5245 decode_klass_not_null(tmp);
5246 } else {
5247 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
5248 }
5249 cmp(trial_klass, tmp);
5250 }
5251
5252 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5253 load_klass(dst, src);
5254 ldr(dst, Address(dst, Klass::prototype_header_offset()));
5255 }
5256
5257 void MacroAssembler::store_klass(Register dst, Register src) {
5258 // FIXME: Should this be a store release? concurrent gcs assumes
5259 // klass length is valid if klass field is not null.
5260 if (UseCompressedClassPointers) {
5261 encode_klass_not_null(src);
5262 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5263 } else {
5264 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5265 }
5266 }
5267
5268 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5269 if (UseCompressedClassPointers) {
5270 // Store to klass gap in destination
5271 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5272 }
5273 }
5274
5275 // Algorithm must match CompressedOops::encode.
5276 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5563 if (as_raw) {
5564 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5565 } else {
5566 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5567 }
5568 }
5569
5570 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5571 Address dst, Register val,
5572 Register tmp1, Register tmp2, Register tmp3) {
5573 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5574 decorators = AccessInternal::decorator_fixup(decorators, type);
5575 bool as_raw = (decorators & AS_RAW) != 0;
5576 if (as_raw) {
5577 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5578 } else {
5579 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5580 }
5581 }
5582
5583 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5584 Register inline_layout_info) {
5585 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5586 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5587 }
5588
5589 void MacroAssembler::first_field_offset(Register inline_klass, Register offset) {
5590 ldr(offset, Address(inline_klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
5591 ldrw(offset, Address(offset, InlineKlass::first_field_offset_offset()));
5592 }
5593
5594 void MacroAssembler::data_for_oop(Register oop, Register data, Register inline_klass) {
5595 // ((address) (void*) o) + vk->first_field_offset();
5596 Register offset = (data == oop) ? rscratch1 : data;
5597 first_field_offset(inline_klass, offset);
5598 if (data == oop) {
5599 add(data, data, offset);
5600 } else {
5601 lea(data, Address(oop, offset));
5602 }
5603 }
5604
5605 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
5606 Register index, Register data) {
5607 assert_different_registers(array, array_klass, index);
5608 assert_different_registers(rscratch1, array, index);
5609
5610 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
5611 ldrw(rscratch1, Address(array_klass, Klass::layout_helper_offset()));
5612
5613 // Klass::layout_helper_log2_element_size(lh)
5614 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
5615 lsr(rscratch1, rscratch1, Klass::_lh_log2_element_size_shift);
5616 andr(rscratch1, rscratch1, Klass::_lh_log2_element_size_mask);
5617 lslv(index, index, rscratch1);
5618
5619 add(data, array, index);
5620 add(data, data, arrayOopDesc::base_offset_in_bytes(T_FLAT_ELEMENT));
5621 }
5622
5623 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5624 Register tmp2, DecoratorSet decorators) {
5625 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5626 }
5627
5628 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5629 Register tmp2, DecoratorSet decorators) {
5630 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5631 }
5632
5633 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5634 Register tmp2, Register tmp3, DecoratorSet decorators) {
5635 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5636 }
5637
5638 // Used for storing nulls.
5639 void MacroAssembler::store_heap_oop_null(Address dst) {
5640 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5641 }
5642
5679 oop_index = oop_recorder()->allocate_metadata_index(obj);
5680 } else {
5681 oop_index = oop_recorder()->find_index(obj);
5682 }
5683 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5684 mov(dst, Address((address)obj, rspec));
5685 }
5686
5687 Address MacroAssembler::constant_oop_address(jobject obj) {
5688 #ifdef ASSERT
5689 {
5690 ThreadInVMfromUnknown tiv;
5691 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5692 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5693 }
5694 #endif
5695 int oop_index = oop_recorder()->find_index(obj);
5696 return Address((address)obj, oop_Relocation::spec(oop_index));
5697 }
5698
5699 // Object / value buffer allocation...
5700 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
5701 Register t1, Register t2,
5702 bool clear_fields, Label& alloc_failed)
5703 {
5704 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
5705 Register layout_size = t1;
5706 assert(new_obj == r0, "needs to be r0");
5707 assert_different_registers(klass, new_obj, t1, t2);
5708
5709 // get instance_size in InstanceKlass (scaled to a count of bytes)
5710 ldrw(layout_size, Address(klass, Klass::layout_helper_offset()));
5711 // test to see if it is malformed in some way
5712 tst(layout_size, Klass::_lh_instance_slow_path_bit);
5713 br(Assembler::NE, slow_case_no_pop);
5714
5715 // Allocate the instance:
5716 // If TLAB is enabled:
5717 // Try to allocate in the TLAB.
5718 // If fails, go to the slow path.
5719 // Initialize the allocation.
5720 // Exit.
5721 //
5722 // Go to slow path.
5723
5724 if (UseTLAB) {
5725 push(klass);
5726 tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case);
5727 if (ZeroTLAB || (!clear_fields)) {
5728 // the fields have been already cleared
5729 b(initialize_header);
5730 } else {
5731 // initialize both the header and fields
5732 b(initialize_object);
5733 }
5734
5735 if (clear_fields) {
5736 // The object is initialized before the header. If the object size is
5737 // zero, go directly to the header initialization.
5738 bind(initialize_object);
5739 subs(layout_size, layout_size, sizeof(oopDesc));
5740 br(Assembler::EQ, initialize_header);
5741
5742 // Initialize topmost object field, divide size by 8, check if odd and
5743 // test if zero.
5744
5745 #ifdef ASSERT
5746 // make sure instance_size was multiple of 8
5747 Label L;
5748 tst(layout_size, 7);
5749 br(Assembler::EQ, L);
5750 stop("object size is not multiple of 8 - adjust this code");
5751 bind(L);
5752 // must be > 0, no extra check needed here
5753 #endif
5754
5755 lsr(layout_size, layout_size, LogBytesPerLong);
5756
5757 // initialize remaining object fields: instance_size was a multiple of 8
5758 {
5759 Label loop;
5760 Register base = t2;
5761
5762 bind(loop);
5763 add(rscratch1, new_obj, layout_size, Assembler::LSL, LogBytesPerLong);
5764 str(zr, Address(rscratch1, sizeof(oopDesc) - 1*oopSize));
5765 subs(layout_size, layout_size, 1);
5766 br(Assembler::NE, loop);
5767 }
5768 } // clear_fields
5769
5770 // initialize object header only.
5771 bind(initialize_header);
5772 pop(klass);
5773 Register mark_word = t2;
5774 ldr(mark_word, Address(klass, Klass::prototype_header_offset()));
5775 str(mark_word, Address(new_obj, oopDesc::mark_offset_in_bytes ()));
5776 store_klass_gap(new_obj, zr); // zero klass gap for compressed oops
5777 mov(t2, klass); // preserve klass
5778 store_klass(new_obj, t2); // src klass reg is potentially compressed
5779
5780 // TODO: Valhalla removed SharedRuntime::dtrace_object_alloc from here ?
5781
5782 b(done);
5783 }
5784
5785 if (UseTLAB) {
5786 bind(slow_case);
5787 pop(klass);
5788 }
5789 bind(slow_case_no_pop);
5790 b(alloc_failed);
5791
5792 bind(done);
5793 }
5794
5795 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5796 void MacroAssembler::tlab_allocate(Register obj,
5797 Register var_size_in_bytes,
5798 int con_size_in_bytes,
5799 Register t1,
5800 Register t2,
5801 Label& slow_case) {
5802 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5803 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5804 }
5805
5806 void MacroAssembler::verify_tlab() {
5807 #ifdef ASSERT
5808 if (UseTLAB && VerifyOops) {
5809 Label next, ok;
5810
5811 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5812
5813 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5814 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5815 cmp(rscratch2, rscratch1);
5816 br(Assembler::HS, next);
5817 STOP("assert(top >= start)");
5818 should_not_reach_here();
5819
5820 bind(next);
5821 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5822 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5823 cmp(rscratch2, rscratch1);
5824 br(Assembler::HS, ok);
5825 STOP("assert(top <= end)");
5826 should_not_reach_here();
5827
5828 bind(ok);
5829 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5830 }
5831 #endif
5832 }
5833
5834 void MacroAssembler::get_inline_type_field_klass(Register holder_klass, Register index, Register inline_klass) {
5835 inline_layout_info(holder_klass, index, inline_klass);
5836 ldr(inline_klass, Address(inline_klass, InlineLayoutInfo::klass_offset()));
5837 }
5838
5839 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
5840 assert_different_registers(holder_klass, index, layout_info);
5841 InlineLayoutInfo array[2];
5842 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
5843 if (is_power_of_2(size)) {
5844 lsl(index, index, log2i_exact(size)); // Scale index by power of 2
5845 } else {
5846 mov(layout_info, size);
5847 mul(index, index, layout_info); // Scale the index to be the entry index * array_element_size
5848 }
5849 ldr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
5850 add(layout_info, layout_info, Array<InlineLayoutInfo>::base_offset_in_bytes());
5851 lea(layout_info, Address(layout_info, index));
5852 }
5853
5854 // Writes to stack successive pages until offset reached to check for
5855 // stack overflow + shadow pages. This clobbers tmp.
5856 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5857 assert_different_registers(tmp, size, rscratch1);
5858 mov(tmp, sp);
5859 // Bang stack for total size given plus shadow page size.
5860 // Bang one page at a time because large size can bang beyond yellow and
5861 // red zones.
5862 Label loop;
5863 mov(rscratch1, (int)os::vm_page_size());
5864 bind(loop);
5865 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5866 subsw(size, size, rscratch1);
5867 str(size, Address(tmp));
5868 br(Assembler::GT, loop);
5869
5870 // Bang down shadow pages too.
5871 // At this point, (tmp-0) is the last address touched, so don't
5872 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5873 // was post-decremented.) Skip this address by starting at i=1, and
5959 }
5960
5961 void MacroAssembler::remove_frame(int framesize) {
5962 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5963 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5964 if (framesize < ((1 << 9) + 2 * wordSize)) {
5965 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5966 add(sp, sp, framesize);
5967 } else {
5968 if (framesize < ((1 << 12) + 2 * wordSize))
5969 add(sp, sp, framesize - 2 * wordSize);
5970 else {
5971 mov(rscratch1, framesize - 2 * wordSize);
5972 add(sp, sp, rscratch1);
5973 }
5974 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5975 }
5976 authenticate_return_address();
5977 }
5978
5979 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
5980 if (needs_stack_repair) {
5981 // Remove the extension of the caller's frame used for inline type unpacking
5982 //
5983 // Right now the stack looks like this:
5984 //
5985 // | Arguments from caller |
5986 // |---------------------------| <-- caller's SP
5987 // | Saved LR #1 |
5988 // | Saved FP #1 |
5989 // |---------------------------|
5990 // | Extension space for |
5991 // | inline arg (un)packing |
5992 // |---------------------------| <-- start of this method's frame
5993 // | Saved LR #2 |
5994 // | Saved FP #2 |
5995 // |---------------------------| <-- FP
5996 // | sp_inc |
5997 // | method locals |
5998 // |---------------------------| <-- SP
5999 //
6000 // There are two copies of FP and LR on the stack. They will be identical
6001 // unless the caller has been deoptimized, in which case LR #1 will be patched
6002 // to point at the deopt blob, and LR #2 will still point into the old method.
6003 //
6004 // The sp_inc stack slot holds the total size of the frame including the
6005 // extension space minus two words for the saved FP and LR.
6006
6007 int sp_inc_offset = initial_framesize - 3 * wordSize; // Immediately below saved LR and FP
6008
6009 ldr(rscratch1, Address(sp, sp_inc_offset));
6010 add(sp, sp, rscratch1);
6011 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6012 } else {
6013 remove_frame(initial_framesize);
6014 }
6015 }
6016
6017 void MacroAssembler::save_stack_increment(int sp_inc, int frame_size) {
6018 int real_frame_size = frame_size + sp_inc;
6019 assert(sp_inc == 0 || sp_inc > 2*wordSize, "invalid sp_inc value");
6020 assert(real_frame_size >= 2*wordSize, "frame size must include FP/LR space");
6021 assert((real_frame_size & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6022
6023 int sp_inc_offset = frame_size - 3 * wordSize; // Immediately below saved LR and FP
6024
6025 // Subtract two words for the saved FP and LR as these will be popped
6026 // separately. See remove_frame above.
6027 mov(rscratch1, real_frame_size - 2*wordSize);
6028 str(rscratch1, Address(sp, sp_inc_offset));
6029 }
6030
6031 // This method counts leading positive bytes (highest bit not set) in provided byte array
6032 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
6033 // Simple and most common case of aligned small array which is not at the
6034 // end of memory page is placed here. All other cases are in stub.
6035 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
6036 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
6037 assert_different_registers(ary1, len, result);
6038
6039 mov(result, len);
6040 cmpw(len, 0);
6041 br(LE, DONE);
6042 cmpw(len, 4 * wordSize);
6043 br(GE, STUB_LONG); // size > 32 then go to stub
6044
6045 int shift = 64 - exact_log2(os::vm_page_size());
6046 lsl(rscratch1, ary1, shift);
6047 mov(rscratch2, (size_t)(4 * wordSize) << shift);
6048 adds(rscratch2, rscratch1, rscratch2); // At end of page?
6049 br(CS, STUB); // at the end of page then go to stub
6923 // On other systems, the helper is a usual C function.
6924 //
6925 void MacroAssembler::get_thread(Register dst) {
6926 RegSet saved_regs =
6927 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6928 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6929
6930 protect_return_address();
6931 push(saved_regs, sp);
6932
6933 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
6934 blr(lr);
6935 if (dst != c_rarg0) {
6936 mov(dst, c_rarg0);
6937 }
6938
6939 pop(saved_regs, sp);
6940 authenticate_return_address();
6941 }
6942
6943 #ifdef COMPILER2
6944 // C2 compiled method's prolog code
6945 // Moved here from aarch64.ad to support Valhalla code belows
6946 void MacroAssembler::verified_entry(Compile* C, int sp_inc) {
6947 if (C->clinit_barrier_on_entry()) {
6948 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
6949
6950 Label L_skip_barrier;
6951
6952 mov_metadata(rscratch2, C->method()->holder()->constant_encoding());
6953 clinit_barrier(rscratch2, rscratch1, &L_skip_barrier);
6954 far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
6955 bind(L_skip_barrier);
6956 }
6957
6958 if (C->max_vector_size() > 0) {
6959 reinitialize_ptrue();
6960 }
6961
6962 int bangsize = C->output()->bang_size_in_bytes();
6963 if (C->output()->need_stack_bang(bangsize))
6964 generate_stack_overflow_check(bangsize);
6965
6966 // n.b. frame size includes space for return pc and rfp
6967 const long framesize = C->output()->frame_size_in_bytes();
6968 build_frame(framesize);
6969
6970 if (C->needs_stack_repair()) {
6971 save_stack_increment(sp_inc, framesize);
6972 }
6973
6974 if (VerifyStackAtCalls) {
6975 Unimplemented();
6976 }
6977 }
6978 #endif // COMPILER2
6979
6980 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6981 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6982 // An inline type might be returned. If fields are in registers we
6983 // need to allocate an inline type instance and initialize it with
6984 // the value of the fields.
6985 Label skip;
6986 // We only need a new buffered inline type if a new one is not returned
6987 tbz(r0, 0, skip);
6988 int call_offset = -1;
6989
6990 // Be careful not to clobber r1-7 which hold returned fields
6991 // Also do not use callee-saved registers as these may be live in the interpreter
6992 Register tmp1 = r13, tmp2 = r14, klass = r15, r0_preserved = r12;
6993
6994 // The following code is similar to allocate_instance but has some slight differences,
6995 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6996 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
6997 Label slow_case;
6998 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6999 mov(r0_preserved, r0); // save r0 for slow_case since *_allocate may corrupt it when allocation failed
7000
7001 if (vk != nullptr) {
7002 // Called from C1, where the return type is statically known.
7003 movptr(klass, (intptr_t)vk->get_InlineKlass());
7004 jint lh = vk->layout_helper();
7005 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
7006 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
7007 tlab_allocate(r0, noreg, lh, tmp1, tmp2, slow_case);
7008 } else {
7009 b(slow_case);
7010 }
7011 } else {
7012 // Call from interpreter. R0 contains ((the InlineKlass* of the return type) | 0x01)
7013 andr(klass, r0, -2);
7014 if (UseTLAB) {
7015 ldrw(tmp2, Address(klass, Klass::layout_helper_offset()));
7016 tst(tmp2, Klass::_lh_instance_slow_path_bit);
7017 br(Assembler::NE, slow_case);
7018 tlab_allocate(r0, tmp2, 0, tmp1, tmp2, slow_case);
7019 } else {
7020 b(slow_case);
7021 }
7022 }
7023 if (UseTLAB) {
7024 // 2. Initialize buffered inline instance header
7025 Register buffer_obj = r0;
7026 mov(rscratch1, (intptr_t)markWord::inline_type_prototype().value());
7027 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes()));
7028 store_klass_gap(buffer_obj, zr);
7029 if (vk == nullptr) {
7030 // store_klass corrupts klass, so save it for later use (interpreter case only).
7031 mov(tmp1, klass);
7032 }
7033 store_klass(buffer_obj, klass);
7034 // 3. Initialize its fields with an inline class specific handler
7035 if (vk != nullptr) {
7036 far_call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
7037 } else {
7038 // tmp1 holds klass preserved above
7039 ldr(tmp1, Address(tmp1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
7040 ldr(tmp1, Address(tmp1, InlineKlass::pack_handler_offset()));
7041 blr(tmp1);
7042 }
7043
7044 membar(Assembler::StoreStore);
7045 b(skip);
7046 } else {
7047 // Must have already branched to slow_case above.
7048 DEBUG_ONLY(should_not_reach_here());
7049 }
7050 bind(slow_case);
7051 // We failed to allocate a new inline type, fall back to a runtime
7052 // call. Some oop field may be live in some registers but we can't
7053 // tell. That runtime call will take care of preserving them
7054 // across a GC if there's one.
7055 mov(r0, r0_preserved);
7056
7057 if (from_interpreter) {
7058 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
7059 } else {
7060 far_call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
7061 call_offset = offset();
7062 }
7063 membar(Assembler::StoreStore);
7064
7065 bind(skip);
7066 return call_offset;
7067 }
7068
7069 // Move a value between registers/stack slots and update the reg_state
7070 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
7071 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
7072 if (reg_state[to->value()] == reg_written) {
7073 return true; // Already written
7074 }
7075
7076 if (from != to && bt != T_VOID) {
7077 if (reg_state[to->value()] == reg_readonly) {
7078 return false; // Not yet writable
7079 }
7080 if (from->is_reg()) {
7081 if (to->is_reg()) {
7082 if (from->is_Register() && to->is_Register()) {
7083 mov(to->as_Register(), from->as_Register());
7084 } else if (from->is_FloatRegister() && to->is_FloatRegister()) {
7085 fmovd(to->as_FloatRegister(), from->as_FloatRegister());
7086 } else {
7087 ShouldNotReachHere();
7088 }
7089 } else {
7090 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
7091 Address to_addr = Address(sp, st_off);
7092 if (from->is_FloatRegister()) {
7093 if (bt == T_DOUBLE) {
7094 strd(from->as_FloatRegister(), to_addr);
7095 } else {
7096 assert(bt == T_FLOAT, "must be float");
7097 strs(from->as_FloatRegister(), to_addr);
7098 }
7099 } else {
7100 str(from->as_Register(), to_addr);
7101 }
7102 }
7103 } else {
7104 Address from_addr = Address(sp, from->reg2stack() * VMRegImpl::stack_slot_size);
7105 if (to->is_reg()) {
7106 if (to->is_FloatRegister()) {
7107 if (bt == T_DOUBLE) {
7108 ldrd(to->as_FloatRegister(), from_addr);
7109 } else {
7110 assert(bt == T_FLOAT, "must be float");
7111 ldrs(to->as_FloatRegister(), from_addr);
7112 }
7113 } else {
7114 ldr(to->as_Register(), from_addr);
7115 }
7116 } else {
7117 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
7118 ldr(rscratch1, from_addr);
7119 str(rscratch1, Address(sp, st_off));
7120 }
7121 }
7122 }
7123
7124 // Update register states
7125 reg_state[from->value()] = reg_writable;
7126 reg_state[to->value()] = reg_written;
7127 return true;
7128 }
7129
7130 // Calculate the extra stack space required for packing or unpacking inline
7131 // args and adjust the stack pointer
7132 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
7133 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
7134 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
7135 assert(sp_inc > 0, "sanity");
7136
7137 // Save a copy of the FP and LR here for deoptimization patching and frame walking
7138 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
7139
7140 // Adjust the stack pointer. This will be repaired on return by MacroAssembler::remove_frame
7141 if (sp_inc < (1 << 9)) {
7142 sub(sp, sp, sp_inc); // Fits in an immediate
7143 } else {
7144 mov(rscratch1, sp_inc);
7145 sub(sp, sp, rscratch1);
7146 }
7147
7148 return sp_inc + 2 * wordSize; // Account for the FP/LR space
7149 }
7150
7151 // Read all fields from an inline type oop and store the values in registers/stack slots
7152 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
7153 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
7154 RegState reg_state[]) {
7155 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
7156 assert(from->is_valid(), "source must be valid");
7157 bool progress = false;
7158 #ifdef ASSERT
7159 const int start_offset = offset();
7160 #endif
7161
7162 Label L_null, L_notNull;
7163 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
7164 Register tmp1 = r10;
7165 Register tmp2 = r11;
7166 Register fromReg = noreg;
7167 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
7168 bool done = true;
7169 bool mark_done = true;
7170 VMReg toReg;
7171 BasicType bt;
7172 // Check if argument requires a null check
7173 bool null_check = false;
7174 VMReg nullCheckReg;
7175 while (stream.next(nullCheckReg, bt)) {
7176 if (sig->at(stream.sig_index())._offset == -1) {
7177 null_check = true;
7178 break;
7179 }
7180 }
7181 stream.reset(sig_index, to_index);
7182 while (stream.next(toReg, bt)) {
7183 assert(toReg->is_valid(), "destination must be valid");
7184 int idx = (int)toReg->value();
7185 if (reg_state[idx] == reg_readonly) {
7186 if (idx != from->value()) {
7187 mark_done = false;
7188 }
7189 done = false;
7190 continue;
7191 } else if (reg_state[idx] == reg_written) {
7192 continue;
7193 }
7194 assert(reg_state[idx] == reg_writable, "must be writable");
7195 reg_state[idx] = reg_written;
7196 progress = true;
7197
7198 if (fromReg == noreg) {
7199 if (from->is_reg()) {
7200 fromReg = from->as_Register();
7201 } else {
7202 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size;
7203 ldr(tmp1, Address(sp, st_off));
7204 fromReg = tmp1;
7205 }
7206 if (null_check) {
7207 // Nullable inline type argument, emit null check
7208 cbz(fromReg, L_null);
7209 }
7210 }
7211 int off = sig->at(stream.sig_index())._offset;
7212 if (off == -1) {
7213 assert(null_check, "Missing null check at");
7214 if (toReg->is_stack()) {
7215 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7216 mov(tmp2, 1);
7217 str(tmp2, Address(sp, st_off));
7218 } else {
7219 mov(toReg->as_Register(), 1);
7220 }
7221 continue;
7222 }
7223 assert(off > 0, "offset in object should be positive");
7224 Address fromAddr = Address(fromReg, off);
7225 if (!toReg->is_FloatRegister()) {
7226 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
7227 if (is_reference_type(bt)) {
7228 load_heap_oop(dst, fromAddr, rscratch1, rscratch2);
7229 } else {
7230 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
7231 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
7232 }
7233 if (toReg->is_stack()) {
7234 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7235 str(dst, Address(sp, st_off));
7236 }
7237 } else if (bt == T_DOUBLE) {
7238 ldrd(toReg->as_FloatRegister(), fromAddr);
7239 } else {
7240 assert(bt == T_FLOAT, "must be float");
7241 ldrs(toReg->as_FloatRegister(), fromAddr);
7242 }
7243 }
7244 if (progress && null_check) {
7245 if (done) {
7246 b(L_notNull);
7247 bind(L_null);
7248 // Set IsInit field to zero to signal that the argument is null.
7249 // Also set all oop fields to zero to make the GC happy.
7250 stream.reset(sig_index, to_index);
7251 while (stream.next(toReg, bt)) {
7252 if (sig->at(stream.sig_index())._offset == -1 ||
7253 bt == T_OBJECT || bt == T_ARRAY) {
7254 if (toReg->is_stack()) {
7255 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7256 str(zr, Address(sp, st_off));
7257 } else {
7258 mov(toReg->as_Register(), zr);
7259 }
7260 }
7261 }
7262 bind(L_notNull);
7263 } else {
7264 bind(L_null);
7265 }
7266 }
7267
7268 sig_index = stream.sig_index();
7269 to_index = stream.regs_index();
7270
7271 if (mark_done && reg_state[from->value()] != reg_written) {
7272 // This is okay because no one else will write to that slot
7273 reg_state[from->value()] = reg_writable;
7274 }
7275 from_index--;
7276 assert(progress || (start_offset == offset()), "should not emit code");
7277 return done;
7278 }
7279
7280 // Pack fields back into an inline type oop
7281 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
7282 VMRegPair* from, int from_count, int& from_index, VMReg to,
7283 RegState reg_state[], Register val_array) {
7284 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
7285 assert(to->is_valid(), "destination must be valid");
7286
7287 if (reg_state[to->value()] == reg_written) {
7288 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7289 return true; // Already written
7290 }
7291
7292 // The GC barrier expanded by store_heap_oop below may call into the
7293 // runtime so use callee-saved registers for any values that need to be
7294 // preserved. The GC barrier assembler should take care of saving the
7295 // Java argument registers.
7296 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
7297 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
7298 Register val_obj_tmp = r21;
7299 Register from_reg_tmp = r22;
7300 Register tmp1 = r14;
7301 Register tmp2 = r13;
7302 Register tmp3 = r12;
7303 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
7304
7305 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
7306
7307 if (reg_state[to->value()] == reg_readonly) {
7308 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
7309 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7310 return false; // Not yet writable
7311 }
7312 val_obj = val_obj_tmp;
7313 }
7314
7315 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
7316 load_heap_oop(val_obj, Address(val_array, index), tmp1, tmp2);
7317
7318 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
7319 VMReg fromReg;
7320 BasicType bt;
7321 Label L_null;
7322 while (stream.next(fromReg, bt)) {
7323 assert(fromReg->is_valid(), "source must be valid");
7324 reg_state[fromReg->value()] = reg_writable;
7325
7326 int off = sig->at(stream.sig_index())._offset;
7327 if (off == -1) {
7328 // Nullable inline type argument, emit null check
7329 Label L_notNull;
7330 if (fromReg->is_stack()) {
7331 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7332 ldrb(tmp2, Address(sp, ld_off));
7333 cbnz(tmp2, L_notNull);
7334 } else {
7335 cbnz(fromReg->as_Register(), L_notNull);
7336 }
7337 mov(val_obj, 0);
7338 b(L_null);
7339 bind(L_notNull);
7340 continue;
7341 }
7342
7343 assert(off > 0, "offset in object should be positive");
7344 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
7345
7346 // Pack the scalarized field into the value object.
7347 Address dst(val_obj, off);
7348
7349 if (!fromReg->is_FloatRegister()) {
7350 Register src;
7351 if (fromReg->is_stack()) {
7352 src = from_reg_tmp;
7353 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7354 load_sized_value(src, Address(sp, ld_off), size_in_bytes, /* is_signed */ false);
7355 } else {
7356 src = fromReg->as_Register();
7357 }
7358 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
7359 if (is_reference_type(bt)) {
7360 store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
7361 } else {
7362 store_sized_value(dst, src, size_in_bytes);
7363 }
7364 } else if (bt == T_DOUBLE) {
7365 strd(fromReg->as_FloatRegister(), dst);
7366 } else {
7367 assert(bt == T_FLOAT, "must be float");
7368 strs(fromReg->as_FloatRegister(), dst);
7369 }
7370 }
7371 bind(L_null);
7372 sig_index = stream.sig_index();
7373 from_index = stream.regs_index();
7374
7375 assert(reg_state[to->value()] == reg_writable, "must have already been read");
7376 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
7377 assert(success, "to register must be writeable");
7378
7379 return true;
7380 }
7381
7382 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
7383 return (reg->is_FloatRegister()) ? v8->as_VMReg() : r14->as_VMReg();
7384 }
7385
7386 void MacroAssembler::cache_wb(Address line) {
7387 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
7388 assert(line.index() == noreg, "index should be noreg");
7389 assert(line.offset() == 0, "offset should be 0");
7390 // would like to assert this
7391 // assert(line._ext.shift == 0, "shift should be zero");
7392 if (VM_Version::supports_dcpop()) {
7393 // writeback using clear virtual address to point of persistence
7394 dc(Assembler::CVAP, line.base());
7395 } else {
7396 // no need to generate anything as Unsafe.writebackMemory should
7397 // never invoke this stub
7398 }
7399 }
7400
7401 void MacroAssembler::cache_wbsync(bool is_pre) {
7402 // we only need a barrier post sync
7403 if (!is_pre) {
7404 membar(Assembler::AnyAny);
7405 }
7764 }
7765
7766 // Check if the lock-stack is full.
7767 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7768 cmpw(top, (unsigned)LockStack::end_offset());
7769 br(Assembler::GE, slow);
7770
7771 // Check for recursion.
7772 subw(t, top, oopSize);
7773 ldr(t, Address(rthread, t));
7774 cmp(obj, t);
7775 br(Assembler::EQ, push);
7776
7777 // Check header for monitor (0b10).
7778 tst(mark, markWord::monitor_value);
7779 br(Assembler::NE, slow);
7780
7781 // Try to lock. Transition lock bits 0b01 => 0b00
7782 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7783 orr(mark, mark, markWord::unlocked_value);
7784 if (EnableValhalla) {
7785 // Mask inline_type bit such that we go to the slow path if object is an inline type
7786 andr(mark, mark, ~((int) markWord::inline_type_bit_in_place));
7787 }
7788 eor(t, mark, markWord::unlocked_value);
7789 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
7790 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
7791 br(Assembler::NE, slow);
7792
7793 bind(push);
7794 // After successful lock, push object on lock-stack.
7795 str(obj, Address(rthread, top));
7796 addw(top, top, oopSize);
7797 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7798 }
7799
7800 // Implements lightweight-unlocking.
7801 //
7802 // - obj: the object to be unlocked
7803 // - t1, t2, t3: temporary registers
7804 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7805 void MacroAssembler::lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7806 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
7807 // cmpxchg clobbers rscratch1.
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