12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "asm/assembler.hpp"
30 #include "asm/assembler.inline.hpp"
31 #include "ci/ciEnv.hpp"
32 #include "compiler/compileTask.hpp"
33 #include "compiler/disassembler.hpp"
34 #include "compiler/oopMap.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/barrierSetAssembler.hpp"
37 #include "gc/shared/cardTableBarrierSet.hpp"
38 #include "gc/shared/cardTable.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/tlab_globals.hpp"
41 #include "interpreter/bytecodeHistogram.hpp"
42 #include "interpreter/interpreter.hpp"
43 #include "jvm.h"
44 #include "memory/resourceArea.hpp"
45 #include "memory/universe.hpp"
46 #include "nativeInst_aarch64.hpp"
47 #include "oops/accessDecorators.hpp"
48 #include "oops/compressedKlass.inline.hpp"
49 #include "oops/compressedOops.inline.hpp"
50 #include "oops/klass.inline.hpp"
51 #include "runtime/continuation.hpp"
52 #include "runtime/icache.hpp"
53 #include "runtime/interfaceSupport.inline.hpp"
54 #include "runtime/javaThread.hpp"
55 #include "runtime/jniHandles.inline.hpp"
56 #include "runtime/sharedRuntime.hpp"
57 #include "runtime/stubRoutines.hpp"
58 #include "utilities/powerOfTwo.hpp"
59 #ifdef COMPILER1
60 #include "c1/c1_LIRAssembler.hpp"
61 #endif
62 #ifdef COMPILER2
63 #include "oops/oop.hpp"
64 #include "opto/compile.hpp"
65 #include "opto/node.hpp"
66 #include "opto/output.hpp"
67 #endif
68
69 #ifdef PRODUCT
70 #define BLOCK_COMMENT(str) /* nothing */
71 #else
72 #define BLOCK_COMMENT(str) block_comment(str)
73 #endif
74 #define STOP(str) stop(str);
75 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
76
77 #ifdef ASSERT
78 extern "C" void disnm(intptr_t p);
1104 }
1105
1106 void MacroAssembler::post_call_nop() {
1107 if (!Continuations::enabled()) {
1108 return;
1109 }
1110 InstructionMark im(this);
1111 relocate(post_call_nop_Relocation::spec());
1112 InlineSkippedInstructionsCounter skipCounter(this);
1113 nop();
1114 movk(zr, 0);
1115 movk(zr, 0);
1116 }
1117
1118 // these are no-ops overridden by InterpreterMacroAssembler
1119
1120 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1121
1122 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1123
1124 // Look up the method for a megamorphic invokeinterface call.
1125 // The target method is determined by <intf_klass, itable_index>.
1126 // The receiver klass is in recv_klass.
1127 // On success, the result will be in method_result, and execution falls through.
1128 // On failure, execution transfers to the given label.
1129 void MacroAssembler::lookup_interface_method(Register recv_klass,
1130 Register intf_klass,
1131 RegisterOrConstant itable_index,
1132 Register method_result,
1133 Register scan_temp,
1134 Label& L_no_such_interface,
1135 bool return_method) {
1136 assert_different_registers(recv_klass, intf_klass, scan_temp);
1137 assert_different_registers(method_result, intf_klass, scan_temp);
1138 assert(recv_klass != method_result || !return_method,
1139 "recv_klass can be destroyed when method isn't needed");
1140 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1141 "caller must use same register for non-constant itable index as for method");
1142
1143 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1557 ldrb(scratch, Address(klass, InstanceKlass::init_state_offset()));
1558 subs(zr, scratch, InstanceKlass::fully_initialized);
1559 br(Assembler::EQ, *L_fast_path);
1560
1561 // Fast path check: current thread is initializer thread
1562 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
1563 cmp(rthread, scratch);
1564
1565 if (L_slow_path == &L_fallthrough) {
1566 br(Assembler::EQ, *L_fast_path);
1567 bind(*L_slow_path);
1568 } else if (L_fast_path == &L_fallthrough) {
1569 br(Assembler::NE, *L_slow_path);
1570 bind(*L_fast_path);
1571 } else {
1572 Unimplemented();
1573 }
1574 }
1575
1576 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
1577 if (!VerifyOops) return;
1578
1579 // Pass register number to verify_oop_subroutine
1580 const char* b = nullptr;
1581 {
1582 ResourceMark rm;
1583 stringStream ss;
1584 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
1585 b = code_string(ss.as_string());
1586 }
1587 BLOCK_COMMENT("verify_oop {");
1588
1589 strip_return_address(); // This might happen within a stack frame.
1590 protect_return_address();
1591 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1592 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1593
1594 mov(r0, reg);
1595 movptr(rscratch1, (uintptr_t)(address)b);
1596
1597 // call indirectly to solve generation ordering problem
1598 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1599 ldr(rscratch2, Address(rscratch2));
1600 blr(rscratch2);
1601
1602 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1603 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1604 authenticate_return_address();
1605
1606 BLOCK_COMMENT("} verify_oop");
1607 }
1608
1609 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
1610 if (!VerifyOops) return;
1611
1612 const char* b = nullptr;
1613 {
1614 ResourceMark rm;
1615 stringStream ss;
1616 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
1617 b = code_string(ss.as_string());
1618 }
1619 BLOCK_COMMENT("verify_oop_addr {");
1620
1621 strip_return_address(); // This might happen within a stack frame.
1622 protect_return_address();
1623 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1624 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1625
1626 // addr may contain sp so we will have to adjust it based on the
1627 // pushes that we just did.
1628 if (addr.uses(sp)) {
1629 lea(r0, addr);
1630 ldr(r0, Address(r0, 4 * wordSize));
1688 call_VM_leaf_base(entry_point, 1);
1689 }
1690
1691 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1692 assert_different_registers(arg_1, c_rarg0);
1693 pass_arg0(this, arg_0);
1694 pass_arg1(this, arg_1);
1695 call_VM_leaf_base(entry_point, 2);
1696 }
1697
1698 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1699 Register arg_1, Register arg_2) {
1700 assert_different_registers(arg_1, c_rarg0);
1701 assert_different_registers(arg_2, c_rarg0, c_rarg1);
1702 pass_arg0(this, arg_0);
1703 pass_arg1(this, arg_1);
1704 pass_arg2(this, arg_2);
1705 call_VM_leaf_base(entry_point, 3);
1706 }
1707
1708 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1709 pass_arg0(this, arg_0);
1710 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1711 }
1712
1713 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1714
1715 assert_different_registers(arg_0, c_rarg1);
1716 pass_arg1(this, arg_1);
1717 pass_arg0(this, arg_0);
1718 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1719 }
1720
1721 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1722 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1723 assert_different_registers(arg_1, c_rarg2);
1724 pass_arg2(this, arg_2);
1725 pass_arg1(this, arg_1);
1726 pass_arg0(this, arg_0);
1727 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1733 assert_different_registers(arg_2, c_rarg3);
1734 pass_arg3(this, arg_3);
1735 pass_arg2(this, arg_2);
1736 pass_arg1(this, arg_1);
1737 pass_arg0(this, arg_0);
1738 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1739 }
1740
1741 void MacroAssembler::null_check(Register reg, int offset) {
1742 if (needs_explicit_null_check(offset)) {
1743 // provoke OS null exception if reg is null by
1744 // accessing M[reg] w/o changing any registers
1745 // NOTE: this is plenty to provoke a segv
1746 ldr(zr, Address(reg));
1747 } else {
1748 // nothing to do, (later) access of M[reg + offset]
1749 // will provoke OS null exception if reg is null
1750 }
1751 }
1752
1753 // MacroAssembler protected routines needed to implement
1754 // public methods
1755
1756 void MacroAssembler::mov(Register r, Address dest) {
1757 code_section()->relocate(pc(), dest.rspec());
1758 uint64_t imm64 = (uint64_t)dest.target();
1759 movptr(r, imm64);
1760 }
1761
1762 // Move a constant pointer into r. In AArch64 mode the virtual
1763 // address space is 48 bits in size, so we only need three
1764 // instructions to create a patchable instruction sequence that can
1765 // reach anywhere.
1766 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1767 #ifndef PRODUCT
1768 {
1769 char buffer[64];
1770 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
1771 block_comment(buffer);
1772 }
4402 adrp(rscratch1, src2, offset);
4403 ldr(rscratch1, Address(rscratch1, offset));
4404 cmp(src1, rscratch1);
4405 }
4406
4407 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4408 cmp(obj1, obj2);
4409 }
4410
4411 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4412 load_method_holder(rresult, rmethod);
4413 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4414 }
4415
4416 void MacroAssembler::load_method_holder(Register holder, Register method) {
4417 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
4418 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
4419 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
4420 }
4421
4422 void MacroAssembler::load_klass(Register dst, Register src) {
4423 if (UseCompressedClassPointers) {
4424 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4425 decode_klass_not_null(dst);
4426 } else {
4427 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4428 }
4429 }
4430
4431 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
4432 if (RestoreMXCSROnJNICalls) {
4433 Label OK;
4434 get_fpcr(tmp1);
4435 mov(tmp2, tmp1);
4436 // Set FPCR to the state we need. We do want Round to Nearest. We
4437 // don't want non-IEEE rounding modes or floating-point traps.
4438 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
4439 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
4440 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
4441 eor(tmp2, tmp1, tmp2);
4477
4478 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
4479 if (UseCompressedClassPointers) {
4480 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4481 if (CompressedKlassPointers::base() == nullptr) {
4482 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
4483 return;
4484 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
4485 && CompressedKlassPointers::shift() == 0) {
4486 // Only the bottom 32 bits matter
4487 cmpw(trial_klass, tmp);
4488 return;
4489 }
4490 decode_klass_not_null(tmp);
4491 } else {
4492 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4493 }
4494 cmp(trial_klass, tmp);
4495 }
4496
4497 void MacroAssembler::store_klass(Register dst, Register src) {
4498 // FIXME: Should this be a store release? concurrent gcs assumes
4499 // klass length is valid if klass field is not null.
4500 if (UseCompressedClassPointers) {
4501 encode_klass_not_null(src);
4502 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4503 } else {
4504 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4505 }
4506 }
4507
4508 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4509 if (UseCompressedClassPointers) {
4510 // Store to klass gap in destination
4511 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
4512 }
4513 }
4514
4515 // Algorithm must match CompressedOops::encode.
4516 void MacroAssembler::encode_heap_oop(Register d, Register s) {
4801 if (as_raw) {
4802 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
4803 } else {
4804 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
4805 }
4806 }
4807
4808 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
4809 Address dst, Register val,
4810 Register tmp1, Register tmp2, Register tmp3) {
4811 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4812 decorators = AccessInternal::decorator_fixup(decorators, type);
4813 bool as_raw = (decorators & AS_RAW) != 0;
4814 if (as_raw) {
4815 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
4816 } else {
4817 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
4818 }
4819 }
4820
4821 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
4822 Register tmp2, DecoratorSet decorators) {
4823 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
4824 }
4825
4826 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4827 Register tmp2, DecoratorSet decorators) {
4828 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
4829 }
4830
4831 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
4832 Register tmp2, Register tmp3, DecoratorSet decorators) {
4833 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
4834 }
4835
4836 // Used for storing nulls.
4837 void MacroAssembler::store_heap_oop_null(Address dst) {
4838 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
4839 }
4840
4877 oop_index = oop_recorder()->allocate_metadata_index(obj);
4878 } else {
4879 oop_index = oop_recorder()->find_index(obj);
4880 }
4881 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
4882 mov(dst, Address((address)obj, rspec));
4883 }
4884
4885 Address MacroAssembler::constant_oop_address(jobject obj) {
4886 #ifdef ASSERT
4887 {
4888 ThreadInVMfromUnknown tiv;
4889 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
4890 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
4891 }
4892 #endif
4893 int oop_index = oop_recorder()->find_index(obj);
4894 return Address((address)obj, oop_Relocation::spec(oop_index));
4895 }
4896
4897 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4898 void MacroAssembler::tlab_allocate(Register obj,
4899 Register var_size_in_bytes,
4900 int con_size_in_bytes,
4901 Register t1,
4902 Register t2,
4903 Label& slow_case) {
4904 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4905 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4906 }
4907
4908 void MacroAssembler::verify_tlab() {
4909 #ifdef ASSERT
4910 if (UseTLAB && VerifyOops) {
4911 Label next, ok;
4912
4913 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
4914
4915 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4916 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
4917 cmp(rscratch2, rscratch1);
4918 br(Assembler::HS, next);
4919 STOP("assert(top >= start)");
4920 should_not_reach_here();
4921
4922 bind(next);
4923 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
4924 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4925 cmp(rscratch2, rscratch1);
4926 br(Assembler::HS, ok);
4927 STOP("assert(top <= end)");
4928 should_not_reach_here();
4929
4930 bind(ok);
4931 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
4932 }
4933 #endif
4934 }
4935
4936 // Writes to stack successive pages until offset reached to check for
4937 // stack overflow + shadow pages. This clobbers tmp.
4938 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
4939 assert_different_registers(tmp, size, rscratch1);
4940 mov(tmp, sp);
4941 // Bang stack for total size given plus shadow page size.
4942 // Bang one page at a time because large size can bang beyond yellow and
4943 // red zones.
4944 Label loop;
4945 mov(rscratch1, (int)os::vm_page_size());
4946 bind(loop);
4947 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
4948 subsw(size, size, rscratch1);
4949 str(size, Address(tmp));
4950 br(Assembler::GT, loop);
4951
4952 // Bang down shadow pages too.
4953 // At this point, (tmp-0) is the last address touched, so don't
4954 // touch it again. (It was touched as (tmp-pagesize) but then tmp
4955 // was post-decremented.) Skip this address by starting at i=1, and
5041 }
5042
5043 void MacroAssembler::remove_frame(int framesize) {
5044 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5045 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5046 if (framesize < ((1 << 9) + 2 * wordSize)) {
5047 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5048 add(sp, sp, framesize);
5049 } else {
5050 if (framesize < ((1 << 12) + 2 * wordSize))
5051 add(sp, sp, framesize - 2 * wordSize);
5052 else {
5053 mov(rscratch1, framesize - 2 * wordSize);
5054 add(sp, sp, rscratch1);
5055 }
5056 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5057 }
5058 authenticate_return_address();
5059 }
5060
5061
5062 // This method counts leading positive bytes (highest bit not set) in provided byte array
5063 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5064 // Simple and most common case of aligned small array which is not at the
5065 // end of memory page is placed here. All other cases are in stub.
5066 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5067 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5068 assert_different_registers(ary1, len, result);
5069
5070 mov(result, len);
5071 cmpw(len, 0);
5072 br(LE, DONE);
5073 cmpw(len, 4 * wordSize);
5074 br(GE, STUB_LONG); // size > 32 then go to stub
5075
5076 int shift = 64 - exact_log2(os::vm_page_size());
5077 lsl(rscratch1, ary1, shift);
5078 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5079 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5080 br(CS, STUB); // at the end of page then go to stub
5955 // On other systems, the helper is a usual C function.
5956 //
5957 void MacroAssembler::get_thread(Register dst) {
5958 RegSet saved_regs =
5959 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
5960 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
5961
5962 protect_return_address();
5963 push(saved_regs, sp);
5964
5965 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
5966 blr(lr);
5967 if (dst != c_rarg0) {
5968 mov(dst, c_rarg0);
5969 }
5970
5971 pop(saved_regs, sp);
5972 authenticate_return_address();
5973 }
5974
5975 void MacroAssembler::cache_wb(Address line) {
5976 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
5977 assert(line.index() == noreg, "index should be noreg");
5978 assert(line.offset() == 0, "offset should be 0");
5979 // would like to assert this
5980 // assert(line._ext.shift == 0, "shift should be zero");
5981 if (VM_Version::supports_dcpop()) {
5982 // writeback using clear virtual address to point of persistence
5983 dc(Assembler::CVAP, line.base());
5984 } else {
5985 // no need to generate anything as Unsafe.writebackMemory should
5986 // never invoke this stub
5987 }
5988 }
5989
5990 void MacroAssembler::cache_wbsync(bool is_pre) {
5991 // we only need a barrier post sync
5992 if (!is_pre) {
5993 membar(Assembler::AnyAny);
5994 }
6328 }
6329
6330 // Implements lightweight-locking.
6331 // Branches to slow upon failure to lock the object, with ZF cleared.
6332 // Falls through upon success with ZF set.
6333 //
6334 // - obj: the object to be locked
6335 // - hdr: the header, already loaded from obj, will be destroyed
6336 // - t1, t2: temporary registers, will be destroyed
6337 void MacroAssembler::lightweight_lock(Register obj, Register hdr, Register t1, Register t2, Label& slow) {
6338 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
6339 assert_different_registers(obj, hdr, t1, t2, rscratch1);
6340
6341 // Check if we would have space on lock-stack for the object.
6342 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
6343 cmpw(t1, (unsigned)LockStack::end_offset() - 1);
6344 br(Assembler::GT, slow);
6345
6346 // Load (object->mark() | 1) into hdr
6347 orr(hdr, hdr, markWord::unlocked_value);
6348 // Clear lock-bits, into t2
6349 eor(t2, hdr, markWord::unlocked_value);
6350 // Try to swing header from unlocked to locked
6351 // Clobbers rscratch1 when UseLSE is false
6352 cmpxchg(/*addr*/ obj, /*expected*/ hdr, /*new*/ t2, Assembler::xword,
6353 /*acquire*/ true, /*release*/ true, /*weak*/ false, t1);
6354 br(Assembler::NE, slow);
6355
6356 // After successful lock, push object on lock-stack
6357 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
6358 str(obj, Address(rthread, t1));
6359 addw(t1, t1, oopSize);
6360 strw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
6361 }
6362
6363 // Implements lightweight-unlocking.
6364 // Branches to slow upon failure, with ZF cleared.
6365 // Falls through upon success, with ZF set.
6366 //
6367 // - obj: the object to be unlocked
|
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "asm/assembler.hpp"
30 #include "asm/assembler.inline.hpp"
31 #include "ci/ciEnv.hpp"
32 #include "ci/ciInlineKlass.hpp"
33 #include "compiler/compileTask.hpp"
34 #include "compiler/disassembler.hpp"
35 #include "compiler/oopMap.hpp"
36 #include "gc/shared/barrierSet.hpp"
37 #include "gc/shared/barrierSetAssembler.hpp"
38 #include "gc/shared/cardTableBarrierSet.hpp"
39 #include "gc/shared/cardTable.hpp"
40 #include "gc/shared/collectedHeap.hpp"
41 #include "gc/shared/tlab_globals.hpp"
42 #include "interpreter/bytecodeHistogram.hpp"
43 #include "interpreter/interpreter.hpp"
44 #include "jvm.h"
45 #include "memory/resourceArea.hpp"
46 #include "memory/universe.hpp"
47 #include "nativeInst_aarch64.hpp"
48 #include "oops/accessDecorators.hpp"
49 #include "oops/compressedKlass.inline.hpp"
50 #include "oops/compressedOops.inline.hpp"
51 #include "oops/klass.inline.hpp"
52 #include "oops/resolvedFieldEntry.hpp"
53 #include "runtime/continuation.hpp"
54 #include "runtime/icache.hpp"
55 #include "runtime/interfaceSupport.inline.hpp"
56 #include "runtime/javaThread.hpp"
57 #include "runtime/jniHandles.inline.hpp"
58 #include "runtime/sharedRuntime.hpp"
59 #include "runtime/signature_cc.hpp"
60 #include "runtime/stubRoutines.hpp"
61 #include "utilities/powerOfTwo.hpp"
62 #include "vmreg_aarch64.inline.hpp"
63 #ifdef COMPILER1
64 #include "c1/c1_LIRAssembler.hpp"
65 #endif
66 #ifdef COMPILER2
67 #include "oops/oop.hpp"
68 #include "opto/compile.hpp"
69 #include "opto/node.hpp"
70 #include "opto/output.hpp"
71 #endif
72
73 #ifdef PRODUCT
74 #define BLOCK_COMMENT(str) /* nothing */
75 #else
76 #define BLOCK_COMMENT(str) block_comment(str)
77 #endif
78 #define STOP(str) stop(str);
79 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
80
81 #ifdef ASSERT
82 extern "C" void disnm(intptr_t p);
1108 }
1109
1110 void MacroAssembler::post_call_nop() {
1111 if (!Continuations::enabled()) {
1112 return;
1113 }
1114 InstructionMark im(this);
1115 relocate(post_call_nop_Relocation::spec());
1116 InlineSkippedInstructionsCounter skipCounter(this);
1117 nop();
1118 movk(zr, 0);
1119 movk(zr, 0);
1120 }
1121
1122 // these are no-ops overridden by InterpreterMacroAssembler
1123
1124 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1125
1126 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1127
1128 void MacroAssembler::get_default_value_oop(Register inline_klass, Register temp_reg, Register obj) {
1129 #ifdef ASSERT
1130 {
1131 Label done_check;
1132 test_klass_is_inline_type(inline_klass, temp_reg, done_check);
1133 stop("get_default_value_oop from non inline type klass");
1134 bind(done_check);
1135 }
1136 #endif
1137 Register offset = temp_reg;
1138 // Getting the offset of the pre-allocated default value
1139 ldr(offset, Address(inline_klass, in_bytes(InstanceKlass::adr_inlineklass_fixed_block_offset())));
1140 ldr(offset, Address(offset, in_bytes(InlineKlass::default_value_offset_offset())));
1141
1142 // Getting the mirror
1143 ldr(obj, Address(inline_klass, in_bytes(Klass::java_mirror_offset())));
1144 resolve_oop_handle(obj, inline_klass, temp_reg);
1145
1146 // Getting the pre-allocated default value from the mirror
1147 Address field(obj, offset);
1148 load_heap_oop(obj, field, inline_klass, rscratch2);
1149 }
1150
1151 void MacroAssembler::get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj) {
1152 #ifdef ASSERT
1153 {
1154 Label done_check;
1155 test_klass_is_empty_inline_type(inline_klass, temp_reg, done_check);
1156 stop("get_empty_value from non-empty inline klass");
1157 bind(done_check);
1158 }
1159 #endif
1160 get_default_value_oop(inline_klass, temp_reg, obj);
1161 }
1162
1163 // Look up the method for a megamorphic invokeinterface call.
1164 // The target method is determined by <intf_klass, itable_index>.
1165 // The receiver klass is in recv_klass.
1166 // On success, the result will be in method_result, and execution falls through.
1167 // On failure, execution transfers to the given label.
1168 void MacroAssembler::lookup_interface_method(Register recv_klass,
1169 Register intf_klass,
1170 RegisterOrConstant itable_index,
1171 Register method_result,
1172 Register scan_temp,
1173 Label& L_no_such_interface,
1174 bool return_method) {
1175 assert_different_registers(recv_klass, intf_klass, scan_temp);
1176 assert_different_registers(method_result, intf_klass, scan_temp);
1177 assert(recv_klass != method_result || !return_method,
1178 "recv_klass can be destroyed when method isn't needed");
1179 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1180 "caller must use same register for non-constant itable index as for method");
1181
1182 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1596 ldrb(scratch, Address(klass, InstanceKlass::init_state_offset()));
1597 subs(zr, scratch, InstanceKlass::fully_initialized);
1598 br(Assembler::EQ, *L_fast_path);
1599
1600 // Fast path check: current thread is initializer thread
1601 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
1602 cmp(rthread, scratch);
1603
1604 if (L_slow_path == &L_fallthrough) {
1605 br(Assembler::EQ, *L_fast_path);
1606 bind(*L_slow_path);
1607 } else if (L_fast_path == &L_fallthrough) {
1608 br(Assembler::NE, *L_slow_path);
1609 bind(*L_fast_path);
1610 } else {
1611 Unimplemented();
1612 }
1613 }
1614
1615 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
1616 if (!VerifyOops || VerifyAdapterSharing) {
1617 // Below address of the code string confuses VerifyAdapterSharing
1618 // because it may differ between otherwise equivalent adapters.
1619 return;
1620 }
1621
1622 // Pass register number to verify_oop_subroutine
1623 const char* b = nullptr;
1624 {
1625 ResourceMark rm;
1626 stringStream ss;
1627 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
1628 b = code_string(ss.as_string());
1629 }
1630 BLOCK_COMMENT("verify_oop {");
1631
1632 strip_return_address(); // This might happen within a stack frame.
1633 protect_return_address();
1634 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1635 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1636
1637 mov(r0, reg);
1638 movptr(rscratch1, (uintptr_t)(address)b);
1639
1640 // call indirectly to solve generation ordering problem
1641 lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1642 ldr(rscratch2, Address(rscratch2));
1643 blr(rscratch2);
1644
1645 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1646 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1647 authenticate_return_address();
1648
1649 BLOCK_COMMENT("} verify_oop");
1650 }
1651
1652 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
1653 if (!VerifyOops || VerifyAdapterSharing) {
1654 // Below address of the code string confuses VerifyAdapterSharing
1655 // because it may differ between otherwise equivalent adapters.
1656 return;
1657 }
1658
1659 const char* b = nullptr;
1660 {
1661 ResourceMark rm;
1662 stringStream ss;
1663 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
1664 b = code_string(ss.as_string());
1665 }
1666 BLOCK_COMMENT("verify_oop_addr {");
1667
1668 strip_return_address(); // This might happen within a stack frame.
1669 protect_return_address();
1670 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1671 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1672
1673 // addr may contain sp so we will have to adjust it based on the
1674 // pushes that we just did.
1675 if (addr.uses(sp)) {
1676 lea(r0, addr);
1677 ldr(r0, Address(r0, 4 * wordSize));
1735 call_VM_leaf_base(entry_point, 1);
1736 }
1737
1738 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1739 assert_different_registers(arg_1, c_rarg0);
1740 pass_arg0(this, arg_0);
1741 pass_arg1(this, arg_1);
1742 call_VM_leaf_base(entry_point, 2);
1743 }
1744
1745 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1746 Register arg_1, Register arg_2) {
1747 assert_different_registers(arg_1, c_rarg0);
1748 assert_different_registers(arg_2, c_rarg0, c_rarg1);
1749 pass_arg0(this, arg_0);
1750 pass_arg1(this, arg_1);
1751 pass_arg2(this, arg_2);
1752 call_VM_leaf_base(entry_point, 3);
1753 }
1754
1755 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1756 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1757 }
1758
1759 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1760 pass_arg0(this, arg_0);
1761 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1762 }
1763
1764 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1765
1766 assert_different_registers(arg_0, c_rarg1);
1767 pass_arg1(this, arg_1);
1768 pass_arg0(this, arg_0);
1769 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1770 }
1771
1772 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1773 assert_different_registers(arg_0, c_rarg1, c_rarg2);
1774 assert_different_registers(arg_1, c_rarg2);
1775 pass_arg2(this, arg_2);
1776 pass_arg1(this, arg_1);
1777 pass_arg0(this, arg_0);
1778 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1784 assert_different_registers(arg_2, c_rarg3);
1785 pass_arg3(this, arg_3);
1786 pass_arg2(this, arg_2);
1787 pass_arg1(this, arg_1);
1788 pass_arg0(this, arg_0);
1789 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1790 }
1791
1792 void MacroAssembler::null_check(Register reg, int offset) {
1793 if (needs_explicit_null_check(offset)) {
1794 // provoke OS null exception if reg is null by
1795 // accessing M[reg] w/o changing any registers
1796 // NOTE: this is plenty to provoke a segv
1797 ldr(zr, Address(reg));
1798 } else {
1799 // nothing to do, (later) access of M[reg + offset]
1800 // will provoke OS null exception if reg is null
1801 }
1802 }
1803
1804 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
1805 assert_different_registers(markword, rscratch2);
1806 andr(markword, markword, markWord::inline_type_mask_in_place);
1807 mov(rscratch2, markWord::inline_type_pattern);
1808 cmp(markword, rscratch2);
1809 br(Assembler::EQ, is_inline_type);
1810 }
1811
1812 void MacroAssembler::test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type) {
1813 ldrw(temp_reg, Address(klass, Klass::access_flags_offset()));
1814 andr(temp_reg, temp_reg, JVM_ACC_IDENTITY);
1815 cbz(temp_reg, is_inline_type);
1816 }
1817
1818 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type) {
1819 assert_different_registers(tmp, rscratch1);
1820 cbz(object, not_inline_type);
1821 const int is_inline_type_mask = markWord::inline_type_pattern;
1822 ldr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
1823 mov(rscratch1, is_inline_type_mask);
1824 andr(tmp, tmp, rscratch1);
1825 cmp(tmp, rscratch1);
1826 br(Assembler::NE, not_inline_type);
1827 }
1828
1829 void MacroAssembler::test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type) {
1830 #ifdef ASSERT
1831 {
1832 Label done_check;
1833 test_klass_is_inline_type(klass, temp_reg, done_check);
1834 stop("test_klass_is_empty_inline_type with non inline type klass");
1835 bind(done_check);
1836 }
1837 #endif
1838 ldrw(temp_reg, Address(klass, InstanceKlass::misc_flags_offset()));
1839 andr(temp_reg, temp_reg, InstanceKlassFlags::is_empty_inline_type_value());
1840 cbnz(temp_reg, is_empty_inline_type);
1841 }
1842
1843 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
1844 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
1845 tbnz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, is_null_free_inline_type);
1846 }
1847
1848 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
1849 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
1850 tbz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, not_null_free_inline_type);
1851 }
1852
1853 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
1854 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
1855 tbnz(flags, ResolvedFieldEntry::is_flat_shift, is_flat);
1856 }
1857
1858 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
1859 Label test_mark_word;
1860 // load mark word
1861 ldr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
1862 // check displaced
1863 tst(temp_reg, markWord::unlocked_value);
1864 br(Assembler::NE, test_mark_word);
1865 // slow path use klass prototype
1866 load_prototype_header(temp_reg, oop);
1867
1868 bind(test_mark_word);
1869 andr(temp_reg, temp_reg, test_bit);
1870 if (jmp_set) {
1871 cbnz(temp_reg, jmp_label);
1872 } else {
1873 cbz(temp_reg, jmp_label);
1874 }
1875 }
1876
1877 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array) {
1878 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
1879 }
1880
1881 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
1882 Label&is_non_flat_array) {
1883 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
1884 }
1885
1886 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array) {
1887 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
1888 }
1889
1890 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
1891 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
1892 }
1893
1894 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
1895 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
1896 br(Assembler::NE, is_flat_array);
1897 }
1898
1899 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
1900 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
1901 br(Assembler::EQ, is_non_flat_array);
1902 }
1903
1904 void MacroAssembler::test_null_free_array_layout(Register lh, Label& is_null_free_array) {
1905 tst(lh, Klass::_lh_null_free_array_bit_inplace);
1906 br(Assembler::NE, is_null_free_array);
1907 }
1908
1909 void MacroAssembler::test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array) {
1910 tst(lh, Klass::_lh_null_free_array_bit_inplace);
1911 br(Assembler::EQ, is_non_null_free_array);
1912 }
1913
1914 // MacroAssembler protected routines needed to implement
1915 // public methods
1916
1917 void MacroAssembler::mov(Register r, Address dest) {
1918 code_section()->relocate(pc(), dest.rspec());
1919 uint64_t imm64 = (uint64_t)dest.target();
1920 movptr(r, imm64);
1921 }
1922
1923 // Move a constant pointer into r. In AArch64 mode the virtual
1924 // address space is 48 bits in size, so we only need three
1925 // instructions to create a patchable instruction sequence that can
1926 // reach anywhere.
1927 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1928 #ifndef PRODUCT
1929 {
1930 char buffer[64];
1931 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
1932 block_comment(buffer);
1933 }
4563 adrp(rscratch1, src2, offset);
4564 ldr(rscratch1, Address(rscratch1, offset));
4565 cmp(src1, rscratch1);
4566 }
4567
4568 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4569 cmp(obj1, obj2);
4570 }
4571
4572 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4573 load_method_holder(rresult, rmethod);
4574 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4575 }
4576
4577 void MacroAssembler::load_method_holder(Register holder, Register method) {
4578 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
4579 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
4580 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
4581 }
4582
4583 void MacroAssembler::load_metadata(Register dst, Register src) {
4584 if (UseCompressedClassPointers) {
4585 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4586 } else {
4587 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4588 }
4589 }
4590
4591 void MacroAssembler::load_klass(Register dst, Register src) {
4592 if (UseCompressedClassPointers) {
4593 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4594 decode_klass_not_null(dst);
4595 } else {
4596 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4597 }
4598 }
4599
4600 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
4601 if (RestoreMXCSROnJNICalls) {
4602 Label OK;
4603 get_fpcr(tmp1);
4604 mov(tmp2, tmp1);
4605 // Set FPCR to the state we need. We do want Round to Nearest. We
4606 // don't want non-IEEE rounding modes or floating-point traps.
4607 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
4608 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
4609 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
4610 eor(tmp2, tmp1, tmp2);
4646
4647 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
4648 if (UseCompressedClassPointers) {
4649 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4650 if (CompressedKlassPointers::base() == nullptr) {
4651 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
4652 return;
4653 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
4654 && CompressedKlassPointers::shift() == 0) {
4655 // Only the bottom 32 bits matter
4656 cmpw(trial_klass, tmp);
4657 return;
4658 }
4659 decode_klass_not_null(tmp);
4660 } else {
4661 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4662 }
4663 cmp(trial_klass, tmp);
4664 }
4665
4666 void MacroAssembler::load_prototype_header(Register dst, Register src) {
4667 load_klass(dst, src);
4668 ldr(dst, Address(dst, Klass::prototype_header_offset()));
4669 }
4670
4671 void MacroAssembler::store_klass(Register dst, Register src) {
4672 // FIXME: Should this be a store release? concurrent gcs assumes
4673 // klass length is valid if klass field is not null.
4674 if (UseCompressedClassPointers) {
4675 encode_klass_not_null(src);
4676 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4677 } else {
4678 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4679 }
4680 }
4681
4682 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4683 if (UseCompressedClassPointers) {
4684 // Store to klass gap in destination
4685 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
4686 }
4687 }
4688
4689 // Algorithm must match CompressedOops::encode.
4690 void MacroAssembler::encode_heap_oop(Register d, Register s) {
4975 if (as_raw) {
4976 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
4977 } else {
4978 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
4979 }
4980 }
4981
4982 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
4983 Address dst, Register val,
4984 Register tmp1, Register tmp2, Register tmp3) {
4985 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4986 decorators = AccessInternal::decorator_fixup(decorators, type);
4987 bool as_raw = (decorators & AS_RAW) != 0;
4988 if (as_raw) {
4989 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
4990 } else {
4991 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
4992 }
4993 }
4994
4995 void MacroAssembler::access_value_copy(DecoratorSet decorators, Register src, Register dst,
4996 Register inline_klass) {
4997 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4998 bs->value_copy(this, decorators, src, dst, inline_klass);
4999 }
5000
5001 void MacroAssembler::first_field_offset(Register inline_klass, Register offset) {
5002 ldr(offset, Address(inline_klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
5003 ldrw(offset, Address(offset, InlineKlass::first_field_offset_offset()));
5004 }
5005
5006 void MacroAssembler::data_for_oop(Register oop, Register data, Register inline_klass) {
5007 // ((address) (void*) o) + vk->first_field_offset();
5008 Register offset = (data == oop) ? rscratch1 : data;
5009 first_field_offset(inline_klass, offset);
5010 if (data == oop) {
5011 add(data, data, offset);
5012 } else {
5013 lea(data, Address(oop, offset));
5014 }
5015 }
5016
5017 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
5018 Register index, Register data) {
5019 assert_different_registers(array, array_klass, index);
5020 assert_different_registers(rscratch1, array, index);
5021
5022 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
5023 ldrw(rscratch1, Address(array_klass, Klass::layout_helper_offset()));
5024
5025 // Klass::layout_helper_log2_element_size(lh)
5026 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
5027 lsr(rscratch1, rscratch1, Klass::_lh_log2_element_size_shift);
5028 andr(rscratch1, rscratch1, Klass::_lh_log2_element_size_mask);
5029 lslv(index, index, rscratch1);
5030
5031 add(data, array, index);
5032 add(data, data, arrayOopDesc::base_offset_in_bytes(T_PRIMITIVE_OBJECT));
5033 }
5034
5035 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5036 Register tmp2, DecoratorSet decorators) {
5037 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5038 }
5039
5040 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5041 Register tmp2, DecoratorSet decorators) {
5042 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5043 }
5044
5045 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5046 Register tmp2, Register tmp3, DecoratorSet decorators) {
5047 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5048 }
5049
5050 // Used for storing nulls.
5051 void MacroAssembler::store_heap_oop_null(Address dst) {
5052 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5053 }
5054
5091 oop_index = oop_recorder()->allocate_metadata_index(obj);
5092 } else {
5093 oop_index = oop_recorder()->find_index(obj);
5094 }
5095 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5096 mov(dst, Address((address)obj, rspec));
5097 }
5098
5099 Address MacroAssembler::constant_oop_address(jobject obj) {
5100 #ifdef ASSERT
5101 {
5102 ThreadInVMfromUnknown tiv;
5103 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5104 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5105 }
5106 #endif
5107 int oop_index = oop_recorder()->find_index(obj);
5108 return Address((address)obj, oop_Relocation::spec(oop_index));
5109 }
5110
5111 // Object / value buffer allocation...
5112 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
5113 Register t1, Register t2,
5114 bool clear_fields, Label& alloc_failed)
5115 {
5116 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
5117 Register layout_size = t1;
5118 assert(new_obj == r0, "needs to be r0");
5119 assert_different_registers(klass, new_obj, t1, t2);
5120
5121 // get instance_size in InstanceKlass (scaled to a count of bytes)
5122 ldrw(layout_size, Address(klass, Klass::layout_helper_offset()));
5123 // test to see if it has a finalizer or is malformed in some way
5124 tst(layout_size, Klass::_lh_instance_slow_path_bit);
5125 br(Assembler::NE, slow_case_no_pop);
5126
5127 // Allocate the instance:
5128 // If TLAB is enabled:
5129 // Try to allocate in the TLAB.
5130 // If fails, go to the slow path.
5131 // Initialize the allocation.
5132 // Exit.
5133 //
5134 // Go to slow path.
5135
5136 if (UseTLAB) {
5137 push(klass);
5138 tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case);
5139 if (ZeroTLAB || (!clear_fields)) {
5140 // the fields have been already cleared
5141 b(initialize_header);
5142 } else {
5143 // initialize both the header and fields
5144 b(initialize_object);
5145 }
5146
5147 if (clear_fields) {
5148 // The object is initialized before the header. If the object size is
5149 // zero, go directly to the header initialization.
5150 bind(initialize_object);
5151 subs(layout_size, layout_size, sizeof(oopDesc));
5152 br(Assembler::EQ, initialize_header);
5153
5154 // Initialize topmost object field, divide size by 8, check if odd and
5155 // test if zero.
5156
5157 #ifdef ASSERT
5158 // make sure instance_size was multiple of 8
5159 Label L;
5160 tst(layout_size, 7);
5161 br(Assembler::EQ, L);
5162 stop("object size is not multiple of 8 - adjust this code");
5163 bind(L);
5164 // must be > 0, no extra check needed here
5165 #endif
5166
5167 lsr(layout_size, layout_size, LogBytesPerLong);
5168
5169 // initialize remaining object fields: instance_size was a multiple of 8
5170 {
5171 Label loop;
5172 Register base = t2;
5173
5174 bind(loop);
5175 add(rscratch1, new_obj, layout_size, Assembler::LSL, LogBytesPerLong);
5176 str(zr, Address(rscratch1, sizeof(oopDesc) - 1*oopSize));
5177 subs(layout_size, layout_size, 1);
5178 br(Assembler::NE, loop);
5179 }
5180 } // clear_fields
5181
5182 // initialize object header only.
5183 bind(initialize_header);
5184 pop(klass);
5185 Register mark_word = t2;
5186 ldr(mark_word, Address(klass, Klass::prototype_header_offset()));
5187 str(mark_word, Address(new_obj, oopDesc::mark_offset_in_bytes ()));
5188 store_klass_gap(new_obj, zr); // zero klass gap for compressed oops
5189 mov(t2, klass); // preserve klass
5190 store_klass(new_obj, t2); // src klass reg is potentially compressed
5191
5192 // TODO: Valhalla removed SharedRuntime::dtrace_object_alloc from here ?
5193
5194 b(done);
5195 }
5196
5197 if (UseTLAB) {
5198 bind(slow_case);
5199 pop(klass);
5200 }
5201 bind(slow_case_no_pop);
5202 b(alloc_failed);
5203
5204 bind(done);
5205 }
5206
5207 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5208 void MacroAssembler::tlab_allocate(Register obj,
5209 Register var_size_in_bytes,
5210 int con_size_in_bytes,
5211 Register t1,
5212 Register t2,
5213 Label& slow_case) {
5214 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5215 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5216 }
5217
5218 void MacroAssembler::verify_tlab() {
5219 #ifdef ASSERT
5220 if (UseTLAB && VerifyOops) {
5221 Label next, ok;
5222
5223 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5224
5225 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5226 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5227 cmp(rscratch2, rscratch1);
5228 br(Assembler::HS, next);
5229 STOP("assert(top >= start)");
5230 should_not_reach_here();
5231
5232 bind(next);
5233 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5234 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5235 cmp(rscratch2, rscratch1);
5236 br(Assembler::HS, ok);
5237 STOP("assert(top <= end)");
5238 should_not_reach_here();
5239
5240 bind(ok);
5241 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5242 }
5243 #endif
5244 }
5245
5246 void MacroAssembler::get_inline_type_field_klass(Register klass, Register index, Register inline_klass) {
5247 ldr(inline_klass, Address(klass, InstanceKlass::inline_type_field_klasses_offset()));
5248 #ifdef ASSERT
5249 {
5250 Label done;
5251 cbnz(inline_klass, done);
5252 stop("get_inline_type_field_klass contains no inline klass");
5253 bind(done);
5254 }
5255 #endif
5256 lea(inline_klass, Address(inline_klass, Array<InlineKlass*>::base_offset_in_bytes()));
5257 ldr(inline_klass, Address(inline_klass, index, Address::lsl(3)));
5258 }
5259
5260 // Writes to stack successive pages until offset reached to check for
5261 // stack overflow + shadow pages. This clobbers tmp.
5262 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5263 assert_different_registers(tmp, size, rscratch1);
5264 mov(tmp, sp);
5265 // Bang stack for total size given plus shadow page size.
5266 // Bang one page at a time because large size can bang beyond yellow and
5267 // red zones.
5268 Label loop;
5269 mov(rscratch1, (int)os::vm_page_size());
5270 bind(loop);
5271 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5272 subsw(size, size, rscratch1);
5273 str(size, Address(tmp));
5274 br(Assembler::GT, loop);
5275
5276 // Bang down shadow pages too.
5277 // At this point, (tmp-0) is the last address touched, so don't
5278 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5279 // was post-decremented.) Skip this address by starting at i=1, and
5365 }
5366
5367 void MacroAssembler::remove_frame(int framesize) {
5368 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5369 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5370 if (framesize < ((1 << 9) + 2 * wordSize)) {
5371 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5372 add(sp, sp, framesize);
5373 } else {
5374 if (framesize < ((1 << 12) + 2 * wordSize))
5375 add(sp, sp, framesize - 2 * wordSize);
5376 else {
5377 mov(rscratch1, framesize - 2 * wordSize);
5378 add(sp, sp, rscratch1);
5379 }
5380 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5381 }
5382 authenticate_return_address();
5383 }
5384
5385 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
5386 if (needs_stack_repair) {
5387 // Remove the extension of the caller's frame used for inline type unpacking
5388 //
5389 // Right now the stack looks like this:
5390 //
5391 // | Arguments from caller |
5392 // |---------------------------| <-- caller's SP
5393 // | Saved LR #1 |
5394 // | Saved FP #1 |
5395 // |---------------------------|
5396 // | Extension space for |
5397 // | inline arg (un)packing |
5398 // |---------------------------| <-- start of this method's frame
5399 // | Saved LR #2 |
5400 // | Saved FP #2 |
5401 // |---------------------------| <-- FP
5402 // | sp_inc |
5403 // | method locals |
5404 // |---------------------------| <-- SP
5405 //
5406 // There are two copies of FP and LR on the stack. They will be identical
5407 // unless the caller has been deoptimized, in which case LR #1 will be patched
5408 // to point at the deopt blob, and LR #2 will still point into the old method.
5409 //
5410 // The sp_inc stack slot holds the total size of the frame including the
5411 // extension space minus two words for the saved FP and LR.
5412
5413 int sp_inc_offset = initial_framesize - 3 * wordSize; // Immediately below saved LR and FP
5414
5415 ldr(rscratch1, Address(sp, sp_inc_offset));
5416 add(sp, sp, rscratch1);
5417 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5418 } else {
5419 remove_frame(initial_framesize);
5420 }
5421 }
5422
5423 void MacroAssembler::save_stack_increment(int sp_inc, int frame_size) {
5424 int real_frame_size = frame_size + sp_inc;
5425 assert(sp_inc == 0 || sp_inc > 2*wordSize, "invalid sp_inc value");
5426 assert(real_frame_size >= 2*wordSize, "frame size must include FP/LR space");
5427 assert((real_frame_size & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5428
5429 int sp_inc_offset = frame_size - 3 * wordSize; // Immediately below saved LR and FP
5430
5431 // Subtract two words for the saved FP and LR as these will be popped
5432 // separately. See remove_frame above.
5433 mov(rscratch1, real_frame_size - 2*wordSize);
5434 str(rscratch1, Address(sp, sp_inc_offset));
5435 }
5436
5437 // This method counts leading positive bytes (highest bit not set) in provided byte array
5438 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5439 // Simple and most common case of aligned small array which is not at the
5440 // end of memory page is placed here. All other cases are in stub.
5441 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5442 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5443 assert_different_registers(ary1, len, result);
5444
5445 mov(result, len);
5446 cmpw(len, 0);
5447 br(LE, DONE);
5448 cmpw(len, 4 * wordSize);
5449 br(GE, STUB_LONG); // size > 32 then go to stub
5450
5451 int shift = 64 - exact_log2(os::vm_page_size());
5452 lsl(rscratch1, ary1, shift);
5453 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5454 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5455 br(CS, STUB); // at the end of page then go to stub
6330 // On other systems, the helper is a usual C function.
6331 //
6332 void MacroAssembler::get_thread(Register dst) {
6333 RegSet saved_regs =
6334 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6335 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6336
6337 protect_return_address();
6338 push(saved_regs, sp);
6339
6340 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
6341 blr(lr);
6342 if (dst != c_rarg0) {
6343 mov(dst, c_rarg0);
6344 }
6345
6346 pop(saved_regs, sp);
6347 authenticate_return_address();
6348 }
6349
6350 #ifdef COMPILER2
6351 // C2 compiled method's prolog code
6352 // Moved here from aarch64.ad to support Valhalla code belows
6353 void MacroAssembler::verified_entry(Compile* C, int sp_inc) {
6354 if (C->clinit_barrier_on_entry()) {
6355 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
6356
6357 Label L_skip_barrier;
6358
6359 mov_metadata(rscratch2, C->method()->holder()->constant_encoding());
6360 clinit_barrier(rscratch2, rscratch1, &L_skip_barrier);
6361 far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
6362 bind(L_skip_barrier);
6363 }
6364
6365 if (C->max_vector_size() > 0) {
6366 reinitialize_ptrue();
6367 }
6368
6369 int bangsize = C->output()->bang_size_in_bytes();
6370 if (C->output()->need_stack_bang(bangsize))
6371 generate_stack_overflow_check(bangsize);
6372
6373 // n.b. frame size includes space for return pc and rfp
6374 const long framesize = C->output()->frame_size_in_bytes();
6375 build_frame(framesize);
6376
6377 if (C->needs_stack_repair()) {
6378 save_stack_increment(sp_inc, framesize);
6379 }
6380
6381 if (VerifyStackAtCalls) {
6382 Unimplemented();
6383 }
6384 }
6385 #endif // COMPILER2
6386
6387 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6388 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6389 // An inline type might be returned. If fields are in registers we
6390 // need to allocate an inline type instance and initialize it with
6391 // the value of the fields.
6392 Label skip;
6393 // We only need a new buffered inline type if a new one is not returned
6394 tbz(r0, 0, skip);
6395 int call_offset = -1;
6396
6397 // Be careful not to clobber r1-7 which hold returned fields
6398 // Also do not use callee-saved registers as these may be live in the interpreter
6399 Register tmp1 = r13, tmp2 = r14, klass = r15, r0_preserved = r12;
6400
6401 // The following code is similar to allocate_instance but has some slight differences,
6402 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6403 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
6404 Label slow_case;
6405 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6406 mov(r0_preserved, r0); // save r0 for slow_case since *_allocate may corrupt it when allocation failed
6407
6408 if (vk != nullptr) {
6409 // Called from C1, where the return type is statically known.
6410 movptr(klass, (intptr_t)vk->get_InlineKlass());
6411 jint obj_size = vk->layout_helper();
6412 assert(obj_size != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6413 if (UseTLAB) {
6414 tlab_allocate(r0, noreg, obj_size, tmp1, tmp2, slow_case);
6415 } else {
6416 b(slow_case);
6417 }
6418 } else {
6419 // Call from interpreter. R0 contains ((the InlineKlass* of the return type) | 0x01)
6420 andr(klass, r0, -2);
6421 ldrw(tmp2, Address(klass, Klass::layout_helper_offset()));
6422 if (UseTLAB) {
6423 tlab_allocate(r0, tmp2, 0, tmp1, tmp2, slow_case);
6424 } else {
6425 b(slow_case);
6426 }
6427 }
6428 if (UseTLAB) {
6429 // 2. Initialize buffered inline instance header
6430 Register buffer_obj = r0;
6431 mov(rscratch1, (intptr_t)markWord::inline_type_prototype().value());
6432 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes()));
6433 store_klass_gap(buffer_obj, zr);
6434 if (vk == nullptr) {
6435 // store_klass corrupts klass, so save it for later use (interpreter case only).
6436 mov(tmp1, klass);
6437 }
6438 store_klass(buffer_obj, klass);
6439 // 3. Initialize its fields with an inline class specific handler
6440 if (vk != nullptr) {
6441 far_call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6442 } else {
6443 // tmp1 holds klass preserved above
6444 ldr(tmp1, Address(tmp1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
6445 ldr(tmp1, Address(tmp1, InlineKlass::pack_handler_offset()));
6446 blr(tmp1);
6447 }
6448
6449 membar(Assembler::StoreStore);
6450 b(skip);
6451 } else {
6452 // Must have already branched to slow_case above.
6453 DEBUG_ONLY(should_not_reach_here());
6454 }
6455 bind(slow_case);
6456 // We failed to allocate a new inline type, fall back to a runtime
6457 // call. Some oop field may be live in some registers but we can't
6458 // tell. That runtime call will take care of preserving them
6459 // across a GC if there's one.
6460 mov(r0, r0_preserved);
6461
6462 if (from_interpreter) {
6463 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6464 } else {
6465 far_call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6466 call_offset = offset();
6467 }
6468 membar(Assembler::StoreStore);
6469
6470 bind(skip);
6471 return call_offset;
6472 }
6473
6474 // Move a value between registers/stack slots and update the reg_state
6475 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6476 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6477 if (reg_state[to->value()] == reg_written) {
6478 return true; // Already written
6479 }
6480
6481 if (from != to && bt != T_VOID) {
6482 if (reg_state[to->value()] == reg_readonly) {
6483 return false; // Not yet writable
6484 }
6485 if (from->is_reg()) {
6486 if (to->is_reg()) {
6487 if (from->is_Register() && to->is_Register()) {
6488 mov(to->as_Register(), from->as_Register());
6489 } else if (from->is_FloatRegister() && to->is_FloatRegister()) {
6490 fmovd(to->as_FloatRegister(), from->as_FloatRegister());
6491 } else {
6492 ShouldNotReachHere();
6493 }
6494 } else {
6495 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
6496 Address to_addr = Address(sp, st_off);
6497 if (from->is_FloatRegister()) {
6498 if (bt == T_DOUBLE) {
6499 strd(from->as_FloatRegister(), to_addr);
6500 } else {
6501 assert(bt == T_FLOAT, "must be float");
6502 strs(from->as_FloatRegister(), to_addr);
6503 }
6504 } else {
6505 str(from->as_Register(), to_addr);
6506 }
6507 }
6508 } else {
6509 Address from_addr = Address(sp, from->reg2stack() * VMRegImpl::stack_slot_size);
6510 if (to->is_reg()) {
6511 if (to->is_FloatRegister()) {
6512 if (bt == T_DOUBLE) {
6513 ldrd(to->as_FloatRegister(), from_addr);
6514 } else {
6515 assert(bt == T_FLOAT, "must be float");
6516 ldrs(to->as_FloatRegister(), from_addr);
6517 }
6518 } else {
6519 ldr(to->as_Register(), from_addr);
6520 }
6521 } else {
6522 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
6523 ldr(rscratch1, from_addr);
6524 str(rscratch1, Address(sp, st_off));
6525 }
6526 }
6527 }
6528
6529 // Update register states
6530 reg_state[from->value()] = reg_writable;
6531 reg_state[to->value()] = reg_written;
6532 return true;
6533 }
6534
6535 // Calculate the extra stack space required for packing or unpacking inline
6536 // args and adjust the stack pointer
6537 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6538 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
6539 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6540 assert(sp_inc > 0, "sanity");
6541
6542 // Save a copy of the FP and LR here for deoptimization patching and frame walking
6543 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6544
6545 // Adjust the stack pointer. This will be repaired on return by MacroAssembler::remove_frame
6546 if (sp_inc < (1 << 9)) {
6547 sub(sp, sp, sp_inc); // Fits in an immediate
6548 } else {
6549 mov(rscratch1, sp_inc);
6550 sub(sp, sp, rscratch1);
6551 }
6552
6553 return sp_inc + 2 * wordSize; // Account for the FP/LR space
6554 }
6555
6556 // Read all fields from an inline type oop and store the values in registers/stack slots
6557 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6558 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6559 RegState reg_state[]) {
6560 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6561 assert(from->is_valid(), "source must be valid");
6562 bool progress = false;
6563 #ifdef ASSERT
6564 const int start_offset = offset();
6565 #endif
6566
6567 Label L_null, L_notNull;
6568 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6569 Register tmp1 = r10;
6570 Register tmp2 = r11;
6571 Register fromReg = noreg;
6572 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
6573 bool done = true;
6574 bool mark_done = true;
6575 VMReg toReg;
6576 BasicType bt;
6577 // Check if argument requires a null check
6578 bool null_check = false;
6579 VMReg nullCheckReg;
6580 while (stream.next(nullCheckReg, bt)) {
6581 if (sig->at(stream.sig_index())._offset == -1) {
6582 null_check = true;
6583 break;
6584 }
6585 }
6586 stream.reset(sig_index, to_index);
6587 while (stream.next(toReg, bt)) {
6588 assert(toReg->is_valid(), "destination must be valid");
6589 int idx = (int)toReg->value();
6590 if (reg_state[idx] == reg_readonly) {
6591 if (idx != from->value()) {
6592 mark_done = false;
6593 }
6594 done = false;
6595 continue;
6596 } else if (reg_state[idx] == reg_written) {
6597 continue;
6598 }
6599 assert(reg_state[idx] == reg_writable, "must be writable");
6600 reg_state[idx] = reg_written;
6601 progress = true;
6602
6603 if (fromReg == noreg) {
6604 if (from->is_reg()) {
6605 fromReg = from->as_Register();
6606 } else {
6607 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size;
6608 ldr(tmp1, Address(sp, st_off));
6609 fromReg = tmp1;
6610 }
6611 if (null_check) {
6612 // Nullable inline type argument, emit null check
6613 cbz(fromReg, L_null);
6614 }
6615 }
6616 int off = sig->at(stream.sig_index())._offset;
6617 if (off == -1) {
6618 assert(null_check, "Missing null check at");
6619 if (toReg->is_stack()) {
6620 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
6621 mov(tmp2, 1);
6622 str(tmp2, Address(sp, st_off));
6623 } else {
6624 mov(toReg->as_Register(), 1);
6625 }
6626 continue;
6627 }
6628 assert(off > 0, "offset in object should be positive");
6629 Address fromAddr = Address(fromReg, off);
6630 if (!toReg->is_FloatRegister()) {
6631 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
6632 if (is_reference_type(bt)) {
6633 load_heap_oop(dst, fromAddr, rscratch1, rscratch2);
6634 } else {
6635 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
6636 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
6637 }
6638 if (toReg->is_stack()) {
6639 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
6640 str(dst, Address(sp, st_off));
6641 }
6642 } else if (bt == T_DOUBLE) {
6643 ldrd(toReg->as_FloatRegister(), fromAddr);
6644 } else {
6645 assert(bt == T_FLOAT, "must be float");
6646 ldrs(toReg->as_FloatRegister(), fromAddr);
6647 }
6648 }
6649 if (progress && null_check) {
6650 if (done) {
6651 b(L_notNull);
6652 bind(L_null);
6653 // Set IsInit field to zero to signal that the argument is null.
6654 // Also set all oop fields to zero to make the GC happy.
6655 stream.reset(sig_index, to_index);
6656 while (stream.next(toReg, bt)) {
6657 if (sig->at(stream.sig_index())._offset == -1 ||
6658 bt == T_OBJECT || bt == T_ARRAY) {
6659 if (toReg->is_stack()) {
6660 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
6661 str(zr, Address(sp, st_off));
6662 } else {
6663 mov(toReg->as_Register(), zr);
6664 }
6665 }
6666 }
6667 bind(L_notNull);
6668 } else {
6669 bind(L_null);
6670 }
6671 }
6672
6673 sig_index = stream.sig_index();
6674 to_index = stream.regs_index();
6675
6676 if (mark_done && reg_state[from->value()] != reg_written) {
6677 // This is okay because no one else will write to that slot
6678 reg_state[from->value()] = reg_writable;
6679 }
6680 from_index--;
6681 assert(progress || (start_offset == offset()), "should not emit code");
6682 return done;
6683 }
6684
6685 // Pack fields back into an inline type oop
6686 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
6687 VMRegPair* from, int from_count, int& from_index, VMReg to,
6688 RegState reg_state[], Register val_array) {
6689 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
6690 assert(to->is_valid(), "destination must be valid");
6691
6692 if (reg_state[to->value()] == reg_written) {
6693 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6694 return true; // Already written
6695 }
6696
6697 // The GC barrier expanded by store_heap_oop below may call into the
6698 // runtime so use callee-saved registers for any values that need to be
6699 // preserved. The GC barrier assembler should take care of saving the
6700 // Java argument registers.
6701 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
6702 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
6703 Register val_obj_tmp = r21;
6704 Register from_reg_tmp = r22;
6705 Register tmp1 = r14;
6706 Register tmp2 = r13;
6707 Register tmp3 = r12;
6708 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
6709
6710 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
6711
6712 if (reg_state[to->value()] == reg_readonly) {
6713 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
6714 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6715 return false; // Not yet writable
6716 }
6717 val_obj = val_obj_tmp;
6718 }
6719
6720 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
6721 load_heap_oop(val_obj, Address(val_array, index), tmp1, tmp2);
6722
6723 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
6724 VMReg fromReg;
6725 BasicType bt;
6726 Label L_null;
6727 while (stream.next(fromReg, bt)) {
6728 assert(fromReg->is_valid(), "source must be valid");
6729 reg_state[fromReg->value()] = reg_writable;
6730
6731 int off = sig->at(stream.sig_index())._offset;
6732 if (off == -1) {
6733 // Nullable inline type argument, emit null check
6734 Label L_notNull;
6735 if (fromReg->is_stack()) {
6736 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
6737 ldrb(tmp2, Address(sp, ld_off));
6738 cbnz(tmp2, L_notNull);
6739 } else {
6740 cbnz(fromReg->as_Register(), L_notNull);
6741 }
6742 mov(val_obj, 0);
6743 b(L_null);
6744 bind(L_notNull);
6745 continue;
6746 }
6747
6748 assert(off > 0, "offset in object should be positive");
6749 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
6750
6751 // Pack the scalarized field into the value object.
6752 Address dst(val_obj, off);
6753
6754 if (!fromReg->is_FloatRegister()) {
6755 Register src;
6756 if (fromReg->is_stack()) {
6757 src = from_reg_tmp;
6758 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
6759 load_sized_value(src, Address(sp, ld_off), size_in_bytes, /* is_signed */ false);
6760 } else {
6761 src = fromReg->as_Register();
6762 }
6763 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
6764 if (is_reference_type(bt)) {
6765 store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
6766 } else {
6767 store_sized_value(dst, src, size_in_bytes);
6768 }
6769 } else if (bt == T_DOUBLE) {
6770 strd(fromReg->as_FloatRegister(), dst);
6771 } else {
6772 assert(bt == T_FLOAT, "must be float");
6773 strs(fromReg->as_FloatRegister(), dst);
6774 }
6775 }
6776 bind(L_null);
6777 sig_index = stream.sig_index();
6778 from_index = stream.regs_index();
6779
6780 assert(reg_state[to->value()] == reg_writable, "must have already been read");
6781 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6782 assert(success, "to register must be writeable");
6783
6784 return true;
6785 }
6786
6787 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6788 return (reg->is_FloatRegister()) ? v8->as_VMReg() : r14->as_VMReg();
6789 }
6790
6791 void MacroAssembler::cache_wb(Address line) {
6792 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6793 assert(line.index() == noreg, "index should be noreg");
6794 assert(line.offset() == 0, "offset should be 0");
6795 // would like to assert this
6796 // assert(line._ext.shift == 0, "shift should be zero");
6797 if (VM_Version::supports_dcpop()) {
6798 // writeback using clear virtual address to point of persistence
6799 dc(Assembler::CVAP, line.base());
6800 } else {
6801 // no need to generate anything as Unsafe.writebackMemory should
6802 // never invoke this stub
6803 }
6804 }
6805
6806 void MacroAssembler::cache_wbsync(bool is_pre) {
6807 // we only need a barrier post sync
6808 if (!is_pre) {
6809 membar(Assembler::AnyAny);
6810 }
7144 }
7145
7146 // Implements lightweight-locking.
7147 // Branches to slow upon failure to lock the object, with ZF cleared.
7148 // Falls through upon success with ZF set.
7149 //
7150 // - obj: the object to be locked
7151 // - hdr: the header, already loaded from obj, will be destroyed
7152 // - t1, t2: temporary registers, will be destroyed
7153 void MacroAssembler::lightweight_lock(Register obj, Register hdr, Register t1, Register t2, Label& slow) {
7154 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
7155 assert_different_registers(obj, hdr, t1, t2, rscratch1);
7156
7157 // Check if we would have space on lock-stack for the object.
7158 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7159 cmpw(t1, (unsigned)LockStack::end_offset() - 1);
7160 br(Assembler::GT, slow);
7161
7162 // Load (object->mark() | 1) into hdr
7163 orr(hdr, hdr, markWord::unlocked_value);
7164 if (EnableValhalla) {
7165 // Mask inline_type bit such that we go to the slow path if object is an inline type
7166 andr(hdr, hdr, ~((int) markWord::inline_type_bit_in_place));
7167 }
7168
7169 // Clear lock-bits, into t2
7170 eor(t2, hdr, markWord::unlocked_value);
7171 // Try to swing header from unlocked to locked
7172 // Clobbers rscratch1 when UseLSE is false
7173 cmpxchg(/*addr*/ obj, /*expected*/ hdr, /*new*/ t2, Assembler::xword,
7174 /*acquire*/ true, /*release*/ true, /*weak*/ false, t1);
7175 br(Assembler::NE, slow);
7176
7177 // After successful lock, push object on lock-stack
7178 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7179 str(obj, Address(rthread, t1));
7180 addw(t1, t1, oopSize);
7181 strw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7182 }
7183
7184 // Implements lightweight-unlocking.
7185 // Branches to slow upon failure, with ZF cleared.
7186 // Falls through upon success, with ZF set.
7187 //
7188 // - obj: the object to be unlocked
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