10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "ci/ciEnv.hpp"
30 #include "code/compiledIC.hpp"
31 #include "compiler/compileTask.hpp"
32 #include "compiler/disassembler.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "gc/shared/barrierSet.hpp"
35 #include "gc/shared/barrierSetAssembler.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/cardTable.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/tlab_globals.hpp"
40 #include "interpreter/bytecodeHistogram.hpp"
41 #include "interpreter/interpreter.hpp"
42 #include "jvm.h"
43 #include "memory/resourceArea.hpp"
44 #include "memory/universe.hpp"
45 #include "nativeInst_aarch64.hpp"
46 #include "oops/accessDecorators.hpp"
47 #include "oops/compressedKlass.inline.hpp"
48 #include "oops/compressedOops.inline.hpp"
49 #include "oops/klass.inline.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/icache.hpp"
52 #include "runtime/interfaceSupport.inline.hpp"
53 #include "runtime/javaThread.hpp"
54 #include "runtime/jniHandles.inline.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/globalDefinitions.hpp"
58 #include "utilities/powerOfTwo.hpp"
59 #ifdef COMPILER1
60 #include "c1/c1_LIRAssembler.hpp"
61 #endif
62 #ifdef COMPILER2
63 #include "oops/oop.hpp"
64 #include "opto/compile.hpp"
65 #include "opto/node.hpp"
66 #include "opto/output.hpp"
67 #endif
68
69 #include <sys/types.h>
70
71 #ifdef PRODUCT
72 #define BLOCK_COMMENT(str) /* nothing */
73 #else
74 #define BLOCK_COMMENT(str) block_comment(str)
75 #endif
76 #define STOP(str) stop(str);
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
1154 }
1155
1156 void MacroAssembler::post_call_nop() {
1157 if (!Continuations::enabled()) {
1158 return;
1159 }
1160 InstructionMark im(this);
1161 relocate(post_call_nop_Relocation::spec());
1162 InlineSkippedInstructionsCounter skipCounter(this);
1163 nop();
1164 movk(zr, 0);
1165 movk(zr, 0);
1166 }
1167
1168 // these are no-ops overridden by InterpreterMacroAssembler
1169
1170 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1171
1172 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1173
1174 // Look up the method for a megamorphic invokeinterface call.
1175 // The target method is determined by <intf_klass, itable_index>.
1176 // The receiver klass is in recv_klass.
1177 // On success, the result will be in method_result, and execution falls through.
1178 // On failure, execution transfers to the given label.
1179 void MacroAssembler::lookup_interface_method(Register recv_klass,
1180 Register intf_klass,
1181 RegisterOrConstant itable_index,
1182 Register method_result,
1183 Register scan_temp,
1184 Label& L_no_such_interface,
1185 bool return_method) {
1186 assert_different_registers(recv_klass, intf_klass, scan_temp);
1187 assert_different_registers(method_result, intf_klass, scan_temp);
1188 assert(recv_klass != method_result || !return_method,
1189 "recv_klass can be destroyed when method isn't needed");
1190 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1191 "caller must use same register for non-constant itable index as for method");
1192
1193 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1841 ldrb(scratch, Address(klass, InstanceKlass::init_state_offset()));
1842 subs(zr, scratch, InstanceKlass::fully_initialized);
1843 br(Assembler::EQ, *L_fast_path);
1844
1845 // Fast path check: current thread is initializer thread
1846 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
1847 cmp(rthread, scratch);
1848
1849 if (L_slow_path == &L_fallthrough) {
1850 br(Assembler::EQ, *L_fast_path);
1851 bind(*L_slow_path);
1852 } else if (L_fast_path == &L_fallthrough) {
1853 br(Assembler::NE, *L_slow_path);
1854 bind(*L_fast_path);
1855 } else {
1856 Unimplemented();
1857 }
1858 }
1859
1860 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
1861 if (!VerifyOops) return;
1862
1863 // Pass register number to verify_oop_subroutine
1864 const char* b = nullptr;
1865 {
1866 ResourceMark rm;
1867 stringStream ss;
1868 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
1869 b = code_string(ss.as_string());
1870 }
1871 BLOCK_COMMENT("verify_oop {");
1872
1873 strip_return_address(); // This might happen within a stack frame.
1874 protect_return_address();
1875 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1876 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1877
1878 mov(r0, reg);
1879 movptr(rscratch1, (uintptr_t)(address)b);
1880
1881 // call indirectly to solve generation ordering problem
1882 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1883 ldr(rscratch2, Address(rscratch2));
1884 blr(rscratch2);
1885
1886 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1887 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1888 authenticate_return_address();
1889
1890 BLOCK_COMMENT("} verify_oop");
1891 }
1892
1893 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
1894 if (!VerifyOops) return;
1895
1896 const char* b = nullptr;
1897 {
1898 ResourceMark rm;
1899 stringStream ss;
1900 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
1901 b = code_string(ss.as_string());
1902 }
1903 BLOCK_COMMENT("verify_oop_addr {");
1904
1905 strip_return_address(); // This might happen within a stack frame.
1906 protect_return_address();
1907 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1908 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1909
1910 // addr may contain sp so we will have to adjust it based on the
1911 // pushes that we just did.
1912 if (addr.uses(sp)) {
1913 lea(r0, addr);
1914 ldr(r0, Address(r0, 4 * wordSize));
1972 call_VM_leaf_base(entry_point, 1);
1973 }
1974
1975 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1976 assert_different_registers(arg_1, c_rarg0);
1977 pass_arg0(this, arg_0);
1978 pass_arg1(this, arg_1);
1979 call_VM_leaf_base(entry_point, 2);
1980 }
1981
1982 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1983 Register arg_1, Register arg_2) {
1984 assert_different_registers(arg_1, c_rarg0);
1985 assert_different_registers(arg_2, c_rarg0, c_rarg1);
1986 pass_arg0(this, arg_0);
1987 pass_arg1(this, arg_1);
1988 pass_arg2(this, arg_2);
1989 call_VM_leaf_base(entry_point, 3);
1990 }
1991
1992 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1993 pass_arg0(this, arg_0);
1994 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1995 }
1996
1997 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1998
1999 assert_different_registers(arg_0, c_rarg1);
2000 pass_arg1(this, arg_1);
2001 pass_arg0(this, arg_0);
2002 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2003 }
2004
2005 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2006 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2007 assert_different_registers(arg_1, c_rarg2);
2008 pass_arg2(this, arg_2);
2009 pass_arg1(this, arg_1);
2010 pass_arg0(this, arg_0);
2011 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2017 assert_different_registers(arg_2, c_rarg3);
2018 pass_arg3(this, arg_3);
2019 pass_arg2(this, arg_2);
2020 pass_arg1(this, arg_1);
2021 pass_arg0(this, arg_0);
2022 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2023 }
2024
2025 void MacroAssembler::null_check(Register reg, int offset) {
2026 if (needs_explicit_null_check(offset)) {
2027 // provoke OS null exception if reg is null by
2028 // accessing M[reg] w/o changing any registers
2029 // NOTE: this is plenty to provoke a segv
2030 ldr(zr, Address(reg));
2031 } else {
2032 // nothing to do, (later) access of M[reg + offset]
2033 // will provoke OS null exception if reg is null
2034 }
2035 }
2036
2037 // MacroAssembler protected routines needed to implement
2038 // public methods
2039
2040 void MacroAssembler::mov(Register r, Address dest) {
2041 code_section()->relocate(pc(), dest.rspec());
2042 uint64_t imm64 = (uint64_t)dest.target();
2043 movptr(r, imm64);
2044 }
2045
2046 // Move a constant pointer into r. In AArch64 mode the virtual
2047 // address space is 48 bits in size, so we only need three
2048 // instructions to create a patchable instruction sequence that can
2049 // reach anywhere.
2050 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2051 #ifndef PRODUCT
2052 {
2053 char buffer[64];
2054 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2055 block_comment(buffer);
2056 }
4821 adrp(rscratch1, src2, offset);
4822 ldr(rscratch1, Address(rscratch1, offset));
4823 cmp(src1, rscratch1);
4824 }
4825
4826 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4827 cmp(obj1, obj2);
4828 }
4829
4830 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4831 load_method_holder(rresult, rmethod);
4832 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4833 }
4834
4835 void MacroAssembler::load_method_holder(Register holder, Register method) {
4836 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
4837 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
4838 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
4839 }
4840
4841 void MacroAssembler::load_klass(Register dst, Register src) {
4842 if (UseCompressedClassPointers) {
4843 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4844 decode_klass_not_null(dst);
4845 } else {
4846 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4847 }
4848 }
4849
4850 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
4851 if (RestoreMXCSROnJNICalls) {
4852 Label OK;
4853 get_fpcr(tmp1);
4854 mov(tmp2, tmp1);
4855 // Set FPCR to the state we need. We do want Round to Nearest. We
4856 // don't want non-IEEE rounding modes or floating-point traps.
4857 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
4858 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
4859 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
4860 eor(tmp2, tmp1, tmp2);
4896
4897 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
4898 if (UseCompressedClassPointers) {
4899 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4900 if (CompressedKlassPointers::base() == nullptr) {
4901 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
4902 return;
4903 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
4904 && CompressedKlassPointers::shift() == 0) {
4905 // Only the bottom 32 bits matter
4906 cmpw(trial_klass, tmp);
4907 return;
4908 }
4909 decode_klass_not_null(tmp);
4910 } else {
4911 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4912 }
4913 cmp(trial_klass, tmp);
4914 }
4915
4916 void MacroAssembler::store_klass(Register dst, Register src) {
4917 // FIXME: Should this be a store release? concurrent gcs assumes
4918 // klass length is valid if klass field is not null.
4919 if (UseCompressedClassPointers) {
4920 encode_klass_not_null(src);
4921 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4922 } else {
4923 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4924 }
4925 }
4926
4927 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4928 if (UseCompressedClassPointers) {
4929 // Store to klass gap in destination
4930 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
4931 }
4932 }
4933
4934 // Algorithm must match CompressedOops::encode.
4935 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5220 if (as_raw) {
5221 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5222 } else {
5223 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5224 }
5225 }
5226
5227 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5228 Address dst, Register val,
5229 Register tmp1, Register tmp2, Register tmp3) {
5230 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5231 decorators = AccessInternal::decorator_fixup(decorators, type);
5232 bool as_raw = (decorators & AS_RAW) != 0;
5233 if (as_raw) {
5234 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5235 } else {
5236 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5237 }
5238 }
5239
5240 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5241 Register tmp2, DecoratorSet decorators) {
5242 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5243 }
5244
5245 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5246 Register tmp2, DecoratorSet decorators) {
5247 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5248 }
5249
5250 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5251 Register tmp2, Register tmp3, DecoratorSet decorators) {
5252 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5253 }
5254
5255 // Used for storing nulls.
5256 void MacroAssembler::store_heap_oop_null(Address dst) {
5257 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5258 }
5259
5296 oop_index = oop_recorder()->allocate_metadata_index(obj);
5297 } else {
5298 oop_index = oop_recorder()->find_index(obj);
5299 }
5300 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5301 mov(dst, Address((address)obj, rspec));
5302 }
5303
5304 Address MacroAssembler::constant_oop_address(jobject obj) {
5305 #ifdef ASSERT
5306 {
5307 ThreadInVMfromUnknown tiv;
5308 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5309 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5310 }
5311 #endif
5312 int oop_index = oop_recorder()->find_index(obj);
5313 return Address((address)obj, oop_Relocation::spec(oop_index));
5314 }
5315
5316 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5317 void MacroAssembler::tlab_allocate(Register obj,
5318 Register var_size_in_bytes,
5319 int con_size_in_bytes,
5320 Register t1,
5321 Register t2,
5322 Label& slow_case) {
5323 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5324 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5325 }
5326
5327 void MacroAssembler::verify_tlab() {
5328 #ifdef ASSERT
5329 if (UseTLAB && VerifyOops) {
5330 Label next, ok;
5331
5332 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5333
5334 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5335 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5336 cmp(rscratch2, rscratch1);
5337 br(Assembler::HS, next);
5338 STOP("assert(top >= start)");
5339 should_not_reach_here();
5340
5341 bind(next);
5342 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5343 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5344 cmp(rscratch2, rscratch1);
5345 br(Assembler::HS, ok);
5346 STOP("assert(top <= end)");
5347 should_not_reach_here();
5348
5349 bind(ok);
5350 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5351 }
5352 #endif
5353 }
5354
5355 // Writes to stack successive pages until offset reached to check for
5356 // stack overflow + shadow pages. This clobbers tmp.
5357 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5358 assert_different_registers(tmp, size, rscratch1);
5359 mov(tmp, sp);
5360 // Bang stack for total size given plus shadow page size.
5361 // Bang one page at a time because large size can bang beyond yellow and
5362 // red zones.
5363 Label loop;
5364 mov(rscratch1, (int)os::vm_page_size());
5365 bind(loop);
5366 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5367 subsw(size, size, rscratch1);
5368 str(size, Address(tmp));
5369 br(Assembler::GT, loop);
5370
5371 // Bang down shadow pages too.
5372 // At this point, (tmp-0) is the last address touched, so don't
5373 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5374 // was post-decremented.) Skip this address by starting at i=1, and
5460 }
5461
5462 void MacroAssembler::remove_frame(int framesize) {
5463 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5464 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5465 if (framesize < ((1 << 9) + 2 * wordSize)) {
5466 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5467 add(sp, sp, framesize);
5468 } else {
5469 if (framesize < ((1 << 12) + 2 * wordSize))
5470 add(sp, sp, framesize - 2 * wordSize);
5471 else {
5472 mov(rscratch1, framesize - 2 * wordSize);
5473 add(sp, sp, rscratch1);
5474 }
5475 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5476 }
5477 authenticate_return_address();
5478 }
5479
5480
5481 // This method counts leading positive bytes (highest bit not set) in provided byte array
5482 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5483 // Simple and most common case of aligned small array which is not at the
5484 // end of memory page is placed here. All other cases are in stub.
5485 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5486 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5487 assert_different_registers(ary1, len, result);
5488
5489 mov(result, len);
5490 cmpw(len, 0);
5491 br(LE, DONE);
5492 cmpw(len, 4 * wordSize);
5493 br(GE, STUB_LONG); // size > 32 then go to stub
5494
5495 int shift = 64 - exact_log2(os::vm_page_size());
5496 lsl(rscratch1, ary1, shift);
5497 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5498 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5499 br(CS, STUB); // at the end of page then go to stub
6373 // On other systems, the helper is a usual C function.
6374 //
6375 void MacroAssembler::get_thread(Register dst) {
6376 RegSet saved_regs =
6377 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6378 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6379
6380 protect_return_address();
6381 push(saved_regs, sp);
6382
6383 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
6384 blr(lr);
6385 if (dst != c_rarg0) {
6386 mov(dst, c_rarg0);
6387 }
6388
6389 pop(saved_regs, sp);
6390 authenticate_return_address();
6391 }
6392
6393 void MacroAssembler::cache_wb(Address line) {
6394 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6395 assert(line.index() == noreg, "index should be noreg");
6396 assert(line.offset() == 0, "offset should be 0");
6397 // would like to assert this
6398 // assert(line._ext.shift == 0, "shift should be zero");
6399 if (VM_Version::supports_dcpop()) {
6400 // writeback using clear virtual address to point of persistence
6401 dc(Assembler::CVAP, line.base());
6402 } else {
6403 // no need to generate anything as Unsafe.writebackMemory should
6404 // never invoke this stub
6405 }
6406 }
6407
6408 void MacroAssembler::cache_wbsync(bool is_pre) {
6409 // we only need a barrier post sync
6410 if (!is_pre) {
6411 membar(Assembler::AnyAny);
6412 }
6771 }
6772
6773 // Check if the lock-stack is full.
6774 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6775 cmpw(top, (unsigned)LockStack::end_offset());
6776 br(Assembler::GE, slow);
6777
6778 // Check for recursion.
6779 subw(t, top, oopSize);
6780 ldr(t, Address(rthread, t));
6781 cmp(obj, t);
6782 br(Assembler::EQ, push);
6783
6784 // Check header for monitor (0b10).
6785 tst(mark, markWord::monitor_value);
6786 br(Assembler::NE, slow);
6787
6788 // Try to lock. Transition lock bits 0b01 => 0b00
6789 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
6790 orr(mark, mark, markWord::unlocked_value);
6791 eor(t, mark, markWord::unlocked_value);
6792 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
6793 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
6794 br(Assembler::NE, slow);
6795
6796 bind(push);
6797 // After successful lock, push object on lock-stack.
6798 str(obj, Address(rthread, top));
6799 addw(top, top, oopSize);
6800 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6801 }
6802
6803 // Implements lightweight-unlocking.
6804 //
6805 // - obj: the object to be unlocked
6806 // - t1, t2, t3: temporary registers
6807 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
6808 void MacroAssembler::lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
6809 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
6810 // cmpxchg clobbers rscratch1.
|
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "ci/ciEnv.hpp"
30 #include "ci/ciInlineKlass.hpp"
31 #include "code/compiledIC.hpp"
32 #include "compiler/compileTask.hpp"
33 #include "compiler/disassembler.hpp"
34 #include "compiler/oopMap.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/barrierSetAssembler.hpp"
37 #include "gc/shared/cardTableBarrierSet.hpp"
38 #include "gc/shared/cardTable.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/tlab_globals.hpp"
41 #include "interpreter/bytecodeHistogram.hpp"
42 #include "interpreter/interpreter.hpp"
43 #include "jvm.h"
44 #include "memory/resourceArea.hpp"
45 #include "memory/universe.hpp"
46 #include "nativeInst_aarch64.hpp"
47 #include "oops/accessDecorators.hpp"
48 #include "oops/compressedKlass.inline.hpp"
49 #include "oops/compressedOops.inline.hpp"
50 #include "oops/klass.inline.hpp"
51 #include "oops/resolvedFieldEntry.hpp"
52 #include "runtime/continuation.hpp"
53 #include "runtime/icache.hpp"
54 #include "runtime/interfaceSupport.inline.hpp"
55 #include "runtime/javaThread.hpp"
56 #include "runtime/jniHandles.inline.hpp"
57 #include "runtime/sharedRuntime.hpp"
58 #include "runtime/signature_cc.hpp"
59 #include "runtime/stubRoutines.hpp"
60 #include "utilities/globalDefinitions.hpp"
61 #include "utilities/powerOfTwo.hpp"
62 #include "vmreg_aarch64.inline.hpp"
63 #ifdef COMPILER1
64 #include "c1/c1_LIRAssembler.hpp"
65 #endif
66 #ifdef COMPILER2
67 #include "oops/oop.hpp"
68 #include "opto/compile.hpp"
69 #include "opto/node.hpp"
70 #include "opto/output.hpp"
71 #endif
72
73 #include <sys/types.h>
74
75 #ifdef PRODUCT
76 #define BLOCK_COMMENT(str) /* nothing */
77 #else
78 #define BLOCK_COMMENT(str) block_comment(str)
79 #endif
80 #define STOP(str) stop(str);
81 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
82
1158 }
1159
1160 void MacroAssembler::post_call_nop() {
1161 if (!Continuations::enabled()) {
1162 return;
1163 }
1164 InstructionMark im(this);
1165 relocate(post_call_nop_Relocation::spec());
1166 InlineSkippedInstructionsCounter skipCounter(this);
1167 nop();
1168 movk(zr, 0);
1169 movk(zr, 0);
1170 }
1171
1172 // these are no-ops overridden by InterpreterMacroAssembler
1173
1174 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1175
1176 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1177
1178 void MacroAssembler::get_default_value_oop(Register inline_klass, Register temp_reg, Register obj) {
1179 #ifdef ASSERT
1180 {
1181 Label done_check;
1182 test_klass_is_inline_type(inline_klass, temp_reg, done_check);
1183 stop("get_default_value_oop from non inline type klass");
1184 bind(done_check);
1185 }
1186 #endif
1187 Register offset = temp_reg;
1188 // Getting the offset of the pre-allocated default value
1189 ldr(offset, Address(inline_klass, in_bytes(InstanceKlass::adr_inlineklass_fixed_block_offset())));
1190 ldr(offset, Address(offset, in_bytes(InlineKlass::default_value_offset_offset())));
1191
1192 // Getting the mirror
1193 ldr(obj, Address(inline_klass, in_bytes(Klass::java_mirror_offset())));
1194 resolve_oop_handle(obj, inline_klass, temp_reg);
1195
1196 // Getting the pre-allocated default value from the mirror
1197 Address field(obj, offset);
1198 load_heap_oop(obj, field, inline_klass, rscratch2);
1199 }
1200
1201 void MacroAssembler::get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj) {
1202 #ifdef ASSERT
1203 {
1204 Label done_check;
1205 test_klass_is_empty_inline_type(inline_klass, temp_reg, done_check);
1206 stop("get_empty_value from non-empty inline klass");
1207 bind(done_check);
1208 }
1209 #endif
1210 get_default_value_oop(inline_klass, temp_reg, obj);
1211 }
1212
1213 // Look up the method for a megamorphic invokeinterface call.
1214 // The target method is determined by <intf_klass, itable_index>.
1215 // The receiver klass is in recv_klass.
1216 // On success, the result will be in method_result, and execution falls through.
1217 // On failure, execution transfers to the given label.
1218 void MacroAssembler::lookup_interface_method(Register recv_klass,
1219 Register intf_klass,
1220 RegisterOrConstant itable_index,
1221 Register method_result,
1222 Register scan_temp,
1223 Label& L_no_such_interface,
1224 bool return_method) {
1225 assert_different_registers(recv_klass, intf_klass, scan_temp);
1226 assert_different_registers(method_result, intf_klass, scan_temp);
1227 assert(recv_klass != method_result || !return_method,
1228 "recv_klass can be destroyed when method isn't needed");
1229 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1230 "caller must use same register for non-constant itable index as for method");
1231
1232 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1880 ldrb(scratch, Address(klass, InstanceKlass::init_state_offset()));
1881 subs(zr, scratch, InstanceKlass::fully_initialized);
1882 br(Assembler::EQ, *L_fast_path);
1883
1884 // Fast path check: current thread is initializer thread
1885 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
1886 cmp(rthread, scratch);
1887
1888 if (L_slow_path == &L_fallthrough) {
1889 br(Assembler::EQ, *L_fast_path);
1890 bind(*L_slow_path);
1891 } else if (L_fast_path == &L_fallthrough) {
1892 br(Assembler::NE, *L_slow_path);
1893 bind(*L_fast_path);
1894 } else {
1895 Unimplemented();
1896 }
1897 }
1898
1899 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
1900 if (!VerifyOops || VerifyAdapterSharing) {
1901 // Below address of the code string confuses VerifyAdapterSharing
1902 // because it may differ between otherwise equivalent adapters.
1903 return;
1904 }
1905
1906 // Pass register number to verify_oop_subroutine
1907 const char* b = nullptr;
1908 {
1909 ResourceMark rm;
1910 stringStream ss;
1911 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
1912 b = code_string(ss.as_string());
1913 }
1914 BLOCK_COMMENT("verify_oop {");
1915
1916 strip_return_address(); // This might happen within a stack frame.
1917 protect_return_address();
1918 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1919 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1920
1921 mov(r0, reg);
1922 movptr(rscratch1, (uintptr_t)(address)b);
1923
1924 // call indirectly to solve generation ordering problem
1925 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1926 ldr(rscratch2, Address(rscratch2));
1927 blr(rscratch2);
1928
1929 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1930 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1931 authenticate_return_address();
1932
1933 BLOCK_COMMENT("} verify_oop");
1934 }
1935
1936 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
1937 if (!VerifyOops || VerifyAdapterSharing) {
1938 // Below address of the code string confuses VerifyAdapterSharing
1939 // because it may differ between otherwise equivalent adapters.
1940 return;
1941 }
1942
1943 const char* b = nullptr;
1944 {
1945 ResourceMark rm;
1946 stringStream ss;
1947 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
1948 b = code_string(ss.as_string());
1949 }
1950 BLOCK_COMMENT("verify_oop_addr {");
1951
1952 strip_return_address(); // This might happen within a stack frame.
1953 protect_return_address();
1954 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1955 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1956
1957 // addr may contain sp so we will have to adjust it based on the
1958 // pushes that we just did.
1959 if (addr.uses(sp)) {
1960 lea(r0, addr);
1961 ldr(r0, Address(r0, 4 * wordSize));
2019 call_VM_leaf_base(entry_point, 1);
2020 }
2021
2022 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2023 assert_different_registers(arg_1, c_rarg0);
2024 pass_arg0(this, arg_0);
2025 pass_arg1(this, arg_1);
2026 call_VM_leaf_base(entry_point, 2);
2027 }
2028
2029 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2030 Register arg_1, Register arg_2) {
2031 assert_different_registers(arg_1, c_rarg0);
2032 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2033 pass_arg0(this, arg_0);
2034 pass_arg1(this, arg_1);
2035 pass_arg2(this, arg_2);
2036 call_VM_leaf_base(entry_point, 3);
2037 }
2038
2039 void MacroAssembler::super_call_VM_leaf(address entry_point) {
2040 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2041 }
2042
2043 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2044 pass_arg0(this, arg_0);
2045 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2046 }
2047
2048 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2049
2050 assert_different_registers(arg_0, c_rarg1);
2051 pass_arg1(this, arg_1);
2052 pass_arg0(this, arg_0);
2053 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2054 }
2055
2056 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2057 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2058 assert_different_registers(arg_1, c_rarg2);
2059 pass_arg2(this, arg_2);
2060 pass_arg1(this, arg_1);
2061 pass_arg0(this, arg_0);
2062 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2068 assert_different_registers(arg_2, c_rarg3);
2069 pass_arg3(this, arg_3);
2070 pass_arg2(this, arg_2);
2071 pass_arg1(this, arg_1);
2072 pass_arg0(this, arg_0);
2073 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2074 }
2075
2076 void MacroAssembler::null_check(Register reg, int offset) {
2077 if (needs_explicit_null_check(offset)) {
2078 // provoke OS null exception if reg is null by
2079 // accessing M[reg] w/o changing any registers
2080 // NOTE: this is plenty to provoke a segv
2081 ldr(zr, Address(reg));
2082 } else {
2083 // nothing to do, (later) access of M[reg + offset]
2084 // will provoke OS null exception if reg is null
2085 }
2086 }
2087
2088 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2089 assert_different_registers(markword, rscratch2);
2090 andr(markword, markword, markWord::inline_type_mask_in_place);
2091 mov(rscratch2, markWord::inline_type_pattern);
2092 cmp(markword, rscratch2);
2093 br(Assembler::EQ, is_inline_type);
2094 }
2095
2096 void MacroAssembler::test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type) {
2097 ldrw(temp_reg, Address(klass, Klass::access_flags_offset()));
2098 andr(temp_reg, temp_reg, JVM_ACC_IDENTITY);
2099 cbz(temp_reg, is_inline_type);
2100 }
2101
2102 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type) {
2103 assert_different_registers(tmp, rscratch1);
2104 cbz(object, not_inline_type);
2105 const int is_inline_type_mask = markWord::inline_type_pattern;
2106 ldr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2107 mov(rscratch1, is_inline_type_mask);
2108 andr(tmp, tmp, rscratch1);
2109 cmp(tmp, rscratch1);
2110 br(Assembler::NE, not_inline_type);
2111 }
2112
2113 void MacroAssembler::test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type) {
2114 #ifdef ASSERT
2115 {
2116 Label done_check;
2117 test_klass_is_inline_type(klass, temp_reg, done_check);
2118 stop("test_klass_is_empty_inline_type with non inline type klass");
2119 bind(done_check);
2120 }
2121 #endif
2122 ldrw(temp_reg, Address(klass, InstanceKlass::misc_flags_offset()));
2123 andr(temp_reg, temp_reg, InstanceKlassFlags::is_empty_inline_type_value());
2124 cbnz(temp_reg, is_empty_inline_type);
2125 }
2126
2127 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2128 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2129 tbnz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, is_null_free_inline_type);
2130 }
2131
2132 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2133 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2134 tbz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, not_null_free_inline_type);
2135 }
2136
2137 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2138 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2139 tbnz(flags, ResolvedFieldEntry::is_flat_shift, is_flat);
2140 }
2141
2142 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2143 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2144 tbnz(flags, ResolvedFieldEntry::has_null_marker_shift, has_null_marker);
2145 }
2146
2147 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2148 Label test_mark_word;
2149 // load mark word
2150 ldr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2151 // check displaced
2152 tst(temp_reg, markWord::unlocked_value);
2153 br(Assembler::NE, test_mark_word);
2154 // slow path use klass prototype
2155 load_prototype_header(temp_reg, oop);
2156
2157 bind(test_mark_word);
2158 andr(temp_reg, temp_reg, test_bit);
2159 if (jmp_set) {
2160 cbnz(temp_reg, jmp_label);
2161 } else {
2162 cbz(temp_reg, jmp_label);
2163 }
2164 }
2165
2166 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array) {
2167 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2168 }
2169
2170 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2171 Label&is_non_flat_array) {
2172 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2173 }
2174
2175 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array) {
2176 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2177 }
2178
2179 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2180 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2181 }
2182
2183 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2184 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2185 br(Assembler::NE, is_flat_array);
2186 }
2187
2188 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
2189 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2190 br(Assembler::EQ, is_non_flat_array);
2191 }
2192
2193 // MacroAssembler protected routines needed to implement
2194 // public methods
2195
2196 void MacroAssembler::mov(Register r, Address dest) {
2197 code_section()->relocate(pc(), dest.rspec());
2198 uint64_t imm64 = (uint64_t)dest.target();
2199 movptr(r, imm64);
2200 }
2201
2202 // Move a constant pointer into r. In AArch64 mode the virtual
2203 // address space is 48 bits in size, so we only need three
2204 // instructions to create a patchable instruction sequence that can
2205 // reach anywhere.
2206 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2207 #ifndef PRODUCT
2208 {
2209 char buffer[64];
2210 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2211 block_comment(buffer);
2212 }
4977 adrp(rscratch1, src2, offset);
4978 ldr(rscratch1, Address(rscratch1, offset));
4979 cmp(src1, rscratch1);
4980 }
4981
4982 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4983 cmp(obj1, obj2);
4984 }
4985
4986 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4987 load_method_holder(rresult, rmethod);
4988 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4989 }
4990
4991 void MacroAssembler::load_method_holder(Register holder, Register method) {
4992 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
4993 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
4994 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
4995 }
4996
4997 void MacroAssembler::load_metadata(Register dst, Register src) {
4998 if (UseCompressedClassPointers) {
4999 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5000 } else {
5001 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5002 }
5003 }
5004
5005 void MacroAssembler::load_klass(Register dst, Register src) {
5006 if (UseCompressedClassPointers) {
5007 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5008 decode_klass_not_null(dst);
5009 } else {
5010 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5011 }
5012 }
5013
5014 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5015 if (RestoreMXCSROnJNICalls) {
5016 Label OK;
5017 get_fpcr(tmp1);
5018 mov(tmp2, tmp1);
5019 // Set FPCR to the state we need. We do want Round to Nearest. We
5020 // don't want non-IEEE rounding modes or floating-point traps.
5021 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5022 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5023 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5024 eor(tmp2, tmp1, tmp2);
5060
5061 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
5062 if (UseCompressedClassPointers) {
5063 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
5064 if (CompressedKlassPointers::base() == nullptr) {
5065 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
5066 return;
5067 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5068 && CompressedKlassPointers::shift() == 0) {
5069 // Only the bottom 32 bits matter
5070 cmpw(trial_klass, tmp);
5071 return;
5072 }
5073 decode_klass_not_null(tmp);
5074 } else {
5075 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
5076 }
5077 cmp(trial_klass, tmp);
5078 }
5079
5080 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5081 load_klass(dst, src);
5082 ldr(dst, Address(dst, Klass::prototype_header_offset()));
5083 }
5084
5085 void MacroAssembler::store_klass(Register dst, Register src) {
5086 // FIXME: Should this be a store release? concurrent gcs assumes
5087 // klass length is valid if klass field is not null.
5088 if (UseCompressedClassPointers) {
5089 encode_klass_not_null(src);
5090 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5091 } else {
5092 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5093 }
5094 }
5095
5096 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5097 if (UseCompressedClassPointers) {
5098 // Store to klass gap in destination
5099 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5100 }
5101 }
5102
5103 // Algorithm must match CompressedOops::encode.
5104 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5389 if (as_raw) {
5390 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5391 } else {
5392 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5393 }
5394 }
5395
5396 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5397 Address dst, Register val,
5398 Register tmp1, Register tmp2, Register tmp3) {
5399 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5400 decorators = AccessInternal::decorator_fixup(decorators, type);
5401 bool as_raw = (decorators & AS_RAW) != 0;
5402 if (as_raw) {
5403 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5404 } else {
5405 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5406 }
5407 }
5408
5409 void MacroAssembler::access_value_copy(DecoratorSet decorators, Register src, Register dst,
5410 Register inline_klass) {
5411 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5412 bs->value_copy(this, decorators, src, dst, inline_klass);
5413 }
5414
5415 void MacroAssembler::first_field_offset(Register inline_klass, Register offset) {
5416 ldr(offset, Address(inline_klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
5417 ldrw(offset, Address(offset, InlineKlass::first_field_offset_offset()));
5418 }
5419
5420 void MacroAssembler::data_for_oop(Register oop, Register data, Register inline_klass) {
5421 // ((address) (void*) o) + vk->first_field_offset();
5422 Register offset = (data == oop) ? rscratch1 : data;
5423 first_field_offset(inline_klass, offset);
5424 if (data == oop) {
5425 add(data, data, offset);
5426 } else {
5427 lea(data, Address(oop, offset));
5428 }
5429 }
5430
5431 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
5432 Register index, Register data) {
5433 assert_different_registers(array, array_klass, index);
5434 assert_different_registers(rscratch1, array, index);
5435
5436 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
5437 ldrw(rscratch1, Address(array_klass, Klass::layout_helper_offset()));
5438
5439 // Klass::layout_helper_log2_element_size(lh)
5440 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
5441 lsr(rscratch1, rscratch1, Klass::_lh_log2_element_size_shift);
5442 andr(rscratch1, rscratch1, Klass::_lh_log2_element_size_mask);
5443 lslv(index, index, rscratch1);
5444
5445 add(data, array, index);
5446 add(data, data, arrayOopDesc::base_offset_in_bytes(T_PRIMITIVE_OBJECT));
5447 }
5448
5449 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5450 Register tmp2, DecoratorSet decorators) {
5451 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5452 }
5453
5454 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5455 Register tmp2, DecoratorSet decorators) {
5456 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5457 }
5458
5459 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5460 Register tmp2, Register tmp3, DecoratorSet decorators) {
5461 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5462 }
5463
5464 // Used for storing nulls.
5465 void MacroAssembler::store_heap_oop_null(Address dst) {
5466 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5467 }
5468
5505 oop_index = oop_recorder()->allocate_metadata_index(obj);
5506 } else {
5507 oop_index = oop_recorder()->find_index(obj);
5508 }
5509 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5510 mov(dst, Address((address)obj, rspec));
5511 }
5512
5513 Address MacroAssembler::constant_oop_address(jobject obj) {
5514 #ifdef ASSERT
5515 {
5516 ThreadInVMfromUnknown tiv;
5517 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5518 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5519 }
5520 #endif
5521 int oop_index = oop_recorder()->find_index(obj);
5522 return Address((address)obj, oop_Relocation::spec(oop_index));
5523 }
5524
5525 // Object / value buffer allocation...
5526 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
5527 Register t1, Register t2,
5528 bool clear_fields, Label& alloc_failed)
5529 {
5530 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
5531 Register layout_size = t1;
5532 assert(new_obj == r0, "needs to be r0");
5533 assert_different_registers(klass, new_obj, t1, t2);
5534
5535 // get instance_size in InstanceKlass (scaled to a count of bytes)
5536 ldrw(layout_size, Address(klass, Klass::layout_helper_offset()));
5537 // test to see if it is malformed in some way
5538 tst(layout_size, Klass::_lh_instance_slow_path_bit);
5539 br(Assembler::NE, slow_case_no_pop);
5540
5541 // Allocate the instance:
5542 // If TLAB is enabled:
5543 // Try to allocate in the TLAB.
5544 // If fails, go to the slow path.
5545 // Initialize the allocation.
5546 // Exit.
5547 //
5548 // Go to slow path.
5549
5550 if (UseTLAB) {
5551 push(klass);
5552 tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case);
5553 if (ZeroTLAB || (!clear_fields)) {
5554 // the fields have been already cleared
5555 b(initialize_header);
5556 } else {
5557 // initialize both the header and fields
5558 b(initialize_object);
5559 }
5560
5561 if (clear_fields) {
5562 // The object is initialized before the header. If the object size is
5563 // zero, go directly to the header initialization.
5564 bind(initialize_object);
5565 subs(layout_size, layout_size, sizeof(oopDesc));
5566 br(Assembler::EQ, initialize_header);
5567
5568 // Initialize topmost object field, divide size by 8, check if odd and
5569 // test if zero.
5570
5571 #ifdef ASSERT
5572 // make sure instance_size was multiple of 8
5573 Label L;
5574 tst(layout_size, 7);
5575 br(Assembler::EQ, L);
5576 stop("object size is not multiple of 8 - adjust this code");
5577 bind(L);
5578 // must be > 0, no extra check needed here
5579 #endif
5580
5581 lsr(layout_size, layout_size, LogBytesPerLong);
5582
5583 // initialize remaining object fields: instance_size was a multiple of 8
5584 {
5585 Label loop;
5586 Register base = t2;
5587
5588 bind(loop);
5589 add(rscratch1, new_obj, layout_size, Assembler::LSL, LogBytesPerLong);
5590 str(zr, Address(rscratch1, sizeof(oopDesc) - 1*oopSize));
5591 subs(layout_size, layout_size, 1);
5592 br(Assembler::NE, loop);
5593 }
5594 } // clear_fields
5595
5596 // initialize object header only.
5597 bind(initialize_header);
5598 pop(klass);
5599 Register mark_word = t2;
5600 ldr(mark_word, Address(klass, Klass::prototype_header_offset()));
5601 str(mark_word, Address(new_obj, oopDesc::mark_offset_in_bytes ()));
5602 store_klass_gap(new_obj, zr); // zero klass gap for compressed oops
5603 mov(t2, klass); // preserve klass
5604 store_klass(new_obj, t2); // src klass reg is potentially compressed
5605
5606 // TODO: Valhalla removed SharedRuntime::dtrace_object_alloc from here ?
5607
5608 b(done);
5609 }
5610
5611 if (UseTLAB) {
5612 bind(slow_case);
5613 pop(klass);
5614 }
5615 bind(slow_case_no_pop);
5616 b(alloc_failed);
5617
5618 bind(done);
5619 }
5620
5621 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5622 void MacroAssembler::tlab_allocate(Register obj,
5623 Register var_size_in_bytes,
5624 int con_size_in_bytes,
5625 Register t1,
5626 Register t2,
5627 Label& slow_case) {
5628 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5629 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5630 }
5631
5632 void MacroAssembler::verify_tlab() {
5633 #ifdef ASSERT
5634 if (UseTLAB && VerifyOops) {
5635 Label next, ok;
5636
5637 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5638
5639 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5640 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5641 cmp(rscratch2, rscratch1);
5642 br(Assembler::HS, next);
5643 STOP("assert(top >= start)");
5644 should_not_reach_here();
5645
5646 bind(next);
5647 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5648 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5649 cmp(rscratch2, rscratch1);
5650 br(Assembler::HS, ok);
5651 STOP("assert(top <= end)");
5652 should_not_reach_here();
5653
5654 bind(ok);
5655 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5656 }
5657 #endif
5658 }
5659
5660 void MacroAssembler::get_inline_type_field_klass(Register klass, Register index, Register inline_klass) {
5661 ldr(inline_klass, Address(klass, InstanceKlass::inline_type_field_klasses_offset()));
5662 #ifdef ASSERT
5663 {
5664 Label done;
5665 cbnz(inline_klass, done);
5666 stop("get_inline_type_field_klass contains no inline klass");
5667 bind(done);
5668 }
5669 #endif
5670 lea(inline_klass, Address(inline_klass, Array<InlineKlass*>::base_offset_in_bytes()));
5671 ldr(inline_klass, Address(inline_klass, index, Address::lsl(3)));
5672 }
5673
5674 // Writes to stack successive pages until offset reached to check for
5675 // stack overflow + shadow pages. This clobbers tmp.
5676 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5677 assert_different_registers(tmp, size, rscratch1);
5678 mov(tmp, sp);
5679 // Bang stack for total size given plus shadow page size.
5680 // Bang one page at a time because large size can bang beyond yellow and
5681 // red zones.
5682 Label loop;
5683 mov(rscratch1, (int)os::vm_page_size());
5684 bind(loop);
5685 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5686 subsw(size, size, rscratch1);
5687 str(size, Address(tmp));
5688 br(Assembler::GT, loop);
5689
5690 // Bang down shadow pages too.
5691 // At this point, (tmp-0) is the last address touched, so don't
5692 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5693 // was post-decremented.) Skip this address by starting at i=1, and
5779 }
5780
5781 void MacroAssembler::remove_frame(int framesize) {
5782 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5783 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5784 if (framesize < ((1 << 9) + 2 * wordSize)) {
5785 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5786 add(sp, sp, framesize);
5787 } else {
5788 if (framesize < ((1 << 12) + 2 * wordSize))
5789 add(sp, sp, framesize - 2 * wordSize);
5790 else {
5791 mov(rscratch1, framesize - 2 * wordSize);
5792 add(sp, sp, rscratch1);
5793 }
5794 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5795 }
5796 authenticate_return_address();
5797 }
5798
5799 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
5800 if (needs_stack_repair) {
5801 // Remove the extension of the caller's frame used for inline type unpacking
5802 //
5803 // Right now the stack looks like this:
5804 //
5805 // | Arguments from caller |
5806 // |---------------------------| <-- caller's SP
5807 // | Saved LR #1 |
5808 // | Saved FP #1 |
5809 // |---------------------------|
5810 // | Extension space for |
5811 // | inline arg (un)packing |
5812 // |---------------------------| <-- start of this method's frame
5813 // | Saved LR #2 |
5814 // | Saved FP #2 |
5815 // |---------------------------| <-- FP
5816 // | sp_inc |
5817 // | method locals |
5818 // |---------------------------| <-- SP
5819 //
5820 // There are two copies of FP and LR on the stack. They will be identical
5821 // unless the caller has been deoptimized, in which case LR #1 will be patched
5822 // to point at the deopt blob, and LR #2 will still point into the old method.
5823 //
5824 // The sp_inc stack slot holds the total size of the frame including the
5825 // extension space minus two words for the saved FP and LR.
5826
5827 int sp_inc_offset = initial_framesize - 3 * wordSize; // Immediately below saved LR and FP
5828
5829 ldr(rscratch1, Address(sp, sp_inc_offset));
5830 add(sp, sp, rscratch1);
5831 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5832 } else {
5833 remove_frame(initial_framesize);
5834 }
5835 }
5836
5837 void MacroAssembler::save_stack_increment(int sp_inc, int frame_size) {
5838 int real_frame_size = frame_size + sp_inc;
5839 assert(sp_inc == 0 || sp_inc > 2*wordSize, "invalid sp_inc value");
5840 assert(real_frame_size >= 2*wordSize, "frame size must include FP/LR space");
5841 assert((real_frame_size & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5842
5843 int sp_inc_offset = frame_size - 3 * wordSize; // Immediately below saved LR and FP
5844
5845 // Subtract two words for the saved FP and LR as these will be popped
5846 // separately. See remove_frame above.
5847 mov(rscratch1, real_frame_size - 2*wordSize);
5848 str(rscratch1, Address(sp, sp_inc_offset));
5849 }
5850
5851 // This method counts leading positive bytes (highest bit not set) in provided byte array
5852 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5853 // Simple and most common case of aligned small array which is not at the
5854 // end of memory page is placed here. All other cases are in stub.
5855 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5856 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5857 assert_different_registers(ary1, len, result);
5858
5859 mov(result, len);
5860 cmpw(len, 0);
5861 br(LE, DONE);
5862 cmpw(len, 4 * wordSize);
5863 br(GE, STUB_LONG); // size > 32 then go to stub
5864
5865 int shift = 64 - exact_log2(os::vm_page_size());
5866 lsl(rscratch1, ary1, shift);
5867 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5868 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5869 br(CS, STUB); // at the end of page then go to stub
6743 // On other systems, the helper is a usual C function.
6744 //
6745 void MacroAssembler::get_thread(Register dst) {
6746 RegSet saved_regs =
6747 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6748 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6749
6750 protect_return_address();
6751 push(saved_regs, sp);
6752
6753 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
6754 blr(lr);
6755 if (dst != c_rarg0) {
6756 mov(dst, c_rarg0);
6757 }
6758
6759 pop(saved_regs, sp);
6760 authenticate_return_address();
6761 }
6762
6763 #ifdef COMPILER2
6764 // C2 compiled method's prolog code
6765 // Moved here from aarch64.ad to support Valhalla code belows
6766 void MacroAssembler::verified_entry(Compile* C, int sp_inc) {
6767 if (C->clinit_barrier_on_entry()) {
6768 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
6769
6770 Label L_skip_barrier;
6771
6772 mov_metadata(rscratch2, C->method()->holder()->constant_encoding());
6773 clinit_barrier(rscratch2, rscratch1, &L_skip_barrier);
6774 far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
6775 bind(L_skip_barrier);
6776 }
6777
6778 if (C->max_vector_size() > 0) {
6779 reinitialize_ptrue();
6780 }
6781
6782 int bangsize = C->output()->bang_size_in_bytes();
6783 if (C->output()->need_stack_bang(bangsize))
6784 generate_stack_overflow_check(bangsize);
6785
6786 // n.b. frame size includes space for return pc and rfp
6787 const long framesize = C->output()->frame_size_in_bytes();
6788 build_frame(framesize);
6789
6790 if (C->needs_stack_repair()) {
6791 save_stack_increment(sp_inc, framesize);
6792 }
6793
6794 if (VerifyStackAtCalls) {
6795 Unimplemented();
6796 }
6797 }
6798 #endif // COMPILER2
6799
6800 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6801 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6802 // An inline type might be returned. If fields are in registers we
6803 // need to allocate an inline type instance and initialize it with
6804 // the value of the fields.
6805 Label skip;
6806 // We only need a new buffered inline type if a new one is not returned
6807 tbz(r0, 0, skip);
6808 int call_offset = -1;
6809
6810 // Be careful not to clobber r1-7 which hold returned fields
6811 // Also do not use callee-saved registers as these may be live in the interpreter
6812 Register tmp1 = r13, tmp2 = r14, klass = r15, r0_preserved = r12;
6813
6814 // The following code is similar to allocate_instance but has some slight differences,
6815 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6816 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
6817 Label slow_case;
6818 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6819 mov(r0_preserved, r0); // save r0 for slow_case since *_allocate may corrupt it when allocation failed
6820
6821 if (vk != nullptr) {
6822 // Called from C1, where the return type is statically known.
6823 movptr(klass, (intptr_t)vk->get_InlineKlass());
6824 jint lh = vk->layout_helper();
6825 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6826 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6827 tlab_allocate(r0, noreg, lh, tmp1, tmp2, slow_case);
6828 } else {
6829 b(slow_case);
6830 }
6831 } else {
6832 // Call from interpreter. R0 contains ((the InlineKlass* of the return type) | 0x01)
6833 andr(klass, r0, -2);
6834 if (UseTLAB) {
6835 ldrw(tmp2, Address(klass, Klass::layout_helper_offset()));
6836 tst(tmp2, Klass::_lh_instance_slow_path_bit);
6837 br(Assembler::NE, slow_case);
6838 tlab_allocate(r0, tmp2, 0, tmp1, tmp2, slow_case);
6839 } else {
6840 b(slow_case);
6841 }
6842 }
6843 if (UseTLAB) {
6844 // 2. Initialize buffered inline instance header
6845 Register buffer_obj = r0;
6846 mov(rscratch1, (intptr_t)markWord::inline_type_prototype().value());
6847 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes()));
6848 store_klass_gap(buffer_obj, zr);
6849 if (vk == nullptr) {
6850 // store_klass corrupts klass, so save it for later use (interpreter case only).
6851 mov(tmp1, klass);
6852 }
6853 store_klass(buffer_obj, klass);
6854 // 3. Initialize its fields with an inline class specific handler
6855 if (vk != nullptr) {
6856 far_call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6857 } else {
6858 // tmp1 holds klass preserved above
6859 ldr(tmp1, Address(tmp1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
6860 ldr(tmp1, Address(tmp1, InlineKlass::pack_handler_offset()));
6861 blr(tmp1);
6862 }
6863
6864 membar(Assembler::StoreStore);
6865 b(skip);
6866 } else {
6867 // Must have already branched to slow_case above.
6868 DEBUG_ONLY(should_not_reach_here());
6869 }
6870 bind(slow_case);
6871 // We failed to allocate a new inline type, fall back to a runtime
6872 // call. Some oop field may be live in some registers but we can't
6873 // tell. That runtime call will take care of preserving them
6874 // across a GC if there's one.
6875 mov(r0, r0_preserved);
6876
6877 if (from_interpreter) {
6878 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6879 } else {
6880 far_call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6881 call_offset = offset();
6882 }
6883 membar(Assembler::StoreStore);
6884
6885 bind(skip);
6886 return call_offset;
6887 }
6888
6889 // Move a value between registers/stack slots and update the reg_state
6890 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6891 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6892 if (reg_state[to->value()] == reg_written) {
6893 return true; // Already written
6894 }
6895
6896 if (from != to && bt != T_VOID) {
6897 if (reg_state[to->value()] == reg_readonly) {
6898 return false; // Not yet writable
6899 }
6900 if (from->is_reg()) {
6901 if (to->is_reg()) {
6902 if (from->is_Register() && to->is_Register()) {
6903 mov(to->as_Register(), from->as_Register());
6904 } else if (from->is_FloatRegister() && to->is_FloatRegister()) {
6905 fmovd(to->as_FloatRegister(), from->as_FloatRegister());
6906 } else {
6907 ShouldNotReachHere();
6908 }
6909 } else {
6910 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
6911 Address to_addr = Address(sp, st_off);
6912 if (from->is_FloatRegister()) {
6913 if (bt == T_DOUBLE) {
6914 strd(from->as_FloatRegister(), to_addr);
6915 } else {
6916 assert(bt == T_FLOAT, "must be float");
6917 strs(from->as_FloatRegister(), to_addr);
6918 }
6919 } else {
6920 str(from->as_Register(), to_addr);
6921 }
6922 }
6923 } else {
6924 Address from_addr = Address(sp, from->reg2stack() * VMRegImpl::stack_slot_size);
6925 if (to->is_reg()) {
6926 if (to->is_FloatRegister()) {
6927 if (bt == T_DOUBLE) {
6928 ldrd(to->as_FloatRegister(), from_addr);
6929 } else {
6930 assert(bt == T_FLOAT, "must be float");
6931 ldrs(to->as_FloatRegister(), from_addr);
6932 }
6933 } else {
6934 ldr(to->as_Register(), from_addr);
6935 }
6936 } else {
6937 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
6938 ldr(rscratch1, from_addr);
6939 str(rscratch1, Address(sp, st_off));
6940 }
6941 }
6942 }
6943
6944 // Update register states
6945 reg_state[from->value()] = reg_writable;
6946 reg_state[to->value()] = reg_written;
6947 return true;
6948 }
6949
6950 // Calculate the extra stack space required for packing or unpacking inline
6951 // args and adjust the stack pointer
6952 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6953 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
6954 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6955 assert(sp_inc > 0, "sanity");
6956
6957 // Save a copy of the FP and LR here for deoptimization patching and frame walking
6958 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6959
6960 // Adjust the stack pointer. This will be repaired on return by MacroAssembler::remove_frame
6961 if (sp_inc < (1 << 9)) {
6962 sub(sp, sp, sp_inc); // Fits in an immediate
6963 } else {
6964 mov(rscratch1, sp_inc);
6965 sub(sp, sp, rscratch1);
6966 }
6967
6968 return sp_inc + 2 * wordSize; // Account for the FP/LR space
6969 }
6970
6971 // Read all fields from an inline type oop and store the values in registers/stack slots
6972 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6973 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6974 RegState reg_state[]) {
6975 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6976 assert(from->is_valid(), "source must be valid");
6977 bool progress = false;
6978 #ifdef ASSERT
6979 const int start_offset = offset();
6980 #endif
6981
6982 Label L_null, L_notNull;
6983 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6984 Register tmp1 = r10;
6985 Register tmp2 = r11;
6986 Register fromReg = noreg;
6987 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
6988 bool done = true;
6989 bool mark_done = true;
6990 VMReg toReg;
6991 BasicType bt;
6992 // Check if argument requires a null check
6993 bool null_check = false;
6994 VMReg nullCheckReg;
6995 while (stream.next(nullCheckReg, bt)) {
6996 if (sig->at(stream.sig_index())._offset == -1) {
6997 null_check = true;
6998 break;
6999 }
7000 }
7001 stream.reset(sig_index, to_index);
7002 while (stream.next(toReg, bt)) {
7003 assert(toReg->is_valid(), "destination must be valid");
7004 int idx = (int)toReg->value();
7005 if (reg_state[idx] == reg_readonly) {
7006 if (idx != from->value()) {
7007 mark_done = false;
7008 }
7009 done = false;
7010 continue;
7011 } else if (reg_state[idx] == reg_written) {
7012 continue;
7013 }
7014 assert(reg_state[idx] == reg_writable, "must be writable");
7015 reg_state[idx] = reg_written;
7016 progress = true;
7017
7018 if (fromReg == noreg) {
7019 if (from->is_reg()) {
7020 fromReg = from->as_Register();
7021 } else {
7022 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size;
7023 ldr(tmp1, Address(sp, st_off));
7024 fromReg = tmp1;
7025 }
7026 if (null_check) {
7027 // Nullable inline type argument, emit null check
7028 cbz(fromReg, L_null);
7029 }
7030 }
7031 int off = sig->at(stream.sig_index())._offset;
7032 if (off == -1) {
7033 assert(null_check, "Missing null check at");
7034 if (toReg->is_stack()) {
7035 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7036 mov(tmp2, 1);
7037 str(tmp2, Address(sp, st_off));
7038 } else {
7039 mov(toReg->as_Register(), 1);
7040 }
7041 continue;
7042 }
7043 assert(off > 0, "offset in object should be positive");
7044 Address fromAddr = Address(fromReg, off);
7045 if (!toReg->is_FloatRegister()) {
7046 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
7047 if (is_reference_type(bt)) {
7048 load_heap_oop(dst, fromAddr, rscratch1, rscratch2);
7049 } else {
7050 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
7051 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
7052 }
7053 if (toReg->is_stack()) {
7054 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7055 str(dst, Address(sp, st_off));
7056 }
7057 } else if (bt == T_DOUBLE) {
7058 ldrd(toReg->as_FloatRegister(), fromAddr);
7059 } else {
7060 assert(bt == T_FLOAT, "must be float");
7061 ldrs(toReg->as_FloatRegister(), fromAddr);
7062 }
7063 }
7064 if (progress && null_check) {
7065 if (done) {
7066 b(L_notNull);
7067 bind(L_null);
7068 // Set IsInit field to zero to signal that the argument is null.
7069 // Also set all oop fields to zero to make the GC happy.
7070 stream.reset(sig_index, to_index);
7071 while (stream.next(toReg, bt)) {
7072 if (sig->at(stream.sig_index())._offset == -1 ||
7073 bt == T_OBJECT || bt == T_ARRAY) {
7074 if (toReg->is_stack()) {
7075 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7076 str(zr, Address(sp, st_off));
7077 } else {
7078 mov(toReg->as_Register(), zr);
7079 }
7080 }
7081 }
7082 bind(L_notNull);
7083 } else {
7084 bind(L_null);
7085 }
7086 }
7087
7088 sig_index = stream.sig_index();
7089 to_index = stream.regs_index();
7090
7091 if (mark_done && reg_state[from->value()] != reg_written) {
7092 // This is okay because no one else will write to that slot
7093 reg_state[from->value()] = reg_writable;
7094 }
7095 from_index--;
7096 assert(progress || (start_offset == offset()), "should not emit code");
7097 return done;
7098 }
7099
7100 // Pack fields back into an inline type oop
7101 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
7102 VMRegPair* from, int from_count, int& from_index, VMReg to,
7103 RegState reg_state[], Register val_array) {
7104 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
7105 assert(to->is_valid(), "destination must be valid");
7106
7107 if (reg_state[to->value()] == reg_written) {
7108 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7109 return true; // Already written
7110 }
7111
7112 // The GC barrier expanded by store_heap_oop below may call into the
7113 // runtime so use callee-saved registers for any values that need to be
7114 // preserved. The GC barrier assembler should take care of saving the
7115 // Java argument registers.
7116 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
7117 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
7118 Register val_obj_tmp = r21;
7119 Register from_reg_tmp = r22;
7120 Register tmp1 = r14;
7121 Register tmp2 = r13;
7122 Register tmp3 = r12;
7123 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
7124
7125 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
7126
7127 if (reg_state[to->value()] == reg_readonly) {
7128 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
7129 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7130 return false; // Not yet writable
7131 }
7132 val_obj = val_obj_tmp;
7133 }
7134
7135 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
7136 load_heap_oop(val_obj, Address(val_array, index), tmp1, tmp2);
7137
7138 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
7139 VMReg fromReg;
7140 BasicType bt;
7141 Label L_null;
7142 while (stream.next(fromReg, bt)) {
7143 assert(fromReg->is_valid(), "source must be valid");
7144 reg_state[fromReg->value()] = reg_writable;
7145
7146 int off = sig->at(stream.sig_index())._offset;
7147 if (off == -1) {
7148 // Nullable inline type argument, emit null check
7149 Label L_notNull;
7150 if (fromReg->is_stack()) {
7151 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7152 ldrb(tmp2, Address(sp, ld_off));
7153 cbnz(tmp2, L_notNull);
7154 } else {
7155 cbnz(fromReg->as_Register(), L_notNull);
7156 }
7157 mov(val_obj, 0);
7158 b(L_null);
7159 bind(L_notNull);
7160 continue;
7161 }
7162
7163 assert(off > 0, "offset in object should be positive");
7164 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
7165
7166 // Pack the scalarized field into the value object.
7167 Address dst(val_obj, off);
7168
7169 if (!fromReg->is_FloatRegister()) {
7170 Register src;
7171 if (fromReg->is_stack()) {
7172 src = from_reg_tmp;
7173 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7174 load_sized_value(src, Address(sp, ld_off), size_in_bytes, /* is_signed */ false);
7175 } else {
7176 src = fromReg->as_Register();
7177 }
7178 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
7179 if (is_reference_type(bt)) {
7180 store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
7181 } else {
7182 store_sized_value(dst, src, size_in_bytes);
7183 }
7184 } else if (bt == T_DOUBLE) {
7185 strd(fromReg->as_FloatRegister(), dst);
7186 } else {
7187 assert(bt == T_FLOAT, "must be float");
7188 strs(fromReg->as_FloatRegister(), dst);
7189 }
7190 }
7191 bind(L_null);
7192 sig_index = stream.sig_index();
7193 from_index = stream.regs_index();
7194
7195 assert(reg_state[to->value()] == reg_writable, "must have already been read");
7196 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
7197 assert(success, "to register must be writeable");
7198
7199 return true;
7200 }
7201
7202 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
7203 return (reg->is_FloatRegister()) ? v8->as_VMReg() : r14->as_VMReg();
7204 }
7205
7206 void MacroAssembler::cache_wb(Address line) {
7207 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
7208 assert(line.index() == noreg, "index should be noreg");
7209 assert(line.offset() == 0, "offset should be 0");
7210 // would like to assert this
7211 // assert(line._ext.shift == 0, "shift should be zero");
7212 if (VM_Version::supports_dcpop()) {
7213 // writeback using clear virtual address to point of persistence
7214 dc(Assembler::CVAP, line.base());
7215 } else {
7216 // no need to generate anything as Unsafe.writebackMemory should
7217 // never invoke this stub
7218 }
7219 }
7220
7221 void MacroAssembler::cache_wbsync(bool is_pre) {
7222 // we only need a barrier post sync
7223 if (!is_pre) {
7224 membar(Assembler::AnyAny);
7225 }
7584 }
7585
7586 // Check if the lock-stack is full.
7587 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7588 cmpw(top, (unsigned)LockStack::end_offset());
7589 br(Assembler::GE, slow);
7590
7591 // Check for recursion.
7592 subw(t, top, oopSize);
7593 ldr(t, Address(rthread, t));
7594 cmp(obj, t);
7595 br(Assembler::EQ, push);
7596
7597 // Check header for monitor (0b10).
7598 tst(mark, markWord::monitor_value);
7599 br(Assembler::NE, slow);
7600
7601 // Try to lock. Transition lock bits 0b01 => 0b00
7602 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7603 orr(mark, mark, markWord::unlocked_value);
7604 if (EnableValhalla) {
7605 // Mask inline_type bit such that we go to the slow path if object is an inline type
7606 andr(mark, mark, ~((int) markWord::inline_type_bit_in_place));
7607 }
7608 eor(t, mark, markWord::unlocked_value);
7609 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
7610 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
7611 br(Assembler::NE, slow);
7612
7613 bind(push);
7614 // After successful lock, push object on lock-stack.
7615 str(obj, Address(rthread, top));
7616 addw(top, top, oopSize);
7617 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7618 }
7619
7620 // Implements lightweight-unlocking.
7621 //
7622 // - obj: the object to be unlocked
7623 // - t1, t2, t3: temporary registers
7624 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7625 void MacroAssembler::lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7626 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
7627 // cmpxchg clobbers rscratch1.
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