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src/hotspot/cpu/aarch64/macroAssembler_aarch64.cpp

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  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include <sys/types.h>
  27 
  28 #include "precompiled.hpp"
  29 #include "jvm.h"
  30 #include "asm/assembler.hpp"
  31 #include "asm/assembler.inline.hpp"
  32 #include "ci/ciEnv.hpp"

  33 #include "gc/shared/barrierSet.hpp"
  34 #include "gc/shared/barrierSetAssembler.hpp"
  35 #include "gc/shared/cardTableBarrierSet.hpp"
  36 #include "gc/shared/cardTable.hpp"
  37 #include "gc/shared/collectedHeap.hpp"
  38 #include "gc/shared/tlab_globals.hpp"
  39 #include "interpreter/bytecodeHistogram.hpp"
  40 #include "interpreter/interpreter.hpp"
  41 #include "compiler/compileTask.hpp"
  42 #include "compiler/disassembler.hpp"
  43 #include "memory/resourceArea.hpp"
  44 #include "memory/universe.hpp"
  45 #include "nativeInst_aarch64.hpp"
  46 #include "oops/accessDecorators.hpp"
  47 #include "oops/compressedOops.inline.hpp"
  48 #include "oops/klass.inline.hpp"
  49 #include "runtime/icache.hpp"
  50 #include "runtime/interfaceSupport.inline.hpp"
  51 #include "runtime/jniHandles.inline.hpp"
  52 #include "runtime/sharedRuntime.hpp"

  53 #include "runtime/stubRoutines.hpp"
  54 #include "runtime/thread.hpp"
  55 #include "utilities/powerOfTwo.hpp"

  56 #ifdef COMPILER1
  57 #include "c1/c1_LIRAssembler.hpp"
  58 #endif
  59 #ifdef COMPILER2
  60 #include "oops/oop.hpp"
  61 #include "opto/compile.hpp"
  62 #include "opto/node.hpp"
  63 #include "opto/output.hpp"
  64 #endif
  65 
  66 #ifdef PRODUCT
  67 #define BLOCK_COMMENT(str) /* nothing */
  68 #else
  69 #define BLOCK_COMMENT(str) block_comment(str)
  70 #endif
  71 #define STOP(str) stop(str);
  72 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  73 
  74 // Patch any kind of instruction; there may be several instructions.
  75 // Return the total length (in bytes) of the instructions.

 758   ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
 759   str(zr, Address(java_thread, JavaThread::vm_result_offset()));
 760   verify_oop(oop_result, "broken oop in call_VM_base");
 761 }
 762 
 763 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
 764   ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
 765   str(zr, Address(java_thread, JavaThread::vm_result_2_offset()));
 766 }
 767 
 768 void MacroAssembler::align(int modulus) {
 769   while (offset() % modulus != 0) nop();
 770 }
 771 
 772 // these are no-ops overridden by InterpreterMacroAssembler
 773 
 774 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
 775 
 776 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
 777 



































 778 // Look up the method for a megamorphic invokeinterface call.
 779 // The target method is determined by <intf_klass, itable_index>.
 780 // The receiver klass is in recv_klass.
 781 // On success, the result will be in method_result, and execution falls through.
 782 // On failure, execution transfers to the given label.
 783 void MacroAssembler::lookup_interface_method(Register recv_klass,
 784                                              Register intf_klass,
 785                                              RegisterOrConstant itable_index,
 786                                              Register method_result,
 787                                              Register scan_temp,
 788                                              Label& L_no_such_interface,
 789                          bool return_method) {
 790   assert_different_registers(recv_klass, intf_klass, scan_temp);
 791   assert_different_registers(method_result, intf_klass, scan_temp);
 792   assert(recv_klass != method_result || !return_method,
 793      "recv_klass can be destroyed when method isn't needed");
 794   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
 795          "caller must use same register for non-constant itable index as for method");
 796 
 797   // Compute start of first itableOffsetEntry (which is at the end of the vtable)

1108   ldrb(scratch, Address(klass, InstanceKlass::init_state_offset()));
1109   subs(zr, scratch, InstanceKlass::fully_initialized);
1110   br(Assembler::EQ, *L_fast_path);
1111 
1112   // Fast path check: current thread is initializer thread
1113   ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
1114   cmp(rthread, scratch);
1115 
1116   if (L_slow_path == &L_fallthrough) {
1117     br(Assembler::EQ, *L_fast_path);
1118     bind(*L_slow_path);
1119   } else if (L_fast_path == &L_fallthrough) {
1120     br(Assembler::NE, *L_slow_path);
1121     bind(*L_fast_path);
1122   } else {
1123     Unimplemented();
1124   }
1125 }
1126 
1127 void MacroAssembler::verify_oop(Register reg, const char* s) {
1128   if (!VerifyOops) return;




1129 
1130   // Pass register number to verify_oop_subroutine
1131   const char* b = NULL;
1132   {
1133     ResourceMark rm;
1134     stringStream ss;
1135     ss.print("verify_oop: %s: %s", reg->name(), s);
1136     b = code_string(ss.as_string());
1137   }
1138   BLOCK_COMMENT("verify_oop {");
1139 
1140   strip_return_address(); // This might happen within a stack frame.
1141   protect_return_address();
1142   stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1143   stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1144 
1145   mov(r0, reg);
1146   movptr(rscratch1, (uintptr_t)(address)b);
1147 
1148   // call indirectly to solve generation ordering problem
1149   lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1150   ldr(rscratch2, Address(rscratch2));
1151   blr(rscratch2);
1152 
1153   ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1154   ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1155   authenticate_return_address();
1156 
1157   BLOCK_COMMENT("} verify_oop");
1158 }
1159 
1160 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
1161   if (!VerifyOops) return;




1162 
1163   const char* b = NULL;
1164   {
1165     ResourceMark rm;
1166     stringStream ss;
1167     ss.print("verify_oop_addr: %s", s);
1168     b = code_string(ss.as_string());
1169   }
1170   BLOCK_COMMENT("verify_oop_addr {");
1171 
1172   strip_return_address(); // This might happen within a stack frame.
1173   protect_return_address();
1174   stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1175   stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1176 
1177   // addr may contain sp so we will have to adjust it based on the
1178   // pushes that we just did.
1179   if (addr.uses(sp)) {
1180     lea(r0, addr);
1181     ldr(r0, Address(r0, 4 * wordSize));

1223   stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1224 
1225   mov(rscratch1, entry_point);
1226   blr(rscratch1);
1227   if (retaddr)
1228     bind(*retaddr);
1229 
1230   ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1231 }
1232 
1233 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1234   call_VM_leaf_base(entry_point, number_of_arguments);
1235 }
1236 
1237 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1238   pass_arg0(this, arg_0);
1239   call_VM_leaf_base(entry_point, 1);
1240 }
1241 
1242 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {

1243   pass_arg0(this, arg_0);
1244   pass_arg1(this, arg_1);
1245   call_VM_leaf_base(entry_point, 2);
1246 }
1247 
1248 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1249                                   Register arg_1, Register arg_2) {


1250   pass_arg0(this, arg_0);
1251   pass_arg1(this, arg_1);
1252   pass_arg2(this, arg_2);
1253   call_VM_leaf_base(entry_point, 3);
1254 }
1255 




1256 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1257   pass_arg0(this, arg_0);
1258   MacroAssembler::call_VM_leaf_base(entry_point, 1);
1259 }
1260 
1261 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1262 
1263   assert(arg_0 != c_rarg1, "smashed arg");
1264   pass_arg1(this, arg_1);
1265   pass_arg0(this, arg_0);
1266   MacroAssembler::call_VM_leaf_base(entry_point, 2);
1267 }
1268 
1269 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1270   assert(arg_0 != c_rarg2, "smashed arg");
1271   assert(arg_1 != c_rarg2, "smashed arg");
1272   pass_arg2(this, arg_2);
1273   assert(arg_0 != c_rarg1, "smashed arg");
1274   pass_arg1(this, arg_1);
1275   pass_arg0(this, arg_0);

1285   assert(arg_1 != c_rarg2, "smashed arg");
1286   pass_arg2(this, arg_2);
1287   assert(arg_0 != c_rarg1, "smashed arg");
1288   pass_arg1(this, arg_1);
1289   pass_arg0(this, arg_0);
1290   MacroAssembler::call_VM_leaf_base(entry_point, 4);
1291 }
1292 
1293 void MacroAssembler::null_check(Register reg, int offset) {
1294   if (needs_explicit_null_check(offset)) {
1295     // provoke OS NULL exception if reg = NULL by
1296     // accessing M[reg] w/o changing any registers
1297     // NOTE: this is plenty to provoke a segv
1298     ldr(zr, Address(reg));
1299   } else {
1300     // nothing to do, (later) access of M[reg + offset]
1301     // will provoke OS NULL exception if reg = NULL
1302   }
1303 }
1304 














































































































1305 // MacroAssembler protected routines needed to implement
1306 // public methods
1307 
1308 void MacroAssembler::mov(Register r, Address dest) {
1309   code_section()->relocate(pc(), dest.rspec());
1310   uint64_t imm64 = (uint64_t)dest.target();
1311   movptr(r, imm64);
1312 }
1313 
1314 // Move a constant pointer into r.  In AArch64 mode the virtual
1315 // address space is 48 bits in size, so we only need three
1316 // instructions to create a patchable instruction sequence that can
1317 // reach anywhere.
1318 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1319 #ifndef PRODUCT
1320   {
1321     char buffer[64];
1322     snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
1323     block_comment(buffer);
1324   }

3683   adrp(rscratch1, src2, offset);
3684   ldr(rscratch1, Address(rscratch1, offset));
3685   cmp(src1, rscratch1);
3686 }
3687 
3688 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
3689   cmp(obj1, obj2);
3690 }
3691 
3692 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
3693   load_method_holder(rresult, rmethod);
3694   ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
3695 }
3696 
3697 void MacroAssembler::load_method_holder(Register holder, Register method) {
3698   ldr(holder, Address(method, Method::const_offset()));                      // ConstMethod*
3699   ldr(holder, Address(holder, ConstMethod::constants_offset()));             // ConstantPool*
3700   ldr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
3701 }
3702 








3703 void MacroAssembler::load_klass(Register dst, Register src) {
3704   if (UseCompressedClassPointers) {
3705     ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3706     decode_klass_not_null(dst);
3707   } else {
3708     ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3709   }
3710 }
3711 
3712 // ((OopHandle)result).resolve();
3713 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
3714   // OopHandle::resolve is an indirection.
3715   access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp, noreg);
3716 }
3717 
3718 // ((WeakHandle)result).resolve();
3719 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
3720   assert_different_registers(rresult, rtmp);
3721   Label resolved;
3722 

3742 
3743 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
3744   if (UseCompressedClassPointers) {
3745     ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3746     if (CompressedKlassPointers::base() == NULL) {
3747       cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
3748       return;
3749     } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
3750                && CompressedKlassPointers::shift() == 0) {
3751       // Only the bottom 32 bits matter
3752       cmpw(trial_klass, tmp);
3753       return;
3754     }
3755     decode_klass_not_null(tmp);
3756   } else {
3757     ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3758   }
3759   cmp(trial_klass, tmp);
3760 }
3761 





3762 void MacroAssembler::store_klass(Register dst, Register src) {
3763   // FIXME: Should this be a store release?  concurrent gcs assumes
3764   // klass length is valid if klass field is not null.
3765   if (UseCompressedClassPointers) {
3766     encode_klass_not_null(src);
3767     strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3768   } else {
3769     str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3770   }
3771 }
3772 
3773 void MacroAssembler::store_klass_gap(Register dst, Register src) {
3774   if (UseCompressedClassPointers) {
3775     // Store to klass gap in destination
3776     strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
3777   }
3778 }
3779 
3780 // Algorithm must match CompressedOops::encode.
3781 void MacroAssembler::encode_heap_oop(Register d, Register s) {

4055   narrowKlass nk = CompressedKlassPointers::encode(k);
4056   movz(dst, (nk >> 16), 16);
4057   movk(dst, nk & 0xffff);
4058 }
4059 
4060 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
4061                                     Register dst, Address src,
4062                                     Register tmp1, Register thread_tmp) {
4063   BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4064   decorators = AccessInternal::decorator_fixup(decorators);
4065   bool as_raw = (decorators & AS_RAW) != 0;
4066   if (as_raw) {
4067     bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4068   } else {
4069     bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4070   }
4071 }
4072 
4073 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
4074                                      Address dst, Register src,
4075                                      Register tmp1, Register thread_tmp) {

4076   BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4077   decorators = AccessInternal::decorator_fixup(decorators);
4078   bool as_raw = (decorators & AS_RAW) != 0;
4079   if (as_raw) {
4080     bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4081   } else {
4082     bs->store_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4083   }
4084 }
4085 








































4086 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
4087                                    Register thread_tmp, DecoratorSet decorators) {
4088   access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
4089 }
4090 
4091 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4092                                             Register thread_tmp, DecoratorSet decorators) {
4093   access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
4094 }
4095 
4096 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
4097                                     Register thread_tmp, DecoratorSet decorators) {
4098   access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
4099 }
4100 
4101 // Used for storing NULLs.
4102 void MacroAssembler::store_heap_oop_null(Address dst) {
4103   access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
4104 }
4105 
4106 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
4107   assert(oop_recorder() != NULL, "this assembler needs a Recorder");
4108   int index = oop_recorder()->allocate_metadata_index(obj);
4109   RelocationHolder rspec = metadata_Relocation::spec(index);
4110   return Address((address)obj, rspec);
4111 }
4112 
4113 // Move an oop into a register.  immediate is true if we want
4114 // immediate instructions and nmethod entry barriers are not enabled.
4115 // i.e. we are not going to patch this instruction while the code is being
4116 // executed by another thread.
4117 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) {
4118   int oop_index;
4119   if (obj == NULL) {
4120     oop_index = oop_recorder()->allocate_oop_index(obj);
4121   } else {
4122 #ifdef ASSERT
4123     {

4147     oop_index = oop_recorder()->allocate_metadata_index(obj);
4148   } else {
4149     oop_index = oop_recorder()->find_index(obj);
4150   }
4151   RelocationHolder rspec = metadata_Relocation::spec(oop_index);
4152   mov(dst, Address((address)obj, rspec));
4153 }
4154 
4155 Address MacroAssembler::constant_oop_address(jobject obj) {
4156 #ifdef ASSERT
4157   {
4158     ThreadInVMfromUnknown tiv;
4159     assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
4160     assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
4161   }
4162 #endif
4163   int oop_index = oop_recorder()->find_index(obj);
4164   return Address((address)obj, oop_Relocation::spec(oop_index));
4165 }
4166 












































































































4167 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4168 void MacroAssembler::tlab_allocate(Register obj,
4169                                    Register var_size_in_bytes,
4170                                    int con_size_in_bytes,
4171                                    Register t1,
4172                                    Register t2,
4173                                    Label& slow_case) {
4174   BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4175   bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4176 }
4177 
4178 // Defines obj, preserves var_size_in_bytes
4179 void MacroAssembler::eden_allocate(Register obj,
4180                                    Register var_size_in_bytes,
4181                                    int con_size_in_bytes,
4182                                    Register t1,
4183                                    Label& slow_case) {
4184   BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4185   bs->eden_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
4186 }

4196     ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
4197     cmp(rscratch2, rscratch1);
4198     br(Assembler::HS, next);
4199     STOP("assert(top >= start)");
4200     should_not_reach_here();
4201 
4202     bind(next);
4203     ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
4204     ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4205     cmp(rscratch2, rscratch1);
4206     br(Assembler::HS, ok);
4207     STOP("assert(top <= end)");
4208     should_not_reach_here();
4209 
4210     bind(ok);
4211     ldp(rscratch2, rscratch1, Address(post(sp, 16)));
4212   }
4213 #endif
4214 }
4215 













4216 // Writes to stack successive pages until offset reached to check for
4217 // stack overflow + shadow pages.  This clobbers tmp.
4218 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
4219   assert_different_registers(tmp, size, rscratch1);
4220   mov(tmp, sp);
4221   // Bang stack for total size given plus shadow page size.
4222   // Bang one page at a time because large size can bang beyond yellow and
4223   // red zones.
4224   Label loop;
4225   mov(rscratch1, os::vm_page_size());
4226   bind(loop);
4227   lea(tmp, Address(tmp, -os::vm_page_size()));
4228   subsw(size, size, rscratch1);
4229   str(size, Address(tmp));
4230   br(Assembler::GT, loop);
4231 
4232   // Bang down shadow pages too.
4233   // At this point, (tmp-0) is the last address touched, so don't
4234   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
4235   // was post-decremented.)  Skip this address by starting at i=1, and

4321 }
4322 
4323 void MacroAssembler::remove_frame(int framesize) {
4324   assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
4325   assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
4326   if (framesize < ((1 << 9) + 2 * wordSize)) {
4327     ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4328     add(sp, sp, framesize);
4329   } else {
4330     if (framesize < ((1 << 12) + 2 * wordSize))
4331       add(sp, sp, framesize - 2 * wordSize);
4332     else {
4333       mov(rscratch1, framesize - 2 * wordSize);
4334       add(sp, sp, rscratch1);
4335     }
4336     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
4337   }
4338   authenticate_return_address();
4339 }
4340 



















































4341 
4342 // This method counts leading positive bytes (highest bit not set) in provided byte array
4343 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
4344     // Simple and most common case of aligned small array which is not at the
4345     // end of memory page is placed here. All other cases are in stub.
4346     Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
4347     const uint64_t UPPER_BIT_MASK=0x8080808080808080;
4348     assert_different_registers(ary1, len, result);
4349 
4350     mov(result, len);
4351     cmpw(len, 0);
4352     br(LE, DONE);
4353     cmpw(len, 4 * wordSize);
4354     br(GE, STUB_LONG); // size > 32 then go to stub
4355 
4356     int shift = 64 - exact_log2(os::vm_page_size());
4357     lsl(rscratch1, ary1, shift);
4358     mov(rscratch2, (size_t)(4 * wordSize) << shift);
4359     adds(rscratch2, rscratch1, rscratch2);  // At end of page?
4360     br(CS, STUB); // at the end of page then go to stub

5177 // On other systems, the helper is a usual C function.
5178 //
5179 void MacroAssembler::get_thread(Register dst) {
5180   RegSet saved_regs =
5181     LINUX_ONLY(RegSet::range(r0, r1)  + lr - dst)
5182     NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
5183 
5184   protect_return_address();
5185   push(saved_regs, sp);
5186 
5187   mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
5188   blr(lr);
5189   if (dst != c_rarg0) {
5190     mov(dst, c_rarg0);
5191   }
5192 
5193   pop(saved_regs, sp);
5194   authenticate_return_address();
5195 }
5196 
















































































































































































































































































































































































































































5197 void MacroAssembler::cache_wb(Address line) {
5198   assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
5199   assert(line.index() == noreg, "index should be noreg");
5200   assert(line.offset() == 0, "offset should be 0");
5201   // would like to assert this
5202   // assert(line._ext.shift == 0, "shift should be zero");
5203   if (VM_Version::features() & VM_Version::CPU_DCPOP) {
5204     // writeback using clear virtual address to point of persistence
5205     dc(Assembler::CVAP, line.base());
5206   } else {
5207     // no need to generate anything as Unsafe.writebackMemory should
5208     // never invoke this stub
5209   }
5210 }
5211 
5212 void MacroAssembler::cache_wbsync(bool is_pre) {
5213   // we only need a barrier post sync
5214   if (!is_pre) {
5215     membar(Assembler::AnyAny);
5216   }

  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include <sys/types.h>
  27 
  28 #include "precompiled.hpp"
  29 #include "jvm.h"
  30 #include "asm/assembler.hpp"
  31 #include "asm/assembler.inline.hpp"
  32 #include "ci/ciEnv.hpp"
  33 #include "ci/ciInlineKlass.hpp"
  34 #include "gc/shared/barrierSet.hpp"
  35 #include "gc/shared/barrierSetAssembler.hpp"
  36 #include "gc/shared/cardTableBarrierSet.hpp"
  37 #include "gc/shared/cardTable.hpp"
  38 #include "gc/shared/collectedHeap.hpp"
  39 #include "gc/shared/tlab_globals.hpp"
  40 #include "interpreter/bytecodeHistogram.hpp"
  41 #include "interpreter/interpreter.hpp"
  42 #include "compiler/compileTask.hpp"
  43 #include "compiler/disassembler.hpp"
  44 #include "memory/resourceArea.hpp"
  45 #include "memory/universe.hpp"
  46 #include "nativeInst_aarch64.hpp"
  47 #include "oops/accessDecorators.hpp"
  48 #include "oops/compressedOops.inline.hpp"
  49 #include "oops/klass.inline.hpp"
  50 #include "runtime/icache.hpp"
  51 #include "runtime/interfaceSupport.inline.hpp"
  52 #include "runtime/jniHandles.inline.hpp"
  53 #include "runtime/sharedRuntime.hpp"
  54 #include "runtime/signature_cc.hpp"
  55 #include "runtime/stubRoutines.hpp"
  56 #include "runtime/thread.hpp"
  57 #include "utilities/powerOfTwo.hpp"
  58 #include "vmreg_aarch64.inline.hpp"
  59 #ifdef COMPILER1
  60 #include "c1/c1_LIRAssembler.hpp"
  61 #endif
  62 #ifdef COMPILER2
  63 #include "oops/oop.hpp"
  64 #include "opto/compile.hpp"
  65 #include "opto/node.hpp"
  66 #include "opto/output.hpp"
  67 #endif
  68 
  69 #ifdef PRODUCT
  70 #define BLOCK_COMMENT(str) /* nothing */
  71 #else
  72 #define BLOCK_COMMENT(str) block_comment(str)
  73 #endif
  74 #define STOP(str) stop(str);
  75 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  76 
  77 // Patch any kind of instruction; there may be several instructions.
  78 // Return the total length (in bytes) of the instructions.

 761   ldr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
 762   str(zr, Address(java_thread, JavaThread::vm_result_offset()));
 763   verify_oop(oop_result, "broken oop in call_VM_base");
 764 }
 765 
 766 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
 767   ldr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
 768   str(zr, Address(java_thread, JavaThread::vm_result_2_offset()));
 769 }
 770 
 771 void MacroAssembler::align(int modulus) {
 772   while (offset() % modulus != 0) nop();
 773 }
 774 
 775 // these are no-ops overridden by InterpreterMacroAssembler
 776 
 777 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
 778 
 779 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
 780 
 781 void MacroAssembler::get_default_value_oop(Register inline_klass, Register temp_reg, Register obj) {
 782 #ifdef ASSERT
 783   {
 784     Label done_check;
 785     test_klass_is_inline_type(inline_klass, temp_reg, done_check);
 786     stop("get_default_value_oop from non inline type klass");
 787     bind(done_check);
 788   }
 789 #endif
 790   Register offset = temp_reg;
 791   // Getting the offset of the pre-allocated default value
 792   ldr(offset, Address(inline_klass, in_bytes(InstanceKlass::adr_inlineklass_fixed_block_offset())));
 793   ldr(offset, Address(offset, in_bytes(InlineKlass::default_value_offset_offset())));
 794 
 795   // Getting the mirror
 796   ldr(obj, Address(inline_klass, in_bytes(Klass::java_mirror_offset())));
 797   resolve_oop_handle(obj, inline_klass);
 798 
 799   // Getting the pre-allocated default value from the mirror
 800   Address field(obj, offset);
 801   load_heap_oop(obj, field);
 802 }
 803 
 804 void MacroAssembler::get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj) {
 805 #ifdef ASSERT
 806   {
 807     Label done_check;
 808     test_klass_is_empty_inline_type(inline_klass, temp_reg, done_check);
 809     stop("get_empty_value from non-empty inline klass");
 810     bind(done_check);
 811   }
 812 #endif
 813   get_default_value_oop(inline_klass, temp_reg, obj);
 814 }
 815 
 816 // Look up the method for a megamorphic invokeinterface call.
 817 // The target method is determined by <intf_klass, itable_index>.
 818 // The receiver klass is in recv_klass.
 819 // On success, the result will be in method_result, and execution falls through.
 820 // On failure, execution transfers to the given label.
 821 void MacroAssembler::lookup_interface_method(Register recv_klass,
 822                                              Register intf_klass,
 823                                              RegisterOrConstant itable_index,
 824                                              Register method_result,
 825                                              Register scan_temp,
 826                                              Label& L_no_such_interface,
 827                          bool return_method) {
 828   assert_different_registers(recv_klass, intf_klass, scan_temp);
 829   assert_different_registers(method_result, intf_klass, scan_temp);
 830   assert(recv_klass != method_result || !return_method,
 831      "recv_klass can be destroyed when method isn't needed");
 832   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
 833          "caller must use same register for non-constant itable index as for method");
 834 
 835   // Compute start of first itableOffsetEntry (which is at the end of the vtable)

1146   ldrb(scratch, Address(klass, InstanceKlass::init_state_offset()));
1147   subs(zr, scratch, InstanceKlass::fully_initialized);
1148   br(Assembler::EQ, *L_fast_path);
1149 
1150   // Fast path check: current thread is initializer thread
1151   ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
1152   cmp(rthread, scratch);
1153 
1154   if (L_slow_path == &L_fallthrough) {
1155     br(Assembler::EQ, *L_fast_path);
1156     bind(*L_slow_path);
1157   } else if (L_fast_path == &L_fallthrough) {
1158     br(Assembler::NE, *L_slow_path);
1159     bind(*L_fast_path);
1160   } else {
1161     Unimplemented();
1162   }
1163 }
1164 
1165 void MacroAssembler::verify_oop(Register reg, const char* s) {
1166   if (!VerifyOops || VerifyAdapterSharing) {
1167     // Below address of the code string confuses VerifyAdapterSharing
1168     // because it may differ between otherwise equivalent adapters.
1169     return;
1170   }
1171 
1172   // Pass register number to verify_oop_subroutine
1173   const char* b = NULL;
1174   {
1175     ResourceMark rm;
1176     stringStream ss;
1177     ss.print("verify_oop: %s: %s", reg->name(), s);
1178     b = code_string(ss.as_string());
1179   }
1180   BLOCK_COMMENT("verify_oop {");
1181 
1182   strip_return_address(); // This might happen within a stack frame.
1183   protect_return_address();
1184   stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1185   stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1186 
1187   mov(r0, reg);
1188   movptr(rscratch1, (uintptr_t)(address)b);
1189 
1190   // call indirectly to solve generation ordering problem
1191   lea(rscratch2, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1192   ldr(rscratch2, Address(rscratch2));
1193   blr(rscratch2);
1194 
1195   ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1196   ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1197   authenticate_return_address();
1198 
1199   BLOCK_COMMENT("} verify_oop");
1200 }
1201 
1202 void MacroAssembler::verify_oop_addr(Address addr, const char* s) {
1203   if (!VerifyOops || VerifyAdapterSharing) {
1204     // Below address of the code string confuses VerifyAdapterSharing
1205     // because it may differ between otherwise equivalent adapters.
1206     return;
1207   }
1208 
1209   const char* b = NULL;
1210   {
1211     ResourceMark rm;
1212     stringStream ss;
1213     ss.print("verify_oop_addr: %s", s);
1214     b = code_string(ss.as_string());
1215   }
1216   BLOCK_COMMENT("verify_oop_addr {");
1217 
1218   strip_return_address(); // This might happen within a stack frame.
1219   protect_return_address();
1220   stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1221   stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1222 
1223   // addr may contain sp so we will have to adjust it based on the
1224   // pushes that we just did.
1225   if (addr.uses(sp)) {
1226     lea(r0, addr);
1227     ldr(r0, Address(r0, 4 * wordSize));

1269   stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
1270 
1271   mov(rscratch1, entry_point);
1272   blr(rscratch1);
1273   if (retaddr)
1274     bind(*retaddr);
1275 
1276   ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
1277 }
1278 
1279 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1280   call_VM_leaf_base(entry_point, number_of_arguments);
1281 }
1282 
1283 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1284   pass_arg0(this, arg_0);
1285   call_VM_leaf_base(entry_point, 1);
1286 }
1287 
1288 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1289   assert_different_registers(arg_1, c_rarg0);
1290   pass_arg0(this, arg_0);
1291   pass_arg1(this, arg_1);
1292   call_VM_leaf_base(entry_point, 2);
1293 }
1294 
1295 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1296                                   Register arg_1, Register arg_2) {
1297   assert_different_registers(arg_1, c_rarg0);
1298   assert_different_registers(arg_2, c_rarg0, c_rarg1);
1299   pass_arg0(this, arg_0);
1300   pass_arg1(this, arg_1);
1301   pass_arg2(this, arg_2);
1302   call_VM_leaf_base(entry_point, 3);
1303 }
1304 
1305 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1306   MacroAssembler::call_VM_leaf_base(entry_point, 1);
1307 }
1308 
1309 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1310   pass_arg0(this, arg_0);
1311   MacroAssembler::call_VM_leaf_base(entry_point, 1);
1312 }
1313 
1314 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1315 
1316   assert(arg_0 != c_rarg1, "smashed arg");
1317   pass_arg1(this, arg_1);
1318   pass_arg0(this, arg_0);
1319   MacroAssembler::call_VM_leaf_base(entry_point, 2);
1320 }
1321 
1322 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1323   assert(arg_0 != c_rarg2, "smashed arg");
1324   assert(arg_1 != c_rarg2, "smashed arg");
1325   pass_arg2(this, arg_2);
1326   assert(arg_0 != c_rarg1, "smashed arg");
1327   pass_arg1(this, arg_1);
1328   pass_arg0(this, arg_0);

1338   assert(arg_1 != c_rarg2, "smashed arg");
1339   pass_arg2(this, arg_2);
1340   assert(arg_0 != c_rarg1, "smashed arg");
1341   pass_arg1(this, arg_1);
1342   pass_arg0(this, arg_0);
1343   MacroAssembler::call_VM_leaf_base(entry_point, 4);
1344 }
1345 
1346 void MacroAssembler::null_check(Register reg, int offset) {
1347   if (needs_explicit_null_check(offset)) {
1348     // provoke OS NULL exception if reg = NULL by
1349     // accessing M[reg] w/o changing any registers
1350     // NOTE: this is plenty to provoke a segv
1351     ldr(zr, Address(reg));
1352   } else {
1353     // nothing to do, (later) access of M[reg + offset]
1354     // will provoke OS NULL exception if reg = NULL
1355   }
1356 }
1357 
1358 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
1359   assert_different_registers(markword, rscratch2);
1360   andr(markword, markword, markWord::inline_type_mask_in_place);
1361   mov(rscratch2, markWord::inline_type_pattern);
1362   cmp(markword, rscratch2);
1363   br(Assembler::EQ, is_inline_type);
1364 }
1365 
1366 void MacroAssembler::test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type) {
1367   ldrw(temp_reg, Address(klass, Klass::access_flags_offset()));
1368   andr(temp_reg, temp_reg, JVM_ACC_VALUE);
1369   cbnz(temp_reg, is_inline_type);
1370 }
1371 
1372 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type) {
1373   assert_different_registers(tmp, rscratch1);
1374   cbz(object, not_inline_type);
1375   const int is_inline_type_mask = markWord::inline_type_pattern;
1376   ldr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
1377   mov(rscratch1, is_inline_type_mask);
1378   andr(tmp, tmp, rscratch1);
1379   cmp(tmp, rscratch1);
1380   br(Assembler::NE, not_inline_type);
1381 }
1382 
1383 void MacroAssembler::test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type) {
1384 #ifdef ASSERT
1385   {
1386     Label done_check;
1387     test_klass_is_inline_type(klass, temp_reg, done_check);
1388     stop("test_klass_is_empty_inline_type with non inline type klass");
1389     bind(done_check);
1390   }
1391 #endif
1392   ldrw(temp_reg, Address(klass, InstanceKlass::misc_flags_offset()));
1393   andr(temp_reg, temp_reg, InstanceKlass::misc_flag_is_empty_inline_type());
1394   cbnz(temp_reg, is_empty_inline_type);
1395 }
1396 
1397 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
1398   assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
1399   tbnz(flags, ConstantPoolCacheEntry::is_null_free_inline_type_shift, is_null_free_inline_type);
1400 }
1401 
1402 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
1403   assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
1404   tbz(flags, ConstantPoolCacheEntry::is_null_free_inline_type_shift, not_null_free_inline_type);
1405 }
1406 
1407 void MacroAssembler::test_field_is_inlined(Register flags, Register temp_reg, Label& is_flattened) {
1408   assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
1409   tbnz(flags, ConstantPoolCacheEntry::is_inlined_shift, is_flattened);
1410 }
1411 
1412 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
1413   Label test_mark_word;
1414   // load mark word
1415   ldr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
1416   // check displaced
1417   tst(temp_reg, markWord::unlocked_value);
1418   br(Assembler::NE, test_mark_word);
1419   // slow path use klass prototype
1420   load_prototype_header(temp_reg, oop);
1421 
1422   bind(test_mark_word);
1423   andr(temp_reg, temp_reg, test_bit);
1424   if (jmp_set) {
1425     cbnz(temp_reg, jmp_label);
1426   } else {
1427     cbz(temp_reg, jmp_label);
1428   }
1429 }
1430 
1431 void MacroAssembler::test_flattened_array_oop(Register oop, Register temp_reg, Label& is_flattened_array) {
1432   test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flattened_array);
1433 }
1434 
1435 void MacroAssembler::test_non_flattened_array_oop(Register oop, Register temp_reg,
1436                                                   Label&is_non_flattened_array) {
1437   test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flattened_array);
1438 }
1439 
1440 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array) {
1441   test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
1442 }
1443 
1444 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
1445   test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
1446 }
1447 
1448 void MacroAssembler::test_flattened_array_layout(Register lh, Label& is_flattened_array) {
1449   tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
1450   br(Assembler::NE, is_flattened_array);
1451 }
1452 
1453 void MacroAssembler::test_non_flattened_array_layout(Register lh, Label& is_non_flattened_array) {
1454   tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
1455   br(Assembler::EQ, is_non_flattened_array);
1456 }
1457 
1458 void MacroAssembler::test_null_free_array_layout(Register lh, Label& is_null_free_array) {
1459   tst(lh, Klass::_lh_null_free_array_bit_inplace);
1460   br(Assembler::NE, is_null_free_array);
1461 }
1462 
1463 void MacroAssembler::test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array) {
1464   tst(lh, Klass::_lh_null_free_array_bit_inplace);
1465   br(Assembler::EQ, is_non_null_free_array);
1466 }
1467 
1468 // MacroAssembler protected routines needed to implement
1469 // public methods
1470 
1471 void MacroAssembler::mov(Register r, Address dest) {
1472   code_section()->relocate(pc(), dest.rspec());
1473   uint64_t imm64 = (uint64_t)dest.target();
1474   movptr(r, imm64);
1475 }
1476 
1477 // Move a constant pointer into r.  In AArch64 mode the virtual
1478 // address space is 48 bits in size, so we only need three
1479 // instructions to create a patchable instruction sequence that can
1480 // reach anywhere.
1481 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
1482 #ifndef PRODUCT
1483   {
1484     char buffer[64];
1485     snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
1486     block_comment(buffer);
1487   }

3846   adrp(rscratch1, src2, offset);
3847   ldr(rscratch1, Address(rscratch1, offset));
3848   cmp(src1, rscratch1);
3849 }
3850 
3851 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
3852   cmp(obj1, obj2);
3853 }
3854 
3855 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
3856   load_method_holder(rresult, rmethod);
3857   ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
3858 }
3859 
3860 void MacroAssembler::load_method_holder(Register holder, Register method) {
3861   ldr(holder, Address(method, Method::const_offset()));                      // ConstMethod*
3862   ldr(holder, Address(holder, ConstMethod::constants_offset()));             // ConstantPool*
3863   ldr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
3864 }
3865 
3866 void MacroAssembler::load_metadata(Register dst, Register src) {
3867   if (UseCompressedClassPointers) {
3868     ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3869   } else {
3870     ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3871   }
3872 }
3873 
3874 void MacroAssembler::load_klass(Register dst, Register src) {
3875   if (UseCompressedClassPointers) {
3876     ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3877     decode_klass_not_null(dst);
3878   } else {
3879     ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
3880   }
3881 }
3882 
3883 // ((OopHandle)result).resolve();
3884 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
3885   // OopHandle::resolve is an indirection.
3886   access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp, noreg);
3887 }
3888 
3889 // ((WeakHandle)result).resolve();
3890 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
3891   assert_different_registers(rresult, rtmp);
3892   Label resolved;
3893 

3913 
3914 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
3915   if (UseCompressedClassPointers) {
3916     ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3917     if (CompressedKlassPointers::base() == NULL) {
3918       cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
3919       return;
3920     } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
3921                && CompressedKlassPointers::shift() == 0) {
3922       // Only the bottom 32 bits matter
3923       cmpw(trial_klass, tmp);
3924       return;
3925     }
3926     decode_klass_not_null(tmp);
3927   } else {
3928     ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
3929   }
3930   cmp(trial_klass, tmp);
3931 }
3932 
3933 void MacroAssembler::load_prototype_header(Register dst, Register src) {
3934   load_klass(dst, src);
3935   ldr(dst, Address(dst, Klass::prototype_header_offset()));
3936 }
3937 
3938 void MacroAssembler::store_klass(Register dst, Register src) {
3939   // FIXME: Should this be a store release?  concurrent gcs assumes
3940   // klass length is valid if klass field is not null.
3941   if (UseCompressedClassPointers) {
3942     encode_klass_not_null(src);
3943     strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3944   } else {
3945     str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
3946   }
3947 }
3948 
3949 void MacroAssembler::store_klass_gap(Register dst, Register src) {
3950   if (UseCompressedClassPointers) {
3951     // Store to klass gap in destination
3952     strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
3953   }
3954 }
3955 
3956 // Algorithm must match CompressedOops::encode.
3957 void MacroAssembler::encode_heap_oop(Register d, Register s) {

4231   narrowKlass nk = CompressedKlassPointers::encode(k);
4232   movz(dst, (nk >> 16), 16);
4233   movk(dst, nk & 0xffff);
4234 }
4235 
4236 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
4237                                     Register dst, Address src,
4238                                     Register tmp1, Register thread_tmp) {
4239   BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4240   decorators = AccessInternal::decorator_fixup(decorators);
4241   bool as_raw = (decorators & AS_RAW) != 0;
4242   if (as_raw) {
4243     bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4244   } else {
4245     bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4246   }
4247 }
4248 
4249 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
4250                                      Address dst, Register src,
4251                                      Register tmp1, Register thread_tmp, Register tmp3) {
4252 
4253   BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4254   decorators = AccessInternal::decorator_fixup(decorators);
4255   bool as_raw = (decorators & AS_RAW) != 0;
4256   if (as_raw) {
4257     bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, thread_tmp, tmp3);
4258   } else {
4259     bs->store_at(this, decorators, type, dst, src, tmp1, thread_tmp, tmp3);
4260   }
4261 }
4262 
4263 void MacroAssembler::access_value_copy(DecoratorSet decorators, Register src, Register dst,
4264                                        Register inline_klass) {
4265   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4266   bs->value_copy(this, decorators, src, dst, inline_klass);
4267 }
4268 
4269 void MacroAssembler::first_field_offset(Register inline_klass, Register offset) {
4270   ldr(offset, Address(inline_klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
4271   ldrw(offset, Address(offset, InlineKlass::first_field_offset_offset()));
4272 }
4273 
4274 void MacroAssembler::data_for_oop(Register oop, Register data, Register inline_klass) {
4275   // ((address) (void*) o) + vk->first_field_offset();
4276   Register offset = (data == oop) ? rscratch1 : data;
4277   first_field_offset(inline_klass, offset);
4278   if (data == oop) {
4279     add(data, data, offset);
4280   } else {
4281     lea(data, Address(oop, offset));
4282   }
4283 }
4284 
4285 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
4286                                                 Register index, Register data) {
4287   assert_different_registers(array, array_klass, index);
4288   assert_different_registers(rscratch1, array, index);
4289 
4290   // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
4291   ldrw(rscratch1, Address(array_klass, Klass::layout_helper_offset()));
4292 
4293   // Klass::layout_helper_log2_element_size(lh)
4294   // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
4295   lsr(rscratch1, rscratch1, Klass::_lh_log2_element_size_shift);
4296   andr(rscratch1, rscratch1, Klass::_lh_log2_element_size_mask);
4297   lslv(index, index, rscratch1);
4298 
4299   add(data, array, index);
4300   add(data, data, arrayOopDesc::base_offset_in_bytes(T_PRIMITIVE_OBJECT));
4301 }
4302 
4303 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
4304                                    Register thread_tmp, DecoratorSet decorators) {
4305   access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
4306 }
4307 
4308 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4309                                             Register thread_tmp, DecoratorSet decorators) {
4310   access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
4311 }
4312 
4313 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
4314                                     Register thread_tmp, Register tmp3, DecoratorSet decorators) {
4315   access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp, tmp3);
4316 }
4317 
4318 // Used for storing NULLs.
4319 void MacroAssembler::store_heap_oop_null(Address dst) {
4320   access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
4321 }
4322 
4323 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
4324   assert(oop_recorder() != NULL, "this assembler needs a Recorder");
4325   int index = oop_recorder()->allocate_metadata_index(obj);
4326   RelocationHolder rspec = metadata_Relocation::spec(index);
4327   return Address((address)obj, rspec);
4328 }
4329 
4330 // Move an oop into a register.  immediate is true if we want
4331 // immediate instructions and nmethod entry barriers are not enabled.
4332 // i.e. we are not going to patch this instruction while the code is being
4333 // executed by another thread.
4334 void MacroAssembler::movoop(Register dst, jobject obj, bool immediate) {
4335   int oop_index;
4336   if (obj == NULL) {
4337     oop_index = oop_recorder()->allocate_oop_index(obj);
4338   } else {
4339 #ifdef ASSERT
4340     {

4364     oop_index = oop_recorder()->allocate_metadata_index(obj);
4365   } else {
4366     oop_index = oop_recorder()->find_index(obj);
4367   }
4368   RelocationHolder rspec = metadata_Relocation::spec(oop_index);
4369   mov(dst, Address((address)obj, rspec));
4370 }
4371 
4372 Address MacroAssembler::constant_oop_address(jobject obj) {
4373 #ifdef ASSERT
4374   {
4375     ThreadInVMfromUnknown tiv;
4376     assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
4377     assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
4378   }
4379 #endif
4380   int oop_index = oop_recorder()->find_index(obj);
4381   return Address((address)obj, oop_Relocation::spec(oop_index));
4382 }
4383 
4384 // Object / value buffer allocation...
4385 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
4386                                        Register t1, Register t2,
4387                                        bool clear_fields, Label& alloc_failed)
4388 {
4389   Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
4390   Register layout_size = t1;
4391   assert(new_obj == r0, "needs to be r0, according to barrier asm eden_allocate");
4392   assert_different_registers(klass, new_obj, t1, t2);
4393 
4394   // get instance_size in InstanceKlass (scaled to a count of bytes)
4395   ldrw(layout_size, Address(klass, Klass::layout_helper_offset()));
4396   // test to see if it has a finalizer or is malformed in some way
4397   tst(layout_size, Klass::_lh_instance_slow_path_bit);
4398   br(Assembler::NE, slow_case_no_pop);
4399 
4400   // Allocate the instance:
4401   //  If TLAB is enabled:
4402   //    Try to allocate in the TLAB.
4403   //    If fails, go to the slow path.
4404   //  Else If inline contiguous allocations are enabled:
4405   //    Try to allocate in eden.
4406   //    If fails due to heap end, go to slow path.
4407   //
4408   //  If TLAB is enabled OR inline contiguous is enabled:
4409   //    Initialize the allocation.
4410   //    Exit.
4411   //
4412   //  Go to slow path.
4413   const bool allow_shared_alloc =
4414     Universe::heap()->supports_inline_contig_alloc();
4415 
4416   push(klass);
4417 
4418   if (UseTLAB) {
4419     tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case);
4420     if (ZeroTLAB || (!clear_fields)) {
4421       // the fields have been already cleared
4422       b(initialize_header);
4423     } else {
4424       // initialize both the header and fields
4425       b(initialize_object);
4426     }
4427   } else {
4428     // Allocation in the shared Eden, if allowed.
4429     //
4430     eden_allocate(new_obj, layout_size, 0, t2, slow_case);
4431   }
4432 
4433   // If UseTLAB or allow_shared_alloc are true, the object is created above and
4434   // there is an initialize need. Otherwise, skip and go to the slow path.
4435   if (UseTLAB || allow_shared_alloc) {
4436     if (clear_fields) {
4437       // The object is initialized before the header.  If the object size is
4438       // zero, go directly to the header initialization.
4439       bind(initialize_object);
4440       subs(layout_size, layout_size, sizeof(oopDesc));
4441       br(Assembler::EQ, initialize_header);
4442 
4443       // Initialize topmost object field, divide size by 8, check if odd and
4444       // test if zero.
4445 
4446   #ifdef ASSERT
4447       // make sure instance_size was multiple of 8
4448       Label L;
4449       tst(layout_size, 7);
4450       br(Assembler::EQ, L);
4451       stop("object size is not multiple of 8 - adjust this code");
4452       bind(L);
4453       // must be > 0, no extra check needed here
4454   #endif
4455 
4456       lsr(layout_size, layout_size, LogBytesPerLong);
4457 
4458       // initialize remaining object fields: instance_size was a multiple of 8
4459       {
4460         Label loop;
4461         Register base = t2;
4462 
4463         bind(loop);
4464         add(rscratch1, new_obj, layout_size, Assembler::LSL, LogBytesPerLong);
4465         str(zr, Address(rscratch1, sizeof(oopDesc) - 1*oopSize));
4466         subs(layout_size, layout_size, 1);
4467         br(Assembler::NE, loop);
4468       }
4469     } // clear_fields
4470 
4471     // initialize object header only.
4472     bind(initialize_header);
4473     pop(klass);
4474     Register mark_word = t2;
4475     ldr(mark_word, Address(klass, Klass::prototype_header_offset()));
4476     str(mark_word, Address(new_obj, oopDesc::mark_offset_in_bytes ()));
4477     store_klass_gap(new_obj, zr);  // zero klass gap for compressed oops
4478     mov(t2, klass);         // preserve klass
4479     store_klass(new_obj, t2);  // src klass reg is potentially compressed
4480 
4481     b(done);
4482   }
4483 
4484   bind(slow_case);
4485   pop(klass);
4486   bind(slow_case_no_pop);
4487   b(alloc_failed);
4488 
4489   bind(done);
4490 }
4491 
4492 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4493 void MacroAssembler::tlab_allocate(Register obj,
4494                                    Register var_size_in_bytes,
4495                                    int con_size_in_bytes,
4496                                    Register t1,
4497                                    Register t2,
4498                                    Label& slow_case) {
4499   BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4500   bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4501 }
4502 
4503 // Defines obj, preserves var_size_in_bytes
4504 void MacroAssembler::eden_allocate(Register obj,
4505                                    Register var_size_in_bytes,
4506                                    int con_size_in_bytes,
4507                                    Register t1,
4508                                    Label& slow_case) {
4509   BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
4510   bs->eden_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
4511 }

4521     ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
4522     cmp(rscratch2, rscratch1);
4523     br(Assembler::HS, next);
4524     STOP("assert(top >= start)");
4525     should_not_reach_here();
4526 
4527     bind(next);
4528     ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
4529     ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
4530     cmp(rscratch2, rscratch1);
4531     br(Assembler::HS, ok);
4532     STOP("assert(top <= end)");
4533     should_not_reach_here();
4534 
4535     bind(ok);
4536     ldp(rscratch2, rscratch1, Address(post(sp, 16)));
4537   }
4538 #endif
4539 }
4540 
4541 void MacroAssembler::get_inline_type_field_klass(Register klass, Register index, Register inline_klass) {
4542   ldr(inline_klass, Address(klass, InstanceKlass::inline_type_field_klasses_offset()));
4543 #ifdef ASSERT
4544   {
4545     Label done;
4546     cbnz(inline_klass, done);
4547     stop("get_inline_type_field_klass contains no inline klass");
4548     bind(done);
4549   }
4550 #endif
4551   ldr(inline_klass, Address(inline_klass, index, Address::lsl(3)));
4552 }
4553 
4554 // Writes to stack successive pages until offset reached to check for
4555 // stack overflow + shadow pages.  This clobbers tmp.
4556 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
4557   assert_different_registers(tmp, size, rscratch1);
4558   mov(tmp, sp);
4559   // Bang stack for total size given plus shadow page size.
4560   // Bang one page at a time because large size can bang beyond yellow and
4561   // red zones.
4562   Label loop;
4563   mov(rscratch1, os::vm_page_size());
4564   bind(loop);
4565   lea(tmp, Address(tmp, -os::vm_page_size()));
4566   subsw(size, size, rscratch1);
4567   str(size, Address(tmp));
4568   br(Assembler::GT, loop);
4569 
4570   // Bang down shadow pages too.
4571   // At this point, (tmp-0) is the last address touched, so don't
4572   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
4573   // was post-decremented.)  Skip this address by starting at i=1, and

4659 }
4660 
4661 void MacroAssembler::remove_frame(int framesize) {
4662   assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
4663   assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
4664   if (framesize < ((1 << 9) + 2 * wordSize)) {
4665     ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
4666     add(sp, sp, framesize);
4667   } else {
4668     if (framesize < ((1 << 12) + 2 * wordSize))
4669       add(sp, sp, framesize - 2 * wordSize);
4670     else {
4671       mov(rscratch1, framesize - 2 * wordSize);
4672       add(sp, sp, rscratch1);
4673     }
4674     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
4675   }
4676   authenticate_return_address();
4677 }
4678 
4679 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
4680   if (needs_stack_repair) {
4681     // Remove the extension of the caller's frame used for inline type unpacking
4682     //
4683     // Right now the stack looks like this:
4684     //
4685     // | Arguments from caller     |
4686     // |---------------------------|  <-- caller's SP
4687     // | Saved LR #1               |
4688     // | Saved FP #1               |
4689     // |---------------------------|
4690     // | Extension space for       |
4691     // |   inline arg (un)packing  |
4692     // |---------------------------|  <-- start of this method's frame
4693     // | Saved LR #2               |
4694     // | Saved FP #2               |
4695     // |---------------------------|  <-- FP
4696     // | sp_inc                    |
4697     // | method locals             |
4698     // |---------------------------|  <-- SP
4699     //
4700     // There are two copies of FP and LR on the stack. They will be identical
4701     // unless the caller has been deoptimized, in which case LR #1 will be patched
4702     // to point at the deopt blob, and LR #2 will still point into the old method.
4703     //
4704     // The sp_inc stack slot holds the total size of the frame including the
4705     // extension space minus two words for the saved FP and LR.
4706 
4707     int sp_inc_offset = initial_framesize - 3 * wordSize;  // Immediately below saved LR and FP
4708 
4709     ldr(rscratch1, Address(sp, sp_inc_offset));
4710     add(sp, sp, rscratch1);
4711     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
4712   } else {
4713     remove_frame(initial_framesize);
4714   }
4715 }
4716 
4717 void MacroAssembler::save_stack_increment(int sp_inc, int frame_size) {
4718   int real_frame_size = frame_size + sp_inc;
4719   assert(sp_inc == 0 || sp_inc > 2*wordSize, "invalid sp_inc value");
4720   assert(real_frame_size >= 2*wordSize, "frame size must include FP/LR space");
4721   assert((real_frame_size & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
4722 
4723   int sp_inc_offset = frame_size - 3 * wordSize;  // Immediately below saved LR and FP
4724 
4725   // Subtract two words for the saved FP and LR as these will be popped
4726   // separately. See remove_frame above.
4727   mov(rscratch1, real_frame_size - 2*wordSize);
4728   str(rscratch1, Address(sp, sp_inc_offset));
4729 }
4730 
4731 // This method counts leading positive bytes (highest bit not set) in provided byte array
4732 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
4733     // Simple and most common case of aligned small array which is not at the
4734     // end of memory page is placed here. All other cases are in stub.
4735     Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
4736     const uint64_t UPPER_BIT_MASK=0x8080808080808080;
4737     assert_different_registers(ary1, len, result);
4738 
4739     mov(result, len);
4740     cmpw(len, 0);
4741     br(LE, DONE);
4742     cmpw(len, 4 * wordSize);
4743     br(GE, STUB_LONG); // size > 32 then go to stub
4744 
4745     int shift = 64 - exact_log2(os::vm_page_size());
4746     lsl(rscratch1, ary1, shift);
4747     mov(rscratch2, (size_t)(4 * wordSize) << shift);
4748     adds(rscratch2, rscratch1, rscratch2);  // At end of page?
4749     br(CS, STUB); // at the end of page then go to stub

5566 // On other systems, the helper is a usual C function.
5567 //
5568 void MacroAssembler::get_thread(Register dst) {
5569   RegSet saved_regs =
5570     LINUX_ONLY(RegSet::range(r0, r1)  + lr - dst)
5571     NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
5572 
5573   protect_return_address();
5574   push(saved_regs, sp);
5575 
5576   mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
5577   blr(lr);
5578   if (dst != c_rarg0) {
5579     mov(dst, c_rarg0);
5580   }
5581 
5582   pop(saved_regs, sp);
5583   authenticate_return_address();
5584 }
5585 
5586 #ifdef COMPILER2
5587 // C2 compiled method's prolog code
5588 // Moved here from aarch64.ad to support Valhalla code belows
5589 void MacroAssembler::verified_entry(Compile* C, int sp_inc) {
5590 
5591   // n.b. frame size includes space for return pc and rfp
5592   const long framesize = C->output()->frame_size_in_bytes();
5593 
5594   // insert a nop at the start of the prolog so we can patch in a
5595   // branch if we need to invalidate the method later
5596   nop();
5597 
5598   int bangsize = C->output()->bang_size_in_bytes();
5599   if (C->output()->need_stack_bang(bangsize))
5600     generate_stack_overflow_check(bangsize);
5601 
5602   build_frame(framesize);
5603 
5604   if (C->needs_stack_repair()) {
5605     save_stack_increment(sp_inc, framesize);
5606   }
5607 
5608   if (VerifyStackAtCalls) {
5609     Unimplemented();
5610   }
5611 }
5612 #endif // COMPILER2
5613 
5614 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
5615   assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
5616   // An inline type might be returned. If fields are in registers we
5617   // need to allocate an inline type instance and initialize it with
5618   // the value of the fields.
5619   Label skip;
5620   // We only need a new buffered inline type if a new one is not returned
5621   tbz(r0, 0, skip);
5622   int call_offset = -1;
5623 
5624   // Be careful not to clobber r1-7 which hold returned fields
5625   // Also do not use callee-saved registers as these may be live in the interpreter
5626   Register tmp1 = r13, tmp2 = r14, klass = r15, r0_preserved = r12;
5627 
5628   // The following code is similar to allocate_instance but has some slight differences,
5629   // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
5630   // allocating is not necessary if vk != NULL, etc. allocate_instance is not aware of these.
5631   Label slow_case;
5632   // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
5633   mov(r0_preserved, r0); // save r0 for slow_case since *_allocate may corrupt it when allocation failed
5634 
5635   if (vk != NULL) {
5636     // Called from C1, where the return type is statically known.
5637     movptr(klass, (intptr_t)vk->get_InlineKlass());
5638     jint obj_size = vk->layout_helper();
5639     assert(obj_size != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
5640     if (UseTLAB) {
5641       tlab_allocate(r0, noreg, obj_size, tmp1, tmp2, slow_case);
5642     } else {
5643       eden_allocate(r0, noreg, obj_size, tmp1, slow_case);
5644     }
5645   } else {
5646     // Call from interpreter. R0 contains ((the InlineKlass* of the return type) | 0x01)
5647     andr(klass, r0, -2);
5648     ldrw(tmp2, Address(klass, Klass::layout_helper_offset()));
5649     if (UseTLAB) {
5650       tlab_allocate(r0, tmp2, 0, tmp1, tmp2, slow_case);
5651     } else {
5652       eden_allocate(r0, tmp2, 0, tmp1, slow_case);
5653     }
5654   }
5655   if (UseTLAB || Universe::heap()->supports_inline_contig_alloc()) {
5656     // 2. Initialize buffered inline instance header
5657     Register buffer_obj = r0;
5658     mov(rscratch1, (intptr_t)markWord::inline_type_prototype().value());
5659     str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes()));
5660     store_klass_gap(buffer_obj, zr);
5661     if (vk == NULL) {
5662       // store_klass corrupts klass, so save it for later use (interpreter case only).
5663       mov(tmp1, klass);
5664     }
5665     store_klass(buffer_obj, klass);
5666     // 3. Initialize its fields with an inline class specific handler
5667     if (vk != NULL) {
5668       far_call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
5669     } else {
5670       // tmp1 holds klass preserved above
5671       ldr(tmp1, Address(tmp1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
5672       ldr(tmp1, Address(tmp1, InlineKlass::pack_handler_offset()));
5673       blr(tmp1);
5674     }
5675 
5676     membar(Assembler::StoreStore);
5677     b(skip);
5678   } else {
5679     // Must have already branched to slow_case in eden_allocate() above.
5680     DEBUG_ONLY(should_not_reach_here());
5681   }
5682   bind(slow_case);
5683   // We failed to allocate a new inline type, fall back to a runtime
5684   // call. Some oop field may be live in some registers but we can't
5685   // tell. That runtime call will take care of preserving them
5686   // across a GC if there's one.
5687   mov(r0, r0_preserved);
5688 
5689   if (from_interpreter) {
5690     super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
5691   } else {
5692     far_call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
5693     call_offset = offset();
5694   }
5695   membar(Assembler::StoreStore);
5696 
5697   bind(skip);
5698   return call_offset;
5699 }
5700 
5701 // Move a value between registers/stack slots and update the reg_state
5702 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
5703   assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
5704   if (reg_state[to->value()] == reg_written) {
5705     return true; // Already written
5706   }
5707 
5708   if (from != to && bt != T_VOID) {
5709     if (reg_state[to->value()] == reg_readonly) {
5710       return false; // Not yet writable
5711     }
5712     if (from->is_reg()) {
5713       if (to->is_reg()) {
5714         if (from->is_Register() && to->is_Register()) {
5715           mov(to->as_Register(), from->as_Register());
5716         } else if (from->is_FloatRegister() && to->is_FloatRegister()) {
5717           fmovd(to->as_FloatRegister(), from->as_FloatRegister());
5718         } else {
5719           ShouldNotReachHere();
5720         }
5721       } else {
5722         int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
5723         Address to_addr = Address(sp, st_off);
5724         if (from->is_FloatRegister()) {
5725           if (bt == T_DOUBLE) {
5726              strd(from->as_FloatRegister(), to_addr);
5727           } else {
5728              assert(bt == T_FLOAT, "must be float");
5729              strs(from->as_FloatRegister(), to_addr);
5730           }
5731         } else {
5732           str(from->as_Register(), to_addr);
5733         }
5734       }
5735     } else {
5736       Address from_addr = Address(sp, from->reg2stack() * VMRegImpl::stack_slot_size);
5737       if (to->is_reg()) {
5738         if (to->is_FloatRegister()) {
5739           if (bt == T_DOUBLE) {
5740             ldrd(to->as_FloatRegister(), from_addr);
5741           } else {
5742             assert(bt == T_FLOAT, "must be float");
5743             ldrs(to->as_FloatRegister(), from_addr);
5744           }
5745         } else {
5746           ldr(to->as_Register(), from_addr);
5747         }
5748       } else {
5749         int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
5750         ldr(rscratch1, from_addr);
5751         str(rscratch1, Address(sp, st_off));
5752       }
5753     }
5754   }
5755 
5756   // Update register states
5757   reg_state[from->value()] = reg_writable;
5758   reg_state[to->value()] = reg_written;
5759   return true;
5760 }
5761 
5762 // Calculate the extra stack space required for packing or unpacking inline
5763 // args and adjust the stack pointer
5764 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
5765   int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
5766   sp_inc = align_up(sp_inc, StackAlignmentInBytes);
5767   assert(sp_inc > 0, "sanity");
5768 
5769   // Save a copy of the FP and LR here for deoptimization patching and frame walking
5770   stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5771 
5772   // Adjust the stack pointer. This will be repaired on return by MacroAssembler::remove_frame
5773   if (sp_inc < (1 << 9)) {
5774     sub(sp, sp, sp_inc);   // Fits in an immediate
5775   } else {
5776     mov(rscratch1, sp_inc);
5777     sub(sp, sp, rscratch1);
5778   }
5779 
5780   return sp_inc + 2 * wordSize;  // Account for the FP/LR space
5781 }
5782 
5783 // Read all fields from an inline type oop and store the values in registers/stack slots
5784 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
5785                                           VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
5786                                           RegState reg_state[]) {
5787   assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
5788   assert(from->is_valid(), "source must be valid");
5789   bool progress = false;
5790 #ifdef ASSERT
5791   const int start_offset = offset();
5792 #endif
5793 
5794   Label L_null, L_notNull;
5795   // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
5796   Register tmp1 = r10;
5797   Register tmp2 = r11;
5798   Register fromReg = noreg;
5799   ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
5800   bool done = true;
5801   bool mark_done = true;
5802   VMReg toReg;
5803   BasicType bt;
5804   // Check if argument requires a null check
5805   bool null_check = false;
5806   VMReg nullCheckReg;
5807   while (stream.next(nullCheckReg, bt)) {
5808     if (sig->at(stream.sig_index())._offset == -1) {
5809       null_check = true;
5810       break;
5811     }
5812   }
5813   stream.reset(sig_index, to_index);
5814   while (stream.next(toReg, bt)) {
5815     assert(toReg->is_valid(), "destination must be valid");
5816     int idx = (int)toReg->value();
5817     if (reg_state[idx] == reg_readonly) {
5818       if (idx != from->value()) {
5819         mark_done = false;
5820       }
5821       done = false;
5822       continue;
5823     } else if (reg_state[idx] == reg_written) {
5824       continue;
5825     }
5826     assert(reg_state[idx] == reg_writable, "must be writable");
5827     reg_state[idx] = reg_written;
5828     progress = true;
5829 
5830     if (fromReg == noreg) {
5831       if (from->is_reg()) {
5832         fromReg = from->as_Register();
5833       } else {
5834         int st_off = from->reg2stack() * VMRegImpl::stack_slot_size;
5835         ldr(tmp1, Address(sp, st_off));
5836         fromReg = tmp1;
5837       }
5838       if (null_check) {
5839         // Nullable inline type argument, emit null check
5840         cbz(fromReg, L_null);
5841       }
5842     }
5843     int off = sig->at(stream.sig_index())._offset;
5844     if (off == -1) {
5845       assert(null_check, "Missing null check at");
5846       if (toReg->is_stack()) {
5847         int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
5848         mov(tmp2, 1);
5849         str(tmp2, Address(sp, st_off));
5850       } else {
5851         mov(toReg->as_Register(), 1);
5852       }
5853       continue;
5854     }
5855     assert(off > 0, "offset in object should be positive");
5856     Address fromAddr = Address(fromReg, off);
5857     if (!toReg->is_FloatRegister()) {
5858       Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
5859       if (is_reference_type(bt)) {
5860         load_heap_oop(dst, fromAddr);
5861       } else {
5862         bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
5863         load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
5864       }
5865       if (toReg->is_stack()) {
5866         int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
5867         str(dst, Address(sp, st_off));
5868       }
5869     } else if (bt == T_DOUBLE) {
5870       ldrd(toReg->as_FloatRegister(), fromAddr);
5871     } else {
5872       assert(bt == T_FLOAT, "must be float");
5873       ldrs(toReg->as_FloatRegister(), fromAddr);
5874     }
5875   }
5876   if (progress && null_check) {
5877     if (done) {
5878       b(L_notNull);
5879       bind(L_null);
5880       // Set IsInit field to zero to signal that the argument is null.
5881       // Also set all oop fields to zero to make the GC happy.
5882       stream.reset(sig_index, to_index);
5883       while (stream.next(toReg, bt)) {
5884         if (sig->at(stream.sig_index())._offset == -1 ||
5885             bt == T_OBJECT || bt == T_ARRAY) {
5886           if (toReg->is_stack()) {
5887             int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
5888             str(zr, Address(sp, st_off));
5889           } else {
5890             mov(toReg->as_Register(), zr);
5891           }
5892         }
5893       }
5894       bind(L_notNull);
5895     } else {
5896       bind(L_null);
5897     }
5898   }
5899 
5900   sig_index = stream.sig_index();
5901   to_index = stream.regs_index();
5902 
5903   if (mark_done && reg_state[from->value()] != reg_written) {
5904     // This is okay because no one else will write to that slot
5905     reg_state[from->value()] = reg_writable;
5906   }
5907   from_index--;
5908   assert(progress || (start_offset == offset()), "should not emit code");
5909   return done;
5910 }
5911 
5912 // Pack fields back into an inline type oop
5913 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
5914                                         VMRegPair* from, int from_count, int& from_index, VMReg to,
5915                                         RegState reg_state[], Register val_array) {
5916   assert(sig->at(sig_index)._bt == T_PRIMITIVE_OBJECT, "should be at end delimiter");
5917   assert(to->is_valid(), "destination must be valid");
5918 
5919   if (reg_state[to->value()] == reg_written) {
5920     skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
5921     return true; // Already written
5922   }
5923 
5924   // The GC barrier expanded by store_heap_oop below may call into the
5925   // runtime so use callee-saved registers for any values that need to be
5926   // preserved. The GC barrier assembler should take care of saving the
5927   // Java argument registers.
5928   // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
5929   // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
5930   Register val_obj_tmp = r21;
5931   Register from_reg_tmp = r22;
5932   Register tmp1 = r14;
5933   Register tmp2 = r13;
5934   Register tmp3 = r12;
5935   Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
5936 
5937   assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
5938 
5939   if (reg_state[to->value()] == reg_readonly) {
5940     if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
5941       skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
5942       return false; // Not yet writable
5943     }
5944     val_obj = val_obj_tmp;
5945   }
5946 
5947   int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_PRIMITIVE_OBJECT);
5948   load_heap_oop(val_obj, Address(val_array, index));
5949 
5950   ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
5951   VMReg fromReg;
5952   BasicType bt;
5953   Label L_null;
5954   while (stream.next(fromReg, bt)) {
5955     assert(fromReg->is_valid(), "source must be valid");
5956     reg_state[fromReg->value()] = reg_writable;
5957 
5958     int off = sig->at(stream.sig_index())._offset;
5959     if (off == -1) {
5960       // Nullable inline type argument, emit null check
5961       Label L_notNull;
5962       if (fromReg->is_stack()) {
5963         int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
5964         ldr(tmp2, Address(sp, ld_off));
5965         cbnz(tmp2, L_notNull);
5966       } else {
5967         cbnz(fromReg->as_Register(), L_notNull);
5968       }
5969       mov(val_obj, 0);
5970       b(L_null);
5971       bind(L_notNull);
5972       continue;
5973     }
5974 
5975     assert(off > 0, "offset in object should be positive");
5976     size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
5977 
5978     // Pack the scalarized field into the value object.
5979     Address dst(val_obj, off);
5980 
5981     if (!fromReg->is_FloatRegister()) {
5982       Register src;
5983       if (fromReg->is_stack()) {
5984         src = from_reg_tmp;
5985         int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
5986         load_sized_value(src, Address(sp, ld_off), size_in_bytes, /* is_signed */ false);
5987       } else {
5988         src = fromReg->as_Register();
5989       }
5990       assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
5991       if (is_reference_type(bt)) {
5992         store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
5993       } else {
5994         store_sized_value(dst, src, size_in_bytes);
5995       }
5996     } else if (bt == T_DOUBLE) {
5997       strd(fromReg->as_FloatRegister(), dst);
5998     } else {
5999       assert(bt == T_FLOAT, "must be float");
6000       strs(fromReg->as_FloatRegister(), dst);
6001     }
6002   }
6003   bind(L_null);
6004   sig_index = stream.sig_index();
6005   from_index = stream.regs_index();
6006 
6007   assert(reg_state[to->value()] == reg_writable, "must have already been read");
6008   bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6009   assert(success, "to register must be writeable");
6010 
6011   return true;
6012 }
6013 
6014 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6015   return (reg->is_FloatRegister()) ? v0->as_VMReg() : r14->as_VMReg();
6016 }
6017 
6018 void MacroAssembler::cache_wb(Address line) {
6019   assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6020   assert(line.index() == noreg, "index should be noreg");
6021   assert(line.offset() == 0, "offset should be 0");
6022   // would like to assert this
6023   // assert(line._ext.shift == 0, "shift should be zero");
6024   if (VM_Version::features() & VM_Version::CPU_DCPOP) {
6025     // writeback using clear virtual address to point of persistence
6026     dc(Assembler::CVAP, line.base());
6027   } else {
6028     // no need to generate anything as Unsafe.writebackMemory should
6029     // never invoke this stub
6030   }
6031 }
6032 
6033 void MacroAssembler::cache_wbsync(bool is_pre) {
6034   // we only need a barrier post sync
6035   if (!is_pre) {
6036     membar(Assembler::AnyAny);
6037   }
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