10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "ci/ciEnv.hpp"
30 #include "code/compiledIC.hpp"
31 #include "compiler/compileTask.hpp"
32 #include "compiler/disassembler.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "gc/shared/barrierSet.hpp"
35 #include "gc/shared/barrierSetAssembler.hpp"
36 #include "gc/shared/cardTableBarrierSet.hpp"
37 #include "gc/shared/cardTable.hpp"
38 #include "gc/shared/collectedHeap.hpp"
39 #include "gc/shared/tlab_globals.hpp"
40 #include "interpreter/bytecodeHistogram.hpp"
41 #include "interpreter/interpreter.hpp"
42 #include "jvm.h"
43 #include "memory/resourceArea.hpp"
44 #include "memory/universe.hpp"
45 #include "nativeInst_aarch64.hpp"
46 #include "oops/accessDecorators.hpp"
47 #include "oops/compressedKlass.inline.hpp"
48 #include "oops/compressedOops.inline.hpp"
49 #include "oops/klass.inline.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/icache.hpp"
52 #include "runtime/interfaceSupport.inline.hpp"
53 #include "runtime/javaThread.hpp"
54 #include "runtime/jniHandles.inline.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/globalDefinitions.hpp"
58 #include "utilities/powerOfTwo.hpp"
59 #ifdef COMPILER1
60 #include "c1/c1_LIRAssembler.hpp"
61 #endif
62 #ifdef COMPILER2
63 #include "oops/oop.hpp"
64 #include "opto/compile.hpp"
65 #include "opto/node.hpp"
66 #include "opto/output.hpp"
67 #endif
68
69 #include <sys/types.h>
70
71 #ifdef PRODUCT
72 #define BLOCK_COMMENT(str) /* nothing */
73 #else
74 #define BLOCK_COMMENT(str) block_comment(str)
75 #endif
76 #define STOP(str) stop(str);
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
1154 }
1155
1156 void MacroAssembler::post_call_nop() {
1157 if (!Continuations::enabled()) {
1158 return;
1159 }
1160 InstructionMark im(this);
1161 relocate(post_call_nop_Relocation::spec());
1162 InlineSkippedInstructionsCounter skipCounter(this);
1163 nop();
1164 movk(zr, 0);
1165 movk(zr, 0);
1166 }
1167
1168 // these are no-ops overridden by InterpreterMacroAssembler
1169
1170 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1171
1172 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1173
1174 // Look up the method for a megamorphic invokeinterface call.
1175 // The target method is determined by <intf_klass, itable_index>.
1176 // The receiver klass is in recv_klass.
1177 // On success, the result will be in method_result, and execution falls through.
1178 // On failure, execution transfers to the given label.
1179 void MacroAssembler::lookup_interface_method(Register recv_klass,
1180 Register intf_klass,
1181 RegisterOrConstant itable_index,
1182 Register method_result,
1183 Register scan_temp,
1184 Label& L_no_such_interface,
1185 bool return_method) {
1186 assert_different_registers(recv_klass, intf_klass, scan_temp);
1187 assert_different_registers(method_result, intf_klass, scan_temp);
1188 assert(recv_klass != method_result || !return_method,
1189 "recv_klass can be destroyed when method isn't needed");
1190 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1191 "caller must use same register for non-constant itable index as for method");
1192
1193 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1842 ldarb(scratch, scratch);
1843 subs(zr, scratch, InstanceKlass::fully_initialized);
1844 br(Assembler::EQ, *L_fast_path);
1845
1846 // Fast path check: current thread is initializer thread
1847 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
1848 cmp(rthread, scratch);
1849
1850 if (L_slow_path == &L_fallthrough) {
1851 br(Assembler::EQ, *L_fast_path);
1852 bind(*L_slow_path);
1853 } else if (L_fast_path == &L_fallthrough) {
1854 br(Assembler::NE, *L_slow_path);
1855 bind(*L_fast_path);
1856 } else {
1857 Unimplemented();
1858 }
1859 }
1860
1861 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
1862 if (!VerifyOops) return;
1863
1864 // Pass register number to verify_oop_subroutine
1865 const char* b = nullptr;
1866 {
1867 ResourceMark rm;
1868 stringStream ss;
1869 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
1870 b = code_string(ss.as_string());
1871 }
1872 BLOCK_COMMENT("verify_oop {");
1873
1874 strip_return_address(); // This might happen within a stack frame.
1875 protect_return_address();
1876 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1877 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1878
1879 mov(r0, reg);
1880 movptr(rscratch1, (uintptr_t)(address)b);
1881
1882 // call indirectly to solve generation ordering problem
1883 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1884 ldr(rscratch2, Address(rscratch2));
1885 blr(rscratch2);
1886
1887 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1888 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1889 authenticate_return_address();
1890
1891 BLOCK_COMMENT("} verify_oop");
1892 }
1893
1894 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
1895 if (!VerifyOops) return;
1896
1897 const char* b = nullptr;
1898 {
1899 ResourceMark rm;
1900 stringStream ss;
1901 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
1902 b = code_string(ss.as_string());
1903 }
1904 BLOCK_COMMENT("verify_oop_addr {");
1905
1906 strip_return_address(); // This might happen within a stack frame.
1907 protect_return_address();
1908 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1909 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1910
1911 // addr may contain sp so we will have to adjust it based on the
1912 // pushes that we just did.
1913 if (addr.uses(sp)) {
1914 lea(r0, addr);
1915 ldr(r0, Address(r0, 4 * wordSize));
1973 call_VM_leaf_base(entry_point, 1);
1974 }
1975
1976 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1977 assert_different_registers(arg_1, c_rarg0);
1978 pass_arg0(this, arg_0);
1979 pass_arg1(this, arg_1);
1980 call_VM_leaf_base(entry_point, 2);
1981 }
1982
1983 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
1984 Register arg_1, Register arg_2) {
1985 assert_different_registers(arg_1, c_rarg0);
1986 assert_different_registers(arg_2, c_rarg0, c_rarg1);
1987 pass_arg0(this, arg_0);
1988 pass_arg1(this, arg_1);
1989 pass_arg2(this, arg_2);
1990 call_VM_leaf_base(entry_point, 3);
1991 }
1992
1993 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1994 pass_arg0(this, arg_0);
1995 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1996 }
1997
1998 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1999
2000 assert_different_registers(arg_0, c_rarg1);
2001 pass_arg1(this, arg_1);
2002 pass_arg0(this, arg_0);
2003 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2004 }
2005
2006 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2007 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2008 assert_different_registers(arg_1, c_rarg2);
2009 pass_arg2(this, arg_2);
2010 pass_arg1(this, arg_1);
2011 pass_arg0(this, arg_0);
2012 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2018 assert_different_registers(arg_2, c_rarg3);
2019 pass_arg3(this, arg_3);
2020 pass_arg2(this, arg_2);
2021 pass_arg1(this, arg_1);
2022 pass_arg0(this, arg_0);
2023 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2024 }
2025
2026 void MacroAssembler::null_check(Register reg, int offset) {
2027 if (needs_explicit_null_check(offset)) {
2028 // provoke OS null exception if reg is null by
2029 // accessing M[reg] w/o changing any registers
2030 // NOTE: this is plenty to provoke a segv
2031 ldr(zr, Address(reg));
2032 } else {
2033 // nothing to do, (later) access of M[reg + offset]
2034 // will provoke OS null exception if reg is null
2035 }
2036 }
2037
2038 // MacroAssembler protected routines needed to implement
2039 // public methods
2040
2041 void MacroAssembler::mov(Register r, Address dest) {
2042 code_section()->relocate(pc(), dest.rspec());
2043 uint64_t imm64 = (uint64_t)dest.target();
2044 movptr(r, imm64);
2045 }
2046
2047 // Move a constant pointer into r. In AArch64 mode the virtual
2048 // address space is 48 bits in size, so we only need three
2049 // instructions to create a patchable instruction sequence that can
2050 // reach anywhere.
2051 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2052 #ifndef PRODUCT
2053 {
2054 char buffer[64];
2055 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2056 block_comment(buffer);
2057 }
4822 adrp(rscratch1, src2, offset);
4823 ldr(rscratch1, Address(rscratch1, offset));
4824 cmp(src1, rscratch1);
4825 }
4826
4827 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4828 cmp(obj1, obj2);
4829 }
4830
4831 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4832 load_method_holder(rresult, rmethod);
4833 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4834 }
4835
4836 void MacroAssembler::load_method_holder(Register holder, Register method) {
4837 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
4838 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
4839 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
4840 }
4841
4842 void MacroAssembler::load_klass(Register dst, Register src) {
4843 if (UseCompressedClassPointers) {
4844 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4845 decode_klass_not_null(dst);
4846 } else {
4847 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4848 }
4849 }
4850
4851 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
4852 if (RestoreMXCSROnJNICalls) {
4853 Label OK;
4854 get_fpcr(tmp1);
4855 mov(tmp2, tmp1);
4856 // Set FPCR to the state we need. We do want Round to Nearest. We
4857 // don't want non-IEEE rounding modes or floating-point traps.
4858 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
4859 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
4860 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
4861 eor(tmp2, tmp1, tmp2);
4897
4898 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
4899 if (UseCompressedClassPointers) {
4900 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4901 if (CompressedKlassPointers::base() == nullptr) {
4902 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
4903 return;
4904 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
4905 && CompressedKlassPointers::shift() == 0) {
4906 // Only the bottom 32 bits matter
4907 cmpw(trial_klass, tmp);
4908 return;
4909 }
4910 decode_klass_not_null(tmp);
4911 } else {
4912 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
4913 }
4914 cmp(trial_klass, tmp);
4915 }
4916
4917 void MacroAssembler::store_klass(Register dst, Register src) {
4918 // FIXME: Should this be a store release? concurrent gcs assumes
4919 // klass length is valid if klass field is not null.
4920 if (UseCompressedClassPointers) {
4921 encode_klass_not_null(src);
4922 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4923 } else {
4924 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
4925 }
4926 }
4927
4928 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4929 if (UseCompressedClassPointers) {
4930 // Store to klass gap in destination
4931 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
4932 }
4933 }
4934
4935 // Algorithm must match CompressedOops::encode.
4936 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5223 if (as_raw) {
5224 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5225 } else {
5226 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5227 }
5228 }
5229
5230 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5231 Address dst, Register val,
5232 Register tmp1, Register tmp2, Register tmp3) {
5233 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5234 decorators = AccessInternal::decorator_fixup(decorators, type);
5235 bool as_raw = (decorators & AS_RAW) != 0;
5236 if (as_raw) {
5237 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5238 } else {
5239 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5240 }
5241 }
5242
5243 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5244 Register tmp2, DecoratorSet decorators) {
5245 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5246 }
5247
5248 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5249 Register tmp2, DecoratorSet decorators) {
5250 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5251 }
5252
5253 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5254 Register tmp2, Register tmp3, DecoratorSet decorators) {
5255 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5256 }
5257
5258 // Used for storing nulls.
5259 void MacroAssembler::store_heap_oop_null(Address dst) {
5260 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5261 }
5262
5299 oop_index = oop_recorder()->allocate_metadata_index(obj);
5300 } else {
5301 oop_index = oop_recorder()->find_index(obj);
5302 }
5303 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5304 mov(dst, Address((address)obj, rspec));
5305 }
5306
5307 Address MacroAssembler::constant_oop_address(jobject obj) {
5308 #ifdef ASSERT
5309 {
5310 ThreadInVMfromUnknown tiv;
5311 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5312 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5313 }
5314 #endif
5315 int oop_index = oop_recorder()->find_index(obj);
5316 return Address((address)obj, oop_Relocation::spec(oop_index));
5317 }
5318
5319 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5320 void MacroAssembler::tlab_allocate(Register obj,
5321 Register var_size_in_bytes,
5322 int con_size_in_bytes,
5323 Register t1,
5324 Register t2,
5325 Label& slow_case) {
5326 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5327 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5328 }
5329
5330 void MacroAssembler::verify_tlab() {
5331 #ifdef ASSERT
5332 if (UseTLAB && VerifyOops) {
5333 Label next, ok;
5334
5335 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5336
5337 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5338 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5339 cmp(rscratch2, rscratch1);
5340 br(Assembler::HS, next);
5341 STOP("assert(top >= start)");
5342 should_not_reach_here();
5343
5344 bind(next);
5345 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5346 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5347 cmp(rscratch2, rscratch1);
5348 br(Assembler::HS, ok);
5349 STOP("assert(top <= end)");
5350 should_not_reach_here();
5351
5352 bind(ok);
5353 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5354 }
5355 #endif
5356 }
5357
5358 // Writes to stack successive pages until offset reached to check for
5359 // stack overflow + shadow pages. This clobbers tmp.
5360 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5361 assert_different_registers(tmp, size, rscratch1);
5362 mov(tmp, sp);
5363 // Bang stack for total size given plus shadow page size.
5364 // Bang one page at a time because large size can bang beyond yellow and
5365 // red zones.
5366 Label loop;
5367 mov(rscratch1, (int)os::vm_page_size());
5368 bind(loop);
5369 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5370 subsw(size, size, rscratch1);
5371 str(size, Address(tmp));
5372 br(Assembler::GT, loop);
5373
5374 // Bang down shadow pages too.
5375 // At this point, (tmp-0) is the last address touched, so don't
5376 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5377 // was post-decremented.) Skip this address by starting at i=1, and
5463 }
5464
5465 void MacroAssembler::remove_frame(int framesize) {
5466 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5467 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5468 if (framesize < ((1 << 9) + 2 * wordSize)) {
5469 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5470 add(sp, sp, framesize);
5471 } else {
5472 if (framesize < ((1 << 12) + 2 * wordSize))
5473 add(sp, sp, framesize - 2 * wordSize);
5474 else {
5475 mov(rscratch1, framesize - 2 * wordSize);
5476 add(sp, sp, rscratch1);
5477 }
5478 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5479 }
5480 authenticate_return_address();
5481 }
5482
5483
5484 // This method counts leading positive bytes (highest bit not set) in provided byte array
5485 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5486 // Simple and most common case of aligned small array which is not at the
5487 // end of memory page is placed here. All other cases are in stub.
5488 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5489 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5490 assert_different_registers(ary1, len, result);
5491
5492 mov(result, len);
5493 cmpw(len, 0);
5494 br(LE, DONE);
5495 cmpw(len, 4 * wordSize);
5496 br(GE, STUB_LONG); // size > 32 then go to stub
5497
5498 int shift = 64 - exact_log2(os::vm_page_size());
5499 lsl(rscratch1, ary1, shift);
5500 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5501 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5502 br(CS, STUB); // at the end of page then go to stub
6376 // On other systems, the helper is a usual C function.
6377 //
6378 void MacroAssembler::get_thread(Register dst) {
6379 RegSet saved_regs =
6380 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6381 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6382
6383 protect_return_address();
6384 push(saved_regs, sp);
6385
6386 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
6387 blr(lr);
6388 if (dst != c_rarg0) {
6389 mov(dst, c_rarg0);
6390 }
6391
6392 pop(saved_regs, sp);
6393 authenticate_return_address();
6394 }
6395
6396 void MacroAssembler::cache_wb(Address line) {
6397 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6398 assert(line.index() == noreg, "index should be noreg");
6399 assert(line.offset() == 0, "offset should be 0");
6400 // would like to assert this
6401 // assert(line._ext.shift == 0, "shift should be zero");
6402 if (VM_Version::supports_dcpop()) {
6403 // writeback using clear virtual address to point of persistence
6404 dc(Assembler::CVAP, line.base());
6405 } else {
6406 // no need to generate anything as Unsafe.writebackMemory should
6407 // never invoke this stub
6408 }
6409 }
6410
6411 void MacroAssembler::cache_wbsync(bool is_pre) {
6412 // we only need a barrier post sync
6413 if (!is_pre) {
6414 membar(Assembler::AnyAny);
6415 }
6774 }
6775
6776 // Check if the lock-stack is full.
6777 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6778 cmpw(top, (unsigned)LockStack::end_offset());
6779 br(Assembler::GE, slow);
6780
6781 // Check for recursion.
6782 subw(t, top, oopSize);
6783 ldr(t, Address(rthread, t));
6784 cmp(obj, t);
6785 br(Assembler::EQ, push);
6786
6787 // Check header for monitor (0b10).
6788 tst(mark, markWord::monitor_value);
6789 br(Assembler::NE, slow);
6790
6791 // Try to lock. Transition lock bits 0b01 => 0b00
6792 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
6793 orr(mark, mark, markWord::unlocked_value);
6794 eor(t, mark, markWord::unlocked_value);
6795 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
6796 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
6797 br(Assembler::NE, slow);
6798
6799 bind(push);
6800 // After successful lock, push object on lock-stack.
6801 str(obj, Address(rthread, top));
6802 addw(top, top, oopSize);
6803 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
6804 }
6805
6806 // Implements lightweight-unlocking.
6807 //
6808 // - obj: the object to be unlocked
6809 // - t1, t2, t3: temporary registers
6810 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
6811 void MacroAssembler::lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
6812 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
6813 // cmpxchg clobbers rscratch1.
|
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.hpp"
28 #include "asm/assembler.inline.hpp"
29 #include "ci/ciEnv.hpp"
30 #include "ci/ciInlineKlass.hpp"
31 #include "code/compiledIC.hpp"
32 #include "compiler/compileTask.hpp"
33 #include "compiler/disassembler.hpp"
34 #include "compiler/oopMap.hpp"
35 #include "gc/shared/barrierSet.hpp"
36 #include "gc/shared/barrierSetAssembler.hpp"
37 #include "gc/shared/cardTableBarrierSet.hpp"
38 #include "gc/shared/cardTable.hpp"
39 #include "gc/shared/collectedHeap.hpp"
40 #include "gc/shared/tlab_globals.hpp"
41 #include "interpreter/bytecodeHistogram.hpp"
42 #include "interpreter/interpreter.hpp"
43 #include "jvm.h"
44 #include "memory/resourceArea.hpp"
45 #include "memory/universe.hpp"
46 #include "nativeInst_aarch64.hpp"
47 #include "oops/accessDecorators.hpp"
48 #include "oops/compressedKlass.inline.hpp"
49 #include "oops/compressedOops.inline.hpp"
50 #include "oops/klass.inline.hpp"
51 #include "oops/resolvedFieldEntry.hpp"
52 #include "runtime/continuation.hpp"
53 #include "runtime/icache.hpp"
54 #include "runtime/interfaceSupport.inline.hpp"
55 #include "runtime/javaThread.hpp"
56 #include "runtime/jniHandles.inline.hpp"
57 #include "runtime/sharedRuntime.hpp"
58 #include "runtime/signature_cc.hpp"
59 #include "runtime/stubRoutines.hpp"
60 #include "utilities/globalDefinitions.hpp"
61 #include "utilities/powerOfTwo.hpp"
62 #include "vmreg_aarch64.inline.hpp"
63 #ifdef COMPILER1
64 #include "c1/c1_LIRAssembler.hpp"
65 #endif
66 #ifdef COMPILER2
67 #include "oops/oop.hpp"
68 #include "opto/compile.hpp"
69 #include "opto/node.hpp"
70 #include "opto/output.hpp"
71 #endif
72
73 #include <sys/types.h>
74
75 #ifdef PRODUCT
76 #define BLOCK_COMMENT(str) /* nothing */
77 #else
78 #define BLOCK_COMMENT(str) block_comment(str)
79 #endif
80 #define STOP(str) stop(str);
81 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
82
1158 }
1159
1160 void MacroAssembler::post_call_nop() {
1161 if (!Continuations::enabled()) {
1162 return;
1163 }
1164 InstructionMark im(this);
1165 relocate(post_call_nop_Relocation::spec());
1166 InlineSkippedInstructionsCounter skipCounter(this);
1167 nop();
1168 movk(zr, 0);
1169 movk(zr, 0);
1170 }
1171
1172 // these are no-ops overridden by InterpreterMacroAssembler
1173
1174 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1175
1176 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1177
1178 void MacroAssembler::get_default_value_oop(Register inline_klass, Register temp_reg, Register obj) {
1179 assert_different_registers(inline_klass, temp_reg, obj, rscratch2);
1180 #ifdef ASSERT
1181 {
1182 Label done_check;
1183 test_klass_is_inline_type(inline_klass, temp_reg, done_check);
1184 stop("get_default_value_oop from non inline type klass");
1185 bind(done_check);
1186 }
1187 #endif
1188 Register offset = temp_reg;
1189 // Getting the offset of the pre-allocated default value
1190 ldr(offset, Address(inline_klass, in_bytes(InstanceKlass::adr_inlineklass_fixed_block_offset())));
1191 load_sized_value(offset, Address(offset, in_bytes(InlineKlass::default_value_offset_offset())), sizeof(int), true /*is_signed*/);
1192
1193 // Getting the mirror
1194 ldr(obj, Address(inline_klass, in_bytes(Klass::java_mirror_offset())));
1195 resolve_oop_handle(obj, inline_klass, rscratch2);
1196
1197 // Getting the pre-allocated default value from the mirror
1198 Address field(obj, offset);
1199 load_heap_oop(obj, field, inline_klass, rscratch2);
1200 }
1201
1202 void MacroAssembler::get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj) {
1203 #ifdef ASSERT
1204 {
1205 Label done_check;
1206 test_klass_is_empty_inline_type(inline_klass, temp_reg, done_check);
1207 stop("get_empty_value from non-empty inline klass");
1208 bind(done_check);
1209 }
1210 #endif
1211 get_default_value_oop(inline_klass, temp_reg, obj);
1212 }
1213
1214 // Look up the method for a megamorphic invokeinterface call.
1215 // The target method is determined by <intf_klass, itable_index>.
1216 // The receiver klass is in recv_klass.
1217 // On success, the result will be in method_result, and execution falls through.
1218 // On failure, execution transfers to the given label.
1219 void MacroAssembler::lookup_interface_method(Register recv_klass,
1220 Register intf_klass,
1221 RegisterOrConstant itable_index,
1222 Register method_result,
1223 Register scan_temp,
1224 Label& L_no_such_interface,
1225 bool return_method) {
1226 assert_different_registers(recv_klass, intf_klass, scan_temp);
1227 assert_different_registers(method_result, intf_klass, scan_temp);
1228 assert(recv_klass != method_result || !return_method,
1229 "recv_klass can be destroyed when method isn't needed");
1230 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1231 "caller must use same register for non-constant itable index as for method");
1232
1233 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1882 ldarb(scratch, scratch);
1883 subs(zr, scratch, InstanceKlass::fully_initialized);
1884 br(Assembler::EQ, *L_fast_path);
1885
1886 // Fast path check: current thread is initializer thread
1887 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
1888 cmp(rthread, scratch);
1889
1890 if (L_slow_path == &L_fallthrough) {
1891 br(Assembler::EQ, *L_fast_path);
1892 bind(*L_slow_path);
1893 } else if (L_fast_path == &L_fallthrough) {
1894 br(Assembler::NE, *L_slow_path);
1895 bind(*L_fast_path);
1896 } else {
1897 Unimplemented();
1898 }
1899 }
1900
1901 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
1902 if (!VerifyOops || VerifyAdapterSharing) {
1903 // Below address of the code string confuses VerifyAdapterSharing
1904 // because it may differ between otherwise equivalent adapters.
1905 return;
1906 }
1907
1908 // Pass register number to verify_oop_subroutine
1909 const char* b = nullptr;
1910 {
1911 ResourceMark rm;
1912 stringStream ss;
1913 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
1914 b = code_string(ss.as_string());
1915 }
1916 BLOCK_COMMENT("verify_oop {");
1917
1918 strip_return_address(); // This might happen within a stack frame.
1919 protect_return_address();
1920 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1921 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1922
1923 mov(r0, reg);
1924 movptr(rscratch1, (uintptr_t)(address)b);
1925
1926 // call indirectly to solve generation ordering problem
1927 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
1928 ldr(rscratch2, Address(rscratch2));
1929 blr(rscratch2);
1930
1931 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
1932 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
1933 authenticate_return_address();
1934
1935 BLOCK_COMMENT("} verify_oop");
1936 }
1937
1938 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
1939 if (!VerifyOops || VerifyAdapterSharing) {
1940 // Below address of the code string confuses VerifyAdapterSharing
1941 // because it may differ between otherwise equivalent adapters.
1942 return;
1943 }
1944
1945 const char* b = nullptr;
1946 {
1947 ResourceMark rm;
1948 stringStream ss;
1949 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
1950 b = code_string(ss.as_string());
1951 }
1952 BLOCK_COMMENT("verify_oop_addr {");
1953
1954 strip_return_address(); // This might happen within a stack frame.
1955 protect_return_address();
1956 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
1957 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
1958
1959 // addr may contain sp so we will have to adjust it based on the
1960 // pushes that we just did.
1961 if (addr.uses(sp)) {
1962 lea(r0, addr);
1963 ldr(r0, Address(r0, 4 * wordSize));
2021 call_VM_leaf_base(entry_point, 1);
2022 }
2023
2024 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2025 assert_different_registers(arg_1, c_rarg0);
2026 pass_arg0(this, arg_0);
2027 pass_arg1(this, arg_1);
2028 call_VM_leaf_base(entry_point, 2);
2029 }
2030
2031 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2032 Register arg_1, Register arg_2) {
2033 assert_different_registers(arg_1, c_rarg0);
2034 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2035 pass_arg0(this, arg_0);
2036 pass_arg1(this, arg_1);
2037 pass_arg2(this, arg_2);
2038 call_VM_leaf_base(entry_point, 3);
2039 }
2040
2041 void MacroAssembler::super_call_VM_leaf(address entry_point) {
2042 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2043 }
2044
2045 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2046 pass_arg0(this, arg_0);
2047 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2048 }
2049
2050 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2051
2052 assert_different_registers(arg_0, c_rarg1);
2053 pass_arg1(this, arg_1);
2054 pass_arg0(this, arg_0);
2055 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2056 }
2057
2058 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2059 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2060 assert_different_registers(arg_1, c_rarg2);
2061 pass_arg2(this, arg_2);
2062 pass_arg1(this, arg_1);
2063 pass_arg0(this, arg_0);
2064 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2070 assert_different_registers(arg_2, c_rarg3);
2071 pass_arg3(this, arg_3);
2072 pass_arg2(this, arg_2);
2073 pass_arg1(this, arg_1);
2074 pass_arg0(this, arg_0);
2075 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2076 }
2077
2078 void MacroAssembler::null_check(Register reg, int offset) {
2079 if (needs_explicit_null_check(offset)) {
2080 // provoke OS null exception if reg is null by
2081 // accessing M[reg] w/o changing any registers
2082 // NOTE: this is plenty to provoke a segv
2083 ldr(zr, Address(reg));
2084 } else {
2085 // nothing to do, (later) access of M[reg + offset]
2086 // will provoke OS null exception if reg is null
2087 }
2088 }
2089
2090 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2091 assert_different_registers(markword, rscratch2);
2092 andr(markword, markword, markWord::inline_type_mask_in_place);
2093 mov(rscratch2, markWord::inline_type_pattern);
2094 cmp(markword, rscratch2);
2095 br(Assembler::EQ, is_inline_type);
2096 }
2097
2098 void MacroAssembler::test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type) {
2099 ldrw(temp_reg, Address(klass, Klass::access_flags_offset()));
2100 andr(temp_reg, temp_reg, JVM_ACC_IDENTITY);
2101 cbz(temp_reg, is_inline_type);
2102 }
2103
2104 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type) {
2105 assert_different_registers(tmp, rscratch1);
2106 cbz(object, not_inline_type);
2107 const int is_inline_type_mask = markWord::inline_type_pattern;
2108 ldr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2109 mov(rscratch1, is_inline_type_mask);
2110 andr(tmp, tmp, rscratch1);
2111 cmp(tmp, rscratch1);
2112 br(Assembler::NE, not_inline_type);
2113 }
2114
2115 void MacroAssembler::test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type) {
2116 #ifdef ASSERT
2117 {
2118 Label done_check;
2119 test_klass_is_inline_type(klass, temp_reg, done_check);
2120 stop("test_klass_is_empty_inline_type with non inline type klass");
2121 bind(done_check);
2122 }
2123 #endif
2124 ldrw(temp_reg, Address(klass, InstanceKlass::misc_flags_offset()));
2125 andr(temp_reg, temp_reg, InstanceKlassFlags::is_empty_inline_type_value());
2126 cbnz(temp_reg, is_empty_inline_type);
2127 }
2128
2129 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2130 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2131 tbnz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, is_null_free_inline_type);
2132 }
2133
2134 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2135 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2136 tbz(flags, ResolvedFieldEntry::is_null_free_inline_type_shift, not_null_free_inline_type);
2137 }
2138
2139 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2140 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2141 tbnz(flags, ResolvedFieldEntry::is_flat_shift, is_flat);
2142 }
2143
2144 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2145 assert(temp_reg == noreg, "not needed"); // keep signature uniform with x86
2146 tbnz(flags, ResolvedFieldEntry::has_null_marker_shift, has_null_marker);
2147 }
2148
2149 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2150 Label test_mark_word;
2151 // load mark word
2152 ldr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2153 // check displaced
2154 tst(temp_reg, markWord::unlocked_value);
2155 br(Assembler::NE, test_mark_word);
2156 // slow path use klass prototype
2157 load_prototype_header(temp_reg, oop);
2158
2159 bind(test_mark_word);
2160 andr(temp_reg, temp_reg, test_bit);
2161 if (jmp_set) {
2162 cbnz(temp_reg, jmp_label);
2163 } else {
2164 cbz(temp_reg, jmp_label);
2165 }
2166 }
2167
2168 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg, Label& is_flat_array) {
2169 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2170 }
2171
2172 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
2173 Label&is_non_flat_array) {
2174 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
2175 }
2176
2177 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array) {
2178 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
2179 }
2180
2181 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
2182 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
2183 }
2184
2185 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
2186 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2187 br(Assembler::NE, is_flat_array);
2188 }
2189
2190 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
2191 tst(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
2192 br(Assembler::EQ, is_non_flat_array);
2193 }
2194
2195 // MacroAssembler protected routines needed to implement
2196 // public methods
2197
2198 void MacroAssembler::mov(Register r, Address dest) {
2199 code_section()->relocate(pc(), dest.rspec());
2200 uint64_t imm64 = (uint64_t)dest.target();
2201 movptr(r, imm64);
2202 }
2203
2204 // Move a constant pointer into r. In AArch64 mode the virtual
2205 // address space is 48 bits in size, so we only need three
2206 // instructions to create a patchable instruction sequence that can
2207 // reach anywhere.
2208 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2209 #ifndef PRODUCT
2210 {
2211 char buffer[64];
2212 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2213 block_comment(buffer);
2214 }
4979 adrp(rscratch1, src2, offset);
4980 ldr(rscratch1, Address(rscratch1, offset));
4981 cmp(src1, rscratch1);
4982 }
4983
4984 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4985 cmp(obj1, obj2);
4986 }
4987
4988 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4989 load_method_holder(rresult, rmethod);
4990 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4991 }
4992
4993 void MacroAssembler::load_method_holder(Register holder, Register method) {
4994 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
4995 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
4996 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
4997 }
4998
4999 void MacroAssembler::load_metadata(Register dst, Register src) {
5000 if (UseCompressedClassPointers) {
5001 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5002 } else {
5003 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5004 }
5005 }
5006
5007 void MacroAssembler::load_klass(Register dst, Register src) {
5008 if (UseCompressedClassPointers) {
5009 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5010 decode_klass_not_null(dst);
5011 } else {
5012 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5013 }
5014 }
5015
5016 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5017 if (RestoreMXCSROnJNICalls) {
5018 Label OK;
5019 get_fpcr(tmp1);
5020 mov(tmp2, tmp1);
5021 // Set FPCR to the state we need. We do want Round to Nearest. We
5022 // don't want non-IEEE rounding modes or floating-point traps.
5023 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5024 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5025 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5026 eor(tmp2, tmp1, tmp2);
5062
5063 void MacroAssembler::cmp_klass(Register oop, Register trial_klass, Register tmp) {
5064 if (UseCompressedClassPointers) {
5065 ldrw(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
5066 if (CompressedKlassPointers::base() == nullptr) {
5067 cmp(trial_klass, tmp, LSL, CompressedKlassPointers::shift());
5068 return;
5069 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5070 && CompressedKlassPointers::shift() == 0) {
5071 // Only the bottom 32 bits matter
5072 cmpw(trial_klass, tmp);
5073 return;
5074 }
5075 decode_klass_not_null(tmp);
5076 } else {
5077 ldr(tmp, Address(oop, oopDesc::klass_offset_in_bytes()));
5078 }
5079 cmp(trial_klass, tmp);
5080 }
5081
5082 void MacroAssembler::load_prototype_header(Register dst, Register src) {
5083 load_klass(dst, src);
5084 ldr(dst, Address(dst, Klass::prototype_header_offset()));
5085 }
5086
5087 void MacroAssembler::store_klass(Register dst, Register src) {
5088 // FIXME: Should this be a store release? concurrent gcs assumes
5089 // klass length is valid if klass field is not null.
5090 if (UseCompressedClassPointers) {
5091 encode_klass_not_null(src);
5092 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5093 } else {
5094 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5095 }
5096 }
5097
5098 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5099 if (UseCompressedClassPointers) {
5100 // Store to klass gap in destination
5101 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5102 }
5103 }
5104
5105 // Algorithm must match CompressedOops::encode.
5106 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5393 if (as_raw) {
5394 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5395 } else {
5396 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5397 }
5398 }
5399
5400 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5401 Address dst, Register val,
5402 Register tmp1, Register tmp2, Register tmp3) {
5403 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5404 decorators = AccessInternal::decorator_fixup(decorators, type);
5405 bool as_raw = (decorators & AS_RAW) != 0;
5406 if (as_raw) {
5407 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5408 } else {
5409 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5410 }
5411 }
5412
5413 void MacroAssembler::access_value_copy(DecoratorSet decorators, Register src, Register dst,
5414 Register inline_klass) {
5415 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5416 bs->value_copy(this, decorators, src, dst, inline_klass);
5417 }
5418
5419 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
5420 Register inline_layout_info) {
5421 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5422 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
5423 }
5424
5425 void MacroAssembler::first_field_offset(Register inline_klass, Register offset) {
5426 ldr(offset, Address(inline_klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
5427 ldrw(offset, Address(offset, InlineKlass::first_field_offset_offset()));
5428 }
5429
5430 void MacroAssembler::data_for_oop(Register oop, Register data, Register inline_klass) {
5431 // ((address) (void*) o) + vk->first_field_offset();
5432 Register offset = (data == oop) ? rscratch1 : data;
5433 first_field_offset(inline_klass, offset);
5434 if (data == oop) {
5435 add(data, data, offset);
5436 } else {
5437 lea(data, Address(oop, offset));
5438 }
5439 }
5440
5441 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
5442 Register index, Register data) {
5443 assert_different_registers(array, array_klass, index);
5444 assert_different_registers(rscratch1, array, index);
5445
5446 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
5447 ldrw(rscratch1, Address(array_klass, Klass::layout_helper_offset()));
5448
5449 // Klass::layout_helper_log2_element_size(lh)
5450 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
5451 lsr(rscratch1, rscratch1, Klass::_lh_log2_element_size_shift);
5452 andr(rscratch1, rscratch1, Klass::_lh_log2_element_size_mask);
5453 lslv(index, index, rscratch1);
5454
5455 add(data, array, index);
5456 add(data, data, arrayOopDesc::base_offset_in_bytes(T_PRIMITIVE_OBJECT));
5457 }
5458
5459 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5460 Register tmp2, DecoratorSet decorators) {
5461 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5462 }
5463
5464 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5465 Register tmp2, DecoratorSet decorators) {
5466 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5467 }
5468
5469 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5470 Register tmp2, Register tmp3, DecoratorSet decorators) {
5471 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5472 }
5473
5474 // Used for storing nulls.
5475 void MacroAssembler::store_heap_oop_null(Address dst) {
5476 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5477 }
5478
5515 oop_index = oop_recorder()->allocate_metadata_index(obj);
5516 } else {
5517 oop_index = oop_recorder()->find_index(obj);
5518 }
5519 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5520 mov(dst, Address((address)obj, rspec));
5521 }
5522
5523 Address MacroAssembler::constant_oop_address(jobject obj) {
5524 #ifdef ASSERT
5525 {
5526 ThreadInVMfromUnknown tiv;
5527 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5528 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5529 }
5530 #endif
5531 int oop_index = oop_recorder()->find_index(obj);
5532 return Address((address)obj, oop_Relocation::spec(oop_index));
5533 }
5534
5535 // Object / value buffer allocation...
5536 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
5537 Register t1, Register t2,
5538 bool clear_fields, Label& alloc_failed)
5539 {
5540 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
5541 Register layout_size = t1;
5542 assert(new_obj == r0, "needs to be r0");
5543 assert_different_registers(klass, new_obj, t1, t2);
5544
5545 // get instance_size in InstanceKlass (scaled to a count of bytes)
5546 ldrw(layout_size, Address(klass, Klass::layout_helper_offset()));
5547 // test to see if it is malformed in some way
5548 tst(layout_size, Klass::_lh_instance_slow_path_bit);
5549 br(Assembler::NE, slow_case_no_pop);
5550
5551 // Allocate the instance:
5552 // If TLAB is enabled:
5553 // Try to allocate in the TLAB.
5554 // If fails, go to the slow path.
5555 // Initialize the allocation.
5556 // Exit.
5557 //
5558 // Go to slow path.
5559
5560 if (UseTLAB) {
5561 push(klass);
5562 tlab_allocate(new_obj, layout_size, 0, klass, t2, slow_case);
5563 if (ZeroTLAB || (!clear_fields)) {
5564 // the fields have been already cleared
5565 b(initialize_header);
5566 } else {
5567 // initialize both the header and fields
5568 b(initialize_object);
5569 }
5570
5571 if (clear_fields) {
5572 // The object is initialized before the header. If the object size is
5573 // zero, go directly to the header initialization.
5574 bind(initialize_object);
5575 subs(layout_size, layout_size, sizeof(oopDesc));
5576 br(Assembler::EQ, initialize_header);
5577
5578 // Initialize topmost object field, divide size by 8, check if odd and
5579 // test if zero.
5580
5581 #ifdef ASSERT
5582 // make sure instance_size was multiple of 8
5583 Label L;
5584 tst(layout_size, 7);
5585 br(Assembler::EQ, L);
5586 stop("object size is not multiple of 8 - adjust this code");
5587 bind(L);
5588 // must be > 0, no extra check needed here
5589 #endif
5590
5591 lsr(layout_size, layout_size, LogBytesPerLong);
5592
5593 // initialize remaining object fields: instance_size was a multiple of 8
5594 {
5595 Label loop;
5596 Register base = t2;
5597
5598 bind(loop);
5599 add(rscratch1, new_obj, layout_size, Assembler::LSL, LogBytesPerLong);
5600 str(zr, Address(rscratch1, sizeof(oopDesc) - 1*oopSize));
5601 subs(layout_size, layout_size, 1);
5602 br(Assembler::NE, loop);
5603 }
5604 } // clear_fields
5605
5606 // initialize object header only.
5607 bind(initialize_header);
5608 pop(klass);
5609 Register mark_word = t2;
5610 ldr(mark_word, Address(klass, Klass::prototype_header_offset()));
5611 str(mark_word, Address(new_obj, oopDesc::mark_offset_in_bytes ()));
5612 store_klass_gap(new_obj, zr); // zero klass gap for compressed oops
5613 mov(t2, klass); // preserve klass
5614 store_klass(new_obj, t2); // src klass reg is potentially compressed
5615
5616 // TODO: Valhalla removed SharedRuntime::dtrace_object_alloc from here ?
5617
5618 b(done);
5619 }
5620
5621 if (UseTLAB) {
5622 bind(slow_case);
5623 pop(klass);
5624 }
5625 bind(slow_case_no_pop);
5626 b(alloc_failed);
5627
5628 bind(done);
5629 }
5630
5631 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5632 void MacroAssembler::tlab_allocate(Register obj,
5633 Register var_size_in_bytes,
5634 int con_size_in_bytes,
5635 Register t1,
5636 Register t2,
5637 Label& slow_case) {
5638 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5639 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5640 }
5641
5642 void MacroAssembler::verify_tlab() {
5643 #ifdef ASSERT
5644 if (UseTLAB && VerifyOops) {
5645 Label next, ok;
5646
5647 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5648
5649 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5650 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5651 cmp(rscratch2, rscratch1);
5652 br(Assembler::HS, next);
5653 STOP("assert(top >= start)");
5654 should_not_reach_here();
5655
5656 bind(next);
5657 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5658 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5659 cmp(rscratch2, rscratch1);
5660 br(Assembler::HS, ok);
5661 STOP("assert(top <= end)");
5662 should_not_reach_here();
5663
5664 bind(ok);
5665 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5666 }
5667 #endif
5668 }
5669
5670 void MacroAssembler::get_inline_type_field_klass(Register holder_klass, Register index, Register inline_klass) {
5671 inline_layout_info(holder_klass, index, inline_klass);
5672 ldr(inline_klass, Address(inline_klass, InlineLayoutInfo::klass_offset()));
5673 }
5674
5675 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
5676 assert_different_registers(holder_klass, index, layout_info);
5677 InlineLayoutInfo array[2];
5678 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
5679 if (is_power_of_2(size)) {
5680 lsl(index, index, log2i_exact(size)); // Scale index by power of 2
5681 } else {
5682 mov(layout_info, size);
5683 mul(index, index, layout_info); // Scale the index to be the entry index * array_element_size
5684 }
5685 ldr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
5686 add(layout_info, layout_info, Array<InlineLayoutInfo>::base_offset_in_bytes());
5687 lea(layout_info, Address(layout_info, index));
5688 }
5689
5690 // Writes to stack successive pages until offset reached to check for
5691 // stack overflow + shadow pages. This clobbers tmp.
5692 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5693 assert_different_registers(tmp, size, rscratch1);
5694 mov(tmp, sp);
5695 // Bang stack for total size given plus shadow page size.
5696 // Bang one page at a time because large size can bang beyond yellow and
5697 // red zones.
5698 Label loop;
5699 mov(rscratch1, (int)os::vm_page_size());
5700 bind(loop);
5701 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5702 subsw(size, size, rscratch1);
5703 str(size, Address(tmp));
5704 br(Assembler::GT, loop);
5705
5706 // Bang down shadow pages too.
5707 // At this point, (tmp-0) is the last address touched, so don't
5708 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5709 // was post-decremented.) Skip this address by starting at i=1, and
5795 }
5796
5797 void MacroAssembler::remove_frame(int framesize) {
5798 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5799 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5800 if (framesize < ((1 << 9) + 2 * wordSize)) {
5801 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5802 add(sp, sp, framesize);
5803 } else {
5804 if (framesize < ((1 << 12) + 2 * wordSize))
5805 add(sp, sp, framesize - 2 * wordSize);
5806 else {
5807 mov(rscratch1, framesize - 2 * wordSize);
5808 add(sp, sp, rscratch1);
5809 }
5810 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5811 }
5812 authenticate_return_address();
5813 }
5814
5815 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
5816 if (needs_stack_repair) {
5817 // Remove the extension of the caller's frame used for inline type unpacking
5818 //
5819 // Right now the stack looks like this:
5820 //
5821 // | Arguments from caller |
5822 // |---------------------------| <-- caller's SP
5823 // | Saved LR #1 |
5824 // | Saved FP #1 |
5825 // |---------------------------|
5826 // | Extension space for |
5827 // | inline arg (un)packing |
5828 // |---------------------------| <-- start of this method's frame
5829 // | Saved LR #2 |
5830 // | Saved FP #2 |
5831 // |---------------------------| <-- FP
5832 // | sp_inc |
5833 // | method locals |
5834 // |---------------------------| <-- SP
5835 //
5836 // There are two copies of FP and LR on the stack. They will be identical
5837 // unless the caller has been deoptimized, in which case LR #1 will be patched
5838 // to point at the deopt blob, and LR #2 will still point into the old method.
5839 //
5840 // The sp_inc stack slot holds the total size of the frame including the
5841 // extension space minus two words for the saved FP and LR.
5842
5843 int sp_inc_offset = initial_framesize - 3 * wordSize; // Immediately below saved LR and FP
5844
5845 ldr(rscratch1, Address(sp, sp_inc_offset));
5846 add(sp, sp, rscratch1);
5847 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5848 } else {
5849 remove_frame(initial_framesize);
5850 }
5851 }
5852
5853 void MacroAssembler::save_stack_increment(int sp_inc, int frame_size) {
5854 int real_frame_size = frame_size + sp_inc;
5855 assert(sp_inc == 0 || sp_inc > 2*wordSize, "invalid sp_inc value");
5856 assert(real_frame_size >= 2*wordSize, "frame size must include FP/LR space");
5857 assert((real_frame_size & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5858
5859 int sp_inc_offset = frame_size - 3 * wordSize; // Immediately below saved LR and FP
5860
5861 // Subtract two words for the saved FP and LR as these will be popped
5862 // separately. See remove_frame above.
5863 mov(rscratch1, real_frame_size - 2*wordSize);
5864 str(rscratch1, Address(sp, sp_inc_offset));
5865 }
5866
5867 // This method counts leading positive bytes (highest bit not set) in provided byte array
5868 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5869 // Simple and most common case of aligned small array which is not at the
5870 // end of memory page is placed here. All other cases are in stub.
5871 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5872 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5873 assert_different_registers(ary1, len, result);
5874
5875 mov(result, len);
5876 cmpw(len, 0);
5877 br(LE, DONE);
5878 cmpw(len, 4 * wordSize);
5879 br(GE, STUB_LONG); // size > 32 then go to stub
5880
5881 int shift = 64 - exact_log2(os::vm_page_size());
5882 lsl(rscratch1, ary1, shift);
5883 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5884 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5885 br(CS, STUB); // at the end of page then go to stub
6759 // On other systems, the helper is a usual C function.
6760 //
6761 void MacroAssembler::get_thread(Register dst) {
6762 RegSet saved_regs =
6763 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6764 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6765
6766 protect_return_address();
6767 push(saved_regs, sp);
6768
6769 mov(lr, CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper));
6770 blr(lr);
6771 if (dst != c_rarg0) {
6772 mov(dst, c_rarg0);
6773 }
6774
6775 pop(saved_regs, sp);
6776 authenticate_return_address();
6777 }
6778
6779 #ifdef COMPILER2
6780 // C2 compiled method's prolog code
6781 // Moved here from aarch64.ad to support Valhalla code belows
6782 void MacroAssembler::verified_entry(Compile* C, int sp_inc) {
6783 if (C->clinit_barrier_on_entry()) {
6784 assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
6785
6786 Label L_skip_barrier;
6787
6788 mov_metadata(rscratch2, C->method()->holder()->constant_encoding());
6789 clinit_barrier(rscratch2, rscratch1, &L_skip_barrier);
6790 far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
6791 bind(L_skip_barrier);
6792 }
6793
6794 if (C->max_vector_size() > 0) {
6795 reinitialize_ptrue();
6796 }
6797
6798 int bangsize = C->output()->bang_size_in_bytes();
6799 if (C->output()->need_stack_bang(bangsize))
6800 generate_stack_overflow_check(bangsize);
6801
6802 // n.b. frame size includes space for return pc and rfp
6803 const long framesize = C->output()->frame_size_in_bytes();
6804 build_frame(framesize);
6805
6806 if (C->needs_stack_repair()) {
6807 save_stack_increment(sp_inc, framesize);
6808 }
6809
6810 if (VerifyStackAtCalls) {
6811 Unimplemented();
6812 }
6813 }
6814 #endif // COMPILER2
6815
6816 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6817 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6818 // An inline type might be returned. If fields are in registers we
6819 // need to allocate an inline type instance and initialize it with
6820 // the value of the fields.
6821 Label skip;
6822 // We only need a new buffered inline type if a new one is not returned
6823 tbz(r0, 0, skip);
6824 int call_offset = -1;
6825
6826 // Be careful not to clobber r1-7 which hold returned fields
6827 // Also do not use callee-saved registers as these may be live in the interpreter
6828 Register tmp1 = r13, tmp2 = r14, klass = r15, r0_preserved = r12;
6829
6830 // The following code is similar to allocate_instance but has some slight differences,
6831 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6832 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
6833 Label slow_case;
6834 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6835 mov(r0_preserved, r0); // save r0 for slow_case since *_allocate may corrupt it when allocation failed
6836
6837 if (vk != nullptr) {
6838 // Called from C1, where the return type is statically known.
6839 movptr(klass, (intptr_t)vk->get_InlineKlass());
6840 jint lh = vk->layout_helper();
6841 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6842 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6843 tlab_allocate(r0, noreg, lh, tmp1, tmp2, slow_case);
6844 } else {
6845 b(slow_case);
6846 }
6847 } else {
6848 // Call from interpreter. R0 contains ((the InlineKlass* of the return type) | 0x01)
6849 andr(klass, r0, -2);
6850 if (UseTLAB) {
6851 ldrw(tmp2, Address(klass, Klass::layout_helper_offset()));
6852 tst(tmp2, Klass::_lh_instance_slow_path_bit);
6853 br(Assembler::NE, slow_case);
6854 tlab_allocate(r0, tmp2, 0, tmp1, tmp2, slow_case);
6855 } else {
6856 b(slow_case);
6857 }
6858 }
6859 if (UseTLAB) {
6860 // 2. Initialize buffered inline instance header
6861 Register buffer_obj = r0;
6862 mov(rscratch1, (intptr_t)markWord::inline_type_prototype().value());
6863 str(rscratch1, Address(buffer_obj, oopDesc::mark_offset_in_bytes()));
6864 store_klass_gap(buffer_obj, zr);
6865 if (vk == nullptr) {
6866 // store_klass corrupts klass, so save it for later use (interpreter case only).
6867 mov(tmp1, klass);
6868 }
6869 store_klass(buffer_obj, klass);
6870 // 3. Initialize its fields with an inline class specific handler
6871 if (vk != nullptr) {
6872 far_call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6873 } else {
6874 // tmp1 holds klass preserved above
6875 ldr(tmp1, Address(tmp1, InstanceKlass::adr_inlineklass_fixed_block_offset()));
6876 ldr(tmp1, Address(tmp1, InlineKlass::pack_handler_offset()));
6877 blr(tmp1);
6878 }
6879
6880 membar(Assembler::StoreStore);
6881 b(skip);
6882 } else {
6883 // Must have already branched to slow_case above.
6884 DEBUG_ONLY(should_not_reach_here());
6885 }
6886 bind(slow_case);
6887 // We failed to allocate a new inline type, fall back to a runtime
6888 // call. Some oop field may be live in some registers but we can't
6889 // tell. That runtime call will take care of preserving them
6890 // across a GC if there's one.
6891 mov(r0, r0_preserved);
6892
6893 if (from_interpreter) {
6894 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6895 } else {
6896 far_call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6897 call_offset = offset();
6898 }
6899 membar(Assembler::StoreStore);
6900
6901 bind(skip);
6902 return call_offset;
6903 }
6904
6905 // Move a value between registers/stack slots and update the reg_state
6906 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6907 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6908 if (reg_state[to->value()] == reg_written) {
6909 return true; // Already written
6910 }
6911
6912 if (from != to && bt != T_VOID) {
6913 if (reg_state[to->value()] == reg_readonly) {
6914 return false; // Not yet writable
6915 }
6916 if (from->is_reg()) {
6917 if (to->is_reg()) {
6918 if (from->is_Register() && to->is_Register()) {
6919 mov(to->as_Register(), from->as_Register());
6920 } else if (from->is_FloatRegister() && to->is_FloatRegister()) {
6921 fmovd(to->as_FloatRegister(), from->as_FloatRegister());
6922 } else {
6923 ShouldNotReachHere();
6924 }
6925 } else {
6926 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
6927 Address to_addr = Address(sp, st_off);
6928 if (from->is_FloatRegister()) {
6929 if (bt == T_DOUBLE) {
6930 strd(from->as_FloatRegister(), to_addr);
6931 } else {
6932 assert(bt == T_FLOAT, "must be float");
6933 strs(from->as_FloatRegister(), to_addr);
6934 }
6935 } else {
6936 str(from->as_Register(), to_addr);
6937 }
6938 }
6939 } else {
6940 Address from_addr = Address(sp, from->reg2stack() * VMRegImpl::stack_slot_size);
6941 if (to->is_reg()) {
6942 if (to->is_FloatRegister()) {
6943 if (bt == T_DOUBLE) {
6944 ldrd(to->as_FloatRegister(), from_addr);
6945 } else {
6946 assert(bt == T_FLOAT, "must be float");
6947 ldrs(to->as_FloatRegister(), from_addr);
6948 }
6949 } else {
6950 ldr(to->as_Register(), from_addr);
6951 }
6952 } else {
6953 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size;
6954 ldr(rscratch1, from_addr);
6955 str(rscratch1, Address(sp, st_off));
6956 }
6957 }
6958 }
6959
6960 // Update register states
6961 reg_state[from->value()] = reg_writable;
6962 reg_state[to->value()] = reg_written;
6963 return true;
6964 }
6965
6966 // Calculate the extra stack space required for packing or unpacking inline
6967 // args and adjust the stack pointer
6968 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6969 int sp_inc = args_on_stack * VMRegImpl::stack_slot_size;
6970 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6971 assert(sp_inc > 0, "sanity");
6972
6973 // Save a copy of the FP and LR here for deoptimization patching and frame walking
6974 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6975
6976 // Adjust the stack pointer. This will be repaired on return by MacroAssembler::remove_frame
6977 if (sp_inc < (1 << 9)) {
6978 sub(sp, sp, sp_inc); // Fits in an immediate
6979 } else {
6980 mov(rscratch1, sp_inc);
6981 sub(sp, sp, rscratch1);
6982 }
6983
6984 return sp_inc + 2 * wordSize; // Account for the FP/LR space
6985 }
6986
6987 // Read all fields from an inline type oop and store the values in registers/stack slots
6988 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6989 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6990 RegState reg_state[]) {
6991 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6992 assert(from->is_valid(), "source must be valid");
6993 bool progress = false;
6994 #ifdef ASSERT
6995 const int start_offset = offset();
6996 #endif
6997
6998 Label L_null, L_notNull;
6999 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
7000 Register tmp1 = r10;
7001 Register tmp2 = r11;
7002 Register fromReg = noreg;
7003 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
7004 bool done = true;
7005 bool mark_done = true;
7006 VMReg toReg;
7007 BasicType bt;
7008 // Check if argument requires a null check
7009 bool null_check = false;
7010 VMReg nullCheckReg;
7011 while (stream.next(nullCheckReg, bt)) {
7012 if (sig->at(stream.sig_index())._offset == -1) {
7013 null_check = true;
7014 break;
7015 }
7016 }
7017 stream.reset(sig_index, to_index);
7018 while (stream.next(toReg, bt)) {
7019 assert(toReg->is_valid(), "destination must be valid");
7020 int idx = (int)toReg->value();
7021 if (reg_state[idx] == reg_readonly) {
7022 if (idx != from->value()) {
7023 mark_done = false;
7024 }
7025 done = false;
7026 continue;
7027 } else if (reg_state[idx] == reg_written) {
7028 continue;
7029 }
7030 assert(reg_state[idx] == reg_writable, "must be writable");
7031 reg_state[idx] = reg_written;
7032 progress = true;
7033
7034 if (fromReg == noreg) {
7035 if (from->is_reg()) {
7036 fromReg = from->as_Register();
7037 } else {
7038 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size;
7039 ldr(tmp1, Address(sp, st_off));
7040 fromReg = tmp1;
7041 }
7042 if (null_check) {
7043 // Nullable inline type argument, emit null check
7044 cbz(fromReg, L_null);
7045 }
7046 }
7047 int off = sig->at(stream.sig_index())._offset;
7048 if (off == -1) {
7049 assert(null_check, "Missing null check at");
7050 if (toReg->is_stack()) {
7051 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7052 mov(tmp2, 1);
7053 str(tmp2, Address(sp, st_off));
7054 } else {
7055 mov(toReg->as_Register(), 1);
7056 }
7057 continue;
7058 }
7059 assert(off > 0, "offset in object should be positive");
7060 Address fromAddr = Address(fromReg, off);
7061 if (!toReg->is_FloatRegister()) {
7062 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
7063 if (is_reference_type(bt)) {
7064 load_heap_oop(dst, fromAddr, rscratch1, rscratch2);
7065 } else {
7066 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
7067 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
7068 }
7069 if (toReg->is_stack()) {
7070 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7071 str(dst, Address(sp, st_off));
7072 }
7073 } else if (bt == T_DOUBLE) {
7074 ldrd(toReg->as_FloatRegister(), fromAddr);
7075 } else {
7076 assert(bt == T_FLOAT, "must be float");
7077 ldrs(toReg->as_FloatRegister(), fromAddr);
7078 }
7079 }
7080 if (progress && null_check) {
7081 if (done) {
7082 b(L_notNull);
7083 bind(L_null);
7084 // Set IsInit field to zero to signal that the argument is null.
7085 // Also set all oop fields to zero to make the GC happy.
7086 stream.reset(sig_index, to_index);
7087 while (stream.next(toReg, bt)) {
7088 if (sig->at(stream.sig_index())._offset == -1 ||
7089 bt == T_OBJECT || bt == T_ARRAY) {
7090 if (toReg->is_stack()) {
7091 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size;
7092 str(zr, Address(sp, st_off));
7093 } else {
7094 mov(toReg->as_Register(), zr);
7095 }
7096 }
7097 }
7098 bind(L_notNull);
7099 } else {
7100 bind(L_null);
7101 }
7102 }
7103
7104 sig_index = stream.sig_index();
7105 to_index = stream.regs_index();
7106
7107 if (mark_done && reg_state[from->value()] != reg_written) {
7108 // This is okay because no one else will write to that slot
7109 reg_state[from->value()] = reg_writable;
7110 }
7111 from_index--;
7112 assert(progress || (start_offset == offset()), "should not emit code");
7113 return done;
7114 }
7115
7116 // Pack fields back into an inline type oop
7117 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
7118 VMRegPair* from, int from_count, int& from_index, VMReg to,
7119 RegState reg_state[], Register val_array) {
7120 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
7121 assert(to->is_valid(), "destination must be valid");
7122
7123 if (reg_state[to->value()] == reg_written) {
7124 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7125 return true; // Already written
7126 }
7127
7128 // The GC barrier expanded by store_heap_oop below may call into the
7129 // runtime so use callee-saved registers for any values that need to be
7130 // preserved. The GC barrier assembler should take care of saving the
7131 // Java argument registers.
7132 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
7133 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
7134 Register val_obj_tmp = r21;
7135 Register from_reg_tmp = r22;
7136 Register tmp1 = r14;
7137 Register tmp2 = r13;
7138 Register tmp3 = r12;
7139 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
7140
7141 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
7142
7143 if (reg_state[to->value()] == reg_readonly) {
7144 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
7145 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7146 return false; // Not yet writable
7147 }
7148 val_obj = val_obj_tmp;
7149 }
7150
7151 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
7152 load_heap_oop(val_obj, Address(val_array, index), tmp1, tmp2);
7153
7154 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
7155 VMReg fromReg;
7156 BasicType bt;
7157 Label L_null;
7158 while (stream.next(fromReg, bt)) {
7159 assert(fromReg->is_valid(), "source must be valid");
7160 reg_state[fromReg->value()] = reg_writable;
7161
7162 int off = sig->at(stream.sig_index())._offset;
7163 if (off == -1) {
7164 // Nullable inline type argument, emit null check
7165 Label L_notNull;
7166 if (fromReg->is_stack()) {
7167 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7168 ldrb(tmp2, Address(sp, ld_off));
7169 cbnz(tmp2, L_notNull);
7170 } else {
7171 cbnz(fromReg->as_Register(), L_notNull);
7172 }
7173 mov(val_obj, 0);
7174 b(L_null);
7175 bind(L_notNull);
7176 continue;
7177 }
7178
7179 assert(off > 0, "offset in object should be positive");
7180 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
7181
7182 // Pack the scalarized field into the value object.
7183 Address dst(val_obj, off);
7184
7185 if (!fromReg->is_FloatRegister()) {
7186 Register src;
7187 if (fromReg->is_stack()) {
7188 src = from_reg_tmp;
7189 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size;
7190 load_sized_value(src, Address(sp, ld_off), size_in_bytes, /* is_signed */ false);
7191 } else {
7192 src = fromReg->as_Register();
7193 }
7194 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
7195 if (is_reference_type(bt)) {
7196 store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
7197 } else {
7198 store_sized_value(dst, src, size_in_bytes);
7199 }
7200 } else if (bt == T_DOUBLE) {
7201 strd(fromReg->as_FloatRegister(), dst);
7202 } else {
7203 assert(bt == T_FLOAT, "must be float");
7204 strs(fromReg->as_FloatRegister(), dst);
7205 }
7206 }
7207 bind(L_null);
7208 sig_index = stream.sig_index();
7209 from_index = stream.regs_index();
7210
7211 assert(reg_state[to->value()] == reg_writable, "must have already been read");
7212 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
7213 assert(success, "to register must be writeable");
7214
7215 return true;
7216 }
7217
7218 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
7219 return (reg->is_FloatRegister()) ? v8->as_VMReg() : r14->as_VMReg();
7220 }
7221
7222 void MacroAssembler::cache_wb(Address line) {
7223 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
7224 assert(line.index() == noreg, "index should be noreg");
7225 assert(line.offset() == 0, "offset should be 0");
7226 // would like to assert this
7227 // assert(line._ext.shift == 0, "shift should be zero");
7228 if (VM_Version::supports_dcpop()) {
7229 // writeback using clear virtual address to point of persistence
7230 dc(Assembler::CVAP, line.base());
7231 } else {
7232 // no need to generate anything as Unsafe.writebackMemory should
7233 // never invoke this stub
7234 }
7235 }
7236
7237 void MacroAssembler::cache_wbsync(bool is_pre) {
7238 // we only need a barrier post sync
7239 if (!is_pre) {
7240 membar(Assembler::AnyAny);
7241 }
7600 }
7601
7602 // Check if the lock-stack is full.
7603 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7604 cmpw(top, (unsigned)LockStack::end_offset());
7605 br(Assembler::GE, slow);
7606
7607 // Check for recursion.
7608 subw(t, top, oopSize);
7609 ldr(t, Address(rthread, t));
7610 cmp(obj, t);
7611 br(Assembler::EQ, push);
7612
7613 // Check header for monitor (0b10).
7614 tst(mark, markWord::monitor_value);
7615 br(Assembler::NE, slow);
7616
7617 // Try to lock. Transition lock bits 0b01 => 0b00
7618 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7619 orr(mark, mark, markWord::unlocked_value);
7620 if (EnableValhalla) {
7621 // Mask inline_type bit such that we go to the slow path if object is an inline type
7622 andr(mark, mark, ~((int) markWord::inline_type_bit_in_place));
7623 }
7624 eor(t, mark, markWord::unlocked_value);
7625 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
7626 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
7627 br(Assembler::NE, slow);
7628
7629 bind(push);
7630 // After successful lock, push object on lock-stack.
7631 str(obj, Address(rthread, top));
7632 addw(top, top, oopSize);
7633 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7634 }
7635
7636 // Implements lightweight-unlocking.
7637 //
7638 // - obj: the object to be unlocked
7639 // - t1, t2, t3: temporary registers
7640 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7641 void MacroAssembler::lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7642 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
7643 // cmpxchg clobbers rscratch1.
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