18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/atomicAccess.hpp"
36 #include "runtime/vm_version.hpp"
37 #include "utilities/globalDefinitions.hpp"
38 #include "utilities/powerOfTwo.hpp"
39
40 class OopMap;
41
42 // MacroAssembler extends Assembler by frequently used macros.
43 //
44 // Instructions for which a 'better' code sequence exists depending
45 // on arguments should also go in here.
46
47 class MacroAssembler: public Assembler {
48 friend class LIR_Assembler;
49
50 public:
51 using Assembler::mov;
52 using Assembler::movi;
53
54 protected:
55
56 // Support for VM calls
57 //
58 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
169
170 void bind(Label& L) {
171 Assembler::bind(L);
172 code()->clear_last_merge_candidate();
173 code()->set_last_label(pc());
174 }
175
176 void membar(Membar_mask_bits order_constraint);
177
178 using Assembler::ldr;
179 using Assembler::str;
180 using Assembler::ldrw;
181 using Assembler::strw;
182
183 void ldr(Register Rx, const Address &adr);
184 void ldrw(Register Rw, const Address &adr);
185 void str(Register Rx, const Address &adr);
186 void strw(Register Rx, const Address &adr);
187
188 // Frame creation and destruction shared between JITs.
189 void build_frame(int framesize);
190 void remove_frame(int framesize);
191
192 virtual void _call_Unimplemented(address call_site) {
193 mov(rscratch2, call_site);
194 }
195
196 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
197 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
198 // https://reviews.llvm.org/D3311
199
200 #ifdef _WIN64
201 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
202 #else
203 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
204 #endif
205
206 // aliases defined in AARCH64 spec
207
208 template<class T>
209 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
680 mrs(0b011, 0b1110, 0b0000, 0b110, reg);
681 }
682
683 // idiv variant which deals with MINLONG as dividend and -1 as divisor
684 int corrected_idivl(Register result, Register ra, Register rb,
685 bool want_remainder, Register tmp = rscratch1);
686 int corrected_idivq(Register result, Register ra, Register rb,
687 bool want_remainder, Register tmp = rscratch1);
688
689 // Support for null-checks
690 //
691 // Generates code that causes a null OS exception if the content of reg is null.
692 // If the accessed location is M[reg + offset] and the offset is known, provide the
693 // offset. No explicit code generation is needed if the offset is within a certain
694 // range (0 <= offset <= page_size).
695
696 virtual void null_check(Register reg, int offset = -1);
697 static bool needs_explicit_null_check(intptr_t offset);
698 static bool uses_implicit_null_check(void* address);
699
700 static address target_addr_for_insn(address insn_addr);
701
702 // Required platform-specific helpers for Label::patch_instructions.
703 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
704 static int pd_patch_instruction_size(address branch, address target);
705 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
706 pd_patch_instruction_size(branch, target);
707 }
708 static address pd_call_destination(address branch) {
709 return target_addr_for_insn(branch);
710 }
711 #ifndef PRODUCT
712 static void pd_print_patched_instruction(address branch);
713 #endif
714
715 static int patch_oop(address insn_addr, address o);
716
717 // Return whether code is emitted to a scratch blob.
718 virtual bool in_scratch_emit_size() {
719 return false;
906 void set_last_Java_frame(Register last_java_sp,
907 Register last_java_fp,
908 Register last_java_pc,
909 Register scratch);
910
911 void reset_last_Java_frame(Register thread);
912
913 // thread in the default location (rthread)
914 void reset_last_Java_frame(bool clear_fp);
915
916 void resolve_jobject(Register value, Register tmp1, Register tmp2);
917 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
918
919 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
920 void c2bool(Register x);
921
922 void load_method_holder_cld(Register rresult, Register rmethod);
923 void load_method_holder(Register holder, Register method);
924
925 // oop manipulations
926 void load_narrow_klass_compact(Register dst, Register src);
927 void load_klass(Register dst, Register src);
928 void store_klass(Register dst, Register src);
929 void cmp_klass(Register obj, Register klass, Register tmp);
930 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
931
932 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
933 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
934 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
935
936 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
937 Register tmp1, Register tmp2);
938
939 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
940 Register tmp1, Register tmp2, Register tmp3);
941
942 void load_heap_oop(Register dst, Address src, Register tmp1,
943 Register tmp2, DecoratorSet decorators = 0);
944
945 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
946 Register tmp2, DecoratorSet decorators = 0);
947 void store_heap_oop(Address dst, Register val, Register tmp1,
948 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
949
950 // currently unimplemented
951 // Used for storing null. All other oop constants should be
952 // stored using routines that take a jobject.
953 void store_heap_oop_null(Address dst);
954
955 void store_klass_gap(Register dst, Register src);
956
957 // This dummy is to prevent a call to store_heap_oop from
958 // converting a zero (like null) into a Register by giving
959 // the compiler two choices it can't resolve
960
961 void store_heap_oop(Address dst, void* dummy);
962
963 void encode_heap_oop(Register d, Register s);
964 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
965 void decode_heap_oop(Register d, Register s);
966 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
967 void encode_heap_oop_not_null(Register r);
968 void decode_heap_oop_not_null(Register r);
969 void encode_heap_oop_not_null(Register dst, Register src);
970 void decode_heap_oop_not_null(Register dst, Register src);
971
972 void set_narrow_oop(Register dst, jobject obj);
973
974 void decode_klass_not_null_for_aot(Register dst, Register src);
984 void reinit_heapbase();
985
986 DEBUG_ONLY(void verify_heapbase(const char* msg);)
987
988 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
989 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
990 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
991 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
992
993 void push_cont_fastpath(Register java_thread = rthread);
994 void pop_cont_fastpath(Register java_thread = rthread);
995
996 // Round up to a power of two
997 void round_to(Register reg, int modulus);
998
999 // java.lang.Math::round intrinsics
1000 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1001 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1002
1003 // allocation
1004 void tlab_allocate(
1005 Register obj, // result: pointer to object after successful allocation
1006 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1007 int con_size_in_bytes, // object size in bytes if known at compile time
1008 Register t1, // temp register
1009 Register t2, // temp register
1010 Label& slow_case // continuation point if fast allocation fails
1011 );
1012 void verify_tlab();
1013
1014 // interface method calling
1015 void lookup_interface_method(Register recv_klass,
1016 Register intf_klass,
1017 RegisterOrConstant itable_index,
1018 Register method_result,
1019 Register scan_temp,
1020 Label& no_such_interface,
1021 bool return_method = true);
1022
1023 void lookup_interface_method_stub(Register recv_klass,
1024 Register holder_klass,
1025 Register resolved_klass,
1026 Register method_result,
1027 Register temp_reg,
1028 Register temp_reg2,
1029 int itable_index,
1030 Label& L_no_such_interface);
1031
1032 // virtual method calling
1033 // n.b. x86 allows RegisterOrConstant for vtable_index
1464 } \
1465 \
1466 void INSN(Register Rd, Register Rn, Register Rm) { \
1467 Assembler::INSN(Rd, Rn, Rm); \
1468 } \
1469 \
1470 void INSN(Register Rd, Register Rn, Register Rm, \
1471 ext::operation option, int amount = 0) { \
1472 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1473 }
1474
1475 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1476
1477 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1478 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1479 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1480 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1481
1482 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1483
1484 void tableswitch(Register index, jint lowbound, jint highbound,
1485 Label &jumptable, Label &jumptable_end, int stride = 1) {
1486 adr(rscratch1, jumptable);
1487 subsw(rscratch2, index, lowbound);
1488 subsw(zr, rscratch2, highbound - lowbound);
1489 br(Assembler::HS, jumptable_end);
1490 add(rscratch1, rscratch1, rscratch2,
1491 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1492 br(rscratch1);
1493 }
1494
1495 // Form an address from base + offset in Rd. Rd may or may not
1496 // actually be used: you must use the Address that is returned. It
1497 // is up to you to ensure that the shift provided matches the size
1498 // of your data.
1499 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1500
1501 // Return true iff an address is within the 48-bit AArch64 address
1502 // space.
1503 bool is_valid_AArch64_address(address a) {
1538 #define ARRAYS_HASHCODE_REGISTERS \
1539 do { \
1540 assert(result == r0 && \
1541 ary == r1 && \
1542 cnt == r2 && \
1543 vdata0 == v3 && \
1544 vdata1 == v2 && \
1545 vdata2 == v1 && \
1546 vdata3 == v0 && \
1547 vmul0 == v4 && \
1548 vmul1 == v5 && \
1549 vmul2 == v6 && \
1550 vmul3 == v7 && \
1551 vpow == v12 && \
1552 vpowm == v13, "registers must match aarch64.ad"); \
1553 } while (0)
1554
1555 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1556
1557 void fill_words(Register base, Register cnt, Register value);
1558 address zero_words(Register base, uint64_t cnt);
1559 address zero_words(Register ptr, Register cnt);
1560 void zero_dcache_blocks(Register base, Register cnt);
1561
1562 static const int zero_words_block_size;
1563
1564 address byte_array_inflate(Register src, Register dst, Register len,
1565 FloatRegister vtmp1, FloatRegister vtmp2,
1566 FloatRegister vtmp3, Register tmp4);
1567
1568 void char_array_compress(Register src, Register dst, Register len,
1569 Register res,
1570 FloatRegister vtmp0, FloatRegister vtmp1,
1571 FloatRegister vtmp2, FloatRegister vtmp3,
1572 FloatRegister vtmp4, FloatRegister vtmp5);
1573
1574 void encode_iso_array(Register src, Register dst,
1575 Register len, Register res, bool ascii,
1576 FloatRegister vtmp0, FloatRegister vtmp1,
1577 FloatRegister vtmp2, FloatRegister vtmp3,
|
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/atomicAccess.hpp"
36 #include "runtime/vm_version.hpp"
37 #include "utilities/globalDefinitions.hpp"
38 #include "utilities/macros.hpp"
39 #include "utilities/powerOfTwo.hpp"
40 #include "runtime/signature.hpp"
41
42
43 class ciInlineKlass;
44
45 class OopMap;
46
47 // MacroAssembler extends Assembler by frequently used macros.
48 //
49 // Instructions for which a 'better' code sequence exists depending
50 // on arguments should also go in here.
51
52 class MacroAssembler: public Assembler {
53 friend class LIR_Assembler;
54
55 public:
56 using Assembler::mov;
57 using Assembler::movi;
58
59 protected:
60
61 // Support for VM calls
62 //
63 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
174
175 void bind(Label& L) {
176 Assembler::bind(L);
177 code()->clear_last_merge_candidate();
178 code()->set_last_label(pc());
179 }
180
181 void membar(Membar_mask_bits order_constraint);
182
183 using Assembler::ldr;
184 using Assembler::str;
185 using Assembler::ldrw;
186 using Assembler::strw;
187
188 void ldr(Register Rx, const Address &adr);
189 void ldrw(Register Rw, const Address &adr);
190 void str(Register Rx, const Address &adr);
191 void strw(Register Rx, const Address &adr);
192
193 // Frame creation and destruction shared between JITs.
194 DEBUG_ONLY(void build_frame(int framesize);)
195 void build_frame(int framesize DEBUG_ONLY(COMMA bool zap_rfp_lr_spills));
196 void remove_frame(int framesize);
197
198 virtual void _call_Unimplemented(address call_site) {
199 mov(rscratch2, call_site);
200 }
201
202 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
203 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
204 // https://reviews.llvm.org/D3311
205
206 #ifdef _WIN64
207 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
208 #else
209 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
210 #endif
211
212 // aliases defined in AARCH64 spec
213
214 template<class T>
215 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
686 mrs(0b011, 0b1110, 0b0000, 0b110, reg);
687 }
688
689 // idiv variant which deals with MINLONG as dividend and -1 as divisor
690 int corrected_idivl(Register result, Register ra, Register rb,
691 bool want_remainder, Register tmp = rscratch1);
692 int corrected_idivq(Register result, Register ra, Register rb,
693 bool want_remainder, Register tmp = rscratch1);
694
695 // Support for null-checks
696 //
697 // Generates code that causes a null OS exception if the content of reg is null.
698 // If the accessed location is M[reg + offset] and the offset is known, provide the
699 // offset. No explicit code generation is needed if the offset is within a certain
700 // range (0 <= offset <= page_size).
701
702 virtual void null_check(Register reg, int offset = -1);
703 static bool needs_explicit_null_check(intptr_t offset);
704 static bool uses_implicit_null_check(void* address);
705
706 // markWord tests, kills markWord reg
707 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
708
709 // inlineKlass queries, kills temp_reg
710 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
711
712 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
713 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
714 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
715
716 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
717 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
718 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
719 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
720 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
721 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
722
723 // Check array klass layout helper for flat or null-free arrays...
724 void test_flat_array_layout(Register lh, Label& is_flat_array);
725
726 static address target_addr_for_insn(address insn_addr);
727
728 // Required platform-specific helpers for Label::patch_instructions.
729 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
730 static int pd_patch_instruction_size(address branch, address target);
731 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
732 pd_patch_instruction_size(branch, target);
733 }
734 static address pd_call_destination(address branch) {
735 return target_addr_for_insn(branch);
736 }
737 #ifndef PRODUCT
738 static void pd_print_patched_instruction(address branch);
739 #endif
740
741 static int patch_oop(address insn_addr, address o);
742
743 // Return whether code is emitted to a scratch blob.
744 virtual bool in_scratch_emit_size() {
745 return false;
932 void set_last_Java_frame(Register last_java_sp,
933 Register last_java_fp,
934 Register last_java_pc,
935 Register scratch);
936
937 void reset_last_Java_frame(Register thread);
938
939 // thread in the default location (rthread)
940 void reset_last_Java_frame(bool clear_fp);
941
942 void resolve_jobject(Register value, Register tmp1, Register tmp2);
943 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
944
945 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
946 void c2bool(Register x);
947
948 void load_method_holder_cld(Register rresult, Register rmethod);
949 void load_method_holder(Register holder, Register method);
950
951 // oop manipulations
952 void load_metadata(Register dst, Register src);
953
954 void load_narrow_klass_compact(Register dst, Register src);
955 void load_klass(Register dst, Register src);
956 void store_klass(Register dst, Register src);
957 void cmp_klass(Register obj, Register klass, Register tmp);
958 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
959
960 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
961 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
962 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
963
964 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
965 Register tmp1, Register tmp2);
966
967 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
968 Register tmp1, Register tmp2, Register tmp3);
969
970 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
971
972 // inline type data payload offsets...
973 void payload_offset(Register inline_klass, Register offset);
974 void payload_address(Register oop, Register data, Register inline_klass);
975
976 void load_heap_oop(Register dst, Address src, Register tmp1,
977 Register tmp2, DecoratorSet decorators = 0);
978
979 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
980 Register tmp2, DecoratorSet decorators = 0);
981 void store_heap_oop(Address dst, Register val, Register tmp1,
982 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
983
984 // currently unimplemented
985 // Used for storing null. All other oop constants should be
986 // stored using routines that take a jobject.
987 void store_heap_oop_null(Address dst);
988
989 void load_prototype_header(Register dst, Register src);
990
991 void store_klass_gap(Register dst, Register src);
992
993 // This dummy is to prevent a call to store_heap_oop from
994 // converting a zero (like null) into a Register by giving
995 // the compiler two choices it can't resolve
996
997 void store_heap_oop(Address dst, void* dummy);
998
999 void encode_heap_oop(Register d, Register s);
1000 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
1001 void decode_heap_oop(Register d, Register s);
1002 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
1003 void encode_heap_oop_not_null(Register r);
1004 void decode_heap_oop_not_null(Register r);
1005 void encode_heap_oop_not_null(Register dst, Register src);
1006 void decode_heap_oop_not_null(Register dst, Register src);
1007
1008 void set_narrow_oop(Register dst, jobject obj);
1009
1010 void decode_klass_not_null_for_aot(Register dst, Register src);
1020 void reinit_heapbase();
1021
1022 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1023
1024 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
1025 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1026 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
1027 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1028
1029 void push_cont_fastpath(Register java_thread = rthread);
1030 void pop_cont_fastpath(Register java_thread = rthread);
1031
1032 // Round up to a power of two
1033 void round_to(Register reg, int modulus);
1034
1035 // java.lang.Math::round intrinsics
1036 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1037 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1038
1039 // allocation
1040
1041 void tlab_allocate(
1042 Register obj, // result: pointer to object after successful allocation
1043 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1044 int con_size_in_bytes, // object size in bytes if known at compile time
1045 Register t1, // temp register
1046 Register t2, // temp register
1047 Label& slow_case // continuation point if fast allocation fails
1048 );
1049 void verify_tlab();
1050
1051 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
1052
1053 // interface method calling
1054 void lookup_interface_method(Register recv_klass,
1055 Register intf_klass,
1056 RegisterOrConstant itable_index,
1057 Register method_result,
1058 Register scan_temp,
1059 Label& no_such_interface,
1060 bool return_method = true);
1061
1062 void lookup_interface_method_stub(Register recv_klass,
1063 Register holder_klass,
1064 Register resolved_klass,
1065 Register method_result,
1066 Register temp_reg,
1067 Register temp_reg2,
1068 int itable_index,
1069 Label& L_no_such_interface);
1070
1071 // virtual method calling
1072 // n.b. x86 allows RegisterOrConstant for vtable_index
1503 } \
1504 \
1505 void INSN(Register Rd, Register Rn, Register Rm) { \
1506 Assembler::INSN(Rd, Rn, Rm); \
1507 } \
1508 \
1509 void INSN(Register Rd, Register Rn, Register Rm, \
1510 ext::operation option, int amount = 0) { \
1511 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1512 }
1513
1514 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1515
1516 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1517 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1518 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1519 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1520
1521 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1522
1523 void verified_entry(Compile* C, int sp_inc);
1524
1525 // Inline type specific methods
1526 #include "asm/macroAssembler_common.hpp"
1527
1528 void save_stack_increment(int sp_inc, int frame_size);
1529
1530 void tableswitch(Register index, jint lowbound, jint highbound,
1531 Label &jumptable, Label &jumptable_end, int stride = 1) {
1532 adr(rscratch1, jumptable);
1533 subsw(rscratch2, index, lowbound);
1534 subsw(zr, rscratch2, highbound - lowbound);
1535 br(Assembler::HS, jumptable_end);
1536 add(rscratch1, rscratch1, rscratch2,
1537 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1538 br(rscratch1);
1539 }
1540
1541 // Form an address from base + offset in Rd. Rd may or may not
1542 // actually be used: you must use the Address that is returned. It
1543 // is up to you to ensure that the shift provided matches the size
1544 // of your data.
1545 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1546
1547 // Return true iff an address is within the 48-bit AArch64 address
1548 // space.
1549 bool is_valid_AArch64_address(address a) {
1584 #define ARRAYS_HASHCODE_REGISTERS \
1585 do { \
1586 assert(result == r0 && \
1587 ary == r1 && \
1588 cnt == r2 && \
1589 vdata0 == v3 && \
1590 vdata1 == v2 && \
1591 vdata2 == v1 && \
1592 vdata3 == v0 && \
1593 vmul0 == v4 && \
1594 vmul1 == v5 && \
1595 vmul2 == v6 && \
1596 vmul3 == v7 && \
1597 vpow == v12 && \
1598 vpowm == v13, "registers must match aarch64.ad"); \
1599 } while (0)
1600
1601 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1602
1603 void fill_words(Register base, Register cnt, Register value);
1604 void fill_words(Register base, uint64_t cnt, Register value);
1605
1606 address zero_words(Register base, uint64_t cnt);
1607 address zero_words(Register ptr, Register cnt);
1608 void zero_dcache_blocks(Register base, Register cnt);
1609
1610 static const int zero_words_block_size;
1611
1612 address byte_array_inflate(Register src, Register dst, Register len,
1613 FloatRegister vtmp1, FloatRegister vtmp2,
1614 FloatRegister vtmp3, Register tmp4);
1615
1616 void char_array_compress(Register src, Register dst, Register len,
1617 Register res,
1618 FloatRegister vtmp0, FloatRegister vtmp1,
1619 FloatRegister vtmp2, FloatRegister vtmp3,
1620 FloatRegister vtmp4, FloatRegister vtmp5);
1621
1622 void encode_iso_array(Register src, Register dst,
1623 Register len, Register res, bool ascii,
1624 FloatRegister vtmp0, FloatRegister vtmp1,
1625 FloatRegister vtmp2, FloatRegister vtmp3,
|