16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/powerOfTwo.hpp"
37
38 class OopMap;
39
40 // MacroAssembler extends Assembler by frequently used macros.
41 //
42 // Instructions for which a 'better' code sequence exists depending
43 // on arguments should also go in here.
44
45 class MacroAssembler: public Assembler {
46 friend class LIR_Assembler;
47
48 public:
49 using Assembler::mov;
50 using Assembler::movi;
51
52 protected:
53
54 // Support for VM calls
55 //
56 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
167
168 void bind(Label& L) {
169 Assembler::bind(L);
170 code()->clear_last_insn();
171 code()->set_last_label(pc());
172 }
173
174 void membar(Membar_mask_bits order_constraint);
175
176 using Assembler::ldr;
177 using Assembler::str;
178 using Assembler::ldrw;
179 using Assembler::strw;
180
181 void ldr(Register Rx, const Address &adr);
182 void ldrw(Register Rw, const Address &adr);
183 void str(Register Rx, const Address &adr);
184 void strw(Register Rx, const Address &adr);
185
186 // Frame creation and destruction shared between JITs.
187 void build_frame(int framesize);
188 void remove_frame(int framesize);
189
190 virtual void _call_Unimplemented(address call_site) {
191 mov(rscratch2, call_site);
192 }
193
194 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
195 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
196 // https://reviews.llvm.org/D3311
197
198 #ifdef _WIN64
199 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
200 #else
201 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
202 #endif
203
204 // aliases defined in AARCH64 spec
205
206 template<class T>
207 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
660 msr(0b011, 0b0100, 0b0010, 0b000, reg);
661 }
662
663 // idiv variant which deals with MINLONG as dividend and -1 as divisor
664 int corrected_idivl(Register result, Register ra, Register rb,
665 bool want_remainder, Register tmp = rscratch1);
666 int corrected_idivq(Register result, Register ra, Register rb,
667 bool want_remainder, Register tmp = rscratch1);
668
669 // Support for null-checks
670 //
671 // Generates code that causes a null OS exception if the content of reg is null.
672 // If the accessed location is M[reg + offset] and the offset is known, provide the
673 // offset. No explicit code generation is needed if the offset is within a certain
674 // range (0 <= offset <= page_size).
675
676 virtual void null_check(Register reg, int offset = -1);
677 static bool needs_explicit_null_check(intptr_t offset);
678 static bool uses_implicit_null_check(void* address);
679
680 static address target_addr_for_insn(address insn_addr);
681 static address target_addr_for_insn_or_null(address insn_addr);
682
683 // Required platform-specific helpers for Label::patch_instructions.
684 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
685 static int pd_patch_instruction_size(address branch, address target);
686 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
687 pd_patch_instruction_size(branch, target);
688 }
689 static address pd_call_destination(address branch) {
690 return target_addr_for_insn(branch);
691 }
692 #ifndef PRODUCT
693 static void pd_print_patched_instruction(address branch);
694 #endif
695
696 static int patch_oop(address insn_addr, address o);
697 static int patch_narrow_klass(address insn_addr, narrowKlass n);
698
699 // Return whether code is emitted to a scratch blob.
889
890 void reset_last_Java_frame(Register thread);
891
892 // thread in the default location (rthread)
893 void reset_last_Java_frame(bool clear_fp);
894
895 // Stores
896 void store_check(Register obj); // store check for obj - register is destroyed afterwards
897 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
898
899 void resolve_jobject(Register value, Register tmp1, Register tmp2);
900 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
901
902 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
903 void c2bool(Register x);
904
905 void load_method_holder_cld(Register rresult, Register rmethod);
906 void load_method_holder(Register holder, Register method);
907
908 // oop manipulations
909 void load_narrow_klass_compact(Register dst, Register src);
910 void load_klass(Register dst, Register src);
911 void store_klass(Register dst, Register src);
912 void cmp_klass(Register obj, Register klass, Register tmp);
913 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
914
915 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
916 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
917 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
918
919 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
920 Register tmp1, Register tmp2);
921
922 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
923 Register tmp1, Register tmp2, Register tmp3);
924
925 void load_heap_oop(Register dst, Address src, Register tmp1,
926 Register tmp2, DecoratorSet decorators = 0);
927
928 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
929 Register tmp2, DecoratorSet decorators = 0);
930 void store_heap_oop(Address dst, Register val, Register tmp1,
931 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
932
933 // currently unimplemented
934 // Used for storing null. All other oop constants should be
935 // stored using routines that take a jobject.
936 void store_heap_oop_null(Address dst);
937
938 void store_klass_gap(Register dst, Register src);
939
940 // This dummy is to prevent a call to store_heap_oop from
941 // converting a zero (like null) into a Register by giving
942 // the compiler two choices it can't resolve
943
944 void store_heap_oop(Address dst, void* dummy);
945
946 void encode_heap_oop(Register d, Register s);
947 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
948 void decode_heap_oop(Register d, Register s);
949 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
950 void encode_heap_oop_not_null(Register r);
951 void decode_heap_oop_not_null(Register r);
952 void encode_heap_oop_not_null(Register dst, Register src);
953 void decode_heap_oop_not_null(Register dst, Register src);
954
955 void set_narrow_oop(Register dst, jobject obj);
956
957 void decode_klass_not_null_for_aot(Register dst, Register src);
967 void reinit_heapbase();
968
969 DEBUG_ONLY(void verify_heapbase(const char* msg);)
970
971 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
972 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
973 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
974 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
975
976 void push_cont_fastpath(Register java_thread = rthread);
977 void pop_cont_fastpath(Register java_thread = rthread);
978
979 // Round up to a power of two
980 void round_to(Register reg, int modulus);
981
982 // java.lang.Math::round intrinsics
983 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
984 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
985
986 // allocation
987 void tlab_allocate(
988 Register obj, // result: pointer to object after successful allocation
989 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
990 int con_size_in_bytes, // object size in bytes if known at compile time
991 Register t1, // temp register
992 Register t2, // temp register
993 Label& slow_case // continuation point if fast allocation fails
994 );
995 void verify_tlab();
996
997 // interface method calling
998 void lookup_interface_method(Register recv_klass,
999 Register intf_klass,
1000 RegisterOrConstant itable_index,
1001 Register method_result,
1002 Register scan_temp,
1003 Label& no_such_interface,
1004 bool return_method = true);
1005
1006 void lookup_interface_method_stub(Register recv_klass,
1007 Register holder_klass,
1008 Register resolved_klass,
1009 Register method_result,
1010 Register temp_reg,
1011 Register temp_reg2,
1012 int itable_index,
1013 Label& L_no_such_interface);
1014
1015 // virtual method calling
1016 // n.b. x86 allows RegisterOrConstant for vtable_index
1432 } \
1433 \
1434 void INSN(Register Rd, Register Rn, Register Rm) { \
1435 Assembler::INSN(Rd, Rn, Rm); \
1436 } \
1437 \
1438 void INSN(Register Rd, Register Rn, Register Rm, \
1439 ext::operation option, int amount = 0) { \
1440 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1441 }
1442
1443 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1444
1445 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1446 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1447 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1448 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1449
1450 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1451
1452 void tableswitch(Register index, jint lowbound, jint highbound,
1453 Label &jumptable, Label &jumptable_end, int stride = 1) {
1454 adr(rscratch1, jumptable);
1455 subsw(rscratch2, index, lowbound);
1456 subsw(zr, rscratch2, highbound - lowbound);
1457 br(Assembler::HS, jumptable_end);
1458 add(rscratch1, rscratch1, rscratch2,
1459 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1460 br(rscratch1);
1461 }
1462
1463 // Form an address from base + offset in Rd. Rd may or may not
1464 // actually be used: you must use the Address that is returned. It
1465 // is up to you to ensure that the shift provided matches the size
1466 // of your data.
1467 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1468
1469 // Return true iff an address is within the 48-bit AArch64 address
1470 // space.
1471 bool is_valid_AArch64_address(address a) {
1503 #define ARRAYS_HASHCODE_REGISTERS \
1504 do { \
1505 assert(result == r0 && \
1506 ary == r1 && \
1507 cnt == r2 && \
1508 vdata0 == v3 && \
1509 vdata1 == v2 && \
1510 vdata2 == v1 && \
1511 vdata3 == v0 && \
1512 vmul0 == v4 && \
1513 vmul1 == v5 && \
1514 vmul2 == v6 && \
1515 vmul3 == v7 && \
1516 vpow == v12 && \
1517 vpowm == v13, "registers must match aarch64.ad"); \
1518 } while (0)
1519
1520 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1521
1522 void fill_words(Register base, Register cnt, Register value);
1523 address zero_words(Register base, uint64_t cnt);
1524 address zero_words(Register ptr, Register cnt);
1525 void zero_dcache_blocks(Register base, Register cnt);
1526
1527 static const int zero_words_block_size;
1528
1529 address byte_array_inflate(Register src, Register dst, Register len,
1530 FloatRegister vtmp1, FloatRegister vtmp2,
1531 FloatRegister vtmp3, Register tmp4);
1532
1533 void char_array_compress(Register src, Register dst, Register len,
1534 Register res,
1535 FloatRegister vtmp0, FloatRegister vtmp1,
1536 FloatRegister vtmp2, FloatRegister vtmp3,
1537 FloatRegister vtmp4, FloatRegister vtmp5);
1538
1539 void encode_iso_array(Register src, Register dst,
1540 Register len, Register res, bool ascii,
1541 FloatRegister vtmp0, FloatRegister vtmp1,
1542 FloatRegister vtmp2, FloatRegister vtmp3,
|
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/macros.hpp"
37 #include "utilities/powerOfTwo.hpp"
38 #include "runtime/signature.hpp"
39
40
41 class ciInlineKlass;
42
43 class OopMap;
44
45 // MacroAssembler extends Assembler by frequently used macros.
46 //
47 // Instructions for which a 'better' code sequence exists depending
48 // on arguments should also go in here.
49
50 class MacroAssembler: public Assembler {
51 friend class LIR_Assembler;
52
53 public:
54 using Assembler::mov;
55 using Assembler::movi;
56
57 protected:
58
59 // Support for VM calls
60 //
61 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
172
173 void bind(Label& L) {
174 Assembler::bind(L);
175 code()->clear_last_insn();
176 code()->set_last_label(pc());
177 }
178
179 void membar(Membar_mask_bits order_constraint);
180
181 using Assembler::ldr;
182 using Assembler::str;
183 using Assembler::ldrw;
184 using Assembler::strw;
185
186 void ldr(Register Rx, const Address &adr);
187 void ldrw(Register Rw, const Address &adr);
188 void str(Register Rx, const Address &adr);
189 void strw(Register Rx, const Address &adr);
190
191 // Frame creation and destruction shared between JITs.
192 DEBUG_ONLY(void build_frame(int framesize);)
193 void build_frame(int framesize DEBUG_ONLY(COMMA bool zap_rfp_lr_spills));
194 void remove_frame(int framesize);
195
196 virtual void _call_Unimplemented(address call_site) {
197 mov(rscratch2, call_site);
198 }
199
200 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
201 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
202 // https://reviews.llvm.org/D3311
203
204 #ifdef _WIN64
205 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
206 #else
207 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
208 #endif
209
210 // aliases defined in AARCH64 spec
211
212 template<class T>
213 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
666 msr(0b011, 0b0100, 0b0010, 0b000, reg);
667 }
668
669 // idiv variant which deals with MINLONG as dividend and -1 as divisor
670 int corrected_idivl(Register result, Register ra, Register rb,
671 bool want_remainder, Register tmp = rscratch1);
672 int corrected_idivq(Register result, Register ra, Register rb,
673 bool want_remainder, Register tmp = rscratch1);
674
675 // Support for null-checks
676 //
677 // Generates code that causes a null OS exception if the content of reg is null.
678 // If the accessed location is M[reg + offset] and the offset is known, provide the
679 // offset. No explicit code generation is needed if the offset is within a certain
680 // range (0 <= offset <= page_size).
681
682 virtual void null_check(Register reg, int offset = -1);
683 static bool needs_explicit_null_check(intptr_t offset);
684 static bool uses_implicit_null_check(void* address);
685
686 // markWord tests, kills markWord reg
687 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
688
689 // inlineKlass queries, kills temp_reg
690 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
691
692 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
693 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
694 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
695 void test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker);
696
697 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
698 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
699 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
700 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
701 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
702 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
703
704 // Check array klass layout helper for flat or null-free arrays...
705 void test_flat_array_layout(Register lh, Label& is_flat_array);
706 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array);
707
708 static address target_addr_for_insn(address insn_addr);
709 static address target_addr_for_insn_or_null(address insn_addr);
710
711 // Required platform-specific helpers for Label::patch_instructions.
712 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
713 static int pd_patch_instruction_size(address branch, address target);
714 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
715 pd_patch_instruction_size(branch, target);
716 }
717 static address pd_call_destination(address branch) {
718 return target_addr_for_insn(branch);
719 }
720 #ifndef PRODUCT
721 static void pd_print_patched_instruction(address branch);
722 #endif
723
724 static int patch_oop(address insn_addr, address o);
725 static int patch_narrow_klass(address insn_addr, narrowKlass n);
726
727 // Return whether code is emitted to a scratch blob.
917
918 void reset_last_Java_frame(Register thread);
919
920 // thread in the default location (rthread)
921 void reset_last_Java_frame(bool clear_fp);
922
923 // Stores
924 void store_check(Register obj); // store check for obj - register is destroyed afterwards
925 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
926
927 void resolve_jobject(Register value, Register tmp1, Register tmp2);
928 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
929
930 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
931 void c2bool(Register x);
932
933 void load_method_holder_cld(Register rresult, Register rmethod);
934 void load_method_holder(Register holder, Register method);
935
936 // oop manipulations
937 void load_metadata(Register dst, Register src);
938
939 void load_narrow_klass_compact(Register dst, Register src);
940 void load_klass(Register dst, Register src);
941 void store_klass(Register dst, Register src);
942 void cmp_klass(Register obj, Register klass, Register tmp);
943 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
944
945 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
946 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
947 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
948
949 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
950 Register tmp1, Register tmp2);
951
952 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
953 Register tmp1, Register tmp2, Register tmp3);
954
955 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
956
957 // inline type data payload offsets...
958 void payload_offset(Register inline_klass, Register offset);
959 void payload_address(Register oop, Register data, Register inline_klass);
960 // get data payload ptr a flat value array at index, kills rcx and index
961 void data_for_value_array_index(Register array, Register array_klass,
962 Register index, Register data);
963
964 void load_heap_oop(Register dst, Address src, Register tmp1,
965 Register tmp2, DecoratorSet decorators = 0);
966
967 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
968 Register tmp2, DecoratorSet decorators = 0);
969 void store_heap_oop(Address dst, Register val, Register tmp1,
970 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
971
972 // currently unimplemented
973 // Used for storing null. All other oop constants should be
974 // stored using routines that take a jobject.
975 void store_heap_oop_null(Address dst);
976
977 void load_prototype_header(Register dst, Register src);
978
979 void store_klass_gap(Register dst, Register src);
980
981 // This dummy is to prevent a call to store_heap_oop from
982 // converting a zero (like null) into a Register by giving
983 // the compiler two choices it can't resolve
984
985 void store_heap_oop(Address dst, void* dummy);
986
987 void encode_heap_oop(Register d, Register s);
988 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
989 void decode_heap_oop(Register d, Register s);
990 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
991 void encode_heap_oop_not_null(Register r);
992 void decode_heap_oop_not_null(Register r);
993 void encode_heap_oop_not_null(Register dst, Register src);
994 void decode_heap_oop_not_null(Register dst, Register src);
995
996 void set_narrow_oop(Register dst, jobject obj);
997
998 void decode_klass_not_null_for_aot(Register dst, Register src);
1008 void reinit_heapbase();
1009
1010 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1011
1012 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
1013 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1014 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
1015 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1016
1017 void push_cont_fastpath(Register java_thread = rthread);
1018 void pop_cont_fastpath(Register java_thread = rthread);
1019
1020 // Round up to a power of two
1021 void round_to(Register reg, int modulus);
1022
1023 // java.lang.Math::round intrinsics
1024 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1025 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1026
1027 // allocation
1028
1029 // Object / value buffer allocation...
1030 // Allocate instance of klass, assumes klass initialized by caller
1031 // new_obj prefers to be rax
1032 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
1033 void allocate_instance(Register klass, Register new_obj,
1034 Register t1, Register t2,
1035 bool clear_fields, Label& alloc_failed);
1036
1037 void tlab_allocate(
1038 Register obj, // result: pointer to object after successful allocation
1039 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1040 int con_size_in_bytes, // object size in bytes if known at compile time
1041 Register t1, // temp register
1042 Register t2, // temp register
1043 Label& slow_case // continuation point if fast allocation fails
1044 );
1045 void verify_tlab();
1046
1047 // For field "index" within "klass", return inline_klass ...
1048 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
1049 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
1050
1051
1052 // interface method calling
1053 void lookup_interface_method(Register recv_klass,
1054 Register intf_klass,
1055 RegisterOrConstant itable_index,
1056 Register method_result,
1057 Register scan_temp,
1058 Label& no_such_interface,
1059 bool return_method = true);
1060
1061 void lookup_interface_method_stub(Register recv_klass,
1062 Register holder_klass,
1063 Register resolved_klass,
1064 Register method_result,
1065 Register temp_reg,
1066 Register temp_reg2,
1067 int itable_index,
1068 Label& L_no_such_interface);
1069
1070 // virtual method calling
1071 // n.b. x86 allows RegisterOrConstant for vtable_index
1487 } \
1488 \
1489 void INSN(Register Rd, Register Rn, Register Rm) { \
1490 Assembler::INSN(Rd, Rn, Rm); \
1491 } \
1492 \
1493 void INSN(Register Rd, Register Rn, Register Rm, \
1494 ext::operation option, int amount = 0) { \
1495 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1496 }
1497
1498 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1499
1500 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1501 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1502 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1503 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1504
1505 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1506
1507 void verified_entry(Compile* C, int sp_inc);
1508
1509 // Inline type specific methods
1510 #include "asm/macroAssembler_common.hpp"
1511
1512 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1513 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1514 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1515 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1516 RegState reg_state[]);
1517 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1518 VMRegPair* from, int from_count, int& from_index, VMReg to,
1519 RegState reg_state[], Register val_array);
1520 int extend_stack_for_inline_args(int args_on_stack);
1521 void remove_frame(int initial_framesize, bool needs_stack_repair);
1522 VMReg spill_reg_for(VMReg reg);
1523 void save_stack_increment(int sp_inc, int frame_size);
1524
1525 void tableswitch(Register index, jint lowbound, jint highbound,
1526 Label &jumptable, Label &jumptable_end, int stride = 1) {
1527 adr(rscratch1, jumptable);
1528 subsw(rscratch2, index, lowbound);
1529 subsw(zr, rscratch2, highbound - lowbound);
1530 br(Assembler::HS, jumptable_end);
1531 add(rscratch1, rscratch1, rscratch2,
1532 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1533 br(rscratch1);
1534 }
1535
1536 // Form an address from base + offset in Rd. Rd may or may not
1537 // actually be used: you must use the Address that is returned. It
1538 // is up to you to ensure that the shift provided matches the size
1539 // of your data.
1540 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1541
1542 // Return true iff an address is within the 48-bit AArch64 address
1543 // space.
1544 bool is_valid_AArch64_address(address a) {
1576 #define ARRAYS_HASHCODE_REGISTERS \
1577 do { \
1578 assert(result == r0 && \
1579 ary == r1 && \
1580 cnt == r2 && \
1581 vdata0 == v3 && \
1582 vdata1 == v2 && \
1583 vdata2 == v1 && \
1584 vdata3 == v0 && \
1585 vmul0 == v4 && \
1586 vmul1 == v5 && \
1587 vmul2 == v6 && \
1588 vmul3 == v7 && \
1589 vpow == v12 && \
1590 vpowm == v13, "registers must match aarch64.ad"); \
1591 } while (0)
1592
1593 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1594
1595 void fill_words(Register base, Register cnt, Register value);
1596 void fill_words(Register base, uint64_t cnt, Register value);
1597
1598 address zero_words(Register base, uint64_t cnt);
1599 address zero_words(Register ptr, Register cnt);
1600 void zero_dcache_blocks(Register base, Register cnt);
1601
1602 static const int zero_words_block_size;
1603
1604 address byte_array_inflate(Register src, Register dst, Register len,
1605 FloatRegister vtmp1, FloatRegister vtmp2,
1606 FloatRegister vtmp3, Register tmp4);
1607
1608 void char_array_compress(Register src, Register dst, Register len,
1609 Register res,
1610 FloatRegister vtmp0, FloatRegister vtmp1,
1611 FloatRegister vtmp2, FloatRegister vtmp3,
1612 FloatRegister vtmp4, FloatRegister vtmp5);
1613
1614 void encode_iso_array(Register src, Register dst,
1615 Register len, Register res, bool ascii,
1616 FloatRegister vtmp0, FloatRegister vtmp1,
1617 FloatRegister vtmp2, FloatRegister vtmp3,
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