16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/powerOfTwo.hpp"
37
38 class OopMap;
39
40 // MacroAssembler extends Assembler by frequently used macros.
41 //
42 // Instructions for which a 'better' code sequence exists depending
43 // on arguments should also go in here.
44
45 class MacroAssembler: public Assembler {
46 friend class LIR_Assembler;
47
48 public:
49 using Assembler::mov;
50 using Assembler::movi;
51
52 protected:
53
54 // Support for VM calls
55 //
56 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
659 msr(0b011, 0b0100, 0b0010, 0b000, reg);
660 }
661
662 // idiv variant which deals with MINLONG as dividend and -1 as divisor
663 int corrected_idivl(Register result, Register ra, Register rb,
664 bool want_remainder, Register tmp = rscratch1);
665 int corrected_idivq(Register result, Register ra, Register rb,
666 bool want_remainder, Register tmp = rscratch1);
667
668 // Support for null-checks
669 //
670 // Generates code that causes a null OS exception if the content of reg is null.
671 // If the accessed location is M[reg + offset] and the offset is known, provide the
672 // offset. No explicit code generation is needed if the offset is within a certain
673 // range (0 <= offset <= page_size).
674
675 virtual void null_check(Register reg, int offset = -1);
676 static bool needs_explicit_null_check(intptr_t offset);
677 static bool uses_implicit_null_check(void* address);
678
679 static address target_addr_for_insn(address insn_addr);
680 static address target_addr_for_insn_or_null(address insn_addr);
681
682 // Required platform-specific helpers for Label::patch_instructions.
683 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
684 static int pd_patch_instruction_size(address branch, address target);
685 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
686 pd_patch_instruction_size(branch, target);
687 }
688 static address pd_call_destination(address branch) {
689 return target_addr_for_insn(branch);
690 }
691 #ifndef PRODUCT
692 static void pd_print_patched_instruction(address branch);
693 #endif
694
695 static int patch_oop(address insn_addr, address o);
696 static int patch_narrow_klass(address insn_addr, narrowKlass n);
697
698 // Return whether code is emitted to a scratch blob.
888
889 void reset_last_Java_frame(Register thread);
890
891 // thread in the default location (rthread)
892 void reset_last_Java_frame(bool clear_fp);
893
894 // Stores
895 void store_check(Register obj); // store check for obj - register is destroyed afterwards
896 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
897
898 void resolve_jobject(Register value, Register tmp1, Register tmp2);
899 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
900
901 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
902 void c2bool(Register x);
903
904 void load_method_holder_cld(Register rresult, Register rmethod);
905 void load_method_holder(Register holder, Register method);
906
907 // oop manipulations
908 void load_narrow_klass_compact(Register dst, Register src);
909 void load_klass(Register dst, Register src);
910 void store_klass(Register dst, Register src);
911 void cmp_klass(Register obj, Register klass, Register tmp);
912 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
913
914 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
915 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
916 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
917
918 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
919 Register tmp1, Register tmp2);
920
921 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
922 Register tmp1, Register tmp2, Register tmp3);
923
924 void load_heap_oop(Register dst, Address src, Register tmp1,
925 Register tmp2, DecoratorSet decorators = 0);
926
927 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
928 Register tmp2, DecoratorSet decorators = 0);
929 void store_heap_oop(Address dst, Register val, Register tmp1,
930 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
931
932 // currently unimplemented
933 // Used for storing null. All other oop constants should be
934 // stored using routines that take a jobject.
935 void store_heap_oop_null(Address dst);
936
937 void store_klass_gap(Register dst, Register src);
938
939 // This dummy is to prevent a call to store_heap_oop from
940 // converting a zero (like null) into a Register by giving
941 // the compiler two choices it can't resolve
942
943 void store_heap_oop(Address dst, void* dummy);
944
945 void encode_heap_oop(Register d, Register s);
946 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
947 void decode_heap_oop(Register d, Register s);
948 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
949 void encode_heap_oop_not_null(Register r);
950 void decode_heap_oop_not_null(Register r);
951 void encode_heap_oop_not_null(Register dst, Register src);
952 void decode_heap_oop_not_null(Register dst, Register src);
953
954 void set_narrow_oop(Register dst, jobject obj);
955
956 void decode_klass_not_null_for_aot(Register dst, Register src);
966 void reinit_heapbase();
967
968 DEBUG_ONLY(void verify_heapbase(const char* msg);)
969
970 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
971 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
972 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
973 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
974
975 void push_cont_fastpath(Register java_thread = rthread);
976 void pop_cont_fastpath(Register java_thread = rthread);
977
978 // Round up to a power of two
979 void round_to(Register reg, int modulus);
980
981 // java.lang.Math::round intrinsics
982 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
983 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
984
985 // allocation
986 void tlab_allocate(
987 Register obj, // result: pointer to object after successful allocation
988 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
989 int con_size_in_bytes, // object size in bytes if known at compile time
990 Register t1, // temp register
991 Register t2, // temp register
992 Label& slow_case // continuation point if fast allocation fails
993 );
994 void verify_tlab();
995
996 // interface method calling
997 void lookup_interface_method(Register recv_klass,
998 Register intf_klass,
999 RegisterOrConstant itable_index,
1000 Register method_result,
1001 Register scan_temp,
1002 Label& no_such_interface,
1003 bool return_method = true);
1004
1005 void lookup_interface_method_stub(Register recv_klass,
1006 Register holder_klass,
1007 Register resolved_klass,
1008 Register method_result,
1009 Register temp_reg,
1010 Register temp_reg2,
1011 int itable_index,
1012 Label& L_no_such_interface);
1013
1014 // virtual method calling
1015 // n.b. x86 allows RegisterOrConstant for vtable_index
1441 } \
1442 \
1443 void INSN(Register Rd, Register Rn, Register Rm) { \
1444 Assembler::INSN(Rd, Rn, Rm); \
1445 } \
1446 \
1447 void INSN(Register Rd, Register Rn, Register Rm, \
1448 ext::operation option, int amount = 0) { \
1449 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1450 }
1451
1452 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1453
1454 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1455 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1456 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1457 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1458
1459 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1460
1461 void tableswitch(Register index, jint lowbound, jint highbound,
1462 Label &jumptable, Label &jumptable_end, int stride = 1) {
1463 adr(rscratch1, jumptable);
1464 subsw(rscratch2, index, lowbound);
1465 subsw(zr, rscratch2, highbound - lowbound);
1466 br(Assembler::HS, jumptable_end);
1467 add(rscratch1, rscratch1, rscratch2,
1468 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1469 br(rscratch1);
1470 }
1471
1472 // Form an address from base + offset in Rd. Rd may or may not
1473 // actually be used: you must use the Address that is returned. It
1474 // is up to you to ensure that the shift provided matches the size
1475 // of your data.
1476 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1477
1478 // Return true iff an address is within the 48-bit AArch64 address
1479 // space.
1480 bool is_valid_AArch64_address(address a) {
1512 #define ARRAYS_HASHCODE_REGISTERS \
1513 do { \
1514 assert(result == r0 && \
1515 ary == r1 && \
1516 cnt == r2 && \
1517 vdata0 == v3 && \
1518 vdata1 == v2 && \
1519 vdata2 == v1 && \
1520 vdata3 == v0 && \
1521 vmul0 == v4 && \
1522 vmul1 == v5 && \
1523 vmul2 == v6 && \
1524 vmul3 == v7 && \
1525 vpow == v12 && \
1526 vpowm == v13, "registers must match aarch64.ad"); \
1527 } while (0)
1528
1529 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1530
1531 void fill_words(Register base, Register cnt, Register value);
1532 address zero_words(Register base, uint64_t cnt);
1533 address zero_words(Register ptr, Register cnt);
1534 void zero_dcache_blocks(Register base, Register cnt);
1535
1536 static const int zero_words_block_size;
1537
1538 address byte_array_inflate(Register src, Register dst, Register len,
1539 FloatRegister vtmp1, FloatRegister vtmp2,
1540 FloatRegister vtmp3, Register tmp4);
1541
1542 void char_array_compress(Register src, Register dst, Register len,
1543 Register res,
1544 FloatRegister vtmp0, FloatRegister vtmp1,
1545 FloatRegister vtmp2, FloatRegister vtmp3,
1546 FloatRegister vtmp4, FloatRegister vtmp5);
1547
1548 void encode_iso_array(Register src, Register dst,
1549 Register len, Register res, bool ascii,
1550 FloatRegister vtmp0, FloatRegister vtmp1,
1551 FloatRegister vtmp2, FloatRegister vtmp3,
|
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/macros.hpp"
37 #include "utilities/powerOfTwo.hpp"
38 #include "runtime/signature.hpp"
39
40
41 class ciInlineKlass;
42
43 class OopMap;
44
45 // MacroAssembler extends Assembler by frequently used macros.
46 //
47 // Instructions for which a 'better' code sequence exists depending
48 // on arguments should also go in here.
49
50 class MacroAssembler: public Assembler {
51 friend class LIR_Assembler;
52
53 public:
54 using Assembler::mov;
55 using Assembler::movi;
56
57 protected:
58
59 // Support for VM calls
60 //
61 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
664 msr(0b011, 0b0100, 0b0010, 0b000, reg);
665 }
666
667 // idiv variant which deals with MINLONG as dividend and -1 as divisor
668 int corrected_idivl(Register result, Register ra, Register rb,
669 bool want_remainder, Register tmp = rscratch1);
670 int corrected_idivq(Register result, Register ra, Register rb,
671 bool want_remainder, Register tmp = rscratch1);
672
673 // Support for null-checks
674 //
675 // Generates code that causes a null OS exception if the content of reg is null.
676 // If the accessed location is M[reg + offset] and the offset is known, provide the
677 // offset. No explicit code generation is needed if the offset is within a certain
678 // range (0 <= offset <= page_size).
679
680 virtual void null_check(Register reg, int offset = -1);
681 static bool needs_explicit_null_check(intptr_t offset);
682 static bool uses_implicit_null_check(void* address);
683
684 // markWord tests, kills markWord reg
685 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
686
687 // inlineKlass queries, kills temp_reg
688 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
689
690 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
691 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
692 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
693 void test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker);
694
695 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
696 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
697 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
698 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
699 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
700 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
701
702 // Check array klass layout helper for flat or null-free arrays...
703 void test_flat_array_layout(Register lh, Label& is_flat_array);
704 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array);
705
706 static address target_addr_for_insn(address insn_addr);
707 static address target_addr_for_insn_or_null(address insn_addr);
708
709 // Required platform-specific helpers for Label::patch_instructions.
710 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
711 static int pd_patch_instruction_size(address branch, address target);
712 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
713 pd_patch_instruction_size(branch, target);
714 }
715 static address pd_call_destination(address branch) {
716 return target_addr_for_insn(branch);
717 }
718 #ifndef PRODUCT
719 static void pd_print_patched_instruction(address branch);
720 #endif
721
722 static int patch_oop(address insn_addr, address o);
723 static int patch_narrow_klass(address insn_addr, narrowKlass n);
724
725 // Return whether code is emitted to a scratch blob.
915
916 void reset_last_Java_frame(Register thread);
917
918 // thread in the default location (rthread)
919 void reset_last_Java_frame(bool clear_fp);
920
921 // Stores
922 void store_check(Register obj); // store check for obj - register is destroyed afterwards
923 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
924
925 void resolve_jobject(Register value, Register tmp1, Register tmp2);
926 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
927
928 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
929 void c2bool(Register x);
930
931 void load_method_holder_cld(Register rresult, Register rmethod);
932 void load_method_holder(Register holder, Register method);
933
934 // oop manipulations
935 void load_metadata(Register dst, Register src);
936
937 void load_narrow_klass_compact(Register dst, Register src);
938 void load_klass(Register dst, Register src);
939 void store_klass(Register dst, Register src);
940 void cmp_klass(Register obj, Register klass, Register tmp);
941 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
942
943 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
944 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
945 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
946
947 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
948 Register tmp1, Register tmp2);
949
950 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
951 Register tmp1, Register tmp2, Register tmp3);
952
953 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
954
955 // inline type data payload offsets...
956 void payload_offset(Register inline_klass, Register offset);
957 void payload_address(Register oop, Register data, Register inline_klass);
958 // get data payload ptr a flat value array at index, kills rcx and index
959 void data_for_value_array_index(Register array, Register array_klass,
960 Register index, Register data);
961
962 void load_heap_oop(Register dst, Address src, Register tmp1,
963 Register tmp2, DecoratorSet decorators = 0);
964
965 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
966 Register tmp2, DecoratorSet decorators = 0);
967 void store_heap_oop(Address dst, Register val, Register tmp1,
968 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
969
970 // currently unimplemented
971 // Used for storing null. All other oop constants should be
972 // stored using routines that take a jobject.
973 void store_heap_oop_null(Address dst);
974
975 void load_prototype_header(Register dst, Register src);
976
977 void store_klass_gap(Register dst, Register src);
978
979 // This dummy is to prevent a call to store_heap_oop from
980 // converting a zero (like null) into a Register by giving
981 // the compiler two choices it can't resolve
982
983 void store_heap_oop(Address dst, void* dummy);
984
985 void encode_heap_oop(Register d, Register s);
986 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
987 void decode_heap_oop(Register d, Register s);
988 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
989 void encode_heap_oop_not_null(Register r);
990 void decode_heap_oop_not_null(Register r);
991 void encode_heap_oop_not_null(Register dst, Register src);
992 void decode_heap_oop_not_null(Register dst, Register src);
993
994 void set_narrow_oop(Register dst, jobject obj);
995
996 void decode_klass_not_null_for_aot(Register dst, Register src);
1006 void reinit_heapbase();
1007
1008 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1009
1010 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
1011 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1012 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
1013 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1014
1015 void push_cont_fastpath(Register java_thread = rthread);
1016 void pop_cont_fastpath(Register java_thread = rthread);
1017
1018 // Round up to a power of two
1019 void round_to(Register reg, int modulus);
1020
1021 // java.lang.Math::round intrinsics
1022 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1023 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1024
1025 // allocation
1026
1027 // Object / value buffer allocation...
1028 // Allocate instance of klass, assumes klass initialized by caller
1029 // new_obj prefers to be rax
1030 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
1031 void allocate_instance(Register klass, Register new_obj,
1032 Register t1, Register t2,
1033 bool clear_fields, Label& alloc_failed);
1034
1035 void tlab_allocate(
1036 Register obj, // result: pointer to object after successful allocation
1037 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1038 int con_size_in_bytes, // object size in bytes if known at compile time
1039 Register t1, // temp register
1040 Register t2, // temp register
1041 Label& slow_case // continuation point if fast allocation fails
1042 );
1043 void verify_tlab();
1044
1045 // For field "index" within "klass", return inline_klass ...
1046 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
1047 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
1048
1049
1050 // interface method calling
1051 void lookup_interface_method(Register recv_klass,
1052 Register intf_klass,
1053 RegisterOrConstant itable_index,
1054 Register method_result,
1055 Register scan_temp,
1056 Label& no_such_interface,
1057 bool return_method = true);
1058
1059 void lookup_interface_method_stub(Register recv_klass,
1060 Register holder_klass,
1061 Register resolved_klass,
1062 Register method_result,
1063 Register temp_reg,
1064 Register temp_reg2,
1065 int itable_index,
1066 Label& L_no_such_interface);
1067
1068 // virtual method calling
1069 // n.b. x86 allows RegisterOrConstant for vtable_index
1495 } \
1496 \
1497 void INSN(Register Rd, Register Rn, Register Rm) { \
1498 Assembler::INSN(Rd, Rn, Rm); \
1499 } \
1500 \
1501 void INSN(Register Rd, Register Rn, Register Rm, \
1502 ext::operation option, int amount = 0) { \
1503 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1504 }
1505
1506 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1507
1508 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1509 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1510 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1511 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1512
1513 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1514
1515 void verified_entry(Compile* C, int sp_inc);
1516
1517 // Inline type specific methods
1518 #include "asm/macroAssembler_common.hpp"
1519
1520 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1521 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1522 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1523 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1524 RegState reg_state[]);
1525 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1526 VMRegPair* from, int from_count, int& from_index, VMReg to,
1527 RegState reg_state[], Register val_array);
1528 int extend_stack_for_inline_args(int args_on_stack);
1529 void remove_frame(int initial_framesize, bool needs_stack_repair);
1530 VMReg spill_reg_for(VMReg reg);
1531 void save_stack_increment(int sp_inc, int frame_size);
1532
1533 void tableswitch(Register index, jint lowbound, jint highbound,
1534 Label &jumptable, Label &jumptable_end, int stride = 1) {
1535 adr(rscratch1, jumptable);
1536 subsw(rscratch2, index, lowbound);
1537 subsw(zr, rscratch2, highbound - lowbound);
1538 br(Assembler::HS, jumptable_end);
1539 add(rscratch1, rscratch1, rscratch2,
1540 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1541 br(rscratch1);
1542 }
1543
1544 // Form an address from base + offset in Rd. Rd may or may not
1545 // actually be used: you must use the Address that is returned. It
1546 // is up to you to ensure that the shift provided matches the size
1547 // of your data.
1548 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1549
1550 // Return true iff an address is within the 48-bit AArch64 address
1551 // space.
1552 bool is_valid_AArch64_address(address a) {
1584 #define ARRAYS_HASHCODE_REGISTERS \
1585 do { \
1586 assert(result == r0 && \
1587 ary == r1 && \
1588 cnt == r2 && \
1589 vdata0 == v3 && \
1590 vdata1 == v2 && \
1591 vdata2 == v1 && \
1592 vdata3 == v0 && \
1593 vmul0 == v4 && \
1594 vmul1 == v5 && \
1595 vmul2 == v6 && \
1596 vmul3 == v7 && \
1597 vpow == v12 && \
1598 vpowm == v13, "registers must match aarch64.ad"); \
1599 } while (0)
1600
1601 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1602
1603 void fill_words(Register base, Register cnt, Register value);
1604 void fill_words(Register base, uint64_t cnt, Register value);
1605
1606 address zero_words(Register base, uint64_t cnt);
1607 address zero_words(Register ptr, Register cnt);
1608 void zero_dcache_blocks(Register base, Register cnt);
1609
1610 static const int zero_words_block_size;
1611
1612 address byte_array_inflate(Register src, Register dst, Register len,
1613 FloatRegister vtmp1, FloatRegister vtmp2,
1614 FloatRegister vtmp3, Register tmp4);
1615
1616 void char_array_compress(Register src, Register dst, Register len,
1617 Register res,
1618 FloatRegister vtmp0, FloatRegister vtmp1,
1619 FloatRegister vtmp2, FloatRegister vtmp3,
1620 FloatRegister vtmp4, FloatRegister vtmp5);
1621
1622 void encode_iso_array(Register src, Register dst,
1623 Register len, Register res, bool ascii,
1624 FloatRegister vtmp0, FloatRegister vtmp1,
1625 FloatRegister vtmp2, FloatRegister vtmp3,
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