15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "oops/compressedKlass.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/powerOfTwo.hpp"
36
37 class OopMap;
38
39 // MacroAssembler extends Assembler by frequently used macros.
40 //
41 // Instructions for which a 'better' code sequence exists depending
42 // on arguments should also go in here.
43
44 class MacroAssembler: public Assembler {
45 friend class LIR_Assembler;
46
47 public:
48 using Assembler::mov;
49 using Assembler::movi;
50
51 protected:
52
53 // Support for VM calls
54 //
55 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
621 msr(0b011, 0b0100, 0b0010, 0b000, reg);
622 }
623
624 // idiv variant which deals with MINLONG as dividend and -1 as divisor
625 int corrected_idivl(Register result, Register ra, Register rb,
626 bool want_remainder, Register tmp = rscratch1);
627 int corrected_idivq(Register result, Register ra, Register rb,
628 bool want_remainder, Register tmp = rscratch1);
629
630 // Support for null-checks
631 //
632 // Generates code that causes a null OS exception if the content of reg is null.
633 // If the accessed location is M[reg + offset] and the offset is known, provide the
634 // offset. No explicit code generation is needed if the offset is within a certain
635 // range (0 <= offset <= page_size).
636
637 virtual void null_check(Register reg, int offset = -1);
638 static bool needs_explicit_null_check(intptr_t offset);
639 static bool uses_implicit_null_check(void* address);
640
641 static address target_addr_for_insn(address insn_addr, unsigned insn);
642 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
643 static address target_addr_for_insn(address insn_addr) {
644 unsigned insn = *(unsigned*)insn_addr;
645 return target_addr_for_insn(insn_addr, insn);
646 }
647 static address target_addr_for_insn_or_null(address insn_addr) {
648 unsigned insn = *(unsigned*)insn_addr;
649 return target_addr_for_insn_or_null(insn_addr, insn);
650 }
651
652 // Required platform-specific helpers for Label::patch_instructions.
653 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
654 static int pd_patch_instruction_size(address branch, address target);
655 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
656 pd_patch_instruction_size(branch, target);
657 }
658 static address pd_call_destination(address branch) {
659 return target_addr_for_insn(branch);
660 }
858
859 void reset_last_Java_frame(Register thread);
860
861 // thread in the default location (rthread)
862 void reset_last_Java_frame(bool clear_fp);
863
864 // Stores
865 void store_check(Register obj); // store check for obj - register is destroyed afterwards
866 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
867
868 void resolve_jobject(Register value, Register tmp1, Register tmp2);
869 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
870
871 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
872 void c2bool(Register x);
873
874 void load_method_holder_cld(Register rresult, Register rmethod);
875 void load_method_holder(Register holder, Register method);
876
877 // oop manipulations
878 void load_klass(Register dst, Register src);
879 void store_klass(Register dst, Register src);
880 void cmp_klass(Register oop, Register trial_klass, Register tmp);
881
882 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
883 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
884 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
885
886 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
887 Register tmp1, Register tmp2);
888
889 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
890 Register tmp1, Register tmp2, Register tmp3);
891
892 void load_heap_oop(Register dst, Address src, Register tmp1,
893 Register tmp2, DecoratorSet decorators = 0);
894
895 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
896 Register tmp2, DecoratorSet decorators = 0);
897 void store_heap_oop(Address dst, Register val, Register tmp1,
898 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
899
900 // currently unimplemented
901 // Used for storing null. All other oop constants should be
902 // stored using routines that take a jobject.
903 void store_heap_oop_null(Address dst);
904
905 void store_klass_gap(Register dst, Register src);
906
907 // This dummy is to prevent a call to store_heap_oop from
908 // converting a zero (like null) into a Register by giving
909 // the compiler two choices it can't resolve
910
911 void store_heap_oop(Address dst, void* dummy);
912
913 void encode_heap_oop(Register d, Register s);
914 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
915 void decode_heap_oop(Register d, Register s);
916 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
917 void encode_heap_oop_not_null(Register r);
918 void decode_heap_oop_not_null(Register r);
919 void encode_heap_oop_not_null(Register dst, Register src);
920 void decode_heap_oop_not_null(Register dst, Register src);
921
922 void set_narrow_oop(Register dst, jobject obj);
923
924 void encode_klass_not_null(Register r);
932 void reinit_heapbase();
933
934 DEBUG_ONLY(void verify_heapbase(const char* msg);)
935
936 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
937 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
938 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
939 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
940
941 void push_cont_fastpath(Register java_thread);
942 void pop_cont_fastpath(Register java_thread);
943
944 // Round up to a power of two
945 void round_to(Register reg, int modulus);
946
947 // java.lang.Math::round intrinsics
948 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
949 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
950
951 // allocation
952 void tlab_allocate(
953 Register obj, // result: pointer to object after successful allocation
954 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
955 int con_size_in_bytes, // object size in bytes if known at compile time
956 Register t1, // temp register
957 Register t2, // temp register
958 Label& slow_case // continuation point if fast allocation fails
959 );
960 void verify_tlab();
961
962 // interface method calling
963 void lookup_interface_method(Register recv_klass,
964 Register intf_klass,
965 RegisterOrConstant itable_index,
966 Register method_result,
967 Register scan_temp,
968 Label& no_such_interface,
969 bool return_method = true);
970
971 void lookup_interface_method_stub(Register recv_klass,
972 Register holder_klass,
973 Register resolved_klass,
974 Register method_result,
975 Register temp_reg,
976 Register temp_reg2,
977 int itable_index,
978 Label& L_no_such_interface);
979
980 // virtual method calling
981 // n.b. x86 allows RegisterOrConstant for vtable_index
1400 } \
1401 \
1402 void INSN(Register Rd, Register Rn, Register Rm) { \
1403 Assembler::INSN(Rd, Rn, Rm); \
1404 } \
1405 \
1406 void INSN(Register Rd, Register Rn, Register Rm, \
1407 ext::operation option, int amount = 0) { \
1408 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1409 }
1410
1411 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1412
1413 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1414 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1415 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1416 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1417
1418 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1419
1420 void tableswitch(Register index, jint lowbound, jint highbound,
1421 Label &jumptable, Label &jumptable_end, int stride = 1) {
1422 adr(rscratch1, jumptable);
1423 subsw(rscratch2, index, lowbound);
1424 subsw(zr, rscratch2, highbound - lowbound);
1425 br(Assembler::HS, jumptable_end);
1426 add(rscratch1, rscratch1, rscratch2,
1427 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1428 br(rscratch1);
1429 }
1430
1431 // Form an address from base + offset in Rd. Rd may or may not
1432 // actually be used: you must use the Address that is returned. It
1433 // is up to you to ensure that the shift provided matches the size
1434 // of your data.
1435 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1436
1437 // Return true iff an address is within the 48-bit AArch64 address
1438 // space.
1439 bool is_valid_AArch64_address(address a) {
1481 #define ARRAYS_HASHCODE_REGISTERS \
1482 do { \
1483 assert(result == r0 && \
1484 ary == r1 && \
1485 cnt == r2 && \
1486 vdata0 == v3 && \
1487 vdata1 == v2 && \
1488 vdata2 == v1 && \
1489 vdata3 == v0 && \
1490 vmul0 == v4 && \
1491 vmul1 == v5 && \
1492 vmul2 == v6 && \
1493 vmul3 == v7 && \
1494 vpow == v12 && \
1495 vpowm == v13, "registers must match aarch64.ad"); \
1496 } while (0)
1497
1498 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1499
1500 void fill_words(Register base, Register cnt, Register value);
1501 address zero_words(Register base, uint64_t cnt);
1502 address zero_words(Register ptr, Register cnt);
1503 void zero_dcache_blocks(Register base, Register cnt);
1504
1505 static const int zero_words_block_size;
1506
1507 address byte_array_inflate(Register src, Register dst, Register len,
1508 FloatRegister vtmp1, FloatRegister vtmp2,
1509 FloatRegister vtmp3, Register tmp4);
1510
1511 void char_array_compress(Register src, Register dst, Register len,
1512 Register res,
1513 FloatRegister vtmp0, FloatRegister vtmp1,
1514 FloatRegister vtmp2, FloatRegister vtmp3,
1515 FloatRegister vtmp4, FloatRegister vtmp5);
1516
1517 void encode_iso_array(Register src, Register dst,
1518 Register len, Register res, bool ascii,
1519 FloatRegister vtmp0, FloatRegister vtmp1,
1520 FloatRegister vtmp2, FloatRegister vtmp3,
|
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "oops/compressedKlass.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/macros.hpp"
36 #include "utilities/powerOfTwo.hpp"
37 #include "runtime/signature.hpp"
38
39
40 class ciInlineKlass;
41
42 class OopMap;
43
44 // MacroAssembler extends Assembler by frequently used macros.
45 //
46 // Instructions for which a 'better' code sequence exists depending
47 // on arguments should also go in here.
48
49 class MacroAssembler: public Assembler {
50 friend class LIR_Assembler;
51
52 public:
53 using Assembler::mov;
54 using Assembler::movi;
55
56 protected:
57
58 // Support for VM calls
59 //
60 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
626 msr(0b011, 0b0100, 0b0010, 0b000, reg);
627 }
628
629 // idiv variant which deals with MINLONG as dividend and -1 as divisor
630 int corrected_idivl(Register result, Register ra, Register rb,
631 bool want_remainder, Register tmp = rscratch1);
632 int corrected_idivq(Register result, Register ra, Register rb,
633 bool want_remainder, Register tmp = rscratch1);
634
635 // Support for null-checks
636 //
637 // Generates code that causes a null OS exception if the content of reg is null.
638 // If the accessed location is M[reg + offset] and the offset is known, provide the
639 // offset. No explicit code generation is needed if the offset is within a certain
640 // range (0 <= offset <= page_size).
641
642 virtual void null_check(Register reg, int offset = -1);
643 static bool needs_explicit_null_check(intptr_t offset);
644 static bool uses_implicit_null_check(void* address);
645
646 // markWord tests, kills markWord reg
647 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
648
649 // inlineKlass queries, kills temp_reg
650 void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type);
651 void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type);
652 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type);
653
654 // Get the default value oop for the given InlineKlass
655 void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj);
656 // The empty value oop, for the given InlineKlass ("empty" as in no instance fields)
657 // get_default_value_oop with extra assertion for empty inline klass
658 void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj);
659
660 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
661 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
662 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
663 void test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker);
664
665 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
666 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
667 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
668 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
669 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
670 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
671
672 // Check array klass layout helper for flat or null-free arrays...
673 void test_flat_array_layout(Register lh, Label& is_flat_array);
674 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array);
675
676 static address target_addr_for_insn(address insn_addr, unsigned insn);
677 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
678 static address target_addr_for_insn(address insn_addr) {
679 unsigned insn = *(unsigned*)insn_addr;
680 return target_addr_for_insn(insn_addr, insn);
681 }
682 static address target_addr_for_insn_or_null(address insn_addr) {
683 unsigned insn = *(unsigned*)insn_addr;
684 return target_addr_for_insn_or_null(insn_addr, insn);
685 }
686
687 // Required platform-specific helpers for Label::patch_instructions.
688 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
689 static int pd_patch_instruction_size(address branch, address target);
690 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
691 pd_patch_instruction_size(branch, target);
692 }
693 static address pd_call_destination(address branch) {
694 return target_addr_for_insn(branch);
695 }
893
894 void reset_last_Java_frame(Register thread);
895
896 // thread in the default location (rthread)
897 void reset_last_Java_frame(bool clear_fp);
898
899 // Stores
900 void store_check(Register obj); // store check for obj - register is destroyed afterwards
901 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
902
903 void resolve_jobject(Register value, Register tmp1, Register tmp2);
904 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
905
906 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
907 void c2bool(Register x);
908
909 void load_method_holder_cld(Register rresult, Register rmethod);
910 void load_method_holder(Register holder, Register method);
911
912 // oop manipulations
913 void load_metadata(Register dst, Register src);
914
915 void load_klass(Register dst, Register src);
916 void store_klass(Register dst, Register src);
917 void cmp_klass(Register oop, Register trial_klass, Register tmp);
918
919 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
920 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
921 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
922
923 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
924 Register tmp1, Register tmp2);
925
926 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
927 Register tmp1, Register tmp2, Register tmp3);
928
929 void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass);
930 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
931
932 // inline type data payload offsets...
933 void first_field_offset(Register inline_klass, Register offset);
934 void data_for_oop(Register oop, Register data, Register inline_klass);
935 // get data payload ptr a flat value array at index, kills rcx and index
936 void data_for_value_array_index(Register array, Register array_klass,
937 Register index, Register data);
938
939 void load_heap_oop(Register dst, Address src, Register tmp1,
940 Register tmp2, DecoratorSet decorators = 0);
941
942 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
943 Register tmp2, DecoratorSet decorators = 0);
944 void store_heap_oop(Address dst, Register val, Register tmp1,
945 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
946
947 // currently unimplemented
948 // Used for storing null. All other oop constants should be
949 // stored using routines that take a jobject.
950 void store_heap_oop_null(Address dst);
951
952 void load_prototype_header(Register dst, Register src);
953
954 void store_klass_gap(Register dst, Register src);
955
956 // This dummy is to prevent a call to store_heap_oop from
957 // converting a zero (like null) into a Register by giving
958 // the compiler two choices it can't resolve
959
960 void store_heap_oop(Address dst, void* dummy);
961
962 void encode_heap_oop(Register d, Register s);
963 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
964 void decode_heap_oop(Register d, Register s);
965 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
966 void encode_heap_oop_not_null(Register r);
967 void decode_heap_oop_not_null(Register r);
968 void encode_heap_oop_not_null(Register dst, Register src);
969 void decode_heap_oop_not_null(Register dst, Register src);
970
971 void set_narrow_oop(Register dst, jobject obj);
972
973 void encode_klass_not_null(Register r);
981 void reinit_heapbase();
982
983 DEBUG_ONLY(void verify_heapbase(const char* msg);)
984
985 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
986 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
987 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
988 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
989
990 void push_cont_fastpath(Register java_thread);
991 void pop_cont_fastpath(Register java_thread);
992
993 // Round up to a power of two
994 void round_to(Register reg, int modulus);
995
996 // java.lang.Math::round intrinsics
997 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
998 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
999
1000 // allocation
1001
1002 // Object / value buffer allocation...
1003 // Allocate instance of klass, assumes klass initialized by caller
1004 // new_obj prefers to be rax
1005 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
1006 void allocate_instance(Register klass, Register new_obj,
1007 Register t1, Register t2,
1008 bool clear_fields, Label& alloc_failed);
1009
1010 void tlab_allocate(
1011 Register obj, // result: pointer to object after successful allocation
1012 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1013 int con_size_in_bytes, // object size in bytes if known at compile time
1014 Register t1, // temp register
1015 Register t2, // temp register
1016 Label& slow_case // continuation point if fast allocation fails
1017 );
1018 void verify_tlab();
1019
1020 // For field "index" within "klass", return inline_klass ...
1021 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
1022 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
1023
1024
1025 // interface method calling
1026 void lookup_interface_method(Register recv_klass,
1027 Register intf_klass,
1028 RegisterOrConstant itable_index,
1029 Register method_result,
1030 Register scan_temp,
1031 Label& no_such_interface,
1032 bool return_method = true);
1033
1034 void lookup_interface_method_stub(Register recv_klass,
1035 Register holder_klass,
1036 Register resolved_klass,
1037 Register method_result,
1038 Register temp_reg,
1039 Register temp_reg2,
1040 int itable_index,
1041 Label& L_no_such_interface);
1042
1043 // virtual method calling
1044 // n.b. x86 allows RegisterOrConstant for vtable_index
1463 } \
1464 \
1465 void INSN(Register Rd, Register Rn, Register Rm) { \
1466 Assembler::INSN(Rd, Rn, Rm); \
1467 } \
1468 \
1469 void INSN(Register Rd, Register Rn, Register Rm, \
1470 ext::operation option, int amount = 0) { \
1471 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1472 }
1473
1474 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1475
1476 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1477 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1478 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1479 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1480
1481 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1482
1483 void verified_entry(Compile* C, int sp_inc);
1484
1485 // Inline type specific methods
1486 #include "asm/macroAssembler_common.hpp"
1487
1488 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1489 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1490 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1491 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1492 RegState reg_state[]);
1493 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1494 VMRegPair* from, int from_count, int& from_index, VMReg to,
1495 RegState reg_state[], Register val_array);
1496 int extend_stack_for_inline_args(int args_on_stack);
1497 void remove_frame(int initial_framesize, bool needs_stack_repair);
1498 VMReg spill_reg_for(VMReg reg);
1499 void save_stack_increment(int sp_inc, int frame_size);
1500
1501 void tableswitch(Register index, jint lowbound, jint highbound,
1502 Label &jumptable, Label &jumptable_end, int stride = 1) {
1503 adr(rscratch1, jumptable);
1504 subsw(rscratch2, index, lowbound);
1505 subsw(zr, rscratch2, highbound - lowbound);
1506 br(Assembler::HS, jumptable_end);
1507 add(rscratch1, rscratch1, rscratch2,
1508 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1509 br(rscratch1);
1510 }
1511
1512 // Form an address from base + offset in Rd. Rd may or may not
1513 // actually be used: you must use the Address that is returned. It
1514 // is up to you to ensure that the shift provided matches the size
1515 // of your data.
1516 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1517
1518 // Return true iff an address is within the 48-bit AArch64 address
1519 // space.
1520 bool is_valid_AArch64_address(address a) {
1562 #define ARRAYS_HASHCODE_REGISTERS \
1563 do { \
1564 assert(result == r0 && \
1565 ary == r1 && \
1566 cnt == r2 && \
1567 vdata0 == v3 && \
1568 vdata1 == v2 && \
1569 vdata2 == v1 && \
1570 vdata3 == v0 && \
1571 vmul0 == v4 && \
1572 vmul1 == v5 && \
1573 vmul2 == v6 && \
1574 vmul3 == v7 && \
1575 vpow == v12 && \
1576 vpowm == v13, "registers must match aarch64.ad"); \
1577 } while (0)
1578
1579 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1580
1581 void fill_words(Register base, Register cnt, Register value);
1582 void fill_words(Register base, uint64_t cnt, Register value);
1583
1584 address zero_words(Register base, uint64_t cnt);
1585 address zero_words(Register ptr, Register cnt);
1586 void zero_dcache_blocks(Register base, Register cnt);
1587
1588 static const int zero_words_block_size;
1589
1590 address byte_array_inflate(Register src, Register dst, Register len,
1591 FloatRegister vtmp1, FloatRegister vtmp2,
1592 FloatRegister vtmp3, Register tmp4);
1593
1594 void char_array_compress(Register src, Register dst, Register len,
1595 Register res,
1596 FloatRegister vtmp0, FloatRegister vtmp1,
1597 FloatRegister vtmp2, FloatRegister vtmp3,
1598 FloatRegister vtmp4, FloatRegister vtmp5);
1599
1600 void encode_iso_array(Register src, Register dst,
1601 Register len, Register res, bool ascii,
1602 FloatRegister vtmp0, FloatRegister vtmp1,
1603 FloatRegister vtmp2, FloatRegister vtmp3,
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