15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "oops/compressedKlass.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/powerOfTwo.hpp"
36
37 class OopMap;
38
39 // MacroAssembler extends Assembler by frequently used macros.
40 //
41 // Instructions for which a 'better' code sequence exists depending
42 // on arguments should also go in here.
43
44 class MacroAssembler: public Assembler {
45 friend class LIR_Assembler;
46
47 public:
48 using Assembler::mov;
49 using Assembler::movi;
50
51 protected:
52
53 // Support for VM calls
54 //
55 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
597 msr(0b011, 0b0100, 0b0010, 0b000, reg);
598 }
599
600 // idiv variant which deals with MINLONG as dividend and -1 as divisor
601 int corrected_idivl(Register result, Register ra, Register rb,
602 bool want_remainder, Register tmp = rscratch1);
603 int corrected_idivq(Register result, Register ra, Register rb,
604 bool want_remainder, Register tmp = rscratch1);
605
606 // Support for null-checks
607 //
608 // Generates code that causes a null OS exception if the content of reg is null.
609 // If the accessed location is M[reg + offset] and the offset is known, provide the
610 // offset. No explicit code generation is needed if the offset is within a certain
611 // range (0 <= offset <= page_size).
612
613 virtual void null_check(Register reg, int offset = -1);
614 static bool needs_explicit_null_check(intptr_t offset);
615 static bool uses_implicit_null_check(void* address);
616
617 static address target_addr_for_insn(address insn_addr, unsigned insn);
618 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
619 static address target_addr_for_insn(address insn_addr) {
620 unsigned insn = *(unsigned*)insn_addr;
621 return target_addr_for_insn(insn_addr, insn);
622 }
623 static address target_addr_for_insn_or_null(address insn_addr) {
624 unsigned insn = *(unsigned*)insn_addr;
625 return target_addr_for_insn_or_null(insn_addr, insn);
626 }
627
628 // Required platform-specific helpers for Label::patch_instructions.
629 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
630 static int pd_patch_instruction_size(address branch, address target);
631 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
632 pd_patch_instruction_size(branch, target);
633 }
634 static address pd_call_destination(address branch) {
635 return target_addr_for_insn(branch);
636 }
833
834 void reset_last_Java_frame(Register thread);
835
836 // thread in the default location (rthread)
837 void reset_last_Java_frame(bool clear_fp);
838
839 // Stores
840 void store_check(Register obj); // store check for obj - register is destroyed afterwards
841 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
842
843 void resolve_jobject(Register value, Register tmp1, Register tmp2);
844 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
845
846 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
847 void c2bool(Register x);
848
849 void load_method_holder_cld(Register rresult, Register rmethod);
850 void load_method_holder(Register holder, Register method);
851
852 // oop manipulations
853 void load_klass(Register dst, Register src);
854 void store_klass(Register dst, Register src);
855 void cmp_klass(Register oop, Register trial_klass, Register tmp);
856
857 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
858 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
859 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
860
861 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
862 Register tmp1, Register tmp2);
863
864 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
865 Register tmp1, Register tmp2, Register tmp3);
866
867 void load_heap_oop(Register dst, Address src, Register tmp1,
868 Register tmp2, DecoratorSet decorators = 0);
869
870 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
871 Register tmp2, DecoratorSet decorators = 0);
872 void store_heap_oop(Address dst, Register val, Register tmp1,
873 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
874
875 // currently unimplemented
876 // Used for storing null. All other oop constants should be
877 // stored using routines that take a jobject.
878 void store_heap_oop_null(Address dst);
879
880 void store_klass_gap(Register dst, Register src);
881
882 // This dummy is to prevent a call to store_heap_oop from
883 // converting a zero (like null) into a Register by giving
884 // the compiler two choices it can't resolve
885
886 void store_heap_oop(Address dst, void* dummy);
887
888 void encode_heap_oop(Register d, Register s);
889 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
890 void decode_heap_oop(Register d, Register s);
891 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
892 void encode_heap_oop_not_null(Register r);
893 void decode_heap_oop_not_null(Register r);
894 void encode_heap_oop_not_null(Register dst, Register src);
895 void decode_heap_oop_not_null(Register dst, Register src);
896
897 void set_narrow_oop(Register dst, jobject obj);
898
899 void encode_klass_not_null(Register r);
907 void reinit_heapbase();
908
909 DEBUG_ONLY(void verify_heapbase(const char* msg);)
910
911 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
912 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
913 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
914 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
915
916 void push_cont_fastpath(Register java_thread);
917 void pop_cont_fastpath(Register java_thread);
918
919 // Round up to a power of two
920 void round_to(Register reg, int modulus);
921
922 // java.lang.Math::round intrinsics
923 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
924 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
925
926 // allocation
927 void tlab_allocate(
928 Register obj, // result: pointer to object after successful allocation
929 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
930 int con_size_in_bytes, // object size in bytes if known at compile time
931 Register t1, // temp register
932 Register t2, // temp register
933 Label& slow_case // continuation point if fast allocation fails
934 );
935 void verify_tlab();
936
937 // interface method calling
938 void lookup_interface_method(Register recv_klass,
939 Register intf_klass,
940 RegisterOrConstant itable_index,
941 Register method_result,
942 Register scan_temp,
943 Label& no_such_interface,
944 bool return_method = true);
945
946 // virtual method calling
947 // n.b. x86 allows RegisterOrConstant for vtable_index
948 void lookup_virtual_method(Register recv_klass,
949 RegisterOrConstant vtable_index,
950 Register method_result);
951
952 // Test sub_klass against super_klass, with fast and slow paths.
953
954 // The fast path produces a tri-state answer: yes / no / maybe-slow.
955 // One of the three labels can be null, meaning take the fall-through.
956 // If super_check_offset is -1, the value is loaded up from super_klass.
1300 } \
1301 \
1302 void INSN(Register Rd, Register Rn, Register Rm) { \
1303 Assembler::INSN(Rd, Rn, Rm); \
1304 } \
1305 \
1306 void INSN(Register Rd, Register Rn, Register Rm, \
1307 ext::operation option, int amount = 0) { \
1308 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1309 }
1310
1311 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1312
1313 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1314 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1315 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1316 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1317
1318 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1319
1320 void tableswitch(Register index, jint lowbound, jint highbound,
1321 Label &jumptable, Label &jumptable_end, int stride = 1) {
1322 adr(rscratch1, jumptable);
1323 subsw(rscratch2, index, lowbound);
1324 subsw(zr, rscratch2, highbound - lowbound);
1325 br(Assembler::HS, jumptable_end);
1326 add(rscratch1, rscratch1, rscratch2,
1327 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1328 br(rscratch1);
1329 }
1330
1331 // Form an address from base + offset in Rd. Rd may or may not
1332 // actually be used: you must use the Address that is returned. It
1333 // is up to you to ensure that the shift provided matches the size
1334 // of your data.
1335 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1336
1337 // Return true iff an address is within the 48-bit AArch64 address
1338 // space.
1339 bool is_valid_AArch64_address(address a) {
1364 }
1365
1366 address read_polling_page(Register r, relocInfo::relocType rtype);
1367 void get_polling_page(Register dest, relocInfo::relocType rtype);
1368
1369 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1370 void update_byte_crc32(Register crc, Register val, Register table);
1371 void update_word_crc32(Register crc, Register v, Register tmp,
1372 Register table0, Register table1, Register table2, Register table3,
1373 bool upper = false);
1374
1375 address count_positives(Register ary1, Register len, Register result);
1376
1377 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1378 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1379
1380 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1381 int elem_size);
1382
1383 void fill_words(Register base, Register cnt, Register value);
1384 address zero_words(Register base, uint64_t cnt);
1385 address zero_words(Register ptr, Register cnt);
1386 void zero_dcache_blocks(Register base, Register cnt);
1387
1388 static const int zero_words_block_size;
1389
1390 address byte_array_inflate(Register src, Register dst, Register len,
1391 FloatRegister vtmp1, FloatRegister vtmp2,
1392 FloatRegister vtmp3, Register tmp4);
1393
1394 void char_array_compress(Register src, Register dst, Register len,
1395 Register res,
1396 FloatRegister vtmp0, FloatRegister vtmp1,
1397 FloatRegister vtmp2, FloatRegister vtmp3,
1398 FloatRegister vtmp4, FloatRegister vtmp5);
1399
1400 void encode_iso_array(Register src, Register dst,
1401 Register len, Register res, bool ascii,
1402 FloatRegister vtmp0, FloatRegister vtmp1,
1403 FloatRegister vtmp2, FloatRegister vtmp3,
|
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "oops/compressedKlass.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/macros.hpp"
36 #include "utilities/powerOfTwo.hpp"
37 #include "runtime/signature.hpp"
38
39
40 class ciInlineKlass;
41
42 class OopMap;
43
44 // MacroAssembler extends Assembler by frequently used macros.
45 //
46 // Instructions for which a 'better' code sequence exists depending
47 // on arguments should also go in here.
48
49 class MacroAssembler: public Assembler {
50 friend class LIR_Assembler;
51
52 public:
53 using Assembler::mov;
54 using Assembler::movi;
55
56 protected:
57
58 // Support for VM calls
59 //
60 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
602 msr(0b011, 0b0100, 0b0010, 0b000, reg);
603 }
604
605 // idiv variant which deals with MINLONG as dividend and -1 as divisor
606 int corrected_idivl(Register result, Register ra, Register rb,
607 bool want_remainder, Register tmp = rscratch1);
608 int corrected_idivq(Register result, Register ra, Register rb,
609 bool want_remainder, Register tmp = rscratch1);
610
611 // Support for null-checks
612 //
613 // Generates code that causes a null OS exception if the content of reg is null.
614 // If the accessed location is M[reg + offset] and the offset is known, provide the
615 // offset. No explicit code generation is needed if the offset is within a certain
616 // range (0 <= offset <= page_size).
617
618 virtual void null_check(Register reg, int offset = -1);
619 static bool needs_explicit_null_check(intptr_t offset);
620 static bool uses_implicit_null_check(void* address);
621
622 // markWord tests, kills markWord reg
623 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
624
625 // inlineKlass queries, kills temp_reg
626 void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type);
627 void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type);
628 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type);
629
630 // Get the default value oop for the given InlineKlass
631 void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj);
632 // The empty value oop, for the given InlineKlass ("empty" as in no instance fields)
633 // get_default_value_oop with extra assertion for empty inline klass
634 void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj);
635
636 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
637 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
638 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
639
640 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
641 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
642 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
643 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
644 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
645 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
646
647 // Check array klass layout helper for flat or null-free arrays...
648 void test_flat_array_layout(Register lh, Label& is_flat_array);
649 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array);
650 void test_null_free_array_layout(Register lh, Label& is_null_free_array);
651 void test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array);
652
653 static address target_addr_for_insn(address insn_addr, unsigned insn);
654 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
655 static address target_addr_for_insn(address insn_addr) {
656 unsigned insn = *(unsigned*)insn_addr;
657 return target_addr_for_insn(insn_addr, insn);
658 }
659 static address target_addr_for_insn_or_null(address insn_addr) {
660 unsigned insn = *(unsigned*)insn_addr;
661 return target_addr_for_insn_or_null(insn_addr, insn);
662 }
663
664 // Required platform-specific helpers for Label::patch_instructions.
665 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
666 static int pd_patch_instruction_size(address branch, address target);
667 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
668 pd_patch_instruction_size(branch, target);
669 }
670 static address pd_call_destination(address branch) {
671 return target_addr_for_insn(branch);
672 }
869
870 void reset_last_Java_frame(Register thread);
871
872 // thread in the default location (rthread)
873 void reset_last_Java_frame(bool clear_fp);
874
875 // Stores
876 void store_check(Register obj); // store check for obj - register is destroyed afterwards
877 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
878
879 void resolve_jobject(Register value, Register tmp1, Register tmp2);
880 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
881
882 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
883 void c2bool(Register x);
884
885 void load_method_holder_cld(Register rresult, Register rmethod);
886 void load_method_holder(Register holder, Register method);
887
888 // oop manipulations
889 void load_metadata(Register dst, Register src);
890
891 void load_klass(Register dst, Register src);
892 void store_klass(Register dst, Register src);
893 void cmp_klass(Register oop, Register trial_klass, Register tmp);
894
895 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
896 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
897 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
898
899 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
900 Register tmp1, Register tmp2);
901
902 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
903 Register tmp1, Register tmp2, Register tmp3);
904
905 void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass);
906
907 // inline type data payload offsets...
908 void first_field_offset(Register inline_klass, Register offset);
909 void data_for_oop(Register oop, Register data, Register inline_klass);
910 // get data payload ptr a flat value array at index, kills rcx and index
911 void data_for_value_array_index(Register array, Register array_klass,
912 Register index, Register data);
913
914 void load_heap_oop(Register dst, Address src, Register tmp1,
915 Register tmp2, DecoratorSet decorators = 0);
916
917 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
918 Register tmp2, DecoratorSet decorators = 0);
919 void store_heap_oop(Address dst, Register val, Register tmp1,
920 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
921
922 // currently unimplemented
923 // Used for storing null. All other oop constants should be
924 // stored using routines that take a jobject.
925 void store_heap_oop_null(Address dst);
926
927 void load_prototype_header(Register dst, Register src);
928
929 void store_klass_gap(Register dst, Register src);
930
931 // This dummy is to prevent a call to store_heap_oop from
932 // converting a zero (like null) into a Register by giving
933 // the compiler two choices it can't resolve
934
935 void store_heap_oop(Address dst, void* dummy);
936
937 void encode_heap_oop(Register d, Register s);
938 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
939 void decode_heap_oop(Register d, Register s);
940 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
941 void encode_heap_oop_not_null(Register r);
942 void decode_heap_oop_not_null(Register r);
943 void encode_heap_oop_not_null(Register dst, Register src);
944 void decode_heap_oop_not_null(Register dst, Register src);
945
946 void set_narrow_oop(Register dst, jobject obj);
947
948 void encode_klass_not_null(Register r);
956 void reinit_heapbase();
957
958 DEBUG_ONLY(void verify_heapbase(const char* msg);)
959
960 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
961 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
962 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
963 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
964
965 void push_cont_fastpath(Register java_thread);
966 void pop_cont_fastpath(Register java_thread);
967
968 // Round up to a power of two
969 void round_to(Register reg, int modulus);
970
971 // java.lang.Math::round intrinsics
972 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
973 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
974
975 // allocation
976
977 // Object / value buffer allocation...
978 // Allocate instance of klass, assumes klass initialized by caller
979 // new_obj prefers to be rax
980 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
981 void allocate_instance(Register klass, Register new_obj,
982 Register t1, Register t2,
983 bool clear_fields, Label& alloc_failed);
984
985 void tlab_allocate(
986 Register obj, // result: pointer to object after successful allocation
987 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
988 int con_size_in_bytes, // object size in bytes if known at compile time
989 Register t1, // temp register
990 Register t2, // temp register
991 Label& slow_case // continuation point if fast allocation fails
992 );
993 void verify_tlab();
994
995 // For field "index" within "klass", return inline_klass ...
996 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
997
998 // interface method calling
999 void lookup_interface_method(Register recv_klass,
1000 Register intf_klass,
1001 RegisterOrConstant itable_index,
1002 Register method_result,
1003 Register scan_temp,
1004 Label& no_such_interface,
1005 bool return_method = true);
1006
1007 // virtual method calling
1008 // n.b. x86 allows RegisterOrConstant for vtable_index
1009 void lookup_virtual_method(Register recv_klass,
1010 RegisterOrConstant vtable_index,
1011 Register method_result);
1012
1013 // Test sub_klass against super_klass, with fast and slow paths.
1014
1015 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1016 // One of the three labels can be null, meaning take the fall-through.
1017 // If super_check_offset is -1, the value is loaded up from super_klass.
1361 } \
1362 \
1363 void INSN(Register Rd, Register Rn, Register Rm) { \
1364 Assembler::INSN(Rd, Rn, Rm); \
1365 } \
1366 \
1367 void INSN(Register Rd, Register Rn, Register Rm, \
1368 ext::operation option, int amount = 0) { \
1369 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1370 }
1371
1372 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1373
1374 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1375 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1376 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1377 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1378
1379 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1380
1381 void verified_entry(Compile* C, int sp_inc);
1382
1383 // Inline type specific methods
1384 #include "asm/macroAssembler_common.hpp"
1385
1386 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1387 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1388 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1389 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1390 RegState reg_state[]);
1391 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1392 VMRegPair* from, int from_count, int& from_index, VMReg to,
1393 RegState reg_state[], Register val_array);
1394 int extend_stack_for_inline_args(int args_on_stack);
1395 void remove_frame(int initial_framesize, bool needs_stack_repair);
1396 VMReg spill_reg_for(VMReg reg);
1397 void save_stack_increment(int sp_inc, int frame_size);
1398
1399 void tableswitch(Register index, jint lowbound, jint highbound,
1400 Label &jumptable, Label &jumptable_end, int stride = 1) {
1401 adr(rscratch1, jumptable);
1402 subsw(rscratch2, index, lowbound);
1403 subsw(zr, rscratch2, highbound - lowbound);
1404 br(Assembler::HS, jumptable_end);
1405 add(rscratch1, rscratch1, rscratch2,
1406 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1407 br(rscratch1);
1408 }
1409
1410 // Form an address from base + offset in Rd. Rd may or may not
1411 // actually be used: you must use the Address that is returned. It
1412 // is up to you to ensure that the shift provided matches the size
1413 // of your data.
1414 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1415
1416 // Return true iff an address is within the 48-bit AArch64 address
1417 // space.
1418 bool is_valid_AArch64_address(address a) {
1443 }
1444
1445 address read_polling_page(Register r, relocInfo::relocType rtype);
1446 void get_polling_page(Register dest, relocInfo::relocType rtype);
1447
1448 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1449 void update_byte_crc32(Register crc, Register val, Register table);
1450 void update_word_crc32(Register crc, Register v, Register tmp,
1451 Register table0, Register table1, Register table2, Register table3,
1452 bool upper = false);
1453
1454 address count_positives(Register ary1, Register len, Register result);
1455
1456 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1457 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1458
1459 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1460 int elem_size);
1461
1462 void fill_words(Register base, Register cnt, Register value);
1463 void fill_words(Register base, uint64_t cnt, Register value);
1464
1465 address zero_words(Register base, uint64_t cnt);
1466 address zero_words(Register ptr, Register cnt);
1467 void zero_dcache_blocks(Register base, Register cnt);
1468
1469 static const int zero_words_block_size;
1470
1471 address byte_array_inflate(Register src, Register dst, Register len,
1472 FloatRegister vtmp1, FloatRegister vtmp2,
1473 FloatRegister vtmp3, Register tmp4);
1474
1475 void char_array_compress(Register src, Register dst, Register len,
1476 Register res,
1477 FloatRegister vtmp0, FloatRegister vtmp1,
1478 FloatRegister vtmp2, FloatRegister vtmp3,
1479 FloatRegister vtmp4, FloatRegister vtmp5);
1480
1481 void encode_iso_array(Register src, Register dst,
1482 Register len, Register res, bool ascii,
1483 FloatRegister vtmp0, FloatRegister vtmp1,
1484 FloatRegister vtmp2, FloatRegister vtmp3,
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