16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/powerOfTwo.hpp"
37
38 class OopMap;
39
40 // MacroAssembler extends Assembler by frequently used macros.
41 //
42 // Instructions for which a 'better' code sequence exists depending
43 // on arguments should also go in here.
44
45 class MacroAssembler: public Assembler {
46 friend class LIR_Assembler;
47
48 public:
49 using Assembler::mov;
50 using Assembler::movi;
51
52 protected:
53
54 // Support for VM calls
55 //
56 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
633 msr(0b011, 0b0100, 0b0010, 0b000, reg);
634 }
635
636 // idiv variant which deals with MINLONG as dividend and -1 as divisor
637 int corrected_idivl(Register result, Register ra, Register rb,
638 bool want_remainder, Register tmp = rscratch1);
639 int corrected_idivq(Register result, Register ra, Register rb,
640 bool want_remainder, Register tmp = rscratch1);
641
642 // Support for null-checks
643 //
644 // Generates code that causes a null OS exception if the content of reg is null.
645 // If the accessed location is M[reg + offset] and the offset is known, provide the
646 // offset. No explicit code generation is needed if the offset is within a certain
647 // range (0 <= offset <= page_size).
648
649 virtual void null_check(Register reg, int offset = -1);
650 static bool needs_explicit_null_check(intptr_t offset);
651 static bool uses_implicit_null_check(void* address);
652
653 static address target_addr_for_insn(address insn_addr, unsigned insn);
654 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
655 static address target_addr_for_insn(address insn_addr) {
656 unsigned insn = *(unsigned*)insn_addr;
657 return target_addr_for_insn(insn_addr, insn);
658 }
659 static address target_addr_for_insn_or_null(address insn_addr) {
660 unsigned insn = *(unsigned*)insn_addr;
661 return target_addr_for_insn_or_null(insn_addr, insn);
662 }
663
664 // Required platform-specific helpers for Label::patch_instructions.
665 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
666 static int pd_patch_instruction_size(address branch, address target);
667 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
668 pd_patch_instruction_size(branch, target);
669 }
670 static address pd_call_destination(address branch) {
671 return target_addr_for_insn(branch);
672 }
870
871 void reset_last_Java_frame(Register thread);
872
873 // thread in the default location (rthread)
874 void reset_last_Java_frame(bool clear_fp);
875
876 // Stores
877 void store_check(Register obj); // store check for obj - register is destroyed afterwards
878 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
879
880 void resolve_jobject(Register value, Register tmp1, Register tmp2);
881 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
882
883 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
884 void c2bool(Register x);
885
886 void load_method_holder_cld(Register rresult, Register rmethod);
887 void load_method_holder(Register holder, Register method);
888
889 // oop manipulations
890 void load_narrow_klass_compact(Register dst, Register src);
891 void load_klass(Register dst, Register src);
892 void store_klass(Register dst, Register src);
893 void cmp_klass(Register obj, Register klass, Register tmp);
894 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
895
896 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
897 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
898 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
899
900 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
901 Register tmp1, Register tmp2);
902
903 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
904 Register tmp1, Register tmp2, Register tmp3);
905
906 void load_heap_oop(Register dst, Address src, Register tmp1,
907 Register tmp2, DecoratorSet decorators = 0);
908
909 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
910 Register tmp2, DecoratorSet decorators = 0);
911 void store_heap_oop(Address dst, Register val, Register tmp1,
912 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
913
914 // currently unimplemented
915 // Used for storing null. All other oop constants should be
916 // stored using routines that take a jobject.
917 void store_heap_oop_null(Address dst);
918
919 void store_klass_gap(Register dst, Register src);
920
921 // This dummy is to prevent a call to store_heap_oop from
922 // converting a zero (like null) into a Register by giving
923 // the compiler two choices it can't resolve
924
925 void store_heap_oop(Address dst, void* dummy);
926
927 void encode_heap_oop(Register d, Register s);
928 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
929 void decode_heap_oop(Register d, Register s);
930 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
931 void encode_heap_oop_not_null(Register r);
932 void decode_heap_oop_not_null(Register r);
933 void encode_heap_oop_not_null(Register dst, Register src);
934 void decode_heap_oop_not_null(Register dst, Register src);
935
936 void set_narrow_oop(Register dst, jobject obj);
937
938 void decode_klass_not_null_for_aot(Register dst, Register src);
951
952 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
953 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
954 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
955 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
956
957 void push_cont_fastpath(Register java_thread = rthread);
958 void pop_cont_fastpath(Register java_thread = rthread);
959
960 void inc_held_monitor_count(Register tmp);
961 void dec_held_monitor_count(Register tmp);
962
963 // Round up to a power of two
964 void round_to(Register reg, int modulus);
965
966 // java.lang.Math::round intrinsics
967 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
968 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
969
970 // allocation
971 void tlab_allocate(
972 Register obj, // result: pointer to object after successful allocation
973 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
974 int con_size_in_bytes, // object size in bytes if known at compile time
975 Register t1, // temp register
976 Register t2, // temp register
977 Label& slow_case // continuation point if fast allocation fails
978 );
979 void verify_tlab();
980
981 // interface method calling
982 void lookup_interface_method(Register recv_klass,
983 Register intf_klass,
984 RegisterOrConstant itable_index,
985 Register method_result,
986 Register scan_temp,
987 Label& no_such_interface,
988 bool return_method = true);
989
990 void lookup_interface_method_stub(Register recv_klass,
991 Register holder_klass,
992 Register resolved_klass,
993 Register method_result,
994 Register temp_reg,
995 Register temp_reg2,
996 int itable_index,
997 Label& L_no_such_interface);
998
999 // virtual method calling
1000 // n.b. x86 allows RegisterOrConstant for vtable_index
1426 } \
1427 \
1428 void INSN(Register Rd, Register Rn, Register Rm) { \
1429 Assembler::INSN(Rd, Rn, Rm); \
1430 } \
1431 \
1432 void INSN(Register Rd, Register Rn, Register Rm, \
1433 ext::operation option, int amount = 0) { \
1434 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1435 }
1436
1437 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1438
1439 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1440 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1441 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1442 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1443
1444 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1445
1446 void tableswitch(Register index, jint lowbound, jint highbound,
1447 Label &jumptable, Label &jumptable_end, int stride = 1) {
1448 adr(rscratch1, jumptable);
1449 subsw(rscratch2, index, lowbound);
1450 subsw(zr, rscratch2, highbound - lowbound);
1451 br(Assembler::HS, jumptable_end);
1452 add(rscratch1, rscratch1, rscratch2,
1453 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1454 br(rscratch1);
1455 }
1456
1457 // Form an address from base + offset in Rd. Rd may or may not
1458 // actually be used: you must use the Address that is returned. It
1459 // is up to you to ensure that the shift provided matches the size
1460 // of your data.
1461 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1462
1463 // Return true iff an address is within the 48-bit AArch64 address
1464 // space.
1465 bool is_valid_AArch64_address(address a) {
1497 #define ARRAYS_HASHCODE_REGISTERS \
1498 do { \
1499 assert(result == r0 && \
1500 ary == r1 && \
1501 cnt == r2 && \
1502 vdata0 == v3 && \
1503 vdata1 == v2 && \
1504 vdata2 == v1 && \
1505 vdata3 == v0 && \
1506 vmul0 == v4 && \
1507 vmul1 == v5 && \
1508 vmul2 == v6 && \
1509 vmul3 == v7 && \
1510 vpow == v12 && \
1511 vpowm == v13, "registers must match aarch64.ad"); \
1512 } while (0)
1513
1514 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1515
1516 void fill_words(Register base, Register cnt, Register value);
1517 address zero_words(Register base, uint64_t cnt);
1518 address zero_words(Register ptr, Register cnt);
1519 void zero_dcache_blocks(Register base, Register cnt);
1520
1521 static const int zero_words_block_size;
1522
1523 address byte_array_inflate(Register src, Register dst, Register len,
1524 FloatRegister vtmp1, FloatRegister vtmp2,
1525 FloatRegister vtmp3, Register tmp4);
1526
1527 void char_array_compress(Register src, Register dst, Register len,
1528 Register res,
1529 FloatRegister vtmp0, FloatRegister vtmp1,
1530 FloatRegister vtmp2, FloatRegister vtmp3,
1531 FloatRegister vtmp4, FloatRegister vtmp5);
1532
1533 void encode_iso_array(Register src, Register dst,
1534 Register len, Register res, bool ascii,
1535 FloatRegister vtmp0, FloatRegister vtmp1,
1536 FloatRegister vtmp2, FloatRegister vtmp3,
|
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/macros.hpp"
37 #include "utilities/powerOfTwo.hpp"
38 #include "runtime/signature.hpp"
39
40
41 class ciInlineKlass;
42
43 class OopMap;
44
45 // MacroAssembler extends Assembler by frequently used macros.
46 //
47 // Instructions for which a 'better' code sequence exists depending
48 // on arguments should also go in here.
49
50 class MacroAssembler: public Assembler {
51 friend class LIR_Assembler;
52
53 public:
54 using Assembler::mov;
55 using Assembler::movi;
56
57 protected:
58
59 // Support for VM calls
60 //
61 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
638 msr(0b011, 0b0100, 0b0010, 0b000, reg);
639 }
640
641 // idiv variant which deals with MINLONG as dividend and -1 as divisor
642 int corrected_idivl(Register result, Register ra, Register rb,
643 bool want_remainder, Register tmp = rscratch1);
644 int corrected_idivq(Register result, Register ra, Register rb,
645 bool want_remainder, Register tmp = rscratch1);
646
647 // Support for null-checks
648 //
649 // Generates code that causes a null OS exception if the content of reg is null.
650 // If the accessed location is M[reg + offset] and the offset is known, provide the
651 // offset. No explicit code generation is needed if the offset is within a certain
652 // range (0 <= offset <= page_size).
653
654 virtual void null_check(Register reg, int offset = -1);
655 static bool needs_explicit_null_check(intptr_t offset);
656 static bool uses_implicit_null_check(void* address);
657
658 // markWord tests, kills markWord reg
659 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
660
661 // inlineKlass queries, kills temp_reg
662 void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type);
663 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
664
665 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
666 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
667 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
668 void test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker);
669
670 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
671 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
672 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
673 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
674 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
675 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
676
677 // Check array klass layout helper for flat or null-free arrays...
678 void test_flat_array_layout(Register lh, Label& is_flat_array);
679 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array);
680
681 static address target_addr_for_insn(address insn_addr, unsigned insn);
682 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
683 static address target_addr_for_insn(address insn_addr) {
684 unsigned insn = *(unsigned*)insn_addr;
685 return target_addr_for_insn(insn_addr, insn);
686 }
687 static address target_addr_for_insn_or_null(address insn_addr) {
688 unsigned insn = *(unsigned*)insn_addr;
689 return target_addr_for_insn_or_null(insn_addr, insn);
690 }
691
692 // Required platform-specific helpers for Label::patch_instructions.
693 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
694 static int pd_patch_instruction_size(address branch, address target);
695 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
696 pd_patch_instruction_size(branch, target);
697 }
698 static address pd_call_destination(address branch) {
699 return target_addr_for_insn(branch);
700 }
898
899 void reset_last_Java_frame(Register thread);
900
901 // thread in the default location (rthread)
902 void reset_last_Java_frame(bool clear_fp);
903
904 // Stores
905 void store_check(Register obj); // store check for obj - register is destroyed afterwards
906 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
907
908 void resolve_jobject(Register value, Register tmp1, Register tmp2);
909 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
910
911 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
912 void c2bool(Register x);
913
914 void load_method_holder_cld(Register rresult, Register rmethod);
915 void load_method_holder(Register holder, Register method);
916
917 // oop manipulations
918 void load_metadata(Register dst, Register src);
919
920 void load_narrow_klass_compact(Register dst, Register src);
921 void load_klass(Register dst, Register src);
922 void store_klass(Register dst, Register src);
923 void cmp_klass(Register obj, Register klass, Register tmp);
924 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
925
926 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
927 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
928 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
929
930 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
931 Register tmp1, Register tmp2);
932
933 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
934 Register tmp1, Register tmp2, Register tmp3);
935
936 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
937
938 // inline type data payload offsets...
939 void payload_offset(Register inline_klass, Register offset);
940 void payload_address(Register oop, Register data, Register inline_klass);
941 // get data payload ptr a flat value array at index, kills rcx and index
942 void data_for_value_array_index(Register array, Register array_klass,
943 Register index, Register data);
944
945 void load_heap_oop(Register dst, Address src, Register tmp1,
946 Register tmp2, DecoratorSet decorators = 0);
947
948 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
949 Register tmp2, DecoratorSet decorators = 0);
950 void store_heap_oop(Address dst, Register val, Register tmp1,
951 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
952
953 // currently unimplemented
954 // Used for storing null. All other oop constants should be
955 // stored using routines that take a jobject.
956 void store_heap_oop_null(Address dst);
957
958 void load_prototype_header(Register dst, Register src);
959
960 void store_klass_gap(Register dst, Register src);
961
962 // This dummy is to prevent a call to store_heap_oop from
963 // converting a zero (like null) into a Register by giving
964 // the compiler two choices it can't resolve
965
966 void store_heap_oop(Address dst, void* dummy);
967
968 void encode_heap_oop(Register d, Register s);
969 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
970 void decode_heap_oop(Register d, Register s);
971 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
972 void encode_heap_oop_not_null(Register r);
973 void decode_heap_oop_not_null(Register r);
974 void encode_heap_oop_not_null(Register dst, Register src);
975 void decode_heap_oop_not_null(Register dst, Register src);
976
977 void set_narrow_oop(Register dst, jobject obj);
978
979 void decode_klass_not_null_for_aot(Register dst, Register src);
992
993 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
994 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
995 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
996 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
997
998 void push_cont_fastpath(Register java_thread = rthread);
999 void pop_cont_fastpath(Register java_thread = rthread);
1000
1001 void inc_held_monitor_count(Register tmp);
1002 void dec_held_monitor_count(Register tmp);
1003
1004 // Round up to a power of two
1005 void round_to(Register reg, int modulus);
1006
1007 // java.lang.Math::round intrinsics
1008 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1009 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1010
1011 // allocation
1012
1013 // Object / value buffer allocation...
1014 // Allocate instance of klass, assumes klass initialized by caller
1015 // new_obj prefers to be rax
1016 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
1017 void allocate_instance(Register klass, Register new_obj,
1018 Register t1, Register t2,
1019 bool clear_fields, Label& alloc_failed);
1020
1021 void tlab_allocate(
1022 Register obj, // result: pointer to object after successful allocation
1023 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1024 int con_size_in_bytes, // object size in bytes if known at compile time
1025 Register t1, // temp register
1026 Register t2, // temp register
1027 Label& slow_case // continuation point if fast allocation fails
1028 );
1029 void verify_tlab();
1030
1031 // For field "index" within "klass", return inline_klass ...
1032 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
1033 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
1034
1035
1036 // interface method calling
1037 void lookup_interface_method(Register recv_klass,
1038 Register intf_klass,
1039 RegisterOrConstant itable_index,
1040 Register method_result,
1041 Register scan_temp,
1042 Label& no_such_interface,
1043 bool return_method = true);
1044
1045 void lookup_interface_method_stub(Register recv_klass,
1046 Register holder_klass,
1047 Register resolved_klass,
1048 Register method_result,
1049 Register temp_reg,
1050 Register temp_reg2,
1051 int itable_index,
1052 Label& L_no_such_interface);
1053
1054 // virtual method calling
1055 // n.b. x86 allows RegisterOrConstant for vtable_index
1481 } \
1482 \
1483 void INSN(Register Rd, Register Rn, Register Rm) { \
1484 Assembler::INSN(Rd, Rn, Rm); \
1485 } \
1486 \
1487 void INSN(Register Rd, Register Rn, Register Rm, \
1488 ext::operation option, int amount = 0) { \
1489 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1490 }
1491
1492 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1493
1494 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1495 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1496 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1497 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1498
1499 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1500
1501 void verified_entry(Compile* C, int sp_inc);
1502
1503 // Inline type specific methods
1504 #include "asm/macroAssembler_common.hpp"
1505
1506 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1507 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1508 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1509 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1510 RegState reg_state[]);
1511 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1512 VMRegPair* from, int from_count, int& from_index, VMReg to,
1513 RegState reg_state[], Register val_array);
1514 int extend_stack_for_inline_args(int args_on_stack);
1515 void remove_frame(int initial_framesize, bool needs_stack_repair);
1516 VMReg spill_reg_for(VMReg reg);
1517 void save_stack_increment(int sp_inc, int frame_size);
1518
1519 void tableswitch(Register index, jint lowbound, jint highbound,
1520 Label &jumptable, Label &jumptable_end, int stride = 1) {
1521 adr(rscratch1, jumptable);
1522 subsw(rscratch2, index, lowbound);
1523 subsw(zr, rscratch2, highbound - lowbound);
1524 br(Assembler::HS, jumptable_end);
1525 add(rscratch1, rscratch1, rscratch2,
1526 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1527 br(rscratch1);
1528 }
1529
1530 // Form an address from base + offset in Rd. Rd may or may not
1531 // actually be used: you must use the Address that is returned. It
1532 // is up to you to ensure that the shift provided matches the size
1533 // of your data.
1534 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1535
1536 // Return true iff an address is within the 48-bit AArch64 address
1537 // space.
1538 bool is_valid_AArch64_address(address a) {
1570 #define ARRAYS_HASHCODE_REGISTERS \
1571 do { \
1572 assert(result == r0 && \
1573 ary == r1 && \
1574 cnt == r2 && \
1575 vdata0 == v3 && \
1576 vdata1 == v2 && \
1577 vdata2 == v1 && \
1578 vdata3 == v0 && \
1579 vmul0 == v4 && \
1580 vmul1 == v5 && \
1581 vmul2 == v6 && \
1582 vmul3 == v7 && \
1583 vpow == v12 && \
1584 vpowm == v13, "registers must match aarch64.ad"); \
1585 } while (0)
1586
1587 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1588
1589 void fill_words(Register base, Register cnt, Register value);
1590 void fill_words(Register base, uint64_t cnt, Register value);
1591
1592 address zero_words(Register base, uint64_t cnt);
1593 address zero_words(Register ptr, Register cnt);
1594 void zero_dcache_blocks(Register base, Register cnt);
1595
1596 static const int zero_words_block_size;
1597
1598 address byte_array_inflate(Register src, Register dst, Register len,
1599 FloatRegister vtmp1, FloatRegister vtmp2,
1600 FloatRegister vtmp3, Register tmp4);
1601
1602 void char_array_compress(Register src, Register dst, Register len,
1603 Register res,
1604 FloatRegister vtmp0, FloatRegister vtmp1,
1605 FloatRegister vtmp2, FloatRegister vtmp3,
1606 FloatRegister vtmp4, FloatRegister vtmp5);
1607
1608 void encode_iso_array(Register src, Register dst,
1609 Register len, Register res, bool ascii,
1610 FloatRegister vtmp0, FloatRegister vtmp1,
1611 FloatRegister vtmp2, FloatRegister vtmp3,
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