15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "oops/compressedKlass.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/powerOfTwo.hpp"
36
37 class OopMap;
38
39 // MacroAssembler extends Assembler by frequently used macros.
40 //
41 // Instructions for which a 'better' code sequence exists depending
42 // on arguments should also go in here.
43
44 class MacroAssembler: public Assembler {
45 friend class LIR_Assembler;
46
47 public:
48 using Assembler::mov;
49 using Assembler::movi;
50
51 protected:
52
53 // Support for VM calls
54 //
55 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
610 msr(0b011, 0b0100, 0b0010, 0b000, reg);
611 }
612
613 // idiv variant which deals with MINLONG as dividend and -1 as divisor
614 int corrected_idivl(Register result, Register ra, Register rb,
615 bool want_remainder, Register tmp = rscratch1);
616 int corrected_idivq(Register result, Register ra, Register rb,
617 bool want_remainder, Register tmp = rscratch1);
618
619 // Support for null-checks
620 //
621 // Generates code that causes a null OS exception if the content of reg is null.
622 // If the accessed location is M[reg + offset] and the offset is known, provide the
623 // offset. No explicit code generation is needed if the offset is within a certain
624 // range (0 <= offset <= page_size).
625
626 virtual void null_check(Register reg, int offset = -1);
627 static bool needs_explicit_null_check(intptr_t offset);
628 static bool uses_implicit_null_check(void* address);
629
630 static address target_addr_for_insn(address insn_addr, unsigned insn);
631 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
632 static address target_addr_for_insn(address insn_addr) {
633 unsigned insn = *(unsigned*)insn_addr;
634 return target_addr_for_insn(insn_addr, insn);
635 }
636 static address target_addr_for_insn_or_null(address insn_addr) {
637 unsigned insn = *(unsigned*)insn_addr;
638 return target_addr_for_insn_or_null(insn_addr, insn);
639 }
640
641 // Required platform-specific helpers for Label::patch_instructions.
642 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
643 static int pd_patch_instruction_size(address branch, address target);
644 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
645 pd_patch_instruction_size(branch, target);
646 }
647 static address pd_call_destination(address branch) {
648 return target_addr_for_insn(branch);
649 }
846
847 void reset_last_Java_frame(Register thread);
848
849 // thread in the default location (rthread)
850 void reset_last_Java_frame(bool clear_fp);
851
852 // Stores
853 void store_check(Register obj); // store check for obj - register is destroyed afterwards
854 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
855
856 void resolve_jobject(Register value, Register tmp1, Register tmp2);
857 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
858
859 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
860 void c2bool(Register x);
861
862 void load_method_holder_cld(Register rresult, Register rmethod);
863 void load_method_holder(Register holder, Register method);
864
865 // oop manipulations
866 void load_klass(Register dst, Register src);
867 void store_klass(Register dst, Register src);
868 void cmp_klass(Register oop, Register trial_klass, Register tmp);
869
870 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
871 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
872 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
873
874 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
875 Register tmp1, Register tmp2);
876
877 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
878 Register tmp1, Register tmp2, Register tmp3);
879
880 void load_heap_oop(Register dst, Address src, Register tmp1,
881 Register tmp2, DecoratorSet decorators = 0);
882
883 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
884 Register tmp2, DecoratorSet decorators = 0);
885 void store_heap_oop(Address dst, Register val, Register tmp1,
886 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
887
888 // currently unimplemented
889 // Used for storing null. All other oop constants should be
890 // stored using routines that take a jobject.
891 void store_heap_oop_null(Address dst);
892
893 void store_klass_gap(Register dst, Register src);
894
895 // This dummy is to prevent a call to store_heap_oop from
896 // converting a zero (like null) into a Register by giving
897 // the compiler two choices it can't resolve
898
899 void store_heap_oop(Address dst, void* dummy);
900
901 void encode_heap_oop(Register d, Register s);
902 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
903 void decode_heap_oop(Register d, Register s);
904 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
905 void encode_heap_oop_not_null(Register r);
906 void decode_heap_oop_not_null(Register r);
907 void encode_heap_oop_not_null(Register dst, Register src);
908 void decode_heap_oop_not_null(Register dst, Register src);
909
910 void set_narrow_oop(Register dst, jobject obj);
911
912 void encode_klass_not_null(Register r);
920 void reinit_heapbase();
921
922 DEBUG_ONLY(void verify_heapbase(const char* msg);)
923
924 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
925 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
926 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
927 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
928
929 void push_cont_fastpath(Register java_thread);
930 void pop_cont_fastpath(Register java_thread);
931
932 // Round up to a power of two
933 void round_to(Register reg, int modulus);
934
935 // java.lang.Math::round intrinsics
936 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
937 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
938
939 // allocation
940 void tlab_allocate(
941 Register obj, // result: pointer to object after successful allocation
942 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
943 int con_size_in_bytes, // object size in bytes if known at compile time
944 Register t1, // temp register
945 Register t2, // temp register
946 Label& slow_case // continuation point if fast allocation fails
947 );
948 void verify_tlab();
949
950 // interface method calling
951 void lookup_interface_method(Register recv_klass,
952 Register intf_klass,
953 RegisterOrConstant itable_index,
954 Register method_result,
955 Register scan_temp,
956 Label& no_such_interface,
957 bool return_method = true);
958
959 void lookup_interface_method_stub(Register recv_klass,
960 Register holder_klass,
961 Register resolved_klass,
962 Register method_result,
963 Register temp_reg,
964 Register temp_reg2,
965 int itable_index,
966 Label& L_no_such_interface);
967
968 // virtual method calling
969 // n.b. x86 allows RegisterOrConstant for vtable_index
1322 } \
1323 \
1324 void INSN(Register Rd, Register Rn, Register Rm) { \
1325 Assembler::INSN(Rd, Rn, Rm); \
1326 } \
1327 \
1328 void INSN(Register Rd, Register Rn, Register Rm, \
1329 ext::operation option, int amount = 0) { \
1330 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1331 }
1332
1333 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1334
1335 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1336 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1337 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1338 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1339
1340 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1341
1342 void tableswitch(Register index, jint lowbound, jint highbound,
1343 Label &jumptable, Label &jumptable_end, int stride = 1) {
1344 adr(rscratch1, jumptable);
1345 subsw(rscratch2, index, lowbound);
1346 subsw(zr, rscratch2, highbound - lowbound);
1347 br(Assembler::HS, jumptable_end);
1348 add(rscratch1, rscratch1, rscratch2,
1349 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1350 br(rscratch1);
1351 }
1352
1353 // Form an address from base + offset in Rd. Rd may or may not
1354 // actually be used: you must use the Address that is returned. It
1355 // is up to you to ensure that the shift provided matches the size
1356 // of your data.
1357 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1358
1359 // Return true iff an address is within the 48-bit AArch64 address
1360 // space.
1361 bool is_valid_AArch64_address(address a) {
1386 }
1387
1388 address read_polling_page(Register r, relocInfo::relocType rtype);
1389 void get_polling_page(Register dest, relocInfo::relocType rtype);
1390
1391 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1392 void update_byte_crc32(Register crc, Register val, Register table);
1393 void update_word_crc32(Register crc, Register v, Register tmp,
1394 Register table0, Register table1, Register table2, Register table3,
1395 bool upper = false);
1396
1397 address count_positives(Register ary1, Register len, Register result);
1398
1399 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1400 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1401
1402 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1403 int elem_size);
1404
1405 void fill_words(Register base, Register cnt, Register value);
1406 address zero_words(Register base, uint64_t cnt);
1407 address zero_words(Register ptr, Register cnt);
1408 void zero_dcache_blocks(Register base, Register cnt);
1409
1410 static const int zero_words_block_size;
1411
1412 address byte_array_inflate(Register src, Register dst, Register len,
1413 FloatRegister vtmp1, FloatRegister vtmp2,
1414 FloatRegister vtmp3, Register tmp4);
1415
1416 void char_array_compress(Register src, Register dst, Register len,
1417 Register res,
1418 FloatRegister vtmp0, FloatRegister vtmp1,
1419 FloatRegister vtmp2, FloatRegister vtmp3,
1420 FloatRegister vtmp4, FloatRegister vtmp5);
1421
1422 void encode_iso_array(Register src, Register dst,
1423 Register len, Register res, bool ascii,
1424 FloatRegister vtmp0, FloatRegister vtmp1,
1425 FloatRegister vtmp2, FloatRegister vtmp3,
|
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "oops/compressedKlass.hpp"
34 #include "runtime/vm_version.hpp"
35 #include "utilities/macros.hpp"
36 #include "utilities/powerOfTwo.hpp"
37 #include "runtime/signature.hpp"
38
39
40 class ciInlineKlass;
41
42 class OopMap;
43
44 // MacroAssembler extends Assembler by frequently used macros.
45 //
46 // Instructions for which a 'better' code sequence exists depending
47 // on arguments should also go in here.
48
49 class MacroAssembler: public Assembler {
50 friend class LIR_Assembler;
51
52 public:
53 using Assembler::mov;
54 using Assembler::movi;
55
56 protected:
57
58 // Support for VM calls
59 //
60 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
615 msr(0b011, 0b0100, 0b0010, 0b000, reg);
616 }
617
618 // idiv variant which deals with MINLONG as dividend and -1 as divisor
619 int corrected_idivl(Register result, Register ra, Register rb,
620 bool want_remainder, Register tmp = rscratch1);
621 int corrected_idivq(Register result, Register ra, Register rb,
622 bool want_remainder, Register tmp = rscratch1);
623
624 // Support for null-checks
625 //
626 // Generates code that causes a null OS exception if the content of reg is null.
627 // If the accessed location is M[reg + offset] and the offset is known, provide the
628 // offset. No explicit code generation is needed if the offset is within a certain
629 // range (0 <= offset <= page_size).
630
631 virtual void null_check(Register reg, int offset = -1);
632 static bool needs_explicit_null_check(intptr_t offset);
633 static bool uses_implicit_null_check(void* address);
634
635 // markWord tests, kills markWord reg
636 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
637
638 // inlineKlass queries, kills temp_reg
639 void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type);
640 void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type);
641 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type);
642
643 // Get the default value oop for the given InlineKlass
644 void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj);
645 // The empty value oop, for the given InlineKlass ("empty" as in no instance fields)
646 // get_default_value_oop with extra assertion for empty inline klass
647 void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj);
648
649 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
650 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
651 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
652
653 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
654 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
655 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
656 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
657 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
658 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
659
660 // Check array klass layout helper for flat or null-free arrays...
661 void test_flat_array_layout(Register lh, Label& is_flat_array);
662 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array);
663 void test_null_free_array_layout(Register lh, Label& is_null_free_array);
664 void test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array);
665
666 static address target_addr_for_insn(address insn_addr, unsigned insn);
667 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
668 static address target_addr_for_insn(address insn_addr) {
669 unsigned insn = *(unsigned*)insn_addr;
670 return target_addr_for_insn(insn_addr, insn);
671 }
672 static address target_addr_for_insn_or_null(address insn_addr) {
673 unsigned insn = *(unsigned*)insn_addr;
674 return target_addr_for_insn_or_null(insn_addr, insn);
675 }
676
677 // Required platform-specific helpers for Label::patch_instructions.
678 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
679 static int pd_patch_instruction_size(address branch, address target);
680 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
681 pd_patch_instruction_size(branch, target);
682 }
683 static address pd_call_destination(address branch) {
684 return target_addr_for_insn(branch);
685 }
882
883 void reset_last_Java_frame(Register thread);
884
885 // thread in the default location (rthread)
886 void reset_last_Java_frame(bool clear_fp);
887
888 // Stores
889 void store_check(Register obj); // store check for obj - register is destroyed afterwards
890 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
891
892 void resolve_jobject(Register value, Register tmp1, Register tmp2);
893 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
894
895 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
896 void c2bool(Register x);
897
898 void load_method_holder_cld(Register rresult, Register rmethod);
899 void load_method_holder(Register holder, Register method);
900
901 // oop manipulations
902 void load_metadata(Register dst, Register src);
903
904 void load_klass(Register dst, Register src);
905 void store_klass(Register dst, Register src);
906 void cmp_klass(Register oop, Register trial_klass, Register tmp);
907
908 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
909 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
910 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
911
912 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
913 Register tmp1, Register tmp2);
914
915 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
916 Register tmp1, Register tmp2, Register tmp3);
917
918 void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass);
919
920 // inline type data payload offsets...
921 void first_field_offset(Register inline_klass, Register offset);
922 void data_for_oop(Register oop, Register data, Register inline_klass);
923 // get data payload ptr a flat value array at index, kills rcx and index
924 void data_for_value_array_index(Register array, Register array_klass,
925 Register index, Register data);
926
927 void load_heap_oop(Register dst, Address src, Register tmp1,
928 Register tmp2, DecoratorSet decorators = 0);
929
930 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
931 Register tmp2, DecoratorSet decorators = 0);
932 void store_heap_oop(Address dst, Register val, Register tmp1,
933 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
934
935 // currently unimplemented
936 // Used for storing null. All other oop constants should be
937 // stored using routines that take a jobject.
938 void store_heap_oop_null(Address dst);
939
940 void load_prototype_header(Register dst, Register src);
941
942 void store_klass_gap(Register dst, Register src);
943
944 // This dummy is to prevent a call to store_heap_oop from
945 // converting a zero (like null) into a Register by giving
946 // the compiler two choices it can't resolve
947
948 void store_heap_oop(Address dst, void* dummy);
949
950 void encode_heap_oop(Register d, Register s);
951 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
952 void decode_heap_oop(Register d, Register s);
953 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
954 void encode_heap_oop_not_null(Register r);
955 void decode_heap_oop_not_null(Register r);
956 void encode_heap_oop_not_null(Register dst, Register src);
957 void decode_heap_oop_not_null(Register dst, Register src);
958
959 void set_narrow_oop(Register dst, jobject obj);
960
961 void encode_klass_not_null(Register r);
969 void reinit_heapbase();
970
971 DEBUG_ONLY(void verify_heapbase(const char* msg);)
972
973 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
974 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
975 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
976 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
977
978 void push_cont_fastpath(Register java_thread);
979 void pop_cont_fastpath(Register java_thread);
980
981 // Round up to a power of two
982 void round_to(Register reg, int modulus);
983
984 // java.lang.Math::round intrinsics
985 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
986 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
987
988 // allocation
989
990 // Object / value buffer allocation...
991 // Allocate instance of klass, assumes klass initialized by caller
992 // new_obj prefers to be rax
993 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
994 void allocate_instance(Register klass, Register new_obj,
995 Register t1, Register t2,
996 bool clear_fields, Label& alloc_failed);
997
998 void tlab_allocate(
999 Register obj, // result: pointer to object after successful allocation
1000 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1001 int con_size_in_bytes, // object size in bytes if known at compile time
1002 Register t1, // temp register
1003 Register t2, // temp register
1004 Label& slow_case // continuation point if fast allocation fails
1005 );
1006 void verify_tlab();
1007
1008 // For field "index" within "klass", return inline_klass ...
1009 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
1010
1011 // interface method calling
1012 void lookup_interface_method(Register recv_klass,
1013 Register intf_klass,
1014 RegisterOrConstant itable_index,
1015 Register method_result,
1016 Register scan_temp,
1017 Label& no_such_interface,
1018 bool return_method = true);
1019
1020 void lookup_interface_method_stub(Register recv_klass,
1021 Register holder_klass,
1022 Register resolved_klass,
1023 Register method_result,
1024 Register temp_reg,
1025 Register temp_reg2,
1026 int itable_index,
1027 Label& L_no_such_interface);
1028
1029 // virtual method calling
1030 // n.b. x86 allows RegisterOrConstant for vtable_index
1383 } \
1384 \
1385 void INSN(Register Rd, Register Rn, Register Rm) { \
1386 Assembler::INSN(Rd, Rn, Rm); \
1387 } \
1388 \
1389 void INSN(Register Rd, Register Rn, Register Rm, \
1390 ext::operation option, int amount = 0) { \
1391 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1392 }
1393
1394 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1395
1396 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1397 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1398 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1399 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1400
1401 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1402
1403 void verified_entry(Compile* C, int sp_inc);
1404
1405 // Inline type specific methods
1406 #include "asm/macroAssembler_common.hpp"
1407
1408 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1409 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1410 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1411 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1412 RegState reg_state[]);
1413 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1414 VMRegPair* from, int from_count, int& from_index, VMReg to,
1415 RegState reg_state[], Register val_array);
1416 int extend_stack_for_inline_args(int args_on_stack);
1417 void remove_frame(int initial_framesize, bool needs_stack_repair);
1418 VMReg spill_reg_for(VMReg reg);
1419 void save_stack_increment(int sp_inc, int frame_size);
1420
1421 void tableswitch(Register index, jint lowbound, jint highbound,
1422 Label &jumptable, Label &jumptable_end, int stride = 1) {
1423 adr(rscratch1, jumptable);
1424 subsw(rscratch2, index, lowbound);
1425 subsw(zr, rscratch2, highbound - lowbound);
1426 br(Assembler::HS, jumptable_end);
1427 add(rscratch1, rscratch1, rscratch2,
1428 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1429 br(rscratch1);
1430 }
1431
1432 // Form an address from base + offset in Rd. Rd may or may not
1433 // actually be used: you must use the Address that is returned. It
1434 // is up to you to ensure that the shift provided matches the size
1435 // of your data.
1436 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1437
1438 // Return true iff an address is within the 48-bit AArch64 address
1439 // space.
1440 bool is_valid_AArch64_address(address a) {
1465 }
1466
1467 address read_polling_page(Register r, relocInfo::relocType rtype);
1468 void get_polling_page(Register dest, relocInfo::relocType rtype);
1469
1470 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1471 void update_byte_crc32(Register crc, Register val, Register table);
1472 void update_word_crc32(Register crc, Register v, Register tmp,
1473 Register table0, Register table1, Register table2, Register table3,
1474 bool upper = false);
1475
1476 address count_positives(Register ary1, Register len, Register result);
1477
1478 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1479 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1480
1481 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1482 int elem_size);
1483
1484 void fill_words(Register base, Register cnt, Register value);
1485 void fill_words(Register base, uint64_t cnt, Register value);
1486
1487 address zero_words(Register base, uint64_t cnt);
1488 address zero_words(Register ptr, Register cnt);
1489 void zero_dcache_blocks(Register base, Register cnt);
1490
1491 static const int zero_words_block_size;
1492
1493 address byte_array_inflate(Register src, Register dst, Register len,
1494 FloatRegister vtmp1, FloatRegister vtmp2,
1495 FloatRegister vtmp3, Register tmp4);
1496
1497 void char_array_compress(Register src, Register dst, Register len,
1498 Register res,
1499 FloatRegister vtmp0, FloatRegister vtmp1,
1500 FloatRegister vtmp2, FloatRegister vtmp3,
1501 FloatRegister vtmp4, FloatRegister vtmp5);
1502
1503 void encode_iso_array(Register src, Register dst,
1504 Register len, Register res, bool ascii,
1505 FloatRegister vtmp0, FloatRegister vtmp1,
1506 FloatRegister vtmp2, FloatRegister vtmp3,
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