14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "runtime/vm_version.hpp"
34 #include "utilities/powerOfTwo.hpp"
35
36 class OopMap;
37
38 // MacroAssembler extends Assembler by frequently used macros.
39 //
40 // Instructions for which a 'better' code sequence exists depending
41 // on arguments should also go in here.
42
43 class MacroAssembler: public Assembler {
44 friend class LIR_Assembler;
45
46 public:
47 using Assembler::mov;
48 using Assembler::movi;
49
50 protected:
51
52 // Support for VM calls
53 //
54 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
581 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
582 }
583
584 // idiv variant which deals with MINLONG as dividend and -1 as divisor
585 int corrected_idivl(Register result, Register ra, Register rb,
586 bool want_remainder, Register tmp = rscratch1);
587 int corrected_idivq(Register result, Register ra, Register rb,
588 bool want_remainder, Register tmp = rscratch1);
589
590 // Support for NULL-checks
591 //
592 // Generates code that causes a NULL OS exception if the content of reg is NULL.
593 // If the accessed location is M[reg + offset] and the offset is known, provide the
594 // offset. No explicit code generation is needed if the offset is within a certain
595 // range (0 <= offset <= page_size).
596
597 virtual void null_check(Register reg, int offset = -1);
598 static bool needs_explicit_null_check(intptr_t offset);
599 static bool uses_implicit_null_check(void* address);
600
601 static address target_addr_for_insn(address insn_addr, unsigned insn);
602 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
603 static address target_addr_for_insn(address insn_addr) {
604 unsigned insn = *(unsigned*)insn_addr;
605 return target_addr_for_insn(insn_addr, insn);
606 }
607 static address target_addr_for_insn_or_null(address insn_addr) {
608 unsigned insn = *(unsigned*)insn_addr;
609 return target_addr_for_insn_or_null(insn_addr, insn);
610 }
611
612 // Required platform-specific helpers for Label::patch_instructions.
613 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
614 static int pd_patch_instruction_size(address branch, address target);
615 static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
616 pd_patch_instruction_size(branch, target);
617 }
618 static address pd_call_destination(address branch) {
619 return target_addr_for_insn(branch);
620 }
814 Register scratch);
815
816 void reset_last_Java_frame(Register thread);
817
818 // thread in the default location (rthread)
819 void reset_last_Java_frame(bool clear_fp);
820
821 // Stores
822 void store_check(Register obj); // store check for obj - register is destroyed afterwards
823 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
824
825 void resolve_jobject(Register value, Register tmp1, Register tmp2);
826
827 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
828 void c2bool(Register x);
829
830 void load_method_holder_cld(Register rresult, Register rmethod);
831 void load_method_holder(Register holder, Register method);
832
833 // oop manipulations
834 void load_klass(Register dst, Register src);
835 void store_klass(Register dst, Register src);
836 void cmp_klass(Register oop, Register trial_klass, Register tmp);
837
838 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
839 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
840 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
841
842 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
843 Register tmp1, Register tmp2);
844
845 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
846 Register tmp1, Register tmp2, Register tmp3);
847
848 void load_heap_oop(Register dst, Address src, Register tmp1,
849 Register tmp2, DecoratorSet decorators = 0);
850
851 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
852 Register tmp2, DecoratorSet decorators = 0);
853 void store_heap_oop(Address dst, Register val, Register tmp1,
854 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
855
856 // currently unimplemented
857 // Used for storing NULL. All other oop constants should be
858 // stored using routines that take a jobject.
859 void store_heap_oop_null(Address dst);
860
861 void store_klass_gap(Register dst, Register src);
862
863 // This dummy is to prevent a call to store_heap_oop from
864 // converting a zero (like NULL) into a Register by giving
865 // the compiler two choices it can't resolve
866
867 void store_heap_oop(Address dst, void* dummy);
868
869 void encode_heap_oop(Register d, Register s);
870 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
871 void decode_heap_oop(Register d, Register s);
872 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
873 void encode_heap_oop_not_null(Register r);
874 void decode_heap_oop_not_null(Register r);
875 void encode_heap_oop_not_null(Register dst, Register src);
876 void decode_heap_oop_not_null(Register dst, Register src);
877
878 void set_narrow_oop(Register dst, jobject obj);
879
880 void encode_klass_not_null(Register r);
888 void reinit_heapbase();
889
890 DEBUG_ONLY(void verify_heapbase(const char* msg);)
891
892 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
893 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
894 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
895 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
896
897 void push_cont_fastpath(Register java_thread);
898 void pop_cont_fastpath(Register java_thread);
899
900 // Round up to a power of two
901 void round_to(Register reg, int modulus);
902
903 // java.lang.Math::round intrinsics
904 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
905 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
906
907 // allocation
908 void tlab_allocate(
909 Register obj, // result: pointer to object after successful allocation
910 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
911 int con_size_in_bytes, // object size in bytes if known at compile time
912 Register t1, // temp register
913 Register t2, // temp register
914 Label& slow_case // continuation point if fast allocation fails
915 );
916 void verify_tlab();
917
918 // interface method calling
919 void lookup_interface_method(Register recv_klass,
920 Register intf_klass,
921 RegisterOrConstant itable_index,
922 Register method_result,
923 Register scan_temp,
924 Label& no_such_interface,
925 bool return_method = true);
926
927 // virtual method calling
928 // n.b. x86 allows RegisterOrConstant for vtable_index
929 void lookup_virtual_method(Register recv_klass,
930 RegisterOrConstant vtable_index,
931 Register method_result);
932
933 // Test sub_klass against super_klass, with fast and slow paths.
934
935 // The fast path produces a tri-state answer: yes / no / maybe-slow.
936 // One of the three labels can be NULL, meaning take the fall-through.
937 // If super_check_offset is -1, the value is loaded up from super_klass.
1281 } \
1282 \
1283 void INSN(Register Rd, Register Rn, Register Rm) { \
1284 Assembler::INSN(Rd, Rn, Rm); \
1285 } \
1286 \
1287 void INSN(Register Rd, Register Rn, Register Rm, \
1288 ext::operation option, int amount = 0) { \
1289 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1290 }
1291
1292 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1293
1294 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1295 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1296 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1297 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1298
1299 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1300
1301 void tableswitch(Register index, jint lowbound, jint highbound,
1302 Label &jumptable, Label &jumptable_end, int stride = 1) {
1303 adr(rscratch1, jumptable);
1304 subsw(rscratch2, index, lowbound);
1305 subsw(zr, rscratch2, highbound - lowbound);
1306 br(Assembler::HS, jumptable_end);
1307 add(rscratch1, rscratch1, rscratch2,
1308 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1309 br(rscratch1);
1310 }
1311
1312 // Form an address from base + offset in Rd. Rd may or may not
1313 // actually be used: you must use the Address that is returned. It
1314 // is up to you to ensure that the shift provided matches the size
1315 // of your data.
1316 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1317
1318 // Return true iff an address is within the 48-bit AArch64 address
1319 // space.
1320 bool is_valid_AArch64_address(address a) {
1345 }
1346
1347 address read_polling_page(Register r, relocInfo::relocType rtype);
1348 void get_polling_page(Register dest, relocInfo::relocType rtype);
1349
1350 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1351 void update_byte_crc32(Register crc, Register val, Register table);
1352 void update_word_crc32(Register crc, Register v, Register tmp,
1353 Register table0, Register table1, Register table2, Register table3,
1354 bool upper = false);
1355
1356 address count_positives(Register ary1, Register len, Register result);
1357
1358 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1359 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1360
1361 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1362 int elem_size);
1363
1364 void fill_words(Register base, Register cnt, Register value);
1365 address zero_words(Register base, uint64_t cnt);
1366 address zero_words(Register ptr, Register cnt);
1367 void zero_dcache_blocks(Register base, Register cnt);
1368
1369 static const int zero_words_block_size;
1370
1371 address byte_array_inflate(Register src, Register dst, Register len,
1372 FloatRegister vtmp1, FloatRegister vtmp2,
1373 FloatRegister vtmp3, Register tmp4);
1374
1375 void char_array_compress(Register src, Register dst, Register len,
1376 Register res,
1377 FloatRegister vtmp0, FloatRegister vtmp1,
1378 FloatRegister vtmp2, FloatRegister vtmp3);
1379
1380 void encode_iso_array(Register src, Register dst,
1381 Register len, Register res, bool ascii,
1382 FloatRegister vtmp0, FloatRegister vtmp1,
1383 FloatRegister vtmp2, FloatRegister vtmp3);
1384
|
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/vmreg.hpp"
31 #include "metaprogramming/enableIf.hpp"
32 #include "oops/compressedOops.hpp"
33 #include "runtime/vm_version.hpp"
34 #include "utilities/macros.hpp"
35 #include "utilities/powerOfTwo.hpp"
36 #include "runtime/signature.hpp"
37
38
39 class ciInlineKlass;
40
41 class OopMap;
42
43 // MacroAssembler extends Assembler by frequently used macros.
44 //
45 // Instructions for which a 'better' code sequence exists depending
46 // on arguments should also go in here.
47
48 class MacroAssembler: public Assembler {
49 friend class LIR_Assembler;
50
51 public:
52 using Assembler::mov;
53 using Assembler::movi;
54
55 protected:
56
57 // Support for VM calls
58 //
59 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
586 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
587 }
588
589 // idiv variant which deals with MINLONG as dividend and -1 as divisor
590 int corrected_idivl(Register result, Register ra, Register rb,
591 bool want_remainder, Register tmp = rscratch1);
592 int corrected_idivq(Register result, Register ra, Register rb,
593 bool want_remainder, Register tmp = rscratch1);
594
595 // Support for NULL-checks
596 //
597 // Generates code that causes a NULL OS exception if the content of reg is NULL.
598 // If the accessed location is M[reg + offset] and the offset is known, provide the
599 // offset. No explicit code generation is needed if the offset is within a certain
600 // range (0 <= offset <= page_size).
601
602 virtual void null_check(Register reg, int offset = -1);
603 static bool needs_explicit_null_check(intptr_t offset);
604 static bool uses_implicit_null_check(void* address);
605
606 // markWord tests, kills markWord reg
607 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
608
609 // inlineKlass queries, kills temp_reg
610 void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type);
611 void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type);
612 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type);
613
614 // Get the default value oop for the given InlineKlass
615 void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj);
616 // The empty value oop, for the given InlineKlass ("empty" as in no instance fields)
617 // get_default_value_oop with extra assertion for empty inline klass
618 void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj);
619
620 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
621 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
622 void test_field_is_inlined(Register flags, Register temp_reg, Label& is_flattened);
623
624 // Check oops for special arrays, i.e. flattened and/or null-free
625 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
626 void test_flattened_array_oop(Register klass, Register temp_reg, Label& is_flattened_array);
627 void test_non_flattened_array_oop(Register oop, Register temp_reg, Label&is_non_flattened_array);
628 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
629 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
630
631 // Check array klass layout helper for flatten or null-free arrays...
632 void test_flattened_array_layout(Register lh, Label& is_flattened_array);
633 void test_non_flattened_array_layout(Register lh, Label& is_non_flattened_array);
634 void test_null_free_array_layout(Register lh, Label& is_null_free_array);
635 void test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array);
636
637 static address target_addr_for_insn(address insn_addr, unsigned insn);
638 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
639 static address target_addr_for_insn(address insn_addr) {
640 unsigned insn = *(unsigned*)insn_addr;
641 return target_addr_for_insn(insn_addr, insn);
642 }
643 static address target_addr_for_insn_or_null(address insn_addr) {
644 unsigned insn = *(unsigned*)insn_addr;
645 return target_addr_for_insn_or_null(insn_addr, insn);
646 }
647
648 // Required platform-specific helpers for Label::patch_instructions.
649 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
650 static int pd_patch_instruction_size(address branch, address target);
651 static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
652 pd_patch_instruction_size(branch, target);
653 }
654 static address pd_call_destination(address branch) {
655 return target_addr_for_insn(branch);
656 }
850 Register scratch);
851
852 void reset_last_Java_frame(Register thread);
853
854 // thread in the default location (rthread)
855 void reset_last_Java_frame(bool clear_fp);
856
857 // Stores
858 void store_check(Register obj); // store check for obj - register is destroyed afterwards
859 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
860
861 void resolve_jobject(Register value, Register tmp1, Register tmp2);
862
863 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
864 void c2bool(Register x);
865
866 void load_method_holder_cld(Register rresult, Register rmethod);
867 void load_method_holder(Register holder, Register method);
868
869 // oop manipulations
870 void load_metadata(Register dst, Register src);
871
872 void load_klass(Register dst, Register src);
873 void store_klass(Register dst, Register src);
874 void cmp_klass(Register oop, Register trial_klass, Register tmp);
875
876 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
877 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
878 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
879
880 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
881 Register tmp1, Register tmp2);
882
883 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
884 Register tmp1, Register tmp2, Register tmp3);
885
886 void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass);
887
888 // inline type data payload offsets...
889 void first_field_offset(Register inline_klass, Register offset);
890 void data_for_oop(Register oop, Register data, Register inline_klass);
891 // get data payload ptr a flat value array at index, kills rcx and index
892 void data_for_value_array_index(Register array, Register array_klass,
893 Register index, Register data);
894
895 void load_heap_oop(Register dst, Address src, Register tmp1,
896 Register tmp2, DecoratorSet decorators = 0);
897
898 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
899 Register tmp2, DecoratorSet decorators = 0);
900 void store_heap_oop(Address dst, Register val, Register tmp1,
901 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
902
903 // currently unimplemented
904 // Used for storing NULL. All other oop constants should be
905 // stored using routines that take a jobject.
906 void store_heap_oop_null(Address dst);
907
908 void load_prototype_header(Register dst, Register src);
909
910 void store_klass_gap(Register dst, Register src);
911
912 // This dummy is to prevent a call to store_heap_oop from
913 // converting a zero (like NULL) into a Register by giving
914 // the compiler two choices it can't resolve
915
916 void store_heap_oop(Address dst, void* dummy);
917
918 void encode_heap_oop(Register d, Register s);
919 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
920 void decode_heap_oop(Register d, Register s);
921 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
922 void encode_heap_oop_not_null(Register r);
923 void decode_heap_oop_not_null(Register r);
924 void encode_heap_oop_not_null(Register dst, Register src);
925 void decode_heap_oop_not_null(Register dst, Register src);
926
927 void set_narrow_oop(Register dst, jobject obj);
928
929 void encode_klass_not_null(Register r);
937 void reinit_heapbase();
938
939 DEBUG_ONLY(void verify_heapbase(const char* msg);)
940
941 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
942 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
943 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
944 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
945
946 void push_cont_fastpath(Register java_thread);
947 void pop_cont_fastpath(Register java_thread);
948
949 // Round up to a power of two
950 void round_to(Register reg, int modulus);
951
952 // java.lang.Math::round intrinsics
953 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
954 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
955
956 // allocation
957
958 // Object / value buffer allocation...
959 // Allocate instance of klass, assumes klass initialized by caller
960 // new_obj prefers to be rax
961 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
962 void allocate_instance(Register klass, Register new_obj,
963 Register t1, Register t2,
964 bool clear_fields, Label& alloc_failed);
965
966 void tlab_allocate(
967 Register obj, // result: pointer to object after successful allocation
968 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
969 int con_size_in_bytes, // object size in bytes if known at compile time
970 Register t1, // temp register
971 Register t2, // temp register
972 Label& slow_case // continuation point if fast allocation fails
973 );
974 void verify_tlab();
975
976 // For field "index" within "klass", return inline_klass ...
977 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
978
979 // interface method calling
980 void lookup_interface_method(Register recv_klass,
981 Register intf_klass,
982 RegisterOrConstant itable_index,
983 Register method_result,
984 Register scan_temp,
985 Label& no_such_interface,
986 bool return_method = true);
987
988 // virtual method calling
989 // n.b. x86 allows RegisterOrConstant for vtable_index
990 void lookup_virtual_method(Register recv_klass,
991 RegisterOrConstant vtable_index,
992 Register method_result);
993
994 // Test sub_klass against super_klass, with fast and slow paths.
995
996 // The fast path produces a tri-state answer: yes / no / maybe-slow.
997 // One of the three labels can be NULL, meaning take the fall-through.
998 // If super_check_offset is -1, the value is loaded up from super_klass.
1342 } \
1343 \
1344 void INSN(Register Rd, Register Rn, Register Rm) { \
1345 Assembler::INSN(Rd, Rn, Rm); \
1346 } \
1347 \
1348 void INSN(Register Rd, Register Rn, Register Rm, \
1349 ext::operation option, int amount = 0) { \
1350 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1351 }
1352
1353 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1354
1355 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1356 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1357 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1358 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1359
1360 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1361
1362 void verified_entry(Compile* C, int sp_inc);
1363
1364 // Inline type specific methods
1365 #include "asm/macroAssembler_common.hpp"
1366
1367 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1368 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1369 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1370 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1371 RegState reg_state[]);
1372 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1373 VMRegPair* from, int from_count, int& from_index, VMReg to,
1374 RegState reg_state[], Register val_array);
1375 int extend_stack_for_inline_args(int args_on_stack);
1376 void remove_frame(int initial_framesize, bool needs_stack_repair);
1377 VMReg spill_reg_for(VMReg reg);
1378 void save_stack_increment(int sp_inc, int frame_size);
1379
1380 void tableswitch(Register index, jint lowbound, jint highbound,
1381 Label &jumptable, Label &jumptable_end, int stride = 1) {
1382 adr(rscratch1, jumptable);
1383 subsw(rscratch2, index, lowbound);
1384 subsw(zr, rscratch2, highbound - lowbound);
1385 br(Assembler::HS, jumptable_end);
1386 add(rscratch1, rscratch1, rscratch2,
1387 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1388 br(rscratch1);
1389 }
1390
1391 // Form an address from base + offset in Rd. Rd may or may not
1392 // actually be used: you must use the Address that is returned. It
1393 // is up to you to ensure that the shift provided matches the size
1394 // of your data.
1395 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1396
1397 // Return true iff an address is within the 48-bit AArch64 address
1398 // space.
1399 bool is_valid_AArch64_address(address a) {
1424 }
1425
1426 address read_polling_page(Register r, relocInfo::relocType rtype);
1427 void get_polling_page(Register dest, relocInfo::relocType rtype);
1428
1429 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1430 void update_byte_crc32(Register crc, Register val, Register table);
1431 void update_word_crc32(Register crc, Register v, Register tmp,
1432 Register table0, Register table1, Register table2, Register table3,
1433 bool upper = false);
1434
1435 address count_positives(Register ary1, Register len, Register result);
1436
1437 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1438 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1439
1440 void string_equals(Register a1, Register a2, Register result, Register cnt1,
1441 int elem_size);
1442
1443 void fill_words(Register base, Register cnt, Register value);
1444 void fill_words(Register base, uint64_t cnt, Register value);
1445
1446 address zero_words(Register base, uint64_t cnt);
1447 address zero_words(Register ptr, Register cnt);
1448 void zero_dcache_blocks(Register base, Register cnt);
1449
1450 static const int zero_words_block_size;
1451
1452 address byte_array_inflate(Register src, Register dst, Register len,
1453 FloatRegister vtmp1, FloatRegister vtmp2,
1454 FloatRegister vtmp3, Register tmp4);
1455
1456 void char_array_compress(Register src, Register dst, Register len,
1457 Register res,
1458 FloatRegister vtmp0, FloatRegister vtmp1,
1459 FloatRegister vtmp2, FloatRegister vtmp3);
1460
1461 void encode_iso_array(Register src, Register dst,
1462 Register len, Register res, bool ascii,
1463 FloatRegister vtmp0, FloatRegister vtmp1,
1464 FloatRegister vtmp2, FloatRegister vtmp3);
1465
|