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src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp

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  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "metaprogramming/enableIf.hpp"
  31 #include "oops/compressedOops.hpp"
  32 #include "runtime/vm_version.hpp"

  33 #include "utilities/powerOfTwo.hpp"




  34 
  35 // MacroAssembler extends Assembler by frequently used macros.
  36 //
  37 // Instructions for which a 'better' code sequence exists depending
  38 // on arguments should also go in here.
  39 
  40 class MacroAssembler: public Assembler {
  41   friend class LIR_Assembler;
  42 
  43  public:
  44   using Assembler::mov;
  45   using Assembler::movi;
  46 
  47  protected:
  48 
  49   // Support for VM calls
  50   //
  51   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  52   // may customize this version by overriding it for its purposes (e.g., to save/restore
  53   // additional registers when doing a VM call).

 582     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 583   }
 584 
 585   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 586   int corrected_idivl(Register result, Register ra, Register rb,
 587                       bool want_remainder, Register tmp = rscratch1);
 588   int corrected_idivq(Register result, Register ra, Register rb,
 589                       bool want_remainder, Register tmp = rscratch1);
 590 
 591   // Support for NULL-checks
 592   //
 593   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 594   // If the accessed location is M[reg + offset] and the offset is known, provide the
 595   // offset. No explicit code generation is needed if the offset is within a certain
 596   // range (0 <= offset <= page_size).
 597 
 598   virtual void null_check(Register reg, int offset = -1);
 599   static bool needs_explicit_null_check(intptr_t offset);
 600   static bool uses_implicit_null_check(void* address);
 601 































 602   static address target_addr_for_insn(address insn_addr, unsigned insn);
 603   static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
 604   static address target_addr_for_insn(address insn_addr) {
 605     unsigned insn = *(unsigned*)insn_addr;
 606     return target_addr_for_insn(insn_addr, insn);
 607   }
 608   static address target_addr_for_insn_or_null(address insn_addr) {
 609     unsigned insn = *(unsigned*)insn_addr;
 610     return target_addr_for_insn_or_null(insn_addr, insn);
 611   }
 612 
 613   // Required platform-specific helpers for Label::patch_instructions.
 614   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 615   static int pd_patch_instruction_size(address branch, address target);
 616   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 617     pd_patch_instruction_size(branch, target);
 618   }
 619   static address pd_call_destination(address branch) {
 620     return target_addr_for_insn(branch);
 621   }

 794                            Register scratch);
 795 
 796   void reset_last_Java_frame(Register thread);
 797 
 798   // thread in the default location (rthread)
 799   void reset_last_Java_frame(bool clear_fp);
 800 
 801   // Stores
 802   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 803   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 804 
 805   void resolve_jobject(Register value, Register thread, Register tmp);
 806 
 807   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 808   void c2bool(Register x);
 809 
 810   void load_method_holder_cld(Register rresult, Register rmethod);
 811   void load_method_holder(Register holder, Register method);
 812 
 813   // oop manipulations


 814   void load_klass(Register dst, Register src);
 815   void store_klass(Register dst, Register src);
 816   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 817 
 818   void resolve_weak_handle(Register result, Register tmp);
 819   void resolve_oop_handle(Register result, Register tmp = r5);
 820   void load_mirror(Register dst, Register method, Register tmp = r5);
 821 
 822   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 823                       Register tmp1, Register tmp_thread);
 824 
 825   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 826                        Register tmp1, Register tmp_thread);









 827 
 828   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 829                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 830 
 831   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 832                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 833   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 834                       Register tmp_thread = noreg, DecoratorSet decorators = 0);
 835 
 836   // currently unimplemented
 837   // Used for storing NULL. All other oop constants should be
 838   // stored using routines that take a jobject.
 839   void store_heap_oop_null(Address dst);
 840 


 841   void store_klass_gap(Register dst, Register src);
 842 
 843   // This dummy is to prevent a call to store_heap_oop from
 844   // converting a zero (like NULL) into a Register by giving
 845   // the compiler two choices it can't resolve
 846 
 847   void store_heap_oop(Address dst, void* dummy);
 848 
 849   void encode_heap_oop(Register d, Register s);
 850   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 851   void decode_heap_oop(Register d, Register s);
 852   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 853   void encode_heap_oop_not_null(Register r);
 854   void decode_heap_oop_not_null(Register r);
 855   void encode_heap_oop_not_null(Register dst, Register src);
 856   void decode_heap_oop_not_null(Register dst, Register src);
 857 
 858   void set_narrow_oop(Register dst, jobject obj);
 859 
 860   void encode_klass_not_null(Register r);
 861   void decode_klass_not_null(Register r);
 862   void encode_klass_not_null(Register dst, Register src);
 863   void decode_klass_not_null(Register dst, Register src);
 864 
 865   void set_narrow_klass(Register dst, Klass* k);
 866 
 867   // if heap base register is used - reinit it with the correct value
 868   void reinit_heapbase();
 869 
 870   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 871 
 872   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 873                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 874   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 875                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 876 
 877   // Round up to a power of two
 878   void round_to(Register reg, int modulus);
 879 
 880   // allocation









 881   void eden_allocate(
 882     Register obj,                      // result: pointer to object after successful allocation
 883     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 884     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 885     Register t1,                       // temp register
 886     Label&   slow_case                 // continuation point if fast allocation fails
 887   );
 888   void tlab_allocate(
 889     Register obj,                      // result: pointer to object after successful allocation
 890     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 891     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 892     Register t1,                       // temp register
 893     Register t2,                       // temp register
 894     Label&   slow_case                 // continuation point if fast allocation fails
 895   );
 896   void verify_tlab();
 897 



 898   // interface method calling
 899   void lookup_interface_method(Register recv_klass,
 900                                Register intf_klass,
 901                                RegisterOrConstant itable_index,
 902                                Register method_result,
 903                                Register scan_temp,
 904                                Label& no_such_interface,
 905                    bool return_method = true);
 906 
 907   // virtual method calling
 908   // n.b. x86 allows RegisterOrConstant for vtable_index
 909   void lookup_virtual_method(Register recv_klass,
 910                              RegisterOrConstant vtable_index,
 911                              Register method_result);
 912 
 913   // Test sub_klass against super_klass, with fast and slow paths.
 914 
 915   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 916   // One of the three labels can be NULL, meaning take the fall-through.
 917   // If super_check_offset is -1, the value is loaded up from super_klass.

1162   }                                                                     \
1163                                                                         \
1164   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1165     Assembler::INSN(Rd, Rn, Rm);                                        \
1166   }                                                                     \
1167                                                                         \
1168   void INSN(Register Rd, Register Rn, Register Rm,                      \
1169            ext::operation option, int amount = 0) {                     \
1170     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1171   }
1172 
1173   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1174 
1175   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1176   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1177   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1178   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1179 
1180   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1181 


















1182   void tableswitch(Register index, jint lowbound, jint highbound,
1183                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1184     adr(rscratch1, jumptable);
1185     subsw(rscratch2, index, lowbound);
1186     subsw(zr, rscratch2, highbound - lowbound);
1187     br(Assembler::HS, jumptable_end);
1188     add(rscratch1, rscratch1, rscratch2,
1189         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1190     br(rscratch1);
1191   }
1192 
1193   // Form an address from base + offset in Rd.  Rd may or may not
1194   // actually be used: you must use the Address that is returned.  It
1195   // is up to you to ensure that the shift provided matches the size
1196   // of your data.
1197   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1198 
1199   // Return true iff an address is within the 48-bit AArch64 address
1200   // space.
1201   bool is_valid_AArch64_address(address a) {

1226   }
1227 
1228   address read_polling_page(Register r, relocInfo::relocType rtype);
1229   void get_polling_page(Register dest, relocInfo::relocType rtype);
1230 
1231   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1232   void update_byte_crc32(Register crc, Register val, Register table);
1233   void update_word_crc32(Register crc, Register v, Register tmp,
1234         Register table0, Register table1, Register table2, Register table3,
1235         bool upper = false);
1236 
1237   address count_positives(Register ary1, Register len, Register result);
1238 
1239   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1240                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1241 
1242   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1243                      int elem_size);
1244 
1245   void fill_words(Register base, Register cnt, Register value);


1246   void zero_words(Register base, uint64_t cnt);
1247   address zero_words(Register ptr, Register cnt);
1248   void zero_dcache_blocks(Register base, Register cnt);
1249 
1250   static const int zero_words_block_size;
1251 
1252   address byte_array_inflate(Register src, Register dst, Register len,
1253                              FloatRegister vtmp1, FloatRegister vtmp2,
1254                              FloatRegister vtmp3, Register tmp4);
1255 
1256   void char_array_compress(Register src, Register dst, Register len,
1257                            Register res,
1258                            FloatRegister vtmp0, FloatRegister vtmp1,
1259                            FloatRegister vtmp2, FloatRegister vtmp3);
1260 
1261   void encode_iso_array(Register src, Register dst,
1262                         Register len, Register res, bool ascii,
1263                         FloatRegister vtmp0, FloatRegister vtmp1,
1264                         FloatRegister vtmp2, FloatRegister vtmp3);
1265 

  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "metaprogramming/enableIf.hpp"
  31 #include "oops/compressedOops.hpp"
  32 #include "runtime/vm_version.hpp"
  33 #include "utilities/macros.hpp"
  34 #include "utilities/powerOfTwo.hpp"
  35 #include "runtime/signature.hpp"
  36 
  37 
  38 class ciInlineKlass;
  39 
  40 // MacroAssembler extends Assembler by frequently used macros.
  41 //
  42 // Instructions for which a 'better' code sequence exists depending
  43 // on arguments should also go in here.
  44 
  45 class MacroAssembler: public Assembler {
  46   friend class LIR_Assembler;
  47 
  48  public:
  49   using Assembler::mov;
  50   using Assembler::movi;
  51 
  52  protected:
  53 
  54   // Support for VM calls
  55   //
  56   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  57   // may customize this version by overriding it for its purposes (e.g., to save/restore
  58   // additional registers when doing a VM call).

 587     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 588   }
 589 
 590   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 591   int corrected_idivl(Register result, Register ra, Register rb,
 592                       bool want_remainder, Register tmp = rscratch1);
 593   int corrected_idivq(Register result, Register ra, Register rb,
 594                       bool want_remainder, Register tmp = rscratch1);
 595 
 596   // Support for NULL-checks
 597   //
 598   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 599   // If the accessed location is M[reg + offset] and the offset is known, provide the
 600   // offset. No explicit code generation is needed if the offset is within a certain
 601   // range (0 <= offset <= page_size).
 602 
 603   virtual void null_check(Register reg, int offset = -1);
 604   static bool needs_explicit_null_check(intptr_t offset);
 605   static bool uses_implicit_null_check(void* address);
 606 
 607   // markWord tests, kills markWord reg
 608   void test_markword_is_inline_type(Register markword, Label& is_inline_type);
 609 
 610   // inlineKlass queries, kills temp_reg
 611   void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type);
 612   void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type);
 613   void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type);
 614 
 615   // Get the default value oop for the given InlineKlass
 616   void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj);
 617   // The empty value oop, for the given InlineKlass ("empty" as in no instance fields)
 618   // get_default_value_oop with extra assertion for empty inline klass
 619   void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj);
 620 
 621   void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
 622   void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
 623   void test_field_is_inlined(Register flags, Register temp_reg, Label& is_flattened);
 624 
 625   // Check oops for special arrays, i.e. flattened and/or null-free
 626   void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
 627   void test_flattened_array_oop(Register klass, Register temp_reg, Label& is_flattened_array);
 628   void test_non_flattened_array_oop(Register oop, Register temp_reg, Label&is_non_flattened_array);
 629   void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
 630   void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
 631 
 632   // Check array klass layout helper for flatten or null-free arrays...
 633   void test_flattened_array_layout(Register lh, Label& is_flattened_array);
 634   void test_non_flattened_array_layout(Register lh, Label& is_non_flattened_array);
 635   void test_null_free_array_layout(Register lh, Label& is_null_free_array);
 636   void test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array);
 637 
 638   static address target_addr_for_insn(address insn_addr, unsigned insn);
 639   static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
 640   static address target_addr_for_insn(address insn_addr) {
 641     unsigned insn = *(unsigned*)insn_addr;
 642     return target_addr_for_insn(insn_addr, insn);
 643   }
 644   static address target_addr_for_insn_or_null(address insn_addr) {
 645     unsigned insn = *(unsigned*)insn_addr;
 646     return target_addr_for_insn_or_null(insn_addr, insn);
 647   }
 648 
 649   // Required platform-specific helpers for Label::patch_instructions.
 650   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 651   static int pd_patch_instruction_size(address branch, address target);
 652   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 653     pd_patch_instruction_size(branch, target);
 654   }
 655   static address pd_call_destination(address branch) {
 656     return target_addr_for_insn(branch);
 657   }

 830                            Register scratch);
 831 
 832   void reset_last_Java_frame(Register thread);
 833 
 834   // thread in the default location (rthread)
 835   void reset_last_Java_frame(bool clear_fp);
 836 
 837   // Stores
 838   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 839   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 840 
 841   void resolve_jobject(Register value, Register thread, Register tmp);
 842 
 843   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 844   void c2bool(Register x);
 845 
 846   void load_method_holder_cld(Register rresult, Register rmethod);
 847   void load_method_holder(Register holder, Register method);
 848 
 849   // oop manipulations
 850   void load_metadata(Register dst, Register src);
 851 
 852   void load_klass(Register dst, Register src);
 853   void store_klass(Register dst, Register src);
 854   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 855 
 856   void resolve_weak_handle(Register result, Register tmp);
 857   void resolve_oop_handle(Register result, Register tmp = r5);
 858   void load_mirror(Register dst, Register method, Register tmp = r5);
 859 
 860   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 861                       Register tmp1, Register tmp_thread);
 862 
 863   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 864                        Register tmp1, Register tmp_thread, Register tmp3 = noreg);
 865 
 866   void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass);
 867 
 868   // inline type data payload offsets...
 869   void first_field_offset(Register inline_klass, Register offset);
 870   void data_for_oop(Register oop, Register data, Register inline_klass);
 871   // get data payload ptr a flat value array at index, kills rcx and index
 872   void data_for_value_array_index(Register array, Register array_klass,
 873                                   Register index, Register data);
 874 
 875   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 876                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 877 
 878   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 879                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 880   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 881                       Register tmp_thread = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
 882 
 883   // currently unimplemented
 884   // Used for storing NULL. All other oop constants should be
 885   // stored using routines that take a jobject.
 886   void store_heap_oop_null(Address dst);
 887 
 888   void load_prototype_header(Register dst, Register src);
 889 
 890   void store_klass_gap(Register dst, Register src);
 891 
 892   // This dummy is to prevent a call to store_heap_oop from
 893   // converting a zero (like NULL) into a Register by giving
 894   // the compiler two choices it can't resolve
 895 
 896   void store_heap_oop(Address dst, void* dummy);
 897 
 898   void encode_heap_oop(Register d, Register s);
 899   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 900   void decode_heap_oop(Register d, Register s);
 901   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 902   void encode_heap_oop_not_null(Register r);
 903   void decode_heap_oop_not_null(Register r);
 904   void encode_heap_oop_not_null(Register dst, Register src);
 905   void decode_heap_oop_not_null(Register dst, Register src);
 906 
 907   void set_narrow_oop(Register dst, jobject obj);
 908 
 909   void encode_klass_not_null(Register r);
 910   void decode_klass_not_null(Register r);
 911   void encode_klass_not_null(Register dst, Register src);
 912   void decode_klass_not_null(Register dst, Register src);
 913 
 914   void set_narrow_klass(Register dst, Klass* k);
 915 
 916   // if heap base register is used - reinit it with the correct value
 917   void reinit_heapbase();
 918 
 919   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 920 
 921   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 922                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 923   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 924                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 925 
 926   // Round up to a power of two
 927   void round_to(Register reg, int modulus);
 928 
 929   // allocation
 930 
 931   // Object / value buffer allocation...
 932   // Allocate instance of klass, assumes klass initialized by caller
 933   // new_obj prefers to be rax
 934   // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
 935   void allocate_instance(Register klass, Register new_obj,
 936                          Register t1, Register t2,
 937                          bool clear_fields, Label& alloc_failed);
 938 
 939   void eden_allocate(
 940     Register obj,                      // result: pointer to object after successful allocation
 941     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 942     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 943     Register t1,                       // temp register
 944     Label&   slow_case                 // continuation point if fast allocation fails
 945   );
 946   void tlab_allocate(
 947     Register obj,                      // result: pointer to object after successful allocation
 948     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 949     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 950     Register t1,                       // temp register
 951     Register t2,                       // temp register
 952     Label&   slow_case                 // continuation point if fast allocation fails
 953   );
 954   void verify_tlab();
 955 
 956   // For field "index" within "klass", return inline_klass ...
 957   void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
 958 
 959   // interface method calling
 960   void lookup_interface_method(Register recv_klass,
 961                                Register intf_klass,
 962                                RegisterOrConstant itable_index,
 963                                Register method_result,
 964                                Register scan_temp,
 965                                Label& no_such_interface,
 966                    bool return_method = true);
 967 
 968   // virtual method calling
 969   // n.b. x86 allows RegisterOrConstant for vtable_index
 970   void lookup_virtual_method(Register recv_klass,
 971                              RegisterOrConstant vtable_index,
 972                              Register method_result);
 973 
 974   // Test sub_klass against super_klass, with fast and slow paths.
 975 
 976   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 977   // One of the three labels can be NULL, meaning take the fall-through.
 978   // If super_check_offset is -1, the value is loaded up from super_klass.

1223   }                                                                     \
1224                                                                         \
1225   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1226     Assembler::INSN(Rd, Rn, Rm);                                        \
1227   }                                                                     \
1228                                                                         \
1229   void INSN(Register Rd, Register Rn, Register Rm,                      \
1230            ext::operation option, int amount = 0) {                     \
1231     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1232   }
1233 
1234   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1235 
1236   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1237   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1238   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1239   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1240 
1241   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1242 
1243   void verified_entry(Compile* C, int sp_inc);
1244 
1245   // Inline type specific methods
1246   #include "asm/macroAssembler_common.hpp"
1247 
1248   int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1249   bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1250   bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1251                             VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1252                             RegState reg_state[]);
1253   bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1254                           VMRegPair* from, int from_count, int& from_index, VMReg to,
1255                           RegState reg_state[], Register val_array);
1256   int extend_stack_for_inline_args(int args_on_stack);
1257   void remove_frame(int initial_framesize, bool needs_stack_repair);
1258   VMReg spill_reg_for(VMReg reg);
1259   void save_stack_increment(int sp_inc, int frame_size);
1260 
1261   void tableswitch(Register index, jint lowbound, jint highbound,
1262                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1263     adr(rscratch1, jumptable);
1264     subsw(rscratch2, index, lowbound);
1265     subsw(zr, rscratch2, highbound - lowbound);
1266     br(Assembler::HS, jumptable_end);
1267     add(rscratch1, rscratch1, rscratch2,
1268         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1269     br(rscratch1);
1270   }
1271 
1272   // Form an address from base + offset in Rd.  Rd may or may not
1273   // actually be used: you must use the Address that is returned.  It
1274   // is up to you to ensure that the shift provided matches the size
1275   // of your data.
1276   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1277 
1278   // Return true iff an address is within the 48-bit AArch64 address
1279   // space.
1280   bool is_valid_AArch64_address(address a) {

1305   }
1306 
1307   address read_polling_page(Register r, relocInfo::relocType rtype);
1308   void get_polling_page(Register dest, relocInfo::relocType rtype);
1309 
1310   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1311   void update_byte_crc32(Register crc, Register val, Register table);
1312   void update_word_crc32(Register crc, Register v, Register tmp,
1313         Register table0, Register table1, Register table2, Register table3,
1314         bool upper = false);
1315 
1316   address count_positives(Register ary1, Register len, Register result);
1317 
1318   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1319                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1320 
1321   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1322                      int elem_size);
1323 
1324   void fill_words(Register base, Register cnt, Register value);
1325   void fill_words(Register base, uint64_t cnt, Register value);
1326 
1327   void zero_words(Register base, uint64_t cnt);
1328   address zero_words(Register ptr, Register cnt);
1329   void zero_dcache_blocks(Register base, Register cnt);
1330 
1331   static const int zero_words_block_size;
1332 
1333   address byte_array_inflate(Register src, Register dst, Register len,
1334                              FloatRegister vtmp1, FloatRegister vtmp2,
1335                              FloatRegister vtmp3, Register tmp4);
1336 
1337   void char_array_compress(Register src, Register dst, Register len,
1338                            Register res,
1339                            FloatRegister vtmp0, FloatRegister vtmp1,
1340                            FloatRegister vtmp2, FloatRegister vtmp3);
1341 
1342   void encode_iso_array(Register src, Register dst,
1343                         Register len, Register res, bool ascii,
1344                         FloatRegister vtmp0, FloatRegister vtmp1,
1345                         FloatRegister vtmp2, FloatRegister vtmp3);
1346 
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