16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/powerOfTwo.hpp"
37
38 class OopMap;
39
40 // MacroAssembler extends Assembler by frequently used macros.
41 //
42 // Instructions for which a 'better' code sequence exists depending
43 // on arguments should also go in here.
44
45 class MacroAssembler: public Assembler {
46 friend class LIR_Assembler;
47
48 public:
49 using Assembler::mov;
50 using Assembler::movi;
51
52 protected:
53
54 // Support for VM calls
55 //
56 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
659 msr(0b011, 0b0100, 0b0010, 0b000, reg);
660 }
661
662 // idiv variant which deals with MINLONG as dividend and -1 as divisor
663 int corrected_idivl(Register result, Register ra, Register rb,
664 bool want_remainder, Register tmp = rscratch1);
665 int corrected_idivq(Register result, Register ra, Register rb,
666 bool want_remainder, Register tmp = rscratch1);
667
668 // Support for null-checks
669 //
670 // Generates code that causes a null OS exception if the content of reg is null.
671 // If the accessed location is M[reg + offset] and the offset is known, provide the
672 // offset. No explicit code generation is needed if the offset is within a certain
673 // range (0 <= offset <= page_size).
674
675 virtual void null_check(Register reg, int offset = -1);
676 static bool needs_explicit_null_check(intptr_t offset);
677 static bool uses_implicit_null_check(void* address);
678
679 static address target_addr_for_insn(address insn_addr, unsigned insn);
680 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
681 static address target_addr_for_insn(address insn_addr) {
682 unsigned insn = *(unsigned*)insn_addr;
683 return target_addr_for_insn(insn_addr, insn);
684 }
685 static address target_addr_for_insn_or_null(address insn_addr) {
686 unsigned insn = *(unsigned*)insn_addr;
687 return target_addr_for_insn_or_null(insn_addr, insn);
688 }
689
690 // Required platform-specific helpers for Label::patch_instructions.
691 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
692 static int pd_patch_instruction_size(address branch, address target);
693 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
694 pd_patch_instruction_size(branch, target);
695 }
696 static address pd_call_destination(address branch) {
697 return target_addr_for_insn(branch);
698 }
896
897 void reset_last_Java_frame(Register thread);
898
899 // thread in the default location (rthread)
900 void reset_last_Java_frame(bool clear_fp);
901
902 // Stores
903 void store_check(Register obj); // store check for obj - register is destroyed afterwards
904 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
905
906 void resolve_jobject(Register value, Register tmp1, Register tmp2);
907 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
908
909 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
910 void c2bool(Register x);
911
912 void load_method_holder_cld(Register rresult, Register rmethod);
913 void load_method_holder(Register holder, Register method);
914
915 // oop manipulations
916 void load_narrow_klass_compact(Register dst, Register src);
917 void load_klass(Register dst, Register src);
918 void store_klass(Register dst, Register src);
919 void cmp_klass(Register obj, Register klass, Register tmp);
920 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
921
922 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
923 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
924 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
925
926 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
927 Register tmp1, Register tmp2);
928
929 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
930 Register tmp1, Register tmp2, Register tmp3);
931
932 void load_heap_oop(Register dst, Address src, Register tmp1,
933 Register tmp2, DecoratorSet decorators = 0);
934
935 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
936 Register tmp2, DecoratorSet decorators = 0);
937 void store_heap_oop(Address dst, Register val, Register tmp1,
938 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
939
940 // currently unimplemented
941 // Used for storing null. All other oop constants should be
942 // stored using routines that take a jobject.
943 void store_heap_oop_null(Address dst);
944
945 void store_klass_gap(Register dst, Register src);
946
947 // This dummy is to prevent a call to store_heap_oop from
948 // converting a zero (like null) into a Register by giving
949 // the compiler two choices it can't resolve
950
951 void store_heap_oop(Address dst, void* dummy);
952
953 void encode_heap_oop(Register d, Register s);
954 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
955 void decode_heap_oop(Register d, Register s);
956 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
957 void encode_heap_oop_not_null(Register r);
958 void decode_heap_oop_not_null(Register r);
959 void encode_heap_oop_not_null(Register dst, Register src);
960 void decode_heap_oop_not_null(Register dst, Register src);
961
962 void set_narrow_oop(Register dst, jobject obj);
963
964 void decode_klass_not_null_for_aot(Register dst, Register src);
974 void reinit_heapbase();
975
976 DEBUG_ONLY(void verify_heapbase(const char* msg);)
977
978 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
979 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
980 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
981 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
982
983 void push_cont_fastpath(Register java_thread = rthread);
984 void pop_cont_fastpath(Register java_thread = rthread);
985
986 // Round up to a power of two
987 void round_to(Register reg, int modulus);
988
989 // java.lang.Math::round intrinsics
990 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
991 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
992
993 // allocation
994 void tlab_allocate(
995 Register obj, // result: pointer to object after successful allocation
996 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
997 int con_size_in_bytes, // object size in bytes if known at compile time
998 Register t1, // temp register
999 Register t2, // temp register
1000 Label& slow_case // continuation point if fast allocation fails
1001 );
1002 void verify_tlab();
1003
1004 // interface method calling
1005 void lookup_interface_method(Register recv_klass,
1006 Register intf_klass,
1007 RegisterOrConstant itable_index,
1008 Register method_result,
1009 Register scan_temp,
1010 Label& no_such_interface,
1011 bool return_method = true);
1012
1013 void lookup_interface_method_stub(Register recv_klass,
1014 Register holder_klass,
1015 Register resolved_klass,
1016 Register method_result,
1017 Register temp_reg,
1018 Register temp_reg2,
1019 int itable_index,
1020 Label& L_no_such_interface);
1021
1022 // virtual method calling
1023 // n.b. x86 allows RegisterOrConstant for vtable_index
1449 } \
1450 \
1451 void INSN(Register Rd, Register Rn, Register Rm) { \
1452 Assembler::INSN(Rd, Rn, Rm); \
1453 } \
1454 \
1455 void INSN(Register Rd, Register Rn, Register Rm, \
1456 ext::operation option, int amount = 0) { \
1457 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1458 }
1459
1460 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1461
1462 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1463 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1464 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1465 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1466
1467 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1468
1469 void tableswitch(Register index, jint lowbound, jint highbound,
1470 Label &jumptable, Label &jumptable_end, int stride = 1) {
1471 adr(rscratch1, jumptable);
1472 subsw(rscratch2, index, lowbound);
1473 subsw(zr, rscratch2, highbound - lowbound);
1474 br(Assembler::HS, jumptable_end);
1475 add(rscratch1, rscratch1, rscratch2,
1476 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1477 br(rscratch1);
1478 }
1479
1480 // Form an address from base + offset in Rd. Rd may or may not
1481 // actually be used: you must use the Address that is returned. It
1482 // is up to you to ensure that the shift provided matches the size
1483 // of your data.
1484 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1485
1486 // Return true iff an address is within the 48-bit AArch64 address
1487 // space.
1488 bool is_valid_AArch64_address(address a) {
1520 #define ARRAYS_HASHCODE_REGISTERS \
1521 do { \
1522 assert(result == r0 && \
1523 ary == r1 && \
1524 cnt == r2 && \
1525 vdata0 == v3 && \
1526 vdata1 == v2 && \
1527 vdata2 == v1 && \
1528 vdata3 == v0 && \
1529 vmul0 == v4 && \
1530 vmul1 == v5 && \
1531 vmul2 == v6 && \
1532 vmul3 == v7 && \
1533 vpow == v12 && \
1534 vpowm == v13, "registers must match aarch64.ad"); \
1535 } while (0)
1536
1537 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1538
1539 void fill_words(Register base, Register cnt, Register value);
1540 address zero_words(Register base, uint64_t cnt);
1541 address zero_words(Register ptr, Register cnt);
1542 void zero_dcache_blocks(Register base, Register cnt);
1543
1544 static const int zero_words_block_size;
1545
1546 address byte_array_inflate(Register src, Register dst, Register len,
1547 FloatRegister vtmp1, FloatRegister vtmp2,
1548 FloatRegister vtmp3, Register tmp4);
1549
1550 void char_array_compress(Register src, Register dst, Register len,
1551 Register res,
1552 FloatRegister vtmp0, FloatRegister vtmp1,
1553 FloatRegister vtmp2, FloatRegister vtmp3,
1554 FloatRegister vtmp4, FloatRegister vtmp5);
1555
1556 void encode_iso_array(Register src, Register dst,
1557 Register len, Register res, bool ascii,
1558 FloatRegister vtmp0, FloatRegister vtmp1,
1559 FloatRegister vtmp2, FloatRegister vtmp3,
|
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/macros.hpp"
37 #include "utilities/powerOfTwo.hpp"
38 #include "runtime/signature.hpp"
39
40
41 class ciInlineKlass;
42
43 class OopMap;
44
45 // MacroAssembler extends Assembler by frequently used macros.
46 //
47 // Instructions for which a 'better' code sequence exists depending
48 // on arguments should also go in here.
49
50 class MacroAssembler: public Assembler {
51 friend class LIR_Assembler;
52
53 public:
54 using Assembler::mov;
55 using Assembler::movi;
56
57 protected:
58
59 // Support for VM calls
60 //
61 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
664 msr(0b011, 0b0100, 0b0010, 0b000, reg);
665 }
666
667 // idiv variant which deals with MINLONG as dividend and -1 as divisor
668 int corrected_idivl(Register result, Register ra, Register rb,
669 bool want_remainder, Register tmp = rscratch1);
670 int corrected_idivq(Register result, Register ra, Register rb,
671 bool want_remainder, Register tmp = rscratch1);
672
673 // Support for null-checks
674 //
675 // Generates code that causes a null OS exception if the content of reg is null.
676 // If the accessed location is M[reg + offset] and the offset is known, provide the
677 // offset. No explicit code generation is needed if the offset is within a certain
678 // range (0 <= offset <= page_size).
679
680 virtual void null_check(Register reg, int offset = -1);
681 static bool needs_explicit_null_check(intptr_t offset);
682 static bool uses_implicit_null_check(void* address);
683
684 // markWord tests, kills markWord reg
685 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
686
687 // inlineKlass queries, kills temp_reg
688 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
689
690 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
691 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
692 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
693 void test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker);
694
695 // Check oops for special arrays, i.e. flat arrays and/or null-free arrays
696 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
697 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
698 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
699 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
700 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
701
702 // Check array klass layout helper for flat or null-free arrays...
703 void test_flat_array_layout(Register lh, Label& is_flat_array);
704 void test_non_flat_array_layout(Register lh, Label& is_non_flat_array);
705
706 static address target_addr_for_insn(address insn_addr, unsigned insn);
707 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
708 static address target_addr_for_insn(address insn_addr) {
709 unsigned insn = *(unsigned*)insn_addr;
710 return target_addr_for_insn(insn_addr, insn);
711 }
712 static address target_addr_for_insn_or_null(address insn_addr) {
713 unsigned insn = *(unsigned*)insn_addr;
714 return target_addr_for_insn_or_null(insn_addr, insn);
715 }
716
717 // Required platform-specific helpers for Label::patch_instructions.
718 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
719 static int pd_patch_instruction_size(address branch, address target);
720 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
721 pd_patch_instruction_size(branch, target);
722 }
723 static address pd_call_destination(address branch) {
724 return target_addr_for_insn(branch);
725 }
923
924 void reset_last_Java_frame(Register thread);
925
926 // thread in the default location (rthread)
927 void reset_last_Java_frame(bool clear_fp);
928
929 // Stores
930 void store_check(Register obj); // store check for obj - register is destroyed afterwards
931 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
932
933 void resolve_jobject(Register value, Register tmp1, Register tmp2);
934 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
935
936 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
937 void c2bool(Register x);
938
939 void load_method_holder_cld(Register rresult, Register rmethod);
940 void load_method_holder(Register holder, Register method);
941
942 // oop manipulations
943 void load_metadata(Register dst, Register src);
944
945 void load_narrow_klass_compact(Register dst, Register src);
946 void load_klass(Register dst, Register src);
947 void store_klass(Register dst, Register src);
948 void cmp_klass(Register obj, Register klass, Register tmp);
949 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
950
951 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
952 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
953 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
954
955 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
956 Register tmp1, Register tmp2);
957
958 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
959 Register tmp1, Register tmp2, Register tmp3);
960
961 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
962
963 // inline type data payload offsets...
964 void payload_offset(Register inline_klass, Register offset);
965 void payload_address(Register oop, Register data, Register inline_klass);
966 // get data payload ptr a flat value array at index, kills rcx and index
967 void data_for_value_array_index(Register array, Register array_klass,
968 Register index, Register data);
969
970 void load_heap_oop(Register dst, Address src, Register tmp1,
971 Register tmp2, DecoratorSet decorators = 0);
972
973 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
974 Register tmp2, DecoratorSet decorators = 0);
975 void store_heap_oop(Address dst, Register val, Register tmp1,
976 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
977
978 // currently unimplemented
979 // Used for storing null. All other oop constants should be
980 // stored using routines that take a jobject.
981 void store_heap_oop_null(Address dst);
982
983 void load_prototype_header(Register dst, Register src);
984
985 void store_klass_gap(Register dst, Register src);
986
987 // This dummy is to prevent a call to store_heap_oop from
988 // converting a zero (like null) into a Register by giving
989 // the compiler two choices it can't resolve
990
991 void store_heap_oop(Address dst, void* dummy);
992
993 void encode_heap_oop(Register d, Register s);
994 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
995 void decode_heap_oop(Register d, Register s);
996 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
997 void encode_heap_oop_not_null(Register r);
998 void decode_heap_oop_not_null(Register r);
999 void encode_heap_oop_not_null(Register dst, Register src);
1000 void decode_heap_oop_not_null(Register dst, Register src);
1001
1002 void set_narrow_oop(Register dst, jobject obj);
1003
1004 void decode_klass_not_null_for_aot(Register dst, Register src);
1014 void reinit_heapbase();
1015
1016 DEBUG_ONLY(void verify_heapbase(const char* msg);)
1017
1018 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
1019 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1020 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
1021 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
1022
1023 void push_cont_fastpath(Register java_thread = rthread);
1024 void pop_cont_fastpath(Register java_thread = rthread);
1025
1026 // Round up to a power of two
1027 void round_to(Register reg, int modulus);
1028
1029 // java.lang.Math::round intrinsics
1030 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1031 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1032
1033 // allocation
1034
1035 // Object / value buffer allocation...
1036 // Allocate instance of klass, assumes klass initialized by caller
1037 // new_obj prefers to be rax
1038 // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
1039 void allocate_instance(Register klass, Register new_obj,
1040 Register t1, Register t2,
1041 bool clear_fields, Label& alloc_failed);
1042
1043 void tlab_allocate(
1044 Register obj, // result: pointer to object after successful allocation
1045 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1046 int con_size_in_bytes, // object size in bytes if known at compile time
1047 Register t1, // temp register
1048 Register t2, // temp register
1049 Label& slow_case // continuation point if fast allocation fails
1050 );
1051 void verify_tlab();
1052
1053 // For field "index" within "klass", return inline_klass ...
1054 void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
1055 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
1056
1057
1058 // interface method calling
1059 void lookup_interface_method(Register recv_klass,
1060 Register intf_klass,
1061 RegisterOrConstant itable_index,
1062 Register method_result,
1063 Register scan_temp,
1064 Label& no_such_interface,
1065 bool return_method = true);
1066
1067 void lookup_interface_method_stub(Register recv_klass,
1068 Register holder_klass,
1069 Register resolved_klass,
1070 Register method_result,
1071 Register temp_reg,
1072 Register temp_reg2,
1073 int itable_index,
1074 Label& L_no_such_interface);
1075
1076 // virtual method calling
1077 // n.b. x86 allows RegisterOrConstant for vtable_index
1503 } \
1504 \
1505 void INSN(Register Rd, Register Rn, Register Rm) { \
1506 Assembler::INSN(Rd, Rn, Rm); \
1507 } \
1508 \
1509 void INSN(Register Rd, Register Rn, Register Rm, \
1510 ext::operation option, int amount = 0) { \
1511 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1512 }
1513
1514 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1515
1516 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1517 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1518 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1519 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1520
1521 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1522
1523 void verified_entry(Compile* C, int sp_inc);
1524
1525 // Inline type specific methods
1526 #include "asm/macroAssembler_common.hpp"
1527
1528 int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1529 bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1530 bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1531 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1532 RegState reg_state[]);
1533 bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1534 VMRegPair* from, int from_count, int& from_index, VMReg to,
1535 RegState reg_state[], Register val_array);
1536 int extend_stack_for_inline_args(int args_on_stack);
1537 void remove_frame(int initial_framesize, bool needs_stack_repair);
1538 VMReg spill_reg_for(VMReg reg);
1539 void save_stack_increment(int sp_inc, int frame_size);
1540
1541 void tableswitch(Register index, jint lowbound, jint highbound,
1542 Label &jumptable, Label &jumptable_end, int stride = 1) {
1543 adr(rscratch1, jumptable);
1544 subsw(rscratch2, index, lowbound);
1545 subsw(zr, rscratch2, highbound - lowbound);
1546 br(Assembler::HS, jumptable_end);
1547 add(rscratch1, rscratch1, rscratch2,
1548 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1549 br(rscratch1);
1550 }
1551
1552 // Form an address from base + offset in Rd. Rd may or may not
1553 // actually be used: you must use the Address that is returned. It
1554 // is up to you to ensure that the shift provided matches the size
1555 // of your data.
1556 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1557
1558 // Return true iff an address is within the 48-bit AArch64 address
1559 // space.
1560 bool is_valid_AArch64_address(address a) {
1592 #define ARRAYS_HASHCODE_REGISTERS \
1593 do { \
1594 assert(result == r0 && \
1595 ary == r1 && \
1596 cnt == r2 && \
1597 vdata0 == v3 && \
1598 vdata1 == v2 && \
1599 vdata2 == v1 && \
1600 vdata3 == v0 && \
1601 vmul0 == v4 && \
1602 vmul1 == v5 && \
1603 vmul2 == v6 && \
1604 vmul3 == v7 && \
1605 vpow == v12 && \
1606 vpowm == v13, "registers must match aarch64.ad"); \
1607 } while (0)
1608
1609 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1610
1611 void fill_words(Register base, Register cnt, Register value);
1612 void fill_words(Register base, uint64_t cnt, Register value);
1613
1614 address zero_words(Register base, uint64_t cnt);
1615 address zero_words(Register ptr, Register cnt);
1616 void zero_dcache_blocks(Register base, Register cnt);
1617
1618 static const int zero_words_block_size;
1619
1620 address byte_array_inflate(Register src, Register dst, Register len,
1621 FloatRegister vtmp1, FloatRegister vtmp2,
1622 FloatRegister vtmp3, Register tmp4);
1623
1624 void char_array_compress(Register src, Register dst, Register len,
1625 Register res,
1626 FloatRegister vtmp0, FloatRegister vtmp1,
1627 FloatRegister vtmp2, FloatRegister vtmp3,
1628 FloatRegister vtmp4, FloatRegister vtmp5);
1629
1630 void encode_iso_array(Register src, Register dst,
1631 Register len, Register res, bool ascii,
1632 FloatRegister vtmp0, FloatRegister vtmp1,
1633 FloatRegister vtmp2, FloatRegister vtmp3,
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