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src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp

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  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "oops/compressedOops.hpp"
  31 #include "runtime/vm_version.hpp"

  32 #include "utilities/powerOfTwo.hpp"




  33 
  34 // MacroAssembler extends Assembler by frequently used macros.
  35 //
  36 // Instructions for which a 'better' code sequence exists depending
  37 // on arguments should also go in here.
  38 
  39 class MacroAssembler: public Assembler {
  40   friend class LIR_Assembler;
  41 
  42  public:
  43   using Assembler::mov;
  44   using Assembler::movi;
  45 
  46  protected:
  47 
  48   // Support for VM calls
  49   //
  50   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  51   // may customize this version by overriding it for its purposes (e.g., to save/restore
  52   // additional registers when doing a VM call).

 582     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 583   }
 584 
 585   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 586   int corrected_idivl(Register result, Register ra, Register rb,
 587                       bool want_remainder, Register tmp = rscratch1);
 588   int corrected_idivq(Register result, Register ra, Register rb,
 589                       bool want_remainder, Register tmp = rscratch1);
 590 
 591   // Support for NULL-checks
 592   //
 593   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 594   // If the accessed location is M[reg + offset] and the offset is known, provide the
 595   // offset. No explicit code generation is needed if the offset is within a certain
 596   // range (0 <= offset <= page_size).
 597 
 598   virtual void null_check(Register reg, int offset = -1);
 599   static bool needs_explicit_null_check(intptr_t offset);
 600   static bool uses_implicit_null_check(void* address);
 601 































 602   static address target_addr_for_insn(address insn_addr, unsigned insn);
 603   static address target_addr_for_insn(address insn_addr) {
 604     unsigned insn = *(unsigned*)insn_addr;
 605     return target_addr_for_insn(insn_addr, insn);
 606   }
 607 
 608   // Required platform-specific helpers for Label::patch_instructions.
 609   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 610   static int pd_patch_instruction_size(address branch, address target);
 611   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 612     pd_patch_instruction_size(branch, target);
 613   }
 614   static address pd_call_destination(address branch) {
 615     return target_addr_for_insn(branch);
 616   }
 617 #ifndef PRODUCT
 618   static void pd_print_patched_instruction(address branch);
 619 #endif
 620 
 621   static int patch_oop(address insn_addr, address o);

 789                            Register scratch);
 790 
 791   void reset_last_Java_frame(Register thread);
 792 
 793   // thread in the default location (rthread)
 794   void reset_last_Java_frame(bool clear_fp);
 795 
 796   // Stores
 797   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 798   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 799 
 800   void resolve_jobject(Register value, Register thread, Register tmp);
 801 
 802   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 803   void c2bool(Register x);
 804 
 805   void load_method_holder_cld(Register rresult, Register rmethod);
 806   void load_method_holder(Register holder, Register method);
 807 
 808   // oop manipulations


 809   void load_klass(Register dst, Register src);
 810   void store_klass(Register dst, Register src);
 811   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 812 
 813   void resolve_weak_handle(Register result, Register tmp);
 814   void resolve_oop_handle(Register result, Register tmp = r5);
 815   void load_mirror(Register dst, Register method, Register tmp = r5);
 816 
 817   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 818                       Register tmp1, Register tmp_thread);
 819 
 820   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 821                        Register tmp1, Register tmp_thread);









 822 
 823   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 824                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 825 
 826   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 827                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 828   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 829                       Register tmp_thread = noreg, DecoratorSet decorators = 0);
 830 
 831   // currently unimplemented
 832   // Used for storing NULL. All other oop constants should be
 833   // stored using routines that take a jobject.
 834   void store_heap_oop_null(Address dst);
 835 


 836   void store_klass_gap(Register dst, Register src);
 837 
 838   // This dummy is to prevent a call to store_heap_oop from
 839   // converting a zero (like NULL) into a Register by giving
 840   // the compiler two choices it can't resolve
 841 
 842   void store_heap_oop(Address dst, void* dummy);
 843 
 844   void encode_heap_oop(Register d, Register s);
 845   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 846   void decode_heap_oop(Register d, Register s);
 847   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 848   void encode_heap_oop_not_null(Register r);
 849   void decode_heap_oop_not_null(Register r);
 850   void encode_heap_oop_not_null(Register dst, Register src);
 851   void decode_heap_oop_not_null(Register dst, Register src);
 852 
 853   void set_narrow_oop(Register dst, jobject obj);
 854 
 855   void encode_klass_not_null(Register r);
 856   void decode_klass_not_null(Register r);
 857   void encode_klass_not_null(Register dst, Register src);
 858   void decode_klass_not_null(Register dst, Register src);
 859 
 860   void set_narrow_klass(Register dst, Klass* k);
 861 
 862   // if heap base register is used - reinit it with the correct value
 863   void reinit_heapbase();
 864 
 865   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 866 
 867   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 868                       int sve_vector_size_in_bytes = 0);
 869   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 870                       int sve_vector_size_in_bytes = 0);
 871 
 872   // Round up to a power of two
 873   void round_to(Register reg, int modulus);
 874 
 875   // allocation









 876   void eden_allocate(
 877     Register obj,                      // result: pointer to object after successful allocation
 878     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 879     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 880     Register t1,                       // temp register
 881     Label&   slow_case                 // continuation point if fast allocation fails
 882   );
 883   void tlab_allocate(
 884     Register obj,                      // result: pointer to object after successful allocation
 885     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 886     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 887     Register t1,                       // temp register
 888     Register t2,                       // temp register
 889     Label&   slow_case                 // continuation point if fast allocation fails
 890   );
 891   void verify_tlab();
 892 



 893   // interface method calling
 894   void lookup_interface_method(Register recv_klass,
 895                                Register intf_klass,
 896                                RegisterOrConstant itable_index,
 897                                Register method_result,
 898                                Register scan_temp,
 899                                Label& no_such_interface,
 900                    bool return_method = true);
 901 
 902   // virtual method calling
 903   // n.b. x86 allows RegisterOrConstant for vtable_index
 904   void lookup_virtual_method(Register recv_klass,
 905                              RegisterOrConstant vtable_index,
 906                              Register method_result);
 907 
 908   // Test sub_klass against super_klass, with fast and slow paths.
 909 
 910   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 911   // One of the three labels can be NULL, meaning take the fall-through.
 912   // If super_check_offset is -1, the value is loaded up from super_klass.

1161   }                                                                     \
1162                                                                         \
1163   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1164     Assembler::INSN(Rd, Rn, Rm);                                        \
1165   }                                                                     \
1166                                                                         \
1167   void INSN(Register Rd, Register Rn, Register Rm,                      \
1168            ext::operation option, int amount = 0) {                     \
1169     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1170   }
1171 
1172   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1173 
1174   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1175   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1176   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1177   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1178 
1179   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1180 


















1181   void tableswitch(Register index, jint lowbound, jint highbound,
1182                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1183     adr(rscratch1, jumptable);
1184     subsw(rscratch2, index, lowbound);
1185     subsw(zr, rscratch2, highbound - lowbound);
1186     br(Assembler::HS, jumptable_end);
1187     add(rscratch1, rscratch1, rscratch2,
1188         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1189     br(rscratch1);
1190   }
1191 
1192   // Form an address from base + offset in Rd.  Rd may or may not
1193   // actually be used: you must use the Address that is returned.  It
1194   // is up to you to ensure that the shift provided matches the size
1195   // of your data.
1196   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1197 
1198   // Return true iff an address is within the 48-bit AArch64 address
1199   // space.
1200   bool is_valid_AArch64_address(address a) {

1225   }
1226 
1227   address read_polling_page(Register r, relocInfo::relocType rtype);
1228   void get_polling_page(Register dest, relocInfo::relocType rtype);
1229 
1230   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1231   void update_byte_crc32(Register crc, Register val, Register table);
1232   void update_word_crc32(Register crc, Register v, Register tmp,
1233         Register table0, Register table1, Register table2, Register table3,
1234         bool upper = false);
1235 
1236   address has_negatives(Register ary1, Register len, Register result);
1237 
1238   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1239                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1240 
1241   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1242                      int elem_size);
1243 
1244   void fill_words(Register base, Register cnt, Register value);


1245   void zero_words(Register base, uint64_t cnt);
1246   address zero_words(Register ptr, Register cnt);
1247   void zero_dcache_blocks(Register base, Register cnt);
1248 
1249   static const int zero_words_block_size;
1250 
1251   address byte_array_inflate(Register src, Register dst, Register len,
1252                              FloatRegister vtmp1, FloatRegister vtmp2,
1253                              FloatRegister vtmp3, Register tmp4);
1254 
1255   void char_array_compress(Register src, Register dst, Register len,
1256                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1257                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1258                            Register result);
1259 
1260   void encode_iso_array(Register src, Register dst,
1261                         Register len, Register result,
1262                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1263                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1264   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,

  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "oops/compressedOops.hpp"
  31 #include "runtime/vm_version.hpp"
  32 #include "utilities/macros.hpp"
  33 #include "utilities/powerOfTwo.hpp"
  34 #include "runtime/signature.hpp"
  35 
  36 
  37 class ciInlineKlass;
  38 
  39 // MacroAssembler extends Assembler by frequently used macros.
  40 //
  41 // Instructions for which a 'better' code sequence exists depending
  42 // on arguments should also go in here.
  43 
  44 class MacroAssembler: public Assembler {
  45   friend class LIR_Assembler;
  46 
  47  public:
  48   using Assembler::mov;
  49   using Assembler::movi;
  50 
  51  protected:
  52 
  53   // Support for VM calls
  54   //
  55   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  56   // may customize this version by overriding it for its purposes (e.g., to save/restore
  57   // additional registers when doing a VM call).

 587     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 588   }
 589 
 590   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 591   int corrected_idivl(Register result, Register ra, Register rb,
 592                       bool want_remainder, Register tmp = rscratch1);
 593   int corrected_idivq(Register result, Register ra, Register rb,
 594                       bool want_remainder, Register tmp = rscratch1);
 595 
 596   // Support for NULL-checks
 597   //
 598   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 599   // If the accessed location is M[reg + offset] and the offset is known, provide the
 600   // offset. No explicit code generation is needed if the offset is within a certain
 601   // range (0 <= offset <= page_size).
 602 
 603   virtual void null_check(Register reg, int offset = -1);
 604   static bool needs_explicit_null_check(intptr_t offset);
 605   static bool uses_implicit_null_check(void* address);
 606 
 607   // markWord tests, kills markWord reg
 608   void test_markword_is_inline_type(Register markword, Label& is_inline_type);
 609 
 610   // inlineKlass queries, kills temp_reg
 611   void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type);
 612   void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type);
 613   void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type);
 614 
 615   // Get the default value oop for the given InlineKlass
 616   void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj);
 617   // The empty value oop, for the given InlineKlass ("empty" as in no instance fields)
 618   // get_default_value_oop with extra assertion for empty inline klass
 619   void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj);
 620 
 621   void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
 622   void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
 623   void test_field_is_inlined(Register flags, Register temp_reg, Label& is_flattened);
 624 
 625   // Check oops for special arrays, i.e. flattened and/or null-free
 626   void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
 627   void test_flattened_array_oop(Register klass, Register temp_reg, Label& is_flattened_array);
 628   void test_non_flattened_array_oop(Register oop, Register temp_reg, Label&is_non_flattened_array);
 629   void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
 630   void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
 631 
 632   // Check array klass layout helper for flatten or null-free arrays...
 633   void test_flattened_array_layout(Register lh, Label& is_flattened_array);
 634   void test_non_flattened_array_layout(Register lh, Label& is_non_flattened_array);
 635   void test_null_free_array_layout(Register lh, Label& is_null_free_array);
 636   void test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array);
 637 
 638   static address target_addr_for_insn(address insn_addr, unsigned insn);
 639   static address target_addr_for_insn(address insn_addr) {
 640     unsigned insn = *(unsigned*)insn_addr;
 641     return target_addr_for_insn(insn_addr, insn);
 642   }
 643 
 644   // Required platform-specific helpers for Label::patch_instructions.
 645   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 646   static int pd_patch_instruction_size(address branch, address target);
 647   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 648     pd_patch_instruction_size(branch, target);
 649   }
 650   static address pd_call_destination(address branch) {
 651     return target_addr_for_insn(branch);
 652   }
 653 #ifndef PRODUCT
 654   static void pd_print_patched_instruction(address branch);
 655 #endif
 656 
 657   static int patch_oop(address insn_addr, address o);

 825                            Register scratch);
 826 
 827   void reset_last_Java_frame(Register thread);
 828 
 829   // thread in the default location (rthread)
 830   void reset_last_Java_frame(bool clear_fp);
 831 
 832   // Stores
 833   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 834   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 835 
 836   void resolve_jobject(Register value, Register thread, Register tmp);
 837 
 838   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 839   void c2bool(Register x);
 840 
 841   void load_method_holder_cld(Register rresult, Register rmethod);
 842   void load_method_holder(Register holder, Register method);
 843 
 844   // oop manipulations
 845   void load_metadata(Register dst, Register src);
 846 
 847   void load_klass(Register dst, Register src);
 848   void store_klass(Register dst, Register src);
 849   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 850 
 851   void resolve_weak_handle(Register result, Register tmp);
 852   void resolve_oop_handle(Register result, Register tmp = r5);
 853   void load_mirror(Register dst, Register method, Register tmp = r5);
 854 
 855   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 856                       Register tmp1, Register tmp_thread);
 857 
 858   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 859                        Register tmp1, Register tmp_thread, Register tmp3 = noreg);
 860 
 861   void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass);
 862 
 863   // inline type data payload offsets...
 864   void first_field_offset(Register inline_klass, Register offset);
 865   void data_for_oop(Register oop, Register data, Register inline_klass);
 866   // get data payload ptr a flat value array at index, kills rcx and index
 867   void data_for_value_array_index(Register array, Register array_klass,
 868                                   Register index, Register data);
 869 
 870   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 871                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 872 
 873   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 874                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 875   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 876                       Register tmp_thread = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
 877 
 878   // currently unimplemented
 879   // Used for storing NULL. All other oop constants should be
 880   // stored using routines that take a jobject.
 881   void store_heap_oop_null(Address dst);
 882 
 883   void load_prototype_header(Register dst, Register src);
 884 
 885   void store_klass_gap(Register dst, Register src);
 886 
 887   // This dummy is to prevent a call to store_heap_oop from
 888   // converting a zero (like NULL) into a Register by giving
 889   // the compiler two choices it can't resolve
 890 
 891   void store_heap_oop(Address dst, void* dummy);
 892 
 893   void encode_heap_oop(Register d, Register s);
 894   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 895   void decode_heap_oop(Register d, Register s);
 896   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 897   void encode_heap_oop_not_null(Register r);
 898   void decode_heap_oop_not_null(Register r);
 899   void encode_heap_oop_not_null(Register dst, Register src);
 900   void decode_heap_oop_not_null(Register dst, Register src);
 901 
 902   void set_narrow_oop(Register dst, jobject obj);
 903 
 904   void encode_klass_not_null(Register r);
 905   void decode_klass_not_null(Register r);
 906   void encode_klass_not_null(Register dst, Register src);
 907   void decode_klass_not_null(Register dst, Register src);
 908 
 909   void set_narrow_klass(Register dst, Klass* k);
 910 
 911   // if heap base register is used - reinit it with the correct value
 912   void reinit_heapbase();
 913 
 914   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 915 
 916   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 917                       int sve_vector_size_in_bytes = 0);
 918   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 919                       int sve_vector_size_in_bytes = 0);
 920 
 921   // Round up to a power of two
 922   void round_to(Register reg, int modulus);
 923 
 924   // allocation
 925 
 926   // Object / value buffer allocation...
 927   // Allocate instance of klass, assumes klass initialized by caller
 928   // new_obj prefers to be rax
 929   // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
 930   void allocate_instance(Register klass, Register new_obj,
 931                          Register t1, Register t2,
 932                          bool clear_fields, Label& alloc_failed);
 933 
 934   void eden_allocate(
 935     Register obj,                      // result: pointer to object after successful allocation
 936     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 937     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 938     Register t1,                       // temp register
 939     Label&   slow_case                 // continuation point if fast allocation fails
 940   );
 941   void tlab_allocate(
 942     Register obj,                      // result: pointer to object after successful allocation
 943     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 944     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 945     Register t1,                       // temp register
 946     Register t2,                       // temp register
 947     Label&   slow_case                 // continuation point if fast allocation fails
 948   );
 949   void verify_tlab();
 950 
 951   // For field "index" within "klass", return inline_klass ...
 952   void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
 953 
 954   // interface method calling
 955   void lookup_interface_method(Register recv_klass,
 956                                Register intf_klass,
 957                                RegisterOrConstant itable_index,
 958                                Register method_result,
 959                                Register scan_temp,
 960                                Label& no_such_interface,
 961                    bool return_method = true);
 962 
 963   // virtual method calling
 964   // n.b. x86 allows RegisterOrConstant for vtable_index
 965   void lookup_virtual_method(Register recv_klass,
 966                              RegisterOrConstant vtable_index,
 967                              Register method_result);
 968 
 969   // Test sub_klass against super_klass, with fast and slow paths.
 970 
 971   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 972   // One of the three labels can be NULL, meaning take the fall-through.
 973   // If super_check_offset is -1, the value is loaded up from super_klass.

1222   }                                                                     \
1223                                                                         \
1224   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1225     Assembler::INSN(Rd, Rn, Rm);                                        \
1226   }                                                                     \
1227                                                                         \
1228   void INSN(Register Rd, Register Rn, Register Rm,                      \
1229            ext::operation option, int amount = 0) {                     \
1230     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1231   }
1232 
1233   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1234 
1235   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1236   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1237   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1238   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1239 
1240   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1241 
1242   void verified_entry(Compile* C, int sp_inc);
1243 
1244   // Inline type specific methods
1245   #include "asm/macroAssembler_common.hpp"
1246 
1247   int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1248   bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1249   bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1250                             VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1251                             RegState reg_state[]);
1252   bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1253                           VMRegPair* from, int from_count, int& from_index, VMReg to,
1254                           RegState reg_state[], Register val_array);
1255   int extend_stack_for_inline_args(int args_on_stack);
1256   void remove_frame(int initial_framesize, bool needs_stack_repair);
1257   VMReg spill_reg_for(VMReg reg);
1258   void save_stack_increment(int sp_inc, int frame_size);
1259 
1260   void tableswitch(Register index, jint lowbound, jint highbound,
1261                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1262     adr(rscratch1, jumptable);
1263     subsw(rscratch2, index, lowbound);
1264     subsw(zr, rscratch2, highbound - lowbound);
1265     br(Assembler::HS, jumptable_end);
1266     add(rscratch1, rscratch1, rscratch2,
1267         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1268     br(rscratch1);
1269   }
1270 
1271   // Form an address from base + offset in Rd.  Rd may or may not
1272   // actually be used: you must use the Address that is returned.  It
1273   // is up to you to ensure that the shift provided matches the size
1274   // of your data.
1275   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1276 
1277   // Return true iff an address is within the 48-bit AArch64 address
1278   // space.
1279   bool is_valid_AArch64_address(address a) {

1304   }
1305 
1306   address read_polling_page(Register r, relocInfo::relocType rtype);
1307   void get_polling_page(Register dest, relocInfo::relocType rtype);
1308 
1309   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1310   void update_byte_crc32(Register crc, Register val, Register table);
1311   void update_word_crc32(Register crc, Register v, Register tmp,
1312         Register table0, Register table1, Register table2, Register table3,
1313         bool upper = false);
1314 
1315   address has_negatives(Register ary1, Register len, Register result);
1316 
1317   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1318                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1319 
1320   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1321                      int elem_size);
1322 
1323   void fill_words(Register base, Register cnt, Register value);
1324   void fill_words(Register base, uint64_t cnt, Register value);
1325 
1326   void zero_words(Register base, uint64_t cnt);
1327   address zero_words(Register ptr, Register cnt);
1328   void zero_dcache_blocks(Register base, Register cnt);
1329 
1330   static const int zero_words_block_size;
1331 
1332   address byte_array_inflate(Register src, Register dst, Register len,
1333                              FloatRegister vtmp1, FloatRegister vtmp2,
1334                              FloatRegister vtmp3, Register tmp4);
1335 
1336   void char_array_compress(Register src, Register dst, Register len,
1337                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1338                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1339                            Register result);
1340 
1341   void encode_iso_array(Register src, Register dst,
1342                         Register len, Register result,
1343                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1344                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1345   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
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