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src/hotspot/cpu/aarch64/macroAssembler_aarch64.hpp

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  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "code/vmreg.hpp"
  31 #include "metaprogramming/enableIf.hpp"
  32 #include "oops/compressedOops.hpp"
  33 #include "runtime/vm_version.hpp"

  34 #include "utilities/powerOfTwo.hpp"




  35 
  36 class OopMap;
  37 
  38 // MacroAssembler extends Assembler by frequently used macros.
  39 //
  40 // Instructions for which a 'better' code sequence exists depending
  41 // on arguments should also go in here.
  42 
  43 class MacroAssembler: public Assembler {
  44   friend class LIR_Assembler;
  45 
  46  public:
  47   using Assembler::mov;
  48   using Assembler::movi;
  49 
  50  protected:
  51 
  52   // Support for VM calls
  53   //
  54   // This is the base routine called by the different versions of call_VM_leaf. The interpreter

 582     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 583   }
 584 
 585   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 586   int corrected_idivl(Register result, Register ra, Register rb,
 587                       bool want_remainder, Register tmp = rscratch1);
 588   int corrected_idivq(Register result, Register ra, Register rb,
 589                       bool want_remainder, Register tmp = rscratch1);
 590 
 591   // Support for NULL-checks
 592   //
 593   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 594   // If the accessed location is M[reg + offset] and the offset is known, provide the
 595   // offset. No explicit code generation is needed if the offset is within a certain
 596   // range (0 <= offset <= page_size).
 597 
 598   virtual void null_check(Register reg, int offset = -1);
 599   static bool needs_explicit_null_check(intptr_t offset);
 600   static bool uses_implicit_null_check(void* address);
 601 































 602   static address target_addr_for_insn(address insn_addr, unsigned insn);
 603   static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
 604   static address target_addr_for_insn(address insn_addr) {
 605     unsigned insn = *(unsigned*)insn_addr;
 606     return target_addr_for_insn(insn_addr, insn);
 607   }
 608   static address target_addr_for_insn_or_null(address insn_addr) {
 609     unsigned insn = *(unsigned*)insn_addr;
 610     return target_addr_for_insn_or_null(insn_addr, insn);
 611   }
 612 
 613   // Required platform-specific helpers for Label::patch_instructions.
 614   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 615   static int pd_patch_instruction_size(address branch, address target);
 616   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 617     pd_patch_instruction_size(branch, target);
 618   }
 619   static address pd_call_destination(address branch) {
 620     return target_addr_for_insn(branch);
 621   }

 815                            Register scratch);
 816 
 817   void reset_last_Java_frame(Register thread);
 818 
 819   // thread in the default location (rthread)
 820   void reset_last_Java_frame(bool clear_fp);
 821 
 822   // Stores
 823   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 824   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 825 
 826   void resolve_jobject(Register value, Register tmp1, Register tmp2);
 827 
 828   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 829   void c2bool(Register x);
 830 
 831   void load_method_holder_cld(Register rresult, Register rmethod);
 832   void load_method_holder(Register holder, Register method);
 833 
 834   // oop manipulations


 835   void load_klass(Register dst, Register src);
 836   void store_klass(Register dst, Register src);
 837   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 838 
 839   void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
 840   void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
 841   void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
 842 
 843   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 844                       Register tmp1, Register tmp2);
 845 
 846   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
 847                        Register tmp1, Register tmp2, Register tmp3);
 848 









 849   void load_heap_oop(Register dst, Address src, Register tmp1,
 850                      Register tmp2, DecoratorSet decorators = 0);
 851 
 852   void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
 853                               Register tmp2, DecoratorSet decorators = 0);
 854   void store_heap_oop(Address dst, Register val, Register tmp1,
 855                       Register tmp2, Register tmp3, DecoratorSet decorators = 0);
 856 
 857   // currently unimplemented
 858   // Used for storing NULL. All other oop constants should be
 859   // stored using routines that take a jobject.
 860   void store_heap_oop_null(Address dst);
 861 


 862   void store_klass_gap(Register dst, Register src);
 863 
 864   // This dummy is to prevent a call to store_heap_oop from
 865   // converting a zero (like NULL) into a Register by giving
 866   // the compiler two choices it can't resolve
 867 
 868   void store_heap_oop(Address dst, void* dummy);
 869 
 870   void encode_heap_oop(Register d, Register s);
 871   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 872   void decode_heap_oop(Register d, Register s);
 873   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 874   void encode_heap_oop_not_null(Register r);
 875   void decode_heap_oop_not_null(Register r);
 876   void encode_heap_oop_not_null(Register dst, Register src);
 877   void decode_heap_oop_not_null(Register dst, Register src);
 878 
 879   void set_narrow_oop(Register dst, jobject obj);
 880 
 881   void encode_klass_not_null(Register r);

 889   void reinit_heapbase();
 890 
 891   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 892 
 893   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 894                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 895   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 896                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 897 
 898   void push_cont_fastpath(Register java_thread);
 899   void pop_cont_fastpath(Register java_thread);
 900 
 901   // Round up to a power of two
 902   void round_to(Register reg, int modulus);
 903 
 904   // java.lang.Math::round intrinsics
 905   void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
 906   void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
 907 
 908   // allocation









 909   void tlab_allocate(
 910     Register obj,                      // result: pointer to object after successful allocation
 911     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 912     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 913     Register t1,                       // temp register
 914     Register t2,                       // temp register
 915     Label&   slow_case                 // continuation point if fast allocation fails
 916   );
 917   void verify_tlab();
 918 



 919   // interface method calling
 920   void lookup_interface_method(Register recv_klass,
 921                                Register intf_klass,
 922                                RegisterOrConstant itable_index,
 923                                Register method_result,
 924                                Register scan_temp,
 925                                Label& no_such_interface,
 926                    bool return_method = true);
 927 
 928   // virtual method calling
 929   // n.b. x86 allows RegisterOrConstant for vtable_index
 930   void lookup_virtual_method(Register recv_klass,
 931                              RegisterOrConstant vtable_index,
 932                              Register method_result);
 933 
 934   // Test sub_klass against super_klass, with fast and slow paths.
 935 
 936   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 937   // One of the three labels can be NULL, meaning take the fall-through.
 938   // If super_check_offset is -1, the value is loaded up from super_klass.

1282   }                                                                     \
1283                                                                         \
1284   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1285     Assembler::INSN(Rd, Rn, Rm);                                        \
1286   }                                                                     \
1287                                                                         \
1288   void INSN(Register Rd, Register Rn, Register Rm,                      \
1289            ext::operation option, int amount = 0) {                     \
1290     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1291   }
1292 
1293   WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1294 
1295   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1296   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1297   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1298   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1299 
1300   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1301 


















1302   void tableswitch(Register index, jint lowbound, jint highbound,
1303                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1304     adr(rscratch1, jumptable);
1305     subsw(rscratch2, index, lowbound);
1306     subsw(zr, rscratch2, highbound - lowbound);
1307     br(Assembler::HS, jumptable_end);
1308     add(rscratch1, rscratch1, rscratch2,
1309         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1310     br(rscratch1);
1311   }
1312 
1313   // Form an address from base + offset in Rd.  Rd may or may not
1314   // actually be used: you must use the Address that is returned.  It
1315   // is up to you to ensure that the shift provided matches the size
1316   // of your data.
1317   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1318 
1319   // Return true iff an address is within the 48-bit AArch64 address
1320   // space.
1321   bool is_valid_AArch64_address(address a) {

1346   }
1347 
1348   address read_polling_page(Register r, relocInfo::relocType rtype);
1349   void get_polling_page(Register dest, relocInfo::relocType rtype);
1350 
1351   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1352   void update_byte_crc32(Register crc, Register val, Register table);
1353   void update_word_crc32(Register crc, Register v, Register tmp,
1354         Register table0, Register table1, Register table2, Register table3,
1355         bool upper = false);
1356 
1357   address count_positives(Register ary1, Register len, Register result);
1358 
1359   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1360                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1361 
1362   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1363                      int elem_size);
1364 
1365   void fill_words(Register base, Register cnt, Register value);


1366   address zero_words(Register base, uint64_t cnt);
1367   address zero_words(Register ptr, Register cnt);
1368   void zero_dcache_blocks(Register base, Register cnt);
1369 
1370   static const int zero_words_block_size;
1371 
1372   address byte_array_inflate(Register src, Register dst, Register len,
1373                              FloatRegister vtmp1, FloatRegister vtmp2,
1374                              FloatRegister vtmp3, Register tmp4);
1375 
1376   void char_array_compress(Register src, Register dst, Register len,
1377                            Register res,
1378                            FloatRegister vtmp0, FloatRegister vtmp1,
1379                            FloatRegister vtmp2, FloatRegister vtmp3);
1380 
1381   void encode_iso_array(Register src, Register dst,
1382                         Register len, Register res, bool ascii,
1383                         FloatRegister vtmp0, FloatRegister vtmp1,
1384                         FloatRegister vtmp2, FloatRegister vtmp3);
1385 

  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "code/vmreg.hpp"
  31 #include "metaprogramming/enableIf.hpp"
  32 #include "oops/compressedOops.hpp"
  33 #include "runtime/vm_version.hpp"
  34 #include "utilities/macros.hpp"
  35 #include "utilities/powerOfTwo.hpp"
  36 #include "runtime/signature.hpp"
  37 
  38 
  39 class ciInlineKlass;
  40 
  41 class OopMap;
  42 
  43 // MacroAssembler extends Assembler by frequently used macros.
  44 //
  45 // Instructions for which a 'better' code sequence exists depending
  46 // on arguments should also go in here.
  47 
  48 class MacroAssembler: public Assembler {
  49   friend class LIR_Assembler;
  50 
  51  public:
  52   using Assembler::mov;
  53   using Assembler::movi;
  54 
  55  protected:
  56 
  57   // Support for VM calls
  58   //
  59   // This is the base routine called by the different versions of call_VM_leaf. The interpreter

 587     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 588   }
 589 
 590   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 591   int corrected_idivl(Register result, Register ra, Register rb,
 592                       bool want_remainder, Register tmp = rscratch1);
 593   int corrected_idivq(Register result, Register ra, Register rb,
 594                       bool want_remainder, Register tmp = rscratch1);
 595 
 596   // Support for NULL-checks
 597   //
 598   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 599   // If the accessed location is M[reg + offset] and the offset is known, provide the
 600   // offset. No explicit code generation is needed if the offset is within a certain
 601   // range (0 <= offset <= page_size).
 602 
 603   virtual void null_check(Register reg, int offset = -1);
 604   static bool needs_explicit_null_check(intptr_t offset);
 605   static bool uses_implicit_null_check(void* address);
 606 
 607   // markWord tests, kills markWord reg
 608   void test_markword_is_inline_type(Register markword, Label& is_inline_type);
 609 
 610   // inlineKlass queries, kills temp_reg
 611   void test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type);
 612   void test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type);
 613   void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type);
 614 
 615   // Get the default value oop for the given InlineKlass
 616   void get_default_value_oop(Register inline_klass, Register temp_reg, Register obj);
 617   // The empty value oop, for the given InlineKlass ("empty" as in no instance fields)
 618   // get_default_value_oop with extra assertion for empty inline klass
 619   void get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj);
 620 
 621   void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
 622   void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free);
 623   void test_field_is_inlined(Register flags, Register temp_reg, Label& is_flattened);
 624 
 625   // Check oops for special arrays, i.e. flattened and/or null-free
 626   void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label);
 627   void test_flattened_array_oop(Register klass, Register temp_reg, Label& is_flattened_array);
 628   void test_non_flattened_array_oop(Register oop, Register temp_reg, Label&is_non_flattened_array);
 629   void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
 630   void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
 631 
 632   // Check array klass layout helper for flatten or null-free arrays...
 633   void test_flattened_array_layout(Register lh, Label& is_flattened_array);
 634   void test_non_flattened_array_layout(Register lh, Label& is_non_flattened_array);
 635   void test_null_free_array_layout(Register lh, Label& is_null_free_array);
 636   void test_non_null_free_array_layout(Register lh, Label& is_non_null_free_array);
 637 
 638   static address target_addr_for_insn(address insn_addr, unsigned insn);
 639   static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
 640   static address target_addr_for_insn(address insn_addr) {
 641     unsigned insn = *(unsigned*)insn_addr;
 642     return target_addr_for_insn(insn_addr, insn);
 643   }
 644   static address target_addr_for_insn_or_null(address insn_addr) {
 645     unsigned insn = *(unsigned*)insn_addr;
 646     return target_addr_for_insn_or_null(insn_addr, insn);
 647   }
 648 
 649   // Required platform-specific helpers for Label::patch_instructions.
 650   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 651   static int pd_patch_instruction_size(address branch, address target);
 652   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 653     pd_patch_instruction_size(branch, target);
 654   }
 655   static address pd_call_destination(address branch) {
 656     return target_addr_for_insn(branch);
 657   }

 851                            Register scratch);
 852 
 853   void reset_last_Java_frame(Register thread);
 854 
 855   // thread in the default location (rthread)
 856   void reset_last_Java_frame(bool clear_fp);
 857 
 858   // Stores
 859   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 860   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 861 
 862   void resolve_jobject(Register value, Register tmp1, Register tmp2);
 863 
 864   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 865   void c2bool(Register x);
 866 
 867   void load_method_holder_cld(Register rresult, Register rmethod);
 868   void load_method_holder(Register holder, Register method);
 869 
 870   // oop manipulations
 871   void load_metadata(Register dst, Register src);
 872 
 873   void load_klass(Register dst, Register src);
 874   void store_klass(Register dst, Register src);
 875   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 876 
 877   void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
 878   void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
 879   void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
 880 
 881   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 882                       Register tmp1, Register tmp2);
 883 
 884   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
 885                        Register tmp1, Register tmp2, Register tmp3);
 886 
 887   void access_value_copy(DecoratorSet decorators, Register src, Register dst, Register inline_klass);
 888 
 889   // inline type data payload offsets...
 890   void first_field_offset(Register inline_klass, Register offset);
 891   void data_for_oop(Register oop, Register data, Register inline_klass);
 892   // get data payload ptr a flat value array at index, kills rcx and index
 893   void data_for_value_array_index(Register array, Register array_klass,
 894                                   Register index, Register data);
 895 
 896   void load_heap_oop(Register dst, Address src, Register tmp1,
 897                      Register tmp2, DecoratorSet decorators = 0);
 898 
 899   void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
 900                               Register tmp2, DecoratorSet decorators = 0);
 901   void store_heap_oop(Address dst, Register val, Register tmp1,
 902                       Register tmp2, Register tmp3, DecoratorSet decorators = 0);
 903 
 904   // currently unimplemented
 905   // Used for storing NULL. All other oop constants should be
 906   // stored using routines that take a jobject.
 907   void store_heap_oop_null(Address dst);
 908 
 909   void load_prototype_header(Register dst, Register src);
 910 
 911   void store_klass_gap(Register dst, Register src);
 912 
 913   // This dummy is to prevent a call to store_heap_oop from
 914   // converting a zero (like NULL) into a Register by giving
 915   // the compiler two choices it can't resolve
 916 
 917   void store_heap_oop(Address dst, void* dummy);
 918 
 919   void encode_heap_oop(Register d, Register s);
 920   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 921   void decode_heap_oop(Register d, Register s);
 922   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 923   void encode_heap_oop_not_null(Register r);
 924   void decode_heap_oop_not_null(Register r);
 925   void encode_heap_oop_not_null(Register dst, Register src);
 926   void decode_heap_oop_not_null(Register dst, Register src);
 927 
 928   void set_narrow_oop(Register dst, jobject obj);
 929 
 930   void encode_klass_not_null(Register r);

 938   void reinit_heapbase();
 939 
 940   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 941 
 942   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 943                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 944   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 945                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 946 
 947   void push_cont_fastpath(Register java_thread);
 948   void pop_cont_fastpath(Register java_thread);
 949 
 950   // Round up to a power of two
 951   void round_to(Register reg, int modulus);
 952 
 953   // java.lang.Math::round intrinsics
 954   void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
 955   void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
 956 
 957   // allocation
 958 
 959   // Object / value buffer allocation...
 960   // Allocate instance of klass, assumes klass initialized by caller
 961   // new_obj prefers to be rax
 962   // Kills t1 and t2, perserves klass, return allocation in new_obj (rsi on LP64)
 963   void allocate_instance(Register klass, Register new_obj,
 964                          Register t1, Register t2,
 965                          bool clear_fields, Label& alloc_failed);
 966 
 967   void tlab_allocate(
 968     Register obj,                      // result: pointer to object after successful allocation
 969     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 970     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 971     Register t1,                       // temp register
 972     Register t2,                       // temp register
 973     Label&   slow_case                 // continuation point if fast allocation fails
 974   );
 975   void verify_tlab();
 976 
 977   // For field "index" within "klass", return inline_klass ...
 978   void get_inline_type_field_klass(Register klass, Register index, Register inline_klass);
 979 
 980   // interface method calling
 981   void lookup_interface_method(Register recv_klass,
 982                                Register intf_klass,
 983                                RegisterOrConstant itable_index,
 984                                Register method_result,
 985                                Register scan_temp,
 986                                Label& no_such_interface,
 987                    bool return_method = true);
 988 
 989   // virtual method calling
 990   // n.b. x86 allows RegisterOrConstant for vtable_index
 991   void lookup_virtual_method(Register recv_klass,
 992                              RegisterOrConstant vtable_index,
 993                              Register method_result);
 994 
 995   // Test sub_klass against super_klass, with fast and slow paths.
 996 
 997   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 998   // One of the three labels can be NULL, meaning take the fall-through.
 999   // If super_check_offset is -1, the value is loaded up from super_klass.

1343   }                                                                     \
1344                                                                         \
1345   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1346     Assembler::INSN(Rd, Rn, Rm);                                        \
1347   }                                                                     \
1348                                                                         \
1349   void INSN(Register Rd, Register Rn, Register Rm,                      \
1350            ext::operation option, int amount = 0) {                     \
1351     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1352   }
1353 
1354   WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1355 
1356   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1357   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1358   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1359   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1360 
1361   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1362 
1363   void verified_entry(Compile* C, int sp_inc);
1364 
1365   // Inline type specific methods
1366   #include "asm/macroAssembler_common.hpp"
1367 
1368   int store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter = true);
1369   bool move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]);
1370   bool unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
1371                             VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
1372                             RegState reg_state[]);
1373   bool pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
1374                           VMRegPair* from, int from_count, int& from_index, VMReg to,
1375                           RegState reg_state[], Register val_array);
1376   int extend_stack_for_inline_args(int args_on_stack);
1377   void remove_frame(int initial_framesize, bool needs_stack_repair);
1378   VMReg spill_reg_for(VMReg reg);
1379   void save_stack_increment(int sp_inc, int frame_size);
1380 
1381   void tableswitch(Register index, jint lowbound, jint highbound,
1382                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1383     adr(rscratch1, jumptable);
1384     subsw(rscratch2, index, lowbound);
1385     subsw(zr, rscratch2, highbound - lowbound);
1386     br(Assembler::HS, jumptable_end);
1387     add(rscratch1, rscratch1, rscratch2,
1388         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1389     br(rscratch1);
1390   }
1391 
1392   // Form an address from base + offset in Rd.  Rd may or may not
1393   // actually be used: you must use the Address that is returned.  It
1394   // is up to you to ensure that the shift provided matches the size
1395   // of your data.
1396   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1397 
1398   // Return true iff an address is within the 48-bit AArch64 address
1399   // space.
1400   bool is_valid_AArch64_address(address a) {

1425   }
1426 
1427   address read_polling_page(Register r, relocInfo::relocType rtype);
1428   void get_polling_page(Register dest, relocInfo::relocType rtype);
1429 
1430   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1431   void update_byte_crc32(Register crc, Register val, Register table);
1432   void update_word_crc32(Register crc, Register v, Register tmp,
1433         Register table0, Register table1, Register table2, Register table3,
1434         bool upper = false);
1435 
1436   address count_positives(Register ary1, Register len, Register result);
1437 
1438   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1439                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1440 
1441   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1442                      int elem_size);
1443 
1444   void fill_words(Register base, Register cnt, Register value);
1445   void fill_words(Register base, uint64_t cnt, Register value);
1446 
1447   address zero_words(Register base, uint64_t cnt);
1448   address zero_words(Register ptr, Register cnt);
1449   void zero_dcache_blocks(Register base, Register cnt);
1450 
1451   static const int zero_words_block_size;
1452 
1453   address byte_array_inflate(Register src, Register dst, Register len,
1454                              FloatRegister vtmp1, FloatRegister vtmp2,
1455                              FloatRegister vtmp3, Register tmp4);
1456 
1457   void char_array_compress(Register src, Register dst, Register len,
1458                            Register res,
1459                            FloatRegister vtmp0, FloatRegister vtmp1,
1460                            FloatRegister vtmp2, FloatRegister vtmp3);
1461 
1462   void encode_iso_array(Register src, Register dst,
1463                         Register len, Register res, bool ascii,
1464                         FloatRegister vtmp0, FloatRegister vtmp1,
1465                         FloatRegister vtmp2, FloatRegister vtmp3);
1466 
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