900 #if defined(ABI_ELFv2)
901 assert(additional_frame_header_slots == 0, "ABIv2 shouldn't use extra slots");
902 // ABIv2 allows omitting the Parameter Save Area if the callee's prototype
903 // indicates that all parameters can be passed in registers.
904 return stack_used ? (arg * 2) : 0;
905 #else
906 // The Parameter Save Area needs to be at least 8 double-word slots for ABIv1.
907 // We have to add extra slots because ABIv1 uses a larger header.
908 return MAX2(arg, 8) * 2 + additional_frame_header_slots;
909 #endif
910 }
911
912 int SharedRuntime::vector_calling_convention(VMRegPair *regs,
913 uint num_bits,
914 uint total_args_passed) {
915 Unimplemented();
916 return 0;
917 }
918
919 static address gen_c2i_adapter(MacroAssembler *masm,
920 int total_args_passed,
921 int comp_args_on_stack,
922 const BasicType *sig_bt,
923 const VMRegPair *regs,
924 Label& call_interpreter,
925 const Register& ientry) {
926
927 address c2i_entrypoint;
928
929 const Register sender_SP = R21_sender_SP; // == R21_tmp1
930 const Register code = R22_tmp2;
931 //const Register ientry = R23_tmp3;
932 const Register value_regs[] = { R24_tmp4, R25_tmp5, R26_tmp6 };
933 const int num_value_regs = sizeof(value_regs) / sizeof(Register);
934 int value_regs_index = 0;
935
936 const Register return_pc = R27_tmp7;
937 const Register tmp = R28_tmp8;
938
939 assert_different_registers(sender_SP, code, ientry, return_pc, tmp);
940
941 // Adapter needs TOP_IJAVA_FRAME_ABI.
942 const int adapter_size = frame::top_ijava_frame_abi_size +
943 align_up(total_args_passed * wordSize, frame::alignment_in_bytes);
944
945 // regular (verified) c2i entry point
946 c2i_entrypoint = __ pc();
947
948 // Does compiled code exists? If yes, patch the caller's callsite.
949 __ ld(code, method_(code));
950 __ cmpdi(CR0, code, 0);
951 __ ld(ientry, method_(interpreter_entry)); // preloaded
952 __ beq(CR0, call_interpreter);
953
954
963 RegisterSaver::restore_argument_registers_and_pop_frame(masm, adapter_size, total_args_passed, regs);
964 __ ld(return_pc, _abi0(lr), R1_SP);
965 __ ld(ientry, method_(interpreter_entry)); // preloaded
966 __ mtlr(return_pc);
967
968
969 // Call the interpreter.
970 __ BIND(call_interpreter);
971 __ mtctr(ientry);
972
973 // Get a copy of the current SP for loading caller's arguments.
974 __ mr(sender_SP, R1_SP);
975
976 // Add space for the adapter.
977 __ resize_frame(-adapter_size, R12_scratch2);
978
979 int st_off = adapter_size - wordSize;
980
981 // Write the args into the outgoing interpreter space.
982 for (int i = 0; i < total_args_passed; i++) {
983 VMReg r_1 = regs[i].first();
984 VMReg r_2 = regs[i].second();
985 if (!r_1->is_valid()) {
986 assert(!r_2->is_valid(), "");
987 continue;
988 }
989 if (r_1->is_stack()) {
990 Register tmp_reg = value_regs[value_regs_index];
991 value_regs_index = (value_regs_index + 1) % num_value_regs;
992 // The calling convention produces OptoRegs that ignore the out
993 // preserve area (JIT's ABI). We must account for it here.
994 int ld_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
995 if (!r_2->is_valid()) {
996 __ lwz(tmp_reg, ld_off, sender_SP);
997 } else {
998 __ ld(tmp_reg, ld_off, sender_SP);
999 }
1000 // Pretend stack targets were loaded into tmp_reg.
1001 r_1 = tmp_reg->as_VMReg();
1002 }
1003
1004 if (r_1->is_Register()) {
1005 Register r = r_1->as_Register();
1006 if (!r_2->is_valid()) {
1007 __ stw(r, st_off, R1_SP);
1008 st_off-=wordSize;
1009 } else {
1010 // Longs are given 2 64-bit slots in the interpreter, but the
1011 // data is passed in only 1 slot.
1012 if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
1013 DEBUG_ONLY( __ li(tmp, 0); __ std(tmp, st_off, R1_SP); )
1014 st_off-=wordSize;
1015 }
1016 __ std(r, st_off, R1_SP);
1017 st_off-=wordSize;
1018 }
1019 } else {
1020 assert(r_1->is_FloatRegister(), "");
1021 FloatRegister f = r_1->as_FloatRegister();
1022 if (!r_2->is_valid()) {
1023 __ stfs(f, st_off, R1_SP);
1024 st_off-=wordSize;
1025 } else {
1026 // In 64bit, doubles are given 2 64-bit slots in the interpreter, but the
1027 // data is passed in only 1 slot.
1028 // One of these should get known junk...
1029 DEBUG_ONLY( __ li(tmp, 0); __ std(tmp, st_off, R1_SP); )
1030 st_off-=wordSize;
1031 __ stfd(f, st_off, R1_SP);
1032 st_off-=wordSize;
1033 }
1034 }
1035 }
1036
1037 // Jump to the interpreter just as if interpreter was doing it.
1038
1039 __ load_const_optimized(R25_templateTableBase, (address)Interpreter::dispatch_table((TosState)0), R11_scratch1);
1040
1041 // load TOS
1042 __ addi(R15_esp, R1_SP, st_off);
1043
1044 // Frame_manager expects initial_caller_sp (= SP without resize by c2i) in R21_tmp1.
1045 assert(sender_SP == R21_sender_SP, "passing initial caller's SP in wrong register");
1046 __ bctr();
1047
1048 return c2i_entrypoint;
1049 }
1050
1051 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
1052 int total_args_passed,
1053 int comp_args_on_stack,
1054 const BasicType *sig_bt,
1055 const VMRegPair *regs) {
1056
1057 // Load method's entry-point from method.
1058 __ ld(R12_scratch2, in_bytes(Method::from_compiled_offset()), R19_method);
1059 __ mtctr(R12_scratch2);
1060
1061 // We will only enter here from an interpreted frame and never from after
1062 // passing thru a c2i. Azul allowed this but we do not. If we lose the
1063 // race and use a c2i we will remain interpreted for the race loser(s).
1064 // This removes all sorts of headaches on the x86 side and also eliminates
1065 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
1066
1067 // Note: r13 contains the senderSP on entry. We must preserve it since
1068 // we may do a i2c -> c2i transition if we lose a race where compiled
1069 // code goes non-entrant while we get args ready.
1070 // In addition we use r13 to locate all the interpreter args as
1071 // we must align the stack to 16 bytes on an i2c entry else we
1072 // lose alignment we expect in all compiled code and register
1073 // save code can segv when fxsave instructions find improperly
1074 // aligned stack pointer.
1075
1076 const Register ld_ptr = R15_esp;
1077 const Register value_regs[] = { R22_tmp2, R23_tmp3, R24_tmp4, R25_tmp5, R26_tmp6 };
1078 const int num_value_regs = sizeof(value_regs) / sizeof(Register);
1079 int value_regs_index = 0;
1080
1081 int ld_offset = total_args_passed*wordSize;
1082
1083 // Cut-out for having no stack args. Since up to 2 int/oop args are passed
1084 // in registers, we will occasionally have no stack args.
1085 int comp_words_on_stack = 0;
1086 if (comp_args_on_stack) {
1087 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
1088 // registers are below. By subtracting stack0, we either get a negative
1089 // number (all values in registers) or the maximum stack slot accessed.
1090
1091 // Convert 4-byte c2 stack slots to words.
1092 comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
1093 // Round up to miminum stack alignment, in wordSize.
1094 comp_words_on_stack = align_up(comp_words_on_stack, 2);
1095 __ resize_frame(-comp_words_on_stack * wordSize, R11_scratch1);
1096 }
1097
1098 // Now generate the shuffle code. Pick up all register args and move the
1099 // rest through register value=Z_R12.
1100 BLOCK_COMMENT("Shuffle arguments");
1101 for (int i = 0; i < total_args_passed; i++) {
1102 if (sig_bt[i] == T_VOID) {
1103 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
1104 continue;
1105 }
1106
1107 // Pick up 0, 1 or 2 words from ld_ptr.
1108 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
1109 "scrambled load targets?");
1110 VMReg r_1 = regs[i].first();
1111 VMReg r_2 = regs[i].second();
1112 if (!r_1->is_valid()) {
1113 assert(!r_2->is_valid(), "");
1114 continue;
1115 }
1116 if (r_1->is_FloatRegister()) {
1117 if (!r_2->is_valid()) {
1118 __ lfs(r_1->as_FloatRegister(), ld_offset, ld_ptr);
1119 ld_offset-=wordSize;
1120 } else {
1121 // Skip the unused interpreter slot.
1122 __ lfd(r_1->as_FloatRegister(), ld_offset-wordSize, ld_ptr);
1123 ld_offset-=2*wordSize;
1124 }
1125 } else {
1126 Register r;
1127 if (r_1->is_stack()) {
1128 // Must do a memory to memory move thru "value".
1129 r = value_regs[value_regs_index];
1130 value_regs_index = (value_regs_index + 1) % num_value_regs;
1131 } else {
1132 r = r_1->as_Register();
1133 }
1134 if (!r_2->is_valid()) {
1135 // Not sure we need to do this but it shouldn't hurt.
1136 if (is_reference_type(sig_bt[i]) || sig_bt[i] == T_ADDRESS) {
1137 __ ld(r, ld_offset, ld_ptr);
1138 ld_offset-=wordSize;
1139 } else {
1140 __ lwz(r, ld_offset, ld_ptr);
1141 ld_offset-=wordSize;
1142 }
1143 } else {
1144 // In 64bit, longs are given 2 64-bit slots in the interpreter, but the
1145 // data is passed in only 1 slot.
1146 if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
1147 ld_offset-=wordSize;
1148 }
1149 __ ld(r, ld_offset, ld_ptr);
1150 ld_offset-=wordSize;
1151 }
1152
1153 if (r_1->is_stack()) {
1154 // Now store value where the compiler expects it
1155 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots())*VMRegImpl::stack_slot_size;
1156
1157 if (sig_bt[i] == T_INT || sig_bt[i] == T_FLOAT ||sig_bt[i] == T_BOOLEAN ||
1158 sig_bt[i] == T_SHORT || sig_bt[i] == T_CHAR || sig_bt[i] == T_BYTE) {
1159 __ stw(r, st_off, R1_SP);
1160 } else {
1161 __ std(r, st_off, R1_SP);
1162 }
1163 }
1164 }
1165 }
1166
1167 __ push_cont_fastpath(); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
1168
1169 BLOCK_COMMENT("Store method");
1170 // Store method into thread->callee_target.
1171 // We might end up in handle_wrong_method if the callee is
1172 // deoptimized as we race thru here. If that happens we don't want
1173 // to take a safepoint because the caller frame will look
1174 // interpreted and arguments are now "compiled" so it is much better
1175 // to make this transition invisible to the stack walking
1176 // code. Unfortunately if we try and find the callee by normal means
1177 // a safepoint is possible. So we stash the desired callee in the
1178 // thread and the vm will find there should this case occur.
1179 __ std(R19_method, thread_(callee_target));
1180
1181 // Jump to the compiled code just as if compiled code was doing it.
1182 __ bctr();
1183 }
1184
1185 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
1186 int total_args_passed,
1187 int comp_args_on_stack,
1188 const BasicType *sig_bt,
1189 const VMRegPair *regs,
1190 address entry_address[AdapterBlob::ENTRY_COUNT]) {
1191 // entry: i2c
1192
1193 __ align(CodeEntryAlignment);
1194 entry_address[AdapterBlob::I2C] = __ pc();
1195 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
1196
1197
1198 // entry: c2i unverified
1199
1200 __ align(CodeEntryAlignment);
1201 BLOCK_COMMENT("c2i unverified entry");
1202 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
1203
1204 // inline_cache contains a CompiledICData
1205 const Register ic = R19_inline_cache_reg;
1206 const Register ic_klass = R11_scratch1;
1207 const Register receiver_klass = R12_scratch2;
1208 const Register code = R21_tmp1;
1209 const Register ientry = R23_tmp3;
1210
1211 assert_different_registers(ic, ic_klass, receiver_klass, R3_ARG1, code, ientry);
1212 assert(R11_scratch1 == R11, "need prologue scratch register");
1213
1214 Label call_interpreter;
1215
1236
1237 // Bypass the barrier for non-static methods
1238 __ lhz(R0, in_bytes(Method::access_flags_offset()), R19_method);
1239 __ andi_(R0, R0, JVM_ACC_STATIC);
1240 __ beq(CR0, L_skip_barrier); // non-static
1241
1242 Register klass = R11_scratch1;
1243 __ load_method_holder(klass, R19_method);
1244 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
1245
1246 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
1247 __ mtctr(klass);
1248 __ bctr();
1249
1250 __ bind(L_skip_barrier);
1251 entry_address[AdapterBlob::C2I_No_Clinit_Check] = __ pc();
1252
1253 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1254 bs->c2i_entry_barrier(masm, /* tmp register*/ ic_klass, /* tmp register*/ receiver_klass, /* tmp register*/ code);
1255
1256 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, call_interpreter, ientry);
1257 return;
1258 }
1259
1260 // An oop arg. Must pass a handle not the oop itself.
1261 static void object_move(MacroAssembler* masm,
1262 int frame_size_in_slots,
1263 OopMap* oop_map, int oop_handle_offset,
1264 bool is_receiver, int* receiver_offset,
1265 VMRegPair src, VMRegPair dst,
1266 Register r_caller_sp, Register r_temp_1, Register r_temp_2) {
1267 assert(!is_receiver || (is_receiver && (*receiver_offset == -1)),
1268 "receiver has already been moved");
1269
1270 // We must pass a handle. First figure out the location we use as a handle.
1271
1272 if (src.first()->is_stack()) {
1273 // stack to stack or reg
1274
1275 const Register r_handle = dst.first()->is_stack() ? r_temp_1 : dst.first()->as_Register();
1276 Label skip;
3806 int frame_complete = __ pc() - start;
3807 __ set_last_Java_frame(R1_SP, noreg);
3808 __ call_VM_leaf(CAST_FROM_FN_PTR(address, JfrIntrinsicSupport::return_lease), R16_thread);
3809 address calls_return_pc = __ last_calls_return_pc();
3810 __ reset_last_Java_frame();
3811 __ pop_frame();
3812 __ ld(tmp1, _abi0(lr), R1_SP);
3813 __ mtlr(tmp1);
3814 __ blr();
3815
3816 OopMapSet* oop_maps = new OopMapSet();
3817 OopMap* map = new OopMap(framesize, 0);
3818 oop_maps->add_gc_map(calls_return_pc - start, map);
3819
3820 RuntimeStub* stub = // codeBlob framesize is in words (not VMRegImpl::slot_size)
3821 RuntimeStub::new_runtime_stub(name, &code, frame_complete,
3822 (framesize >> (LogBytesPerWord - LogBytesPerInt)),
3823 oop_maps, false);
3824 return stub;
3825 }
3826
3827 #endif // INCLUDE_JFR
|
900 #if defined(ABI_ELFv2)
901 assert(additional_frame_header_slots == 0, "ABIv2 shouldn't use extra slots");
902 // ABIv2 allows omitting the Parameter Save Area if the callee's prototype
903 // indicates that all parameters can be passed in registers.
904 return stack_used ? (arg * 2) : 0;
905 #else
906 // The Parameter Save Area needs to be at least 8 double-word slots for ABIv1.
907 // We have to add extra slots because ABIv1 uses a larger header.
908 return MAX2(arg, 8) * 2 + additional_frame_header_slots;
909 #endif
910 }
911
912 int SharedRuntime::vector_calling_convention(VMRegPair *regs,
913 uint num_bits,
914 uint total_args_passed) {
915 Unimplemented();
916 return 0;
917 }
918
919 static address gen_c2i_adapter(MacroAssembler *masm,
920 int comp_args_on_stack,
921 const GrowableArray<SigEntry>* sig,
922 const VMRegPair *regs,
923 Label& call_interpreter,
924 const Register& ientry) {
925
926 address c2i_entrypoint;
927
928 const Register sender_SP = R21_sender_SP; // == R21_tmp1
929 const Register code = R22_tmp2;
930 //const Register ientry = R23_tmp3;
931 const Register value_regs[] = { R24_tmp4, R25_tmp5, R26_tmp6 };
932 const int num_value_regs = sizeof(value_regs) / sizeof(Register);
933 int value_regs_index = 0;
934 int total_args_passed = sig->length();
935
936 const Register return_pc = R27_tmp7;
937 const Register tmp = R28_tmp8;
938
939 assert_different_registers(sender_SP, code, ientry, return_pc, tmp);
940
941 // Adapter needs TOP_IJAVA_FRAME_ABI.
942 const int adapter_size = frame::top_ijava_frame_abi_size +
943 align_up(total_args_passed * wordSize, frame::alignment_in_bytes);
944
945 // regular (verified) c2i entry point
946 c2i_entrypoint = __ pc();
947
948 // Does compiled code exists? If yes, patch the caller's callsite.
949 __ ld(code, method_(code));
950 __ cmpdi(CR0, code, 0);
951 __ ld(ientry, method_(interpreter_entry)); // preloaded
952 __ beq(CR0, call_interpreter);
953
954
963 RegisterSaver::restore_argument_registers_and_pop_frame(masm, adapter_size, total_args_passed, regs);
964 __ ld(return_pc, _abi0(lr), R1_SP);
965 __ ld(ientry, method_(interpreter_entry)); // preloaded
966 __ mtlr(return_pc);
967
968
969 // Call the interpreter.
970 __ BIND(call_interpreter);
971 __ mtctr(ientry);
972
973 // Get a copy of the current SP for loading caller's arguments.
974 __ mr(sender_SP, R1_SP);
975
976 // Add space for the adapter.
977 __ resize_frame(-adapter_size, R12_scratch2);
978
979 int st_off = adapter_size - wordSize;
980
981 // Write the args into the outgoing interpreter space.
982 for (int i = 0; i < total_args_passed; i++) {
983 BasicType bt = sig->at(i)._bt;
984
985 VMReg r_1 = regs[i].first();
986 VMReg r_2 = regs[i].second();
987 if (!r_1->is_valid()) {
988 assert(!r_2->is_valid(), "");
989 continue;
990 }
991 if (r_1->is_stack()) {
992 Register tmp_reg = value_regs[value_regs_index];
993 value_regs_index = (value_regs_index + 1) % num_value_regs;
994 // The calling convention produces OptoRegs that ignore the out
995 // preserve area (JIT's ABI). We must account for it here.
996 int ld_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
997 if (!r_2->is_valid()) {
998 __ lwz(tmp_reg, ld_off, sender_SP);
999 } else {
1000 __ ld(tmp_reg, ld_off, sender_SP);
1001 }
1002 // Pretend stack targets were loaded into tmp_reg.
1003 r_1 = tmp_reg->as_VMReg();
1004 }
1005
1006 if (r_1->is_Register()) {
1007 Register r = r_1->as_Register();
1008 if (!r_2->is_valid()) {
1009 __ stw(r, st_off, R1_SP);
1010 st_off-=wordSize;
1011 } else {
1012 // Longs are given 2 64-bit slots in the interpreter, but the
1013 // data is passed in only 1 slot.
1014 if (bt == T_LONG || bt == T_DOUBLE) {
1015 DEBUG_ONLY( __ li(tmp, 0); __ std(tmp, st_off, R1_SP); )
1016 st_off-=wordSize;
1017 }
1018 __ std(r, st_off, R1_SP);
1019 st_off-=wordSize;
1020 }
1021 } else {
1022 assert(r_1->is_FloatRegister(), "");
1023 FloatRegister f = r_1->as_FloatRegister();
1024 if (!r_2->is_valid()) {
1025 __ stfs(f, st_off, R1_SP);
1026 st_off-=wordSize;
1027 } else {
1028 // In 64bit, doubles are given 2 64-bit slots in the interpreter, but the
1029 // data is passed in only 1 slot.
1030 // One of these should get known junk...
1031 DEBUG_ONLY( __ li(tmp, 0); __ std(tmp, st_off, R1_SP); )
1032 st_off-=wordSize;
1033 __ stfd(f, st_off, R1_SP);
1034 st_off-=wordSize;
1035 }
1036 }
1037 }
1038
1039 // Jump to the interpreter just as if interpreter was doing it.
1040
1041 __ load_const_optimized(R25_templateTableBase, (address)Interpreter::dispatch_table((TosState)0), R11_scratch1);
1042
1043 // load TOS
1044 __ addi(R15_esp, R1_SP, st_off);
1045
1046 // Frame_manager expects initial_caller_sp (= SP without resize by c2i) in R21_tmp1.
1047 assert(sender_SP == R21_sender_SP, "passing initial caller's SP in wrong register");
1048 __ bctr();
1049
1050 return c2i_entrypoint;
1051 }
1052
1053 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm, int comp_args_on_stack, const GrowableArray<SigEntry>* sig, const VMRegPair *regs) {
1054
1055 // Load method's entry-point from method.
1056 __ ld(R12_scratch2, in_bytes(Method::from_compiled_offset()), R19_method);
1057 __ mtctr(R12_scratch2);
1058
1059 // We will only enter here from an interpreted frame and never from after
1060 // passing thru a c2i. Azul allowed this but we do not. If we lose the
1061 // race and use a c2i we will remain interpreted for the race loser(s).
1062 // This removes all sorts of headaches on the x86 side and also eliminates
1063 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
1064
1065 // Note: r13 contains the senderSP on entry. We must preserve it since
1066 // we may do a i2c -> c2i transition if we lose a race where compiled
1067 // code goes non-entrant while we get args ready.
1068 // In addition we use r13 to locate all the interpreter args as
1069 // we must align the stack to 16 bytes on an i2c entry else we
1070 // lose alignment we expect in all compiled code and register
1071 // save code can segv when fxsave instructions find improperly
1072 // aligned stack pointer.
1073
1074 const Register ld_ptr = R15_esp;
1075 const Register value_regs[] = { R22_tmp2, R23_tmp3, R24_tmp4, R25_tmp5, R26_tmp6 };
1076 const int num_value_regs = sizeof(value_regs) / sizeof(Register);
1077 int value_regs_index = 0;
1078
1079 int total_args_passed = sig->length();
1080 int ld_offset = total_args_passed*wordSize;
1081
1082 // Cut-out for having no stack args. Since up to 2 int/oop args are passed
1083 // in registers, we will occasionally have no stack args.
1084 int comp_words_on_stack = 0;
1085 if (comp_args_on_stack) {
1086 // Sig words on the stack are greater-than VMRegImpl::stack0. Those in
1087 // registers are below. By subtracting stack0, we either get a negative
1088 // number (all values in registers) or the maximum stack slot accessed.
1089
1090 // Convert 4-byte c2 stack slots to words.
1091 comp_words_on_stack = align_up(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
1092 // Round up to miminum stack alignment, in wordSize.
1093 comp_words_on_stack = align_up(comp_words_on_stack, 2);
1094 __ resize_frame(-comp_words_on_stack * wordSize, R11_scratch1);
1095 }
1096
1097 // Now generate the shuffle code. Pick up all register args and move the
1098 // rest through register value=Z_R12.
1099 BLOCK_COMMENT("Shuffle arguments");
1100
1101 for (int i = 0; i < total_args_passed; i++) {
1102 BasicType bt = sig->at(i)._bt;
1103 if (bt == T_VOID) {
1104 assert(i > 0 && (sig->at(i - 1)._bt == T_LONG || sig->at(i - 1)._bt == T_DOUBLE), "missing half");
1105 continue;
1106 }
1107
1108 // Pick up 0, 1 or 2 words from ld_ptr.
1109 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
1110 "scrambled load targets?");
1111 VMReg r_1 = regs[i].first();
1112 VMReg r_2 = regs[i].second();
1113 if (!r_1->is_valid()) {
1114 assert(!r_2->is_valid(), "");
1115 continue;
1116 }
1117 if (r_1->is_FloatRegister()) {
1118 if (!r_2->is_valid()) {
1119 __ lfs(r_1->as_FloatRegister(), ld_offset, ld_ptr);
1120 ld_offset-=wordSize;
1121 } else {
1122 // Skip the unused interpreter slot.
1123 __ lfd(r_1->as_FloatRegister(), ld_offset-wordSize, ld_ptr);
1124 ld_offset-=2*wordSize;
1125 }
1126 } else {
1127 Register r;
1128 if (r_1->is_stack()) {
1129 // Must do a memory to memory move thru "value".
1130 r = value_regs[value_regs_index];
1131 value_regs_index = (value_regs_index + 1) % num_value_regs;
1132 } else {
1133 r = r_1->as_Register();
1134 }
1135 if (!r_2->is_valid()) {
1136 // Not sure we need to do this but it shouldn't hurt.
1137 if (is_reference_type(bt) || bt == T_ADDRESS) {
1138 __ ld(r, ld_offset, ld_ptr);
1139 ld_offset-=wordSize;
1140 } else {
1141 __ lwz(r, ld_offset, ld_ptr);
1142 ld_offset-=wordSize;
1143 }
1144 } else {
1145 // In 64bit, longs are given 2 64-bit slots in the interpreter, but the
1146 // data is passed in only 1 slot.
1147 if (bt == T_LONG || bt == T_DOUBLE) {
1148 ld_offset-=wordSize;
1149 }
1150 __ ld(r, ld_offset, ld_ptr);
1151 ld_offset-=wordSize;
1152 }
1153
1154 if (r_1->is_stack()) {
1155 // Now store value where the compiler expects it
1156 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots())*VMRegImpl::stack_slot_size;
1157
1158 if (bt == T_INT || bt == T_FLOAT || bt == T_BOOLEAN ||
1159 bt == T_SHORT || bt == T_CHAR || bt == T_BYTE) {
1160 __ stw(r, st_off, R1_SP);
1161 } else {
1162 __ std(r, st_off, R1_SP);
1163 }
1164 }
1165 }
1166 }
1167
1168 __ push_cont_fastpath(); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
1169
1170 BLOCK_COMMENT("Store method");
1171 // Store method into thread->callee_target.
1172 // We might end up in handle_wrong_method if the callee is
1173 // deoptimized as we race thru here. If that happens we don't want
1174 // to take a safepoint because the caller frame will look
1175 // interpreted and arguments are now "compiled" so it is much better
1176 // to make this transition invisible to the stack walking
1177 // code. Unfortunately if we try and find the callee by normal means
1178 // a safepoint is possible. So we stash the desired callee in the
1179 // thread and the vm will find there should this case occur.
1180 __ std(R19_method, thread_(callee_target));
1181
1182 // Jump to the compiled code just as if compiled code was doing it.
1183 __ bctr();
1184 }
1185
1186 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler* masm,
1187 int comp_args_on_stack,
1188 const GrowableArray<SigEntry>* sig,
1189 const VMRegPair* regs,
1190 const GrowableArray<SigEntry>* sig_cc,
1191 const VMRegPair* regs_cc,
1192 const GrowableArray<SigEntry>* sig_cc_ro,
1193 const VMRegPair* regs_cc_ro,
1194 address entry_address[AdapterBlob::ENTRY_COUNT],
1195 AdapterBlob*& new_adapter,
1196 bool allocate_code_blob) {
1197 // entry: i2c
1198
1199 __ align(CodeEntryAlignment);
1200 entry_address[AdapterBlob::I2C] = __ pc();
1201 gen_i2c_adapter(masm, comp_args_on_stack, sig, regs);
1202
1203
1204 // entry: c2i unverified
1205
1206 __ align(CodeEntryAlignment);
1207 BLOCK_COMMENT("c2i unverified entry");
1208 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
1209
1210 // inline_cache contains a CompiledICData
1211 const Register ic = R19_inline_cache_reg;
1212 const Register ic_klass = R11_scratch1;
1213 const Register receiver_klass = R12_scratch2;
1214 const Register code = R21_tmp1;
1215 const Register ientry = R23_tmp3;
1216
1217 assert_different_registers(ic, ic_klass, receiver_klass, R3_ARG1, code, ientry);
1218 assert(R11_scratch1 == R11, "need prologue scratch register");
1219
1220 Label call_interpreter;
1221
1242
1243 // Bypass the barrier for non-static methods
1244 __ lhz(R0, in_bytes(Method::access_flags_offset()), R19_method);
1245 __ andi_(R0, R0, JVM_ACC_STATIC);
1246 __ beq(CR0, L_skip_barrier); // non-static
1247
1248 Register klass = R11_scratch1;
1249 __ load_method_holder(klass, R19_method);
1250 __ clinit_barrier(klass, R16_thread, &L_skip_barrier /*L_fast_path*/);
1251
1252 __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub(), R0);
1253 __ mtctr(klass);
1254 __ bctr();
1255
1256 __ bind(L_skip_barrier);
1257 entry_address[AdapterBlob::C2I_No_Clinit_Check] = __ pc();
1258
1259 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1260 bs->c2i_entry_barrier(masm, /* tmp register*/ ic_klass, /* tmp register*/ receiver_klass, /* tmp register*/ code);
1261
1262 gen_c2i_adapter(masm, comp_args_on_stack, sig, regs, call_interpreter, ientry);
1263 return;
1264 }
1265
1266 // An oop arg. Must pass a handle not the oop itself.
1267 static void object_move(MacroAssembler* masm,
1268 int frame_size_in_slots,
1269 OopMap* oop_map, int oop_handle_offset,
1270 bool is_receiver, int* receiver_offset,
1271 VMRegPair src, VMRegPair dst,
1272 Register r_caller_sp, Register r_temp_1, Register r_temp_2) {
1273 assert(!is_receiver || (is_receiver && (*receiver_offset == -1)),
1274 "receiver has already been moved");
1275
1276 // We must pass a handle. First figure out the location we use as a handle.
1277
1278 if (src.first()->is_stack()) {
1279 // stack to stack or reg
1280
1281 const Register r_handle = dst.first()->is_stack() ? r_temp_1 : dst.first()->as_Register();
1282 Label skip;
3812 int frame_complete = __ pc() - start;
3813 __ set_last_Java_frame(R1_SP, noreg);
3814 __ call_VM_leaf(CAST_FROM_FN_PTR(address, JfrIntrinsicSupport::return_lease), R16_thread);
3815 address calls_return_pc = __ last_calls_return_pc();
3816 __ reset_last_Java_frame();
3817 __ pop_frame();
3818 __ ld(tmp1, _abi0(lr), R1_SP);
3819 __ mtlr(tmp1);
3820 __ blr();
3821
3822 OopMapSet* oop_maps = new OopMapSet();
3823 OopMap* map = new OopMap(framesize, 0);
3824 oop_maps->add_gc_map(calls_return_pc - start, map);
3825
3826 RuntimeStub* stub = // codeBlob framesize is in words (not VMRegImpl::slot_size)
3827 RuntimeStub::new_runtime_stub(name, &code, frame_complete,
3828 (framesize >> (LogBytesPerWord - LogBytesPerInt)),
3829 oop_maps, false);
3830 return stub;
3831 }
3832 #endif // INCLUDE_JFR
3833
3834 const uint SharedRuntime::java_return_convention_max_int = Argument::n_int_register_parameters_j;
3835 const uint SharedRuntime::java_return_convention_max_float = Argument::n_float_register_parameters_j;
3836
3837 int SharedRuntime::java_return_convention(const BasicType *sig_bt, VMRegPair *regs, int total_args_passed) {
3838 Unimplemented();
3839 return 0;
3840 }
3841
3842 BufferedInlineTypeBlob* SharedRuntime::generate_buffered_inline_type_adapter(const InlineKlass* vk) {
3843 Unimplemented();
3844 return nullptr;
3845 }
3846
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