15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_RISCV_MACROASSEMBLER_RISCV_HPP
28 #define CPU_RISCV_MACROASSEMBLER_RISCV_HPP
29
30 #include "asm/assembler.inline.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "utilities/powerOfTwo.hpp"
35
36 // MacroAssembler extends Assembler by frequently used macros.
37 //
38 // Instructions for which a 'better' code sequence exists depending
39 // on arguments should also go in here.
40
41 class MacroAssembler: public Assembler {
42
43 public:
44
45 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
46
47 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp_reg = t0);
48
49 // Alignment
50 int align(int modulus, int extra_offset = 0);
51
52 static inline void assert_alignment(address pc, int alignment = MacroAssembler::instruction_size) {
53 assert(is_aligned(pc, alignment), "bad alignment");
54 }
121 address entry_point,
122 Register arg_1, Register arg_2, Register arg_3,
123 bool check_exceptions = true);
124
125 void get_vm_result_oop(Register oop_result, Register java_thread);
126 void get_vm_result_metadata(Register metadata_result, Register java_thread);
127
128 // These always tightly bind to MacroAssembler::call_VM_leaf_base
129 // bypassing the virtual implementation
130 void call_VM_leaf(address entry_point,
131 int number_of_arguments = 0);
132 void call_VM_leaf(address entry_point,
133 Register arg_0);
134 void call_VM_leaf(address entry_point,
135 Register arg_0, Register arg_1);
136 void call_VM_leaf(address entry_point,
137 Register arg_0, Register arg_1, Register arg_2);
138
139 // These always tightly bind to MacroAssembler::call_VM_base
140 // bypassing the virtual implementation
141 void super_call_VM_leaf(address entry_point, Register arg_0);
142 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1);
143 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2);
144 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3);
145
146 // last Java Frame (fills frame anchor)
147 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, address last_java_pc, Register tmp);
148 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Label &last_java_pc, Register tmp);
149 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Register last_java_pc);
150
151 // thread in the default location (xthread)
152 void reset_last_Java_frame(bool clear_fp);
153
154 virtual void call_VM_leaf_base(
155 address entry_point, // the entry point
156 int number_of_arguments, // the number of arguments to pop after the call
157 Label* retaddr = nullptr
158 );
159
160 virtual void call_VM_leaf_base(
179 virtual void check_and_handle_earlyret(Register java_thread);
180 virtual void check_and_handle_popframe(Register java_thread);
181
182 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
183 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
184 void resolve_jobject(Register value, Register tmp1, Register tmp2);
185 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
186
187 void movoop(Register dst, jobject obj);
188 void mov_metadata(Register dst, Metadata* obj);
189 void bang_stack_size(Register size, Register tmp);
190 void set_narrow_oop(Register dst, jobject obj);
191 void set_narrow_klass(Register dst, Klass* k);
192
193 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
194 void access_load_at(BasicType type, DecoratorSet decorators, Register dst,
195 Address src, Register tmp1, Register tmp2);
196 void access_store_at(BasicType type, DecoratorSet decorators, Address dst,
197 Register val, Register tmp1, Register tmp2, Register tmp3);
198 void load_klass(Register dst, Register src, Register tmp = t0);
199 void load_narrow_klass_compact(Register dst, Register src);
200 void store_klass(Register dst, Register src, Register tmp = t0);
201 void cmp_klass_beq(Register obj, Register klass,
202 Register tmp1, Register tmp2,
203 Label &L, bool is_far = false);
204 void cmp_klass_bne(Register obj, Register klass,
205 Register tmp1, Register tmp2,
206 Label &L, bool is_far = false);
207
208 void encode_klass_not_null(Register r, Register tmp = t0);
209 void decode_klass_not_null(Register r, Register tmp = t0);
210 void encode_klass_not_null(Register dst, Register src, Register tmp);
211 void decode_klass_not_null(Register dst, Register src, Register tmp);
212 void decode_heap_oop_not_null(Register r);
213 void decode_heap_oop_not_null(Register dst, Register src);
214 void decode_heap_oop(Register d, Register s);
215 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
216 void encode_heap_oop_not_null(Register r);
217 void encode_heap_oop_not_null(Register dst, Register src);
218 void encode_heap_oop(Register d, Register s);
231 // stored using routines that take a jobject.
232 void store_heap_oop_null(Address dst);
233
234 // This dummy is to prevent a call to store_heap_oop from
235 // converting a zero (linked null) into a Register by giving
236 // the compiler two choices it can't resolve
237
238 void store_heap_oop(Address dst, void* dummy);
239
240 // Support for null-checks
241 //
242 // Generates code that causes a null OS exception if the content of reg is null.
243 // If the accessed location is M[reg + offset] and the offset is known, provide the
244 // offset. No explicit code generateion is needed if the offset is within a certain
245 // range (0 <= offset <= page_size).
246
247 virtual void null_check(Register reg, int offset = -1);
248 static bool needs_explicit_null_check(intptr_t offset);
249 static bool uses_implicit_null_check(void* address);
250
251 // interface method calling
252 void lookup_interface_method(Register recv_klass,
253 Register intf_klass,
254 RegisterOrConstant itable_index,
255 Register method_result,
256 Register scan_tmp,
257 Label& no_such_interface,
258 bool return_method = true);
259
260 void lookup_interface_method_stub(Register recv_klass,
261 Register holder_klass,
262 Register resolved_klass,
263 Register method_result,
264 Register temp_reg,
265 Register temp_reg2,
266 int itable_index,
267 Label& L_no_such_interface);
268
269 // virtual method calling
270 // n.n. x86 allows RegisterOrConstant for vtable_index
273 Register method_result);
274
275 // Form an address from base + offset in Rd. Rd my or may not
276 // actually be used: you must use the Address that is returned. It
277 // is up to you to ensure that the shift provided matches the size
278 // of your data.
279 Address form_address(Register Rd, Register base, int64_t byte_offset);
280
281 // Sometimes we get misaligned loads and stores, usually from Unsafe
282 // accesses, and these can exceed the offset range.
283 Address legitimize_address(Register Rd, const Address &adr) {
284 if (adr.getMode() == Address::base_plus_offset) {
285 if (!is_simm12(adr.offset())) {
286 return form_address(Rd, adr.base(), adr.offset());
287 }
288 }
289 return adr;
290 }
291
292 // allocation
293 void tlab_allocate(
294 Register obj, // result: pointer to object after successful allocation
295 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
296 int con_size_in_bytes, // object size in bytes if known at compile time
297 Register tmp1, // temp register
298 Register tmp2, // temp register
299 Label& slow_case, // continuation point of fast allocation fails
300 bool is_far = false
301 );
302
303 // Test sub_klass against super_klass, with fast and slow paths.
304
305 // The fast path produces a tri-state answer: yes / no / maybe-slow.
306 // One of the three labels can be null, meaning take the fall-through.
307 // If super_check_offset is -1, the value is loaded up from super_klass.
308 // No registers are killed, except tmp_reg
309 void check_klass_subtype_fast_path(Register sub_klass,
310 Register super_klass,
311 Register tmp_reg,
312 Label* L_success,
1261
1262 void load_byte_map_base(Register reg);
1263
1264 void bang_stack_with_offset(int offset) {
1265 // stack grows down, caller passes positive offset
1266 assert(offset > 0, "must bang with negative offset");
1267 sub(t0, sp, offset);
1268 sd(zr, Address(t0));
1269 }
1270
1271 virtual void _call_Unimplemented(address call_site) {
1272 mv(t1, call_site);
1273 }
1274
1275 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
1276
1277 // Frame creation and destruction shared between JITs.
1278 void build_frame(int framesize);
1279 void remove_frame(int framesize);
1280
1281 void reserved_stack_check();
1282
1283 void get_polling_page(Register dest, relocInfo::relocType rtype);
1284 void read_polling_page(Register r, int32_t offset, relocInfo::relocType rtype);
1285
1286 // RISCV64 OpenJDK uses three different types of calls:
1287 //
1288 // - far call: auipc reg, pc_relative_offset; jalr ra, reg, offset
1289 // The offset has the range [-(2G + 2K), 2G - 2K). Addresses out of the
1290 // range in the code cache requires indirect call.
1291 // If a jump is needed rather than a call, a far jump 'jalr x0, reg, offset'
1292 // can be used instead.
1293 // All instructions are embedded at a call site.
1294 //
1295 // - indirect call: movptr + jalr
1296 // This can reach anywhere in the address space, but it cannot be patched
1297 // while code is running, so it must only be modified at a safepoint.
1298 // This form of call is most suitable for targets at fixed addresses,
1299 // which will never be patched.
1300 //
1333 int ic_check(int end_alignment = MacroAssembler::instruction_size);
1334
1335 // Support for memory inc/dec
1336 // n.b. increment/decrement calls with an Address destination will
1337 // need to use a scratch register to load the value to be
1338 // incremented. increment/decrement calls which add or subtract a
1339 // constant value other than sign-extended 12-bit immediate will need
1340 // to use a 2nd scratch register to hold the constant. so, an address
1341 // increment/decrement may trash both t0 and t1.
1342
1343 void increment(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1344 void incrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1345
1346 void decrement(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1347 void decrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1348
1349 void clinit_barrier(Register klass, Register tmp, Label* L_fast_path = nullptr, Label* L_slow_path = nullptr);
1350
1351 void load_method_holder_cld(Register result, Register method);
1352 void load_method_holder(Register holder, Register method);
1353
1354 void compute_index(Register str1, Register trailing_zeros, Register match_mask,
1355 Register result, Register char_tmp, Register tmp,
1356 bool haystack_isL);
1357 void compute_match_mask(Register src, Register pattern, Register match_mask,
1358 Register mask1, Register mask2);
1359
1360 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1361 void kernel_crc32(Register crc, Register buf, Register len,
1362 Register table0, Register table1, Register table2, Register table3,
1363 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register tmp6);
1364 void update_word_crc32(Register crc, Register v, Register tmp1, Register tmp2, Register tmp3,
1365 Register table0, Register table1, Register table2, Register table3,
1366 bool upper);
1367 void update_byte_crc32(Register crc, Register val, Register table);
1368
1369 #ifdef COMPILER2
1370 void vector_update_crc32(Register crc, Register buf, Register len,
1371 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5,
1372 Register table0, Register table3);
1789
1790 // the instruction sequence of load_label is as below:
1791 // auipc
1792 // load
1793 static bool check_load_pc_relative_data_dependency(address instr) {
1794 address auipc = instr;
1795 address load = auipc + MacroAssembler::instruction_size;
1796
1797 return extract_rd(load) == extract_rd(auipc) &&
1798 extract_rs1(load) == extract_rd(load);
1799 }
1800
1801 static bool is_li32_at(address instr);
1802 static bool is_pc_relative_at(address branch);
1803
1804 static bool is_membar(address addr) {
1805 return (Bytes::get_native_u4(addr) & 0x7f) == 0b1111 && extract_funct3(addr) == 0;
1806 }
1807 static uint32_t get_membar_kind(address addr);
1808 static void set_membar_kind(address addr, uint32_t order_kind);
1809 };
1810
1811 #ifdef ASSERT
1812 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1813 #endif
1814
1815 #endif // CPU_RISCV_MACROASSEMBLER_RISCV_HPP
|
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_RISCV_MACROASSEMBLER_RISCV_HPP
28 #define CPU_RISCV_MACROASSEMBLER_RISCV_HPP
29
30 #include "asm/assembler.inline.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "utilities/powerOfTwo.hpp"
35 #include "runtime/signature.hpp"
36
37 class ciInlineKlass;
38
39 // MacroAssembler extends Assembler by frequently used macros.
40 //
41 // Instructions for which a 'better' code sequence exists depending
42 // on arguments should also go in here.
43
44 class MacroAssembler: public Assembler {
45
46 public:
47
48 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
49
50 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp_reg = t0);
51
52 // Alignment
53 int align(int modulus, int extra_offset = 0);
54
55 static inline void assert_alignment(address pc, int alignment = MacroAssembler::instruction_size) {
56 assert(is_aligned(pc, alignment), "bad alignment");
57 }
124 address entry_point,
125 Register arg_1, Register arg_2, Register arg_3,
126 bool check_exceptions = true);
127
128 void get_vm_result_oop(Register oop_result, Register java_thread);
129 void get_vm_result_metadata(Register metadata_result, Register java_thread);
130
131 // These always tightly bind to MacroAssembler::call_VM_leaf_base
132 // bypassing the virtual implementation
133 void call_VM_leaf(address entry_point,
134 int number_of_arguments = 0);
135 void call_VM_leaf(address entry_point,
136 Register arg_0);
137 void call_VM_leaf(address entry_point,
138 Register arg_0, Register arg_1);
139 void call_VM_leaf(address entry_point,
140 Register arg_0, Register arg_1, Register arg_2);
141
142 // These always tightly bind to MacroAssembler::call_VM_base
143 // bypassing the virtual implementation
144 void super_call_VM_leaf(address entry_point);
145 void super_call_VM_leaf(address entry_point, Register arg_0);
146 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1);
147 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2);
148 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3);
149
150 // last Java Frame (fills frame anchor)
151 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, address last_java_pc, Register tmp);
152 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Label &last_java_pc, Register tmp);
153 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Register last_java_pc);
154
155 // thread in the default location (xthread)
156 void reset_last_Java_frame(bool clear_fp);
157
158 virtual void call_VM_leaf_base(
159 address entry_point, // the entry point
160 int number_of_arguments, // the number of arguments to pop after the call
161 Label* retaddr = nullptr
162 );
163
164 virtual void call_VM_leaf_base(
183 virtual void check_and_handle_earlyret(Register java_thread);
184 virtual void check_and_handle_popframe(Register java_thread);
185
186 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
187 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
188 void resolve_jobject(Register value, Register tmp1, Register tmp2);
189 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
190
191 void movoop(Register dst, jobject obj);
192 void mov_metadata(Register dst, Metadata* obj);
193 void bang_stack_size(Register size, Register tmp);
194 void set_narrow_oop(Register dst, jobject obj);
195 void set_narrow_klass(Register dst, Klass* k);
196
197 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
198 void access_load_at(BasicType type, DecoratorSet decorators, Register dst,
199 Address src, Register tmp1, Register tmp2);
200 void access_store_at(BasicType type, DecoratorSet decorators, Address dst,
201 Register val, Register tmp1, Register tmp2, Register tmp3);
202 void load_klass(Register dst, Register src, Register tmp = t0);
203 void load_prototype_header(Register dst, Register src, Register tmp = t0);
204 void load_narrow_klass_compact(Register dst, Register src);
205 void store_klass(Register dst, Register src, Register tmp = t0);
206 void cmp_klass_beq(Register obj, Register klass,
207 Register tmp1, Register tmp2,
208 Label &L, bool is_far = false);
209 void cmp_klass_bne(Register obj, Register klass,
210 Register tmp1, Register tmp2,
211 Label &L, bool is_far = false);
212
213 void encode_klass_not_null(Register r, Register tmp = t0);
214 void decode_klass_not_null(Register r, Register tmp = t0);
215 void encode_klass_not_null(Register dst, Register src, Register tmp);
216 void decode_klass_not_null(Register dst, Register src, Register tmp);
217 void decode_heap_oop_not_null(Register r);
218 void decode_heap_oop_not_null(Register dst, Register src);
219 void decode_heap_oop(Register d, Register s);
220 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
221 void encode_heap_oop_not_null(Register r);
222 void encode_heap_oop_not_null(Register dst, Register src);
223 void encode_heap_oop(Register d, Register s);
236 // stored using routines that take a jobject.
237 void store_heap_oop_null(Address dst);
238
239 // This dummy is to prevent a call to store_heap_oop from
240 // converting a zero (linked null) into a Register by giving
241 // the compiler two choices it can't resolve
242
243 void store_heap_oop(Address dst, void* dummy);
244
245 // Support for null-checks
246 //
247 // Generates code that causes a null OS exception if the content of reg is null.
248 // If the accessed location is M[reg + offset] and the offset is known, provide the
249 // offset. No explicit code generateion is needed if the offset is within a certain
250 // range (0 <= offset <= page_size).
251
252 virtual void null_check(Register reg, int offset = -1);
253 static bool needs_explicit_null_check(intptr_t offset);
254 static bool uses_implicit_null_check(void* address);
255
256 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
257 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type);
258 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
259
260 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
261 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
262 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t tst_bit, bool jmp_set, Label& jmp_label);
263 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
264 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
265 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
266 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
267
268 // Check array klass layout helper for flat or null-free arrays...
269 void test_flat_array_layout(Register lh, Label& is_flat_array);
270
271 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
272
273 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
274
275 // inline type data payload offsets...
276 void payload_offset(Register inline_klass, Register offset);
277 void payload_address(Register oop, Register data, Register inline_klass);
278
279 // interface method calling
280 void lookup_interface_method(Register recv_klass,
281 Register intf_klass,
282 RegisterOrConstant itable_index,
283 Register method_result,
284 Register scan_tmp,
285 Label& no_such_interface,
286 bool return_method = true);
287
288 void lookup_interface_method_stub(Register recv_klass,
289 Register holder_klass,
290 Register resolved_klass,
291 Register method_result,
292 Register temp_reg,
293 Register temp_reg2,
294 int itable_index,
295 Label& L_no_such_interface);
296
297 // virtual method calling
298 // n.n. x86 allows RegisterOrConstant for vtable_index
301 Register method_result);
302
303 // Form an address from base + offset in Rd. Rd my or may not
304 // actually be used: you must use the Address that is returned. It
305 // is up to you to ensure that the shift provided matches the size
306 // of your data.
307 Address form_address(Register Rd, Register base, int64_t byte_offset);
308
309 // Sometimes we get misaligned loads and stores, usually from Unsafe
310 // accesses, and these can exceed the offset range.
311 Address legitimize_address(Register Rd, const Address &adr) {
312 if (adr.getMode() == Address::base_plus_offset) {
313 if (!is_simm12(adr.offset())) {
314 return form_address(Rd, adr.base(), adr.offset());
315 }
316 }
317 return adr;
318 }
319
320 // allocation
321
322 void tlab_allocate(
323 Register obj, // result: pointer to object after successful allocation
324 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
325 int con_size_in_bytes, // object size in bytes if known at compile time
326 Register tmp1, // temp register
327 Register tmp2, // temp register
328 Label& slow_case, // continuation point of fast allocation fails
329 bool is_far = false
330 );
331
332 // Test sub_klass against super_klass, with fast and slow paths.
333
334 // The fast path produces a tri-state answer: yes / no / maybe-slow.
335 // One of the three labels can be null, meaning take the fall-through.
336 // If super_check_offset is -1, the value is loaded up from super_klass.
337 // No registers are killed, except tmp_reg
338 void check_klass_subtype_fast_path(Register sub_klass,
339 Register super_klass,
340 Register tmp_reg,
341 Label* L_success,
1290
1291 void load_byte_map_base(Register reg);
1292
1293 void bang_stack_with_offset(int offset) {
1294 // stack grows down, caller passes positive offset
1295 assert(offset > 0, "must bang with negative offset");
1296 sub(t0, sp, offset);
1297 sd(zr, Address(t0));
1298 }
1299
1300 virtual void _call_Unimplemented(address call_site) {
1301 mv(t1, call_site);
1302 }
1303
1304 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
1305
1306 // Frame creation and destruction shared between JITs.
1307 void build_frame(int framesize);
1308 void remove_frame(int framesize);
1309
1310 void verified_entry(Compile* C, int sp_inc);
1311
1312 void reserved_stack_check();
1313
1314 void get_polling_page(Register dest, relocInfo::relocType rtype);
1315 void read_polling_page(Register r, int32_t offset, relocInfo::relocType rtype);
1316
1317 // RISCV64 OpenJDK uses three different types of calls:
1318 //
1319 // - far call: auipc reg, pc_relative_offset; jalr ra, reg, offset
1320 // The offset has the range [-(2G + 2K), 2G - 2K). Addresses out of the
1321 // range in the code cache requires indirect call.
1322 // If a jump is needed rather than a call, a far jump 'jalr x0, reg, offset'
1323 // can be used instead.
1324 // All instructions are embedded at a call site.
1325 //
1326 // - indirect call: movptr + jalr
1327 // This can reach anywhere in the address space, but it cannot be patched
1328 // while code is running, so it must only be modified at a safepoint.
1329 // This form of call is most suitable for targets at fixed addresses,
1330 // which will never be patched.
1331 //
1364 int ic_check(int end_alignment = MacroAssembler::instruction_size);
1365
1366 // Support for memory inc/dec
1367 // n.b. increment/decrement calls with an Address destination will
1368 // need to use a scratch register to load the value to be
1369 // incremented. increment/decrement calls which add or subtract a
1370 // constant value other than sign-extended 12-bit immediate will need
1371 // to use a 2nd scratch register to hold the constant. so, an address
1372 // increment/decrement may trash both t0 and t1.
1373
1374 void increment(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1375 void incrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1376
1377 void decrement(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1378 void decrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1379
1380 void clinit_barrier(Register klass, Register tmp, Label* L_fast_path = nullptr, Label* L_slow_path = nullptr);
1381
1382 void load_method_holder_cld(Register result, Register method);
1383 void load_method_holder(Register holder, Register method);
1384 void load_metadata(Register dst, Register src);
1385
1386 void compute_index(Register str1, Register trailing_zeros, Register match_mask,
1387 Register result, Register char_tmp, Register tmp,
1388 bool haystack_isL);
1389 void compute_match_mask(Register src, Register pattern, Register match_mask,
1390 Register mask1, Register mask2);
1391
1392 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1393 void kernel_crc32(Register crc, Register buf, Register len,
1394 Register table0, Register table1, Register table2, Register table3,
1395 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register tmp6);
1396 void update_word_crc32(Register crc, Register v, Register tmp1, Register tmp2, Register tmp3,
1397 Register table0, Register table1, Register table2, Register table3,
1398 bool upper);
1399 void update_byte_crc32(Register crc, Register val, Register table);
1400
1401 #ifdef COMPILER2
1402 void vector_update_crc32(Register crc, Register buf, Register len,
1403 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5,
1404 Register table0, Register table3);
1821
1822 // the instruction sequence of load_label is as below:
1823 // auipc
1824 // load
1825 static bool check_load_pc_relative_data_dependency(address instr) {
1826 address auipc = instr;
1827 address load = auipc + MacroAssembler::instruction_size;
1828
1829 return extract_rd(load) == extract_rd(auipc) &&
1830 extract_rs1(load) == extract_rd(load);
1831 }
1832
1833 static bool is_li32_at(address instr);
1834 static bool is_pc_relative_at(address branch);
1835
1836 static bool is_membar(address addr) {
1837 return (Bytes::get_native_u4(addr) & 0x7f) == 0b1111 && extract_funct3(addr) == 0;
1838 }
1839 static uint32_t get_membar_kind(address addr);
1840 static void set_membar_kind(address addr, uint32_t order_kind);
1841
1842 public:
1843 // Inline type specific methods
1844 #include "asm/macroAssembler_common.hpp"
1845 };
1846
1847 #ifdef ASSERT
1848 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1849 #endif
1850
1851 #endif // CPU_RISCV_MACROASSEMBLER_RISCV_HPP
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