15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_RISCV_MACROASSEMBLER_RISCV_HPP
28 #define CPU_RISCV_MACROASSEMBLER_RISCV_HPP
29
30 #include "asm/assembler.inline.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "utilities/powerOfTwo.hpp"
35
36 // MacroAssembler extends Assembler by frequently used macros.
37 //
38 // Instructions for which a 'better' code sequence exists depending
39 // on arguments should also go in here.
40
41 class MacroAssembler: public Assembler {
42
43 public:
44
45 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
46
47 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp_reg = t0);
48
49 // Alignment
50 int align(int modulus, int extra_offset = 0);
51
52 static inline void assert_alignment(address pc, int alignment = MacroAssembler::instruction_size) {
53 assert(is_aligned(pc, alignment), "bad alignment");
54 }
121 address entry_point,
122 Register arg_1, Register arg_2, Register arg_3,
123 bool check_exceptions = true);
124
125 void get_vm_result_oop(Register oop_result, Register java_thread);
126 void get_vm_result_metadata(Register metadata_result, Register java_thread);
127
128 // These always tightly bind to MacroAssembler::call_VM_leaf_base
129 // bypassing the virtual implementation
130 void call_VM_leaf(address entry_point,
131 int number_of_arguments = 0);
132 void call_VM_leaf(address entry_point,
133 Register arg_0);
134 void call_VM_leaf(address entry_point,
135 Register arg_0, Register arg_1);
136 void call_VM_leaf(address entry_point,
137 Register arg_0, Register arg_1, Register arg_2);
138
139 // These always tightly bind to MacroAssembler::call_VM_base
140 // bypassing the virtual implementation
141 void super_call_VM_leaf(address entry_point, Register arg_0);
142 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1);
143 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2);
144 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3);
145
146 // last Java Frame (fills frame anchor)
147 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, address last_java_pc, Register tmp);
148 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Label &last_java_pc, Register tmp);
149 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Register last_java_pc);
150
151 // thread in the default location (xthread)
152 void reset_last_Java_frame(bool clear_fp);
153
154 virtual void call_VM_leaf_base(
155 address entry_point, // the entry point
156 int number_of_arguments, // the number of arguments to pop after the call
157 Label* retaddr = nullptr
158 );
159
160 virtual void call_VM_leaf_base(
179 virtual void check_and_handle_earlyret(Register java_thread);
180 virtual void check_and_handle_popframe(Register java_thread);
181
182 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
183 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
184 void resolve_jobject(Register value, Register tmp1, Register tmp2);
185 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
186
187 void movoop(Register dst, jobject obj);
188 void mov_metadata(Register dst, Metadata* obj);
189 void bang_stack_size(Register size, Register tmp);
190 void set_narrow_oop(Register dst, jobject obj);
191 void set_narrow_klass(Register dst, Klass* k);
192
193 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
194 void access_load_at(BasicType type, DecoratorSet decorators, Register dst,
195 Address src, Register tmp1, Register tmp2);
196 void access_store_at(BasicType type, DecoratorSet decorators, Address dst,
197 Register val, Register tmp1, Register tmp2, Register tmp3);
198 void load_klass(Register dst, Register src, Register tmp = t0);
199 void load_narrow_klass_compact(Register dst, Register src);
200 void load_narrow_klass(Register dst, Register src);
201 void store_klass(Register dst, Register src, Register tmp = t0);
202 void cmp_klass_beq(Register obj, Register klass,
203 Register tmp1, Register tmp2,
204 Label &L, bool is_far = false);
205 void cmp_klass_bne(Register obj, Register klass,
206 Register tmp1, Register tmp2,
207 Label &L, bool is_far = false);
208
209 void encode_klass_not_null(Register r, Register tmp = t0);
210 void decode_klass_not_null(Register r, Register tmp = t0);
211 void encode_klass_not_null(Register dst, Register src, Register tmp);
212 void decode_klass_not_null(Register dst, Register src, Register tmp);
213 void decode_heap_oop_not_null(Register r);
214 void decode_heap_oop_not_null(Register dst, Register src);
215 void decode_heap_oop(Register d, Register s);
216 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
217 void encode_heap_oop_not_null(Register r);
218 void encode_heap_oop_not_null(Register dst, Register src);
232 // stored using routines that take a jobject.
233 void store_heap_oop_null(Address dst);
234
235 // This dummy is to prevent a call to store_heap_oop from
236 // converting a zero (linked null) into a Register by giving
237 // the compiler two choices it can't resolve
238
239 void store_heap_oop(Address dst, void* dummy);
240
241 // Support for null-checks
242 //
243 // Generates code that causes a null OS exception if the content of reg is null.
244 // If the accessed location is M[reg + offset] and the offset is known, provide the
245 // offset. No explicit code generateion is needed if the offset is within a certain
246 // range (0 <= offset <= page_size).
247
248 virtual void null_check(Register reg, int offset = -1);
249 static bool needs_explicit_null_check(intptr_t offset);
250 static bool uses_implicit_null_check(void* address);
251
252 // interface method calling
253 void lookup_interface_method(Register recv_klass,
254 Register intf_klass,
255 RegisterOrConstant itable_index,
256 Register method_result,
257 Register scan_tmp,
258 Label& no_such_interface,
259 bool return_method = true);
260
261 void lookup_interface_method_stub(Register recv_klass,
262 Register holder_klass,
263 Register resolved_klass,
264 Register method_result,
265 Register temp_reg,
266 Register temp_reg2,
267 int itable_index,
268 Label& L_no_such_interface);
269
270 // virtual method calling
271 // n.n. x86 allows RegisterOrConstant for vtable_index
274 Register method_result);
275
276 // Form an address from base + offset in Rd. Rd my or may not
277 // actually be used: you must use the Address that is returned. It
278 // is up to you to ensure that the shift provided matches the size
279 // of your data.
280 Address form_address(Register Rd, Register base, int64_t byte_offset);
281
282 // Sometimes we get misaligned loads and stores, usually from Unsafe
283 // accesses, and these can exceed the offset range.
284 Address legitimize_address(Register Rd, const Address &adr) {
285 if (adr.getMode() == Address::base_plus_offset) {
286 if (!is_simm12(adr.offset())) {
287 return form_address(Rd, adr.base(), adr.offset());
288 }
289 }
290 return adr;
291 }
292
293 // allocation
294 void tlab_allocate(
295 Register obj, // result: pointer to object after successful allocation
296 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
297 int con_size_in_bytes, // object size in bytes if known at compile time
298 Register tmp1, // temp register
299 Register tmp2, // temp register
300 Label& slow_case, // continuation point of fast allocation fails
301 bool is_far = false
302 );
303
304 // Test sub_klass against super_klass, with fast and slow paths.
305
306 // The fast path produces a tri-state answer: yes / no / maybe-slow.
307 // One of the three labels can be null, meaning take the fall-through.
308 // If super_check_offset is -1, the value is loaded up from super_klass.
309 // No registers are killed, except tmp_reg
310 void check_klass_subtype_fast_path(Register sub_klass,
311 Register super_klass,
312 Register tmp_reg,
313 Label* L_success,
1262
1263 void load_byte_map_base(Register reg);
1264
1265 void bang_stack_with_offset(int offset) {
1266 // stack grows down, caller passes positive offset
1267 assert(offset > 0, "must bang with negative offset");
1268 sub(t0, sp, offset);
1269 sd(zr, Address(t0));
1270 }
1271
1272 virtual void _call_Unimplemented(address call_site) {
1273 mv(t1, call_site);
1274 }
1275
1276 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
1277
1278 // Frame creation and destruction shared between JITs.
1279 void build_frame(int framesize);
1280 void remove_frame(int framesize);
1281
1282 void reserved_stack_check();
1283
1284 void get_polling_page(Register dest, relocInfo::relocType rtype);
1285 void read_polling_page(Register r, int32_t offset, relocInfo::relocType rtype);
1286
1287 // RISCV64 OpenJDK uses three different types of calls:
1288 //
1289 // - far call: auipc reg, pc_relative_offset; jalr ra, reg, offset
1290 // The offset has the range [-(2G + 2K), 2G - 2K). Addresses out of the
1291 // range in the code cache requires indirect call.
1292 // If a jump is needed rather than a call, a far jump 'jalr x0, reg, offset'
1293 // can be used instead.
1294 // All instructions are embedded at a call site.
1295 //
1296 // - indirect call: movptr + jalr
1297 // This can reach anywhere in the address space, but it cannot be patched
1298 // while code is running, so it must only be modified at a safepoint.
1299 // This form of call is most suitable for targets at fixed addresses,
1300 // which will never be patched.
1301 //
1334 int ic_check(int end_alignment = MacroAssembler::instruction_size);
1335
1336 // Support for memory inc/dec
1337 // n.b. increment/decrement calls with an Address destination will
1338 // need to use a scratch register to load the value to be
1339 // incremented. increment/decrement calls which add or subtract a
1340 // constant value other than sign-extended 12-bit immediate will need
1341 // to use a 2nd scratch register to hold the constant. so, an address
1342 // increment/decrement may trash both t0 and t1.
1343
1344 void increment(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1345 void incrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1346
1347 void decrement(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1348 void decrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1349
1350 void clinit_barrier(Register klass, Register tmp, Label* L_fast_path = nullptr, Label* L_slow_path = nullptr);
1351
1352 void load_method_holder_cld(Register result, Register method);
1353 void load_method_holder(Register holder, Register method);
1354
1355 void compute_index(Register str1, Register trailing_zeros, Register match_mask,
1356 Register result, Register char_tmp, Register tmp,
1357 bool haystack_isL);
1358 void compute_match_mask(Register src, Register pattern, Register match_mask,
1359 Register mask1, Register mask2);
1360
1361 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1362 void kernel_crc32(Register crc, Register buf, Register len,
1363 Register table0, Register table1, Register table2, Register table3,
1364 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register tmp6);
1365 void update_word_crc32(Register crc, Register v, Register tmp1, Register tmp2, Register tmp3,
1366 Register table0, Register table1, Register table2, Register table3,
1367 bool upper);
1368 void update_byte_crc32(Register crc, Register val, Register table);
1369
1370 #ifdef COMPILER2
1371 void vector_update_crc32(Register crc, Register buf, Register len,
1372 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5,
1373 Register table0, Register table3);
1790
1791 // the instruction sequence of load_label is as below:
1792 // auipc
1793 // load
1794 static bool check_load_pc_relative_data_dependency(address instr) {
1795 address auipc = instr;
1796 address load = auipc + MacroAssembler::instruction_size;
1797
1798 return extract_rd(load) == extract_rd(auipc) &&
1799 extract_rs1(load) == extract_rd(load);
1800 }
1801
1802 static bool is_li32_at(address instr);
1803 static bool is_pc_relative_at(address branch);
1804
1805 static bool is_membar(address addr) {
1806 return (Bytes::get_native_u4(addr) & 0x7f) == 0b1111 && extract_funct3(addr) == 0;
1807 }
1808 static uint32_t get_membar_kind(address addr);
1809 static void set_membar_kind(address addr, uint32_t order_kind);
1810 };
1811
1812 #ifdef ASSERT
1813 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1814 #endif
1815
1816 #endif // CPU_RISCV_MACROASSEMBLER_RISCV_HPP
|
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_RISCV_MACROASSEMBLER_RISCV_HPP
28 #define CPU_RISCV_MACROASSEMBLER_RISCV_HPP
29
30 #include "asm/assembler.inline.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "utilities/powerOfTwo.hpp"
35 #include "runtime/signature.hpp"
36
37 class ciInlineKlass;
38
39 // MacroAssembler extends Assembler by frequently used macros.
40 //
41 // Instructions for which a 'better' code sequence exists depending
42 // on arguments should also go in here.
43
44 class MacroAssembler: public Assembler {
45
46 public:
47
48 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
49
50 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp_reg = t0);
51
52 // Alignment
53 int align(int modulus, int extra_offset = 0);
54
55 static inline void assert_alignment(address pc, int alignment = MacroAssembler::instruction_size) {
56 assert(is_aligned(pc, alignment), "bad alignment");
57 }
124 address entry_point,
125 Register arg_1, Register arg_2, Register arg_3,
126 bool check_exceptions = true);
127
128 void get_vm_result_oop(Register oop_result, Register java_thread);
129 void get_vm_result_metadata(Register metadata_result, Register java_thread);
130
131 // These always tightly bind to MacroAssembler::call_VM_leaf_base
132 // bypassing the virtual implementation
133 void call_VM_leaf(address entry_point,
134 int number_of_arguments = 0);
135 void call_VM_leaf(address entry_point,
136 Register arg_0);
137 void call_VM_leaf(address entry_point,
138 Register arg_0, Register arg_1);
139 void call_VM_leaf(address entry_point,
140 Register arg_0, Register arg_1, Register arg_2);
141
142 // These always tightly bind to MacroAssembler::call_VM_base
143 // bypassing the virtual implementation
144 void super_call_VM_leaf(address entry_point);
145 void super_call_VM_leaf(address entry_point, Register arg_0);
146 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1);
147 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2);
148 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3);
149
150 // last Java Frame (fills frame anchor)
151 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, address last_java_pc, Register tmp);
152 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Label &last_java_pc, Register tmp);
153 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Register last_java_pc);
154
155 // thread in the default location (xthread)
156 void reset_last_Java_frame(bool clear_fp);
157
158 virtual void call_VM_leaf_base(
159 address entry_point, // the entry point
160 int number_of_arguments, // the number of arguments to pop after the call
161 Label* retaddr = nullptr
162 );
163
164 virtual void call_VM_leaf_base(
183 virtual void check_and_handle_earlyret(Register java_thread);
184 virtual void check_and_handle_popframe(Register java_thread);
185
186 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
187 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
188 void resolve_jobject(Register value, Register tmp1, Register tmp2);
189 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
190
191 void movoop(Register dst, jobject obj);
192 void mov_metadata(Register dst, Metadata* obj);
193 void bang_stack_size(Register size, Register tmp);
194 void set_narrow_oop(Register dst, jobject obj);
195 void set_narrow_klass(Register dst, Klass* k);
196
197 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
198 void access_load_at(BasicType type, DecoratorSet decorators, Register dst,
199 Address src, Register tmp1, Register tmp2);
200 void access_store_at(BasicType type, DecoratorSet decorators, Address dst,
201 Register val, Register tmp1, Register tmp2, Register tmp3);
202 void load_klass(Register dst, Register src, Register tmp = t0);
203 void load_prototype_header(Register dst, Register src, Register tmp = t0);
204 void load_narrow_klass_compact(Register dst, Register src);
205 void load_narrow_klass(Register dst, Register src);
206 void store_klass(Register dst, Register src, Register tmp = t0);
207 void cmp_klass_beq(Register obj, Register klass,
208 Register tmp1, Register tmp2,
209 Label &L, bool is_far = false);
210 void cmp_klass_bne(Register obj, Register klass,
211 Register tmp1, Register tmp2,
212 Label &L, bool is_far = false);
213
214 void encode_klass_not_null(Register r, Register tmp = t0);
215 void decode_klass_not_null(Register r, Register tmp = t0);
216 void encode_klass_not_null(Register dst, Register src, Register tmp);
217 void decode_klass_not_null(Register dst, Register src, Register tmp);
218 void decode_heap_oop_not_null(Register r);
219 void decode_heap_oop_not_null(Register dst, Register src);
220 void decode_heap_oop(Register d, Register s);
221 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
222 void encode_heap_oop_not_null(Register r);
223 void encode_heap_oop_not_null(Register dst, Register src);
237 // stored using routines that take a jobject.
238 void store_heap_oop_null(Address dst);
239
240 // This dummy is to prevent a call to store_heap_oop from
241 // converting a zero (linked null) into a Register by giving
242 // the compiler two choices it can't resolve
243
244 void store_heap_oop(Address dst, void* dummy);
245
246 // Support for null-checks
247 //
248 // Generates code that causes a null OS exception if the content of reg is null.
249 // If the accessed location is M[reg + offset] and the offset is known, provide the
250 // offset. No explicit code generateion is needed if the offset is within a certain
251 // range (0 <= offset <= page_size).
252
253 virtual void null_check(Register reg, int offset = -1);
254 static bool needs_explicit_null_check(intptr_t offset);
255 static bool uses_implicit_null_check(void* address);
256
257 void test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free);
258 void test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type);
259 void test_field_is_flat(Register flags, Register temp_reg, Label& is_flat);
260
261 void test_markword_is_inline_type(Register markword, Label& is_inline_type);
262 void test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type, bool can_be_null = true);
263 void test_oop_prototype_bit(Register oop, Register temp_reg, int32_t tst_bit, bool jmp_set, Label& jmp_label);
264 void test_flat_array_oop(Register klass, Register temp_reg, Label& is_flat_array);
265 void test_null_free_array_oop(Register oop, Register temp_reg, Label& is_null_free_array);
266 void test_non_flat_array_oop(Register oop, Register temp_reg, Label&is_non_flat_array);
267 void test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array);
268
269 // Check array klass layout helper for flat or null-free arrays...
270 void test_flat_array_layout(Register lh, Label& is_flat_array);
271
272 void inline_layout_info(Register holder_klass, Register index, Register layout_info);
273
274 void flat_field_copy(DecoratorSet decorators, Register src, Register dst, Register inline_layout_info);
275
276 // inline type data payload offsets...
277 void payload_offset(Register inline_klass, Register offset);
278 void payload_address(Register oop, Register data, Register inline_klass);
279
280 // interface method calling
281 void lookup_interface_method(Register recv_klass,
282 Register intf_klass,
283 RegisterOrConstant itable_index,
284 Register method_result,
285 Register scan_tmp,
286 Label& no_such_interface,
287 bool return_method = true);
288
289 void lookup_interface_method_stub(Register recv_klass,
290 Register holder_klass,
291 Register resolved_klass,
292 Register method_result,
293 Register temp_reg,
294 Register temp_reg2,
295 int itable_index,
296 Label& L_no_such_interface);
297
298 // virtual method calling
299 // n.n. x86 allows RegisterOrConstant for vtable_index
302 Register method_result);
303
304 // Form an address from base + offset in Rd. Rd my or may not
305 // actually be used: you must use the Address that is returned. It
306 // is up to you to ensure that the shift provided matches the size
307 // of your data.
308 Address form_address(Register Rd, Register base, int64_t byte_offset);
309
310 // Sometimes we get misaligned loads and stores, usually from Unsafe
311 // accesses, and these can exceed the offset range.
312 Address legitimize_address(Register Rd, const Address &adr) {
313 if (adr.getMode() == Address::base_plus_offset) {
314 if (!is_simm12(adr.offset())) {
315 return form_address(Rd, adr.base(), adr.offset());
316 }
317 }
318 return adr;
319 }
320
321 // allocation
322
323 void tlab_allocate(
324 Register obj, // result: pointer to object after successful allocation
325 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
326 int con_size_in_bytes, // object size in bytes if known at compile time
327 Register tmp1, // temp register
328 Register tmp2, // temp register
329 Label& slow_case, // continuation point of fast allocation fails
330 bool is_far = false
331 );
332
333 // Test sub_klass against super_klass, with fast and slow paths.
334
335 // The fast path produces a tri-state answer: yes / no / maybe-slow.
336 // One of the three labels can be null, meaning take the fall-through.
337 // If super_check_offset is -1, the value is loaded up from super_klass.
338 // No registers are killed, except tmp_reg
339 void check_klass_subtype_fast_path(Register sub_klass,
340 Register super_klass,
341 Register tmp_reg,
342 Label* L_success,
1291
1292 void load_byte_map_base(Register reg);
1293
1294 void bang_stack_with_offset(int offset) {
1295 // stack grows down, caller passes positive offset
1296 assert(offset > 0, "must bang with negative offset");
1297 sub(t0, sp, offset);
1298 sd(zr, Address(t0));
1299 }
1300
1301 virtual void _call_Unimplemented(address call_site) {
1302 mv(t1, call_site);
1303 }
1304
1305 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
1306
1307 // Frame creation and destruction shared between JITs.
1308 void build_frame(int framesize);
1309 void remove_frame(int framesize);
1310
1311 void verified_entry(Compile* C, int sp_inc);
1312
1313 void reserved_stack_check();
1314
1315 void get_polling_page(Register dest, relocInfo::relocType rtype);
1316 void read_polling_page(Register r, int32_t offset, relocInfo::relocType rtype);
1317
1318 // RISCV64 OpenJDK uses three different types of calls:
1319 //
1320 // - far call: auipc reg, pc_relative_offset; jalr ra, reg, offset
1321 // The offset has the range [-(2G + 2K), 2G - 2K). Addresses out of the
1322 // range in the code cache requires indirect call.
1323 // If a jump is needed rather than a call, a far jump 'jalr x0, reg, offset'
1324 // can be used instead.
1325 // All instructions are embedded at a call site.
1326 //
1327 // - indirect call: movptr + jalr
1328 // This can reach anywhere in the address space, but it cannot be patched
1329 // while code is running, so it must only be modified at a safepoint.
1330 // This form of call is most suitable for targets at fixed addresses,
1331 // which will never be patched.
1332 //
1365 int ic_check(int end_alignment = MacroAssembler::instruction_size);
1366
1367 // Support for memory inc/dec
1368 // n.b. increment/decrement calls with an Address destination will
1369 // need to use a scratch register to load the value to be
1370 // incremented. increment/decrement calls which add or subtract a
1371 // constant value other than sign-extended 12-bit immediate will need
1372 // to use a 2nd scratch register to hold the constant. so, an address
1373 // increment/decrement may trash both t0 and t1.
1374
1375 void increment(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1376 void incrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1377
1378 void decrement(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1379 void decrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1380
1381 void clinit_barrier(Register klass, Register tmp, Label* L_fast_path = nullptr, Label* L_slow_path = nullptr);
1382
1383 void load_method_holder_cld(Register result, Register method);
1384 void load_method_holder(Register holder, Register method);
1385 void load_metadata(Register dst, Register src);
1386
1387 void compute_index(Register str1, Register trailing_zeros, Register match_mask,
1388 Register result, Register char_tmp, Register tmp,
1389 bool haystack_isL);
1390 void compute_match_mask(Register src, Register pattern, Register match_mask,
1391 Register mask1, Register mask2);
1392
1393 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1394 void kernel_crc32(Register crc, Register buf, Register len,
1395 Register table0, Register table1, Register table2, Register table3,
1396 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register tmp6);
1397 void update_word_crc32(Register crc, Register v, Register tmp1, Register tmp2, Register tmp3,
1398 Register table0, Register table1, Register table2, Register table3,
1399 bool upper);
1400 void update_byte_crc32(Register crc, Register val, Register table);
1401
1402 #ifdef COMPILER2
1403 void vector_update_crc32(Register crc, Register buf, Register len,
1404 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5,
1405 Register table0, Register table3);
1822
1823 // the instruction sequence of load_label is as below:
1824 // auipc
1825 // load
1826 static bool check_load_pc_relative_data_dependency(address instr) {
1827 address auipc = instr;
1828 address load = auipc + MacroAssembler::instruction_size;
1829
1830 return extract_rd(load) == extract_rd(auipc) &&
1831 extract_rs1(load) == extract_rd(load);
1832 }
1833
1834 static bool is_li32_at(address instr);
1835 static bool is_pc_relative_at(address branch);
1836
1837 static bool is_membar(address addr) {
1838 return (Bytes::get_native_u4(addr) & 0x7f) == 0b1111 && extract_funct3(addr) == 0;
1839 }
1840 static uint32_t get_membar_kind(address addr);
1841 static void set_membar_kind(address addr, uint32_t order_kind);
1842
1843 public:
1844 // Inline type specific methods
1845 #include "asm/macroAssembler_common.hpp"
1846 };
1847
1848 #ifdef ASSERT
1849 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1850 #endif
1851
1852 #endif // CPU_RISCV_MACROASSEMBLER_RISCV_HPP
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