321 // VM needs caller's callsite
322 // VM needs target method
323 // This needs to be a long call since we will relocate this adapter to
324 // the codeBuffer and it may not reach
325
326 #ifndef PRODUCT
327 assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
328 #endif
329
330 __ mv(c_rarg0, xmethod);
331 __ mv(c_rarg1, ra);
332 __ rt_call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
333
334 __ pop_CPU_state();
335 // restore sp
336 __ leave();
337 __ bind(L);
338 }
339
340 static void gen_c2i_adapter(MacroAssembler *masm,
341 int total_args_passed,
342 int comp_args_on_stack,
343 const BasicType *sig_bt,
344 const VMRegPair *regs,
345 Label& skip_fixup) {
346 // Before we get into the guts of the C2I adapter, see if we should be here
347 // at all. We've come from compiled code and are attempting to jump to the
348 // interpreter, which means the caller made a static call to get here
349 // (vcalls always get a compiled target if there is one). Check for a
350 // compiled target. If there is one, we need to patch the caller's call.
351 patch_callers_callsite(masm);
352
353 __ bind(skip_fixup);
354
355 int words_pushed = 0;
356
357 // Since all args are passed on the stack, total_args_passed *
358 // Interpreter::stackElementSize is the space we need.
359
360 int extraspace = total_args_passed * Interpreter::stackElementSize;
361
362 __ mv(x19_sender_sp, sp);
363
364 // stack is aligned, keep it that way
365 extraspace = align_up(extraspace, 2 * wordSize);
366
367 if (extraspace) {
368 __ sub(sp, sp, extraspace);
369 }
370
371 // Now write the args into the outgoing interpreter space
372 for (int i = 0; i < total_args_passed; i++) {
373 if (sig_bt[i] == T_VOID) {
374 assert(i > 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "missing half");
375 continue;
376 }
377
378 // offset to start parameters
379 int st_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
380 int next_off = st_off - Interpreter::stackElementSize;
381
382 // Say 4 args:
383 // i st_off
384 // 0 32 T_LONG
385 // 1 24 T_VOID
386 // 2 16 T_OBJECT
387 // 3 8 T_BOOL
388 // - 0 return address
389 //
390 // However to make thing extra confusing. Because we can fit a Java long/double in
391 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
392 // leaves one slot empty and only stores to a single slot. In this case the
393 // slot that is occupied is the T_VOID slot. See I said it was confusing.
394
395 VMReg r_1 = regs[i].first();
396 VMReg r_2 = regs[i].second();
397 if (!r_1->is_valid()) {
398 assert(!r_2->is_valid(), "");
399 continue;
400 }
401 if (r_1->is_stack()) {
402 // memory to memory use t0
403 int ld_off = (r_1->reg2stack() * VMRegImpl::stack_slot_size
404 + extraspace
405 + words_pushed * wordSize);
406 if (!r_2->is_valid()) {
407 __ lwu(t0, Address(sp, ld_off));
408 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
409 } else {
410 __ ld(t0, Address(sp, ld_off), /*temp register*/esp);
411
412 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
413 // T_DOUBLE and T_LONG use two slots in the interpreter
414 if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
415 // ld_off == LSW, ld_off+wordSize == MSW
416 // st_off == MSW, next_off == LSW
417 __ sd(t0, Address(sp, next_off), /*temp register*/esp);
418 #ifdef ASSERT
419 // Overwrite the unused slot with known junk
420 __ mv(t0, 0xdeadffffdeadaaaaul);
421 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
422 #endif /* ASSERT */
423 } else {
424 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
425 }
426 }
427 } else if (r_1->is_Register()) {
428 Register r = r_1->as_Register();
429 if (!r_2->is_valid()) {
430 // must be only an int (or less ) so move only 32bits to slot
431 __ sd(r, Address(sp, st_off));
432 } else {
433 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
434 // T_DOUBLE and T_LONG use two slots in the interpreter
435 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
436 // long/double in gpr
437 #ifdef ASSERT
438 // Overwrite the unused slot with known junk
439 __ mv(t0, 0xdeadffffdeadaaabul);
440 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
441 #endif /* ASSERT */
442 __ sd(r, Address(sp, next_off));
443 } else {
444 __ sd(r, Address(sp, st_off));
445 }
446 }
447 } else {
448 assert(r_1->is_FloatRegister(), "");
449 if (!r_2->is_valid()) {
450 // only a float use just part of the slot
451 __ fsw(r_1->as_FloatRegister(), Address(sp, st_off));
452 } else {
453 #ifdef ASSERT
454 // Overwrite the unused slot with known junk
455 __ mv(t0, 0xdeadffffdeadaaacul);
456 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
457 #endif /* ASSERT */
458 __ fsd(r_1->as_FloatRegister(), Address(sp, next_off));
459 }
460 }
461 }
462
463 __ mv(esp, sp); // Interp expects args on caller's expression stack
464
465 __ ld(t1, Address(xmethod, in_bytes(Method::interpreter_entry_offset())));
466 __ jr(t1);
467 }
468
469 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
470 int total_args_passed,
471 int comp_args_on_stack,
472 const BasicType *sig_bt,
473 const VMRegPair *regs) {
474 // Note: x19_sender_sp contains the senderSP on entry. We must
475 // preserve it since we may do a i2c -> c2i transition if we lose a
476 // race where compiled code goes non-entrant while we get args
477 // ready.
478
479 // Cut-out for having no stack args.
480 int comp_words_on_stack = align_up(comp_args_on_stack * VMRegImpl::stack_slot_size, wordSize) >> LogBytesPerWord;
481 if (comp_args_on_stack != 0) {
482 __ sub(t0, sp, comp_words_on_stack * wordSize);
483 __ andi(sp, t0, -16);
484 }
485
486 // Will jump to the compiled code just as if compiled code was doing it.
487 // Pre-load the register-jump target early, to schedule it better.
488 __ ld(t1, Address(xmethod, in_bytes(Method::from_compiled_offset())));
489
490 // Now generate the shuffle code.
491 for (int i = 0; i < total_args_passed; i++) {
492 if (sig_bt[i] == T_VOID) {
493 assert(i > 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "missing half");
494 continue;
495 }
496
497 // Pick up 0, 1 or 2 words from SP+offset.
498
499 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
500 "scrambled load targets?");
501 // Load in argument order going down.
502 int ld_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
503 // Point to interpreter value (vs. tag)
504 int next_off = ld_off - Interpreter::stackElementSize;
505
506 VMReg r_1 = regs[i].first();
507 VMReg r_2 = regs[i].second();
508 if (!r_1->is_valid()) {
509 assert(!r_2->is_valid(), "");
510 continue;
511 }
512 if (r_1->is_stack()) {
513 // Convert stack slot to an SP offset (+ wordSize to account for return address )
514 int st_off = regs[i].first()->reg2stack() * VMRegImpl::stack_slot_size;
515 if (!r_2->is_valid()) {
516 __ lw(t0, Address(esp, ld_off));
517 __ sd(t0, Address(sp, st_off), /*temp register*/t2);
518 } else {
519 //
520 // We are using two optoregs. This can be either T_OBJECT,
521 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
522 // two slots but only uses one for thr T_LONG or T_DOUBLE case
523 // So we must adjust where to pick up the data to match the
524 // interpreter.
525 //
526 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
527 // are accessed as negative so LSW is at LOW address
528
529 // ld_off is MSW so get LSW
530 const int offset = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
531 next_off : ld_off;
532 __ ld(t0, Address(esp, offset));
533 // st_off is LSW (i.e. reg.first())
534 __ sd(t0, Address(sp, st_off), /*temp register*/t2);
535 }
536 } else if (r_1->is_Register()) { // Register argument
537 Register r = r_1->as_Register();
538 if (r_2->is_valid()) {
539 //
540 // We are using two VMRegs. This can be either T_OBJECT,
541 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
542 // two slots but only uses one for thr T_LONG or T_DOUBLE case
543 // So we must adjust where to pick up the data to match the
544 // interpreter.
545
546 const int offset = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
547 next_off : ld_off;
548
549 // this can be a misaligned move
550 __ ld(r, Address(esp, offset));
551 } else {
552 // sign extend and use a full word?
553 __ lw(r, Address(esp, ld_off));
554 }
555 } else {
556 if (!r_2->is_valid()) {
557 __ flw(r_1->as_FloatRegister(), Address(esp, ld_off));
558 } else {
559 __ fld(r_1->as_FloatRegister(), Address(esp, next_off));
560 }
561 }
562 }
563
564 __ push_cont_fastpath(xthread); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
565
566 // 6243940 We might end up in handle_wrong_method if
567 // the callee is deoptimized as we race thru here. If that
568 // happens we don't want to take a safepoint because the
569 // caller frame will look interpreted and arguments are now
570 // "compiled" so it is much better to make this transition
571 // invisible to the stack walking code. Unfortunately if
572 // we try and find the callee by normal means a safepoint
573 // is possible. So we stash the desired callee in the thread
574 // and the vm will find there should this case occur.
575
576 __ sd(xmethod, Address(xthread, JavaThread::callee_target_offset()));
577
578 __ jr(t1);
579 }
580
581 // ---------------------------------------------------------------
582
583 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
584 int total_args_passed,
585 int comp_args_on_stack,
586 const BasicType *sig_bt,
587 const VMRegPair *regs,
588 address entry_address[AdapterBlob::ENTRY_COUNT]) {
589 entry_address[AdapterBlob::I2C] = __ pc();
590 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
591
592 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
593 Label skip_fixup;
594
595 const Register receiver = j_rarg0;
596 const Register data = t0;
597
598 // -------------------------------------------------------------------------
599 // Generate a C2I adapter. On entry we know xmethod holds the Method* during calls
600 // to the interpreter. The args start out packed in the compiled layout. They
601 // need to be unpacked into the interpreter layout. This will almost always
602 // require some stack space. We grow the current (compiled) stack, then repack
603 // the args. We finally end in a jump to the generic interpreter entry point.
604 // On exit from the interpreter, the interpreter will restore our SP (lest the
605 // compiled code, which relies solely on SP and not FP, get sick).
606
607 {
608 __ block_comment("c2i_unverified_entry {");
609
610 __ ic_check();
621 // Class initialization barrier for static methods
622 entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
623 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
624 Label L_skip_barrier;
625
626 // Bypass the barrier for non-static methods
627 __ load_unsigned_short(t0, Address(xmethod, Method::access_flags_offset()));
628 __ test_bit(t1, t0, exact_log2(JVM_ACC_STATIC));
629 __ beqz(t1, L_skip_barrier); // non-static
630
631 __ load_method_holder(t1, xmethod);
632 __ clinit_barrier(t1, t0, &L_skip_barrier);
633 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
634
635 __ bind(L_skip_barrier);
636 entry_address[AdapterBlob::C2I_No_Clinit_Check] = __ pc();
637
638 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
639 bs->c2i_entry_barrier(masm);
640
641 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
642 return;
643 }
644
645 int SharedRuntime::vector_calling_convention(VMRegPair *regs,
646 uint num_bits,
647 uint total_args_passed) {
648 assert(total_args_passed <= Argument::n_vector_register_parameters_c, "unsupported");
649 assert(num_bits >= 64 && num_bits <= 2048 && is_power_of_2(num_bits), "unsupported");
650
651 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
652 static const VectorRegister VEC_ArgReg[Argument::n_vector_register_parameters_c] = {
653 v8, v9, v10, v11, v12, v13, v14, v15,
654 v16, v17, v18, v19, v20, v21, v22, v23
655 };
656
657 const int next_reg_val = 3;
658 for (uint i = 0; i < total_args_passed; i++) {
659 VMReg vmreg = VEC_ArgReg[i]->as_VMReg();
660 regs[i].set_pair(vmreg->next(next_reg_val), vmreg);
661 }
2688 int frame_complete = __ pc() - start;
2689 address the_pc = __ pc();
2690 jfr_prologue(the_pc, masm, xthread);
2691 __ call_VM_leaf(CAST_FROM_FN_PTR(address, JfrIntrinsicSupport::return_lease), 1);
2692
2693 jfr_epilogue(masm);
2694 __ leave();
2695 __ ret();
2696
2697 OopMap* map = new OopMap(framesize, 1);
2698 oop_maps->add_gc_map(the_pc - start, map);
2699
2700 RuntimeStub* stub = // codeBlob framesize is in words (not VMRegImpl::slot_size)
2701 RuntimeStub::new_runtime_stub(name, &code, frame_complete,
2702 (framesize >> (LogBytesPerWord - LogBytesPerInt)),
2703 oop_maps, false);
2704 return stub;
2705 }
2706
2707 #endif // INCLUDE_JFR
|
321 // VM needs caller's callsite
322 // VM needs target method
323 // This needs to be a long call since we will relocate this adapter to
324 // the codeBuffer and it may not reach
325
326 #ifndef PRODUCT
327 assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
328 #endif
329
330 __ mv(c_rarg0, xmethod);
331 __ mv(c_rarg1, ra);
332 __ rt_call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
333
334 __ pop_CPU_state();
335 // restore sp
336 __ leave();
337 __ bind(L);
338 }
339
340 static void gen_c2i_adapter(MacroAssembler *masm,
341 int comp_args_on_stack,
342 const GrowableArray<SigEntry>* sig,
343 const VMRegPair *regs,
344 Label& skip_fixup) {
345 // Before we get into the guts of the C2I adapter, see if we should be here
346 // at all. We've come from compiled code and are attempting to jump to the
347 // interpreter, which means the caller made a static call to get here
348 // (vcalls always get a compiled target if there is one). Check for a
349 // compiled target. If there is one, we need to patch the caller's call.
350 patch_callers_callsite(masm);
351
352 __ bind(skip_fixup);
353
354 int words_pushed = 0;
355
356 // Since all args are passed on the stack, total_args_passed *
357 // Interpreter::stackElementSize is the space we need.
358
359 int total_args_passed = sig->length();
360 int extraspace = total_args_passed * Interpreter::stackElementSize;
361
362 __ mv(x19_sender_sp, sp);
363
364 // stack is aligned, keep it that way
365 extraspace = align_up(extraspace, 2 * wordSize);
366
367 if (extraspace) {
368 __ sub(sp, sp, extraspace);
369 }
370
371 // Now write the args into the outgoing interpreter space
372 for (int i = 0; i < total_args_passed; i++) {
373 BasicType bt = sig->at(i)._bt;
374 if (bt == T_VOID) {
375 assert(i > 0 && (sig->at(i - 1)._bt == T_LONG || sig->at(i - 1)._bt == T_DOUBLE), "missing half");
376 continue;
377 }
378
379 // offset to start parameters
380 int st_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
381 int next_off = st_off - Interpreter::stackElementSize;
382
383 // Say 4 args:
384 // i st_off
385 // 0 32 T_LONG
386 // 1 24 T_VOID
387 // 2 16 T_OBJECT
388 // 3 8 T_BOOL
389 // - 0 return address
390 //
391 // However to make thing extra confusing. Because we can fit a Java long/double in
392 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
393 // leaves one slot empty and only stores to a single slot. In this case the
394 // slot that is occupied is the T_VOID slot. See I said it was confusing.
395
396 VMReg r_1 = regs[i].first();
397 VMReg r_2 = regs[i].second();
398 if (!r_1->is_valid()) {
399 assert(!r_2->is_valid(), "");
400 continue;
401 }
402 if (r_1->is_stack()) {
403 // memory to memory use t0
404 int ld_off = (r_1->reg2stack() * VMRegImpl::stack_slot_size
405 + extraspace
406 + words_pushed * wordSize);
407 if (!r_2->is_valid()) {
408 __ lwu(t0, Address(sp, ld_off));
409 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
410 } else {
411 __ ld(t0, Address(sp, ld_off), /*temp register*/esp);
412
413 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
414 // T_DOUBLE and T_LONG use two slots in the interpreter
415 if (bt == T_LONG || bt == T_DOUBLE) {
416 // ld_off == LSW, ld_off+wordSize == MSW
417 // st_off == MSW, next_off == LSW
418 __ sd(t0, Address(sp, next_off), /*temp register*/esp);
419 #ifdef ASSERT
420 // Overwrite the unused slot with known junk
421 __ mv(t0, 0xdeadffffdeadaaaaul);
422 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
423 #endif /* ASSERT */
424 } else {
425 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
426 }
427 }
428 } else if (r_1->is_Register()) {
429 Register r = r_1->as_Register();
430 if (!r_2->is_valid()) {
431 // must be only an int (or less ) so move only 32bits to slot
432 __ sd(r, Address(sp, st_off));
433 } else {
434 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
435 // T_DOUBLE and T_LONG use two slots in the interpreter
436 if (bt == T_LONG || bt == T_DOUBLE) {
437 // long/double in gpr
438 #ifdef ASSERT
439 // Overwrite the unused slot with known junk
440 __ mv(t0, 0xdeadffffdeadaaabul);
441 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
442 #endif /* ASSERT */
443 __ sd(r, Address(sp, next_off));
444 } else {
445 __ sd(r, Address(sp, st_off));
446 }
447 }
448 } else {
449 assert(r_1->is_FloatRegister(), "");
450 if (!r_2->is_valid()) {
451 // only a float use just part of the slot
452 __ fsw(r_1->as_FloatRegister(), Address(sp, st_off));
453 } else {
454 #ifdef ASSERT
455 // Overwrite the unused slot with known junk
456 __ mv(t0, 0xdeadffffdeadaaacul);
457 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
458 #endif /* ASSERT */
459 __ fsd(r_1->as_FloatRegister(), Address(sp, next_off));
460 }
461 }
462 }
463
464 __ mv(esp, sp); // Interp expects args on caller's expression stack
465
466 __ ld(t1, Address(xmethod, in_bytes(Method::interpreter_entry_offset())));
467 __ jr(t1);
468 }
469
470 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
471 int comp_args_on_stack,
472 const GrowableArray<SigEntry>* sig,
473 const VMRegPair *regs) {
474 // Note: x19_sender_sp contains the senderSP on entry. We must
475 // preserve it since we may do a i2c -> c2i transition if we lose a
476 // race where compiled code goes non-entrant while we get args
477 // ready.
478
479 // Cut-out for having no stack args.
480 int comp_words_on_stack = align_up(comp_args_on_stack * VMRegImpl::stack_slot_size, wordSize) >> LogBytesPerWord;
481 if (comp_args_on_stack != 0) {
482 __ sub(t0, sp, comp_words_on_stack * wordSize);
483 __ andi(sp, t0, -16);
484 }
485
486 // Will jump to the compiled code just as if compiled code was doing it.
487 // Pre-load the register-jump target early, to schedule it better.
488 __ ld(t1, Address(xmethod, in_bytes(Method::from_compiled_offset())));
489
490 // Now generate the shuffle code.
491 int total_args_passed = sig->length();
492 for (int i = 0; i < total_args_passed; i++) {
493 BasicType bt = sig->at(i)._bt;
494 if (bt == T_VOID) {
495 assert(i > 0 && (sig->at(i - 1)._bt == T_LONG || sig->at(i - 1)._bt == T_DOUBLE), "missing half");
496 continue;
497 }
498
499 // Pick up 0, 1 or 2 words from SP+offset.
500
501 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
502 "scrambled load targets?");
503 // Load in argument order going down.
504 int ld_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
505 // Point to interpreter value (vs. tag)
506 int next_off = ld_off - Interpreter::stackElementSize;
507
508 VMReg r_1 = regs[i].first();
509 VMReg r_2 = regs[i].second();
510 if (!r_1->is_valid()) {
511 assert(!r_2->is_valid(), "");
512 continue;
513 }
514 if (r_1->is_stack()) {
515 // Convert stack slot to an SP offset (+ wordSize to account for return address )
516 int st_off = regs[i].first()->reg2stack() * VMRegImpl::stack_slot_size;
517 if (!r_2->is_valid()) {
518 __ lw(t0, Address(esp, ld_off));
519 __ sd(t0, Address(sp, st_off), /*temp register*/t2);
520 } else {
521 //
522 // We are using two optoregs. This can be either T_OBJECT,
523 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
524 // two slots but only uses one for thr T_LONG or T_DOUBLE case
525 // So we must adjust where to pick up the data to match the
526 // interpreter.
527 //
528 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
529 // are accessed as negative so LSW is at LOW address
530
531 // ld_off is MSW so get LSW
532 const int offset = (bt == T_LONG || bt == T_DOUBLE) ?
533 next_off : ld_off;
534 __ ld(t0, Address(esp, offset));
535 // st_off is LSW (i.e. reg.first())
536 __ sd(t0, Address(sp, st_off), /*temp register*/t2);
537 }
538 } else if (r_1->is_Register()) { // Register argument
539 Register r = r_1->as_Register();
540 if (r_2->is_valid()) {
541 //
542 // We are using two VMRegs. This can be either T_OBJECT,
543 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
544 // two slots but only uses one for thr T_LONG or T_DOUBLE case
545 // So we must adjust where to pick up the data to match the
546 // interpreter.
547
548 const int offset = (bt == T_LONG || bt == T_DOUBLE) ?
549 next_off : ld_off;
550
551 // this can be a misaligned move
552 __ ld(r, Address(esp, offset));
553 } else {
554 // sign extend and use a full word?
555 __ lw(r, Address(esp, ld_off));
556 }
557 } else {
558 if (!r_2->is_valid()) {
559 __ flw(r_1->as_FloatRegister(), Address(esp, ld_off));
560 } else {
561 __ fld(r_1->as_FloatRegister(), Address(esp, next_off));
562 }
563 }
564 }
565
566 __ push_cont_fastpath(xthread); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
567
568 // 6243940 We might end up in handle_wrong_method if
569 // the callee is deoptimized as we race thru here. If that
570 // happens we don't want to take a safepoint because the
571 // caller frame will look interpreted and arguments are now
572 // "compiled" so it is much better to make this transition
573 // invisible to the stack walking code. Unfortunately if
574 // we try and find the callee by normal means a safepoint
575 // is possible. So we stash the desired callee in the thread
576 // and the vm will find there should this case occur.
577
578 __ sd(xmethod, Address(xthread, JavaThread::callee_target_offset()));
579
580 __ jr(t1);
581 }
582
583 // ---------------------------------------------------------------
584
585 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler* masm,
586 int comp_args_on_stack,
587 const GrowableArray<SigEntry>* sig,
588 const VMRegPair* regs,
589 const GrowableArray<SigEntry>* sig_cc,
590 const VMRegPair* regs_cc,
591 const GrowableArray<SigEntry>* sig_cc_ro,
592 const VMRegPair* regs_cc_ro,
593 address entry_address[AdapterBlob::ENTRY_COUNT],
594 AdapterBlob*& new_adapter,
595 bool allocate_code_blob) {
596 entry_address[AdapterBlob::I2C] = __ pc();
597 gen_i2c_adapter(masm, comp_args_on_stack, sig, regs);
598
599 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
600 Label skip_fixup;
601
602 const Register receiver = j_rarg0;
603 const Register data = t0;
604
605 // -------------------------------------------------------------------------
606 // Generate a C2I adapter. On entry we know xmethod holds the Method* during calls
607 // to the interpreter. The args start out packed in the compiled layout. They
608 // need to be unpacked into the interpreter layout. This will almost always
609 // require some stack space. We grow the current (compiled) stack, then repack
610 // the args. We finally end in a jump to the generic interpreter entry point.
611 // On exit from the interpreter, the interpreter will restore our SP (lest the
612 // compiled code, which relies solely on SP and not FP, get sick).
613
614 {
615 __ block_comment("c2i_unverified_entry {");
616
617 __ ic_check();
628 // Class initialization barrier for static methods
629 entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
630 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
631 Label L_skip_barrier;
632
633 // Bypass the barrier for non-static methods
634 __ load_unsigned_short(t0, Address(xmethod, Method::access_flags_offset()));
635 __ test_bit(t1, t0, exact_log2(JVM_ACC_STATIC));
636 __ beqz(t1, L_skip_barrier); // non-static
637
638 __ load_method_holder(t1, xmethod);
639 __ clinit_barrier(t1, t0, &L_skip_barrier);
640 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
641
642 __ bind(L_skip_barrier);
643 entry_address[AdapterBlob::C2I_No_Clinit_Check] = __ pc();
644
645 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
646 bs->c2i_entry_barrier(masm);
647
648 gen_c2i_adapter(masm, comp_args_on_stack, sig, regs, skip_fixup);
649 return;
650 }
651
652 int SharedRuntime::vector_calling_convention(VMRegPair *regs,
653 uint num_bits,
654 uint total_args_passed) {
655 assert(total_args_passed <= Argument::n_vector_register_parameters_c, "unsupported");
656 assert(num_bits >= 64 && num_bits <= 2048 && is_power_of_2(num_bits), "unsupported");
657
658 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
659 static const VectorRegister VEC_ArgReg[Argument::n_vector_register_parameters_c] = {
660 v8, v9, v10, v11, v12, v13, v14, v15,
661 v16, v17, v18, v19, v20, v21, v22, v23
662 };
663
664 const int next_reg_val = 3;
665 for (uint i = 0; i < total_args_passed; i++) {
666 VMReg vmreg = VEC_ArgReg[i]->as_VMReg();
667 regs[i].set_pair(vmreg->next(next_reg_val), vmreg);
668 }
2695 int frame_complete = __ pc() - start;
2696 address the_pc = __ pc();
2697 jfr_prologue(the_pc, masm, xthread);
2698 __ call_VM_leaf(CAST_FROM_FN_PTR(address, JfrIntrinsicSupport::return_lease), 1);
2699
2700 jfr_epilogue(masm);
2701 __ leave();
2702 __ ret();
2703
2704 OopMap* map = new OopMap(framesize, 1);
2705 oop_maps->add_gc_map(the_pc - start, map);
2706
2707 RuntimeStub* stub = // codeBlob framesize is in words (not VMRegImpl::slot_size)
2708 RuntimeStub::new_runtime_stub(name, &code, frame_complete,
2709 (framesize >> (LogBytesPerWord - LogBytesPerInt)),
2710 oop_maps, false);
2711 return stub;
2712 }
2713
2714 #endif // INCLUDE_JFR
2715
2716 const uint SharedRuntime::java_return_convention_max_int = Argument::n_int_register_parameters_j;
2717 const uint SharedRuntime::java_return_convention_max_float = Argument::n_float_register_parameters_j;
2718
2719 int SharedRuntime::java_return_convention(const BasicType *sig_bt, VMRegPair *regs, int total_args_passed) {
2720 Unimplemented();
2721 return 0;
2722 }
2723
2724 BufferedInlineTypeBlob* SharedRuntime::generate_buffered_inline_type_adapter(const InlineKlass* vk) {
2725 Unimplemented();
2726 return nullptr;
2727 }
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