9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "code/compiledIC.hpp"
30 #include "code/debugInfoRec.hpp"
31 #include "code/vtableStubs.hpp"
32 #include "compiler/oopMap.hpp"
33 #include "gc/shared/barrierSetAssembler.hpp"
34 #include "interpreter/interp_masm.hpp"
35 #include "interpreter/interpreter.hpp"
36 #include "logging/log.hpp"
37 #include "memory/resourceArea.hpp"
38 #include "nativeInst_riscv.hpp"
39 #include "oops/klass.inline.hpp"
40 #include "oops/method.inline.hpp"
41 #include "prims/methodHandles.hpp"
42 #include "runtime/continuation.hpp"
43 #include "runtime/continuationEntry.inline.hpp"
44 #include "runtime/globals.hpp"
45 #include "runtime/jniHandles.hpp"
46 #include "runtime/safepointMechanism.hpp"
47 #include "runtime/sharedRuntime.hpp"
48 #include "runtime/signature.hpp"
292 }
293 break;
294 case T_DOUBLE:
295 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
296 if (fp_args < Argument::n_float_register_parameters_j) {
297 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
298 } else {
299 stk_args = align_up(stk_args, 2);
300 regs[i].set2(VMRegImpl::stack2reg(stk_args));
301 stk_args += 2;
302 }
303 break;
304 default:
305 ShouldNotReachHere();
306 }
307 }
308
309 return stk_args;
310 }
311
312 // Patch the callers callsite with entry to compiled code if it exists.
313 static void patch_callers_callsite(MacroAssembler *masm) {
314 Label L;
315 __ ld(t0, Address(xmethod, in_bytes(Method::code_offset())));
316 __ beqz(t0, L);
317
318 __ enter();
319 __ push_CPU_state();
320
321 // VM needs caller's callsite
322 // VM needs target method
323 // This needs to be a long call since we will relocate this adapter to
324 // the codeBuffer and it may not reach
325
326 #ifndef PRODUCT
327 assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
328 #endif
329
330 __ mv(c_rarg0, xmethod);
331 __ mv(c_rarg1, ra);
332 __ rt_call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
333
334 __ pop_CPU_state();
335 // restore sp
336 __ leave();
337 __ bind(L);
338 }
339
340 static void gen_c2i_adapter(MacroAssembler *masm,
341 int total_args_passed,
342 int comp_args_on_stack,
343 const BasicType *sig_bt,
344 const VMRegPair *regs,
345 Label& skip_fixup) {
346 // Before we get into the guts of the C2I adapter, see if we should be here
347 // at all. We've come from compiled code and are attempting to jump to the
348 // interpreter, which means the caller made a static call to get here
349 // (vcalls always get a compiled target if there is one). Check for a
350 // compiled target. If there is one, we need to patch the caller's call.
351 patch_callers_callsite(masm);
352
353 __ bind(skip_fixup);
354
355 int words_pushed = 0;
356
357 // Since all args are passed on the stack, total_args_passed *
358 // Interpreter::stackElementSize is the space we need.
359
360 int extraspace = total_args_passed * Interpreter::stackElementSize;
361
362 __ mv(x19_sender_sp, sp);
363
364 // stack is aligned, keep it that way
365 extraspace = align_up(extraspace, 2 * wordSize);
366
367 if (extraspace) {
368 __ sub(sp, sp, extraspace);
369 }
370
371 // Now write the args into the outgoing interpreter space
372 for (int i = 0; i < total_args_passed; i++) {
373 if (sig_bt[i] == T_VOID) {
374 assert(i > 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "missing half");
375 continue;
376 }
377
378 // offset to start parameters
379 int st_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
380 int next_off = st_off - Interpreter::stackElementSize;
381
382 // Say 4 args:
383 // i st_off
384 // 0 32 T_LONG
385 // 1 24 T_VOID
386 // 2 16 T_OBJECT
387 // 3 8 T_BOOL
388 // - 0 return address
389 //
390 // However to make thing extra confusing. Because we can fit a Java long/double in
391 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
392 // leaves one slot empty and only stores to a single slot. In this case the
393 // slot that is occupied is the T_VOID slot. See I said it was confusing.
394
395 VMReg r_1 = regs[i].first();
396 VMReg r_2 = regs[i].second();
397 if (!r_1->is_valid()) {
398 assert(!r_2->is_valid(), "");
399 continue;
400 }
401 if (r_1->is_stack()) {
402 // memory to memory use t0
403 int ld_off = (r_1->reg2stack() * VMRegImpl::stack_slot_size
404 + extraspace
405 + words_pushed * wordSize);
406 if (!r_2->is_valid()) {
407 __ lwu(t0, Address(sp, ld_off));
408 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
409 } else {
410 __ ld(t0, Address(sp, ld_off), /*temp register*/esp);
411
412 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
413 // T_DOUBLE and T_LONG use two slots in the interpreter
414 if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
415 // ld_off == LSW, ld_off+wordSize == MSW
416 // st_off == MSW, next_off == LSW
417 __ sd(t0, Address(sp, next_off), /*temp register*/esp);
418 #ifdef ASSERT
419 // Overwrite the unused slot with known junk
420 __ mv(t0, 0xdeadffffdeadaaaaul);
421 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
422 #endif /* ASSERT */
423 } else {
424 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
425 }
426 }
427 } else if (r_1->is_Register()) {
428 Register r = r_1->as_Register();
429 if (!r_2->is_valid()) {
430 // must be only an int (or less ) so move only 32bits to slot
431 __ sd(r, Address(sp, st_off));
432 } else {
433 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
434 // T_DOUBLE and T_LONG use two slots in the interpreter
435 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
436 // long/double in gpr
437 #ifdef ASSERT
438 // Overwrite the unused slot with known junk
439 __ mv(t0, 0xdeadffffdeadaaabul);
440 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
441 #endif /* ASSERT */
442 __ sd(r, Address(sp, next_off));
443 } else {
444 __ sd(r, Address(sp, st_off));
445 }
446 }
447 } else {
448 assert(r_1->is_FloatRegister(), "");
449 if (!r_2->is_valid()) {
450 // only a float use just part of the slot
451 __ fsw(r_1->as_FloatRegister(), Address(sp, st_off));
452 } else {
453 #ifdef ASSERT
454 // Overwrite the unused slot with known junk
455 __ mv(t0, 0xdeadffffdeadaaacul);
456 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
457 #endif /* ASSERT */
458 __ fsd(r_1->as_FloatRegister(), Address(sp, next_off));
459 }
460 }
461 }
462
463 __ mv(esp, sp); // Interp expects args on caller's expression stack
464
465 __ ld(t1, Address(xmethod, in_bytes(Method::interpreter_entry_offset())));
466 __ jr(t1);
467 }
468
469 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
470 int total_args_passed,
471 int comp_args_on_stack,
472 const BasicType *sig_bt,
473 const VMRegPair *regs) {
474 // Note: x19_sender_sp contains the senderSP on entry. We must
475 // preserve it since we may do a i2c -> c2i transition if we lose a
476 // race where compiled code goes non-entrant while we get args
477 // ready.
478
479 // Cut-out for having no stack args.
480 int comp_words_on_stack = align_up(comp_args_on_stack * VMRegImpl::stack_slot_size, wordSize) >> LogBytesPerWord;
481 if (comp_args_on_stack != 0) {
482 __ sub(t0, sp, comp_words_on_stack * wordSize);
483 __ andi(sp, t0, -16);
484 }
485
486 // Will jump to the compiled code just as if compiled code was doing it.
487 // Pre-load the register-jump target early, to schedule it better.
488 __ ld(t1, Address(xmethod, in_bytes(Method::from_compiled_offset())));
489
490 // Now generate the shuffle code.
491 for (int i = 0; i < total_args_passed; i++) {
492 if (sig_bt[i] == T_VOID) {
493 assert(i > 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "missing half");
494 continue;
495 }
496
497 // Pick up 0, 1 or 2 words from SP+offset.
498
499 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
500 "scrambled load targets?");
501 // Load in argument order going down.
502 int ld_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
503 // Point to interpreter value (vs. tag)
504 int next_off = ld_off - Interpreter::stackElementSize;
505
506 VMReg r_1 = regs[i].first();
507 VMReg r_2 = regs[i].second();
508 if (!r_1->is_valid()) {
509 assert(!r_2->is_valid(), "");
510 continue;
511 }
512 if (r_1->is_stack()) {
513 // Convert stack slot to an SP offset (+ wordSize to account for return address )
514 int st_off = regs[i].first()->reg2stack() * VMRegImpl::stack_slot_size;
515 if (!r_2->is_valid()) {
516 __ lw(t0, Address(esp, ld_off));
517 __ sd(t0, Address(sp, st_off), /*temp register*/t2);
518 } else {
519 //
520 // We are using two optoregs. This can be either T_OBJECT,
521 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
522 // two slots but only uses one for thr T_LONG or T_DOUBLE case
523 // So we must adjust where to pick up the data to match the
524 // interpreter.
525 //
526 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
527 // are accessed as negative so LSW is at LOW address
528
529 // ld_off is MSW so get LSW
530 const int offset = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
531 next_off : ld_off;
532 __ ld(t0, Address(esp, offset));
533 // st_off is LSW (i.e. reg.first())
534 __ sd(t0, Address(sp, st_off), /*temp register*/t2);
535 }
536 } else if (r_1->is_Register()) { // Register argument
537 Register r = r_1->as_Register();
538 if (r_2->is_valid()) {
539 //
540 // We are using two VMRegs. This can be either T_OBJECT,
541 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
542 // two slots but only uses one for thr T_LONG or T_DOUBLE case
543 // So we must adjust where to pick up the data to match the
544 // interpreter.
545
546 const int offset = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
547 next_off : ld_off;
548
549 // this can be a misaligned move
550 __ ld(r, Address(esp, offset));
551 } else {
552 // sign extend and use a full word?
553 __ lw(r, Address(esp, ld_off));
554 }
555 } else {
556 if (!r_2->is_valid()) {
557 __ flw(r_1->as_FloatRegister(), Address(esp, ld_off));
558 } else {
559 __ fld(r_1->as_FloatRegister(), Address(esp, next_off));
560 }
561 }
562 }
563
564 __ push_cont_fastpath(xthread); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
565
566 // 6243940 We might end up in handle_wrong_method if
567 // the callee is deoptimized as we race thru here. If that
568 // happens we don't want to take a safepoint because the
569 // caller frame will look interpreted and arguments are now
570 // "compiled" so it is much better to make this transition
571 // invisible to the stack walking code. Unfortunately if
572 // we try and find the callee by normal means a safepoint
573 // is possible. So we stash the desired callee in the thread
574 // and the vm will find there should this case occur.
575
576 __ sd(xmethod, Address(xthread, JavaThread::callee_target_offset()));
577
578 __ jr(t1);
579 }
580
581 // ---------------------------------------------------------------
582
583 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
584 int total_args_passed,
585 int comp_args_on_stack,
586 const BasicType *sig_bt,
587 const VMRegPair *regs,
588 address entry_address[AdapterBlob::ENTRY_COUNT]) {
589 entry_address[AdapterBlob::I2C] = __ pc();
590 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
591
592 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
593 Label skip_fixup;
594
595 const Register receiver = j_rarg0;
596 const Register data = t0;
597
598 // -------------------------------------------------------------------------
599 // Generate a C2I adapter. On entry we know xmethod holds the Method* during calls
600 // to the interpreter. The args start out packed in the compiled layout. They
601 // need to be unpacked into the interpreter layout. This will almost always
602 // require some stack space. We grow the current (compiled) stack, then repack
603 // the args. We finally end in a jump to the generic interpreter entry point.
604 // On exit from the interpreter, the interpreter will restore our SP (lest the
605 // compiled code, which relies solely on SP and not FP, get sick).
606
607 {
608 __ block_comment("c2i_unverified_entry {");
609
610 __ ic_check();
611 __ ld(xmethod, Address(data, CompiledICData::speculated_method_offset()));
612
613 __ ld(t0, Address(xmethod, in_bytes(Method::code_offset())));
614 __ beqz(t0, skip_fixup);
615 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
616 __ block_comment("} c2i_unverified_entry");
617 }
618
619 entry_address[AdapterBlob::C2I] = __ pc();
620
621 // Class initialization barrier for static methods
622 entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
623 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
624 Label L_skip_barrier;
625
626 // Bypass the barrier for non-static methods
627 __ load_unsigned_short(t0, Address(xmethod, Method::access_flags_offset()));
628 __ test_bit(t1, t0, exact_log2(JVM_ACC_STATIC));
629 __ beqz(t1, L_skip_barrier); // non-static
630
631 __ load_method_holder(t1, xmethod);
632 __ clinit_barrier(t1, t0, &L_skip_barrier);
633 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
634
635 __ bind(L_skip_barrier);
636 entry_address[AdapterBlob::C2I_No_Clinit_Check] = __ pc();
637
638 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
639 bs->c2i_entry_barrier(masm);
640
641 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
642 return;
643 }
644
645 int SharedRuntime::vector_calling_convention(VMRegPair *regs,
646 uint num_bits,
647 uint total_args_passed) {
648 assert(total_args_passed <= Argument::n_vector_register_parameters_c, "unsupported");
649 assert(num_bits >= 64 && num_bits <= 2048 && is_power_of_2(num_bits), "unsupported");
650
651 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
652 static const VectorRegister VEC_ArgReg[Argument::n_vector_register_parameters_c] = {
653 v8, v9, v10, v11, v12, v13, v14, v15,
654 v16, v17, v18, v19, v20, v21, v22, v23
655 };
656
657 const int next_reg_val = 3;
658 for (uint i = 0; i < total_args_passed; i++) {
659 VMReg vmreg = VEC_ArgReg[i]->as_VMReg();
660 regs[i].set_pair(vmreg->next(next_reg_val), vmreg);
661 }
662 return 0;
|
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "classfile/symbolTable.hpp"
30 #include "code/compiledIC.hpp"
31 #include "code/debugInfoRec.hpp"
32 #include "code/vtableStubs.hpp"
33 #include "compiler/oopMap.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "interpreter/interp_masm.hpp"
36 #include "interpreter/interpreter.hpp"
37 #include "logging/log.hpp"
38 #include "memory/resourceArea.hpp"
39 #include "nativeInst_riscv.hpp"
40 #include "oops/klass.inline.hpp"
41 #include "oops/method.inline.hpp"
42 #include "prims/methodHandles.hpp"
43 #include "runtime/continuation.hpp"
44 #include "runtime/continuationEntry.inline.hpp"
45 #include "runtime/globals.hpp"
46 #include "runtime/jniHandles.hpp"
47 #include "runtime/safepointMechanism.hpp"
48 #include "runtime/sharedRuntime.hpp"
49 #include "runtime/signature.hpp"
293 }
294 break;
295 case T_DOUBLE:
296 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
297 if (fp_args < Argument::n_float_register_parameters_j) {
298 regs[i].set2(FP_ArgReg[fp_args++]->as_VMReg());
299 } else {
300 stk_args = align_up(stk_args, 2);
301 regs[i].set2(VMRegImpl::stack2reg(stk_args));
302 stk_args += 2;
303 }
304 break;
305 default:
306 ShouldNotReachHere();
307 }
308 }
309
310 return stk_args;
311 }
312
313 const uint SharedRuntime::java_return_convention_max_int = Argument::n_int_register_parameters_j;
314 const uint SharedRuntime::java_return_convention_max_float = Argument::n_float_register_parameters_j;
315
316 int SharedRuntime::java_return_convention(const BasicType *sig_bt,
317 VMRegPair *regs,
318 int total_args_passed) {
319 // Create the mapping between argument positions and registers.
320
321 static const Register INT_ArgReg[java_return_convention_max_int] = {
322 x10 /* j_rarg7 */, j_rarg6, j_rarg5, j_rarg4, j_rarg3, j_rarg2, j_rarg1, j_rarg0
323 };
324
325 static const FloatRegister FP_ArgReg[java_return_convention_max_float] = {
326 j_farg0, j_farg1, j_farg2, j_farg3, j_farg4, j_farg5, j_farg6, j_farg7
327 };
328
329 uint int_args = 0;
330 uint fp_args = 0;
331
332 for (int i = 0; i < total_args_passed; i++) {
333 switch (sig_bt[i]) {
334 case T_BOOLEAN:
335 case T_CHAR:
336 case T_BYTE:
337 case T_SHORT:
338 case T_INT:
339 if (int_args < SharedRuntime::java_return_convention_max_int) {
340 regs[i].set1(INT_ArgReg[int_args]->as_VMReg());
341 int_args ++;
342 } else {
343 return -1;
344 }
345 break;
346 case T_VOID:
347 // halves of T_LONG or T_DOUBLE
348 assert(i != 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "expecting half");
349 regs[i].set_bad();
350 break;
351 case T_LONG:
352 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
353 // fall through
354 case T_OBJECT:
355 case T_ARRAY:
356 case T_ADDRESS:
357 // Should T_METADATA be added to java_calling_convention as well ?
358 case T_METADATA:
359 if (int_args < SharedRuntime::java_return_convention_max_int) {
360 regs[i].set2(INT_ArgReg[int_args]->as_VMReg());
361 int_args ++;
362 } else {
363 return -1;
364 }
365 break;
366 case T_FLOAT:
367 if (fp_args < SharedRuntime::java_return_convention_max_float) {
368 regs[i].set1(FP_ArgReg[fp_args]->as_VMReg());
369 fp_args ++;
370 } else {
371 return -1;
372 }
373 break;
374 case T_DOUBLE:
375 assert((i + 1) < total_args_passed && sig_bt[i + 1] == T_VOID, "expecting half");
376 if (fp_args < SharedRuntime::java_return_convention_max_float) {
377 regs[i].set2(FP_ArgReg[fp_args]->as_VMReg());
378 fp_args ++;
379 } else {
380 return -1;
381 }
382 break;
383 default:
384 ShouldNotReachHere();
385 break;
386 }
387 }
388
389 return int_args + fp_args;
390 }
391
392 BufferedInlineTypeBlob* SharedRuntime::generate_buffered_inline_type_adapter(const InlineKlass* vk) {
393 Unimplemented();
394 return nullptr;
395 }
396
397 // Patch the callers callsite with entry to compiled code if it exists.
398 static void patch_callers_callsite(MacroAssembler *masm) {
399 Label L;
400 __ ld(t0, Address(xmethod, in_bytes(Method::code_offset())));
401 __ beqz(t0, L);
402
403 __ enter();
404 __ push_CPU_state();
405
406 // VM needs caller's callsite
407 // VM needs target method
408 // This needs to be a long call since we will relocate this adapter to
409 // the codeBuffer and it may not reach
410
411 #ifndef PRODUCT
412 assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
413 #endif
414
415 __ mv(c_rarg0, xmethod);
416 __ mv(c_rarg1, ra);
417 __ rt_call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
418
419 __ pop_CPU_state();
420 // restore sp
421 __ leave();
422 __ bind(L);
423 }
424
425 // For each inline type argument, sig includes the list of fields of
426 // the inline type. This utility function computes the number of
427 // arguments for the call if inline types are passed by reference (the
428 // calling convention the interpreter expects).
429 static int compute_total_args_passed_int(const GrowableArray<SigEntry>* sig_extended) {
430 int total_args_passed = 0;
431 assert(!InlineTypePassFieldsAsArgs, "");
432 total_args_passed = sig_extended->length();
433 return total_args_passed;
434 }
435
436 static void gen_c2i_adapter_helper(MacroAssembler* masm,
437 BasicType bt,
438 BasicType prev_bt,
439 size_t size_in_bytes,
440 const VMRegPair& reg_pair,
441 const Address& to,
442 int extraspace) {
443 if (bt == T_VOID) {
444 assert(prev_bt == T_LONG || prev_bt == T_DOUBLE, "missing half");
445 return;
446 }
447
448 // Say 4 args:
449 // i st_off
450 // 0 32 T_LONG
451 // 1 24 T_VOID
452 // 2 16 T_OBJECT
453 // 3 8 T_BOOL
454 // - 0 return address
455 //
456 // However to make thing extra confusing. Because we can fit a Java long/double in
457 // a single slot on a 64 bit vm and it would be silly to break them up, the interpreter
458 // leaves one slot empty and only stores to a single slot. In this case the
459 // slot that is occupied is the T_VOID slot. See I said it was confusing.
460
461 bool wide = (size_in_bytes == wordSize);
462
463 VMReg r_1 = reg_pair.first();
464 VMReg r_2 = reg_pair.second();
465 assert(r_2->is_valid() == wide, "invalid size");
466 if (!r_1->is_valid()) {
467 assert(!r_2->is_valid(), "");
468 return;
469 }
470
471 if (!r_1->is_FloatRegister()) {
472 Register val = t1;
473 if (r_1->is_stack()) {
474 int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
475 __ load_sized_value(val, Address(sp, ld_off), size_in_bytes, /* is_signed */ false);
476 } else {
477 val = r_1->as_Register();
478 }
479 __ store_sized_value(to, val, size_in_bytes);
480 } else {
481 if (wide) {
482 __ fsd(r_1->as_FloatRegister(), to);
483 } else {
484 // only a float use just part of the slot
485 __ fsw(r_1->as_FloatRegister(), to);
486 }
487 }
488 }
489
490 static void gen_c2i_adapter(MacroAssembler *masm,
491 const GrowableArray<SigEntry>* sig_extended,
492 const VMRegPair *regs,
493 bool requires_clinit_barrier,
494 address& c2i_no_clinit_check_entry,
495 Label& skip_fixup,
496 address start,
497 OopMapSet* oop_maps,
498 int& frame_complete,
499 int& frame_size_in_words,
500 bool alloc_inline_receiver) {
501 if (requires_clinit_barrier) {
502 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
503 Label L_skip_barrier;
504
505 { // Bypass the barrier for non-static methods
506 __ lhu(t0, Address(xmethod, Method::access_flags_offset()));
507 __ test_bit(t0, t0, exact_log2(JVM_ACC_STATIC));
508 __ beqz(t0, L_skip_barrier); // non-static
509 }
510
511 __ load_method_holder(t1, xmethod);
512 __ clinit_barrier(t1, t0, &L_skip_barrier);
513 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
514
515 __ bind(L_skip_barrier);
516 c2i_no_clinit_check_entry = __ pc();
517 }
518
519 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
520 bs->c2i_entry_barrier(masm);
521
522 // Before we get into the guts of the C2I adapter, see if we should be here
523 // at all. We've come from compiled code and are attempting to jump to the
524 // interpreter, which means the caller made a static call to get here
525 // (vcalls always get a compiled target if there is one). Check for a
526 // compiled target. If there is one, we need to patch the caller's call.
527 patch_callers_callsite(masm);
528
529 __ bind(skip_fixup);
530
531 // Since all args are passed on the stack, total_args_passed *
532 // Interpreter::stackElementSize is the space we need.
533
534 int total_args_passed = compute_total_args_passed_int(sig_extended);
535 int extraspace = total_args_passed * Interpreter::stackElementSize;
536
537 __ mv(x19_sender_sp, sp);
538
539 // stack is aligned, keep it that way
540 extraspace = align_up(extraspace, StackAlignmentInBytes);
541
542 if (extraspace) {
543 __ sub(sp, sp, extraspace);
544 }
545
546 // Now write the args into the outgoing interpreter space
547
548 // next_arg_comp is the next argument from the compiler point of
549 // view (inline type fields are passed in registers/on the stack). In
550 // sig_extended, an inline type argument starts with: T_METADATA,
551 // followed by the types of the fields of the inline type and T_VOID
552 // to mark the end of the inline type. ignored counts the number of
553 // T_METADATA/T_VOID. next_vt_arg is the next inline type argument:
554 // used to get the buffer for that argument from the pool of buffers
555 // we allocated above and want to pass to the
556 // interpreter. next_arg_int is the next argument from the
557 // interpreter point of view (inline types are passed by reference).
558 for (int next_arg_comp = 0, ignored = 0, next_vt_arg = 0, next_arg_int = 0;
559 next_arg_comp < sig_extended->length(); next_arg_comp++) {
560 assert(ignored <= next_arg_comp, "shouldn't skip over more slots than there are arguments");
561 assert(next_arg_int <= total_args_passed, "more arguments for the interpreter than expected?");
562 BasicType bt = sig_extended->at(next_arg_comp)._bt;
563 assert(!InlineTypePassFieldsAsArgs, "");
564
565 int st_off = (total_args_passed - next_arg_int - 1) * Interpreter::stackElementSize;
566 int next_off = st_off - Interpreter::stackElementSize;
567 const int offset = (bt == T_LONG || bt == T_DOUBLE) ? next_off : st_off;
568 const VMRegPair reg_pair = regs[next_arg_comp-ignored];
569 size_t size_in_bytes = reg_pair.second()->is_valid() ? 8 : 4;
570 gen_c2i_adapter_helper(masm, bt, next_arg_comp > 0 ? sig_extended->at(next_arg_comp - 1)._bt : T_ILLEGAL,
571 size_in_bytes, reg_pair, Address(sp, offset), extraspace);
572 next_arg_int++;
573
574 #ifdef ASSERT
575 if (bt == T_LONG || bt == T_DOUBLE) {
576 // Overwrite the unused slot with known junk
577 __ mv(t0, CONST64(0xdeadffffdeadaaaa));
578 __ sd(t0, Address(sp, st_off));
579 }
580 #endif /* ASSERT */
581 }
582
583 __ mv(esp, sp); // Interp expects args on caller's expression stack
584
585 __ ld(t1, Address(xmethod, in_bytes(Method::interpreter_entry_offset())));
586 __ jr(t1);
587 }
588
589 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
590 int comp_args_on_stack,
591 const GrowableArray<SigEntry>* sig,
592 const VMRegPair *regs) {
593 // Note: x19_sender_sp contains the senderSP on entry. We must
594 // preserve it since we may do a i2c -> c2i transition if we lose a
595 // race where compiled code goes non-entrant while we get args
596 // ready.
597
598 // Cut-out for having no stack args.
599 int comp_words_on_stack = 0;
600 if (comp_args_on_stack != 0) {
601 comp_words_on_stack = align_up(comp_args_on_stack * VMRegImpl::stack_slot_size, wordSize) >> LogBytesPerWord;
602 __ sub(t0, sp, comp_words_on_stack * wordSize);
603 __ andi(sp, t0, -16);
604 }
605
606 // Will jump to the compiled code just as if compiled code was doing it.
607 // Pre-load the register-jump target early, to schedule it better.
608 __ ld(t1, Address(xmethod, in_bytes(Method::from_compiled_inline_offset())));
609
610 int total_args_passed = sig->length();
611
612 // Now generate the shuffle code.
613 for (int i = 0; i < total_args_passed; i++) {
614 BasicType bt = sig->at(i)._bt;
615 if (bt == T_VOID) {
616 assert(i > 0 && (sig->at(i - 1)._bt == T_LONG || sig->at(i - 1)._bt == T_DOUBLE), "missing half");
617 continue;
618 }
619
620 // Pick up 0, 1 or 2 words from SP+offset.
621
622 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
623 "scrambled load targets?");
624 // Load in argument order going down.
625 int ld_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
626 // Point to interpreter value (vs. tag)
627 int next_off = ld_off - Interpreter::stackElementSize;
628
629 VMReg r_1 = regs[i].first();
630 VMReg r_2 = regs[i].second();
631 if (!r_1->is_valid()) {
632 assert(!r_2->is_valid(), "");
633 continue;
634 }
635 if (r_1->is_stack()) {
636 // Convert stack slot to an SP offset (+ wordSize to account for return address )
637 int st_off = regs[i].first()->reg2stack() * VMRegImpl::stack_slot_size;
638 if (!r_2->is_valid()) {
639 __ lw(t0, Address(esp, ld_off));
640 __ sd(t0, Address(sp, st_off), /*temp register*/t2);
641 } else {
642 //
643 // We are using two optoregs. This can be either T_OBJECT,
644 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
645 // two slots but only uses one for thr T_LONG or T_DOUBLE case
646 // So we must adjust where to pick up the data to match the
647 // interpreter.
648 //
649 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
650 // are accessed as negative so LSW is at LOW address
651
652 // ld_off is MSW so get LSW
653 const int offset = (bt == T_LONG || bt == T_DOUBLE) ? next_off : ld_off;
654 __ ld(t0, Address(esp, offset));
655 // st_off is LSW (i.e. reg.first())
656 __ sd(t0, Address(sp, st_off), /*temp register*/t2);
657 }
658 } else if (r_1->is_Register()) { // Register argument
659 Register r = r_1->as_Register();
660 if (r_2->is_valid()) {
661 //
662 // We are using two VMRegs. This can be either T_OBJECT,
663 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
664 // two slots but only uses one for thr T_LONG or T_DOUBLE case
665 // So we must adjust where to pick up the data to match the
666 // interpreter.
667
668 const int offset = (bt == T_LONG || bt == T_DOUBLE) ? next_off : ld_off;
669
670 // this can be a misaligned move
671 __ ld(r, Address(esp, offset));
672 } else {
673 // sign extend and use a full word?
674 __ lw(r, Address(esp, ld_off));
675 }
676 } else {
677 if (!r_2->is_valid()) {
678 __ flw(r_1->as_FloatRegister(), Address(esp, ld_off));
679 } else {
680 __ fld(r_1->as_FloatRegister(), Address(esp, next_off));
681 }
682 }
683 }
684
685 __ push_cont_fastpath(xthread); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
686
687 // 6243940 We might end up in handle_wrong_method if
688 // the callee is deoptimized as we race thru here. If that
689 // happens we don't want to take a safepoint because the
690 // caller frame will look interpreted and arguments are now
691 // "compiled" so it is much better to make this transition
692 // invisible to the stack walking code. Unfortunately if
693 // we try and find the callee by normal means a safepoint
694 // is possible. So we stash the desired callee in the thread
695 // and the vm will find there should this case occur.
696
697 __ sd(xmethod, Address(xthread, JavaThread::callee_target_offset()));
698
699 __ jr(t1);
700 }
701
702 static void gen_inline_cache_check(MacroAssembler *masm, Label& skip_fixup) {
703 Register data = t0;
704
705 __ ic_check();
706 __ ld(xmethod, Address(data, CompiledICData::speculated_method_offset()));
707
708 // Method might have been compiled since the call site was patched to
709 // interpreted; if that is the case treat it as a miss so we can get
710 // the call site corrected.
711 __ ld(t0, Address(xmethod, in_bytes(Method::code_offset())));
712 __ beqz(t0, skip_fixup);
713 __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
714 }
715
716 // ---------------------------------------------------------------
717
718 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler* masm,
719 int comp_args_on_stack,
720 const GrowableArray<SigEntry>* sig,
721 const VMRegPair* regs,
722 const GrowableArray<SigEntry>* sig_cc,
723 const VMRegPair* regs_cc,
724 const GrowableArray<SigEntry>* sig_cc_ro,
725 const VMRegPair* regs_cc_ro,
726 address entry_address[AdapterBlob::ENTRY_COUNT],
727 AdapterBlob*& new_adapter,
728 bool allocate_code_blob) {
729
730 entry_address[AdapterBlob::I2C] = __ pc();
731 gen_i2c_adapter(masm, comp_args_on_stack, sig, regs);
732
733 // -------------------------------------------------------------------------
734 // Generate a C2I adapter. On entry we know xmethod holds the Method* during calls
735 // to the interpreter. The args start out packed in the compiled layout. They
736 // need to be unpacked into the interpreter layout. This will almost always
737 // require some stack space. We grow the current (compiled) stack, then repack
738 // the args. We finally end in a jump to the generic interpreter entry point.
739 // On exit from the interpreter, the interpreter will restore our SP (lest the
740 // compiled code, which relies solely on SP and not FP, get sick).
741 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
742 entry_address[AdapterBlob::C2I_Unverified_Inline] = __ pc();
743
744 Label skip_fixup;
745 gen_inline_cache_check(masm, skip_fixup);
746
747 OopMapSet* oop_maps = new OopMapSet();
748 int frame_complete = CodeOffsets::frame_never_safe;
749 int frame_size_in_words = 0;
750
751 // Scalarized c2i adapter with non-scalarized receiver (i.e., don't pack receiver)
752 entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
753 entry_address[AdapterBlob::C2I_Inline_RO] = __ pc();
754 if (regs_cc != regs_cc_ro) {
755 // No class init barrier needed because method is guaranteed to be non-static
756 gen_c2i_adapter(masm, sig_cc_ro, regs_cc_ro, /* requires_clinit_barrier = */ false, entry_address[AdapterBlob::C2I_No_Clinit_Check],
757 skip_fixup, entry_address[AdapterBlob::I2C], oop_maps, frame_complete, frame_size_in_words, /* alloc_inline_receiver = */ false);
758 skip_fixup.reset();
759 }
760
761 // Scalarized c2i adapter
762 entry_address[AdapterBlob::C2I] = __ pc();
763 entry_address[AdapterBlob::C2I_Inline] = __ pc();
764 gen_c2i_adapter(masm, sig_cc, regs_cc, /* requires_clinit_barrier = */ true, entry_address[AdapterBlob::C2I_No_Clinit_Check],
765 skip_fixup, entry_address[AdapterBlob::I2C], oop_maps, frame_complete, frame_size_in_words, /* alloc_inline_receiver = */ true);
766
767 // Non-scalarized c2i adapter
768 if (regs != regs_cc) {
769 entry_address[AdapterBlob::C2I_Unverified_Inline] = __ pc();
770 Label inline_entry_skip_fixup;
771 gen_inline_cache_check(masm, inline_entry_skip_fixup);
772
773 entry_address[AdapterBlob::C2I_Inline] = __ pc();
774 gen_c2i_adapter(masm, sig, regs, /* requires_clinit_barrier = */ true, entry_address[AdapterBlob::C2I_No_Clinit_Check],
775 inline_entry_skip_fixup, entry_address[AdapterBlob::I2C], oop_maps, frame_complete, frame_size_in_words, /* alloc_inline_receiver = */ false);
776 }
777
778 // The c2i adapters might safepoint and trigger a GC. The caller must make sure that
779 // the GC knows about the location of oop argument locations passed to the c2i adapter.
780 if (allocate_code_blob) {
781 bool caller_must_gc_arguments = (regs != regs_cc);
782 int entry_offset[AdapterHandlerEntry::ENTRIES_COUNT];
783 assert(AdapterHandlerEntry::ENTRIES_COUNT == 7, "sanity");
784 AdapterHandlerLibrary::address_to_offset(entry_address, entry_offset);
785 new_adapter = AdapterBlob::create(masm->code(), entry_offset, frame_complete, frame_size_in_words, oop_maps, caller_must_gc_arguments);
786 }
787 }
788
789 int SharedRuntime::vector_calling_convention(VMRegPair *regs,
790 uint num_bits,
791 uint total_args_passed) {
792 assert(total_args_passed <= Argument::n_vector_register_parameters_c, "unsupported");
793 assert(num_bits >= 64 && num_bits <= 2048 && is_power_of_2(num_bits), "unsupported");
794
795 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
796 static const VectorRegister VEC_ArgReg[Argument::n_vector_register_parameters_c] = {
797 v8, v9, v10, v11, v12, v13, v14, v15,
798 v16, v17, v18, v19, v20, v21, v22, v23
799 };
800
801 const int next_reg_val = 3;
802 for (uint i = 0; i < total_args_passed; i++) {
803 VMReg vmreg = VEC_ArgReg[i]->as_VMReg();
804 regs[i].set_pair(vmreg->next(next_reg_val), vmreg);
805 }
806 return 0;
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