326 // VM needs caller's callsite
327 // VM needs target method
328 // This needs to be a long call since we will relocate this adapter to
329 // the codeBuffer and it may not reach
330
331 #ifndef PRODUCT
332 assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
333 #endif
334
335 __ mv(c_rarg0, xmethod);
336 __ mv(c_rarg1, ra);
337 __ rt_call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
338
339 __ pop_CPU_state();
340 // restore sp
341 __ leave();
342 __ bind(L);
343 }
344
345 static void gen_c2i_adapter(MacroAssembler *masm,
346 int total_args_passed,
347 int comp_args_on_stack,
348 const BasicType *sig_bt,
349 const VMRegPair *regs,
350 Label& skip_fixup) {
351 // Before we get into the guts of the C2I adapter, see if we should be here
352 // at all. We've come from compiled code and are attempting to jump to the
353 // interpreter, which means the caller made a static call to get here
354 // (vcalls always get a compiled target if there is one). Check for a
355 // compiled target. If there is one, we need to patch the caller's call.
356 patch_callers_callsite(masm);
357
358 __ bind(skip_fixup);
359
360 int words_pushed = 0;
361
362 // Since all args are passed on the stack, total_args_passed *
363 // Interpreter::stackElementSize is the space we need.
364
365 int extraspace = total_args_passed * Interpreter::stackElementSize;
366
367 __ mv(x19_sender_sp, sp);
368
369 // stack is aligned, keep it that way
370 extraspace = align_up(extraspace, 2 * wordSize);
371
372 if (extraspace) {
373 __ sub(sp, sp, extraspace);
374 }
375
376 // Now write the args into the outgoing interpreter space
377 for (int i = 0; i < total_args_passed; i++) {
378 if (sig_bt[i] == T_VOID) {
379 assert(i > 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "missing half");
380 continue;
381 }
382
383 // offset to start parameters
384 int st_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
385 int next_off = st_off - Interpreter::stackElementSize;
386
387 // Say 4 args:
388 // i st_off
389 // 0 32 T_LONG
390 // 1 24 T_VOID
391 // 2 16 T_OBJECT
392 // 3 8 T_BOOL
393 // - 0 return address
394 //
395 // However to make thing extra confusing. Because we can fit a Java long/double in
396 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
397 // leaves one slot empty and only stores to a single slot. In this case the
398 // slot that is occupied is the T_VOID slot. See I said it was confusing.
399
400 VMReg r_1 = regs[i].first();
401 VMReg r_2 = regs[i].second();
402 if (!r_1->is_valid()) {
403 assert(!r_2->is_valid(), "");
404 continue;
405 }
406 if (r_1->is_stack()) {
407 // memory to memory use t0
408 int ld_off = (r_1->reg2stack() * VMRegImpl::stack_slot_size
409 + extraspace
410 + words_pushed * wordSize);
411 if (!r_2->is_valid()) {
412 __ lwu(t0, Address(sp, ld_off));
413 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
414 } else {
415 __ ld(t0, Address(sp, ld_off), /*temp register*/esp);
416
417 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
418 // T_DOUBLE and T_LONG use two slots in the interpreter
419 if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
420 // ld_off == LSW, ld_off+wordSize == MSW
421 // st_off == MSW, next_off == LSW
422 __ sd(t0, Address(sp, next_off), /*temp register*/esp);
423 #ifdef ASSERT
424 // Overwrite the unused slot with known junk
425 __ mv(t0, 0xdeadffffdeadaaaaul);
426 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
427 #endif /* ASSERT */
428 } else {
429 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
430 }
431 }
432 } else if (r_1->is_Register()) {
433 Register r = r_1->as_Register();
434 if (!r_2->is_valid()) {
435 // must be only an int (or less ) so move only 32bits to slot
436 __ sd(r, Address(sp, st_off));
437 } else {
438 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
439 // T_DOUBLE and T_LONG use two slots in the interpreter
440 if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
441 // long/double in gpr
442 #ifdef ASSERT
443 // Overwrite the unused slot with known junk
444 __ mv(t0, 0xdeadffffdeadaaabul);
445 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
446 #endif /* ASSERT */
447 __ sd(r, Address(sp, next_off));
448 } else {
449 __ sd(r, Address(sp, st_off));
450 }
451 }
452 } else {
453 assert(r_1->is_FloatRegister(), "");
454 if (!r_2->is_valid()) {
455 // only a float use just part of the slot
456 __ fsw(r_1->as_FloatRegister(), Address(sp, st_off));
457 } else {
458 #ifdef ASSERT
459 // Overwrite the unused slot with known junk
460 __ mv(t0, 0xdeadffffdeadaaacul);
461 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
462 #endif /* ASSERT */
463 __ fsd(r_1->as_FloatRegister(), Address(sp, next_off));
464 }
465 }
466 }
467
468 __ mv(esp, sp); // Interp expects args on caller's expression stack
469
470 __ ld(t1, Address(xmethod, in_bytes(Method::interpreter_entry_offset())));
471 __ jr(t1);
472 }
473
474 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
475 int total_args_passed,
476 int comp_args_on_stack,
477 const BasicType *sig_bt,
478 const VMRegPair *regs) {
479 // Note: x19_sender_sp contains the senderSP on entry. We must
480 // preserve it since we may do a i2c -> c2i transition if we lose a
481 // race where compiled code goes non-entrant while we get args
482 // ready.
483
484 // Cut-out for having no stack args.
485 int comp_words_on_stack = align_up(comp_args_on_stack * VMRegImpl::stack_slot_size, wordSize) >> LogBytesPerWord;
486 if (comp_args_on_stack != 0) {
487 __ sub(t0, sp, comp_words_on_stack * wordSize);
488 __ andi(sp, t0, -16);
489 }
490
491 // Will jump to the compiled code just as if compiled code was doing it.
492 // Pre-load the register-jump target early, to schedule it better.
493 __ ld(t1, Address(xmethod, in_bytes(Method::from_compiled_offset())));
494
495 #if INCLUDE_JVMCI
496 if (EnableJVMCI) {
497 // check if this call should be routed towards a specific entry point
498 __ ld(t0, Address(xthread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
499 Label no_alternative_target;
500 __ beqz(t0, no_alternative_target);
501 __ mv(t1, t0);
502 __ sd(zr, Address(xthread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
503 __ bind(no_alternative_target);
504 }
505 #endif // INCLUDE_JVMCI
506
507 // Now generate the shuffle code.
508 for (int i = 0; i < total_args_passed; i++) {
509 if (sig_bt[i] == T_VOID) {
510 assert(i > 0 && (sig_bt[i - 1] == T_LONG || sig_bt[i - 1] == T_DOUBLE), "missing half");
511 continue;
512 }
513
514 // Pick up 0, 1 or 2 words from SP+offset.
515
516 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
517 "scrambled load targets?");
518 // Load in argument order going down.
519 int ld_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
520 // Point to interpreter value (vs. tag)
521 int next_off = ld_off - Interpreter::stackElementSize;
522
523 VMReg r_1 = regs[i].first();
524 VMReg r_2 = regs[i].second();
525 if (!r_1->is_valid()) {
526 assert(!r_2->is_valid(), "");
527 continue;
528 }
529 if (r_1->is_stack()) {
530 // Convert stack slot to an SP offset (+ wordSize to account for return address )
531 int st_off = regs[i].first()->reg2stack() * VMRegImpl::stack_slot_size;
532 if (!r_2->is_valid()) {
533 __ lw(t0, Address(esp, ld_off));
534 __ sd(t0, Address(sp, st_off), /*temp register*/t2);
535 } else {
536 //
537 // We are using two optoregs. This can be either T_OBJECT,
538 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
539 // two slots but only uses one for thr T_LONG or T_DOUBLE case
540 // So we must adjust where to pick up the data to match the
541 // interpreter.
542 //
543 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
544 // are accessed as negative so LSW is at LOW address
545
546 // ld_off is MSW so get LSW
547 const int offset = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
548 next_off : ld_off;
549 __ ld(t0, Address(esp, offset));
550 // st_off is LSW (i.e. reg.first())
551 __ sd(t0, Address(sp, st_off), /*temp register*/t2);
552 }
553 } else if (r_1->is_Register()) { // Register argument
554 Register r = r_1->as_Register();
555 if (r_2->is_valid()) {
556 //
557 // We are using two VMRegs. This can be either T_OBJECT,
558 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
559 // two slots but only uses one for thr T_LONG or T_DOUBLE case
560 // So we must adjust where to pick up the data to match the
561 // interpreter.
562
563 const int offset = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
564 next_off : ld_off;
565
566 // this can be a misaligned move
567 __ ld(r, Address(esp, offset));
568 } else {
569 // sign extend and use a full word?
570 __ lw(r, Address(esp, ld_off));
571 }
572 } else {
573 if (!r_2->is_valid()) {
574 __ flw(r_1->as_FloatRegister(), Address(esp, ld_off));
575 } else {
576 __ fld(r_1->as_FloatRegister(), Address(esp, next_off));
577 }
578 }
579 }
580
581 __ push_cont_fastpath(xthread); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
582
583 // 6243940 We might end up in handle_wrong_method if
584 // the callee is deoptimized as we race thru here. If that
585 // happens we don't want to take a safepoint because the
586 // caller frame will look interpreted and arguments are now
587 // "compiled" so it is much better to make this transition
588 // invisible to the stack walking code. Unfortunately if
589 // we try and find the callee by normal means a safepoint
590 // is possible. So we stash the desired callee in the thread
591 // and the vm will find there should this case occur.
592
593 __ sd(xmethod, Address(xthread, JavaThread::callee_target_offset()));
594
595 __ jr(t1);
596 }
597
598 // ---------------------------------------------------------------
599
600 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
601 int total_args_passed,
602 int comp_args_on_stack,
603 const BasicType *sig_bt,
604 const VMRegPair *regs,
605 address entry_address[AdapterBlob::ENTRY_COUNT]) {
606 entry_address[AdapterBlob::I2C] = __ pc();
607 gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
608
609 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
610 Label skip_fixup;
611
612 const Register receiver = j_rarg0;
613 const Register data = t0;
614
615 // -------------------------------------------------------------------------
616 // Generate a C2I adapter. On entry we know xmethod holds the Method* during calls
617 // to the interpreter. The args start out packed in the compiled layout. They
618 // need to be unpacked into the interpreter layout. This will almost always
619 // require some stack space. We grow the current (compiled) stack, then repack
620 // the args. We finally end in a jump to the generic interpreter entry point.
621 // On exit from the interpreter, the interpreter will restore our SP (lest the
622 // compiled code, which relies solely on SP and not FP, get sick).
623
624 {
625 __ block_comment("c2i_unverified_entry {");
626
627 __ ic_check();
638 // Class initialization barrier for static methods
639 entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
640 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
641 Label L_skip_barrier;
642
643 // Bypass the barrier for non-static methods
644 __ load_unsigned_short(t0, Address(xmethod, Method::access_flags_offset()));
645 __ test_bit(t1, t0, exact_log2(JVM_ACC_STATIC));
646 __ beqz(t1, L_skip_barrier); // non-static
647
648 __ load_method_holder(t1, xmethod);
649 __ clinit_barrier(t1, t0, &L_skip_barrier);
650 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
651
652 __ bind(L_skip_barrier);
653 entry_address[AdapterBlob::C2I_No_Clinit_Check] = __ pc();
654
655 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
656 bs->c2i_entry_barrier(masm);
657
658 gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
659 return;
660 }
661
662 int SharedRuntime::vector_calling_convention(VMRegPair *regs,
663 uint num_bits,
664 uint total_args_passed) {
665 assert(total_args_passed <= Argument::n_vector_register_parameters_c, "unsupported");
666 assert(num_bits >= 64 && num_bits <= 2048 && is_power_of_2(num_bits), "unsupported");
667
668 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
669 static const VectorRegister VEC_ArgReg[Argument::n_vector_register_parameters_c] = {
670 v8, v9, v10, v11, v12, v13, v14, v15,
671 v16, v17, v18, v19, v20, v21, v22, v23
672 };
673
674 const int next_reg_val = 3;
675 for (uint i = 0; i < total_args_passed; i++) {
676 VMReg vmreg = VEC_ArgReg[i]->as_VMReg();
677 regs[i].set_pair(vmreg->next(next_reg_val), vmreg);
678 }
2765 int frame_complete = __ pc() - start;
2766 address the_pc = __ pc();
2767 jfr_prologue(the_pc, masm, xthread);
2768 __ call_VM_leaf(CAST_FROM_FN_PTR(address, JfrIntrinsicSupport::return_lease), 1);
2769
2770 jfr_epilogue(masm);
2771 __ leave();
2772 __ ret();
2773
2774 OopMap* map = new OopMap(framesize, 1);
2775 oop_maps->add_gc_map(the_pc - start, map);
2776
2777 RuntimeStub* stub = // codeBlob framesize is in words (not VMRegImpl::slot_size)
2778 RuntimeStub::new_runtime_stub(name, &code, frame_complete,
2779 (framesize >> (LogBytesPerWord - LogBytesPerInt)),
2780 oop_maps, false);
2781 return stub;
2782 }
2783
2784 #endif // INCLUDE_JFR
|
326 // VM needs caller's callsite
327 // VM needs target method
328 // This needs to be a long call since we will relocate this adapter to
329 // the codeBuffer and it may not reach
330
331 #ifndef PRODUCT
332 assert(frame::arg_reg_save_area_bytes == 0, "not expecting frame reg save area");
333 #endif
334
335 __ mv(c_rarg0, xmethod);
336 __ mv(c_rarg1, ra);
337 __ rt_call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
338
339 __ pop_CPU_state();
340 // restore sp
341 __ leave();
342 __ bind(L);
343 }
344
345 static void gen_c2i_adapter(MacroAssembler *masm,
346 int comp_args_on_stack,
347 const GrowableArray<SigEntry>* sig,
348 const VMRegPair *regs,
349 Label& skip_fixup) {
350 // Before we get into the guts of the C2I adapter, see if we should be here
351 // at all. We've come from compiled code and are attempting to jump to the
352 // interpreter, which means the caller made a static call to get here
353 // (vcalls always get a compiled target if there is one). Check for a
354 // compiled target. If there is one, we need to patch the caller's call.
355 patch_callers_callsite(masm);
356
357 __ bind(skip_fixup);
358
359 int words_pushed = 0;
360
361 // Since all args are passed on the stack, total_args_passed *
362 // Interpreter::stackElementSize is the space we need.
363
364 int total_args_passed = sig->length();
365 int extraspace = total_args_passed * Interpreter::stackElementSize;
366
367 __ mv(x19_sender_sp, sp);
368
369 // stack is aligned, keep it that way
370 extraspace = align_up(extraspace, 2 * wordSize);
371
372 if (extraspace) {
373 __ sub(sp, sp, extraspace);
374 }
375
376 // Now write the args into the outgoing interpreter space
377 for (int i = 0; i < total_args_passed; i++) {
378 BasicType bt = sig->at(i)._bt;
379 if (bt == T_VOID) {
380 assert(i > 0 && (sig->at(i - 1)._bt == T_LONG || sig->at(i - 1)._bt == T_DOUBLE), "missing half");
381 continue;
382 }
383
384 // offset to start parameters
385 int st_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
386 int next_off = st_off - Interpreter::stackElementSize;
387
388 // Say 4 args:
389 // i st_off
390 // 0 32 T_LONG
391 // 1 24 T_VOID
392 // 2 16 T_OBJECT
393 // 3 8 T_BOOL
394 // - 0 return address
395 //
396 // However to make thing extra confusing. Because we can fit a Java long/double in
397 // a single slot on a 64 bt vm and it would be silly to break them up, the interpreter
398 // leaves one slot empty and only stores to a single slot. In this case the
399 // slot that is occupied is the T_VOID slot. See I said it was confusing.
400
401 VMReg r_1 = regs[i].first();
402 VMReg r_2 = regs[i].second();
403 if (!r_1->is_valid()) {
404 assert(!r_2->is_valid(), "");
405 continue;
406 }
407 if (r_1->is_stack()) {
408 // memory to memory use t0
409 int ld_off = (r_1->reg2stack() * VMRegImpl::stack_slot_size
410 + extraspace
411 + words_pushed * wordSize);
412 if (!r_2->is_valid()) {
413 __ lwu(t0, Address(sp, ld_off));
414 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
415 } else {
416 __ ld(t0, Address(sp, ld_off), /*temp register*/esp);
417
418 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
419 // T_DOUBLE and T_LONG use two slots in the interpreter
420 if (bt == T_LONG || bt == T_DOUBLE) {
421 // ld_off == LSW, ld_off+wordSize == MSW
422 // st_off == MSW, next_off == LSW
423 __ sd(t0, Address(sp, next_off), /*temp register*/esp);
424 #ifdef ASSERT
425 // Overwrite the unused slot with known junk
426 __ mv(t0, 0xdeadffffdeadaaaaul);
427 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
428 #endif /* ASSERT */
429 } else {
430 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
431 }
432 }
433 } else if (r_1->is_Register()) {
434 Register r = r_1->as_Register();
435 if (!r_2->is_valid()) {
436 // must be only an int (or less ) so move only 32bits to slot
437 __ sd(r, Address(sp, st_off));
438 } else {
439 // Two VMREgs|OptoRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
440 // T_DOUBLE and T_LONG use two slots in the interpreter
441 if (bt == T_LONG || bt == T_DOUBLE) {
442 // long/double in gpr
443 #ifdef ASSERT
444 // Overwrite the unused slot with known junk
445 __ mv(t0, 0xdeadffffdeadaaabul);
446 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
447 #endif /* ASSERT */
448 __ sd(r, Address(sp, next_off));
449 } else {
450 __ sd(r, Address(sp, st_off));
451 }
452 }
453 } else {
454 assert(r_1->is_FloatRegister(), "");
455 if (!r_2->is_valid()) {
456 // only a float use just part of the slot
457 __ fsw(r_1->as_FloatRegister(), Address(sp, st_off));
458 } else {
459 #ifdef ASSERT
460 // Overwrite the unused slot with known junk
461 __ mv(t0, 0xdeadffffdeadaaacul);
462 __ sd(t0, Address(sp, st_off), /*temp register*/esp);
463 #endif /* ASSERT */
464 __ fsd(r_1->as_FloatRegister(), Address(sp, next_off));
465 }
466 }
467 }
468
469 __ mv(esp, sp); // Interp expects args on caller's expression stack
470
471 __ ld(t1, Address(xmethod, in_bytes(Method::interpreter_entry_offset())));
472 __ jr(t1);
473 }
474
475 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
476 int comp_args_on_stack,
477 const GrowableArray<SigEntry>* sig,
478 const VMRegPair *regs) {
479 // Note: x19_sender_sp contains the senderSP on entry. We must
480 // preserve it since we may do a i2c -> c2i transition if we lose a
481 // race where compiled code goes non-entrant while we get args
482 // ready.
483
484 // Cut-out for having no stack args.
485 int comp_words_on_stack = align_up(comp_args_on_stack * VMRegImpl::stack_slot_size, wordSize) >> LogBytesPerWord;
486 if (comp_args_on_stack != 0) {
487 __ sub(t0, sp, comp_words_on_stack * wordSize);
488 __ andi(sp, t0, -16);
489 }
490
491 // Will jump to the compiled code just as if compiled code was doing it.
492 // Pre-load the register-jump target early, to schedule it better.
493 __ ld(t1, Address(xmethod, in_bytes(Method::from_compiled_offset())));
494
495 #if INCLUDE_JVMCI
496 if (EnableJVMCI) {
497 // check if this call should be routed towards a specific entry point
498 __ ld(t0, Address(xthread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
499 Label no_alternative_target;
500 __ beqz(t0, no_alternative_target);
501 __ mv(t1, t0);
502 __ sd(zr, Address(xthread, in_bytes(JavaThread::jvmci_alternate_call_target_offset())));
503 __ bind(no_alternative_target);
504 }
505 #endif // INCLUDE_JVMCI
506
507 // Now generate the shuffle code.
508 int total_args_passed = sig->length();
509 for (int i = 0; i < total_args_passed; i++) {
510 BasicType bt = sig->at(i)._bt;
511 if (bt == T_VOID) {
512 assert(i > 0 && (sig->at(i - 1)._bt == T_LONG || sig->at(i - 1)._bt == T_DOUBLE), "missing half");
513 continue;
514 }
515
516 // Pick up 0, 1 or 2 words from SP+offset.
517
518 assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
519 "scrambled load targets?");
520 // Load in argument order going down.
521 int ld_off = (total_args_passed - i - 1) * Interpreter::stackElementSize;
522 // Point to interpreter value (vs. tag)
523 int next_off = ld_off - Interpreter::stackElementSize;
524
525 VMReg r_1 = regs[i].first();
526 VMReg r_2 = regs[i].second();
527 if (!r_1->is_valid()) {
528 assert(!r_2->is_valid(), "");
529 continue;
530 }
531 if (r_1->is_stack()) {
532 // Convert stack slot to an SP offset (+ wordSize to account for return address )
533 int st_off = regs[i].first()->reg2stack() * VMRegImpl::stack_slot_size;
534 if (!r_2->is_valid()) {
535 __ lw(t0, Address(esp, ld_off));
536 __ sd(t0, Address(sp, st_off), /*temp register*/t2);
537 } else {
538 //
539 // We are using two optoregs. This can be either T_OBJECT,
540 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
541 // two slots but only uses one for thr T_LONG or T_DOUBLE case
542 // So we must adjust where to pick up the data to match the
543 // interpreter.
544 //
545 // Interpreter local[n] == MSW, local[n+1] == LSW however locals
546 // are accessed as negative so LSW is at LOW address
547
548 // ld_off is MSW so get LSW
549 const int offset = (bt == T_LONG || bt == T_DOUBLE) ?
550 next_off : ld_off;
551 __ ld(t0, Address(esp, offset));
552 // st_off is LSW (i.e. reg.first())
553 __ sd(t0, Address(sp, st_off), /*temp register*/t2);
554 }
555 } else if (r_1->is_Register()) { // Register argument
556 Register r = r_1->as_Register();
557 if (r_2->is_valid()) {
558 //
559 // We are using two VMRegs. This can be either T_OBJECT,
560 // T_ADDRESS, T_LONG, or T_DOUBLE the interpreter allocates
561 // two slots but only uses one for thr T_LONG or T_DOUBLE case
562 // So we must adjust where to pick up the data to match the
563 // interpreter.
564
565 const int offset = (bt == T_LONG || bt == T_DOUBLE) ?
566 next_off : ld_off;
567
568 // this can be a misaligned move
569 __ ld(r, Address(esp, offset));
570 } else {
571 // sign extend and use a full word?
572 __ lw(r, Address(esp, ld_off));
573 }
574 } else {
575 if (!r_2->is_valid()) {
576 __ flw(r_1->as_FloatRegister(), Address(esp, ld_off));
577 } else {
578 __ fld(r_1->as_FloatRegister(), Address(esp, next_off));
579 }
580 }
581 }
582
583 __ push_cont_fastpath(xthread); // Set JavaThread::_cont_fastpath to the sp of the oldest interpreted frame we know about
584
585 // 6243940 We might end up in handle_wrong_method if
586 // the callee is deoptimized as we race thru here. If that
587 // happens we don't want to take a safepoint because the
588 // caller frame will look interpreted and arguments are now
589 // "compiled" so it is much better to make this transition
590 // invisible to the stack walking code. Unfortunately if
591 // we try and find the callee by normal means a safepoint
592 // is possible. So we stash the desired callee in the thread
593 // and the vm will find there should this case occur.
594
595 __ sd(xmethod, Address(xthread, JavaThread::callee_target_offset()));
596
597 __ jr(t1);
598 }
599
600 // ---------------------------------------------------------------
601
602 void SharedRuntime::generate_i2c2i_adapters(MacroAssembler* masm,
603 int comp_args_on_stack,
604 const GrowableArray<SigEntry>* sig,
605 const VMRegPair* regs,
606 const GrowableArray<SigEntry>* sig_cc,
607 const VMRegPair* regs_cc,
608 const GrowableArray<SigEntry>* sig_cc_ro,
609 const VMRegPair* regs_cc_ro,
610 address entry_address[AdapterBlob::ENTRY_COUNT],
611 AdapterBlob*& new_adapter,
612 bool allocate_code_blob) {
613 entry_address[AdapterBlob::I2C] = __ pc();
614 gen_i2c_adapter(masm, comp_args_on_stack, sig, regs);
615
616 entry_address[AdapterBlob::C2I_Unverified] = __ pc();
617 Label skip_fixup;
618
619 const Register receiver = j_rarg0;
620 const Register data = t0;
621
622 // -------------------------------------------------------------------------
623 // Generate a C2I adapter. On entry we know xmethod holds the Method* during calls
624 // to the interpreter. The args start out packed in the compiled layout. They
625 // need to be unpacked into the interpreter layout. This will almost always
626 // require some stack space. We grow the current (compiled) stack, then repack
627 // the args. We finally end in a jump to the generic interpreter entry point.
628 // On exit from the interpreter, the interpreter will restore our SP (lest the
629 // compiled code, which relies solely on SP and not FP, get sick).
630
631 {
632 __ block_comment("c2i_unverified_entry {");
633
634 __ ic_check();
645 // Class initialization barrier for static methods
646 entry_address[AdapterBlob::C2I_No_Clinit_Check] = nullptr;
647 assert(VM_Version::supports_fast_class_init_checks(), "sanity");
648 Label L_skip_barrier;
649
650 // Bypass the barrier for non-static methods
651 __ load_unsigned_short(t0, Address(xmethod, Method::access_flags_offset()));
652 __ test_bit(t1, t0, exact_log2(JVM_ACC_STATIC));
653 __ beqz(t1, L_skip_barrier); // non-static
654
655 __ load_method_holder(t1, xmethod);
656 __ clinit_barrier(t1, t0, &L_skip_barrier);
657 __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
658
659 __ bind(L_skip_barrier);
660 entry_address[AdapterBlob::C2I_No_Clinit_Check] = __ pc();
661
662 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
663 bs->c2i_entry_barrier(masm);
664
665 gen_c2i_adapter(masm, comp_args_on_stack, sig, regs, skip_fixup);
666 return;
667 }
668
669 int SharedRuntime::vector_calling_convention(VMRegPair *regs,
670 uint num_bits,
671 uint total_args_passed) {
672 assert(total_args_passed <= Argument::n_vector_register_parameters_c, "unsupported");
673 assert(num_bits >= 64 && num_bits <= 2048 && is_power_of_2(num_bits), "unsupported");
674
675 // check more info at https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-cc.adoc
676 static const VectorRegister VEC_ArgReg[Argument::n_vector_register_parameters_c] = {
677 v8, v9, v10, v11, v12, v13, v14, v15,
678 v16, v17, v18, v19, v20, v21, v22, v23
679 };
680
681 const int next_reg_val = 3;
682 for (uint i = 0; i < total_args_passed; i++) {
683 VMReg vmreg = VEC_ArgReg[i]->as_VMReg();
684 regs[i].set_pair(vmreg->next(next_reg_val), vmreg);
685 }
2772 int frame_complete = __ pc() - start;
2773 address the_pc = __ pc();
2774 jfr_prologue(the_pc, masm, xthread);
2775 __ call_VM_leaf(CAST_FROM_FN_PTR(address, JfrIntrinsicSupport::return_lease), 1);
2776
2777 jfr_epilogue(masm);
2778 __ leave();
2779 __ ret();
2780
2781 OopMap* map = new OopMap(framesize, 1);
2782 oop_maps->add_gc_map(the_pc - start, map);
2783
2784 RuntimeStub* stub = // codeBlob framesize is in words (not VMRegImpl::slot_size)
2785 RuntimeStub::new_runtime_stub(name, &code, frame_complete,
2786 (framesize >> (LogBytesPerWord - LogBytesPerInt)),
2787 oop_maps, false);
2788 return stub;
2789 }
2790
2791 #endif // INCLUDE_JFR
2792
2793 const uint SharedRuntime::java_return_convention_max_int = Argument::n_int_register_parameters_j;
2794 const uint SharedRuntime::java_return_convention_max_float = Argument::n_float_register_parameters_j;
2795
2796 int SharedRuntime::java_return_convention(const BasicType *sig_bt, VMRegPair *regs, int total_args_passed) {
2797 Unimplemented();
2798 return 0;
2799 }
2800
2801 BufferedInlineTypeBlob* SharedRuntime::generate_buffered_inline_type_adapter(const InlineKlass* vk) {
2802 Unimplemented();
2803 return nullptr;
2804 }
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