< prev index next >

src/hotspot/cpu/riscv/vm_version_riscv.cpp

Print this page
@@ -1,7 +1,7 @@
  /*
-  * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
+  * Copyright (c) 1997, 2026, Oracle and/or its affiliates. All rights reserved.
   * Copyright (c) 2020, 2023, Huawei Technologies Co., Ltd. All rights reserved.
   * Copyright (c) 2023, Rivos Inc. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it

@@ -216,10 +216,19 @@
  
    if (UseCRC32CIntrinsics) {
      warning("CRC32C intrinsics are not available on this CPU.");
      FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
    }
+ 
+   if (InlineTypePassFieldsAsArgs) {
+     warning("InlineTypePassFieldsAsArgs is not supported on this CPU");
+     FLAG_SET_DEFAULT(InlineTypePassFieldsAsArgs, false);
+   }
+   if (InlineTypeReturnedAsFields) {
+     warning("InlineTypeReturnedAsFields is not supported on this CPU");
+     FLAG_SET_DEFAULT(InlineTypeReturnedAsFields, false);
+   }
  }
  
  #ifdef COMPILER2
  void VM_Version::c2_initialize() {
    if (!UseRVV) {
< prev index next >