11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "crc32c.h"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/barrierSetAssembler.hpp"
34 #include "gc/shared/collectedHeap.inline.hpp"
35 #include "gc/shared/tlab_globals.hpp"
36 #include "interpreter/bytecodeHistogram.hpp"
37 #include "interpreter/interpreter.hpp"
38 #include "jvm.h"
39 #include "memory/resourceArea.hpp"
40 #include "memory/universe.hpp"
41 #include "oops/accessDecorators.hpp"
42 #include "oops/compressedKlass.inline.hpp"
43 #include "oops/compressedOops.inline.hpp"
44 #include "oops/klass.inline.hpp"
45 #include "prims/methodHandles.hpp"
46 #include "runtime/continuation.hpp"
47 #include "runtime/interfaceSupport.inline.hpp"
48 #include "runtime/javaThread.hpp"
49 #include "runtime/jniHandles.hpp"
50 #include "runtime/objectMonitor.hpp"
51 #include "runtime/os.hpp"
52 #include "runtime/safepoint.hpp"
53 #include "runtime/safepointMechanism.hpp"
54 #include "runtime/sharedRuntime.hpp"
55 #include "runtime/stubRoutines.hpp"
56 #include "utilities/checkedCast.hpp"
57 #include "utilities/macros.hpp"
58
59 #ifdef PRODUCT
60 #define BLOCK_COMMENT(str) /* nothing */
61 #define STOP(error) stop(error)
62 #else
63 #define BLOCK_COMMENT(str) block_comment(str)
64 #define STOP(error) block_comment(error); stop(error)
65 #endif
66
67 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
68
69 #ifdef ASSERT
70 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
71 #endif
72
73 static const Assembler::Condition reverse[] = {
74 Assembler::noOverflow /* overflow = 0x0 */ ,
75 Assembler::overflow /* noOverflow = 0x1 */ ,
76 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
77 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
1701 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1702 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1703 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1704 pass_arg2(this, arg_2);
1705 pass_arg1(this, arg_1);
1706 pass_arg0(this, arg_0);
1707 call_VM_leaf(entry_point, 3);
1708 }
1709
1710 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1711 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1712 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1713 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1714 pass_arg3(this, arg_3);
1715 pass_arg2(this, arg_2);
1716 pass_arg1(this, arg_1);
1717 pass_arg0(this, arg_0);
1718 call_VM_leaf(entry_point, 3);
1719 }
1720
1721 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1722 pass_arg0(this, arg_0);
1723 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1724 }
1725
1726 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1727 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1728 pass_arg1(this, arg_1);
1729 pass_arg0(this, arg_0);
1730 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1731 }
1732
1733 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1734 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1735 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1736 pass_arg2(this, arg_2);
1737 pass_arg1(this, arg_1);
1738 pass_arg0(this, arg_0);
1739 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1740 }
2885 lea(rscratch, src);
2886 Assembler::mulss(dst, Address(rscratch, 0));
2887 }
2888 }
2889
2890 void MacroAssembler::null_check(Register reg, int offset) {
2891 if (needs_explicit_null_check(offset)) {
2892 // provoke OS null exception if reg is null by
2893 // accessing M[reg] w/o changing any (non-CC) registers
2894 // NOTE: cmpl is plenty here to provoke a segv
2895 cmpptr(rax, Address(reg, 0));
2896 // Note: should probably use testl(rax, Address(reg, 0));
2897 // may be shorter code (however, this version of
2898 // testl needs to be implemented first)
2899 } else {
2900 // nothing to do, (later) access of M[reg + offset]
2901 // will provoke OS null exception if reg is null
2902 }
2903 }
2904
2905 void MacroAssembler::os_breakpoint() {
2906 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2907 // (e.g., MSVC can't call ps() otherwise)
2908 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2909 }
2910
2911 void MacroAssembler::unimplemented(const char* what) {
2912 const char* buf = nullptr;
2913 {
2914 ResourceMark rm;
2915 stringStream ss;
2916 ss.print("unimplemented: %s", what);
2917 buf = code_string(ss.as_string());
2918 }
2919 stop(buf);
2920 }
2921
2922 #ifdef _LP64
2923 #define XSTATE_BV 0x200
2924 #endif
4049 }
4050
4051 // C++ bool manipulation
4052 void MacroAssembler::testbool(Register dst) {
4053 if(sizeof(bool) == 1)
4054 testb(dst, 0xff);
4055 else if(sizeof(bool) == 2) {
4056 // testw implementation needed for two byte bools
4057 ShouldNotReachHere();
4058 } else if(sizeof(bool) == 4)
4059 testl(dst, dst);
4060 else
4061 // unsupported
4062 ShouldNotReachHere();
4063 }
4064
4065 void MacroAssembler::testptr(Register dst, Register src) {
4066 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4067 }
4068
4069 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4070 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4071 Register var_size_in_bytes,
4072 int con_size_in_bytes,
4073 Register t1,
4074 Register t2,
4075 Label& slow_case) {
4076 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4077 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4078 }
4079
4080 RegSet MacroAssembler::call_clobbered_gp_registers() {
4081 RegSet regs;
4082 #ifdef _LP64
4083 regs += RegSet::of(rax, rcx, rdx);
4084 #ifndef WINDOWS
4085 regs += RegSet::of(rsi, rdi);
4086 #endif
4087 regs += RegSet::range(r8, r11);
4088 #else
4307 // clear topmost word (no jump would be needed if conditional assignment worked here)
4308 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4309 // index could be 0 now, must check again
4310 jcc(Assembler::zero, done);
4311 bind(even);
4312 }
4313 #endif // !_LP64
4314 // initialize remaining object fields: index is a multiple of 2 now
4315 {
4316 Label loop;
4317 bind(loop);
4318 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4319 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4320 decrement(index);
4321 jcc(Assembler::notZero, loop);
4322 }
4323
4324 bind(done);
4325 }
4326
4327 // Look up the method for a megamorphic invokeinterface call.
4328 // The target method is determined by <intf_klass, itable_index>.
4329 // The receiver klass is in recv_klass.
4330 // On success, the result will be in method_result, and execution falls through.
4331 // On failure, execution transfers to the given label.
4332 void MacroAssembler::lookup_interface_method(Register recv_klass,
4333 Register intf_klass,
4334 RegisterOrConstant itable_index,
4335 Register method_result,
4336 Register scan_temp,
4337 Label& L_no_such_interface,
4338 bool return_method) {
4339 assert_different_registers(recv_klass, intf_klass, scan_temp);
4340 assert_different_registers(method_result, intf_klass, scan_temp);
4341 assert(recv_klass != method_result || !return_method,
4342 "recv_klass can be destroyed when method isn't needed");
4343
4344 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4345 "caller must use same register for non-constant itable index as for method");
4346
5108 } else {
5109 Label L;
5110 jccb(negate_condition(cc), L);
5111 movl(dst, src);
5112 bind(L);
5113 }
5114 }
5115
5116 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5117 if (VM_Version::supports_cmov()) {
5118 cmovl(cc, dst, src);
5119 } else {
5120 Label L;
5121 jccb(negate_condition(cc), L);
5122 movl(dst, src);
5123 bind(L);
5124 }
5125 }
5126
5127 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5128 if (!VerifyOops) return;
5129
5130 BLOCK_COMMENT("verify_oop {");
5131 #ifdef _LP64
5132 push(rscratch1);
5133 #endif
5134 push(rax); // save rax
5135 push(reg); // pass register argument
5136
5137 // Pass register number to verify_oop_subroutine
5138 const char* b = nullptr;
5139 {
5140 ResourceMark rm;
5141 stringStream ss;
5142 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5143 b = code_string(ss.as_string());
5144 }
5145 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5146 pushptr(buffer.addr(), rscratch1);
5147
5148 // call indirectly to solve generation ordering problem
5170 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5171 int stackElementSize = Interpreter::stackElementSize;
5172 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5173 #ifdef ASSERT
5174 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5175 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5176 #endif
5177 Register scale_reg = noreg;
5178 Address::ScaleFactor scale_factor = Address::no_scale;
5179 if (arg_slot.is_constant()) {
5180 offset += arg_slot.as_constant() * stackElementSize;
5181 } else {
5182 scale_reg = arg_slot.as_register();
5183 scale_factor = Address::times(stackElementSize);
5184 }
5185 offset += wordSize; // return PC is on stack
5186 return Address(rsp, scale_reg, scale_factor, offset);
5187 }
5188
5189 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5190 if (!VerifyOops) return;
5191
5192 #ifdef _LP64
5193 push(rscratch1);
5194 #endif
5195 push(rax); // save rax,
5196 // addr may contain rsp so we will have to adjust it based on the push
5197 // we just did (and on 64 bit we do two pushes)
5198 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5199 // stores rax into addr which is backwards of what was intended.
5200 if (addr.uses(rsp)) {
5201 lea(rax, addr);
5202 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5203 } else {
5204 pushptr(addr);
5205 }
5206
5207 // Pass register number to verify_oop_subroutine
5208 const char* b = nullptr;
5209 {
5210 ResourceMark rm;
5657
5658 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5659 // get mirror
5660 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5661 load_method_holder(mirror, method);
5662 movptr(mirror, Address(mirror, mirror_offset));
5663 resolve_oop_handle(mirror, tmp);
5664 }
5665
5666 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5667 load_method_holder(rresult, rmethod);
5668 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5669 }
5670
5671 void MacroAssembler::load_method_holder(Register holder, Register method) {
5672 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5673 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5674 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5675 }
5676
5677 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5678 assert_different_registers(src, tmp);
5679 assert_different_registers(dst, tmp);
5680 #ifdef _LP64
5681 if (UseCompressedClassPointers) {
5682 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5683 decode_klass_not_null(dst, tmp);
5684 } else
5685 #endif
5686 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5687 }
5688
5689 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5690 assert_different_registers(src, tmp);
5691 assert_different_registers(dst, tmp);
5692 #ifdef _LP64
5693 if (UseCompressedClassPointers) {
5694 encode_klass_not_null(src, tmp);
5695 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5696 } else
5697 #endif
5698 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5699 }
5700
5701 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5702 Register tmp1, Register thread_tmp) {
5703 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5704 decorators = AccessInternal::decorator_fixup(decorators, type);
5705 bool as_raw = (decorators & AS_RAW) != 0;
5706 if (as_raw) {
5707 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5708 } else {
5709 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5710 }
5711 }
5712
5713 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5714 Register tmp1, Register tmp2, Register tmp3) {
5715 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5716 decorators = AccessInternal::decorator_fixup(decorators, type);
5717 bool as_raw = (decorators & AS_RAW) != 0;
5718 if (as_raw) {
5719 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5720 } else {
5721 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5722 }
5723 }
5724
5725 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5726 Register thread_tmp, DecoratorSet decorators) {
5727 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
5728 }
5729
5730 // Doesn't do verification, generates fixed size code
5731 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5732 Register thread_tmp, DecoratorSet decorators) {
5733 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
5734 }
5735
5736 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5737 Register tmp2, Register tmp3, DecoratorSet decorators) {
5738 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5739 }
5740
5741 // Used for storing nulls.
5742 void MacroAssembler::store_heap_oop_null(Address dst) {
5743 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5744 }
6044
6045 void MacroAssembler::reinit_heapbase() {
6046 if (UseCompressedOops) {
6047 if (Universe::heap() != nullptr) {
6048 if (CompressedOops::base() == nullptr) {
6049 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6050 } else {
6051 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6052 }
6053 } else {
6054 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6055 }
6056 }
6057 }
6058
6059 #endif // _LP64
6060
6061 #if COMPILER2_OR_JVMCI
6062
6063 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6064 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6065 // cnt - number of qwords (8-byte words).
6066 // base - start address, qword aligned.
6067 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6068 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6069 if (use64byteVector) {
6070 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
6071 } else if (MaxVectorSize >= 32) {
6072 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6073 } else {
6074 pxor(xtmp, xtmp);
6075 }
6076 jmp(L_zero_64_bytes);
6077
6078 BIND(L_loop);
6079 if (MaxVectorSize >= 32) {
6080 fill64(base, 0, xtmp, use64byteVector);
6081 } else {
6082 movdqu(Address(base, 0), xtmp);
6083 movdqu(Address(base, 16), xtmp);
6084 movdqu(Address(base, 32), xtmp);
6085 movdqu(Address(base, 48), xtmp);
6086 }
6087 addptr(base, 64);
6088
6089 BIND(L_zero_64_bytes);
6090 subptr(cnt, 8);
6091 jccb(Assembler::greaterEqual, L_loop);
6092
6093 // Copy trailing 64 bytes
6094 if (use64byteVector) {
6095 addptr(cnt, 8);
6096 jccb(Assembler::equal, L_end);
6097 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
6098 jmp(L_end);
6099 } else {
6100 addptr(cnt, 4);
6101 jccb(Assembler::less, L_tail);
6102 if (MaxVectorSize >= 32) {
6103 vmovdqu(Address(base, 0), xtmp);
6104 } else {
6105 movdqu(Address(base, 0), xtmp);
6106 movdqu(Address(base, 16), xtmp);
6107 }
6108 }
6109 addptr(base, 32);
6110 subptr(cnt, 4);
6111
6112 BIND(L_tail);
6113 addptr(cnt, 4);
6114 jccb(Assembler::lessEqual, L_end);
6115 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6116 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
6117 } else {
6118 decrement(cnt);
6119
6120 BIND(L_sloop);
6121 movq(Address(base, 0), xtmp);
6122 addptr(base, 8);
6123 decrement(cnt);
6124 jccb(Assembler::greaterEqual, L_sloop);
6125 }
6126 BIND(L_end);
6127 }
6128
6129 // Clearing constant sized memory using YMM/ZMM registers.
6130 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6131 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6132 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6133
6134 int vector64_count = (cnt & (~0x7)) >> 3;
6135 cnt = cnt & 0x7;
6136 const int fill64_per_loop = 4;
6137 const int max_unrolled_fill64 = 8;
6138
6139 // 64 byte initialization loop.
6140 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6141 int start64 = 0;
6142 if (vector64_count > max_unrolled_fill64) {
6143 Label LOOP;
6144 Register index = rtmp;
6145
6146 start64 = vector64_count - (vector64_count % fill64_per_loop);
6147
6148 movl(index, 0);
6198 break;
6199 case 7:
6200 if (use64byteVector) {
6201 movl(rtmp, 0x7F);
6202 kmovwl(mask, rtmp);
6203 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6204 } else {
6205 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6206 movl(rtmp, 0x7);
6207 kmovwl(mask, rtmp);
6208 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6209 }
6210 break;
6211 default:
6212 fatal("Unexpected length : %d\n",cnt);
6213 break;
6214 }
6215 }
6216 }
6217
6218 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
6219 bool is_large, KRegister mask) {
6220 // cnt - number of qwords (8-byte words).
6221 // base - start address, qword aligned.
6222 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6223 assert(base==rdi, "base register must be edi for rep stos");
6224 assert(tmp==rax, "tmp register must be eax for rep stos");
6225 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6226 assert(InitArrayShortSize % BytesPerLong == 0,
6227 "InitArrayShortSize should be the multiple of BytesPerLong");
6228
6229 Label DONE;
6230 if (!is_large || !UseXMMForObjInit) {
6231 xorptr(tmp, tmp);
6232 }
6233
6234 if (!is_large) {
6235 Label LOOP, LONG;
6236 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6237 jccb(Assembler::greater, LONG);
6238
6239 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6240
6241 decrement(cnt);
6242 jccb(Assembler::negative, DONE); // Zero length
6243
6244 // Use individual pointer-sized stores for small counts:
6245 BIND(LOOP);
6246 movptr(Address(base, cnt, Address::times_ptr), tmp);
6247 decrement(cnt);
6248 jccb(Assembler::greaterEqual, LOOP);
6249 jmpb(DONE);
6250
6251 BIND(LONG);
6252 }
6253
6254 // Use longer rep-prefixed ops for non-small counts:
6255 if (UseFastStosb) {
6256 shlptr(cnt, 3); // convert to number of bytes
6257 rep_stosb();
6258 } else if (UseXMMForObjInit) {
6259 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6260 } else {
6261 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6262 rep_stos();
6263 }
6264
6265 BIND(DONE);
6266 }
6267
6268 #endif //COMPILER2_OR_JVMCI
6269
6270
6271 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6272 Register to, Register value, Register count,
6273 Register rtmp, XMMRegister xtmp) {
6274 ShortBranchVerifier sbv(this);
6275 assert_different_registers(to, value, count, rtmp);
6276 Label L_exit;
6277 Label L_fill_2_bytes, L_fill_4_bytes;
6278
6279 #if defined(COMPILER2) && defined(_LP64)
10294
10295 // Load top.
10296 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10297
10298 // Check if the lock-stack is full.
10299 cmpl(top, LockStack::end_offset());
10300 jcc(Assembler::greaterEqual, slow);
10301
10302 // Check for recursion.
10303 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10304 jcc(Assembler::equal, push);
10305
10306 // Check header for monitor (0b10).
10307 testptr(reg_rax, markWord::monitor_value);
10308 jcc(Assembler::notZero, slow);
10309
10310 // Try to lock. Transition lock bits 0b01 => 0b00
10311 movptr(tmp, reg_rax);
10312 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10313 orptr(reg_rax, markWord::unlocked_value);
10314 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10315 jcc(Assembler::notEqual, slow);
10316
10317 // Restore top, CAS clobbers register.
10318 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10319
10320 bind(push);
10321 // After successful lock, push object on lock-stack.
10322 movptr(Address(thread, top), obj);
10323 incrementl(top, oopSize);
10324 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10325 }
10326
10327 // Implements lightweight-unlocking.
10328 //
10329 // obj: the object to be unlocked
10330 // reg_rax: rax
10331 // thread: the thread
10332 // tmp: a temporary register
10333 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
|
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "ci/ciInlineKlass.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "jvm.h"
40 #include "memory/resourceArea.hpp"
41 #include "memory/universe.hpp"
42 #include "oops/accessDecorators.hpp"
43 #include "oops/compressedKlass.inline.hpp"
44 #include "oops/compressedOops.inline.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "oops/resolvedFieldEntry.hpp"
47 #include "prims/methodHandles.hpp"
48 #include "runtime/continuation.hpp"
49 #include "runtime/interfaceSupport.inline.hpp"
50 #include "runtime/javaThread.hpp"
51 #include "runtime/jniHandles.hpp"
52 #include "runtime/objectMonitor.hpp"
53 #include "runtime/os.hpp"
54 #include "runtime/safepoint.hpp"
55 #include "runtime/safepointMechanism.hpp"
56 #include "runtime/sharedRuntime.hpp"
57 #include "runtime/signature_cc.hpp"
58 #include "runtime/stubRoutines.hpp"
59 #include "utilities/checkedCast.hpp"
60 #include "utilities/macros.hpp"
61 #include "vmreg_x86.inline.hpp"
62 #ifdef COMPILER2
63 #include "opto/output.hpp"
64 #endif
65
66 #ifdef PRODUCT
67 #define BLOCK_COMMENT(str) /* nothing */
68 #define STOP(error) stop(error)
69 #else
70 #define BLOCK_COMMENT(str) block_comment(str)
71 #define STOP(error) block_comment(error); stop(error)
72 #endif
73
74 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
75
76 #ifdef ASSERT
77 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
78 #endif
79
80 static const Assembler::Condition reverse[] = {
81 Assembler::noOverflow /* overflow = 0x0 */ ,
82 Assembler::overflow /* noOverflow = 0x1 */ ,
83 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
84 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
1708 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1709 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1710 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1711 pass_arg2(this, arg_2);
1712 pass_arg1(this, arg_1);
1713 pass_arg0(this, arg_0);
1714 call_VM_leaf(entry_point, 3);
1715 }
1716
1717 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1718 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1719 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1720 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1721 pass_arg3(this, arg_3);
1722 pass_arg2(this, arg_2);
1723 pass_arg1(this, arg_1);
1724 pass_arg0(this, arg_0);
1725 call_VM_leaf(entry_point, 3);
1726 }
1727
1728 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1729 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1730 }
1731
1732 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1733 pass_arg0(this, arg_0);
1734 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1735 }
1736
1737 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1738 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1739 pass_arg1(this, arg_1);
1740 pass_arg0(this, arg_0);
1741 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1742 }
1743
1744 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1745 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1746 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1747 pass_arg2(this, arg_2);
1748 pass_arg1(this, arg_1);
1749 pass_arg0(this, arg_0);
1750 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1751 }
2896 lea(rscratch, src);
2897 Assembler::mulss(dst, Address(rscratch, 0));
2898 }
2899 }
2900
2901 void MacroAssembler::null_check(Register reg, int offset) {
2902 if (needs_explicit_null_check(offset)) {
2903 // provoke OS null exception if reg is null by
2904 // accessing M[reg] w/o changing any (non-CC) registers
2905 // NOTE: cmpl is plenty here to provoke a segv
2906 cmpptr(rax, Address(reg, 0));
2907 // Note: should probably use testl(rax, Address(reg, 0));
2908 // may be shorter code (however, this version of
2909 // testl needs to be implemented first)
2910 } else {
2911 // nothing to do, (later) access of M[reg + offset]
2912 // will provoke OS null exception if reg is null
2913 }
2914 }
2915
2916 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2917 andptr(markword, markWord::inline_type_mask_in_place);
2918 cmpptr(markword, markWord::inline_type_pattern);
2919 jcc(Assembler::equal, is_inline_type);
2920 }
2921
2922 void MacroAssembler::test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type) {
2923 movl(temp_reg, Address(klass, Klass::access_flags_offset()));
2924 testl(temp_reg, JVM_ACC_IDENTITY);
2925 jcc(Assembler::zero, is_inline_type);
2926 }
2927
2928 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type) {
2929 testptr(object, object);
2930 jcc(Assembler::zero, not_inline_type);
2931 const int is_inline_type_mask = markWord::inline_type_pattern;
2932 movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2933 andptr(tmp, is_inline_type_mask);
2934 cmpptr(tmp, is_inline_type_mask);
2935 jcc(Assembler::notEqual, not_inline_type);
2936 }
2937
2938 void MacroAssembler::test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type) {
2939 #ifdef ASSERT
2940 {
2941 Label done_check;
2942 test_klass_is_inline_type(klass, temp_reg, done_check);
2943 stop("test_klass_is_empty_inline_type with non inline type klass");
2944 bind(done_check);
2945 }
2946 #endif
2947 movl(temp_reg, Address(klass, InstanceKlass::misc_flags_offset()));
2948 testl(temp_reg, InstanceKlassFlags::is_empty_inline_type_value());
2949 jcc(Assembler::notZero, is_empty_inline_type);
2950 }
2951
2952 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2953 movl(temp_reg, flags);
2954 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2955 jcc(Assembler::notEqual, is_null_free_inline_type);
2956 }
2957
2958 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2959 movl(temp_reg, flags);
2960 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2961 jcc(Assembler::equal, not_null_free_inline_type);
2962 }
2963
2964 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2965 movl(temp_reg, flags);
2966 testl(temp_reg, 1 << ResolvedFieldEntry::is_flat_shift);
2967 jcc(Assembler::notEqual, is_flat);
2968 }
2969
2970 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2971 movl(temp_reg, flags);
2972 testl(temp_reg, 1 << ResolvedFieldEntry::has_null_marker_shift);
2973 jcc(Assembler::notEqual, has_null_marker);
2974 }
2975
2976 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2977 Label test_mark_word;
2978 // load mark word
2979 movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2980 // check displaced
2981 testl(temp_reg, markWord::unlocked_value);
2982 jccb(Assembler::notZero, test_mark_word);
2983 // slow path use klass prototype
2984 push(rscratch1);
2985 load_prototype_header(temp_reg, oop, rscratch1);
2986 pop(rscratch1);
2987
2988 bind(test_mark_word);
2989 testl(temp_reg, test_bit);
2990 jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
2991 }
2992
2993 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg,
2994 Label& is_flat_array) {
2995 #ifdef _LP64
2996 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2997 #else
2998 load_klass(temp_reg, oop, noreg);
2999 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
3000 test_flat_array_layout(temp_reg, is_flat_array);
3001 #endif
3002 }
3003
3004 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
3005 Label& is_non_flat_array) {
3006 #ifdef _LP64
3007 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
3008 #else
3009 load_klass(temp_reg, oop, noreg);
3010 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
3011 test_non_flat_array_layout(temp_reg, is_non_flat_array);
3012 #endif
3013 }
3014
3015 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
3016 #ifdef _LP64
3017 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
3018 #else
3019 Unimplemented();
3020 #endif
3021 }
3022
3023 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
3024 #ifdef _LP64
3025 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
3026 #else
3027 Unimplemented();
3028 #endif
3029 }
3030
3031 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
3032 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
3033 jcc(Assembler::notZero, is_flat_array);
3034 }
3035
3036 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
3037 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
3038 jcc(Assembler::zero, is_non_flat_array);
3039 }
3040
3041 void MacroAssembler::os_breakpoint() {
3042 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3043 // (e.g., MSVC can't call ps() otherwise)
3044 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3045 }
3046
3047 void MacroAssembler::unimplemented(const char* what) {
3048 const char* buf = nullptr;
3049 {
3050 ResourceMark rm;
3051 stringStream ss;
3052 ss.print("unimplemented: %s", what);
3053 buf = code_string(ss.as_string());
3054 }
3055 stop(buf);
3056 }
3057
3058 #ifdef _LP64
3059 #define XSTATE_BV 0x200
3060 #endif
4185 }
4186
4187 // C++ bool manipulation
4188 void MacroAssembler::testbool(Register dst) {
4189 if(sizeof(bool) == 1)
4190 testb(dst, 0xff);
4191 else if(sizeof(bool) == 2) {
4192 // testw implementation needed for two byte bools
4193 ShouldNotReachHere();
4194 } else if(sizeof(bool) == 4)
4195 testl(dst, dst);
4196 else
4197 // unsupported
4198 ShouldNotReachHere();
4199 }
4200
4201 void MacroAssembler::testptr(Register dst, Register src) {
4202 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4203 }
4204
4205 // Object / value buffer allocation...
4206 //
4207 // Kills klass and rsi on LP64
4208 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
4209 Register t1, Register t2,
4210 bool clear_fields, Label& alloc_failed)
4211 {
4212 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
4213 Register layout_size = t1;
4214 assert(new_obj == rax, "needs to be rax");
4215 assert_different_registers(klass, new_obj, t1, t2);
4216
4217 // get instance_size in InstanceKlass (scaled to a count of bytes)
4218 movl(layout_size, Address(klass, Klass::layout_helper_offset()));
4219 // test to see if it is malformed in some way
4220 testl(layout_size, Klass::_lh_instance_slow_path_bit);
4221 jcc(Assembler::notZero, slow_case_no_pop);
4222
4223 // Allocate the instance:
4224 // If TLAB is enabled:
4225 // Try to allocate in the TLAB.
4226 // If fails, go to the slow path.
4227 // Else If inline contiguous allocations are enabled:
4228 // Try to allocate in eden.
4229 // If fails due to heap end, go to slow path.
4230 //
4231 // If TLAB is enabled OR inline contiguous is enabled:
4232 // Initialize the allocation.
4233 // Exit.
4234 //
4235 // Go to slow path.
4236
4237 push(klass);
4238 const Register thread = LP64_ONLY(r15_thread) NOT_LP64(klass);
4239 #ifndef _LP64
4240 if (UseTLAB) {
4241 get_thread(thread);
4242 }
4243 #endif // _LP64
4244
4245 if (UseTLAB) {
4246 tlab_allocate(thread, new_obj, layout_size, 0, klass, t2, slow_case);
4247 if (ZeroTLAB || (!clear_fields)) {
4248 // the fields have been already cleared
4249 jmp(initialize_header);
4250 } else {
4251 // initialize both the header and fields
4252 jmp(initialize_object);
4253 }
4254 } else {
4255 jmp(slow_case);
4256 }
4257
4258 // If UseTLAB is true, the object is created above and there is an initialize need.
4259 // Otherwise, skip and go to the slow path.
4260 if (UseTLAB) {
4261 if (clear_fields) {
4262 // The object is initialized before the header. If the object size is
4263 // zero, go directly to the header initialization.
4264 bind(initialize_object);
4265 decrement(layout_size, sizeof(oopDesc));
4266 jcc(Assembler::zero, initialize_header);
4267
4268 // Initialize topmost object field, divide size by 8, check if odd and
4269 // test if zero.
4270 Register zero = klass;
4271 xorl(zero, zero); // use zero reg to clear memory (shorter code)
4272 shrl(layout_size, LogBytesPerLong); // divide by 2*oopSize and set carry flag if odd
4273
4274 #ifdef ASSERT
4275 // make sure instance_size was multiple of 8
4276 Label L;
4277 // Ignore partial flag stall after shrl() since it is debug VM
4278 jcc(Assembler::carryClear, L);
4279 stop("object size is not multiple of 2 - adjust this code");
4280 bind(L);
4281 // must be > 0, no extra check needed here
4282 #endif
4283
4284 // initialize remaining object fields: instance_size was a multiple of 8
4285 {
4286 Label loop;
4287 bind(loop);
4288 movptr(Address(new_obj, layout_size, Address::times_8, sizeof(oopDesc) - 1*oopSize), zero);
4289 NOT_LP64(movptr(Address(new_obj, layout_size, Address::times_8, sizeof(oopDesc) - 2*oopSize), zero));
4290 decrement(layout_size);
4291 jcc(Assembler::notZero, loop);
4292 }
4293 } // clear_fields
4294
4295 // initialize object header only.
4296 bind(initialize_header);
4297 pop(klass);
4298 Register mark_word = t2;
4299 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
4300 movptr(Address(new_obj, oopDesc::mark_offset_in_bytes ()), mark_word);
4301 #ifdef _LP64
4302 xorl(rsi, rsi); // use zero reg to clear memory (shorter code)
4303 store_klass_gap(new_obj, rsi); // zero klass gap for compressed oops
4304 #endif
4305 movptr(t2, klass); // preserve klass
4306 store_klass(new_obj, t2, rscratch1); // src klass reg is potentially compressed
4307
4308 jmp(done);
4309 }
4310
4311 bind(slow_case);
4312 pop(klass);
4313 bind(slow_case_no_pop);
4314 jmp(alloc_failed);
4315
4316 bind(done);
4317 }
4318
4319 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4320 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4321 Register var_size_in_bytes,
4322 int con_size_in_bytes,
4323 Register t1,
4324 Register t2,
4325 Label& slow_case) {
4326 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4327 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4328 }
4329
4330 RegSet MacroAssembler::call_clobbered_gp_registers() {
4331 RegSet regs;
4332 #ifdef _LP64
4333 regs += RegSet::of(rax, rcx, rdx);
4334 #ifndef WINDOWS
4335 regs += RegSet::of(rsi, rdi);
4336 #endif
4337 regs += RegSet::range(r8, r11);
4338 #else
4557 // clear topmost word (no jump would be needed if conditional assignment worked here)
4558 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4559 // index could be 0 now, must check again
4560 jcc(Assembler::zero, done);
4561 bind(even);
4562 }
4563 #endif // !_LP64
4564 // initialize remaining object fields: index is a multiple of 2 now
4565 {
4566 Label loop;
4567 bind(loop);
4568 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4569 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4570 decrement(index);
4571 jcc(Assembler::notZero, loop);
4572 }
4573
4574 bind(done);
4575 }
4576
4577 void MacroAssembler::get_inline_type_field_klass(Register holder_klass, Register index, Register inline_klass) {
4578 inline_layout_info(holder_klass, index, inline_klass);
4579 movptr(inline_klass, Address(inline_klass, InlineLayoutInfo::klass_offset()));
4580 }
4581
4582 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
4583 movptr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
4584 #ifdef ASSERT
4585 {
4586 Label done;
4587 cmpptr(layout_info, 0);
4588 jcc(Assembler::notEqual, done);
4589 stop("inline_layout_info_array is null");
4590 bind(done);
4591 }
4592 #endif
4593
4594 InlineLayoutInfo array[2];
4595 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
4596 if (is_power_of_2(size)) {
4597 shll(index, log2i_exact(size)); // Scale index by power of 2
4598 } else {
4599 imull(index, index, size); // Scale the index to be the entry index * array_element_size
4600 }
4601 lea(layout_info, Address(layout_info, index, Address::times_1, Array<InlineLayoutInfo>::base_offset_in_bytes()));
4602 }
4603
4604 void MacroAssembler::get_default_value_oop(Register inline_klass, Register temp_reg, Register obj) {
4605 #ifdef ASSERT
4606 {
4607 Label done_check;
4608 test_klass_is_inline_type(inline_klass, temp_reg, done_check);
4609 stop("get_default_value_oop from non inline type klass");
4610 bind(done_check);
4611 }
4612 #endif
4613 Register offset = temp_reg;
4614 // Getting the offset of the pre-allocated default value
4615 movptr(offset, Address(inline_klass, in_bytes(InstanceKlass::adr_inlineklass_fixed_block_offset())));
4616 movl(offset, Address(offset, in_bytes(InlineKlass::default_value_offset_offset())));
4617
4618 // Getting the mirror
4619 movptr(obj, Address(inline_klass, in_bytes(Klass::java_mirror_offset())));
4620 resolve_oop_handle(obj, inline_klass);
4621
4622 // Getting the pre-allocated default value from the mirror
4623 Address field(obj, offset, Address::times_1);
4624 load_heap_oop(obj, field);
4625 }
4626
4627 void MacroAssembler::get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj) {
4628 #ifdef ASSERT
4629 {
4630 Label done_check;
4631 test_klass_is_empty_inline_type(inline_klass, temp_reg, done_check);
4632 stop("get_empty_value from non-empty inline klass");
4633 bind(done_check);
4634 }
4635 #endif
4636 get_default_value_oop(inline_klass, temp_reg, obj);
4637 }
4638
4639
4640 // Look up the method for a megamorphic invokeinterface call.
4641 // The target method is determined by <intf_klass, itable_index>.
4642 // The receiver klass is in recv_klass.
4643 // On success, the result will be in method_result, and execution falls through.
4644 // On failure, execution transfers to the given label.
4645 void MacroAssembler::lookup_interface_method(Register recv_klass,
4646 Register intf_klass,
4647 RegisterOrConstant itable_index,
4648 Register method_result,
4649 Register scan_temp,
4650 Label& L_no_such_interface,
4651 bool return_method) {
4652 assert_different_registers(recv_klass, intf_klass, scan_temp);
4653 assert_different_registers(method_result, intf_klass, scan_temp);
4654 assert(recv_klass != method_result || !return_method,
4655 "recv_klass can be destroyed when method isn't needed");
4656
4657 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4658 "caller must use same register for non-constant itable index as for method");
4659
5421 } else {
5422 Label L;
5423 jccb(negate_condition(cc), L);
5424 movl(dst, src);
5425 bind(L);
5426 }
5427 }
5428
5429 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5430 if (VM_Version::supports_cmov()) {
5431 cmovl(cc, dst, src);
5432 } else {
5433 Label L;
5434 jccb(negate_condition(cc), L);
5435 movl(dst, src);
5436 bind(L);
5437 }
5438 }
5439
5440 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5441 if (!VerifyOops || VerifyAdapterSharing) {
5442 // Below address of the code string confuses VerifyAdapterSharing
5443 // because it may differ between otherwise equivalent adapters.
5444 return;
5445 }
5446
5447 BLOCK_COMMENT("verify_oop {");
5448 #ifdef _LP64
5449 push(rscratch1);
5450 #endif
5451 push(rax); // save rax
5452 push(reg); // pass register argument
5453
5454 // Pass register number to verify_oop_subroutine
5455 const char* b = nullptr;
5456 {
5457 ResourceMark rm;
5458 stringStream ss;
5459 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5460 b = code_string(ss.as_string());
5461 }
5462 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5463 pushptr(buffer.addr(), rscratch1);
5464
5465 // call indirectly to solve generation ordering problem
5487 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5488 int stackElementSize = Interpreter::stackElementSize;
5489 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5490 #ifdef ASSERT
5491 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5492 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5493 #endif
5494 Register scale_reg = noreg;
5495 Address::ScaleFactor scale_factor = Address::no_scale;
5496 if (arg_slot.is_constant()) {
5497 offset += arg_slot.as_constant() * stackElementSize;
5498 } else {
5499 scale_reg = arg_slot.as_register();
5500 scale_factor = Address::times(stackElementSize);
5501 }
5502 offset += wordSize; // return PC is on stack
5503 return Address(rsp, scale_reg, scale_factor, offset);
5504 }
5505
5506 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5507 if (!VerifyOops || VerifyAdapterSharing) {
5508 // Below address of the code string confuses VerifyAdapterSharing
5509 // because it may differ between otherwise equivalent adapters.
5510 return;
5511 }
5512
5513 #ifdef _LP64
5514 push(rscratch1);
5515 #endif
5516 push(rax); // save rax,
5517 // addr may contain rsp so we will have to adjust it based on the push
5518 // we just did (and on 64 bit we do two pushes)
5519 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5520 // stores rax into addr which is backwards of what was intended.
5521 if (addr.uses(rsp)) {
5522 lea(rax, addr);
5523 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5524 } else {
5525 pushptr(addr);
5526 }
5527
5528 // Pass register number to verify_oop_subroutine
5529 const char* b = nullptr;
5530 {
5531 ResourceMark rm;
5978
5979 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5980 // get mirror
5981 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5982 load_method_holder(mirror, method);
5983 movptr(mirror, Address(mirror, mirror_offset));
5984 resolve_oop_handle(mirror, tmp);
5985 }
5986
5987 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5988 load_method_holder(rresult, rmethod);
5989 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5990 }
5991
5992 void MacroAssembler::load_method_holder(Register holder, Register method) {
5993 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5994 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5995 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5996 }
5997
5998 void MacroAssembler::load_metadata(Register dst, Register src) {
5999 if (UseCompressedClassPointers) {
6000 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6001 } else {
6002 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6003 }
6004 }
6005
6006 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
6007 assert_different_registers(src, tmp);
6008 assert_different_registers(dst, tmp);
6009 #ifdef _LP64
6010 if (UseCompressedClassPointers) {
6011 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6012 decode_klass_not_null(dst, tmp);
6013 } else
6014 #endif
6015 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6016 }
6017
6018 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
6019 load_klass(dst, src, tmp);
6020 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6021 }
6022
6023 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
6024 assert_different_registers(src, tmp);
6025 assert_different_registers(dst, tmp);
6026 #ifdef _LP64
6027 if (UseCompressedClassPointers) {
6028 encode_klass_not_null(src, tmp);
6029 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6030 } else
6031 #endif
6032 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6033 }
6034
6035 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6036 Register tmp1, Register thread_tmp) {
6037 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6038 decorators = AccessInternal::decorator_fixup(decorators, type);
6039 bool as_raw = (decorators & AS_RAW) != 0;
6040 if (as_raw) {
6041 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6042 } else {
6043 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6044 }
6045 }
6046
6047 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
6048 Register tmp1, Register tmp2, Register tmp3) {
6049 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6050 decorators = AccessInternal::decorator_fixup(decorators, type);
6051 bool as_raw = (decorators & AS_RAW) != 0;
6052 if (as_raw) {
6053 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6054 } else {
6055 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6056 }
6057 }
6058
6059 void MacroAssembler::access_value_copy(DecoratorSet decorators, Register src, Register dst,
6060 Register inline_klass) {
6061 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6062 bs->value_copy(this, decorators, src, dst, inline_klass);
6063 }
6064
6065 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
6066 Register inline_layout_info) {
6067 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6068 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
6069 }
6070
6071 void MacroAssembler::first_field_offset(Register inline_klass, Register offset) {
6072 movptr(offset, Address(inline_klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
6073 movl(offset, Address(offset, InlineKlass::first_field_offset_offset()));
6074 }
6075
6076 void MacroAssembler::data_for_oop(Register oop, Register data, Register inline_klass) {
6077 // ((address) (void*) o) + vk->first_field_offset();
6078 Register offset = (data == oop) ? rscratch1 : data;
6079 first_field_offset(inline_klass, offset);
6080 if (data == oop) {
6081 addptr(data, offset);
6082 } else {
6083 lea(data, Address(oop, offset));
6084 }
6085 }
6086
6087 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
6088 Register index, Register data) {
6089 assert(index != rcx, "index needs to shift by rcx");
6090 assert_different_registers(array, array_klass, index);
6091 assert_different_registers(rcx, array, index);
6092
6093 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
6094 movl(rcx, Address(array_klass, Klass::layout_helper_offset()));
6095
6096 // Klass::layout_helper_log2_element_size(lh)
6097 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
6098 shrl(rcx, Klass::_lh_log2_element_size_shift);
6099 andl(rcx, Klass::_lh_log2_element_size_mask);
6100 shlptr(index); // index << rcx
6101
6102 lea(data, Address(array, index, Address::times_1, arrayOopDesc::base_offset_in_bytes(T_PRIMITIVE_OBJECT)));
6103 }
6104
6105 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6106 Register thread_tmp, DecoratorSet decorators) {
6107 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6108 }
6109
6110 // Doesn't do verification, generates fixed size code
6111 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6112 Register thread_tmp, DecoratorSet decorators) {
6113 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6114 }
6115
6116 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
6117 Register tmp2, Register tmp3, DecoratorSet decorators) {
6118 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
6119 }
6120
6121 // Used for storing nulls.
6122 void MacroAssembler::store_heap_oop_null(Address dst) {
6123 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
6124 }
6424
6425 void MacroAssembler::reinit_heapbase() {
6426 if (UseCompressedOops) {
6427 if (Universe::heap() != nullptr) {
6428 if (CompressedOops::base() == nullptr) {
6429 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6430 } else {
6431 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6432 }
6433 } else {
6434 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6435 }
6436 }
6437 }
6438
6439 #endif // _LP64
6440
6441 #if COMPILER2_OR_JVMCI
6442
6443 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6444 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
6445 // cnt - number of qwords (8-byte words).
6446 // base - start address, qword aligned.
6447 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6448 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6449 if (use64byteVector) {
6450 evpbroadcastq(xtmp, val, AVX_512bit);
6451 } else if (MaxVectorSize >= 32) {
6452 movdq(xtmp, val);
6453 punpcklqdq(xtmp, xtmp);
6454 vinserti128_high(xtmp, xtmp);
6455 } else {
6456 movdq(xtmp, val);
6457 punpcklqdq(xtmp, xtmp);
6458 }
6459 jmp(L_zero_64_bytes);
6460
6461 BIND(L_loop);
6462 if (MaxVectorSize >= 32) {
6463 fill64(base, 0, xtmp, use64byteVector);
6464 } else {
6465 movdqu(Address(base, 0), xtmp);
6466 movdqu(Address(base, 16), xtmp);
6467 movdqu(Address(base, 32), xtmp);
6468 movdqu(Address(base, 48), xtmp);
6469 }
6470 addptr(base, 64);
6471
6472 BIND(L_zero_64_bytes);
6473 subptr(cnt, 8);
6474 jccb(Assembler::greaterEqual, L_loop);
6475
6476 // Copy trailing 64 bytes
6477 if (use64byteVector) {
6478 addptr(cnt, 8);
6479 jccb(Assembler::equal, L_end);
6480 fill64_masked(3, base, 0, xtmp, mask, cnt, val, true);
6481 jmp(L_end);
6482 } else {
6483 addptr(cnt, 4);
6484 jccb(Assembler::less, L_tail);
6485 if (MaxVectorSize >= 32) {
6486 vmovdqu(Address(base, 0), xtmp);
6487 } else {
6488 movdqu(Address(base, 0), xtmp);
6489 movdqu(Address(base, 16), xtmp);
6490 }
6491 }
6492 addptr(base, 32);
6493 subptr(cnt, 4);
6494
6495 BIND(L_tail);
6496 addptr(cnt, 4);
6497 jccb(Assembler::lessEqual, L_end);
6498 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6499 fill32_masked(3, base, 0, xtmp, mask, cnt, val);
6500 } else {
6501 decrement(cnt);
6502
6503 BIND(L_sloop);
6504 movq(Address(base, 0), xtmp);
6505 addptr(base, 8);
6506 decrement(cnt);
6507 jccb(Assembler::greaterEqual, L_sloop);
6508 }
6509 BIND(L_end);
6510 }
6511
6512 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6513 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6514 // An inline type might be returned. If fields are in registers we
6515 // need to allocate an inline type instance and initialize it with
6516 // the value of the fields.
6517 Label skip;
6518 // We only need a new buffered inline type if a new one is not returned
6519 testptr(rax, 1);
6520 jcc(Assembler::zero, skip);
6521 int call_offset = -1;
6522
6523 #ifdef _LP64
6524 // The following code is similar to allocate_instance but has some slight differences,
6525 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6526 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
6527 Label slow_case;
6528 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6529 mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
6530 if (vk != nullptr) {
6531 // Called from C1, where the return type is statically known.
6532 movptr(rbx, (intptr_t)vk->get_InlineKlass());
6533 jint lh = vk->layout_helper();
6534 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6535 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6536 tlab_allocate(r15_thread, rax, noreg, lh, r13, r14, slow_case);
6537 } else {
6538 jmp(slow_case);
6539 }
6540 } else {
6541 // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
6542 mov(rbx, rax);
6543 andptr(rbx, -2);
6544 if (UseTLAB) {
6545 movl(r14, Address(rbx, Klass::layout_helper_offset()));
6546 testl(r14, Klass::_lh_instance_slow_path_bit);
6547 jcc(Assembler::notZero, slow_case);
6548 tlab_allocate(r15_thread, rax, r14, 0, r13, r14, slow_case);
6549 } else {
6550 jmp(slow_case);
6551 }
6552 }
6553 if (UseTLAB) {
6554 // 2. Initialize buffered inline instance header
6555 Register buffer_obj = rax;
6556 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
6557 xorl(r13, r13);
6558 store_klass_gap(buffer_obj, r13);
6559 if (vk == nullptr) {
6560 // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
6561 mov(r13, rbx);
6562 }
6563 store_klass(buffer_obj, rbx, rscratch1);
6564 // 3. Initialize its fields with an inline class specific handler
6565 if (vk != nullptr) {
6566 call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6567 } else {
6568 movptr(rbx, Address(r13, InstanceKlass::adr_inlineklass_fixed_block_offset()));
6569 movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
6570 call(rbx);
6571 }
6572 jmp(skip);
6573 }
6574 bind(slow_case);
6575 // We failed to allocate a new inline type, fall back to a runtime
6576 // call. Some oop field may be live in some registers but we can't
6577 // tell. That runtime call will take care of preserving them
6578 // across a GC if there's one.
6579 mov(rax, rscratch1);
6580 #endif
6581
6582 if (from_interpreter) {
6583 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6584 } else {
6585 call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6586 call_offset = offset();
6587 }
6588
6589 bind(skip);
6590 return call_offset;
6591 }
6592
6593 // Move a value between registers/stack slots and update the reg_state
6594 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6595 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6596 if (reg_state[to->value()] == reg_written) {
6597 return true; // Already written
6598 }
6599 if (from != to && bt != T_VOID) {
6600 if (reg_state[to->value()] == reg_readonly) {
6601 return false; // Not yet writable
6602 }
6603 if (from->is_reg()) {
6604 if (to->is_reg()) {
6605 if (from->is_XMMRegister()) {
6606 if (bt == T_DOUBLE) {
6607 movdbl(to->as_XMMRegister(), from->as_XMMRegister());
6608 } else {
6609 assert(bt == T_FLOAT, "must be float");
6610 movflt(to->as_XMMRegister(), from->as_XMMRegister());
6611 }
6612 } else {
6613 movq(to->as_Register(), from->as_Register());
6614 }
6615 } else {
6616 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6617 Address to_addr = Address(rsp, st_off);
6618 if (from->is_XMMRegister()) {
6619 if (bt == T_DOUBLE) {
6620 movdbl(to_addr, from->as_XMMRegister());
6621 } else {
6622 assert(bt == T_FLOAT, "must be float");
6623 movflt(to_addr, from->as_XMMRegister());
6624 }
6625 } else {
6626 movq(to_addr, from->as_Register());
6627 }
6628 }
6629 } else {
6630 Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
6631 if (to->is_reg()) {
6632 if (to->is_XMMRegister()) {
6633 if (bt == T_DOUBLE) {
6634 movdbl(to->as_XMMRegister(), from_addr);
6635 } else {
6636 assert(bt == T_FLOAT, "must be float");
6637 movflt(to->as_XMMRegister(), from_addr);
6638 }
6639 } else {
6640 movq(to->as_Register(), from_addr);
6641 }
6642 } else {
6643 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6644 movq(r13, from_addr);
6645 movq(Address(rsp, st_off), r13);
6646 }
6647 }
6648 }
6649 // Update register states
6650 reg_state[from->value()] = reg_writable;
6651 reg_state[to->value()] = reg_written;
6652 return true;
6653 }
6654
6655 // Calculate the extra stack space required for packing or unpacking inline
6656 // args and adjust the stack pointer
6657 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6658 // Two additional slots to account for return address
6659 int sp_inc = (args_on_stack + 2) * VMRegImpl::stack_slot_size;
6660 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6661 // Save the return address, adjust the stack (make sure it is properly
6662 // 16-byte aligned) and copy the return address to the new top of the stack.
6663 // The stack will be repaired on return (see MacroAssembler::remove_frame).
6664 assert(sp_inc > 0, "sanity");
6665 pop(r13);
6666 subptr(rsp, sp_inc);
6667 push(r13);
6668 return sp_inc;
6669 }
6670
6671 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
6672 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6673 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6674 RegState reg_state[]) {
6675 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6676 assert(from->is_valid(), "source must be valid");
6677 bool progress = false;
6678 #ifdef ASSERT
6679 const int start_offset = offset();
6680 #endif
6681
6682 Label L_null, L_notNull;
6683 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6684 Register tmp1 = r10;
6685 Register tmp2 = r13;
6686 Register fromReg = noreg;
6687 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
6688 bool done = true;
6689 bool mark_done = true;
6690 VMReg toReg;
6691 BasicType bt;
6692 // Check if argument requires a null check
6693 bool null_check = false;
6694 VMReg nullCheckReg;
6695 while (stream.next(nullCheckReg, bt)) {
6696 if (sig->at(stream.sig_index())._offset == -1) {
6697 null_check = true;
6698 break;
6699 }
6700 }
6701 stream.reset(sig_index, to_index);
6702 while (stream.next(toReg, bt)) {
6703 assert(toReg->is_valid(), "destination must be valid");
6704 int idx = (int)toReg->value();
6705 if (reg_state[idx] == reg_readonly) {
6706 if (idx != from->value()) {
6707 mark_done = false;
6708 }
6709 done = false;
6710 continue;
6711 } else if (reg_state[idx] == reg_written) {
6712 continue;
6713 }
6714 assert(reg_state[idx] == reg_writable, "must be writable");
6715 reg_state[idx] = reg_written;
6716 progress = true;
6717
6718 if (fromReg == noreg) {
6719 if (from->is_reg()) {
6720 fromReg = from->as_Register();
6721 } else {
6722 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6723 movq(tmp1, Address(rsp, st_off));
6724 fromReg = tmp1;
6725 }
6726 if (null_check) {
6727 // Nullable inline type argument, emit null check
6728 testptr(fromReg, fromReg);
6729 jcc(Assembler::zero, L_null);
6730 }
6731 }
6732 int off = sig->at(stream.sig_index())._offset;
6733 if (off == -1) {
6734 assert(null_check, "Missing null check at");
6735 if (toReg->is_stack()) {
6736 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6737 movq(Address(rsp, st_off), 1);
6738 } else {
6739 movq(toReg->as_Register(), 1);
6740 }
6741 continue;
6742 }
6743 assert(off > 0, "offset in object should be positive");
6744 Address fromAddr = Address(fromReg, off);
6745 if (!toReg->is_XMMRegister()) {
6746 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
6747 if (is_reference_type(bt)) {
6748 load_heap_oop(dst, fromAddr);
6749 } else {
6750 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
6751 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
6752 }
6753 if (toReg->is_stack()) {
6754 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6755 movq(Address(rsp, st_off), dst);
6756 }
6757 } else if (bt == T_DOUBLE) {
6758 movdbl(toReg->as_XMMRegister(), fromAddr);
6759 } else {
6760 assert(bt == T_FLOAT, "must be float");
6761 movflt(toReg->as_XMMRegister(), fromAddr);
6762 }
6763 }
6764 if (progress && null_check) {
6765 if (done) {
6766 jmp(L_notNull);
6767 bind(L_null);
6768 // Set IsInit field to zero to signal that the argument is null.
6769 // Also set all oop fields to zero to make the GC happy.
6770 stream.reset(sig_index, to_index);
6771 while (stream.next(toReg, bt)) {
6772 if (sig->at(stream.sig_index())._offset == -1 ||
6773 bt == T_OBJECT || bt == T_ARRAY) {
6774 if (toReg->is_stack()) {
6775 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6776 movq(Address(rsp, st_off), 0);
6777 } else {
6778 xorq(toReg->as_Register(), toReg->as_Register());
6779 }
6780 }
6781 }
6782 bind(L_notNull);
6783 } else {
6784 bind(L_null);
6785 }
6786 }
6787
6788 sig_index = stream.sig_index();
6789 to_index = stream.regs_index();
6790
6791 if (mark_done && reg_state[from->value()] != reg_written) {
6792 // This is okay because no one else will write to that slot
6793 reg_state[from->value()] = reg_writable;
6794 }
6795 from_index--;
6796 assert(progress || (start_offset == offset()), "should not emit code");
6797 return done;
6798 }
6799
6800 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
6801 VMRegPair* from, int from_count, int& from_index, VMReg to,
6802 RegState reg_state[], Register val_array) {
6803 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
6804 assert(to->is_valid(), "destination must be valid");
6805
6806 if (reg_state[to->value()] == reg_written) {
6807 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6808 return true; // Already written
6809 }
6810
6811 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
6812 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
6813 Register val_obj_tmp = r11;
6814 Register from_reg_tmp = r14;
6815 Register tmp1 = r10;
6816 Register tmp2 = r13;
6817 Register tmp3 = rbx;
6818 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
6819
6820 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
6821
6822 if (reg_state[to->value()] == reg_readonly) {
6823 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
6824 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
6825 return false; // Not yet writable
6826 }
6827 val_obj = val_obj_tmp;
6828 }
6829
6830 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
6831 load_heap_oop(val_obj, Address(val_array, index));
6832
6833 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
6834 VMReg fromReg;
6835 BasicType bt;
6836 Label L_null;
6837 while (stream.next(fromReg, bt)) {
6838 assert(fromReg->is_valid(), "source must be valid");
6839 reg_state[fromReg->value()] = reg_writable;
6840
6841 int off = sig->at(stream.sig_index())._offset;
6842 if (off == -1) {
6843 // Nullable inline type argument, emit null check
6844 Label L_notNull;
6845 if (fromReg->is_stack()) {
6846 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6847 testb(Address(rsp, ld_off), 1);
6848 } else {
6849 testb(fromReg->as_Register(), 1);
6850 }
6851 jcc(Assembler::notZero, L_notNull);
6852 movptr(val_obj, 0);
6853 jmp(L_null);
6854 bind(L_notNull);
6855 continue;
6856 }
6857
6858 assert(off > 0, "offset in object should be positive");
6859 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
6860
6861 Address dst(val_obj, off);
6862 if (!fromReg->is_XMMRegister()) {
6863 Register src;
6864 if (fromReg->is_stack()) {
6865 src = from_reg_tmp;
6866 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6867 load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
6868 } else {
6869 src = fromReg->as_Register();
6870 }
6871 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
6872 if (is_reference_type(bt)) {
6873 store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
6874 } else {
6875 store_sized_value(dst, src, size_in_bytes);
6876 }
6877 } else if (bt == T_DOUBLE) {
6878 movdbl(dst, fromReg->as_XMMRegister());
6879 } else {
6880 assert(bt == T_FLOAT, "must be float");
6881 movflt(dst, fromReg->as_XMMRegister());
6882 }
6883 }
6884 bind(L_null);
6885 sig_index = stream.sig_index();
6886 from_index = stream.regs_index();
6887
6888 assert(reg_state[to->value()] == reg_writable, "must have already been read");
6889 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
6890 assert(success, "to register must be writeable");
6891 return true;
6892 }
6893
6894 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
6895 return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
6896 }
6897
6898 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
6899 assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
6900 if (needs_stack_repair) {
6901 movq(rbp, Address(rsp, initial_framesize));
6902 // The stack increment resides just below the saved rbp
6903 addq(rsp, Address(rsp, initial_framesize - wordSize));
6904 } else {
6905 if (initial_framesize > 0) {
6906 addq(rsp, initial_framesize);
6907 }
6908 pop(rbp);
6909 }
6910 }
6911
6912 // Clearing constant sized memory using YMM/ZMM registers.
6913 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6914 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6915 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6916
6917 int vector64_count = (cnt & (~0x7)) >> 3;
6918 cnt = cnt & 0x7;
6919 const int fill64_per_loop = 4;
6920 const int max_unrolled_fill64 = 8;
6921
6922 // 64 byte initialization loop.
6923 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6924 int start64 = 0;
6925 if (vector64_count > max_unrolled_fill64) {
6926 Label LOOP;
6927 Register index = rtmp;
6928
6929 start64 = vector64_count - (vector64_count % fill64_per_loop);
6930
6931 movl(index, 0);
6981 break;
6982 case 7:
6983 if (use64byteVector) {
6984 movl(rtmp, 0x7F);
6985 kmovwl(mask, rtmp);
6986 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6987 } else {
6988 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6989 movl(rtmp, 0x7);
6990 kmovwl(mask, rtmp);
6991 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6992 }
6993 break;
6994 default:
6995 fatal("Unexpected length : %d\n",cnt);
6996 break;
6997 }
6998 }
6999 }
7000
7001 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
7002 bool is_large, bool word_copy_only, KRegister mask) {
7003 // cnt - number of qwords (8-byte words).
7004 // base - start address, qword aligned.
7005 // is_large - if optimizers know cnt is larger than InitArrayShortSize
7006 assert(base==rdi, "base register must be edi for rep stos");
7007 assert(val==rax, "val register must be eax for rep stos");
7008 assert(cnt==rcx, "cnt register must be ecx for rep stos");
7009 assert(InitArrayShortSize % BytesPerLong == 0,
7010 "InitArrayShortSize should be the multiple of BytesPerLong");
7011
7012 Label DONE;
7013
7014 if (!is_large) {
7015 Label LOOP, LONG;
7016 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7017 jccb(Assembler::greater, LONG);
7018
7019 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7020
7021 decrement(cnt);
7022 jccb(Assembler::negative, DONE); // Zero length
7023
7024 // Use individual pointer-sized stores for small counts:
7025 BIND(LOOP);
7026 movptr(Address(base, cnt, Address::times_ptr), val);
7027 decrement(cnt);
7028 jccb(Assembler::greaterEqual, LOOP);
7029 jmpb(DONE);
7030
7031 BIND(LONG);
7032 }
7033
7034 // Use longer rep-prefixed ops for non-small counts:
7035 if (UseFastStosb && !word_copy_only) {
7036 shlptr(cnt, 3); // convert to number of bytes
7037 rep_stosb();
7038 } else if (UseXMMForObjInit) {
7039 xmm_clear_mem(base, cnt, val, xtmp, mask);
7040 } else {
7041 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7042 rep_stos();
7043 }
7044
7045 BIND(DONE);
7046 }
7047
7048 #endif //COMPILER2_OR_JVMCI
7049
7050
7051 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7052 Register to, Register value, Register count,
7053 Register rtmp, XMMRegister xtmp) {
7054 ShortBranchVerifier sbv(this);
7055 assert_different_registers(to, value, count, rtmp);
7056 Label L_exit;
7057 Label L_fill_2_bytes, L_fill_4_bytes;
7058
7059 #if defined(COMPILER2) && defined(_LP64)
11074
11075 // Load top.
11076 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
11077
11078 // Check if the lock-stack is full.
11079 cmpl(top, LockStack::end_offset());
11080 jcc(Assembler::greaterEqual, slow);
11081
11082 // Check for recursion.
11083 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
11084 jcc(Assembler::equal, push);
11085
11086 // Check header for monitor (0b10).
11087 testptr(reg_rax, markWord::monitor_value);
11088 jcc(Assembler::notZero, slow);
11089
11090 // Try to lock. Transition lock bits 0b01 => 0b00
11091 movptr(tmp, reg_rax);
11092 andptr(tmp, ~(int32_t)markWord::unlocked_value);
11093 orptr(reg_rax, markWord::unlocked_value);
11094 if (EnableValhalla) {
11095 // Mask inline_type bit such that we go to the slow path if object is an inline type
11096 andptr(reg_rax, ~((int) markWord::inline_type_bit_in_place));
11097 }
11098 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
11099 jcc(Assembler::notEqual, slow);
11100
11101 // Restore top, CAS clobbers register.
11102 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
11103
11104 bind(push);
11105 // After successful lock, push object on lock-stack.
11106 movptr(Address(thread, top), obj);
11107 incrementl(top, oopSize);
11108 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
11109 }
11110
11111 // Implements lightweight-unlocking.
11112 //
11113 // obj: the object to be unlocked
11114 // reg_rax: rax
11115 // thread: the thread
11116 // tmp: a temporary register
11117 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
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