1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "crc32c.h"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/barrierSetAssembler.hpp"
34 #include "gc/shared/collectedHeap.inline.hpp"
35 #include "gc/shared/tlab_globals.hpp"
36 #include "interpreter/bytecodeHistogram.hpp"
37 #include "interpreter/interpreter.hpp"
38 #include "jvm.h"
39 #include "memory/resourceArea.hpp"
40 #include "memory/universe.hpp"
41 #include "oops/accessDecorators.hpp"
42 #include "oops/compressedKlass.inline.hpp"
43 #include "oops/compressedOops.inline.hpp"
44 #include "oops/klass.inline.hpp"
45 #include "prims/methodHandles.hpp"
46 #include "runtime/continuation.hpp"
47 #include "runtime/interfaceSupport.inline.hpp"
48 #include "runtime/javaThread.hpp"
49 #include "runtime/jniHandles.hpp"
50 #include "runtime/objectMonitor.hpp"
51 #include "runtime/os.hpp"
52 #include "runtime/safepoint.hpp"
53 #include "runtime/safepointMechanism.hpp"
54 #include "runtime/sharedRuntime.hpp"
55 #include "runtime/stubRoutines.hpp"
56 #include "utilities/checkedCast.hpp"
57 #include "utilities/macros.hpp"
58
59 #ifdef PRODUCT
60 #define BLOCK_COMMENT(str) /* nothing */
61 #define STOP(error) stop(error)
62 #else
63 #define BLOCK_COMMENT(str) block_comment(str)
64 #define STOP(error) block_comment(error); stop(error)
65 #endif
66
67 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
68
69 #ifdef ASSERT
70 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
71 #endif
72
73 static const Assembler::Condition reverse[] = {
74 Assembler::noOverflow /* overflow = 0x0 */ ,
75 Assembler::overflow /* noOverflow = 0x1 */ ,
76 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
77 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
1701 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1702 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1703 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1704 pass_arg2(this, arg_2);
1705 pass_arg1(this, arg_1);
1706 pass_arg0(this, arg_0);
1707 call_VM_leaf(entry_point, 3);
1708 }
1709
1710 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1711 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1712 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1713 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1714 pass_arg3(this, arg_3);
1715 pass_arg2(this, arg_2);
1716 pass_arg1(this, arg_1);
1717 pass_arg0(this, arg_0);
1718 call_VM_leaf(entry_point, 3);
1719 }
1720
1721 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1722 pass_arg0(this, arg_0);
1723 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1724 }
1725
1726 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1727 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1728 pass_arg1(this, arg_1);
1729 pass_arg0(this, arg_0);
1730 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1731 }
1732
1733 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1734 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1735 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1736 pass_arg2(this, arg_2);
1737 pass_arg1(this, arg_1);
1738 pass_arg0(this, arg_0);
1739 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1740 }
2885 lea(rscratch, src);
2886 Assembler::mulss(dst, Address(rscratch, 0));
2887 }
2888 }
2889
2890 void MacroAssembler::null_check(Register reg, int offset) {
2891 if (needs_explicit_null_check(offset)) {
2892 // provoke OS null exception if reg is null by
2893 // accessing M[reg] w/o changing any (non-CC) registers
2894 // NOTE: cmpl is plenty here to provoke a segv
2895 cmpptr(rax, Address(reg, 0));
2896 // Note: should probably use testl(rax, Address(reg, 0));
2897 // may be shorter code (however, this version of
2898 // testl needs to be implemented first)
2899 } else {
2900 // nothing to do, (later) access of M[reg + offset]
2901 // will provoke OS null exception if reg is null
2902 }
2903 }
2904
2905 void MacroAssembler::os_breakpoint() {
2906 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2907 // (e.g., MSVC can't call ps() otherwise)
2908 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2909 }
2910
2911 void MacroAssembler::unimplemented(const char* what) {
2912 const char* buf = nullptr;
2913 {
2914 ResourceMark rm;
2915 stringStream ss;
2916 ss.print("unimplemented: %s", what);
2917 buf = code_string(ss.as_string());
2918 }
2919 stop(buf);
2920 }
2921
2922 #ifdef _LP64
2923 #define XSTATE_BV 0x200
2924 #endif
4060 }
4061
4062 // C++ bool manipulation
4063 void MacroAssembler::testbool(Register dst) {
4064 if(sizeof(bool) == 1)
4065 testb(dst, 0xff);
4066 else if(sizeof(bool) == 2) {
4067 // testw implementation needed for two byte bools
4068 ShouldNotReachHere();
4069 } else if(sizeof(bool) == 4)
4070 testl(dst, dst);
4071 else
4072 // unsupported
4073 ShouldNotReachHere();
4074 }
4075
4076 void MacroAssembler::testptr(Register dst, Register src) {
4077 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4078 }
4079
4080 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4081 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4082 Register var_size_in_bytes,
4083 int con_size_in_bytes,
4084 Register t1,
4085 Register t2,
4086 Label& slow_case) {
4087 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4088 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4089 }
4090
4091 RegSet MacroAssembler::call_clobbered_gp_registers() {
4092 RegSet regs;
4093 #ifdef _LP64
4094 regs += RegSet::of(rax, rcx, rdx);
4095 #ifndef WINDOWS
4096 regs += RegSet::of(rsi, rdi);
4097 #endif
4098 regs += RegSet::range(r8, r11);
4099 #else
4318 // clear topmost word (no jump would be needed if conditional assignment worked here)
4319 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4320 // index could be 0 now, must check again
4321 jcc(Assembler::zero, done);
4322 bind(even);
4323 }
4324 #endif // !_LP64
4325 // initialize remaining object fields: index is a multiple of 2 now
4326 {
4327 Label loop;
4328 bind(loop);
4329 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4330 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4331 decrement(index);
4332 jcc(Assembler::notZero, loop);
4333 }
4334
4335 bind(done);
4336 }
4337
4338 // Look up the method for a megamorphic invokeinterface call.
4339 // The target method is determined by <intf_klass, itable_index>.
4340 // The receiver klass is in recv_klass.
4341 // On success, the result will be in method_result, and execution falls through.
4342 // On failure, execution transfers to the given label.
4343 void MacroAssembler::lookup_interface_method(Register recv_klass,
4344 Register intf_klass,
4345 RegisterOrConstant itable_index,
4346 Register method_result,
4347 Register scan_temp,
4348 Label& L_no_such_interface,
4349 bool return_method) {
4350 assert_different_registers(recv_klass, intf_klass, scan_temp);
4351 assert_different_registers(method_result, intf_klass, scan_temp);
4352 assert(recv_klass != method_result || !return_method,
4353 "recv_klass can be destroyed when method isn't needed");
4354
4355 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4356 "caller must use same register for non-constant itable index as for method");
4357
5382 } else {
5383 Label L;
5384 jccb(negate_condition(cc), L);
5385 movl(dst, src);
5386 bind(L);
5387 }
5388 }
5389
5390 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5391 if (VM_Version::supports_cmov()) {
5392 cmovl(cc, dst, src);
5393 } else {
5394 Label L;
5395 jccb(negate_condition(cc), L);
5396 movl(dst, src);
5397 bind(L);
5398 }
5399 }
5400
5401 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5402 if (!VerifyOops) return;
5403
5404 BLOCK_COMMENT("verify_oop {");
5405 #ifdef _LP64
5406 push(rscratch1);
5407 #endif
5408 push(rax); // save rax
5409 push(reg); // pass register argument
5410
5411 // Pass register number to verify_oop_subroutine
5412 const char* b = nullptr;
5413 {
5414 ResourceMark rm;
5415 stringStream ss;
5416 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5417 b = code_string(ss.as_string());
5418 }
5419 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5420 pushptr(buffer.addr(), rscratch1);
5421
5422 // call indirectly to solve generation ordering problem
5444 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5445 int stackElementSize = Interpreter::stackElementSize;
5446 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5447 #ifdef ASSERT
5448 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5449 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5450 #endif
5451 Register scale_reg = noreg;
5452 Address::ScaleFactor scale_factor = Address::no_scale;
5453 if (arg_slot.is_constant()) {
5454 offset += arg_slot.as_constant() * stackElementSize;
5455 } else {
5456 scale_reg = arg_slot.as_register();
5457 scale_factor = Address::times(stackElementSize);
5458 }
5459 offset += wordSize; // return PC is on stack
5460 return Address(rsp, scale_reg, scale_factor, offset);
5461 }
5462
5463 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5464 if (!VerifyOops) return;
5465
5466 #ifdef _LP64
5467 push(rscratch1);
5468 #endif
5469 push(rax); // save rax,
5470 // addr may contain rsp so we will have to adjust it based on the push
5471 // we just did (and on 64 bit we do two pushes)
5472 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5473 // stores rax into addr which is backwards of what was intended.
5474 if (addr.uses(rsp)) {
5475 lea(rax, addr);
5476 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5477 } else {
5478 pushptr(addr);
5479 }
5480
5481 // Pass register number to verify_oop_subroutine
5482 const char* b = nullptr;
5483 {
5484 ResourceMark rm;
5931
5932 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5933 // get mirror
5934 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5935 load_method_holder(mirror, method);
5936 movptr(mirror, Address(mirror, mirror_offset));
5937 resolve_oop_handle(mirror, tmp);
5938 }
5939
5940 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5941 load_method_holder(rresult, rmethod);
5942 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5943 }
5944
5945 void MacroAssembler::load_method_holder(Register holder, Register method) {
5946 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5947 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5948 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5949 }
5950
5951 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5952 assert_different_registers(src, tmp);
5953 assert_different_registers(dst, tmp);
5954 #ifdef _LP64
5955 if (UseCompressedClassPointers) {
5956 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5957 decode_klass_not_null(dst, tmp);
5958 } else
5959 #endif
5960 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5961 }
5962
5963 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5964 assert_different_registers(src, tmp);
5965 assert_different_registers(dst, tmp);
5966 #ifdef _LP64
5967 if (UseCompressedClassPointers) {
5968 encode_klass_not_null(src, tmp);
5969 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5970 } else
5971 #endif
5972 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5973 }
5974
5975 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5976 Register tmp1, Register thread_tmp) {
5977 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5978 decorators = AccessInternal::decorator_fixup(decorators, type);
5979 bool as_raw = (decorators & AS_RAW) != 0;
5980 if (as_raw) {
5981 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5982 } else {
5983 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5984 }
5985 }
5986
5987 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5988 Register tmp1, Register tmp2, Register tmp3) {
5989 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5990 decorators = AccessInternal::decorator_fixup(decorators, type);
5991 bool as_raw = (decorators & AS_RAW) != 0;
5992 if (as_raw) {
5993 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5994 } else {
5995 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5996 }
5997 }
5998
5999 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6000 Register thread_tmp, DecoratorSet decorators) {
6001 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6002 }
6003
6004 // Doesn't do verification, generates fixed size code
6005 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6006 Register thread_tmp, DecoratorSet decorators) {
6007 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6008 }
6009
6010 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
6011 Register tmp2, Register tmp3, DecoratorSet decorators) {
6012 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
6013 }
6014
6015 // Used for storing nulls.
6016 void MacroAssembler::store_heap_oop_null(Address dst) {
6017 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
6018 }
6318
6319 void MacroAssembler::reinit_heapbase() {
6320 if (UseCompressedOops) {
6321 if (Universe::heap() != nullptr) {
6322 if (CompressedOops::base() == nullptr) {
6323 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6324 } else {
6325 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6326 }
6327 } else {
6328 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6329 }
6330 }
6331 }
6332
6333 #endif // _LP64
6334
6335 #if COMPILER2_OR_JVMCI
6336
6337 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6338 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6339 // cnt - number of qwords (8-byte words).
6340 // base - start address, qword aligned.
6341 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6342 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6343 if (use64byteVector) {
6344 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
6345 } else if (MaxVectorSize >= 32) {
6346 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6347 } else {
6348 pxor(xtmp, xtmp);
6349 }
6350 jmp(L_zero_64_bytes);
6351
6352 BIND(L_loop);
6353 if (MaxVectorSize >= 32) {
6354 fill64(base, 0, xtmp, use64byteVector);
6355 } else {
6356 movdqu(Address(base, 0), xtmp);
6357 movdqu(Address(base, 16), xtmp);
6358 movdqu(Address(base, 32), xtmp);
6359 movdqu(Address(base, 48), xtmp);
6360 }
6361 addptr(base, 64);
6362
6363 BIND(L_zero_64_bytes);
6364 subptr(cnt, 8);
6365 jccb(Assembler::greaterEqual, L_loop);
6366
6367 // Copy trailing 64 bytes
6368 if (use64byteVector) {
6369 addptr(cnt, 8);
6370 jccb(Assembler::equal, L_end);
6371 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
6372 jmp(L_end);
6373 } else {
6374 addptr(cnt, 4);
6375 jccb(Assembler::less, L_tail);
6376 if (MaxVectorSize >= 32) {
6377 vmovdqu(Address(base, 0), xtmp);
6378 } else {
6379 movdqu(Address(base, 0), xtmp);
6380 movdqu(Address(base, 16), xtmp);
6381 }
6382 }
6383 addptr(base, 32);
6384 subptr(cnt, 4);
6385
6386 BIND(L_tail);
6387 addptr(cnt, 4);
6388 jccb(Assembler::lessEqual, L_end);
6389 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6390 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
6391 } else {
6392 decrement(cnt);
6393
6394 BIND(L_sloop);
6395 movq(Address(base, 0), xtmp);
6396 addptr(base, 8);
6397 decrement(cnt);
6398 jccb(Assembler::greaterEqual, L_sloop);
6399 }
6400 BIND(L_end);
6401 }
6402
6403 // Clearing constant sized memory using YMM/ZMM registers.
6404 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6405 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6406 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6407
6408 int vector64_count = (cnt & (~0x7)) >> 3;
6409 cnt = cnt & 0x7;
6410 const int fill64_per_loop = 4;
6411 const int max_unrolled_fill64 = 8;
6412
6413 // 64 byte initialization loop.
6414 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6415 int start64 = 0;
6416 if (vector64_count > max_unrolled_fill64) {
6417 Label LOOP;
6418 Register index = rtmp;
6419
6420 start64 = vector64_count - (vector64_count % fill64_per_loop);
6421
6422 movl(index, 0);
6472 break;
6473 case 7:
6474 if (use64byteVector) {
6475 movl(rtmp, 0x7F);
6476 kmovwl(mask, rtmp);
6477 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6478 } else {
6479 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6480 movl(rtmp, 0x7);
6481 kmovwl(mask, rtmp);
6482 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6483 }
6484 break;
6485 default:
6486 fatal("Unexpected length : %d\n",cnt);
6487 break;
6488 }
6489 }
6490 }
6491
6492 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
6493 bool is_large, KRegister mask) {
6494 // cnt - number of qwords (8-byte words).
6495 // base - start address, qword aligned.
6496 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6497 assert(base==rdi, "base register must be edi for rep stos");
6498 assert(tmp==rax, "tmp register must be eax for rep stos");
6499 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6500 assert(InitArrayShortSize % BytesPerLong == 0,
6501 "InitArrayShortSize should be the multiple of BytesPerLong");
6502
6503 Label DONE;
6504 if (!is_large || !UseXMMForObjInit) {
6505 xorptr(tmp, tmp);
6506 }
6507
6508 if (!is_large) {
6509 Label LOOP, LONG;
6510 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6511 jccb(Assembler::greater, LONG);
6512
6513 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6514
6515 decrement(cnt);
6516 jccb(Assembler::negative, DONE); // Zero length
6517
6518 // Use individual pointer-sized stores for small counts:
6519 BIND(LOOP);
6520 movptr(Address(base, cnt, Address::times_ptr), tmp);
6521 decrement(cnt);
6522 jccb(Assembler::greaterEqual, LOOP);
6523 jmpb(DONE);
6524
6525 BIND(LONG);
6526 }
6527
6528 // Use longer rep-prefixed ops for non-small counts:
6529 if (UseFastStosb) {
6530 shlptr(cnt, 3); // convert to number of bytes
6531 rep_stosb();
6532 } else if (UseXMMForObjInit) {
6533 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6534 } else {
6535 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6536 rep_stos();
6537 }
6538
6539 BIND(DONE);
6540 }
6541
6542 #endif //COMPILER2_OR_JVMCI
6543
6544
6545 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6546 Register to, Register value, Register count,
6547 Register rtmp, XMMRegister xtmp) {
6548 ShortBranchVerifier sbv(this);
6549 assert_different_registers(to, value, count, rtmp);
6550 Label L_exit;
6551 Label L_fill_2_bytes, L_fill_4_bytes;
6552
6553 #if defined(COMPILER2) && defined(_LP64)
10641
10642 // Load top.
10643 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10644
10645 // Check if the lock-stack is full.
10646 cmpl(top, LockStack::end_offset());
10647 jcc(Assembler::greaterEqual, slow);
10648
10649 // Check for recursion.
10650 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10651 jcc(Assembler::equal, push);
10652
10653 // Check header for monitor (0b10).
10654 testptr(reg_rax, markWord::monitor_value);
10655 jcc(Assembler::notZero, slow);
10656
10657 // Try to lock. Transition lock bits 0b01 => 0b00
10658 movptr(tmp, reg_rax);
10659 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10660 orptr(reg_rax, markWord::unlocked_value);
10661 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10662 jcc(Assembler::notEqual, slow);
10663
10664 // Restore top, CAS clobbers register.
10665 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10666
10667 bind(push);
10668 // After successful lock, push object on lock-stack.
10669 movptr(Address(thread, top), obj);
10670 incrementl(top, oopSize);
10671 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10672 }
10673
10674 // Implements lightweight-unlocking.
10675 //
10676 // obj: the object to be unlocked
10677 // reg_rax: rax
10678 // thread: the thread
10679 // tmp: a temporary register
10680 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
|
1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "ci/ciInlineKlass.hpp"
32 #include "crc32c.h"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/collectedHeap.inline.hpp"
36 #include "gc/shared/tlab_globals.hpp"
37 #include "interpreter/bytecodeHistogram.hpp"
38 #include "interpreter/interpreter.hpp"
39 #include "jvm.h"
40 #include "memory/resourceArea.hpp"
41 #include "memory/universe.hpp"
42 #include "oops/accessDecorators.hpp"
43 #include "oops/compressedKlass.inline.hpp"
44 #include "oops/compressedOops.inline.hpp"
45 #include "oops/klass.inline.hpp"
46 #include "oops/resolvedFieldEntry.hpp"
47 #include "prims/methodHandles.hpp"
48 #include "runtime/continuation.hpp"
49 #include "runtime/interfaceSupport.inline.hpp"
50 #include "runtime/javaThread.hpp"
51 #include "runtime/jniHandles.hpp"
52 #include "runtime/objectMonitor.hpp"
53 #include "runtime/os.hpp"
54 #include "runtime/safepoint.hpp"
55 #include "runtime/safepointMechanism.hpp"
56 #include "runtime/sharedRuntime.hpp"
57 #include "runtime/signature_cc.hpp"
58 #include "runtime/stubRoutines.hpp"
59 #include "utilities/checkedCast.hpp"
60 #include "utilities/macros.hpp"
61 #include "vmreg_x86.inline.hpp"
62 #ifdef COMPILER2
63 #include "opto/output.hpp"
64 #endif
65
66 #ifdef PRODUCT
67 #define BLOCK_COMMENT(str) /* nothing */
68 #define STOP(error) stop(error)
69 #else
70 #define BLOCK_COMMENT(str) block_comment(str)
71 #define STOP(error) block_comment(error); stop(error)
72 #endif
73
74 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
75
76 #ifdef ASSERT
77 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
78 #endif
79
80 static const Assembler::Condition reverse[] = {
81 Assembler::noOverflow /* overflow = 0x0 */ ,
82 Assembler::overflow /* noOverflow = 0x1 */ ,
83 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
84 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
1708 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1709 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1710 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1711 pass_arg2(this, arg_2);
1712 pass_arg1(this, arg_1);
1713 pass_arg0(this, arg_0);
1714 call_VM_leaf(entry_point, 3);
1715 }
1716
1717 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1718 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1719 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1720 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1721 pass_arg3(this, arg_3);
1722 pass_arg2(this, arg_2);
1723 pass_arg1(this, arg_1);
1724 pass_arg0(this, arg_0);
1725 call_VM_leaf(entry_point, 3);
1726 }
1727
1728 void MacroAssembler::super_call_VM_leaf(address entry_point) {
1729 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1730 }
1731
1732 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1733 pass_arg0(this, arg_0);
1734 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1735 }
1736
1737 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1738 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1739 pass_arg1(this, arg_1);
1740 pass_arg0(this, arg_0);
1741 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1742 }
1743
1744 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1745 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1746 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1747 pass_arg2(this, arg_2);
1748 pass_arg1(this, arg_1);
1749 pass_arg0(this, arg_0);
1750 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1751 }
2896 lea(rscratch, src);
2897 Assembler::mulss(dst, Address(rscratch, 0));
2898 }
2899 }
2900
2901 void MacroAssembler::null_check(Register reg, int offset) {
2902 if (needs_explicit_null_check(offset)) {
2903 // provoke OS null exception if reg is null by
2904 // accessing M[reg] w/o changing any (non-CC) registers
2905 // NOTE: cmpl is plenty here to provoke a segv
2906 cmpptr(rax, Address(reg, 0));
2907 // Note: should probably use testl(rax, Address(reg, 0));
2908 // may be shorter code (however, this version of
2909 // testl needs to be implemented first)
2910 } else {
2911 // nothing to do, (later) access of M[reg + offset]
2912 // will provoke OS null exception if reg is null
2913 }
2914 }
2915
2916 void MacroAssembler::test_markword_is_inline_type(Register markword, Label& is_inline_type) {
2917 andptr(markword, markWord::inline_type_mask_in_place);
2918 cmpptr(markword, markWord::inline_type_pattern);
2919 jcc(Assembler::equal, is_inline_type);
2920 }
2921
2922 void MacroAssembler::test_klass_is_inline_type(Register klass, Register temp_reg, Label& is_inline_type) {
2923 movl(temp_reg, Address(klass, Klass::access_flags_offset()));
2924 testl(temp_reg, JVM_ACC_IDENTITY);
2925 jcc(Assembler::zero, is_inline_type);
2926 }
2927
2928 void MacroAssembler::test_oop_is_not_inline_type(Register object, Register tmp, Label& not_inline_type) {
2929 testptr(object, object);
2930 jcc(Assembler::zero, not_inline_type);
2931 const int is_inline_type_mask = markWord::inline_type_pattern;
2932 movptr(tmp, Address(object, oopDesc::mark_offset_in_bytes()));
2933 andptr(tmp, is_inline_type_mask);
2934 cmpptr(tmp, is_inline_type_mask);
2935 jcc(Assembler::notEqual, not_inline_type);
2936 }
2937
2938 void MacroAssembler::test_klass_is_empty_inline_type(Register klass, Register temp_reg, Label& is_empty_inline_type) {
2939 #ifdef ASSERT
2940 {
2941 Label done_check;
2942 test_klass_is_inline_type(klass, temp_reg, done_check);
2943 stop("test_klass_is_empty_inline_type with non inline type klass");
2944 bind(done_check);
2945 }
2946 #endif
2947 movl(temp_reg, Address(klass, InstanceKlass::misc_flags_offset()));
2948 testl(temp_reg, InstanceKlassFlags::is_empty_inline_type_value());
2949 jcc(Assembler::notZero, is_empty_inline_type);
2950 }
2951
2952 void MacroAssembler::test_field_is_null_free_inline_type(Register flags, Register temp_reg, Label& is_null_free_inline_type) {
2953 movl(temp_reg, flags);
2954 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2955 jcc(Assembler::notEqual, is_null_free_inline_type);
2956 }
2957
2958 void MacroAssembler::test_field_is_not_null_free_inline_type(Register flags, Register temp_reg, Label& not_null_free_inline_type) {
2959 movl(temp_reg, flags);
2960 testl(temp_reg, 1 << ResolvedFieldEntry::is_null_free_inline_type_shift);
2961 jcc(Assembler::equal, not_null_free_inline_type);
2962 }
2963
2964 void MacroAssembler::test_field_is_flat(Register flags, Register temp_reg, Label& is_flat) {
2965 movl(temp_reg, flags);
2966 testl(temp_reg, 1 << ResolvedFieldEntry::is_flat_shift);
2967 jcc(Assembler::notEqual, is_flat);
2968 }
2969
2970 void MacroAssembler::test_field_has_null_marker(Register flags, Register temp_reg, Label& has_null_marker) {
2971 movl(temp_reg, flags);
2972 testl(temp_reg, 1 << ResolvedFieldEntry::has_null_marker_shift);
2973 jcc(Assembler::notEqual, has_null_marker);
2974 }
2975
2976 void MacroAssembler::test_oop_prototype_bit(Register oop, Register temp_reg, int32_t test_bit, bool jmp_set, Label& jmp_label) {
2977 Label test_mark_word;
2978 // load mark word
2979 movptr(temp_reg, Address(oop, oopDesc::mark_offset_in_bytes()));
2980 // check displaced
2981 testl(temp_reg, markWord::unlocked_value);
2982 jccb(Assembler::notZero, test_mark_word);
2983 // slow path use klass prototype
2984 push(rscratch1);
2985 load_prototype_header(temp_reg, oop, rscratch1);
2986 pop(rscratch1);
2987
2988 bind(test_mark_word);
2989 testl(temp_reg, test_bit);
2990 jcc((jmp_set) ? Assembler::notZero : Assembler::zero, jmp_label);
2991 }
2992
2993 void MacroAssembler::test_flat_array_oop(Register oop, Register temp_reg,
2994 Label& is_flat_array) {
2995 #ifdef _LP64
2996 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, true, is_flat_array);
2997 #else
2998 load_klass(temp_reg, oop, noreg);
2999 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
3000 test_flat_array_layout(temp_reg, is_flat_array);
3001 #endif
3002 }
3003
3004 void MacroAssembler::test_non_flat_array_oop(Register oop, Register temp_reg,
3005 Label& is_non_flat_array) {
3006 #ifdef _LP64
3007 test_oop_prototype_bit(oop, temp_reg, markWord::flat_array_bit_in_place, false, is_non_flat_array);
3008 #else
3009 load_klass(temp_reg, oop, noreg);
3010 movl(temp_reg, Address(temp_reg, Klass::layout_helper_offset()));
3011 test_non_flat_array_layout(temp_reg, is_non_flat_array);
3012 #endif
3013 }
3014
3015 void MacroAssembler::test_null_free_array_oop(Register oop, Register temp_reg, Label&is_null_free_array) {
3016 #ifdef _LP64
3017 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, true, is_null_free_array);
3018 #else
3019 Unimplemented();
3020 #endif
3021 }
3022
3023 void MacroAssembler::test_non_null_free_array_oop(Register oop, Register temp_reg, Label&is_non_null_free_array) {
3024 #ifdef _LP64
3025 test_oop_prototype_bit(oop, temp_reg, markWord::null_free_array_bit_in_place, false, is_non_null_free_array);
3026 #else
3027 Unimplemented();
3028 #endif
3029 }
3030
3031 void MacroAssembler::test_flat_array_layout(Register lh, Label& is_flat_array) {
3032 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
3033 jcc(Assembler::notZero, is_flat_array);
3034 }
3035
3036 void MacroAssembler::test_non_flat_array_layout(Register lh, Label& is_non_flat_array) {
3037 testl(lh, Klass::_lh_array_tag_flat_value_bit_inplace);
3038 jcc(Assembler::zero, is_non_flat_array);
3039 }
3040
3041 void MacroAssembler::os_breakpoint() {
3042 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3043 // (e.g., MSVC can't call ps() otherwise)
3044 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3045 }
3046
3047 void MacroAssembler::unimplemented(const char* what) {
3048 const char* buf = nullptr;
3049 {
3050 ResourceMark rm;
3051 stringStream ss;
3052 ss.print("unimplemented: %s", what);
3053 buf = code_string(ss.as_string());
3054 }
3055 stop(buf);
3056 }
3057
3058 #ifdef _LP64
3059 #define XSTATE_BV 0x200
3060 #endif
4196 }
4197
4198 // C++ bool manipulation
4199 void MacroAssembler::testbool(Register dst) {
4200 if(sizeof(bool) == 1)
4201 testb(dst, 0xff);
4202 else if(sizeof(bool) == 2) {
4203 // testw implementation needed for two byte bools
4204 ShouldNotReachHere();
4205 } else if(sizeof(bool) == 4)
4206 testl(dst, dst);
4207 else
4208 // unsupported
4209 ShouldNotReachHere();
4210 }
4211
4212 void MacroAssembler::testptr(Register dst, Register src) {
4213 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4214 }
4215
4216 // Object / value buffer allocation...
4217 //
4218 // Kills klass and rsi on LP64
4219 void MacroAssembler::allocate_instance(Register klass, Register new_obj,
4220 Register t1, Register t2,
4221 bool clear_fields, Label& alloc_failed)
4222 {
4223 Label done, initialize_header, initialize_object, slow_case, slow_case_no_pop;
4224 Register layout_size = t1;
4225 assert(new_obj == rax, "needs to be rax");
4226 assert_different_registers(klass, new_obj, t1, t2);
4227
4228 // get instance_size in InstanceKlass (scaled to a count of bytes)
4229 movl(layout_size, Address(klass, Klass::layout_helper_offset()));
4230 // test to see if it is malformed in some way
4231 testl(layout_size, Klass::_lh_instance_slow_path_bit);
4232 jcc(Assembler::notZero, slow_case_no_pop);
4233
4234 // Allocate the instance:
4235 // If TLAB is enabled:
4236 // Try to allocate in the TLAB.
4237 // If fails, go to the slow path.
4238 // Else If inline contiguous allocations are enabled:
4239 // Try to allocate in eden.
4240 // If fails due to heap end, go to slow path.
4241 //
4242 // If TLAB is enabled OR inline contiguous is enabled:
4243 // Initialize the allocation.
4244 // Exit.
4245 //
4246 // Go to slow path.
4247
4248 push(klass);
4249 const Register thread = LP64_ONLY(r15_thread) NOT_LP64(klass);
4250 #ifndef _LP64
4251 if (UseTLAB) {
4252 get_thread(thread);
4253 }
4254 #endif // _LP64
4255
4256 if (UseTLAB) {
4257 tlab_allocate(thread, new_obj, layout_size, 0, klass, t2, slow_case);
4258 if (ZeroTLAB || (!clear_fields)) {
4259 // the fields have been already cleared
4260 jmp(initialize_header);
4261 } else {
4262 // initialize both the header and fields
4263 jmp(initialize_object);
4264 }
4265 } else {
4266 jmp(slow_case);
4267 }
4268
4269 // If UseTLAB is true, the object is created above and there is an initialize need.
4270 // Otherwise, skip and go to the slow path.
4271 if (UseTLAB) {
4272 if (clear_fields) {
4273 // The object is initialized before the header. If the object size is
4274 // zero, go directly to the header initialization.
4275 bind(initialize_object);
4276 decrement(layout_size, sizeof(oopDesc));
4277 jcc(Assembler::zero, initialize_header);
4278
4279 // Initialize topmost object field, divide size by 8, check if odd and
4280 // test if zero.
4281 Register zero = klass;
4282 xorl(zero, zero); // use zero reg to clear memory (shorter code)
4283 shrl(layout_size, LogBytesPerLong); // divide by 2*oopSize and set carry flag if odd
4284
4285 #ifdef ASSERT
4286 // make sure instance_size was multiple of 8
4287 Label L;
4288 // Ignore partial flag stall after shrl() since it is debug VM
4289 jcc(Assembler::carryClear, L);
4290 stop("object size is not multiple of 2 - adjust this code");
4291 bind(L);
4292 // must be > 0, no extra check needed here
4293 #endif
4294
4295 // initialize remaining object fields: instance_size was a multiple of 8
4296 {
4297 Label loop;
4298 bind(loop);
4299 movptr(Address(new_obj, layout_size, Address::times_8, sizeof(oopDesc) - 1*oopSize), zero);
4300 NOT_LP64(movptr(Address(new_obj, layout_size, Address::times_8, sizeof(oopDesc) - 2*oopSize), zero));
4301 decrement(layout_size);
4302 jcc(Assembler::notZero, loop);
4303 }
4304 } // clear_fields
4305
4306 // initialize object header only.
4307 bind(initialize_header);
4308 pop(klass);
4309 Register mark_word = t2;
4310 movptr(mark_word, Address(klass, Klass::prototype_header_offset()));
4311 movptr(Address(new_obj, oopDesc::mark_offset_in_bytes ()), mark_word);
4312 #ifdef _LP64
4313 xorl(rsi, rsi); // use zero reg to clear memory (shorter code)
4314 store_klass_gap(new_obj, rsi); // zero klass gap for compressed oops
4315 #endif
4316 movptr(t2, klass); // preserve klass
4317 store_klass(new_obj, t2, rscratch1); // src klass reg is potentially compressed
4318
4319 jmp(done);
4320 }
4321
4322 bind(slow_case);
4323 pop(klass);
4324 bind(slow_case_no_pop);
4325 jmp(alloc_failed);
4326
4327 bind(done);
4328 }
4329
4330 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4331 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4332 Register var_size_in_bytes,
4333 int con_size_in_bytes,
4334 Register t1,
4335 Register t2,
4336 Label& slow_case) {
4337 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4338 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4339 }
4340
4341 RegSet MacroAssembler::call_clobbered_gp_registers() {
4342 RegSet regs;
4343 #ifdef _LP64
4344 regs += RegSet::of(rax, rcx, rdx);
4345 #ifndef WINDOWS
4346 regs += RegSet::of(rsi, rdi);
4347 #endif
4348 regs += RegSet::range(r8, r11);
4349 #else
4568 // clear topmost word (no jump would be needed if conditional assignment worked here)
4569 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4570 // index could be 0 now, must check again
4571 jcc(Assembler::zero, done);
4572 bind(even);
4573 }
4574 #endif // !_LP64
4575 // initialize remaining object fields: index is a multiple of 2 now
4576 {
4577 Label loop;
4578 bind(loop);
4579 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4580 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4581 decrement(index);
4582 jcc(Assembler::notZero, loop);
4583 }
4584
4585 bind(done);
4586 }
4587
4588 void MacroAssembler::get_inline_type_field_klass(Register holder_klass, Register index, Register inline_klass) {
4589 inline_layout_info(holder_klass, index, inline_klass);
4590 movptr(inline_klass, Address(inline_klass, InlineLayoutInfo::klass_offset()));
4591 }
4592
4593 void MacroAssembler::inline_layout_info(Register holder_klass, Register index, Register layout_info) {
4594 movptr(layout_info, Address(holder_klass, InstanceKlass::inline_layout_info_array_offset()));
4595 #ifdef ASSERT
4596 {
4597 Label done;
4598 cmpptr(layout_info, 0);
4599 jcc(Assembler::notEqual, done);
4600 stop("inline_layout_info_array is null");
4601 bind(done);
4602 }
4603 #endif
4604
4605 InlineLayoutInfo array[2];
4606 int size = (char*)&array[1] - (char*)&array[0]; // computing size of array elements
4607 if (is_power_of_2(size)) {
4608 shll(index, log2i_exact(size)); // Scale index by power of 2
4609 } else {
4610 imull(index, index, size); // Scale the index to be the entry index * array_element_size
4611 }
4612 lea(layout_info, Address(layout_info, index, Address::times_1, Array<InlineLayoutInfo>::base_offset_in_bytes()));
4613 }
4614
4615 void MacroAssembler::get_default_value_oop(Register inline_klass, Register temp_reg, Register obj) {
4616 #ifdef ASSERT
4617 {
4618 Label done_check;
4619 test_klass_is_inline_type(inline_klass, temp_reg, done_check);
4620 stop("get_default_value_oop from non inline type klass");
4621 bind(done_check);
4622 }
4623 #endif
4624 Register offset = temp_reg;
4625 // Getting the offset of the pre-allocated default value
4626 movptr(offset, Address(inline_klass, in_bytes(InstanceKlass::adr_inlineklass_fixed_block_offset())));
4627 movl(offset, Address(offset, in_bytes(InlineKlass::default_value_offset_offset())));
4628
4629 // Getting the mirror
4630 movptr(obj, Address(inline_klass, in_bytes(Klass::java_mirror_offset())));
4631 resolve_oop_handle(obj, inline_klass);
4632
4633 // Getting the pre-allocated default value from the mirror
4634 Address field(obj, offset, Address::times_1);
4635 load_heap_oop(obj, field);
4636 }
4637
4638 void MacroAssembler::get_empty_inline_type_oop(Register inline_klass, Register temp_reg, Register obj) {
4639 #ifdef ASSERT
4640 {
4641 Label done_check;
4642 test_klass_is_empty_inline_type(inline_klass, temp_reg, done_check);
4643 stop("get_empty_value from non-empty inline klass");
4644 bind(done_check);
4645 }
4646 #endif
4647 get_default_value_oop(inline_klass, temp_reg, obj);
4648 }
4649
4650
4651 // Look up the method for a megamorphic invokeinterface call.
4652 // The target method is determined by <intf_klass, itable_index>.
4653 // The receiver klass is in recv_klass.
4654 // On success, the result will be in method_result, and execution falls through.
4655 // On failure, execution transfers to the given label.
4656 void MacroAssembler::lookup_interface_method(Register recv_klass,
4657 Register intf_klass,
4658 RegisterOrConstant itable_index,
4659 Register method_result,
4660 Register scan_temp,
4661 Label& L_no_such_interface,
4662 bool return_method) {
4663 assert_different_registers(recv_klass, intf_klass, scan_temp);
4664 assert_different_registers(method_result, intf_klass, scan_temp);
4665 assert(recv_klass != method_result || !return_method,
4666 "recv_klass can be destroyed when method isn't needed");
4667
4668 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4669 "caller must use same register for non-constant itable index as for method");
4670
5695 } else {
5696 Label L;
5697 jccb(negate_condition(cc), L);
5698 movl(dst, src);
5699 bind(L);
5700 }
5701 }
5702
5703 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5704 if (VM_Version::supports_cmov()) {
5705 cmovl(cc, dst, src);
5706 } else {
5707 Label L;
5708 jccb(negate_condition(cc), L);
5709 movl(dst, src);
5710 bind(L);
5711 }
5712 }
5713
5714 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5715 if (!VerifyOops || VerifyAdapterSharing) {
5716 // Below address of the code string confuses VerifyAdapterSharing
5717 // because it may differ between otherwise equivalent adapters.
5718 return;
5719 }
5720
5721 BLOCK_COMMENT("verify_oop {");
5722 #ifdef _LP64
5723 push(rscratch1);
5724 #endif
5725 push(rax); // save rax
5726 push(reg); // pass register argument
5727
5728 // Pass register number to verify_oop_subroutine
5729 const char* b = nullptr;
5730 {
5731 ResourceMark rm;
5732 stringStream ss;
5733 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5734 b = code_string(ss.as_string());
5735 }
5736 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5737 pushptr(buffer.addr(), rscratch1);
5738
5739 // call indirectly to solve generation ordering problem
5761 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5762 int stackElementSize = Interpreter::stackElementSize;
5763 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5764 #ifdef ASSERT
5765 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5766 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5767 #endif
5768 Register scale_reg = noreg;
5769 Address::ScaleFactor scale_factor = Address::no_scale;
5770 if (arg_slot.is_constant()) {
5771 offset += arg_slot.as_constant() * stackElementSize;
5772 } else {
5773 scale_reg = arg_slot.as_register();
5774 scale_factor = Address::times(stackElementSize);
5775 }
5776 offset += wordSize; // return PC is on stack
5777 return Address(rsp, scale_reg, scale_factor, offset);
5778 }
5779
5780 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5781 if (!VerifyOops || VerifyAdapterSharing) {
5782 // Below address of the code string confuses VerifyAdapterSharing
5783 // because it may differ between otherwise equivalent adapters.
5784 return;
5785 }
5786
5787 #ifdef _LP64
5788 push(rscratch1);
5789 #endif
5790 push(rax); // save rax,
5791 // addr may contain rsp so we will have to adjust it based on the push
5792 // we just did (and on 64 bit we do two pushes)
5793 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5794 // stores rax into addr which is backwards of what was intended.
5795 if (addr.uses(rsp)) {
5796 lea(rax, addr);
5797 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5798 } else {
5799 pushptr(addr);
5800 }
5801
5802 // Pass register number to verify_oop_subroutine
5803 const char* b = nullptr;
5804 {
5805 ResourceMark rm;
6252
6253 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
6254 // get mirror
6255 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6256 load_method_holder(mirror, method);
6257 movptr(mirror, Address(mirror, mirror_offset));
6258 resolve_oop_handle(mirror, tmp);
6259 }
6260
6261 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
6262 load_method_holder(rresult, rmethod);
6263 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
6264 }
6265
6266 void MacroAssembler::load_method_holder(Register holder, Register method) {
6267 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
6268 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
6269 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
6270 }
6271
6272 void MacroAssembler::load_metadata(Register dst, Register src) {
6273 if (UseCompressedClassPointers) {
6274 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6275 } else {
6276 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6277 }
6278 }
6279
6280 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
6281 assert_different_registers(src, tmp);
6282 assert_different_registers(dst, tmp);
6283 #ifdef _LP64
6284 if (UseCompressedClassPointers) {
6285 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6286 decode_klass_not_null(dst, tmp);
6287 } else
6288 #endif
6289 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6290 }
6291
6292 void MacroAssembler::load_prototype_header(Register dst, Register src, Register tmp) {
6293 load_klass(dst, src, tmp);
6294 movptr(dst, Address(dst, Klass::prototype_header_offset()));
6295 }
6296
6297 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
6298 assert_different_registers(src, tmp);
6299 assert_different_registers(dst, tmp);
6300 #ifdef _LP64
6301 if (UseCompressedClassPointers) {
6302 encode_klass_not_null(src, tmp);
6303 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6304 } else
6305 #endif
6306 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6307 }
6308
6309 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6310 Register tmp1, Register thread_tmp) {
6311 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6312 decorators = AccessInternal::decorator_fixup(decorators, type);
6313 bool as_raw = (decorators & AS_RAW) != 0;
6314 if (as_raw) {
6315 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6316 } else {
6317 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6318 }
6319 }
6320
6321 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
6322 Register tmp1, Register tmp2, Register tmp3) {
6323 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6324 decorators = AccessInternal::decorator_fixup(decorators, type);
6325 bool as_raw = (decorators & AS_RAW) != 0;
6326 if (as_raw) {
6327 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6328 } else {
6329 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6330 }
6331 }
6332
6333 void MacroAssembler::flat_field_copy(DecoratorSet decorators, Register src, Register dst,
6334 Register inline_layout_info) {
6335 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6336 bs->flat_field_copy(this, decorators, src, dst, inline_layout_info);
6337 }
6338
6339 void MacroAssembler::first_field_offset(Register inline_klass, Register offset) {
6340 movptr(offset, Address(inline_klass, InstanceKlass::adr_inlineklass_fixed_block_offset()));
6341 movl(offset, Address(offset, InlineKlass::first_field_offset_offset()));
6342 }
6343
6344 void MacroAssembler::data_for_oop(Register oop, Register data, Register inline_klass) {
6345 // ((address) (void*) o) + vk->first_field_offset();
6346 Register offset = (data == oop) ? rscratch1 : data;
6347 first_field_offset(inline_klass, offset);
6348 if (data == oop) {
6349 addptr(data, offset);
6350 } else {
6351 lea(data, Address(oop, offset));
6352 }
6353 }
6354
6355 void MacroAssembler::data_for_value_array_index(Register array, Register array_klass,
6356 Register index, Register data) {
6357 assert(index != rcx, "index needs to shift by rcx");
6358 assert_different_registers(array, array_klass, index);
6359 assert_different_registers(rcx, array, index);
6360
6361 // array->base() + (index << Klass::layout_helper_log2_element_size(lh));
6362 movl(rcx, Address(array_klass, Klass::layout_helper_offset()));
6363
6364 // Klass::layout_helper_log2_element_size(lh)
6365 // (lh >> _lh_log2_element_size_shift) & _lh_log2_element_size_mask;
6366 shrl(rcx, Klass::_lh_log2_element_size_shift);
6367 andl(rcx, Klass::_lh_log2_element_size_mask);
6368 shlptr(index); // index << rcx
6369
6370 lea(data, Address(array, index, Address::times_1, arrayOopDesc::base_offset_in_bytes(T_FLAT_ELEMENT)));
6371 }
6372
6373 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6374 Register thread_tmp, DecoratorSet decorators) {
6375 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6376 }
6377
6378 // Doesn't do verification, generates fixed size code
6379 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6380 Register thread_tmp, DecoratorSet decorators) {
6381 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6382 }
6383
6384 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
6385 Register tmp2, Register tmp3, DecoratorSet decorators) {
6386 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
6387 }
6388
6389 // Used for storing nulls.
6390 void MacroAssembler::store_heap_oop_null(Address dst) {
6391 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
6392 }
6692
6693 void MacroAssembler::reinit_heapbase() {
6694 if (UseCompressedOops) {
6695 if (Universe::heap() != nullptr) {
6696 if (CompressedOops::base() == nullptr) {
6697 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6698 } else {
6699 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6700 }
6701 } else {
6702 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6703 }
6704 }
6705 }
6706
6707 #endif // _LP64
6708
6709 #if COMPILER2_OR_JVMCI
6710
6711 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6712 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp, KRegister mask) {
6713 // cnt - number of qwords (8-byte words).
6714 // base - start address, qword aligned.
6715 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6716 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6717 if (use64byteVector) {
6718 evpbroadcastq(xtmp, val, AVX_512bit);
6719 } else if (MaxVectorSize >= 32) {
6720 movdq(xtmp, val);
6721 punpcklqdq(xtmp, xtmp);
6722 vinserti128_high(xtmp, xtmp);
6723 } else {
6724 movdq(xtmp, val);
6725 punpcklqdq(xtmp, xtmp);
6726 }
6727 jmp(L_zero_64_bytes);
6728
6729 BIND(L_loop);
6730 if (MaxVectorSize >= 32) {
6731 fill64(base, 0, xtmp, use64byteVector);
6732 } else {
6733 movdqu(Address(base, 0), xtmp);
6734 movdqu(Address(base, 16), xtmp);
6735 movdqu(Address(base, 32), xtmp);
6736 movdqu(Address(base, 48), xtmp);
6737 }
6738 addptr(base, 64);
6739
6740 BIND(L_zero_64_bytes);
6741 subptr(cnt, 8);
6742 jccb(Assembler::greaterEqual, L_loop);
6743
6744 // Copy trailing 64 bytes
6745 if (use64byteVector) {
6746 addptr(cnt, 8);
6747 jccb(Assembler::equal, L_end);
6748 fill64_masked(3, base, 0, xtmp, mask, cnt, val, true);
6749 jmp(L_end);
6750 } else {
6751 addptr(cnt, 4);
6752 jccb(Assembler::less, L_tail);
6753 if (MaxVectorSize >= 32) {
6754 vmovdqu(Address(base, 0), xtmp);
6755 } else {
6756 movdqu(Address(base, 0), xtmp);
6757 movdqu(Address(base, 16), xtmp);
6758 }
6759 }
6760 addptr(base, 32);
6761 subptr(cnt, 4);
6762
6763 BIND(L_tail);
6764 addptr(cnt, 4);
6765 jccb(Assembler::lessEqual, L_end);
6766 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6767 fill32_masked(3, base, 0, xtmp, mask, cnt, val);
6768 } else {
6769 decrement(cnt);
6770
6771 BIND(L_sloop);
6772 movq(Address(base, 0), xtmp);
6773 addptr(base, 8);
6774 decrement(cnt);
6775 jccb(Assembler::greaterEqual, L_sloop);
6776 }
6777 BIND(L_end);
6778 }
6779
6780 int MacroAssembler::store_inline_type_fields_to_buf(ciInlineKlass* vk, bool from_interpreter) {
6781 assert(InlineTypeReturnedAsFields, "Inline types should never be returned as fields");
6782 // An inline type might be returned. If fields are in registers we
6783 // need to allocate an inline type instance and initialize it with
6784 // the value of the fields.
6785 Label skip;
6786 // We only need a new buffered inline type if a new one is not returned
6787 testptr(rax, 1);
6788 jcc(Assembler::zero, skip);
6789 int call_offset = -1;
6790
6791 #ifdef _LP64
6792 // The following code is similar to allocate_instance but has some slight differences,
6793 // e.g. object size is always not zero, sometimes it's constant; storing klass ptr after
6794 // allocating is not necessary if vk != nullptr, etc. allocate_instance is not aware of these.
6795 Label slow_case;
6796 // 1. Try to allocate a new buffered inline instance either from TLAB or eden space
6797 mov(rscratch1, rax); // save rax for slow_case since *_allocate may corrupt it when allocation failed
6798 if (vk != nullptr) {
6799 // Called from C1, where the return type is statically known.
6800 movptr(rbx, (intptr_t)vk->get_InlineKlass());
6801 jint lh = vk->layout_helper();
6802 assert(lh != Klass::_lh_neutral_value, "inline class in return type must have been resolved");
6803 if (UseTLAB && !Klass::layout_helper_needs_slow_path(lh)) {
6804 tlab_allocate(r15_thread, rax, noreg, lh, r13, r14, slow_case);
6805 } else {
6806 jmp(slow_case);
6807 }
6808 } else {
6809 // Call from interpreter. RAX contains ((the InlineKlass* of the return type) | 0x01)
6810 mov(rbx, rax);
6811 andptr(rbx, -2);
6812 if (UseTLAB) {
6813 movl(r14, Address(rbx, Klass::layout_helper_offset()));
6814 testl(r14, Klass::_lh_instance_slow_path_bit);
6815 jcc(Assembler::notZero, slow_case);
6816 tlab_allocate(r15_thread, rax, r14, 0, r13, r14, slow_case);
6817 } else {
6818 jmp(slow_case);
6819 }
6820 }
6821 if (UseTLAB) {
6822 // 2. Initialize buffered inline instance header
6823 Register buffer_obj = rax;
6824 movptr(Address(buffer_obj, oopDesc::mark_offset_in_bytes()), (intptr_t)markWord::inline_type_prototype().value());
6825 xorl(r13, r13);
6826 store_klass_gap(buffer_obj, r13);
6827 if (vk == nullptr) {
6828 // store_klass corrupts rbx(klass), so save it in r13 for later use (interpreter case only).
6829 mov(r13, rbx);
6830 }
6831 store_klass(buffer_obj, rbx, rscratch1);
6832 // 3. Initialize its fields with an inline class specific handler
6833 if (vk != nullptr) {
6834 call(RuntimeAddress(vk->pack_handler())); // no need for call info as this will not safepoint.
6835 } else {
6836 movptr(rbx, Address(r13, InstanceKlass::adr_inlineklass_fixed_block_offset()));
6837 movptr(rbx, Address(rbx, InlineKlass::pack_handler_offset()));
6838 call(rbx);
6839 }
6840 jmp(skip);
6841 }
6842 bind(slow_case);
6843 // We failed to allocate a new inline type, fall back to a runtime
6844 // call. Some oop field may be live in some registers but we can't
6845 // tell. That runtime call will take care of preserving them
6846 // across a GC if there's one.
6847 mov(rax, rscratch1);
6848 #endif
6849
6850 if (from_interpreter) {
6851 super_call_VM_leaf(StubRoutines::store_inline_type_fields_to_buf());
6852 } else {
6853 call(RuntimeAddress(StubRoutines::store_inline_type_fields_to_buf()));
6854 call_offset = offset();
6855 }
6856
6857 bind(skip);
6858 return call_offset;
6859 }
6860
6861 // Move a value between registers/stack slots and update the reg_state
6862 bool MacroAssembler::move_helper(VMReg from, VMReg to, BasicType bt, RegState reg_state[]) {
6863 assert(from->is_valid() && to->is_valid(), "source and destination must be valid");
6864 if (reg_state[to->value()] == reg_written) {
6865 return true; // Already written
6866 }
6867 if (from != to && bt != T_VOID) {
6868 if (reg_state[to->value()] == reg_readonly) {
6869 return false; // Not yet writable
6870 }
6871 if (from->is_reg()) {
6872 if (to->is_reg()) {
6873 if (from->is_XMMRegister()) {
6874 if (bt == T_DOUBLE) {
6875 movdbl(to->as_XMMRegister(), from->as_XMMRegister());
6876 } else {
6877 assert(bt == T_FLOAT, "must be float");
6878 movflt(to->as_XMMRegister(), from->as_XMMRegister());
6879 }
6880 } else {
6881 movq(to->as_Register(), from->as_Register());
6882 }
6883 } else {
6884 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6885 Address to_addr = Address(rsp, st_off);
6886 if (from->is_XMMRegister()) {
6887 if (bt == T_DOUBLE) {
6888 movdbl(to_addr, from->as_XMMRegister());
6889 } else {
6890 assert(bt == T_FLOAT, "must be float");
6891 movflt(to_addr, from->as_XMMRegister());
6892 }
6893 } else {
6894 movq(to_addr, from->as_Register());
6895 }
6896 }
6897 } else {
6898 Address from_addr = Address(rsp, from->reg2stack() * VMRegImpl::stack_slot_size + wordSize);
6899 if (to->is_reg()) {
6900 if (to->is_XMMRegister()) {
6901 if (bt == T_DOUBLE) {
6902 movdbl(to->as_XMMRegister(), from_addr);
6903 } else {
6904 assert(bt == T_FLOAT, "must be float");
6905 movflt(to->as_XMMRegister(), from_addr);
6906 }
6907 } else {
6908 movq(to->as_Register(), from_addr);
6909 }
6910 } else {
6911 int st_off = to->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6912 movq(r13, from_addr);
6913 movq(Address(rsp, st_off), r13);
6914 }
6915 }
6916 }
6917 // Update register states
6918 reg_state[from->value()] = reg_writable;
6919 reg_state[to->value()] = reg_written;
6920 return true;
6921 }
6922
6923 // Calculate the extra stack space required for packing or unpacking inline
6924 // args and adjust the stack pointer
6925 int MacroAssembler::extend_stack_for_inline_args(int args_on_stack) {
6926 // Two additional slots to account for return address
6927 int sp_inc = (args_on_stack + 2) * VMRegImpl::stack_slot_size;
6928 sp_inc = align_up(sp_inc, StackAlignmentInBytes);
6929 // Save the return address, adjust the stack (make sure it is properly
6930 // 16-byte aligned) and copy the return address to the new top of the stack.
6931 // The stack will be repaired on return (see MacroAssembler::remove_frame).
6932 assert(sp_inc > 0, "sanity");
6933 pop(r13);
6934 subptr(rsp, sp_inc);
6935 push(r13);
6936 return sp_inc;
6937 }
6938
6939 // Read all fields from an inline type buffer and store the field values in registers/stack slots.
6940 bool MacroAssembler::unpack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index,
6941 VMReg from, int& from_index, VMRegPair* to, int to_count, int& to_index,
6942 RegState reg_state[]) {
6943 assert(sig->at(sig_index)._bt == T_VOID, "should be at end delimiter");
6944 assert(from->is_valid(), "source must be valid");
6945 bool progress = false;
6946 #ifdef ASSERT
6947 const int start_offset = offset();
6948 #endif
6949
6950 Label L_null, L_notNull;
6951 // Don't use r14 as tmp because it's used for spilling (see MacroAssembler::spill_reg_for)
6952 Register tmp1 = r10;
6953 Register tmp2 = r13;
6954 Register fromReg = noreg;
6955 ScalarizedInlineArgsStream stream(sig, sig_index, to, to_count, to_index, -1);
6956 bool done = true;
6957 bool mark_done = true;
6958 VMReg toReg;
6959 BasicType bt;
6960 // Check if argument requires a null check
6961 bool null_check = false;
6962 VMReg nullCheckReg;
6963 while (stream.next(nullCheckReg, bt)) {
6964 if (sig->at(stream.sig_index())._offset == -1) {
6965 null_check = true;
6966 break;
6967 }
6968 }
6969 stream.reset(sig_index, to_index);
6970 while (stream.next(toReg, bt)) {
6971 assert(toReg->is_valid(), "destination must be valid");
6972 int idx = (int)toReg->value();
6973 if (reg_state[idx] == reg_readonly) {
6974 if (idx != from->value()) {
6975 mark_done = false;
6976 }
6977 done = false;
6978 continue;
6979 } else if (reg_state[idx] == reg_written) {
6980 continue;
6981 }
6982 assert(reg_state[idx] == reg_writable, "must be writable");
6983 reg_state[idx] = reg_written;
6984 progress = true;
6985
6986 if (fromReg == noreg) {
6987 if (from->is_reg()) {
6988 fromReg = from->as_Register();
6989 } else {
6990 int st_off = from->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
6991 movq(tmp1, Address(rsp, st_off));
6992 fromReg = tmp1;
6993 }
6994 if (null_check) {
6995 // Nullable inline type argument, emit null check
6996 testptr(fromReg, fromReg);
6997 jcc(Assembler::zero, L_null);
6998 }
6999 }
7000 int off = sig->at(stream.sig_index())._offset;
7001 if (off == -1) {
7002 assert(null_check, "Missing null check at");
7003 if (toReg->is_stack()) {
7004 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
7005 movq(Address(rsp, st_off), 1);
7006 } else {
7007 movq(toReg->as_Register(), 1);
7008 }
7009 continue;
7010 }
7011 assert(off > 0, "offset in object should be positive");
7012 Address fromAddr = Address(fromReg, off);
7013 if (!toReg->is_XMMRegister()) {
7014 Register dst = toReg->is_stack() ? tmp2 : toReg->as_Register();
7015 if (is_reference_type(bt)) {
7016 load_heap_oop(dst, fromAddr);
7017 } else {
7018 bool is_signed = (bt != T_CHAR) && (bt != T_BOOLEAN);
7019 load_sized_value(dst, fromAddr, type2aelembytes(bt), is_signed);
7020 }
7021 if (toReg->is_stack()) {
7022 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
7023 movq(Address(rsp, st_off), dst);
7024 }
7025 } else if (bt == T_DOUBLE) {
7026 movdbl(toReg->as_XMMRegister(), fromAddr);
7027 } else {
7028 assert(bt == T_FLOAT, "must be float");
7029 movflt(toReg->as_XMMRegister(), fromAddr);
7030 }
7031 }
7032 if (progress && null_check) {
7033 if (done) {
7034 jmp(L_notNull);
7035 bind(L_null);
7036 // Set IsInit field to zero to signal that the argument is null.
7037 // Also set all oop fields to zero to make the GC happy.
7038 stream.reset(sig_index, to_index);
7039 while (stream.next(toReg, bt)) {
7040 if (sig->at(stream.sig_index())._offset == -1 ||
7041 bt == T_OBJECT || bt == T_ARRAY) {
7042 if (toReg->is_stack()) {
7043 int st_off = toReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
7044 movq(Address(rsp, st_off), 0);
7045 } else {
7046 xorq(toReg->as_Register(), toReg->as_Register());
7047 }
7048 }
7049 }
7050 bind(L_notNull);
7051 } else {
7052 bind(L_null);
7053 }
7054 }
7055
7056 sig_index = stream.sig_index();
7057 to_index = stream.regs_index();
7058
7059 if (mark_done && reg_state[from->value()] != reg_written) {
7060 // This is okay because no one else will write to that slot
7061 reg_state[from->value()] = reg_writable;
7062 }
7063 from_index--;
7064 assert(progress || (start_offset == offset()), "should not emit code");
7065 return done;
7066 }
7067
7068 bool MacroAssembler::pack_inline_helper(const GrowableArray<SigEntry>* sig, int& sig_index, int vtarg_index,
7069 VMRegPair* from, int from_count, int& from_index, VMReg to,
7070 RegState reg_state[], Register val_array) {
7071 assert(sig->at(sig_index)._bt == T_METADATA, "should be at delimiter");
7072 assert(to->is_valid(), "destination must be valid");
7073
7074 if (reg_state[to->value()] == reg_written) {
7075 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7076 return true; // Already written
7077 }
7078
7079 // TODO 8284443 Isn't it an issue if below code uses r14 as tmp when it contains a spilled value?
7080 // Be careful with r14 because it's used for spilling (see MacroAssembler::spill_reg_for).
7081 Register val_obj_tmp = r11;
7082 Register from_reg_tmp = r14;
7083 Register tmp1 = r10;
7084 Register tmp2 = r13;
7085 Register tmp3 = rbx;
7086 Register val_obj = to->is_stack() ? val_obj_tmp : to->as_Register();
7087
7088 assert_different_registers(val_obj_tmp, from_reg_tmp, tmp1, tmp2, tmp3, val_array);
7089
7090 if (reg_state[to->value()] == reg_readonly) {
7091 if (!is_reg_in_unpacked_fields(sig, sig_index, to, from, from_count, from_index)) {
7092 skip_unpacked_fields(sig, sig_index, from, from_count, from_index);
7093 return false; // Not yet writable
7094 }
7095 val_obj = val_obj_tmp;
7096 }
7097
7098 int index = arrayOopDesc::base_offset_in_bytes(T_OBJECT) + vtarg_index * type2aelembytes(T_OBJECT);
7099 load_heap_oop(val_obj, Address(val_array, index));
7100
7101 ScalarizedInlineArgsStream stream(sig, sig_index, from, from_count, from_index);
7102 VMReg fromReg;
7103 BasicType bt;
7104 Label L_null;
7105 while (stream.next(fromReg, bt)) {
7106 assert(fromReg->is_valid(), "source must be valid");
7107 reg_state[fromReg->value()] = reg_writable;
7108
7109 int off = sig->at(stream.sig_index())._offset;
7110 if (off == -1) {
7111 // Nullable inline type argument, emit null check
7112 Label L_notNull;
7113 if (fromReg->is_stack()) {
7114 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
7115 testb(Address(rsp, ld_off), 1);
7116 } else {
7117 testb(fromReg->as_Register(), 1);
7118 }
7119 jcc(Assembler::notZero, L_notNull);
7120 movptr(val_obj, 0);
7121 jmp(L_null);
7122 bind(L_notNull);
7123 continue;
7124 }
7125
7126 assert(off > 0, "offset in object should be positive");
7127 size_t size_in_bytes = is_java_primitive(bt) ? type2aelembytes(bt) : wordSize;
7128
7129 Address dst(val_obj, off);
7130 if (!fromReg->is_XMMRegister()) {
7131 Register src;
7132 if (fromReg->is_stack()) {
7133 src = from_reg_tmp;
7134 int ld_off = fromReg->reg2stack() * VMRegImpl::stack_slot_size + wordSize;
7135 load_sized_value(src, Address(rsp, ld_off), size_in_bytes, /* is_signed */ false);
7136 } else {
7137 src = fromReg->as_Register();
7138 }
7139 assert_different_registers(dst.base(), src, tmp1, tmp2, tmp3, val_array);
7140 if (is_reference_type(bt)) {
7141 store_heap_oop(dst, src, tmp1, tmp2, tmp3, IN_HEAP | ACCESS_WRITE | IS_DEST_UNINITIALIZED);
7142 } else {
7143 store_sized_value(dst, src, size_in_bytes);
7144 }
7145 } else if (bt == T_DOUBLE) {
7146 movdbl(dst, fromReg->as_XMMRegister());
7147 } else {
7148 assert(bt == T_FLOAT, "must be float");
7149 movflt(dst, fromReg->as_XMMRegister());
7150 }
7151 }
7152 bind(L_null);
7153 sig_index = stream.sig_index();
7154 from_index = stream.regs_index();
7155
7156 assert(reg_state[to->value()] == reg_writable, "must have already been read");
7157 bool success = move_helper(val_obj->as_VMReg(), to, T_OBJECT, reg_state);
7158 assert(success, "to register must be writeable");
7159 return true;
7160 }
7161
7162 VMReg MacroAssembler::spill_reg_for(VMReg reg) {
7163 return reg->is_XMMRegister() ? xmm8->as_VMReg() : r14->as_VMReg();
7164 }
7165
7166 void MacroAssembler::remove_frame(int initial_framesize, bool needs_stack_repair) {
7167 assert((initial_framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
7168 if (needs_stack_repair) {
7169 movq(rbp, Address(rsp, initial_framesize));
7170 // The stack increment resides just below the saved rbp
7171 addq(rsp, Address(rsp, initial_framesize - wordSize));
7172 } else {
7173 if (initial_framesize > 0) {
7174 addq(rsp, initial_framesize);
7175 }
7176 pop(rbp);
7177 }
7178 }
7179
7180 // Clearing constant sized memory using YMM/ZMM registers.
7181 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
7182 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
7183 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
7184
7185 int vector64_count = (cnt & (~0x7)) >> 3;
7186 cnt = cnt & 0x7;
7187 const int fill64_per_loop = 4;
7188 const int max_unrolled_fill64 = 8;
7189
7190 // 64 byte initialization loop.
7191 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
7192 int start64 = 0;
7193 if (vector64_count > max_unrolled_fill64) {
7194 Label LOOP;
7195 Register index = rtmp;
7196
7197 start64 = vector64_count - (vector64_count % fill64_per_loop);
7198
7199 movl(index, 0);
7249 break;
7250 case 7:
7251 if (use64byteVector) {
7252 movl(rtmp, 0x7F);
7253 kmovwl(mask, rtmp);
7254 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
7255 } else {
7256 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
7257 movl(rtmp, 0x7);
7258 kmovwl(mask, rtmp);
7259 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
7260 }
7261 break;
7262 default:
7263 fatal("Unexpected length : %d\n",cnt);
7264 break;
7265 }
7266 }
7267 }
7268
7269 void MacroAssembler::clear_mem(Register base, Register cnt, Register val, XMMRegister xtmp,
7270 bool is_large, bool word_copy_only, KRegister mask) {
7271 // cnt - number of qwords (8-byte words).
7272 // base - start address, qword aligned.
7273 // is_large - if optimizers know cnt is larger than InitArrayShortSize
7274 assert(base==rdi, "base register must be edi for rep stos");
7275 assert(val==rax, "val register must be eax for rep stos");
7276 assert(cnt==rcx, "cnt register must be ecx for rep stos");
7277 assert(InitArrayShortSize % BytesPerLong == 0,
7278 "InitArrayShortSize should be the multiple of BytesPerLong");
7279
7280 Label DONE;
7281
7282 if (!is_large) {
7283 Label LOOP, LONG;
7284 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
7285 jccb(Assembler::greater, LONG);
7286
7287 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7288
7289 decrement(cnt);
7290 jccb(Assembler::negative, DONE); // Zero length
7291
7292 // Use individual pointer-sized stores for small counts:
7293 BIND(LOOP);
7294 movptr(Address(base, cnt, Address::times_ptr), val);
7295 decrement(cnt);
7296 jccb(Assembler::greaterEqual, LOOP);
7297 jmpb(DONE);
7298
7299 BIND(LONG);
7300 }
7301
7302 // Use longer rep-prefixed ops for non-small counts:
7303 if (UseFastStosb && !word_copy_only) {
7304 shlptr(cnt, 3); // convert to number of bytes
7305 rep_stosb();
7306 } else if (UseXMMForObjInit) {
7307 xmm_clear_mem(base, cnt, val, xtmp, mask);
7308 } else {
7309 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
7310 rep_stos();
7311 }
7312
7313 BIND(DONE);
7314 }
7315
7316 #endif //COMPILER2_OR_JVMCI
7317
7318
7319 void MacroAssembler::generate_fill(BasicType t, bool aligned,
7320 Register to, Register value, Register count,
7321 Register rtmp, XMMRegister xtmp) {
7322 ShortBranchVerifier sbv(this);
7323 assert_different_registers(to, value, count, rtmp);
7324 Label L_exit;
7325 Label L_fill_2_bytes, L_fill_4_bytes;
7326
7327 #if defined(COMPILER2) && defined(_LP64)
11415
11416 // Load top.
11417 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
11418
11419 // Check if the lock-stack is full.
11420 cmpl(top, LockStack::end_offset());
11421 jcc(Assembler::greaterEqual, slow);
11422
11423 // Check for recursion.
11424 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
11425 jcc(Assembler::equal, push);
11426
11427 // Check header for monitor (0b10).
11428 testptr(reg_rax, markWord::monitor_value);
11429 jcc(Assembler::notZero, slow);
11430
11431 // Try to lock. Transition lock bits 0b01 => 0b00
11432 movptr(tmp, reg_rax);
11433 andptr(tmp, ~(int32_t)markWord::unlocked_value);
11434 orptr(reg_rax, markWord::unlocked_value);
11435 if (EnableValhalla) {
11436 // Mask inline_type bit such that we go to the slow path if object is an inline type
11437 andptr(reg_rax, ~((int) markWord::inline_type_bit_in_place));
11438 }
11439 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
11440 jcc(Assembler::notEqual, slow);
11441
11442 // Restore top, CAS clobbers register.
11443 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
11444
11445 bind(push);
11446 // After successful lock, push object on lock-stack.
11447 movptr(Address(thread, top), obj);
11448 incrementl(top, oopSize);
11449 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
11450 }
11451
11452 // Implements lightweight-unlocking.
11453 //
11454 // obj: the object to be unlocked
11455 // reg_rax: rax
11456 // thread: the thread
11457 // tmp: a temporary register
11458 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
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