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src/hotspot/cpu/x86/sharedRuntime_x86_32.cpp

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 465       else if( freg_arg1 == fltarg_flt_dbl ) freg_arg1 = i;
 466       else // Else double is passed low on the stack to be aligned.
 467         stack += 2;
 468     } else if( sig_bt[i] == T_LONG ) {
 469       stack += 2;
 470     }
 471   }
 472   int dstack = 0;             // Separate counter for placing doubles
 473 
 474   // Now pick where all else goes.
 475   for( i = 0; i < total_args_passed; i++) {
 476     // From the type and the argument number (count) compute the location
 477     switch( sig_bt[i] ) {
 478     case T_SHORT:
 479     case T_CHAR:
 480     case T_BYTE:
 481     case T_BOOLEAN:
 482     case T_INT:
 483     case T_ARRAY:
 484     case T_OBJECT:

 485     case T_ADDRESS:
 486       if( reg_arg0 == 9999 )  {
 487         reg_arg0 = i;
 488         regs[i].set1(rcx->as_VMReg());
 489       } else if( reg_arg1 == 9999 )  {
 490         reg_arg1 = i;
 491         regs[i].set1(rdx->as_VMReg());
 492       } else {
 493         regs[i].set1(VMRegImpl::stack2reg(stack++));
 494       }
 495       break;
 496     case T_FLOAT:
 497       if( freg_arg0 == fltarg_flt_dbl || freg_arg0 == fltarg_float_only ) {
 498         freg_arg0 = i;
 499         regs[i].set1(xmm0->as_VMReg());
 500       } else if( freg_arg1 == fltarg_flt_dbl || freg_arg1 == fltarg_float_only ) {
 501         freg_arg1 = i;
 502         regs[i].set1(xmm1->as_VMReg());
 503       } else {
 504         regs[i].set1(VMRegImpl::stack2reg(stack++));

 515         regs[i].set2(xmm0->as_VMReg());
 516       } else if( freg_arg1 == (uint)i ) {
 517         regs[i].set2(xmm1->as_VMReg());
 518       } else {
 519         regs[i].set2(VMRegImpl::stack2reg(dstack));
 520         dstack += 2;
 521       }
 522       break;
 523     case T_VOID: regs[i].set_bad(); break;
 524       break;
 525     default:
 526       ShouldNotReachHere();
 527       break;
 528     }
 529   }
 530 
 531   // return value can be odd number of VMRegImpl stack slots make multiple of 2
 532   return align_up(stack, 2);
 533 }
 534 









 535 // Patch the callers callsite with entry to compiled code if it exists.
 536 static void patch_callers_callsite(MacroAssembler *masm) {
 537   Label L;
 538   __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
 539   __ jcc(Assembler::equal, L);
 540   // Schedule the branch target address early.
 541   // Call into the VM to patch the caller, then jump to compiled callee
 542   // rax, isn't live so capture return address while we easily can
 543   __ movptr(rax, Address(rsp, 0));
 544   __ pusha();
 545   __ pushf();
 546 
 547   if (UseSSE == 1) {
 548     __ subptr(rsp, 2*wordSize);
 549     __ movflt(Address(rsp, 0), xmm0);
 550     __ movflt(Address(rsp, wordSize), xmm1);
 551   }
 552   if (UseSSE >= 2) {
 553     __ subptr(rsp, 4*wordSize);
 554     __ movdbl(Address(rsp, 0), xmm0);

 576     __ addptr(rsp, 2*wordSize);
 577   }
 578   if (UseSSE >= 2) {
 579     __ movdbl(xmm0, Address(rsp, 0));
 580     __ movdbl(xmm1, Address(rsp, 2*wordSize));
 581     __ addptr(rsp, 4*wordSize);
 582   }
 583 
 584   __ popf();
 585   __ popa();
 586   __ bind(L);
 587 }
 588 
 589 
 590 static void move_c2i_double(MacroAssembler *masm, XMMRegister r, int st_off) {
 591   int next_off = st_off - Interpreter::stackElementSize;
 592   __ movdbl(Address(rsp, next_off), r);
 593 }
 594 
 595 static void gen_c2i_adapter(MacroAssembler *masm,
 596                             int total_args_passed,
 597                             int comp_args_on_stack,
 598                             const BasicType *sig_bt,
 599                             const VMRegPair *regs,
 600                             Label& skip_fixup) {




 601   // Before we get into the guts of the C2I adapter, see if we should be here
 602   // at all.  We've come from compiled code and are attempting to jump to the
 603   // interpreter, which means the caller made a static call to get here
 604   // (vcalls always get a compiled target if there is one).  Check for a
 605   // compiled target.  If there is one, we need to patch the caller's call.
 606   patch_callers_callsite(masm);
 607 
 608   __ bind(skip_fixup);
 609 
 610 #ifdef COMPILER2
 611   // C2 may leave the stack dirty if not in SSE2+ mode
 612   if (UseSSE >= 2) {
 613     __ verify_FPU(0, "c2i transition should have clean FPU stack");
 614   } else {
 615     __ empty_FPU_stack();
 616   }
 617 #endif /* COMPILER2 */
 618 
 619   // Since all args are passed on the stack, total_args_passed * interpreter_
 620   // stack_element_size  is the
 621   // space we need.
 622   int extraspace = total_args_passed * Interpreter::stackElementSize;
 623 
 624   // Get return address
 625   __ pop(rax);
 626 
 627   // set senderSP value
 628   __ movptr(rsi, rsp);
 629 
 630   __ subptr(rsp, extraspace);
 631 
 632   // Now write the args into the outgoing interpreter space
 633   for (int i = 0; i < total_args_passed; i++) {
 634     if (sig_bt[i] == T_VOID) {
 635       assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
 636       continue;
 637     }
 638 
 639     // st_off points to lowest address on stack.
 640     int st_off = ((total_args_passed - 1) - i) * Interpreter::stackElementSize;
 641     int next_off = st_off - Interpreter::stackElementSize;
 642 
 643     // Say 4 args:
 644     // i   st_off
 645     // 0   12 T_LONG
 646     // 1    8 T_VOID
 647     // 2    4 T_OBJECT
 648     // 3    0 T_BOOL
 649     VMReg r_1 = regs[i].first();
 650     VMReg r_2 = regs[i].second();
 651     if (!r_1->is_valid()) {
 652       assert(!r_2->is_valid(), "");
 653       continue;
 654     }
 655 
 656     if (r_1->is_stack()) {
 657       // memory to memory use fpu stack top
 658       int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
 659 
 660       if (!r_2->is_valid()) {

 670 #ifndef _LP64
 671         __ movptr(rdi, Address(rsp, ld_off + wordSize));
 672         __ movptr(Address(rsp, st_off), rdi);
 673 #else
 674 #ifdef ASSERT
 675         // Overwrite the unused slot with known junk
 676         __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
 677         __ movptr(Address(rsp, st_off), rax);
 678 #endif /* ASSERT */
 679 #endif // _LP64
 680       }
 681     } else if (r_1->is_Register()) {
 682       Register r = r_1->as_Register();
 683       if (!r_2->is_valid()) {
 684         __ movl(Address(rsp, st_off), r);
 685       } else {
 686         // long/double in gpr
 687         NOT_LP64(ShouldNotReachHere());
 688         // Two VMRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
 689         // T_DOUBLE and T_LONG use two slots in the interpreter
 690         if ( sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
 691           // long/double in gpr
 692 #ifdef ASSERT
 693           // Overwrite the unused slot with known junk
 694           LP64_ONLY(__ mov64(rax, CONST64(0xdeadffffdeadaaab)));
 695           __ movptr(Address(rsp, st_off), rax);
 696 #endif /* ASSERT */
 697           __ movptr(Address(rsp, next_off), r);
 698         } else {
 699           __ movptr(Address(rsp, st_off), r);
 700         }
 701       }
 702     } else {
 703       assert(r_1->is_XMMRegister(), "");
 704       if (!r_2->is_valid()) {
 705         __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
 706       } else {
 707         assert(sig_bt[i] == T_DOUBLE || sig_bt[i] == T_LONG, "wrong type");
 708         move_c2i_double(masm, r_1->as_XMMRegister(), st_off);
 709       }
 710     }
 711   }
 712 
 713   // Schedule the branch target address early.
 714   __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
 715   // And repush original return address
 716   __ push(rax);
 717   __ jmp(rcx);
 718 }
 719 
 720 
 721 static void move_i2c_double(MacroAssembler *masm, XMMRegister r, Register saved_sp, int ld_off) {
 722   int next_val_off = ld_off - Interpreter::stackElementSize;
 723   __ movdbl(r, Address(saved_sp, next_val_off));
 724 }
 725 
 726 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg,
 727                         address code_start, address code_end,
 728                         Label& L_ok) {
 729   Label L_fail;
 730   __ lea(temp_reg, ExternalAddress(code_start));
 731   __ cmpptr(pc_reg, temp_reg);
 732   __ jcc(Assembler::belowEqual, L_fail);
 733   __ lea(temp_reg, ExternalAddress(code_end));
 734   __ cmpptr(pc_reg, temp_reg);
 735   __ jcc(Assembler::below, L_ok);
 736   __ bind(L_fail);
 737 }
 738 
 739 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
 740                                     int total_args_passed,
 741                                     int comp_args_on_stack,
 742                                     const BasicType *sig_bt,
 743                                     const VMRegPair *regs) {

 744   // Note: rsi contains the senderSP on entry. We must preserve it since
 745   // we may do a i2c -> c2i transition if we lose a race where compiled
 746   // code goes non-entrant while we get args ready.
 747 
 748   // Adapters can be frameless because they do not require the caller
 749   // to perform additional cleanup work, such as correcting the stack pointer.
 750   // An i2c adapter is frameless because the *caller* frame, which is interpreted,
 751   // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
 752   // even if a callee has modified the stack pointer.
 753   // A c2i adapter is frameless because the *callee* frame, which is interpreted,
 754   // routinely repairs its caller's stack pointer (from sender_sp, which is set
 755   // up via the senderSP register).
 756   // In other words, if *either* the caller or callee is interpreted, we can
 757   // get the stack pointer repaired after a call.
 758   // This is why c2i and i2c adapters cannot be indefinitely composed.
 759   // In particular, if a c2i adapter were to somehow call an i2c adapter,
 760   // both caller and callee would be compiled methods, and neither would
 761   // clean up the stack pointer changes performed by the two adapters.
 762   // If this happens, control eventually transfers back to the compiled
 763   // caller, but with an uncorrected stack, causing delayed havoc.

 812   }
 813 
 814   // Align the outgoing SP
 815   __ andptr(rsp, -(StackAlignmentInBytes));
 816 
 817   // push the return address on the stack (note that pushing, rather
 818   // than storing it, yields the correct frame alignment for the callee)
 819   __ push(rax);
 820 
 821   // Put saved SP in another register
 822   const Register saved_sp = rax;
 823   __ movptr(saved_sp, rdi);
 824 
 825 
 826   // Will jump to the compiled code just as if compiled code was doing it.
 827   // Pre-load the register-jump target early, to schedule it better.
 828   __ movptr(rdi, Address(rbx, in_bytes(Method::from_compiled_offset())));
 829 
 830   // Now generate the shuffle code.  Pick up all register args and move the
 831   // rest through the floating point stack top.
 832   for (int i = 0; i < total_args_passed; i++) {
 833     if (sig_bt[i] == T_VOID) {
 834       // Longs and doubles are passed in native word order, but misaligned
 835       // in the 32-bit build.
 836       assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
 837       continue;
 838     }
 839 
 840     // Pick up 0, 1 or 2 words from SP+offset.
 841 
 842     assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
 843             "scrambled load targets?");
 844     // Load in argument order going down.
 845     int ld_off = (total_args_passed - i) * Interpreter::stackElementSize;
 846     // Point to interpreter value (vs. tag)
 847     int next_off = ld_off - Interpreter::stackElementSize;
 848     //
 849     //
 850     //
 851     VMReg r_1 = regs[i].first();
 852     VMReg r_2 = regs[i].second();
 853     if (!r_1->is_valid()) {
 854       assert(!r_2->is_valid(), "");
 855       continue;
 856     }
 857     if (r_1->is_stack()) {
 858       // Convert stack slot to an SP offset (+ wordSize to account for return address )
 859       int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
 860 
 861       // We can use rsi as a temp here because compiled code doesn't need rsi as an input
 862       // and if we end up going thru a c2i because of a miss a reasonable value of rsi
 863       // we be generated.
 864       if (!r_2->is_valid()) {
 865         // __ fld_s(Address(saved_sp, ld_off));
 866         // __ fstp_s(Address(rsp, st_off));
 867         __ movl(rsi, Address(saved_sp, ld_off));
 868         __ movptr(Address(rsp, st_off), rsi);
 869       } else {
 870         // Interpreter local[n] == MSW, local[n+1] == LSW however locals
 871         // are accessed as negative so LSW is at LOW address
 872 
 873         // ld_off is MSW so get LSW
 874         // st_off is LSW (i.e. reg.first())
 875         // __ fld_d(Address(saved_sp, next_off));
 876         // __ fstp_d(Address(rsp, st_off));
 877         //
 878         // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
 879         // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
 880         // So we must adjust where to pick up the data to match the interpreter.
 881         //
 882         // Interpreter local[n] == MSW, local[n+1] == LSW however locals
 883         // are accessed as negative so LSW is at LOW address
 884 
 885         // ld_off is MSW so get LSW
 886         const int offset = (NOT_LP64(true ||) sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
 887                            next_off : ld_off;
 888         __ movptr(rsi, Address(saved_sp, offset));
 889         __ movptr(Address(rsp, st_off), rsi);
 890 #ifndef _LP64
 891         __ movptr(rsi, Address(saved_sp, ld_off));
 892         __ movptr(Address(rsp, st_off + wordSize), rsi);
 893 #endif // _LP64
 894       }
 895     } else if (r_1->is_Register()) {  // Register argument
 896       Register r = r_1->as_Register();
 897       assert(r != rax, "must be different");
 898       if (r_2->is_valid()) {
 899         //
 900         // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
 901         // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
 902         // So we must adjust where to pick up the data to match the interpreter.
 903 
 904         const int offset = (NOT_LP64(true ||) sig_bt[i]==T_LONG||sig_bt[i]==T_DOUBLE)?
 905                            next_off : ld_off;
 906 
 907         // this can be a misaligned move
 908         __ movptr(r, Address(saved_sp, offset));
 909 #ifndef _LP64
 910         assert(r_2->as_Register() != rax, "need another temporary register");
 911         // Remember r_1 is low address (and LSB on x86)
 912         // So r_2 gets loaded from high address regardless of the platform
 913         __ movptr(r_2->as_Register(), Address(saved_sp, ld_off));
 914 #endif // _LP64
 915       } else {
 916         __ movl(r, Address(saved_sp, ld_off));
 917       }
 918     } else {
 919       assert(r_1->is_XMMRegister(), "");
 920       if (!r_2->is_valid()) {
 921         __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
 922       } else {
 923         move_i2c_double(masm, r_1->as_XMMRegister(), saved_sp, ld_off);
 924       }

 932   // "compiled" so it is much better to make this transition
 933   // invisible to the stack walking code. Unfortunately if
 934   // we try and find the callee by normal means a safepoint
 935   // is possible. So we stash the desired callee in the thread
 936   // and the vm will find there should this case occur.
 937 
 938   __ get_thread(rax);
 939   __ movptr(Address(rax, JavaThread::callee_target_offset()), rbx);
 940 
 941   // move Method* to rax, in case we end up in an c2i adapter.
 942   // the c2i adapters expect Method* in rax, (c2) because c2's
 943   // resolve stubs return the result (the method) in rax,.
 944   // I'd love to fix this.
 945   __ mov(rax, rbx);
 946 
 947   __ jmp(rdi);
 948 }
 949 
 950 // ---------------------------------------------------------------
 951 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
 952                                                             int total_args_passed,
 953                                                             int comp_args_on_stack,
 954                                                             const BasicType *sig_bt,
 955                                                             const VMRegPair *regs,
 956                                                             AdapterFingerPrint* fingerprint) {

 957   address i2c_entry = __ pc();
 958 
 959   gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
 960 
 961   // -------------------------------------------------------------------------
 962   // Generate a C2I adapter.  On entry we know rbx, holds the Method* during calls
 963   // to the interpreter.  The args start out packed in the compiled layout.  They
 964   // need to be unpacked into the interpreter layout.  This will almost always
 965   // require some stack space.  We grow the current (compiled) stack, then repack
 966   // the args.  We  finally end in a jump to the generic interpreter entry point.
 967   // On exit from the interpreter, the interpreter will restore our SP (lest the
 968   // compiled code, which relys solely on SP and not EBP, get sick).
 969 
 970   address c2i_unverified_entry = __ pc();
 971   Label skip_fixup;
 972 
 973   Register holder = rax;
 974   Register receiver = rcx;
 975   Register temp = rbx;
 976 
 977   {
 978 
 979     Label missed;
 980     __ movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
 981     __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset()));
 982     __ movptr(rbx, Address(holder, CompiledICHolder::holder_metadata_offset()));
 983     __ jcc(Assembler::notEqual, missed);
 984     // Method might have been compiled since the call site was patched to
 985     // interpreted if that is the case treat it as a miss so we can get
 986     // the call site corrected.
 987     __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
 988     __ jcc(Assembler::equal, skip_fixup);
 989 
 990     __ bind(missed);
 991     __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 992   }
 993 
 994   address c2i_entry = __ pc();
 995 
 996   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
 997   bs->c2i_entry_barrier(masm);
 998 
 999   gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);



1000 
1001   __ flush();

1002   return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
1003 }
1004 
1005 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1006                                          VMRegPair *regs,
1007                                          VMRegPair *regs2,
1008                                          int total_args_passed) {
1009   assert(regs2 == NULL, "not needed on x86");
1010 // We return the amount of VMRegImpl stack slots we need to reserve for all
1011 // the arguments NOT counting out_preserve_stack_slots.
1012 
1013   uint    stack = 0;        // All arguments on stack
1014 
1015   for( int i = 0; i < total_args_passed; i++) {
1016     // From the type and the argument number (count) compute the location
1017     switch( sig_bt[i] ) {
1018     case T_BOOLEAN:
1019     case T_CHAR:
1020     case T_FLOAT:
1021     case T_BYTE:
1022     case T_SHORT:
1023     case T_INT:
1024     case T_OBJECT:

1025     case T_ARRAY:
1026     case T_ADDRESS:
1027     case T_METADATA:
1028       regs[i].set1(VMRegImpl::stack2reg(stack++));
1029       break;
1030     case T_LONG:
1031     case T_DOUBLE: // The stack numbering is reversed from Java
1032       // Since C arguments do not get reversed, the ordering for
1033       // doubles on the stack must be opposite the Java convention
1034       assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
1035       regs[i].set2(VMRegImpl::stack2reg(stack));
1036       stack += 2;
1037       break;
1038     case T_VOID: regs[i].set_bad(); break;
1039     default:
1040       ShouldNotReachHere();
1041       break;
1042     }
1043   }
1044   return stack;

1703   // caller.
1704   //
1705   OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1706 
1707   // Mark location of rbp,
1708   // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, rbp->as_VMReg());
1709 
1710   // We know that we only have args in at most two integer registers (rcx, rdx). So rax, rbx
1711   // Are free to temporaries if we have to do  stack to steck moves.
1712   // All inbound args are referenced based on rbp, and all outbound args via rsp.
1713 
1714   for (int i = 0; i < total_in_args ; i++, c_arg++ ) {
1715     switch (in_sig_bt[i]) {
1716       case T_ARRAY:
1717         if (is_critical_native) {
1718           VMRegPair in_arg = in_regs[i];
1719           unpack_array_argument(masm, in_arg, in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]);
1720           c_arg++;
1721           break;
1722         }

1723       case T_OBJECT:
1724         assert(!is_critical_native, "no oop arguments");
1725         object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
1726                     ((i == 0) && (!is_static)),
1727                     &receiver_offset);
1728         break;
1729       case T_VOID:
1730         break;
1731 
1732       case T_FLOAT:
1733         float_move(masm, in_regs[i], out_regs[c_arg]);
1734           break;
1735 
1736       case T_DOUBLE:
1737         assert( i + 1 < total_in_args &&
1738                 in_sig_bt[i + 1] == T_VOID &&
1739                 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
1740         double_move(masm, in_regs[i], out_regs[c_arg]);
1741         break;
1742 

1874   // Verify or restore cpu control state after JNI call
1875   __ restore_cpu_control_state_after_jni();
1876 
1877   // WARNING - on Windows Java Natives use pascal calling convention and pop the
1878   // arguments off of the stack. We could just re-adjust the stack pointer here
1879   // and continue to do SP relative addressing but we instead switch to FP
1880   // relative addressing.
1881 
1882   // Unpack native results.
1883   switch (ret_type) {
1884   case T_BOOLEAN: __ c2bool(rax);            break;
1885   case T_CHAR   : __ andptr(rax, 0xFFFF);    break;
1886   case T_BYTE   : __ sign_extend_byte (rax); break;
1887   case T_SHORT  : __ sign_extend_short(rax); break;
1888   case T_INT    : /* nothing to do */        break;
1889   case T_DOUBLE :
1890   case T_FLOAT  :
1891     // Result is in st0 we'll save as needed
1892     break;
1893   case T_ARRAY:                 // Really a handle

1894   case T_OBJECT:                // Really a handle
1895       break; // can't de-handlize until after safepoint check
1896   case T_VOID: break;
1897   case T_LONG: break;
1898   default       : ShouldNotReachHere();
1899   }
1900 
1901   Label after_transition;
1902 
1903   // If this is a critical native, check for a safepoint or suspend request after the call.
1904   // If a safepoint is needed, transition to native, then to native_trans to handle
1905   // safepoints like the native methods that are not critical natives.
1906   if (is_critical_native) {
1907     Label needs_safepoint;
1908     __ safepoint_poll(needs_safepoint, thread, false /* at_return */, false /* in_nmethod */);
1909     __ cmpl(Address(thread, JavaThread::suspend_flags_offset()), 0);
1910     __ jcc(Assembler::equal, after_transition);
1911     __ bind(needs_safepoint);
1912   }
1913 

2968   __ bind(pending);
2969 
2970   RegisterSaver::restore_live_registers(masm);
2971 
2972   // exception pending => remove activation and forward to exception handler
2973 
2974   __ get_thread(thread);
2975   __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
2976   __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
2977   __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2978 
2979   // -------------
2980   // make sure all code is generated
2981   masm->flush();
2982 
2983   // return the  blob
2984   // frame_size_words or bytes??
2985   return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
2986 }
2987 





2988 #ifdef COMPILER2
2989 RuntimeStub* SharedRuntime::make_native_invoker(address call_target,
2990                                                 int shadow_space_bytes,
2991                                                 const GrowableArray<VMReg>& input_registers,
2992                                                 const GrowableArray<VMReg>& output_registers) {
2993   ShouldNotCallThis();
2994   return nullptr;
2995 }
2996 #endif

 465       else if( freg_arg1 == fltarg_flt_dbl ) freg_arg1 = i;
 466       else // Else double is passed low on the stack to be aligned.
 467         stack += 2;
 468     } else if( sig_bt[i] == T_LONG ) {
 469       stack += 2;
 470     }
 471   }
 472   int dstack = 0;             // Separate counter for placing doubles
 473 
 474   // Now pick where all else goes.
 475   for( i = 0; i < total_args_passed; i++) {
 476     // From the type and the argument number (count) compute the location
 477     switch( sig_bt[i] ) {
 478     case T_SHORT:
 479     case T_CHAR:
 480     case T_BYTE:
 481     case T_BOOLEAN:
 482     case T_INT:
 483     case T_ARRAY:
 484     case T_OBJECT:
 485     case T_INLINE_TYPE:
 486     case T_ADDRESS:
 487       if( reg_arg0 == 9999 )  {
 488         reg_arg0 = i;
 489         regs[i].set1(rcx->as_VMReg());
 490       } else if( reg_arg1 == 9999 )  {
 491         reg_arg1 = i;
 492         regs[i].set1(rdx->as_VMReg());
 493       } else {
 494         regs[i].set1(VMRegImpl::stack2reg(stack++));
 495       }
 496       break;
 497     case T_FLOAT:
 498       if( freg_arg0 == fltarg_flt_dbl || freg_arg0 == fltarg_float_only ) {
 499         freg_arg0 = i;
 500         regs[i].set1(xmm0->as_VMReg());
 501       } else if( freg_arg1 == fltarg_flt_dbl || freg_arg1 == fltarg_float_only ) {
 502         freg_arg1 = i;
 503         regs[i].set1(xmm1->as_VMReg());
 504       } else {
 505         regs[i].set1(VMRegImpl::stack2reg(stack++));

 516         regs[i].set2(xmm0->as_VMReg());
 517       } else if( freg_arg1 == (uint)i ) {
 518         regs[i].set2(xmm1->as_VMReg());
 519       } else {
 520         regs[i].set2(VMRegImpl::stack2reg(dstack));
 521         dstack += 2;
 522       }
 523       break;
 524     case T_VOID: regs[i].set_bad(); break;
 525       break;
 526     default:
 527       ShouldNotReachHere();
 528       break;
 529     }
 530   }
 531 
 532   // return value can be odd number of VMRegImpl stack slots make multiple of 2
 533   return align_up(stack, 2);
 534 }
 535 
 536 const uint SharedRuntime::java_return_convention_max_int = 1;
 537 const uint SharedRuntime::java_return_convention_max_float = 1;
 538 int SharedRuntime::java_return_convention(const BasicType *sig_bt,
 539                                           VMRegPair *regs,
 540                                           int total_args_passed) {
 541   Unimplemented();
 542   return 0;
 543 }
 544 
 545 // Patch the callers callsite with entry to compiled code if it exists.
 546 static void patch_callers_callsite(MacroAssembler *masm) {
 547   Label L;
 548   __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
 549   __ jcc(Assembler::equal, L);
 550   // Schedule the branch target address early.
 551   // Call into the VM to patch the caller, then jump to compiled callee
 552   // rax, isn't live so capture return address while we easily can
 553   __ movptr(rax, Address(rsp, 0));
 554   __ pusha();
 555   __ pushf();
 556 
 557   if (UseSSE == 1) {
 558     __ subptr(rsp, 2*wordSize);
 559     __ movflt(Address(rsp, 0), xmm0);
 560     __ movflt(Address(rsp, wordSize), xmm1);
 561   }
 562   if (UseSSE >= 2) {
 563     __ subptr(rsp, 4*wordSize);
 564     __ movdbl(Address(rsp, 0), xmm0);

 586     __ addptr(rsp, 2*wordSize);
 587   }
 588   if (UseSSE >= 2) {
 589     __ movdbl(xmm0, Address(rsp, 0));
 590     __ movdbl(xmm1, Address(rsp, 2*wordSize));
 591     __ addptr(rsp, 4*wordSize);
 592   }
 593 
 594   __ popf();
 595   __ popa();
 596   __ bind(L);
 597 }
 598 
 599 
 600 static void move_c2i_double(MacroAssembler *masm, XMMRegister r, int st_off) {
 601   int next_off = st_off - Interpreter::stackElementSize;
 602   __ movdbl(Address(rsp, next_off), r);
 603 }
 604 
 605 static void gen_c2i_adapter(MacroAssembler *masm,
 606                             const GrowableArray<SigEntry>& sig_extended,


 607                             const VMRegPair *regs,
 608                             Label& skip_fixup,
 609                             address start,
 610                             OopMapSet*& oop_maps,
 611                             int& frame_complete,
 612                             int& frame_size_in_words) {
 613   // Before we get into the guts of the C2I adapter, see if we should be here
 614   // at all.  We've come from compiled code and are attempting to jump to the
 615   // interpreter, which means the caller made a static call to get here
 616   // (vcalls always get a compiled target if there is one).  Check for a
 617   // compiled target.  If there is one, we need to patch the caller's call.
 618   patch_callers_callsite(masm);
 619 
 620   __ bind(skip_fixup);
 621 
 622 #ifdef COMPILER2
 623   // C2 may leave the stack dirty if not in SSE2+ mode
 624   if (UseSSE >= 2) {
 625     __ verify_FPU(0, "c2i transition should have clean FPU stack");
 626   } else {
 627     __ empty_FPU_stack();
 628   }
 629 #endif /* COMPILER2 */
 630 
 631   // Since all args are passed on the stack, total_args_passed * interpreter_
 632   // stack_element_size  is the
 633   // space we need.
 634   int extraspace = sig_extended.length() * Interpreter::stackElementSize;
 635 
 636   // Get return address
 637   __ pop(rax);
 638 
 639   // set senderSP value
 640   __ movptr(rsi, rsp);
 641 
 642   __ subptr(rsp, extraspace);
 643 
 644   // Now write the args into the outgoing interpreter space
 645   for (int i = 0; i < sig_extended.length(); i++) {
 646     if (sig_extended.at(i)._bt == T_VOID) {
 647       assert(i > 0 && (sig_extended.at(i-1)._bt == T_LONG || sig_extended.at(i-1)._bt == T_DOUBLE), "missing half");
 648       continue;
 649     }
 650 
 651     // st_off points to lowest address on stack.
 652     int st_off = ((sig_extended.length() - 1) - i) * Interpreter::stackElementSize;
 653     int next_off = st_off - Interpreter::stackElementSize;
 654 
 655     // Say 4 args:
 656     // i   st_off
 657     // 0   12 T_LONG
 658     // 1    8 T_VOID
 659     // 2    4 T_OBJECT
 660     // 3    0 T_BOOL
 661     VMReg r_1 = regs[i].first();
 662     VMReg r_2 = regs[i].second();
 663     if (!r_1->is_valid()) {
 664       assert(!r_2->is_valid(), "");
 665       continue;
 666     }
 667 
 668     if (r_1->is_stack()) {
 669       // memory to memory use fpu stack top
 670       int ld_off = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
 671 
 672       if (!r_2->is_valid()) {

 682 #ifndef _LP64
 683         __ movptr(rdi, Address(rsp, ld_off + wordSize));
 684         __ movptr(Address(rsp, st_off), rdi);
 685 #else
 686 #ifdef ASSERT
 687         // Overwrite the unused slot with known junk
 688         __ mov64(rax, CONST64(0xdeadffffdeadaaaa));
 689         __ movptr(Address(rsp, st_off), rax);
 690 #endif /* ASSERT */
 691 #endif // _LP64
 692       }
 693     } else if (r_1->is_Register()) {
 694       Register r = r_1->as_Register();
 695       if (!r_2->is_valid()) {
 696         __ movl(Address(rsp, st_off), r);
 697       } else {
 698         // long/double in gpr
 699         NOT_LP64(ShouldNotReachHere());
 700         // Two VMRegs can be T_OBJECT, T_ADDRESS, T_DOUBLE, T_LONG
 701         // T_DOUBLE and T_LONG use two slots in the interpreter
 702         if (sig_extended.at(i)._bt == T_LONG || sig_extended.at(i)._bt == T_DOUBLE) {
 703           // long/double in gpr
 704 #ifdef ASSERT
 705           // Overwrite the unused slot with known junk
 706           LP64_ONLY(__ mov64(rax, CONST64(0xdeadffffdeadaaab)));
 707           __ movptr(Address(rsp, st_off), rax);
 708 #endif /* ASSERT */
 709           __ movptr(Address(rsp, next_off), r);
 710         } else {
 711           __ movptr(Address(rsp, st_off), r);
 712         }
 713       }
 714     } else {
 715       assert(r_1->is_XMMRegister(), "");
 716       if (!r_2->is_valid()) {
 717         __ movflt(Address(rsp, st_off), r_1->as_XMMRegister());
 718       } else {
 719         assert(sig_extended.at(i)._bt == T_DOUBLE || sig_extended.at(i)._bt == T_LONG, "wrong type");
 720         move_c2i_double(masm, r_1->as_XMMRegister(), st_off);
 721       }
 722     }
 723   }
 724 
 725   // Schedule the branch target address early.
 726   __ movptr(rcx, Address(rbx, in_bytes(Method::interpreter_entry_offset())));
 727   // And repush original return address
 728   __ push(rax);
 729   __ jmp(rcx);
 730 }
 731 
 732 
 733 static void move_i2c_double(MacroAssembler *masm, XMMRegister r, Register saved_sp, int ld_off) {
 734   int next_val_off = ld_off - Interpreter::stackElementSize;
 735   __ movdbl(r, Address(saved_sp, next_val_off));
 736 }
 737 
 738 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg,
 739                         address code_start, address code_end,
 740                         Label& L_ok) {
 741   Label L_fail;
 742   __ lea(temp_reg, ExternalAddress(code_start));
 743   __ cmpptr(pc_reg, temp_reg);
 744   __ jcc(Assembler::belowEqual, L_fail);
 745   __ lea(temp_reg, ExternalAddress(code_end));
 746   __ cmpptr(pc_reg, temp_reg);
 747   __ jcc(Assembler::below, L_ok);
 748   __ bind(L_fail);
 749 }
 750 
 751 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,

 752                                     int comp_args_on_stack,
 753                                     const GrowableArray<SigEntry>& sig_extended,
 754                                     const VMRegPair *regs) {
 755 
 756   // Note: rsi contains the senderSP on entry. We must preserve it since
 757   // we may do a i2c -> c2i transition if we lose a race where compiled
 758   // code goes non-entrant while we get args ready.
 759 
 760   // Adapters can be frameless because they do not require the caller
 761   // to perform additional cleanup work, such as correcting the stack pointer.
 762   // An i2c adapter is frameless because the *caller* frame, which is interpreted,
 763   // routinely repairs its own stack pointer (from interpreter_frame_last_sp),
 764   // even if a callee has modified the stack pointer.
 765   // A c2i adapter is frameless because the *callee* frame, which is interpreted,
 766   // routinely repairs its caller's stack pointer (from sender_sp, which is set
 767   // up via the senderSP register).
 768   // In other words, if *either* the caller or callee is interpreted, we can
 769   // get the stack pointer repaired after a call.
 770   // This is why c2i and i2c adapters cannot be indefinitely composed.
 771   // In particular, if a c2i adapter were to somehow call an i2c adapter,
 772   // both caller and callee would be compiled methods, and neither would
 773   // clean up the stack pointer changes performed by the two adapters.
 774   // If this happens, control eventually transfers back to the compiled
 775   // caller, but with an uncorrected stack, causing delayed havoc.

 824   }
 825 
 826   // Align the outgoing SP
 827   __ andptr(rsp, -(StackAlignmentInBytes));
 828 
 829   // push the return address on the stack (note that pushing, rather
 830   // than storing it, yields the correct frame alignment for the callee)
 831   __ push(rax);
 832 
 833   // Put saved SP in another register
 834   const Register saved_sp = rax;
 835   __ movptr(saved_sp, rdi);
 836 
 837 
 838   // Will jump to the compiled code just as if compiled code was doing it.
 839   // Pre-load the register-jump target early, to schedule it better.
 840   __ movptr(rdi, Address(rbx, in_bytes(Method::from_compiled_offset())));
 841 
 842   // Now generate the shuffle code.  Pick up all register args and move the
 843   // rest through the floating point stack top.
 844   for (int i = 0; i < sig_extended.length(); i++) {
 845     if (sig_extended.at(i)._bt == T_VOID) {
 846       // Longs and doubles are passed in native word order, but misaligned
 847       // in the 32-bit build.
 848       assert(i > 0 && (sig_extended.at(i-1)._bt == T_LONG || sig_extended.at(i-1)._bt == T_DOUBLE), "missing half");
 849       continue;
 850     }
 851 
 852     // Pick up 0, 1 or 2 words from SP+offset.
 853 
 854     assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(),
 855             "scrambled load targets?");
 856     // Load in argument order going down.
 857     int ld_off = (sig_extended.length() - i) * Interpreter::stackElementSize;
 858     // Point to interpreter value (vs. tag)
 859     int next_off = ld_off - Interpreter::stackElementSize;
 860     //
 861     //
 862     //
 863     VMReg r_1 = regs[i].first();
 864     VMReg r_2 = regs[i].second();
 865     if (!r_1->is_valid()) {
 866       assert(!r_2->is_valid(), "");
 867       continue;
 868     }
 869     if (r_1->is_stack()) {
 870       // Convert stack slot to an SP offset (+ wordSize to account for return address )
 871       int st_off = regs[i].first()->reg2stack()*VMRegImpl::stack_slot_size + wordSize;
 872 
 873       // We can use rsi as a temp here because compiled code doesn't need rsi as an input
 874       // and if we end up going thru a c2i because of a miss a reasonable value of rsi
 875       // we be generated.
 876       if (!r_2->is_valid()) {
 877         // __ fld_s(Address(saved_sp, ld_off));
 878         // __ fstp_s(Address(rsp, st_off));
 879         __ movl(rsi, Address(saved_sp, ld_off));
 880         __ movptr(Address(rsp, st_off), rsi);
 881       } else {
 882         // Interpreter local[n] == MSW, local[n+1] == LSW however locals
 883         // are accessed as negative so LSW is at LOW address
 884 
 885         // ld_off is MSW so get LSW
 886         // st_off is LSW (i.e. reg.first())
 887         // __ fld_d(Address(saved_sp, next_off));
 888         // __ fstp_d(Address(rsp, st_off));
 889         //
 890         // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
 891         // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
 892         // So we must adjust where to pick up the data to match the interpreter.
 893         //
 894         // Interpreter local[n] == MSW, local[n+1] == LSW however locals
 895         // are accessed as negative so LSW is at LOW address
 896 
 897         // ld_off is MSW so get LSW
 898         const int offset = (NOT_LP64(true ||) sig_extended.at(i)._bt==T_LONG||sig_extended.at(i)._bt==T_DOUBLE)?
 899                            next_off : ld_off;
 900         __ movptr(rsi, Address(saved_sp, offset));
 901         __ movptr(Address(rsp, st_off), rsi);
 902 #ifndef _LP64
 903         __ movptr(rsi, Address(saved_sp, ld_off));
 904         __ movptr(Address(rsp, st_off + wordSize), rsi);
 905 #endif // _LP64
 906       }
 907     } else if (r_1->is_Register()) {  // Register argument
 908       Register r = r_1->as_Register();
 909       assert(r != rax, "must be different");
 910       if (r_2->is_valid()) {
 911         //
 912         // We are using two VMRegs. This can be either T_OBJECT, T_ADDRESS, T_LONG, or T_DOUBLE
 913         // the interpreter allocates two slots but only uses one for thr T_LONG or T_DOUBLE case
 914         // So we must adjust where to pick up the data to match the interpreter.
 915 
 916         const int offset = (NOT_LP64(true ||) sig_extended.at(i)._bt==T_LONG||sig_extended.at(i)._bt==T_DOUBLE)?
 917                            next_off : ld_off;
 918 
 919         // this can be a misaligned move
 920         __ movptr(r, Address(saved_sp, offset));
 921 #ifndef _LP64
 922         assert(r_2->as_Register() != rax, "need another temporary register");
 923         // Remember r_1 is low address (and LSB on x86)
 924         // So r_2 gets loaded from high address regardless of the platform
 925         __ movptr(r_2->as_Register(), Address(saved_sp, ld_off));
 926 #endif // _LP64
 927       } else {
 928         __ movl(r, Address(saved_sp, ld_off));
 929       }
 930     } else {
 931       assert(r_1->is_XMMRegister(), "");
 932       if (!r_2->is_valid()) {
 933         __ movflt(r_1->as_XMMRegister(), Address(saved_sp, ld_off));
 934       } else {
 935         move_i2c_double(masm, r_1->as_XMMRegister(), saved_sp, ld_off);
 936       }

 944   // "compiled" so it is much better to make this transition
 945   // invisible to the stack walking code. Unfortunately if
 946   // we try and find the callee by normal means a safepoint
 947   // is possible. So we stash the desired callee in the thread
 948   // and the vm will find there should this case occur.
 949 
 950   __ get_thread(rax);
 951   __ movptr(Address(rax, JavaThread::callee_target_offset()), rbx);
 952 
 953   // move Method* to rax, in case we end up in an c2i adapter.
 954   // the c2i adapters expect Method* in rax, (c2) because c2's
 955   // resolve stubs return the result (the method) in rax,.
 956   // I'd love to fix this.
 957   __ mov(rax, rbx);
 958 
 959   __ jmp(rdi);
 960 }
 961 
 962 // ---------------------------------------------------------------
 963 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,

 964                                                             int comp_args_on_stack,
 965                                                             const GrowableArray<SigEntry>& sig_extended,
 966                                                             const VMRegPair *regs,
 967                                                             AdapterFingerPrint* fingerprint,
 968                                                             AdapterBlob*& new_adapter) {
 969   address i2c_entry = __ pc();
 970 
 971   gen_i2c_adapter(masm, comp_args_on_stack, sig_extended, regs);
 972 
 973   // -------------------------------------------------------------------------
 974   // Generate a C2I adapter.  On entry we know rbx, holds the Method* during calls
 975   // to the interpreter.  The args start out packed in the compiled layout.  They
 976   // need to be unpacked into the interpreter layout.  This will almost always
 977   // require some stack space.  We grow the current (compiled) stack, then repack
 978   // the args.  We  finally end in a jump to the generic interpreter entry point.
 979   // On exit from the interpreter, the interpreter will restore our SP (lest the
 980   // compiled code, which relys solely on SP and not EBP, get sick).
 981 
 982   address c2i_unverified_entry = __ pc();
 983   Label skip_fixup;
 984 
 985   Register holder = rax;
 986   Register receiver = rcx;
 987   Register temp = rbx;
 988 
 989   {
 990 
 991     Label missed;
 992     __ movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
 993     __ cmpptr(temp, Address(holder, CompiledICHolder::holder_klass_offset()));
 994     __ movptr(rbx, Address(holder, CompiledICHolder::holder_metadata_offset()));
 995     __ jcc(Assembler::notEqual, missed);
 996     // Method might have been compiled since the call site was patched to
 997     // interpreted if that is the case treat it as a miss so we can get
 998     // the call site corrected.
 999     __ cmpptr(Address(rbx, in_bytes(Method::code_offset())), (int32_t)NULL_WORD);
1000     __ jcc(Assembler::equal, skip_fixup);
1001 
1002     __ bind(missed);
1003     __ jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1004   }
1005 
1006   address c2i_entry = __ pc();
1007 
1008   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
1009   bs->c2i_entry_barrier(masm);
1010 
1011   OopMapSet* oop_maps = NULL;
1012   int frame_complete = CodeOffsets::frame_never_safe;
1013   int frame_size_in_words = 0;
1014   gen_c2i_adapter(masm, sig_extended, regs, skip_fixup, i2c_entry, oop_maps, frame_complete, frame_size_in_words);
1015 
1016   __ flush();
1017   new_adapter = AdapterBlob::create(masm->code(), frame_complete, frame_size_in_words, oop_maps);
1018   return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
1019 }
1020 
1021 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1022                                          VMRegPair *regs,
1023                                          VMRegPair *regs2,
1024                                          int total_args_passed) {
1025   assert(regs2 == NULL, "not needed on x86");
1026 // We return the amount of VMRegImpl stack slots we need to reserve for all
1027 // the arguments NOT counting out_preserve_stack_slots.
1028 
1029   uint    stack = 0;        // All arguments on stack
1030 
1031   for( int i = 0; i < total_args_passed; i++) {
1032     // From the type and the argument number (count) compute the location
1033     switch( sig_bt[i] ) {
1034     case T_BOOLEAN:
1035     case T_CHAR:
1036     case T_FLOAT:
1037     case T_BYTE:
1038     case T_SHORT:
1039     case T_INT:
1040     case T_OBJECT:
1041     case T_INLINE_TYPE:
1042     case T_ARRAY:
1043     case T_ADDRESS:
1044     case T_METADATA:
1045       regs[i].set1(VMRegImpl::stack2reg(stack++));
1046       break;
1047     case T_LONG:
1048     case T_DOUBLE: // The stack numbering is reversed from Java
1049       // Since C arguments do not get reversed, the ordering for
1050       // doubles on the stack must be opposite the Java convention
1051       assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
1052       regs[i].set2(VMRegImpl::stack2reg(stack));
1053       stack += 2;
1054       break;
1055     case T_VOID: regs[i].set_bad(); break;
1056     default:
1057       ShouldNotReachHere();
1058       break;
1059     }
1060   }
1061   return stack;

1720   // caller.
1721   //
1722   OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1723 
1724   // Mark location of rbp,
1725   // map->set_callee_saved(VMRegImpl::stack2reg( stack_slots - 2), stack_slots * 2, 0, rbp->as_VMReg());
1726 
1727   // We know that we only have args in at most two integer registers (rcx, rdx). So rax, rbx
1728   // Are free to temporaries if we have to do  stack to steck moves.
1729   // All inbound args are referenced based on rbp, and all outbound args via rsp.
1730 
1731   for (int i = 0; i < total_in_args ; i++, c_arg++ ) {
1732     switch (in_sig_bt[i]) {
1733       case T_ARRAY:
1734         if (is_critical_native) {
1735           VMRegPair in_arg = in_regs[i];
1736           unpack_array_argument(masm, in_arg, in_elem_bt[i], out_regs[c_arg + 1], out_regs[c_arg]);
1737           c_arg++;
1738           break;
1739         }
1740       case T_INLINE_TYPE:
1741       case T_OBJECT:
1742         assert(!is_critical_native, "no oop arguments");
1743         object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
1744                     ((i == 0) && (!is_static)),
1745                     &receiver_offset);
1746         break;
1747       case T_VOID:
1748         break;
1749 
1750       case T_FLOAT:
1751         float_move(masm, in_regs[i], out_regs[c_arg]);
1752           break;
1753 
1754       case T_DOUBLE:
1755         assert( i + 1 < total_in_args &&
1756                 in_sig_bt[i + 1] == T_VOID &&
1757                 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
1758         double_move(masm, in_regs[i], out_regs[c_arg]);
1759         break;
1760 

1892   // Verify or restore cpu control state after JNI call
1893   __ restore_cpu_control_state_after_jni();
1894 
1895   // WARNING - on Windows Java Natives use pascal calling convention and pop the
1896   // arguments off of the stack. We could just re-adjust the stack pointer here
1897   // and continue to do SP relative addressing but we instead switch to FP
1898   // relative addressing.
1899 
1900   // Unpack native results.
1901   switch (ret_type) {
1902   case T_BOOLEAN: __ c2bool(rax);            break;
1903   case T_CHAR   : __ andptr(rax, 0xFFFF);    break;
1904   case T_BYTE   : __ sign_extend_byte (rax); break;
1905   case T_SHORT  : __ sign_extend_short(rax); break;
1906   case T_INT    : /* nothing to do */        break;
1907   case T_DOUBLE :
1908   case T_FLOAT  :
1909     // Result is in st0 we'll save as needed
1910     break;
1911   case T_ARRAY:                 // Really a handle
1912   case T_INLINE_TYPE:           // Really a handle
1913   case T_OBJECT:                // Really a handle
1914       break; // can't de-handlize until after safepoint check
1915   case T_VOID: break;
1916   case T_LONG: break;
1917   default       : ShouldNotReachHere();
1918   }
1919 
1920   Label after_transition;
1921 
1922   // If this is a critical native, check for a safepoint or suspend request after the call.
1923   // If a safepoint is needed, transition to native, then to native_trans to handle
1924   // safepoints like the native methods that are not critical natives.
1925   if (is_critical_native) {
1926     Label needs_safepoint;
1927     __ safepoint_poll(needs_safepoint, thread, false /* at_return */, false /* in_nmethod */);
1928     __ cmpl(Address(thread, JavaThread::suspend_flags_offset()), 0);
1929     __ jcc(Assembler::equal, after_transition);
1930     __ bind(needs_safepoint);
1931   }
1932 

2987   __ bind(pending);
2988 
2989   RegisterSaver::restore_live_registers(masm);
2990 
2991   // exception pending => remove activation and forward to exception handler
2992 
2993   __ get_thread(thread);
2994   __ movptr(Address(thread, JavaThread::vm_result_offset()), NULL_WORD);
2995   __ movptr(rax, Address(thread, Thread::pending_exception_offset()));
2996   __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
2997 
2998   // -------------
2999   // make sure all code is generated
3000   masm->flush();
3001 
3002   // return the  blob
3003   // frame_size_words or bytes??
3004   return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
3005 }
3006 
3007 BufferedInlineTypeBlob* SharedRuntime::generate_buffered_inline_type_adapter(const InlineKlass* vk) {
3008   Unimplemented();
3009   return NULL;
3010 }
3011 
3012 #ifdef COMPILER2
3013 RuntimeStub* SharedRuntime::make_native_invoker(address call_target,
3014                                                 int shadow_space_bytes,
3015                                                 const GrowableArray<VMReg>& input_registers,
3016                                                 const GrowableArray<VMReg>& output_registers) {
3017   ShouldNotCallThis();
3018   return nullptr;
3019 }
3020 #endif
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