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src/hotspot/cpu/x86/x86.ad

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 2709 
 2710   uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
 2711     return MachNode::size(ra_);
 2712   }
 2713 
 2714 %}
 2715 
 2716 encode %{
 2717 
 2718   enc_class call_epilog %{
 2719     if (VerifyStackAtCalls) {
 2720       // Check that stack depth is unchanged: find majik cookie on stack
 2721       int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
 2722       Label L;
 2723       __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
 2724       __ jccb(Assembler::equal, L);
 2725       // Die if stack mismatch
 2726       __ int3();
 2727       __ bind(L);
 2728     }

































 2729   %}
 2730 
 2731 %}
 2732 
 2733 // Operands for bound floating pointer register arguments
 2734 operand rxmm0() %{
 2735   constraint(ALLOC_IN_RC(xmm0_reg));
 2736   match(VecX);
 2737   format%{%}
 2738   interface(REG_INTER);
 2739 %}
 2740 
 2741 //----------OPERANDS-----------------------------------------------------------
 2742 // Operand definitions must precede instruction definitions for correct parsing
 2743 // in the ADLC because operands constitute user defined types which are used in
 2744 // instruction definitions.
 2745 
 2746 // Vectors
 2747 
 2748 // Dummy generic vector class. Should be used for all vector operands.

 2709 
 2710   uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
 2711     return MachNode::size(ra_);
 2712   }
 2713 
 2714 %}
 2715 
 2716 encode %{
 2717 
 2718   enc_class call_epilog %{
 2719     if (VerifyStackAtCalls) {
 2720       // Check that stack depth is unchanged: find majik cookie on stack
 2721       int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
 2722       Label L;
 2723       __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
 2724       __ jccb(Assembler::equal, L);
 2725       // Die if stack mismatch
 2726       __ int3();
 2727       __ bind(L);
 2728     }
 2729     if (tf()->returns_inline_type_as_fields() && !_method->is_method_handle_intrinsic()) {
 2730       // The last return value is not set by the callee but used to pass IsInit information to compiled code.
 2731       // Search for the corresponding projection, get the register and emit code that initialized it.
 2732       uint con = (tf()->range_cc()->cnt() - 1);
 2733       for (DUIterator_Fast imax, i = fast_outs(imax); i < imax; i++) {
 2734         ProjNode* proj = fast_out(i)->as_Proj();
 2735         if (proj->_con == con) {
 2736           // Set IsInit if rax is non-null (a non-null value is returned buffered or scalarized)
 2737           OptoReg::Name optoReg = ra_->get_reg_first(proj);
 2738           VMReg reg = OptoReg::as_VMReg(optoReg, ra_->_framesize, OptoReg::reg2stack(ra_->_matcher._new_SP));
 2739           Register toReg = reg->is_reg() ? reg->as_Register() : rscratch1;
 2740           __ testq(rax, rax);
 2741           __ setb(Assembler::notZero, toReg);
 2742           __ movzbl(toReg, toReg);
 2743           if (reg->is_stack()) {
 2744             int st_off = reg->reg2stack() * VMRegImpl::stack_slot_size;
 2745             __ movq(Address(rsp, st_off), toReg);
 2746           }
 2747           break;
 2748         }
 2749       }
 2750       if (return_value_is_used()) {
 2751         // An inline type is returned as fields in multiple registers.
 2752         // Rax either contains an oop if the inline type is buffered or a pointer
 2753         // to the corresponding InlineKlass with the lowest bit set to 1. Zero rax
 2754         // if the lowest bit is set to allow C2 to use the oop after null checking.
 2755         // rax &= (rax & 1) - 1
 2756         __ movptr(rscratch1, rax);
 2757         __ andptr(rscratch1, 0x1);
 2758         __ subptr(rscratch1, 0x1);
 2759         __ andptr(rax, rscratch1);
 2760       }
 2761     }
 2762   %}
 2763 
 2764 %}
 2765 
 2766 // Operands for bound floating pointer register arguments
 2767 operand rxmm0() %{
 2768   constraint(ALLOC_IN_RC(xmm0_reg));
 2769   match(VecX);
 2770   format%{%}
 2771   interface(REG_INTER);
 2772 %}
 2773 
 2774 //----------OPERANDS-----------------------------------------------------------
 2775 // Operand definitions must precede instruction definitions for correct parsing
 2776 // in the ADLC because operands constitute user defined types which are used in
 2777 // instruction definitions.
 2778 
 2779 // Vectors
 2780 
 2781 // Dummy generic vector class. Should be used for all vector operands.
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