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src/hotspot/cpu/x86/x86.ad

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2564   uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
2565     return MachNode::size(ra_);
2566   }
2567 
2568 %}
2569 
2570 encode %{
2571 
2572   enc_class call_epilog %{
2573     if (VerifyStackAtCalls) {
2574       // Check that stack depth is unchanged: find majik cookie on stack
2575       int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
2576       C2_MacroAssembler _masm(&cbuf);
2577       Label L;
2578       __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
2579       __ jccb(Assembler::equal, L);
2580       // Die if stack mismatch
2581       __ int3();
2582       __ bind(L);
2583     }












2584   %}
2585 
2586 %}
2587 
2588 // Operands for bound floating pointer register arguments
2589 operand rxmm0() %{
2590   constraint(ALLOC_IN_RC(xmm0_reg));
2591   match(VecX);
2592   format%{%}
2593   interface(REG_INTER);
2594 %}
2595 
2596 //----------OPERANDS-----------------------------------------------------------
2597 // Operand definitions must precede instruction definitions for correct parsing
2598 // in the ADLC because operands constitute user defined types which are used in
2599 // instruction definitions.
2600 
2601 // Vectors
2602 
2603 // Dummy generic vector class. Should be used for all vector operands.

2564   uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
2565     return MachNode::size(ra_);
2566   }
2567 
2568 %}
2569 
2570 encode %{
2571 
2572   enc_class call_epilog %{
2573     if (VerifyStackAtCalls) {
2574       // Check that stack depth is unchanged: find majik cookie on stack
2575       int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
2576       C2_MacroAssembler _masm(&cbuf);
2577       Label L;
2578       __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
2579       __ jccb(Assembler::equal, L);
2580       // Die if stack mismatch
2581       __ int3();
2582       __ bind(L);
2583     }
2584     if (tf()->returns_inline_type_as_fields() && !_method->is_method_handle_intrinsic() && return_value_is_used()) {
2585       // An inline type is returned as fields in multiple registers.
2586       // Rax either contains an oop if the inline type is buffered or a pointer
2587       // to the corresponding InlineKlass with the lowest bit set to 1. Zero rax
2588       // if the lowest bit is set to allow C2 to use the oop after null checking.
2589       // rax &= (rax & 1) - 1
2590       C2_MacroAssembler _masm(&cbuf);
2591       __ movptr(rscratch1, rax);
2592       __ andptr(rscratch1, 0x1);
2593       __ subptr(rscratch1, 0x1);
2594       __ andptr(rax, rscratch1);
2595     }
2596   %}
2597 
2598 %}
2599 
2600 // Operands for bound floating pointer register arguments
2601 operand rxmm0() %{
2602   constraint(ALLOC_IN_RC(xmm0_reg));
2603   match(VecX);
2604   format%{%}
2605   interface(REG_INTER);
2606 %}
2607 
2608 //----------OPERANDS-----------------------------------------------------------
2609 // Operand definitions must precede instruction definitions for correct parsing
2610 // in the ADLC because operands constitute user defined types which are used in
2611 // instruction definitions.
2612 
2613 // Vectors
2614 
2615 // Dummy generic vector class. Should be used for all vector operands.
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