2701
2702 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
2703 return MachNode::size(ra_);
2704 }
2705
2706 %}
2707
2708 encode %{
2709
2710 enc_class call_epilog %{
2711 if (VerifyStackAtCalls) {
2712 // Check that stack depth is unchanged: find majik cookie on stack
2713 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
2714 Label L;
2715 __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
2716 __ jccb(Assembler::equal, L);
2717 // Die if stack mismatch
2718 __ int3();
2719 __ bind(L);
2720 }
2721 %}
2722
2723 %}
2724
2725 // Operands for bound floating pointer register arguments
2726 operand rxmm0() %{
2727 constraint(ALLOC_IN_RC(xmm0_reg));
2728 match(VecX);
2729 format%{%}
2730 interface(REG_INTER);
2731 %}
2732
2733 //----------OPERANDS-----------------------------------------------------------
2734 // Operand definitions must precede instruction definitions for correct parsing
2735 // in the ADLC because operands constitute user defined types which are used in
2736 // instruction definitions.
2737
2738 // Vectors
2739
2740 // Dummy generic vector class. Should be used for all vector operands.
|
2701
2702 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
2703 return MachNode::size(ra_);
2704 }
2705
2706 %}
2707
2708 encode %{
2709
2710 enc_class call_epilog %{
2711 if (VerifyStackAtCalls) {
2712 // Check that stack depth is unchanged: find majik cookie on stack
2713 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
2714 Label L;
2715 __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
2716 __ jccb(Assembler::equal, L);
2717 // Die if stack mismatch
2718 __ int3();
2719 __ bind(L);
2720 }
2721 if (tf()->returns_inline_type_as_fields() && !_method->is_method_handle_intrinsic()) {
2722 // The last return value is not set by the callee but used to pass IsInit information to compiled code.
2723 // Search for the corresponding projection, get the register and emit code that initialized it.
2724 uint con = (tf()->range_cc()->cnt() - 1);
2725 for (DUIterator_Fast imax, i = fast_outs(imax); i < imax; i++) {
2726 ProjNode* proj = fast_out(i)->as_Proj();
2727 if (proj->_con == con) {
2728 // Set IsInit if rax is non-null (a non-null value is returned buffered or scalarized)
2729 OptoReg::Name optoReg = ra_->get_reg_first(proj);
2730 VMReg reg = OptoReg::as_VMReg(optoReg, ra_->_framesize, OptoReg::reg2stack(ra_->_matcher._new_SP));
2731 Register toReg = reg->is_reg() ? reg->as_Register() : rscratch1;
2732 __ testq(rax, rax);
2733 __ setb(Assembler::notZero, toReg);
2734 __ movzbl(toReg, toReg);
2735 if (reg->is_stack()) {
2736 int st_off = reg->reg2stack() * VMRegImpl::stack_slot_size;
2737 __ movq(Address(rsp, st_off), toReg);
2738 }
2739 break;
2740 }
2741 }
2742 if (return_value_is_used()) {
2743 // An inline type is returned as fields in multiple registers.
2744 // Rax either contains an oop if the inline type is buffered or a pointer
2745 // to the corresponding InlineKlass with the lowest bit set to 1. Zero rax
2746 // if the lowest bit is set to allow C2 to use the oop after null checking.
2747 // rax &= (rax & 1) - 1
2748 __ movptr(rscratch1, rax);
2749 __ andptr(rscratch1, 0x1);
2750 __ subptr(rscratch1, 0x1);
2751 __ andptr(rax, rscratch1);
2752 }
2753 }
2754 %}
2755
2756 %}
2757
2758 // Operands for bound floating pointer register arguments
2759 operand rxmm0() %{
2760 constraint(ALLOC_IN_RC(xmm0_reg));
2761 match(VecX);
2762 format%{%}
2763 interface(REG_INTER);
2764 %}
2765
2766 //----------OPERANDS-----------------------------------------------------------
2767 // Operand definitions must precede instruction definitions for correct parsing
2768 // in the ADLC because operands constitute user defined types which are used in
2769 // instruction definitions.
2770
2771 // Vectors
2772
2773 // Dummy generic vector class. Should be used for all vector operands.
|