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src/hotspot/cpu/x86/x86.ad

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2407   uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
2408     return MachNode::size(ra_);
2409   }
2410 
2411 %}
2412 
2413 encode %{
2414 
2415   enc_class call_epilog %{
2416     if (VerifyStackAtCalls) {
2417       // Check that stack depth is unchanged: find majik cookie on stack
2418       int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
2419       C2_MacroAssembler _masm(&cbuf);
2420       Label L;
2421       __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
2422       __ jccb(Assembler::equal, L);
2423       // Die if stack mismatch
2424       __ int3();
2425       __ bind(L);
2426     }












2427   %}
2428 
2429 %}
2430 
2431 // Operands for bound floating pointer register arguments
2432 operand rxmm0() %{
2433   constraint(ALLOC_IN_RC(xmm0_reg));
2434   match(VecX);
2435   format%{%}
2436   interface(REG_INTER);
2437 %}
2438 
2439 //----------OPERANDS-----------------------------------------------------------
2440 // Operand definitions must precede instruction definitions for correct parsing
2441 // in the ADLC because operands constitute user defined types which are used in
2442 // instruction definitions.
2443 
2444 // Vectors
2445 
2446 // Dummy generic vector class. Should be used for all vector operands.

2407   uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
2408     return MachNode::size(ra_);
2409   }
2410 
2411 %}
2412 
2413 encode %{
2414 
2415   enc_class call_epilog %{
2416     if (VerifyStackAtCalls) {
2417       // Check that stack depth is unchanged: find majik cookie on stack
2418       int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
2419       C2_MacroAssembler _masm(&cbuf);
2420       Label L;
2421       __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
2422       __ jccb(Assembler::equal, L);
2423       // Die if stack mismatch
2424       __ int3();
2425       __ bind(L);
2426     }
2427     if (tf()->returns_inline_type_as_fields() && !_method->is_method_handle_intrinsic()) {
2428       // An inline type is returned as fields in multiple registers.
2429       // Rax either contains an oop if the inline type is buffered or a pointer
2430       // to the corresponding InlineKlass with the lowest bit set to 1. Zero rax
2431       // if the lowest bit is set to allow C2 to use the oop after null checking.
2432       // rax &= (rax & 1) - 1
2433       C2_MacroAssembler _masm(&cbuf);
2434       __ movptr(rscratch1, rax);
2435       __ andptr(rscratch1, 0x1);
2436       __ subptr(rscratch1, 0x1);
2437       __ andptr(rax, rscratch1);
2438     }
2439   %}
2440 
2441 %}
2442 
2443 // Operands for bound floating pointer register arguments
2444 operand rxmm0() %{
2445   constraint(ALLOC_IN_RC(xmm0_reg));
2446   match(VecX);
2447   format%{%}
2448   interface(REG_INTER);
2449 %}
2450 
2451 //----------OPERANDS-----------------------------------------------------------
2452 // Operand definitions must precede instruction definitions for correct parsing
2453 // in the ADLC because operands constitute user defined types which are used in
2454 // instruction definitions.
2455 
2456 // Vectors
2457 
2458 // Dummy generic vector class. Should be used for all vector operands.
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