2766 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
2767 return MachNode::size(ra_);
2768 }
2769
2770 %}
2771
2772 encode %{
2773
2774 enc_class call_epilog %{
2775 C2_MacroAssembler _masm(&cbuf);
2776 if (VerifyStackAtCalls) {
2777 // Check that stack depth is unchanged: find majik cookie on stack
2778 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
2779 Label L;
2780 __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
2781 __ jccb(Assembler::equal, L);
2782 // Die if stack mismatch
2783 __ int3();
2784 __ bind(L);
2785 }
2786 %}
2787
2788 %}
2789
2790 // Operands for bound floating pointer register arguments
2791 operand rxmm0() %{
2792 constraint(ALLOC_IN_RC(xmm0_reg));
2793 match(VecX);
2794 format%{%}
2795 interface(REG_INTER);
2796 %}
2797
2798 //----------OPERANDS-----------------------------------------------------------
2799 // Operand definitions must precede instruction definitions for correct parsing
2800 // in the ADLC because operands constitute user defined types which are used in
2801 // instruction definitions.
2802
2803 // Vectors
2804
2805 // Dummy generic vector class. Should be used for all vector operands.
|
2766 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
2767 return MachNode::size(ra_);
2768 }
2769
2770 %}
2771
2772 encode %{
2773
2774 enc_class call_epilog %{
2775 C2_MacroAssembler _masm(&cbuf);
2776 if (VerifyStackAtCalls) {
2777 // Check that stack depth is unchanged: find majik cookie on stack
2778 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
2779 Label L;
2780 __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
2781 __ jccb(Assembler::equal, L);
2782 // Die if stack mismatch
2783 __ int3();
2784 __ bind(L);
2785 }
2786 if (tf()->returns_inline_type_as_fields() && !_method->is_method_handle_intrinsic()) {
2787 C2_MacroAssembler _masm(&cbuf);
2788 // The last return value is not set by the callee but used to pass IsInit information to compiled code.
2789 // Search for the corresponding projection, get the register and emit code that initialized it.
2790 uint con = (tf()->range_cc()->cnt() - 1);
2791 for (DUIterator_Fast imax, i = fast_outs(imax); i < imax; i++) {
2792 ProjNode* proj = fast_out(i)->as_Proj();
2793 if (proj->_con == con) {
2794 // Set IsInit if rax is non-null (a non-null value is returned buffered or scalarized)
2795 OptoReg::Name optoReg = ra_->get_reg_first(proj);
2796 VMReg reg = OptoReg::as_VMReg(optoReg, ra_->_framesize, OptoReg::reg2stack(ra_->_matcher._new_SP));
2797 Register toReg = reg->is_reg() ? reg->as_Register() : rscratch1;
2798 __ testq(rax, rax);
2799 __ setb(Assembler::notZero, toReg);
2800 __ movzbl(toReg, toReg);
2801 if (reg->is_stack()) {
2802 int st_off = reg->reg2stack() * VMRegImpl::stack_slot_size;
2803 __ movq(Address(rsp, st_off), toReg);
2804 }
2805 break;
2806 }
2807 }
2808 if (return_value_is_used()) {
2809 // An inline type is returned as fields in multiple registers.
2810 // Rax either contains an oop if the inline type is buffered or a pointer
2811 // to the corresponding InlineKlass with the lowest bit set to 1. Zero rax
2812 // if the lowest bit is set to allow C2 to use the oop after null checking.
2813 // rax &= (rax & 1) - 1
2814 __ movptr(rscratch1, rax);
2815 __ andptr(rscratch1, 0x1);
2816 __ subptr(rscratch1, 0x1);
2817 __ andptr(rax, rscratch1);
2818 }
2819 }
2820 %}
2821
2822 %}
2823
2824 // Operands for bound floating pointer register arguments
2825 operand rxmm0() %{
2826 constraint(ALLOC_IN_RC(xmm0_reg));
2827 match(VecX);
2828 format%{%}
2829 interface(REG_INTER);
2830 %}
2831
2832 //----------OPERANDS-----------------------------------------------------------
2833 // Operand definitions must precede instruction definitions for correct parsing
2834 // in the ADLC because operands constitute user defined types which are used in
2835 // instruction definitions.
2836
2837 // Vectors
2838
2839 // Dummy generic vector class. Should be used for all vector operands.
|