2774
2775 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
2776 return MachNode::size(ra_);
2777 }
2778
2779 %}
2780
2781 encode %{
2782
2783 enc_class call_epilog %{
2784 if (VerifyStackAtCalls) {
2785 // Check that stack depth is unchanged: find majik cookie on stack
2786 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
2787 Label L;
2788 __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
2789 __ jccb(Assembler::equal, L);
2790 // Die if stack mismatch
2791 __ int3();
2792 __ bind(L);
2793 }
2794 %}
2795
2796 %}
2797
2798 // Operands for bound floating pointer register arguments
2799 operand rxmm0() %{
2800 constraint(ALLOC_IN_RC(xmm0_reg));
2801 match(VecX);
2802 format%{%}
2803 interface(REG_INTER);
2804 %}
2805
2806 //----------OPERANDS-----------------------------------------------------------
2807 // Operand definitions must precede instruction definitions for correct parsing
2808 // in the ADLC because operands constitute user defined types which are used in
2809 // instruction definitions.
2810
2811 // Vectors
2812
2813 // Dummy generic vector class. Should be used for all vector operands.
|
2774
2775 uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
2776 return MachNode::size(ra_);
2777 }
2778
2779 %}
2780
2781 encode %{
2782
2783 enc_class call_epilog %{
2784 if (VerifyStackAtCalls) {
2785 // Check that stack depth is unchanged: find majik cookie on stack
2786 int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
2787 Label L;
2788 __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
2789 __ jccb(Assembler::equal, L);
2790 // Die if stack mismatch
2791 __ int3();
2792 __ bind(L);
2793 }
2794 if (tf()->returns_inline_type_as_fields() && !_method->is_method_handle_intrinsic()) {
2795 // The last return value is not set by the callee but used to pass IsInit information to compiled code.
2796 // Search for the corresponding projection, get the register and emit code that initialized it.
2797 uint con = (tf()->range_cc()->cnt() - 1);
2798 for (DUIterator_Fast imax, i = fast_outs(imax); i < imax; i++) {
2799 ProjNode* proj = fast_out(i)->as_Proj();
2800 if (proj->_con == con) {
2801 // Set IsInit if rax is non-null (a non-null value is returned buffered or scalarized)
2802 OptoReg::Name optoReg = ra_->get_reg_first(proj);
2803 VMReg reg = OptoReg::as_VMReg(optoReg, ra_->_framesize, OptoReg::reg2stack(ra_->_matcher._new_SP));
2804 Register toReg = reg->is_reg() ? reg->as_Register() : rscratch1;
2805 __ testq(rax, rax);
2806 __ setb(Assembler::notZero, toReg);
2807 __ movzbl(toReg, toReg);
2808 if (reg->is_stack()) {
2809 int st_off = reg->reg2stack() * VMRegImpl::stack_slot_size;
2810 __ movq(Address(rsp, st_off), toReg);
2811 }
2812 break;
2813 }
2814 }
2815 if (return_value_is_used()) {
2816 // An inline type is returned as fields in multiple registers.
2817 // Rax either contains an oop if the inline type is buffered or a pointer
2818 // to the corresponding InlineKlass with the lowest bit set to 1. Zero rax
2819 // if the lowest bit is set to allow C2 to use the oop after null checking.
2820 // rax &= (rax & 1) - 1
2821 __ movptr(rscratch1, rax);
2822 __ andptr(rscratch1, 0x1);
2823 __ subptr(rscratch1, 0x1);
2824 __ andptr(rax, rscratch1);
2825 }
2826 }
2827 %}
2828
2829 %}
2830
2831 // Operands for bound floating pointer register arguments
2832 operand rxmm0() %{
2833 constraint(ALLOC_IN_RC(xmm0_reg));
2834 match(VecX);
2835 format%{%}
2836 interface(REG_INTER);
2837 %}
2838
2839 //----------OPERANDS-----------------------------------------------------------
2840 // Operand definitions must precede instruction definitions for correct parsing
2841 // in the ADLC because operands constitute user defined types which are used in
2842 // instruction definitions.
2843
2844 // Vectors
2845
2846 // Dummy generic vector class. Should be used for all vector operands.
|