< prev index next >

src/hotspot/cpu/x86/x86.ad

Print this page

 2761   uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
 2762     return MachNode::size(ra_);
 2763   }
 2764 
 2765 %}
 2766 
 2767 encode %{
 2768 
 2769   enc_class call_epilog %{
 2770     C2_MacroAssembler _masm(&cbuf);
 2771     if (VerifyStackAtCalls) {
 2772       // Check that stack depth is unchanged: find majik cookie on stack
 2773       int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
 2774       Label L;
 2775       __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
 2776       __ jccb(Assembler::equal, L);
 2777       // Die if stack mismatch
 2778       __ int3();
 2779       __ bind(L);
 2780     }




































 2781   %}
 2782 
 2783 %}
 2784 
 2785 // Operands for bound floating pointer register arguments
 2786 operand rxmm0() %{
 2787   constraint(ALLOC_IN_RC(xmm0_reg));
 2788   match(VecX);
 2789   format%{%}
 2790   interface(REG_INTER);
 2791 %}
 2792 
 2793 //----------OPERANDS-----------------------------------------------------------
 2794 // Operand definitions must precede instruction definitions for correct parsing
 2795 // in the ADLC because operands constitute user defined types which are used in
 2796 // instruction definitions.
 2797 
 2798 // Vectors
 2799 
 2800 // Dummy generic vector class. Should be used for all vector operands.

 2761   uint MachBreakpointNode::size(PhaseRegAlloc* ra_) const {
 2762     return MachNode::size(ra_);
 2763   }
 2764 
 2765 %}
 2766 
 2767 encode %{
 2768 
 2769   enc_class call_epilog %{
 2770     C2_MacroAssembler _masm(&cbuf);
 2771     if (VerifyStackAtCalls) {
 2772       // Check that stack depth is unchanged: find majik cookie on stack
 2773       int framesize = ra_->reg2offset_unchecked(OptoReg::add(ra_->_matcher._old_SP, -3*VMRegImpl::slots_per_word));
 2774       Label L;
 2775       __ cmpptr(Address(rsp, framesize), (int32_t)0xbadb100d);
 2776       __ jccb(Assembler::equal, L);
 2777       // Die if stack mismatch
 2778       __ int3();
 2779       __ bind(L);
 2780     }
 2781     if (tf()->returns_inline_type_as_fields() && !_method->is_method_handle_intrinsic()) {
 2782       C2_MacroAssembler _masm(&cbuf);
 2783       if (!_method->signature()->returns_null_free_inline_type()) {
 2784         // The last return value is not set by the callee but used to pass IsInit information to compiled code.
 2785         // Search for the corresponding projection, get the register and emit code that initialized it.
 2786         uint con = (tf()->range_cc()->cnt() - 1);
 2787         for (DUIterator_Fast imax, i = fast_outs(imax); i < imax; i++) {
 2788           ProjNode* proj = fast_out(i)->as_Proj();
 2789           if (proj->_con == con) {
 2790             // Set IsInit if rax is non-null (a non-null value is returned buffered or scalarized)
 2791             OptoReg::Name optoReg = ra_->get_reg_first(proj);
 2792             VMReg reg = OptoReg::as_VMReg(optoReg, ra_->_framesize, OptoReg::reg2stack(ra_->_matcher._new_SP));
 2793             Register toReg = reg->is_reg() ? reg->as_Register() : rscratch1;
 2794             __ testq(rax, rax);
 2795             __ set_byte_if_not_zero(toReg);
 2796             __ movzbl(toReg, toReg);
 2797             if (reg->is_stack()) {
 2798               int st_off = reg->reg2stack() * VMRegImpl::stack_slot_size;
 2799               __ movq(Address(rsp, st_off), toReg);
 2800             }
 2801             break;
 2802           }
 2803         }
 2804       }
 2805       if (return_value_is_used()) {
 2806         // An inline type is returned as fields in multiple registers.
 2807         // Rax either contains an oop if the inline type is buffered or a pointer
 2808         // to the corresponding InlineKlass with the lowest bit set to 1. Zero rax
 2809         // if the lowest bit is set to allow C2 to use the oop after null checking.
 2810         // rax &= (rax & 1) - 1
 2811         __ movptr(rscratch1, rax);
 2812         __ andptr(rscratch1, 0x1);
 2813         __ subptr(rscratch1, 0x1);
 2814         __ andptr(rax, rscratch1);
 2815       }
 2816     }
 2817   %}
 2818 
 2819 %}
 2820 
 2821 // Operands for bound floating pointer register arguments
 2822 operand rxmm0() %{
 2823   constraint(ALLOC_IN_RC(xmm0_reg));
 2824   match(VecX);
 2825   format%{%}
 2826   interface(REG_INTER);
 2827 %}
 2828 
 2829 //----------OPERANDS-----------------------------------------------------------
 2830 // Operand definitions must precede instruction definitions for correct parsing
 2831 // in the ADLC because operands constitute user defined types which are used in
 2832 // instruction definitions.
 2833 
 2834 // Vectors
 2835 
 2836 // Dummy generic vector class. Should be used for all vector operands.
< prev index next >